1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 int ql_errlev = ql_log_all; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount = 0; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable=1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI. Default is 1 - perform FDMI."); 117 118 #define MAX_Q_DEPTH 64 119 static int ql2xmaxqdepth = MAX_Q_DEPTH; 120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xmaxqdepth, 122 "Maximum queue depth to set for each LUN. " 123 "Default is 64."); 124 125 #if (IS_ENABLED(CONFIG_NVME_FC)) 126 int ql2xenabledif; 127 #else 128 int ql2xenabledif = 2; 129 #endif 130 module_param(ql2xenabledif, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xenabledif, 132 " Enable T10-CRC-DIF:\n" 133 " Default is 2.\n" 134 " 0 -- No DIF Support\n" 135 " 1 -- Enable DIF for all types\n" 136 " 2 -- Enable DIF for all types, except Type 0.\n"); 137 138 #if (IS_ENABLED(CONFIG_NVME_FC)) 139 int ql2xnvmeenable = 1; 140 #else 141 int ql2xnvmeenable; 142 #endif 143 module_param(ql2xnvmeenable, int, 0644); 144 MODULE_PARM_DESC(ql2xnvmeenable, 145 "Enables NVME support. " 146 "0 - no NVMe. Default is Y"); 147 148 int ql2xenablehba_err_chk = 2; 149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xenablehba_err_chk, 151 " Enable T10-CRC-DIF Error isolation by HBA:\n" 152 " Default is 2.\n" 153 " 0 -- Error isolation disabled\n" 154 " 1 -- Error isolation enabled only for DIX Type 0\n" 155 " 2 -- Error isolation enabled for all Types\n"); 156 157 int ql2xiidmaenable=1; 158 module_param(ql2xiidmaenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xiidmaenable, 160 "Enables iIDMA settings " 161 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 162 163 int ql2xmqsupport = 1; 164 module_param(ql2xmqsupport, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xmqsupport, 166 "Enable on demand multiple queue pairs support " 167 "Default is 1 for supported. " 168 "Set it to 0 to turn off mq qpair support."); 169 170 int ql2xfwloadbin; 171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xfwloadbin, 174 "Option to specify location from which to load ISP firmware:.\n" 175 " 2 -- load firmware via the request_firmware() (hotplug).\n" 176 " interface.\n" 177 " 1 -- load firmware from flash.\n" 178 " 0 -- use default semantics.\n"); 179 180 int ql2xetsenable; 181 module_param(ql2xetsenable, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xetsenable, 183 "Enables firmware ETS burst." 184 "Default is 0 - skip ETS enablement."); 185 186 int ql2xdbwr = 1; 187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 188 MODULE_PARM_DESC(ql2xdbwr, 189 "Option to specify scheme for request queue posting.\n" 190 " 0 -- Regular doorbell.\n" 191 " 1 -- CAMRAM doorbell (faster).\n"); 192 193 int ql2xtargetreset = 1; 194 module_param(ql2xtargetreset, int, S_IRUGO); 195 MODULE_PARM_DESC(ql2xtargetreset, 196 "Enable target reset." 197 "Default is 1 - use hw defaults."); 198 199 int ql2xgffidenable; 200 module_param(ql2xgffidenable, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xgffidenable, 202 "Enables GFF_ID checks of port type. " 203 "Default is 0 - Do not use GFF_ID information."); 204 205 int ql2xasynctmfenable = 1; 206 module_param(ql2xasynctmfenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xasynctmfenable, 208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 210 211 int ql2xdontresethba; 212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 213 MODULE_PARM_DESC(ql2xdontresethba, 214 "Option to specify reset behaviour.\n" 215 " 0 (Default) -- Reset on failure.\n" 216 " 1 -- Do not reset on failure.\n"); 217 218 uint64_t ql2xmaxlun = MAX_LUNS; 219 module_param(ql2xmaxlun, ullong, S_IRUGO); 220 MODULE_PARM_DESC(ql2xmaxlun, 221 "Defines the maximum LU number to register with the SCSI " 222 "midlayer. Default is 65535."); 223 224 int ql2xmdcapmask = 0x1F; 225 module_param(ql2xmdcapmask, int, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmdcapmask, 227 "Set the Minidump driver capture mask level. " 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 229 230 int ql2xmdenable = 1; 231 module_param(ql2xmdenable, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdenable, 233 "Enable/disable MiniDump. " 234 "0 - MiniDump disabled. " 235 "1 (Default) - MiniDump enabled."); 236 237 int ql2xexlogins = 0; 238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 239 MODULE_PARM_DESC(ql2xexlogins, 240 "Number of extended Logins. " 241 "0 (Default)- Disabled."); 242 243 int ql2xexchoffld = 1024; 244 module_param(ql2xexchoffld, uint, 0644); 245 MODULE_PARM_DESC(ql2xexchoffld, 246 "Number of target exchanges."); 247 248 int ql2xiniexchg = 1024; 249 module_param(ql2xiniexchg, uint, 0644); 250 MODULE_PARM_DESC(ql2xiniexchg, 251 "Number of initiator exchanges."); 252 253 int ql2xfwholdabts = 0; 254 module_param(ql2xfwholdabts, int, S_IRUGO); 255 MODULE_PARM_DESC(ql2xfwholdabts, 256 "Allow FW to hold status IOCB until ABTS rsp received. " 257 "0 (Default) Do not set fw option. " 258 "1 - Set fw option to hold ABTS."); 259 260 int ql2xmvasynctoatio = 1; 261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 262 MODULE_PARM_DESC(ql2xmvasynctoatio, 263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 264 "0 (Default). Do not move IOCBs" 265 "1 - Move IOCBs."); 266 267 int ql2xautodetectsfp = 1; 268 module_param(ql2xautodetectsfp, int, 0444); 269 MODULE_PARM_DESC(ql2xautodetectsfp, 270 "Detect SFP range and set appropriate distance.\n" 271 "1 (Default): Enable\n"); 272 273 int ql2xenablemsix = 1; 274 module_param(ql2xenablemsix, int, 0444); 275 MODULE_PARM_DESC(ql2xenablemsix, 276 "Set to enable MSI or MSI-X interrupt mechanism.\n" 277 " Default is 1, enable MSI-X interrupt mechanism.\n" 278 " 0 -- enable traditional pin-based mechanism.\n" 279 " 1 -- enable MSI-X interrupt mechanism.\n" 280 " 2 -- enable MSI interrupt mechanism.\n"); 281 282 int qla2xuseresexchforels; 283 module_param(qla2xuseresexchforels, int, 0444); 284 MODULE_PARM_DESC(qla2xuseresexchforels, 285 "Reserve 1/2 of emergency exchanges for ELS.\n" 286 " 0 (default): disabled"); 287 288 int ql2xprotmask; 289 module_param(ql2xprotmask, int, 0644); 290 MODULE_PARM_DESC(ql2xprotmask, 291 "Override DIF/DIX protection capabilities mask\n" 292 "Default is 0 which sets protection mask based on " 293 "capabilities reported by HBA firmware.\n"); 294 295 int ql2xprotguard; 296 module_param(ql2xprotguard, int, 0644); 297 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 298 " 0 -- Let HBA firmware decide\n" 299 " 1 -- Force T10 CRC\n" 300 " 2 -- Force IP checksum\n"); 301 302 int ql2xdifbundlinginternalbuffers; 303 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 304 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 305 "Force using internal buffers for DIF information\n" 306 "0 (Default). Based on check.\n" 307 "1 Force using internal buffers\n"); 308 309 /* 310 * SCSI host template entry points 311 */ 312 static int qla2xxx_slave_configure(struct scsi_device * device); 313 static int qla2xxx_slave_alloc(struct scsi_device *); 314 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 315 static void qla2xxx_scan_start(struct Scsi_Host *); 316 static void qla2xxx_slave_destroy(struct scsi_device *); 317 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 318 static int qla2xxx_eh_abort(struct scsi_cmnd *); 319 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 320 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 321 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 322 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 323 324 static void qla2x00_clear_drv_active(struct qla_hw_data *); 325 static void qla2x00_free_device(scsi_qla_host_t *); 326 static int qla2xxx_map_queues(struct Scsi_Host *shost); 327 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 328 329 330 struct scsi_host_template qla2xxx_driver_template = { 331 .module = THIS_MODULE, 332 .name = QLA2XXX_DRIVER_NAME, 333 .queuecommand = qla2xxx_queuecommand, 334 335 .eh_timed_out = fc_eh_timed_out, 336 .eh_abort_handler = qla2xxx_eh_abort, 337 .eh_device_reset_handler = qla2xxx_eh_device_reset, 338 .eh_target_reset_handler = qla2xxx_eh_target_reset, 339 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 340 .eh_host_reset_handler = qla2xxx_eh_host_reset, 341 342 .slave_configure = qla2xxx_slave_configure, 343 344 .slave_alloc = qla2xxx_slave_alloc, 345 .slave_destroy = qla2xxx_slave_destroy, 346 .scan_finished = qla2xxx_scan_finished, 347 .scan_start = qla2xxx_scan_start, 348 .change_queue_depth = scsi_change_queue_depth, 349 .map_queues = qla2xxx_map_queues, 350 .this_id = -1, 351 .cmd_per_lun = 3, 352 .sg_tablesize = SG_ALL, 353 354 .max_sectors = 0xFFFF, 355 .shost_attrs = qla2x00_host_attrs, 356 357 .supported_mode = MODE_INITIATOR, 358 .track_queue_depth = 1, 359 }; 360 361 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 362 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 363 364 /* TODO Convert to inlines 365 * 366 * Timer routines 367 */ 368 369 __inline__ void 370 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 371 { 372 timer_setup(&vha->timer, qla2x00_timer, 0); 373 vha->timer.expires = jiffies + interval * HZ; 374 add_timer(&vha->timer); 375 vha->timer_active = 1; 376 } 377 378 static inline void 379 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 /* Currently used for 82XX only. */ 382 if (vha->device_flags & DFLG_DEV_FAILED) { 383 ql_dbg(ql_dbg_timer, vha, 0x600d, 384 "Device in a failed state, returning.\n"); 385 return; 386 } 387 388 mod_timer(&vha->timer, jiffies + interval * HZ); 389 } 390 391 static __inline__ void 392 qla2x00_stop_timer(scsi_qla_host_t *vha) 393 { 394 del_timer_sync(&vha->timer); 395 vha->timer_active = 0; 396 } 397 398 static int qla2x00_do_dpc(void *data); 399 400 static void qla2x00_rst_aen(scsi_qla_host_t *); 401 402 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 403 struct req_que **, struct rsp_que **); 404 static void qla2x00_free_fw_dump(struct qla_hw_data *); 405 static void qla2x00_mem_free(struct qla_hw_data *); 406 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 407 struct qla_qpair *qpair); 408 409 /* -------------------------------------------------------------------------- */ 410 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 struct qla_hw_data *ha = vha->hw; 414 rsp->qpair = ha->base_qpair; 415 rsp->req = req; 416 ha->base_qpair->hw = ha; 417 ha->base_qpair->req = req; 418 ha->base_qpair->rsp = rsp; 419 ha->base_qpair->vha = vha; 420 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 421 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 422 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 423 ha->base_qpair->srb_mempool = ha->srb_mempool; 424 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 425 ha->base_qpair->enable_class_2 = ql2xenableclass2; 426 /* init qpair to this cpu. Will adjust at run time. */ 427 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 428 ha->base_qpair->pdev = ha->pdev; 429 430 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 431 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 432 } 433 434 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 435 struct rsp_que *rsp) 436 { 437 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 438 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 439 GFP_KERNEL); 440 if (!ha->req_q_map) { 441 ql_log(ql_log_fatal, vha, 0x003b, 442 "Unable to allocate memory for request queue ptrs.\n"); 443 goto fail_req_map; 444 } 445 446 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 447 GFP_KERNEL); 448 if (!ha->rsp_q_map) { 449 ql_log(ql_log_fatal, vha, 0x003c, 450 "Unable to allocate memory for response queue ptrs.\n"); 451 goto fail_rsp_map; 452 } 453 454 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 455 if (ha->base_qpair == NULL) { 456 ql_log(ql_log_warn, vha, 0x00e0, 457 "Failed to allocate base queue pair memory.\n"); 458 goto fail_base_qpair; 459 } 460 461 qla_init_base_qpair(vha, req, rsp); 462 463 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 464 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 465 GFP_KERNEL); 466 if (!ha->queue_pair_map) { 467 ql_log(ql_log_fatal, vha, 0x0180, 468 "Unable to allocate memory for queue pair ptrs.\n"); 469 goto fail_qpair_map; 470 } 471 } 472 473 /* 474 * Make sure we record at least the request and response queue zero in 475 * case we need to free them if part of the probe fails. 476 */ 477 ha->rsp_q_map[0] = rsp; 478 ha->req_q_map[0] = req; 479 set_bit(0, ha->rsp_qid_map); 480 set_bit(0, ha->req_qid_map); 481 return 0; 482 483 fail_qpair_map: 484 kfree(ha->base_qpair); 485 ha->base_qpair = NULL; 486 fail_base_qpair: 487 kfree(ha->rsp_q_map); 488 ha->rsp_q_map = NULL; 489 fail_rsp_map: 490 kfree(ha->req_q_map); 491 ha->req_q_map = NULL; 492 fail_req_map: 493 return -ENOMEM; 494 } 495 496 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 497 { 498 if (IS_QLAFX00(ha)) { 499 if (req && req->ring_fx00) 500 dma_free_coherent(&ha->pdev->dev, 501 (req->length_fx00 + 1) * sizeof(request_t), 502 req->ring_fx00, req->dma_fx00); 503 } else if (req && req->ring) 504 dma_free_coherent(&ha->pdev->dev, 505 (req->length + 1) * sizeof(request_t), 506 req->ring, req->dma); 507 508 if (req) 509 kfree(req->outstanding_cmds); 510 511 kfree(req); 512 } 513 514 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 515 { 516 if (IS_QLAFX00(ha)) { 517 if (rsp && rsp->ring_fx00) 518 dma_free_coherent(&ha->pdev->dev, 519 (rsp->length_fx00 + 1) * sizeof(request_t), 520 rsp->ring_fx00, rsp->dma_fx00); 521 } else if (rsp && rsp->ring) { 522 dma_free_coherent(&ha->pdev->dev, 523 (rsp->length + 1) * sizeof(response_t), 524 rsp->ring, rsp->dma); 525 } 526 kfree(rsp); 527 } 528 529 static void qla2x00_free_queues(struct qla_hw_data *ha) 530 { 531 struct req_que *req; 532 struct rsp_que *rsp; 533 int cnt; 534 unsigned long flags; 535 536 if (ha->queue_pair_map) { 537 kfree(ha->queue_pair_map); 538 ha->queue_pair_map = NULL; 539 } 540 if (ha->base_qpair) { 541 kfree(ha->base_qpair); 542 ha->base_qpair = NULL; 543 } 544 545 spin_lock_irqsave(&ha->hardware_lock, flags); 546 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 547 if (!test_bit(cnt, ha->req_qid_map)) 548 continue; 549 550 req = ha->req_q_map[cnt]; 551 clear_bit(cnt, ha->req_qid_map); 552 ha->req_q_map[cnt] = NULL; 553 554 spin_unlock_irqrestore(&ha->hardware_lock, flags); 555 qla2x00_free_req_que(ha, req); 556 spin_lock_irqsave(&ha->hardware_lock, flags); 557 } 558 spin_unlock_irqrestore(&ha->hardware_lock, flags); 559 560 kfree(ha->req_q_map); 561 ha->req_q_map = NULL; 562 563 564 spin_lock_irqsave(&ha->hardware_lock, flags); 565 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 566 if (!test_bit(cnt, ha->rsp_qid_map)) 567 continue; 568 569 rsp = ha->rsp_q_map[cnt]; 570 clear_bit(cnt, ha->rsp_qid_map); 571 ha->rsp_q_map[cnt] = NULL; 572 spin_unlock_irqrestore(&ha->hardware_lock, flags); 573 qla2x00_free_rsp_que(ha, rsp); 574 spin_lock_irqsave(&ha->hardware_lock, flags); 575 } 576 spin_unlock_irqrestore(&ha->hardware_lock, flags); 577 578 kfree(ha->rsp_q_map); 579 ha->rsp_q_map = NULL; 580 } 581 582 static char * 583 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 584 { 585 struct qla_hw_data *ha = vha->hw; 586 static char *pci_bus_modes[] = { 587 "33", "66", "100", "133", 588 }; 589 uint16_t pci_bus; 590 591 strcpy(str, "PCI"); 592 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 593 if (pci_bus) { 594 strcat(str, "-X ("); 595 strcat(str, pci_bus_modes[pci_bus]); 596 } else { 597 pci_bus = (ha->pci_attr & BIT_8) >> 8; 598 strcat(str, " ("); 599 strcat(str, pci_bus_modes[pci_bus]); 600 } 601 strcat(str, " MHz)"); 602 603 return (str); 604 } 605 606 static char * 607 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 608 { 609 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 610 struct qla_hw_data *ha = vha->hw; 611 uint32_t pci_bus; 612 613 if (pci_is_pcie(ha->pdev)) { 614 char lwstr[6]; 615 uint32_t lstat, lspeed, lwidth; 616 617 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 618 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 619 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 620 621 strcpy(str, "PCIe ("); 622 switch (lspeed) { 623 case 1: 624 strcat(str, "2.5GT/s "); 625 break; 626 case 2: 627 strcat(str, "5.0GT/s "); 628 break; 629 case 3: 630 strcat(str, "8.0GT/s "); 631 break; 632 default: 633 strcat(str, "<unknown> "); 634 break; 635 } 636 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 637 strcat(str, lwstr); 638 639 return str; 640 } 641 642 strcpy(str, "PCI"); 643 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 644 if (pci_bus == 0 || pci_bus == 8) { 645 strcat(str, " ("); 646 strcat(str, pci_bus_modes[pci_bus >> 3]); 647 } else { 648 strcat(str, "-X "); 649 if (pci_bus & BIT_2) 650 strcat(str, "Mode 2"); 651 else 652 strcat(str, "Mode 1"); 653 strcat(str, " ("); 654 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 655 } 656 strcat(str, " MHz)"); 657 658 return str; 659 } 660 661 static char * 662 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 663 { 664 char un_str[10]; 665 struct qla_hw_data *ha = vha->hw; 666 667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 668 ha->fw_minor_version, ha->fw_subminor_version); 669 670 if (ha->fw_attributes & BIT_9) { 671 strcat(str, "FLX"); 672 return (str); 673 } 674 675 switch (ha->fw_attributes & 0xFF) { 676 case 0x7: 677 strcat(str, "EF"); 678 break; 679 case 0x17: 680 strcat(str, "TP"); 681 break; 682 case 0x37: 683 strcat(str, "IP"); 684 break; 685 case 0x77: 686 strcat(str, "VI"); 687 break; 688 default: 689 sprintf(un_str, "(%x)", ha->fw_attributes); 690 strcat(str, un_str); 691 break; 692 } 693 if (ha->fw_attributes & 0x100) 694 strcat(str, "X"); 695 696 return (str); 697 } 698 699 static char * 700 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 701 { 702 struct qla_hw_data *ha = vha->hw; 703 704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 706 return str; 707 } 708 709 void 710 qla2x00_sp_free_dma(void *ptr) 711 { 712 srb_t *sp = ptr; 713 struct qla_hw_data *ha = sp->vha->hw; 714 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 715 void *ctx = GET_CMD_CTX_SP(sp); 716 717 if (sp->flags & SRB_DMA_VALID) { 718 scsi_dma_unmap(cmd); 719 sp->flags &= ~SRB_DMA_VALID; 720 } 721 722 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 723 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 724 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 725 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 726 } 727 728 if (!ctx) 729 goto end; 730 731 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 732 /* List assured to be having elements */ 733 qla2x00_clean_dsd_pool(ha, ctx); 734 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 735 } 736 737 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 738 struct crc_context *ctx0 = ctx; 739 740 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 741 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 742 } 743 744 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 745 struct ct6_dsd *ctx1 = ctx; 746 747 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 748 ctx1->fcp_cmnd_dma); 749 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 750 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 751 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 752 mempool_free(ctx1, ha->ctx_mempool); 753 } 754 755 end: 756 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 757 CMD_SP(cmd) = NULL; 758 qla2x00_rel_sp(sp); 759 } 760 } 761 762 void 763 qla2x00_sp_compl(void *ptr, int res) 764 { 765 srb_t *sp = ptr; 766 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 767 768 cmd->result = res; 769 770 if (atomic_read(&sp->ref_count) == 0) { 771 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 772 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 773 sp, GET_CMD_SP(sp)); 774 if (ql2xextended_error_logging & ql_dbg_io) 775 WARN_ON(atomic_read(&sp->ref_count) == 0); 776 return; 777 } 778 if (!atomic_dec_and_test(&sp->ref_count)) 779 return; 780 781 sp->free(sp); 782 cmd->scsi_done(cmd); 783 } 784 785 void 786 qla2xxx_qpair_sp_free_dma(void *ptr) 787 { 788 srb_t *sp = (srb_t *)ptr; 789 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 790 struct qla_hw_data *ha = sp->fcport->vha->hw; 791 void *ctx = GET_CMD_CTX_SP(sp); 792 793 if (sp->flags & SRB_DMA_VALID) { 794 scsi_dma_unmap(cmd); 795 sp->flags &= ~SRB_DMA_VALID; 796 } 797 798 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 799 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 800 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 801 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 802 } 803 804 if (!ctx) 805 goto end; 806 807 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 808 /* List assured to be having elements */ 809 qla2x00_clean_dsd_pool(ha, ctx); 810 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 811 } 812 813 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 814 struct crc_context *ctx0 = ctx; 815 816 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 817 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 818 } 819 820 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 821 struct ct6_dsd *ctx1 = ctx; 822 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 823 ctx1->fcp_cmnd_dma); 824 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 825 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 826 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 827 mempool_free(ctx1, ha->ctx_mempool); 828 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 829 } 830 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 831 struct crc_context *difctx = sp->u.scmd.ctx; 832 struct dsd_dma *dif_dsd, *nxt_dsd; 833 834 list_for_each_entry_safe(dif_dsd, nxt_dsd, 835 &difctx->ldif_dma_hndl_list, list) { 836 list_del(&dif_dsd->list); 837 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 838 dif_dsd->dsd_list_dma); 839 kfree(dif_dsd); 840 difctx->no_dif_bundl--; 841 } 842 843 list_for_each_entry_safe(dif_dsd, nxt_dsd, 844 &difctx->ldif_dsd_list, list) { 845 list_del(&dif_dsd->list); 846 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 847 dif_dsd->dsd_list_dma); 848 kfree(dif_dsd); 849 difctx->no_ldif_dsd--; 850 } 851 852 if (difctx->no_ldif_dsd) { 853 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 854 "%s: difctx->no_ldif_dsd=%x\n", 855 __func__, difctx->no_ldif_dsd); 856 } 857 858 if (difctx->no_dif_bundl) { 859 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 860 "%s: difctx->no_dif_bundl=%x\n", 861 __func__, difctx->no_dif_bundl); 862 } 863 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 864 } 865 866 end: 867 CMD_SP(cmd) = NULL; 868 qla2xxx_rel_qpair_sp(sp->qpair, sp); 869 } 870 871 void 872 qla2xxx_qpair_sp_compl(void *ptr, int res) 873 { 874 srb_t *sp = ptr; 875 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 876 877 cmd->result = res; 878 879 if (atomic_read(&sp->ref_count) == 0) { 880 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 881 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 882 sp, GET_CMD_SP(sp)); 883 if (ql2xextended_error_logging & ql_dbg_io) 884 WARN_ON(atomic_read(&sp->ref_count) == 0); 885 return; 886 } 887 if (!atomic_dec_and_test(&sp->ref_count)) 888 return; 889 890 sp->free(sp); 891 cmd->scsi_done(cmd); 892 } 893 894 /* If we are SP1 here, we need to still take and release the host_lock as SP1 895 * does not have the changes necessary to avoid taking host->host_lock. 896 */ 897 static int 898 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 899 { 900 scsi_qla_host_t *vha = shost_priv(host); 901 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 902 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 903 struct qla_hw_data *ha = vha->hw; 904 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 905 srb_t *sp; 906 int rval; 907 struct qla_qpair *qpair = NULL; 908 uint32_t tag; 909 uint16_t hwq; 910 911 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 912 cmd->result = DID_NO_CONNECT << 16; 913 goto qc24_fail_command; 914 } 915 916 if (ha->mqenable) { 917 tag = blk_mq_unique_tag(cmd->request); 918 hwq = blk_mq_unique_tag_to_hwq(tag); 919 qpair = ha->queue_pair_map[hwq]; 920 921 if (qpair) 922 return qla2xxx_mqueuecommand(host, cmd, qpair); 923 } 924 925 if (ha->flags.eeh_busy) { 926 if (ha->flags.pci_channel_io_perm_failure) { 927 ql_dbg(ql_dbg_aer, vha, 0x9010, 928 "PCI Channel IO permanent failure, exiting " 929 "cmd=%p.\n", cmd); 930 cmd->result = DID_NO_CONNECT << 16; 931 } else { 932 ql_dbg(ql_dbg_aer, vha, 0x9011, 933 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 934 cmd->result = DID_REQUEUE << 16; 935 } 936 goto qc24_fail_command; 937 } 938 939 rval = fc_remote_port_chkready(rport); 940 if (rval) { 941 cmd->result = rval; 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 943 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 944 cmd, rval); 945 goto qc24_fail_command; 946 } 947 948 if (!vha->flags.difdix_supported && 949 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 950 ql_dbg(ql_dbg_io, vha, 0x3004, 951 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 952 cmd); 953 cmd->result = DID_NO_CONNECT << 16; 954 goto qc24_fail_command; 955 } 956 957 if (!fcport) { 958 cmd->result = DID_NO_CONNECT << 16; 959 goto qc24_fail_command; 960 } 961 962 if (atomic_read(&fcport->state) != FCS_ONLINE) { 963 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 964 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 965 ql_dbg(ql_dbg_io, vha, 0x3005, 966 "Returning DNC, fcport_state=%d loop_state=%d.\n", 967 atomic_read(&fcport->state), 968 atomic_read(&base_vha->loop_state)); 969 cmd->result = DID_NO_CONNECT << 16; 970 goto qc24_fail_command; 971 } 972 goto qc24_target_busy; 973 } 974 975 /* 976 * Return target busy if we've received a non-zero retry_delay_timer 977 * in a FCP_RSP. 978 */ 979 if (fcport->retry_delay_timestamp == 0) { 980 /* retry delay not set */ 981 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 982 fcport->retry_delay_timestamp = 0; 983 else 984 goto qc24_target_busy; 985 986 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 987 if (!sp) 988 goto qc24_host_busy; 989 990 sp->u.scmd.cmd = cmd; 991 sp->type = SRB_SCSI_CMD; 992 atomic_set(&sp->ref_count, 1); 993 CMD_SP(cmd) = (void *)sp; 994 sp->free = qla2x00_sp_free_dma; 995 sp->done = qla2x00_sp_compl; 996 997 rval = ha->isp_ops->start_scsi(sp); 998 if (rval != QLA_SUCCESS) { 999 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 1000 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1001 goto qc24_host_busy_free_sp; 1002 } 1003 1004 return 0; 1005 1006 qc24_host_busy_free_sp: 1007 sp->free(sp); 1008 1009 qc24_host_busy: 1010 return SCSI_MLQUEUE_HOST_BUSY; 1011 1012 qc24_target_busy: 1013 return SCSI_MLQUEUE_TARGET_BUSY; 1014 1015 qc24_fail_command: 1016 cmd->scsi_done(cmd); 1017 1018 return 0; 1019 } 1020 1021 /* For MQ supported I/O */ 1022 int 1023 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 1024 struct qla_qpair *qpair) 1025 { 1026 scsi_qla_host_t *vha = shost_priv(host); 1027 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1028 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1029 struct qla_hw_data *ha = vha->hw; 1030 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1031 srb_t *sp; 1032 int rval; 1033 1034 rval = fc_remote_port_chkready(rport); 1035 if (rval) { 1036 cmd->result = rval; 1037 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1038 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1039 cmd, rval); 1040 goto qc24_fail_command; 1041 } 1042 1043 if (!fcport) { 1044 cmd->result = DID_NO_CONNECT << 16; 1045 goto qc24_fail_command; 1046 } 1047 1048 if (atomic_read(&fcport->state) != FCS_ONLINE) { 1049 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1050 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1051 ql_dbg(ql_dbg_io, vha, 0x3077, 1052 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1053 atomic_read(&fcport->state), 1054 atomic_read(&base_vha->loop_state)); 1055 cmd->result = DID_NO_CONNECT << 16; 1056 goto qc24_fail_command; 1057 } 1058 goto qc24_target_busy; 1059 } 1060 1061 /* 1062 * Return target busy if we've received a non-zero retry_delay_timer 1063 * in a FCP_RSP. 1064 */ 1065 if (fcport->retry_delay_timestamp == 0) { 1066 /* retry delay not set */ 1067 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1068 fcport->retry_delay_timestamp = 0; 1069 else 1070 goto qc24_target_busy; 1071 1072 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC); 1073 if (!sp) 1074 goto qc24_host_busy; 1075 1076 sp->u.scmd.cmd = cmd; 1077 sp->type = SRB_SCSI_CMD; 1078 atomic_set(&sp->ref_count, 1); 1079 CMD_SP(cmd) = (void *)sp; 1080 sp->free = qla2xxx_qpair_sp_free_dma; 1081 sp->done = qla2xxx_qpair_sp_compl; 1082 sp->qpair = qpair; 1083 1084 rval = ha->isp_ops->start_scsi_mq(sp); 1085 if (rval != QLA_SUCCESS) { 1086 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1087 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1088 if (rval == QLA_INTERFACE_ERROR) 1089 goto qc24_fail_command; 1090 goto qc24_host_busy_free_sp; 1091 } 1092 1093 return 0; 1094 1095 qc24_host_busy_free_sp: 1096 sp->free(sp); 1097 1098 qc24_host_busy: 1099 return SCSI_MLQUEUE_HOST_BUSY; 1100 1101 qc24_target_busy: 1102 return SCSI_MLQUEUE_TARGET_BUSY; 1103 1104 qc24_fail_command: 1105 cmd->scsi_done(cmd); 1106 1107 return 0; 1108 } 1109 1110 /* 1111 * qla2x00_eh_wait_on_command 1112 * Waits for the command to be returned by the Firmware for some 1113 * max time. 1114 * 1115 * Input: 1116 * cmd = Scsi Command to wait on. 1117 * 1118 * Return: 1119 * Not Found : 0 1120 * Found : 1 1121 */ 1122 static int 1123 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1124 { 1125 #define ABORT_POLLING_PERIOD 1000 1126 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1127 unsigned long wait_iter = ABORT_WAIT_ITER; 1128 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1129 struct qla_hw_data *ha = vha->hw; 1130 int ret = QLA_SUCCESS; 1131 1132 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1133 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1134 "Return:eh_wait.\n"); 1135 return ret; 1136 } 1137 1138 while (CMD_SP(cmd) && wait_iter--) { 1139 msleep(ABORT_POLLING_PERIOD); 1140 } 1141 if (CMD_SP(cmd)) 1142 ret = QLA_FUNCTION_FAILED; 1143 1144 return ret; 1145 } 1146 1147 /* 1148 * qla2x00_wait_for_hba_online 1149 * Wait till the HBA is online after going through 1150 * <= MAX_RETRIES_OF_ISP_ABORT or 1151 * finally HBA is disabled ie marked offline 1152 * 1153 * Input: 1154 * ha - pointer to host adapter structure 1155 * 1156 * Note: 1157 * Does context switching-Release SPIN_LOCK 1158 * (if any) before calling this routine. 1159 * 1160 * Return: 1161 * Success (Adapter is online) : 0 1162 * Failed (Adapter is offline/disabled) : 1 1163 */ 1164 int 1165 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1166 { 1167 int return_status; 1168 unsigned long wait_online; 1169 struct qla_hw_data *ha = vha->hw; 1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1171 1172 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1173 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1174 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1175 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1176 ha->dpc_active) && time_before(jiffies, wait_online)) { 1177 1178 msleep(1000); 1179 } 1180 if (base_vha->flags.online) 1181 return_status = QLA_SUCCESS; 1182 else 1183 return_status = QLA_FUNCTION_FAILED; 1184 1185 return (return_status); 1186 } 1187 1188 static inline int test_fcport_count(scsi_qla_host_t *vha) 1189 { 1190 struct qla_hw_data *ha = vha->hw; 1191 unsigned long flags; 1192 int res; 1193 1194 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1195 ql_dbg(ql_dbg_init, vha, 0x00ec, 1196 "tgt %p, fcport_count=%d\n", 1197 vha, vha->fcport_count); 1198 res = (vha->fcport_count == 0); 1199 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1200 1201 return res; 1202 } 1203 1204 /* 1205 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1206 * it has dependency on UNLOADING flag to stop device discovery 1207 */ 1208 void 1209 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1210 { 1211 qla2x00_mark_all_devices_lost(vha, 0); 1212 1213 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1214 } 1215 1216 /* 1217 * qla2x00_wait_for_hba_ready 1218 * Wait till the HBA is ready before doing driver unload 1219 * 1220 * Input: 1221 * ha - pointer to host adapter structure 1222 * 1223 * Note: 1224 * Does context switching-Release SPIN_LOCK 1225 * (if any) before calling this routine. 1226 * 1227 */ 1228 static void 1229 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1230 { 1231 struct qla_hw_data *ha = vha->hw; 1232 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1233 1234 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1235 ha->flags.mbox_busy) || 1236 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1237 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1238 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1239 break; 1240 msleep(1000); 1241 } 1242 } 1243 1244 int 1245 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1246 { 1247 int return_status; 1248 unsigned long wait_reset; 1249 struct qla_hw_data *ha = vha->hw; 1250 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1251 1252 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1253 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1254 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1255 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1256 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1257 1258 msleep(1000); 1259 1260 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1261 ha->flags.chip_reset_done) 1262 break; 1263 } 1264 if (ha->flags.chip_reset_done) 1265 return_status = QLA_SUCCESS; 1266 else 1267 return_status = QLA_FUNCTION_FAILED; 1268 1269 return return_status; 1270 } 1271 1272 static int 1273 sp_get(struct srb *sp) 1274 { 1275 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count)) 1276 /* kref get fail */ 1277 return ENXIO; 1278 else 1279 return 0; 1280 } 1281 1282 #define ISP_REG_DISCONNECT 0xffffffffU 1283 /************************************************************************** 1284 * qla2x00_isp_reg_stat 1285 * 1286 * Description: 1287 * Read the host status register of ISP before aborting the command. 1288 * 1289 * Input: 1290 * ha = pointer to host adapter structure. 1291 * 1292 * 1293 * Returns: 1294 * Either true or false. 1295 * 1296 * Note: Return true if there is register disconnect. 1297 **************************************************************************/ 1298 static inline 1299 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1300 { 1301 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1302 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1303 1304 if (IS_P3P_TYPE(ha)) 1305 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1306 else 1307 return ((RD_REG_DWORD(®->host_status)) == 1308 ISP_REG_DISCONNECT); 1309 } 1310 1311 /************************************************************************** 1312 * qla2xxx_eh_abort 1313 * 1314 * Description: 1315 * The abort function will abort the specified command. 1316 * 1317 * Input: 1318 * cmd = Linux SCSI command packet to be aborted. 1319 * 1320 * Returns: 1321 * Either SUCCESS or FAILED. 1322 * 1323 * Note: 1324 * Only return FAILED if command not returned by firmware. 1325 **************************************************************************/ 1326 static int 1327 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1328 { 1329 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1330 srb_t *sp; 1331 int ret; 1332 unsigned int id; 1333 uint64_t lun; 1334 unsigned long flags; 1335 int rval, wait = 0; 1336 struct qla_hw_data *ha = vha->hw; 1337 struct qla_qpair *qpair; 1338 1339 if (qla2x00_isp_reg_stat(ha)) { 1340 ql_log(ql_log_info, vha, 0x8042, 1341 "PCI/Register disconnect, exiting.\n"); 1342 return FAILED; 1343 } 1344 1345 ret = fc_block_scsi_eh(cmd); 1346 if (ret != 0) 1347 return ret; 1348 ret = SUCCESS; 1349 1350 sp = (srb_t *) CMD_SP(cmd); 1351 if (!sp) 1352 return SUCCESS; 1353 1354 qpair = sp->qpair; 1355 if (!qpair) 1356 return SUCCESS; 1357 1358 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1359 if (!CMD_SP(cmd)) { 1360 /* there's a chance an interrupt could clear 1361 the ptr as part of done & free */ 1362 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1363 return SUCCESS; 1364 } 1365 1366 if (sp_get(sp)){ 1367 /* ref_count is already 0 */ 1368 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1369 return SUCCESS; 1370 } 1371 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1372 1373 id = cmd->device->id; 1374 lun = cmd->device->lun; 1375 1376 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1377 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1378 vha->host_no, id, lun, sp, cmd, sp->handle); 1379 1380 /* Get a reference to the sp and drop the lock.*/ 1381 1382 rval = ha->isp_ops->abort_command(sp); 1383 if (rval) { 1384 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1385 ret = SUCCESS; 1386 else 1387 ret = FAILED; 1388 1389 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1390 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1391 } else { 1392 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1393 "Abort command mbx success cmd=%p.\n", cmd); 1394 wait = 1; 1395 } 1396 1397 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1398 /* 1399 * Clear the slot in the oustanding_cmds array if we can't find the 1400 * command to reclaim the resources. 1401 */ 1402 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1403 vha->req->outstanding_cmds[sp->handle] = NULL; 1404 1405 /* 1406 * sp->done will do ref_count-- 1407 * sp_get() took an extra count above 1408 */ 1409 sp->done(sp, DID_RESET << 16); 1410 1411 /* Did the command return during mailbox execution? */ 1412 if (ret == FAILED && !CMD_SP(cmd)) 1413 ret = SUCCESS; 1414 1415 if (!CMD_SP(cmd)) 1416 wait = 0; 1417 1418 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1419 1420 /* Wait for the command to be returned. */ 1421 if (wait) { 1422 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1423 ql_log(ql_log_warn, vha, 0x8006, 1424 "Abort handler timed out cmd=%p.\n", cmd); 1425 ret = FAILED; 1426 } 1427 } 1428 1429 ql_log(ql_log_info, vha, 0x801c, 1430 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1431 vha->host_no, id, lun, wait, ret); 1432 1433 return ret; 1434 } 1435 1436 int 1437 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1438 uint64_t l, enum nexus_wait_type type) 1439 { 1440 int cnt, match, status; 1441 unsigned long flags; 1442 struct qla_hw_data *ha = vha->hw; 1443 struct req_que *req; 1444 srb_t *sp; 1445 struct scsi_cmnd *cmd; 1446 1447 status = QLA_SUCCESS; 1448 1449 spin_lock_irqsave(&ha->hardware_lock, flags); 1450 req = vha->req; 1451 for (cnt = 1; status == QLA_SUCCESS && 1452 cnt < req->num_outstanding_cmds; cnt++) { 1453 sp = req->outstanding_cmds[cnt]; 1454 if (!sp) 1455 continue; 1456 if (sp->type != SRB_SCSI_CMD) 1457 continue; 1458 if (vha->vp_idx != sp->vha->vp_idx) 1459 continue; 1460 match = 0; 1461 cmd = GET_CMD_SP(sp); 1462 switch (type) { 1463 case WAIT_HOST: 1464 match = 1; 1465 break; 1466 case WAIT_TARGET: 1467 match = cmd->device->id == t; 1468 break; 1469 case WAIT_LUN: 1470 match = (cmd->device->id == t && 1471 cmd->device->lun == l); 1472 break; 1473 } 1474 if (!match) 1475 continue; 1476 1477 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1478 status = qla2x00_eh_wait_on_command(cmd); 1479 spin_lock_irqsave(&ha->hardware_lock, flags); 1480 } 1481 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1482 1483 return status; 1484 } 1485 1486 static char *reset_errors[] = { 1487 "HBA not online", 1488 "HBA not ready", 1489 "Task management failed", 1490 "Waiting for command completions", 1491 }; 1492 1493 static int 1494 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1495 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1496 { 1497 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1498 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1499 int err; 1500 1501 if (!fcport) { 1502 return FAILED; 1503 } 1504 1505 err = fc_block_scsi_eh(cmd); 1506 if (err != 0) 1507 return err; 1508 1509 ql_log(ql_log_info, vha, 0x8009, 1510 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1511 cmd->device->id, cmd->device->lun, cmd); 1512 1513 err = 0; 1514 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1515 ql_log(ql_log_warn, vha, 0x800a, 1516 "Wait for hba online failed for cmd=%p.\n", cmd); 1517 goto eh_reset_failed; 1518 } 1519 err = 2; 1520 if (do_reset(fcport, cmd->device->lun, 1) 1521 != QLA_SUCCESS) { 1522 ql_log(ql_log_warn, vha, 0x800c, 1523 "do_reset failed for cmd=%p.\n", cmd); 1524 goto eh_reset_failed; 1525 } 1526 err = 3; 1527 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1528 cmd->device->lun, type) != QLA_SUCCESS) { 1529 ql_log(ql_log_warn, vha, 0x800d, 1530 "wait for pending cmds failed for cmd=%p.\n", cmd); 1531 goto eh_reset_failed; 1532 } 1533 1534 ql_log(ql_log_info, vha, 0x800e, 1535 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1536 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1537 1538 return SUCCESS; 1539 1540 eh_reset_failed: 1541 ql_log(ql_log_info, vha, 0x800f, 1542 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1543 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1544 cmd); 1545 return FAILED; 1546 } 1547 1548 static int 1549 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1550 { 1551 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1552 struct qla_hw_data *ha = vha->hw; 1553 1554 if (qla2x00_isp_reg_stat(ha)) { 1555 ql_log(ql_log_info, vha, 0x803e, 1556 "PCI/Register disconnect, exiting.\n"); 1557 return FAILED; 1558 } 1559 1560 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1561 ha->isp_ops->lun_reset); 1562 } 1563 1564 static int 1565 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1566 { 1567 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1568 struct qla_hw_data *ha = vha->hw; 1569 1570 if (qla2x00_isp_reg_stat(ha)) { 1571 ql_log(ql_log_info, vha, 0x803f, 1572 "PCI/Register disconnect, exiting.\n"); 1573 return FAILED; 1574 } 1575 1576 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1577 ha->isp_ops->target_reset); 1578 } 1579 1580 /************************************************************************** 1581 * qla2xxx_eh_bus_reset 1582 * 1583 * Description: 1584 * The bus reset function will reset the bus and abort any executing 1585 * commands. 1586 * 1587 * Input: 1588 * cmd = Linux SCSI command packet of the command that cause the 1589 * bus reset. 1590 * 1591 * Returns: 1592 * SUCCESS/FAILURE (defined as macro in scsi.h). 1593 * 1594 **************************************************************************/ 1595 static int 1596 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1597 { 1598 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1599 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1600 int ret = FAILED; 1601 unsigned int id; 1602 uint64_t lun; 1603 struct qla_hw_data *ha = vha->hw; 1604 1605 if (qla2x00_isp_reg_stat(ha)) { 1606 ql_log(ql_log_info, vha, 0x8040, 1607 "PCI/Register disconnect, exiting.\n"); 1608 return FAILED; 1609 } 1610 1611 id = cmd->device->id; 1612 lun = cmd->device->lun; 1613 1614 if (!fcport) { 1615 return ret; 1616 } 1617 1618 ret = fc_block_scsi_eh(cmd); 1619 if (ret != 0) 1620 return ret; 1621 ret = FAILED; 1622 1623 ql_log(ql_log_info, vha, 0x8012, 1624 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1625 1626 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1627 ql_log(ql_log_fatal, vha, 0x8013, 1628 "Wait for hba online failed board disabled.\n"); 1629 goto eh_bus_reset_done; 1630 } 1631 1632 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1633 ret = SUCCESS; 1634 1635 if (ret == FAILED) 1636 goto eh_bus_reset_done; 1637 1638 /* Flush outstanding commands. */ 1639 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1640 QLA_SUCCESS) { 1641 ql_log(ql_log_warn, vha, 0x8014, 1642 "Wait for pending commands failed.\n"); 1643 ret = FAILED; 1644 } 1645 1646 eh_bus_reset_done: 1647 ql_log(ql_log_warn, vha, 0x802b, 1648 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1649 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1650 1651 return ret; 1652 } 1653 1654 /************************************************************************** 1655 * qla2xxx_eh_host_reset 1656 * 1657 * Description: 1658 * The reset function will reset the Adapter. 1659 * 1660 * Input: 1661 * cmd = Linux SCSI command packet of the command that cause the 1662 * adapter reset. 1663 * 1664 * Returns: 1665 * Either SUCCESS or FAILED. 1666 * 1667 * Note: 1668 **************************************************************************/ 1669 static int 1670 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1671 { 1672 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1673 struct qla_hw_data *ha = vha->hw; 1674 int ret = FAILED; 1675 unsigned int id; 1676 uint64_t lun; 1677 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1678 1679 if (qla2x00_isp_reg_stat(ha)) { 1680 ql_log(ql_log_info, vha, 0x8041, 1681 "PCI/Register disconnect, exiting.\n"); 1682 schedule_work(&ha->board_disable); 1683 return SUCCESS; 1684 } 1685 1686 id = cmd->device->id; 1687 lun = cmd->device->lun; 1688 1689 ql_log(ql_log_info, vha, 0x8018, 1690 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1691 1692 /* 1693 * No point in issuing another reset if one is active. Also do not 1694 * attempt a reset if we are updating flash. 1695 */ 1696 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1697 goto eh_host_reset_lock; 1698 1699 if (vha != base_vha) { 1700 if (qla2x00_vp_abort_isp(vha)) 1701 goto eh_host_reset_lock; 1702 } else { 1703 if (IS_P3P_TYPE(vha->hw)) { 1704 if (!qla82xx_fcoe_ctx_reset(vha)) { 1705 /* Ctx reset success */ 1706 ret = SUCCESS; 1707 goto eh_host_reset_lock; 1708 } 1709 /* fall thru if ctx reset failed */ 1710 } 1711 if (ha->wq) 1712 flush_workqueue(ha->wq); 1713 1714 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1715 if (ha->isp_ops->abort_isp(base_vha)) { 1716 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1717 /* failed. schedule dpc to try */ 1718 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1719 1720 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1721 ql_log(ql_log_warn, vha, 0x802a, 1722 "wait for hba online failed.\n"); 1723 goto eh_host_reset_lock; 1724 } 1725 } 1726 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1727 } 1728 1729 /* Waiting for command to be returned to OS.*/ 1730 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1731 QLA_SUCCESS) 1732 ret = SUCCESS; 1733 1734 eh_host_reset_lock: 1735 ql_log(ql_log_info, vha, 0x8017, 1736 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1737 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1738 1739 return ret; 1740 } 1741 1742 /* 1743 * qla2x00_loop_reset 1744 * Issue loop reset. 1745 * 1746 * Input: 1747 * ha = adapter block pointer. 1748 * 1749 * Returns: 1750 * 0 = success 1751 */ 1752 int 1753 qla2x00_loop_reset(scsi_qla_host_t *vha) 1754 { 1755 int ret; 1756 struct fc_port *fcport; 1757 struct qla_hw_data *ha = vha->hw; 1758 1759 if (IS_QLAFX00(ha)) { 1760 return qlafx00_loop_reset(vha); 1761 } 1762 1763 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1764 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1765 if (fcport->port_type != FCT_TARGET) 1766 continue; 1767 1768 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1769 if (ret != QLA_SUCCESS) { 1770 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1771 "Bus Reset failed: Reset=%d " 1772 "d_id=%x.\n", ret, fcport->d_id.b24); 1773 } 1774 } 1775 } 1776 1777 1778 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1779 atomic_set(&vha->loop_state, LOOP_DOWN); 1780 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1781 qla2x00_mark_all_devices_lost(vha, 0); 1782 ret = qla2x00_full_login_lip(vha); 1783 if (ret != QLA_SUCCESS) { 1784 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1785 "full_login_lip=%d.\n", ret); 1786 } 1787 } 1788 1789 if (ha->flags.enable_lip_reset) { 1790 ret = qla2x00_lip_reset(vha); 1791 if (ret != QLA_SUCCESS) 1792 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1793 "lip_reset failed (%d).\n", ret); 1794 } 1795 1796 /* Issue marker command only when we are going to start the I/O */ 1797 vha->marker_needed = 1; 1798 1799 return QLA_SUCCESS; 1800 } 1801 1802 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1803 unsigned long *flags) 1804 __releases(qp->qp_lock_ptr) 1805 __acquires(qp->qp_lock_ptr) 1806 { 1807 scsi_qla_host_t *vha = qp->vha; 1808 struct qla_hw_data *ha = vha->hw; 1809 1810 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS) { 1811 if (!sp_get(sp)) { 1812 /* got sp */ 1813 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1814 qla_nvme_abort(ha, sp, res); 1815 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1816 } 1817 } else if (GET_CMD_SP(sp) && !ha->flags.eeh_busy && 1818 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1819 !qla2x00_isp_reg_stat(ha) && sp->type == SRB_SCSI_CMD) { 1820 /* 1821 * Don't abort commands in adapter during EEH recovery as it's 1822 * not accessible/responding. 1823 * 1824 * Get a reference to the sp and drop the lock. The reference 1825 * ensures this sp->done() call and not the call in 1826 * qla2xxx_eh_abort() ends the SCSI cmd (with result 'res'). 1827 */ 1828 if (!sp_get(sp)) { 1829 int status; 1830 1831 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1832 status = qla2xxx_eh_abort(GET_CMD_SP(sp)); 1833 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1834 /* 1835 * Get rid of extra reference caused 1836 * by early exit from qla2xxx_eh_abort 1837 */ 1838 if (status == FAST_IO_FAIL) 1839 atomic_dec(&sp->ref_count); 1840 } 1841 } 1842 sp->done(sp, res); 1843 } 1844 1845 static void 1846 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1847 { 1848 int cnt; 1849 unsigned long flags; 1850 srb_t *sp; 1851 scsi_qla_host_t *vha = qp->vha; 1852 struct qla_hw_data *ha = vha->hw; 1853 struct req_que *req; 1854 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1855 struct qla_tgt_cmd *cmd; 1856 1857 if (!ha->req_q_map) 1858 return; 1859 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1860 req = qp->req; 1861 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1862 sp = req->outstanding_cmds[cnt]; 1863 if (sp) { 1864 req->outstanding_cmds[cnt] = NULL; 1865 switch (sp->cmd_type) { 1866 case TYPE_SRB: 1867 qla2x00_abort_srb(qp, sp, res, &flags); 1868 break; 1869 case TYPE_TGT_CMD: 1870 if (!vha->hw->tgt.tgt_ops || !tgt || 1871 qla_ini_mode_enabled(vha)) { 1872 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1873 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1874 vha->dpc_flags); 1875 continue; 1876 } 1877 cmd = (struct qla_tgt_cmd *)sp; 1878 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1879 break; 1880 case TYPE_TGT_TMCMD: 1881 /* 1882 * Currently, only ABTS response gets on the 1883 * outstanding_cmds[] 1884 */ 1885 ha->tgt.tgt_ops->free_mcmd( 1886 (struct qla_tgt_mgmt_cmd *)sp); 1887 break; 1888 default: 1889 break; 1890 } 1891 } 1892 } 1893 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1894 } 1895 1896 void 1897 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1898 { 1899 int que; 1900 struct qla_hw_data *ha = vha->hw; 1901 1902 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1903 1904 for (que = 0; que < ha->max_qpairs; que++) { 1905 if (!ha->queue_pair_map[que]) 1906 continue; 1907 1908 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1909 } 1910 } 1911 1912 static int 1913 qla2xxx_slave_alloc(struct scsi_device *sdev) 1914 { 1915 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1916 1917 if (!rport || fc_remote_port_chkready(rport)) 1918 return -ENXIO; 1919 1920 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1921 1922 return 0; 1923 } 1924 1925 static int 1926 qla2xxx_slave_configure(struct scsi_device *sdev) 1927 { 1928 scsi_qla_host_t *vha = shost_priv(sdev->host); 1929 struct req_que *req = vha->req; 1930 1931 if (IS_T10_PI_CAPABLE(vha->hw)) 1932 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1933 1934 scsi_change_queue_depth(sdev, req->max_q_depth); 1935 return 0; 1936 } 1937 1938 static void 1939 qla2xxx_slave_destroy(struct scsi_device *sdev) 1940 { 1941 sdev->hostdata = NULL; 1942 } 1943 1944 /** 1945 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1946 * @ha: HA context 1947 * 1948 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1949 * supported addressing method. 1950 */ 1951 static void 1952 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1953 { 1954 /* Assume a 32bit DMA mask. */ 1955 ha->flags.enable_64bit_addressing = 0; 1956 1957 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1958 /* Any upper-dword bits set? */ 1959 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1960 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1961 /* Ok, a 64bit DMA mask is applicable. */ 1962 ha->flags.enable_64bit_addressing = 1; 1963 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1964 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1965 return; 1966 } 1967 } 1968 1969 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1970 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1971 } 1972 1973 static void 1974 qla2x00_enable_intrs(struct qla_hw_data *ha) 1975 { 1976 unsigned long flags = 0; 1977 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1978 1979 spin_lock_irqsave(&ha->hardware_lock, flags); 1980 ha->interrupts_on = 1; 1981 /* enable risc and host interrupts */ 1982 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1983 RD_REG_WORD(®->ictrl); 1984 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1985 1986 } 1987 1988 static void 1989 qla2x00_disable_intrs(struct qla_hw_data *ha) 1990 { 1991 unsigned long flags = 0; 1992 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1993 1994 spin_lock_irqsave(&ha->hardware_lock, flags); 1995 ha->interrupts_on = 0; 1996 /* disable risc and host interrupts */ 1997 WRT_REG_WORD(®->ictrl, 0); 1998 RD_REG_WORD(®->ictrl); 1999 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2000 } 2001 2002 static void 2003 qla24xx_enable_intrs(struct qla_hw_data *ha) 2004 { 2005 unsigned long flags = 0; 2006 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2007 2008 spin_lock_irqsave(&ha->hardware_lock, flags); 2009 ha->interrupts_on = 1; 2010 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 2011 RD_REG_DWORD(®->ictrl); 2012 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2013 } 2014 2015 static void 2016 qla24xx_disable_intrs(struct qla_hw_data *ha) 2017 { 2018 unsigned long flags = 0; 2019 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2020 2021 if (IS_NOPOLLING_TYPE(ha)) 2022 return; 2023 spin_lock_irqsave(&ha->hardware_lock, flags); 2024 ha->interrupts_on = 0; 2025 WRT_REG_DWORD(®->ictrl, 0); 2026 RD_REG_DWORD(®->ictrl); 2027 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2028 } 2029 2030 static int 2031 qla2x00_iospace_config(struct qla_hw_data *ha) 2032 { 2033 resource_size_t pio; 2034 uint16_t msix; 2035 2036 if (pci_request_selected_regions(ha->pdev, ha->bars, 2037 QLA2XXX_DRIVER_NAME)) { 2038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2039 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2040 pci_name(ha->pdev)); 2041 goto iospace_error_exit; 2042 } 2043 if (!(ha->bars & 1)) 2044 goto skip_pio; 2045 2046 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2047 pio = pci_resource_start(ha->pdev, 0); 2048 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2049 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2050 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2051 "Invalid pci I/O region size (%s).\n", 2052 pci_name(ha->pdev)); 2053 pio = 0; 2054 } 2055 } else { 2056 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2057 "Region #0 no a PIO resource (%s).\n", 2058 pci_name(ha->pdev)); 2059 pio = 0; 2060 } 2061 ha->pio_address = pio; 2062 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2063 "PIO address=%llu.\n", 2064 (unsigned long long)ha->pio_address); 2065 2066 skip_pio: 2067 /* Use MMIO operations for all accesses. */ 2068 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2069 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2070 "Region #1 not an MMIO resource (%s), aborting.\n", 2071 pci_name(ha->pdev)); 2072 goto iospace_error_exit; 2073 } 2074 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2076 "Invalid PCI mem region size (%s), aborting.\n", 2077 pci_name(ha->pdev)); 2078 goto iospace_error_exit; 2079 } 2080 2081 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2082 if (!ha->iobase) { 2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2084 "Cannot remap MMIO (%s), aborting.\n", 2085 pci_name(ha->pdev)); 2086 goto iospace_error_exit; 2087 } 2088 2089 /* Determine queue resources */ 2090 ha->max_req_queues = ha->max_rsp_queues = 1; 2091 ha->msix_count = QLA_BASE_VECTORS; 2092 if (!ql2xmqsupport || !ql2xnvmeenable || 2093 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2094 goto mqiobase_exit; 2095 2096 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2097 pci_resource_len(ha->pdev, 3)); 2098 if (ha->mqiobase) { 2099 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2100 "MQIO Base=%p.\n", ha->mqiobase); 2101 /* Read MSIX vector size of the board */ 2102 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2103 ha->msix_count = msix + 1; 2104 /* Max queues are bounded by available msix vectors */ 2105 /* MB interrupt uses 1 vector */ 2106 ha->max_req_queues = ha->msix_count - 1; 2107 ha->max_rsp_queues = ha->max_req_queues; 2108 /* Queue pairs is the max value minus the base queue pair */ 2109 ha->max_qpairs = ha->max_rsp_queues - 1; 2110 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2111 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2112 2113 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2114 "MSI-X vector count: %d.\n", ha->msix_count); 2115 } else 2116 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2117 "BAR 3 not enabled.\n"); 2118 2119 mqiobase_exit: 2120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2121 "MSIX Count: %d.\n", ha->msix_count); 2122 return (0); 2123 2124 iospace_error_exit: 2125 return (-ENOMEM); 2126 } 2127 2128 2129 static int 2130 qla83xx_iospace_config(struct qla_hw_data *ha) 2131 { 2132 uint16_t msix; 2133 2134 if (pci_request_selected_regions(ha->pdev, ha->bars, 2135 QLA2XXX_DRIVER_NAME)) { 2136 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2137 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2138 pci_name(ha->pdev)); 2139 2140 goto iospace_error_exit; 2141 } 2142 2143 /* Use MMIO operations for all accesses. */ 2144 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2145 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2146 "Invalid pci I/O region size (%s).\n", 2147 pci_name(ha->pdev)); 2148 goto iospace_error_exit; 2149 } 2150 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2151 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2152 "Invalid PCI mem region size (%s), aborting\n", 2153 pci_name(ha->pdev)); 2154 goto iospace_error_exit; 2155 } 2156 2157 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2158 if (!ha->iobase) { 2159 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2160 "Cannot remap MMIO (%s), aborting.\n", 2161 pci_name(ha->pdev)); 2162 goto iospace_error_exit; 2163 } 2164 2165 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2166 /* 83XX 26XX always use MQ type access for queues 2167 * - mbar 2, a.k.a region 4 */ 2168 ha->max_req_queues = ha->max_rsp_queues = 1; 2169 ha->msix_count = QLA_BASE_VECTORS; 2170 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2171 pci_resource_len(ha->pdev, 4)); 2172 2173 if (!ha->mqiobase) { 2174 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2175 "BAR2/region4 not enabled\n"); 2176 goto mqiobase_exit; 2177 } 2178 2179 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2180 pci_resource_len(ha->pdev, 2)); 2181 if (ha->msixbase) { 2182 /* Read MSIX vector size of the board */ 2183 pci_read_config_word(ha->pdev, 2184 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2185 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2186 /* 2187 * By default, driver uses at least two msix vectors 2188 * (default & rspq) 2189 */ 2190 if (ql2xmqsupport || ql2xnvmeenable) { 2191 /* MB interrupt uses 1 vector */ 2192 ha->max_req_queues = ha->msix_count - 1; 2193 2194 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2195 if (QLA_TGT_MODE_ENABLED()) 2196 ha->max_req_queues--; 2197 2198 ha->max_rsp_queues = ha->max_req_queues; 2199 2200 /* Queue pairs is the max value minus 2201 * the base queue pair */ 2202 ha->max_qpairs = ha->max_req_queues - 1; 2203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2204 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2205 } 2206 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2207 "MSI-X vector count: %d.\n", ha->msix_count); 2208 } else 2209 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2210 "BAR 1 not enabled.\n"); 2211 2212 mqiobase_exit: 2213 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2214 "MSIX Count: %d.\n", ha->msix_count); 2215 return 0; 2216 2217 iospace_error_exit: 2218 return -ENOMEM; 2219 } 2220 2221 static struct isp_operations qla2100_isp_ops = { 2222 .pci_config = qla2100_pci_config, 2223 .reset_chip = qla2x00_reset_chip, 2224 .chip_diag = qla2x00_chip_diag, 2225 .config_rings = qla2x00_config_rings, 2226 .reset_adapter = qla2x00_reset_adapter, 2227 .nvram_config = qla2x00_nvram_config, 2228 .update_fw_options = qla2x00_update_fw_options, 2229 .load_risc = qla2x00_load_risc, 2230 .pci_info_str = qla2x00_pci_info_str, 2231 .fw_version_str = qla2x00_fw_version_str, 2232 .intr_handler = qla2100_intr_handler, 2233 .enable_intrs = qla2x00_enable_intrs, 2234 .disable_intrs = qla2x00_disable_intrs, 2235 .abort_command = qla2x00_abort_command, 2236 .target_reset = qla2x00_abort_target, 2237 .lun_reset = qla2x00_lun_reset, 2238 .fabric_login = qla2x00_login_fabric, 2239 .fabric_logout = qla2x00_fabric_logout, 2240 .calc_req_entries = qla2x00_calc_iocbs_32, 2241 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2242 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2243 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2244 .read_nvram = qla2x00_read_nvram_data, 2245 .write_nvram = qla2x00_write_nvram_data, 2246 .fw_dump = qla2100_fw_dump, 2247 .beacon_on = NULL, 2248 .beacon_off = NULL, 2249 .beacon_blink = NULL, 2250 .read_optrom = qla2x00_read_optrom_data, 2251 .write_optrom = qla2x00_write_optrom_data, 2252 .get_flash_version = qla2x00_get_flash_version, 2253 .start_scsi = qla2x00_start_scsi, 2254 .start_scsi_mq = NULL, 2255 .abort_isp = qla2x00_abort_isp, 2256 .iospace_config = qla2x00_iospace_config, 2257 .initialize_adapter = qla2x00_initialize_adapter, 2258 }; 2259 2260 static struct isp_operations qla2300_isp_ops = { 2261 .pci_config = qla2300_pci_config, 2262 .reset_chip = qla2x00_reset_chip, 2263 .chip_diag = qla2x00_chip_diag, 2264 .config_rings = qla2x00_config_rings, 2265 .reset_adapter = qla2x00_reset_adapter, 2266 .nvram_config = qla2x00_nvram_config, 2267 .update_fw_options = qla2x00_update_fw_options, 2268 .load_risc = qla2x00_load_risc, 2269 .pci_info_str = qla2x00_pci_info_str, 2270 .fw_version_str = qla2x00_fw_version_str, 2271 .intr_handler = qla2300_intr_handler, 2272 .enable_intrs = qla2x00_enable_intrs, 2273 .disable_intrs = qla2x00_disable_intrs, 2274 .abort_command = qla2x00_abort_command, 2275 .target_reset = qla2x00_abort_target, 2276 .lun_reset = qla2x00_lun_reset, 2277 .fabric_login = qla2x00_login_fabric, 2278 .fabric_logout = qla2x00_fabric_logout, 2279 .calc_req_entries = qla2x00_calc_iocbs_32, 2280 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2281 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2282 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2283 .read_nvram = qla2x00_read_nvram_data, 2284 .write_nvram = qla2x00_write_nvram_data, 2285 .fw_dump = qla2300_fw_dump, 2286 .beacon_on = qla2x00_beacon_on, 2287 .beacon_off = qla2x00_beacon_off, 2288 .beacon_blink = qla2x00_beacon_blink, 2289 .read_optrom = qla2x00_read_optrom_data, 2290 .write_optrom = qla2x00_write_optrom_data, 2291 .get_flash_version = qla2x00_get_flash_version, 2292 .start_scsi = qla2x00_start_scsi, 2293 .start_scsi_mq = NULL, 2294 .abort_isp = qla2x00_abort_isp, 2295 .iospace_config = qla2x00_iospace_config, 2296 .initialize_adapter = qla2x00_initialize_adapter, 2297 }; 2298 2299 static struct isp_operations qla24xx_isp_ops = { 2300 .pci_config = qla24xx_pci_config, 2301 .reset_chip = qla24xx_reset_chip, 2302 .chip_diag = qla24xx_chip_diag, 2303 .config_rings = qla24xx_config_rings, 2304 .reset_adapter = qla24xx_reset_adapter, 2305 .nvram_config = qla24xx_nvram_config, 2306 .update_fw_options = qla24xx_update_fw_options, 2307 .load_risc = qla24xx_load_risc, 2308 .pci_info_str = qla24xx_pci_info_str, 2309 .fw_version_str = qla24xx_fw_version_str, 2310 .intr_handler = qla24xx_intr_handler, 2311 .enable_intrs = qla24xx_enable_intrs, 2312 .disable_intrs = qla24xx_disable_intrs, 2313 .abort_command = qla24xx_abort_command, 2314 .target_reset = qla24xx_abort_target, 2315 .lun_reset = qla24xx_lun_reset, 2316 .fabric_login = qla24xx_login_fabric, 2317 .fabric_logout = qla24xx_fabric_logout, 2318 .calc_req_entries = NULL, 2319 .build_iocbs = NULL, 2320 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2321 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2322 .read_nvram = qla24xx_read_nvram_data, 2323 .write_nvram = qla24xx_write_nvram_data, 2324 .fw_dump = qla24xx_fw_dump, 2325 .beacon_on = qla24xx_beacon_on, 2326 .beacon_off = qla24xx_beacon_off, 2327 .beacon_blink = qla24xx_beacon_blink, 2328 .read_optrom = qla24xx_read_optrom_data, 2329 .write_optrom = qla24xx_write_optrom_data, 2330 .get_flash_version = qla24xx_get_flash_version, 2331 .start_scsi = qla24xx_start_scsi, 2332 .start_scsi_mq = NULL, 2333 .abort_isp = qla2x00_abort_isp, 2334 .iospace_config = qla2x00_iospace_config, 2335 .initialize_adapter = qla2x00_initialize_adapter, 2336 }; 2337 2338 static struct isp_operations qla25xx_isp_ops = { 2339 .pci_config = qla25xx_pci_config, 2340 .reset_chip = qla24xx_reset_chip, 2341 .chip_diag = qla24xx_chip_diag, 2342 .config_rings = qla24xx_config_rings, 2343 .reset_adapter = qla24xx_reset_adapter, 2344 .nvram_config = qla24xx_nvram_config, 2345 .update_fw_options = qla24xx_update_fw_options, 2346 .load_risc = qla24xx_load_risc, 2347 .pci_info_str = qla24xx_pci_info_str, 2348 .fw_version_str = qla24xx_fw_version_str, 2349 .intr_handler = qla24xx_intr_handler, 2350 .enable_intrs = qla24xx_enable_intrs, 2351 .disable_intrs = qla24xx_disable_intrs, 2352 .abort_command = qla24xx_abort_command, 2353 .target_reset = qla24xx_abort_target, 2354 .lun_reset = qla24xx_lun_reset, 2355 .fabric_login = qla24xx_login_fabric, 2356 .fabric_logout = qla24xx_fabric_logout, 2357 .calc_req_entries = NULL, 2358 .build_iocbs = NULL, 2359 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2360 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2361 .read_nvram = qla25xx_read_nvram_data, 2362 .write_nvram = qla25xx_write_nvram_data, 2363 .fw_dump = qla25xx_fw_dump, 2364 .beacon_on = qla24xx_beacon_on, 2365 .beacon_off = qla24xx_beacon_off, 2366 .beacon_blink = qla24xx_beacon_blink, 2367 .read_optrom = qla25xx_read_optrom_data, 2368 .write_optrom = qla24xx_write_optrom_data, 2369 .get_flash_version = qla24xx_get_flash_version, 2370 .start_scsi = qla24xx_dif_start_scsi, 2371 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2372 .abort_isp = qla2x00_abort_isp, 2373 .iospace_config = qla2x00_iospace_config, 2374 .initialize_adapter = qla2x00_initialize_adapter, 2375 }; 2376 2377 static struct isp_operations qla81xx_isp_ops = { 2378 .pci_config = qla25xx_pci_config, 2379 .reset_chip = qla24xx_reset_chip, 2380 .chip_diag = qla24xx_chip_diag, 2381 .config_rings = qla24xx_config_rings, 2382 .reset_adapter = qla24xx_reset_adapter, 2383 .nvram_config = qla81xx_nvram_config, 2384 .update_fw_options = qla81xx_update_fw_options, 2385 .load_risc = qla81xx_load_risc, 2386 .pci_info_str = qla24xx_pci_info_str, 2387 .fw_version_str = qla24xx_fw_version_str, 2388 .intr_handler = qla24xx_intr_handler, 2389 .enable_intrs = qla24xx_enable_intrs, 2390 .disable_intrs = qla24xx_disable_intrs, 2391 .abort_command = qla24xx_abort_command, 2392 .target_reset = qla24xx_abort_target, 2393 .lun_reset = qla24xx_lun_reset, 2394 .fabric_login = qla24xx_login_fabric, 2395 .fabric_logout = qla24xx_fabric_logout, 2396 .calc_req_entries = NULL, 2397 .build_iocbs = NULL, 2398 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2399 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2400 .read_nvram = NULL, 2401 .write_nvram = NULL, 2402 .fw_dump = qla81xx_fw_dump, 2403 .beacon_on = qla24xx_beacon_on, 2404 .beacon_off = qla24xx_beacon_off, 2405 .beacon_blink = qla83xx_beacon_blink, 2406 .read_optrom = qla25xx_read_optrom_data, 2407 .write_optrom = qla24xx_write_optrom_data, 2408 .get_flash_version = qla24xx_get_flash_version, 2409 .start_scsi = qla24xx_dif_start_scsi, 2410 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2411 .abort_isp = qla2x00_abort_isp, 2412 .iospace_config = qla2x00_iospace_config, 2413 .initialize_adapter = qla2x00_initialize_adapter, 2414 }; 2415 2416 static struct isp_operations qla82xx_isp_ops = { 2417 .pci_config = qla82xx_pci_config, 2418 .reset_chip = qla82xx_reset_chip, 2419 .chip_diag = qla24xx_chip_diag, 2420 .config_rings = qla82xx_config_rings, 2421 .reset_adapter = qla24xx_reset_adapter, 2422 .nvram_config = qla81xx_nvram_config, 2423 .update_fw_options = qla24xx_update_fw_options, 2424 .load_risc = qla82xx_load_risc, 2425 .pci_info_str = qla24xx_pci_info_str, 2426 .fw_version_str = qla24xx_fw_version_str, 2427 .intr_handler = qla82xx_intr_handler, 2428 .enable_intrs = qla82xx_enable_intrs, 2429 .disable_intrs = qla82xx_disable_intrs, 2430 .abort_command = qla24xx_abort_command, 2431 .target_reset = qla24xx_abort_target, 2432 .lun_reset = qla24xx_lun_reset, 2433 .fabric_login = qla24xx_login_fabric, 2434 .fabric_logout = qla24xx_fabric_logout, 2435 .calc_req_entries = NULL, 2436 .build_iocbs = NULL, 2437 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2438 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2439 .read_nvram = qla24xx_read_nvram_data, 2440 .write_nvram = qla24xx_write_nvram_data, 2441 .fw_dump = qla82xx_fw_dump, 2442 .beacon_on = qla82xx_beacon_on, 2443 .beacon_off = qla82xx_beacon_off, 2444 .beacon_blink = NULL, 2445 .read_optrom = qla82xx_read_optrom_data, 2446 .write_optrom = qla82xx_write_optrom_data, 2447 .get_flash_version = qla82xx_get_flash_version, 2448 .start_scsi = qla82xx_start_scsi, 2449 .start_scsi_mq = NULL, 2450 .abort_isp = qla82xx_abort_isp, 2451 .iospace_config = qla82xx_iospace_config, 2452 .initialize_adapter = qla2x00_initialize_adapter, 2453 }; 2454 2455 static struct isp_operations qla8044_isp_ops = { 2456 .pci_config = qla82xx_pci_config, 2457 .reset_chip = qla82xx_reset_chip, 2458 .chip_diag = qla24xx_chip_diag, 2459 .config_rings = qla82xx_config_rings, 2460 .reset_adapter = qla24xx_reset_adapter, 2461 .nvram_config = qla81xx_nvram_config, 2462 .update_fw_options = qla24xx_update_fw_options, 2463 .load_risc = qla82xx_load_risc, 2464 .pci_info_str = qla24xx_pci_info_str, 2465 .fw_version_str = qla24xx_fw_version_str, 2466 .intr_handler = qla8044_intr_handler, 2467 .enable_intrs = qla82xx_enable_intrs, 2468 .disable_intrs = qla82xx_disable_intrs, 2469 .abort_command = qla24xx_abort_command, 2470 .target_reset = qla24xx_abort_target, 2471 .lun_reset = qla24xx_lun_reset, 2472 .fabric_login = qla24xx_login_fabric, 2473 .fabric_logout = qla24xx_fabric_logout, 2474 .calc_req_entries = NULL, 2475 .build_iocbs = NULL, 2476 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2477 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2478 .read_nvram = NULL, 2479 .write_nvram = NULL, 2480 .fw_dump = qla8044_fw_dump, 2481 .beacon_on = qla82xx_beacon_on, 2482 .beacon_off = qla82xx_beacon_off, 2483 .beacon_blink = NULL, 2484 .read_optrom = qla8044_read_optrom_data, 2485 .write_optrom = qla8044_write_optrom_data, 2486 .get_flash_version = qla82xx_get_flash_version, 2487 .start_scsi = qla82xx_start_scsi, 2488 .start_scsi_mq = NULL, 2489 .abort_isp = qla8044_abort_isp, 2490 .iospace_config = qla82xx_iospace_config, 2491 .initialize_adapter = qla2x00_initialize_adapter, 2492 }; 2493 2494 static struct isp_operations qla83xx_isp_ops = { 2495 .pci_config = qla25xx_pci_config, 2496 .reset_chip = qla24xx_reset_chip, 2497 .chip_diag = qla24xx_chip_diag, 2498 .config_rings = qla24xx_config_rings, 2499 .reset_adapter = qla24xx_reset_adapter, 2500 .nvram_config = qla81xx_nvram_config, 2501 .update_fw_options = qla81xx_update_fw_options, 2502 .load_risc = qla81xx_load_risc, 2503 .pci_info_str = qla24xx_pci_info_str, 2504 .fw_version_str = qla24xx_fw_version_str, 2505 .intr_handler = qla24xx_intr_handler, 2506 .enable_intrs = qla24xx_enable_intrs, 2507 .disable_intrs = qla24xx_disable_intrs, 2508 .abort_command = qla24xx_abort_command, 2509 .target_reset = qla24xx_abort_target, 2510 .lun_reset = qla24xx_lun_reset, 2511 .fabric_login = qla24xx_login_fabric, 2512 .fabric_logout = qla24xx_fabric_logout, 2513 .calc_req_entries = NULL, 2514 .build_iocbs = NULL, 2515 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2516 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2517 .read_nvram = NULL, 2518 .write_nvram = NULL, 2519 .fw_dump = qla83xx_fw_dump, 2520 .beacon_on = qla24xx_beacon_on, 2521 .beacon_off = qla24xx_beacon_off, 2522 .beacon_blink = qla83xx_beacon_blink, 2523 .read_optrom = qla25xx_read_optrom_data, 2524 .write_optrom = qla24xx_write_optrom_data, 2525 .get_flash_version = qla24xx_get_flash_version, 2526 .start_scsi = qla24xx_dif_start_scsi, 2527 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2528 .abort_isp = qla2x00_abort_isp, 2529 .iospace_config = qla83xx_iospace_config, 2530 .initialize_adapter = qla2x00_initialize_adapter, 2531 }; 2532 2533 static struct isp_operations qlafx00_isp_ops = { 2534 .pci_config = qlafx00_pci_config, 2535 .reset_chip = qlafx00_soft_reset, 2536 .chip_diag = qlafx00_chip_diag, 2537 .config_rings = qlafx00_config_rings, 2538 .reset_adapter = qlafx00_soft_reset, 2539 .nvram_config = NULL, 2540 .update_fw_options = NULL, 2541 .load_risc = NULL, 2542 .pci_info_str = qlafx00_pci_info_str, 2543 .fw_version_str = qlafx00_fw_version_str, 2544 .intr_handler = qlafx00_intr_handler, 2545 .enable_intrs = qlafx00_enable_intrs, 2546 .disable_intrs = qlafx00_disable_intrs, 2547 .abort_command = qla24xx_async_abort_command, 2548 .target_reset = qlafx00_abort_target, 2549 .lun_reset = qlafx00_lun_reset, 2550 .fabric_login = NULL, 2551 .fabric_logout = NULL, 2552 .calc_req_entries = NULL, 2553 .build_iocbs = NULL, 2554 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2555 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2556 .read_nvram = qla24xx_read_nvram_data, 2557 .write_nvram = qla24xx_write_nvram_data, 2558 .fw_dump = NULL, 2559 .beacon_on = qla24xx_beacon_on, 2560 .beacon_off = qla24xx_beacon_off, 2561 .beacon_blink = NULL, 2562 .read_optrom = qla24xx_read_optrom_data, 2563 .write_optrom = qla24xx_write_optrom_data, 2564 .get_flash_version = qla24xx_get_flash_version, 2565 .start_scsi = qlafx00_start_scsi, 2566 .start_scsi_mq = NULL, 2567 .abort_isp = qlafx00_abort_isp, 2568 .iospace_config = qlafx00_iospace_config, 2569 .initialize_adapter = qlafx00_initialize_adapter, 2570 }; 2571 2572 static struct isp_operations qla27xx_isp_ops = { 2573 .pci_config = qla25xx_pci_config, 2574 .reset_chip = qla24xx_reset_chip, 2575 .chip_diag = qla24xx_chip_diag, 2576 .config_rings = qla24xx_config_rings, 2577 .reset_adapter = qla24xx_reset_adapter, 2578 .nvram_config = qla81xx_nvram_config, 2579 .update_fw_options = qla81xx_update_fw_options, 2580 .load_risc = qla81xx_load_risc, 2581 .pci_info_str = qla24xx_pci_info_str, 2582 .fw_version_str = qla24xx_fw_version_str, 2583 .intr_handler = qla24xx_intr_handler, 2584 .enable_intrs = qla24xx_enable_intrs, 2585 .disable_intrs = qla24xx_disable_intrs, 2586 .abort_command = qla24xx_abort_command, 2587 .target_reset = qla24xx_abort_target, 2588 .lun_reset = qla24xx_lun_reset, 2589 .fabric_login = qla24xx_login_fabric, 2590 .fabric_logout = qla24xx_fabric_logout, 2591 .calc_req_entries = NULL, 2592 .build_iocbs = NULL, 2593 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2594 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2595 .read_nvram = NULL, 2596 .write_nvram = NULL, 2597 .fw_dump = qla27xx_fwdump, 2598 .beacon_on = qla24xx_beacon_on, 2599 .beacon_off = qla24xx_beacon_off, 2600 .beacon_blink = qla83xx_beacon_blink, 2601 .read_optrom = qla25xx_read_optrom_data, 2602 .write_optrom = qla24xx_write_optrom_data, 2603 .get_flash_version = qla24xx_get_flash_version, 2604 .start_scsi = qla24xx_dif_start_scsi, 2605 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2606 .abort_isp = qla2x00_abort_isp, 2607 .iospace_config = qla83xx_iospace_config, 2608 .initialize_adapter = qla2x00_initialize_adapter, 2609 }; 2610 2611 static inline void 2612 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2613 { 2614 ha->device_type = DT_EXTENDED_IDS; 2615 switch (ha->pdev->device) { 2616 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2617 ha->isp_type |= DT_ISP2100; 2618 ha->device_type &= ~DT_EXTENDED_IDS; 2619 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2620 break; 2621 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2622 ha->isp_type |= DT_ISP2200; 2623 ha->device_type &= ~DT_EXTENDED_IDS; 2624 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2625 break; 2626 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2627 ha->isp_type |= DT_ISP2300; 2628 ha->device_type |= DT_ZIO_SUPPORTED; 2629 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2630 break; 2631 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2632 ha->isp_type |= DT_ISP2312; 2633 ha->device_type |= DT_ZIO_SUPPORTED; 2634 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2635 break; 2636 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2637 ha->isp_type |= DT_ISP2322; 2638 ha->device_type |= DT_ZIO_SUPPORTED; 2639 if (ha->pdev->subsystem_vendor == 0x1028 && 2640 ha->pdev->subsystem_device == 0x0170) 2641 ha->device_type |= DT_OEM_001; 2642 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2645 ha->isp_type |= DT_ISP6312; 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2647 break; 2648 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2649 ha->isp_type |= DT_ISP6322; 2650 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2651 break; 2652 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2653 ha->isp_type |= DT_ISP2422; 2654 ha->device_type |= DT_ZIO_SUPPORTED; 2655 ha->device_type |= DT_FWI2; 2656 ha->device_type |= DT_IIDMA; 2657 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2658 break; 2659 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2660 ha->isp_type |= DT_ISP2432; 2661 ha->device_type |= DT_ZIO_SUPPORTED; 2662 ha->device_type |= DT_FWI2; 2663 ha->device_type |= DT_IIDMA; 2664 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2665 break; 2666 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2667 ha->isp_type |= DT_ISP8432; 2668 ha->device_type |= DT_ZIO_SUPPORTED; 2669 ha->device_type |= DT_FWI2; 2670 ha->device_type |= DT_IIDMA; 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2672 break; 2673 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2674 ha->isp_type |= DT_ISP5422; 2675 ha->device_type |= DT_FWI2; 2676 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2677 break; 2678 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2679 ha->isp_type |= DT_ISP5432; 2680 ha->device_type |= DT_FWI2; 2681 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2682 break; 2683 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2684 ha->isp_type |= DT_ISP2532; 2685 ha->device_type |= DT_ZIO_SUPPORTED; 2686 ha->device_type |= DT_FWI2; 2687 ha->device_type |= DT_IIDMA; 2688 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2689 break; 2690 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2691 ha->isp_type |= DT_ISP8001; 2692 ha->device_type |= DT_ZIO_SUPPORTED; 2693 ha->device_type |= DT_FWI2; 2694 ha->device_type |= DT_IIDMA; 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2696 break; 2697 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2698 ha->isp_type |= DT_ISP8021; 2699 ha->device_type |= DT_ZIO_SUPPORTED; 2700 ha->device_type |= DT_FWI2; 2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2702 /* Initialize 82XX ISP flags */ 2703 qla82xx_init_flags(ha); 2704 break; 2705 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2706 ha->isp_type |= DT_ISP8044; 2707 ha->device_type |= DT_ZIO_SUPPORTED; 2708 ha->device_type |= DT_FWI2; 2709 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2710 /* Initialize 82XX ISP flags */ 2711 qla82xx_init_flags(ha); 2712 break; 2713 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2714 ha->isp_type |= DT_ISP2031; 2715 ha->device_type |= DT_ZIO_SUPPORTED; 2716 ha->device_type |= DT_FWI2; 2717 ha->device_type |= DT_IIDMA; 2718 ha->device_type |= DT_T10_PI; 2719 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2720 break; 2721 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2722 ha->isp_type |= DT_ISP8031; 2723 ha->device_type |= DT_ZIO_SUPPORTED; 2724 ha->device_type |= DT_FWI2; 2725 ha->device_type |= DT_IIDMA; 2726 ha->device_type |= DT_T10_PI; 2727 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2728 break; 2729 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2730 ha->isp_type |= DT_ISPFX00; 2731 break; 2732 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2733 ha->isp_type |= DT_ISP2071; 2734 ha->device_type |= DT_ZIO_SUPPORTED; 2735 ha->device_type |= DT_FWI2; 2736 ha->device_type |= DT_IIDMA; 2737 ha->device_type |= DT_T10_PI; 2738 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2739 break; 2740 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2741 ha->isp_type |= DT_ISP2271; 2742 ha->device_type |= DT_ZIO_SUPPORTED; 2743 ha->device_type |= DT_FWI2; 2744 ha->device_type |= DT_IIDMA; 2745 ha->device_type |= DT_T10_PI; 2746 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2747 break; 2748 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2749 ha->isp_type |= DT_ISP2261; 2750 ha->device_type |= DT_ZIO_SUPPORTED; 2751 ha->device_type |= DT_FWI2; 2752 ha->device_type |= DT_IIDMA; 2753 ha->device_type |= DT_T10_PI; 2754 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2755 break; 2756 } 2757 2758 if (IS_QLA82XX(ha)) 2759 ha->port_no = ha->portnum & 1; 2760 else { 2761 /* Get adapter physical port no from interrupt pin register. */ 2762 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2763 if (IS_QLA27XX(ha)) 2764 ha->port_no--; 2765 else 2766 ha->port_no = !(ha->port_no & 1); 2767 } 2768 2769 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2770 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2771 ha->device_type, ha->port_no, ha->fw_srisc_address); 2772 } 2773 2774 static void 2775 qla2xxx_scan_start(struct Scsi_Host *shost) 2776 { 2777 scsi_qla_host_t *vha = shost_priv(shost); 2778 2779 if (vha->hw->flags.running_gold_fw) 2780 return; 2781 2782 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2783 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2784 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2785 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2786 } 2787 2788 static int 2789 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2790 { 2791 scsi_qla_host_t *vha = shost_priv(shost); 2792 2793 if (test_bit(UNLOADING, &vha->dpc_flags)) 2794 return 1; 2795 if (!vha->host) 2796 return 1; 2797 if (time > vha->hw->loop_reset_delay * HZ) 2798 return 1; 2799 2800 return atomic_read(&vha->loop_state) == LOOP_READY; 2801 } 2802 2803 static void qla2x00_iocb_work_fn(struct work_struct *work) 2804 { 2805 struct scsi_qla_host *vha = container_of(work, 2806 struct scsi_qla_host, iocb_work); 2807 struct qla_hw_data *ha = vha->hw; 2808 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2809 int i = 2; 2810 unsigned long flags; 2811 2812 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2813 return; 2814 2815 while (!list_empty(&vha->work_list) && i > 0) { 2816 qla2x00_do_work(vha); 2817 i--; 2818 } 2819 2820 spin_lock_irqsave(&vha->work_lock, flags); 2821 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2822 spin_unlock_irqrestore(&vha->work_lock, flags); 2823 } 2824 2825 /* 2826 * PCI driver interface 2827 */ 2828 static int 2829 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2830 { 2831 int ret = -ENODEV; 2832 struct Scsi_Host *host; 2833 scsi_qla_host_t *base_vha = NULL; 2834 struct qla_hw_data *ha; 2835 char pci_info[30]; 2836 char fw_str[30], wq_name[30]; 2837 struct scsi_host_template *sht; 2838 int bars, mem_only = 0; 2839 uint16_t req_length = 0, rsp_length = 0; 2840 struct req_que *req = NULL; 2841 struct rsp_que *rsp = NULL; 2842 int i; 2843 2844 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2845 sht = &qla2xxx_driver_template; 2846 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2847 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2848 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2849 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2850 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2851 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2852 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2853 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2854 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2855 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2856 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2857 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2858 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2859 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2860 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2861 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2862 mem_only = 1; 2863 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2864 "Mem only adapter.\n"); 2865 } 2866 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2867 "Bars=%d.\n", bars); 2868 2869 if (mem_only) { 2870 if (pci_enable_device_mem(pdev)) 2871 return ret; 2872 } else { 2873 if (pci_enable_device(pdev)) 2874 return ret; 2875 } 2876 2877 /* This may fail but that's ok */ 2878 pci_enable_pcie_error_reporting(pdev); 2879 2880 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2881 if (!ha) { 2882 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2883 "Unable to allocate memory for ha.\n"); 2884 goto disable_device; 2885 } 2886 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2887 "Memory allocated for ha=%p.\n", ha); 2888 ha->pdev = pdev; 2889 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2890 spin_lock_init(&ha->tgt.q_full_lock); 2891 spin_lock_init(&ha->tgt.sess_lock); 2892 spin_lock_init(&ha->tgt.atio_lock); 2893 2894 atomic_set(&ha->nvme_active_aen_cnt, 0); 2895 2896 /* Clear our data area */ 2897 ha->bars = bars; 2898 ha->mem_only = mem_only; 2899 spin_lock_init(&ha->hardware_lock); 2900 spin_lock_init(&ha->vport_slock); 2901 mutex_init(&ha->selflogin_lock); 2902 mutex_init(&ha->optrom_mutex); 2903 2904 /* Set ISP-type information. */ 2905 qla2x00_set_isp_flags(ha); 2906 2907 /* Set EEH reset type to fundamental if required by hba */ 2908 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2909 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2910 pdev->needs_freset = 1; 2911 2912 ha->prev_topology = 0; 2913 ha->init_cb_size = sizeof(init_cb_t); 2914 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2915 ha->optrom_size = OPTROM_SIZE_2300; 2916 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2917 atomic_set(&ha->num_pend_mbx_stage1, 0); 2918 atomic_set(&ha->num_pend_mbx_stage2, 0); 2919 atomic_set(&ha->num_pend_mbx_stage3, 0); 2920 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2921 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2922 2923 /* Assign ISP specific operations. */ 2924 if (IS_QLA2100(ha)) { 2925 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2926 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2927 req_length = REQUEST_ENTRY_CNT_2100; 2928 rsp_length = RESPONSE_ENTRY_CNT_2100; 2929 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2930 ha->gid_list_info_size = 4; 2931 ha->flash_conf_off = ~0; 2932 ha->flash_data_off = ~0; 2933 ha->nvram_conf_off = ~0; 2934 ha->nvram_data_off = ~0; 2935 ha->isp_ops = &qla2100_isp_ops; 2936 } else if (IS_QLA2200(ha)) { 2937 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2938 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2939 req_length = REQUEST_ENTRY_CNT_2200; 2940 rsp_length = RESPONSE_ENTRY_CNT_2100; 2941 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2942 ha->gid_list_info_size = 4; 2943 ha->flash_conf_off = ~0; 2944 ha->flash_data_off = ~0; 2945 ha->nvram_conf_off = ~0; 2946 ha->nvram_data_off = ~0; 2947 ha->isp_ops = &qla2100_isp_ops; 2948 } else if (IS_QLA23XX(ha)) { 2949 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2950 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2951 req_length = REQUEST_ENTRY_CNT_2200; 2952 rsp_length = RESPONSE_ENTRY_CNT_2300; 2953 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2954 ha->gid_list_info_size = 6; 2955 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2956 ha->optrom_size = OPTROM_SIZE_2322; 2957 ha->flash_conf_off = ~0; 2958 ha->flash_data_off = ~0; 2959 ha->nvram_conf_off = ~0; 2960 ha->nvram_data_off = ~0; 2961 ha->isp_ops = &qla2300_isp_ops; 2962 } else if (IS_QLA24XX_TYPE(ha)) { 2963 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2964 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2965 req_length = REQUEST_ENTRY_CNT_24XX; 2966 rsp_length = RESPONSE_ENTRY_CNT_2300; 2967 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2968 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2969 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2970 ha->gid_list_info_size = 8; 2971 ha->optrom_size = OPTROM_SIZE_24XX; 2972 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2973 ha->isp_ops = &qla24xx_isp_ops; 2974 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2975 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2976 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2977 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2978 } else if (IS_QLA25XX(ha)) { 2979 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2980 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2981 req_length = REQUEST_ENTRY_CNT_24XX; 2982 rsp_length = RESPONSE_ENTRY_CNT_2300; 2983 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2984 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2985 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2986 ha->gid_list_info_size = 8; 2987 ha->optrom_size = OPTROM_SIZE_25XX; 2988 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2989 ha->isp_ops = &qla25xx_isp_ops; 2990 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2991 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2992 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2993 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2994 } else if (IS_QLA81XX(ha)) { 2995 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2996 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2997 req_length = REQUEST_ENTRY_CNT_24XX; 2998 rsp_length = RESPONSE_ENTRY_CNT_2300; 2999 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3000 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3001 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3002 ha->gid_list_info_size = 8; 3003 ha->optrom_size = OPTROM_SIZE_81XX; 3004 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3005 ha->isp_ops = &qla81xx_isp_ops; 3006 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3007 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3008 ha->nvram_conf_off = ~0; 3009 ha->nvram_data_off = ~0; 3010 } else if (IS_QLA82XX(ha)) { 3011 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3012 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3013 req_length = REQUEST_ENTRY_CNT_82XX; 3014 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3015 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3016 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3017 ha->gid_list_info_size = 8; 3018 ha->optrom_size = OPTROM_SIZE_82XX; 3019 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3020 ha->isp_ops = &qla82xx_isp_ops; 3021 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3022 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3023 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3024 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3025 } else if (IS_QLA8044(ha)) { 3026 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3027 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3028 req_length = REQUEST_ENTRY_CNT_82XX; 3029 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3030 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3031 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3032 ha->gid_list_info_size = 8; 3033 ha->optrom_size = OPTROM_SIZE_83XX; 3034 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3035 ha->isp_ops = &qla8044_isp_ops; 3036 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3037 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3038 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3039 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3040 } else if (IS_QLA83XX(ha)) { 3041 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3043 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3044 req_length = REQUEST_ENTRY_CNT_83XX; 3045 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3046 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3047 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3048 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3049 ha->gid_list_info_size = 8; 3050 ha->optrom_size = OPTROM_SIZE_83XX; 3051 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3052 ha->isp_ops = &qla83xx_isp_ops; 3053 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3054 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3055 ha->nvram_conf_off = ~0; 3056 ha->nvram_data_off = ~0; 3057 } else if (IS_QLAFX00(ha)) { 3058 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3059 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3060 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3061 req_length = REQUEST_ENTRY_CNT_FX00; 3062 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3063 ha->isp_ops = &qlafx00_isp_ops; 3064 ha->port_down_retry_count = 30; /* default value */ 3065 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3066 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3067 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3068 ha->mr.fw_hbt_en = 1; 3069 ha->mr.host_info_resend = false; 3070 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3071 } else if (IS_QLA27XX(ha)) { 3072 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3073 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3074 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3075 req_length = REQUEST_ENTRY_CNT_83XX; 3076 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3077 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3078 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3079 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3080 ha->gid_list_info_size = 8; 3081 ha->optrom_size = OPTROM_SIZE_83XX; 3082 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3083 ha->isp_ops = &qla27xx_isp_ops; 3084 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3085 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3086 ha->nvram_conf_off = ~0; 3087 ha->nvram_data_off = ~0; 3088 } 3089 3090 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3091 "mbx_count=%d, req_length=%d, " 3092 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3093 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3094 "max_fibre_devices=%d.\n", 3095 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3096 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3097 ha->nvram_npiv_size, ha->max_fibre_devices); 3098 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3099 "isp_ops=%p, flash_conf_off=%d, " 3100 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3101 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3102 ha->nvram_conf_off, ha->nvram_data_off); 3103 3104 /* Configure PCI I/O space */ 3105 ret = ha->isp_ops->iospace_config(ha); 3106 if (ret) 3107 goto iospace_config_failed; 3108 3109 ql_log_pci(ql_log_info, pdev, 0x001d, 3110 "Found an ISP%04X irq %d iobase 0x%p.\n", 3111 pdev->device, pdev->irq, ha->iobase); 3112 mutex_init(&ha->vport_lock); 3113 mutex_init(&ha->mq_lock); 3114 init_completion(&ha->mbx_cmd_comp); 3115 complete(&ha->mbx_cmd_comp); 3116 init_completion(&ha->mbx_intr_comp); 3117 init_completion(&ha->dcbx_comp); 3118 init_completion(&ha->lb_portup_comp); 3119 3120 set_bit(0, (unsigned long *) ha->vp_idx_map); 3121 3122 qla2x00_config_dma_addressing(ha); 3123 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3124 "64 Bit addressing is %s.\n", 3125 ha->flags.enable_64bit_addressing ? "enable" : 3126 "disable"); 3127 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3128 if (ret) { 3129 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3130 "Failed to allocate memory for adapter, aborting.\n"); 3131 3132 goto probe_hw_failed; 3133 } 3134 3135 req->max_q_depth = MAX_Q_DEPTH; 3136 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3137 req->max_q_depth = ql2xmaxqdepth; 3138 3139 3140 base_vha = qla2x00_create_host(sht, ha); 3141 if (!base_vha) { 3142 ret = -ENOMEM; 3143 goto probe_hw_failed; 3144 } 3145 3146 pci_set_drvdata(pdev, base_vha); 3147 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3148 3149 host = base_vha->host; 3150 base_vha->req = req; 3151 if (IS_QLA2XXX_MIDTYPE(ha)) 3152 base_vha->mgmt_svr_loop_id = 3153 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3154 else 3155 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3156 base_vha->vp_idx; 3157 3158 /* Setup fcport template structure. */ 3159 ha->mr.fcport.vha = base_vha; 3160 ha->mr.fcport.port_type = FCT_UNKNOWN; 3161 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3162 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3163 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3164 ha->mr.fcport.scan_state = 1; 3165 3166 /* Set the SG table size based on ISP type */ 3167 if (!IS_FWI2_CAPABLE(ha)) { 3168 if (IS_QLA2100(ha)) 3169 host->sg_tablesize = 32; 3170 } else { 3171 if (!IS_QLA82XX(ha)) 3172 host->sg_tablesize = QLA_SG_ALL; 3173 } 3174 host->max_id = ha->max_fibre_devices; 3175 host->cmd_per_lun = 3; 3176 host->unique_id = host->host_no; 3177 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3178 host->max_cmd_len = 32; 3179 else 3180 host->max_cmd_len = MAX_CMDSZ; 3181 host->max_channel = MAX_BUSES - 1; 3182 /* Older HBAs support only 16-bit LUNs */ 3183 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3184 ql2xmaxlun > 0xffff) 3185 host->max_lun = 0xffff; 3186 else 3187 host->max_lun = ql2xmaxlun; 3188 host->transportt = qla2xxx_transport_template; 3189 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3190 3191 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3192 "max_id=%d this_id=%d " 3193 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3194 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3195 host->this_id, host->cmd_per_lun, host->unique_id, 3196 host->max_cmd_len, host->max_channel, host->max_lun, 3197 host->transportt, sht->vendor_id); 3198 3199 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3200 3201 /* Set up the irqs */ 3202 ret = qla2x00_request_irqs(ha, rsp); 3203 if (ret) 3204 goto probe_failed; 3205 3206 /* Alloc arrays of request and response ring ptrs */ 3207 ret = qla2x00_alloc_queues(ha, req, rsp); 3208 if (ret) { 3209 ql_log(ql_log_fatal, base_vha, 0x003d, 3210 "Failed to allocate memory for queue pointers..." 3211 "aborting.\n"); 3212 goto probe_failed; 3213 } 3214 3215 if (ha->mqenable) { 3216 /* number of hardware queues supported by blk/scsi-mq*/ 3217 host->nr_hw_queues = ha->max_qpairs; 3218 3219 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3220 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3221 } else { 3222 if (ql2xnvmeenable) { 3223 host->nr_hw_queues = ha->max_qpairs; 3224 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3225 "FC-NVMe support is enabled, HW queues=%d\n", 3226 host->nr_hw_queues); 3227 } else { 3228 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3229 "blk/scsi-mq disabled.\n"); 3230 } 3231 } 3232 3233 qlt_probe_one_stage1(base_vha, ha); 3234 3235 pci_save_state(pdev); 3236 3237 /* Assign back pointers */ 3238 rsp->req = req; 3239 req->rsp = rsp; 3240 3241 if (IS_QLAFX00(ha)) { 3242 ha->rsp_q_map[0] = rsp; 3243 ha->req_q_map[0] = req; 3244 set_bit(0, ha->req_qid_map); 3245 set_bit(0, ha->rsp_qid_map); 3246 } 3247 3248 /* FWI2-capable only. */ 3249 req->req_q_in = &ha->iobase->isp24.req_q_in; 3250 req->req_q_out = &ha->iobase->isp24.req_q_out; 3251 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3252 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3253 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3254 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3255 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3256 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3257 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3258 } 3259 3260 if (IS_QLAFX00(ha)) { 3261 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3262 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3263 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3264 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3265 } 3266 3267 if (IS_P3P_TYPE(ha)) { 3268 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3269 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3270 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3271 } 3272 3273 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3274 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3275 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3276 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3277 "req->req_q_in=%p req->req_q_out=%p " 3278 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3279 req->req_q_in, req->req_q_out, 3280 rsp->rsp_q_in, rsp->rsp_q_out); 3281 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3282 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3283 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3284 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3285 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3286 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3287 3288 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3289 3290 if (ha->isp_ops->initialize_adapter(base_vha)) { 3291 ql_log(ql_log_fatal, base_vha, 0x00d6, 3292 "Failed to initialize adapter - Adapter flags %x.\n", 3293 base_vha->device_flags); 3294 3295 if (IS_QLA82XX(ha)) { 3296 qla82xx_idc_lock(ha); 3297 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3298 QLA8XXX_DEV_FAILED); 3299 qla82xx_idc_unlock(ha); 3300 ql_log(ql_log_fatal, base_vha, 0x00d7, 3301 "HW State: FAILED.\n"); 3302 } else if (IS_QLA8044(ha)) { 3303 qla8044_idc_lock(ha); 3304 qla8044_wr_direct(base_vha, 3305 QLA8044_CRB_DEV_STATE_INDEX, 3306 QLA8XXX_DEV_FAILED); 3307 qla8044_idc_unlock(ha); 3308 ql_log(ql_log_fatal, base_vha, 0x0150, 3309 "HW State: FAILED.\n"); 3310 } 3311 3312 ret = -ENODEV; 3313 goto probe_failed; 3314 } 3315 3316 if (IS_QLAFX00(ha)) 3317 host->can_queue = QLAFX00_MAX_CANQUEUE; 3318 else 3319 host->can_queue = req->num_outstanding_cmds - 10; 3320 3321 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3322 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3323 host->can_queue, base_vha->req, 3324 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3325 3326 if (ha->mqenable) { 3327 bool startit = false; 3328 3329 if (QLA_TGT_MODE_ENABLED()) 3330 startit = false; 3331 3332 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3333 startit = true; 3334 3335 /* Create start of day qpairs for Block MQ */ 3336 for (i = 0; i < ha->max_qpairs; i++) 3337 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3338 } 3339 3340 if (ha->flags.running_gold_fw) 3341 goto skip_dpc; 3342 3343 /* 3344 * Startup the kernel thread for this host adapter 3345 */ 3346 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3347 "%s_dpc", base_vha->host_str); 3348 if (IS_ERR(ha->dpc_thread)) { 3349 ql_log(ql_log_fatal, base_vha, 0x00ed, 3350 "Failed to start DPC thread.\n"); 3351 ret = PTR_ERR(ha->dpc_thread); 3352 ha->dpc_thread = NULL; 3353 goto probe_failed; 3354 } 3355 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3356 "DPC thread started successfully.\n"); 3357 3358 /* 3359 * If we're not coming up in initiator mode, we might sit for 3360 * a while without waking up the dpc thread, which leads to a 3361 * stuck process warning. So just kick the dpc once here and 3362 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3363 */ 3364 qla2xxx_wake_dpc(base_vha); 3365 3366 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3367 3368 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3369 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3370 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3371 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3372 3373 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3374 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3375 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3376 INIT_WORK(&ha->idc_state_handler, 3377 qla83xx_idc_state_handler_work); 3378 INIT_WORK(&ha->nic_core_unrecoverable, 3379 qla83xx_nic_core_unrecoverable_work); 3380 } 3381 3382 skip_dpc: 3383 list_add_tail(&base_vha->list, &ha->vp_list); 3384 base_vha->host->irq = ha->pdev->irq; 3385 3386 /* Initialized the timer */ 3387 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3388 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3389 "Started qla2x00_timer with " 3390 "interval=%d.\n", WATCH_INTERVAL); 3391 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3392 "Detected hba at address=%p.\n", 3393 ha); 3394 3395 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3396 if (ha->fw_attributes & BIT_4) { 3397 int prot = 0, guard; 3398 base_vha->flags.difdix_supported = 1; 3399 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3400 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3401 if (ql2xenabledif == 1) 3402 prot = SHOST_DIX_TYPE0_PROTECTION; 3403 if (ql2xprotmask) 3404 scsi_host_set_prot(host, ql2xprotmask); 3405 else 3406 scsi_host_set_prot(host, 3407 prot | SHOST_DIF_TYPE1_PROTECTION 3408 | SHOST_DIF_TYPE2_PROTECTION 3409 | SHOST_DIF_TYPE3_PROTECTION 3410 | SHOST_DIX_TYPE1_PROTECTION 3411 | SHOST_DIX_TYPE2_PROTECTION 3412 | SHOST_DIX_TYPE3_PROTECTION); 3413 3414 guard = SHOST_DIX_GUARD_CRC; 3415 3416 if (IS_PI_IPGUARD_CAPABLE(ha) && 3417 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3418 guard |= SHOST_DIX_GUARD_IP; 3419 3420 if (ql2xprotguard) 3421 scsi_host_set_guard(host, ql2xprotguard); 3422 else 3423 scsi_host_set_guard(host, guard); 3424 } else 3425 base_vha->flags.difdix_supported = 0; 3426 } 3427 3428 ha->isp_ops->enable_intrs(ha); 3429 3430 if (IS_QLAFX00(ha)) { 3431 ret = qlafx00_fx_disc(base_vha, 3432 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3433 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3434 QLA_SG_ALL : 128; 3435 } 3436 3437 ret = scsi_add_host(host, &pdev->dev); 3438 if (ret) 3439 goto probe_failed; 3440 3441 base_vha->flags.init_done = 1; 3442 base_vha->flags.online = 1; 3443 ha->prev_minidump_failed = 0; 3444 3445 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3446 "Init done and hba is online.\n"); 3447 3448 if (qla_ini_mode_enabled(base_vha) || 3449 qla_dual_mode_enabled(base_vha)) 3450 scsi_scan_host(host); 3451 else 3452 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3453 "skipping scsi_scan_host() for non-initiator port\n"); 3454 3455 qla2x00_alloc_sysfs_attr(base_vha); 3456 3457 if (IS_QLAFX00(ha)) { 3458 ret = qlafx00_fx_disc(base_vha, 3459 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3460 3461 /* Register system information */ 3462 ret = qlafx00_fx_disc(base_vha, 3463 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3464 } 3465 3466 qla2x00_init_host_attr(base_vha); 3467 3468 qla2x00_dfs_setup(base_vha); 3469 3470 ql_log(ql_log_info, base_vha, 0x00fb, 3471 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3472 ql_log(ql_log_info, base_vha, 0x00fc, 3473 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3474 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3475 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3476 base_vha->host_no, 3477 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3478 3479 qlt_add_target(ha, base_vha); 3480 3481 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3482 3483 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3484 return -ENODEV; 3485 3486 if (ha->flags.detected_lr_sfp) { 3487 ql_log(ql_log_info, base_vha, 0xffff, 3488 "Reset chip to pick up LR SFP setting\n"); 3489 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3490 qla2xxx_wake_dpc(base_vha); 3491 } 3492 3493 return 0; 3494 3495 probe_failed: 3496 if (base_vha->timer_active) 3497 qla2x00_stop_timer(base_vha); 3498 base_vha->flags.online = 0; 3499 if (ha->dpc_thread) { 3500 struct task_struct *t = ha->dpc_thread; 3501 3502 ha->dpc_thread = NULL; 3503 kthread_stop(t); 3504 } 3505 3506 qla2x00_free_device(base_vha); 3507 scsi_host_put(base_vha->host); 3508 /* 3509 * Need to NULL out local req/rsp after 3510 * qla2x00_free_device => qla2x00_free_queues frees 3511 * what these are pointing to. Or else we'll 3512 * fall over below in qla2x00_free_req/rsp_que. 3513 */ 3514 req = NULL; 3515 rsp = NULL; 3516 3517 probe_hw_failed: 3518 qla2x00_mem_free(ha); 3519 qla2x00_free_req_que(ha, req); 3520 qla2x00_free_rsp_que(ha, rsp); 3521 qla2x00_clear_drv_active(ha); 3522 3523 iospace_config_failed: 3524 if (IS_P3P_TYPE(ha)) { 3525 if (!ha->nx_pcibase) 3526 iounmap((device_reg_t *)ha->nx_pcibase); 3527 if (!ql2xdbwr) 3528 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3529 } else { 3530 if (ha->iobase) 3531 iounmap(ha->iobase); 3532 if (ha->cregbase) 3533 iounmap(ha->cregbase); 3534 } 3535 pci_release_selected_regions(ha->pdev, ha->bars); 3536 kfree(ha); 3537 3538 disable_device: 3539 pci_disable_device(pdev); 3540 return ret; 3541 } 3542 3543 static void 3544 qla2x00_shutdown(struct pci_dev *pdev) 3545 { 3546 scsi_qla_host_t *vha; 3547 struct qla_hw_data *ha; 3548 3549 vha = pci_get_drvdata(pdev); 3550 ha = vha->hw; 3551 3552 ql_log(ql_log_info, vha, 0xfffa, 3553 "Adapter shutdown\n"); 3554 3555 /* 3556 * Prevent future board_disable and wait 3557 * until any pending board_disable has completed. 3558 */ 3559 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3560 cancel_work_sync(&ha->board_disable); 3561 3562 if (!atomic_read(&pdev->enable_cnt)) 3563 return; 3564 3565 /* Notify ISPFX00 firmware */ 3566 if (IS_QLAFX00(ha)) 3567 qlafx00_driver_shutdown(vha, 20); 3568 3569 /* Turn-off FCE trace */ 3570 if (ha->flags.fce_enabled) { 3571 qla2x00_disable_fce_trace(vha, NULL, NULL); 3572 ha->flags.fce_enabled = 0; 3573 } 3574 3575 /* Turn-off EFT trace */ 3576 if (ha->eft) 3577 qla2x00_disable_eft_trace(vha); 3578 3579 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3580 if (ha->flags.fw_started) 3581 qla2x00_abort_isp_cleanup(vha); 3582 } else { 3583 /* Stop currently executing firmware. */ 3584 qla2x00_try_to_stop_firmware(vha); 3585 } 3586 3587 /* Turn adapter off line */ 3588 vha->flags.online = 0; 3589 3590 /* turn-off interrupts on the card */ 3591 if (ha->interrupts_on) { 3592 vha->flags.init_done = 0; 3593 ha->isp_ops->disable_intrs(ha); 3594 } 3595 3596 qla2x00_free_irqs(vha); 3597 3598 qla2x00_free_fw_dump(ha); 3599 3600 pci_disable_device(pdev); 3601 ql_log(ql_log_info, vha, 0xfffe, 3602 "Adapter shutdown successfully.\n"); 3603 } 3604 3605 /* Deletes all the virtual ports for a given ha */ 3606 static void 3607 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3608 { 3609 scsi_qla_host_t *vha; 3610 unsigned long flags; 3611 3612 mutex_lock(&ha->vport_lock); 3613 while (ha->cur_vport_count) { 3614 spin_lock_irqsave(&ha->vport_slock, flags); 3615 3616 BUG_ON(base_vha->list.next == &ha->vp_list); 3617 /* This assumes first entry in ha->vp_list is always base vha */ 3618 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3619 scsi_host_get(vha->host); 3620 3621 spin_unlock_irqrestore(&ha->vport_slock, flags); 3622 mutex_unlock(&ha->vport_lock); 3623 3624 qla_nvme_delete(vha); 3625 3626 fc_vport_terminate(vha->fc_vport); 3627 scsi_host_put(vha->host); 3628 3629 mutex_lock(&ha->vport_lock); 3630 } 3631 mutex_unlock(&ha->vport_lock); 3632 } 3633 3634 /* Stops all deferred work threads */ 3635 static void 3636 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3637 { 3638 /* Cancel all work and destroy DPC workqueues */ 3639 if (ha->dpc_lp_wq) { 3640 cancel_work_sync(&ha->idc_aen); 3641 destroy_workqueue(ha->dpc_lp_wq); 3642 ha->dpc_lp_wq = NULL; 3643 } 3644 3645 if (ha->dpc_hp_wq) { 3646 cancel_work_sync(&ha->nic_core_reset); 3647 cancel_work_sync(&ha->idc_state_handler); 3648 cancel_work_sync(&ha->nic_core_unrecoverable); 3649 destroy_workqueue(ha->dpc_hp_wq); 3650 ha->dpc_hp_wq = NULL; 3651 } 3652 3653 /* Kill the kernel thread for this host */ 3654 if (ha->dpc_thread) { 3655 struct task_struct *t = ha->dpc_thread; 3656 3657 /* 3658 * qla2xxx_wake_dpc checks for ->dpc_thread 3659 * so we need to zero it out. 3660 */ 3661 ha->dpc_thread = NULL; 3662 kthread_stop(t); 3663 } 3664 } 3665 3666 static void 3667 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3668 { 3669 if (IS_QLA82XX(ha)) { 3670 3671 iounmap((device_reg_t *)ha->nx_pcibase); 3672 if (!ql2xdbwr) 3673 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3674 } else { 3675 if (ha->iobase) 3676 iounmap(ha->iobase); 3677 3678 if (ha->cregbase) 3679 iounmap(ha->cregbase); 3680 3681 if (ha->mqiobase) 3682 iounmap(ha->mqiobase); 3683 3684 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3685 iounmap(ha->msixbase); 3686 } 3687 } 3688 3689 static void 3690 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3691 { 3692 if (IS_QLA8044(ha)) { 3693 qla8044_idc_lock(ha); 3694 qla8044_clear_drv_active(ha); 3695 qla8044_idc_unlock(ha); 3696 } else if (IS_QLA82XX(ha)) { 3697 qla82xx_idc_lock(ha); 3698 qla82xx_clear_drv_active(ha); 3699 qla82xx_idc_unlock(ha); 3700 } 3701 } 3702 3703 static void 3704 qla2x00_remove_one(struct pci_dev *pdev) 3705 { 3706 scsi_qla_host_t *base_vha; 3707 struct qla_hw_data *ha; 3708 3709 base_vha = pci_get_drvdata(pdev); 3710 ha = base_vha->hw; 3711 ql_log(ql_log_info, base_vha, 0xb079, 3712 "Removing driver\n"); 3713 3714 /* Indicate device removal to prevent future board_disable and wait 3715 * until any pending board_disable has completed. */ 3716 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3717 cancel_work_sync(&ha->board_disable); 3718 3719 /* 3720 * If the PCI device is disabled then there was a PCI-disconnect and 3721 * qla2x00_disable_board_on_pci_error has taken care of most of the 3722 * resources. 3723 */ 3724 if (!atomic_read(&pdev->enable_cnt)) { 3725 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3726 base_vha->gnl.l, base_vha->gnl.ldma); 3727 3728 scsi_host_put(base_vha->host); 3729 kfree(ha); 3730 pci_set_drvdata(pdev, NULL); 3731 return; 3732 } 3733 qla2x00_wait_for_hba_ready(base_vha); 3734 3735 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3736 if (ha->flags.fw_started) 3737 qla2x00_abort_isp_cleanup(base_vha); 3738 } else if (!IS_QLAFX00(ha)) { 3739 if (IS_QLA8031(ha)) { 3740 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3741 "Clearing fcoe driver presence.\n"); 3742 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3743 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3744 "Error while clearing DRV-Presence.\n"); 3745 } 3746 3747 qla2x00_try_to_stop_firmware(base_vha); 3748 } 3749 3750 qla2x00_wait_for_sess_deletion(base_vha); 3751 3752 /* 3753 * if UNLOAD flag is already set, then continue unload, 3754 * where it was set first. 3755 */ 3756 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3757 return; 3758 3759 set_bit(UNLOADING, &base_vha->dpc_flags); 3760 3761 qla_nvme_delete(base_vha); 3762 3763 dma_free_coherent(&ha->pdev->dev, 3764 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3765 3766 vfree(base_vha->scan.l); 3767 3768 if (IS_QLAFX00(ha)) 3769 qlafx00_driver_shutdown(base_vha, 20); 3770 3771 qla2x00_delete_all_vps(ha, base_vha); 3772 3773 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3774 3775 qla2x00_dfs_remove(base_vha); 3776 3777 qla84xx_put_chip(base_vha); 3778 3779 /* Disable timer */ 3780 if (base_vha->timer_active) 3781 qla2x00_stop_timer(base_vha); 3782 3783 base_vha->flags.online = 0; 3784 3785 /* free DMA memory */ 3786 if (ha->exlogin_buf) 3787 qla2x00_free_exlogin_buffer(ha); 3788 3789 /* free DMA memory */ 3790 if (ha->exchoffld_buf) 3791 qla2x00_free_exchoffld_buffer(ha); 3792 3793 qla2x00_destroy_deferred_work(ha); 3794 3795 qlt_remove_target(ha, base_vha); 3796 3797 qla2x00_free_sysfs_attr(base_vha, true); 3798 3799 fc_remove_host(base_vha->host); 3800 qlt_remove_target_resources(ha); 3801 3802 scsi_remove_host(base_vha->host); 3803 3804 qla2x00_free_device(base_vha); 3805 3806 qla2x00_clear_drv_active(ha); 3807 3808 scsi_host_put(base_vha->host); 3809 3810 qla2x00_unmap_iobases(ha); 3811 3812 pci_release_selected_regions(ha->pdev, ha->bars); 3813 kfree(ha); 3814 3815 pci_disable_pcie_error_reporting(pdev); 3816 3817 pci_disable_device(pdev); 3818 } 3819 3820 static void 3821 qla2x00_free_device(scsi_qla_host_t *vha) 3822 { 3823 struct qla_hw_data *ha = vha->hw; 3824 3825 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3826 3827 /* Disable timer */ 3828 if (vha->timer_active) 3829 qla2x00_stop_timer(vha); 3830 3831 qla25xx_delete_queues(vha); 3832 vha->flags.online = 0; 3833 3834 /* turn-off interrupts on the card */ 3835 if (ha->interrupts_on) { 3836 vha->flags.init_done = 0; 3837 ha->isp_ops->disable_intrs(ha); 3838 } 3839 3840 qla2x00_free_fcports(vha); 3841 3842 qla2x00_free_irqs(vha); 3843 3844 /* Flush the work queue and remove it */ 3845 if (ha->wq) { 3846 flush_workqueue(ha->wq); 3847 destroy_workqueue(ha->wq); 3848 ha->wq = NULL; 3849 } 3850 3851 3852 qla2x00_mem_free(ha); 3853 3854 qla82xx_md_free(vha); 3855 3856 qla2x00_free_queues(ha); 3857 } 3858 3859 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3860 { 3861 fc_port_t *fcport, *tfcport; 3862 3863 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3864 list_del(&fcport->list); 3865 qla2x00_clear_loop_id(fcport); 3866 kfree(fcport); 3867 } 3868 } 3869 3870 static inline void 3871 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3872 int defer) 3873 { 3874 struct fc_rport *rport; 3875 scsi_qla_host_t *base_vha; 3876 unsigned long flags; 3877 3878 if (!fcport->rport) 3879 return; 3880 3881 rport = fcport->rport; 3882 if (defer) { 3883 base_vha = pci_get_drvdata(vha->hw->pdev); 3884 spin_lock_irqsave(vha->host->host_lock, flags); 3885 fcport->drport = rport; 3886 spin_unlock_irqrestore(vha->host->host_lock, flags); 3887 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3888 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3889 qla2xxx_wake_dpc(base_vha); 3890 } else { 3891 int now; 3892 if (rport) { 3893 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3894 "%s %8phN. rport %p roles %x\n", 3895 __func__, fcport->port_name, rport, 3896 rport->roles); 3897 fc_remote_port_delete(rport); 3898 } 3899 qlt_do_generation_tick(vha, &now); 3900 } 3901 } 3902 3903 /* 3904 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3905 * 3906 * Input: ha = adapter block pointer. fcport = port structure pointer. 3907 * 3908 * Return: None. 3909 * 3910 * Context: 3911 */ 3912 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3913 int do_login, int defer) 3914 { 3915 if (IS_QLAFX00(vha->hw)) { 3916 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3917 qla2x00_schedule_rport_del(vha, fcport, defer); 3918 return; 3919 } 3920 3921 if (atomic_read(&fcport->state) == FCS_ONLINE && 3922 vha->vp_idx == fcport->vha->vp_idx) { 3923 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3924 qla2x00_schedule_rport_del(vha, fcport, defer); 3925 } 3926 /* 3927 * We may need to retry the login, so don't change the state of the 3928 * port but do the retries. 3929 */ 3930 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3931 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3932 3933 if (!do_login) 3934 return; 3935 3936 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3937 } 3938 3939 /* 3940 * qla2x00_mark_all_devices_lost 3941 * Updates fcport state when device goes offline. 3942 * 3943 * Input: 3944 * ha = adapter block pointer. 3945 * fcport = port structure pointer. 3946 * 3947 * Return: 3948 * None. 3949 * 3950 * Context: 3951 */ 3952 void 3953 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3954 { 3955 fc_port_t *fcport; 3956 3957 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3958 "Mark all dev lost\n"); 3959 3960 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3961 fcport->scan_state = 0; 3962 qlt_schedule_sess_for_deletion(fcport); 3963 3964 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3965 continue; 3966 3967 /* 3968 * No point in marking the device as lost, if the device is 3969 * already DEAD. 3970 */ 3971 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3972 continue; 3973 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3974 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3975 if (defer) 3976 qla2x00_schedule_rport_del(vha, fcport, defer); 3977 else if (vha->vp_idx == fcport->vha->vp_idx) 3978 qla2x00_schedule_rport_del(vha, fcport, defer); 3979 } 3980 } 3981 } 3982 3983 /* 3984 * qla2x00_mem_alloc 3985 * Allocates adapter memory. 3986 * 3987 * Returns: 3988 * 0 = success. 3989 * !0 = failure. 3990 */ 3991 static int 3992 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3993 struct req_que **req, struct rsp_que **rsp) 3994 { 3995 char name[16]; 3996 3997 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3998 &ha->init_cb_dma, GFP_KERNEL); 3999 if (!ha->init_cb) 4000 goto fail; 4001 4002 if (qlt_mem_alloc(ha) < 0) 4003 goto fail_free_init_cb; 4004 4005 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4006 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4007 if (!ha->gid_list) 4008 goto fail_free_tgt_mem; 4009 4010 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4011 if (!ha->srb_mempool) 4012 goto fail_free_gid_list; 4013 4014 if (IS_P3P_TYPE(ha)) { 4015 /* Allocate cache for CT6 Ctx. */ 4016 if (!ctx_cachep) { 4017 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4018 sizeof(struct ct6_dsd), 0, 4019 SLAB_HWCACHE_ALIGN, NULL); 4020 if (!ctx_cachep) 4021 goto fail_free_srb_mempool; 4022 } 4023 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4024 ctx_cachep); 4025 if (!ha->ctx_mempool) 4026 goto fail_free_srb_mempool; 4027 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4028 "ctx_cachep=%p ctx_mempool=%p.\n", 4029 ctx_cachep, ha->ctx_mempool); 4030 } 4031 4032 /* Get memory for cached NVRAM */ 4033 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4034 if (!ha->nvram) 4035 goto fail_free_ctx_mempool; 4036 4037 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4038 ha->pdev->device); 4039 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4040 DMA_POOL_SIZE, 8, 0); 4041 if (!ha->s_dma_pool) 4042 goto fail_free_nvram; 4043 4044 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4045 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4046 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4047 4048 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4049 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4050 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4051 if (!ha->dl_dma_pool) { 4052 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4053 "Failed to allocate memory for dl_dma_pool.\n"); 4054 goto fail_s_dma_pool; 4055 } 4056 4057 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4058 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4059 if (!ha->fcp_cmnd_dma_pool) { 4060 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4061 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4062 goto fail_dl_dma_pool; 4063 } 4064 4065 if (ql2xenabledif) { 4066 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4067 struct dsd_dma *dsd, *nxt; 4068 uint i; 4069 /* Creata a DMA pool of buffers for DIF bundling */ 4070 ha->dif_bundl_pool = dma_pool_create(name, 4071 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4072 if (!ha->dif_bundl_pool) { 4073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4074 "%s: failed create dif_bundl_pool\n", 4075 __func__); 4076 goto fail_dif_bundl_dma_pool; 4077 } 4078 4079 INIT_LIST_HEAD(&ha->pool.good.head); 4080 INIT_LIST_HEAD(&ha->pool.unusable.head); 4081 ha->pool.good.count = 0; 4082 ha->pool.unusable.count = 0; 4083 for (i = 0; i < 128; i++) { 4084 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4085 if (!dsd) { 4086 ql_dbg_pci(ql_dbg_init, ha->pdev, 4087 0xe0ee, "%s: failed alloc dsd\n", 4088 __func__); 4089 return 1; 4090 } 4091 ha->dif_bundle_kallocs++; 4092 4093 dsd->dsd_addr = dma_pool_alloc( 4094 ha->dif_bundl_pool, GFP_ATOMIC, 4095 &dsd->dsd_list_dma); 4096 if (!dsd->dsd_addr) { 4097 ql_dbg_pci(ql_dbg_init, ha->pdev, 4098 0xe0ee, 4099 "%s: failed alloc ->dsd_addr\n", 4100 __func__); 4101 kfree(dsd); 4102 ha->dif_bundle_kallocs--; 4103 continue; 4104 } 4105 ha->dif_bundle_dma_allocs++; 4106 4107 /* 4108 * if DMA buffer crosses 4G boundary, 4109 * put it on bad list 4110 */ 4111 if (MSD(dsd->dsd_list_dma) ^ 4112 MSD(dsd->dsd_list_dma + bufsize)) { 4113 list_add_tail(&dsd->list, 4114 &ha->pool.unusable.head); 4115 ha->pool.unusable.count++; 4116 } else { 4117 list_add_tail(&dsd->list, 4118 &ha->pool.good.head); 4119 ha->pool.good.count++; 4120 } 4121 } 4122 4123 /* return the good ones back to the pool */ 4124 list_for_each_entry_safe(dsd, nxt, 4125 &ha->pool.good.head, list) { 4126 list_del(&dsd->list); 4127 dma_pool_free(ha->dif_bundl_pool, 4128 dsd->dsd_addr, dsd->dsd_list_dma); 4129 ha->dif_bundle_dma_allocs--; 4130 kfree(dsd); 4131 ha->dif_bundle_kallocs--; 4132 } 4133 4134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4135 "%s: dif dma pool (good=%u unusable=%u)\n", 4136 __func__, ha->pool.good.count, 4137 ha->pool.unusable.count); 4138 } 4139 4140 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4141 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4142 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4143 ha->dif_bundl_pool); 4144 } 4145 4146 /* Allocate memory for SNS commands */ 4147 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4148 /* Get consistent memory allocated for SNS commands */ 4149 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4150 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4151 if (!ha->sns_cmd) 4152 goto fail_dma_pool; 4153 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4154 "sns_cmd: %p.\n", ha->sns_cmd); 4155 } else { 4156 /* Get consistent memory allocated for MS IOCB */ 4157 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4158 &ha->ms_iocb_dma); 4159 if (!ha->ms_iocb) 4160 goto fail_dma_pool; 4161 /* Get consistent memory allocated for CT SNS commands */ 4162 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4163 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4164 if (!ha->ct_sns) 4165 goto fail_free_ms_iocb; 4166 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4167 "ms_iocb=%p ct_sns=%p.\n", 4168 ha->ms_iocb, ha->ct_sns); 4169 } 4170 4171 /* Allocate memory for request ring */ 4172 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4173 if (!*req) { 4174 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4175 "Failed to allocate memory for req.\n"); 4176 goto fail_req; 4177 } 4178 (*req)->length = req_len; 4179 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4180 ((*req)->length + 1) * sizeof(request_t), 4181 &(*req)->dma, GFP_KERNEL); 4182 if (!(*req)->ring) { 4183 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4184 "Failed to allocate memory for req_ring.\n"); 4185 goto fail_req_ring; 4186 } 4187 /* Allocate memory for response ring */ 4188 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4189 if (!*rsp) { 4190 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4191 "Failed to allocate memory for rsp.\n"); 4192 goto fail_rsp; 4193 } 4194 (*rsp)->hw = ha; 4195 (*rsp)->length = rsp_len; 4196 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4197 ((*rsp)->length + 1) * sizeof(response_t), 4198 &(*rsp)->dma, GFP_KERNEL); 4199 if (!(*rsp)->ring) { 4200 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4201 "Failed to allocate memory for rsp_ring.\n"); 4202 goto fail_rsp_ring; 4203 } 4204 (*req)->rsp = *rsp; 4205 (*rsp)->req = *req; 4206 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4207 "req=%p req->length=%d req->ring=%p rsp=%p " 4208 "rsp->length=%d rsp->ring=%p.\n", 4209 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4210 (*rsp)->ring); 4211 /* Allocate memory for NVRAM data for vports */ 4212 if (ha->nvram_npiv_size) { 4213 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4214 sizeof(struct qla_npiv_entry), 4215 GFP_KERNEL); 4216 if (!ha->npiv_info) { 4217 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4218 "Failed to allocate memory for npiv_info.\n"); 4219 goto fail_npiv_info; 4220 } 4221 } else 4222 ha->npiv_info = NULL; 4223 4224 /* Get consistent memory allocated for EX-INIT-CB. */ 4225 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4226 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4227 &ha->ex_init_cb_dma); 4228 if (!ha->ex_init_cb) 4229 goto fail_ex_init_cb; 4230 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4231 "ex_init_cb=%p.\n", ha->ex_init_cb); 4232 } 4233 4234 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4235 4236 /* Get consistent memory allocated for Async Port-Database. */ 4237 if (!IS_FWI2_CAPABLE(ha)) { 4238 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4239 &ha->async_pd_dma); 4240 if (!ha->async_pd) 4241 goto fail_async_pd; 4242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4243 "async_pd=%p.\n", ha->async_pd); 4244 } 4245 4246 INIT_LIST_HEAD(&ha->vp_list); 4247 4248 /* Allocate memory for our loop_id bitmap */ 4249 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4250 sizeof(long), 4251 GFP_KERNEL); 4252 if (!ha->loop_id_map) 4253 goto fail_loop_id_map; 4254 else { 4255 qla2x00_set_reserved_loop_ids(ha); 4256 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4257 "loop_id_map=%p.\n", ha->loop_id_map); 4258 } 4259 4260 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4261 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4262 if (!ha->sfp_data) { 4263 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4264 "Unable to allocate memory for SFP read-data.\n"); 4265 goto fail_sfp_data; 4266 } 4267 4268 return 0; 4269 4270 fail_sfp_data: 4271 kfree(ha->loop_id_map); 4272 fail_loop_id_map: 4273 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4274 fail_async_pd: 4275 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4276 fail_ex_init_cb: 4277 kfree(ha->npiv_info); 4278 fail_npiv_info: 4279 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4280 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4281 (*rsp)->ring = NULL; 4282 (*rsp)->dma = 0; 4283 fail_rsp_ring: 4284 kfree(*rsp); 4285 *rsp = NULL; 4286 fail_rsp: 4287 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4288 sizeof(request_t), (*req)->ring, (*req)->dma); 4289 (*req)->ring = NULL; 4290 (*req)->dma = 0; 4291 fail_req_ring: 4292 kfree(*req); 4293 *req = NULL; 4294 fail_req: 4295 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4296 ha->ct_sns, ha->ct_sns_dma); 4297 ha->ct_sns = NULL; 4298 ha->ct_sns_dma = 0; 4299 fail_free_ms_iocb: 4300 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4301 ha->ms_iocb = NULL; 4302 ha->ms_iocb_dma = 0; 4303 4304 if (ha->sns_cmd) 4305 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4306 ha->sns_cmd, ha->sns_cmd_dma); 4307 fail_dma_pool: 4308 if (ql2xenabledif) { 4309 struct dsd_dma *dsd, *nxt; 4310 4311 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4312 list) { 4313 list_del(&dsd->list); 4314 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4315 dsd->dsd_list_dma); 4316 ha->dif_bundle_dma_allocs--; 4317 kfree(dsd); 4318 ha->dif_bundle_kallocs--; 4319 ha->pool.unusable.count--; 4320 } 4321 dma_pool_destroy(ha->dif_bundl_pool); 4322 ha->dif_bundl_pool = NULL; 4323 } 4324 4325 fail_dif_bundl_dma_pool: 4326 if (IS_QLA82XX(ha) || ql2xenabledif) { 4327 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4328 ha->fcp_cmnd_dma_pool = NULL; 4329 } 4330 fail_dl_dma_pool: 4331 if (IS_QLA82XX(ha) || ql2xenabledif) { 4332 dma_pool_destroy(ha->dl_dma_pool); 4333 ha->dl_dma_pool = NULL; 4334 } 4335 fail_s_dma_pool: 4336 dma_pool_destroy(ha->s_dma_pool); 4337 ha->s_dma_pool = NULL; 4338 fail_free_nvram: 4339 kfree(ha->nvram); 4340 ha->nvram = NULL; 4341 fail_free_ctx_mempool: 4342 mempool_destroy(ha->ctx_mempool); 4343 ha->ctx_mempool = NULL; 4344 fail_free_srb_mempool: 4345 mempool_destroy(ha->srb_mempool); 4346 ha->srb_mempool = NULL; 4347 fail_free_gid_list: 4348 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4349 ha->gid_list, 4350 ha->gid_list_dma); 4351 ha->gid_list = NULL; 4352 ha->gid_list_dma = 0; 4353 fail_free_tgt_mem: 4354 qlt_mem_free(ha); 4355 fail_free_init_cb: 4356 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4357 ha->init_cb_dma); 4358 ha->init_cb = NULL; 4359 ha->init_cb_dma = 0; 4360 fail: 4361 ql_log(ql_log_fatal, NULL, 0x0030, 4362 "Memory allocation failure.\n"); 4363 return -ENOMEM; 4364 } 4365 4366 int 4367 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4368 { 4369 int rval; 4370 uint16_t size, max_cnt, temp; 4371 struct qla_hw_data *ha = vha->hw; 4372 4373 /* Return if we don't need to alloacate any extended logins */ 4374 if (!ql2xexlogins) 4375 return QLA_SUCCESS; 4376 4377 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4378 return QLA_SUCCESS; 4379 4380 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4381 max_cnt = 0; 4382 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4383 if (rval != QLA_SUCCESS) { 4384 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4385 "Failed to get exlogin status.\n"); 4386 return rval; 4387 } 4388 4389 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4390 temp *= size; 4391 4392 if (temp != ha->exlogin_size) { 4393 qla2x00_free_exlogin_buffer(ha); 4394 ha->exlogin_size = temp; 4395 4396 ql_log(ql_log_info, vha, 0xd024, 4397 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4398 max_cnt, size, temp); 4399 4400 ql_log(ql_log_info, vha, 0xd025, 4401 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4402 4403 /* Get consistent memory for extended logins */ 4404 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4405 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4406 if (!ha->exlogin_buf) { 4407 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4408 "Failed to allocate memory for exlogin_buf_dma.\n"); 4409 return -ENOMEM; 4410 } 4411 } 4412 4413 /* Now configure the dma buffer */ 4414 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4415 if (rval) { 4416 ql_log(ql_log_fatal, vha, 0xd033, 4417 "Setup extended login buffer ****FAILED****.\n"); 4418 qla2x00_free_exlogin_buffer(ha); 4419 } 4420 4421 return rval; 4422 } 4423 4424 /* 4425 * qla2x00_free_exlogin_buffer 4426 * 4427 * Input: 4428 * ha = adapter block pointer 4429 */ 4430 void 4431 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4432 { 4433 if (ha->exlogin_buf) { 4434 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4435 ha->exlogin_buf, ha->exlogin_buf_dma); 4436 ha->exlogin_buf = NULL; 4437 ha->exlogin_size = 0; 4438 } 4439 } 4440 4441 static void 4442 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4443 { 4444 u32 temp; 4445 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4446 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4447 4448 if (max_cnt > vha->hw->max_exchg) 4449 max_cnt = vha->hw->max_exchg; 4450 4451 if (qla_ini_mode_enabled(vha)) { 4452 if (vha->ql2xiniexchg > max_cnt) 4453 vha->ql2xiniexchg = max_cnt; 4454 4455 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4456 *ret_cnt = vha->ql2xiniexchg; 4457 4458 } else if (qla_tgt_mode_enabled(vha)) { 4459 if (vha->ql2xexchoffld > max_cnt) { 4460 vha->ql2xexchoffld = max_cnt; 4461 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4462 } 4463 4464 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4465 *ret_cnt = vha->ql2xexchoffld; 4466 } else if (qla_dual_mode_enabled(vha)) { 4467 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4468 if (temp > max_cnt) { 4469 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4470 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4471 temp = max_cnt; 4472 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4473 } 4474 4475 if (temp > FW_DEF_EXCHANGES_CNT) 4476 *ret_cnt = temp; 4477 } 4478 } 4479 4480 int 4481 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4482 { 4483 int rval; 4484 u16 size, max_cnt; 4485 u32 actual_cnt, totsz; 4486 struct qla_hw_data *ha = vha->hw; 4487 4488 if (!ha->flags.exchoffld_enabled) 4489 return QLA_SUCCESS; 4490 4491 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4492 return QLA_SUCCESS; 4493 4494 max_cnt = 0; 4495 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4496 if (rval != QLA_SUCCESS) { 4497 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4498 "Failed to get exlogin status.\n"); 4499 return rval; 4500 } 4501 4502 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4503 ql_log(ql_log_info, vha, 0xd014, 4504 "Actual exchange offload count: %d.\n", actual_cnt); 4505 4506 totsz = actual_cnt * size; 4507 4508 if (totsz != ha->exchoffld_size) { 4509 qla2x00_free_exchoffld_buffer(ha); 4510 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4511 ha->exchoffld_size = 0; 4512 ha->flags.exchoffld_enabled = 0; 4513 return QLA_SUCCESS; 4514 } 4515 4516 ha->exchoffld_size = totsz; 4517 4518 ql_log(ql_log_info, vha, 0xd016, 4519 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4520 max_cnt, actual_cnt, size, totsz); 4521 4522 ql_log(ql_log_info, vha, 0xd017, 4523 "Exchange Buffers requested size = 0x%x\n", 4524 ha->exchoffld_size); 4525 4526 /* Get consistent memory for extended logins */ 4527 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4528 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4529 if (!ha->exchoffld_buf) { 4530 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4531 "Failed to allocate memory for Exchange Offload.\n"); 4532 4533 if (ha->max_exchg > 4534 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4535 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4536 } else if (ha->max_exchg > 4537 (FW_DEF_EXCHANGES_CNT + 512)) { 4538 ha->max_exchg -= 512; 4539 } else { 4540 ha->flags.exchoffld_enabled = 0; 4541 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4542 "Disabling Exchange offload due to lack of memory\n"); 4543 } 4544 ha->exchoffld_size = 0; 4545 4546 return -ENOMEM; 4547 } 4548 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4549 /* pathological case */ 4550 qla2x00_free_exchoffld_buffer(ha); 4551 ha->exchoffld_size = 0; 4552 ha->flags.exchoffld_enabled = 0; 4553 ql_log(ql_log_info, vha, 0xd016, 4554 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4555 ha->exchoffld_size, actual_cnt, size, totsz); 4556 return 0; 4557 } 4558 4559 /* Now configure the dma buffer */ 4560 rval = qla_set_exchoffld_mem_cfg(vha); 4561 if (rval) { 4562 ql_log(ql_log_fatal, vha, 0xd02e, 4563 "Setup exchange offload buffer ****FAILED****.\n"); 4564 qla2x00_free_exchoffld_buffer(ha); 4565 } else { 4566 /* re-adjust number of target exchange */ 4567 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4568 4569 if (qla_ini_mode_enabled(vha)) 4570 icb->exchange_count = 0; 4571 else 4572 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4573 } 4574 4575 return rval; 4576 } 4577 4578 /* 4579 * qla2x00_free_exchoffld_buffer 4580 * 4581 * Input: 4582 * ha = adapter block pointer 4583 */ 4584 void 4585 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4586 { 4587 if (ha->exchoffld_buf) { 4588 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4589 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4590 ha->exchoffld_buf = NULL; 4591 ha->exchoffld_size = 0; 4592 } 4593 } 4594 4595 /* 4596 * qla2x00_free_fw_dump 4597 * Frees fw dump stuff. 4598 * 4599 * Input: 4600 * ha = adapter block pointer 4601 */ 4602 static void 4603 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4604 { 4605 if (ha->fce) 4606 dma_free_coherent(&ha->pdev->dev, 4607 FCE_SIZE, ha->fce, ha->fce_dma); 4608 4609 if (ha->eft) 4610 dma_free_coherent(&ha->pdev->dev, 4611 EFT_SIZE, ha->eft, ha->eft_dma); 4612 4613 if (ha->fw_dump) 4614 vfree(ha->fw_dump); 4615 if (ha->fw_dump_template) 4616 vfree(ha->fw_dump_template); 4617 4618 ha->fce = NULL; 4619 ha->fce_dma = 0; 4620 ha->eft = NULL; 4621 ha->eft_dma = 0; 4622 ha->fw_dumped = 0; 4623 ha->fw_dump_cap_flags = 0; 4624 ha->fw_dump_reading = 0; 4625 ha->fw_dump = NULL; 4626 ha->fw_dump_len = 0; 4627 ha->fw_dump_template = NULL; 4628 ha->fw_dump_template_len = 0; 4629 } 4630 4631 /* 4632 * qla2x00_mem_free 4633 * Frees all adapter allocated memory. 4634 * 4635 * Input: 4636 * ha = adapter block pointer. 4637 */ 4638 static void 4639 qla2x00_mem_free(struct qla_hw_data *ha) 4640 { 4641 qla2x00_free_fw_dump(ha); 4642 4643 if (ha->mctp_dump) 4644 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4645 ha->mctp_dump_dma); 4646 4647 mempool_destroy(ha->srb_mempool); 4648 4649 if (ha->dcbx_tlv) 4650 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4651 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4652 4653 if (ha->xgmac_data) 4654 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4655 ha->xgmac_data, ha->xgmac_data_dma); 4656 4657 if (ha->sns_cmd) 4658 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4659 ha->sns_cmd, ha->sns_cmd_dma); 4660 4661 if (ha->ct_sns) 4662 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4663 ha->ct_sns, ha->ct_sns_dma); 4664 4665 if (ha->sfp_data) 4666 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4667 ha->sfp_data_dma); 4668 4669 if (ha->ms_iocb) 4670 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4671 4672 if (ha->ex_init_cb) 4673 dma_pool_free(ha->s_dma_pool, 4674 ha->ex_init_cb, ha->ex_init_cb_dma); 4675 4676 if (ha->async_pd) 4677 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4678 4679 dma_pool_destroy(ha->s_dma_pool); 4680 4681 if (ha->gid_list) 4682 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4683 ha->gid_list, ha->gid_list_dma); 4684 4685 if (IS_QLA82XX(ha)) { 4686 if (!list_empty(&ha->gbl_dsd_list)) { 4687 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4688 4689 /* clean up allocated prev pool */ 4690 list_for_each_entry_safe(dsd_ptr, 4691 tdsd_ptr, &ha->gbl_dsd_list, list) { 4692 dma_pool_free(ha->dl_dma_pool, 4693 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4694 list_del(&dsd_ptr->list); 4695 kfree(dsd_ptr); 4696 } 4697 } 4698 } 4699 4700 dma_pool_destroy(ha->dl_dma_pool); 4701 4702 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4703 4704 mempool_destroy(ha->ctx_mempool); 4705 4706 if (ql2xenabledif) { 4707 struct dsd_dma *dsd, *nxt; 4708 4709 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4710 list) { 4711 list_del(&dsd->list); 4712 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4713 dsd->dsd_list_dma); 4714 ha->dif_bundle_dma_allocs--; 4715 kfree(dsd); 4716 ha->dif_bundle_kallocs--; 4717 ha->pool.unusable.count--; 4718 } 4719 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4720 list_del(&dsd->list); 4721 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4722 dsd->dsd_list_dma); 4723 ha->dif_bundle_dma_allocs--; 4724 kfree(dsd); 4725 ha->dif_bundle_kallocs--; 4726 } 4727 } 4728 4729 if (ha->dif_bundl_pool) 4730 dma_pool_destroy(ha->dif_bundl_pool); 4731 4732 qlt_mem_free(ha); 4733 4734 if (ha->init_cb) 4735 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4736 ha->init_cb, ha->init_cb_dma); 4737 4738 vfree(ha->optrom_buffer); 4739 kfree(ha->nvram); 4740 kfree(ha->npiv_info); 4741 kfree(ha->swl); 4742 kfree(ha->loop_id_map); 4743 4744 ha->srb_mempool = NULL; 4745 ha->ctx_mempool = NULL; 4746 ha->sns_cmd = NULL; 4747 ha->sns_cmd_dma = 0; 4748 ha->ct_sns = NULL; 4749 ha->ct_sns_dma = 0; 4750 ha->ms_iocb = NULL; 4751 ha->ms_iocb_dma = 0; 4752 ha->init_cb = NULL; 4753 ha->init_cb_dma = 0; 4754 ha->ex_init_cb = NULL; 4755 ha->ex_init_cb_dma = 0; 4756 ha->async_pd = NULL; 4757 ha->async_pd_dma = 0; 4758 ha->loop_id_map = NULL; 4759 ha->npiv_info = NULL; 4760 ha->optrom_buffer = NULL; 4761 ha->swl = NULL; 4762 ha->nvram = NULL; 4763 ha->mctp_dump = NULL; 4764 ha->dcbx_tlv = NULL; 4765 ha->xgmac_data = NULL; 4766 ha->sfp_data = NULL; 4767 4768 ha->s_dma_pool = NULL; 4769 ha->dl_dma_pool = NULL; 4770 ha->fcp_cmnd_dma_pool = NULL; 4771 4772 ha->gid_list = NULL; 4773 ha->gid_list_dma = 0; 4774 4775 ha->tgt.atio_ring = NULL; 4776 ha->tgt.atio_dma = 0; 4777 ha->tgt.tgt_vp_map = NULL; 4778 } 4779 4780 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4781 struct qla_hw_data *ha) 4782 { 4783 struct Scsi_Host *host; 4784 struct scsi_qla_host *vha = NULL; 4785 4786 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4787 if (!host) { 4788 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4789 "Failed to allocate host from the scsi layer, aborting.\n"); 4790 return NULL; 4791 } 4792 4793 /* Clear our data area */ 4794 vha = shost_priv(host); 4795 memset(vha, 0, sizeof(scsi_qla_host_t)); 4796 4797 vha->host = host; 4798 vha->host_no = host->host_no; 4799 vha->hw = ha; 4800 4801 vha->qlini_mode = ql2x_ini_mode; 4802 vha->ql2xexchoffld = ql2xexchoffld; 4803 vha->ql2xiniexchg = ql2xiniexchg; 4804 4805 INIT_LIST_HEAD(&vha->vp_fcports); 4806 INIT_LIST_HEAD(&vha->work_list); 4807 INIT_LIST_HEAD(&vha->list); 4808 INIT_LIST_HEAD(&vha->qla_cmd_list); 4809 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4810 INIT_LIST_HEAD(&vha->logo_list); 4811 INIT_LIST_HEAD(&vha->plogi_ack_list); 4812 INIT_LIST_HEAD(&vha->qp_list); 4813 INIT_LIST_HEAD(&vha->gnl.fcports); 4814 INIT_LIST_HEAD(&vha->nvme_rport_list); 4815 INIT_LIST_HEAD(&vha->gpnid_list); 4816 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4817 4818 spin_lock_init(&vha->work_lock); 4819 spin_lock_init(&vha->cmd_list_lock); 4820 init_waitqueue_head(&vha->fcport_waitQ); 4821 init_waitqueue_head(&vha->vref_waitq); 4822 4823 vha->gnl.size = sizeof(struct get_name_list_extended) * 4824 (ha->max_loop_id + 1); 4825 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4826 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4827 if (!vha->gnl.l) { 4828 ql_log(ql_log_fatal, vha, 0xd04a, 4829 "Alloc failed for name list.\n"); 4830 scsi_remove_host(vha->host); 4831 return NULL; 4832 } 4833 4834 /* todo: what about ext login? */ 4835 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4836 vha->scan.l = vmalloc(vha->scan.size); 4837 if (!vha->scan.l) { 4838 ql_log(ql_log_fatal, vha, 0xd04a, 4839 "Alloc failed for scan database.\n"); 4840 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4841 vha->gnl.l, vha->gnl.ldma); 4842 scsi_remove_host(vha->host); 4843 return NULL; 4844 } 4845 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4846 4847 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4848 ql_dbg(ql_dbg_init, vha, 0x0041, 4849 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4850 vha->host, vha->hw, vha, 4851 dev_name(&(ha->pdev->dev))); 4852 4853 return vha; 4854 } 4855 4856 struct qla_work_evt * 4857 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4858 { 4859 struct qla_work_evt *e; 4860 uint8_t bail; 4861 4862 QLA_VHA_MARK_BUSY(vha, bail); 4863 if (bail) 4864 return NULL; 4865 4866 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4867 if (!e) { 4868 QLA_VHA_MARK_NOT_BUSY(vha); 4869 return NULL; 4870 } 4871 4872 INIT_LIST_HEAD(&e->list); 4873 e->type = type; 4874 e->flags = QLA_EVT_FLAG_FREE; 4875 return e; 4876 } 4877 4878 int 4879 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4880 { 4881 unsigned long flags; 4882 bool q = false; 4883 4884 spin_lock_irqsave(&vha->work_lock, flags); 4885 list_add_tail(&e->list, &vha->work_list); 4886 4887 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4888 q = true; 4889 4890 spin_unlock_irqrestore(&vha->work_lock, flags); 4891 4892 if (q) 4893 queue_work(vha->hw->wq, &vha->iocb_work); 4894 4895 return QLA_SUCCESS; 4896 } 4897 4898 int 4899 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4900 u32 data) 4901 { 4902 struct qla_work_evt *e; 4903 4904 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4905 if (!e) 4906 return QLA_FUNCTION_FAILED; 4907 4908 e->u.aen.code = code; 4909 e->u.aen.data = data; 4910 return qla2x00_post_work(vha, e); 4911 } 4912 4913 int 4914 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4915 { 4916 struct qla_work_evt *e; 4917 4918 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4919 if (!e) 4920 return QLA_FUNCTION_FAILED; 4921 4922 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4923 return qla2x00_post_work(vha, e); 4924 } 4925 4926 #define qla2x00_post_async_work(name, type) \ 4927 int qla2x00_post_async_##name##_work( \ 4928 struct scsi_qla_host *vha, \ 4929 fc_port_t *fcport, uint16_t *data) \ 4930 { \ 4931 struct qla_work_evt *e; \ 4932 \ 4933 e = qla2x00_alloc_work(vha, type); \ 4934 if (!e) \ 4935 return QLA_FUNCTION_FAILED; \ 4936 \ 4937 e->u.logio.fcport = fcport; \ 4938 if (data) { \ 4939 e->u.logio.data[0] = data[0]; \ 4940 e->u.logio.data[1] = data[1]; \ 4941 } \ 4942 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4943 return qla2x00_post_work(vha, e); \ 4944 } 4945 4946 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4947 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4948 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4949 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4950 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4951 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4952 4953 int 4954 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4955 { 4956 struct qla_work_evt *e; 4957 4958 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4959 if (!e) 4960 return QLA_FUNCTION_FAILED; 4961 4962 e->u.uevent.code = code; 4963 return qla2x00_post_work(vha, e); 4964 } 4965 4966 static void 4967 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4968 { 4969 char event_string[40]; 4970 char *envp[] = { event_string, NULL }; 4971 4972 switch (code) { 4973 case QLA_UEVENT_CODE_FW_DUMP: 4974 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4975 vha->host_no); 4976 break; 4977 default: 4978 /* do nothing */ 4979 break; 4980 } 4981 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4982 } 4983 4984 int 4985 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4986 uint32_t *data, int cnt) 4987 { 4988 struct qla_work_evt *e; 4989 4990 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4991 if (!e) 4992 return QLA_FUNCTION_FAILED; 4993 4994 e->u.aenfx.evtcode = evtcode; 4995 e->u.aenfx.count = cnt; 4996 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4997 return qla2x00_post_work(vha, e); 4998 } 4999 5000 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5001 { 5002 unsigned long flags; 5003 5004 if (IS_SW_RESV_ADDR(fcport->d_id)) 5005 return; 5006 5007 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5008 if (fcport->disc_state == DSC_UPD_FCPORT) { 5009 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5010 return; 5011 } 5012 fcport->jiffies_at_registration = jiffies; 5013 fcport->sec_since_registration = 0; 5014 fcport->next_disc_state = DSC_DELETED; 5015 fcport->disc_state = DSC_UPD_FCPORT; 5016 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5017 5018 queue_work(system_unbound_wq, &fcport->reg_work); 5019 } 5020 5021 static 5022 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5023 { 5024 unsigned long flags; 5025 fc_port_t *fcport = NULL, *tfcp; 5026 struct qlt_plogi_ack_t *pla = 5027 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5028 uint8_t free_fcport = 0; 5029 5030 ql_dbg(ql_dbg_disc, vha, 0xffff, 5031 "%s %d %8phC enter\n", 5032 __func__, __LINE__, e->u.new_sess.port_name); 5033 5034 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5035 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5036 if (fcport) { 5037 fcport->d_id = e->u.new_sess.id; 5038 if (pla) { 5039 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5040 memcpy(fcport->node_name, 5041 pla->iocb.u.isp24.u.plogi.node_name, 5042 WWN_SIZE); 5043 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5044 /* we took an extra ref_count to prevent PLOGI ACK when 5045 * fcport/sess has not been created. 5046 */ 5047 pla->ref_count--; 5048 } 5049 } else { 5050 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5051 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5052 if (fcport) { 5053 fcport->d_id = e->u.new_sess.id; 5054 fcport->flags |= FCF_FABRIC_DEVICE; 5055 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5056 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP) 5057 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 5058 5059 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) { 5060 fcport->fc4_type = FC4_TYPE_OTHER; 5061 fcport->fc4f_nvme = FC4_TYPE_NVME; 5062 } 5063 5064 memcpy(fcport->port_name, e->u.new_sess.port_name, 5065 WWN_SIZE); 5066 } else { 5067 ql_dbg(ql_dbg_disc, vha, 0xffff, 5068 "%s %8phC mem alloc fail.\n", 5069 __func__, e->u.new_sess.port_name); 5070 5071 if (pla) 5072 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5073 return; 5074 } 5075 5076 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5077 /* search again to make sure no one else got ahead */ 5078 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5079 e->u.new_sess.port_name, 1); 5080 if (tfcp) { 5081 /* should rarily happen */ 5082 ql_dbg(ql_dbg_disc, vha, 0xffff, 5083 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5084 __func__, tfcp->port_name, tfcp->disc_state, 5085 tfcp->fw_login_state); 5086 5087 free_fcport = 1; 5088 } else { 5089 list_add_tail(&fcport->list, &vha->vp_fcports); 5090 5091 } 5092 if (pla) { 5093 qlt_plogi_ack_link(vha, pla, fcport, 5094 QLT_PLOGI_LINK_SAME_WWN); 5095 pla->ref_count--; 5096 } 5097 } 5098 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5099 5100 if (fcport) { 5101 fcport->id_changed = 1; 5102 fcport->scan_state = QLA_FCPORT_FOUND; 5103 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5104 5105 if (pla) { 5106 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5107 u16 wd3_lo; 5108 5109 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5110 fcport->local = 0; 5111 fcport->loop_id = 5112 le16_to_cpu( 5113 pla->iocb.u.isp24.nport_handle); 5114 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5115 wd3_lo = 5116 le16_to_cpu( 5117 pla->iocb.u.isp24.u.prli.wd3_lo); 5118 5119 if (wd3_lo & BIT_7) 5120 fcport->conf_compl_supported = 1; 5121 5122 if ((wd3_lo & BIT_4) == 0) 5123 fcport->port_type = FCT_INITIATOR; 5124 else 5125 fcport->port_type = FCT_TARGET; 5126 } 5127 qlt_plogi_ack_unref(vha, pla); 5128 } else { 5129 fc_port_t *dfcp = NULL; 5130 5131 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5132 tfcp = qla2x00_find_fcport_by_nportid(vha, 5133 &e->u.new_sess.id, 1); 5134 if (tfcp && (tfcp != fcport)) { 5135 /* 5136 * We have a conflict fcport with same NportID. 5137 */ 5138 ql_dbg(ql_dbg_disc, vha, 0xffff, 5139 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5140 __func__, tfcp->port_name, tfcp->disc_state, 5141 tfcp->fw_login_state); 5142 5143 switch (tfcp->disc_state) { 5144 case DSC_DELETED: 5145 break; 5146 case DSC_DELETE_PEND: 5147 fcport->login_pause = 1; 5148 tfcp->conflict = fcport; 5149 break; 5150 default: 5151 fcport->login_pause = 1; 5152 tfcp->conflict = fcport; 5153 dfcp = tfcp; 5154 break; 5155 } 5156 } 5157 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5158 if (dfcp) 5159 qlt_schedule_sess_for_deletion(tfcp); 5160 5161 5162 if (N2N_TOPO(vha->hw)) 5163 fcport->flags &= ~FCF_FABRIC_DEVICE; 5164 5165 if (N2N_TOPO(vha->hw)) { 5166 if (vha->flags.nvme_enabled) { 5167 fcport->fc4f_nvme = 1; 5168 fcport->n2n_flag = 1; 5169 } 5170 fcport->fw_login_state = 0; 5171 /* 5172 * wait link init done before sending login 5173 */ 5174 } else { 5175 qla24xx_fcport_handle_login(vha, fcport); 5176 } 5177 } 5178 } 5179 5180 if (free_fcport) { 5181 qla2x00_free_fcport(fcport); 5182 if (pla) 5183 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5184 } 5185 } 5186 5187 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5188 { 5189 struct srb *sp = e->u.iosb.sp; 5190 int rval; 5191 5192 rval = qla2x00_start_sp(sp); 5193 if (rval != QLA_SUCCESS) { 5194 ql_dbg(ql_dbg_disc, vha, 0x2043, 5195 "%s: %s: Re-issue IOCB failed (%d).\n", 5196 __func__, sp->name, rval); 5197 qla24xx_sp_unmap(vha, sp); 5198 } 5199 } 5200 5201 void 5202 qla2x00_do_work(struct scsi_qla_host *vha) 5203 { 5204 struct qla_work_evt *e, *tmp; 5205 unsigned long flags; 5206 LIST_HEAD(work); 5207 int rc; 5208 5209 spin_lock_irqsave(&vha->work_lock, flags); 5210 list_splice_init(&vha->work_list, &work); 5211 spin_unlock_irqrestore(&vha->work_lock, flags); 5212 5213 list_for_each_entry_safe(e, tmp, &work, list) { 5214 rc = QLA_SUCCESS; 5215 switch (e->type) { 5216 case QLA_EVT_AEN: 5217 fc_host_post_event(vha->host, fc_get_event_number(), 5218 e->u.aen.code, e->u.aen.data); 5219 break; 5220 case QLA_EVT_IDC_ACK: 5221 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5222 break; 5223 case QLA_EVT_ASYNC_LOGIN: 5224 qla2x00_async_login(vha, e->u.logio.fcport, 5225 e->u.logio.data); 5226 break; 5227 case QLA_EVT_ASYNC_LOGOUT: 5228 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5229 break; 5230 case QLA_EVT_ASYNC_LOGOUT_DONE: 5231 qla2x00_async_logout_done(vha, e->u.logio.fcport, 5232 e->u.logio.data); 5233 break; 5234 case QLA_EVT_ASYNC_ADISC: 5235 qla2x00_async_adisc(vha, e->u.logio.fcport, 5236 e->u.logio.data); 5237 break; 5238 case QLA_EVT_UEVENT: 5239 qla2x00_uevent_emit(vha, e->u.uevent.code); 5240 break; 5241 case QLA_EVT_AENFX: 5242 qlafx00_process_aen(vha, e); 5243 break; 5244 case QLA_EVT_GPNID: 5245 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5246 break; 5247 case QLA_EVT_UNMAP: 5248 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5249 break; 5250 case QLA_EVT_RELOGIN: 5251 qla2x00_relogin(vha); 5252 break; 5253 case QLA_EVT_NEW_SESS: 5254 qla24xx_create_new_sess(vha, e); 5255 break; 5256 case QLA_EVT_GPDB: 5257 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5258 e->u.fcport.opt); 5259 break; 5260 case QLA_EVT_PRLI: 5261 qla24xx_async_prli(vha, e->u.fcport.fcport); 5262 break; 5263 case QLA_EVT_GPSC: 5264 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5265 break; 5266 case QLA_EVT_GNL: 5267 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5268 break; 5269 case QLA_EVT_NACK: 5270 qla24xx_do_nack_work(vha, e); 5271 break; 5272 case QLA_EVT_ASYNC_PRLO: 5273 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5274 break; 5275 case QLA_EVT_ASYNC_PRLO_DONE: 5276 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5277 e->u.logio.data); 5278 break; 5279 case QLA_EVT_GPNFT: 5280 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5281 e->u.gpnft.sp); 5282 break; 5283 case QLA_EVT_GPNFT_DONE: 5284 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5285 break; 5286 case QLA_EVT_GNNFT_DONE: 5287 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5288 break; 5289 case QLA_EVT_GNNID: 5290 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5291 break; 5292 case QLA_EVT_GFPNID: 5293 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5294 break; 5295 case QLA_EVT_SP_RETRY: 5296 qla_sp_retry(vha, e); 5297 break; 5298 case QLA_EVT_IIDMA: 5299 qla_do_iidma_work(vha, e->u.fcport.fcport); 5300 break; 5301 case QLA_EVT_ELS_PLOGI: 5302 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5303 e->u.fcport.fcport, false); 5304 break; 5305 } 5306 5307 if (rc == EAGAIN) { 5308 /* put 'work' at head of 'vha->work_list' */ 5309 spin_lock_irqsave(&vha->work_lock, flags); 5310 list_splice(&work, &vha->work_list); 5311 spin_unlock_irqrestore(&vha->work_lock, flags); 5312 break; 5313 } 5314 list_del_init(&e->list); 5315 if (e->flags & QLA_EVT_FLAG_FREE) 5316 kfree(e); 5317 5318 /* For each work completed decrement vha ref count */ 5319 QLA_VHA_MARK_NOT_BUSY(vha); 5320 } 5321 } 5322 5323 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5324 { 5325 struct qla_work_evt *e; 5326 5327 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5328 5329 if (!e) { 5330 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5331 return QLA_FUNCTION_FAILED; 5332 } 5333 5334 return qla2x00_post_work(vha, e); 5335 } 5336 5337 /* Relogins all the fcports of a vport 5338 * Context: dpc thread 5339 */ 5340 void qla2x00_relogin(struct scsi_qla_host *vha) 5341 { 5342 fc_port_t *fcport; 5343 int status, relogin_needed = 0; 5344 struct event_arg ea; 5345 5346 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5347 /* 5348 * If the port is not ONLINE then try to login 5349 * to it if we haven't run out of retries. 5350 */ 5351 if (atomic_read(&fcport->state) != FCS_ONLINE && 5352 fcport->login_retry) { 5353 if (fcport->scan_state != QLA_FCPORT_FOUND || 5354 fcport->disc_state == DSC_LOGIN_COMPLETE) 5355 continue; 5356 5357 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5358 fcport->disc_state == DSC_DELETE_PEND) { 5359 relogin_needed = 1; 5360 } else { 5361 if (vha->hw->current_topology != ISP_CFG_NL) { 5362 memset(&ea, 0, sizeof(ea)); 5363 ea.event = FCME_RELOGIN; 5364 ea.fcport = fcport; 5365 qla2x00_fcport_event_handler(vha, &ea); 5366 } else if (vha->hw->current_topology == 5367 ISP_CFG_NL) { 5368 fcport->login_retry--; 5369 status = 5370 qla2x00_local_device_login(vha, 5371 fcport); 5372 if (status == QLA_SUCCESS) { 5373 fcport->old_loop_id = 5374 fcport->loop_id; 5375 ql_dbg(ql_dbg_disc, vha, 0x2003, 5376 "Port login OK: logged in ID 0x%x.\n", 5377 fcport->loop_id); 5378 qla2x00_update_fcport 5379 (vha, fcport); 5380 } else if (status == 1) { 5381 set_bit(RELOGIN_NEEDED, 5382 &vha->dpc_flags); 5383 /* retry the login again */ 5384 ql_dbg(ql_dbg_disc, vha, 0x2007, 5385 "Retrying %d login again loop_id 0x%x.\n", 5386 fcport->login_retry, 5387 fcport->loop_id); 5388 } else { 5389 fcport->login_retry = 0; 5390 } 5391 5392 if (fcport->login_retry == 0 && 5393 status != QLA_SUCCESS) 5394 qla2x00_clear_loop_id(fcport); 5395 } 5396 } 5397 } 5398 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5399 break; 5400 } 5401 5402 if (relogin_needed) 5403 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5404 5405 ql_dbg(ql_dbg_disc, vha, 0x400e, 5406 "Relogin end.\n"); 5407 } 5408 5409 /* Schedule work on any of the dpc-workqueues */ 5410 void 5411 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5412 { 5413 struct qla_hw_data *ha = base_vha->hw; 5414 5415 switch (work_code) { 5416 case MBA_IDC_AEN: /* 0x8200 */ 5417 if (ha->dpc_lp_wq) 5418 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5419 break; 5420 5421 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5422 if (!ha->flags.nic_core_reset_hdlr_active) { 5423 if (ha->dpc_hp_wq) 5424 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5425 } else 5426 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5427 "NIC Core reset is already active. Skip " 5428 "scheduling it again.\n"); 5429 break; 5430 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5431 if (ha->dpc_hp_wq) 5432 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5433 break; 5434 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5435 if (ha->dpc_hp_wq) 5436 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5437 break; 5438 default: 5439 ql_log(ql_log_warn, base_vha, 0xb05f, 5440 "Unknown work-code=0x%x.\n", work_code); 5441 } 5442 5443 return; 5444 } 5445 5446 /* Work: Perform NIC Core Unrecoverable state handling */ 5447 void 5448 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5449 { 5450 struct qla_hw_data *ha = 5451 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5452 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5453 uint32_t dev_state = 0; 5454 5455 qla83xx_idc_lock(base_vha, 0); 5456 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5457 qla83xx_reset_ownership(base_vha); 5458 if (ha->flags.nic_core_reset_owner) { 5459 ha->flags.nic_core_reset_owner = 0; 5460 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5461 QLA8XXX_DEV_FAILED); 5462 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5463 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5464 } 5465 qla83xx_idc_unlock(base_vha, 0); 5466 } 5467 5468 /* Work: Execute IDC state handler */ 5469 void 5470 qla83xx_idc_state_handler_work(struct work_struct *work) 5471 { 5472 struct qla_hw_data *ha = 5473 container_of(work, struct qla_hw_data, idc_state_handler); 5474 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5475 uint32_t dev_state = 0; 5476 5477 qla83xx_idc_lock(base_vha, 0); 5478 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5479 if (dev_state == QLA8XXX_DEV_FAILED || 5480 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5481 qla83xx_idc_state_handler(base_vha); 5482 qla83xx_idc_unlock(base_vha, 0); 5483 } 5484 5485 static int 5486 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5487 { 5488 int rval = QLA_SUCCESS; 5489 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5490 uint32_t heart_beat_counter1, heart_beat_counter2; 5491 5492 do { 5493 if (time_after(jiffies, heart_beat_wait)) { 5494 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5495 "Nic Core f/w is not alive.\n"); 5496 rval = QLA_FUNCTION_FAILED; 5497 break; 5498 } 5499 5500 qla83xx_idc_lock(base_vha, 0); 5501 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5502 &heart_beat_counter1); 5503 qla83xx_idc_unlock(base_vha, 0); 5504 msleep(100); 5505 qla83xx_idc_lock(base_vha, 0); 5506 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5507 &heart_beat_counter2); 5508 qla83xx_idc_unlock(base_vha, 0); 5509 } while (heart_beat_counter1 == heart_beat_counter2); 5510 5511 return rval; 5512 } 5513 5514 /* Work: Perform NIC Core Reset handling */ 5515 void 5516 qla83xx_nic_core_reset_work(struct work_struct *work) 5517 { 5518 struct qla_hw_data *ha = 5519 container_of(work, struct qla_hw_data, nic_core_reset); 5520 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5521 uint32_t dev_state = 0; 5522 5523 if (IS_QLA2031(ha)) { 5524 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5525 ql_log(ql_log_warn, base_vha, 0xb081, 5526 "Failed to dump mctp\n"); 5527 return; 5528 } 5529 5530 if (!ha->flags.nic_core_reset_hdlr_active) { 5531 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5532 qla83xx_idc_lock(base_vha, 0); 5533 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5534 &dev_state); 5535 qla83xx_idc_unlock(base_vha, 0); 5536 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5537 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5538 "Nic Core f/w is alive.\n"); 5539 return; 5540 } 5541 } 5542 5543 ha->flags.nic_core_reset_hdlr_active = 1; 5544 if (qla83xx_nic_core_reset(base_vha)) { 5545 /* NIC Core reset failed. */ 5546 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5547 "NIC Core reset failed.\n"); 5548 } 5549 ha->flags.nic_core_reset_hdlr_active = 0; 5550 } 5551 } 5552 5553 /* Work: Handle 8200 IDC aens */ 5554 void 5555 qla83xx_service_idc_aen(struct work_struct *work) 5556 { 5557 struct qla_hw_data *ha = 5558 container_of(work, struct qla_hw_data, idc_aen); 5559 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5560 uint32_t dev_state, idc_control; 5561 5562 qla83xx_idc_lock(base_vha, 0); 5563 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5564 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5565 qla83xx_idc_unlock(base_vha, 0); 5566 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5567 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5568 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5569 "Application requested NIC Core Reset.\n"); 5570 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5571 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5572 QLA_SUCCESS) { 5573 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5574 "Other protocol driver requested NIC Core Reset.\n"); 5575 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5576 } 5577 } else if (dev_state == QLA8XXX_DEV_FAILED || 5578 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5579 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5580 } 5581 } 5582 5583 static void 5584 qla83xx_wait_logic(void) 5585 { 5586 int i; 5587 5588 /* Yield CPU */ 5589 if (!in_interrupt()) { 5590 /* 5591 * Wait about 200ms before retrying again. 5592 * This controls the number of retries for single 5593 * lock operation. 5594 */ 5595 msleep(100); 5596 schedule(); 5597 } else { 5598 for (i = 0; i < 20; i++) 5599 cpu_relax(); /* This a nop instr on i386 */ 5600 } 5601 } 5602 5603 static int 5604 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5605 { 5606 int rval; 5607 uint32_t data; 5608 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5609 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5610 struct qla_hw_data *ha = base_vha->hw; 5611 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5612 "Trying force recovery of the IDC lock.\n"); 5613 5614 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5615 if (rval) 5616 return rval; 5617 5618 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5619 return QLA_SUCCESS; 5620 } else { 5621 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5622 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5623 data); 5624 if (rval) 5625 return rval; 5626 5627 msleep(200); 5628 5629 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5630 &data); 5631 if (rval) 5632 return rval; 5633 5634 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5635 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5636 ~(idc_lck_rcvry_stage_mask)); 5637 rval = qla83xx_wr_reg(base_vha, 5638 QLA83XX_IDC_LOCK_RECOVERY, data); 5639 if (rval) 5640 return rval; 5641 5642 /* Forcefully perform IDC UnLock */ 5643 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5644 &data); 5645 if (rval) 5646 return rval; 5647 /* Clear lock-id by setting 0xff */ 5648 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5649 0xff); 5650 if (rval) 5651 return rval; 5652 /* Clear lock-recovery by setting 0x0 */ 5653 rval = qla83xx_wr_reg(base_vha, 5654 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5655 if (rval) 5656 return rval; 5657 } else 5658 return QLA_SUCCESS; 5659 } 5660 5661 return rval; 5662 } 5663 5664 static int 5665 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5666 { 5667 int rval = QLA_SUCCESS; 5668 uint32_t o_drv_lockid, n_drv_lockid; 5669 unsigned long lock_recovery_timeout; 5670 5671 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5672 retry_lockid: 5673 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5674 if (rval) 5675 goto exit; 5676 5677 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5678 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5679 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5680 return QLA_SUCCESS; 5681 else 5682 return QLA_FUNCTION_FAILED; 5683 } 5684 5685 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5686 if (rval) 5687 goto exit; 5688 5689 if (o_drv_lockid == n_drv_lockid) { 5690 qla83xx_wait_logic(); 5691 goto retry_lockid; 5692 } else 5693 return QLA_SUCCESS; 5694 5695 exit: 5696 return rval; 5697 } 5698 5699 void 5700 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5701 { 5702 uint16_t options = (requester_id << 15) | BIT_6; 5703 uint32_t data; 5704 uint32_t lock_owner; 5705 struct qla_hw_data *ha = base_vha->hw; 5706 5707 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5708 retry_lock: 5709 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5710 == QLA_SUCCESS) { 5711 if (data) { 5712 /* Setting lock-id to our function-number */ 5713 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5714 ha->portnum); 5715 } else { 5716 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5717 &lock_owner); 5718 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5719 "Failed to acquire IDC lock, acquired by %d, " 5720 "retrying...\n", lock_owner); 5721 5722 /* Retry/Perform IDC-Lock recovery */ 5723 if (qla83xx_idc_lock_recovery(base_vha) 5724 == QLA_SUCCESS) { 5725 qla83xx_wait_logic(); 5726 goto retry_lock; 5727 } else 5728 ql_log(ql_log_warn, base_vha, 0xb075, 5729 "IDC Lock recovery FAILED.\n"); 5730 } 5731 5732 } 5733 5734 return; 5735 5736 /* XXX: IDC-lock implementation using access-control mbx */ 5737 retry_lock2: 5738 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5739 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5740 "Failed to acquire IDC lock. retrying...\n"); 5741 /* Retry/Perform IDC-Lock recovery */ 5742 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5743 qla83xx_wait_logic(); 5744 goto retry_lock2; 5745 } else 5746 ql_log(ql_log_warn, base_vha, 0xb076, 5747 "IDC Lock recovery FAILED.\n"); 5748 } 5749 5750 return; 5751 } 5752 5753 void 5754 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5755 { 5756 #if 0 5757 uint16_t options = (requester_id << 15) | BIT_7; 5758 #endif 5759 uint16_t retry; 5760 uint32_t data; 5761 struct qla_hw_data *ha = base_vha->hw; 5762 5763 /* IDC-unlock implementation using driver-unlock/lock-id 5764 * remote registers 5765 */ 5766 retry = 0; 5767 retry_unlock: 5768 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5769 == QLA_SUCCESS) { 5770 if (data == ha->portnum) { 5771 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5772 /* Clearing lock-id by setting 0xff */ 5773 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5774 } else if (retry < 10) { 5775 /* SV: XXX: IDC unlock retrying needed here? */ 5776 5777 /* Retry for IDC-unlock */ 5778 qla83xx_wait_logic(); 5779 retry++; 5780 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5781 "Failed to release IDC lock, retrying=%d\n", retry); 5782 goto retry_unlock; 5783 } 5784 } else if (retry < 10) { 5785 /* Retry for IDC-unlock */ 5786 qla83xx_wait_logic(); 5787 retry++; 5788 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5789 "Failed to read drv-lockid, retrying=%d\n", retry); 5790 goto retry_unlock; 5791 } 5792 5793 return; 5794 5795 #if 0 5796 /* XXX: IDC-unlock implementation using access-control mbx */ 5797 retry = 0; 5798 retry_unlock2: 5799 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5800 if (retry < 10) { 5801 /* Retry for IDC-unlock */ 5802 qla83xx_wait_logic(); 5803 retry++; 5804 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5805 "Failed to release IDC lock, retrying=%d\n", retry); 5806 goto retry_unlock2; 5807 } 5808 } 5809 5810 return; 5811 #endif 5812 } 5813 5814 int 5815 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5816 { 5817 int rval = QLA_SUCCESS; 5818 struct qla_hw_data *ha = vha->hw; 5819 uint32_t drv_presence; 5820 5821 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5822 if (rval == QLA_SUCCESS) { 5823 drv_presence |= (1 << ha->portnum); 5824 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5825 drv_presence); 5826 } 5827 5828 return rval; 5829 } 5830 5831 int 5832 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5833 { 5834 int rval = QLA_SUCCESS; 5835 5836 qla83xx_idc_lock(vha, 0); 5837 rval = __qla83xx_set_drv_presence(vha); 5838 qla83xx_idc_unlock(vha, 0); 5839 5840 return rval; 5841 } 5842 5843 int 5844 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5845 { 5846 int rval = QLA_SUCCESS; 5847 struct qla_hw_data *ha = vha->hw; 5848 uint32_t drv_presence; 5849 5850 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5851 if (rval == QLA_SUCCESS) { 5852 drv_presence &= ~(1 << ha->portnum); 5853 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5854 drv_presence); 5855 } 5856 5857 return rval; 5858 } 5859 5860 int 5861 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5862 { 5863 int rval = QLA_SUCCESS; 5864 5865 qla83xx_idc_lock(vha, 0); 5866 rval = __qla83xx_clear_drv_presence(vha); 5867 qla83xx_idc_unlock(vha, 0); 5868 5869 return rval; 5870 } 5871 5872 static void 5873 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5874 { 5875 struct qla_hw_data *ha = vha->hw; 5876 uint32_t drv_ack, drv_presence; 5877 unsigned long ack_timeout; 5878 5879 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5880 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5881 while (1) { 5882 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5883 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5884 if ((drv_ack & drv_presence) == drv_presence) 5885 break; 5886 5887 if (time_after_eq(jiffies, ack_timeout)) { 5888 ql_log(ql_log_warn, vha, 0xb067, 5889 "RESET ACK TIMEOUT! drv_presence=0x%x " 5890 "drv_ack=0x%x\n", drv_presence, drv_ack); 5891 /* 5892 * The function(s) which did not ack in time are forced 5893 * to withdraw any further participation in the IDC 5894 * reset. 5895 */ 5896 if (drv_ack != drv_presence) 5897 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5898 drv_ack); 5899 break; 5900 } 5901 5902 qla83xx_idc_unlock(vha, 0); 5903 msleep(1000); 5904 qla83xx_idc_lock(vha, 0); 5905 } 5906 5907 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5908 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5909 } 5910 5911 static int 5912 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5913 { 5914 int rval = QLA_SUCCESS; 5915 uint32_t idc_control; 5916 5917 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5918 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5919 5920 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5921 __qla83xx_get_idc_control(vha, &idc_control); 5922 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5923 __qla83xx_set_idc_control(vha, 0); 5924 5925 qla83xx_idc_unlock(vha, 0); 5926 rval = qla83xx_restart_nic_firmware(vha); 5927 qla83xx_idc_lock(vha, 0); 5928 5929 if (rval != QLA_SUCCESS) { 5930 ql_log(ql_log_fatal, vha, 0xb06a, 5931 "Failed to restart NIC f/w.\n"); 5932 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5933 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5934 } else { 5935 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5936 "Success in restarting nic f/w.\n"); 5937 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5938 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5939 } 5940 5941 return rval; 5942 } 5943 5944 /* Assumes idc_lock always held on entry */ 5945 int 5946 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5947 { 5948 struct qla_hw_data *ha = base_vha->hw; 5949 int rval = QLA_SUCCESS; 5950 unsigned long dev_init_timeout; 5951 uint32_t dev_state; 5952 5953 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5954 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5955 5956 while (1) { 5957 5958 if (time_after_eq(jiffies, dev_init_timeout)) { 5959 ql_log(ql_log_warn, base_vha, 0xb06e, 5960 "Initialization TIMEOUT!\n"); 5961 /* Init timeout. Disable further NIC Core 5962 * communication. 5963 */ 5964 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5965 QLA8XXX_DEV_FAILED); 5966 ql_log(ql_log_info, base_vha, 0xb06f, 5967 "HW State: FAILED.\n"); 5968 } 5969 5970 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5971 switch (dev_state) { 5972 case QLA8XXX_DEV_READY: 5973 if (ha->flags.nic_core_reset_owner) 5974 qla83xx_idc_audit(base_vha, 5975 IDC_AUDIT_COMPLETION); 5976 ha->flags.nic_core_reset_owner = 0; 5977 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5978 "Reset_owner reset by 0x%x.\n", 5979 ha->portnum); 5980 goto exit; 5981 case QLA8XXX_DEV_COLD: 5982 if (ha->flags.nic_core_reset_owner) 5983 rval = qla83xx_device_bootstrap(base_vha); 5984 else { 5985 /* Wait for AEN to change device-state */ 5986 qla83xx_idc_unlock(base_vha, 0); 5987 msleep(1000); 5988 qla83xx_idc_lock(base_vha, 0); 5989 } 5990 break; 5991 case QLA8XXX_DEV_INITIALIZING: 5992 /* Wait for AEN to change device-state */ 5993 qla83xx_idc_unlock(base_vha, 0); 5994 msleep(1000); 5995 qla83xx_idc_lock(base_vha, 0); 5996 break; 5997 case QLA8XXX_DEV_NEED_RESET: 5998 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5999 qla83xx_need_reset_handler(base_vha); 6000 else { 6001 /* Wait for AEN to change device-state */ 6002 qla83xx_idc_unlock(base_vha, 0); 6003 msleep(1000); 6004 qla83xx_idc_lock(base_vha, 0); 6005 } 6006 /* reset timeout value after need reset handler */ 6007 dev_init_timeout = jiffies + 6008 (ha->fcoe_dev_init_timeout * HZ); 6009 break; 6010 case QLA8XXX_DEV_NEED_QUIESCENT: 6011 /* XXX: DEBUG for now */ 6012 qla83xx_idc_unlock(base_vha, 0); 6013 msleep(1000); 6014 qla83xx_idc_lock(base_vha, 0); 6015 break; 6016 case QLA8XXX_DEV_QUIESCENT: 6017 /* XXX: DEBUG for now */ 6018 if (ha->flags.quiesce_owner) 6019 goto exit; 6020 6021 qla83xx_idc_unlock(base_vha, 0); 6022 msleep(1000); 6023 qla83xx_idc_lock(base_vha, 0); 6024 dev_init_timeout = jiffies + 6025 (ha->fcoe_dev_init_timeout * HZ); 6026 break; 6027 case QLA8XXX_DEV_FAILED: 6028 if (ha->flags.nic_core_reset_owner) 6029 qla83xx_idc_audit(base_vha, 6030 IDC_AUDIT_COMPLETION); 6031 ha->flags.nic_core_reset_owner = 0; 6032 __qla83xx_clear_drv_presence(base_vha); 6033 qla83xx_idc_unlock(base_vha, 0); 6034 qla8xxx_dev_failed_handler(base_vha); 6035 rval = QLA_FUNCTION_FAILED; 6036 qla83xx_idc_lock(base_vha, 0); 6037 goto exit; 6038 case QLA8XXX_BAD_VALUE: 6039 qla83xx_idc_unlock(base_vha, 0); 6040 msleep(1000); 6041 qla83xx_idc_lock(base_vha, 0); 6042 break; 6043 default: 6044 ql_log(ql_log_warn, base_vha, 0xb071, 6045 "Unknown Device State: %x.\n", dev_state); 6046 qla83xx_idc_unlock(base_vha, 0); 6047 qla8xxx_dev_failed_handler(base_vha); 6048 rval = QLA_FUNCTION_FAILED; 6049 qla83xx_idc_lock(base_vha, 0); 6050 goto exit; 6051 } 6052 } 6053 6054 exit: 6055 return rval; 6056 } 6057 6058 void 6059 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6060 { 6061 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6062 board_disable); 6063 struct pci_dev *pdev = ha->pdev; 6064 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6065 6066 /* 6067 * if UNLOAD flag is already set, then continue unload, 6068 * where it was set first. 6069 */ 6070 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6071 return; 6072 6073 ql_log(ql_log_warn, base_vha, 0x015b, 6074 "Disabling adapter.\n"); 6075 6076 if (!atomic_read(&pdev->enable_cnt)) { 6077 ql_log(ql_log_info, base_vha, 0xfffc, 6078 "PCI device disabled, no action req for PCI error=%lx\n", 6079 base_vha->pci_flags); 6080 return; 6081 } 6082 6083 qla2x00_wait_for_sess_deletion(base_vha); 6084 6085 set_bit(UNLOADING, &base_vha->dpc_flags); 6086 6087 qla2x00_delete_all_vps(ha, base_vha); 6088 6089 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6090 6091 qla2x00_dfs_remove(base_vha); 6092 6093 qla84xx_put_chip(base_vha); 6094 6095 if (base_vha->timer_active) 6096 qla2x00_stop_timer(base_vha); 6097 6098 base_vha->flags.online = 0; 6099 6100 qla2x00_destroy_deferred_work(ha); 6101 6102 /* 6103 * Do not try to stop beacon blink as it will issue a mailbox 6104 * command. 6105 */ 6106 qla2x00_free_sysfs_attr(base_vha, false); 6107 6108 fc_remove_host(base_vha->host); 6109 6110 scsi_remove_host(base_vha->host); 6111 6112 base_vha->flags.init_done = 0; 6113 qla25xx_delete_queues(base_vha); 6114 qla2x00_free_fcports(base_vha); 6115 qla2x00_free_irqs(base_vha); 6116 qla2x00_mem_free(ha); 6117 qla82xx_md_free(base_vha); 6118 qla2x00_free_queues(ha); 6119 6120 qla2x00_unmap_iobases(ha); 6121 6122 pci_release_selected_regions(ha->pdev, ha->bars); 6123 pci_disable_pcie_error_reporting(pdev); 6124 pci_disable_device(pdev); 6125 6126 /* 6127 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6128 */ 6129 } 6130 6131 /************************************************************************** 6132 * qla2x00_do_dpc 6133 * This kernel thread is a task that is schedule by the interrupt handler 6134 * to perform the background processing for interrupts. 6135 * 6136 * Notes: 6137 * This task always run in the context of a kernel thread. It 6138 * is kick-off by the driver's detect code and starts up 6139 * up one per adapter. It immediately goes to sleep and waits for 6140 * some fibre event. When either the interrupt handler or 6141 * the timer routine detects a event it will one of the task 6142 * bits then wake us up. 6143 **************************************************************************/ 6144 static int 6145 qla2x00_do_dpc(void *data) 6146 { 6147 scsi_qla_host_t *base_vha; 6148 struct qla_hw_data *ha; 6149 uint32_t online; 6150 struct qla_qpair *qpair; 6151 6152 ha = (struct qla_hw_data *)data; 6153 base_vha = pci_get_drvdata(ha->pdev); 6154 6155 set_user_nice(current, MIN_NICE); 6156 6157 set_current_state(TASK_INTERRUPTIBLE); 6158 while (!kthread_should_stop()) { 6159 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6160 "DPC handler sleeping.\n"); 6161 6162 schedule(); 6163 6164 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6165 goto end_loop; 6166 6167 if (ha->flags.eeh_busy) { 6168 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6169 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6170 goto end_loop; 6171 } 6172 6173 ha->dpc_active = 1; 6174 6175 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6176 "DPC handler waking up, dpc_flags=0x%lx.\n", 6177 base_vha->dpc_flags); 6178 6179 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6180 break; 6181 6182 if (IS_P3P_TYPE(ha)) { 6183 if (IS_QLA8044(ha)) { 6184 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6185 &base_vha->dpc_flags)) { 6186 qla8044_idc_lock(ha); 6187 qla8044_wr_direct(base_vha, 6188 QLA8044_CRB_DEV_STATE_INDEX, 6189 QLA8XXX_DEV_FAILED); 6190 qla8044_idc_unlock(ha); 6191 ql_log(ql_log_info, base_vha, 0x4004, 6192 "HW State: FAILED.\n"); 6193 qla8044_device_state_handler(base_vha); 6194 continue; 6195 } 6196 6197 } else { 6198 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6199 &base_vha->dpc_flags)) { 6200 qla82xx_idc_lock(ha); 6201 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6202 QLA8XXX_DEV_FAILED); 6203 qla82xx_idc_unlock(ha); 6204 ql_log(ql_log_info, base_vha, 0x0151, 6205 "HW State: FAILED.\n"); 6206 qla82xx_device_state_handler(base_vha); 6207 continue; 6208 } 6209 } 6210 6211 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6212 &base_vha->dpc_flags)) { 6213 6214 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6215 "FCoE context reset scheduled.\n"); 6216 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6217 &base_vha->dpc_flags))) { 6218 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6219 /* FCoE-ctx reset failed. 6220 * Escalate to chip-reset 6221 */ 6222 set_bit(ISP_ABORT_NEEDED, 6223 &base_vha->dpc_flags); 6224 } 6225 clear_bit(ABORT_ISP_ACTIVE, 6226 &base_vha->dpc_flags); 6227 } 6228 6229 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6230 "FCoE context reset end.\n"); 6231 } 6232 } else if (IS_QLAFX00(ha)) { 6233 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6234 &base_vha->dpc_flags)) { 6235 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6236 "Firmware Reset Recovery\n"); 6237 if (qlafx00_reset_initialize(base_vha)) { 6238 /* Failed. Abort isp later. */ 6239 if (!test_bit(UNLOADING, 6240 &base_vha->dpc_flags)) { 6241 set_bit(ISP_UNRECOVERABLE, 6242 &base_vha->dpc_flags); 6243 ql_dbg(ql_dbg_dpc, base_vha, 6244 0x4021, 6245 "Reset Recovery Failed\n"); 6246 } 6247 } 6248 } 6249 6250 if (test_and_clear_bit(FX00_TARGET_SCAN, 6251 &base_vha->dpc_flags)) { 6252 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6253 "ISPFx00 Target Scan scheduled\n"); 6254 if (qlafx00_rescan_isp(base_vha)) { 6255 if (!test_bit(UNLOADING, 6256 &base_vha->dpc_flags)) 6257 set_bit(ISP_UNRECOVERABLE, 6258 &base_vha->dpc_flags); 6259 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6260 "ISPFx00 Target Scan Failed\n"); 6261 } 6262 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6263 "ISPFx00 Target Scan End\n"); 6264 } 6265 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6266 &base_vha->dpc_flags)) { 6267 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6268 "ISPFx00 Host Info resend scheduled\n"); 6269 qlafx00_fx_disc(base_vha, 6270 &base_vha->hw->mr.fcport, 6271 FXDISC_REG_HOST_INFO); 6272 } 6273 } 6274 6275 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6276 &base_vha->dpc_flags) && 6277 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6278 qla24xx_detect_sfp(base_vha); 6279 6280 if (ha->flags.detected_lr_sfp != 6281 ha->flags.using_lr_setting) 6282 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6283 } 6284 6285 if (test_and_clear_bit 6286 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6287 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6288 bool do_reset = true; 6289 6290 switch (base_vha->qlini_mode) { 6291 case QLA2XXX_INI_MODE_ENABLED: 6292 break; 6293 case QLA2XXX_INI_MODE_DISABLED: 6294 if (!qla_tgt_mode_enabled(base_vha) && 6295 !ha->flags.fw_started) 6296 do_reset = false; 6297 break; 6298 case QLA2XXX_INI_MODE_DUAL: 6299 if (!qla_dual_mode_enabled(base_vha) && 6300 !ha->flags.fw_started) 6301 do_reset = false; 6302 break; 6303 default: 6304 break; 6305 } 6306 6307 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6308 &base_vha->dpc_flags))) { 6309 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6310 "ISP abort scheduled.\n"); 6311 if (ha->isp_ops->abort_isp(base_vha)) { 6312 /* failed. retry later */ 6313 set_bit(ISP_ABORT_NEEDED, 6314 &base_vha->dpc_flags); 6315 } 6316 clear_bit(ABORT_ISP_ACTIVE, 6317 &base_vha->dpc_flags); 6318 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6319 "ISP abort end.\n"); 6320 } 6321 } 6322 6323 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6324 &base_vha->dpc_flags)) { 6325 qla2x00_update_fcports(base_vha); 6326 } 6327 6328 if (IS_QLAFX00(ha)) 6329 goto loop_resync_check; 6330 6331 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6332 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6333 "Quiescence mode scheduled.\n"); 6334 if (IS_P3P_TYPE(ha)) { 6335 if (IS_QLA82XX(ha)) 6336 qla82xx_device_state_handler(base_vha); 6337 if (IS_QLA8044(ha)) 6338 qla8044_device_state_handler(base_vha); 6339 clear_bit(ISP_QUIESCE_NEEDED, 6340 &base_vha->dpc_flags); 6341 if (!ha->flags.quiesce_owner) { 6342 qla2x00_perform_loop_resync(base_vha); 6343 if (IS_QLA82XX(ha)) { 6344 qla82xx_idc_lock(ha); 6345 qla82xx_clear_qsnt_ready( 6346 base_vha); 6347 qla82xx_idc_unlock(ha); 6348 } else if (IS_QLA8044(ha)) { 6349 qla8044_idc_lock(ha); 6350 qla8044_clear_qsnt_ready( 6351 base_vha); 6352 qla8044_idc_unlock(ha); 6353 } 6354 } 6355 } else { 6356 clear_bit(ISP_QUIESCE_NEEDED, 6357 &base_vha->dpc_flags); 6358 qla2x00_quiesce_io(base_vha); 6359 } 6360 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6361 "Quiescence mode end.\n"); 6362 } 6363 6364 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6365 &base_vha->dpc_flags) && 6366 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6367 6368 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6369 "Reset marker scheduled.\n"); 6370 qla2x00_rst_aen(base_vha); 6371 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6372 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6373 "Reset marker end.\n"); 6374 } 6375 6376 /* Retry each device up to login retry count */ 6377 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6378 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6379 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6380 6381 if (!base_vha->relogin_jif || 6382 time_after_eq(jiffies, base_vha->relogin_jif)) { 6383 base_vha->relogin_jif = jiffies + HZ; 6384 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6385 6386 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6387 "Relogin scheduled.\n"); 6388 qla24xx_post_relogin_work(base_vha); 6389 } 6390 } 6391 loop_resync_check: 6392 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6393 &base_vha->dpc_flags)) { 6394 6395 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6396 "Loop resync scheduled.\n"); 6397 6398 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6399 &base_vha->dpc_flags))) { 6400 6401 qla2x00_loop_resync(base_vha); 6402 6403 clear_bit(LOOP_RESYNC_ACTIVE, 6404 &base_vha->dpc_flags); 6405 } 6406 6407 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6408 "Loop resync end.\n"); 6409 } 6410 6411 if (IS_QLAFX00(ha)) 6412 goto intr_on_check; 6413 6414 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6415 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6416 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6417 qla2xxx_flash_npiv_conf(base_vha); 6418 } 6419 6420 intr_on_check: 6421 if (!ha->interrupts_on) 6422 ha->isp_ops->enable_intrs(ha); 6423 6424 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6425 &base_vha->dpc_flags)) { 6426 if (ha->beacon_blink_led == 1) 6427 ha->isp_ops->beacon_blink(base_vha); 6428 } 6429 6430 /* qpair online check */ 6431 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6432 &base_vha->dpc_flags)) { 6433 if (ha->flags.eeh_busy || 6434 ha->flags.pci_channel_io_perm_failure) 6435 online = 0; 6436 else 6437 online = 1; 6438 6439 mutex_lock(&ha->mq_lock); 6440 list_for_each_entry(qpair, &base_vha->qp_list, 6441 qp_list_elem) 6442 qpair->online = online; 6443 mutex_unlock(&ha->mq_lock); 6444 } 6445 6446 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6447 &base_vha->dpc_flags)) { 6448 ql_log(ql_log_info, base_vha, 0xffffff, 6449 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6450 ha->nvme_last_rptd_aen); 6451 if (qla27xx_set_zio_threshold(base_vha, 6452 ha->nvme_last_rptd_aen)) { 6453 ql_log(ql_log_info, base_vha, 0xffffff, 6454 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6455 ha->nvme_last_rptd_aen); 6456 } 6457 } 6458 6459 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6460 &base_vha->dpc_flags)) { 6461 ql_log(ql_log_info, base_vha, 0xffffff, 6462 "SET ZIO Activity exchange threshold to %d.\n", 6463 ha->last_zio_threshold); 6464 qla27xx_set_zio_threshold(base_vha, 6465 ha->last_zio_threshold); 6466 } 6467 6468 if (!IS_QLAFX00(ha)) 6469 qla2x00_do_dpc_all_vps(base_vha); 6470 6471 if (test_and_clear_bit(N2N_LINK_RESET, 6472 &base_vha->dpc_flags)) { 6473 qla2x00_lip_reset(base_vha); 6474 } 6475 6476 ha->dpc_active = 0; 6477 end_loop: 6478 set_current_state(TASK_INTERRUPTIBLE); 6479 } /* End of while(1) */ 6480 __set_current_state(TASK_RUNNING); 6481 6482 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6483 "DPC handler exiting.\n"); 6484 6485 /* 6486 * Make sure that nobody tries to wake us up again. 6487 */ 6488 ha->dpc_active = 0; 6489 6490 /* Cleanup any residual CTX SRBs. */ 6491 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6492 6493 return 0; 6494 } 6495 6496 void 6497 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6498 { 6499 struct qla_hw_data *ha = vha->hw; 6500 struct task_struct *t = ha->dpc_thread; 6501 6502 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6503 wake_up_process(t); 6504 } 6505 6506 /* 6507 * qla2x00_rst_aen 6508 * Processes asynchronous reset. 6509 * 6510 * Input: 6511 * ha = adapter block pointer. 6512 */ 6513 static void 6514 qla2x00_rst_aen(scsi_qla_host_t *vha) 6515 { 6516 if (vha->flags.online && !vha->flags.reset_active && 6517 !atomic_read(&vha->loop_down_timer) && 6518 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6519 do { 6520 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6521 6522 /* 6523 * Issue marker command only when we are going to start 6524 * the I/O. 6525 */ 6526 vha->marker_needed = 1; 6527 } while (!atomic_read(&vha->loop_down_timer) && 6528 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6529 } 6530 } 6531 6532 /************************************************************************** 6533 * qla2x00_timer 6534 * 6535 * Description: 6536 * One second timer 6537 * 6538 * Context: Interrupt 6539 ***************************************************************************/ 6540 void 6541 qla2x00_timer(struct timer_list *t) 6542 { 6543 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6544 unsigned long cpu_flags = 0; 6545 int start_dpc = 0; 6546 int index; 6547 srb_t *sp; 6548 uint16_t w; 6549 struct qla_hw_data *ha = vha->hw; 6550 struct req_que *req; 6551 6552 if (ha->flags.eeh_busy) { 6553 ql_dbg(ql_dbg_timer, vha, 0x6000, 6554 "EEH = %d, restarting timer.\n", 6555 ha->flags.eeh_busy); 6556 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6557 return; 6558 } 6559 6560 /* 6561 * Hardware read to raise pending EEH errors during mailbox waits. If 6562 * the read returns -1 then disable the board. 6563 */ 6564 if (!pci_channel_offline(ha->pdev)) { 6565 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6566 qla2x00_check_reg16_for_disconnect(vha, w); 6567 } 6568 6569 /* Make sure qla82xx_watchdog is run only for physical port */ 6570 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6571 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6572 start_dpc++; 6573 if (IS_QLA82XX(ha)) 6574 qla82xx_watchdog(vha); 6575 else if (IS_QLA8044(ha)) 6576 qla8044_watchdog(vha); 6577 } 6578 6579 if (!vha->vp_idx && IS_QLAFX00(ha)) 6580 qlafx00_timer_routine(vha); 6581 6582 /* Loop down handler. */ 6583 if (atomic_read(&vha->loop_down_timer) > 0 && 6584 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6585 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6586 && vha->flags.online) { 6587 6588 if (atomic_read(&vha->loop_down_timer) == 6589 vha->loop_down_abort_time) { 6590 6591 ql_log(ql_log_info, vha, 0x6008, 6592 "Loop down - aborting the queues before time expires.\n"); 6593 6594 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6595 atomic_set(&vha->loop_state, LOOP_DEAD); 6596 6597 /* 6598 * Schedule an ISP abort to return any FCP2-device 6599 * commands. 6600 */ 6601 /* NPIV - scan physical port only */ 6602 if (!vha->vp_idx) { 6603 spin_lock_irqsave(&ha->hardware_lock, 6604 cpu_flags); 6605 req = ha->req_q_map[0]; 6606 for (index = 1; 6607 index < req->num_outstanding_cmds; 6608 index++) { 6609 fc_port_t *sfcp; 6610 6611 sp = req->outstanding_cmds[index]; 6612 if (!sp) 6613 continue; 6614 if (sp->cmd_type != TYPE_SRB) 6615 continue; 6616 if (sp->type != SRB_SCSI_CMD) 6617 continue; 6618 sfcp = sp->fcport; 6619 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6620 continue; 6621 6622 if (IS_QLA82XX(ha)) 6623 set_bit(FCOE_CTX_RESET_NEEDED, 6624 &vha->dpc_flags); 6625 else 6626 set_bit(ISP_ABORT_NEEDED, 6627 &vha->dpc_flags); 6628 break; 6629 } 6630 spin_unlock_irqrestore(&ha->hardware_lock, 6631 cpu_flags); 6632 } 6633 start_dpc++; 6634 } 6635 6636 /* if the loop has been down for 4 minutes, reinit adapter */ 6637 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6638 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6639 ql_log(ql_log_warn, vha, 0x6009, 6640 "Loop down - aborting ISP.\n"); 6641 6642 if (IS_QLA82XX(ha)) 6643 set_bit(FCOE_CTX_RESET_NEEDED, 6644 &vha->dpc_flags); 6645 else 6646 set_bit(ISP_ABORT_NEEDED, 6647 &vha->dpc_flags); 6648 } 6649 } 6650 ql_dbg(ql_dbg_timer, vha, 0x600a, 6651 "Loop down - seconds remaining %d.\n", 6652 atomic_read(&vha->loop_down_timer)); 6653 } 6654 /* Check if beacon LED needs to be blinked for physical host only */ 6655 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6656 /* There is no beacon_blink function for ISP82xx */ 6657 if (!IS_P3P_TYPE(ha)) { 6658 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6659 start_dpc++; 6660 } 6661 } 6662 6663 /* Process any deferred work. */ 6664 if (!list_empty(&vha->work_list)) { 6665 unsigned long flags; 6666 bool q = false; 6667 6668 spin_lock_irqsave(&vha->work_lock, flags); 6669 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6670 q = true; 6671 spin_unlock_irqrestore(&vha->work_lock, flags); 6672 if (q) 6673 queue_work(vha->hw->wq, &vha->iocb_work); 6674 } 6675 6676 /* 6677 * FC-NVME 6678 * see if the active AEN count has changed from what was last reported. 6679 */ 6680 if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) != 6681 ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) { 6682 ql_log(ql_log_info, vha, 0x3002, 6683 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6684 ha->nvme_last_rptd_aen); 6685 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6686 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6687 start_dpc++; 6688 } 6689 6690 if (!vha->vp_idx && 6691 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 6692 (ha->zio_mode == QLA_ZIO_MODE_6) && 6693 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) { 6694 ql_log(ql_log_info, vha, 0x3002, 6695 "Sched: Set ZIO exchange threshold to %d.\n", 6696 ha->last_zio_threshold); 6697 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 6698 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6699 start_dpc++; 6700 } 6701 6702 /* Schedule the DPC routine if needed */ 6703 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6704 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6705 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6706 start_dpc || 6707 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6708 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6709 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6710 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6711 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6712 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6713 ql_dbg(ql_dbg_timer, vha, 0x600b, 6714 "isp_abort_needed=%d loop_resync_needed=%d " 6715 "fcport_update_needed=%d start_dpc=%d " 6716 "reset_marker_needed=%d", 6717 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6718 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6719 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6720 start_dpc, 6721 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6722 ql_dbg(ql_dbg_timer, vha, 0x600c, 6723 "beacon_blink_needed=%d isp_unrecoverable=%d " 6724 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6725 "relogin_needed=%d.\n", 6726 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6727 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6728 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6729 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6730 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6731 qla2xxx_wake_dpc(vha); 6732 } 6733 6734 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6735 } 6736 6737 /* Firmware interface routines. */ 6738 6739 #define FW_BLOBS 11 6740 #define FW_ISP21XX 0 6741 #define FW_ISP22XX 1 6742 #define FW_ISP2300 2 6743 #define FW_ISP2322 3 6744 #define FW_ISP24XX 4 6745 #define FW_ISP25XX 5 6746 #define FW_ISP81XX 6 6747 #define FW_ISP82XX 7 6748 #define FW_ISP2031 8 6749 #define FW_ISP8031 9 6750 #define FW_ISP27XX 10 6751 6752 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6753 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6754 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6755 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6756 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6757 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6758 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6759 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6760 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6761 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6762 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6763 6764 6765 static DEFINE_MUTEX(qla_fw_lock); 6766 6767 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6768 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6769 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6770 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6771 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6772 { .name = FW_FILE_ISP24XX, }, 6773 { .name = FW_FILE_ISP25XX, }, 6774 { .name = FW_FILE_ISP81XX, }, 6775 { .name = FW_FILE_ISP82XX, }, 6776 { .name = FW_FILE_ISP2031, }, 6777 { .name = FW_FILE_ISP8031, }, 6778 { .name = FW_FILE_ISP27XX, }, 6779 }; 6780 6781 struct fw_blob * 6782 qla2x00_request_firmware(scsi_qla_host_t *vha) 6783 { 6784 struct qla_hw_data *ha = vha->hw; 6785 struct fw_blob *blob; 6786 6787 if (IS_QLA2100(ha)) { 6788 blob = &qla_fw_blobs[FW_ISP21XX]; 6789 } else if (IS_QLA2200(ha)) { 6790 blob = &qla_fw_blobs[FW_ISP22XX]; 6791 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6792 blob = &qla_fw_blobs[FW_ISP2300]; 6793 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6794 blob = &qla_fw_blobs[FW_ISP2322]; 6795 } else if (IS_QLA24XX_TYPE(ha)) { 6796 blob = &qla_fw_blobs[FW_ISP24XX]; 6797 } else if (IS_QLA25XX(ha)) { 6798 blob = &qla_fw_blobs[FW_ISP25XX]; 6799 } else if (IS_QLA81XX(ha)) { 6800 blob = &qla_fw_blobs[FW_ISP81XX]; 6801 } else if (IS_QLA82XX(ha)) { 6802 blob = &qla_fw_blobs[FW_ISP82XX]; 6803 } else if (IS_QLA2031(ha)) { 6804 blob = &qla_fw_blobs[FW_ISP2031]; 6805 } else if (IS_QLA8031(ha)) { 6806 blob = &qla_fw_blobs[FW_ISP8031]; 6807 } else if (IS_QLA27XX(ha)) { 6808 blob = &qla_fw_blobs[FW_ISP27XX]; 6809 } else { 6810 return NULL; 6811 } 6812 6813 mutex_lock(&qla_fw_lock); 6814 if (blob->fw) 6815 goto out; 6816 6817 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6818 ql_log(ql_log_warn, vha, 0x0063, 6819 "Failed to load firmware image (%s).\n", blob->name); 6820 blob->fw = NULL; 6821 blob = NULL; 6822 goto out; 6823 } 6824 6825 out: 6826 mutex_unlock(&qla_fw_lock); 6827 return blob; 6828 } 6829 6830 static void 6831 qla2x00_release_firmware(void) 6832 { 6833 int idx; 6834 6835 mutex_lock(&qla_fw_lock); 6836 for (idx = 0; idx < FW_BLOBS; idx++) 6837 release_firmware(qla_fw_blobs[idx].fw); 6838 mutex_unlock(&qla_fw_lock); 6839 } 6840 6841 static pci_ers_result_t 6842 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6843 { 6844 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6845 struct qla_hw_data *ha = vha->hw; 6846 6847 ql_dbg(ql_dbg_aer, vha, 0x9000, 6848 "PCI error detected, state %x.\n", state); 6849 6850 if (!atomic_read(&pdev->enable_cnt)) { 6851 ql_log(ql_log_info, vha, 0xffff, 6852 "PCI device is disabled,state %x\n", state); 6853 return PCI_ERS_RESULT_NEED_RESET; 6854 } 6855 6856 switch (state) { 6857 case pci_channel_io_normal: 6858 ha->flags.eeh_busy = 0; 6859 if (ql2xmqsupport || ql2xnvmeenable) { 6860 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6861 qla2xxx_wake_dpc(vha); 6862 } 6863 return PCI_ERS_RESULT_CAN_RECOVER; 6864 case pci_channel_io_frozen: 6865 ha->flags.eeh_busy = 1; 6866 /* For ISP82XX complete any pending mailbox cmd */ 6867 if (IS_QLA82XX(ha)) { 6868 ha->flags.isp82xx_fw_hung = 1; 6869 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6870 qla82xx_clear_pending_mbx(vha); 6871 } 6872 qla2x00_free_irqs(vha); 6873 pci_disable_device(pdev); 6874 /* Return back all IOs */ 6875 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6876 if (ql2xmqsupport || ql2xnvmeenable) { 6877 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6878 qla2xxx_wake_dpc(vha); 6879 } 6880 return PCI_ERS_RESULT_NEED_RESET; 6881 case pci_channel_io_perm_failure: 6882 ha->flags.pci_channel_io_perm_failure = 1; 6883 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6884 if (ql2xmqsupport || ql2xnvmeenable) { 6885 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6886 qla2xxx_wake_dpc(vha); 6887 } 6888 return PCI_ERS_RESULT_DISCONNECT; 6889 } 6890 return PCI_ERS_RESULT_NEED_RESET; 6891 } 6892 6893 static pci_ers_result_t 6894 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6895 { 6896 int risc_paused = 0; 6897 uint32_t stat; 6898 unsigned long flags; 6899 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6900 struct qla_hw_data *ha = base_vha->hw; 6901 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6902 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6903 6904 if (IS_QLA82XX(ha)) 6905 return PCI_ERS_RESULT_RECOVERED; 6906 6907 spin_lock_irqsave(&ha->hardware_lock, flags); 6908 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6909 stat = RD_REG_DWORD(®->hccr); 6910 if (stat & HCCR_RISC_PAUSE) 6911 risc_paused = 1; 6912 } else if (IS_QLA23XX(ha)) { 6913 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6914 if (stat & HSR_RISC_PAUSED) 6915 risc_paused = 1; 6916 } else if (IS_FWI2_CAPABLE(ha)) { 6917 stat = RD_REG_DWORD(®24->host_status); 6918 if (stat & HSRX_RISC_PAUSED) 6919 risc_paused = 1; 6920 } 6921 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6922 6923 if (risc_paused) { 6924 ql_log(ql_log_info, base_vha, 0x9003, 6925 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6926 ha->isp_ops->fw_dump(base_vha, 0); 6927 6928 return PCI_ERS_RESULT_NEED_RESET; 6929 } else 6930 return PCI_ERS_RESULT_RECOVERED; 6931 } 6932 6933 static uint32_t 6934 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6935 { 6936 uint32_t rval = QLA_FUNCTION_FAILED; 6937 uint32_t drv_active = 0; 6938 struct qla_hw_data *ha = base_vha->hw; 6939 int fn; 6940 struct pci_dev *other_pdev = NULL; 6941 6942 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6943 "Entered %s.\n", __func__); 6944 6945 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6946 6947 if (base_vha->flags.online) { 6948 /* Abort all outstanding commands, 6949 * so as to be requeued later */ 6950 qla2x00_abort_isp_cleanup(base_vha); 6951 } 6952 6953 6954 fn = PCI_FUNC(ha->pdev->devfn); 6955 while (fn > 0) { 6956 fn--; 6957 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6958 "Finding pci device at function = 0x%x.\n", fn); 6959 other_pdev = 6960 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6961 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6962 fn)); 6963 6964 if (!other_pdev) 6965 continue; 6966 if (atomic_read(&other_pdev->enable_cnt)) { 6967 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6968 "Found PCI func available and enable at 0x%x.\n", 6969 fn); 6970 pci_dev_put(other_pdev); 6971 break; 6972 } 6973 pci_dev_put(other_pdev); 6974 } 6975 6976 if (!fn) { 6977 /* Reset owner */ 6978 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6979 "This devfn is reset owner = 0x%x.\n", 6980 ha->pdev->devfn); 6981 qla82xx_idc_lock(ha); 6982 6983 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6984 QLA8XXX_DEV_INITIALIZING); 6985 6986 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6987 QLA82XX_IDC_VERSION); 6988 6989 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6990 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6991 "drv_active = 0x%x.\n", drv_active); 6992 6993 qla82xx_idc_unlock(ha); 6994 /* Reset if device is not already reset 6995 * drv_active would be 0 if a reset has already been done 6996 */ 6997 if (drv_active) 6998 rval = qla82xx_start_firmware(base_vha); 6999 else 7000 rval = QLA_SUCCESS; 7001 qla82xx_idc_lock(ha); 7002 7003 if (rval != QLA_SUCCESS) { 7004 ql_log(ql_log_info, base_vha, 0x900b, 7005 "HW State: FAILED.\n"); 7006 qla82xx_clear_drv_active(ha); 7007 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 7008 QLA8XXX_DEV_FAILED); 7009 } else { 7010 ql_log(ql_log_info, base_vha, 0x900c, 7011 "HW State: READY.\n"); 7012 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 7013 QLA8XXX_DEV_READY); 7014 qla82xx_idc_unlock(ha); 7015 ha->flags.isp82xx_fw_hung = 0; 7016 rval = qla82xx_restart_isp(base_vha); 7017 qla82xx_idc_lock(ha); 7018 /* Clear driver state register */ 7019 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 7020 qla82xx_set_drv_active(base_vha); 7021 } 7022 qla82xx_idc_unlock(ha); 7023 } else { 7024 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 7025 "This devfn is not reset owner = 0x%x.\n", 7026 ha->pdev->devfn); 7027 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 7028 QLA8XXX_DEV_READY)) { 7029 ha->flags.isp82xx_fw_hung = 0; 7030 rval = qla82xx_restart_isp(base_vha); 7031 qla82xx_idc_lock(ha); 7032 qla82xx_set_drv_active(base_vha); 7033 qla82xx_idc_unlock(ha); 7034 } 7035 } 7036 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7037 7038 return rval; 7039 } 7040 7041 static pci_ers_result_t 7042 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7043 { 7044 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7045 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7046 struct qla_hw_data *ha = base_vha->hw; 7047 struct rsp_que *rsp; 7048 int rc, retries = 10; 7049 7050 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 7051 "Slot Reset.\n"); 7052 7053 /* Workaround: qla2xxx driver which access hardware earlier 7054 * needs error state to be pci_channel_io_online. 7055 * Otherwise mailbox command timesout. 7056 */ 7057 pdev->error_state = pci_channel_io_normal; 7058 7059 pci_restore_state(pdev); 7060 7061 /* pci_restore_state() clears the saved_state flag of the device 7062 * save restored state which resets saved_state flag 7063 */ 7064 pci_save_state(pdev); 7065 7066 if (ha->mem_only) 7067 rc = pci_enable_device_mem(pdev); 7068 else 7069 rc = pci_enable_device(pdev); 7070 7071 if (rc) { 7072 ql_log(ql_log_warn, base_vha, 0x9005, 7073 "Can't re-enable PCI device after reset.\n"); 7074 goto exit_slot_reset; 7075 } 7076 7077 rsp = ha->rsp_q_map[0]; 7078 if (qla2x00_request_irqs(ha, rsp)) 7079 goto exit_slot_reset; 7080 7081 if (ha->isp_ops->pci_config(base_vha)) 7082 goto exit_slot_reset; 7083 7084 if (IS_QLA82XX(ha)) { 7085 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 7086 ret = PCI_ERS_RESULT_RECOVERED; 7087 goto exit_slot_reset; 7088 } else 7089 goto exit_slot_reset; 7090 } 7091 7092 while (ha->flags.mbox_busy && retries--) 7093 msleep(1000); 7094 7095 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7096 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7097 ret = PCI_ERS_RESULT_RECOVERED; 7098 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7099 7100 7101 exit_slot_reset: 7102 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7103 "slot_reset return %x.\n", ret); 7104 7105 return ret; 7106 } 7107 7108 static void 7109 qla2xxx_pci_resume(struct pci_dev *pdev) 7110 { 7111 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7112 struct qla_hw_data *ha = base_vha->hw; 7113 int ret; 7114 7115 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7116 "pci_resume.\n"); 7117 7118 ret = qla2x00_wait_for_hba_online(base_vha); 7119 if (ret != QLA_SUCCESS) { 7120 ql_log(ql_log_fatal, base_vha, 0x9002, 7121 "The device failed to resume I/O from slot/link_reset.\n"); 7122 } 7123 7124 ha->flags.eeh_busy = 0; 7125 } 7126 7127 static void 7128 qla_pci_reset_prepare(struct pci_dev *pdev) 7129 { 7130 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7131 struct qla_hw_data *ha = base_vha->hw; 7132 struct qla_qpair *qpair; 7133 7134 ql_log(ql_log_warn, base_vha, 0xffff, 7135 "%s.\n", __func__); 7136 7137 /* 7138 * PCI FLR/function reset is about to reset the 7139 * slot. Stop the chip to stop all DMA access. 7140 * It is assumed that pci_reset_done will be called 7141 * after FLR to resume Chip operation. 7142 */ 7143 ha->flags.eeh_busy = 1; 7144 mutex_lock(&ha->mq_lock); 7145 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7146 qpair->online = 0; 7147 mutex_unlock(&ha->mq_lock); 7148 7149 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7150 qla2x00_abort_isp_cleanup(base_vha); 7151 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7152 } 7153 7154 static void 7155 qla_pci_reset_done(struct pci_dev *pdev) 7156 { 7157 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7158 struct qla_hw_data *ha = base_vha->hw; 7159 struct qla_qpair *qpair; 7160 7161 ql_log(ql_log_warn, base_vha, 0xffff, 7162 "%s.\n", __func__); 7163 7164 /* 7165 * FLR just completed by PCI layer. Resume adapter 7166 */ 7167 ha->flags.eeh_busy = 0; 7168 mutex_lock(&ha->mq_lock); 7169 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7170 qpair->online = 1; 7171 mutex_unlock(&ha->mq_lock); 7172 7173 base_vha->flags.online = 1; 7174 ha->isp_ops->abort_isp(base_vha); 7175 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7176 } 7177 7178 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7179 { 7180 int rc; 7181 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7182 struct blk_mq_queue_map *qmap = &shost->tag_set.map[0]; 7183 7184 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7185 rc = blk_mq_map_queues(qmap); 7186 else 7187 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7188 return rc; 7189 } 7190 7191 static const struct pci_error_handlers qla2xxx_err_handler = { 7192 .error_detected = qla2xxx_pci_error_detected, 7193 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7194 .slot_reset = qla2xxx_pci_slot_reset, 7195 .resume = qla2xxx_pci_resume, 7196 .reset_prepare = qla_pci_reset_prepare, 7197 .reset_done = qla_pci_reset_done, 7198 }; 7199 7200 static struct pci_device_id qla2xxx_pci_tbl[] = { 7201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7217 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7218 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7219 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7220 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7221 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7222 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7223 { 0 }, 7224 }; 7225 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7226 7227 static struct pci_driver qla2xxx_pci_driver = { 7228 .name = QLA2XXX_DRIVER_NAME, 7229 .driver = { 7230 .owner = THIS_MODULE, 7231 }, 7232 .id_table = qla2xxx_pci_tbl, 7233 .probe = qla2x00_probe_one, 7234 .remove = qla2x00_remove_one, 7235 .shutdown = qla2x00_shutdown, 7236 .err_handler = &qla2xxx_err_handler, 7237 }; 7238 7239 static const struct file_operations apidev_fops = { 7240 .owner = THIS_MODULE, 7241 .llseek = noop_llseek, 7242 }; 7243 7244 /** 7245 * qla2x00_module_init - Module initialization. 7246 **/ 7247 static int __init 7248 qla2x00_module_init(void) 7249 { 7250 int ret = 0; 7251 7252 /* Allocate cache for SRBs. */ 7253 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7254 SLAB_HWCACHE_ALIGN, NULL); 7255 if (srb_cachep == NULL) { 7256 ql_log(ql_log_fatal, NULL, 0x0001, 7257 "Unable to allocate SRB cache...Failing load!.\n"); 7258 return -ENOMEM; 7259 } 7260 7261 /* Initialize target kmem_cache and mem_pools */ 7262 ret = qlt_init(); 7263 if (ret < 0) { 7264 kmem_cache_destroy(srb_cachep); 7265 return ret; 7266 } else if (ret > 0) { 7267 /* 7268 * If initiator mode is explictly disabled by qlt_init(), 7269 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7270 * performing scsi_scan_target() during LOOP UP event. 7271 */ 7272 qla2xxx_transport_functions.disable_target_scan = 1; 7273 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7274 } 7275 7276 /* Derive version string. */ 7277 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7278 if (ql2xextended_error_logging) 7279 strcat(qla2x00_version_str, "-debug"); 7280 if (ql2xextended_error_logging == 1) 7281 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7282 7283 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7284 qla_insert_tgt_attrs(); 7285 7286 qla2xxx_transport_template = 7287 fc_attach_transport(&qla2xxx_transport_functions); 7288 if (!qla2xxx_transport_template) { 7289 kmem_cache_destroy(srb_cachep); 7290 ql_log(ql_log_fatal, NULL, 0x0002, 7291 "fc_attach_transport failed...Failing load!.\n"); 7292 qlt_exit(); 7293 return -ENODEV; 7294 } 7295 7296 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7297 if (apidev_major < 0) { 7298 ql_log(ql_log_fatal, NULL, 0x0003, 7299 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7300 } 7301 7302 qla2xxx_transport_vport_template = 7303 fc_attach_transport(&qla2xxx_transport_vport_functions); 7304 if (!qla2xxx_transport_vport_template) { 7305 kmem_cache_destroy(srb_cachep); 7306 qlt_exit(); 7307 fc_release_transport(qla2xxx_transport_template); 7308 ql_log(ql_log_fatal, NULL, 0x0004, 7309 "fc_attach_transport vport failed...Failing load!.\n"); 7310 return -ENODEV; 7311 } 7312 ql_log(ql_log_info, NULL, 0x0005, 7313 "QLogic Fibre Channel HBA Driver: %s.\n", 7314 qla2x00_version_str); 7315 ret = pci_register_driver(&qla2xxx_pci_driver); 7316 if (ret) { 7317 kmem_cache_destroy(srb_cachep); 7318 qlt_exit(); 7319 fc_release_transport(qla2xxx_transport_template); 7320 fc_release_transport(qla2xxx_transport_vport_template); 7321 ql_log(ql_log_fatal, NULL, 0x0006, 7322 "pci_register_driver failed...ret=%d Failing load!.\n", 7323 ret); 7324 } 7325 return ret; 7326 } 7327 7328 /** 7329 * qla2x00_module_exit - Module cleanup. 7330 **/ 7331 static void __exit 7332 qla2x00_module_exit(void) 7333 { 7334 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7335 pci_unregister_driver(&qla2xxx_pci_driver); 7336 qla2x00_release_firmware(); 7337 kmem_cache_destroy(srb_cachep); 7338 qlt_exit(); 7339 kmem_cache_destroy(ctx_cachep); 7340 fc_release_transport(qla2xxx_transport_template); 7341 fc_release_transport(qla2xxx_transport_vport_template); 7342 } 7343 7344 module_init(qla2x00_module_init); 7345 module_exit(qla2x00_module_exit); 7346 7347 MODULE_AUTHOR("QLogic Corporation"); 7348 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7349 MODULE_LICENSE("GPL"); 7350 MODULE_VERSION(QLA2XXX_VERSION); 7351 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7352 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7353 MODULE_FIRMWARE(FW_FILE_ISP2300); 7354 MODULE_FIRMWARE(FW_FILE_ISP2322); 7355 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7356 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7357