1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 MODULE_PARM_DESC(ql2xextended_error_logging, 85 "Option to enable extended error logging,\n" 86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 97 "\t\t0x1e400000 - Preferred value for capturing essential " 98 "debug information (equivalent to old " 99 "ql2xextended_error_logging=1).\n" 100 "\t\tDo LOGICAL OR of the value to enable more than one level"); 101 102 int ql2xshiftctondsd = 6; 103 module_param(ql2xshiftctondsd, int, S_IRUGO); 104 MODULE_PARM_DESC(ql2xshiftctondsd, 105 "Set to control shifting of command type processing " 106 "based on total number of SG elements."); 107 108 int ql2xfdmienable=1; 109 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 110 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 MODULE_PARM_DESC(ql2xfdmienable, 112 "Enables FDMI registrations. " 113 "0 - no FDMI. Default is 1 - perform FDMI."); 114 115 #define MAX_Q_DEPTH 32 116 static int ql2xmaxqdepth = MAX_Q_DEPTH; 117 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 118 MODULE_PARM_DESC(ql2xmaxqdepth, 119 "Maximum queue depth to set for each LUN. " 120 "Default is 32."); 121 122 int ql2xenabledif = 2; 123 module_param(ql2xenabledif, int, S_IRUGO); 124 MODULE_PARM_DESC(ql2xenabledif, 125 " Enable T10-CRC-DIF:\n" 126 " Default is 2.\n" 127 " 0 -- No DIF Support\n" 128 " 1 -- Enable DIF for all types\n" 129 " 2 -- Enable DIF for all types, except Type 0.\n"); 130 131 int ql2xenablehba_err_chk = 2; 132 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 133 MODULE_PARM_DESC(ql2xenablehba_err_chk, 134 " Enable T10-CRC-DIF Error isolation by HBA:\n" 135 " Default is 2.\n" 136 " 0 -- Error isolation disabled\n" 137 " 1 -- Error isolation enabled only for DIX Type 0\n" 138 " 2 -- Error isolation enabled for all Types\n"); 139 140 int ql2xiidmaenable=1; 141 module_param(ql2xiidmaenable, int, S_IRUGO); 142 MODULE_PARM_DESC(ql2xiidmaenable, 143 "Enables iIDMA settings " 144 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 145 146 int ql2xmaxqueues = 1; 147 module_param(ql2xmaxqueues, int, S_IRUGO); 148 MODULE_PARM_DESC(ql2xmaxqueues, 149 "Enables MQ settings " 150 "Default is 1 for single queue. Set it to number " 151 "of queues in MQ mode."); 152 153 int ql2xmultique_tag; 154 module_param(ql2xmultique_tag, int, S_IRUGO); 155 MODULE_PARM_DESC(ql2xmultique_tag, 156 "Enables CPU affinity settings for the driver " 157 "Default is 0 for no affinity of request and response IO. " 158 "Set it to 1 to turn on the cpu affinity."); 159 160 int ql2xfwloadbin; 161 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 162 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 163 MODULE_PARM_DESC(ql2xfwloadbin, 164 "Option to specify location from which to load ISP firmware:.\n" 165 " 2 -- load firmware via the request_firmware() (hotplug).\n" 166 " interface.\n" 167 " 1 -- load firmware from flash.\n" 168 " 0 -- use default semantics.\n"); 169 170 int ql2xetsenable; 171 module_param(ql2xetsenable, int, S_IRUGO); 172 MODULE_PARM_DESC(ql2xetsenable, 173 "Enables firmware ETS burst." 174 "Default is 0 - skip ETS enablement."); 175 176 int ql2xdbwr = 1; 177 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 178 MODULE_PARM_DESC(ql2xdbwr, 179 "Option to specify scheme for request queue posting.\n" 180 " 0 -- Regular doorbell.\n" 181 " 1 -- CAMRAM doorbell (faster).\n"); 182 183 int ql2xtargetreset = 1; 184 module_param(ql2xtargetreset, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xtargetreset, 186 "Enable target reset." 187 "Default is 1 - use hw defaults."); 188 189 int ql2xgffidenable; 190 module_param(ql2xgffidenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xgffidenable, 192 "Enables GFF_ID checks of port type. " 193 "Default is 0 - Do not use GFF_ID information."); 194 195 int ql2xasynctmfenable; 196 module_param(ql2xasynctmfenable, int, S_IRUGO); 197 MODULE_PARM_DESC(ql2xasynctmfenable, 198 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 199 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 200 201 int ql2xdontresethba; 202 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 203 MODULE_PARM_DESC(ql2xdontresethba, 204 "Option to specify reset behaviour.\n" 205 " 0 (Default) -- Reset on failure.\n" 206 " 1 -- Do not reset on failure.\n"); 207 208 uint64_t ql2xmaxlun = MAX_LUNS; 209 module_param(ql2xmaxlun, ullong, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmaxlun, 211 "Defines the maximum LU number to register with the SCSI " 212 "midlayer. Default is 65535."); 213 214 int ql2xmdcapmask = 0x1F; 215 module_param(ql2xmdcapmask, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdcapmask, 217 "Set the Minidump driver capture mask level. " 218 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 219 220 int ql2xmdenable = 1; 221 module_param(ql2xmdenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xmdenable, 223 "Enable/disable MiniDump. " 224 "0 - MiniDump disabled. " 225 "1 (Default) - MiniDump enabled."); 226 227 int ql2xexlogins = 0; 228 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xexlogins, 230 "Number of extended Logins. " 231 "0 (Default)- Disabled."); 232 233 int ql2xexchoffld = 0; 234 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 235 MODULE_PARM_DESC(ql2xexchoffld, 236 "Number of exchanges to offload. " 237 "0 (Default)- Disabled."); 238 239 int ql2xfwholdabts = 0; 240 module_param(ql2xfwholdabts, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xfwholdabts, 242 "Allow FW to hold status IOCB until ABTS rsp received. " 243 "0 (Default) Do not set fw option. " 244 "1 - Set fw option to hold ABTS."); 245 246 /* 247 * SCSI host template entry points 248 */ 249 static int qla2xxx_slave_configure(struct scsi_device * device); 250 static int qla2xxx_slave_alloc(struct scsi_device *); 251 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 252 static void qla2xxx_scan_start(struct Scsi_Host *); 253 static void qla2xxx_slave_destroy(struct scsi_device *); 254 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 255 static int qla2xxx_eh_abort(struct scsi_cmnd *); 256 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 257 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 258 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 259 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 260 261 static void qla2x00_clear_drv_active(struct qla_hw_data *); 262 static void qla2x00_free_device(scsi_qla_host_t *); 263 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 264 265 struct scsi_host_template qla2xxx_driver_template = { 266 .module = THIS_MODULE, 267 .name = QLA2XXX_DRIVER_NAME, 268 .queuecommand = qla2xxx_queuecommand, 269 270 .eh_abort_handler = qla2xxx_eh_abort, 271 .eh_device_reset_handler = qla2xxx_eh_device_reset, 272 .eh_target_reset_handler = qla2xxx_eh_target_reset, 273 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 274 .eh_host_reset_handler = qla2xxx_eh_host_reset, 275 276 .slave_configure = qla2xxx_slave_configure, 277 278 .slave_alloc = qla2xxx_slave_alloc, 279 .slave_destroy = qla2xxx_slave_destroy, 280 .scan_finished = qla2xxx_scan_finished, 281 .scan_start = qla2xxx_scan_start, 282 .change_queue_depth = scsi_change_queue_depth, 283 .this_id = -1, 284 .cmd_per_lun = 3, 285 .use_clustering = ENABLE_CLUSTERING, 286 .sg_tablesize = SG_ALL, 287 288 .max_sectors = 0xFFFF, 289 .shost_attrs = qla2x00_host_attrs, 290 291 .supported_mode = MODE_INITIATOR, 292 .track_queue_depth = 1, 293 }; 294 295 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 296 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 297 298 /* TODO Convert to inlines 299 * 300 * Timer routines 301 */ 302 303 __inline__ void 304 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 305 { 306 init_timer(&vha->timer); 307 vha->timer.expires = jiffies + interval * HZ; 308 vha->timer.data = (unsigned long)vha; 309 vha->timer.function = (void (*)(unsigned long))func; 310 add_timer(&vha->timer); 311 vha->timer_active = 1; 312 } 313 314 static inline void 315 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 316 { 317 /* Currently used for 82XX only. */ 318 if (vha->device_flags & DFLG_DEV_FAILED) { 319 ql_dbg(ql_dbg_timer, vha, 0x600d, 320 "Device in a failed state, returning.\n"); 321 return; 322 } 323 324 mod_timer(&vha->timer, jiffies + interval * HZ); 325 } 326 327 static __inline__ void 328 qla2x00_stop_timer(scsi_qla_host_t *vha) 329 { 330 del_timer_sync(&vha->timer); 331 vha->timer_active = 0; 332 } 333 334 static int qla2x00_do_dpc(void *data); 335 336 static void qla2x00_rst_aen(scsi_qla_host_t *); 337 338 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 339 struct req_que **, struct rsp_que **); 340 static void qla2x00_free_fw_dump(struct qla_hw_data *); 341 static void qla2x00_mem_free(struct qla_hw_data *); 342 343 /* -------------------------------------------------------------------------- */ 344 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 345 struct rsp_que *rsp) 346 { 347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 348 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 349 GFP_KERNEL); 350 if (!ha->req_q_map) { 351 ql_log(ql_log_fatal, vha, 0x003b, 352 "Unable to allocate memory for request queue ptrs.\n"); 353 goto fail_req_map; 354 } 355 356 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 357 GFP_KERNEL); 358 if (!ha->rsp_q_map) { 359 ql_log(ql_log_fatal, vha, 0x003c, 360 "Unable to allocate memory for response queue ptrs.\n"); 361 goto fail_rsp_map; 362 } 363 /* 364 * Make sure we record at least the request and response queue zero in 365 * case we need to free them if part of the probe fails. 366 */ 367 ha->rsp_q_map[0] = rsp; 368 ha->req_q_map[0] = req; 369 set_bit(0, ha->rsp_qid_map); 370 set_bit(0, ha->req_qid_map); 371 return 1; 372 373 fail_rsp_map: 374 kfree(ha->req_q_map); 375 ha->req_q_map = NULL; 376 fail_req_map: 377 return -ENOMEM; 378 } 379 380 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 381 { 382 if (IS_QLAFX00(ha)) { 383 if (req && req->ring_fx00) 384 dma_free_coherent(&ha->pdev->dev, 385 (req->length_fx00 + 1) * sizeof(request_t), 386 req->ring_fx00, req->dma_fx00); 387 } else if (req && req->ring) 388 dma_free_coherent(&ha->pdev->dev, 389 (req->length + 1) * sizeof(request_t), 390 req->ring, req->dma); 391 392 if (req) 393 kfree(req->outstanding_cmds); 394 395 kfree(req); 396 req = NULL; 397 } 398 399 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 400 { 401 if (IS_QLAFX00(ha)) { 402 if (rsp && rsp->ring) 403 dma_free_coherent(&ha->pdev->dev, 404 (rsp->length_fx00 + 1) * sizeof(request_t), 405 rsp->ring_fx00, rsp->dma_fx00); 406 } else if (rsp && rsp->ring) { 407 dma_free_coherent(&ha->pdev->dev, 408 (rsp->length + 1) * sizeof(response_t), 409 rsp->ring, rsp->dma); 410 } 411 kfree(rsp); 412 rsp = NULL; 413 } 414 415 static void qla2x00_free_queues(struct qla_hw_data *ha) 416 { 417 struct req_que *req; 418 struct rsp_que *rsp; 419 int cnt; 420 421 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 422 if (!test_bit(cnt, ha->req_qid_map)) 423 continue; 424 425 req = ha->req_q_map[cnt]; 426 qla2x00_free_req_que(ha, req); 427 } 428 kfree(ha->req_q_map); 429 ha->req_q_map = NULL; 430 431 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 432 if (!test_bit(cnt, ha->rsp_qid_map)) 433 continue; 434 435 rsp = ha->rsp_q_map[cnt]; 436 qla2x00_free_rsp_que(ha, rsp); 437 } 438 kfree(ha->rsp_q_map); 439 ha->rsp_q_map = NULL; 440 } 441 442 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 443 { 444 uint16_t options = 0; 445 int ques, req, ret; 446 struct qla_hw_data *ha = vha->hw; 447 448 if (!(ha->fw_attributes & BIT_6)) { 449 ql_log(ql_log_warn, vha, 0x00d8, 450 "Firmware is not multi-queue capable.\n"); 451 goto fail; 452 } 453 if (ql2xmultique_tag) { 454 /* create a request queue for IO */ 455 options |= BIT_7; 456 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 457 QLA_DEFAULT_QUE_QOS); 458 if (!req) { 459 ql_log(ql_log_warn, vha, 0x00e0, 460 "Failed to create request queue.\n"); 461 goto fail; 462 } 463 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 464 vha->req = ha->req_q_map[req]; 465 options |= BIT_1; 466 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 467 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 468 if (!ret) { 469 ql_log(ql_log_warn, vha, 0x00e8, 470 "Failed to create response queue.\n"); 471 goto fail2; 472 } 473 } 474 ha->flags.cpu_affinity_enabled = 1; 475 ql_dbg(ql_dbg_multiq, vha, 0xc007, 476 "CPU affinity mode enabled, " 477 "no. of response queues:%d no. of request queues:%d.\n", 478 ha->max_rsp_queues, ha->max_req_queues); 479 ql_dbg(ql_dbg_init, vha, 0x00e9, 480 "CPU affinity mode enabled, " 481 "no. of response queues:%d no. of request queues:%d.\n", 482 ha->max_rsp_queues, ha->max_req_queues); 483 } 484 return 0; 485 fail2: 486 qla25xx_delete_queues(vha); 487 destroy_workqueue(ha->wq); 488 ha->wq = NULL; 489 vha->req = ha->req_q_map[0]; 490 fail: 491 ha->mqenable = 0; 492 kfree(ha->req_q_map); 493 kfree(ha->rsp_q_map); 494 ha->max_req_queues = ha->max_rsp_queues = 1; 495 return 1; 496 } 497 498 static char * 499 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 500 { 501 struct qla_hw_data *ha = vha->hw; 502 static char *pci_bus_modes[] = { 503 "33", "66", "100", "133", 504 }; 505 uint16_t pci_bus; 506 507 strcpy(str, "PCI"); 508 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 509 if (pci_bus) { 510 strcat(str, "-X ("); 511 strcat(str, pci_bus_modes[pci_bus]); 512 } else { 513 pci_bus = (ha->pci_attr & BIT_8) >> 8; 514 strcat(str, " ("); 515 strcat(str, pci_bus_modes[pci_bus]); 516 } 517 strcat(str, " MHz)"); 518 519 return (str); 520 } 521 522 static char * 523 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 524 { 525 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 526 struct qla_hw_data *ha = vha->hw; 527 uint32_t pci_bus; 528 529 if (pci_is_pcie(ha->pdev)) { 530 char lwstr[6]; 531 uint32_t lstat, lspeed, lwidth; 532 533 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 534 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 535 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 536 537 strcpy(str, "PCIe ("); 538 switch (lspeed) { 539 case 1: 540 strcat(str, "2.5GT/s "); 541 break; 542 case 2: 543 strcat(str, "5.0GT/s "); 544 break; 545 case 3: 546 strcat(str, "8.0GT/s "); 547 break; 548 default: 549 strcat(str, "<unknown> "); 550 break; 551 } 552 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 553 strcat(str, lwstr); 554 555 return str; 556 } 557 558 strcpy(str, "PCI"); 559 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 560 if (pci_bus == 0 || pci_bus == 8) { 561 strcat(str, " ("); 562 strcat(str, pci_bus_modes[pci_bus >> 3]); 563 } else { 564 strcat(str, "-X "); 565 if (pci_bus & BIT_2) 566 strcat(str, "Mode 2"); 567 else 568 strcat(str, "Mode 1"); 569 strcat(str, " ("); 570 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 571 } 572 strcat(str, " MHz)"); 573 574 return str; 575 } 576 577 static char * 578 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 579 { 580 char un_str[10]; 581 struct qla_hw_data *ha = vha->hw; 582 583 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 584 ha->fw_minor_version, ha->fw_subminor_version); 585 586 if (ha->fw_attributes & BIT_9) { 587 strcat(str, "FLX"); 588 return (str); 589 } 590 591 switch (ha->fw_attributes & 0xFF) { 592 case 0x7: 593 strcat(str, "EF"); 594 break; 595 case 0x17: 596 strcat(str, "TP"); 597 break; 598 case 0x37: 599 strcat(str, "IP"); 600 break; 601 case 0x77: 602 strcat(str, "VI"); 603 break; 604 default: 605 sprintf(un_str, "(%x)", ha->fw_attributes); 606 strcat(str, un_str); 607 break; 608 } 609 if (ha->fw_attributes & 0x100) 610 strcat(str, "X"); 611 612 return (str); 613 } 614 615 static char * 616 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 617 { 618 struct qla_hw_data *ha = vha->hw; 619 620 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 621 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 622 return str; 623 } 624 625 void 626 qla2x00_sp_free_dma(void *vha, void *ptr) 627 { 628 srb_t *sp = (srb_t *)ptr; 629 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 630 struct qla_hw_data *ha = sp->fcport->vha->hw; 631 void *ctx = GET_CMD_CTX_SP(sp); 632 633 if (sp->flags & SRB_DMA_VALID) { 634 scsi_dma_unmap(cmd); 635 sp->flags &= ~SRB_DMA_VALID; 636 } 637 638 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 639 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 640 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 641 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 642 } 643 644 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 645 /* List assured to be having elements */ 646 qla2x00_clean_dsd_pool(ha, sp, NULL); 647 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 648 } 649 650 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 651 dma_pool_free(ha->dl_dma_pool, ctx, 652 ((struct crc_context *)ctx)->crc_ctx_dma); 653 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 654 } 655 656 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 657 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 658 659 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 660 ctx1->fcp_cmnd_dma); 661 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 662 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 663 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 664 mempool_free(ctx1, ha->ctx_mempool); 665 ctx1 = NULL; 666 } 667 668 CMD_SP(cmd) = NULL; 669 qla2x00_rel_sp(sp->fcport->vha, sp); 670 } 671 672 static void 673 qla2x00_sp_compl(void *data, void *ptr, int res) 674 { 675 struct qla_hw_data *ha = (struct qla_hw_data *)data; 676 srb_t *sp = (srb_t *)ptr; 677 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 678 679 cmd->result = res; 680 681 if (atomic_read(&sp->ref_count) == 0) { 682 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 683 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 684 sp, GET_CMD_SP(sp)); 685 if (ql2xextended_error_logging & ql_dbg_io) 686 WARN_ON(atomic_read(&sp->ref_count) == 0); 687 return; 688 } 689 if (!atomic_dec_and_test(&sp->ref_count)) 690 return; 691 692 qla2x00_sp_free_dma(ha, sp); 693 cmd->scsi_done(cmd); 694 } 695 696 /* If we are SP1 here, we need to still take and release the host_lock as SP1 697 * does not have the changes necessary to avoid taking host->host_lock. 698 */ 699 static int 700 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 701 { 702 scsi_qla_host_t *vha = shost_priv(host); 703 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 704 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 705 struct qla_hw_data *ha = vha->hw; 706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 707 srb_t *sp; 708 int rval; 709 710 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 711 cmd->result = DID_NO_CONNECT << 16; 712 goto qc24_fail_command; 713 } 714 715 if (ha->flags.eeh_busy) { 716 if (ha->flags.pci_channel_io_perm_failure) { 717 ql_dbg(ql_dbg_aer, vha, 0x9010, 718 "PCI Channel IO permanent failure, exiting " 719 "cmd=%p.\n", cmd); 720 cmd->result = DID_NO_CONNECT << 16; 721 } else { 722 ql_dbg(ql_dbg_aer, vha, 0x9011, 723 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 724 cmd->result = DID_REQUEUE << 16; 725 } 726 goto qc24_fail_command; 727 } 728 729 rval = fc_remote_port_chkready(rport); 730 if (rval) { 731 cmd->result = rval; 732 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 733 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 734 cmd, rval); 735 goto qc24_fail_command; 736 } 737 738 if (!vha->flags.difdix_supported && 739 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 740 ql_dbg(ql_dbg_io, vha, 0x3004, 741 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 742 cmd); 743 cmd->result = DID_NO_CONNECT << 16; 744 goto qc24_fail_command; 745 } 746 747 if (!fcport) { 748 cmd->result = DID_NO_CONNECT << 16; 749 goto qc24_fail_command; 750 } 751 752 if (atomic_read(&fcport->state) != FCS_ONLINE) { 753 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 754 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 755 ql_dbg(ql_dbg_io, vha, 0x3005, 756 "Returning DNC, fcport_state=%d loop_state=%d.\n", 757 atomic_read(&fcport->state), 758 atomic_read(&base_vha->loop_state)); 759 cmd->result = DID_NO_CONNECT << 16; 760 goto qc24_fail_command; 761 } 762 goto qc24_target_busy; 763 } 764 765 /* 766 * Return target busy if we've received a non-zero retry_delay_timer 767 * in a FCP_RSP. 768 */ 769 if (fcport->retry_delay_timestamp == 0) { 770 /* retry delay not set */ 771 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 772 fcport->retry_delay_timestamp = 0; 773 else 774 goto qc24_target_busy; 775 776 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 777 if (!sp) 778 goto qc24_host_busy; 779 780 sp->u.scmd.cmd = cmd; 781 sp->type = SRB_SCSI_CMD; 782 atomic_set(&sp->ref_count, 1); 783 CMD_SP(cmd) = (void *)sp; 784 sp->free = qla2x00_sp_free_dma; 785 sp->done = qla2x00_sp_compl; 786 787 rval = ha->isp_ops->start_scsi(sp); 788 if (rval != QLA_SUCCESS) { 789 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 790 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 791 goto qc24_host_busy_free_sp; 792 } 793 794 return 0; 795 796 qc24_host_busy_free_sp: 797 qla2x00_sp_free_dma(ha, sp); 798 799 qc24_host_busy: 800 return SCSI_MLQUEUE_HOST_BUSY; 801 802 qc24_target_busy: 803 return SCSI_MLQUEUE_TARGET_BUSY; 804 805 qc24_fail_command: 806 cmd->scsi_done(cmd); 807 808 return 0; 809 } 810 811 /* 812 * qla2x00_eh_wait_on_command 813 * Waits for the command to be returned by the Firmware for some 814 * max time. 815 * 816 * Input: 817 * cmd = Scsi Command to wait on. 818 * 819 * Return: 820 * Not Found : 0 821 * Found : 1 822 */ 823 static int 824 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 825 { 826 #define ABORT_POLLING_PERIOD 1000 827 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 828 unsigned long wait_iter = ABORT_WAIT_ITER; 829 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 830 struct qla_hw_data *ha = vha->hw; 831 int ret = QLA_SUCCESS; 832 833 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 834 ql_dbg(ql_dbg_taskm, vha, 0x8005, 835 "Return:eh_wait.\n"); 836 return ret; 837 } 838 839 while (CMD_SP(cmd) && wait_iter--) { 840 msleep(ABORT_POLLING_PERIOD); 841 } 842 if (CMD_SP(cmd)) 843 ret = QLA_FUNCTION_FAILED; 844 845 return ret; 846 } 847 848 /* 849 * qla2x00_wait_for_hba_online 850 * Wait till the HBA is online after going through 851 * <= MAX_RETRIES_OF_ISP_ABORT or 852 * finally HBA is disabled ie marked offline 853 * 854 * Input: 855 * ha - pointer to host adapter structure 856 * 857 * Note: 858 * Does context switching-Release SPIN_LOCK 859 * (if any) before calling this routine. 860 * 861 * Return: 862 * Success (Adapter is online) : 0 863 * Failed (Adapter is offline/disabled) : 1 864 */ 865 int 866 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 867 { 868 int return_status; 869 unsigned long wait_online; 870 struct qla_hw_data *ha = vha->hw; 871 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 872 873 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 874 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 875 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 876 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 877 ha->dpc_active) && time_before(jiffies, wait_online)) { 878 879 msleep(1000); 880 } 881 if (base_vha->flags.online) 882 return_status = QLA_SUCCESS; 883 else 884 return_status = QLA_FUNCTION_FAILED; 885 886 return (return_status); 887 } 888 889 /* 890 * qla2x00_wait_for_hba_ready 891 * Wait till the HBA is ready before doing driver unload 892 * 893 * Input: 894 * ha - pointer to host adapter structure 895 * 896 * Note: 897 * Does context switching-Release SPIN_LOCK 898 * (if any) before calling this routine. 899 * 900 */ 901 static void 902 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 903 { 904 struct qla_hw_data *ha = vha->hw; 905 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 906 907 while ((qla2x00_reset_active(vha) || ha->dpc_active || 908 ha->flags.mbox_busy) || 909 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 910 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 911 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 912 break; 913 msleep(1000); 914 } 915 } 916 917 int 918 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 919 { 920 int return_status; 921 unsigned long wait_reset; 922 struct qla_hw_data *ha = vha->hw; 923 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 924 925 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 926 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 927 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 928 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 929 ha->dpc_active) && time_before(jiffies, wait_reset)) { 930 931 msleep(1000); 932 933 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 934 ha->flags.chip_reset_done) 935 break; 936 } 937 if (ha->flags.chip_reset_done) 938 return_status = QLA_SUCCESS; 939 else 940 return_status = QLA_FUNCTION_FAILED; 941 942 return return_status; 943 } 944 945 static void 946 sp_get(struct srb *sp) 947 { 948 atomic_inc(&sp->ref_count); 949 } 950 951 #define ISP_REG_DISCONNECT 0xffffffffU 952 /************************************************************************** 953 * qla2x00_isp_reg_stat 954 * 955 * Description: 956 * Read the host status register of ISP before aborting the command. 957 * 958 * Input: 959 * ha = pointer to host adapter structure. 960 * 961 * 962 * Returns: 963 * Either true or false. 964 * 965 * Note: Return true if there is register disconnect. 966 **************************************************************************/ 967 static inline 968 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 969 { 970 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 971 972 return ((RD_REG_DWORD(®->host_status)) == ISP_REG_DISCONNECT); 973 } 974 975 /************************************************************************** 976 * qla2xxx_eh_abort 977 * 978 * Description: 979 * The abort function will abort the specified command. 980 * 981 * Input: 982 * cmd = Linux SCSI command packet to be aborted. 983 * 984 * Returns: 985 * Either SUCCESS or FAILED. 986 * 987 * Note: 988 * Only return FAILED if command not returned by firmware. 989 **************************************************************************/ 990 static int 991 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 992 { 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 994 srb_t *sp; 995 int ret; 996 unsigned int id; 997 uint64_t lun; 998 unsigned long flags; 999 int rval, wait = 0; 1000 struct qla_hw_data *ha = vha->hw; 1001 1002 if (qla2x00_isp_reg_stat(ha)) { 1003 ql_log(ql_log_info, vha, 0x8042, 1004 "PCI/Register disconnect, exiting.\n"); 1005 return FAILED; 1006 } 1007 if (!CMD_SP(cmd)) 1008 return SUCCESS; 1009 1010 ret = fc_block_scsi_eh(cmd); 1011 if (ret != 0) 1012 return ret; 1013 ret = SUCCESS; 1014 1015 id = cmd->device->id; 1016 lun = cmd->device->lun; 1017 1018 spin_lock_irqsave(&ha->hardware_lock, flags); 1019 sp = (srb_t *) CMD_SP(cmd); 1020 if (!sp) { 1021 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1022 return SUCCESS; 1023 } 1024 1025 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1026 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1027 vha->host_no, id, lun, sp, cmd, sp->handle); 1028 1029 /* Get a reference to the sp and drop the lock.*/ 1030 sp_get(sp); 1031 1032 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1033 rval = ha->isp_ops->abort_command(sp); 1034 if (rval) { 1035 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1036 ret = SUCCESS; 1037 else 1038 ret = FAILED; 1039 1040 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1041 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1042 } else { 1043 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1044 "Abort command mbx success cmd=%p.\n", cmd); 1045 wait = 1; 1046 } 1047 1048 spin_lock_irqsave(&ha->hardware_lock, flags); 1049 sp->done(ha, sp, 0); 1050 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1051 1052 /* Did the command return during mailbox execution? */ 1053 if (ret == FAILED && !CMD_SP(cmd)) 1054 ret = SUCCESS; 1055 1056 /* Wait for the command to be returned. */ 1057 if (wait) { 1058 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1059 ql_log(ql_log_warn, vha, 0x8006, 1060 "Abort handler timed out cmd=%p.\n", cmd); 1061 ret = FAILED; 1062 } 1063 } 1064 1065 ql_log(ql_log_info, vha, 0x801c, 1066 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1067 vha->host_no, id, lun, wait, ret); 1068 1069 return ret; 1070 } 1071 1072 int 1073 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1074 uint64_t l, enum nexus_wait_type type) 1075 { 1076 int cnt, match, status; 1077 unsigned long flags; 1078 struct qla_hw_data *ha = vha->hw; 1079 struct req_que *req; 1080 srb_t *sp; 1081 struct scsi_cmnd *cmd; 1082 1083 status = QLA_SUCCESS; 1084 1085 spin_lock_irqsave(&ha->hardware_lock, flags); 1086 req = vha->req; 1087 for (cnt = 1; status == QLA_SUCCESS && 1088 cnt < req->num_outstanding_cmds; cnt++) { 1089 sp = req->outstanding_cmds[cnt]; 1090 if (!sp) 1091 continue; 1092 if (sp->type != SRB_SCSI_CMD) 1093 continue; 1094 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1095 continue; 1096 match = 0; 1097 cmd = GET_CMD_SP(sp); 1098 switch (type) { 1099 case WAIT_HOST: 1100 match = 1; 1101 break; 1102 case WAIT_TARGET: 1103 match = cmd->device->id == t; 1104 break; 1105 case WAIT_LUN: 1106 match = (cmd->device->id == t && 1107 cmd->device->lun == l); 1108 break; 1109 } 1110 if (!match) 1111 continue; 1112 1113 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1114 status = qla2x00_eh_wait_on_command(cmd); 1115 spin_lock_irqsave(&ha->hardware_lock, flags); 1116 } 1117 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1118 1119 return status; 1120 } 1121 1122 static char *reset_errors[] = { 1123 "HBA not online", 1124 "HBA not ready", 1125 "Task management failed", 1126 "Waiting for command completions", 1127 }; 1128 1129 static int 1130 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1131 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1132 { 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1134 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1135 int err; 1136 1137 if (!fcport) { 1138 return FAILED; 1139 } 1140 1141 err = fc_block_scsi_eh(cmd); 1142 if (err != 0) 1143 return err; 1144 1145 ql_log(ql_log_info, vha, 0x8009, 1146 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1147 cmd->device->id, cmd->device->lun, cmd); 1148 1149 err = 0; 1150 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1151 ql_log(ql_log_warn, vha, 0x800a, 1152 "Wait for hba online failed for cmd=%p.\n", cmd); 1153 goto eh_reset_failed; 1154 } 1155 err = 2; 1156 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1157 != QLA_SUCCESS) { 1158 ql_log(ql_log_warn, vha, 0x800c, 1159 "do_reset failed for cmd=%p.\n", cmd); 1160 goto eh_reset_failed; 1161 } 1162 err = 3; 1163 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1164 cmd->device->lun, type) != QLA_SUCCESS) { 1165 ql_log(ql_log_warn, vha, 0x800d, 1166 "wait for pending cmds failed for cmd=%p.\n", cmd); 1167 goto eh_reset_failed; 1168 } 1169 1170 ql_log(ql_log_info, vha, 0x800e, 1171 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1172 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1173 1174 return SUCCESS; 1175 1176 eh_reset_failed: 1177 ql_log(ql_log_info, vha, 0x800f, 1178 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1179 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1180 cmd); 1181 return FAILED; 1182 } 1183 1184 static int 1185 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1186 { 1187 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1188 struct qla_hw_data *ha = vha->hw; 1189 1190 if (qla2x00_isp_reg_stat(ha)) { 1191 ql_log(ql_log_info, vha, 0x803e, 1192 "PCI/Register disconnect, exiting.\n"); 1193 return FAILED; 1194 } 1195 1196 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1197 ha->isp_ops->lun_reset); 1198 } 1199 1200 static int 1201 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1202 { 1203 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1204 struct qla_hw_data *ha = vha->hw; 1205 1206 if (qla2x00_isp_reg_stat(ha)) { 1207 ql_log(ql_log_info, vha, 0x803f, 1208 "PCI/Register disconnect, exiting.\n"); 1209 return FAILED; 1210 } 1211 1212 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1213 ha->isp_ops->target_reset); 1214 } 1215 1216 /************************************************************************** 1217 * qla2xxx_eh_bus_reset 1218 * 1219 * Description: 1220 * The bus reset function will reset the bus and abort any executing 1221 * commands. 1222 * 1223 * Input: 1224 * cmd = Linux SCSI command packet of the command that cause the 1225 * bus reset. 1226 * 1227 * Returns: 1228 * SUCCESS/FAILURE (defined as macro in scsi.h). 1229 * 1230 **************************************************************************/ 1231 static int 1232 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1233 { 1234 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1235 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1236 int ret = FAILED; 1237 unsigned int id; 1238 uint64_t lun; 1239 struct qla_hw_data *ha = vha->hw; 1240 1241 if (qla2x00_isp_reg_stat(ha)) { 1242 ql_log(ql_log_info, vha, 0x8040, 1243 "PCI/Register disconnect, exiting.\n"); 1244 return FAILED; 1245 } 1246 1247 id = cmd->device->id; 1248 lun = cmd->device->lun; 1249 1250 if (!fcport) { 1251 return ret; 1252 } 1253 1254 ret = fc_block_scsi_eh(cmd); 1255 if (ret != 0) 1256 return ret; 1257 ret = FAILED; 1258 1259 ql_log(ql_log_info, vha, 0x8012, 1260 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1261 1262 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1263 ql_log(ql_log_fatal, vha, 0x8013, 1264 "Wait for hba online failed board disabled.\n"); 1265 goto eh_bus_reset_done; 1266 } 1267 1268 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1269 ret = SUCCESS; 1270 1271 if (ret == FAILED) 1272 goto eh_bus_reset_done; 1273 1274 /* Flush outstanding commands. */ 1275 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1276 QLA_SUCCESS) { 1277 ql_log(ql_log_warn, vha, 0x8014, 1278 "Wait for pending commands failed.\n"); 1279 ret = FAILED; 1280 } 1281 1282 eh_bus_reset_done: 1283 ql_log(ql_log_warn, vha, 0x802b, 1284 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1285 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1286 1287 return ret; 1288 } 1289 1290 /************************************************************************** 1291 * qla2xxx_eh_host_reset 1292 * 1293 * Description: 1294 * The reset function will reset the Adapter. 1295 * 1296 * Input: 1297 * cmd = Linux SCSI command packet of the command that cause the 1298 * adapter reset. 1299 * 1300 * Returns: 1301 * Either SUCCESS or FAILED. 1302 * 1303 * Note: 1304 **************************************************************************/ 1305 static int 1306 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1307 { 1308 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1309 struct qla_hw_data *ha = vha->hw; 1310 int ret = FAILED; 1311 unsigned int id; 1312 uint64_t lun; 1313 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1314 1315 if (qla2x00_isp_reg_stat(ha)) { 1316 ql_log(ql_log_info, vha, 0x8041, 1317 "PCI/Register disconnect, exiting.\n"); 1318 schedule_work(&ha->board_disable); 1319 return SUCCESS; 1320 } 1321 1322 id = cmd->device->id; 1323 lun = cmd->device->lun; 1324 1325 ql_log(ql_log_info, vha, 0x8018, 1326 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1327 1328 /* 1329 * No point in issuing another reset if one is active. Also do not 1330 * attempt a reset if we are updating flash. 1331 */ 1332 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1333 goto eh_host_reset_lock; 1334 1335 if (vha != base_vha) { 1336 if (qla2x00_vp_abort_isp(vha)) 1337 goto eh_host_reset_lock; 1338 } else { 1339 if (IS_P3P_TYPE(vha->hw)) { 1340 if (!qla82xx_fcoe_ctx_reset(vha)) { 1341 /* Ctx reset success */ 1342 ret = SUCCESS; 1343 goto eh_host_reset_lock; 1344 } 1345 /* fall thru if ctx reset failed */ 1346 } 1347 if (ha->wq) 1348 flush_workqueue(ha->wq); 1349 1350 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1351 if (ha->isp_ops->abort_isp(base_vha)) { 1352 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1353 /* failed. schedule dpc to try */ 1354 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1355 1356 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1357 ql_log(ql_log_warn, vha, 0x802a, 1358 "wait for hba online failed.\n"); 1359 goto eh_host_reset_lock; 1360 } 1361 } 1362 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1363 } 1364 1365 /* Waiting for command to be returned to OS.*/ 1366 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1367 QLA_SUCCESS) 1368 ret = SUCCESS; 1369 1370 eh_host_reset_lock: 1371 ql_log(ql_log_info, vha, 0x8017, 1372 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1373 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1374 1375 return ret; 1376 } 1377 1378 /* 1379 * qla2x00_loop_reset 1380 * Issue loop reset. 1381 * 1382 * Input: 1383 * ha = adapter block pointer. 1384 * 1385 * Returns: 1386 * 0 = success 1387 */ 1388 int 1389 qla2x00_loop_reset(scsi_qla_host_t *vha) 1390 { 1391 int ret; 1392 struct fc_port *fcport; 1393 struct qla_hw_data *ha = vha->hw; 1394 1395 if (IS_QLAFX00(ha)) { 1396 return qlafx00_loop_reset(vha); 1397 } 1398 1399 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1400 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1401 if (fcport->port_type != FCT_TARGET) 1402 continue; 1403 1404 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1405 if (ret != QLA_SUCCESS) { 1406 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1407 "Bus Reset failed: Reset=%d " 1408 "d_id=%x.\n", ret, fcport->d_id.b24); 1409 } 1410 } 1411 } 1412 1413 1414 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1415 atomic_set(&vha->loop_state, LOOP_DOWN); 1416 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1417 qla2x00_mark_all_devices_lost(vha, 0); 1418 ret = qla2x00_full_login_lip(vha); 1419 if (ret != QLA_SUCCESS) { 1420 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1421 "full_login_lip=%d.\n", ret); 1422 } 1423 } 1424 1425 if (ha->flags.enable_lip_reset) { 1426 ret = qla2x00_lip_reset(vha); 1427 if (ret != QLA_SUCCESS) 1428 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1429 "lip_reset failed (%d).\n", ret); 1430 } 1431 1432 /* Issue marker command only when we are going to start the I/O */ 1433 vha->marker_needed = 1; 1434 1435 return QLA_SUCCESS; 1436 } 1437 1438 void 1439 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1440 { 1441 int que, cnt; 1442 unsigned long flags; 1443 srb_t *sp; 1444 struct qla_hw_data *ha = vha->hw; 1445 struct req_que *req; 1446 1447 qlt_host_reset_handler(ha); 1448 1449 spin_lock_irqsave(&ha->hardware_lock, flags); 1450 for (que = 0; que < ha->max_req_queues; que++) { 1451 req = ha->req_q_map[que]; 1452 if (!req) 1453 continue; 1454 if (!req->outstanding_cmds) 1455 continue; 1456 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1457 sp = req->outstanding_cmds[cnt]; 1458 if (sp) { 1459 /* Don't abort commands in adapter during EEH 1460 * recovery as it's not accessible/responding. 1461 */ 1462 if (!ha->flags.eeh_busy) { 1463 /* Get a reference to the sp and drop the lock. 1464 * The reference ensures this sp->done() call 1465 * - and not the call in qla2xxx_eh_abort() - 1466 * ends the SCSI command (with result 'res'). 1467 */ 1468 sp_get(sp); 1469 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1470 qla2xxx_eh_abort(GET_CMD_SP(sp)); 1471 spin_lock_irqsave(&ha->hardware_lock, flags); 1472 } 1473 req->outstanding_cmds[cnt] = NULL; 1474 sp->done(vha, sp, res); 1475 } 1476 } 1477 } 1478 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1479 } 1480 1481 static int 1482 qla2xxx_slave_alloc(struct scsi_device *sdev) 1483 { 1484 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1485 1486 if (!rport || fc_remote_port_chkready(rport)) 1487 return -ENXIO; 1488 1489 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1490 1491 return 0; 1492 } 1493 1494 static int 1495 qla2xxx_slave_configure(struct scsi_device *sdev) 1496 { 1497 scsi_qla_host_t *vha = shost_priv(sdev->host); 1498 struct req_que *req = vha->req; 1499 1500 if (IS_T10_PI_CAPABLE(vha->hw)) 1501 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1502 1503 scsi_change_queue_depth(sdev, req->max_q_depth); 1504 return 0; 1505 } 1506 1507 static void 1508 qla2xxx_slave_destroy(struct scsi_device *sdev) 1509 { 1510 sdev->hostdata = NULL; 1511 } 1512 1513 /** 1514 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1515 * @ha: HA context 1516 * 1517 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1518 * supported addressing method. 1519 */ 1520 static void 1521 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1522 { 1523 /* Assume a 32bit DMA mask. */ 1524 ha->flags.enable_64bit_addressing = 0; 1525 1526 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1527 /* Any upper-dword bits set? */ 1528 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1529 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1530 /* Ok, a 64bit DMA mask is applicable. */ 1531 ha->flags.enable_64bit_addressing = 1; 1532 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1533 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1534 return; 1535 } 1536 } 1537 1538 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1539 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1540 } 1541 1542 static void 1543 qla2x00_enable_intrs(struct qla_hw_data *ha) 1544 { 1545 unsigned long flags = 0; 1546 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1547 1548 spin_lock_irqsave(&ha->hardware_lock, flags); 1549 ha->interrupts_on = 1; 1550 /* enable risc and host interrupts */ 1551 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1552 RD_REG_WORD(®->ictrl); 1553 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1554 1555 } 1556 1557 static void 1558 qla2x00_disable_intrs(struct qla_hw_data *ha) 1559 { 1560 unsigned long flags = 0; 1561 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1562 1563 spin_lock_irqsave(&ha->hardware_lock, flags); 1564 ha->interrupts_on = 0; 1565 /* disable risc and host interrupts */ 1566 WRT_REG_WORD(®->ictrl, 0); 1567 RD_REG_WORD(®->ictrl); 1568 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1569 } 1570 1571 static void 1572 qla24xx_enable_intrs(struct qla_hw_data *ha) 1573 { 1574 unsigned long flags = 0; 1575 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1576 1577 spin_lock_irqsave(&ha->hardware_lock, flags); 1578 ha->interrupts_on = 1; 1579 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1580 RD_REG_DWORD(®->ictrl); 1581 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1582 } 1583 1584 static void 1585 qla24xx_disable_intrs(struct qla_hw_data *ha) 1586 { 1587 unsigned long flags = 0; 1588 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1589 1590 if (IS_NOPOLLING_TYPE(ha)) 1591 return; 1592 spin_lock_irqsave(&ha->hardware_lock, flags); 1593 ha->interrupts_on = 0; 1594 WRT_REG_DWORD(®->ictrl, 0); 1595 RD_REG_DWORD(®->ictrl); 1596 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1597 } 1598 1599 static int 1600 qla2x00_iospace_config(struct qla_hw_data *ha) 1601 { 1602 resource_size_t pio; 1603 uint16_t msix; 1604 int cpus; 1605 1606 if (pci_request_selected_regions(ha->pdev, ha->bars, 1607 QLA2XXX_DRIVER_NAME)) { 1608 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1609 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1610 pci_name(ha->pdev)); 1611 goto iospace_error_exit; 1612 } 1613 if (!(ha->bars & 1)) 1614 goto skip_pio; 1615 1616 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1617 pio = pci_resource_start(ha->pdev, 0); 1618 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1619 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1620 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1621 "Invalid pci I/O region size (%s).\n", 1622 pci_name(ha->pdev)); 1623 pio = 0; 1624 } 1625 } else { 1626 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1627 "Region #0 no a PIO resource (%s).\n", 1628 pci_name(ha->pdev)); 1629 pio = 0; 1630 } 1631 ha->pio_address = pio; 1632 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1633 "PIO address=%llu.\n", 1634 (unsigned long long)ha->pio_address); 1635 1636 skip_pio: 1637 /* Use MMIO operations for all accesses. */ 1638 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1639 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1640 "Region #1 not an MMIO resource (%s), aborting.\n", 1641 pci_name(ha->pdev)); 1642 goto iospace_error_exit; 1643 } 1644 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1646 "Invalid PCI mem region size (%s), aborting.\n", 1647 pci_name(ha->pdev)); 1648 goto iospace_error_exit; 1649 } 1650 1651 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1652 if (!ha->iobase) { 1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1654 "Cannot remap MMIO (%s), aborting.\n", 1655 pci_name(ha->pdev)); 1656 goto iospace_error_exit; 1657 } 1658 1659 /* Determine queue resources */ 1660 ha->max_req_queues = ha->max_rsp_queues = 1; 1661 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1662 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1663 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1664 goto mqiobase_exit; 1665 1666 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1667 pci_resource_len(ha->pdev, 3)); 1668 if (ha->mqiobase) { 1669 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1670 "MQIO Base=%p.\n", ha->mqiobase); 1671 /* Read MSIX vector size of the board */ 1672 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1673 ha->msix_count = msix; 1674 /* Max queues are bounded by available msix vectors */ 1675 /* queue 0 uses two msix vectors */ 1676 if (ql2xmultique_tag) { 1677 cpus = num_online_cpus(); 1678 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1679 (cpus + 1) : (ha->msix_count - 1); 1680 ha->max_req_queues = 2; 1681 } else if (ql2xmaxqueues > 1) { 1682 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1683 QLA_MQ_SIZE : ql2xmaxqueues; 1684 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1685 "QoS mode set, max no of request queues:%d.\n", 1686 ha->max_req_queues); 1687 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1688 "QoS mode set, max no of request queues:%d.\n", 1689 ha->max_req_queues); 1690 } 1691 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1692 "MSI-X vector count: %d.\n", msix); 1693 } else 1694 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1695 "BAR 3 not enabled.\n"); 1696 1697 mqiobase_exit: 1698 ha->msix_count = ha->max_rsp_queues + 1; 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1700 "MSIX Count:%d.\n", ha->msix_count); 1701 return (0); 1702 1703 iospace_error_exit: 1704 return (-ENOMEM); 1705 } 1706 1707 1708 static int 1709 qla83xx_iospace_config(struct qla_hw_data *ha) 1710 { 1711 uint16_t msix; 1712 int cpus; 1713 1714 if (pci_request_selected_regions(ha->pdev, ha->bars, 1715 QLA2XXX_DRIVER_NAME)) { 1716 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1717 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1718 pci_name(ha->pdev)); 1719 1720 goto iospace_error_exit; 1721 } 1722 1723 /* Use MMIO operations for all accesses. */ 1724 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1725 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1726 "Invalid pci I/O region size (%s).\n", 1727 pci_name(ha->pdev)); 1728 goto iospace_error_exit; 1729 } 1730 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1731 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1732 "Invalid PCI mem region size (%s), aborting\n", 1733 pci_name(ha->pdev)); 1734 goto iospace_error_exit; 1735 } 1736 1737 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1738 if (!ha->iobase) { 1739 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1740 "Cannot remap MMIO (%s), aborting.\n", 1741 pci_name(ha->pdev)); 1742 goto iospace_error_exit; 1743 } 1744 1745 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1746 /* 83XX 26XX always use MQ type access for queues 1747 * - mbar 2, a.k.a region 4 */ 1748 ha->max_req_queues = ha->max_rsp_queues = 1; 1749 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1750 pci_resource_len(ha->pdev, 4)); 1751 1752 if (!ha->mqiobase) { 1753 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1754 "BAR2/region4 not enabled\n"); 1755 goto mqiobase_exit; 1756 } 1757 1758 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1759 pci_resource_len(ha->pdev, 2)); 1760 if (ha->msixbase) { 1761 /* Read MSIX vector size of the board */ 1762 pci_read_config_word(ha->pdev, 1763 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1764 ha->msix_count = msix; 1765 /* Max queues are bounded by available msix vectors */ 1766 /* queue 0 uses two msix vectors */ 1767 if (ql2xmultique_tag) { 1768 cpus = num_online_cpus(); 1769 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1770 (cpus + 1) : (ha->msix_count - 1); 1771 ha->max_req_queues = 2; 1772 } else if (ql2xmaxqueues > 1) { 1773 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1774 QLA_MQ_SIZE : ql2xmaxqueues; 1775 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1776 "QoS mode set, max no of request queues:%d.\n", 1777 ha->max_req_queues); 1778 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1779 "QoS mode set, max no of request queues:%d.\n", 1780 ha->max_req_queues); 1781 } 1782 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1783 "MSI-X vector count: %d.\n", msix); 1784 } else 1785 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1786 "BAR 1 not enabled.\n"); 1787 1788 mqiobase_exit: 1789 ha->msix_count = ha->max_rsp_queues + 1; 1790 1791 qlt_83xx_iospace_config(ha); 1792 1793 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1794 "MSIX Count:%d.\n", ha->msix_count); 1795 return 0; 1796 1797 iospace_error_exit: 1798 return -ENOMEM; 1799 } 1800 1801 static struct isp_operations qla2100_isp_ops = { 1802 .pci_config = qla2100_pci_config, 1803 .reset_chip = qla2x00_reset_chip, 1804 .chip_diag = qla2x00_chip_diag, 1805 .config_rings = qla2x00_config_rings, 1806 .reset_adapter = qla2x00_reset_adapter, 1807 .nvram_config = qla2x00_nvram_config, 1808 .update_fw_options = qla2x00_update_fw_options, 1809 .load_risc = qla2x00_load_risc, 1810 .pci_info_str = qla2x00_pci_info_str, 1811 .fw_version_str = qla2x00_fw_version_str, 1812 .intr_handler = qla2100_intr_handler, 1813 .enable_intrs = qla2x00_enable_intrs, 1814 .disable_intrs = qla2x00_disable_intrs, 1815 .abort_command = qla2x00_abort_command, 1816 .target_reset = qla2x00_abort_target, 1817 .lun_reset = qla2x00_lun_reset, 1818 .fabric_login = qla2x00_login_fabric, 1819 .fabric_logout = qla2x00_fabric_logout, 1820 .calc_req_entries = qla2x00_calc_iocbs_32, 1821 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1822 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1823 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1824 .read_nvram = qla2x00_read_nvram_data, 1825 .write_nvram = qla2x00_write_nvram_data, 1826 .fw_dump = qla2100_fw_dump, 1827 .beacon_on = NULL, 1828 .beacon_off = NULL, 1829 .beacon_blink = NULL, 1830 .read_optrom = qla2x00_read_optrom_data, 1831 .write_optrom = qla2x00_write_optrom_data, 1832 .get_flash_version = qla2x00_get_flash_version, 1833 .start_scsi = qla2x00_start_scsi, 1834 .abort_isp = qla2x00_abort_isp, 1835 .iospace_config = qla2x00_iospace_config, 1836 .initialize_adapter = qla2x00_initialize_adapter, 1837 }; 1838 1839 static struct isp_operations qla2300_isp_ops = { 1840 .pci_config = qla2300_pci_config, 1841 .reset_chip = qla2x00_reset_chip, 1842 .chip_diag = qla2x00_chip_diag, 1843 .config_rings = qla2x00_config_rings, 1844 .reset_adapter = qla2x00_reset_adapter, 1845 .nvram_config = qla2x00_nvram_config, 1846 .update_fw_options = qla2x00_update_fw_options, 1847 .load_risc = qla2x00_load_risc, 1848 .pci_info_str = qla2x00_pci_info_str, 1849 .fw_version_str = qla2x00_fw_version_str, 1850 .intr_handler = qla2300_intr_handler, 1851 .enable_intrs = qla2x00_enable_intrs, 1852 .disable_intrs = qla2x00_disable_intrs, 1853 .abort_command = qla2x00_abort_command, 1854 .target_reset = qla2x00_abort_target, 1855 .lun_reset = qla2x00_lun_reset, 1856 .fabric_login = qla2x00_login_fabric, 1857 .fabric_logout = qla2x00_fabric_logout, 1858 .calc_req_entries = qla2x00_calc_iocbs_32, 1859 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1860 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1861 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1862 .read_nvram = qla2x00_read_nvram_data, 1863 .write_nvram = qla2x00_write_nvram_data, 1864 .fw_dump = qla2300_fw_dump, 1865 .beacon_on = qla2x00_beacon_on, 1866 .beacon_off = qla2x00_beacon_off, 1867 .beacon_blink = qla2x00_beacon_blink, 1868 .read_optrom = qla2x00_read_optrom_data, 1869 .write_optrom = qla2x00_write_optrom_data, 1870 .get_flash_version = qla2x00_get_flash_version, 1871 .start_scsi = qla2x00_start_scsi, 1872 .abort_isp = qla2x00_abort_isp, 1873 .iospace_config = qla2x00_iospace_config, 1874 .initialize_adapter = qla2x00_initialize_adapter, 1875 }; 1876 1877 static struct isp_operations qla24xx_isp_ops = { 1878 .pci_config = qla24xx_pci_config, 1879 .reset_chip = qla24xx_reset_chip, 1880 .chip_diag = qla24xx_chip_diag, 1881 .config_rings = qla24xx_config_rings, 1882 .reset_adapter = qla24xx_reset_adapter, 1883 .nvram_config = qla24xx_nvram_config, 1884 .update_fw_options = qla24xx_update_fw_options, 1885 .load_risc = qla24xx_load_risc, 1886 .pci_info_str = qla24xx_pci_info_str, 1887 .fw_version_str = qla24xx_fw_version_str, 1888 .intr_handler = qla24xx_intr_handler, 1889 .enable_intrs = qla24xx_enable_intrs, 1890 .disable_intrs = qla24xx_disable_intrs, 1891 .abort_command = qla24xx_abort_command, 1892 .target_reset = qla24xx_abort_target, 1893 .lun_reset = qla24xx_lun_reset, 1894 .fabric_login = qla24xx_login_fabric, 1895 .fabric_logout = qla24xx_fabric_logout, 1896 .calc_req_entries = NULL, 1897 .build_iocbs = NULL, 1898 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1899 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1900 .read_nvram = qla24xx_read_nvram_data, 1901 .write_nvram = qla24xx_write_nvram_data, 1902 .fw_dump = qla24xx_fw_dump, 1903 .beacon_on = qla24xx_beacon_on, 1904 .beacon_off = qla24xx_beacon_off, 1905 .beacon_blink = qla24xx_beacon_blink, 1906 .read_optrom = qla24xx_read_optrom_data, 1907 .write_optrom = qla24xx_write_optrom_data, 1908 .get_flash_version = qla24xx_get_flash_version, 1909 .start_scsi = qla24xx_start_scsi, 1910 .abort_isp = qla2x00_abort_isp, 1911 .iospace_config = qla2x00_iospace_config, 1912 .initialize_adapter = qla2x00_initialize_adapter, 1913 }; 1914 1915 static struct isp_operations qla25xx_isp_ops = { 1916 .pci_config = qla25xx_pci_config, 1917 .reset_chip = qla24xx_reset_chip, 1918 .chip_diag = qla24xx_chip_diag, 1919 .config_rings = qla24xx_config_rings, 1920 .reset_adapter = qla24xx_reset_adapter, 1921 .nvram_config = qla24xx_nvram_config, 1922 .update_fw_options = qla24xx_update_fw_options, 1923 .load_risc = qla24xx_load_risc, 1924 .pci_info_str = qla24xx_pci_info_str, 1925 .fw_version_str = qla24xx_fw_version_str, 1926 .intr_handler = qla24xx_intr_handler, 1927 .enable_intrs = qla24xx_enable_intrs, 1928 .disable_intrs = qla24xx_disable_intrs, 1929 .abort_command = qla24xx_abort_command, 1930 .target_reset = qla24xx_abort_target, 1931 .lun_reset = qla24xx_lun_reset, 1932 .fabric_login = qla24xx_login_fabric, 1933 .fabric_logout = qla24xx_fabric_logout, 1934 .calc_req_entries = NULL, 1935 .build_iocbs = NULL, 1936 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1937 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1938 .read_nvram = qla25xx_read_nvram_data, 1939 .write_nvram = qla25xx_write_nvram_data, 1940 .fw_dump = qla25xx_fw_dump, 1941 .beacon_on = qla24xx_beacon_on, 1942 .beacon_off = qla24xx_beacon_off, 1943 .beacon_blink = qla24xx_beacon_blink, 1944 .read_optrom = qla25xx_read_optrom_data, 1945 .write_optrom = qla24xx_write_optrom_data, 1946 .get_flash_version = qla24xx_get_flash_version, 1947 .start_scsi = qla24xx_dif_start_scsi, 1948 .abort_isp = qla2x00_abort_isp, 1949 .iospace_config = qla2x00_iospace_config, 1950 .initialize_adapter = qla2x00_initialize_adapter, 1951 }; 1952 1953 static struct isp_operations qla81xx_isp_ops = { 1954 .pci_config = qla25xx_pci_config, 1955 .reset_chip = qla24xx_reset_chip, 1956 .chip_diag = qla24xx_chip_diag, 1957 .config_rings = qla24xx_config_rings, 1958 .reset_adapter = qla24xx_reset_adapter, 1959 .nvram_config = qla81xx_nvram_config, 1960 .update_fw_options = qla81xx_update_fw_options, 1961 .load_risc = qla81xx_load_risc, 1962 .pci_info_str = qla24xx_pci_info_str, 1963 .fw_version_str = qla24xx_fw_version_str, 1964 .intr_handler = qla24xx_intr_handler, 1965 .enable_intrs = qla24xx_enable_intrs, 1966 .disable_intrs = qla24xx_disable_intrs, 1967 .abort_command = qla24xx_abort_command, 1968 .target_reset = qla24xx_abort_target, 1969 .lun_reset = qla24xx_lun_reset, 1970 .fabric_login = qla24xx_login_fabric, 1971 .fabric_logout = qla24xx_fabric_logout, 1972 .calc_req_entries = NULL, 1973 .build_iocbs = NULL, 1974 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1975 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1976 .read_nvram = NULL, 1977 .write_nvram = NULL, 1978 .fw_dump = qla81xx_fw_dump, 1979 .beacon_on = qla24xx_beacon_on, 1980 .beacon_off = qla24xx_beacon_off, 1981 .beacon_blink = qla83xx_beacon_blink, 1982 .read_optrom = qla25xx_read_optrom_data, 1983 .write_optrom = qla24xx_write_optrom_data, 1984 .get_flash_version = qla24xx_get_flash_version, 1985 .start_scsi = qla24xx_dif_start_scsi, 1986 .abort_isp = qla2x00_abort_isp, 1987 .iospace_config = qla2x00_iospace_config, 1988 .initialize_adapter = qla2x00_initialize_adapter, 1989 }; 1990 1991 static struct isp_operations qla82xx_isp_ops = { 1992 .pci_config = qla82xx_pci_config, 1993 .reset_chip = qla82xx_reset_chip, 1994 .chip_diag = qla24xx_chip_diag, 1995 .config_rings = qla82xx_config_rings, 1996 .reset_adapter = qla24xx_reset_adapter, 1997 .nvram_config = qla81xx_nvram_config, 1998 .update_fw_options = qla24xx_update_fw_options, 1999 .load_risc = qla82xx_load_risc, 2000 .pci_info_str = qla24xx_pci_info_str, 2001 .fw_version_str = qla24xx_fw_version_str, 2002 .intr_handler = qla82xx_intr_handler, 2003 .enable_intrs = qla82xx_enable_intrs, 2004 .disable_intrs = qla82xx_disable_intrs, 2005 .abort_command = qla24xx_abort_command, 2006 .target_reset = qla24xx_abort_target, 2007 .lun_reset = qla24xx_lun_reset, 2008 .fabric_login = qla24xx_login_fabric, 2009 .fabric_logout = qla24xx_fabric_logout, 2010 .calc_req_entries = NULL, 2011 .build_iocbs = NULL, 2012 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2013 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2014 .read_nvram = qla24xx_read_nvram_data, 2015 .write_nvram = qla24xx_write_nvram_data, 2016 .fw_dump = qla82xx_fw_dump, 2017 .beacon_on = qla82xx_beacon_on, 2018 .beacon_off = qla82xx_beacon_off, 2019 .beacon_blink = NULL, 2020 .read_optrom = qla82xx_read_optrom_data, 2021 .write_optrom = qla82xx_write_optrom_data, 2022 .get_flash_version = qla82xx_get_flash_version, 2023 .start_scsi = qla82xx_start_scsi, 2024 .abort_isp = qla82xx_abort_isp, 2025 .iospace_config = qla82xx_iospace_config, 2026 .initialize_adapter = qla2x00_initialize_adapter, 2027 }; 2028 2029 static struct isp_operations qla8044_isp_ops = { 2030 .pci_config = qla82xx_pci_config, 2031 .reset_chip = qla82xx_reset_chip, 2032 .chip_diag = qla24xx_chip_diag, 2033 .config_rings = qla82xx_config_rings, 2034 .reset_adapter = qla24xx_reset_adapter, 2035 .nvram_config = qla81xx_nvram_config, 2036 .update_fw_options = qla24xx_update_fw_options, 2037 .load_risc = qla82xx_load_risc, 2038 .pci_info_str = qla24xx_pci_info_str, 2039 .fw_version_str = qla24xx_fw_version_str, 2040 .intr_handler = qla8044_intr_handler, 2041 .enable_intrs = qla82xx_enable_intrs, 2042 .disable_intrs = qla82xx_disable_intrs, 2043 .abort_command = qla24xx_abort_command, 2044 .target_reset = qla24xx_abort_target, 2045 .lun_reset = qla24xx_lun_reset, 2046 .fabric_login = qla24xx_login_fabric, 2047 .fabric_logout = qla24xx_fabric_logout, 2048 .calc_req_entries = NULL, 2049 .build_iocbs = NULL, 2050 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2052 .read_nvram = NULL, 2053 .write_nvram = NULL, 2054 .fw_dump = qla8044_fw_dump, 2055 .beacon_on = qla82xx_beacon_on, 2056 .beacon_off = qla82xx_beacon_off, 2057 .beacon_blink = NULL, 2058 .read_optrom = qla8044_read_optrom_data, 2059 .write_optrom = qla8044_write_optrom_data, 2060 .get_flash_version = qla82xx_get_flash_version, 2061 .start_scsi = qla82xx_start_scsi, 2062 .abort_isp = qla8044_abort_isp, 2063 .iospace_config = qla82xx_iospace_config, 2064 .initialize_adapter = qla2x00_initialize_adapter, 2065 }; 2066 2067 static struct isp_operations qla83xx_isp_ops = { 2068 .pci_config = qla25xx_pci_config, 2069 .reset_chip = qla24xx_reset_chip, 2070 .chip_diag = qla24xx_chip_diag, 2071 .config_rings = qla24xx_config_rings, 2072 .reset_adapter = qla24xx_reset_adapter, 2073 .nvram_config = qla81xx_nvram_config, 2074 .update_fw_options = qla81xx_update_fw_options, 2075 .load_risc = qla81xx_load_risc, 2076 .pci_info_str = qla24xx_pci_info_str, 2077 .fw_version_str = qla24xx_fw_version_str, 2078 .intr_handler = qla24xx_intr_handler, 2079 .enable_intrs = qla24xx_enable_intrs, 2080 .disable_intrs = qla24xx_disable_intrs, 2081 .abort_command = qla24xx_abort_command, 2082 .target_reset = qla24xx_abort_target, 2083 .lun_reset = qla24xx_lun_reset, 2084 .fabric_login = qla24xx_login_fabric, 2085 .fabric_logout = qla24xx_fabric_logout, 2086 .calc_req_entries = NULL, 2087 .build_iocbs = NULL, 2088 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2089 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2090 .read_nvram = NULL, 2091 .write_nvram = NULL, 2092 .fw_dump = qla83xx_fw_dump, 2093 .beacon_on = qla24xx_beacon_on, 2094 .beacon_off = qla24xx_beacon_off, 2095 .beacon_blink = qla83xx_beacon_blink, 2096 .read_optrom = qla25xx_read_optrom_data, 2097 .write_optrom = qla24xx_write_optrom_data, 2098 .get_flash_version = qla24xx_get_flash_version, 2099 .start_scsi = qla24xx_dif_start_scsi, 2100 .abort_isp = qla2x00_abort_isp, 2101 .iospace_config = qla83xx_iospace_config, 2102 .initialize_adapter = qla2x00_initialize_adapter, 2103 }; 2104 2105 static struct isp_operations qlafx00_isp_ops = { 2106 .pci_config = qlafx00_pci_config, 2107 .reset_chip = qlafx00_soft_reset, 2108 .chip_diag = qlafx00_chip_diag, 2109 .config_rings = qlafx00_config_rings, 2110 .reset_adapter = qlafx00_soft_reset, 2111 .nvram_config = NULL, 2112 .update_fw_options = NULL, 2113 .load_risc = NULL, 2114 .pci_info_str = qlafx00_pci_info_str, 2115 .fw_version_str = qlafx00_fw_version_str, 2116 .intr_handler = qlafx00_intr_handler, 2117 .enable_intrs = qlafx00_enable_intrs, 2118 .disable_intrs = qlafx00_disable_intrs, 2119 .abort_command = qla24xx_async_abort_command, 2120 .target_reset = qlafx00_abort_target, 2121 .lun_reset = qlafx00_lun_reset, 2122 .fabric_login = NULL, 2123 .fabric_logout = NULL, 2124 .calc_req_entries = NULL, 2125 .build_iocbs = NULL, 2126 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2127 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2128 .read_nvram = qla24xx_read_nvram_data, 2129 .write_nvram = qla24xx_write_nvram_data, 2130 .fw_dump = NULL, 2131 .beacon_on = qla24xx_beacon_on, 2132 .beacon_off = qla24xx_beacon_off, 2133 .beacon_blink = NULL, 2134 .read_optrom = qla24xx_read_optrom_data, 2135 .write_optrom = qla24xx_write_optrom_data, 2136 .get_flash_version = qla24xx_get_flash_version, 2137 .start_scsi = qlafx00_start_scsi, 2138 .abort_isp = qlafx00_abort_isp, 2139 .iospace_config = qlafx00_iospace_config, 2140 .initialize_adapter = qlafx00_initialize_adapter, 2141 }; 2142 2143 static struct isp_operations qla27xx_isp_ops = { 2144 .pci_config = qla25xx_pci_config, 2145 .reset_chip = qla24xx_reset_chip, 2146 .chip_diag = qla24xx_chip_diag, 2147 .config_rings = qla24xx_config_rings, 2148 .reset_adapter = qla24xx_reset_adapter, 2149 .nvram_config = qla81xx_nvram_config, 2150 .update_fw_options = qla81xx_update_fw_options, 2151 .load_risc = qla81xx_load_risc, 2152 .pci_info_str = qla24xx_pci_info_str, 2153 .fw_version_str = qla24xx_fw_version_str, 2154 .intr_handler = qla24xx_intr_handler, 2155 .enable_intrs = qla24xx_enable_intrs, 2156 .disable_intrs = qla24xx_disable_intrs, 2157 .abort_command = qla24xx_abort_command, 2158 .target_reset = qla24xx_abort_target, 2159 .lun_reset = qla24xx_lun_reset, 2160 .fabric_login = qla24xx_login_fabric, 2161 .fabric_logout = qla24xx_fabric_logout, 2162 .calc_req_entries = NULL, 2163 .build_iocbs = NULL, 2164 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2165 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2166 .read_nvram = NULL, 2167 .write_nvram = NULL, 2168 .fw_dump = qla27xx_fwdump, 2169 .beacon_on = qla24xx_beacon_on, 2170 .beacon_off = qla24xx_beacon_off, 2171 .beacon_blink = qla83xx_beacon_blink, 2172 .read_optrom = qla25xx_read_optrom_data, 2173 .write_optrom = qla24xx_write_optrom_data, 2174 .get_flash_version = qla24xx_get_flash_version, 2175 .start_scsi = qla24xx_dif_start_scsi, 2176 .abort_isp = qla2x00_abort_isp, 2177 .iospace_config = qla83xx_iospace_config, 2178 .initialize_adapter = qla2x00_initialize_adapter, 2179 }; 2180 2181 static inline void 2182 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2183 { 2184 ha->device_type = DT_EXTENDED_IDS; 2185 switch (ha->pdev->device) { 2186 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2187 ha->isp_type |= DT_ISP2100; 2188 ha->device_type &= ~DT_EXTENDED_IDS; 2189 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2190 break; 2191 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2192 ha->isp_type |= DT_ISP2200; 2193 ha->device_type &= ~DT_EXTENDED_IDS; 2194 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2195 break; 2196 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2197 ha->isp_type |= DT_ISP2300; 2198 ha->device_type |= DT_ZIO_SUPPORTED; 2199 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2200 break; 2201 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2202 ha->isp_type |= DT_ISP2312; 2203 ha->device_type |= DT_ZIO_SUPPORTED; 2204 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2205 break; 2206 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2207 ha->isp_type |= DT_ISP2322; 2208 ha->device_type |= DT_ZIO_SUPPORTED; 2209 if (ha->pdev->subsystem_vendor == 0x1028 && 2210 ha->pdev->subsystem_device == 0x0170) 2211 ha->device_type |= DT_OEM_001; 2212 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2213 break; 2214 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2215 ha->isp_type |= DT_ISP6312; 2216 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2217 break; 2218 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2219 ha->isp_type |= DT_ISP6322; 2220 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2221 break; 2222 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2223 ha->isp_type |= DT_ISP2422; 2224 ha->device_type |= DT_ZIO_SUPPORTED; 2225 ha->device_type |= DT_FWI2; 2226 ha->device_type |= DT_IIDMA; 2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2228 break; 2229 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2230 ha->isp_type |= DT_ISP2432; 2231 ha->device_type |= DT_ZIO_SUPPORTED; 2232 ha->device_type |= DT_FWI2; 2233 ha->device_type |= DT_IIDMA; 2234 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2235 break; 2236 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2237 ha->isp_type |= DT_ISP8432; 2238 ha->device_type |= DT_ZIO_SUPPORTED; 2239 ha->device_type |= DT_FWI2; 2240 ha->device_type |= DT_IIDMA; 2241 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2242 break; 2243 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2244 ha->isp_type |= DT_ISP5422; 2245 ha->device_type |= DT_FWI2; 2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2247 break; 2248 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2249 ha->isp_type |= DT_ISP5432; 2250 ha->device_type |= DT_FWI2; 2251 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2252 break; 2253 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2254 ha->isp_type |= DT_ISP2532; 2255 ha->device_type |= DT_ZIO_SUPPORTED; 2256 ha->device_type |= DT_FWI2; 2257 ha->device_type |= DT_IIDMA; 2258 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2259 break; 2260 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2261 ha->isp_type |= DT_ISP8001; 2262 ha->device_type |= DT_ZIO_SUPPORTED; 2263 ha->device_type |= DT_FWI2; 2264 ha->device_type |= DT_IIDMA; 2265 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2266 break; 2267 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2268 ha->isp_type |= DT_ISP8021; 2269 ha->device_type |= DT_ZIO_SUPPORTED; 2270 ha->device_type |= DT_FWI2; 2271 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2272 /* Initialize 82XX ISP flags */ 2273 qla82xx_init_flags(ha); 2274 break; 2275 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2276 ha->isp_type |= DT_ISP8044; 2277 ha->device_type |= DT_ZIO_SUPPORTED; 2278 ha->device_type |= DT_FWI2; 2279 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2280 /* Initialize 82XX ISP flags */ 2281 qla82xx_init_flags(ha); 2282 break; 2283 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2284 ha->isp_type |= DT_ISP2031; 2285 ha->device_type |= DT_ZIO_SUPPORTED; 2286 ha->device_type |= DT_FWI2; 2287 ha->device_type |= DT_IIDMA; 2288 ha->device_type |= DT_T10_PI; 2289 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2290 break; 2291 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2292 ha->isp_type |= DT_ISP8031; 2293 ha->device_type |= DT_ZIO_SUPPORTED; 2294 ha->device_type |= DT_FWI2; 2295 ha->device_type |= DT_IIDMA; 2296 ha->device_type |= DT_T10_PI; 2297 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2298 break; 2299 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2300 ha->isp_type |= DT_ISPFX00; 2301 break; 2302 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2303 ha->isp_type |= DT_ISP2071; 2304 ha->device_type |= DT_ZIO_SUPPORTED; 2305 ha->device_type |= DT_FWI2; 2306 ha->device_type |= DT_IIDMA; 2307 ha->device_type |= DT_T10_PI; 2308 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2309 break; 2310 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2311 ha->isp_type |= DT_ISP2271; 2312 ha->device_type |= DT_ZIO_SUPPORTED; 2313 ha->device_type |= DT_FWI2; 2314 ha->device_type |= DT_IIDMA; 2315 ha->device_type |= DT_T10_PI; 2316 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2317 break; 2318 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2319 ha->isp_type |= DT_ISP2261; 2320 ha->device_type |= DT_ZIO_SUPPORTED; 2321 ha->device_type |= DT_FWI2; 2322 ha->device_type |= DT_IIDMA; 2323 ha->device_type |= DT_T10_PI; 2324 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2325 break; 2326 } 2327 2328 if (IS_QLA82XX(ha)) 2329 ha->port_no = ha->portnum & 1; 2330 else { 2331 /* Get adapter physical port no from interrupt pin register. */ 2332 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2333 if (IS_QLA27XX(ha)) 2334 ha->port_no--; 2335 else 2336 ha->port_no = !(ha->port_no & 1); 2337 } 2338 2339 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2340 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2341 ha->device_type, ha->port_no, ha->fw_srisc_address); 2342 } 2343 2344 static void 2345 qla2xxx_scan_start(struct Scsi_Host *shost) 2346 { 2347 scsi_qla_host_t *vha = shost_priv(shost); 2348 2349 if (vha->hw->flags.running_gold_fw) 2350 return; 2351 2352 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2353 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2354 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2355 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2356 } 2357 2358 static int 2359 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2360 { 2361 scsi_qla_host_t *vha = shost_priv(shost); 2362 2363 if (test_bit(UNLOADING, &vha->dpc_flags)) 2364 return 1; 2365 if (!vha->host) 2366 return 1; 2367 if (time > vha->hw->loop_reset_delay * HZ) 2368 return 1; 2369 2370 return atomic_read(&vha->loop_state) == LOOP_READY; 2371 } 2372 2373 /* 2374 * PCI driver interface 2375 */ 2376 static int 2377 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2378 { 2379 int ret = -ENODEV; 2380 struct Scsi_Host *host; 2381 scsi_qla_host_t *base_vha = NULL; 2382 struct qla_hw_data *ha; 2383 char pci_info[30]; 2384 char fw_str[30], wq_name[30]; 2385 struct scsi_host_template *sht; 2386 int bars, mem_only = 0; 2387 uint16_t req_length = 0, rsp_length = 0; 2388 struct req_que *req = NULL; 2389 struct rsp_que *rsp = NULL; 2390 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2391 sht = &qla2xxx_driver_template; 2392 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2393 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2394 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2395 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2396 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2397 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2398 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2399 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2400 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2401 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2402 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2403 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2404 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2405 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2406 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2407 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2408 mem_only = 1; 2409 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2410 "Mem only adapter.\n"); 2411 } 2412 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2413 "Bars=%d.\n", bars); 2414 2415 if (mem_only) { 2416 if (pci_enable_device_mem(pdev)) 2417 goto probe_out; 2418 } else { 2419 if (pci_enable_device(pdev)) 2420 goto probe_out; 2421 } 2422 2423 /* This may fail but that's ok */ 2424 pci_enable_pcie_error_reporting(pdev); 2425 2426 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2427 if (!ha) { 2428 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2429 "Unable to allocate memory for ha.\n"); 2430 goto probe_out; 2431 } 2432 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2433 "Memory allocated for ha=%p.\n", ha); 2434 ha->pdev = pdev; 2435 ha->tgt.enable_class_2 = ql2xenableclass2; 2436 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2437 spin_lock_init(&ha->tgt.q_full_lock); 2438 spin_lock_init(&ha->tgt.sess_lock); 2439 spin_lock_init(&ha->tgt.atio_lock); 2440 2441 2442 /* Clear our data area */ 2443 ha->bars = bars; 2444 ha->mem_only = mem_only; 2445 spin_lock_init(&ha->hardware_lock); 2446 spin_lock_init(&ha->vport_slock); 2447 mutex_init(&ha->selflogin_lock); 2448 mutex_init(&ha->optrom_mutex); 2449 2450 /* Set ISP-type information. */ 2451 qla2x00_set_isp_flags(ha); 2452 2453 /* Set EEH reset type to fundamental if required by hba */ 2454 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2455 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2456 pdev->needs_freset = 1; 2457 2458 ha->prev_topology = 0; 2459 ha->init_cb_size = sizeof(init_cb_t); 2460 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2461 ha->optrom_size = OPTROM_SIZE_2300; 2462 2463 /* Assign ISP specific operations. */ 2464 if (IS_QLA2100(ha)) { 2465 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2466 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2467 req_length = REQUEST_ENTRY_CNT_2100; 2468 rsp_length = RESPONSE_ENTRY_CNT_2100; 2469 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2470 ha->gid_list_info_size = 4; 2471 ha->flash_conf_off = ~0; 2472 ha->flash_data_off = ~0; 2473 ha->nvram_conf_off = ~0; 2474 ha->nvram_data_off = ~0; 2475 ha->isp_ops = &qla2100_isp_ops; 2476 } else if (IS_QLA2200(ha)) { 2477 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2478 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2479 req_length = REQUEST_ENTRY_CNT_2200; 2480 rsp_length = RESPONSE_ENTRY_CNT_2100; 2481 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2482 ha->gid_list_info_size = 4; 2483 ha->flash_conf_off = ~0; 2484 ha->flash_data_off = ~0; 2485 ha->nvram_conf_off = ~0; 2486 ha->nvram_data_off = ~0; 2487 ha->isp_ops = &qla2100_isp_ops; 2488 } else if (IS_QLA23XX(ha)) { 2489 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2490 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2491 req_length = REQUEST_ENTRY_CNT_2200; 2492 rsp_length = RESPONSE_ENTRY_CNT_2300; 2493 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2494 ha->gid_list_info_size = 6; 2495 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2496 ha->optrom_size = OPTROM_SIZE_2322; 2497 ha->flash_conf_off = ~0; 2498 ha->flash_data_off = ~0; 2499 ha->nvram_conf_off = ~0; 2500 ha->nvram_data_off = ~0; 2501 ha->isp_ops = &qla2300_isp_ops; 2502 } else if (IS_QLA24XX_TYPE(ha)) { 2503 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2504 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2505 req_length = REQUEST_ENTRY_CNT_24XX; 2506 rsp_length = RESPONSE_ENTRY_CNT_2300; 2507 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2508 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2509 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2510 ha->gid_list_info_size = 8; 2511 ha->optrom_size = OPTROM_SIZE_24XX; 2512 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2513 ha->isp_ops = &qla24xx_isp_ops; 2514 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2515 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2516 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2517 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2518 } else if (IS_QLA25XX(ha)) { 2519 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2520 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2521 req_length = REQUEST_ENTRY_CNT_24XX; 2522 rsp_length = RESPONSE_ENTRY_CNT_2300; 2523 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2524 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2525 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2526 ha->gid_list_info_size = 8; 2527 ha->optrom_size = OPTROM_SIZE_25XX; 2528 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2529 ha->isp_ops = &qla25xx_isp_ops; 2530 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2531 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2532 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2533 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2534 } else if (IS_QLA81XX(ha)) { 2535 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2536 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2537 req_length = REQUEST_ENTRY_CNT_24XX; 2538 rsp_length = RESPONSE_ENTRY_CNT_2300; 2539 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2540 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2541 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2542 ha->gid_list_info_size = 8; 2543 ha->optrom_size = OPTROM_SIZE_81XX; 2544 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2545 ha->isp_ops = &qla81xx_isp_ops; 2546 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2547 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2548 ha->nvram_conf_off = ~0; 2549 ha->nvram_data_off = ~0; 2550 } else if (IS_QLA82XX(ha)) { 2551 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2552 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2553 req_length = REQUEST_ENTRY_CNT_82XX; 2554 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2555 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2556 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2557 ha->gid_list_info_size = 8; 2558 ha->optrom_size = OPTROM_SIZE_82XX; 2559 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2560 ha->isp_ops = &qla82xx_isp_ops; 2561 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2562 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2563 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2564 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2565 } else if (IS_QLA8044(ha)) { 2566 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2567 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2568 req_length = REQUEST_ENTRY_CNT_82XX; 2569 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2570 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2571 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2572 ha->gid_list_info_size = 8; 2573 ha->optrom_size = OPTROM_SIZE_83XX; 2574 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2575 ha->isp_ops = &qla8044_isp_ops; 2576 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2577 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2578 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2579 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2580 } else if (IS_QLA83XX(ha)) { 2581 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2582 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2583 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2584 req_length = REQUEST_ENTRY_CNT_83XX; 2585 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2586 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2587 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2588 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2589 ha->gid_list_info_size = 8; 2590 ha->optrom_size = OPTROM_SIZE_83XX; 2591 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2592 ha->isp_ops = &qla83xx_isp_ops; 2593 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2594 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2595 ha->nvram_conf_off = ~0; 2596 ha->nvram_data_off = ~0; 2597 } else if (IS_QLAFX00(ha)) { 2598 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2599 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2600 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2601 req_length = REQUEST_ENTRY_CNT_FX00; 2602 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2603 ha->isp_ops = &qlafx00_isp_ops; 2604 ha->port_down_retry_count = 30; /* default value */ 2605 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2606 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2607 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2608 ha->mr.fw_hbt_en = 1; 2609 ha->mr.host_info_resend = false; 2610 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2611 } else if (IS_QLA27XX(ha)) { 2612 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2613 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2614 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2615 req_length = REQUEST_ENTRY_CNT_83XX; 2616 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2617 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2618 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2619 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2620 ha->gid_list_info_size = 8; 2621 ha->optrom_size = OPTROM_SIZE_83XX; 2622 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2623 ha->isp_ops = &qla27xx_isp_ops; 2624 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2625 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2626 ha->nvram_conf_off = ~0; 2627 ha->nvram_data_off = ~0; 2628 } 2629 2630 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2631 "mbx_count=%d, req_length=%d, " 2632 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2633 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2634 "max_fibre_devices=%d.\n", 2635 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2636 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2637 ha->nvram_npiv_size, ha->max_fibre_devices); 2638 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2639 "isp_ops=%p, flash_conf_off=%d, " 2640 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2641 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2642 ha->nvram_conf_off, ha->nvram_data_off); 2643 2644 /* Configure PCI I/O space */ 2645 ret = ha->isp_ops->iospace_config(ha); 2646 if (ret) 2647 goto iospace_config_failed; 2648 2649 ql_log_pci(ql_log_info, pdev, 0x001d, 2650 "Found an ISP%04X irq %d iobase 0x%p.\n", 2651 pdev->device, pdev->irq, ha->iobase); 2652 mutex_init(&ha->vport_lock); 2653 init_completion(&ha->mbx_cmd_comp); 2654 complete(&ha->mbx_cmd_comp); 2655 init_completion(&ha->mbx_intr_comp); 2656 init_completion(&ha->dcbx_comp); 2657 init_completion(&ha->lb_portup_comp); 2658 2659 set_bit(0, (unsigned long *) ha->vp_idx_map); 2660 2661 qla2x00_config_dma_addressing(ha); 2662 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2663 "64 Bit addressing is %s.\n", 2664 ha->flags.enable_64bit_addressing ? "enable" : 2665 "disable"); 2666 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2667 if (ret) { 2668 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2669 "Failed to allocate memory for adapter, aborting.\n"); 2670 2671 goto probe_hw_failed; 2672 } 2673 2674 req->max_q_depth = MAX_Q_DEPTH; 2675 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2676 req->max_q_depth = ql2xmaxqdepth; 2677 2678 2679 base_vha = qla2x00_create_host(sht, ha); 2680 if (!base_vha) { 2681 ret = -ENOMEM; 2682 qla2x00_mem_free(ha); 2683 qla2x00_free_req_que(ha, req); 2684 qla2x00_free_rsp_que(ha, rsp); 2685 goto probe_hw_failed; 2686 } 2687 2688 pci_set_drvdata(pdev, base_vha); 2689 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2690 2691 host = base_vha->host; 2692 base_vha->req = req; 2693 if (IS_QLA2XXX_MIDTYPE(ha)) 2694 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2695 else 2696 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2697 base_vha->vp_idx; 2698 2699 /* Setup fcport template structure. */ 2700 ha->mr.fcport.vha = base_vha; 2701 ha->mr.fcport.port_type = FCT_UNKNOWN; 2702 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2703 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2704 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2705 ha->mr.fcport.scan_state = 1; 2706 2707 /* Set the SG table size based on ISP type */ 2708 if (!IS_FWI2_CAPABLE(ha)) { 2709 if (IS_QLA2100(ha)) 2710 host->sg_tablesize = 32; 2711 } else { 2712 if (!IS_QLA82XX(ha)) 2713 host->sg_tablesize = QLA_SG_ALL; 2714 } 2715 host->max_id = ha->max_fibre_devices; 2716 host->cmd_per_lun = 3; 2717 host->unique_id = host->host_no; 2718 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2719 host->max_cmd_len = 32; 2720 else 2721 host->max_cmd_len = MAX_CMDSZ; 2722 host->max_channel = MAX_BUSES - 1; 2723 /* Older HBAs support only 16-bit LUNs */ 2724 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2725 ql2xmaxlun > 0xffff) 2726 host->max_lun = 0xffff; 2727 else 2728 host->max_lun = ql2xmaxlun; 2729 host->transportt = qla2xxx_transport_template; 2730 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2731 2732 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2733 "max_id=%d this_id=%d " 2734 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2735 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2736 host->this_id, host->cmd_per_lun, host->unique_id, 2737 host->max_cmd_len, host->max_channel, host->max_lun, 2738 host->transportt, sht->vendor_id); 2739 2740 que_init: 2741 /* Alloc arrays of request and response ring ptrs */ 2742 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2743 ql_log(ql_log_fatal, base_vha, 0x003d, 2744 "Failed to allocate memory for queue pointers..." 2745 "aborting.\n"); 2746 goto probe_init_failed; 2747 } 2748 2749 qlt_probe_one_stage1(base_vha, ha); 2750 2751 /* Set up the irqs */ 2752 ret = qla2x00_request_irqs(ha, rsp); 2753 if (ret) 2754 goto probe_init_failed; 2755 2756 pci_save_state(pdev); 2757 2758 /* Assign back pointers */ 2759 rsp->req = req; 2760 req->rsp = rsp; 2761 2762 if (IS_QLAFX00(ha)) { 2763 ha->rsp_q_map[0] = rsp; 2764 ha->req_q_map[0] = req; 2765 set_bit(0, ha->req_qid_map); 2766 set_bit(0, ha->rsp_qid_map); 2767 } 2768 2769 /* FWI2-capable only. */ 2770 req->req_q_in = &ha->iobase->isp24.req_q_in; 2771 req->req_q_out = &ha->iobase->isp24.req_q_out; 2772 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2773 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2774 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2775 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2776 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2777 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2778 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2779 } 2780 2781 if (IS_QLAFX00(ha)) { 2782 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2783 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2784 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2785 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2786 } 2787 2788 if (IS_P3P_TYPE(ha)) { 2789 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2790 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2791 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2792 } 2793 2794 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2795 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2796 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2797 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2798 "req->req_q_in=%p req->req_q_out=%p " 2799 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2800 req->req_q_in, req->req_q_out, 2801 rsp->rsp_q_in, rsp->rsp_q_out); 2802 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2803 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2804 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2805 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2806 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2807 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2808 2809 if (ha->isp_ops->initialize_adapter(base_vha)) { 2810 ql_log(ql_log_fatal, base_vha, 0x00d6, 2811 "Failed to initialize adapter - Adapter flags %x.\n", 2812 base_vha->device_flags); 2813 2814 if (IS_QLA82XX(ha)) { 2815 qla82xx_idc_lock(ha); 2816 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2817 QLA8XXX_DEV_FAILED); 2818 qla82xx_idc_unlock(ha); 2819 ql_log(ql_log_fatal, base_vha, 0x00d7, 2820 "HW State: FAILED.\n"); 2821 } else if (IS_QLA8044(ha)) { 2822 qla8044_idc_lock(ha); 2823 qla8044_wr_direct(base_vha, 2824 QLA8044_CRB_DEV_STATE_INDEX, 2825 QLA8XXX_DEV_FAILED); 2826 qla8044_idc_unlock(ha); 2827 ql_log(ql_log_fatal, base_vha, 0x0150, 2828 "HW State: FAILED.\n"); 2829 } 2830 2831 ret = -ENODEV; 2832 goto probe_failed; 2833 } 2834 2835 if (IS_QLAFX00(ha)) 2836 host->can_queue = QLAFX00_MAX_CANQUEUE; 2837 else 2838 host->can_queue = req->num_outstanding_cmds - 10; 2839 2840 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2841 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2842 host->can_queue, base_vha->req, 2843 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2844 2845 if (ha->mqenable) { 2846 if (qla25xx_setup_mode(base_vha)) { 2847 ql_log(ql_log_warn, base_vha, 0x00ec, 2848 "Failed to create queues, falling back to single queue mode.\n"); 2849 goto que_init; 2850 } 2851 } 2852 2853 if (ha->flags.running_gold_fw) 2854 goto skip_dpc; 2855 2856 /* 2857 * Startup the kernel thread for this host adapter 2858 */ 2859 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2860 "%s_dpc", base_vha->host_str); 2861 if (IS_ERR(ha->dpc_thread)) { 2862 ql_log(ql_log_fatal, base_vha, 0x00ed, 2863 "Failed to start DPC thread.\n"); 2864 ret = PTR_ERR(ha->dpc_thread); 2865 goto probe_failed; 2866 } 2867 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2868 "DPC thread started successfully.\n"); 2869 2870 /* 2871 * If we're not coming up in initiator mode, we might sit for 2872 * a while without waking up the dpc thread, which leads to a 2873 * stuck process warning. So just kick the dpc once here and 2874 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2875 */ 2876 qla2xxx_wake_dpc(base_vha); 2877 2878 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2879 2880 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2881 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2882 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2883 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2884 2885 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2886 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2887 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2888 INIT_WORK(&ha->idc_state_handler, 2889 qla83xx_idc_state_handler_work); 2890 INIT_WORK(&ha->nic_core_unrecoverable, 2891 qla83xx_nic_core_unrecoverable_work); 2892 } 2893 2894 skip_dpc: 2895 list_add_tail(&base_vha->list, &ha->vp_list); 2896 base_vha->host->irq = ha->pdev->irq; 2897 2898 /* Initialized the timer */ 2899 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2900 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2901 "Started qla2x00_timer with " 2902 "interval=%d.\n", WATCH_INTERVAL); 2903 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2904 "Detected hba at address=%p.\n", 2905 ha); 2906 2907 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2908 if (ha->fw_attributes & BIT_4) { 2909 int prot = 0, guard; 2910 base_vha->flags.difdix_supported = 1; 2911 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2912 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2913 if (ql2xenabledif == 1) 2914 prot = SHOST_DIX_TYPE0_PROTECTION; 2915 scsi_host_set_prot(host, 2916 prot | SHOST_DIF_TYPE1_PROTECTION 2917 | SHOST_DIF_TYPE2_PROTECTION 2918 | SHOST_DIF_TYPE3_PROTECTION 2919 | SHOST_DIX_TYPE1_PROTECTION 2920 | SHOST_DIX_TYPE2_PROTECTION 2921 | SHOST_DIX_TYPE3_PROTECTION); 2922 2923 guard = SHOST_DIX_GUARD_CRC; 2924 2925 if (IS_PI_IPGUARD_CAPABLE(ha) && 2926 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2927 guard |= SHOST_DIX_GUARD_IP; 2928 2929 scsi_host_set_guard(host, guard); 2930 } else 2931 base_vha->flags.difdix_supported = 0; 2932 } 2933 2934 ha->isp_ops->enable_intrs(ha); 2935 2936 if (IS_QLAFX00(ha)) { 2937 ret = qlafx00_fx_disc(base_vha, 2938 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2939 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2940 QLA_SG_ALL : 128; 2941 } 2942 2943 ret = scsi_add_host(host, &pdev->dev); 2944 if (ret) 2945 goto probe_failed; 2946 2947 base_vha->flags.init_done = 1; 2948 base_vha->flags.online = 1; 2949 ha->prev_minidump_failed = 0; 2950 2951 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2952 "Init done and hba is online.\n"); 2953 2954 if (qla_ini_mode_enabled(base_vha)) 2955 scsi_scan_host(host); 2956 else 2957 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2958 "skipping scsi_scan_host() for non-initiator port\n"); 2959 2960 qla2x00_alloc_sysfs_attr(base_vha); 2961 2962 if (IS_QLAFX00(ha)) { 2963 ret = qlafx00_fx_disc(base_vha, 2964 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2965 2966 /* Register system information */ 2967 ret = qlafx00_fx_disc(base_vha, 2968 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2969 } 2970 2971 qla2x00_init_host_attr(base_vha); 2972 2973 qla2x00_dfs_setup(base_vha); 2974 2975 ql_log(ql_log_info, base_vha, 0x00fb, 2976 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2977 ql_log(ql_log_info, base_vha, 0x00fc, 2978 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2979 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2980 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2981 base_vha->host_no, 2982 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2983 2984 qlt_add_target(ha, base_vha); 2985 2986 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2987 2988 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2989 return -ENODEV; 2990 2991 return 0; 2992 2993 probe_init_failed: 2994 qla2x00_free_req_que(ha, req); 2995 ha->req_q_map[0] = NULL; 2996 clear_bit(0, ha->req_qid_map); 2997 qla2x00_free_rsp_que(ha, rsp); 2998 ha->rsp_q_map[0] = NULL; 2999 clear_bit(0, ha->rsp_qid_map); 3000 ha->max_req_queues = ha->max_rsp_queues = 0; 3001 3002 probe_failed: 3003 if (base_vha->timer_active) 3004 qla2x00_stop_timer(base_vha); 3005 base_vha->flags.online = 0; 3006 if (ha->dpc_thread) { 3007 struct task_struct *t = ha->dpc_thread; 3008 3009 ha->dpc_thread = NULL; 3010 kthread_stop(t); 3011 } 3012 3013 qla2x00_free_device(base_vha); 3014 3015 scsi_host_put(base_vha->host); 3016 3017 probe_hw_failed: 3018 qla2x00_clear_drv_active(ha); 3019 3020 iospace_config_failed: 3021 if (IS_P3P_TYPE(ha)) { 3022 if (!ha->nx_pcibase) 3023 iounmap((device_reg_t *)ha->nx_pcibase); 3024 if (!ql2xdbwr) 3025 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3026 } else { 3027 if (ha->iobase) 3028 iounmap(ha->iobase); 3029 if (ha->cregbase) 3030 iounmap(ha->cregbase); 3031 } 3032 pci_release_selected_regions(ha->pdev, ha->bars); 3033 kfree(ha); 3034 ha = NULL; 3035 3036 probe_out: 3037 pci_disable_device(pdev); 3038 return ret; 3039 } 3040 3041 static void 3042 qla2x00_shutdown(struct pci_dev *pdev) 3043 { 3044 scsi_qla_host_t *vha; 3045 struct qla_hw_data *ha; 3046 3047 if (!atomic_read(&pdev->enable_cnt)) 3048 return; 3049 3050 vha = pci_get_drvdata(pdev); 3051 ha = vha->hw; 3052 3053 /* Notify ISPFX00 firmware */ 3054 if (IS_QLAFX00(ha)) 3055 qlafx00_driver_shutdown(vha, 20); 3056 3057 /* Turn-off FCE trace */ 3058 if (ha->flags.fce_enabled) { 3059 qla2x00_disable_fce_trace(vha, NULL, NULL); 3060 ha->flags.fce_enabled = 0; 3061 } 3062 3063 /* Turn-off EFT trace */ 3064 if (ha->eft) 3065 qla2x00_disable_eft_trace(vha); 3066 3067 /* Stop currently executing firmware. */ 3068 qla2x00_try_to_stop_firmware(vha); 3069 3070 /* Turn adapter off line */ 3071 vha->flags.online = 0; 3072 3073 /* turn-off interrupts on the card */ 3074 if (ha->interrupts_on) { 3075 vha->flags.init_done = 0; 3076 ha->isp_ops->disable_intrs(ha); 3077 } 3078 3079 qla2x00_free_irqs(vha); 3080 3081 qla2x00_free_fw_dump(ha); 3082 3083 pci_disable_pcie_error_reporting(pdev); 3084 pci_disable_device(pdev); 3085 } 3086 3087 /* Deletes all the virtual ports for a given ha */ 3088 static void 3089 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3090 { 3091 scsi_qla_host_t *vha; 3092 unsigned long flags; 3093 3094 mutex_lock(&ha->vport_lock); 3095 while (ha->cur_vport_count) { 3096 spin_lock_irqsave(&ha->vport_slock, flags); 3097 3098 BUG_ON(base_vha->list.next == &ha->vp_list); 3099 /* This assumes first entry in ha->vp_list is always base vha */ 3100 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3101 scsi_host_get(vha->host); 3102 3103 spin_unlock_irqrestore(&ha->vport_slock, flags); 3104 mutex_unlock(&ha->vport_lock); 3105 3106 fc_vport_terminate(vha->fc_vport); 3107 scsi_host_put(vha->host); 3108 3109 mutex_lock(&ha->vport_lock); 3110 } 3111 mutex_unlock(&ha->vport_lock); 3112 } 3113 3114 /* Stops all deferred work threads */ 3115 static void 3116 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3117 { 3118 /* Flush the work queue and remove it */ 3119 if (ha->wq) { 3120 flush_workqueue(ha->wq); 3121 destroy_workqueue(ha->wq); 3122 ha->wq = NULL; 3123 } 3124 3125 /* Cancel all work and destroy DPC workqueues */ 3126 if (ha->dpc_lp_wq) { 3127 cancel_work_sync(&ha->idc_aen); 3128 destroy_workqueue(ha->dpc_lp_wq); 3129 ha->dpc_lp_wq = NULL; 3130 } 3131 3132 if (ha->dpc_hp_wq) { 3133 cancel_work_sync(&ha->nic_core_reset); 3134 cancel_work_sync(&ha->idc_state_handler); 3135 cancel_work_sync(&ha->nic_core_unrecoverable); 3136 destroy_workqueue(ha->dpc_hp_wq); 3137 ha->dpc_hp_wq = NULL; 3138 } 3139 3140 /* Kill the kernel thread for this host */ 3141 if (ha->dpc_thread) { 3142 struct task_struct *t = ha->dpc_thread; 3143 3144 /* 3145 * qla2xxx_wake_dpc checks for ->dpc_thread 3146 * so we need to zero it out. 3147 */ 3148 ha->dpc_thread = NULL; 3149 kthread_stop(t); 3150 } 3151 } 3152 3153 static void 3154 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3155 { 3156 if (IS_QLA82XX(ha)) { 3157 3158 iounmap((device_reg_t *)ha->nx_pcibase); 3159 if (!ql2xdbwr) 3160 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3161 } else { 3162 if (ha->iobase) 3163 iounmap(ha->iobase); 3164 3165 if (ha->cregbase) 3166 iounmap(ha->cregbase); 3167 3168 if (ha->mqiobase) 3169 iounmap(ha->mqiobase); 3170 3171 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3172 iounmap(ha->msixbase); 3173 } 3174 } 3175 3176 static void 3177 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3178 { 3179 if (IS_QLA8044(ha)) { 3180 qla8044_idc_lock(ha); 3181 qla8044_clear_drv_active(ha); 3182 qla8044_idc_unlock(ha); 3183 } else if (IS_QLA82XX(ha)) { 3184 qla82xx_idc_lock(ha); 3185 qla82xx_clear_drv_active(ha); 3186 qla82xx_idc_unlock(ha); 3187 } 3188 } 3189 3190 static void 3191 qla2x00_remove_one(struct pci_dev *pdev) 3192 { 3193 scsi_qla_host_t *base_vha; 3194 struct qla_hw_data *ha; 3195 3196 base_vha = pci_get_drvdata(pdev); 3197 ha = base_vha->hw; 3198 3199 /* Indicate device removal to prevent future board_disable and wait 3200 * until any pending board_disable has completed. */ 3201 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3202 cancel_work_sync(&ha->board_disable); 3203 3204 /* 3205 * If the PCI device is disabled then there was a PCI-disconnect and 3206 * qla2x00_disable_board_on_pci_error has taken care of most of the 3207 * resources. 3208 */ 3209 if (!atomic_read(&pdev->enable_cnt)) { 3210 scsi_host_put(base_vha->host); 3211 kfree(ha); 3212 pci_set_drvdata(pdev, NULL); 3213 return; 3214 } 3215 3216 qla2x00_wait_for_hba_ready(base_vha); 3217 3218 /* if UNLOAD flag is already set, then continue unload, 3219 * where it was set first. 3220 */ 3221 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3222 return; 3223 3224 set_bit(UNLOADING, &base_vha->dpc_flags); 3225 3226 if (IS_QLAFX00(ha)) 3227 qlafx00_driver_shutdown(base_vha, 20); 3228 3229 qla2x00_delete_all_vps(ha, base_vha); 3230 3231 if (IS_QLA8031(ha)) { 3232 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3233 "Clearing fcoe driver presence.\n"); 3234 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3235 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3236 "Error while clearing DRV-Presence.\n"); 3237 } 3238 3239 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3240 3241 qla2x00_dfs_remove(base_vha); 3242 3243 qla84xx_put_chip(base_vha); 3244 3245 /* Laser should be disabled only for ISP2031 */ 3246 if (IS_QLA2031(ha)) 3247 qla83xx_disable_laser(base_vha); 3248 3249 /* Disable timer */ 3250 if (base_vha->timer_active) 3251 qla2x00_stop_timer(base_vha); 3252 3253 base_vha->flags.online = 0; 3254 3255 /* free DMA memory */ 3256 if (ha->exlogin_buf) 3257 qla2x00_free_exlogin_buffer(ha); 3258 3259 /* free DMA memory */ 3260 if (ha->exchoffld_buf) 3261 qla2x00_free_exchoffld_buffer(ha); 3262 3263 qla2x00_destroy_deferred_work(ha); 3264 3265 qlt_remove_target(ha, base_vha); 3266 3267 qla2x00_free_sysfs_attr(base_vha, true); 3268 3269 fc_remove_host(base_vha->host); 3270 3271 scsi_remove_host(base_vha->host); 3272 3273 qla2x00_free_device(base_vha); 3274 3275 qla2x00_clear_drv_active(ha); 3276 3277 scsi_host_put(base_vha->host); 3278 3279 qla2x00_unmap_iobases(ha); 3280 3281 pci_release_selected_regions(ha->pdev, ha->bars); 3282 kfree(ha); 3283 ha = NULL; 3284 3285 pci_disable_pcie_error_reporting(pdev); 3286 3287 pci_disable_device(pdev); 3288 } 3289 3290 static void 3291 qla2x00_free_device(scsi_qla_host_t *vha) 3292 { 3293 struct qla_hw_data *ha = vha->hw; 3294 3295 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3296 3297 /* Disable timer */ 3298 if (vha->timer_active) 3299 qla2x00_stop_timer(vha); 3300 3301 qla25xx_delete_queues(vha); 3302 3303 if (ha->flags.fce_enabled) 3304 qla2x00_disable_fce_trace(vha, NULL, NULL); 3305 3306 if (ha->eft) 3307 qla2x00_disable_eft_trace(vha); 3308 3309 /* Stop currently executing firmware. */ 3310 qla2x00_try_to_stop_firmware(vha); 3311 3312 vha->flags.online = 0; 3313 3314 /* turn-off interrupts on the card */ 3315 if (ha->interrupts_on) { 3316 vha->flags.init_done = 0; 3317 ha->isp_ops->disable_intrs(ha); 3318 } 3319 3320 qla2x00_free_irqs(vha); 3321 3322 qla2x00_free_fcports(vha); 3323 3324 qla2x00_mem_free(ha); 3325 3326 qla82xx_md_free(vha); 3327 3328 qla2x00_free_queues(ha); 3329 } 3330 3331 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3332 { 3333 fc_port_t *fcport, *tfcport; 3334 3335 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3336 list_del(&fcport->list); 3337 qla2x00_clear_loop_id(fcport); 3338 kfree(fcport); 3339 fcport = NULL; 3340 } 3341 } 3342 3343 static inline void 3344 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3345 int defer) 3346 { 3347 struct fc_rport *rport; 3348 scsi_qla_host_t *base_vha; 3349 unsigned long flags; 3350 3351 if (!fcport->rport) 3352 return; 3353 3354 rport = fcport->rport; 3355 if (defer) { 3356 base_vha = pci_get_drvdata(vha->hw->pdev); 3357 spin_lock_irqsave(vha->host->host_lock, flags); 3358 fcport->drport = rport; 3359 spin_unlock_irqrestore(vha->host->host_lock, flags); 3360 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3361 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3362 qla2xxx_wake_dpc(base_vha); 3363 } else { 3364 int now; 3365 if (rport) 3366 fc_remote_port_delete(rport); 3367 qlt_do_generation_tick(vha, &now); 3368 qlt_fc_port_deleted(vha, fcport, now); 3369 } 3370 } 3371 3372 /* 3373 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3374 * 3375 * Input: ha = adapter block pointer. fcport = port structure pointer. 3376 * 3377 * Return: None. 3378 * 3379 * Context: 3380 */ 3381 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3382 int do_login, int defer) 3383 { 3384 if (IS_QLAFX00(vha->hw)) { 3385 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3386 qla2x00_schedule_rport_del(vha, fcport, defer); 3387 return; 3388 } 3389 3390 if (atomic_read(&fcport->state) == FCS_ONLINE && 3391 vha->vp_idx == fcport->vha->vp_idx) { 3392 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3393 qla2x00_schedule_rport_del(vha, fcport, defer); 3394 } 3395 /* 3396 * We may need to retry the login, so don't change the state of the 3397 * port but do the retries. 3398 */ 3399 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3400 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3401 3402 if (!do_login) 3403 return; 3404 3405 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3406 3407 if (fcport->login_retry == 0) { 3408 fcport->login_retry = vha->hw->login_retry_count; 3409 3410 ql_dbg(ql_dbg_disc, vha, 0x2067, 3411 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3412 fcport->port_name, fcport->loop_id, fcport->login_retry); 3413 } 3414 } 3415 3416 /* 3417 * qla2x00_mark_all_devices_lost 3418 * Updates fcport state when device goes offline. 3419 * 3420 * Input: 3421 * ha = adapter block pointer. 3422 * fcport = port structure pointer. 3423 * 3424 * Return: 3425 * None. 3426 * 3427 * Context: 3428 */ 3429 void 3430 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3431 { 3432 fc_port_t *fcport; 3433 3434 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3435 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3436 continue; 3437 3438 /* 3439 * No point in marking the device as lost, if the device is 3440 * already DEAD. 3441 */ 3442 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3443 continue; 3444 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3445 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3446 if (defer) 3447 qla2x00_schedule_rport_del(vha, fcport, defer); 3448 else if (vha->vp_idx == fcport->vha->vp_idx) 3449 qla2x00_schedule_rport_del(vha, fcport, defer); 3450 } 3451 } 3452 } 3453 3454 /* 3455 * qla2x00_mem_alloc 3456 * Allocates adapter memory. 3457 * 3458 * Returns: 3459 * 0 = success. 3460 * !0 = failure. 3461 */ 3462 static int 3463 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3464 struct req_que **req, struct rsp_que **rsp) 3465 { 3466 char name[16]; 3467 3468 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3469 &ha->init_cb_dma, GFP_KERNEL); 3470 if (!ha->init_cb) 3471 goto fail; 3472 3473 if (qlt_mem_alloc(ha) < 0) 3474 goto fail_free_init_cb; 3475 3476 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3477 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3478 if (!ha->gid_list) 3479 goto fail_free_tgt_mem; 3480 3481 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3482 if (!ha->srb_mempool) 3483 goto fail_free_gid_list; 3484 3485 if (IS_P3P_TYPE(ha)) { 3486 /* Allocate cache for CT6 Ctx. */ 3487 if (!ctx_cachep) { 3488 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3489 sizeof(struct ct6_dsd), 0, 3490 SLAB_HWCACHE_ALIGN, NULL); 3491 if (!ctx_cachep) 3492 goto fail_free_gid_list; 3493 } 3494 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3495 ctx_cachep); 3496 if (!ha->ctx_mempool) 3497 goto fail_free_srb_mempool; 3498 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3499 "ctx_cachep=%p ctx_mempool=%p.\n", 3500 ctx_cachep, ha->ctx_mempool); 3501 } 3502 3503 /* Get memory for cached NVRAM */ 3504 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3505 if (!ha->nvram) 3506 goto fail_free_ctx_mempool; 3507 3508 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3509 ha->pdev->device); 3510 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3511 DMA_POOL_SIZE, 8, 0); 3512 if (!ha->s_dma_pool) 3513 goto fail_free_nvram; 3514 3515 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3516 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3517 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3518 3519 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3520 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3521 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3522 if (!ha->dl_dma_pool) { 3523 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3524 "Failed to allocate memory for dl_dma_pool.\n"); 3525 goto fail_s_dma_pool; 3526 } 3527 3528 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3529 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3530 if (!ha->fcp_cmnd_dma_pool) { 3531 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3532 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3533 goto fail_dl_dma_pool; 3534 } 3535 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3536 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3537 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3538 } 3539 3540 /* Allocate memory for SNS commands */ 3541 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3542 /* Get consistent memory allocated for SNS commands */ 3543 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3544 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3545 if (!ha->sns_cmd) 3546 goto fail_dma_pool; 3547 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3548 "sns_cmd: %p.\n", ha->sns_cmd); 3549 } else { 3550 /* Get consistent memory allocated for MS IOCB */ 3551 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3552 &ha->ms_iocb_dma); 3553 if (!ha->ms_iocb) 3554 goto fail_dma_pool; 3555 /* Get consistent memory allocated for CT SNS commands */ 3556 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3557 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3558 if (!ha->ct_sns) 3559 goto fail_free_ms_iocb; 3560 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3561 "ms_iocb=%p ct_sns=%p.\n", 3562 ha->ms_iocb, ha->ct_sns); 3563 } 3564 3565 /* Allocate memory for request ring */ 3566 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3567 if (!*req) { 3568 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3569 "Failed to allocate memory for req.\n"); 3570 goto fail_req; 3571 } 3572 (*req)->length = req_len; 3573 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3574 ((*req)->length + 1) * sizeof(request_t), 3575 &(*req)->dma, GFP_KERNEL); 3576 if (!(*req)->ring) { 3577 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3578 "Failed to allocate memory for req_ring.\n"); 3579 goto fail_req_ring; 3580 } 3581 /* Allocate memory for response ring */ 3582 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3583 if (!*rsp) { 3584 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3585 "Failed to allocate memory for rsp.\n"); 3586 goto fail_rsp; 3587 } 3588 (*rsp)->hw = ha; 3589 (*rsp)->length = rsp_len; 3590 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3591 ((*rsp)->length + 1) * sizeof(response_t), 3592 &(*rsp)->dma, GFP_KERNEL); 3593 if (!(*rsp)->ring) { 3594 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3595 "Failed to allocate memory for rsp_ring.\n"); 3596 goto fail_rsp_ring; 3597 } 3598 (*req)->rsp = *rsp; 3599 (*rsp)->req = *req; 3600 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3601 "req=%p req->length=%d req->ring=%p rsp=%p " 3602 "rsp->length=%d rsp->ring=%p.\n", 3603 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3604 (*rsp)->ring); 3605 /* Allocate memory for NVRAM data for vports */ 3606 if (ha->nvram_npiv_size) { 3607 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3608 ha->nvram_npiv_size, GFP_KERNEL); 3609 if (!ha->npiv_info) { 3610 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3611 "Failed to allocate memory for npiv_info.\n"); 3612 goto fail_npiv_info; 3613 } 3614 } else 3615 ha->npiv_info = NULL; 3616 3617 /* Get consistent memory allocated for EX-INIT-CB. */ 3618 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3619 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3620 &ha->ex_init_cb_dma); 3621 if (!ha->ex_init_cb) 3622 goto fail_ex_init_cb; 3623 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3624 "ex_init_cb=%p.\n", ha->ex_init_cb); 3625 } 3626 3627 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3628 3629 /* Get consistent memory allocated for Async Port-Database. */ 3630 if (!IS_FWI2_CAPABLE(ha)) { 3631 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3632 &ha->async_pd_dma); 3633 if (!ha->async_pd) 3634 goto fail_async_pd; 3635 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3636 "async_pd=%p.\n", ha->async_pd); 3637 } 3638 3639 INIT_LIST_HEAD(&ha->vp_list); 3640 3641 /* Allocate memory for our loop_id bitmap */ 3642 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3643 GFP_KERNEL); 3644 if (!ha->loop_id_map) 3645 goto fail_async_pd; 3646 else { 3647 qla2x00_set_reserved_loop_ids(ha); 3648 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3649 "loop_id_map=%p.\n", ha->loop_id_map); 3650 } 3651 3652 return 0; 3653 3654 fail_async_pd: 3655 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3656 fail_ex_init_cb: 3657 kfree(ha->npiv_info); 3658 fail_npiv_info: 3659 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3660 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3661 (*rsp)->ring = NULL; 3662 (*rsp)->dma = 0; 3663 fail_rsp_ring: 3664 kfree(*rsp); 3665 fail_rsp: 3666 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3667 sizeof(request_t), (*req)->ring, (*req)->dma); 3668 (*req)->ring = NULL; 3669 (*req)->dma = 0; 3670 fail_req_ring: 3671 kfree(*req); 3672 fail_req: 3673 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3674 ha->ct_sns, ha->ct_sns_dma); 3675 ha->ct_sns = NULL; 3676 ha->ct_sns_dma = 0; 3677 fail_free_ms_iocb: 3678 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3679 ha->ms_iocb = NULL; 3680 ha->ms_iocb_dma = 0; 3681 fail_dma_pool: 3682 if (IS_QLA82XX(ha) || ql2xenabledif) { 3683 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3684 ha->fcp_cmnd_dma_pool = NULL; 3685 } 3686 fail_dl_dma_pool: 3687 if (IS_QLA82XX(ha) || ql2xenabledif) { 3688 dma_pool_destroy(ha->dl_dma_pool); 3689 ha->dl_dma_pool = NULL; 3690 } 3691 fail_s_dma_pool: 3692 dma_pool_destroy(ha->s_dma_pool); 3693 ha->s_dma_pool = NULL; 3694 fail_free_nvram: 3695 kfree(ha->nvram); 3696 ha->nvram = NULL; 3697 fail_free_ctx_mempool: 3698 mempool_destroy(ha->ctx_mempool); 3699 ha->ctx_mempool = NULL; 3700 fail_free_srb_mempool: 3701 mempool_destroy(ha->srb_mempool); 3702 ha->srb_mempool = NULL; 3703 fail_free_gid_list: 3704 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3705 ha->gid_list, 3706 ha->gid_list_dma); 3707 ha->gid_list = NULL; 3708 ha->gid_list_dma = 0; 3709 fail_free_tgt_mem: 3710 qlt_mem_free(ha); 3711 fail_free_init_cb: 3712 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3713 ha->init_cb_dma); 3714 ha->init_cb = NULL; 3715 ha->init_cb_dma = 0; 3716 fail: 3717 ql_log(ql_log_fatal, NULL, 0x0030, 3718 "Memory allocation failure.\n"); 3719 return -ENOMEM; 3720 } 3721 3722 int 3723 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3724 { 3725 int rval; 3726 uint16_t size, max_cnt, temp; 3727 struct qla_hw_data *ha = vha->hw; 3728 3729 /* Return if we don't need to alloacate any extended logins */ 3730 if (!ql2xexlogins) 3731 return QLA_SUCCESS; 3732 3733 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3734 max_cnt = 0; 3735 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3736 if (rval != QLA_SUCCESS) { 3737 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3738 "Failed to get exlogin status.\n"); 3739 return rval; 3740 } 3741 3742 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3743 ha->exlogin_size = (size * temp); 3744 ql_log(ql_log_info, vha, 0xd024, 3745 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3746 max_cnt, size, temp); 3747 3748 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3749 ha->exlogin_size); 3750 3751 /* Get consistent memory for extended logins */ 3752 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 3753 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 3754 if (!ha->exlogin_buf) { 3755 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 3756 "Failed to allocate memory for exlogin_buf_dma.\n"); 3757 return -ENOMEM; 3758 } 3759 3760 /* Now configure the dma buffer */ 3761 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 3762 if (rval) { 3763 ql_log(ql_log_fatal, vha, 0x00cf, 3764 "Setup extended login buffer ****FAILED****.\n"); 3765 qla2x00_free_exlogin_buffer(ha); 3766 } 3767 3768 return rval; 3769 } 3770 3771 /* 3772 * qla2x00_free_exlogin_buffer 3773 * 3774 * Input: 3775 * ha = adapter block pointer 3776 */ 3777 void 3778 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 3779 { 3780 if (ha->exlogin_buf) { 3781 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 3782 ha->exlogin_buf, ha->exlogin_buf_dma); 3783 ha->exlogin_buf = NULL; 3784 ha->exlogin_size = 0; 3785 } 3786 } 3787 3788 int 3789 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 3790 { 3791 int rval; 3792 uint16_t size, max_cnt, temp; 3793 struct qla_hw_data *ha = vha->hw; 3794 3795 /* Return if we don't need to alloacate any extended logins */ 3796 if (!ql2xexchoffld) 3797 return QLA_SUCCESS; 3798 3799 ql_log(ql_log_info, vha, 0xd014, 3800 "Exchange offload count: %d.\n", ql2xexlogins); 3801 3802 max_cnt = 0; 3803 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 3804 if (rval != QLA_SUCCESS) { 3805 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 3806 "Failed to get exlogin status.\n"); 3807 return rval; 3808 } 3809 3810 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 3811 ha->exchoffld_size = (size * temp); 3812 ql_log(ql_log_info, vha, 0xd016, 3813 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 3814 max_cnt, size, temp); 3815 3816 ql_log(ql_log_info, vha, 0xd017, 3817 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 3818 3819 /* Get consistent memory for extended logins */ 3820 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 3821 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 3822 if (!ha->exchoffld_buf) { 3823 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 3824 "Failed to allocate memory for exchoffld_buf_dma.\n"); 3825 return -ENOMEM; 3826 } 3827 3828 /* Now configure the dma buffer */ 3829 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 3830 if (rval) { 3831 ql_log(ql_log_fatal, vha, 0xd02e, 3832 "Setup exchange offload buffer ****FAILED****.\n"); 3833 qla2x00_free_exchoffld_buffer(ha); 3834 } 3835 3836 return rval; 3837 } 3838 3839 /* 3840 * qla2x00_free_exchoffld_buffer 3841 * 3842 * Input: 3843 * ha = adapter block pointer 3844 */ 3845 void 3846 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 3847 { 3848 if (ha->exchoffld_buf) { 3849 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 3850 ha->exchoffld_buf, ha->exchoffld_buf_dma); 3851 ha->exchoffld_buf = NULL; 3852 ha->exchoffld_size = 0; 3853 } 3854 } 3855 3856 /* 3857 * qla2x00_free_fw_dump 3858 * Frees fw dump stuff. 3859 * 3860 * Input: 3861 * ha = adapter block pointer 3862 */ 3863 static void 3864 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3865 { 3866 if (ha->fce) 3867 dma_free_coherent(&ha->pdev->dev, 3868 FCE_SIZE, ha->fce, ha->fce_dma); 3869 3870 if (ha->eft) 3871 dma_free_coherent(&ha->pdev->dev, 3872 EFT_SIZE, ha->eft, ha->eft_dma); 3873 3874 if (ha->fw_dump) 3875 vfree(ha->fw_dump); 3876 if (ha->fw_dump_template) 3877 vfree(ha->fw_dump_template); 3878 3879 ha->fce = NULL; 3880 ha->fce_dma = 0; 3881 ha->eft = NULL; 3882 ha->eft_dma = 0; 3883 ha->fw_dumped = 0; 3884 ha->fw_dump_cap_flags = 0; 3885 ha->fw_dump_reading = 0; 3886 ha->fw_dump = NULL; 3887 ha->fw_dump_len = 0; 3888 ha->fw_dump_template = NULL; 3889 ha->fw_dump_template_len = 0; 3890 } 3891 3892 /* 3893 * qla2x00_mem_free 3894 * Frees all adapter allocated memory. 3895 * 3896 * Input: 3897 * ha = adapter block pointer. 3898 */ 3899 static void 3900 qla2x00_mem_free(struct qla_hw_data *ha) 3901 { 3902 qla2x00_free_fw_dump(ha); 3903 3904 if (ha->mctp_dump) 3905 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3906 ha->mctp_dump_dma); 3907 3908 if (ha->srb_mempool) 3909 mempool_destroy(ha->srb_mempool); 3910 3911 if (ha->dcbx_tlv) 3912 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3913 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3914 3915 if (ha->xgmac_data) 3916 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3917 ha->xgmac_data, ha->xgmac_data_dma); 3918 3919 if (ha->sns_cmd) 3920 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3921 ha->sns_cmd, ha->sns_cmd_dma); 3922 3923 if (ha->ct_sns) 3924 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3925 ha->ct_sns, ha->ct_sns_dma); 3926 3927 if (ha->sfp_data) 3928 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3929 3930 if (ha->ms_iocb) 3931 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3932 3933 if (ha->ex_init_cb) 3934 dma_pool_free(ha->s_dma_pool, 3935 ha->ex_init_cb, ha->ex_init_cb_dma); 3936 3937 if (ha->async_pd) 3938 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3939 3940 if (ha->s_dma_pool) 3941 dma_pool_destroy(ha->s_dma_pool); 3942 3943 if (ha->gid_list) 3944 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3945 ha->gid_list, ha->gid_list_dma); 3946 3947 if (IS_QLA82XX(ha)) { 3948 if (!list_empty(&ha->gbl_dsd_list)) { 3949 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3950 3951 /* clean up allocated prev pool */ 3952 list_for_each_entry_safe(dsd_ptr, 3953 tdsd_ptr, &ha->gbl_dsd_list, list) { 3954 dma_pool_free(ha->dl_dma_pool, 3955 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3956 list_del(&dsd_ptr->list); 3957 kfree(dsd_ptr); 3958 } 3959 } 3960 } 3961 3962 if (ha->dl_dma_pool) 3963 dma_pool_destroy(ha->dl_dma_pool); 3964 3965 if (ha->fcp_cmnd_dma_pool) 3966 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3967 3968 if (ha->ctx_mempool) 3969 mempool_destroy(ha->ctx_mempool); 3970 3971 qlt_mem_free(ha); 3972 3973 if (ha->init_cb) 3974 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3975 ha->init_cb, ha->init_cb_dma); 3976 vfree(ha->optrom_buffer); 3977 kfree(ha->nvram); 3978 kfree(ha->npiv_info); 3979 kfree(ha->swl); 3980 kfree(ha->loop_id_map); 3981 3982 ha->srb_mempool = NULL; 3983 ha->ctx_mempool = NULL; 3984 ha->sns_cmd = NULL; 3985 ha->sns_cmd_dma = 0; 3986 ha->ct_sns = NULL; 3987 ha->ct_sns_dma = 0; 3988 ha->ms_iocb = NULL; 3989 ha->ms_iocb_dma = 0; 3990 ha->init_cb = NULL; 3991 ha->init_cb_dma = 0; 3992 ha->ex_init_cb = NULL; 3993 ha->ex_init_cb_dma = 0; 3994 ha->async_pd = NULL; 3995 ha->async_pd_dma = 0; 3996 3997 ha->s_dma_pool = NULL; 3998 ha->dl_dma_pool = NULL; 3999 ha->fcp_cmnd_dma_pool = NULL; 4000 4001 ha->gid_list = NULL; 4002 ha->gid_list_dma = 0; 4003 4004 ha->tgt.atio_ring = NULL; 4005 ha->tgt.atio_dma = 0; 4006 ha->tgt.tgt_vp_map = NULL; 4007 } 4008 4009 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4010 struct qla_hw_data *ha) 4011 { 4012 struct Scsi_Host *host; 4013 struct scsi_qla_host *vha = NULL; 4014 4015 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4016 if (host == NULL) { 4017 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4018 "Failed to allocate host from the scsi layer, aborting.\n"); 4019 goto fail; 4020 } 4021 4022 /* Clear our data area */ 4023 vha = shost_priv(host); 4024 memset(vha, 0, sizeof(scsi_qla_host_t)); 4025 4026 vha->host = host; 4027 vha->host_no = host->host_no; 4028 vha->hw = ha; 4029 4030 INIT_LIST_HEAD(&vha->vp_fcports); 4031 INIT_LIST_HEAD(&vha->work_list); 4032 INIT_LIST_HEAD(&vha->list); 4033 INIT_LIST_HEAD(&vha->qla_cmd_list); 4034 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4035 INIT_LIST_HEAD(&vha->logo_list); 4036 INIT_LIST_HEAD(&vha->plogi_ack_list); 4037 4038 spin_lock_init(&vha->work_lock); 4039 spin_lock_init(&vha->cmd_list_lock); 4040 4041 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4042 ql_dbg(ql_dbg_init, vha, 0x0041, 4043 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4044 vha->host, vha->hw, vha, 4045 dev_name(&(ha->pdev->dev))); 4046 4047 return vha; 4048 4049 fail: 4050 return vha; 4051 } 4052 4053 static struct qla_work_evt * 4054 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4055 { 4056 struct qla_work_evt *e; 4057 uint8_t bail; 4058 4059 QLA_VHA_MARK_BUSY(vha, bail); 4060 if (bail) 4061 return NULL; 4062 4063 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4064 if (!e) { 4065 QLA_VHA_MARK_NOT_BUSY(vha); 4066 return NULL; 4067 } 4068 4069 INIT_LIST_HEAD(&e->list); 4070 e->type = type; 4071 e->flags = QLA_EVT_FLAG_FREE; 4072 return e; 4073 } 4074 4075 static int 4076 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4077 { 4078 unsigned long flags; 4079 4080 spin_lock_irqsave(&vha->work_lock, flags); 4081 list_add_tail(&e->list, &vha->work_list); 4082 spin_unlock_irqrestore(&vha->work_lock, flags); 4083 qla2xxx_wake_dpc(vha); 4084 4085 return QLA_SUCCESS; 4086 } 4087 4088 int 4089 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4090 u32 data) 4091 { 4092 struct qla_work_evt *e; 4093 4094 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4095 if (!e) 4096 return QLA_FUNCTION_FAILED; 4097 4098 e->u.aen.code = code; 4099 e->u.aen.data = data; 4100 return qla2x00_post_work(vha, e); 4101 } 4102 4103 int 4104 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4105 { 4106 struct qla_work_evt *e; 4107 4108 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4109 if (!e) 4110 return QLA_FUNCTION_FAILED; 4111 4112 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4113 return qla2x00_post_work(vha, e); 4114 } 4115 4116 #define qla2x00_post_async_work(name, type) \ 4117 int qla2x00_post_async_##name##_work( \ 4118 struct scsi_qla_host *vha, \ 4119 fc_port_t *fcport, uint16_t *data) \ 4120 { \ 4121 struct qla_work_evt *e; \ 4122 \ 4123 e = qla2x00_alloc_work(vha, type); \ 4124 if (!e) \ 4125 return QLA_FUNCTION_FAILED; \ 4126 \ 4127 e->u.logio.fcport = fcport; \ 4128 if (data) { \ 4129 e->u.logio.data[0] = data[0]; \ 4130 e->u.logio.data[1] = data[1]; \ 4131 } \ 4132 return qla2x00_post_work(vha, e); \ 4133 } 4134 4135 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4136 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 4137 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4138 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4139 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4140 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4141 4142 int 4143 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4144 { 4145 struct qla_work_evt *e; 4146 4147 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4148 if (!e) 4149 return QLA_FUNCTION_FAILED; 4150 4151 e->u.uevent.code = code; 4152 return qla2x00_post_work(vha, e); 4153 } 4154 4155 static void 4156 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4157 { 4158 char event_string[40]; 4159 char *envp[] = { event_string, NULL }; 4160 4161 switch (code) { 4162 case QLA_UEVENT_CODE_FW_DUMP: 4163 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4164 vha->host_no); 4165 break; 4166 default: 4167 /* do nothing */ 4168 break; 4169 } 4170 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4171 } 4172 4173 int 4174 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4175 uint32_t *data, int cnt) 4176 { 4177 struct qla_work_evt *e; 4178 4179 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4180 if (!e) 4181 return QLA_FUNCTION_FAILED; 4182 4183 e->u.aenfx.evtcode = evtcode; 4184 e->u.aenfx.count = cnt; 4185 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4186 return qla2x00_post_work(vha, e); 4187 } 4188 4189 void 4190 qla2x00_do_work(struct scsi_qla_host *vha) 4191 { 4192 struct qla_work_evt *e, *tmp; 4193 unsigned long flags; 4194 LIST_HEAD(work); 4195 4196 spin_lock_irqsave(&vha->work_lock, flags); 4197 list_splice_init(&vha->work_list, &work); 4198 spin_unlock_irqrestore(&vha->work_lock, flags); 4199 4200 list_for_each_entry_safe(e, tmp, &work, list) { 4201 list_del_init(&e->list); 4202 4203 switch (e->type) { 4204 case QLA_EVT_AEN: 4205 fc_host_post_event(vha->host, fc_get_event_number(), 4206 e->u.aen.code, e->u.aen.data); 4207 break; 4208 case QLA_EVT_IDC_ACK: 4209 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4210 break; 4211 case QLA_EVT_ASYNC_LOGIN: 4212 qla2x00_async_login(vha, e->u.logio.fcport, 4213 e->u.logio.data); 4214 break; 4215 case QLA_EVT_ASYNC_LOGIN_DONE: 4216 qla2x00_async_login_done(vha, e->u.logio.fcport, 4217 e->u.logio.data); 4218 break; 4219 case QLA_EVT_ASYNC_LOGOUT: 4220 qla2x00_async_logout(vha, e->u.logio.fcport); 4221 break; 4222 case QLA_EVT_ASYNC_LOGOUT_DONE: 4223 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4224 e->u.logio.data); 4225 break; 4226 case QLA_EVT_ASYNC_ADISC: 4227 qla2x00_async_adisc(vha, e->u.logio.fcport, 4228 e->u.logio.data); 4229 break; 4230 case QLA_EVT_ASYNC_ADISC_DONE: 4231 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4232 e->u.logio.data); 4233 break; 4234 case QLA_EVT_UEVENT: 4235 qla2x00_uevent_emit(vha, e->u.uevent.code); 4236 break; 4237 case QLA_EVT_AENFX: 4238 qlafx00_process_aen(vha, e); 4239 break; 4240 } 4241 if (e->flags & QLA_EVT_FLAG_FREE) 4242 kfree(e); 4243 4244 /* For each work completed decrement vha ref count */ 4245 QLA_VHA_MARK_NOT_BUSY(vha); 4246 } 4247 } 4248 4249 /* Relogins all the fcports of a vport 4250 * Context: dpc thread 4251 */ 4252 void qla2x00_relogin(struct scsi_qla_host *vha) 4253 { 4254 fc_port_t *fcport; 4255 int status; 4256 uint16_t next_loopid = 0; 4257 struct qla_hw_data *ha = vha->hw; 4258 uint16_t data[2]; 4259 4260 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4261 /* 4262 * If the port is not ONLINE then try to login 4263 * to it if we haven't run out of retries. 4264 */ 4265 if (atomic_read(&fcport->state) != FCS_ONLINE && 4266 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4267 fcport->login_retry--; 4268 if (fcport->flags & FCF_FABRIC_DEVICE) { 4269 if (fcport->flags & FCF_FCP2_DEVICE) 4270 ha->isp_ops->fabric_logout(vha, 4271 fcport->loop_id, 4272 fcport->d_id.b.domain, 4273 fcport->d_id.b.area, 4274 fcport->d_id.b.al_pa); 4275 4276 if (fcport->loop_id == FC_NO_LOOP_ID) { 4277 fcport->loop_id = next_loopid = 4278 ha->min_external_loopid; 4279 status = qla2x00_find_new_loop_id( 4280 vha, fcport); 4281 if (status != QLA_SUCCESS) { 4282 /* Ran out of IDs to use */ 4283 break; 4284 } 4285 } 4286 4287 if (IS_ALOGIO_CAPABLE(ha)) { 4288 fcport->flags |= FCF_ASYNC_SENT; 4289 data[0] = 0; 4290 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4291 status = qla2x00_post_async_login_work( 4292 vha, fcport, data); 4293 if (status == QLA_SUCCESS) 4294 continue; 4295 /* Attempt a retry. */ 4296 status = 1; 4297 } else { 4298 status = qla2x00_fabric_login(vha, 4299 fcport, &next_loopid); 4300 if (status == QLA_SUCCESS) { 4301 int status2; 4302 uint8_t opts; 4303 4304 opts = 0; 4305 if (fcport->flags & 4306 FCF_FCP2_DEVICE) 4307 opts |= BIT_1; 4308 status2 = 4309 qla2x00_get_port_database( 4310 vha, fcport, opts); 4311 if (status2 != QLA_SUCCESS) 4312 status = 1; 4313 } 4314 } 4315 } else 4316 status = qla2x00_local_device_login(vha, 4317 fcport); 4318 4319 if (status == QLA_SUCCESS) { 4320 fcport->old_loop_id = fcport->loop_id; 4321 4322 ql_dbg(ql_dbg_disc, vha, 0x2003, 4323 "Port login OK: logged in ID 0x%x.\n", 4324 fcport->loop_id); 4325 4326 qla2x00_update_fcport(vha, fcport); 4327 4328 } else if (status == 1) { 4329 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4330 /* retry the login again */ 4331 ql_dbg(ql_dbg_disc, vha, 0x2007, 4332 "Retrying %d login again loop_id 0x%x.\n", 4333 fcport->login_retry, fcport->loop_id); 4334 } else { 4335 fcport->login_retry = 0; 4336 } 4337 4338 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4339 qla2x00_clear_loop_id(fcport); 4340 } 4341 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4342 break; 4343 } 4344 } 4345 4346 /* Schedule work on any of the dpc-workqueues */ 4347 void 4348 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4349 { 4350 struct qla_hw_data *ha = base_vha->hw; 4351 4352 switch (work_code) { 4353 case MBA_IDC_AEN: /* 0x8200 */ 4354 if (ha->dpc_lp_wq) 4355 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4356 break; 4357 4358 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4359 if (!ha->flags.nic_core_reset_hdlr_active) { 4360 if (ha->dpc_hp_wq) 4361 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4362 } else 4363 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4364 "NIC Core reset is already active. Skip " 4365 "scheduling it again.\n"); 4366 break; 4367 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4368 if (ha->dpc_hp_wq) 4369 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4370 break; 4371 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4372 if (ha->dpc_hp_wq) 4373 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4374 break; 4375 default: 4376 ql_log(ql_log_warn, base_vha, 0xb05f, 4377 "Unknown work-code=0x%x.\n", work_code); 4378 } 4379 4380 return; 4381 } 4382 4383 /* Work: Perform NIC Core Unrecoverable state handling */ 4384 void 4385 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4386 { 4387 struct qla_hw_data *ha = 4388 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4389 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4390 uint32_t dev_state = 0; 4391 4392 qla83xx_idc_lock(base_vha, 0); 4393 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4394 qla83xx_reset_ownership(base_vha); 4395 if (ha->flags.nic_core_reset_owner) { 4396 ha->flags.nic_core_reset_owner = 0; 4397 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4398 QLA8XXX_DEV_FAILED); 4399 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4400 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4401 } 4402 qla83xx_idc_unlock(base_vha, 0); 4403 } 4404 4405 /* Work: Execute IDC state handler */ 4406 void 4407 qla83xx_idc_state_handler_work(struct work_struct *work) 4408 { 4409 struct qla_hw_data *ha = 4410 container_of(work, struct qla_hw_data, idc_state_handler); 4411 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4412 uint32_t dev_state = 0; 4413 4414 qla83xx_idc_lock(base_vha, 0); 4415 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4416 if (dev_state == QLA8XXX_DEV_FAILED || 4417 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4418 qla83xx_idc_state_handler(base_vha); 4419 qla83xx_idc_unlock(base_vha, 0); 4420 } 4421 4422 static int 4423 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4424 { 4425 int rval = QLA_SUCCESS; 4426 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4427 uint32_t heart_beat_counter1, heart_beat_counter2; 4428 4429 do { 4430 if (time_after(jiffies, heart_beat_wait)) { 4431 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4432 "Nic Core f/w is not alive.\n"); 4433 rval = QLA_FUNCTION_FAILED; 4434 break; 4435 } 4436 4437 qla83xx_idc_lock(base_vha, 0); 4438 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4439 &heart_beat_counter1); 4440 qla83xx_idc_unlock(base_vha, 0); 4441 msleep(100); 4442 qla83xx_idc_lock(base_vha, 0); 4443 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4444 &heart_beat_counter2); 4445 qla83xx_idc_unlock(base_vha, 0); 4446 } while (heart_beat_counter1 == heart_beat_counter2); 4447 4448 return rval; 4449 } 4450 4451 /* Work: Perform NIC Core Reset handling */ 4452 void 4453 qla83xx_nic_core_reset_work(struct work_struct *work) 4454 { 4455 struct qla_hw_data *ha = 4456 container_of(work, struct qla_hw_data, nic_core_reset); 4457 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4458 uint32_t dev_state = 0; 4459 4460 if (IS_QLA2031(ha)) { 4461 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4462 ql_log(ql_log_warn, base_vha, 0xb081, 4463 "Failed to dump mctp\n"); 4464 return; 4465 } 4466 4467 if (!ha->flags.nic_core_reset_hdlr_active) { 4468 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4469 qla83xx_idc_lock(base_vha, 0); 4470 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4471 &dev_state); 4472 qla83xx_idc_unlock(base_vha, 0); 4473 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4474 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4475 "Nic Core f/w is alive.\n"); 4476 return; 4477 } 4478 } 4479 4480 ha->flags.nic_core_reset_hdlr_active = 1; 4481 if (qla83xx_nic_core_reset(base_vha)) { 4482 /* NIC Core reset failed. */ 4483 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4484 "NIC Core reset failed.\n"); 4485 } 4486 ha->flags.nic_core_reset_hdlr_active = 0; 4487 } 4488 } 4489 4490 /* Work: Handle 8200 IDC aens */ 4491 void 4492 qla83xx_service_idc_aen(struct work_struct *work) 4493 { 4494 struct qla_hw_data *ha = 4495 container_of(work, struct qla_hw_data, idc_aen); 4496 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4497 uint32_t dev_state, idc_control; 4498 4499 qla83xx_idc_lock(base_vha, 0); 4500 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4501 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4502 qla83xx_idc_unlock(base_vha, 0); 4503 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4504 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4505 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4506 "Application requested NIC Core Reset.\n"); 4507 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4508 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4509 QLA_SUCCESS) { 4510 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4511 "Other protocol driver requested NIC Core Reset.\n"); 4512 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4513 } 4514 } else if (dev_state == QLA8XXX_DEV_FAILED || 4515 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4516 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4517 } 4518 } 4519 4520 static void 4521 qla83xx_wait_logic(void) 4522 { 4523 int i; 4524 4525 /* Yield CPU */ 4526 if (!in_interrupt()) { 4527 /* 4528 * Wait about 200ms before retrying again. 4529 * This controls the number of retries for single 4530 * lock operation. 4531 */ 4532 msleep(100); 4533 schedule(); 4534 } else { 4535 for (i = 0; i < 20; i++) 4536 cpu_relax(); /* This a nop instr on i386 */ 4537 } 4538 } 4539 4540 static int 4541 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4542 { 4543 int rval; 4544 uint32_t data; 4545 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4546 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4547 struct qla_hw_data *ha = base_vha->hw; 4548 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4549 "Trying force recovery of the IDC lock.\n"); 4550 4551 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4552 if (rval) 4553 return rval; 4554 4555 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4556 return QLA_SUCCESS; 4557 } else { 4558 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4559 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4560 data); 4561 if (rval) 4562 return rval; 4563 4564 msleep(200); 4565 4566 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4567 &data); 4568 if (rval) 4569 return rval; 4570 4571 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4572 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4573 ~(idc_lck_rcvry_stage_mask)); 4574 rval = qla83xx_wr_reg(base_vha, 4575 QLA83XX_IDC_LOCK_RECOVERY, data); 4576 if (rval) 4577 return rval; 4578 4579 /* Forcefully perform IDC UnLock */ 4580 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4581 &data); 4582 if (rval) 4583 return rval; 4584 /* Clear lock-id by setting 0xff */ 4585 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4586 0xff); 4587 if (rval) 4588 return rval; 4589 /* Clear lock-recovery by setting 0x0 */ 4590 rval = qla83xx_wr_reg(base_vha, 4591 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4592 if (rval) 4593 return rval; 4594 } else 4595 return QLA_SUCCESS; 4596 } 4597 4598 return rval; 4599 } 4600 4601 static int 4602 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4603 { 4604 int rval = QLA_SUCCESS; 4605 uint32_t o_drv_lockid, n_drv_lockid; 4606 unsigned long lock_recovery_timeout; 4607 4608 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4609 retry_lockid: 4610 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4611 if (rval) 4612 goto exit; 4613 4614 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4615 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4616 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4617 return QLA_SUCCESS; 4618 else 4619 return QLA_FUNCTION_FAILED; 4620 } 4621 4622 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4623 if (rval) 4624 goto exit; 4625 4626 if (o_drv_lockid == n_drv_lockid) { 4627 qla83xx_wait_logic(); 4628 goto retry_lockid; 4629 } else 4630 return QLA_SUCCESS; 4631 4632 exit: 4633 return rval; 4634 } 4635 4636 void 4637 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4638 { 4639 uint16_t options = (requester_id << 15) | BIT_6; 4640 uint32_t data; 4641 uint32_t lock_owner; 4642 struct qla_hw_data *ha = base_vha->hw; 4643 4644 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4645 retry_lock: 4646 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4647 == QLA_SUCCESS) { 4648 if (data) { 4649 /* Setting lock-id to our function-number */ 4650 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4651 ha->portnum); 4652 } else { 4653 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4654 &lock_owner); 4655 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4656 "Failed to acquire IDC lock, acquired by %d, " 4657 "retrying...\n", lock_owner); 4658 4659 /* Retry/Perform IDC-Lock recovery */ 4660 if (qla83xx_idc_lock_recovery(base_vha) 4661 == QLA_SUCCESS) { 4662 qla83xx_wait_logic(); 4663 goto retry_lock; 4664 } else 4665 ql_log(ql_log_warn, base_vha, 0xb075, 4666 "IDC Lock recovery FAILED.\n"); 4667 } 4668 4669 } 4670 4671 return; 4672 4673 /* XXX: IDC-lock implementation using access-control mbx */ 4674 retry_lock2: 4675 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4676 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4677 "Failed to acquire IDC lock. retrying...\n"); 4678 /* Retry/Perform IDC-Lock recovery */ 4679 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4680 qla83xx_wait_logic(); 4681 goto retry_lock2; 4682 } else 4683 ql_log(ql_log_warn, base_vha, 0xb076, 4684 "IDC Lock recovery FAILED.\n"); 4685 } 4686 4687 return; 4688 } 4689 4690 void 4691 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4692 { 4693 #if 0 4694 uint16_t options = (requester_id << 15) | BIT_7; 4695 #endif 4696 uint16_t retry; 4697 uint32_t data; 4698 struct qla_hw_data *ha = base_vha->hw; 4699 4700 /* IDC-unlock implementation using driver-unlock/lock-id 4701 * remote registers 4702 */ 4703 retry = 0; 4704 retry_unlock: 4705 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4706 == QLA_SUCCESS) { 4707 if (data == ha->portnum) { 4708 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4709 /* Clearing lock-id by setting 0xff */ 4710 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4711 } else if (retry < 10) { 4712 /* SV: XXX: IDC unlock retrying needed here? */ 4713 4714 /* Retry for IDC-unlock */ 4715 qla83xx_wait_logic(); 4716 retry++; 4717 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4718 "Failed to release IDC lock, retrying=%d\n", retry); 4719 goto retry_unlock; 4720 } 4721 } else if (retry < 10) { 4722 /* Retry for IDC-unlock */ 4723 qla83xx_wait_logic(); 4724 retry++; 4725 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4726 "Failed to read drv-lockid, retrying=%d\n", retry); 4727 goto retry_unlock; 4728 } 4729 4730 return; 4731 4732 #if 0 4733 /* XXX: IDC-unlock implementation using access-control mbx */ 4734 retry = 0; 4735 retry_unlock2: 4736 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4737 if (retry < 10) { 4738 /* Retry for IDC-unlock */ 4739 qla83xx_wait_logic(); 4740 retry++; 4741 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4742 "Failed to release IDC lock, retrying=%d\n", retry); 4743 goto retry_unlock2; 4744 } 4745 } 4746 4747 return; 4748 #endif 4749 } 4750 4751 int 4752 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4753 { 4754 int rval = QLA_SUCCESS; 4755 struct qla_hw_data *ha = vha->hw; 4756 uint32_t drv_presence; 4757 4758 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4759 if (rval == QLA_SUCCESS) { 4760 drv_presence |= (1 << ha->portnum); 4761 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4762 drv_presence); 4763 } 4764 4765 return rval; 4766 } 4767 4768 int 4769 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4770 { 4771 int rval = QLA_SUCCESS; 4772 4773 qla83xx_idc_lock(vha, 0); 4774 rval = __qla83xx_set_drv_presence(vha); 4775 qla83xx_idc_unlock(vha, 0); 4776 4777 return rval; 4778 } 4779 4780 int 4781 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4782 { 4783 int rval = QLA_SUCCESS; 4784 struct qla_hw_data *ha = vha->hw; 4785 uint32_t drv_presence; 4786 4787 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4788 if (rval == QLA_SUCCESS) { 4789 drv_presence &= ~(1 << ha->portnum); 4790 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4791 drv_presence); 4792 } 4793 4794 return rval; 4795 } 4796 4797 int 4798 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4799 { 4800 int rval = QLA_SUCCESS; 4801 4802 qla83xx_idc_lock(vha, 0); 4803 rval = __qla83xx_clear_drv_presence(vha); 4804 qla83xx_idc_unlock(vha, 0); 4805 4806 return rval; 4807 } 4808 4809 static void 4810 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4811 { 4812 struct qla_hw_data *ha = vha->hw; 4813 uint32_t drv_ack, drv_presence; 4814 unsigned long ack_timeout; 4815 4816 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4817 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4818 while (1) { 4819 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4820 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4821 if ((drv_ack & drv_presence) == drv_presence) 4822 break; 4823 4824 if (time_after_eq(jiffies, ack_timeout)) { 4825 ql_log(ql_log_warn, vha, 0xb067, 4826 "RESET ACK TIMEOUT! drv_presence=0x%x " 4827 "drv_ack=0x%x\n", drv_presence, drv_ack); 4828 /* 4829 * The function(s) which did not ack in time are forced 4830 * to withdraw any further participation in the IDC 4831 * reset. 4832 */ 4833 if (drv_ack != drv_presence) 4834 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4835 drv_ack); 4836 break; 4837 } 4838 4839 qla83xx_idc_unlock(vha, 0); 4840 msleep(1000); 4841 qla83xx_idc_lock(vha, 0); 4842 } 4843 4844 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4845 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4846 } 4847 4848 static int 4849 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4850 { 4851 int rval = QLA_SUCCESS; 4852 uint32_t idc_control; 4853 4854 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4855 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4856 4857 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4858 __qla83xx_get_idc_control(vha, &idc_control); 4859 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4860 __qla83xx_set_idc_control(vha, 0); 4861 4862 qla83xx_idc_unlock(vha, 0); 4863 rval = qla83xx_restart_nic_firmware(vha); 4864 qla83xx_idc_lock(vha, 0); 4865 4866 if (rval != QLA_SUCCESS) { 4867 ql_log(ql_log_fatal, vha, 0xb06a, 4868 "Failed to restart NIC f/w.\n"); 4869 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4870 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4871 } else { 4872 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4873 "Success in restarting nic f/w.\n"); 4874 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4875 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4876 } 4877 4878 return rval; 4879 } 4880 4881 /* Assumes idc_lock always held on entry */ 4882 int 4883 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4884 { 4885 struct qla_hw_data *ha = base_vha->hw; 4886 int rval = QLA_SUCCESS; 4887 unsigned long dev_init_timeout; 4888 uint32_t dev_state; 4889 4890 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4891 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4892 4893 while (1) { 4894 4895 if (time_after_eq(jiffies, dev_init_timeout)) { 4896 ql_log(ql_log_warn, base_vha, 0xb06e, 4897 "Initialization TIMEOUT!\n"); 4898 /* Init timeout. Disable further NIC Core 4899 * communication. 4900 */ 4901 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4902 QLA8XXX_DEV_FAILED); 4903 ql_log(ql_log_info, base_vha, 0xb06f, 4904 "HW State: FAILED.\n"); 4905 } 4906 4907 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4908 switch (dev_state) { 4909 case QLA8XXX_DEV_READY: 4910 if (ha->flags.nic_core_reset_owner) 4911 qla83xx_idc_audit(base_vha, 4912 IDC_AUDIT_COMPLETION); 4913 ha->flags.nic_core_reset_owner = 0; 4914 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4915 "Reset_owner reset by 0x%x.\n", 4916 ha->portnum); 4917 goto exit; 4918 case QLA8XXX_DEV_COLD: 4919 if (ha->flags.nic_core_reset_owner) 4920 rval = qla83xx_device_bootstrap(base_vha); 4921 else { 4922 /* Wait for AEN to change device-state */ 4923 qla83xx_idc_unlock(base_vha, 0); 4924 msleep(1000); 4925 qla83xx_idc_lock(base_vha, 0); 4926 } 4927 break; 4928 case QLA8XXX_DEV_INITIALIZING: 4929 /* Wait for AEN to change device-state */ 4930 qla83xx_idc_unlock(base_vha, 0); 4931 msleep(1000); 4932 qla83xx_idc_lock(base_vha, 0); 4933 break; 4934 case QLA8XXX_DEV_NEED_RESET: 4935 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4936 qla83xx_need_reset_handler(base_vha); 4937 else { 4938 /* Wait for AEN to change device-state */ 4939 qla83xx_idc_unlock(base_vha, 0); 4940 msleep(1000); 4941 qla83xx_idc_lock(base_vha, 0); 4942 } 4943 /* reset timeout value after need reset handler */ 4944 dev_init_timeout = jiffies + 4945 (ha->fcoe_dev_init_timeout * HZ); 4946 break; 4947 case QLA8XXX_DEV_NEED_QUIESCENT: 4948 /* XXX: DEBUG for now */ 4949 qla83xx_idc_unlock(base_vha, 0); 4950 msleep(1000); 4951 qla83xx_idc_lock(base_vha, 0); 4952 break; 4953 case QLA8XXX_DEV_QUIESCENT: 4954 /* XXX: DEBUG for now */ 4955 if (ha->flags.quiesce_owner) 4956 goto exit; 4957 4958 qla83xx_idc_unlock(base_vha, 0); 4959 msleep(1000); 4960 qla83xx_idc_lock(base_vha, 0); 4961 dev_init_timeout = jiffies + 4962 (ha->fcoe_dev_init_timeout * HZ); 4963 break; 4964 case QLA8XXX_DEV_FAILED: 4965 if (ha->flags.nic_core_reset_owner) 4966 qla83xx_idc_audit(base_vha, 4967 IDC_AUDIT_COMPLETION); 4968 ha->flags.nic_core_reset_owner = 0; 4969 __qla83xx_clear_drv_presence(base_vha); 4970 qla83xx_idc_unlock(base_vha, 0); 4971 qla8xxx_dev_failed_handler(base_vha); 4972 rval = QLA_FUNCTION_FAILED; 4973 qla83xx_idc_lock(base_vha, 0); 4974 goto exit; 4975 case QLA8XXX_BAD_VALUE: 4976 qla83xx_idc_unlock(base_vha, 0); 4977 msleep(1000); 4978 qla83xx_idc_lock(base_vha, 0); 4979 break; 4980 default: 4981 ql_log(ql_log_warn, base_vha, 0xb071, 4982 "Unknown Device State: %x.\n", dev_state); 4983 qla83xx_idc_unlock(base_vha, 0); 4984 qla8xxx_dev_failed_handler(base_vha); 4985 rval = QLA_FUNCTION_FAILED; 4986 qla83xx_idc_lock(base_vha, 0); 4987 goto exit; 4988 } 4989 } 4990 4991 exit: 4992 return rval; 4993 } 4994 4995 void 4996 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4997 { 4998 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4999 board_disable); 5000 struct pci_dev *pdev = ha->pdev; 5001 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5002 5003 /* if UNLOAD flag is already set, then continue unload, 5004 * where it was set first. 5005 */ 5006 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5007 return; 5008 5009 ql_log(ql_log_warn, base_vha, 0x015b, 5010 "Disabling adapter.\n"); 5011 5012 set_bit(UNLOADING, &base_vha->dpc_flags); 5013 5014 qla2x00_delete_all_vps(ha, base_vha); 5015 5016 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5017 5018 qla2x00_dfs_remove(base_vha); 5019 5020 qla84xx_put_chip(base_vha); 5021 5022 if (base_vha->timer_active) 5023 qla2x00_stop_timer(base_vha); 5024 5025 base_vha->flags.online = 0; 5026 5027 qla2x00_destroy_deferred_work(ha); 5028 5029 /* 5030 * Do not try to stop beacon blink as it will issue a mailbox 5031 * command. 5032 */ 5033 qla2x00_free_sysfs_attr(base_vha, false); 5034 5035 fc_remove_host(base_vha->host); 5036 5037 scsi_remove_host(base_vha->host); 5038 5039 base_vha->flags.init_done = 0; 5040 qla25xx_delete_queues(base_vha); 5041 qla2x00_free_irqs(base_vha); 5042 qla2x00_free_fcports(base_vha); 5043 qla2x00_mem_free(ha); 5044 qla82xx_md_free(base_vha); 5045 qla2x00_free_queues(ha); 5046 5047 qla2x00_unmap_iobases(ha); 5048 5049 pci_release_selected_regions(ha->pdev, ha->bars); 5050 pci_disable_pcie_error_reporting(pdev); 5051 pci_disable_device(pdev); 5052 5053 /* 5054 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5055 */ 5056 } 5057 5058 /************************************************************************** 5059 * qla2x00_do_dpc 5060 * This kernel thread is a task that is schedule by the interrupt handler 5061 * to perform the background processing for interrupts. 5062 * 5063 * Notes: 5064 * This task always run in the context of a kernel thread. It 5065 * is kick-off by the driver's detect code and starts up 5066 * up one per adapter. It immediately goes to sleep and waits for 5067 * some fibre event. When either the interrupt handler or 5068 * the timer routine detects a event it will one of the task 5069 * bits then wake us up. 5070 **************************************************************************/ 5071 static int 5072 qla2x00_do_dpc(void *data) 5073 { 5074 scsi_qla_host_t *base_vha; 5075 struct qla_hw_data *ha; 5076 5077 ha = (struct qla_hw_data *)data; 5078 base_vha = pci_get_drvdata(ha->pdev); 5079 5080 set_user_nice(current, MIN_NICE); 5081 5082 set_current_state(TASK_INTERRUPTIBLE); 5083 while (!kthread_should_stop()) { 5084 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5085 "DPC handler sleeping.\n"); 5086 5087 schedule(); 5088 5089 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5090 goto end_loop; 5091 5092 if (ha->flags.eeh_busy) { 5093 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5094 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5095 goto end_loop; 5096 } 5097 5098 ha->dpc_active = 1; 5099 5100 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5101 "DPC handler waking up, dpc_flags=0x%lx.\n", 5102 base_vha->dpc_flags); 5103 5104 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5105 break; 5106 5107 qla2x00_do_work(base_vha); 5108 5109 if (IS_P3P_TYPE(ha)) { 5110 if (IS_QLA8044(ha)) { 5111 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5112 &base_vha->dpc_flags)) { 5113 qla8044_idc_lock(ha); 5114 qla8044_wr_direct(base_vha, 5115 QLA8044_CRB_DEV_STATE_INDEX, 5116 QLA8XXX_DEV_FAILED); 5117 qla8044_idc_unlock(ha); 5118 ql_log(ql_log_info, base_vha, 0x4004, 5119 "HW State: FAILED.\n"); 5120 qla8044_device_state_handler(base_vha); 5121 continue; 5122 } 5123 5124 } else { 5125 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5126 &base_vha->dpc_flags)) { 5127 qla82xx_idc_lock(ha); 5128 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5129 QLA8XXX_DEV_FAILED); 5130 qla82xx_idc_unlock(ha); 5131 ql_log(ql_log_info, base_vha, 0x0151, 5132 "HW State: FAILED.\n"); 5133 qla82xx_device_state_handler(base_vha); 5134 continue; 5135 } 5136 } 5137 5138 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5139 &base_vha->dpc_flags)) { 5140 5141 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5142 "FCoE context reset scheduled.\n"); 5143 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5144 &base_vha->dpc_flags))) { 5145 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5146 /* FCoE-ctx reset failed. 5147 * Escalate to chip-reset 5148 */ 5149 set_bit(ISP_ABORT_NEEDED, 5150 &base_vha->dpc_flags); 5151 } 5152 clear_bit(ABORT_ISP_ACTIVE, 5153 &base_vha->dpc_flags); 5154 } 5155 5156 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5157 "FCoE context reset end.\n"); 5158 } 5159 } else if (IS_QLAFX00(ha)) { 5160 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5161 &base_vha->dpc_flags)) { 5162 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5163 "Firmware Reset Recovery\n"); 5164 if (qlafx00_reset_initialize(base_vha)) { 5165 /* Failed. Abort isp later. */ 5166 if (!test_bit(UNLOADING, 5167 &base_vha->dpc_flags)) { 5168 set_bit(ISP_UNRECOVERABLE, 5169 &base_vha->dpc_flags); 5170 ql_dbg(ql_dbg_dpc, base_vha, 5171 0x4021, 5172 "Reset Recovery Failed\n"); 5173 } 5174 } 5175 } 5176 5177 if (test_and_clear_bit(FX00_TARGET_SCAN, 5178 &base_vha->dpc_flags)) { 5179 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5180 "ISPFx00 Target Scan scheduled\n"); 5181 if (qlafx00_rescan_isp(base_vha)) { 5182 if (!test_bit(UNLOADING, 5183 &base_vha->dpc_flags)) 5184 set_bit(ISP_UNRECOVERABLE, 5185 &base_vha->dpc_flags); 5186 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5187 "ISPFx00 Target Scan Failed\n"); 5188 } 5189 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5190 "ISPFx00 Target Scan End\n"); 5191 } 5192 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5193 &base_vha->dpc_flags)) { 5194 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5195 "ISPFx00 Host Info resend scheduled\n"); 5196 qlafx00_fx_disc(base_vha, 5197 &base_vha->hw->mr.fcport, 5198 FXDISC_REG_HOST_INFO); 5199 } 5200 } 5201 5202 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5203 &base_vha->dpc_flags)) { 5204 5205 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5206 "ISP abort scheduled.\n"); 5207 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5208 &base_vha->dpc_flags))) { 5209 5210 if (ha->isp_ops->abort_isp(base_vha)) { 5211 /* failed. retry later */ 5212 set_bit(ISP_ABORT_NEEDED, 5213 &base_vha->dpc_flags); 5214 } 5215 clear_bit(ABORT_ISP_ACTIVE, 5216 &base_vha->dpc_flags); 5217 } 5218 5219 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5220 "ISP abort end.\n"); 5221 } 5222 5223 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5224 &base_vha->dpc_flags)) { 5225 qla2x00_update_fcports(base_vha); 5226 } 5227 5228 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 5229 int ret; 5230 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 5231 if (ret != QLA_SUCCESS) 5232 ql_log(ql_log_warn, base_vha, 0x121, 5233 "Failed to enable receiving of RSCN " 5234 "requests: 0x%x.\n", ret); 5235 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 5236 } 5237 5238 if (IS_QLAFX00(ha)) 5239 goto loop_resync_check; 5240 5241 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5242 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5243 "Quiescence mode scheduled.\n"); 5244 if (IS_P3P_TYPE(ha)) { 5245 if (IS_QLA82XX(ha)) 5246 qla82xx_device_state_handler(base_vha); 5247 if (IS_QLA8044(ha)) 5248 qla8044_device_state_handler(base_vha); 5249 clear_bit(ISP_QUIESCE_NEEDED, 5250 &base_vha->dpc_flags); 5251 if (!ha->flags.quiesce_owner) { 5252 qla2x00_perform_loop_resync(base_vha); 5253 if (IS_QLA82XX(ha)) { 5254 qla82xx_idc_lock(ha); 5255 qla82xx_clear_qsnt_ready( 5256 base_vha); 5257 qla82xx_idc_unlock(ha); 5258 } else if (IS_QLA8044(ha)) { 5259 qla8044_idc_lock(ha); 5260 qla8044_clear_qsnt_ready( 5261 base_vha); 5262 qla8044_idc_unlock(ha); 5263 } 5264 } 5265 } else { 5266 clear_bit(ISP_QUIESCE_NEEDED, 5267 &base_vha->dpc_flags); 5268 qla2x00_quiesce_io(base_vha); 5269 } 5270 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5271 "Quiescence mode end.\n"); 5272 } 5273 5274 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5275 &base_vha->dpc_flags) && 5276 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5277 5278 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5279 "Reset marker scheduled.\n"); 5280 qla2x00_rst_aen(base_vha); 5281 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5282 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5283 "Reset marker end.\n"); 5284 } 5285 5286 /* Retry each device up to login retry count */ 5287 if ((test_and_clear_bit(RELOGIN_NEEDED, 5288 &base_vha->dpc_flags)) && 5289 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5290 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5291 5292 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5293 "Relogin scheduled.\n"); 5294 qla2x00_relogin(base_vha); 5295 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5296 "Relogin end.\n"); 5297 } 5298 loop_resync_check: 5299 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5300 &base_vha->dpc_flags)) { 5301 5302 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5303 "Loop resync scheduled.\n"); 5304 5305 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5306 &base_vha->dpc_flags))) { 5307 5308 qla2x00_loop_resync(base_vha); 5309 5310 clear_bit(LOOP_RESYNC_ACTIVE, 5311 &base_vha->dpc_flags); 5312 } 5313 5314 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5315 "Loop resync end.\n"); 5316 } 5317 5318 if (IS_QLAFX00(ha)) 5319 goto intr_on_check; 5320 5321 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5322 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5323 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5324 qla2xxx_flash_npiv_conf(base_vha); 5325 } 5326 5327 intr_on_check: 5328 if (!ha->interrupts_on) 5329 ha->isp_ops->enable_intrs(ha); 5330 5331 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5332 &base_vha->dpc_flags)) { 5333 if (ha->beacon_blink_led == 1) 5334 ha->isp_ops->beacon_blink(base_vha); 5335 } 5336 5337 if (!IS_QLAFX00(ha)) 5338 qla2x00_do_dpc_all_vps(base_vha); 5339 5340 ha->dpc_active = 0; 5341 end_loop: 5342 set_current_state(TASK_INTERRUPTIBLE); 5343 } /* End of while(1) */ 5344 __set_current_state(TASK_RUNNING); 5345 5346 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5347 "DPC handler exiting.\n"); 5348 5349 /* 5350 * Make sure that nobody tries to wake us up again. 5351 */ 5352 ha->dpc_active = 0; 5353 5354 /* Cleanup any residual CTX SRBs. */ 5355 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5356 5357 return 0; 5358 } 5359 5360 void 5361 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5362 { 5363 struct qla_hw_data *ha = vha->hw; 5364 struct task_struct *t = ha->dpc_thread; 5365 5366 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5367 wake_up_process(t); 5368 } 5369 5370 /* 5371 * qla2x00_rst_aen 5372 * Processes asynchronous reset. 5373 * 5374 * Input: 5375 * ha = adapter block pointer. 5376 */ 5377 static void 5378 qla2x00_rst_aen(scsi_qla_host_t *vha) 5379 { 5380 if (vha->flags.online && !vha->flags.reset_active && 5381 !atomic_read(&vha->loop_down_timer) && 5382 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5383 do { 5384 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5385 5386 /* 5387 * Issue marker command only when we are going to start 5388 * the I/O. 5389 */ 5390 vha->marker_needed = 1; 5391 } while (!atomic_read(&vha->loop_down_timer) && 5392 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5393 } 5394 } 5395 5396 /************************************************************************** 5397 * qla2x00_timer 5398 * 5399 * Description: 5400 * One second timer 5401 * 5402 * Context: Interrupt 5403 ***************************************************************************/ 5404 void 5405 qla2x00_timer(scsi_qla_host_t *vha) 5406 { 5407 unsigned long cpu_flags = 0; 5408 int start_dpc = 0; 5409 int index; 5410 srb_t *sp; 5411 uint16_t w; 5412 struct qla_hw_data *ha = vha->hw; 5413 struct req_que *req; 5414 5415 if (ha->flags.eeh_busy) { 5416 ql_dbg(ql_dbg_timer, vha, 0x6000, 5417 "EEH = %d, restarting timer.\n", 5418 ha->flags.eeh_busy); 5419 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5420 return; 5421 } 5422 5423 /* 5424 * Hardware read to raise pending EEH errors during mailbox waits. If 5425 * the read returns -1 then disable the board. 5426 */ 5427 if (!pci_channel_offline(ha->pdev)) { 5428 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5429 qla2x00_check_reg16_for_disconnect(vha, w); 5430 } 5431 5432 /* Make sure qla82xx_watchdog is run only for physical port */ 5433 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5434 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5435 start_dpc++; 5436 if (IS_QLA82XX(ha)) 5437 qla82xx_watchdog(vha); 5438 else if (IS_QLA8044(ha)) 5439 qla8044_watchdog(vha); 5440 } 5441 5442 if (!vha->vp_idx && IS_QLAFX00(ha)) 5443 qlafx00_timer_routine(vha); 5444 5445 /* Loop down handler. */ 5446 if (atomic_read(&vha->loop_down_timer) > 0 && 5447 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5448 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5449 && vha->flags.online) { 5450 5451 if (atomic_read(&vha->loop_down_timer) == 5452 vha->loop_down_abort_time) { 5453 5454 ql_log(ql_log_info, vha, 0x6008, 5455 "Loop down - aborting the queues before time expires.\n"); 5456 5457 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5458 atomic_set(&vha->loop_state, LOOP_DEAD); 5459 5460 /* 5461 * Schedule an ISP abort to return any FCP2-device 5462 * commands. 5463 */ 5464 /* NPIV - scan physical port only */ 5465 if (!vha->vp_idx) { 5466 spin_lock_irqsave(&ha->hardware_lock, 5467 cpu_flags); 5468 req = ha->req_q_map[0]; 5469 for (index = 1; 5470 index < req->num_outstanding_cmds; 5471 index++) { 5472 fc_port_t *sfcp; 5473 5474 sp = req->outstanding_cmds[index]; 5475 if (!sp) 5476 continue; 5477 if (sp->type != SRB_SCSI_CMD) 5478 continue; 5479 sfcp = sp->fcport; 5480 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5481 continue; 5482 5483 if (IS_QLA82XX(ha)) 5484 set_bit(FCOE_CTX_RESET_NEEDED, 5485 &vha->dpc_flags); 5486 else 5487 set_bit(ISP_ABORT_NEEDED, 5488 &vha->dpc_flags); 5489 break; 5490 } 5491 spin_unlock_irqrestore(&ha->hardware_lock, 5492 cpu_flags); 5493 } 5494 start_dpc++; 5495 } 5496 5497 /* if the loop has been down for 4 minutes, reinit adapter */ 5498 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5499 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5500 ql_log(ql_log_warn, vha, 0x6009, 5501 "Loop down - aborting ISP.\n"); 5502 5503 if (IS_QLA82XX(ha)) 5504 set_bit(FCOE_CTX_RESET_NEEDED, 5505 &vha->dpc_flags); 5506 else 5507 set_bit(ISP_ABORT_NEEDED, 5508 &vha->dpc_flags); 5509 } 5510 } 5511 ql_dbg(ql_dbg_timer, vha, 0x600a, 5512 "Loop down - seconds remaining %d.\n", 5513 atomic_read(&vha->loop_down_timer)); 5514 } 5515 /* Check if beacon LED needs to be blinked for physical host only */ 5516 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5517 /* There is no beacon_blink function for ISP82xx */ 5518 if (!IS_P3P_TYPE(ha)) { 5519 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5520 start_dpc++; 5521 } 5522 } 5523 5524 /* Process any deferred work. */ 5525 if (!list_empty(&vha->work_list)) 5526 start_dpc++; 5527 5528 /* Schedule the DPC routine if needed */ 5529 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5530 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5531 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5532 start_dpc || 5533 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5534 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5535 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5536 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5537 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5538 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5539 ql_dbg(ql_dbg_timer, vha, 0x600b, 5540 "isp_abort_needed=%d loop_resync_needed=%d " 5541 "fcport_update_needed=%d start_dpc=%d " 5542 "reset_marker_needed=%d", 5543 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5544 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5545 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5546 start_dpc, 5547 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5548 ql_dbg(ql_dbg_timer, vha, 0x600c, 5549 "beacon_blink_needed=%d isp_unrecoverable=%d " 5550 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5551 "relogin_needed=%d.\n", 5552 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5553 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5554 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5555 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5556 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5557 qla2xxx_wake_dpc(vha); 5558 } 5559 5560 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5561 } 5562 5563 /* Firmware interface routines. */ 5564 5565 #define FW_BLOBS 11 5566 #define FW_ISP21XX 0 5567 #define FW_ISP22XX 1 5568 #define FW_ISP2300 2 5569 #define FW_ISP2322 3 5570 #define FW_ISP24XX 4 5571 #define FW_ISP25XX 5 5572 #define FW_ISP81XX 6 5573 #define FW_ISP82XX 7 5574 #define FW_ISP2031 8 5575 #define FW_ISP8031 9 5576 #define FW_ISP27XX 10 5577 5578 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5579 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5580 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5581 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5582 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5583 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5584 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5585 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5586 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5587 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5588 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5589 5590 5591 static DEFINE_MUTEX(qla_fw_lock); 5592 5593 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5594 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5595 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5596 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5597 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5598 { .name = FW_FILE_ISP24XX, }, 5599 { .name = FW_FILE_ISP25XX, }, 5600 { .name = FW_FILE_ISP81XX, }, 5601 { .name = FW_FILE_ISP82XX, }, 5602 { .name = FW_FILE_ISP2031, }, 5603 { .name = FW_FILE_ISP8031, }, 5604 { .name = FW_FILE_ISP27XX, }, 5605 }; 5606 5607 struct fw_blob * 5608 qla2x00_request_firmware(scsi_qla_host_t *vha) 5609 { 5610 struct qla_hw_data *ha = vha->hw; 5611 struct fw_blob *blob; 5612 5613 if (IS_QLA2100(ha)) { 5614 blob = &qla_fw_blobs[FW_ISP21XX]; 5615 } else if (IS_QLA2200(ha)) { 5616 blob = &qla_fw_blobs[FW_ISP22XX]; 5617 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5618 blob = &qla_fw_blobs[FW_ISP2300]; 5619 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5620 blob = &qla_fw_blobs[FW_ISP2322]; 5621 } else if (IS_QLA24XX_TYPE(ha)) { 5622 blob = &qla_fw_blobs[FW_ISP24XX]; 5623 } else if (IS_QLA25XX(ha)) { 5624 blob = &qla_fw_blobs[FW_ISP25XX]; 5625 } else if (IS_QLA81XX(ha)) { 5626 blob = &qla_fw_blobs[FW_ISP81XX]; 5627 } else if (IS_QLA82XX(ha)) { 5628 blob = &qla_fw_blobs[FW_ISP82XX]; 5629 } else if (IS_QLA2031(ha)) { 5630 blob = &qla_fw_blobs[FW_ISP2031]; 5631 } else if (IS_QLA8031(ha)) { 5632 blob = &qla_fw_blobs[FW_ISP8031]; 5633 } else if (IS_QLA27XX(ha)) { 5634 blob = &qla_fw_blobs[FW_ISP27XX]; 5635 } else { 5636 return NULL; 5637 } 5638 5639 mutex_lock(&qla_fw_lock); 5640 if (blob->fw) 5641 goto out; 5642 5643 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5644 ql_log(ql_log_warn, vha, 0x0063, 5645 "Failed to load firmware image (%s).\n", blob->name); 5646 blob->fw = NULL; 5647 blob = NULL; 5648 goto out; 5649 } 5650 5651 out: 5652 mutex_unlock(&qla_fw_lock); 5653 return blob; 5654 } 5655 5656 static void 5657 qla2x00_release_firmware(void) 5658 { 5659 int idx; 5660 5661 mutex_lock(&qla_fw_lock); 5662 for (idx = 0; idx < FW_BLOBS; idx++) 5663 release_firmware(qla_fw_blobs[idx].fw); 5664 mutex_unlock(&qla_fw_lock); 5665 } 5666 5667 static pci_ers_result_t 5668 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5669 { 5670 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5671 struct qla_hw_data *ha = vha->hw; 5672 5673 ql_dbg(ql_dbg_aer, vha, 0x9000, 5674 "PCI error detected, state %x.\n", state); 5675 5676 switch (state) { 5677 case pci_channel_io_normal: 5678 ha->flags.eeh_busy = 0; 5679 return PCI_ERS_RESULT_CAN_RECOVER; 5680 case pci_channel_io_frozen: 5681 ha->flags.eeh_busy = 1; 5682 /* For ISP82XX complete any pending mailbox cmd */ 5683 if (IS_QLA82XX(ha)) { 5684 ha->flags.isp82xx_fw_hung = 1; 5685 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5686 qla82xx_clear_pending_mbx(vha); 5687 } 5688 qla2x00_free_irqs(vha); 5689 pci_disable_device(pdev); 5690 /* Return back all IOs */ 5691 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5692 return PCI_ERS_RESULT_NEED_RESET; 5693 case pci_channel_io_perm_failure: 5694 ha->flags.pci_channel_io_perm_failure = 1; 5695 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5696 return PCI_ERS_RESULT_DISCONNECT; 5697 } 5698 return PCI_ERS_RESULT_NEED_RESET; 5699 } 5700 5701 static pci_ers_result_t 5702 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5703 { 5704 int risc_paused = 0; 5705 uint32_t stat; 5706 unsigned long flags; 5707 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5708 struct qla_hw_data *ha = base_vha->hw; 5709 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5710 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5711 5712 if (IS_QLA82XX(ha)) 5713 return PCI_ERS_RESULT_RECOVERED; 5714 5715 spin_lock_irqsave(&ha->hardware_lock, flags); 5716 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5717 stat = RD_REG_DWORD(®->hccr); 5718 if (stat & HCCR_RISC_PAUSE) 5719 risc_paused = 1; 5720 } else if (IS_QLA23XX(ha)) { 5721 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5722 if (stat & HSR_RISC_PAUSED) 5723 risc_paused = 1; 5724 } else if (IS_FWI2_CAPABLE(ha)) { 5725 stat = RD_REG_DWORD(®24->host_status); 5726 if (stat & HSRX_RISC_PAUSED) 5727 risc_paused = 1; 5728 } 5729 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5730 5731 if (risc_paused) { 5732 ql_log(ql_log_info, base_vha, 0x9003, 5733 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5734 ha->isp_ops->fw_dump(base_vha, 0); 5735 5736 return PCI_ERS_RESULT_NEED_RESET; 5737 } else 5738 return PCI_ERS_RESULT_RECOVERED; 5739 } 5740 5741 static uint32_t 5742 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5743 { 5744 uint32_t rval = QLA_FUNCTION_FAILED; 5745 uint32_t drv_active = 0; 5746 struct qla_hw_data *ha = base_vha->hw; 5747 int fn; 5748 struct pci_dev *other_pdev = NULL; 5749 5750 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5751 "Entered %s.\n", __func__); 5752 5753 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5754 5755 if (base_vha->flags.online) { 5756 /* Abort all outstanding commands, 5757 * so as to be requeued later */ 5758 qla2x00_abort_isp_cleanup(base_vha); 5759 } 5760 5761 5762 fn = PCI_FUNC(ha->pdev->devfn); 5763 while (fn > 0) { 5764 fn--; 5765 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5766 "Finding pci device at function = 0x%x.\n", fn); 5767 other_pdev = 5768 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5769 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5770 fn)); 5771 5772 if (!other_pdev) 5773 continue; 5774 if (atomic_read(&other_pdev->enable_cnt)) { 5775 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5776 "Found PCI func available and enable at 0x%x.\n", 5777 fn); 5778 pci_dev_put(other_pdev); 5779 break; 5780 } 5781 pci_dev_put(other_pdev); 5782 } 5783 5784 if (!fn) { 5785 /* Reset owner */ 5786 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5787 "This devfn is reset owner = 0x%x.\n", 5788 ha->pdev->devfn); 5789 qla82xx_idc_lock(ha); 5790 5791 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5792 QLA8XXX_DEV_INITIALIZING); 5793 5794 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5795 QLA82XX_IDC_VERSION); 5796 5797 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5798 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5799 "drv_active = 0x%x.\n", drv_active); 5800 5801 qla82xx_idc_unlock(ha); 5802 /* Reset if device is not already reset 5803 * drv_active would be 0 if a reset has already been done 5804 */ 5805 if (drv_active) 5806 rval = qla82xx_start_firmware(base_vha); 5807 else 5808 rval = QLA_SUCCESS; 5809 qla82xx_idc_lock(ha); 5810 5811 if (rval != QLA_SUCCESS) { 5812 ql_log(ql_log_info, base_vha, 0x900b, 5813 "HW State: FAILED.\n"); 5814 qla82xx_clear_drv_active(ha); 5815 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5816 QLA8XXX_DEV_FAILED); 5817 } else { 5818 ql_log(ql_log_info, base_vha, 0x900c, 5819 "HW State: READY.\n"); 5820 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5821 QLA8XXX_DEV_READY); 5822 qla82xx_idc_unlock(ha); 5823 ha->flags.isp82xx_fw_hung = 0; 5824 rval = qla82xx_restart_isp(base_vha); 5825 qla82xx_idc_lock(ha); 5826 /* Clear driver state register */ 5827 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5828 qla82xx_set_drv_active(base_vha); 5829 } 5830 qla82xx_idc_unlock(ha); 5831 } else { 5832 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5833 "This devfn is not reset owner = 0x%x.\n", 5834 ha->pdev->devfn); 5835 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5836 QLA8XXX_DEV_READY)) { 5837 ha->flags.isp82xx_fw_hung = 0; 5838 rval = qla82xx_restart_isp(base_vha); 5839 qla82xx_idc_lock(ha); 5840 qla82xx_set_drv_active(base_vha); 5841 qla82xx_idc_unlock(ha); 5842 } 5843 } 5844 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5845 5846 return rval; 5847 } 5848 5849 static pci_ers_result_t 5850 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5851 { 5852 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5853 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5854 struct qla_hw_data *ha = base_vha->hw; 5855 struct rsp_que *rsp; 5856 int rc, retries = 10; 5857 5858 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5859 "Slot Reset.\n"); 5860 5861 /* Workaround: qla2xxx driver which access hardware earlier 5862 * needs error state to be pci_channel_io_online. 5863 * Otherwise mailbox command timesout. 5864 */ 5865 pdev->error_state = pci_channel_io_normal; 5866 5867 pci_restore_state(pdev); 5868 5869 /* pci_restore_state() clears the saved_state flag of the device 5870 * save restored state which resets saved_state flag 5871 */ 5872 pci_save_state(pdev); 5873 5874 if (ha->mem_only) 5875 rc = pci_enable_device_mem(pdev); 5876 else 5877 rc = pci_enable_device(pdev); 5878 5879 if (rc) { 5880 ql_log(ql_log_warn, base_vha, 0x9005, 5881 "Can't re-enable PCI device after reset.\n"); 5882 goto exit_slot_reset; 5883 } 5884 5885 rsp = ha->rsp_q_map[0]; 5886 if (qla2x00_request_irqs(ha, rsp)) 5887 goto exit_slot_reset; 5888 5889 if (ha->isp_ops->pci_config(base_vha)) 5890 goto exit_slot_reset; 5891 5892 if (IS_QLA82XX(ha)) { 5893 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5894 ret = PCI_ERS_RESULT_RECOVERED; 5895 goto exit_slot_reset; 5896 } else 5897 goto exit_slot_reset; 5898 } 5899 5900 while (ha->flags.mbox_busy && retries--) 5901 msleep(1000); 5902 5903 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5904 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5905 ret = PCI_ERS_RESULT_RECOVERED; 5906 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5907 5908 5909 exit_slot_reset: 5910 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5911 "slot_reset return %x.\n", ret); 5912 5913 return ret; 5914 } 5915 5916 static void 5917 qla2xxx_pci_resume(struct pci_dev *pdev) 5918 { 5919 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5920 struct qla_hw_data *ha = base_vha->hw; 5921 int ret; 5922 5923 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5924 "pci_resume.\n"); 5925 5926 ret = qla2x00_wait_for_hba_online(base_vha); 5927 if (ret != QLA_SUCCESS) { 5928 ql_log(ql_log_fatal, base_vha, 0x9002, 5929 "The device failed to resume I/O from slot/link_reset.\n"); 5930 } 5931 5932 pci_cleanup_aer_uncorrect_error_status(pdev); 5933 5934 ha->flags.eeh_busy = 0; 5935 } 5936 5937 static void 5938 qla83xx_disable_laser(scsi_qla_host_t *vha) 5939 { 5940 uint32_t reg, data, fn; 5941 struct qla_hw_data *ha = vha->hw; 5942 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5943 5944 /* pci func #/port # */ 5945 ql_dbg(ql_dbg_init, vha, 0x004b, 5946 "Disabling Laser for hba: %p\n", vha); 5947 5948 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5949 (BIT_15|BIT_14|BIT_13|BIT_12)); 5950 5951 fn = (fn >> 12); 5952 5953 if (fn & 1) 5954 reg = PORT_1_2031; 5955 else 5956 reg = PORT_0_2031; 5957 5958 data = LASER_OFF_2031; 5959 5960 qla83xx_wr_reg(vha, reg, data); 5961 } 5962 5963 static const struct pci_error_handlers qla2xxx_err_handler = { 5964 .error_detected = qla2xxx_pci_error_detected, 5965 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5966 .slot_reset = qla2xxx_pci_slot_reset, 5967 .resume = qla2xxx_pci_resume, 5968 }; 5969 5970 static struct pci_device_id qla2xxx_pci_tbl[] = { 5971 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5972 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5973 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5974 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5975 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5976 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5985 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5986 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5987 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5988 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5989 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5990 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5991 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5992 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 5993 { 0 }, 5994 }; 5995 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5996 5997 static struct pci_driver qla2xxx_pci_driver = { 5998 .name = QLA2XXX_DRIVER_NAME, 5999 .driver = { 6000 .owner = THIS_MODULE, 6001 }, 6002 .id_table = qla2xxx_pci_tbl, 6003 .probe = qla2x00_probe_one, 6004 .remove = qla2x00_remove_one, 6005 .shutdown = qla2x00_shutdown, 6006 .err_handler = &qla2xxx_err_handler, 6007 }; 6008 6009 static const struct file_operations apidev_fops = { 6010 .owner = THIS_MODULE, 6011 .llseek = noop_llseek, 6012 }; 6013 6014 /** 6015 * qla2x00_module_init - Module initialization. 6016 **/ 6017 static int __init 6018 qla2x00_module_init(void) 6019 { 6020 int ret = 0; 6021 6022 /* Allocate cache for SRBs. */ 6023 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6024 SLAB_HWCACHE_ALIGN, NULL); 6025 if (srb_cachep == NULL) { 6026 ql_log(ql_log_fatal, NULL, 0x0001, 6027 "Unable to allocate SRB cache...Failing load!.\n"); 6028 return -ENOMEM; 6029 } 6030 6031 /* Initialize target kmem_cache and mem_pools */ 6032 ret = qlt_init(); 6033 if (ret < 0) { 6034 kmem_cache_destroy(srb_cachep); 6035 return ret; 6036 } else if (ret > 0) { 6037 /* 6038 * If initiator mode is explictly disabled by qlt_init(), 6039 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6040 * performing scsi_scan_target() during LOOP UP event. 6041 */ 6042 qla2xxx_transport_functions.disable_target_scan = 1; 6043 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6044 } 6045 6046 /* Derive version string. */ 6047 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6048 if (ql2xextended_error_logging) 6049 strcat(qla2x00_version_str, "-debug"); 6050 6051 qla2xxx_transport_template = 6052 fc_attach_transport(&qla2xxx_transport_functions); 6053 if (!qla2xxx_transport_template) { 6054 kmem_cache_destroy(srb_cachep); 6055 ql_log(ql_log_fatal, NULL, 0x0002, 6056 "fc_attach_transport failed...Failing load!.\n"); 6057 qlt_exit(); 6058 return -ENODEV; 6059 } 6060 6061 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6062 if (apidev_major < 0) { 6063 ql_log(ql_log_fatal, NULL, 0x0003, 6064 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6065 } 6066 6067 qla2xxx_transport_vport_template = 6068 fc_attach_transport(&qla2xxx_transport_vport_functions); 6069 if (!qla2xxx_transport_vport_template) { 6070 kmem_cache_destroy(srb_cachep); 6071 qlt_exit(); 6072 fc_release_transport(qla2xxx_transport_template); 6073 ql_log(ql_log_fatal, NULL, 0x0004, 6074 "fc_attach_transport vport failed...Failing load!.\n"); 6075 return -ENODEV; 6076 } 6077 ql_log(ql_log_info, NULL, 0x0005, 6078 "QLogic Fibre Channel HBA Driver: %s.\n", 6079 qla2x00_version_str); 6080 ret = pci_register_driver(&qla2xxx_pci_driver); 6081 if (ret) { 6082 kmem_cache_destroy(srb_cachep); 6083 qlt_exit(); 6084 fc_release_transport(qla2xxx_transport_template); 6085 fc_release_transport(qla2xxx_transport_vport_template); 6086 ql_log(ql_log_fatal, NULL, 0x0006, 6087 "pci_register_driver failed...ret=%d Failing load!.\n", 6088 ret); 6089 } 6090 return ret; 6091 } 6092 6093 /** 6094 * qla2x00_module_exit - Module cleanup. 6095 **/ 6096 static void __exit 6097 qla2x00_module_exit(void) 6098 { 6099 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6100 pci_unregister_driver(&qla2xxx_pci_driver); 6101 qla2x00_release_firmware(); 6102 kmem_cache_destroy(srb_cachep); 6103 qlt_exit(); 6104 if (ctx_cachep) 6105 kmem_cache_destroy(ctx_cachep); 6106 fc_release_transport(qla2xxx_transport_template); 6107 fc_release_transport(qla2xxx_transport_vport_template); 6108 } 6109 6110 module_init(qla2x00_module_init); 6111 module_exit(qla2x00_module_exit); 6112 6113 MODULE_AUTHOR("QLogic Corporation"); 6114 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6115 MODULE_LICENSE("GPL"); 6116 MODULE_VERSION(QLA2XXX_VERSION); 6117 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6118 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6119 MODULE_FIRMWARE(FW_FILE_ISP2300); 6120 MODULE_FIRMWARE(FW_FILE_ISP2322); 6121 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6122 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6123