1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 uint ql_errlev = 0x8001; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable = 1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI. Default is 1 - perform FDMI."); 117 118 #define MAX_Q_DEPTH 64 119 static int ql2xmaxqdepth = MAX_Q_DEPTH; 120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xmaxqdepth, 122 "Maximum queue depth to set for each LUN. " 123 "Default is 64."); 124 125 #if (IS_ENABLED(CONFIG_NVME_FC)) 126 int ql2xenabledif; 127 #else 128 int ql2xenabledif = 2; 129 #endif 130 module_param(ql2xenabledif, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xenabledif, 132 " Enable T10-CRC-DIF:\n" 133 " Default is 2.\n" 134 " 0 -- No DIF Support\n" 135 " 1 -- Enable DIF for all types\n" 136 " 2 -- Enable DIF for all types, except Type 0.\n"); 137 138 #if (IS_ENABLED(CONFIG_NVME_FC)) 139 int ql2xnvmeenable = 1; 140 #else 141 int ql2xnvmeenable; 142 #endif 143 module_param(ql2xnvmeenable, int, 0644); 144 MODULE_PARM_DESC(ql2xnvmeenable, 145 "Enables NVME support. " 146 "0 - no NVMe. Default is Y"); 147 148 int ql2xenablehba_err_chk = 2; 149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xenablehba_err_chk, 151 " Enable T10-CRC-DIF Error isolation by HBA:\n" 152 " Default is 2.\n" 153 " 0 -- Error isolation disabled\n" 154 " 1 -- Error isolation enabled only for DIX Type 0\n" 155 " 2 -- Error isolation enabled for all Types\n"); 156 157 int ql2xiidmaenable = 1; 158 module_param(ql2xiidmaenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xiidmaenable, 160 "Enables iIDMA settings " 161 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 162 163 int ql2xmqsupport = 1; 164 module_param(ql2xmqsupport, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xmqsupport, 166 "Enable on demand multiple queue pairs support " 167 "Default is 1 for supported. " 168 "Set it to 0 to turn off mq qpair support."); 169 170 int ql2xfwloadbin; 171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xfwloadbin, 174 "Option to specify location from which to load ISP firmware:.\n" 175 " 2 -- load firmware via the request_firmware() (hotplug).\n" 176 " interface.\n" 177 " 1 -- load firmware from flash.\n" 178 " 0 -- use default semantics.\n"); 179 180 int ql2xetsenable; 181 module_param(ql2xetsenable, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xetsenable, 183 "Enables firmware ETS burst." 184 "Default is 0 - skip ETS enablement."); 185 186 int ql2xdbwr = 1; 187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 188 MODULE_PARM_DESC(ql2xdbwr, 189 "Option to specify scheme for request queue posting.\n" 190 " 0 -- Regular doorbell.\n" 191 " 1 -- CAMRAM doorbell (faster).\n"); 192 193 int ql2xtargetreset = 1; 194 module_param(ql2xtargetreset, int, S_IRUGO); 195 MODULE_PARM_DESC(ql2xtargetreset, 196 "Enable target reset." 197 "Default is 1 - use hw defaults."); 198 199 int ql2xgffidenable; 200 module_param(ql2xgffidenable, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xgffidenable, 202 "Enables GFF_ID checks of port type. " 203 "Default is 0 - Do not use GFF_ID information."); 204 205 int ql2xasynctmfenable = 1; 206 module_param(ql2xasynctmfenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xasynctmfenable, 208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 210 211 int ql2xdontresethba; 212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 213 MODULE_PARM_DESC(ql2xdontresethba, 214 "Option to specify reset behaviour.\n" 215 " 0 (Default) -- Reset on failure.\n" 216 " 1 -- Do not reset on failure.\n"); 217 218 uint64_t ql2xmaxlun = MAX_LUNS; 219 module_param(ql2xmaxlun, ullong, S_IRUGO); 220 MODULE_PARM_DESC(ql2xmaxlun, 221 "Defines the maximum LU number to register with the SCSI " 222 "midlayer. Default is 65535."); 223 224 int ql2xmdcapmask = 0x1F; 225 module_param(ql2xmdcapmask, int, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmdcapmask, 227 "Set the Minidump driver capture mask level. " 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 229 230 int ql2xmdenable = 1; 231 module_param(ql2xmdenable, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdenable, 233 "Enable/disable MiniDump. " 234 "0 - MiniDump disabled. " 235 "1 (Default) - MiniDump enabled."); 236 237 int ql2xexlogins; 238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 239 MODULE_PARM_DESC(ql2xexlogins, 240 "Number of extended Logins. " 241 "0 (Default)- Disabled."); 242 243 int ql2xexchoffld = 1024; 244 module_param(ql2xexchoffld, uint, 0644); 245 MODULE_PARM_DESC(ql2xexchoffld, 246 "Number of target exchanges."); 247 248 int ql2xiniexchg = 1024; 249 module_param(ql2xiniexchg, uint, 0644); 250 MODULE_PARM_DESC(ql2xiniexchg, 251 "Number of initiator exchanges."); 252 253 int ql2xfwholdabts; 254 module_param(ql2xfwholdabts, int, S_IRUGO); 255 MODULE_PARM_DESC(ql2xfwholdabts, 256 "Allow FW to hold status IOCB until ABTS rsp received. " 257 "0 (Default) Do not set fw option. " 258 "1 - Set fw option to hold ABTS."); 259 260 int ql2xmvasynctoatio = 1; 261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 262 MODULE_PARM_DESC(ql2xmvasynctoatio, 263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 264 "0 (Default). Do not move IOCBs" 265 "1 - Move IOCBs."); 266 267 int ql2xautodetectsfp = 1; 268 module_param(ql2xautodetectsfp, int, 0444); 269 MODULE_PARM_DESC(ql2xautodetectsfp, 270 "Detect SFP range and set appropriate distance.\n" 271 "1 (Default): Enable\n"); 272 273 int ql2xenablemsix = 1; 274 module_param(ql2xenablemsix, int, 0444); 275 MODULE_PARM_DESC(ql2xenablemsix, 276 "Set to enable MSI or MSI-X interrupt mechanism.\n" 277 " Default is 1, enable MSI-X interrupt mechanism.\n" 278 " 0 -- enable traditional pin-based mechanism.\n" 279 " 1 -- enable MSI-X interrupt mechanism.\n" 280 " 2 -- enable MSI interrupt mechanism.\n"); 281 282 int qla2xuseresexchforels; 283 module_param(qla2xuseresexchforels, int, 0444); 284 MODULE_PARM_DESC(qla2xuseresexchforels, 285 "Reserve 1/2 of emergency exchanges for ELS.\n" 286 " 0 (default): disabled"); 287 288 static int ql2xprotmask; 289 module_param(ql2xprotmask, int, 0644); 290 MODULE_PARM_DESC(ql2xprotmask, 291 "Override DIF/DIX protection capabilities mask\n" 292 "Default is 0 which sets protection mask based on " 293 "capabilities reported by HBA firmware.\n"); 294 295 static int ql2xprotguard; 296 module_param(ql2xprotguard, int, 0644); 297 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 298 " 0 -- Let HBA firmware decide\n" 299 " 1 -- Force T10 CRC\n" 300 " 2 -- Force IP checksum\n"); 301 302 int ql2xdifbundlinginternalbuffers; 303 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 304 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 305 "Force using internal buffers for DIF information\n" 306 "0 (Default). Based on check.\n" 307 "1 Force using internal buffers\n"); 308 309 static void qla2x00_clear_drv_active(struct qla_hw_data *); 310 static void qla2x00_free_device(scsi_qla_host_t *); 311 static int qla2xxx_map_queues(struct Scsi_Host *shost); 312 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 313 314 315 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 316 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 317 318 /* TODO Convert to inlines 319 * 320 * Timer routines 321 */ 322 323 __inline__ void 324 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 325 { 326 timer_setup(&vha->timer, qla2x00_timer, 0); 327 vha->timer.expires = jiffies + interval * HZ; 328 add_timer(&vha->timer); 329 vha->timer_active = 1; 330 } 331 332 static inline void 333 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 334 { 335 /* Currently used for 82XX only. */ 336 if (vha->device_flags & DFLG_DEV_FAILED) { 337 ql_dbg(ql_dbg_timer, vha, 0x600d, 338 "Device in a failed state, returning.\n"); 339 return; 340 } 341 342 mod_timer(&vha->timer, jiffies + interval * HZ); 343 } 344 345 static __inline__ void 346 qla2x00_stop_timer(scsi_qla_host_t *vha) 347 { 348 del_timer_sync(&vha->timer); 349 vha->timer_active = 0; 350 } 351 352 static int qla2x00_do_dpc(void *data); 353 354 static void qla2x00_rst_aen(scsi_qla_host_t *); 355 356 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 357 struct req_que **, struct rsp_que **); 358 static void qla2x00_free_fw_dump(struct qla_hw_data *); 359 static void qla2x00_mem_free(struct qla_hw_data *); 360 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 361 struct qla_qpair *qpair); 362 363 /* -------------------------------------------------------------------------- */ 364 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 365 struct rsp_que *rsp) 366 { 367 struct qla_hw_data *ha = vha->hw; 368 369 rsp->qpair = ha->base_qpair; 370 rsp->req = req; 371 ha->base_qpair->hw = ha; 372 ha->base_qpair->req = req; 373 ha->base_qpair->rsp = rsp; 374 ha->base_qpair->vha = vha; 375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 378 ha->base_qpair->srb_mempool = ha->srb_mempool; 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 380 ha->base_qpair->enable_class_2 = ql2xenableclass2; 381 /* init qpair to this cpu. Will adjust at run time. */ 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 383 ha->base_qpair->pdev = ha->pdev; 384 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 387 } 388 389 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 390 struct rsp_que *rsp) 391 { 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 393 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 395 GFP_KERNEL); 396 if (!ha->req_q_map) { 397 ql_log(ql_log_fatal, vha, 0x003b, 398 "Unable to allocate memory for request queue ptrs.\n"); 399 goto fail_req_map; 400 } 401 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 403 GFP_KERNEL); 404 if (!ha->rsp_q_map) { 405 ql_log(ql_log_fatal, vha, 0x003c, 406 "Unable to allocate memory for response queue ptrs.\n"); 407 goto fail_rsp_map; 408 } 409 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 411 if (ha->base_qpair == NULL) { 412 ql_log(ql_log_warn, vha, 0x00e0, 413 "Failed to allocate base queue pair memory.\n"); 414 goto fail_base_qpair; 415 } 416 417 qla_init_base_qpair(vha, req, rsp); 418 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 421 GFP_KERNEL); 422 if (!ha->queue_pair_map) { 423 ql_log(ql_log_fatal, vha, 0x0180, 424 "Unable to allocate memory for queue pair ptrs.\n"); 425 goto fail_qpair_map; 426 } 427 } 428 429 /* 430 * Make sure we record at least the request and response queue zero in 431 * case we need to free them if part of the probe fails. 432 */ 433 ha->rsp_q_map[0] = rsp; 434 ha->req_q_map[0] = req; 435 set_bit(0, ha->rsp_qid_map); 436 set_bit(0, ha->req_qid_map); 437 return 0; 438 439 fail_qpair_map: 440 kfree(ha->base_qpair); 441 ha->base_qpair = NULL; 442 fail_base_qpair: 443 kfree(ha->rsp_q_map); 444 ha->rsp_q_map = NULL; 445 fail_rsp_map: 446 kfree(ha->req_q_map); 447 ha->req_q_map = NULL; 448 fail_req_map: 449 return -ENOMEM; 450 } 451 452 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 453 { 454 if (IS_QLAFX00(ha)) { 455 if (req && req->ring_fx00) 456 dma_free_coherent(&ha->pdev->dev, 457 (req->length_fx00 + 1) * sizeof(request_t), 458 req->ring_fx00, req->dma_fx00); 459 } else if (req && req->ring) 460 dma_free_coherent(&ha->pdev->dev, 461 (req->length + 1) * sizeof(request_t), 462 req->ring, req->dma); 463 464 if (req) 465 kfree(req->outstanding_cmds); 466 467 kfree(req); 468 } 469 470 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 471 { 472 if (IS_QLAFX00(ha)) { 473 if (rsp && rsp->ring_fx00) 474 dma_free_coherent(&ha->pdev->dev, 475 (rsp->length_fx00 + 1) * sizeof(request_t), 476 rsp->ring_fx00, rsp->dma_fx00); 477 } else if (rsp && rsp->ring) { 478 dma_free_coherent(&ha->pdev->dev, 479 (rsp->length + 1) * sizeof(response_t), 480 rsp->ring, rsp->dma); 481 } 482 kfree(rsp); 483 } 484 485 static void qla2x00_free_queues(struct qla_hw_data *ha) 486 { 487 struct req_que *req; 488 struct rsp_que *rsp; 489 int cnt; 490 unsigned long flags; 491 492 if (ha->queue_pair_map) { 493 kfree(ha->queue_pair_map); 494 ha->queue_pair_map = NULL; 495 } 496 if (ha->base_qpair) { 497 kfree(ha->base_qpair); 498 ha->base_qpair = NULL; 499 } 500 501 spin_lock_irqsave(&ha->hardware_lock, flags); 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 503 if (!test_bit(cnt, ha->req_qid_map)) 504 continue; 505 506 req = ha->req_q_map[cnt]; 507 clear_bit(cnt, ha->req_qid_map); 508 ha->req_q_map[cnt] = NULL; 509 510 spin_unlock_irqrestore(&ha->hardware_lock, flags); 511 qla2x00_free_req_que(ha, req); 512 spin_lock_irqsave(&ha->hardware_lock, flags); 513 } 514 spin_unlock_irqrestore(&ha->hardware_lock, flags); 515 516 kfree(ha->req_q_map); 517 ha->req_q_map = NULL; 518 519 520 spin_lock_irqsave(&ha->hardware_lock, flags); 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 522 if (!test_bit(cnt, ha->rsp_qid_map)) 523 continue; 524 525 rsp = ha->rsp_q_map[cnt]; 526 clear_bit(cnt, ha->rsp_qid_map); 527 ha->rsp_q_map[cnt] = NULL; 528 spin_unlock_irqrestore(&ha->hardware_lock, flags); 529 qla2x00_free_rsp_que(ha, rsp); 530 spin_lock_irqsave(&ha->hardware_lock, flags); 531 } 532 spin_unlock_irqrestore(&ha->hardware_lock, flags); 533 534 kfree(ha->rsp_q_map); 535 ha->rsp_q_map = NULL; 536 } 537 538 static char * 539 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 540 { 541 struct qla_hw_data *ha = vha->hw; 542 static const char *const pci_bus_modes[] = { 543 "33", "66", "100", "133", 544 }; 545 uint16_t pci_bus; 546 547 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 548 if (pci_bus) { 549 snprintf(str, str_len, "PCI-X (%s MHz)", 550 pci_bus_modes[pci_bus]); 551 } else { 552 pci_bus = (ha->pci_attr & BIT_8) >> 8; 553 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 554 } 555 556 return str; 557 } 558 559 static char * 560 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 561 { 562 static const char *const pci_bus_modes[] = { 563 "33", "66", "100", "133", 564 }; 565 struct qla_hw_data *ha = vha->hw; 566 uint32_t pci_bus; 567 568 if (pci_is_pcie(ha->pdev)) { 569 uint32_t lstat, lspeed, lwidth; 570 const char *speed_str; 571 572 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 573 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 574 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 575 576 switch (lspeed) { 577 case 1: 578 speed_str = "2.5GT/s"; 579 break; 580 case 2: 581 speed_str = "5.0GT/s"; 582 break; 583 case 3: 584 speed_str = "8.0GT/s"; 585 break; 586 default: 587 speed_str = "<unknown>"; 588 break; 589 } 590 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 591 592 return str; 593 } 594 595 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 596 if (pci_bus == 0 || pci_bus == 8) 597 snprintf(str, str_len, "PCI (%s MHz)", 598 pci_bus_modes[pci_bus >> 3]); 599 else 600 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 601 pci_bus & 4 ? 2 : 1, 602 pci_bus_modes[pci_bus & 3]); 603 604 return str; 605 } 606 607 static char * 608 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 609 { 610 char un_str[10]; 611 struct qla_hw_data *ha = vha->hw; 612 613 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 614 ha->fw_minor_version, ha->fw_subminor_version); 615 616 if (ha->fw_attributes & BIT_9) { 617 strcat(str, "FLX"); 618 return (str); 619 } 620 621 switch (ha->fw_attributes & 0xFF) { 622 case 0x7: 623 strcat(str, "EF"); 624 break; 625 case 0x17: 626 strcat(str, "TP"); 627 break; 628 case 0x37: 629 strcat(str, "IP"); 630 break; 631 case 0x77: 632 strcat(str, "VI"); 633 break; 634 default: 635 sprintf(un_str, "(%x)", ha->fw_attributes); 636 strcat(str, un_str); 637 break; 638 } 639 if (ha->fw_attributes & 0x100) 640 strcat(str, "X"); 641 642 return (str); 643 } 644 645 static char * 646 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 647 { 648 struct qla_hw_data *ha = vha->hw; 649 650 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 651 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 652 return str; 653 } 654 655 void qla2x00_sp_free_dma(srb_t *sp) 656 { 657 struct qla_hw_data *ha = sp->vha->hw; 658 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 659 660 if (sp->flags & SRB_DMA_VALID) { 661 scsi_dma_unmap(cmd); 662 sp->flags &= ~SRB_DMA_VALID; 663 } 664 665 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 666 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 667 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 668 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 669 } 670 671 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 672 /* List assured to be having elements */ 673 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 674 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 675 } 676 677 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 678 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 679 680 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 681 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 682 } 683 684 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 685 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 686 687 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 688 ctx1->fcp_cmnd_dma); 689 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 690 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 691 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 692 mempool_free(ctx1, ha->ctx_mempool); 693 } 694 } 695 696 void qla2x00_sp_compl(srb_t *sp, int res) 697 { 698 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 699 struct completion *comp = sp->comp; 700 701 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 702 return; 703 704 atomic_dec(&sp->ref_count); 705 706 sp->free(sp); 707 cmd->result = res; 708 CMD_SP(cmd) = NULL; 709 cmd->scsi_done(cmd); 710 if (comp) 711 complete(comp); 712 } 713 714 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 715 { 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 717 struct qla_hw_data *ha = sp->fcport->vha->hw; 718 719 if (sp->flags & SRB_DMA_VALID) { 720 scsi_dma_unmap(cmd); 721 sp->flags &= ~SRB_DMA_VALID; 722 } 723 724 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 725 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 726 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 727 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 728 } 729 730 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 731 /* List assured to be having elements */ 732 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 733 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 734 } 735 736 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 737 struct crc_context *difctx = sp->u.scmd.crc_ctx; 738 struct dsd_dma *dif_dsd, *nxt_dsd; 739 740 list_for_each_entry_safe(dif_dsd, nxt_dsd, 741 &difctx->ldif_dma_hndl_list, list) { 742 list_del(&dif_dsd->list); 743 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 744 dif_dsd->dsd_list_dma); 745 kfree(dif_dsd); 746 difctx->no_dif_bundl--; 747 } 748 749 list_for_each_entry_safe(dif_dsd, nxt_dsd, 750 &difctx->ldif_dsd_list, list) { 751 list_del(&dif_dsd->list); 752 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 753 dif_dsd->dsd_list_dma); 754 kfree(dif_dsd); 755 difctx->no_ldif_dsd--; 756 } 757 758 if (difctx->no_ldif_dsd) { 759 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 760 "%s: difctx->no_ldif_dsd=%x\n", 761 __func__, difctx->no_ldif_dsd); 762 } 763 764 if (difctx->no_dif_bundl) { 765 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 766 "%s: difctx->no_dif_bundl=%x\n", 767 __func__, difctx->no_dif_bundl); 768 } 769 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 770 } 771 772 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 773 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 774 775 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 776 ctx1->fcp_cmnd_dma); 777 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 778 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 779 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 780 mempool_free(ctx1, ha->ctx_mempool); 781 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 782 } 783 784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 785 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 786 787 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 789 } 790 } 791 792 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 793 { 794 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 795 struct completion *comp = sp->comp; 796 797 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 798 return; 799 800 atomic_dec(&sp->ref_count); 801 802 sp->free(sp); 803 cmd->result = res; 804 CMD_SP(cmd) = NULL; 805 cmd->scsi_done(cmd); 806 if (comp) 807 complete(comp); 808 } 809 810 static int 811 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 812 { 813 scsi_qla_host_t *vha = shost_priv(host); 814 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 815 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 816 struct qla_hw_data *ha = vha->hw; 817 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 818 srb_t *sp; 819 int rval; 820 821 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 822 WARN_ON_ONCE(!rport)) { 823 cmd->result = DID_NO_CONNECT << 16; 824 goto qc24_fail_command; 825 } 826 827 if (ha->mqenable) { 828 uint32_t tag; 829 uint16_t hwq; 830 struct qla_qpair *qpair = NULL; 831 832 tag = blk_mq_unique_tag(cmd->request); 833 hwq = blk_mq_unique_tag_to_hwq(tag); 834 qpair = ha->queue_pair_map[hwq]; 835 836 if (qpair) 837 return qla2xxx_mqueuecommand(host, cmd, qpair); 838 } 839 840 if (ha->flags.eeh_busy) { 841 if (ha->flags.pci_channel_io_perm_failure) { 842 ql_dbg(ql_dbg_aer, vha, 0x9010, 843 "PCI Channel IO permanent failure, exiting " 844 "cmd=%p.\n", cmd); 845 cmd->result = DID_NO_CONNECT << 16; 846 } else { 847 ql_dbg(ql_dbg_aer, vha, 0x9011, 848 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 849 cmd->result = DID_REQUEUE << 16; 850 } 851 goto qc24_fail_command; 852 } 853 854 rval = fc_remote_port_chkready(rport); 855 if (rval) { 856 cmd->result = rval; 857 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 858 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 859 cmd, rval); 860 goto qc24_fail_command; 861 } 862 863 if (!vha->flags.difdix_supported && 864 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 865 ql_dbg(ql_dbg_io, vha, 0x3004, 866 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 867 cmd); 868 cmd->result = DID_NO_CONNECT << 16; 869 goto qc24_fail_command; 870 } 871 872 if (!fcport) { 873 cmd->result = DID_NO_CONNECT << 16; 874 goto qc24_fail_command; 875 } 876 877 if (atomic_read(&fcport->state) != FCS_ONLINE) { 878 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 879 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 880 ql_dbg(ql_dbg_io, vha, 0x3005, 881 "Returning DNC, fcport_state=%d loop_state=%d.\n", 882 atomic_read(&fcport->state), 883 atomic_read(&base_vha->loop_state)); 884 cmd->result = DID_NO_CONNECT << 16; 885 goto qc24_fail_command; 886 } 887 goto qc24_target_busy; 888 } 889 890 /* 891 * Return target busy if we've received a non-zero retry_delay_timer 892 * in a FCP_RSP. 893 */ 894 if (fcport->retry_delay_timestamp == 0) { 895 /* retry delay not set */ 896 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 897 fcport->retry_delay_timestamp = 0; 898 else 899 goto qc24_target_busy; 900 901 sp = scsi_cmd_priv(cmd); 902 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 903 904 sp->u.scmd.cmd = cmd; 905 sp->type = SRB_SCSI_CMD; 906 atomic_set(&sp->ref_count, 1); 907 CMD_SP(cmd) = (void *)sp; 908 sp->free = qla2x00_sp_free_dma; 909 sp->done = qla2x00_sp_compl; 910 911 rval = ha->isp_ops->start_scsi(sp); 912 if (rval != QLA_SUCCESS) { 913 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 914 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 915 goto qc24_host_busy_free_sp; 916 } 917 918 return 0; 919 920 qc24_host_busy_free_sp: 921 sp->free(sp); 922 923 qc24_target_busy: 924 return SCSI_MLQUEUE_TARGET_BUSY; 925 926 qc24_fail_command: 927 cmd->scsi_done(cmd); 928 929 return 0; 930 } 931 932 /* For MQ supported I/O */ 933 int 934 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 935 struct qla_qpair *qpair) 936 { 937 scsi_qla_host_t *vha = shost_priv(host); 938 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 939 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 940 struct qla_hw_data *ha = vha->hw; 941 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 942 srb_t *sp; 943 int rval; 944 945 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 946 if (rval) { 947 cmd->result = rval; 948 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 949 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 950 cmd, rval); 951 goto qc24_fail_command; 952 } 953 954 if (!fcport) { 955 cmd->result = DID_NO_CONNECT << 16; 956 goto qc24_fail_command; 957 } 958 959 if (atomic_read(&fcport->state) != FCS_ONLINE) { 960 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 961 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 962 ql_dbg(ql_dbg_io, vha, 0x3077, 963 "Returning DNC, fcport_state=%d loop_state=%d.\n", 964 atomic_read(&fcport->state), 965 atomic_read(&base_vha->loop_state)); 966 cmd->result = DID_NO_CONNECT << 16; 967 goto qc24_fail_command; 968 } 969 goto qc24_target_busy; 970 } 971 972 /* 973 * Return target busy if we've received a non-zero retry_delay_timer 974 * in a FCP_RSP. 975 */ 976 if (fcport->retry_delay_timestamp == 0) { 977 /* retry delay not set */ 978 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 979 fcport->retry_delay_timestamp = 0; 980 else 981 goto qc24_target_busy; 982 983 sp = scsi_cmd_priv(cmd); 984 qla2xxx_init_sp(sp, vha, qpair, fcport); 985 986 sp->u.scmd.cmd = cmd; 987 sp->type = SRB_SCSI_CMD; 988 atomic_set(&sp->ref_count, 1); 989 CMD_SP(cmd) = (void *)sp; 990 sp->free = qla2xxx_qpair_sp_free_dma; 991 sp->done = qla2xxx_qpair_sp_compl; 992 sp->qpair = qpair; 993 994 rval = ha->isp_ops->start_scsi_mq(sp); 995 if (rval != QLA_SUCCESS) { 996 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 997 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 998 if (rval == QLA_INTERFACE_ERROR) 999 goto qc24_fail_command; 1000 goto qc24_host_busy_free_sp; 1001 } 1002 1003 return 0; 1004 1005 qc24_host_busy_free_sp: 1006 sp->free(sp); 1007 1008 qc24_target_busy: 1009 return SCSI_MLQUEUE_TARGET_BUSY; 1010 1011 qc24_fail_command: 1012 cmd->scsi_done(cmd); 1013 1014 return 0; 1015 } 1016 1017 /* 1018 * qla2x00_eh_wait_on_command 1019 * Waits for the command to be returned by the Firmware for some 1020 * max time. 1021 * 1022 * Input: 1023 * cmd = Scsi Command to wait on. 1024 * 1025 * Return: 1026 * Completed in time : QLA_SUCCESS 1027 * Did not complete in time : QLA_FUNCTION_FAILED 1028 */ 1029 static int 1030 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1031 { 1032 #define ABORT_POLLING_PERIOD 1000 1033 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1034 unsigned long wait_iter = ABORT_WAIT_ITER; 1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1036 struct qla_hw_data *ha = vha->hw; 1037 int ret = QLA_SUCCESS; 1038 1039 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1040 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1041 "Return:eh_wait.\n"); 1042 return ret; 1043 } 1044 1045 while (CMD_SP(cmd) && wait_iter--) { 1046 msleep(ABORT_POLLING_PERIOD); 1047 } 1048 if (CMD_SP(cmd)) 1049 ret = QLA_FUNCTION_FAILED; 1050 1051 return ret; 1052 } 1053 1054 /* 1055 * qla2x00_wait_for_hba_online 1056 * Wait till the HBA is online after going through 1057 * <= MAX_RETRIES_OF_ISP_ABORT or 1058 * finally HBA is disabled ie marked offline 1059 * 1060 * Input: 1061 * ha - pointer to host adapter structure 1062 * 1063 * Note: 1064 * Does context switching-Release SPIN_LOCK 1065 * (if any) before calling this routine. 1066 * 1067 * Return: 1068 * Success (Adapter is online) : 0 1069 * Failed (Adapter is offline/disabled) : 1 1070 */ 1071 int 1072 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1073 { 1074 int return_status; 1075 unsigned long wait_online; 1076 struct qla_hw_data *ha = vha->hw; 1077 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1078 1079 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1080 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1081 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1082 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1083 ha->dpc_active) && time_before(jiffies, wait_online)) { 1084 1085 msleep(1000); 1086 } 1087 if (base_vha->flags.online) 1088 return_status = QLA_SUCCESS; 1089 else 1090 return_status = QLA_FUNCTION_FAILED; 1091 1092 return (return_status); 1093 } 1094 1095 static inline int test_fcport_count(scsi_qla_host_t *vha) 1096 { 1097 struct qla_hw_data *ha = vha->hw; 1098 unsigned long flags; 1099 int res; 1100 1101 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1102 ql_dbg(ql_dbg_init, vha, 0x00ec, 1103 "tgt %p, fcport_count=%d\n", 1104 vha, vha->fcport_count); 1105 res = (vha->fcport_count == 0); 1106 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1107 1108 return res; 1109 } 1110 1111 /* 1112 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1113 * it has dependency on UNLOADING flag to stop device discovery 1114 */ 1115 void 1116 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1117 { 1118 u8 i; 1119 1120 qla2x00_mark_all_devices_lost(vha, 0); 1121 1122 for (i = 0; i < 10; i++) { 1123 if (wait_event_timeout(vha->fcport_waitQ, 1124 test_fcport_count(vha), HZ) > 0) 1125 break; 1126 } 1127 1128 flush_workqueue(vha->hw->wq); 1129 } 1130 1131 /* 1132 * qla2x00_wait_for_hba_ready 1133 * Wait till the HBA is ready before doing driver unload 1134 * 1135 * Input: 1136 * ha - pointer to host adapter structure 1137 * 1138 * Note: 1139 * Does context switching-Release SPIN_LOCK 1140 * (if any) before calling this routine. 1141 * 1142 */ 1143 static void 1144 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1145 { 1146 struct qla_hw_data *ha = vha->hw; 1147 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1148 1149 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1150 ha->flags.mbox_busy) || 1151 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1152 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1153 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1154 break; 1155 msleep(1000); 1156 } 1157 } 1158 1159 int 1160 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1161 { 1162 int return_status; 1163 unsigned long wait_reset; 1164 struct qla_hw_data *ha = vha->hw; 1165 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1166 1167 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1168 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1169 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1170 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1171 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1172 1173 msleep(1000); 1174 1175 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1176 ha->flags.chip_reset_done) 1177 break; 1178 } 1179 if (ha->flags.chip_reset_done) 1180 return_status = QLA_SUCCESS; 1181 else 1182 return_status = QLA_FUNCTION_FAILED; 1183 1184 return return_status; 1185 } 1186 1187 static int 1188 sp_get(struct srb *sp) 1189 { 1190 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count)) 1191 /* kref get fail */ 1192 return ENXIO; 1193 else 1194 return 0; 1195 } 1196 1197 #define ISP_REG_DISCONNECT 0xffffffffU 1198 /************************************************************************** 1199 * qla2x00_isp_reg_stat 1200 * 1201 * Description: 1202 * Read the host status register of ISP before aborting the command. 1203 * 1204 * Input: 1205 * ha = pointer to host adapter structure. 1206 * 1207 * 1208 * Returns: 1209 * Either true or false. 1210 * 1211 * Note: Return true if there is register disconnect. 1212 **************************************************************************/ 1213 static inline 1214 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1215 { 1216 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1217 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1218 1219 if (IS_P3P_TYPE(ha)) 1220 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1221 else 1222 return ((RD_REG_DWORD(®->host_status)) == 1223 ISP_REG_DISCONNECT); 1224 } 1225 1226 /************************************************************************** 1227 * qla2xxx_eh_abort 1228 * 1229 * Description: 1230 * The abort function will abort the specified command. 1231 * 1232 * Input: 1233 * cmd = Linux SCSI command packet to be aborted. 1234 * 1235 * Returns: 1236 * Either SUCCESS or FAILED. 1237 * 1238 * Note: 1239 * Only return FAILED if command not returned by firmware. 1240 **************************************************************************/ 1241 static int 1242 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1243 { 1244 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1245 DECLARE_COMPLETION_ONSTACK(comp); 1246 srb_t *sp; 1247 int ret; 1248 unsigned int id; 1249 uint64_t lun; 1250 int rval; 1251 struct qla_hw_data *ha = vha->hw; 1252 1253 if (qla2x00_isp_reg_stat(ha)) { 1254 ql_log(ql_log_info, vha, 0x8042, 1255 "PCI/Register disconnect, exiting.\n"); 1256 return FAILED; 1257 } 1258 1259 ret = fc_block_scsi_eh(cmd); 1260 if (ret != 0) 1261 return ret; 1262 1263 sp = scsi_cmd_priv(cmd); 1264 1265 if (sp->fcport && sp->fcport->deleted) 1266 return SUCCESS; 1267 1268 /* Return if the command has already finished. */ 1269 if (sp_get(sp)) 1270 return SUCCESS; 1271 1272 id = cmd->device->id; 1273 lun = cmd->device->lun; 1274 1275 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1276 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1277 vha->host_no, id, lun, sp, cmd, sp->handle); 1278 1279 rval = ha->isp_ops->abort_command(sp); 1280 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1281 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1282 1283 switch (rval) { 1284 case QLA_SUCCESS: 1285 /* 1286 * The command has been aborted. That means that the firmware 1287 * won't report a completion. 1288 */ 1289 sp->done(sp, DID_ABORT << 16); 1290 ret = SUCCESS; 1291 break; 1292 case QLA_FUNCTION_PARAMETER_ERROR: { 1293 /* Wait for the command completion. */ 1294 uint32_t ratov = ha->r_a_tov/10; 1295 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000); 1296 1297 WARN_ON_ONCE(sp->comp); 1298 sp->comp = ∁ 1299 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1300 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1301 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1302 __func__, ha->r_a_tov); 1303 ret = FAILED; 1304 } else { 1305 ret = SUCCESS; 1306 } 1307 break; 1308 } 1309 default: 1310 /* 1311 * Either abort failed or abort and completion raced. Let 1312 * the SCSI core retry the abort in the former case. 1313 */ 1314 ret = FAILED; 1315 break; 1316 } 1317 1318 sp->comp = NULL; 1319 atomic_dec(&sp->ref_count); 1320 ql_log(ql_log_info, vha, 0x801c, 1321 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1322 vha->host_no, id, lun, ret); 1323 1324 return ret; 1325 } 1326 1327 /* 1328 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1329 */ 1330 int 1331 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1332 uint64_t l, enum nexus_wait_type type) 1333 { 1334 int cnt, match, status; 1335 unsigned long flags; 1336 struct qla_hw_data *ha = vha->hw; 1337 struct req_que *req; 1338 srb_t *sp; 1339 struct scsi_cmnd *cmd; 1340 1341 status = QLA_SUCCESS; 1342 1343 spin_lock_irqsave(&ha->hardware_lock, flags); 1344 req = vha->req; 1345 for (cnt = 1; status == QLA_SUCCESS && 1346 cnt < req->num_outstanding_cmds; cnt++) { 1347 sp = req->outstanding_cmds[cnt]; 1348 if (!sp) 1349 continue; 1350 if (sp->type != SRB_SCSI_CMD) 1351 continue; 1352 if (vha->vp_idx != sp->vha->vp_idx) 1353 continue; 1354 match = 0; 1355 cmd = GET_CMD_SP(sp); 1356 switch (type) { 1357 case WAIT_HOST: 1358 match = 1; 1359 break; 1360 case WAIT_TARGET: 1361 match = cmd->device->id == t; 1362 break; 1363 case WAIT_LUN: 1364 match = (cmd->device->id == t && 1365 cmd->device->lun == l); 1366 break; 1367 } 1368 if (!match) 1369 continue; 1370 1371 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1372 status = qla2x00_eh_wait_on_command(cmd); 1373 spin_lock_irqsave(&ha->hardware_lock, flags); 1374 } 1375 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1376 1377 return status; 1378 } 1379 1380 static char *reset_errors[] = { 1381 "HBA not online", 1382 "HBA not ready", 1383 "Task management failed", 1384 "Waiting for command completions", 1385 }; 1386 1387 static int 1388 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1389 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1390 { 1391 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1392 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1393 int err; 1394 1395 if (!fcport) { 1396 return FAILED; 1397 } 1398 1399 err = fc_block_scsi_eh(cmd); 1400 if (err != 0) 1401 return err; 1402 1403 if (fcport->deleted) 1404 return SUCCESS; 1405 1406 ql_log(ql_log_info, vha, 0x8009, 1407 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1408 cmd->device->id, cmd->device->lun, cmd); 1409 1410 err = 0; 1411 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1412 ql_log(ql_log_warn, vha, 0x800a, 1413 "Wait for hba online failed for cmd=%p.\n", cmd); 1414 goto eh_reset_failed; 1415 } 1416 err = 2; 1417 if (do_reset(fcport, cmd->device->lun, 1) 1418 != QLA_SUCCESS) { 1419 ql_log(ql_log_warn, vha, 0x800c, 1420 "do_reset failed for cmd=%p.\n", cmd); 1421 goto eh_reset_failed; 1422 } 1423 err = 3; 1424 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1425 cmd->device->lun, type) != QLA_SUCCESS) { 1426 ql_log(ql_log_warn, vha, 0x800d, 1427 "wait for pending cmds failed for cmd=%p.\n", cmd); 1428 goto eh_reset_failed; 1429 } 1430 1431 ql_log(ql_log_info, vha, 0x800e, 1432 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1433 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1434 1435 return SUCCESS; 1436 1437 eh_reset_failed: 1438 ql_log(ql_log_info, vha, 0x800f, 1439 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1440 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1441 cmd); 1442 return FAILED; 1443 } 1444 1445 static int 1446 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1447 { 1448 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1449 struct qla_hw_data *ha = vha->hw; 1450 1451 if (qla2x00_isp_reg_stat(ha)) { 1452 ql_log(ql_log_info, vha, 0x803e, 1453 "PCI/Register disconnect, exiting.\n"); 1454 return FAILED; 1455 } 1456 1457 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1458 ha->isp_ops->lun_reset); 1459 } 1460 1461 static int 1462 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1463 { 1464 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1465 struct qla_hw_data *ha = vha->hw; 1466 1467 if (qla2x00_isp_reg_stat(ha)) { 1468 ql_log(ql_log_info, vha, 0x803f, 1469 "PCI/Register disconnect, exiting.\n"); 1470 return FAILED; 1471 } 1472 1473 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1474 ha->isp_ops->target_reset); 1475 } 1476 1477 /************************************************************************** 1478 * qla2xxx_eh_bus_reset 1479 * 1480 * Description: 1481 * The bus reset function will reset the bus and abort any executing 1482 * commands. 1483 * 1484 * Input: 1485 * cmd = Linux SCSI command packet of the command that cause the 1486 * bus reset. 1487 * 1488 * Returns: 1489 * SUCCESS/FAILURE (defined as macro in scsi.h). 1490 * 1491 **************************************************************************/ 1492 static int 1493 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1494 { 1495 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1496 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1497 int ret = FAILED; 1498 unsigned int id; 1499 uint64_t lun; 1500 struct qla_hw_data *ha = vha->hw; 1501 1502 if (qla2x00_isp_reg_stat(ha)) { 1503 ql_log(ql_log_info, vha, 0x8040, 1504 "PCI/Register disconnect, exiting.\n"); 1505 return FAILED; 1506 } 1507 1508 id = cmd->device->id; 1509 lun = cmd->device->lun; 1510 1511 if (!fcport) { 1512 return ret; 1513 } 1514 1515 ret = fc_block_scsi_eh(cmd); 1516 if (ret != 0) 1517 return ret; 1518 ret = FAILED; 1519 1520 if (qla2x00_chip_is_down(vha)) 1521 return ret; 1522 1523 ql_log(ql_log_info, vha, 0x8012, 1524 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1525 1526 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1527 ql_log(ql_log_fatal, vha, 0x8013, 1528 "Wait for hba online failed board disabled.\n"); 1529 goto eh_bus_reset_done; 1530 } 1531 1532 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1533 ret = SUCCESS; 1534 1535 if (ret == FAILED) 1536 goto eh_bus_reset_done; 1537 1538 /* Flush outstanding commands. */ 1539 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1540 QLA_SUCCESS) { 1541 ql_log(ql_log_warn, vha, 0x8014, 1542 "Wait for pending commands failed.\n"); 1543 ret = FAILED; 1544 } 1545 1546 eh_bus_reset_done: 1547 ql_log(ql_log_warn, vha, 0x802b, 1548 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1549 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1550 1551 return ret; 1552 } 1553 1554 /************************************************************************** 1555 * qla2xxx_eh_host_reset 1556 * 1557 * Description: 1558 * The reset function will reset the Adapter. 1559 * 1560 * Input: 1561 * cmd = Linux SCSI command packet of the command that cause the 1562 * adapter reset. 1563 * 1564 * Returns: 1565 * Either SUCCESS or FAILED. 1566 * 1567 * Note: 1568 **************************************************************************/ 1569 static int 1570 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1571 { 1572 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1573 struct qla_hw_data *ha = vha->hw; 1574 int ret = FAILED; 1575 unsigned int id; 1576 uint64_t lun; 1577 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1578 1579 if (qla2x00_isp_reg_stat(ha)) { 1580 ql_log(ql_log_info, vha, 0x8041, 1581 "PCI/Register disconnect, exiting.\n"); 1582 schedule_work(&ha->board_disable); 1583 return SUCCESS; 1584 } 1585 1586 id = cmd->device->id; 1587 lun = cmd->device->lun; 1588 1589 ql_log(ql_log_info, vha, 0x8018, 1590 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1591 1592 /* 1593 * No point in issuing another reset if one is active. Also do not 1594 * attempt a reset if we are updating flash. 1595 */ 1596 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1597 goto eh_host_reset_lock; 1598 1599 if (vha != base_vha) { 1600 if (qla2x00_vp_abort_isp(vha)) 1601 goto eh_host_reset_lock; 1602 } else { 1603 if (IS_P3P_TYPE(vha->hw)) { 1604 if (!qla82xx_fcoe_ctx_reset(vha)) { 1605 /* Ctx reset success */ 1606 ret = SUCCESS; 1607 goto eh_host_reset_lock; 1608 } 1609 /* fall thru if ctx reset failed */ 1610 } 1611 if (ha->wq) 1612 flush_workqueue(ha->wq); 1613 1614 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1615 if (ha->isp_ops->abort_isp(base_vha)) { 1616 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1617 /* failed. schedule dpc to try */ 1618 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1619 1620 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1621 ql_log(ql_log_warn, vha, 0x802a, 1622 "wait for hba online failed.\n"); 1623 goto eh_host_reset_lock; 1624 } 1625 } 1626 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1627 } 1628 1629 /* Waiting for command to be returned to OS.*/ 1630 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1631 QLA_SUCCESS) 1632 ret = SUCCESS; 1633 1634 eh_host_reset_lock: 1635 ql_log(ql_log_info, vha, 0x8017, 1636 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1637 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1638 1639 return ret; 1640 } 1641 1642 /* 1643 * qla2x00_loop_reset 1644 * Issue loop reset. 1645 * 1646 * Input: 1647 * ha = adapter block pointer. 1648 * 1649 * Returns: 1650 * 0 = success 1651 */ 1652 int 1653 qla2x00_loop_reset(scsi_qla_host_t *vha) 1654 { 1655 int ret; 1656 struct fc_port *fcport; 1657 struct qla_hw_data *ha = vha->hw; 1658 1659 if (IS_QLAFX00(ha)) { 1660 return qlafx00_loop_reset(vha); 1661 } 1662 1663 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1664 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1665 if (fcport->port_type != FCT_TARGET) 1666 continue; 1667 1668 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1669 if (ret != QLA_SUCCESS) { 1670 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1671 "Bus Reset failed: Reset=%d " 1672 "d_id=%x.\n", ret, fcport->d_id.b24); 1673 } 1674 } 1675 } 1676 1677 1678 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1679 atomic_set(&vha->loop_state, LOOP_DOWN); 1680 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1681 qla2x00_mark_all_devices_lost(vha, 0); 1682 ret = qla2x00_full_login_lip(vha); 1683 if (ret != QLA_SUCCESS) { 1684 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1685 "full_login_lip=%d.\n", ret); 1686 } 1687 } 1688 1689 if (ha->flags.enable_lip_reset) { 1690 ret = qla2x00_lip_reset(vha); 1691 if (ret != QLA_SUCCESS) 1692 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1693 "lip_reset failed (%d).\n", ret); 1694 } 1695 1696 /* Issue marker command only when we are going to start the I/O */ 1697 vha->marker_needed = 1; 1698 1699 return QLA_SUCCESS; 1700 } 1701 1702 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1703 unsigned long *flags) 1704 __releases(qp->qp_lock_ptr) 1705 __acquires(qp->qp_lock_ptr) 1706 { 1707 DECLARE_COMPLETION_ONSTACK(comp); 1708 scsi_qla_host_t *vha = qp->vha; 1709 struct qla_hw_data *ha = vha->hw; 1710 int rval; 1711 1712 if (sp_get(sp)) 1713 return; 1714 1715 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1716 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1717 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1718 !qla2x00_isp_reg_stat(ha))) { 1719 sp->comp = ∁ 1720 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1721 rval = ha->isp_ops->abort_command(sp); 1722 1723 switch (rval) { 1724 case QLA_SUCCESS: 1725 sp->done(sp, res); 1726 break; 1727 case QLA_FUNCTION_PARAMETER_ERROR: 1728 wait_for_completion(&comp); 1729 break; 1730 } 1731 1732 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1733 sp->comp = NULL; 1734 } 1735 1736 atomic_dec(&sp->ref_count); 1737 } 1738 1739 static void 1740 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1741 { 1742 int cnt; 1743 unsigned long flags; 1744 srb_t *sp; 1745 scsi_qla_host_t *vha = qp->vha; 1746 struct qla_hw_data *ha = vha->hw; 1747 struct req_que *req; 1748 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1749 struct qla_tgt_cmd *cmd; 1750 1751 if (!ha->req_q_map) 1752 return; 1753 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1754 req = qp->req; 1755 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1756 sp = req->outstanding_cmds[cnt]; 1757 if (sp) { 1758 req->outstanding_cmds[cnt] = NULL; 1759 switch (sp->cmd_type) { 1760 case TYPE_SRB: 1761 qla2x00_abort_srb(qp, sp, res, &flags); 1762 break; 1763 case TYPE_TGT_CMD: 1764 if (!vha->hw->tgt.tgt_ops || !tgt || 1765 qla_ini_mode_enabled(vha)) { 1766 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1767 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1768 vha->dpc_flags); 1769 continue; 1770 } 1771 cmd = (struct qla_tgt_cmd *)sp; 1772 cmd->aborted = 1; 1773 break; 1774 case TYPE_TGT_TMCMD: 1775 /* Skip task management functions. */ 1776 break; 1777 default: 1778 break; 1779 } 1780 } 1781 } 1782 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1783 } 1784 1785 void 1786 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1787 { 1788 int que; 1789 struct qla_hw_data *ha = vha->hw; 1790 1791 /* Continue only if initialization complete. */ 1792 if (!ha->base_qpair) 1793 return; 1794 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1795 1796 if (!ha->queue_pair_map) 1797 return; 1798 for (que = 0; que < ha->max_qpairs; que++) { 1799 if (!ha->queue_pair_map[que]) 1800 continue; 1801 1802 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1803 } 1804 } 1805 1806 static int 1807 qla2xxx_slave_alloc(struct scsi_device *sdev) 1808 { 1809 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1810 1811 if (!rport || fc_remote_port_chkready(rport)) 1812 return -ENXIO; 1813 1814 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1815 1816 return 0; 1817 } 1818 1819 static int 1820 qla2xxx_slave_configure(struct scsi_device *sdev) 1821 { 1822 scsi_qla_host_t *vha = shost_priv(sdev->host); 1823 struct req_que *req = vha->req; 1824 1825 if (IS_T10_PI_CAPABLE(vha->hw)) 1826 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1827 1828 scsi_change_queue_depth(sdev, req->max_q_depth); 1829 return 0; 1830 } 1831 1832 static void 1833 qla2xxx_slave_destroy(struct scsi_device *sdev) 1834 { 1835 sdev->hostdata = NULL; 1836 } 1837 1838 /** 1839 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1840 * @ha: HA context 1841 * 1842 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1843 * supported addressing method. 1844 */ 1845 static void 1846 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1847 { 1848 /* Assume a 32bit DMA mask. */ 1849 ha->flags.enable_64bit_addressing = 0; 1850 1851 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1852 /* Any upper-dword bits set? */ 1853 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1854 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1855 /* Ok, a 64bit DMA mask is applicable. */ 1856 ha->flags.enable_64bit_addressing = 1; 1857 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1858 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1859 return; 1860 } 1861 } 1862 1863 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1864 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1865 } 1866 1867 static void 1868 qla2x00_enable_intrs(struct qla_hw_data *ha) 1869 { 1870 unsigned long flags = 0; 1871 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1872 1873 spin_lock_irqsave(&ha->hardware_lock, flags); 1874 ha->interrupts_on = 1; 1875 /* enable risc and host interrupts */ 1876 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1877 RD_REG_WORD(®->ictrl); 1878 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1879 1880 } 1881 1882 static void 1883 qla2x00_disable_intrs(struct qla_hw_data *ha) 1884 { 1885 unsigned long flags = 0; 1886 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1887 1888 spin_lock_irqsave(&ha->hardware_lock, flags); 1889 ha->interrupts_on = 0; 1890 /* disable risc and host interrupts */ 1891 WRT_REG_WORD(®->ictrl, 0); 1892 RD_REG_WORD(®->ictrl); 1893 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1894 } 1895 1896 static void 1897 qla24xx_enable_intrs(struct qla_hw_data *ha) 1898 { 1899 unsigned long flags = 0; 1900 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1901 1902 spin_lock_irqsave(&ha->hardware_lock, flags); 1903 ha->interrupts_on = 1; 1904 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1905 RD_REG_DWORD(®->ictrl); 1906 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1907 } 1908 1909 static void 1910 qla24xx_disable_intrs(struct qla_hw_data *ha) 1911 { 1912 unsigned long flags = 0; 1913 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1914 1915 if (IS_NOPOLLING_TYPE(ha)) 1916 return; 1917 spin_lock_irqsave(&ha->hardware_lock, flags); 1918 ha->interrupts_on = 0; 1919 WRT_REG_DWORD(®->ictrl, 0); 1920 RD_REG_DWORD(®->ictrl); 1921 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1922 } 1923 1924 static int 1925 qla2x00_iospace_config(struct qla_hw_data *ha) 1926 { 1927 resource_size_t pio; 1928 uint16_t msix; 1929 1930 if (pci_request_selected_regions(ha->pdev, ha->bars, 1931 QLA2XXX_DRIVER_NAME)) { 1932 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1933 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1934 pci_name(ha->pdev)); 1935 goto iospace_error_exit; 1936 } 1937 if (!(ha->bars & 1)) 1938 goto skip_pio; 1939 1940 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1941 pio = pci_resource_start(ha->pdev, 0); 1942 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1943 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1944 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1945 "Invalid pci I/O region size (%s).\n", 1946 pci_name(ha->pdev)); 1947 pio = 0; 1948 } 1949 } else { 1950 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1951 "Region #0 no a PIO resource (%s).\n", 1952 pci_name(ha->pdev)); 1953 pio = 0; 1954 } 1955 ha->pio_address = pio; 1956 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1957 "PIO address=%llu.\n", 1958 (unsigned long long)ha->pio_address); 1959 1960 skip_pio: 1961 /* Use MMIO operations for all accesses. */ 1962 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1963 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1964 "Region #1 not an MMIO resource (%s), aborting.\n", 1965 pci_name(ha->pdev)); 1966 goto iospace_error_exit; 1967 } 1968 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1969 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1970 "Invalid PCI mem region size (%s), aborting.\n", 1971 pci_name(ha->pdev)); 1972 goto iospace_error_exit; 1973 } 1974 1975 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1976 if (!ha->iobase) { 1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1978 "Cannot remap MMIO (%s), aborting.\n", 1979 pci_name(ha->pdev)); 1980 goto iospace_error_exit; 1981 } 1982 1983 /* Determine queue resources */ 1984 ha->max_req_queues = ha->max_rsp_queues = 1; 1985 ha->msix_count = QLA_BASE_VECTORS; 1986 if (!ql2xmqsupport || !ql2xnvmeenable || 1987 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1988 goto mqiobase_exit; 1989 1990 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1991 pci_resource_len(ha->pdev, 3)); 1992 if (ha->mqiobase) { 1993 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1994 "MQIO Base=%p.\n", ha->mqiobase); 1995 /* Read MSIX vector size of the board */ 1996 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1997 ha->msix_count = msix + 1; 1998 /* Max queues are bounded by available msix vectors */ 1999 /* MB interrupt uses 1 vector */ 2000 ha->max_req_queues = ha->msix_count - 1; 2001 ha->max_rsp_queues = ha->max_req_queues; 2002 /* Queue pairs is the max value minus the base queue pair */ 2003 ha->max_qpairs = ha->max_rsp_queues - 1; 2004 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2005 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2006 2007 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2008 "MSI-X vector count: %d.\n", ha->msix_count); 2009 } else 2010 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2011 "BAR 3 not enabled.\n"); 2012 2013 mqiobase_exit: 2014 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2015 "MSIX Count: %d.\n", ha->msix_count); 2016 return (0); 2017 2018 iospace_error_exit: 2019 return (-ENOMEM); 2020 } 2021 2022 2023 static int 2024 qla83xx_iospace_config(struct qla_hw_data *ha) 2025 { 2026 uint16_t msix; 2027 2028 if (pci_request_selected_regions(ha->pdev, ha->bars, 2029 QLA2XXX_DRIVER_NAME)) { 2030 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2031 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2032 pci_name(ha->pdev)); 2033 2034 goto iospace_error_exit; 2035 } 2036 2037 /* Use MMIO operations for all accesses. */ 2038 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2039 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2040 "Invalid pci I/O region size (%s).\n", 2041 pci_name(ha->pdev)); 2042 goto iospace_error_exit; 2043 } 2044 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2045 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2046 "Invalid PCI mem region size (%s), aborting\n", 2047 pci_name(ha->pdev)); 2048 goto iospace_error_exit; 2049 } 2050 2051 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2052 if (!ha->iobase) { 2053 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2054 "Cannot remap MMIO (%s), aborting.\n", 2055 pci_name(ha->pdev)); 2056 goto iospace_error_exit; 2057 } 2058 2059 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2060 /* 83XX 26XX always use MQ type access for queues 2061 * - mbar 2, a.k.a region 4 */ 2062 ha->max_req_queues = ha->max_rsp_queues = 1; 2063 ha->msix_count = QLA_BASE_VECTORS; 2064 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2065 pci_resource_len(ha->pdev, 4)); 2066 2067 if (!ha->mqiobase) { 2068 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2069 "BAR2/region4 not enabled\n"); 2070 goto mqiobase_exit; 2071 } 2072 2073 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2074 pci_resource_len(ha->pdev, 2)); 2075 if (ha->msixbase) { 2076 /* Read MSIX vector size of the board */ 2077 pci_read_config_word(ha->pdev, 2078 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2079 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2080 /* 2081 * By default, driver uses at least two msix vectors 2082 * (default & rspq) 2083 */ 2084 if (ql2xmqsupport || ql2xnvmeenable) { 2085 /* MB interrupt uses 1 vector */ 2086 ha->max_req_queues = ha->msix_count - 1; 2087 2088 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2089 if (QLA_TGT_MODE_ENABLED()) 2090 ha->max_req_queues--; 2091 2092 ha->max_rsp_queues = ha->max_req_queues; 2093 2094 /* Queue pairs is the max value minus 2095 * the base queue pair */ 2096 ha->max_qpairs = ha->max_req_queues - 1; 2097 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2098 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2099 } 2100 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2101 "MSI-X vector count: %d.\n", ha->msix_count); 2102 } else 2103 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2104 "BAR 1 not enabled.\n"); 2105 2106 mqiobase_exit: 2107 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2108 "MSIX Count: %d.\n", ha->msix_count); 2109 return 0; 2110 2111 iospace_error_exit: 2112 return -ENOMEM; 2113 } 2114 2115 static struct isp_operations qla2100_isp_ops = { 2116 .pci_config = qla2100_pci_config, 2117 .reset_chip = qla2x00_reset_chip, 2118 .chip_diag = qla2x00_chip_diag, 2119 .config_rings = qla2x00_config_rings, 2120 .reset_adapter = qla2x00_reset_adapter, 2121 .nvram_config = qla2x00_nvram_config, 2122 .update_fw_options = qla2x00_update_fw_options, 2123 .load_risc = qla2x00_load_risc, 2124 .pci_info_str = qla2x00_pci_info_str, 2125 .fw_version_str = qla2x00_fw_version_str, 2126 .intr_handler = qla2100_intr_handler, 2127 .enable_intrs = qla2x00_enable_intrs, 2128 .disable_intrs = qla2x00_disable_intrs, 2129 .abort_command = qla2x00_abort_command, 2130 .target_reset = qla2x00_abort_target, 2131 .lun_reset = qla2x00_lun_reset, 2132 .fabric_login = qla2x00_login_fabric, 2133 .fabric_logout = qla2x00_fabric_logout, 2134 .calc_req_entries = qla2x00_calc_iocbs_32, 2135 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2136 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2137 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2138 .read_nvram = qla2x00_read_nvram_data, 2139 .write_nvram = qla2x00_write_nvram_data, 2140 .fw_dump = qla2100_fw_dump, 2141 .beacon_on = NULL, 2142 .beacon_off = NULL, 2143 .beacon_blink = NULL, 2144 .read_optrom = qla2x00_read_optrom_data, 2145 .write_optrom = qla2x00_write_optrom_data, 2146 .get_flash_version = qla2x00_get_flash_version, 2147 .start_scsi = qla2x00_start_scsi, 2148 .start_scsi_mq = NULL, 2149 .abort_isp = qla2x00_abort_isp, 2150 .iospace_config = qla2x00_iospace_config, 2151 .initialize_adapter = qla2x00_initialize_adapter, 2152 }; 2153 2154 static struct isp_operations qla2300_isp_ops = { 2155 .pci_config = qla2300_pci_config, 2156 .reset_chip = qla2x00_reset_chip, 2157 .chip_diag = qla2x00_chip_diag, 2158 .config_rings = qla2x00_config_rings, 2159 .reset_adapter = qla2x00_reset_adapter, 2160 .nvram_config = qla2x00_nvram_config, 2161 .update_fw_options = qla2x00_update_fw_options, 2162 .load_risc = qla2x00_load_risc, 2163 .pci_info_str = qla2x00_pci_info_str, 2164 .fw_version_str = qla2x00_fw_version_str, 2165 .intr_handler = qla2300_intr_handler, 2166 .enable_intrs = qla2x00_enable_intrs, 2167 .disable_intrs = qla2x00_disable_intrs, 2168 .abort_command = qla2x00_abort_command, 2169 .target_reset = qla2x00_abort_target, 2170 .lun_reset = qla2x00_lun_reset, 2171 .fabric_login = qla2x00_login_fabric, 2172 .fabric_logout = qla2x00_fabric_logout, 2173 .calc_req_entries = qla2x00_calc_iocbs_32, 2174 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2175 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2176 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2177 .read_nvram = qla2x00_read_nvram_data, 2178 .write_nvram = qla2x00_write_nvram_data, 2179 .fw_dump = qla2300_fw_dump, 2180 .beacon_on = qla2x00_beacon_on, 2181 .beacon_off = qla2x00_beacon_off, 2182 .beacon_blink = qla2x00_beacon_blink, 2183 .read_optrom = qla2x00_read_optrom_data, 2184 .write_optrom = qla2x00_write_optrom_data, 2185 .get_flash_version = qla2x00_get_flash_version, 2186 .start_scsi = qla2x00_start_scsi, 2187 .start_scsi_mq = NULL, 2188 .abort_isp = qla2x00_abort_isp, 2189 .iospace_config = qla2x00_iospace_config, 2190 .initialize_adapter = qla2x00_initialize_adapter, 2191 }; 2192 2193 static struct isp_operations qla24xx_isp_ops = { 2194 .pci_config = qla24xx_pci_config, 2195 .reset_chip = qla24xx_reset_chip, 2196 .chip_diag = qla24xx_chip_diag, 2197 .config_rings = qla24xx_config_rings, 2198 .reset_adapter = qla24xx_reset_adapter, 2199 .nvram_config = qla24xx_nvram_config, 2200 .update_fw_options = qla24xx_update_fw_options, 2201 .load_risc = qla24xx_load_risc, 2202 .pci_info_str = qla24xx_pci_info_str, 2203 .fw_version_str = qla24xx_fw_version_str, 2204 .intr_handler = qla24xx_intr_handler, 2205 .enable_intrs = qla24xx_enable_intrs, 2206 .disable_intrs = qla24xx_disable_intrs, 2207 .abort_command = qla24xx_abort_command, 2208 .target_reset = qla24xx_abort_target, 2209 .lun_reset = qla24xx_lun_reset, 2210 .fabric_login = qla24xx_login_fabric, 2211 .fabric_logout = qla24xx_fabric_logout, 2212 .calc_req_entries = NULL, 2213 .build_iocbs = NULL, 2214 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2215 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2216 .read_nvram = qla24xx_read_nvram_data, 2217 .write_nvram = qla24xx_write_nvram_data, 2218 .fw_dump = qla24xx_fw_dump, 2219 .beacon_on = qla24xx_beacon_on, 2220 .beacon_off = qla24xx_beacon_off, 2221 .beacon_blink = qla24xx_beacon_blink, 2222 .read_optrom = qla24xx_read_optrom_data, 2223 .write_optrom = qla24xx_write_optrom_data, 2224 .get_flash_version = qla24xx_get_flash_version, 2225 .start_scsi = qla24xx_start_scsi, 2226 .start_scsi_mq = NULL, 2227 .abort_isp = qla2x00_abort_isp, 2228 .iospace_config = qla2x00_iospace_config, 2229 .initialize_adapter = qla2x00_initialize_adapter, 2230 }; 2231 2232 static struct isp_operations qla25xx_isp_ops = { 2233 .pci_config = qla25xx_pci_config, 2234 .reset_chip = qla24xx_reset_chip, 2235 .chip_diag = qla24xx_chip_diag, 2236 .config_rings = qla24xx_config_rings, 2237 .reset_adapter = qla24xx_reset_adapter, 2238 .nvram_config = qla24xx_nvram_config, 2239 .update_fw_options = qla24xx_update_fw_options, 2240 .load_risc = qla24xx_load_risc, 2241 .pci_info_str = qla24xx_pci_info_str, 2242 .fw_version_str = qla24xx_fw_version_str, 2243 .intr_handler = qla24xx_intr_handler, 2244 .enable_intrs = qla24xx_enable_intrs, 2245 .disable_intrs = qla24xx_disable_intrs, 2246 .abort_command = qla24xx_abort_command, 2247 .target_reset = qla24xx_abort_target, 2248 .lun_reset = qla24xx_lun_reset, 2249 .fabric_login = qla24xx_login_fabric, 2250 .fabric_logout = qla24xx_fabric_logout, 2251 .calc_req_entries = NULL, 2252 .build_iocbs = NULL, 2253 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2254 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2255 .read_nvram = qla25xx_read_nvram_data, 2256 .write_nvram = qla25xx_write_nvram_data, 2257 .fw_dump = qla25xx_fw_dump, 2258 .beacon_on = qla24xx_beacon_on, 2259 .beacon_off = qla24xx_beacon_off, 2260 .beacon_blink = qla24xx_beacon_blink, 2261 .read_optrom = qla25xx_read_optrom_data, 2262 .write_optrom = qla24xx_write_optrom_data, 2263 .get_flash_version = qla24xx_get_flash_version, 2264 .start_scsi = qla24xx_dif_start_scsi, 2265 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2266 .abort_isp = qla2x00_abort_isp, 2267 .iospace_config = qla2x00_iospace_config, 2268 .initialize_adapter = qla2x00_initialize_adapter, 2269 }; 2270 2271 static struct isp_operations qla81xx_isp_ops = { 2272 .pci_config = qla25xx_pci_config, 2273 .reset_chip = qla24xx_reset_chip, 2274 .chip_diag = qla24xx_chip_diag, 2275 .config_rings = qla24xx_config_rings, 2276 .reset_adapter = qla24xx_reset_adapter, 2277 .nvram_config = qla81xx_nvram_config, 2278 .update_fw_options = qla81xx_update_fw_options, 2279 .load_risc = qla81xx_load_risc, 2280 .pci_info_str = qla24xx_pci_info_str, 2281 .fw_version_str = qla24xx_fw_version_str, 2282 .intr_handler = qla24xx_intr_handler, 2283 .enable_intrs = qla24xx_enable_intrs, 2284 .disable_intrs = qla24xx_disable_intrs, 2285 .abort_command = qla24xx_abort_command, 2286 .target_reset = qla24xx_abort_target, 2287 .lun_reset = qla24xx_lun_reset, 2288 .fabric_login = qla24xx_login_fabric, 2289 .fabric_logout = qla24xx_fabric_logout, 2290 .calc_req_entries = NULL, 2291 .build_iocbs = NULL, 2292 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2293 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2294 .read_nvram = NULL, 2295 .write_nvram = NULL, 2296 .fw_dump = qla81xx_fw_dump, 2297 .beacon_on = qla24xx_beacon_on, 2298 .beacon_off = qla24xx_beacon_off, 2299 .beacon_blink = qla83xx_beacon_blink, 2300 .read_optrom = qla25xx_read_optrom_data, 2301 .write_optrom = qla24xx_write_optrom_data, 2302 .get_flash_version = qla24xx_get_flash_version, 2303 .start_scsi = qla24xx_dif_start_scsi, 2304 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2305 .abort_isp = qla2x00_abort_isp, 2306 .iospace_config = qla2x00_iospace_config, 2307 .initialize_adapter = qla2x00_initialize_adapter, 2308 }; 2309 2310 static struct isp_operations qla82xx_isp_ops = { 2311 .pci_config = qla82xx_pci_config, 2312 .reset_chip = qla82xx_reset_chip, 2313 .chip_diag = qla24xx_chip_diag, 2314 .config_rings = qla82xx_config_rings, 2315 .reset_adapter = qla24xx_reset_adapter, 2316 .nvram_config = qla81xx_nvram_config, 2317 .update_fw_options = qla24xx_update_fw_options, 2318 .load_risc = qla82xx_load_risc, 2319 .pci_info_str = qla24xx_pci_info_str, 2320 .fw_version_str = qla24xx_fw_version_str, 2321 .intr_handler = qla82xx_intr_handler, 2322 .enable_intrs = qla82xx_enable_intrs, 2323 .disable_intrs = qla82xx_disable_intrs, 2324 .abort_command = qla24xx_abort_command, 2325 .target_reset = qla24xx_abort_target, 2326 .lun_reset = qla24xx_lun_reset, 2327 .fabric_login = qla24xx_login_fabric, 2328 .fabric_logout = qla24xx_fabric_logout, 2329 .calc_req_entries = NULL, 2330 .build_iocbs = NULL, 2331 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2332 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2333 .read_nvram = qla24xx_read_nvram_data, 2334 .write_nvram = qla24xx_write_nvram_data, 2335 .fw_dump = qla82xx_fw_dump, 2336 .beacon_on = qla82xx_beacon_on, 2337 .beacon_off = qla82xx_beacon_off, 2338 .beacon_blink = NULL, 2339 .read_optrom = qla82xx_read_optrom_data, 2340 .write_optrom = qla82xx_write_optrom_data, 2341 .get_flash_version = qla82xx_get_flash_version, 2342 .start_scsi = qla82xx_start_scsi, 2343 .start_scsi_mq = NULL, 2344 .abort_isp = qla82xx_abort_isp, 2345 .iospace_config = qla82xx_iospace_config, 2346 .initialize_adapter = qla2x00_initialize_adapter, 2347 }; 2348 2349 static struct isp_operations qla8044_isp_ops = { 2350 .pci_config = qla82xx_pci_config, 2351 .reset_chip = qla82xx_reset_chip, 2352 .chip_diag = qla24xx_chip_diag, 2353 .config_rings = qla82xx_config_rings, 2354 .reset_adapter = qla24xx_reset_adapter, 2355 .nvram_config = qla81xx_nvram_config, 2356 .update_fw_options = qla24xx_update_fw_options, 2357 .load_risc = qla82xx_load_risc, 2358 .pci_info_str = qla24xx_pci_info_str, 2359 .fw_version_str = qla24xx_fw_version_str, 2360 .intr_handler = qla8044_intr_handler, 2361 .enable_intrs = qla82xx_enable_intrs, 2362 .disable_intrs = qla82xx_disable_intrs, 2363 .abort_command = qla24xx_abort_command, 2364 .target_reset = qla24xx_abort_target, 2365 .lun_reset = qla24xx_lun_reset, 2366 .fabric_login = qla24xx_login_fabric, 2367 .fabric_logout = qla24xx_fabric_logout, 2368 .calc_req_entries = NULL, 2369 .build_iocbs = NULL, 2370 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2371 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2372 .read_nvram = NULL, 2373 .write_nvram = NULL, 2374 .fw_dump = qla8044_fw_dump, 2375 .beacon_on = qla82xx_beacon_on, 2376 .beacon_off = qla82xx_beacon_off, 2377 .beacon_blink = NULL, 2378 .read_optrom = qla8044_read_optrom_data, 2379 .write_optrom = qla8044_write_optrom_data, 2380 .get_flash_version = qla82xx_get_flash_version, 2381 .start_scsi = qla82xx_start_scsi, 2382 .start_scsi_mq = NULL, 2383 .abort_isp = qla8044_abort_isp, 2384 .iospace_config = qla82xx_iospace_config, 2385 .initialize_adapter = qla2x00_initialize_adapter, 2386 }; 2387 2388 static struct isp_operations qla83xx_isp_ops = { 2389 .pci_config = qla25xx_pci_config, 2390 .reset_chip = qla24xx_reset_chip, 2391 .chip_diag = qla24xx_chip_diag, 2392 .config_rings = qla24xx_config_rings, 2393 .reset_adapter = qla24xx_reset_adapter, 2394 .nvram_config = qla81xx_nvram_config, 2395 .update_fw_options = qla81xx_update_fw_options, 2396 .load_risc = qla81xx_load_risc, 2397 .pci_info_str = qla24xx_pci_info_str, 2398 .fw_version_str = qla24xx_fw_version_str, 2399 .intr_handler = qla24xx_intr_handler, 2400 .enable_intrs = qla24xx_enable_intrs, 2401 .disable_intrs = qla24xx_disable_intrs, 2402 .abort_command = qla24xx_abort_command, 2403 .target_reset = qla24xx_abort_target, 2404 .lun_reset = qla24xx_lun_reset, 2405 .fabric_login = qla24xx_login_fabric, 2406 .fabric_logout = qla24xx_fabric_logout, 2407 .calc_req_entries = NULL, 2408 .build_iocbs = NULL, 2409 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2410 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2411 .read_nvram = NULL, 2412 .write_nvram = NULL, 2413 .fw_dump = qla83xx_fw_dump, 2414 .beacon_on = qla24xx_beacon_on, 2415 .beacon_off = qla24xx_beacon_off, 2416 .beacon_blink = qla83xx_beacon_blink, 2417 .read_optrom = qla25xx_read_optrom_data, 2418 .write_optrom = qla24xx_write_optrom_data, 2419 .get_flash_version = qla24xx_get_flash_version, 2420 .start_scsi = qla24xx_dif_start_scsi, 2421 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2422 .abort_isp = qla2x00_abort_isp, 2423 .iospace_config = qla83xx_iospace_config, 2424 .initialize_adapter = qla2x00_initialize_adapter, 2425 }; 2426 2427 static struct isp_operations qlafx00_isp_ops = { 2428 .pci_config = qlafx00_pci_config, 2429 .reset_chip = qlafx00_soft_reset, 2430 .chip_diag = qlafx00_chip_diag, 2431 .config_rings = qlafx00_config_rings, 2432 .reset_adapter = qlafx00_soft_reset, 2433 .nvram_config = NULL, 2434 .update_fw_options = NULL, 2435 .load_risc = NULL, 2436 .pci_info_str = qlafx00_pci_info_str, 2437 .fw_version_str = qlafx00_fw_version_str, 2438 .intr_handler = qlafx00_intr_handler, 2439 .enable_intrs = qlafx00_enable_intrs, 2440 .disable_intrs = qlafx00_disable_intrs, 2441 .abort_command = qla24xx_async_abort_command, 2442 .target_reset = qlafx00_abort_target, 2443 .lun_reset = qlafx00_lun_reset, 2444 .fabric_login = NULL, 2445 .fabric_logout = NULL, 2446 .calc_req_entries = NULL, 2447 .build_iocbs = NULL, 2448 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2449 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2450 .read_nvram = qla24xx_read_nvram_data, 2451 .write_nvram = qla24xx_write_nvram_data, 2452 .fw_dump = NULL, 2453 .beacon_on = qla24xx_beacon_on, 2454 .beacon_off = qla24xx_beacon_off, 2455 .beacon_blink = NULL, 2456 .read_optrom = qla24xx_read_optrom_data, 2457 .write_optrom = qla24xx_write_optrom_data, 2458 .get_flash_version = qla24xx_get_flash_version, 2459 .start_scsi = qlafx00_start_scsi, 2460 .start_scsi_mq = NULL, 2461 .abort_isp = qlafx00_abort_isp, 2462 .iospace_config = qlafx00_iospace_config, 2463 .initialize_adapter = qlafx00_initialize_adapter, 2464 }; 2465 2466 static struct isp_operations qla27xx_isp_ops = { 2467 .pci_config = qla25xx_pci_config, 2468 .reset_chip = qla24xx_reset_chip, 2469 .chip_diag = qla24xx_chip_diag, 2470 .config_rings = qla24xx_config_rings, 2471 .reset_adapter = qla24xx_reset_adapter, 2472 .nvram_config = qla81xx_nvram_config, 2473 .update_fw_options = qla24xx_update_fw_options, 2474 .load_risc = qla81xx_load_risc, 2475 .pci_info_str = qla24xx_pci_info_str, 2476 .fw_version_str = qla24xx_fw_version_str, 2477 .intr_handler = qla24xx_intr_handler, 2478 .enable_intrs = qla24xx_enable_intrs, 2479 .disable_intrs = qla24xx_disable_intrs, 2480 .abort_command = qla24xx_abort_command, 2481 .target_reset = qla24xx_abort_target, 2482 .lun_reset = qla24xx_lun_reset, 2483 .fabric_login = qla24xx_login_fabric, 2484 .fabric_logout = qla24xx_fabric_logout, 2485 .calc_req_entries = NULL, 2486 .build_iocbs = NULL, 2487 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2488 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2489 .read_nvram = NULL, 2490 .write_nvram = NULL, 2491 .fw_dump = qla27xx_fwdump, 2492 .beacon_on = qla24xx_beacon_on, 2493 .beacon_off = qla24xx_beacon_off, 2494 .beacon_blink = qla83xx_beacon_blink, 2495 .read_optrom = qla25xx_read_optrom_data, 2496 .write_optrom = qla24xx_write_optrom_data, 2497 .get_flash_version = qla24xx_get_flash_version, 2498 .start_scsi = qla24xx_dif_start_scsi, 2499 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2500 .abort_isp = qla2x00_abort_isp, 2501 .iospace_config = qla83xx_iospace_config, 2502 .initialize_adapter = qla2x00_initialize_adapter, 2503 }; 2504 2505 static inline void 2506 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2507 { 2508 ha->device_type = DT_EXTENDED_IDS; 2509 switch (ha->pdev->device) { 2510 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2511 ha->isp_type |= DT_ISP2100; 2512 ha->device_type &= ~DT_EXTENDED_IDS; 2513 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2514 break; 2515 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2516 ha->isp_type |= DT_ISP2200; 2517 ha->device_type &= ~DT_EXTENDED_IDS; 2518 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2519 break; 2520 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2521 ha->isp_type |= DT_ISP2300; 2522 ha->device_type |= DT_ZIO_SUPPORTED; 2523 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2524 break; 2525 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2526 ha->isp_type |= DT_ISP2312; 2527 ha->device_type |= DT_ZIO_SUPPORTED; 2528 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2529 break; 2530 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2531 ha->isp_type |= DT_ISP2322; 2532 ha->device_type |= DT_ZIO_SUPPORTED; 2533 if (ha->pdev->subsystem_vendor == 0x1028 && 2534 ha->pdev->subsystem_device == 0x0170) 2535 ha->device_type |= DT_OEM_001; 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2537 break; 2538 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2539 ha->isp_type |= DT_ISP6312; 2540 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2541 break; 2542 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2543 ha->isp_type |= DT_ISP6322; 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2545 break; 2546 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2547 ha->isp_type |= DT_ISP2422; 2548 ha->device_type |= DT_ZIO_SUPPORTED; 2549 ha->device_type |= DT_FWI2; 2550 ha->device_type |= DT_IIDMA; 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2552 break; 2553 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2554 ha->isp_type |= DT_ISP2432; 2555 ha->device_type |= DT_ZIO_SUPPORTED; 2556 ha->device_type |= DT_FWI2; 2557 ha->device_type |= DT_IIDMA; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2561 ha->isp_type |= DT_ISP8432; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->device_type |= DT_FWI2; 2564 ha->device_type |= DT_IIDMA; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2568 ha->isp_type |= DT_ISP5422; 2569 ha->device_type |= DT_FWI2; 2570 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2571 break; 2572 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2573 ha->isp_type |= DT_ISP5432; 2574 ha->device_type |= DT_FWI2; 2575 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2576 break; 2577 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2578 ha->isp_type |= DT_ISP2532; 2579 ha->device_type |= DT_ZIO_SUPPORTED; 2580 ha->device_type |= DT_FWI2; 2581 ha->device_type |= DT_IIDMA; 2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2583 break; 2584 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2585 ha->isp_type |= DT_ISP8001; 2586 ha->device_type |= DT_ZIO_SUPPORTED; 2587 ha->device_type |= DT_FWI2; 2588 ha->device_type |= DT_IIDMA; 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2590 break; 2591 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2592 ha->isp_type |= DT_ISP8021; 2593 ha->device_type |= DT_ZIO_SUPPORTED; 2594 ha->device_type |= DT_FWI2; 2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2596 /* Initialize 82XX ISP flags */ 2597 qla82xx_init_flags(ha); 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2600 ha->isp_type |= DT_ISP8044; 2601 ha->device_type |= DT_ZIO_SUPPORTED; 2602 ha->device_type |= DT_FWI2; 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2604 /* Initialize 82XX ISP flags */ 2605 qla82xx_init_flags(ha); 2606 break; 2607 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2608 ha->isp_type |= DT_ISP2031; 2609 ha->device_type |= DT_ZIO_SUPPORTED; 2610 ha->device_type |= DT_FWI2; 2611 ha->device_type |= DT_IIDMA; 2612 ha->device_type |= DT_T10_PI; 2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2614 break; 2615 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2616 ha->isp_type |= DT_ISP8031; 2617 ha->device_type |= DT_ZIO_SUPPORTED; 2618 ha->device_type |= DT_FWI2; 2619 ha->device_type |= DT_IIDMA; 2620 ha->device_type |= DT_T10_PI; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2622 break; 2623 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2624 ha->isp_type |= DT_ISPFX00; 2625 break; 2626 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2627 ha->isp_type |= DT_ISP2071; 2628 ha->device_type |= DT_ZIO_SUPPORTED; 2629 ha->device_type |= DT_FWI2; 2630 ha->device_type |= DT_IIDMA; 2631 ha->device_type |= DT_T10_PI; 2632 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2633 break; 2634 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2635 ha->isp_type |= DT_ISP2271; 2636 ha->device_type |= DT_ZIO_SUPPORTED; 2637 ha->device_type |= DT_FWI2; 2638 ha->device_type |= DT_IIDMA; 2639 ha->device_type |= DT_T10_PI; 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2643 ha->isp_type |= DT_ISP2261; 2644 ha->device_type |= DT_ZIO_SUPPORTED; 2645 ha->device_type |= DT_FWI2; 2646 ha->device_type |= DT_IIDMA; 2647 ha->device_type |= DT_T10_PI; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2651 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2652 ha->isp_type |= DT_ISP2081; 2653 ha->device_type |= DT_ZIO_SUPPORTED; 2654 ha->device_type |= DT_FWI2; 2655 ha->device_type |= DT_IIDMA; 2656 ha->device_type |= DT_T10_PI; 2657 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2658 break; 2659 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2660 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2661 ha->isp_type |= DT_ISP2281; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 ha->device_type |= DT_FWI2; 2664 ha->device_type |= DT_IIDMA; 2665 ha->device_type |= DT_T10_PI; 2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2667 break; 2668 } 2669 2670 if (IS_QLA82XX(ha)) 2671 ha->port_no = ha->portnum & 1; 2672 else { 2673 /* Get adapter physical port no from interrupt pin register. */ 2674 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2675 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2676 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2677 ha->port_no--; 2678 else 2679 ha->port_no = !(ha->port_no & 1); 2680 } 2681 2682 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2683 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2684 ha->device_type, ha->port_no, ha->fw_srisc_address); 2685 } 2686 2687 static void 2688 qla2xxx_scan_start(struct Scsi_Host *shost) 2689 { 2690 scsi_qla_host_t *vha = shost_priv(shost); 2691 2692 if (vha->hw->flags.running_gold_fw) 2693 return; 2694 2695 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2696 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2697 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2698 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2699 } 2700 2701 static int 2702 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2703 { 2704 scsi_qla_host_t *vha = shost_priv(shost); 2705 2706 if (test_bit(UNLOADING, &vha->dpc_flags)) 2707 return 1; 2708 if (!vha->host) 2709 return 1; 2710 if (time > vha->hw->loop_reset_delay * HZ) 2711 return 1; 2712 2713 return atomic_read(&vha->loop_state) == LOOP_READY; 2714 } 2715 2716 static void qla2x00_iocb_work_fn(struct work_struct *work) 2717 { 2718 struct scsi_qla_host *vha = container_of(work, 2719 struct scsi_qla_host, iocb_work); 2720 struct qla_hw_data *ha = vha->hw; 2721 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2722 int i = 2; 2723 unsigned long flags; 2724 2725 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2726 return; 2727 2728 while (!list_empty(&vha->work_list) && i > 0) { 2729 qla2x00_do_work(vha); 2730 i--; 2731 } 2732 2733 spin_lock_irqsave(&vha->work_lock, flags); 2734 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2735 spin_unlock_irqrestore(&vha->work_lock, flags); 2736 } 2737 2738 /* 2739 * PCI driver interface 2740 */ 2741 static int 2742 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2743 { 2744 int ret = -ENODEV; 2745 struct Scsi_Host *host; 2746 scsi_qla_host_t *base_vha = NULL; 2747 struct qla_hw_data *ha; 2748 char pci_info[30]; 2749 char fw_str[30], wq_name[30]; 2750 struct scsi_host_template *sht; 2751 int bars, mem_only = 0; 2752 uint16_t req_length = 0, rsp_length = 0; 2753 struct req_que *req = NULL; 2754 struct rsp_que *rsp = NULL; 2755 int i; 2756 2757 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2758 sht = &qla2xxx_driver_template; 2759 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2763 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2764 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2765 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2766 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2776 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2777 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2778 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2779 mem_only = 1; 2780 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2781 "Mem only adapter.\n"); 2782 } 2783 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2784 "Bars=%d.\n", bars); 2785 2786 if (mem_only) { 2787 if (pci_enable_device_mem(pdev)) 2788 return ret; 2789 } else { 2790 if (pci_enable_device(pdev)) 2791 return ret; 2792 } 2793 2794 /* This may fail but that's ok */ 2795 pci_enable_pcie_error_reporting(pdev); 2796 2797 /* Turn off T10-DIF when FC-NVMe is enabled */ 2798 if (ql2xnvmeenable) 2799 ql2xenabledif = 0; 2800 2801 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2802 if (!ha) { 2803 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2804 "Unable to allocate memory for ha.\n"); 2805 goto disable_device; 2806 } 2807 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2808 "Memory allocated for ha=%p.\n", ha); 2809 ha->pdev = pdev; 2810 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2811 spin_lock_init(&ha->tgt.q_full_lock); 2812 spin_lock_init(&ha->tgt.sess_lock); 2813 spin_lock_init(&ha->tgt.atio_lock); 2814 2815 atomic_set(&ha->nvme_active_aen_cnt, 0); 2816 2817 /* Clear our data area */ 2818 ha->bars = bars; 2819 ha->mem_only = mem_only; 2820 spin_lock_init(&ha->hardware_lock); 2821 spin_lock_init(&ha->vport_slock); 2822 mutex_init(&ha->selflogin_lock); 2823 mutex_init(&ha->optrom_mutex); 2824 2825 /* Set ISP-type information. */ 2826 qla2x00_set_isp_flags(ha); 2827 2828 /* Set EEH reset type to fundamental if required by hba */ 2829 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2830 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2831 pdev->needs_freset = 1; 2832 2833 ha->prev_topology = 0; 2834 ha->init_cb_size = sizeof(init_cb_t); 2835 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2836 ha->optrom_size = OPTROM_SIZE_2300; 2837 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2838 atomic_set(&ha->num_pend_mbx_stage1, 0); 2839 atomic_set(&ha->num_pend_mbx_stage2, 0); 2840 atomic_set(&ha->num_pend_mbx_stage3, 0); 2841 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2842 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2843 2844 /* Assign ISP specific operations. */ 2845 if (IS_QLA2100(ha)) { 2846 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2847 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2848 req_length = REQUEST_ENTRY_CNT_2100; 2849 rsp_length = RESPONSE_ENTRY_CNT_2100; 2850 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2851 ha->gid_list_info_size = 4; 2852 ha->flash_conf_off = ~0; 2853 ha->flash_data_off = ~0; 2854 ha->nvram_conf_off = ~0; 2855 ha->nvram_data_off = ~0; 2856 ha->isp_ops = &qla2100_isp_ops; 2857 } else if (IS_QLA2200(ha)) { 2858 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2859 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2860 req_length = REQUEST_ENTRY_CNT_2200; 2861 rsp_length = RESPONSE_ENTRY_CNT_2100; 2862 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2863 ha->gid_list_info_size = 4; 2864 ha->flash_conf_off = ~0; 2865 ha->flash_data_off = ~0; 2866 ha->nvram_conf_off = ~0; 2867 ha->nvram_data_off = ~0; 2868 ha->isp_ops = &qla2100_isp_ops; 2869 } else if (IS_QLA23XX(ha)) { 2870 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2871 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2872 req_length = REQUEST_ENTRY_CNT_2200; 2873 rsp_length = RESPONSE_ENTRY_CNT_2300; 2874 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2875 ha->gid_list_info_size = 6; 2876 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2877 ha->optrom_size = OPTROM_SIZE_2322; 2878 ha->flash_conf_off = ~0; 2879 ha->flash_data_off = ~0; 2880 ha->nvram_conf_off = ~0; 2881 ha->nvram_data_off = ~0; 2882 ha->isp_ops = &qla2300_isp_ops; 2883 } else if (IS_QLA24XX_TYPE(ha)) { 2884 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2885 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2886 req_length = REQUEST_ENTRY_CNT_24XX; 2887 rsp_length = RESPONSE_ENTRY_CNT_2300; 2888 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2889 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2890 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2891 ha->gid_list_info_size = 8; 2892 ha->optrom_size = OPTROM_SIZE_24XX; 2893 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2894 ha->isp_ops = &qla24xx_isp_ops; 2895 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2896 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2897 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2898 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2899 } else if (IS_QLA25XX(ha)) { 2900 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2901 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2902 req_length = REQUEST_ENTRY_CNT_24XX; 2903 rsp_length = RESPONSE_ENTRY_CNT_2300; 2904 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2905 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2906 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2907 ha->gid_list_info_size = 8; 2908 ha->optrom_size = OPTROM_SIZE_25XX; 2909 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2910 ha->isp_ops = &qla25xx_isp_ops; 2911 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2912 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2913 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2914 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2915 } else if (IS_QLA81XX(ha)) { 2916 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2917 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2918 req_length = REQUEST_ENTRY_CNT_24XX; 2919 rsp_length = RESPONSE_ENTRY_CNT_2300; 2920 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2921 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2922 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2923 ha->gid_list_info_size = 8; 2924 ha->optrom_size = OPTROM_SIZE_81XX; 2925 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2926 ha->isp_ops = &qla81xx_isp_ops; 2927 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2928 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2929 ha->nvram_conf_off = ~0; 2930 ha->nvram_data_off = ~0; 2931 } else if (IS_QLA82XX(ha)) { 2932 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2933 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2934 req_length = REQUEST_ENTRY_CNT_82XX; 2935 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2936 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2937 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2938 ha->gid_list_info_size = 8; 2939 ha->optrom_size = OPTROM_SIZE_82XX; 2940 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2941 ha->isp_ops = &qla82xx_isp_ops; 2942 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2943 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2944 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2945 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2946 } else if (IS_QLA8044(ha)) { 2947 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2948 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2949 req_length = REQUEST_ENTRY_CNT_82XX; 2950 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2951 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2952 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2953 ha->gid_list_info_size = 8; 2954 ha->optrom_size = OPTROM_SIZE_83XX; 2955 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2956 ha->isp_ops = &qla8044_isp_ops; 2957 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2958 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2959 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2960 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2961 } else if (IS_QLA83XX(ha)) { 2962 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2963 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2964 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2965 req_length = REQUEST_ENTRY_CNT_83XX; 2966 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2967 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2968 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2969 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2970 ha->gid_list_info_size = 8; 2971 ha->optrom_size = OPTROM_SIZE_83XX; 2972 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2973 ha->isp_ops = &qla83xx_isp_ops; 2974 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2975 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2976 ha->nvram_conf_off = ~0; 2977 ha->nvram_data_off = ~0; 2978 } else if (IS_QLAFX00(ha)) { 2979 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2980 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2981 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2982 req_length = REQUEST_ENTRY_CNT_FX00; 2983 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2984 ha->isp_ops = &qlafx00_isp_ops; 2985 ha->port_down_retry_count = 30; /* default value */ 2986 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2987 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2988 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2989 ha->mr.fw_hbt_en = 1; 2990 ha->mr.host_info_resend = false; 2991 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2992 } else if (IS_QLA27XX(ha)) { 2993 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2994 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2995 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2996 req_length = REQUEST_ENTRY_CNT_83XX; 2997 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2998 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2999 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3000 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3001 ha->gid_list_info_size = 8; 3002 ha->optrom_size = OPTROM_SIZE_83XX; 3003 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3004 ha->isp_ops = &qla27xx_isp_ops; 3005 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3006 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3007 ha->nvram_conf_off = ~0; 3008 ha->nvram_data_off = ~0; 3009 } else if (IS_QLA28XX(ha)) { 3010 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3011 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3012 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3013 req_length = REQUEST_ENTRY_CNT_24XX; 3014 rsp_length = RESPONSE_ENTRY_CNT_2300; 3015 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3016 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3017 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3018 ha->gid_list_info_size = 8; 3019 ha->optrom_size = OPTROM_SIZE_28XX; 3020 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3021 ha->isp_ops = &qla27xx_isp_ops; 3022 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3023 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3024 ha->nvram_conf_off = ~0; 3025 ha->nvram_data_off = ~0; 3026 } 3027 3028 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3029 "mbx_count=%d, req_length=%d, " 3030 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3031 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3032 "max_fibre_devices=%d.\n", 3033 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3034 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3035 ha->nvram_npiv_size, ha->max_fibre_devices); 3036 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3037 "isp_ops=%p, flash_conf_off=%d, " 3038 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3039 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3040 ha->nvram_conf_off, ha->nvram_data_off); 3041 3042 /* Configure PCI I/O space */ 3043 ret = ha->isp_ops->iospace_config(ha); 3044 if (ret) 3045 goto iospace_config_failed; 3046 3047 ql_log_pci(ql_log_info, pdev, 0x001d, 3048 "Found an ISP%04X irq %d iobase 0x%p.\n", 3049 pdev->device, pdev->irq, ha->iobase); 3050 mutex_init(&ha->vport_lock); 3051 mutex_init(&ha->mq_lock); 3052 init_completion(&ha->mbx_cmd_comp); 3053 complete(&ha->mbx_cmd_comp); 3054 init_completion(&ha->mbx_intr_comp); 3055 init_completion(&ha->dcbx_comp); 3056 init_completion(&ha->lb_portup_comp); 3057 3058 set_bit(0, (unsigned long *) ha->vp_idx_map); 3059 3060 qla2x00_config_dma_addressing(ha); 3061 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3062 "64 Bit addressing is %s.\n", 3063 ha->flags.enable_64bit_addressing ? "enable" : 3064 "disable"); 3065 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3066 if (ret) { 3067 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3068 "Failed to allocate memory for adapter, aborting.\n"); 3069 3070 goto probe_hw_failed; 3071 } 3072 3073 req->max_q_depth = MAX_Q_DEPTH; 3074 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3075 req->max_q_depth = ql2xmaxqdepth; 3076 3077 3078 base_vha = qla2x00_create_host(sht, ha); 3079 if (!base_vha) { 3080 ret = -ENOMEM; 3081 goto probe_hw_failed; 3082 } 3083 3084 pci_set_drvdata(pdev, base_vha); 3085 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3086 3087 host = base_vha->host; 3088 base_vha->req = req; 3089 if (IS_QLA2XXX_MIDTYPE(ha)) 3090 base_vha->mgmt_svr_loop_id = 3091 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3092 else 3093 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3094 base_vha->vp_idx; 3095 3096 /* Setup fcport template structure. */ 3097 ha->mr.fcport.vha = base_vha; 3098 ha->mr.fcport.port_type = FCT_UNKNOWN; 3099 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3100 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3101 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3102 ha->mr.fcport.scan_state = 1; 3103 3104 /* Set the SG table size based on ISP type */ 3105 if (!IS_FWI2_CAPABLE(ha)) { 3106 if (IS_QLA2100(ha)) 3107 host->sg_tablesize = 32; 3108 } else { 3109 if (!IS_QLA82XX(ha)) 3110 host->sg_tablesize = QLA_SG_ALL; 3111 } 3112 host->max_id = ha->max_fibre_devices; 3113 host->cmd_per_lun = 3; 3114 host->unique_id = host->host_no; 3115 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3116 host->max_cmd_len = 32; 3117 else 3118 host->max_cmd_len = MAX_CMDSZ; 3119 host->max_channel = MAX_BUSES - 1; 3120 /* Older HBAs support only 16-bit LUNs */ 3121 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3122 ql2xmaxlun > 0xffff) 3123 host->max_lun = 0xffff; 3124 else 3125 host->max_lun = ql2xmaxlun; 3126 host->transportt = qla2xxx_transport_template; 3127 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3128 3129 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3130 "max_id=%d this_id=%d " 3131 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3132 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3133 host->this_id, host->cmd_per_lun, host->unique_id, 3134 host->max_cmd_len, host->max_channel, host->max_lun, 3135 host->transportt, sht->vendor_id); 3136 3137 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3138 3139 /* Set up the irqs */ 3140 ret = qla2x00_request_irqs(ha, rsp); 3141 if (ret) 3142 goto probe_failed; 3143 3144 /* Alloc arrays of request and response ring ptrs */ 3145 ret = qla2x00_alloc_queues(ha, req, rsp); 3146 if (ret) { 3147 ql_log(ql_log_fatal, base_vha, 0x003d, 3148 "Failed to allocate memory for queue pointers..." 3149 "aborting.\n"); 3150 ret = -ENODEV; 3151 goto probe_failed; 3152 } 3153 3154 if (ha->mqenable) { 3155 /* number of hardware queues supported by blk/scsi-mq*/ 3156 host->nr_hw_queues = ha->max_qpairs; 3157 3158 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3159 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3160 } else { 3161 if (ql2xnvmeenable) { 3162 host->nr_hw_queues = ha->max_qpairs; 3163 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3164 "FC-NVMe support is enabled, HW queues=%d\n", 3165 host->nr_hw_queues); 3166 } else { 3167 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3168 "blk/scsi-mq disabled.\n"); 3169 } 3170 } 3171 3172 qlt_probe_one_stage1(base_vha, ha); 3173 3174 pci_save_state(pdev); 3175 3176 /* Assign back pointers */ 3177 rsp->req = req; 3178 req->rsp = rsp; 3179 3180 if (IS_QLAFX00(ha)) { 3181 ha->rsp_q_map[0] = rsp; 3182 ha->req_q_map[0] = req; 3183 set_bit(0, ha->req_qid_map); 3184 set_bit(0, ha->rsp_qid_map); 3185 } 3186 3187 /* FWI2-capable only. */ 3188 req->req_q_in = &ha->iobase->isp24.req_q_in; 3189 req->req_q_out = &ha->iobase->isp24.req_q_out; 3190 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3191 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3192 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3193 IS_QLA28XX(ha)) { 3194 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3195 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3196 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3197 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3198 } 3199 3200 if (IS_QLAFX00(ha)) { 3201 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3202 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3203 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3204 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3205 } 3206 3207 if (IS_P3P_TYPE(ha)) { 3208 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3209 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3210 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3211 } 3212 3213 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3214 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3215 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3216 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3217 "req->req_q_in=%p req->req_q_out=%p " 3218 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3219 req->req_q_in, req->req_q_out, 3220 rsp->rsp_q_in, rsp->rsp_q_out); 3221 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3222 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3223 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3224 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3225 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3226 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3227 3228 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3229 if (unlikely(!ha->wq)) { 3230 ret = -ENOMEM; 3231 goto probe_failed; 3232 } 3233 3234 if (ha->isp_ops->initialize_adapter(base_vha)) { 3235 ql_log(ql_log_fatal, base_vha, 0x00d6, 3236 "Failed to initialize adapter - Adapter flags %x.\n", 3237 base_vha->device_flags); 3238 3239 if (IS_QLA82XX(ha)) { 3240 qla82xx_idc_lock(ha); 3241 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3242 QLA8XXX_DEV_FAILED); 3243 qla82xx_idc_unlock(ha); 3244 ql_log(ql_log_fatal, base_vha, 0x00d7, 3245 "HW State: FAILED.\n"); 3246 } else if (IS_QLA8044(ha)) { 3247 qla8044_idc_lock(ha); 3248 qla8044_wr_direct(base_vha, 3249 QLA8044_CRB_DEV_STATE_INDEX, 3250 QLA8XXX_DEV_FAILED); 3251 qla8044_idc_unlock(ha); 3252 ql_log(ql_log_fatal, base_vha, 0x0150, 3253 "HW State: FAILED.\n"); 3254 } 3255 3256 ret = -ENODEV; 3257 goto probe_failed; 3258 } 3259 3260 if (IS_QLAFX00(ha)) 3261 host->can_queue = QLAFX00_MAX_CANQUEUE; 3262 else 3263 host->can_queue = req->num_outstanding_cmds - 10; 3264 3265 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3266 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3267 host->can_queue, base_vha->req, 3268 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3269 3270 if (ha->mqenable) { 3271 bool startit = false; 3272 3273 if (QLA_TGT_MODE_ENABLED()) 3274 startit = false; 3275 3276 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3277 startit = true; 3278 3279 /* Create start of day qpairs for Block MQ */ 3280 for (i = 0; i < ha->max_qpairs; i++) 3281 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3282 } 3283 3284 if (ha->flags.running_gold_fw) 3285 goto skip_dpc; 3286 3287 /* 3288 * Startup the kernel thread for this host adapter 3289 */ 3290 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3291 "%s_dpc", base_vha->host_str); 3292 if (IS_ERR(ha->dpc_thread)) { 3293 ql_log(ql_log_fatal, base_vha, 0x00ed, 3294 "Failed to start DPC thread.\n"); 3295 ret = PTR_ERR(ha->dpc_thread); 3296 ha->dpc_thread = NULL; 3297 goto probe_failed; 3298 } 3299 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3300 "DPC thread started successfully.\n"); 3301 3302 /* 3303 * If we're not coming up in initiator mode, we might sit for 3304 * a while without waking up the dpc thread, which leads to a 3305 * stuck process warning. So just kick the dpc once here and 3306 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3307 */ 3308 qla2xxx_wake_dpc(base_vha); 3309 3310 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3311 3312 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3313 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3314 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3315 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3316 3317 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3318 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3319 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3320 INIT_WORK(&ha->idc_state_handler, 3321 qla83xx_idc_state_handler_work); 3322 INIT_WORK(&ha->nic_core_unrecoverable, 3323 qla83xx_nic_core_unrecoverable_work); 3324 } 3325 3326 skip_dpc: 3327 list_add_tail(&base_vha->list, &ha->vp_list); 3328 base_vha->host->irq = ha->pdev->irq; 3329 3330 /* Initialized the timer */ 3331 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3332 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3333 "Started qla2x00_timer with " 3334 "interval=%d.\n", WATCH_INTERVAL); 3335 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3336 "Detected hba at address=%p.\n", 3337 ha); 3338 3339 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3340 if (ha->fw_attributes & BIT_4) { 3341 int prot = 0, guard; 3342 3343 base_vha->flags.difdix_supported = 1; 3344 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3345 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3346 if (ql2xenabledif == 1) 3347 prot = SHOST_DIX_TYPE0_PROTECTION; 3348 if (ql2xprotmask) 3349 scsi_host_set_prot(host, ql2xprotmask); 3350 else 3351 scsi_host_set_prot(host, 3352 prot | SHOST_DIF_TYPE1_PROTECTION 3353 | SHOST_DIF_TYPE2_PROTECTION 3354 | SHOST_DIF_TYPE3_PROTECTION 3355 | SHOST_DIX_TYPE1_PROTECTION 3356 | SHOST_DIX_TYPE2_PROTECTION 3357 | SHOST_DIX_TYPE3_PROTECTION); 3358 3359 guard = SHOST_DIX_GUARD_CRC; 3360 3361 if (IS_PI_IPGUARD_CAPABLE(ha) && 3362 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3363 guard |= SHOST_DIX_GUARD_IP; 3364 3365 if (ql2xprotguard) 3366 scsi_host_set_guard(host, ql2xprotguard); 3367 else 3368 scsi_host_set_guard(host, guard); 3369 } else 3370 base_vha->flags.difdix_supported = 0; 3371 } 3372 3373 ha->isp_ops->enable_intrs(ha); 3374 3375 if (IS_QLAFX00(ha)) { 3376 ret = qlafx00_fx_disc(base_vha, 3377 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3378 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3379 QLA_SG_ALL : 128; 3380 } 3381 3382 ret = scsi_add_host(host, &pdev->dev); 3383 if (ret) 3384 goto probe_failed; 3385 3386 base_vha->flags.init_done = 1; 3387 base_vha->flags.online = 1; 3388 ha->prev_minidump_failed = 0; 3389 3390 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3391 "Init done and hba is online.\n"); 3392 3393 if (qla_ini_mode_enabled(base_vha) || 3394 qla_dual_mode_enabled(base_vha)) 3395 scsi_scan_host(host); 3396 else 3397 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3398 "skipping scsi_scan_host() for non-initiator port\n"); 3399 3400 qla2x00_alloc_sysfs_attr(base_vha); 3401 3402 if (IS_QLAFX00(ha)) { 3403 ret = qlafx00_fx_disc(base_vha, 3404 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3405 3406 /* Register system information */ 3407 ret = qlafx00_fx_disc(base_vha, 3408 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3409 } 3410 3411 qla2x00_init_host_attr(base_vha); 3412 3413 qla2x00_dfs_setup(base_vha); 3414 3415 ql_log(ql_log_info, base_vha, 0x00fb, 3416 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3417 ql_log(ql_log_info, base_vha, 0x00fc, 3418 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3419 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3420 sizeof(pci_info)), 3421 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3422 base_vha->host_no, 3423 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3424 3425 qlt_add_target(ha, base_vha); 3426 3427 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3428 3429 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3430 return -ENODEV; 3431 3432 if (ha->flags.detected_lr_sfp) { 3433 ql_log(ql_log_info, base_vha, 0xffff, 3434 "Reset chip to pick up LR SFP setting\n"); 3435 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3436 qla2xxx_wake_dpc(base_vha); 3437 } 3438 3439 return 0; 3440 3441 probe_failed: 3442 if (base_vha->gnl.l) { 3443 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3444 base_vha->gnl.l, base_vha->gnl.ldma); 3445 base_vha->gnl.l = NULL; 3446 } 3447 3448 if (base_vha->timer_active) 3449 qla2x00_stop_timer(base_vha); 3450 base_vha->flags.online = 0; 3451 if (ha->dpc_thread) { 3452 struct task_struct *t = ha->dpc_thread; 3453 3454 ha->dpc_thread = NULL; 3455 kthread_stop(t); 3456 } 3457 3458 qla2x00_free_device(base_vha); 3459 scsi_host_put(base_vha->host); 3460 /* 3461 * Need to NULL out local req/rsp after 3462 * qla2x00_free_device => qla2x00_free_queues frees 3463 * what these are pointing to. Or else we'll 3464 * fall over below in qla2x00_free_req/rsp_que. 3465 */ 3466 req = NULL; 3467 rsp = NULL; 3468 3469 probe_hw_failed: 3470 qla2x00_mem_free(ha); 3471 qla2x00_free_req_que(ha, req); 3472 qla2x00_free_rsp_que(ha, rsp); 3473 qla2x00_clear_drv_active(ha); 3474 3475 iospace_config_failed: 3476 if (IS_P3P_TYPE(ha)) { 3477 if (!ha->nx_pcibase) 3478 iounmap((device_reg_t *)ha->nx_pcibase); 3479 if (!ql2xdbwr) 3480 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3481 } else { 3482 if (ha->iobase) 3483 iounmap(ha->iobase); 3484 if (ha->cregbase) 3485 iounmap(ha->cregbase); 3486 } 3487 pci_release_selected_regions(ha->pdev, ha->bars); 3488 kfree(ha); 3489 3490 disable_device: 3491 pci_disable_device(pdev); 3492 return ret; 3493 } 3494 3495 static void 3496 qla2x00_shutdown(struct pci_dev *pdev) 3497 { 3498 scsi_qla_host_t *vha; 3499 struct qla_hw_data *ha; 3500 3501 vha = pci_get_drvdata(pdev); 3502 ha = vha->hw; 3503 3504 ql_log(ql_log_info, vha, 0xfffa, 3505 "Adapter shutdown\n"); 3506 3507 /* 3508 * Prevent future board_disable and wait 3509 * until any pending board_disable has completed. 3510 */ 3511 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3512 cancel_work_sync(&ha->board_disable); 3513 3514 if (!atomic_read(&pdev->enable_cnt)) 3515 return; 3516 3517 /* Notify ISPFX00 firmware */ 3518 if (IS_QLAFX00(ha)) 3519 qlafx00_driver_shutdown(vha, 20); 3520 3521 /* Turn-off FCE trace */ 3522 if (ha->flags.fce_enabled) { 3523 qla2x00_disable_fce_trace(vha, NULL, NULL); 3524 ha->flags.fce_enabled = 0; 3525 } 3526 3527 /* Turn-off EFT trace */ 3528 if (ha->eft) 3529 qla2x00_disable_eft_trace(vha); 3530 3531 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3532 IS_QLA28XX(ha)) { 3533 if (ha->flags.fw_started) 3534 qla2x00_abort_isp_cleanup(vha); 3535 } else { 3536 /* Stop currently executing firmware. */ 3537 qla2x00_try_to_stop_firmware(vha); 3538 } 3539 3540 /* Disable timer */ 3541 if (vha->timer_active) 3542 qla2x00_stop_timer(vha); 3543 3544 /* Turn adapter off line */ 3545 vha->flags.online = 0; 3546 3547 /* turn-off interrupts on the card */ 3548 if (ha->interrupts_on) { 3549 vha->flags.init_done = 0; 3550 ha->isp_ops->disable_intrs(ha); 3551 } 3552 3553 qla2x00_free_irqs(vha); 3554 3555 qla2x00_free_fw_dump(ha); 3556 3557 pci_disable_device(pdev); 3558 ql_log(ql_log_info, vha, 0xfffe, 3559 "Adapter shutdown successfully.\n"); 3560 } 3561 3562 /* Deletes all the virtual ports for a given ha */ 3563 static void 3564 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3565 { 3566 scsi_qla_host_t *vha; 3567 unsigned long flags; 3568 3569 mutex_lock(&ha->vport_lock); 3570 while (ha->cur_vport_count) { 3571 spin_lock_irqsave(&ha->vport_slock, flags); 3572 3573 BUG_ON(base_vha->list.next == &ha->vp_list); 3574 /* This assumes first entry in ha->vp_list is always base vha */ 3575 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3576 scsi_host_get(vha->host); 3577 3578 spin_unlock_irqrestore(&ha->vport_slock, flags); 3579 mutex_unlock(&ha->vport_lock); 3580 3581 qla_nvme_delete(vha); 3582 3583 fc_vport_terminate(vha->fc_vport); 3584 scsi_host_put(vha->host); 3585 3586 mutex_lock(&ha->vport_lock); 3587 } 3588 mutex_unlock(&ha->vport_lock); 3589 } 3590 3591 /* Stops all deferred work threads */ 3592 static void 3593 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3594 { 3595 /* Cancel all work and destroy DPC workqueues */ 3596 if (ha->dpc_lp_wq) { 3597 cancel_work_sync(&ha->idc_aen); 3598 destroy_workqueue(ha->dpc_lp_wq); 3599 ha->dpc_lp_wq = NULL; 3600 } 3601 3602 if (ha->dpc_hp_wq) { 3603 cancel_work_sync(&ha->nic_core_reset); 3604 cancel_work_sync(&ha->idc_state_handler); 3605 cancel_work_sync(&ha->nic_core_unrecoverable); 3606 destroy_workqueue(ha->dpc_hp_wq); 3607 ha->dpc_hp_wq = NULL; 3608 } 3609 3610 /* Kill the kernel thread for this host */ 3611 if (ha->dpc_thread) { 3612 struct task_struct *t = ha->dpc_thread; 3613 3614 /* 3615 * qla2xxx_wake_dpc checks for ->dpc_thread 3616 * so we need to zero it out. 3617 */ 3618 ha->dpc_thread = NULL; 3619 kthread_stop(t); 3620 } 3621 } 3622 3623 static void 3624 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3625 { 3626 if (IS_QLA82XX(ha)) { 3627 3628 iounmap((device_reg_t *)ha->nx_pcibase); 3629 if (!ql2xdbwr) 3630 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3631 } else { 3632 if (ha->iobase) 3633 iounmap(ha->iobase); 3634 3635 if (ha->cregbase) 3636 iounmap(ha->cregbase); 3637 3638 if (ha->mqiobase) 3639 iounmap(ha->mqiobase); 3640 3641 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3642 ha->msixbase) 3643 iounmap(ha->msixbase); 3644 } 3645 } 3646 3647 static void 3648 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3649 { 3650 if (IS_QLA8044(ha)) { 3651 qla8044_idc_lock(ha); 3652 qla8044_clear_drv_active(ha); 3653 qla8044_idc_unlock(ha); 3654 } else if (IS_QLA82XX(ha)) { 3655 qla82xx_idc_lock(ha); 3656 qla82xx_clear_drv_active(ha); 3657 qla82xx_idc_unlock(ha); 3658 } 3659 } 3660 3661 static void 3662 qla2x00_remove_one(struct pci_dev *pdev) 3663 { 3664 scsi_qla_host_t *base_vha; 3665 struct qla_hw_data *ha; 3666 3667 base_vha = pci_get_drvdata(pdev); 3668 ha = base_vha->hw; 3669 ql_log(ql_log_info, base_vha, 0xb079, 3670 "Removing driver\n"); 3671 3672 /* Indicate device removal to prevent future board_disable and wait 3673 * until any pending board_disable has completed. */ 3674 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3675 cancel_work_sync(&ha->board_disable); 3676 3677 /* 3678 * If the PCI device is disabled then there was a PCI-disconnect and 3679 * qla2x00_disable_board_on_pci_error has taken care of most of the 3680 * resources. 3681 */ 3682 if (!atomic_read(&pdev->enable_cnt)) { 3683 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3684 base_vha->gnl.l, base_vha->gnl.ldma); 3685 base_vha->gnl.l = NULL; 3686 scsi_host_put(base_vha->host); 3687 kfree(ha); 3688 pci_set_drvdata(pdev, NULL); 3689 return; 3690 } 3691 qla2x00_wait_for_hba_ready(base_vha); 3692 3693 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3694 IS_QLA28XX(ha)) { 3695 if (ha->flags.fw_started) 3696 qla2x00_abort_isp_cleanup(base_vha); 3697 } else if (!IS_QLAFX00(ha)) { 3698 if (IS_QLA8031(ha)) { 3699 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3700 "Clearing fcoe driver presence.\n"); 3701 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3702 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3703 "Error while clearing DRV-Presence.\n"); 3704 } 3705 3706 qla2x00_try_to_stop_firmware(base_vha); 3707 } 3708 3709 qla2x00_wait_for_sess_deletion(base_vha); 3710 3711 /* 3712 * if UNLOAD flag is already set, then continue unload, 3713 * where it was set first. 3714 */ 3715 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3716 return; 3717 3718 set_bit(UNLOADING, &base_vha->dpc_flags); 3719 3720 qla_nvme_delete(base_vha); 3721 3722 dma_free_coherent(&ha->pdev->dev, 3723 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3724 3725 base_vha->gnl.l = NULL; 3726 3727 vfree(base_vha->scan.l); 3728 3729 if (IS_QLAFX00(ha)) 3730 qlafx00_driver_shutdown(base_vha, 20); 3731 3732 qla2x00_delete_all_vps(ha, base_vha); 3733 3734 qla2x00_dfs_remove(base_vha); 3735 3736 qla84xx_put_chip(base_vha); 3737 3738 /* Disable timer */ 3739 if (base_vha->timer_active) 3740 qla2x00_stop_timer(base_vha); 3741 3742 base_vha->flags.online = 0; 3743 3744 /* free DMA memory */ 3745 if (ha->exlogin_buf) 3746 qla2x00_free_exlogin_buffer(ha); 3747 3748 /* free DMA memory */ 3749 if (ha->exchoffld_buf) 3750 qla2x00_free_exchoffld_buffer(ha); 3751 3752 qla2x00_destroy_deferred_work(ha); 3753 3754 qlt_remove_target(ha, base_vha); 3755 3756 qla2x00_free_sysfs_attr(base_vha, true); 3757 3758 fc_remove_host(base_vha->host); 3759 qlt_remove_target_resources(ha); 3760 3761 scsi_remove_host(base_vha->host); 3762 3763 qla2x00_free_device(base_vha); 3764 3765 qla2x00_clear_drv_active(ha); 3766 3767 scsi_host_put(base_vha->host); 3768 3769 qla2x00_unmap_iobases(ha); 3770 3771 pci_release_selected_regions(ha->pdev, ha->bars); 3772 kfree(ha); 3773 3774 pci_disable_pcie_error_reporting(pdev); 3775 3776 pci_disable_device(pdev); 3777 } 3778 3779 static void 3780 qla2x00_free_device(scsi_qla_host_t *vha) 3781 { 3782 struct qla_hw_data *ha = vha->hw; 3783 3784 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3785 3786 /* Disable timer */ 3787 if (vha->timer_active) 3788 qla2x00_stop_timer(vha); 3789 3790 qla25xx_delete_queues(vha); 3791 vha->flags.online = 0; 3792 3793 /* turn-off interrupts on the card */ 3794 if (ha->interrupts_on) { 3795 vha->flags.init_done = 0; 3796 ha->isp_ops->disable_intrs(ha); 3797 } 3798 3799 qla2x00_free_fcports(vha); 3800 3801 qla2x00_free_irqs(vha); 3802 3803 /* Flush the work queue and remove it */ 3804 if (ha->wq) { 3805 flush_workqueue(ha->wq); 3806 destroy_workqueue(ha->wq); 3807 ha->wq = NULL; 3808 } 3809 3810 3811 qla2x00_mem_free(ha); 3812 3813 qla82xx_md_free(vha); 3814 3815 qla2x00_free_queues(ha); 3816 } 3817 3818 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3819 { 3820 fc_port_t *fcport, *tfcport; 3821 3822 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3823 qla2x00_free_fcport(fcport); 3824 } 3825 3826 static inline void 3827 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3828 int defer) 3829 { 3830 struct fc_rport *rport; 3831 scsi_qla_host_t *base_vha; 3832 unsigned long flags; 3833 3834 if (!fcport->rport) 3835 return; 3836 3837 rport = fcport->rport; 3838 if (defer) { 3839 base_vha = pci_get_drvdata(vha->hw->pdev); 3840 spin_lock_irqsave(vha->host->host_lock, flags); 3841 fcport->drport = rport; 3842 spin_unlock_irqrestore(vha->host->host_lock, flags); 3843 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3844 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3845 qla2xxx_wake_dpc(base_vha); 3846 } else { 3847 int now; 3848 3849 if (rport) { 3850 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3851 "%s %8phN. rport %p roles %x\n", 3852 __func__, fcport->port_name, rport, 3853 rport->roles); 3854 fc_remote_port_delete(rport); 3855 } 3856 qlt_do_generation_tick(vha, &now); 3857 } 3858 } 3859 3860 /* 3861 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3862 * 3863 * Input: ha = adapter block pointer. fcport = port structure pointer. 3864 * 3865 * Return: None. 3866 * 3867 * Context: 3868 */ 3869 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3870 int do_login, int defer) 3871 { 3872 if (IS_QLAFX00(vha->hw)) { 3873 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3874 qla2x00_schedule_rport_del(vha, fcport, defer); 3875 return; 3876 } 3877 3878 if (atomic_read(&fcport->state) == FCS_ONLINE && 3879 vha->vp_idx == fcport->vha->vp_idx) { 3880 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3881 qla2x00_schedule_rport_del(vha, fcport, defer); 3882 } 3883 /* 3884 * We may need to retry the login, so don't change the state of the 3885 * port but do the retries. 3886 */ 3887 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3888 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3889 3890 if (!do_login) 3891 return; 3892 3893 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3894 } 3895 3896 /* 3897 * qla2x00_mark_all_devices_lost 3898 * Updates fcport state when device goes offline. 3899 * 3900 * Input: 3901 * ha = adapter block pointer. 3902 * fcport = port structure pointer. 3903 * 3904 * Return: 3905 * None. 3906 * 3907 * Context: 3908 */ 3909 void 3910 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3911 { 3912 fc_port_t *fcport; 3913 3914 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3915 "Mark all dev lost\n"); 3916 3917 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3918 fcport->scan_state = 0; 3919 qlt_schedule_sess_for_deletion(fcport); 3920 3921 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3922 continue; 3923 3924 /* 3925 * No point in marking the device as lost, if the device is 3926 * already DEAD. 3927 */ 3928 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3929 continue; 3930 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3931 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3932 if (defer) 3933 qla2x00_schedule_rport_del(vha, fcport, defer); 3934 else if (vha->vp_idx == fcport->vha->vp_idx) 3935 qla2x00_schedule_rport_del(vha, fcport, defer); 3936 } 3937 } 3938 } 3939 3940 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3941 { 3942 int i; 3943 3944 if (IS_FWI2_CAPABLE(ha)) 3945 return; 3946 3947 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3948 set_bit(i, ha->loop_id_map); 3949 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3950 set_bit(BROADCAST, ha->loop_id_map); 3951 } 3952 3953 /* 3954 * qla2x00_mem_alloc 3955 * Allocates adapter memory. 3956 * 3957 * Returns: 3958 * 0 = success. 3959 * !0 = failure. 3960 */ 3961 static int 3962 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3963 struct req_que **req, struct rsp_que **rsp) 3964 { 3965 char name[16]; 3966 3967 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3968 &ha->init_cb_dma, GFP_KERNEL); 3969 if (!ha->init_cb) 3970 goto fail; 3971 3972 if (qlt_mem_alloc(ha) < 0) 3973 goto fail_free_init_cb; 3974 3975 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3976 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3977 if (!ha->gid_list) 3978 goto fail_free_tgt_mem; 3979 3980 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3981 if (!ha->srb_mempool) 3982 goto fail_free_gid_list; 3983 3984 if (IS_P3P_TYPE(ha)) { 3985 /* Allocate cache for CT6 Ctx. */ 3986 if (!ctx_cachep) { 3987 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3988 sizeof(struct ct6_dsd), 0, 3989 SLAB_HWCACHE_ALIGN, NULL); 3990 if (!ctx_cachep) 3991 goto fail_free_srb_mempool; 3992 } 3993 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3994 ctx_cachep); 3995 if (!ha->ctx_mempool) 3996 goto fail_free_srb_mempool; 3997 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3998 "ctx_cachep=%p ctx_mempool=%p.\n", 3999 ctx_cachep, ha->ctx_mempool); 4000 } 4001 4002 /* Get memory for cached NVRAM */ 4003 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4004 if (!ha->nvram) 4005 goto fail_free_ctx_mempool; 4006 4007 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4008 ha->pdev->device); 4009 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4010 DMA_POOL_SIZE, 8, 0); 4011 if (!ha->s_dma_pool) 4012 goto fail_free_nvram; 4013 4014 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4015 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4016 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4017 4018 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4019 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4020 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4021 if (!ha->dl_dma_pool) { 4022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4023 "Failed to allocate memory for dl_dma_pool.\n"); 4024 goto fail_s_dma_pool; 4025 } 4026 4027 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4028 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4029 if (!ha->fcp_cmnd_dma_pool) { 4030 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4031 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4032 goto fail_dl_dma_pool; 4033 } 4034 4035 if (ql2xenabledif) { 4036 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4037 struct dsd_dma *dsd, *nxt; 4038 uint i; 4039 /* Creata a DMA pool of buffers for DIF bundling */ 4040 ha->dif_bundl_pool = dma_pool_create(name, 4041 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4042 if (!ha->dif_bundl_pool) { 4043 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4044 "%s: failed create dif_bundl_pool\n", 4045 __func__); 4046 goto fail_dif_bundl_dma_pool; 4047 } 4048 4049 INIT_LIST_HEAD(&ha->pool.good.head); 4050 INIT_LIST_HEAD(&ha->pool.unusable.head); 4051 ha->pool.good.count = 0; 4052 ha->pool.unusable.count = 0; 4053 for (i = 0; i < 128; i++) { 4054 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4055 if (!dsd) { 4056 ql_dbg_pci(ql_dbg_init, ha->pdev, 4057 0xe0ee, "%s: failed alloc dsd\n", 4058 __func__); 4059 return 1; 4060 } 4061 ha->dif_bundle_kallocs++; 4062 4063 dsd->dsd_addr = dma_pool_alloc( 4064 ha->dif_bundl_pool, GFP_ATOMIC, 4065 &dsd->dsd_list_dma); 4066 if (!dsd->dsd_addr) { 4067 ql_dbg_pci(ql_dbg_init, ha->pdev, 4068 0xe0ee, 4069 "%s: failed alloc ->dsd_addr\n", 4070 __func__); 4071 kfree(dsd); 4072 ha->dif_bundle_kallocs--; 4073 continue; 4074 } 4075 ha->dif_bundle_dma_allocs++; 4076 4077 /* 4078 * if DMA buffer crosses 4G boundary, 4079 * put it on bad list 4080 */ 4081 if (MSD(dsd->dsd_list_dma) ^ 4082 MSD(dsd->dsd_list_dma + bufsize)) { 4083 list_add_tail(&dsd->list, 4084 &ha->pool.unusable.head); 4085 ha->pool.unusable.count++; 4086 } else { 4087 list_add_tail(&dsd->list, 4088 &ha->pool.good.head); 4089 ha->pool.good.count++; 4090 } 4091 } 4092 4093 /* return the good ones back to the pool */ 4094 list_for_each_entry_safe(dsd, nxt, 4095 &ha->pool.good.head, list) { 4096 list_del(&dsd->list); 4097 dma_pool_free(ha->dif_bundl_pool, 4098 dsd->dsd_addr, dsd->dsd_list_dma); 4099 ha->dif_bundle_dma_allocs--; 4100 kfree(dsd); 4101 ha->dif_bundle_kallocs--; 4102 } 4103 4104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4105 "%s: dif dma pool (good=%u unusable=%u)\n", 4106 __func__, ha->pool.good.count, 4107 ha->pool.unusable.count); 4108 } 4109 4110 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4111 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4112 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4113 ha->dif_bundl_pool); 4114 } 4115 4116 /* Allocate memory for SNS commands */ 4117 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4118 /* Get consistent memory allocated for SNS commands */ 4119 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4120 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4121 if (!ha->sns_cmd) 4122 goto fail_dma_pool; 4123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4124 "sns_cmd: %p.\n", ha->sns_cmd); 4125 } else { 4126 /* Get consistent memory allocated for MS IOCB */ 4127 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4128 &ha->ms_iocb_dma); 4129 if (!ha->ms_iocb) 4130 goto fail_dma_pool; 4131 /* Get consistent memory allocated for CT SNS commands */ 4132 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4133 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4134 if (!ha->ct_sns) 4135 goto fail_free_ms_iocb; 4136 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4137 "ms_iocb=%p ct_sns=%p.\n", 4138 ha->ms_iocb, ha->ct_sns); 4139 } 4140 4141 /* Allocate memory for request ring */ 4142 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4143 if (!*req) { 4144 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4145 "Failed to allocate memory for req.\n"); 4146 goto fail_req; 4147 } 4148 (*req)->length = req_len; 4149 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4150 ((*req)->length + 1) * sizeof(request_t), 4151 &(*req)->dma, GFP_KERNEL); 4152 if (!(*req)->ring) { 4153 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4154 "Failed to allocate memory for req_ring.\n"); 4155 goto fail_req_ring; 4156 } 4157 /* Allocate memory for response ring */ 4158 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4159 if (!*rsp) { 4160 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4161 "Failed to allocate memory for rsp.\n"); 4162 goto fail_rsp; 4163 } 4164 (*rsp)->hw = ha; 4165 (*rsp)->length = rsp_len; 4166 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4167 ((*rsp)->length + 1) * sizeof(response_t), 4168 &(*rsp)->dma, GFP_KERNEL); 4169 if (!(*rsp)->ring) { 4170 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4171 "Failed to allocate memory for rsp_ring.\n"); 4172 goto fail_rsp_ring; 4173 } 4174 (*req)->rsp = *rsp; 4175 (*rsp)->req = *req; 4176 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4177 "req=%p req->length=%d req->ring=%p rsp=%p " 4178 "rsp->length=%d rsp->ring=%p.\n", 4179 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4180 (*rsp)->ring); 4181 /* Allocate memory for NVRAM data for vports */ 4182 if (ha->nvram_npiv_size) { 4183 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4184 sizeof(struct qla_npiv_entry), 4185 GFP_KERNEL); 4186 if (!ha->npiv_info) { 4187 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4188 "Failed to allocate memory for npiv_info.\n"); 4189 goto fail_npiv_info; 4190 } 4191 } else 4192 ha->npiv_info = NULL; 4193 4194 /* Get consistent memory allocated for EX-INIT-CB. */ 4195 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4196 IS_QLA28XX(ha)) { 4197 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4198 &ha->ex_init_cb_dma); 4199 if (!ha->ex_init_cb) 4200 goto fail_ex_init_cb; 4201 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4202 "ex_init_cb=%p.\n", ha->ex_init_cb); 4203 } 4204 4205 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4206 4207 /* Get consistent memory allocated for Async Port-Database. */ 4208 if (!IS_FWI2_CAPABLE(ha)) { 4209 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4210 &ha->async_pd_dma); 4211 if (!ha->async_pd) 4212 goto fail_async_pd; 4213 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4214 "async_pd=%p.\n", ha->async_pd); 4215 } 4216 4217 INIT_LIST_HEAD(&ha->vp_list); 4218 4219 /* Allocate memory for our loop_id bitmap */ 4220 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4221 sizeof(long), 4222 GFP_KERNEL); 4223 if (!ha->loop_id_map) 4224 goto fail_loop_id_map; 4225 else { 4226 qla2x00_set_reserved_loop_ids(ha); 4227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4228 "loop_id_map=%p.\n", ha->loop_id_map); 4229 } 4230 4231 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4232 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4233 if (!ha->sfp_data) { 4234 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4235 "Unable to allocate memory for SFP read-data.\n"); 4236 goto fail_sfp_data; 4237 } 4238 4239 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4240 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4241 GFP_KERNEL); 4242 if (!ha->flt) { 4243 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4244 "Unable to allocate memory for FLT.\n"); 4245 goto fail_flt_buffer; 4246 } 4247 4248 return 0; 4249 4250 fail_flt_buffer: 4251 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4252 ha->sfp_data, ha->sfp_data_dma); 4253 fail_sfp_data: 4254 kfree(ha->loop_id_map); 4255 fail_loop_id_map: 4256 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4257 fail_async_pd: 4258 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4259 fail_ex_init_cb: 4260 kfree(ha->npiv_info); 4261 fail_npiv_info: 4262 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4263 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4264 (*rsp)->ring = NULL; 4265 (*rsp)->dma = 0; 4266 fail_rsp_ring: 4267 kfree(*rsp); 4268 *rsp = NULL; 4269 fail_rsp: 4270 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4271 sizeof(request_t), (*req)->ring, (*req)->dma); 4272 (*req)->ring = NULL; 4273 (*req)->dma = 0; 4274 fail_req_ring: 4275 kfree(*req); 4276 *req = NULL; 4277 fail_req: 4278 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4279 ha->ct_sns, ha->ct_sns_dma); 4280 ha->ct_sns = NULL; 4281 ha->ct_sns_dma = 0; 4282 fail_free_ms_iocb: 4283 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4284 ha->ms_iocb = NULL; 4285 ha->ms_iocb_dma = 0; 4286 4287 if (ha->sns_cmd) 4288 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4289 ha->sns_cmd, ha->sns_cmd_dma); 4290 fail_dma_pool: 4291 if (ql2xenabledif) { 4292 struct dsd_dma *dsd, *nxt; 4293 4294 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4295 list) { 4296 list_del(&dsd->list); 4297 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4298 dsd->dsd_list_dma); 4299 ha->dif_bundle_dma_allocs--; 4300 kfree(dsd); 4301 ha->dif_bundle_kallocs--; 4302 ha->pool.unusable.count--; 4303 } 4304 dma_pool_destroy(ha->dif_bundl_pool); 4305 ha->dif_bundl_pool = NULL; 4306 } 4307 4308 fail_dif_bundl_dma_pool: 4309 if (IS_QLA82XX(ha) || ql2xenabledif) { 4310 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4311 ha->fcp_cmnd_dma_pool = NULL; 4312 } 4313 fail_dl_dma_pool: 4314 if (IS_QLA82XX(ha) || ql2xenabledif) { 4315 dma_pool_destroy(ha->dl_dma_pool); 4316 ha->dl_dma_pool = NULL; 4317 } 4318 fail_s_dma_pool: 4319 dma_pool_destroy(ha->s_dma_pool); 4320 ha->s_dma_pool = NULL; 4321 fail_free_nvram: 4322 kfree(ha->nvram); 4323 ha->nvram = NULL; 4324 fail_free_ctx_mempool: 4325 mempool_destroy(ha->ctx_mempool); 4326 ha->ctx_mempool = NULL; 4327 fail_free_srb_mempool: 4328 mempool_destroy(ha->srb_mempool); 4329 ha->srb_mempool = NULL; 4330 fail_free_gid_list: 4331 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4332 ha->gid_list, 4333 ha->gid_list_dma); 4334 ha->gid_list = NULL; 4335 ha->gid_list_dma = 0; 4336 fail_free_tgt_mem: 4337 qlt_mem_free(ha); 4338 fail_free_init_cb: 4339 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4340 ha->init_cb_dma); 4341 ha->init_cb = NULL; 4342 ha->init_cb_dma = 0; 4343 fail: 4344 ql_log(ql_log_fatal, NULL, 0x0030, 4345 "Memory allocation failure.\n"); 4346 return -ENOMEM; 4347 } 4348 4349 int 4350 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4351 { 4352 int rval; 4353 uint16_t size, max_cnt, temp; 4354 struct qla_hw_data *ha = vha->hw; 4355 4356 /* Return if we don't need to alloacate any extended logins */ 4357 if (!ql2xexlogins) 4358 return QLA_SUCCESS; 4359 4360 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4361 return QLA_SUCCESS; 4362 4363 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4364 max_cnt = 0; 4365 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4366 if (rval != QLA_SUCCESS) { 4367 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4368 "Failed to get exlogin status.\n"); 4369 return rval; 4370 } 4371 4372 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4373 temp *= size; 4374 4375 if (temp != ha->exlogin_size) { 4376 qla2x00_free_exlogin_buffer(ha); 4377 ha->exlogin_size = temp; 4378 4379 ql_log(ql_log_info, vha, 0xd024, 4380 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4381 max_cnt, size, temp); 4382 4383 ql_log(ql_log_info, vha, 0xd025, 4384 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4385 4386 /* Get consistent memory for extended logins */ 4387 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4388 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4389 if (!ha->exlogin_buf) { 4390 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4391 "Failed to allocate memory for exlogin_buf_dma.\n"); 4392 return -ENOMEM; 4393 } 4394 } 4395 4396 /* Now configure the dma buffer */ 4397 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4398 if (rval) { 4399 ql_log(ql_log_fatal, vha, 0xd033, 4400 "Setup extended login buffer ****FAILED****.\n"); 4401 qla2x00_free_exlogin_buffer(ha); 4402 } 4403 4404 return rval; 4405 } 4406 4407 /* 4408 * qla2x00_free_exlogin_buffer 4409 * 4410 * Input: 4411 * ha = adapter block pointer 4412 */ 4413 void 4414 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4415 { 4416 if (ha->exlogin_buf) { 4417 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4418 ha->exlogin_buf, ha->exlogin_buf_dma); 4419 ha->exlogin_buf = NULL; 4420 ha->exlogin_size = 0; 4421 } 4422 } 4423 4424 static void 4425 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4426 { 4427 u32 temp; 4428 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4429 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4430 4431 if (max_cnt > vha->hw->max_exchg) 4432 max_cnt = vha->hw->max_exchg; 4433 4434 if (qla_ini_mode_enabled(vha)) { 4435 if (vha->ql2xiniexchg > max_cnt) 4436 vha->ql2xiniexchg = max_cnt; 4437 4438 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4439 *ret_cnt = vha->ql2xiniexchg; 4440 4441 } else if (qla_tgt_mode_enabled(vha)) { 4442 if (vha->ql2xexchoffld > max_cnt) { 4443 vha->ql2xexchoffld = max_cnt; 4444 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4445 } 4446 4447 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4448 *ret_cnt = vha->ql2xexchoffld; 4449 } else if (qla_dual_mode_enabled(vha)) { 4450 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4451 if (temp > max_cnt) { 4452 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4453 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4454 temp = max_cnt; 4455 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4456 } 4457 4458 if (temp > FW_DEF_EXCHANGES_CNT) 4459 *ret_cnt = temp; 4460 } 4461 } 4462 4463 int 4464 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4465 { 4466 int rval; 4467 u16 size, max_cnt; 4468 u32 actual_cnt, totsz; 4469 struct qla_hw_data *ha = vha->hw; 4470 4471 if (!ha->flags.exchoffld_enabled) 4472 return QLA_SUCCESS; 4473 4474 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4475 return QLA_SUCCESS; 4476 4477 max_cnt = 0; 4478 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4479 if (rval != QLA_SUCCESS) { 4480 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4481 "Failed to get exlogin status.\n"); 4482 return rval; 4483 } 4484 4485 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4486 ql_log(ql_log_info, vha, 0xd014, 4487 "Actual exchange offload count: %d.\n", actual_cnt); 4488 4489 totsz = actual_cnt * size; 4490 4491 if (totsz != ha->exchoffld_size) { 4492 qla2x00_free_exchoffld_buffer(ha); 4493 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4494 ha->exchoffld_size = 0; 4495 ha->flags.exchoffld_enabled = 0; 4496 return QLA_SUCCESS; 4497 } 4498 4499 ha->exchoffld_size = totsz; 4500 4501 ql_log(ql_log_info, vha, 0xd016, 4502 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4503 max_cnt, actual_cnt, size, totsz); 4504 4505 ql_log(ql_log_info, vha, 0xd017, 4506 "Exchange Buffers requested size = 0x%x\n", 4507 ha->exchoffld_size); 4508 4509 /* Get consistent memory for extended logins */ 4510 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4511 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4512 if (!ha->exchoffld_buf) { 4513 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4514 "Failed to allocate memory for Exchange Offload.\n"); 4515 4516 if (ha->max_exchg > 4517 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4518 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4519 } else if (ha->max_exchg > 4520 (FW_DEF_EXCHANGES_CNT + 512)) { 4521 ha->max_exchg -= 512; 4522 } else { 4523 ha->flags.exchoffld_enabled = 0; 4524 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4525 "Disabling Exchange offload due to lack of memory\n"); 4526 } 4527 ha->exchoffld_size = 0; 4528 4529 return -ENOMEM; 4530 } 4531 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4532 /* pathological case */ 4533 qla2x00_free_exchoffld_buffer(ha); 4534 ha->exchoffld_size = 0; 4535 ha->flags.exchoffld_enabled = 0; 4536 ql_log(ql_log_info, vha, 0xd016, 4537 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4538 ha->exchoffld_size, actual_cnt, size, totsz); 4539 return 0; 4540 } 4541 4542 /* Now configure the dma buffer */ 4543 rval = qla_set_exchoffld_mem_cfg(vha); 4544 if (rval) { 4545 ql_log(ql_log_fatal, vha, 0xd02e, 4546 "Setup exchange offload buffer ****FAILED****.\n"); 4547 qla2x00_free_exchoffld_buffer(ha); 4548 } else { 4549 /* re-adjust number of target exchange */ 4550 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4551 4552 if (qla_ini_mode_enabled(vha)) 4553 icb->exchange_count = 0; 4554 else 4555 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4556 } 4557 4558 return rval; 4559 } 4560 4561 /* 4562 * qla2x00_free_exchoffld_buffer 4563 * 4564 * Input: 4565 * ha = adapter block pointer 4566 */ 4567 void 4568 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4569 { 4570 if (ha->exchoffld_buf) { 4571 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4572 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4573 ha->exchoffld_buf = NULL; 4574 ha->exchoffld_size = 0; 4575 } 4576 } 4577 4578 /* 4579 * qla2x00_free_fw_dump 4580 * Frees fw dump stuff. 4581 * 4582 * Input: 4583 * ha = adapter block pointer 4584 */ 4585 static void 4586 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4587 { 4588 struct fwdt *fwdt = ha->fwdt; 4589 uint j; 4590 4591 if (ha->fce) 4592 dma_free_coherent(&ha->pdev->dev, 4593 FCE_SIZE, ha->fce, ha->fce_dma); 4594 4595 if (ha->eft) 4596 dma_free_coherent(&ha->pdev->dev, 4597 EFT_SIZE, ha->eft, ha->eft_dma); 4598 4599 if (ha->fw_dump) 4600 vfree(ha->fw_dump); 4601 4602 ha->fce = NULL; 4603 ha->fce_dma = 0; 4604 ha->flags.fce_enabled = 0; 4605 ha->eft = NULL; 4606 ha->eft_dma = 0; 4607 ha->fw_dumped = 0; 4608 ha->fw_dump_cap_flags = 0; 4609 ha->fw_dump_reading = 0; 4610 ha->fw_dump = NULL; 4611 ha->fw_dump_len = 0; 4612 4613 for (j = 0; j < 2; j++, fwdt++) { 4614 if (fwdt->template) 4615 vfree(fwdt->template); 4616 fwdt->template = NULL; 4617 fwdt->length = 0; 4618 } 4619 } 4620 4621 /* 4622 * qla2x00_mem_free 4623 * Frees all adapter allocated memory. 4624 * 4625 * Input: 4626 * ha = adapter block pointer. 4627 */ 4628 static void 4629 qla2x00_mem_free(struct qla_hw_data *ha) 4630 { 4631 qla2x00_free_fw_dump(ha); 4632 4633 if (ha->mctp_dump) 4634 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4635 ha->mctp_dump_dma); 4636 ha->mctp_dump = NULL; 4637 4638 mempool_destroy(ha->srb_mempool); 4639 ha->srb_mempool = NULL; 4640 4641 if (ha->dcbx_tlv) 4642 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4643 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4644 ha->dcbx_tlv = NULL; 4645 4646 if (ha->xgmac_data) 4647 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4648 ha->xgmac_data, ha->xgmac_data_dma); 4649 ha->xgmac_data = NULL; 4650 4651 if (ha->sns_cmd) 4652 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4653 ha->sns_cmd, ha->sns_cmd_dma); 4654 ha->sns_cmd = NULL; 4655 ha->sns_cmd_dma = 0; 4656 4657 if (ha->ct_sns) 4658 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4659 ha->ct_sns, ha->ct_sns_dma); 4660 ha->ct_sns = NULL; 4661 ha->ct_sns_dma = 0; 4662 4663 if (ha->sfp_data) 4664 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4665 ha->sfp_data_dma); 4666 ha->sfp_data = NULL; 4667 4668 if (ha->flt) 4669 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4670 ha->flt, ha->flt_dma); 4671 ha->flt = NULL; 4672 ha->flt_dma = 0; 4673 4674 if (ha->ms_iocb) 4675 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4676 ha->ms_iocb = NULL; 4677 ha->ms_iocb_dma = 0; 4678 4679 if (ha->ex_init_cb) 4680 dma_pool_free(ha->s_dma_pool, 4681 ha->ex_init_cb, ha->ex_init_cb_dma); 4682 ha->ex_init_cb = NULL; 4683 ha->ex_init_cb_dma = 0; 4684 4685 if (ha->async_pd) 4686 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4687 ha->async_pd = NULL; 4688 ha->async_pd_dma = 0; 4689 4690 dma_pool_destroy(ha->s_dma_pool); 4691 ha->s_dma_pool = NULL; 4692 4693 if (ha->gid_list) 4694 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4695 ha->gid_list, ha->gid_list_dma); 4696 ha->gid_list = NULL; 4697 ha->gid_list_dma = 0; 4698 4699 if (IS_QLA82XX(ha)) { 4700 if (!list_empty(&ha->gbl_dsd_list)) { 4701 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4702 4703 /* clean up allocated prev pool */ 4704 list_for_each_entry_safe(dsd_ptr, 4705 tdsd_ptr, &ha->gbl_dsd_list, list) { 4706 dma_pool_free(ha->dl_dma_pool, 4707 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4708 list_del(&dsd_ptr->list); 4709 kfree(dsd_ptr); 4710 } 4711 } 4712 } 4713 4714 dma_pool_destroy(ha->dl_dma_pool); 4715 ha->dl_dma_pool = NULL; 4716 4717 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4718 ha->fcp_cmnd_dma_pool = NULL; 4719 4720 mempool_destroy(ha->ctx_mempool); 4721 ha->ctx_mempool = NULL; 4722 4723 if (ql2xenabledif && ha->dif_bundl_pool) { 4724 struct dsd_dma *dsd, *nxt; 4725 4726 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4727 list) { 4728 list_del(&dsd->list); 4729 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4730 dsd->dsd_list_dma); 4731 ha->dif_bundle_dma_allocs--; 4732 kfree(dsd); 4733 ha->dif_bundle_kallocs--; 4734 ha->pool.unusable.count--; 4735 } 4736 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4737 list_del(&dsd->list); 4738 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4739 dsd->dsd_list_dma); 4740 ha->dif_bundle_dma_allocs--; 4741 kfree(dsd); 4742 ha->dif_bundle_kallocs--; 4743 } 4744 } 4745 4746 dma_pool_destroy(ha->dif_bundl_pool); 4747 ha->dif_bundl_pool = NULL; 4748 4749 qlt_mem_free(ha); 4750 4751 if (ha->init_cb) 4752 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4753 ha->init_cb, ha->init_cb_dma); 4754 ha->init_cb = NULL; 4755 ha->init_cb_dma = 0; 4756 4757 vfree(ha->optrom_buffer); 4758 ha->optrom_buffer = NULL; 4759 kfree(ha->nvram); 4760 ha->nvram = NULL; 4761 kfree(ha->npiv_info); 4762 ha->npiv_info = NULL; 4763 kfree(ha->swl); 4764 ha->swl = NULL; 4765 kfree(ha->loop_id_map); 4766 ha->loop_id_map = NULL; 4767 } 4768 4769 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4770 struct qla_hw_data *ha) 4771 { 4772 struct Scsi_Host *host; 4773 struct scsi_qla_host *vha = NULL; 4774 4775 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4776 if (!host) { 4777 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4778 "Failed to allocate host from the scsi layer, aborting.\n"); 4779 return NULL; 4780 } 4781 4782 /* Clear our data area */ 4783 vha = shost_priv(host); 4784 memset(vha, 0, sizeof(scsi_qla_host_t)); 4785 4786 vha->host = host; 4787 vha->host_no = host->host_no; 4788 vha->hw = ha; 4789 4790 vha->qlini_mode = ql2x_ini_mode; 4791 vha->ql2xexchoffld = ql2xexchoffld; 4792 vha->ql2xiniexchg = ql2xiniexchg; 4793 4794 INIT_LIST_HEAD(&vha->vp_fcports); 4795 INIT_LIST_HEAD(&vha->work_list); 4796 INIT_LIST_HEAD(&vha->list); 4797 INIT_LIST_HEAD(&vha->qla_cmd_list); 4798 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4799 INIT_LIST_HEAD(&vha->logo_list); 4800 INIT_LIST_HEAD(&vha->plogi_ack_list); 4801 INIT_LIST_HEAD(&vha->qp_list); 4802 INIT_LIST_HEAD(&vha->gnl.fcports); 4803 INIT_LIST_HEAD(&vha->gpnid_list); 4804 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4805 4806 spin_lock_init(&vha->work_lock); 4807 spin_lock_init(&vha->cmd_list_lock); 4808 init_waitqueue_head(&vha->fcport_waitQ); 4809 init_waitqueue_head(&vha->vref_waitq); 4810 4811 vha->gnl.size = sizeof(struct get_name_list_extended) * 4812 (ha->max_loop_id + 1); 4813 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4814 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4815 if (!vha->gnl.l) { 4816 ql_log(ql_log_fatal, vha, 0xd04a, 4817 "Alloc failed for name list.\n"); 4818 scsi_host_put(vha->host); 4819 return NULL; 4820 } 4821 4822 /* todo: what about ext login? */ 4823 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4824 vha->scan.l = vmalloc(vha->scan.size); 4825 if (!vha->scan.l) { 4826 ql_log(ql_log_fatal, vha, 0xd04a, 4827 "Alloc failed for scan database.\n"); 4828 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4829 vha->gnl.l, vha->gnl.ldma); 4830 vha->gnl.l = NULL; 4831 scsi_host_put(vha->host); 4832 return NULL; 4833 } 4834 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4835 4836 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4837 ql_dbg(ql_dbg_init, vha, 0x0041, 4838 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4839 vha->host, vha->hw, vha, 4840 dev_name(&(ha->pdev->dev))); 4841 4842 return vha; 4843 } 4844 4845 struct qla_work_evt * 4846 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4847 { 4848 struct qla_work_evt *e; 4849 uint8_t bail; 4850 4851 QLA_VHA_MARK_BUSY(vha, bail); 4852 if (bail) 4853 return NULL; 4854 4855 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4856 if (!e) { 4857 QLA_VHA_MARK_NOT_BUSY(vha); 4858 return NULL; 4859 } 4860 4861 INIT_LIST_HEAD(&e->list); 4862 e->type = type; 4863 e->flags = QLA_EVT_FLAG_FREE; 4864 return e; 4865 } 4866 4867 int 4868 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4869 { 4870 unsigned long flags; 4871 bool q = false; 4872 4873 spin_lock_irqsave(&vha->work_lock, flags); 4874 list_add_tail(&e->list, &vha->work_list); 4875 4876 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4877 q = true; 4878 4879 spin_unlock_irqrestore(&vha->work_lock, flags); 4880 4881 if (q) 4882 queue_work(vha->hw->wq, &vha->iocb_work); 4883 4884 return QLA_SUCCESS; 4885 } 4886 4887 int 4888 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4889 u32 data) 4890 { 4891 struct qla_work_evt *e; 4892 4893 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4894 if (!e) 4895 return QLA_FUNCTION_FAILED; 4896 4897 e->u.aen.code = code; 4898 e->u.aen.data = data; 4899 return qla2x00_post_work(vha, e); 4900 } 4901 4902 int 4903 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4904 { 4905 struct qla_work_evt *e; 4906 4907 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4908 if (!e) 4909 return QLA_FUNCTION_FAILED; 4910 4911 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4912 return qla2x00_post_work(vha, e); 4913 } 4914 4915 #define qla2x00_post_async_work(name, type) \ 4916 int qla2x00_post_async_##name##_work( \ 4917 struct scsi_qla_host *vha, \ 4918 fc_port_t *fcport, uint16_t *data) \ 4919 { \ 4920 struct qla_work_evt *e; \ 4921 \ 4922 e = qla2x00_alloc_work(vha, type); \ 4923 if (!e) \ 4924 return QLA_FUNCTION_FAILED; \ 4925 \ 4926 e->u.logio.fcport = fcport; \ 4927 if (data) { \ 4928 e->u.logio.data[0] = data[0]; \ 4929 e->u.logio.data[1] = data[1]; \ 4930 } \ 4931 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4932 return qla2x00_post_work(vha, e); \ 4933 } 4934 4935 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4936 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4937 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4938 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4939 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4940 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4941 4942 int 4943 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4944 { 4945 struct qla_work_evt *e; 4946 4947 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4948 if (!e) 4949 return QLA_FUNCTION_FAILED; 4950 4951 e->u.uevent.code = code; 4952 return qla2x00_post_work(vha, e); 4953 } 4954 4955 static void 4956 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4957 { 4958 char event_string[40]; 4959 char *envp[] = { event_string, NULL }; 4960 4961 switch (code) { 4962 case QLA_UEVENT_CODE_FW_DUMP: 4963 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4964 vha->host_no); 4965 break; 4966 default: 4967 /* do nothing */ 4968 break; 4969 } 4970 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4971 } 4972 4973 int 4974 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4975 uint32_t *data, int cnt) 4976 { 4977 struct qla_work_evt *e; 4978 4979 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4980 if (!e) 4981 return QLA_FUNCTION_FAILED; 4982 4983 e->u.aenfx.evtcode = evtcode; 4984 e->u.aenfx.count = cnt; 4985 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4986 return qla2x00_post_work(vha, e); 4987 } 4988 4989 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 4990 { 4991 unsigned long flags; 4992 4993 if (IS_SW_RESV_ADDR(fcport->d_id)) 4994 return; 4995 4996 spin_lock_irqsave(&fcport->vha->work_lock, flags); 4997 if (fcport->disc_state == DSC_UPD_FCPORT) { 4998 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4999 return; 5000 } 5001 fcport->jiffies_at_registration = jiffies; 5002 fcport->sec_since_registration = 0; 5003 fcport->next_disc_state = DSC_DELETED; 5004 fcport->disc_state = DSC_UPD_FCPORT; 5005 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5006 5007 queue_work(system_unbound_wq, &fcport->reg_work); 5008 } 5009 5010 static 5011 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5012 { 5013 unsigned long flags; 5014 fc_port_t *fcport = NULL, *tfcp; 5015 struct qlt_plogi_ack_t *pla = 5016 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5017 uint8_t free_fcport = 0; 5018 5019 ql_dbg(ql_dbg_disc, vha, 0xffff, 5020 "%s %d %8phC enter\n", 5021 __func__, __LINE__, e->u.new_sess.port_name); 5022 5023 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5024 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5025 if (fcport) { 5026 fcport->d_id = e->u.new_sess.id; 5027 if (pla) { 5028 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5029 memcpy(fcport->node_name, 5030 pla->iocb.u.isp24.u.plogi.node_name, 5031 WWN_SIZE); 5032 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5033 /* we took an extra ref_count to prevent PLOGI ACK when 5034 * fcport/sess has not been created. 5035 */ 5036 pla->ref_count--; 5037 } 5038 } else { 5039 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5040 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5041 if (fcport) { 5042 fcport->d_id = e->u.new_sess.id; 5043 fcport->flags |= FCF_FABRIC_DEVICE; 5044 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5045 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP) 5046 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 5047 5048 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) { 5049 fcport->fc4_type = FC4_TYPE_OTHER; 5050 fcport->fc4f_nvme = FC4_TYPE_NVME; 5051 } 5052 5053 memcpy(fcport->port_name, e->u.new_sess.port_name, 5054 WWN_SIZE); 5055 5056 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) 5057 fcport->n2n_flag = 1; 5058 5059 } else { 5060 ql_dbg(ql_dbg_disc, vha, 0xffff, 5061 "%s %8phC mem alloc fail.\n", 5062 __func__, e->u.new_sess.port_name); 5063 5064 if (pla) { 5065 list_del(&pla->list); 5066 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5067 } 5068 return; 5069 } 5070 5071 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5072 /* search again to make sure no one else got ahead */ 5073 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5074 e->u.new_sess.port_name, 1); 5075 if (tfcp) { 5076 /* should rarily happen */ 5077 ql_dbg(ql_dbg_disc, vha, 0xffff, 5078 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5079 __func__, tfcp->port_name, tfcp->disc_state, 5080 tfcp->fw_login_state); 5081 5082 free_fcport = 1; 5083 } else { 5084 list_add_tail(&fcport->list, &vha->vp_fcports); 5085 5086 } 5087 if (pla) { 5088 qlt_plogi_ack_link(vha, pla, fcport, 5089 QLT_PLOGI_LINK_SAME_WWN); 5090 pla->ref_count--; 5091 } 5092 } 5093 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5094 5095 if (fcport) { 5096 fcport->id_changed = 1; 5097 fcport->scan_state = QLA_FCPORT_FOUND; 5098 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5099 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5100 5101 if (pla) { 5102 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5103 u16 wd3_lo; 5104 5105 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5106 fcport->local = 0; 5107 fcport->loop_id = 5108 le16_to_cpu( 5109 pla->iocb.u.isp24.nport_handle); 5110 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5111 wd3_lo = 5112 le16_to_cpu( 5113 pla->iocb.u.isp24.u.prli.wd3_lo); 5114 5115 if (wd3_lo & BIT_7) 5116 fcport->conf_compl_supported = 1; 5117 5118 if ((wd3_lo & BIT_4) == 0) 5119 fcport->port_type = FCT_INITIATOR; 5120 else 5121 fcport->port_type = FCT_TARGET; 5122 } 5123 qlt_plogi_ack_unref(vha, pla); 5124 } else { 5125 fc_port_t *dfcp = NULL; 5126 5127 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5128 tfcp = qla2x00_find_fcport_by_nportid(vha, 5129 &e->u.new_sess.id, 1); 5130 if (tfcp && (tfcp != fcport)) { 5131 /* 5132 * We have a conflict fcport with same NportID. 5133 */ 5134 ql_dbg(ql_dbg_disc, vha, 0xffff, 5135 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5136 __func__, tfcp->port_name, tfcp->disc_state, 5137 tfcp->fw_login_state); 5138 5139 switch (tfcp->disc_state) { 5140 case DSC_DELETED: 5141 break; 5142 case DSC_DELETE_PEND: 5143 fcport->login_pause = 1; 5144 tfcp->conflict = fcport; 5145 break; 5146 default: 5147 fcport->login_pause = 1; 5148 tfcp->conflict = fcport; 5149 dfcp = tfcp; 5150 break; 5151 } 5152 } 5153 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5154 if (dfcp) 5155 qlt_schedule_sess_for_deletion(tfcp); 5156 5157 if (N2N_TOPO(vha->hw)) { 5158 fcport->flags &= ~FCF_FABRIC_DEVICE; 5159 fcport->keep_nport_handle = 1; 5160 if (vha->flags.nvme_enabled) { 5161 fcport->fc4f_nvme = 1; 5162 fcport->n2n_flag = 1; 5163 } 5164 fcport->fw_login_state = 0; 5165 /* 5166 * wait link init done before sending login 5167 */ 5168 } else { 5169 qla24xx_fcport_handle_login(vha, fcport); 5170 } 5171 } 5172 } 5173 5174 if (free_fcport) { 5175 qla2x00_free_fcport(fcport); 5176 if (pla) { 5177 list_del(&pla->list); 5178 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5179 } 5180 } 5181 } 5182 5183 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5184 { 5185 struct srb *sp = e->u.iosb.sp; 5186 int rval; 5187 5188 rval = qla2x00_start_sp(sp); 5189 if (rval != QLA_SUCCESS) { 5190 ql_dbg(ql_dbg_disc, vha, 0x2043, 5191 "%s: %s: Re-issue IOCB failed (%d).\n", 5192 __func__, sp->name, rval); 5193 qla24xx_sp_unmap(vha, sp); 5194 } 5195 } 5196 5197 void 5198 qla2x00_do_work(struct scsi_qla_host *vha) 5199 { 5200 struct qla_work_evt *e, *tmp; 5201 unsigned long flags; 5202 LIST_HEAD(work); 5203 int rc; 5204 5205 spin_lock_irqsave(&vha->work_lock, flags); 5206 list_splice_init(&vha->work_list, &work); 5207 spin_unlock_irqrestore(&vha->work_lock, flags); 5208 5209 list_for_each_entry_safe(e, tmp, &work, list) { 5210 rc = QLA_SUCCESS; 5211 switch (e->type) { 5212 case QLA_EVT_AEN: 5213 fc_host_post_event(vha->host, fc_get_event_number(), 5214 e->u.aen.code, e->u.aen.data); 5215 break; 5216 case QLA_EVT_IDC_ACK: 5217 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5218 break; 5219 case QLA_EVT_ASYNC_LOGIN: 5220 qla2x00_async_login(vha, e->u.logio.fcport, 5221 e->u.logio.data); 5222 break; 5223 case QLA_EVT_ASYNC_LOGOUT: 5224 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5225 break; 5226 case QLA_EVT_ASYNC_LOGOUT_DONE: 5227 qla2x00_async_logout_done(vha, e->u.logio.fcport, 5228 e->u.logio.data); 5229 break; 5230 case QLA_EVT_ASYNC_ADISC: 5231 qla2x00_async_adisc(vha, e->u.logio.fcport, 5232 e->u.logio.data); 5233 break; 5234 case QLA_EVT_UEVENT: 5235 qla2x00_uevent_emit(vha, e->u.uevent.code); 5236 break; 5237 case QLA_EVT_AENFX: 5238 qlafx00_process_aen(vha, e); 5239 break; 5240 case QLA_EVT_GPNID: 5241 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5242 break; 5243 case QLA_EVT_UNMAP: 5244 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5245 break; 5246 case QLA_EVT_RELOGIN: 5247 qla2x00_relogin(vha); 5248 break; 5249 case QLA_EVT_NEW_SESS: 5250 qla24xx_create_new_sess(vha, e); 5251 break; 5252 case QLA_EVT_GPDB: 5253 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5254 e->u.fcport.opt); 5255 break; 5256 case QLA_EVT_PRLI: 5257 qla24xx_async_prli(vha, e->u.fcport.fcport); 5258 break; 5259 case QLA_EVT_GPSC: 5260 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5261 break; 5262 case QLA_EVT_GNL: 5263 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5264 break; 5265 case QLA_EVT_NACK: 5266 qla24xx_do_nack_work(vha, e); 5267 break; 5268 case QLA_EVT_ASYNC_PRLO: 5269 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5270 break; 5271 case QLA_EVT_ASYNC_PRLO_DONE: 5272 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5273 e->u.logio.data); 5274 break; 5275 case QLA_EVT_GPNFT: 5276 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5277 e->u.gpnft.sp); 5278 break; 5279 case QLA_EVT_GPNFT_DONE: 5280 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5281 break; 5282 case QLA_EVT_GNNFT_DONE: 5283 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5284 break; 5285 case QLA_EVT_GNNID: 5286 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5287 break; 5288 case QLA_EVT_GFPNID: 5289 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5290 break; 5291 case QLA_EVT_SP_RETRY: 5292 qla_sp_retry(vha, e); 5293 break; 5294 case QLA_EVT_IIDMA: 5295 qla_do_iidma_work(vha, e->u.fcport.fcport); 5296 break; 5297 case QLA_EVT_ELS_PLOGI: 5298 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5299 e->u.fcport.fcport, false); 5300 break; 5301 } 5302 5303 if (rc == EAGAIN) { 5304 /* put 'work' at head of 'vha->work_list' */ 5305 spin_lock_irqsave(&vha->work_lock, flags); 5306 list_splice(&work, &vha->work_list); 5307 spin_unlock_irqrestore(&vha->work_lock, flags); 5308 break; 5309 } 5310 list_del_init(&e->list); 5311 if (e->flags & QLA_EVT_FLAG_FREE) 5312 kfree(e); 5313 5314 /* For each work completed decrement vha ref count */ 5315 QLA_VHA_MARK_NOT_BUSY(vha); 5316 } 5317 } 5318 5319 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5320 { 5321 struct qla_work_evt *e; 5322 5323 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5324 5325 if (!e) { 5326 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5327 return QLA_FUNCTION_FAILED; 5328 } 5329 5330 return qla2x00_post_work(vha, e); 5331 } 5332 5333 /* Relogins all the fcports of a vport 5334 * Context: dpc thread 5335 */ 5336 void qla2x00_relogin(struct scsi_qla_host *vha) 5337 { 5338 fc_port_t *fcport; 5339 int status, relogin_needed = 0; 5340 struct event_arg ea; 5341 5342 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5343 /* 5344 * If the port is not ONLINE then try to login 5345 * to it if we haven't run out of retries. 5346 */ 5347 if (atomic_read(&fcport->state) != FCS_ONLINE && 5348 fcport->login_retry) { 5349 if (fcport->scan_state != QLA_FCPORT_FOUND || 5350 fcport->disc_state == DSC_LOGIN_COMPLETE) 5351 continue; 5352 5353 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5354 fcport->disc_state == DSC_DELETE_PEND) { 5355 relogin_needed = 1; 5356 } else { 5357 if (vha->hw->current_topology != ISP_CFG_NL) { 5358 memset(&ea, 0, sizeof(ea)); 5359 ea.fcport = fcport; 5360 qla24xx_handle_relogin_event(vha, &ea); 5361 } else if (vha->hw->current_topology == 5362 ISP_CFG_NL) { 5363 fcport->login_retry--; 5364 status = 5365 qla2x00_local_device_login(vha, 5366 fcport); 5367 if (status == QLA_SUCCESS) { 5368 fcport->old_loop_id = 5369 fcport->loop_id; 5370 ql_dbg(ql_dbg_disc, vha, 0x2003, 5371 "Port login OK: logged in ID 0x%x.\n", 5372 fcport->loop_id); 5373 qla2x00_update_fcport 5374 (vha, fcport); 5375 } else if (status == 1) { 5376 set_bit(RELOGIN_NEEDED, 5377 &vha->dpc_flags); 5378 /* retry the login again */ 5379 ql_dbg(ql_dbg_disc, vha, 0x2007, 5380 "Retrying %d login again loop_id 0x%x.\n", 5381 fcport->login_retry, 5382 fcport->loop_id); 5383 } else { 5384 fcport->login_retry = 0; 5385 } 5386 5387 if (fcport->login_retry == 0 && 5388 status != QLA_SUCCESS) 5389 qla2x00_clear_loop_id(fcport); 5390 } 5391 } 5392 } 5393 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5394 break; 5395 } 5396 5397 if (relogin_needed) 5398 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5399 5400 ql_dbg(ql_dbg_disc, vha, 0x400e, 5401 "Relogin end.\n"); 5402 } 5403 5404 /* Schedule work on any of the dpc-workqueues */ 5405 void 5406 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5407 { 5408 struct qla_hw_data *ha = base_vha->hw; 5409 5410 switch (work_code) { 5411 case MBA_IDC_AEN: /* 0x8200 */ 5412 if (ha->dpc_lp_wq) 5413 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5414 break; 5415 5416 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5417 if (!ha->flags.nic_core_reset_hdlr_active) { 5418 if (ha->dpc_hp_wq) 5419 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5420 } else 5421 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5422 "NIC Core reset is already active. Skip " 5423 "scheduling it again.\n"); 5424 break; 5425 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5426 if (ha->dpc_hp_wq) 5427 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5428 break; 5429 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5430 if (ha->dpc_hp_wq) 5431 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5432 break; 5433 default: 5434 ql_log(ql_log_warn, base_vha, 0xb05f, 5435 "Unknown work-code=0x%x.\n", work_code); 5436 } 5437 5438 return; 5439 } 5440 5441 /* Work: Perform NIC Core Unrecoverable state handling */ 5442 void 5443 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5444 { 5445 struct qla_hw_data *ha = 5446 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5447 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5448 uint32_t dev_state = 0; 5449 5450 qla83xx_idc_lock(base_vha, 0); 5451 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5452 qla83xx_reset_ownership(base_vha); 5453 if (ha->flags.nic_core_reset_owner) { 5454 ha->flags.nic_core_reset_owner = 0; 5455 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5456 QLA8XXX_DEV_FAILED); 5457 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5458 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5459 } 5460 qla83xx_idc_unlock(base_vha, 0); 5461 } 5462 5463 /* Work: Execute IDC state handler */ 5464 void 5465 qla83xx_idc_state_handler_work(struct work_struct *work) 5466 { 5467 struct qla_hw_data *ha = 5468 container_of(work, struct qla_hw_data, idc_state_handler); 5469 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5470 uint32_t dev_state = 0; 5471 5472 qla83xx_idc_lock(base_vha, 0); 5473 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5474 if (dev_state == QLA8XXX_DEV_FAILED || 5475 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5476 qla83xx_idc_state_handler(base_vha); 5477 qla83xx_idc_unlock(base_vha, 0); 5478 } 5479 5480 static int 5481 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5482 { 5483 int rval = QLA_SUCCESS; 5484 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5485 uint32_t heart_beat_counter1, heart_beat_counter2; 5486 5487 do { 5488 if (time_after(jiffies, heart_beat_wait)) { 5489 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5490 "Nic Core f/w is not alive.\n"); 5491 rval = QLA_FUNCTION_FAILED; 5492 break; 5493 } 5494 5495 qla83xx_idc_lock(base_vha, 0); 5496 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5497 &heart_beat_counter1); 5498 qla83xx_idc_unlock(base_vha, 0); 5499 msleep(100); 5500 qla83xx_idc_lock(base_vha, 0); 5501 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5502 &heart_beat_counter2); 5503 qla83xx_idc_unlock(base_vha, 0); 5504 } while (heart_beat_counter1 == heart_beat_counter2); 5505 5506 return rval; 5507 } 5508 5509 /* Work: Perform NIC Core Reset handling */ 5510 void 5511 qla83xx_nic_core_reset_work(struct work_struct *work) 5512 { 5513 struct qla_hw_data *ha = 5514 container_of(work, struct qla_hw_data, nic_core_reset); 5515 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5516 uint32_t dev_state = 0; 5517 5518 if (IS_QLA2031(ha)) { 5519 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5520 ql_log(ql_log_warn, base_vha, 0xb081, 5521 "Failed to dump mctp\n"); 5522 return; 5523 } 5524 5525 if (!ha->flags.nic_core_reset_hdlr_active) { 5526 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5527 qla83xx_idc_lock(base_vha, 0); 5528 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5529 &dev_state); 5530 qla83xx_idc_unlock(base_vha, 0); 5531 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5532 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5533 "Nic Core f/w is alive.\n"); 5534 return; 5535 } 5536 } 5537 5538 ha->flags.nic_core_reset_hdlr_active = 1; 5539 if (qla83xx_nic_core_reset(base_vha)) { 5540 /* NIC Core reset failed. */ 5541 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5542 "NIC Core reset failed.\n"); 5543 } 5544 ha->flags.nic_core_reset_hdlr_active = 0; 5545 } 5546 } 5547 5548 /* Work: Handle 8200 IDC aens */ 5549 void 5550 qla83xx_service_idc_aen(struct work_struct *work) 5551 { 5552 struct qla_hw_data *ha = 5553 container_of(work, struct qla_hw_data, idc_aen); 5554 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5555 uint32_t dev_state, idc_control; 5556 5557 qla83xx_idc_lock(base_vha, 0); 5558 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5559 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5560 qla83xx_idc_unlock(base_vha, 0); 5561 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5562 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5563 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5564 "Application requested NIC Core Reset.\n"); 5565 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5566 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5567 QLA_SUCCESS) { 5568 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5569 "Other protocol driver requested NIC Core Reset.\n"); 5570 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5571 } 5572 } else if (dev_state == QLA8XXX_DEV_FAILED || 5573 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5574 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5575 } 5576 } 5577 5578 static void 5579 qla83xx_wait_logic(void) 5580 { 5581 int i; 5582 5583 /* Yield CPU */ 5584 if (!in_interrupt()) { 5585 /* 5586 * Wait about 200ms before retrying again. 5587 * This controls the number of retries for single 5588 * lock operation. 5589 */ 5590 msleep(100); 5591 schedule(); 5592 } else { 5593 for (i = 0; i < 20; i++) 5594 cpu_relax(); /* This a nop instr on i386 */ 5595 } 5596 } 5597 5598 static int 5599 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5600 { 5601 int rval; 5602 uint32_t data; 5603 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5604 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5605 struct qla_hw_data *ha = base_vha->hw; 5606 5607 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5608 "Trying force recovery of the IDC lock.\n"); 5609 5610 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5611 if (rval) 5612 return rval; 5613 5614 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5615 return QLA_SUCCESS; 5616 } else { 5617 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5618 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5619 data); 5620 if (rval) 5621 return rval; 5622 5623 msleep(200); 5624 5625 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5626 &data); 5627 if (rval) 5628 return rval; 5629 5630 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5631 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5632 ~(idc_lck_rcvry_stage_mask)); 5633 rval = qla83xx_wr_reg(base_vha, 5634 QLA83XX_IDC_LOCK_RECOVERY, data); 5635 if (rval) 5636 return rval; 5637 5638 /* Forcefully perform IDC UnLock */ 5639 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5640 &data); 5641 if (rval) 5642 return rval; 5643 /* Clear lock-id by setting 0xff */ 5644 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5645 0xff); 5646 if (rval) 5647 return rval; 5648 /* Clear lock-recovery by setting 0x0 */ 5649 rval = qla83xx_wr_reg(base_vha, 5650 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5651 if (rval) 5652 return rval; 5653 } else 5654 return QLA_SUCCESS; 5655 } 5656 5657 return rval; 5658 } 5659 5660 static int 5661 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5662 { 5663 int rval = QLA_SUCCESS; 5664 uint32_t o_drv_lockid, n_drv_lockid; 5665 unsigned long lock_recovery_timeout; 5666 5667 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5668 retry_lockid: 5669 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5670 if (rval) 5671 goto exit; 5672 5673 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5674 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5675 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5676 return QLA_SUCCESS; 5677 else 5678 return QLA_FUNCTION_FAILED; 5679 } 5680 5681 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5682 if (rval) 5683 goto exit; 5684 5685 if (o_drv_lockid == n_drv_lockid) { 5686 qla83xx_wait_logic(); 5687 goto retry_lockid; 5688 } else 5689 return QLA_SUCCESS; 5690 5691 exit: 5692 return rval; 5693 } 5694 5695 void 5696 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5697 { 5698 uint32_t data; 5699 uint32_t lock_owner; 5700 struct qla_hw_data *ha = base_vha->hw; 5701 5702 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5703 retry_lock: 5704 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5705 == QLA_SUCCESS) { 5706 if (data) { 5707 /* Setting lock-id to our function-number */ 5708 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5709 ha->portnum); 5710 } else { 5711 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5712 &lock_owner); 5713 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5714 "Failed to acquire IDC lock, acquired by %d, " 5715 "retrying...\n", lock_owner); 5716 5717 /* Retry/Perform IDC-Lock recovery */ 5718 if (qla83xx_idc_lock_recovery(base_vha) 5719 == QLA_SUCCESS) { 5720 qla83xx_wait_logic(); 5721 goto retry_lock; 5722 } else 5723 ql_log(ql_log_warn, base_vha, 0xb075, 5724 "IDC Lock recovery FAILED.\n"); 5725 } 5726 5727 } 5728 5729 return; 5730 } 5731 5732 void 5733 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5734 { 5735 #if 0 5736 uint16_t options = (requester_id << 15) | BIT_7; 5737 #endif 5738 uint16_t retry; 5739 uint32_t data; 5740 struct qla_hw_data *ha = base_vha->hw; 5741 5742 /* IDC-unlock implementation using driver-unlock/lock-id 5743 * remote registers 5744 */ 5745 retry = 0; 5746 retry_unlock: 5747 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5748 == QLA_SUCCESS) { 5749 if (data == ha->portnum) { 5750 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5751 /* Clearing lock-id by setting 0xff */ 5752 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5753 } else if (retry < 10) { 5754 /* SV: XXX: IDC unlock retrying needed here? */ 5755 5756 /* Retry for IDC-unlock */ 5757 qla83xx_wait_logic(); 5758 retry++; 5759 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5760 "Failed to release IDC lock, retrying=%d\n", retry); 5761 goto retry_unlock; 5762 } 5763 } else if (retry < 10) { 5764 /* Retry for IDC-unlock */ 5765 qla83xx_wait_logic(); 5766 retry++; 5767 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5768 "Failed to read drv-lockid, retrying=%d\n", retry); 5769 goto retry_unlock; 5770 } 5771 5772 return; 5773 5774 #if 0 5775 /* XXX: IDC-unlock implementation using access-control mbx */ 5776 retry = 0; 5777 retry_unlock2: 5778 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5779 if (retry < 10) { 5780 /* Retry for IDC-unlock */ 5781 qla83xx_wait_logic(); 5782 retry++; 5783 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5784 "Failed to release IDC lock, retrying=%d\n", retry); 5785 goto retry_unlock2; 5786 } 5787 } 5788 5789 return; 5790 #endif 5791 } 5792 5793 int 5794 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5795 { 5796 int rval = QLA_SUCCESS; 5797 struct qla_hw_data *ha = vha->hw; 5798 uint32_t drv_presence; 5799 5800 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5801 if (rval == QLA_SUCCESS) { 5802 drv_presence |= (1 << ha->portnum); 5803 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5804 drv_presence); 5805 } 5806 5807 return rval; 5808 } 5809 5810 int 5811 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5812 { 5813 int rval = QLA_SUCCESS; 5814 5815 qla83xx_idc_lock(vha, 0); 5816 rval = __qla83xx_set_drv_presence(vha); 5817 qla83xx_idc_unlock(vha, 0); 5818 5819 return rval; 5820 } 5821 5822 int 5823 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5824 { 5825 int rval = QLA_SUCCESS; 5826 struct qla_hw_data *ha = vha->hw; 5827 uint32_t drv_presence; 5828 5829 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5830 if (rval == QLA_SUCCESS) { 5831 drv_presence &= ~(1 << ha->portnum); 5832 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5833 drv_presence); 5834 } 5835 5836 return rval; 5837 } 5838 5839 int 5840 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5841 { 5842 int rval = QLA_SUCCESS; 5843 5844 qla83xx_idc_lock(vha, 0); 5845 rval = __qla83xx_clear_drv_presence(vha); 5846 qla83xx_idc_unlock(vha, 0); 5847 5848 return rval; 5849 } 5850 5851 static void 5852 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5853 { 5854 struct qla_hw_data *ha = vha->hw; 5855 uint32_t drv_ack, drv_presence; 5856 unsigned long ack_timeout; 5857 5858 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5859 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5860 while (1) { 5861 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5862 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5863 if ((drv_ack & drv_presence) == drv_presence) 5864 break; 5865 5866 if (time_after_eq(jiffies, ack_timeout)) { 5867 ql_log(ql_log_warn, vha, 0xb067, 5868 "RESET ACK TIMEOUT! drv_presence=0x%x " 5869 "drv_ack=0x%x\n", drv_presence, drv_ack); 5870 /* 5871 * The function(s) which did not ack in time are forced 5872 * to withdraw any further participation in the IDC 5873 * reset. 5874 */ 5875 if (drv_ack != drv_presence) 5876 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5877 drv_ack); 5878 break; 5879 } 5880 5881 qla83xx_idc_unlock(vha, 0); 5882 msleep(1000); 5883 qla83xx_idc_lock(vha, 0); 5884 } 5885 5886 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5887 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5888 } 5889 5890 static int 5891 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5892 { 5893 int rval = QLA_SUCCESS; 5894 uint32_t idc_control; 5895 5896 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5897 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5898 5899 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5900 __qla83xx_get_idc_control(vha, &idc_control); 5901 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5902 __qla83xx_set_idc_control(vha, 0); 5903 5904 qla83xx_idc_unlock(vha, 0); 5905 rval = qla83xx_restart_nic_firmware(vha); 5906 qla83xx_idc_lock(vha, 0); 5907 5908 if (rval != QLA_SUCCESS) { 5909 ql_log(ql_log_fatal, vha, 0xb06a, 5910 "Failed to restart NIC f/w.\n"); 5911 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5912 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5913 } else { 5914 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5915 "Success in restarting nic f/w.\n"); 5916 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5917 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5918 } 5919 5920 return rval; 5921 } 5922 5923 /* Assumes idc_lock always held on entry */ 5924 int 5925 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5926 { 5927 struct qla_hw_data *ha = base_vha->hw; 5928 int rval = QLA_SUCCESS; 5929 unsigned long dev_init_timeout; 5930 uint32_t dev_state; 5931 5932 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5933 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5934 5935 while (1) { 5936 5937 if (time_after_eq(jiffies, dev_init_timeout)) { 5938 ql_log(ql_log_warn, base_vha, 0xb06e, 5939 "Initialization TIMEOUT!\n"); 5940 /* Init timeout. Disable further NIC Core 5941 * communication. 5942 */ 5943 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5944 QLA8XXX_DEV_FAILED); 5945 ql_log(ql_log_info, base_vha, 0xb06f, 5946 "HW State: FAILED.\n"); 5947 } 5948 5949 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5950 switch (dev_state) { 5951 case QLA8XXX_DEV_READY: 5952 if (ha->flags.nic_core_reset_owner) 5953 qla83xx_idc_audit(base_vha, 5954 IDC_AUDIT_COMPLETION); 5955 ha->flags.nic_core_reset_owner = 0; 5956 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5957 "Reset_owner reset by 0x%x.\n", 5958 ha->portnum); 5959 goto exit; 5960 case QLA8XXX_DEV_COLD: 5961 if (ha->flags.nic_core_reset_owner) 5962 rval = qla83xx_device_bootstrap(base_vha); 5963 else { 5964 /* Wait for AEN to change device-state */ 5965 qla83xx_idc_unlock(base_vha, 0); 5966 msleep(1000); 5967 qla83xx_idc_lock(base_vha, 0); 5968 } 5969 break; 5970 case QLA8XXX_DEV_INITIALIZING: 5971 /* Wait for AEN to change device-state */ 5972 qla83xx_idc_unlock(base_vha, 0); 5973 msleep(1000); 5974 qla83xx_idc_lock(base_vha, 0); 5975 break; 5976 case QLA8XXX_DEV_NEED_RESET: 5977 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5978 qla83xx_need_reset_handler(base_vha); 5979 else { 5980 /* Wait for AEN to change device-state */ 5981 qla83xx_idc_unlock(base_vha, 0); 5982 msleep(1000); 5983 qla83xx_idc_lock(base_vha, 0); 5984 } 5985 /* reset timeout value after need reset handler */ 5986 dev_init_timeout = jiffies + 5987 (ha->fcoe_dev_init_timeout * HZ); 5988 break; 5989 case QLA8XXX_DEV_NEED_QUIESCENT: 5990 /* XXX: DEBUG for now */ 5991 qla83xx_idc_unlock(base_vha, 0); 5992 msleep(1000); 5993 qla83xx_idc_lock(base_vha, 0); 5994 break; 5995 case QLA8XXX_DEV_QUIESCENT: 5996 /* XXX: DEBUG for now */ 5997 if (ha->flags.quiesce_owner) 5998 goto exit; 5999 6000 qla83xx_idc_unlock(base_vha, 0); 6001 msleep(1000); 6002 qla83xx_idc_lock(base_vha, 0); 6003 dev_init_timeout = jiffies + 6004 (ha->fcoe_dev_init_timeout * HZ); 6005 break; 6006 case QLA8XXX_DEV_FAILED: 6007 if (ha->flags.nic_core_reset_owner) 6008 qla83xx_idc_audit(base_vha, 6009 IDC_AUDIT_COMPLETION); 6010 ha->flags.nic_core_reset_owner = 0; 6011 __qla83xx_clear_drv_presence(base_vha); 6012 qla83xx_idc_unlock(base_vha, 0); 6013 qla8xxx_dev_failed_handler(base_vha); 6014 rval = QLA_FUNCTION_FAILED; 6015 qla83xx_idc_lock(base_vha, 0); 6016 goto exit; 6017 case QLA8XXX_BAD_VALUE: 6018 qla83xx_idc_unlock(base_vha, 0); 6019 msleep(1000); 6020 qla83xx_idc_lock(base_vha, 0); 6021 break; 6022 default: 6023 ql_log(ql_log_warn, base_vha, 0xb071, 6024 "Unknown Device State: %x.\n", dev_state); 6025 qla83xx_idc_unlock(base_vha, 0); 6026 qla8xxx_dev_failed_handler(base_vha); 6027 rval = QLA_FUNCTION_FAILED; 6028 qla83xx_idc_lock(base_vha, 0); 6029 goto exit; 6030 } 6031 } 6032 6033 exit: 6034 return rval; 6035 } 6036 6037 void 6038 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6039 { 6040 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6041 board_disable); 6042 struct pci_dev *pdev = ha->pdev; 6043 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6044 6045 /* 6046 * if UNLOAD flag is already set, then continue unload, 6047 * where it was set first. 6048 */ 6049 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6050 return; 6051 6052 ql_log(ql_log_warn, base_vha, 0x015b, 6053 "Disabling adapter.\n"); 6054 6055 if (!atomic_read(&pdev->enable_cnt)) { 6056 ql_log(ql_log_info, base_vha, 0xfffc, 6057 "PCI device disabled, no action req for PCI error=%lx\n", 6058 base_vha->pci_flags); 6059 return; 6060 } 6061 6062 qla2x00_wait_for_sess_deletion(base_vha); 6063 6064 set_bit(UNLOADING, &base_vha->dpc_flags); 6065 6066 qla2x00_delete_all_vps(ha, base_vha); 6067 6068 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6069 6070 qla2x00_dfs_remove(base_vha); 6071 6072 qla84xx_put_chip(base_vha); 6073 6074 if (base_vha->timer_active) 6075 qla2x00_stop_timer(base_vha); 6076 6077 base_vha->flags.online = 0; 6078 6079 qla2x00_destroy_deferred_work(ha); 6080 6081 /* 6082 * Do not try to stop beacon blink as it will issue a mailbox 6083 * command. 6084 */ 6085 qla2x00_free_sysfs_attr(base_vha, false); 6086 6087 fc_remove_host(base_vha->host); 6088 6089 scsi_remove_host(base_vha->host); 6090 6091 base_vha->flags.init_done = 0; 6092 qla25xx_delete_queues(base_vha); 6093 qla2x00_free_fcports(base_vha); 6094 qla2x00_free_irqs(base_vha); 6095 qla2x00_mem_free(ha); 6096 qla82xx_md_free(base_vha); 6097 qla2x00_free_queues(ha); 6098 6099 qla2x00_unmap_iobases(ha); 6100 6101 pci_release_selected_regions(ha->pdev, ha->bars); 6102 pci_disable_pcie_error_reporting(pdev); 6103 pci_disable_device(pdev); 6104 6105 /* 6106 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6107 */ 6108 } 6109 6110 /************************************************************************** 6111 * qla2x00_do_dpc 6112 * This kernel thread is a task that is schedule by the interrupt handler 6113 * to perform the background processing for interrupts. 6114 * 6115 * Notes: 6116 * This task always run in the context of a kernel thread. It 6117 * is kick-off by the driver's detect code and starts up 6118 * up one per adapter. It immediately goes to sleep and waits for 6119 * some fibre event. When either the interrupt handler or 6120 * the timer routine detects a event it will one of the task 6121 * bits then wake us up. 6122 **************************************************************************/ 6123 static int 6124 qla2x00_do_dpc(void *data) 6125 { 6126 scsi_qla_host_t *base_vha; 6127 struct qla_hw_data *ha; 6128 uint32_t online; 6129 struct qla_qpair *qpair; 6130 6131 ha = (struct qla_hw_data *)data; 6132 base_vha = pci_get_drvdata(ha->pdev); 6133 6134 set_user_nice(current, MIN_NICE); 6135 6136 set_current_state(TASK_INTERRUPTIBLE); 6137 while (!kthread_should_stop()) { 6138 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6139 "DPC handler sleeping.\n"); 6140 6141 schedule(); 6142 6143 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6144 goto end_loop; 6145 6146 if (ha->flags.eeh_busy) { 6147 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6148 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6149 goto end_loop; 6150 } 6151 6152 ha->dpc_active = 1; 6153 6154 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6155 "DPC handler waking up, dpc_flags=0x%lx.\n", 6156 base_vha->dpc_flags); 6157 6158 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6159 break; 6160 6161 if (IS_P3P_TYPE(ha)) { 6162 if (IS_QLA8044(ha)) { 6163 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6164 &base_vha->dpc_flags)) { 6165 qla8044_idc_lock(ha); 6166 qla8044_wr_direct(base_vha, 6167 QLA8044_CRB_DEV_STATE_INDEX, 6168 QLA8XXX_DEV_FAILED); 6169 qla8044_idc_unlock(ha); 6170 ql_log(ql_log_info, base_vha, 0x4004, 6171 "HW State: FAILED.\n"); 6172 qla8044_device_state_handler(base_vha); 6173 continue; 6174 } 6175 6176 } else { 6177 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6178 &base_vha->dpc_flags)) { 6179 qla82xx_idc_lock(ha); 6180 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6181 QLA8XXX_DEV_FAILED); 6182 qla82xx_idc_unlock(ha); 6183 ql_log(ql_log_info, base_vha, 0x0151, 6184 "HW State: FAILED.\n"); 6185 qla82xx_device_state_handler(base_vha); 6186 continue; 6187 } 6188 } 6189 6190 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6191 &base_vha->dpc_flags)) { 6192 6193 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6194 "FCoE context reset scheduled.\n"); 6195 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6196 &base_vha->dpc_flags))) { 6197 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6198 /* FCoE-ctx reset failed. 6199 * Escalate to chip-reset 6200 */ 6201 set_bit(ISP_ABORT_NEEDED, 6202 &base_vha->dpc_flags); 6203 } 6204 clear_bit(ABORT_ISP_ACTIVE, 6205 &base_vha->dpc_flags); 6206 } 6207 6208 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6209 "FCoE context reset end.\n"); 6210 } 6211 } else if (IS_QLAFX00(ha)) { 6212 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6213 &base_vha->dpc_flags)) { 6214 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6215 "Firmware Reset Recovery\n"); 6216 if (qlafx00_reset_initialize(base_vha)) { 6217 /* Failed. Abort isp later. */ 6218 if (!test_bit(UNLOADING, 6219 &base_vha->dpc_flags)) { 6220 set_bit(ISP_UNRECOVERABLE, 6221 &base_vha->dpc_flags); 6222 ql_dbg(ql_dbg_dpc, base_vha, 6223 0x4021, 6224 "Reset Recovery Failed\n"); 6225 } 6226 } 6227 } 6228 6229 if (test_and_clear_bit(FX00_TARGET_SCAN, 6230 &base_vha->dpc_flags)) { 6231 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6232 "ISPFx00 Target Scan scheduled\n"); 6233 if (qlafx00_rescan_isp(base_vha)) { 6234 if (!test_bit(UNLOADING, 6235 &base_vha->dpc_flags)) 6236 set_bit(ISP_UNRECOVERABLE, 6237 &base_vha->dpc_flags); 6238 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6239 "ISPFx00 Target Scan Failed\n"); 6240 } 6241 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6242 "ISPFx00 Target Scan End\n"); 6243 } 6244 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6245 &base_vha->dpc_flags)) { 6246 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6247 "ISPFx00 Host Info resend scheduled\n"); 6248 qlafx00_fx_disc(base_vha, 6249 &base_vha->hw->mr.fcport, 6250 FXDISC_REG_HOST_INFO); 6251 } 6252 } 6253 6254 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6255 &base_vha->dpc_flags) && 6256 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6257 qla24xx_detect_sfp(base_vha); 6258 6259 if (ha->flags.detected_lr_sfp != 6260 ha->flags.using_lr_setting) 6261 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6262 } 6263 6264 if (test_and_clear_bit 6265 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6266 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6267 bool do_reset = true; 6268 6269 switch (base_vha->qlini_mode) { 6270 case QLA2XXX_INI_MODE_ENABLED: 6271 break; 6272 case QLA2XXX_INI_MODE_DISABLED: 6273 if (!qla_tgt_mode_enabled(base_vha) && 6274 !ha->flags.fw_started) 6275 do_reset = false; 6276 break; 6277 case QLA2XXX_INI_MODE_DUAL: 6278 if (!qla_dual_mode_enabled(base_vha) && 6279 !ha->flags.fw_started) 6280 do_reset = false; 6281 break; 6282 default: 6283 break; 6284 } 6285 6286 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6287 &base_vha->dpc_flags))) { 6288 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6289 "ISP abort scheduled.\n"); 6290 if (ha->isp_ops->abort_isp(base_vha)) { 6291 /* failed. retry later */ 6292 set_bit(ISP_ABORT_NEEDED, 6293 &base_vha->dpc_flags); 6294 } 6295 clear_bit(ABORT_ISP_ACTIVE, 6296 &base_vha->dpc_flags); 6297 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6298 "ISP abort end.\n"); 6299 } 6300 } 6301 6302 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6303 &base_vha->dpc_flags)) { 6304 qla2x00_update_fcports(base_vha); 6305 } 6306 6307 if (IS_QLAFX00(ha)) 6308 goto loop_resync_check; 6309 6310 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6311 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6312 "Quiescence mode scheduled.\n"); 6313 if (IS_P3P_TYPE(ha)) { 6314 if (IS_QLA82XX(ha)) 6315 qla82xx_device_state_handler(base_vha); 6316 if (IS_QLA8044(ha)) 6317 qla8044_device_state_handler(base_vha); 6318 clear_bit(ISP_QUIESCE_NEEDED, 6319 &base_vha->dpc_flags); 6320 if (!ha->flags.quiesce_owner) { 6321 qla2x00_perform_loop_resync(base_vha); 6322 if (IS_QLA82XX(ha)) { 6323 qla82xx_idc_lock(ha); 6324 qla82xx_clear_qsnt_ready( 6325 base_vha); 6326 qla82xx_idc_unlock(ha); 6327 } else if (IS_QLA8044(ha)) { 6328 qla8044_idc_lock(ha); 6329 qla8044_clear_qsnt_ready( 6330 base_vha); 6331 qla8044_idc_unlock(ha); 6332 } 6333 } 6334 } else { 6335 clear_bit(ISP_QUIESCE_NEEDED, 6336 &base_vha->dpc_flags); 6337 qla2x00_quiesce_io(base_vha); 6338 } 6339 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6340 "Quiescence mode end.\n"); 6341 } 6342 6343 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6344 &base_vha->dpc_flags) && 6345 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6346 6347 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6348 "Reset marker scheduled.\n"); 6349 qla2x00_rst_aen(base_vha); 6350 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6351 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6352 "Reset marker end.\n"); 6353 } 6354 6355 /* Retry each device up to login retry count */ 6356 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6357 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6358 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6359 6360 if (!base_vha->relogin_jif || 6361 time_after_eq(jiffies, base_vha->relogin_jif)) { 6362 base_vha->relogin_jif = jiffies + HZ; 6363 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6364 6365 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6366 "Relogin scheduled.\n"); 6367 qla24xx_post_relogin_work(base_vha); 6368 } 6369 } 6370 loop_resync_check: 6371 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6372 &base_vha->dpc_flags)) { 6373 6374 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6375 "Loop resync scheduled.\n"); 6376 6377 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6378 &base_vha->dpc_flags))) { 6379 6380 qla2x00_loop_resync(base_vha); 6381 6382 clear_bit(LOOP_RESYNC_ACTIVE, 6383 &base_vha->dpc_flags); 6384 } 6385 6386 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6387 "Loop resync end.\n"); 6388 } 6389 6390 if (IS_QLAFX00(ha)) 6391 goto intr_on_check; 6392 6393 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6394 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6395 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6396 qla2xxx_flash_npiv_conf(base_vha); 6397 } 6398 6399 intr_on_check: 6400 if (!ha->interrupts_on) 6401 ha->isp_ops->enable_intrs(ha); 6402 6403 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6404 &base_vha->dpc_flags)) { 6405 if (ha->beacon_blink_led == 1) 6406 ha->isp_ops->beacon_blink(base_vha); 6407 } 6408 6409 /* qpair online check */ 6410 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6411 &base_vha->dpc_flags)) { 6412 if (ha->flags.eeh_busy || 6413 ha->flags.pci_channel_io_perm_failure) 6414 online = 0; 6415 else 6416 online = 1; 6417 6418 mutex_lock(&ha->mq_lock); 6419 list_for_each_entry(qpair, &base_vha->qp_list, 6420 qp_list_elem) 6421 qpair->online = online; 6422 mutex_unlock(&ha->mq_lock); 6423 } 6424 6425 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6426 &base_vha->dpc_flags)) { 6427 ql_log(ql_log_info, base_vha, 0xffffff, 6428 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6429 ha->nvme_last_rptd_aen); 6430 if (qla27xx_set_zio_threshold(base_vha, 6431 ha->nvme_last_rptd_aen)) { 6432 ql_log(ql_log_info, base_vha, 0xffffff, 6433 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6434 ha->nvme_last_rptd_aen); 6435 } 6436 } 6437 6438 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6439 &base_vha->dpc_flags)) { 6440 ql_log(ql_log_info, base_vha, 0xffffff, 6441 "SET ZIO Activity exchange threshold to %d.\n", 6442 ha->last_zio_threshold); 6443 qla27xx_set_zio_threshold(base_vha, 6444 ha->last_zio_threshold); 6445 } 6446 6447 if (!IS_QLAFX00(ha)) 6448 qla2x00_do_dpc_all_vps(base_vha); 6449 6450 if (test_and_clear_bit(N2N_LINK_RESET, 6451 &base_vha->dpc_flags)) { 6452 qla2x00_lip_reset(base_vha); 6453 } 6454 6455 ha->dpc_active = 0; 6456 end_loop: 6457 set_current_state(TASK_INTERRUPTIBLE); 6458 } /* End of while(1) */ 6459 __set_current_state(TASK_RUNNING); 6460 6461 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6462 "DPC handler exiting.\n"); 6463 6464 /* 6465 * Make sure that nobody tries to wake us up again. 6466 */ 6467 ha->dpc_active = 0; 6468 6469 /* Cleanup any residual CTX SRBs. */ 6470 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6471 6472 return 0; 6473 } 6474 6475 void 6476 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6477 { 6478 struct qla_hw_data *ha = vha->hw; 6479 struct task_struct *t = ha->dpc_thread; 6480 6481 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6482 wake_up_process(t); 6483 } 6484 6485 /* 6486 * qla2x00_rst_aen 6487 * Processes asynchronous reset. 6488 * 6489 * Input: 6490 * ha = adapter block pointer. 6491 */ 6492 static void 6493 qla2x00_rst_aen(scsi_qla_host_t *vha) 6494 { 6495 if (vha->flags.online && !vha->flags.reset_active && 6496 !atomic_read(&vha->loop_down_timer) && 6497 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6498 do { 6499 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6500 6501 /* 6502 * Issue marker command only when we are going to start 6503 * the I/O. 6504 */ 6505 vha->marker_needed = 1; 6506 } while (!atomic_read(&vha->loop_down_timer) && 6507 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6508 } 6509 } 6510 6511 /************************************************************************** 6512 * qla2x00_timer 6513 * 6514 * Description: 6515 * One second timer 6516 * 6517 * Context: Interrupt 6518 ***************************************************************************/ 6519 void 6520 qla2x00_timer(struct timer_list *t) 6521 { 6522 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6523 unsigned long cpu_flags = 0; 6524 int start_dpc = 0; 6525 int index; 6526 srb_t *sp; 6527 uint16_t w; 6528 struct qla_hw_data *ha = vha->hw; 6529 struct req_que *req; 6530 6531 if (ha->flags.eeh_busy) { 6532 ql_dbg(ql_dbg_timer, vha, 0x6000, 6533 "EEH = %d, restarting timer.\n", 6534 ha->flags.eeh_busy); 6535 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6536 return; 6537 } 6538 6539 /* 6540 * Hardware read to raise pending EEH errors during mailbox waits. If 6541 * the read returns -1 then disable the board. 6542 */ 6543 if (!pci_channel_offline(ha->pdev)) { 6544 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6545 qla2x00_check_reg16_for_disconnect(vha, w); 6546 } 6547 6548 /* Make sure qla82xx_watchdog is run only for physical port */ 6549 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6550 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6551 start_dpc++; 6552 if (IS_QLA82XX(ha)) 6553 qla82xx_watchdog(vha); 6554 else if (IS_QLA8044(ha)) 6555 qla8044_watchdog(vha); 6556 } 6557 6558 if (!vha->vp_idx && IS_QLAFX00(ha)) 6559 qlafx00_timer_routine(vha); 6560 6561 /* Loop down handler. */ 6562 if (atomic_read(&vha->loop_down_timer) > 0 && 6563 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6564 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6565 && vha->flags.online) { 6566 6567 if (atomic_read(&vha->loop_down_timer) == 6568 vha->loop_down_abort_time) { 6569 6570 ql_log(ql_log_info, vha, 0x6008, 6571 "Loop down - aborting the queues before time expires.\n"); 6572 6573 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6574 atomic_set(&vha->loop_state, LOOP_DEAD); 6575 6576 /* 6577 * Schedule an ISP abort to return any FCP2-device 6578 * commands. 6579 */ 6580 /* NPIV - scan physical port only */ 6581 if (!vha->vp_idx) { 6582 spin_lock_irqsave(&ha->hardware_lock, 6583 cpu_flags); 6584 req = ha->req_q_map[0]; 6585 for (index = 1; 6586 index < req->num_outstanding_cmds; 6587 index++) { 6588 fc_port_t *sfcp; 6589 6590 sp = req->outstanding_cmds[index]; 6591 if (!sp) 6592 continue; 6593 if (sp->cmd_type != TYPE_SRB) 6594 continue; 6595 if (sp->type != SRB_SCSI_CMD) 6596 continue; 6597 sfcp = sp->fcport; 6598 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6599 continue; 6600 6601 if (IS_QLA82XX(ha)) 6602 set_bit(FCOE_CTX_RESET_NEEDED, 6603 &vha->dpc_flags); 6604 else 6605 set_bit(ISP_ABORT_NEEDED, 6606 &vha->dpc_flags); 6607 break; 6608 } 6609 spin_unlock_irqrestore(&ha->hardware_lock, 6610 cpu_flags); 6611 } 6612 start_dpc++; 6613 } 6614 6615 /* if the loop has been down for 4 minutes, reinit adapter */ 6616 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6617 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6618 ql_log(ql_log_warn, vha, 0x6009, 6619 "Loop down - aborting ISP.\n"); 6620 6621 if (IS_QLA82XX(ha)) 6622 set_bit(FCOE_CTX_RESET_NEEDED, 6623 &vha->dpc_flags); 6624 else 6625 set_bit(ISP_ABORT_NEEDED, 6626 &vha->dpc_flags); 6627 } 6628 } 6629 ql_dbg(ql_dbg_timer, vha, 0x600a, 6630 "Loop down - seconds remaining %d.\n", 6631 atomic_read(&vha->loop_down_timer)); 6632 } 6633 /* Check if beacon LED needs to be blinked for physical host only */ 6634 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6635 /* There is no beacon_blink function for ISP82xx */ 6636 if (!IS_P3P_TYPE(ha)) { 6637 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6638 start_dpc++; 6639 } 6640 } 6641 6642 /* Process any deferred work. */ 6643 if (!list_empty(&vha->work_list)) { 6644 unsigned long flags; 6645 bool q = false; 6646 6647 spin_lock_irqsave(&vha->work_lock, flags); 6648 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6649 q = true; 6650 spin_unlock_irqrestore(&vha->work_lock, flags); 6651 if (q) 6652 queue_work(vha->hw->wq, &vha->iocb_work); 6653 } 6654 6655 /* 6656 * FC-NVME 6657 * see if the active AEN count has changed from what was last reported. 6658 */ 6659 if (!vha->vp_idx && 6660 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) && 6661 ha->zio_mode == QLA_ZIO_MODE_6 && 6662 !ha->flags.host_shutting_down) { 6663 ql_log(ql_log_info, vha, 0x3002, 6664 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6665 ha->nvme_last_rptd_aen); 6666 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6667 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6668 start_dpc++; 6669 } 6670 6671 if (!vha->vp_idx && 6672 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 6673 (ha->zio_mode == QLA_ZIO_MODE_6) && 6674 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 6675 ql_log(ql_log_info, vha, 0x3002, 6676 "Sched: Set ZIO exchange threshold to %d.\n", 6677 ha->last_zio_threshold); 6678 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 6679 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6680 start_dpc++; 6681 } 6682 6683 /* Schedule the DPC routine if needed */ 6684 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6685 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6686 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6687 start_dpc || 6688 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6689 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6690 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6691 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6692 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6693 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6694 ql_dbg(ql_dbg_timer, vha, 0x600b, 6695 "isp_abort_needed=%d loop_resync_needed=%d " 6696 "fcport_update_needed=%d start_dpc=%d " 6697 "reset_marker_needed=%d", 6698 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6699 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6700 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6701 start_dpc, 6702 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6703 ql_dbg(ql_dbg_timer, vha, 0x600c, 6704 "beacon_blink_needed=%d isp_unrecoverable=%d " 6705 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6706 "relogin_needed=%d.\n", 6707 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6708 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6709 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6710 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6711 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6712 qla2xxx_wake_dpc(vha); 6713 } 6714 6715 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6716 } 6717 6718 /* Firmware interface routines. */ 6719 6720 #define FW_ISP21XX 0 6721 #define FW_ISP22XX 1 6722 #define FW_ISP2300 2 6723 #define FW_ISP2322 3 6724 #define FW_ISP24XX 4 6725 #define FW_ISP25XX 5 6726 #define FW_ISP81XX 6 6727 #define FW_ISP82XX 7 6728 #define FW_ISP2031 8 6729 #define FW_ISP8031 9 6730 #define FW_ISP27XX 10 6731 #define FW_ISP28XX 11 6732 6733 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6734 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6735 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6736 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6737 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6738 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6739 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6740 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6741 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6742 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6743 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6744 #define FW_FILE_ISP28XX "ql2800_fw.bin" 6745 6746 6747 static DEFINE_MUTEX(qla_fw_lock); 6748 6749 static struct fw_blob qla_fw_blobs[] = { 6750 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6751 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6752 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6753 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6754 { .name = FW_FILE_ISP24XX, }, 6755 { .name = FW_FILE_ISP25XX, }, 6756 { .name = FW_FILE_ISP81XX, }, 6757 { .name = FW_FILE_ISP82XX, }, 6758 { .name = FW_FILE_ISP2031, }, 6759 { .name = FW_FILE_ISP8031, }, 6760 { .name = FW_FILE_ISP27XX, }, 6761 { .name = FW_FILE_ISP28XX, }, 6762 { .name = NULL, }, 6763 }; 6764 6765 struct fw_blob * 6766 qla2x00_request_firmware(scsi_qla_host_t *vha) 6767 { 6768 struct qla_hw_data *ha = vha->hw; 6769 struct fw_blob *blob; 6770 6771 if (IS_QLA2100(ha)) { 6772 blob = &qla_fw_blobs[FW_ISP21XX]; 6773 } else if (IS_QLA2200(ha)) { 6774 blob = &qla_fw_blobs[FW_ISP22XX]; 6775 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6776 blob = &qla_fw_blobs[FW_ISP2300]; 6777 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6778 blob = &qla_fw_blobs[FW_ISP2322]; 6779 } else if (IS_QLA24XX_TYPE(ha)) { 6780 blob = &qla_fw_blobs[FW_ISP24XX]; 6781 } else if (IS_QLA25XX(ha)) { 6782 blob = &qla_fw_blobs[FW_ISP25XX]; 6783 } else if (IS_QLA81XX(ha)) { 6784 blob = &qla_fw_blobs[FW_ISP81XX]; 6785 } else if (IS_QLA82XX(ha)) { 6786 blob = &qla_fw_blobs[FW_ISP82XX]; 6787 } else if (IS_QLA2031(ha)) { 6788 blob = &qla_fw_blobs[FW_ISP2031]; 6789 } else if (IS_QLA8031(ha)) { 6790 blob = &qla_fw_blobs[FW_ISP8031]; 6791 } else if (IS_QLA27XX(ha)) { 6792 blob = &qla_fw_blobs[FW_ISP27XX]; 6793 } else if (IS_QLA28XX(ha)) { 6794 blob = &qla_fw_blobs[FW_ISP28XX]; 6795 } else { 6796 return NULL; 6797 } 6798 6799 if (!blob->name) 6800 return NULL; 6801 6802 mutex_lock(&qla_fw_lock); 6803 if (blob->fw) 6804 goto out; 6805 6806 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6807 ql_log(ql_log_warn, vha, 0x0063, 6808 "Failed to load firmware image (%s).\n", blob->name); 6809 blob->fw = NULL; 6810 blob = NULL; 6811 } 6812 6813 out: 6814 mutex_unlock(&qla_fw_lock); 6815 return blob; 6816 } 6817 6818 static void 6819 qla2x00_release_firmware(void) 6820 { 6821 struct fw_blob *blob; 6822 6823 mutex_lock(&qla_fw_lock); 6824 for (blob = qla_fw_blobs; blob->name; blob++) 6825 release_firmware(blob->fw); 6826 mutex_unlock(&qla_fw_lock); 6827 } 6828 6829 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 6830 { 6831 struct qla_hw_data *ha = vha->hw; 6832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6833 struct qla_qpair *qpair = NULL; 6834 struct scsi_qla_host *vp; 6835 fc_port_t *fcport; 6836 int i; 6837 unsigned long flags; 6838 6839 ha->chip_reset++; 6840 6841 ha->base_qpair->chip_reset = ha->chip_reset; 6842 for (i = 0; i < ha->max_qpairs; i++) { 6843 if (ha->queue_pair_map[i]) 6844 ha->queue_pair_map[i]->chip_reset = 6845 ha->base_qpair->chip_reset; 6846 } 6847 6848 /* purge MBox commands */ 6849 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6850 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6851 complete(&ha->mbx_intr_comp); 6852 } 6853 6854 i = 0; 6855 6856 while (atomic_read(&ha->num_pend_mbx_stage3) || 6857 atomic_read(&ha->num_pend_mbx_stage2) || 6858 atomic_read(&ha->num_pend_mbx_stage1)) { 6859 msleep(20); 6860 i++; 6861 if (i > 50) 6862 break; 6863 } 6864 6865 ha->flags.purge_mbox = 0; 6866 6867 mutex_lock(&ha->mq_lock); 6868 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 6869 qpair->online = 0; 6870 mutex_unlock(&ha->mq_lock); 6871 6872 qla2x00_mark_all_devices_lost(vha, 0); 6873 6874 spin_lock_irqsave(&ha->vport_slock, flags); 6875 list_for_each_entry(vp, &ha->vp_list, list) { 6876 atomic_inc(&vp->vref_count); 6877 spin_unlock_irqrestore(&ha->vport_slock, flags); 6878 qla2x00_mark_all_devices_lost(vp, 0); 6879 spin_lock_irqsave(&ha->vport_slock, flags); 6880 atomic_dec(&vp->vref_count); 6881 } 6882 spin_unlock_irqrestore(&ha->vport_slock, flags); 6883 6884 /* Clear all async request states across all VPs. */ 6885 list_for_each_entry(fcport, &vha->vp_fcports, list) 6886 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6887 6888 spin_lock_irqsave(&ha->vport_slock, flags); 6889 list_for_each_entry(vp, &ha->vp_list, list) { 6890 atomic_inc(&vp->vref_count); 6891 spin_unlock_irqrestore(&ha->vport_slock, flags); 6892 list_for_each_entry(fcport, &vp->vp_fcports, list) 6893 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6894 spin_lock_irqsave(&ha->vport_slock, flags); 6895 atomic_dec(&vp->vref_count); 6896 } 6897 spin_unlock_irqrestore(&ha->vport_slock, flags); 6898 } 6899 6900 6901 static pci_ers_result_t 6902 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6903 { 6904 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6905 struct qla_hw_data *ha = vha->hw; 6906 6907 ql_dbg(ql_dbg_aer, vha, 0x9000, 6908 "PCI error detected, state %x.\n", state); 6909 6910 if (!atomic_read(&pdev->enable_cnt)) { 6911 ql_log(ql_log_info, vha, 0xffff, 6912 "PCI device is disabled,state %x\n", state); 6913 return PCI_ERS_RESULT_NEED_RESET; 6914 } 6915 6916 switch (state) { 6917 case pci_channel_io_normal: 6918 ha->flags.eeh_busy = 0; 6919 if (ql2xmqsupport || ql2xnvmeenable) { 6920 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6921 qla2xxx_wake_dpc(vha); 6922 } 6923 return PCI_ERS_RESULT_CAN_RECOVER; 6924 case pci_channel_io_frozen: 6925 ha->flags.eeh_busy = 1; 6926 qla_pci_error_cleanup(vha); 6927 return PCI_ERS_RESULT_NEED_RESET; 6928 case pci_channel_io_perm_failure: 6929 ha->flags.pci_channel_io_perm_failure = 1; 6930 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6931 if (ql2xmqsupport || ql2xnvmeenable) { 6932 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6933 qla2xxx_wake_dpc(vha); 6934 } 6935 return PCI_ERS_RESULT_DISCONNECT; 6936 } 6937 return PCI_ERS_RESULT_NEED_RESET; 6938 } 6939 6940 static pci_ers_result_t 6941 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6942 { 6943 int risc_paused = 0; 6944 uint32_t stat; 6945 unsigned long flags; 6946 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6947 struct qla_hw_data *ha = base_vha->hw; 6948 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6949 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6950 6951 if (IS_QLA82XX(ha)) 6952 return PCI_ERS_RESULT_RECOVERED; 6953 6954 spin_lock_irqsave(&ha->hardware_lock, flags); 6955 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6956 stat = RD_REG_DWORD(®->hccr); 6957 if (stat & HCCR_RISC_PAUSE) 6958 risc_paused = 1; 6959 } else if (IS_QLA23XX(ha)) { 6960 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6961 if (stat & HSR_RISC_PAUSED) 6962 risc_paused = 1; 6963 } else if (IS_FWI2_CAPABLE(ha)) { 6964 stat = RD_REG_DWORD(®24->host_status); 6965 if (stat & HSRX_RISC_PAUSED) 6966 risc_paused = 1; 6967 } 6968 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6969 6970 if (risc_paused) { 6971 ql_log(ql_log_info, base_vha, 0x9003, 6972 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6973 ha->isp_ops->fw_dump(base_vha, 0); 6974 6975 return PCI_ERS_RESULT_NEED_RESET; 6976 } else 6977 return PCI_ERS_RESULT_RECOVERED; 6978 } 6979 6980 static pci_ers_result_t 6981 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6982 { 6983 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6984 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6985 struct qla_hw_data *ha = base_vha->hw; 6986 int rc; 6987 struct qla_qpair *qpair = NULL; 6988 6989 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6990 "Slot Reset.\n"); 6991 6992 /* Workaround: qla2xxx driver which access hardware earlier 6993 * needs error state to be pci_channel_io_online. 6994 * Otherwise mailbox command timesout. 6995 */ 6996 pdev->error_state = pci_channel_io_normal; 6997 6998 pci_restore_state(pdev); 6999 7000 /* pci_restore_state() clears the saved_state flag of the device 7001 * save restored state which resets saved_state flag 7002 */ 7003 pci_save_state(pdev); 7004 7005 if (ha->mem_only) 7006 rc = pci_enable_device_mem(pdev); 7007 else 7008 rc = pci_enable_device(pdev); 7009 7010 if (rc) { 7011 ql_log(ql_log_warn, base_vha, 0x9005, 7012 "Can't re-enable PCI device after reset.\n"); 7013 goto exit_slot_reset; 7014 } 7015 7016 7017 if (ha->isp_ops->pci_config(base_vha)) 7018 goto exit_slot_reset; 7019 7020 mutex_lock(&ha->mq_lock); 7021 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7022 qpair->online = 1; 7023 mutex_unlock(&ha->mq_lock); 7024 7025 base_vha->flags.online = 1; 7026 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7027 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7028 ret = PCI_ERS_RESULT_RECOVERED; 7029 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7030 7031 7032 exit_slot_reset: 7033 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7034 "slot_reset return %x.\n", ret); 7035 7036 return ret; 7037 } 7038 7039 static void 7040 qla2xxx_pci_resume(struct pci_dev *pdev) 7041 { 7042 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7043 struct qla_hw_data *ha = base_vha->hw; 7044 int ret; 7045 7046 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7047 "pci_resume.\n"); 7048 7049 ha->flags.eeh_busy = 0; 7050 7051 ret = qla2x00_wait_for_hba_online(base_vha); 7052 if (ret != QLA_SUCCESS) { 7053 ql_log(ql_log_fatal, base_vha, 0x9002, 7054 "The device failed to resume I/O from slot/link_reset.\n"); 7055 } 7056 } 7057 7058 static void 7059 qla_pci_reset_prepare(struct pci_dev *pdev) 7060 { 7061 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7062 struct qla_hw_data *ha = base_vha->hw; 7063 struct qla_qpair *qpair; 7064 7065 ql_log(ql_log_warn, base_vha, 0xffff, 7066 "%s.\n", __func__); 7067 7068 /* 7069 * PCI FLR/function reset is about to reset the 7070 * slot. Stop the chip to stop all DMA access. 7071 * It is assumed that pci_reset_done will be called 7072 * after FLR to resume Chip operation. 7073 */ 7074 ha->flags.eeh_busy = 1; 7075 mutex_lock(&ha->mq_lock); 7076 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7077 qpair->online = 0; 7078 mutex_unlock(&ha->mq_lock); 7079 7080 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7081 qla2x00_abort_isp_cleanup(base_vha); 7082 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7083 } 7084 7085 static void 7086 qla_pci_reset_done(struct pci_dev *pdev) 7087 { 7088 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7089 struct qla_hw_data *ha = base_vha->hw; 7090 struct qla_qpair *qpair; 7091 7092 ql_log(ql_log_warn, base_vha, 0xffff, 7093 "%s.\n", __func__); 7094 7095 /* 7096 * FLR just completed by PCI layer. Resume adapter 7097 */ 7098 ha->flags.eeh_busy = 0; 7099 mutex_lock(&ha->mq_lock); 7100 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7101 qpair->online = 1; 7102 mutex_unlock(&ha->mq_lock); 7103 7104 base_vha->flags.online = 1; 7105 ha->isp_ops->abort_isp(base_vha); 7106 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7107 } 7108 7109 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7110 { 7111 int rc; 7112 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7113 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7114 7115 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7116 rc = blk_mq_map_queues(qmap); 7117 else 7118 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7119 return rc; 7120 } 7121 7122 struct scsi_host_template qla2xxx_driver_template = { 7123 .module = THIS_MODULE, 7124 .name = QLA2XXX_DRIVER_NAME, 7125 .queuecommand = qla2xxx_queuecommand, 7126 7127 .eh_timed_out = fc_eh_timed_out, 7128 .eh_abort_handler = qla2xxx_eh_abort, 7129 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7130 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7131 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7132 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7133 7134 .slave_configure = qla2xxx_slave_configure, 7135 7136 .slave_alloc = qla2xxx_slave_alloc, 7137 .slave_destroy = qla2xxx_slave_destroy, 7138 .scan_finished = qla2xxx_scan_finished, 7139 .scan_start = qla2xxx_scan_start, 7140 .change_queue_depth = scsi_change_queue_depth, 7141 .map_queues = qla2xxx_map_queues, 7142 .this_id = -1, 7143 .cmd_per_lun = 3, 7144 .sg_tablesize = SG_ALL, 7145 7146 .max_sectors = 0xFFFF, 7147 .shost_attrs = qla2x00_host_attrs, 7148 7149 .supported_mode = MODE_INITIATOR, 7150 .track_queue_depth = 1, 7151 .cmd_size = sizeof(srb_t), 7152 }; 7153 7154 static const struct pci_error_handlers qla2xxx_err_handler = { 7155 .error_detected = qla2xxx_pci_error_detected, 7156 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7157 .slot_reset = qla2xxx_pci_slot_reset, 7158 .resume = qla2xxx_pci_resume, 7159 .reset_prepare = qla_pci_reset_prepare, 7160 .reset_done = qla_pci_reset_done, 7161 }; 7162 7163 static struct pci_device_id qla2xxx_pci_tbl[] = { 7164 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7165 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7166 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7169 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7170 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7171 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7172 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7173 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7179 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7180 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7181 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7182 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7185 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7191 { 0 }, 7192 }; 7193 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7194 7195 static struct pci_driver qla2xxx_pci_driver = { 7196 .name = QLA2XXX_DRIVER_NAME, 7197 .driver = { 7198 .owner = THIS_MODULE, 7199 }, 7200 .id_table = qla2xxx_pci_tbl, 7201 .probe = qla2x00_probe_one, 7202 .remove = qla2x00_remove_one, 7203 .shutdown = qla2x00_shutdown, 7204 .err_handler = &qla2xxx_err_handler, 7205 }; 7206 7207 static const struct file_operations apidev_fops = { 7208 .owner = THIS_MODULE, 7209 .llseek = noop_llseek, 7210 }; 7211 7212 /** 7213 * qla2x00_module_init - Module initialization. 7214 **/ 7215 static int __init 7216 qla2x00_module_init(void) 7217 { 7218 int ret = 0; 7219 7220 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7221 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7222 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7223 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7224 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7225 BUILD_BUG_ON(sizeof(request_t) != 64); 7226 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7227 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7228 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7229 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7230 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7231 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7232 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7233 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7234 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7235 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7236 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7237 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7238 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7239 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7240 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7241 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7242 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7243 7244 /* Allocate cache for SRBs. */ 7245 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7246 SLAB_HWCACHE_ALIGN, NULL); 7247 if (srb_cachep == NULL) { 7248 ql_log(ql_log_fatal, NULL, 0x0001, 7249 "Unable to allocate SRB cache...Failing load!.\n"); 7250 return -ENOMEM; 7251 } 7252 7253 /* Initialize target kmem_cache and mem_pools */ 7254 ret = qlt_init(); 7255 if (ret < 0) { 7256 goto destroy_cache; 7257 } else if (ret > 0) { 7258 /* 7259 * If initiator mode is explictly disabled by qlt_init(), 7260 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7261 * performing scsi_scan_target() during LOOP UP event. 7262 */ 7263 qla2xxx_transport_functions.disable_target_scan = 1; 7264 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7265 } 7266 7267 /* Derive version string. */ 7268 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7269 if (ql2xextended_error_logging) 7270 strcat(qla2x00_version_str, "-debug"); 7271 if (ql2xextended_error_logging == 1) 7272 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7273 7274 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7275 qla_insert_tgt_attrs(); 7276 7277 qla2xxx_transport_template = 7278 fc_attach_transport(&qla2xxx_transport_functions); 7279 if (!qla2xxx_transport_template) { 7280 ql_log(ql_log_fatal, NULL, 0x0002, 7281 "fc_attach_transport failed...Failing load!.\n"); 7282 ret = -ENODEV; 7283 goto qlt_exit; 7284 } 7285 7286 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7287 if (apidev_major < 0) { 7288 ql_log(ql_log_fatal, NULL, 0x0003, 7289 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7290 } 7291 7292 qla2xxx_transport_vport_template = 7293 fc_attach_transport(&qla2xxx_transport_vport_functions); 7294 if (!qla2xxx_transport_vport_template) { 7295 ql_log(ql_log_fatal, NULL, 0x0004, 7296 "fc_attach_transport vport failed...Failing load!.\n"); 7297 ret = -ENODEV; 7298 goto unreg_chrdev; 7299 } 7300 ql_log(ql_log_info, NULL, 0x0005, 7301 "QLogic Fibre Channel HBA Driver: %s.\n", 7302 qla2x00_version_str); 7303 ret = pci_register_driver(&qla2xxx_pci_driver); 7304 if (ret) { 7305 ql_log(ql_log_fatal, NULL, 0x0006, 7306 "pci_register_driver failed...ret=%d Failing load!.\n", 7307 ret); 7308 goto release_vport_transport; 7309 } 7310 return ret; 7311 7312 release_vport_transport: 7313 fc_release_transport(qla2xxx_transport_vport_template); 7314 7315 unreg_chrdev: 7316 if (apidev_major >= 0) 7317 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7318 fc_release_transport(qla2xxx_transport_template); 7319 7320 qlt_exit: 7321 qlt_exit(); 7322 7323 destroy_cache: 7324 kmem_cache_destroy(srb_cachep); 7325 return ret; 7326 } 7327 7328 /** 7329 * qla2x00_module_exit - Module cleanup. 7330 **/ 7331 static void __exit 7332 qla2x00_module_exit(void) 7333 { 7334 pci_unregister_driver(&qla2xxx_pci_driver); 7335 qla2x00_release_firmware(); 7336 kmem_cache_destroy(ctx_cachep); 7337 fc_release_transport(qla2xxx_transport_vport_template); 7338 if (apidev_major >= 0) 7339 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7340 fc_release_transport(qla2xxx_transport_template); 7341 qlt_exit(); 7342 kmem_cache_destroy(srb_cachep); 7343 } 7344 7345 module_init(qla2x00_module_init); 7346 module_exit(qla2x00_module_exit); 7347 7348 MODULE_AUTHOR("QLogic Corporation"); 7349 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7350 MODULE_LICENSE("GPL"); 7351 MODULE_VERSION(QLA2XXX_VERSION); 7352 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7353 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7354 MODULE_FIRMWARE(FW_FILE_ISP2300); 7355 MODULE_FIRMWARE(FW_FILE_ISP2322); 7356 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7357 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7358