1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 MODULE_PARM_DESC(ql2xextended_error_logging, 85 "Option to enable extended error logging,\n" 86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 97 "\t\t0x1e400000 - Preferred value for capturing essential " 98 "debug information (equivalent to old " 99 "ql2xextended_error_logging=1).\n" 100 "\t\tDo LOGICAL OR of the value to enable more than one level"); 101 102 int ql2xshiftctondsd = 6; 103 module_param(ql2xshiftctondsd, int, S_IRUGO); 104 MODULE_PARM_DESC(ql2xshiftctondsd, 105 "Set to control shifting of command type processing " 106 "based on total number of SG elements."); 107 108 int ql2xfdmienable=1; 109 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 110 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 MODULE_PARM_DESC(ql2xfdmienable, 112 "Enables FDMI registrations. " 113 "0 - no FDMI. Default is 1 - perform FDMI."); 114 115 #define MAX_Q_DEPTH 32 116 static int ql2xmaxqdepth = MAX_Q_DEPTH; 117 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 118 MODULE_PARM_DESC(ql2xmaxqdepth, 119 "Maximum queue depth to set for each LUN. " 120 "Default is 32."); 121 122 int ql2xenabledif = 2; 123 module_param(ql2xenabledif, int, S_IRUGO); 124 MODULE_PARM_DESC(ql2xenabledif, 125 " Enable T10-CRC-DIF:\n" 126 " Default is 2.\n" 127 " 0 -- No DIF Support\n" 128 " 1 -- Enable DIF for all types\n" 129 " 2 -- Enable DIF for all types, except Type 0.\n"); 130 131 int ql2xenablehba_err_chk = 2; 132 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 133 MODULE_PARM_DESC(ql2xenablehba_err_chk, 134 " Enable T10-CRC-DIF Error isolation by HBA:\n" 135 " Default is 2.\n" 136 " 0 -- Error isolation disabled\n" 137 " 1 -- Error isolation enabled only for DIX Type 0\n" 138 " 2 -- Error isolation enabled for all Types\n"); 139 140 int ql2xiidmaenable=1; 141 module_param(ql2xiidmaenable, int, S_IRUGO); 142 MODULE_PARM_DESC(ql2xiidmaenable, 143 "Enables iIDMA settings " 144 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 145 146 int ql2xmaxqueues = 1; 147 module_param(ql2xmaxqueues, int, S_IRUGO); 148 MODULE_PARM_DESC(ql2xmaxqueues, 149 "Enables MQ settings " 150 "Default is 1 for single queue. Set it to number " 151 "of queues in MQ mode."); 152 153 int ql2xmultique_tag; 154 module_param(ql2xmultique_tag, int, S_IRUGO); 155 MODULE_PARM_DESC(ql2xmultique_tag, 156 "Enables CPU affinity settings for the driver " 157 "Default is 0 for no affinity of request and response IO. " 158 "Set it to 1 to turn on the cpu affinity."); 159 160 int ql2xfwloadbin; 161 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 162 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 163 MODULE_PARM_DESC(ql2xfwloadbin, 164 "Option to specify location from which to load ISP firmware:.\n" 165 " 2 -- load firmware via the request_firmware() (hotplug).\n" 166 " interface.\n" 167 " 1 -- load firmware from flash.\n" 168 " 0 -- use default semantics.\n"); 169 170 int ql2xetsenable; 171 module_param(ql2xetsenable, int, S_IRUGO); 172 MODULE_PARM_DESC(ql2xetsenable, 173 "Enables firmware ETS burst." 174 "Default is 0 - skip ETS enablement."); 175 176 int ql2xdbwr = 1; 177 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 178 MODULE_PARM_DESC(ql2xdbwr, 179 "Option to specify scheme for request queue posting.\n" 180 " 0 -- Regular doorbell.\n" 181 " 1 -- CAMRAM doorbell (faster).\n"); 182 183 int ql2xtargetreset = 1; 184 module_param(ql2xtargetreset, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xtargetreset, 186 "Enable target reset." 187 "Default is 1 - use hw defaults."); 188 189 int ql2xgffidenable; 190 module_param(ql2xgffidenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xgffidenable, 192 "Enables GFF_ID checks of port type. " 193 "Default is 0 - Do not use GFF_ID information."); 194 195 int ql2xasynctmfenable; 196 module_param(ql2xasynctmfenable, int, S_IRUGO); 197 MODULE_PARM_DESC(ql2xasynctmfenable, 198 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 199 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 200 201 int ql2xdontresethba; 202 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 203 MODULE_PARM_DESC(ql2xdontresethba, 204 "Option to specify reset behaviour.\n" 205 " 0 (Default) -- Reset on failure.\n" 206 " 1 -- Do not reset on failure.\n"); 207 208 uint64_t ql2xmaxlun = MAX_LUNS; 209 module_param(ql2xmaxlun, ullong, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmaxlun, 211 "Defines the maximum LU number to register with the SCSI " 212 "midlayer. Default is 65535."); 213 214 int ql2xmdcapmask = 0x1F; 215 module_param(ql2xmdcapmask, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdcapmask, 217 "Set the Minidump driver capture mask level. " 218 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 219 220 int ql2xmdenable = 1; 221 module_param(ql2xmdenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xmdenable, 223 "Enable/disable MiniDump. " 224 "0 - MiniDump disabled. " 225 "1 (Default) - MiniDump enabled."); 226 227 int ql2xexlogins = 0; 228 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xexlogins, 230 "Number of extended Logins. " 231 "0 (Default)- Disabled."); 232 233 int ql2xexchoffld = 0; 234 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 235 MODULE_PARM_DESC(ql2xexchoffld, 236 "Number of exchanges to offload. " 237 "0 (Default)- Disabled."); 238 239 int ql2xfwholdabts = 0; 240 module_param(ql2xfwholdabts, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xfwholdabts, 242 "Allow FW to hold status IOCB until ABTS rsp received. " 243 "0 (Default) Do not set fw option. " 244 "1 - Set fw option to hold ABTS."); 245 246 /* 247 * SCSI host template entry points 248 */ 249 static int qla2xxx_slave_configure(struct scsi_device * device); 250 static int qla2xxx_slave_alloc(struct scsi_device *); 251 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 252 static void qla2xxx_scan_start(struct Scsi_Host *); 253 static void qla2xxx_slave_destroy(struct scsi_device *); 254 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 255 static int qla2xxx_eh_abort(struct scsi_cmnd *); 256 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 257 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 258 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 259 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 260 261 static void qla2x00_clear_drv_active(struct qla_hw_data *); 262 static void qla2x00_free_device(scsi_qla_host_t *); 263 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 264 265 struct scsi_host_template qla2xxx_driver_template = { 266 .module = THIS_MODULE, 267 .name = QLA2XXX_DRIVER_NAME, 268 .queuecommand = qla2xxx_queuecommand, 269 270 .eh_abort_handler = qla2xxx_eh_abort, 271 .eh_device_reset_handler = qla2xxx_eh_device_reset, 272 .eh_target_reset_handler = qla2xxx_eh_target_reset, 273 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 274 .eh_host_reset_handler = qla2xxx_eh_host_reset, 275 276 .slave_configure = qla2xxx_slave_configure, 277 278 .slave_alloc = qla2xxx_slave_alloc, 279 .slave_destroy = qla2xxx_slave_destroy, 280 .scan_finished = qla2xxx_scan_finished, 281 .scan_start = qla2xxx_scan_start, 282 .change_queue_depth = scsi_change_queue_depth, 283 .this_id = -1, 284 .cmd_per_lun = 3, 285 .use_clustering = ENABLE_CLUSTERING, 286 .sg_tablesize = SG_ALL, 287 288 .max_sectors = 0xFFFF, 289 .shost_attrs = qla2x00_host_attrs, 290 291 .supported_mode = MODE_INITIATOR, 292 .track_queue_depth = 1, 293 }; 294 295 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 296 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 297 298 /* TODO Convert to inlines 299 * 300 * Timer routines 301 */ 302 303 __inline__ void 304 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 305 { 306 init_timer(&vha->timer); 307 vha->timer.expires = jiffies + interval * HZ; 308 vha->timer.data = (unsigned long)vha; 309 vha->timer.function = (void (*)(unsigned long))func; 310 add_timer(&vha->timer); 311 vha->timer_active = 1; 312 } 313 314 static inline void 315 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 316 { 317 /* Currently used for 82XX only. */ 318 if (vha->device_flags & DFLG_DEV_FAILED) { 319 ql_dbg(ql_dbg_timer, vha, 0x600d, 320 "Device in a failed state, returning.\n"); 321 return; 322 } 323 324 mod_timer(&vha->timer, jiffies + interval * HZ); 325 } 326 327 static __inline__ void 328 qla2x00_stop_timer(scsi_qla_host_t *vha) 329 { 330 del_timer_sync(&vha->timer); 331 vha->timer_active = 0; 332 } 333 334 static int qla2x00_do_dpc(void *data); 335 336 static void qla2x00_rst_aen(scsi_qla_host_t *); 337 338 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 339 struct req_que **, struct rsp_que **); 340 static void qla2x00_free_fw_dump(struct qla_hw_data *); 341 static void qla2x00_mem_free(struct qla_hw_data *); 342 343 /* -------------------------------------------------------------------------- */ 344 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 345 struct rsp_que *rsp) 346 { 347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 348 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 349 GFP_KERNEL); 350 if (!ha->req_q_map) { 351 ql_log(ql_log_fatal, vha, 0x003b, 352 "Unable to allocate memory for request queue ptrs.\n"); 353 goto fail_req_map; 354 } 355 356 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 357 GFP_KERNEL); 358 if (!ha->rsp_q_map) { 359 ql_log(ql_log_fatal, vha, 0x003c, 360 "Unable to allocate memory for response queue ptrs.\n"); 361 goto fail_rsp_map; 362 } 363 /* 364 * Make sure we record at least the request and response queue zero in 365 * case we need to free them if part of the probe fails. 366 */ 367 ha->rsp_q_map[0] = rsp; 368 ha->req_q_map[0] = req; 369 set_bit(0, ha->rsp_qid_map); 370 set_bit(0, ha->req_qid_map); 371 return 1; 372 373 fail_rsp_map: 374 kfree(ha->req_q_map); 375 ha->req_q_map = NULL; 376 fail_req_map: 377 return -ENOMEM; 378 } 379 380 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 381 { 382 if (IS_QLAFX00(ha)) { 383 if (req && req->ring_fx00) 384 dma_free_coherent(&ha->pdev->dev, 385 (req->length_fx00 + 1) * sizeof(request_t), 386 req->ring_fx00, req->dma_fx00); 387 } else if (req && req->ring) 388 dma_free_coherent(&ha->pdev->dev, 389 (req->length + 1) * sizeof(request_t), 390 req->ring, req->dma); 391 392 if (req) 393 kfree(req->outstanding_cmds); 394 395 kfree(req); 396 req = NULL; 397 } 398 399 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 400 { 401 if (IS_QLAFX00(ha)) { 402 if (rsp && rsp->ring) 403 dma_free_coherent(&ha->pdev->dev, 404 (rsp->length_fx00 + 1) * sizeof(request_t), 405 rsp->ring_fx00, rsp->dma_fx00); 406 } else if (rsp && rsp->ring) { 407 dma_free_coherent(&ha->pdev->dev, 408 (rsp->length + 1) * sizeof(response_t), 409 rsp->ring, rsp->dma); 410 } 411 kfree(rsp); 412 rsp = NULL; 413 } 414 415 static void qla2x00_free_queues(struct qla_hw_data *ha) 416 { 417 struct req_que *req; 418 struct rsp_que *rsp; 419 int cnt; 420 421 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 422 if (!test_bit(cnt, ha->req_qid_map)) 423 continue; 424 425 req = ha->req_q_map[cnt]; 426 qla2x00_free_req_que(ha, req); 427 } 428 kfree(ha->req_q_map); 429 ha->req_q_map = NULL; 430 431 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 432 if (!test_bit(cnt, ha->rsp_qid_map)) 433 continue; 434 435 rsp = ha->rsp_q_map[cnt]; 436 qla2x00_free_rsp_que(ha, rsp); 437 } 438 kfree(ha->rsp_q_map); 439 ha->rsp_q_map = NULL; 440 } 441 442 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 443 { 444 uint16_t options = 0; 445 int ques, req, ret; 446 struct qla_hw_data *ha = vha->hw; 447 448 if (!(ha->fw_attributes & BIT_6)) { 449 ql_log(ql_log_warn, vha, 0x00d8, 450 "Firmware is not multi-queue capable.\n"); 451 goto fail; 452 } 453 if (ql2xmultique_tag) { 454 /* create a request queue for IO */ 455 options |= BIT_7; 456 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 457 QLA_DEFAULT_QUE_QOS); 458 if (!req) { 459 ql_log(ql_log_warn, vha, 0x00e0, 460 "Failed to create request queue.\n"); 461 goto fail; 462 } 463 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 464 vha->req = ha->req_q_map[req]; 465 options |= BIT_1; 466 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 467 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 468 if (!ret) { 469 ql_log(ql_log_warn, vha, 0x00e8, 470 "Failed to create response queue.\n"); 471 goto fail2; 472 } 473 } 474 ha->flags.cpu_affinity_enabled = 1; 475 ql_dbg(ql_dbg_multiq, vha, 0xc007, 476 "CPU affinity mode enabled, " 477 "no. of response queues:%d no. of request queues:%d.\n", 478 ha->max_rsp_queues, ha->max_req_queues); 479 ql_dbg(ql_dbg_init, vha, 0x00e9, 480 "CPU affinity mode enabled, " 481 "no. of response queues:%d no. of request queues:%d.\n", 482 ha->max_rsp_queues, ha->max_req_queues); 483 } 484 return 0; 485 fail2: 486 qla25xx_delete_queues(vha); 487 destroy_workqueue(ha->wq); 488 ha->wq = NULL; 489 vha->req = ha->req_q_map[0]; 490 fail: 491 ha->mqenable = 0; 492 kfree(ha->req_q_map); 493 kfree(ha->rsp_q_map); 494 ha->max_req_queues = ha->max_rsp_queues = 1; 495 return 1; 496 } 497 498 static char * 499 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 500 { 501 struct qla_hw_data *ha = vha->hw; 502 static char *pci_bus_modes[] = { 503 "33", "66", "100", "133", 504 }; 505 uint16_t pci_bus; 506 507 strcpy(str, "PCI"); 508 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 509 if (pci_bus) { 510 strcat(str, "-X ("); 511 strcat(str, pci_bus_modes[pci_bus]); 512 } else { 513 pci_bus = (ha->pci_attr & BIT_8) >> 8; 514 strcat(str, " ("); 515 strcat(str, pci_bus_modes[pci_bus]); 516 } 517 strcat(str, " MHz)"); 518 519 return (str); 520 } 521 522 static char * 523 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 524 { 525 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 526 struct qla_hw_data *ha = vha->hw; 527 uint32_t pci_bus; 528 529 if (pci_is_pcie(ha->pdev)) { 530 char lwstr[6]; 531 uint32_t lstat, lspeed, lwidth; 532 533 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 534 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 535 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 536 537 strcpy(str, "PCIe ("); 538 switch (lspeed) { 539 case 1: 540 strcat(str, "2.5GT/s "); 541 break; 542 case 2: 543 strcat(str, "5.0GT/s "); 544 break; 545 case 3: 546 strcat(str, "8.0GT/s "); 547 break; 548 default: 549 strcat(str, "<unknown> "); 550 break; 551 } 552 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 553 strcat(str, lwstr); 554 555 return str; 556 } 557 558 strcpy(str, "PCI"); 559 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 560 if (pci_bus == 0 || pci_bus == 8) { 561 strcat(str, " ("); 562 strcat(str, pci_bus_modes[pci_bus >> 3]); 563 } else { 564 strcat(str, "-X "); 565 if (pci_bus & BIT_2) 566 strcat(str, "Mode 2"); 567 else 568 strcat(str, "Mode 1"); 569 strcat(str, " ("); 570 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 571 } 572 strcat(str, " MHz)"); 573 574 return str; 575 } 576 577 static char * 578 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 579 { 580 char un_str[10]; 581 struct qla_hw_data *ha = vha->hw; 582 583 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 584 ha->fw_minor_version, ha->fw_subminor_version); 585 586 if (ha->fw_attributes & BIT_9) { 587 strcat(str, "FLX"); 588 return (str); 589 } 590 591 switch (ha->fw_attributes & 0xFF) { 592 case 0x7: 593 strcat(str, "EF"); 594 break; 595 case 0x17: 596 strcat(str, "TP"); 597 break; 598 case 0x37: 599 strcat(str, "IP"); 600 break; 601 case 0x77: 602 strcat(str, "VI"); 603 break; 604 default: 605 sprintf(un_str, "(%x)", ha->fw_attributes); 606 strcat(str, un_str); 607 break; 608 } 609 if (ha->fw_attributes & 0x100) 610 strcat(str, "X"); 611 612 return (str); 613 } 614 615 static char * 616 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 617 { 618 struct qla_hw_data *ha = vha->hw; 619 620 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 621 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 622 return str; 623 } 624 625 void 626 qla2x00_sp_free_dma(void *vha, void *ptr) 627 { 628 srb_t *sp = (srb_t *)ptr; 629 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 630 struct qla_hw_data *ha = sp->fcport->vha->hw; 631 void *ctx = GET_CMD_CTX_SP(sp); 632 633 if (sp->flags & SRB_DMA_VALID) { 634 scsi_dma_unmap(cmd); 635 sp->flags &= ~SRB_DMA_VALID; 636 } 637 638 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 639 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 640 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 641 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 642 } 643 644 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 645 /* List assured to be having elements */ 646 qla2x00_clean_dsd_pool(ha, sp, NULL); 647 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 648 } 649 650 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 651 dma_pool_free(ha->dl_dma_pool, ctx, 652 ((struct crc_context *)ctx)->crc_ctx_dma); 653 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 654 } 655 656 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 657 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 658 659 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 660 ctx1->fcp_cmnd_dma); 661 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 662 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 663 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 664 mempool_free(ctx1, ha->ctx_mempool); 665 ctx1 = NULL; 666 } 667 668 CMD_SP(cmd) = NULL; 669 qla2x00_rel_sp(sp->fcport->vha, sp); 670 } 671 672 static void 673 qla2x00_sp_compl(void *data, void *ptr, int res) 674 { 675 struct qla_hw_data *ha = (struct qla_hw_data *)data; 676 srb_t *sp = (srb_t *)ptr; 677 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 678 679 cmd->result = res; 680 681 if (atomic_read(&sp->ref_count) == 0) { 682 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 683 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 684 sp, GET_CMD_SP(sp)); 685 if (ql2xextended_error_logging & ql_dbg_io) 686 WARN_ON(atomic_read(&sp->ref_count) == 0); 687 return; 688 } 689 if (!atomic_dec_and_test(&sp->ref_count)) 690 return; 691 692 qla2x00_sp_free_dma(ha, sp); 693 cmd->scsi_done(cmd); 694 } 695 696 /* If we are SP1 here, we need to still take and release the host_lock as SP1 697 * does not have the changes necessary to avoid taking host->host_lock. 698 */ 699 static int 700 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 701 { 702 scsi_qla_host_t *vha = shost_priv(host); 703 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 704 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 705 struct qla_hw_data *ha = vha->hw; 706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 707 srb_t *sp; 708 int rval; 709 710 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 711 cmd->result = DID_NO_CONNECT << 16; 712 goto qc24_fail_command; 713 } 714 715 if (ha->flags.eeh_busy) { 716 if (ha->flags.pci_channel_io_perm_failure) { 717 ql_dbg(ql_dbg_aer, vha, 0x9010, 718 "PCI Channel IO permanent failure, exiting " 719 "cmd=%p.\n", cmd); 720 cmd->result = DID_NO_CONNECT << 16; 721 } else { 722 ql_dbg(ql_dbg_aer, vha, 0x9011, 723 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 724 cmd->result = DID_REQUEUE << 16; 725 } 726 goto qc24_fail_command; 727 } 728 729 rval = fc_remote_port_chkready(rport); 730 if (rval) { 731 cmd->result = rval; 732 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 733 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 734 cmd, rval); 735 goto qc24_fail_command; 736 } 737 738 if (!vha->flags.difdix_supported && 739 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 740 ql_dbg(ql_dbg_io, vha, 0x3004, 741 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 742 cmd); 743 cmd->result = DID_NO_CONNECT << 16; 744 goto qc24_fail_command; 745 } 746 747 if (!fcport) { 748 cmd->result = DID_NO_CONNECT << 16; 749 goto qc24_fail_command; 750 } 751 752 if (atomic_read(&fcport->state) != FCS_ONLINE) { 753 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 754 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 755 ql_dbg(ql_dbg_io, vha, 0x3005, 756 "Returning DNC, fcport_state=%d loop_state=%d.\n", 757 atomic_read(&fcport->state), 758 atomic_read(&base_vha->loop_state)); 759 cmd->result = DID_NO_CONNECT << 16; 760 goto qc24_fail_command; 761 } 762 goto qc24_target_busy; 763 } 764 765 /* 766 * Return target busy if we've received a non-zero retry_delay_timer 767 * in a FCP_RSP. 768 */ 769 if (fcport->retry_delay_timestamp == 0) { 770 /* retry delay not set */ 771 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 772 fcport->retry_delay_timestamp = 0; 773 else 774 goto qc24_target_busy; 775 776 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 777 if (!sp) 778 goto qc24_host_busy; 779 780 sp->u.scmd.cmd = cmd; 781 sp->type = SRB_SCSI_CMD; 782 atomic_set(&sp->ref_count, 1); 783 CMD_SP(cmd) = (void *)sp; 784 sp->free = qla2x00_sp_free_dma; 785 sp->done = qla2x00_sp_compl; 786 787 rval = ha->isp_ops->start_scsi(sp); 788 if (rval != QLA_SUCCESS) { 789 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 790 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 791 goto qc24_host_busy_free_sp; 792 } 793 794 return 0; 795 796 qc24_host_busy_free_sp: 797 qla2x00_sp_free_dma(ha, sp); 798 799 qc24_host_busy: 800 return SCSI_MLQUEUE_HOST_BUSY; 801 802 qc24_target_busy: 803 return SCSI_MLQUEUE_TARGET_BUSY; 804 805 qc24_fail_command: 806 cmd->scsi_done(cmd); 807 808 return 0; 809 } 810 811 /* 812 * qla2x00_eh_wait_on_command 813 * Waits for the command to be returned by the Firmware for some 814 * max time. 815 * 816 * Input: 817 * cmd = Scsi Command to wait on. 818 * 819 * Return: 820 * Not Found : 0 821 * Found : 1 822 */ 823 static int 824 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 825 { 826 #define ABORT_POLLING_PERIOD 1000 827 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 828 unsigned long wait_iter = ABORT_WAIT_ITER; 829 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 830 struct qla_hw_data *ha = vha->hw; 831 int ret = QLA_SUCCESS; 832 833 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 834 ql_dbg(ql_dbg_taskm, vha, 0x8005, 835 "Return:eh_wait.\n"); 836 return ret; 837 } 838 839 while (CMD_SP(cmd) && wait_iter--) { 840 msleep(ABORT_POLLING_PERIOD); 841 } 842 if (CMD_SP(cmd)) 843 ret = QLA_FUNCTION_FAILED; 844 845 return ret; 846 } 847 848 /* 849 * qla2x00_wait_for_hba_online 850 * Wait till the HBA is online after going through 851 * <= MAX_RETRIES_OF_ISP_ABORT or 852 * finally HBA is disabled ie marked offline 853 * 854 * Input: 855 * ha - pointer to host adapter structure 856 * 857 * Note: 858 * Does context switching-Release SPIN_LOCK 859 * (if any) before calling this routine. 860 * 861 * Return: 862 * Success (Adapter is online) : 0 863 * Failed (Adapter is offline/disabled) : 1 864 */ 865 int 866 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 867 { 868 int return_status; 869 unsigned long wait_online; 870 struct qla_hw_data *ha = vha->hw; 871 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 872 873 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 874 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 875 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 876 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 877 ha->dpc_active) && time_before(jiffies, wait_online)) { 878 879 msleep(1000); 880 } 881 if (base_vha->flags.online) 882 return_status = QLA_SUCCESS; 883 else 884 return_status = QLA_FUNCTION_FAILED; 885 886 return (return_status); 887 } 888 889 /* 890 * qla2x00_wait_for_hba_ready 891 * Wait till the HBA is ready before doing driver unload 892 * 893 * Input: 894 * ha - pointer to host adapter structure 895 * 896 * Note: 897 * Does context switching-Release SPIN_LOCK 898 * (if any) before calling this routine. 899 * 900 */ 901 static void 902 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 903 { 904 struct qla_hw_data *ha = vha->hw; 905 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 906 907 while ((qla2x00_reset_active(vha) || ha->dpc_active || 908 ha->flags.mbox_busy) || 909 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 910 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 911 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 912 break; 913 msleep(1000); 914 } 915 } 916 917 int 918 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 919 { 920 int return_status; 921 unsigned long wait_reset; 922 struct qla_hw_data *ha = vha->hw; 923 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 924 925 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 926 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 927 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 928 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 929 ha->dpc_active) && time_before(jiffies, wait_reset)) { 930 931 msleep(1000); 932 933 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 934 ha->flags.chip_reset_done) 935 break; 936 } 937 if (ha->flags.chip_reset_done) 938 return_status = QLA_SUCCESS; 939 else 940 return_status = QLA_FUNCTION_FAILED; 941 942 return return_status; 943 } 944 945 static void 946 sp_get(struct srb *sp) 947 { 948 atomic_inc(&sp->ref_count); 949 } 950 951 #define ISP_REG_DISCONNECT 0xffffffffU 952 /************************************************************************** 953 * qla2x00_isp_reg_stat 954 * 955 * Description: 956 * Read the host status register of ISP before aborting the command. 957 * 958 * Input: 959 * ha = pointer to host adapter structure. 960 * 961 * 962 * Returns: 963 * Either true or false. 964 * 965 * Note: Return true if there is register disconnect. 966 **************************************************************************/ 967 static inline 968 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 969 { 970 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 971 972 return ((RD_REG_DWORD(®->host_status)) == ISP_REG_DISCONNECT); 973 } 974 975 /************************************************************************** 976 * qla2xxx_eh_abort 977 * 978 * Description: 979 * The abort function will abort the specified command. 980 * 981 * Input: 982 * cmd = Linux SCSI command packet to be aborted. 983 * 984 * Returns: 985 * Either SUCCESS or FAILED. 986 * 987 * Note: 988 * Only return FAILED if command not returned by firmware. 989 **************************************************************************/ 990 static int 991 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 992 { 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 994 srb_t *sp; 995 int ret; 996 unsigned int id; 997 uint64_t lun; 998 unsigned long flags; 999 int rval, wait = 0; 1000 struct qla_hw_data *ha = vha->hw; 1001 1002 if (qla2x00_isp_reg_stat(ha)) { 1003 ql_log(ql_log_info, vha, 0x8042, 1004 "PCI/Register disconnect, exiting.\n"); 1005 return FAILED; 1006 } 1007 if (!CMD_SP(cmd)) 1008 return SUCCESS; 1009 1010 ret = fc_block_scsi_eh(cmd); 1011 if (ret != 0) 1012 return ret; 1013 ret = SUCCESS; 1014 1015 id = cmd->device->id; 1016 lun = cmd->device->lun; 1017 1018 spin_lock_irqsave(&ha->hardware_lock, flags); 1019 sp = (srb_t *) CMD_SP(cmd); 1020 if (!sp) { 1021 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1022 return SUCCESS; 1023 } 1024 1025 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1026 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1027 vha->host_no, id, lun, sp, cmd, sp->handle); 1028 1029 /* Get a reference to the sp and drop the lock.*/ 1030 sp_get(sp); 1031 1032 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1033 rval = ha->isp_ops->abort_command(sp); 1034 if (rval) { 1035 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1036 ret = SUCCESS; 1037 else 1038 ret = FAILED; 1039 1040 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1041 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1042 } else { 1043 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1044 "Abort command mbx success cmd=%p.\n", cmd); 1045 wait = 1; 1046 } 1047 1048 spin_lock_irqsave(&ha->hardware_lock, flags); 1049 sp->done(ha, sp, 0); 1050 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1051 1052 /* Did the command return during mailbox execution? */ 1053 if (ret == FAILED && !CMD_SP(cmd)) 1054 ret = SUCCESS; 1055 1056 /* Wait for the command to be returned. */ 1057 if (wait) { 1058 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1059 ql_log(ql_log_warn, vha, 0x8006, 1060 "Abort handler timed out cmd=%p.\n", cmd); 1061 ret = FAILED; 1062 } 1063 } 1064 1065 ql_log(ql_log_info, vha, 0x801c, 1066 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1067 vha->host_no, id, lun, wait, ret); 1068 1069 return ret; 1070 } 1071 1072 int 1073 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1074 uint64_t l, enum nexus_wait_type type) 1075 { 1076 int cnt, match, status; 1077 unsigned long flags; 1078 struct qla_hw_data *ha = vha->hw; 1079 struct req_que *req; 1080 srb_t *sp; 1081 struct scsi_cmnd *cmd; 1082 1083 status = QLA_SUCCESS; 1084 1085 spin_lock_irqsave(&ha->hardware_lock, flags); 1086 req = vha->req; 1087 for (cnt = 1; status == QLA_SUCCESS && 1088 cnt < req->num_outstanding_cmds; cnt++) { 1089 sp = req->outstanding_cmds[cnt]; 1090 if (!sp) 1091 continue; 1092 if (sp->type != SRB_SCSI_CMD) 1093 continue; 1094 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1095 continue; 1096 match = 0; 1097 cmd = GET_CMD_SP(sp); 1098 switch (type) { 1099 case WAIT_HOST: 1100 match = 1; 1101 break; 1102 case WAIT_TARGET: 1103 match = cmd->device->id == t; 1104 break; 1105 case WAIT_LUN: 1106 match = (cmd->device->id == t && 1107 cmd->device->lun == l); 1108 break; 1109 } 1110 if (!match) 1111 continue; 1112 1113 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1114 status = qla2x00_eh_wait_on_command(cmd); 1115 spin_lock_irqsave(&ha->hardware_lock, flags); 1116 } 1117 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1118 1119 return status; 1120 } 1121 1122 static char *reset_errors[] = { 1123 "HBA not online", 1124 "HBA not ready", 1125 "Task management failed", 1126 "Waiting for command completions", 1127 }; 1128 1129 static int 1130 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1131 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1132 { 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1134 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1135 int err; 1136 1137 if (!fcport) { 1138 return FAILED; 1139 } 1140 1141 err = fc_block_scsi_eh(cmd); 1142 if (err != 0) 1143 return err; 1144 1145 ql_log(ql_log_info, vha, 0x8009, 1146 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1147 cmd->device->id, cmd->device->lun, cmd); 1148 1149 err = 0; 1150 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1151 ql_log(ql_log_warn, vha, 0x800a, 1152 "Wait for hba online failed for cmd=%p.\n", cmd); 1153 goto eh_reset_failed; 1154 } 1155 err = 2; 1156 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1157 != QLA_SUCCESS) { 1158 ql_log(ql_log_warn, vha, 0x800c, 1159 "do_reset failed for cmd=%p.\n", cmd); 1160 goto eh_reset_failed; 1161 } 1162 err = 3; 1163 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1164 cmd->device->lun, type) != QLA_SUCCESS) { 1165 ql_log(ql_log_warn, vha, 0x800d, 1166 "wait for pending cmds failed for cmd=%p.\n", cmd); 1167 goto eh_reset_failed; 1168 } 1169 1170 ql_log(ql_log_info, vha, 0x800e, 1171 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1172 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1173 1174 return SUCCESS; 1175 1176 eh_reset_failed: 1177 ql_log(ql_log_info, vha, 0x800f, 1178 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1179 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1180 cmd); 1181 return FAILED; 1182 } 1183 1184 static int 1185 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1186 { 1187 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1188 struct qla_hw_data *ha = vha->hw; 1189 1190 if (qla2x00_isp_reg_stat(ha)) { 1191 ql_log(ql_log_info, vha, 0x803e, 1192 "PCI/Register disconnect, exiting.\n"); 1193 return FAILED; 1194 } 1195 1196 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1197 ha->isp_ops->lun_reset); 1198 } 1199 1200 static int 1201 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1202 { 1203 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1204 struct qla_hw_data *ha = vha->hw; 1205 1206 if (qla2x00_isp_reg_stat(ha)) { 1207 ql_log(ql_log_info, vha, 0x803f, 1208 "PCI/Register disconnect, exiting.\n"); 1209 return FAILED; 1210 } 1211 1212 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1213 ha->isp_ops->target_reset); 1214 } 1215 1216 /************************************************************************** 1217 * qla2xxx_eh_bus_reset 1218 * 1219 * Description: 1220 * The bus reset function will reset the bus and abort any executing 1221 * commands. 1222 * 1223 * Input: 1224 * cmd = Linux SCSI command packet of the command that cause the 1225 * bus reset. 1226 * 1227 * Returns: 1228 * SUCCESS/FAILURE (defined as macro in scsi.h). 1229 * 1230 **************************************************************************/ 1231 static int 1232 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1233 { 1234 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1235 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1236 int ret = FAILED; 1237 unsigned int id; 1238 uint64_t lun; 1239 struct qla_hw_data *ha = vha->hw; 1240 1241 if (qla2x00_isp_reg_stat(ha)) { 1242 ql_log(ql_log_info, vha, 0x8040, 1243 "PCI/Register disconnect, exiting.\n"); 1244 return FAILED; 1245 } 1246 1247 id = cmd->device->id; 1248 lun = cmd->device->lun; 1249 1250 if (!fcport) { 1251 return ret; 1252 } 1253 1254 ret = fc_block_scsi_eh(cmd); 1255 if (ret != 0) 1256 return ret; 1257 ret = FAILED; 1258 1259 ql_log(ql_log_info, vha, 0x8012, 1260 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1261 1262 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1263 ql_log(ql_log_fatal, vha, 0x8013, 1264 "Wait for hba online failed board disabled.\n"); 1265 goto eh_bus_reset_done; 1266 } 1267 1268 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1269 ret = SUCCESS; 1270 1271 if (ret == FAILED) 1272 goto eh_bus_reset_done; 1273 1274 /* Flush outstanding commands. */ 1275 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1276 QLA_SUCCESS) { 1277 ql_log(ql_log_warn, vha, 0x8014, 1278 "Wait for pending commands failed.\n"); 1279 ret = FAILED; 1280 } 1281 1282 eh_bus_reset_done: 1283 ql_log(ql_log_warn, vha, 0x802b, 1284 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1285 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1286 1287 return ret; 1288 } 1289 1290 /************************************************************************** 1291 * qla2xxx_eh_host_reset 1292 * 1293 * Description: 1294 * The reset function will reset the Adapter. 1295 * 1296 * Input: 1297 * cmd = Linux SCSI command packet of the command that cause the 1298 * adapter reset. 1299 * 1300 * Returns: 1301 * Either SUCCESS or FAILED. 1302 * 1303 * Note: 1304 **************************************************************************/ 1305 static int 1306 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1307 { 1308 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1309 struct qla_hw_data *ha = vha->hw; 1310 int ret = FAILED; 1311 unsigned int id; 1312 uint64_t lun; 1313 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1314 1315 if (qla2x00_isp_reg_stat(ha)) { 1316 ql_log(ql_log_info, vha, 0x8041, 1317 "PCI/Register disconnect, exiting.\n"); 1318 schedule_work(&ha->board_disable); 1319 return SUCCESS; 1320 } 1321 1322 id = cmd->device->id; 1323 lun = cmd->device->lun; 1324 1325 ql_log(ql_log_info, vha, 0x8018, 1326 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1327 1328 /* 1329 * No point in issuing another reset if one is active. Also do not 1330 * attempt a reset if we are updating flash. 1331 */ 1332 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1333 goto eh_host_reset_lock; 1334 1335 if (vha != base_vha) { 1336 if (qla2x00_vp_abort_isp(vha)) 1337 goto eh_host_reset_lock; 1338 } else { 1339 if (IS_P3P_TYPE(vha->hw)) { 1340 if (!qla82xx_fcoe_ctx_reset(vha)) { 1341 /* Ctx reset success */ 1342 ret = SUCCESS; 1343 goto eh_host_reset_lock; 1344 } 1345 /* fall thru if ctx reset failed */ 1346 } 1347 if (ha->wq) 1348 flush_workqueue(ha->wq); 1349 1350 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1351 if (ha->isp_ops->abort_isp(base_vha)) { 1352 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1353 /* failed. schedule dpc to try */ 1354 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1355 1356 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1357 ql_log(ql_log_warn, vha, 0x802a, 1358 "wait for hba online failed.\n"); 1359 goto eh_host_reset_lock; 1360 } 1361 } 1362 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1363 } 1364 1365 /* Waiting for command to be returned to OS.*/ 1366 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1367 QLA_SUCCESS) 1368 ret = SUCCESS; 1369 1370 eh_host_reset_lock: 1371 ql_log(ql_log_info, vha, 0x8017, 1372 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1373 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1374 1375 return ret; 1376 } 1377 1378 /* 1379 * qla2x00_loop_reset 1380 * Issue loop reset. 1381 * 1382 * Input: 1383 * ha = adapter block pointer. 1384 * 1385 * Returns: 1386 * 0 = success 1387 */ 1388 int 1389 qla2x00_loop_reset(scsi_qla_host_t *vha) 1390 { 1391 int ret; 1392 struct fc_port *fcport; 1393 struct qla_hw_data *ha = vha->hw; 1394 1395 if (IS_QLAFX00(ha)) { 1396 return qlafx00_loop_reset(vha); 1397 } 1398 1399 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1400 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1401 if (fcport->port_type != FCT_TARGET) 1402 continue; 1403 1404 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1405 if (ret != QLA_SUCCESS) { 1406 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1407 "Bus Reset failed: Reset=%d " 1408 "d_id=%x.\n", ret, fcport->d_id.b24); 1409 } 1410 } 1411 } 1412 1413 1414 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1415 atomic_set(&vha->loop_state, LOOP_DOWN); 1416 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1417 qla2x00_mark_all_devices_lost(vha, 0); 1418 ret = qla2x00_full_login_lip(vha); 1419 if (ret != QLA_SUCCESS) { 1420 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1421 "full_login_lip=%d.\n", ret); 1422 } 1423 } 1424 1425 if (ha->flags.enable_lip_reset) { 1426 ret = qla2x00_lip_reset(vha); 1427 if (ret != QLA_SUCCESS) 1428 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1429 "lip_reset failed (%d).\n", ret); 1430 } 1431 1432 /* Issue marker command only when we are going to start the I/O */ 1433 vha->marker_needed = 1; 1434 1435 return QLA_SUCCESS; 1436 } 1437 1438 void 1439 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1440 { 1441 int que, cnt; 1442 unsigned long flags; 1443 srb_t *sp; 1444 struct qla_hw_data *ha = vha->hw; 1445 struct req_que *req; 1446 1447 qlt_host_reset_handler(ha); 1448 1449 spin_lock_irqsave(&ha->hardware_lock, flags); 1450 for (que = 0; que < ha->max_req_queues; que++) { 1451 req = ha->req_q_map[que]; 1452 if (!req) 1453 continue; 1454 if (!req->outstanding_cmds) 1455 continue; 1456 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1457 sp = req->outstanding_cmds[cnt]; 1458 if (sp) { 1459 /* Get a reference to the sp and drop the lock. 1460 * The reference ensures this sp->done() call 1461 * - and not the call in qla2xxx_eh_abort() - 1462 * ends the SCSI command (with result 'res'). 1463 */ 1464 sp_get(sp); 1465 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1466 qla2xxx_eh_abort(GET_CMD_SP(sp)); 1467 spin_lock_irqsave(&ha->hardware_lock, flags); 1468 req->outstanding_cmds[cnt] = NULL; 1469 sp->done(vha, sp, res); 1470 } 1471 } 1472 } 1473 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1474 } 1475 1476 static int 1477 qla2xxx_slave_alloc(struct scsi_device *sdev) 1478 { 1479 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1480 1481 if (!rport || fc_remote_port_chkready(rport)) 1482 return -ENXIO; 1483 1484 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1485 1486 return 0; 1487 } 1488 1489 static int 1490 qla2xxx_slave_configure(struct scsi_device *sdev) 1491 { 1492 scsi_qla_host_t *vha = shost_priv(sdev->host); 1493 struct req_que *req = vha->req; 1494 1495 if (IS_T10_PI_CAPABLE(vha->hw)) 1496 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1497 1498 scsi_change_queue_depth(sdev, req->max_q_depth); 1499 return 0; 1500 } 1501 1502 static void 1503 qla2xxx_slave_destroy(struct scsi_device *sdev) 1504 { 1505 sdev->hostdata = NULL; 1506 } 1507 1508 /** 1509 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1510 * @ha: HA context 1511 * 1512 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1513 * supported addressing method. 1514 */ 1515 static void 1516 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1517 { 1518 /* Assume a 32bit DMA mask. */ 1519 ha->flags.enable_64bit_addressing = 0; 1520 1521 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1522 /* Any upper-dword bits set? */ 1523 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1524 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1525 /* Ok, a 64bit DMA mask is applicable. */ 1526 ha->flags.enable_64bit_addressing = 1; 1527 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1528 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1529 return; 1530 } 1531 } 1532 1533 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1534 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1535 } 1536 1537 static void 1538 qla2x00_enable_intrs(struct qla_hw_data *ha) 1539 { 1540 unsigned long flags = 0; 1541 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1542 1543 spin_lock_irqsave(&ha->hardware_lock, flags); 1544 ha->interrupts_on = 1; 1545 /* enable risc and host interrupts */ 1546 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1547 RD_REG_WORD(®->ictrl); 1548 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1549 1550 } 1551 1552 static void 1553 qla2x00_disable_intrs(struct qla_hw_data *ha) 1554 { 1555 unsigned long flags = 0; 1556 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1557 1558 spin_lock_irqsave(&ha->hardware_lock, flags); 1559 ha->interrupts_on = 0; 1560 /* disable risc and host interrupts */ 1561 WRT_REG_WORD(®->ictrl, 0); 1562 RD_REG_WORD(®->ictrl); 1563 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1564 } 1565 1566 static void 1567 qla24xx_enable_intrs(struct qla_hw_data *ha) 1568 { 1569 unsigned long flags = 0; 1570 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1571 1572 spin_lock_irqsave(&ha->hardware_lock, flags); 1573 ha->interrupts_on = 1; 1574 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1575 RD_REG_DWORD(®->ictrl); 1576 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1577 } 1578 1579 static void 1580 qla24xx_disable_intrs(struct qla_hw_data *ha) 1581 { 1582 unsigned long flags = 0; 1583 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1584 1585 if (IS_NOPOLLING_TYPE(ha)) 1586 return; 1587 spin_lock_irqsave(&ha->hardware_lock, flags); 1588 ha->interrupts_on = 0; 1589 WRT_REG_DWORD(®->ictrl, 0); 1590 RD_REG_DWORD(®->ictrl); 1591 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1592 } 1593 1594 static int 1595 qla2x00_iospace_config(struct qla_hw_data *ha) 1596 { 1597 resource_size_t pio; 1598 uint16_t msix; 1599 int cpus; 1600 1601 if (pci_request_selected_regions(ha->pdev, ha->bars, 1602 QLA2XXX_DRIVER_NAME)) { 1603 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1604 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1605 pci_name(ha->pdev)); 1606 goto iospace_error_exit; 1607 } 1608 if (!(ha->bars & 1)) 1609 goto skip_pio; 1610 1611 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1612 pio = pci_resource_start(ha->pdev, 0); 1613 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1614 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1615 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1616 "Invalid pci I/O region size (%s).\n", 1617 pci_name(ha->pdev)); 1618 pio = 0; 1619 } 1620 } else { 1621 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1622 "Region #0 no a PIO resource (%s).\n", 1623 pci_name(ha->pdev)); 1624 pio = 0; 1625 } 1626 ha->pio_address = pio; 1627 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1628 "PIO address=%llu.\n", 1629 (unsigned long long)ha->pio_address); 1630 1631 skip_pio: 1632 /* Use MMIO operations for all accesses. */ 1633 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1634 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1635 "Region #1 not an MMIO resource (%s), aborting.\n", 1636 pci_name(ha->pdev)); 1637 goto iospace_error_exit; 1638 } 1639 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1640 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1641 "Invalid PCI mem region size (%s), aborting.\n", 1642 pci_name(ha->pdev)); 1643 goto iospace_error_exit; 1644 } 1645 1646 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1647 if (!ha->iobase) { 1648 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1649 "Cannot remap MMIO (%s), aborting.\n", 1650 pci_name(ha->pdev)); 1651 goto iospace_error_exit; 1652 } 1653 1654 /* Determine queue resources */ 1655 ha->max_req_queues = ha->max_rsp_queues = 1; 1656 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1657 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1658 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1659 goto mqiobase_exit; 1660 1661 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1662 pci_resource_len(ha->pdev, 3)); 1663 if (ha->mqiobase) { 1664 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1665 "MQIO Base=%p.\n", ha->mqiobase); 1666 /* Read MSIX vector size of the board */ 1667 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1668 ha->msix_count = msix; 1669 /* Max queues are bounded by available msix vectors */ 1670 /* queue 0 uses two msix vectors */ 1671 if (ql2xmultique_tag) { 1672 cpus = num_online_cpus(); 1673 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1674 (cpus + 1) : (ha->msix_count - 1); 1675 ha->max_req_queues = 2; 1676 } else if (ql2xmaxqueues > 1) { 1677 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1678 QLA_MQ_SIZE : ql2xmaxqueues; 1679 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1680 "QoS mode set, max no of request queues:%d.\n", 1681 ha->max_req_queues); 1682 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1683 "QoS mode set, max no of request queues:%d.\n", 1684 ha->max_req_queues); 1685 } 1686 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1687 "MSI-X vector count: %d.\n", msix); 1688 } else 1689 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1690 "BAR 3 not enabled.\n"); 1691 1692 mqiobase_exit: 1693 ha->msix_count = ha->max_rsp_queues + 1; 1694 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1695 "MSIX Count:%d.\n", ha->msix_count); 1696 return (0); 1697 1698 iospace_error_exit: 1699 return (-ENOMEM); 1700 } 1701 1702 1703 static int 1704 qla83xx_iospace_config(struct qla_hw_data *ha) 1705 { 1706 uint16_t msix; 1707 int cpus; 1708 1709 if (pci_request_selected_regions(ha->pdev, ha->bars, 1710 QLA2XXX_DRIVER_NAME)) { 1711 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1712 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1713 pci_name(ha->pdev)); 1714 1715 goto iospace_error_exit; 1716 } 1717 1718 /* Use MMIO operations for all accesses. */ 1719 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1720 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1721 "Invalid pci I/O region size (%s).\n", 1722 pci_name(ha->pdev)); 1723 goto iospace_error_exit; 1724 } 1725 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1726 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1727 "Invalid PCI mem region size (%s), aborting\n", 1728 pci_name(ha->pdev)); 1729 goto iospace_error_exit; 1730 } 1731 1732 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1733 if (!ha->iobase) { 1734 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1735 "Cannot remap MMIO (%s), aborting.\n", 1736 pci_name(ha->pdev)); 1737 goto iospace_error_exit; 1738 } 1739 1740 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1741 /* 83XX 26XX always use MQ type access for queues 1742 * - mbar 2, a.k.a region 4 */ 1743 ha->max_req_queues = ha->max_rsp_queues = 1; 1744 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1745 pci_resource_len(ha->pdev, 4)); 1746 1747 if (!ha->mqiobase) { 1748 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1749 "BAR2/region4 not enabled\n"); 1750 goto mqiobase_exit; 1751 } 1752 1753 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1754 pci_resource_len(ha->pdev, 2)); 1755 if (ha->msixbase) { 1756 /* Read MSIX vector size of the board */ 1757 pci_read_config_word(ha->pdev, 1758 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1759 ha->msix_count = msix; 1760 /* Max queues are bounded by available msix vectors */ 1761 /* queue 0 uses two msix vectors */ 1762 if (ql2xmultique_tag) { 1763 cpus = num_online_cpus(); 1764 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1765 (cpus + 1) : (ha->msix_count - 1); 1766 ha->max_req_queues = 2; 1767 } else if (ql2xmaxqueues > 1) { 1768 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1769 QLA_MQ_SIZE : ql2xmaxqueues; 1770 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1771 "QoS mode set, max no of request queues:%d.\n", 1772 ha->max_req_queues); 1773 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1774 "QoS mode set, max no of request queues:%d.\n", 1775 ha->max_req_queues); 1776 } 1777 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1778 "MSI-X vector count: %d.\n", msix); 1779 } else 1780 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1781 "BAR 1 not enabled.\n"); 1782 1783 mqiobase_exit: 1784 ha->msix_count = ha->max_rsp_queues + 1; 1785 1786 qlt_83xx_iospace_config(ha); 1787 1788 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1789 "MSIX Count:%d.\n", ha->msix_count); 1790 return 0; 1791 1792 iospace_error_exit: 1793 return -ENOMEM; 1794 } 1795 1796 static struct isp_operations qla2100_isp_ops = { 1797 .pci_config = qla2100_pci_config, 1798 .reset_chip = qla2x00_reset_chip, 1799 .chip_diag = qla2x00_chip_diag, 1800 .config_rings = qla2x00_config_rings, 1801 .reset_adapter = qla2x00_reset_adapter, 1802 .nvram_config = qla2x00_nvram_config, 1803 .update_fw_options = qla2x00_update_fw_options, 1804 .load_risc = qla2x00_load_risc, 1805 .pci_info_str = qla2x00_pci_info_str, 1806 .fw_version_str = qla2x00_fw_version_str, 1807 .intr_handler = qla2100_intr_handler, 1808 .enable_intrs = qla2x00_enable_intrs, 1809 .disable_intrs = qla2x00_disable_intrs, 1810 .abort_command = qla2x00_abort_command, 1811 .target_reset = qla2x00_abort_target, 1812 .lun_reset = qla2x00_lun_reset, 1813 .fabric_login = qla2x00_login_fabric, 1814 .fabric_logout = qla2x00_fabric_logout, 1815 .calc_req_entries = qla2x00_calc_iocbs_32, 1816 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1817 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1818 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1819 .read_nvram = qla2x00_read_nvram_data, 1820 .write_nvram = qla2x00_write_nvram_data, 1821 .fw_dump = qla2100_fw_dump, 1822 .beacon_on = NULL, 1823 .beacon_off = NULL, 1824 .beacon_blink = NULL, 1825 .read_optrom = qla2x00_read_optrom_data, 1826 .write_optrom = qla2x00_write_optrom_data, 1827 .get_flash_version = qla2x00_get_flash_version, 1828 .start_scsi = qla2x00_start_scsi, 1829 .abort_isp = qla2x00_abort_isp, 1830 .iospace_config = qla2x00_iospace_config, 1831 .initialize_adapter = qla2x00_initialize_adapter, 1832 }; 1833 1834 static struct isp_operations qla2300_isp_ops = { 1835 .pci_config = qla2300_pci_config, 1836 .reset_chip = qla2x00_reset_chip, 1837 .chip_diag = qla2x00_chip_diag, 1838 .config_rings = qla2x00_config_rings, 1839 .reset_adapter = qla2x00_reset_adapter, 1840 .nvram_config = qla2x00_nvram_config, 1841 .update_fw_options = qla2x00_update_fw_options, 1842 .load_risc = qla2x00_load_risc, 1843 .pci_info_str = qla2x00_pci_info_str, 1844 .fw_version_str = qla2x00_fw_version_str, 1845 .intr_handler = qla2300_intr_handler, 1846 .enable_intrs = qla2x00_enable_intrs, 1847 .disable_intrs = qla2x00_disable_intrs, 1848 .abort_command = qla2x00_abort_command, 1849 .target_reset = qla2x00_abort_target, 1850 .lun_reset = qla2x00_lun_reset, 1851 .fabric_login = qla2x00_login_fabric, 1852 .fabric_logout = qla2x00_fabric_logout, 1853 .calc_req_entries = qla2x00_calc_iocbs_32, 1854 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1855 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1856 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1857 .read_nvram = qla2x00_read_nvram_data, 1858 .write_nvram = qla2x00_write_nvram_data, 1859 .fw_dump = qla2300_fw_dump, 1860 .beacon_on = qla2x00_beacon_on, 1861 .beacon_off = qla2x00_beacon_off, 1862 .beacon_blink = qla2x00_beacon_blink, 1863 .read_optrom = qla2x00_read_optrom_data, 1864 .write_optrom = qla2x00_write_optrom_data, 1865 .get_flash_version = qla2x00_get_flash_version, 1866 .start_scsi = qla2x00_start_scsi, 1867 .abort_isp = qla2x00_abort_isp, 1868 .iospace_config = qla2x00_iospace_config, 1869 .initialize_adapter = qla2x00_initialize_adapter, 1870 }; 1871 1872 static struct isp_operations qla24xx_isp_ops = { 1873 .pci_config = qla24xx_pci_config, 1874 .reset_chip = qla24xx_reset_chip, 1875 .chip_diag = qla24xx_chip_diag, 1876 .config_rings = qla24xx_config_rings, 1877 .reset_adapter = qla24xx_reset_adapter, 1878 .nvram_config = qla24xx_nvram_config, 1879 .update_fw_options = qla24xx_update_fw_options, 1880 .load_risc = qla24xx_load_risc, 1881 .pci_info_str = qla24xx_pci_info_str, 1882 .fw_version_str = qla24xx_fw_version_str, 1883 .intr_handler = qla24xx_intr_handler, 1884 .enable_intrs = qla24xx_enable_intrs, 1885 .disable_intrs = qla24xx_disable_intrs, 1886 .abort_command = qla24xx_abort_command, 1887 .target_reset = qla24xx_abort_target, 1888 .lun_reset = qla24xx_lun_reset, 1889 .fabric_login = qla24xx_login_fabric, 1890 .fabric_logout = qla24xx_fabric_logout, 1891 .calc_req_entries = NULL, 1892 .build_iocbs = NULL, 1893 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1894 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1895 .read_nvram = qla24xx_read_nvram_data, 1896 .write_nvram = qla24xx_write_nvram_data, 1897 .fw_dump = qla24xx_fw_dump, 1898 .beacon_on = qla24xx_beacon_on, 1899 .beacon_off = qla24xx_beacon_off, 1900 .beacon_blink = qla24xx_beacon_blink, 1901 .read_optrom = qla24xx_read_optrom_data, 1902 .write_optrom = qla24xx_write_optrom_data, 1903 .get_flash_version = qla24xx_get_flash_version, 1904 .start_scsi = qla24xx_start_scsi, 1905 .abort_isp = qla2x00_abort_isp, 1906 .iospace_config = qla2x00_iospace_config, 1907 .initialize_adapter = qla2x00_initialize_adapter, 1908 }; 1909 1910 static struct isp_operations qla25xx_isp_ops = { 1911 .pci_config = qla25xx_pci_config, 1912 .reset_chip = qla24xx_reset_chip, 1913 .chip_diag = qla24xx_chip_diag, 1914 .config_rings = qla24xx_config_rings, 1915 .reset_adapter = qla24xx_reset_adapter, 1916 .nvram_config = qla24xx_nvram_config, 1917 .update_fw_options = qla24xx_update_fw_options, 1918 .load_risc = qla24xx_load_risc, 1919 .pci_info_str = qla24xx_pci_info_str, 1920 .fw_version_str = qla24xx_fw_version_str, 1921 .intr_handler = qla24xx_intr_handler, 1922 .enable_intrs = qla24xx_enable_intrs, 1923 .disable_intrs = qla24xx_disable_intrs, 1924 .abort_command = qla24xx_abort_command, 1925 .target_reset = qla24xx_abort_target, 1926 .lun_reset = qla24xx_lun_reset, 1927 .fabric_login = qla24xx_login_fabric, 1928 .fabric_logout = qla24xx_fabric_logout, 1929 .calc_req_entries = NULL, 1930 .build_iocbs = NULL, 1931 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1932 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1933 .read_nvram = qla25xx_read_nvram_data, 1934 .write_nvram = qla25xx_write_nvram_data, 1935 .fw_dump = qla25xx_fw_dump, 1936 .beacon_on = qla24xx_beacon_on, 1937 .beacon_off = qla24xx_beacon_off, 1938 .beacon_blink = qla24xx_beacon_blink, 1939 .read_optrom = qla25xx_read_optrom_data, 1940 .write_optrom = qla24xx_write_optrom_data, 1941 .get_flash_version = qla24xx_get_flash_version, 1942 .start_scsi = qla24xx_dif_start_scsi, 1943 .abort_isp = qla2x00_abort_isp, 1944 .iospace_config = qla2x00_iospace_config, 1945 .initialize_adapter = qla2x00_initialize_adapter, 1946 }; 1947 1948 static struct isp_operations qla81xx_isp_ops = { 1949 .pci_config = qla25xx_pci_config, 1950 .reset_chip = qla24xx_reset_chip, 1951 .chip_diag = qla24xx_chip_diag, 1952 .config_rings = qla24xx_config_rings, 1953 .reset_adapter = qla24xx_reset_adapter, 1954 .nvram_config = qla81xx_nvram_config, 1955 .update_fw_options = qla81xx_update_fw_options, 1956 .load_risc = qla81xx_load_risc, 1957 .pci_info_str = qla24xx_pci_info_str, 1958 .fw_version_str = qla24xx_fw_version_str, 1959 .intr_handler = qla24xx_intr_handler, 1960 .enable_intrs = qla24xx_enable_intrs, 1961 .disable_intrs = qla24xx_disable_intrs, 1962 .abort_command = qla24xx_abort_command, 1963 .target_reset = qla24xx_abort_target, 1964 .lun_reset = qla24xx_lun_reset, 1965 .fabric_login = qla24xx_login_fabric, 1966 .fabric_logout = qla24xx_fabric_logout, 1967 .calc_req_entries = NULL, 1968 .build_iocbs = NULL, 1969 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1970 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1971 .read_nvram = NULL, 1972 .write_nvram = NULL, 1973 .fw_dump = qla81xx_fw_dump, 1974 .beacon_on = qla24xx_beacon_on, 1975 .beacon_off = qla24xx_beacon_off, 1976 .beacon_blink = qla83xx_beacon_blink, 1977 .read_optrom = qla25xx_read_optrom_data, 1978 .write_optrom = qla24xx_write_optrom_data, 1979 .get_flash_version = qla24xx_get_flash_version, 1980 .start_scsi = qla24xx_dif_start_scsi, 1981 .abort_isp = qla2x00_abort_isp, 1982 .iospace_config = qla2x00_iospace_config, 1983 .initialize_adapter = qla2x00_initialize_adapter, 1984 }; 1985 1986 static struct isp_operations qla82xx_isp_ops = { 1987 .pci_config = qla82xx_pci_config, 1988 .reset_chip = qla82xx_reset_chip, 1989 .chip_diag = qla24xx_chip_diag, 1990 .config_rings = qla82xx_config_rings, 1991 .reset_adapter = qla24xx_reset_adapter, 1992 .nvram_config = qla81xx_nvram_config, 1993 .update_fw_options = qla24xx_update_fw_options, 1994 .load_risc = qla82xx_load_risc, 1995 .pci_info_str = qla24xx_pci_info_str, 1996 .fw_version_str = qla24xx_fw_version_str, 1997 .intr_handler = qla82xx_intr_handler, 1998 .enable_intrs = qla82xx_enable_intrs, 1999 .disable_intrs = qla82xx_disable_intrs, 2000 .abort_command = qla24xx_abort_command, 2001 .target_reset = qla24xx_abort_target, 2002 .lun_reset = qla24xx_lun_reset, 2003 .fabric_login = qla24xx_login_fabric, 2004 .fabric_logout = qla24xx_fabric_logout, 2005 .calc_req_entries = NULL, 2006 .build_iocbs = NULL, 2007 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2008 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2009 .read_nvram = qla24xx_read_nvram_data, 2010 .write_nvram = qla24xx_write_nvram_data, 2011 .fw_dump = qla82xx_fw_dump, 2012 .beacon_on = qla82xx_beacon_on, 2013 .beacon_off = qla82xx_beacon_off, 2014 .beacon_blink = NULL, 2015 .read_optrom = qla82xx_read_optrom_data, 2016 .write_optrom = qla82xx_write_optrom_data, 2017 .get_flash_version = qla82xx_get_flash_version, 2018 .start_scsi = qla82xx_start_scsi, 2019 .abort_isp = qla82xx_abort_isp, 2020 .iospace_config = qla82xx_iospace_config, 2021 .initialize_adapter = qla2x00_initialize_adapter, 2022 }; 2023 2024 static struct isp_operations qla8044_isp_ops = { 2025 .pci_config = qla82xx_pci_config, 2026 .reset_chip = qla82xx_reset_chip, 2027 .chip_diag = qla24xx_chip_diag, 2028 .config_rings = qla82xx_config_rings, 2029 .reset_adapter = qla24xx_reset_adapter, 2030 .nvram_config = qla81xx_nvram_config, 2031 .update_fw_options = qla24xx_update_fw_options, 2032 .load_risc = qla82xx_load_risc, 2033 .pci_info_str = qla24xx_pci_info_str, 2034 .fw_version_str = qla24xx_fw_version_str, 2035 .intr_handler = qla8044_intr_handler, 2036 .enable_intrs = qla82xx_enable_intrs, 2037 .disable_intrs = qla82xx_disable_intrs, 2038 .abort_command = qla24xx_abort_command, 2039 .target_reset = qla24xx_abort_target, 2040 .lun_reset = qla24xx_lun_reset, 2041 .fabric_login = qla24xx_login_fabric, 2042 .fabric_logout = qla24xx_fabric_logout, 2043 .calc_req_entries = NULL, 2044 .build_iocbs = NULL, 2045 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2046 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2047 .read_nvram = NULL, 2048 .write_nvram = NULL, 2049 .fw_dump = qla8044_fw_dump, 2050 .beacon_on = qla82xx_beacon_on, 2051 .beacon_off = qla82xx_beacon_off, 2052 .beacon_blink = NULL, 2053 .read_optrom = qla8044_read_optrom_data, 2054 .write_optrom = qla8044_write_optrom_data, 2055 .get_flash_version = qla82xx_get_flash_version, 2056 .start_scsi = qla82xx_start_scsi, 2057 .abort_isp = qla8044_abort_isp, 2058 .iospace_config = qla82xx_iospace_config, 2059 .initialize_adapter = qla2x00_initialize_adapter, 2060 }; 2061 2062 static struct isp_operations qla83xx_isp_ops = { 2063 .pci_config = qla25xx_pci_config, 2064 .reset_chip = qla24xx_reset_chip, 2065 .chip_diag = qla24xx_chip_diag, 2066 .config_rings = qla24xx_config_rings, 2067 .reset_adapter = qla24xx_reset_adapter, 2068 .nvram_config = qla81xx_nvram_config, 2069 .update_fw_options = qla81xx_update_fw_options, 2070 .load_risc = qla81xx_load_risc, 2071 .pci_info_str = qla24xx_pci_info_str, 2072 .fw_version_str = qla24xx_fw_version_str, 2073 .intr_handler = qla24xx_intr_handler, 2074 .enable_intrs = qla24xx_enable_intrs, 2075 .disable_intrs = qla24xx_disable_intrs, 2076 .abort_command = qla24xx_abort_command, 2077 .target_reset = qla24xx_abort_target, 2078 .lun_reset = qla24xx_lun_reset, 2079 .fabric_login = qla24xx_login_fabric, 2080 .fabric_logout = qla24xx_fabric_logout, 2081 .calc_req_entries = NULL, 2082 .build_iocbs = NULL, 2083 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2084 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2085 .read_nvram = NULL, 2086 .write_nvram = NULL, 2087 .fw_dump = qla83xx_fw_dump, 2088 .beacon_on = qla24xx_beacon_on, 2089 .beacon_off = qla24xx_beacon_off, 2090 .beacon_blink = qla83xx_beacon_blink, 2091 .read_optrom = qla25xx_read_optrom_data, 2092 .write_optrom = qla24xx_write_optrom_data, 2093 .get_flash_version = qla24xx_get_flash_version, 2094 .start_scsi = qla24xx_dif_start_scsi, 2095 .abort_isp = qla2x00_abort_isp, 2096 .iospace_config = qla83xx_iospace_config, 2097 .initialize_adapter = qla2x00_initialize_adapter, 2098 }; 2099 2100 static struct isp_operations qlafx00_isp_ops = { 2101 .pci_config = qlafx00_pci_config, 2102 .reset_chip = qlafx00_soft_reset, 2103 .chip_diag = qlafx00_chip_diag, 2104 .config_rings = qlafx00_config_rings, 2105 .reset_adapter = qlafx00_soft_reset, 2106 .nvram_config = NULL, 2107 .update_fw_options = NULL, 2108 .load_risc = NULL, 2109 .pci_info_str = qlafx00_pci_info_str, 2110 .fw_version_str = qlafx00_fw_version_str, 2111 .intr_handler = qlafx00_intr_handler, 2112 .enable_intrs = qlafx00_enable_intrs, 2113 .disable_intrs = qlafx00_disable_intrs, 2114 .abort_command = qla24xx_async_abort_command, 2115 .target_reset = qlafx00_abort_target, 2116 .lun_reset = qlafx00_lun_reset, 2117 .fabric_login = NULL, 2118 .fabric_logout = NULL, 2119 .calc_req_entries = NULL, 2120 .build_iocbs = NULL, 2121 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2122 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2123 .read_nvram = qla24xx_read_nvram_data, 2124 .write_nvram = qla24xx_write_nvram_data, 2125 .fw_dump = NULL, 2126 .beacon_on = qla24xx_beacon_on, 2127 .beacon_off = qla24xx_beacon_off, 2128 .beacon_blink = NULL, 2129 .read_optrom = qla24xx_read_optrom_data, 2130 .write_optrom = qla24xx_write_optrom_data, 2131 .get_flash_version = qla24xx_get_flash_version, 2132 .start_scsi = qlafx00_start_scsi, 2133 .abort_isp = qlafx00_abort_isp, 2134 .iospace_config = qlafx00_iospace_config, 2135 .initialize_adapter = qlafx00_initialize_adapter, 2136 }; 2137 2138 static struct isp_operations qla27xx_isp_ops = { 2139 .pci_config = qla25xx_pci_config, 2140 .reset_chip = qla24xx_reset_chip, 2141 .chip_diag = qla24xx_chip_diag, 2142 .config_rings = qla24xx_config_rings, 2143 .reset_adapter = qla24xx_reset_adapter, 2144 .nvram_config = qla81xx_nvram_config, 2145 .update_fw_options = qla81xx_update_fw_options, 2146 .load_risc = qla81xx_load_risc, 2147 .pci_info_str = qla24xx_pci_info_str, 2148 .fw_version_str = qla24xx_fw_version_str, 2149 .intr_handler = qla24xx_intr_handler, 2150 .enable_intrs = qla24xx_enable_intrs, 2151 .disable_intrs = qla24xx_disable_intrs, 2152 .abort_command = qla24xx_abort_command, 2153 .target_reset = qla24xx_abort_target, 2154 .lun_reset = qla24xx_lun_reset, 2155 .fabric_login = qla24xx_login_fabric, 2156 .fabric_logout = qla24xx_fabric_logout, 2157 .calc_req_entries = NULL, 2158 .build_iocbs = NULL, 2159 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2160 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2161 .read_nvram = NULL, 2162 .write_nvram = NULL, 2163 .fw_dump = qla27xx_fwdump, 2164 .beacon_on = qla24xx_beacon_on, 2165 .beacon_off = qla24xx_beacon_off, 2166 .beacon_blink = qla83xx_beacon_blink, 2167 .read_optrom = qla25xx_read_optrom_data, 2168 .write_optrom = qla24xx_write_optrom_data, 2169 .get_flash_version = qla24xx_get_flash_version, 2170 .start_scsi = qla24xx_dif_start_scsi, 2171 .abort_isp = qla2x00_abort_isp, 2172 .iospace_config = qla83xx_iospace_config, 2173 .initialize_adapter = qla2x00_initialize_adapter, 2174 }; 2175 2176 static inline void 2177 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2178 { 2179 ha->device_type = DT_EXTENDED_IDS; 2180 switch (ha->pdev->device) { 2181 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2182 ha->isp_type |= DT_ISP2100; 2183 ha->device_type &= ~DT_EXTENDED_IDS; 2184 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2185 break; 2186 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2187 ha->isp_type |= DT_ISP2200; 2188 ha->device_type &= ~DT_EXTENDED_IDS; 2189 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2190 break; 2191 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2192 ha->isp_type |= DT_ISP2300; 2193 ha->device_type |= DT_ZIO_SUPPORTED; 2194 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2195 break; 2196 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2197 ha->isp_type |= DT_ISP2312; 2198 ha->device_type |= DT_ZIO_SUPPORTED; 2199 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2200 break; 2201 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2202 ha->isp_type |= DT_ISP2322; 2203 ha->device_type |= DT_ZIO_SUPPORTED; 2204 if (ha->pdev->subsystem_vendor == 0x1028 && 2205 ha->pdev->subsystem_device == 0x0170) 2206 ha->device_type |= DT_OEM_001; 2207 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2208 break; 2209 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2210 ha->isp_type |= DT_ISP6312; 2211 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2212 break; 2213 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2214 ha->isp_type |= DT_ISP6322; 2215 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2216 break; 2217 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2218 ha->isp_type |= DT_ISP2422; 2219 ha->device_type |= DT_ZIO_SUPPORTED; 2220 ha->device_type |= DT_FWI2; 2221 ha->device_type |= DT_IIDMA; 2222 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2223 break; 2224 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2225 ha->isp_type |= DT_ISP2432; 2226 ha->device_type |= DT_ZIO_SUPPORTED; 2227 ha->device_type |= DT_FWI2; 2228 ha->device_type |= DT_IIDMA; 2229 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2230 break; 2231 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2232 ha->isp_type |= DT_ISP8432; 2233 ha->device_type |= DT_ZIO_SUPPORTED; 2234 ha->device_type |= DT_FWI2; 2235 ha->device_type |= DT_IIDMA; 2236 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2237 break; 2238 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2239 ha->isp_type |= DT_ISP5422; 2240 ha->device_type |= DT_FWI2; 2241 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2242 break; 2243 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2244 ha->isp_type |= DT_ISP5432; 2245 ha->device_type |= DT_FWI2; 2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2247 break; 2248 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2249 ha->isp_type |= DT_ISP2532; 2250 ha->device_type |= DT_ZIO_SUPPORTED; 2251 ha->device_type |= DT_FWI2; 2252 ha->device_type |= DT_IIDMA; 2253 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2254 break; 2255 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2256 ha->isp_type |= DT_ISP8001; 2257 ha->device_type |= DT_ZIO_SUPPORTED; 2258 ha->device_type |= DT_FWI2; 2259 ha->device_type |= DT_IIDMA; 2260 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2261 break; 2262 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2263 ha->isp_type |= DT_ISP8021; 2264 ha->device_type |= DT_ZIO_SUPPORTED; 2265 ha->device_type |= DT_FWI2; 2266 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2267 /* Initialize 82XX ISP flags */ 2268 qla82xx_init_flags(ha); 2269 break; 2270 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2271 ha->isp_type |= DT_ISP8044; 2272 ha->device_type |= DT_ZIO_SUPPORTED; 2273 ha->device_type |= DT_FWI2; 2274 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2275 /* Initialize 82XX ISP flags */ 2276 qla82xx_init_flags(ha); 2277 break; 2278 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2279 ha->isp_type |= DT_ISP2031; 2280 ha->device_type |= DT_ZIO_SUPPORTED; 2281 ha->device_type |= DT_FWI2; 2282 ha->device_type |= DT_IIDMA; 2283 ha->device_type |= DT_T10_PI; 2284 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2285 break; 2286 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2287 ha->isp_type |= DT_ISP8031; 2288 ha->device_type |= DT_ZIO_SUPPORTED; 2289 ha->device_type |= DT_FWI2; 2290 ha->device_type |= DT_IIDMA; 2291 ha->device_type |= DT_T10_PI; 2292 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2293 break; 2294 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2295 ha->isp_type |= DT_ISPFX00; 2296 break; 2297 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2298 ha->isp_type |= DT_ISP2071; 2299 ha->device_type |= DT_ZIO_SUPPORTED; 2300 ha->device_type |= DT_FWI2; 2301 ha->device_type |= DT_IIDMA; 2302 ha->device_type |= DT_T10_PI; 2303 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2304 break; 2305 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2306 ha->isp_type |= DT_ISP2271; 2307 ha->device_type |= DT_ZIO_SUPPORTED; 2308 ha->device_type |= DT_FWI2; 2309 ha->device_type |= DT_IIDMA; 2310 ha->device_type |= DT_T10_PI; 2311 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2312 break; 2313 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2314 ha->isp_type |= DT_ISP2261; 2315 ha->device_type |= DT_ZIO_SUPPORTED; 2316 ha->device_type |= DT_FWI2; 2317 ha->device_type |= DT_IIDMA; 2318 ha->device_type |= DT_T10_PI; 2319 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2320 break; 2321 } 2322 2323 if (IS_QLA82XX(ha)) 2324 ha->port_no = ha->portnum & 1; 2325 else { 2326 /* Get adapter physical port no from interrupt pin register. */ 2327 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2328 if (IS_QLA27XX(ha)) 2329 ha->port_no--; 2330 else 2331 ha->port_no = !(ha->port_no & 1); 2332 } 2333 2334 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2335 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2336 ha->device_type, ha->port_no, ha->fw_srisc_address); 2337 } 2338 2339 static void 2340 qla2xxx_scan_start(struct Scsi_Host *shost) 2341 { 2342 scsi_qla_host_t *vha = shost_priv(shost); 2343 2344 if (vha->hw->flags.running_gold_fw) 2345 return; 2346 2347 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2348 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2349 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2350 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2351 } 2352 2353 static int 2354 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2355 { 2356 scsi_qla_host_t *vha = shost_priv(shost); 2357 2358 if (test_bit(UNLOADING, &vha->dpc_flags)) 2359 return 1; 2360 if (!vha->host) 2361 return 1; 2362 if (time > vha->hw->loop_reset_delay * HZ) 2363 return 1; 2364 2365 return atomic_read(&vha->loop_state) == LOOP_READY; 2366 } 2367 2368 /* 2369 * PCI driver interface 2370 */ 2371 static int 2372 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2373 { 2374 int ret = -ENODEV; 2375 struct Scsi_Host *host; 2376 scsi_qla_host_t *base_vha = NULL; 2377 struct qla_hw_data *ha; 2378 char pci_info[30]; 2379 char fw_str[30], wq_name[30]; 2380 struct scsi_host_template *sht; 2381 int bars, mem_only = 0; 2382 uint16_t req_length = 0, rsp_length = 0; 2383 struct req_que *req = NULL; 2384 struct rsp_que *rsp = NULL; 2385 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2386 sht = &qla2xxx_driver_template; 2387 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2388 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2389 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2390 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2391 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2392 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2393 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2394 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2395 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2396 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2397 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2398 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2399 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2400 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2401 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2402 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2403 mem_only = 1; 2404 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2405 "Mem only adapter.\n"); 2406 } 2407 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2408 "Bars=%d.\n", bars); 2409 2410 if (mem_only) { 2411 if (pci_enable_device_mem(pdev)) 2412 goto probe_out; 2413 } else { 2414 if (pci_enable_device(pdev)) 2415 goto probe_out; 2416 } 2417 2418 /* This may fail but that's ok */ 2419 pci_enable_pcie_error_reporting(pdev); 2420 2421 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2422 if (!ha) { 2423 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2424 "Unable to allocate memory for ha.\n"); 2425 goto probe_out; 2426 } 2427 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2428 "Memory allocated for ha=%p.\n", ha); 2429 ha->pdev = pdev; 2430 ha->tgt.enable_class_2 = ql2xenableclass2; 2431 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2432 spin_lock_init(&ha->tgt.q_full_lock); 2433 spin_lock_init(&ha->tgt.sess_lock); 2434 spin_lock_init(&ha->tgt.atio_lock); 2435 2436 2437 /* Clear our data area */ 2438 ha->bars = bars; 2439 ha->mem_only = mem_only; 2440 spin_lock_init(&ha->hardware_lock); 2441 spin_lock_init(&ha->vport_slock); 2442 mutex_init(&ha->selflogin_lock); 2443 mutex_init(&ha->optrom_mutex); 2444 2445 /* Set ISP-type information. */ 2446 qla2x00_set_isp_flags(ha); 2447 2448 /* Set EEH reset type to fundamental if required by hba */ 2449 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2450 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2451 pdev->needs_freset = 1; 2452 2453 ha->prev_topology = 0; 2454 ha->init_cb_size = sizeof(init_cb_t); 2455 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2456 ha->optrom_size = OPTROM_SIZE_2300; 2457 2458 /* Assign ISP specific operations. */ 2459 if (IS_QLA2100(ha)) { 2460 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2461 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2462 req_length = REQUEST_ENTRY_CNT_2100; 2463 rsp_length = RESPONSE_ENTRY_CNT_2100; 2464 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2465 ha->gid_list_info_size = 4; 2466 ha->flash_conf_off = ~0; 2467 ha->flash_data_off = ~0; 2468 ha->nvram_conf_off = ~0; 2469 ha->nvram_data_off = ~0; 2470 ha->isp_ops = &qla2100_isp_ops; 2471 } else if (IS_QLA2200(ha)) { 2472 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2473 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2474 req_length = REQUEST_ENTRY_CNT_2200; 2475 rsp_length = RESPONSE_ENTRY_CNT_2100; 2476 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2477 ha->gid_list_info_size = 4; 2478 ha->flash_conf_off = ~0; 2479 ha->flash_data_off = ~0; 2480 ha->nvram_conf_off = ~0; 2481 ha->nvram_data_off = ~0; 2482 ha->isp_ops = &qla2100_isp_ops; 2483 } else if (IS_QLA23XX(ha)) { 2484 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2485 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2486 req_length = REQUEST_ENTRY_CNT_2200; 2487 rsp_length = RESPONSE_ENTRY_CNT_2300; 2488 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2489 ha->gid_list_info_size = 6; 2490 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2491 ha->optrom_size = OPTROM_SIZE_2322; 2492 ha->flash_conf_off = ~0; 2493 ha->flash_data_off = ~0; 2494 ha->nvram_conf_off = ~0; 2495 ha->nvram_data_off = ~0; 2496 ha->isp_ops = &qla2300_isp_ops; 2497 } else if (IS_QLA24XX_TYPE(ha)) { 2498 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2499 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2500 req_length = REQUEST_ENTRY_CNT_24XX; 2501 rsp_length = RESPONSE_ENTRY_CNT_2300; 2502 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2503 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2504 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2505 ha->gid_list_info_size = 8; 2506 ha->optrom_size = OPTROM_SIZE_24XX; 2507 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2508 ha->isp_ops = &qla24xx_isp_ops; 2509 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2510 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2511 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2512 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2513 } else if (IS_QLA25XX(ha)) { 2514 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2515 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2516 req_length = REQUEST_ENTRY_CNT_24XX; 2517 rsp_length = RESPONSE_ENTRY_CNT_2300; 2518 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2519 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2520 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2521 ha->gid_list_info_size = 8; 2522 ha->optrom_size = OPTROM_SIZE_25XX; 2523 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2524 ha->isp_ops = &qla25xx_isp_ops; 2525 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2526 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2527 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2528 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2529 } else if (IS_QLA81XX(ha)) { 2530 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2531 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2532 req_length = REQUEST_ENTRY_CNT_24XX; 2533 rsp_length = RESPONSE_ENTRY_CNT_2300; 2534 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2535 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2536 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2537 ha->gid_list_info_size = 8; 2538 ha->optrom_size = OPTROM_SIZE_81XX; 2539 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2540 ha->isp_ops = &qla81xx_isp_ops; 2541 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2542 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2543 ha->nvram_conf_off = ~0; 2544 ha->nvram_data_off = ~0; 2545 } else if (IS_QLA82XX(ha)) { 2546 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2547 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2548 req_length = REQUEST_ENTRY_CNT_82XX; 2549 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2550 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2551 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2552 ha->gid_list_info_size = 8; 2553 ha->optrom_size = OPTROM_SIZE_82XX; 2554 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2555 ha->isp_ops = &qla82xx_isp_ops; 2556 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2557 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2558 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2559 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2560 } else if (IS_QLA8044(ha)) { 2561 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2562 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2563 req_length = REQUEST_ENTRY_CNT_82XX; 2564 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2565 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2566 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2567 ha->gid_list_info_size = 8; 2568 ha->optrom_size = OPTROM_SIZE_83XX; 2569 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2570 ha->isp_ops = &qla8044_isp_ops; 2571 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2572 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2573 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2574 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2575 } else if (IS_QLA83XX(ha)) { 2576 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2577 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2578 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2579 req_length = REQUEST_ENTRY_CNT_83XX; 2580 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2581 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2582 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2583 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2584 ha->gid_list_info_size = 8; 2585 ha->optrom_size = OPTROM_SIZE_83XX; 2586 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2587 ha->isp_ops = &qla83xx_isp_ops; 2588 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2589 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2590 ha->nvram_conf_off = ~0; 2591 ha->nvram_data_off = ~0; 2592 } else if (IS_QLAFX00(ha)) { 2593 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2594 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2595 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2596 req_length = REQUEST_ENTRY_CNT_FX00; 2597 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2598 ha->isp_ops = &qlafx00_isp_ops; 2599 ha->port_down_retry_count = 30; /* default value */ 2600 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2601 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2602 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2603 ha->mr.fw_hbt_en = 1; 2604 ha->mr.host_info_resend = false; 2605 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2606 } else if (IS_QLA27XX(ha)) { 2607 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2608 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2609 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2610 req_length = REQUEST_ENTRY_CNT_83XX; 2611 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2612 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2613 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2614 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2615 ha->gid_list_info_size = 8; 2616 ha->optrom_size = OPTROM_SIZE_83XX; 2617 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2618 ha->isp_ops = &qla27xx_isp_ops; 2619 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2620 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2621 ha->nvram_conf_off = ~0; 2622 ha->nvram_data_off = ~0; 2623 } 2624 2625 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2626 "mbx_count=%d, req_length=%d, " 2627 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2628 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2629 "max_fibre_devices=%d.\n", 2630 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2631 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2632 ha->nvram_npiv_size, ha->max_fibre_devices); 2633 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2634 "isp_ops=%p, flash_conf_off=%d, " 2635 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2636 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2637 ha->nvram_conf_off, ha->nvram_data_off); 2638 2639 /* Configure PCI I/O space */ 2640 ret = ha->isp_ops->iospace_config(ha); 2641 if (ret) 2642 goto iospace_config_failed; 2643 2644 ql_log_pci(ql_log_info, pdev, 0x001d, 2645 "Found an ISP%04X irq %d iobase 0x%p.\n", 2646 pdev->device, pdev->irq, ha->iobase); 2647 mutex_init(&ha->vport_lock); 2648 init_completion(&ha->mbx_cmd_comp); 2649 complete(&ha->mbx_cmd_comp); 2650 init_completion(&ha->mbx_intr_comp); 2651 init_completion(&ha->dcbx_comp); 2652 init_completion(&ha->lb_portup_comp); 2653 2654 set_bit(0, (unsigned long *) ha->vp_idx_map); 2655 2656 qla2x00_config_dma_addressing(ha); 2657 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2658 "64 Bit addressing is %s.\n", 2659 ha->flags.enable_64bit_addressing ? "enable" : 2660 "disable"); 2661 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2662 if (ret) { 2663 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2664 "Failed to allocate memory for adapter, aborting.\n"); 2665 2666 goto probe_hw_failed; 2667 } 2668 2669 req->max_q_depth = MAX_Q_DEPTH; 2670 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2671 req->max_q_depth = ql2xmaxqdepth; 2672 2673 2674 base_vha = qla2x00_create_host(sht, ha); 2675 if (!base_vha) { 2676 ret = -ENOMEM; 2677 qla2x00_mem_free(ha); 2678 qla2x00_free_req_que(ha, req); 2679 qla2x00_free_rsp_que(ha, rsp); 2680 goto probe_hw_failed; 2681 } 2682 2683 pci_set_drvdata(pdev, base_vha); 2684 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2685 2686 host = base_vha->host; 2687 base_vha->req = req; 2688 if (IS_QLA2XXX_MIDTYPE(ha)) 2689 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2690 else 2691 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2692 base_vha->vp_idx; 2693 2694 /* Setup fcport template structure. */ 2695 ha->mr.fcport.vha = base_vha; 2696 ha->mr.fcport.port_type = FCT_UNKNOWN; 2697 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2698 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2699 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2700 ha->mr.fcport.scan_state = 1; 2701 2702 /* Set the SG table size based on ISP type */ 2703 if (!IS_FWI2_CAPABLE(ha)) { 2704 if (IS_QLA2100(ha)) 2705 host->sg_tablesize = 32; 2706 } else { 2707 if (!IS_QLA82XX(ha)) 2708 host->sg_tablesize = QLA_SG_ALL; 2709 } 2710 host->max_id = ha->max_fibre_devices; 2711 host->cmd_per_lun = 3; 2712 host->unique_id = host->host_no; 2713 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2714 host->max_cmd_len = 32; 2715 else 2716 host->max_cmd_len = MAX_CMDSZ; 2717 host->max_channel = MAX_BUSES - 1; 2718 /* Older HBAs support only 16-bit LUNs */ 2719 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2720 ql2xmaxlun > 0xffff) 2721 host->max_lun = 0xffff; 2722 else 2723 host->max_lun = ql2xmaxlun; 2724 host->transportt = qla2xxx_transport_template; 2725 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2726 2727 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2728 "max_id=%d this_id=%d " 2729 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2730 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2731 host->this_id, host->cmd_per_lun, host->unique_id, 2732 host->max_cmd_len, host->max_channel, host->max_lun, 2733 host->transportt, sht->vendor_id); 2734 2735 que_init: 2736 /* Alloc arrays of request and response ring ptrs */ 2737 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2738 ql_log(ql_log_fatal, base_vha, 0x003d, 2739 "Failed to allocate memory for queue pointers..." 2740 "aborting.\n"); 2741 goto probe_init_failed; 2742 } 2743 2744 qlt_probe_one_stage1(base_vha, ha); 2745 2746 /* Set up the irqs */ 2747 ret = qla2x00_request_irqs(ha, rsp); 2748 if (ret) 2749 goto probe_init_failed; 2750 2751 pci_save_state(pdev); 2752 2753 /* Assign back pointers */ 2754 rsp->req = req; 2755 req->rsp = rsp; 2756 2757 if (IS_QLAFX00(ha)) { 2758 ha->rsp_q_map[0] = rsp; 2759 ha->req_q_map[0] = req; 2760 set_bit(0, ha->req_qid_map); 2761 set_bit(0, ha->rsp_qid_map); 2762 } 2763 2764 /* FWI2-capable only. */ 2765 req->req_q_in = &ha->iobase->isp24.req_q_in; 2766 req->req_q_out = &ha->iobase->isp24.req_q_out; 2767 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2768 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2769 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2770 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2771 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2772 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2773 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2774 } 2775 2776 if (IS_QLAFX00(ha)) { 2777 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2778 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2779 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2780 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2781 } 2782 2783 if (IS_P3P_TYPE(ha)) { 2784 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2785 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2786 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2787 } 2788 2789 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2790 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2791 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2792 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2793 "req->req_q_in=%p req->req_q_out=%p " 2794 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2795 req->req_q_in, req->req_q_out, 2796 rsp->rsp_q_in, rsp->rsp_q_out); 2797 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2798 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2799 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2800 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2801 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2802 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2803 2804 if (ha->isp_ops->initialize_adapter(base_vha)) { 2805 ql_log(ql_log_fatal, base_vha, 0x00d6, 2806 "Failed to initialize adapter - Adapter flags %x.\n", 2807 base_vha->device_flags); 2808 2809 if (IS_QLA82XX(ha)) { 2810 qla82xx_idc_lock(ha); 2811 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2812 QLA8XXX_DEV_FAILED); 2813 qla82xx_idc_unlock(ha); 2814 ql_log(ql_log_fatal, base_vha, 0x00d7, 2815 "HW State: FAILED.\n"); 2816 } else if (IS_QLA8044(ha)) { 2817 qla8044_idc_lock(ha); 2818 qla8044_wr_direct(base_vha, 2819 QLA8044_CRB_DEV_STATE_INDEX, 2820 QLA8XXX_DEV_FAILED); 2821 qla8044_idc_unlock(ha); 2822 ql_log(ql_log_fatal, base_vha, 0x0150, 2823 "HW State: FAILED.\n"); 2824 } 2825 2826 ret = -ENODEV; 2827 goto probe_failed; 2828 } 2829 2830 if (IS_QLAFX00(ha)) 2831 host->can_queue = QLAFX00_MAX_CANQUEUE; 2832 else 2833 host->can_queue = req->num_outstanding_cmds - 10; 2834 2835 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2836 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2837 host->can_queue, base_vha->req, 2838 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2839 2840 if (ha->mqenable) { 2841 if (qla25xx_setup_mode(base_vha)) { 2842 ql_log(ql_log_warn, base_vha, 0x00ec, 2843 "Failed to create queues, falling back to single queue mode.\n"); 2844 goto que_init; 2845 } 2846 } 2847 2848 if (ha->flags.running_gold_fw) 2849 goto skip_dpc; 2850 2851 /* 2852 * Startup the kernel thread for this host adapter 2853 */ 2854 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2855 "%s_dpc", base_vha->host_str); 2856 if (IS_ERR(ha->dpc_thread)) { 2857 ql_log(ql_log_fatal, base_vha, 0x00ed, 2858 "Failed to start DPC thread.\n"); 2859 ret = PTR_ERR(ha->dpc_thread); 2860 goto probe_failed; 2861 } 2862 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2863 "DPC thread started successfully.\n"); 2864 2865 /* 2866 * If we're not coming up in initiator mode, we might sit for 2867 * a while without waking up the dpc thread, which leads to a 2868 * stuck process warning. So just kick the dpc once here and 2869 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2870 */ 2871 qla2xxx_wake_dpc(base_vha); 2872 2873 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2874 2875 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2876 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2877 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2878 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2879 2880 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2881 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2882 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2883 INIT_WORK(&ha->idc_state_handler, 2884 qla83xx_idc_state_handler_work); 2885 INIT_WORK(&ha->nic_core_unrecoverable, 2886 qla83xx_nic_core_unrecoverable_work); 2887 } 2888 2889 skip_dpc: 2890 list_add_tail(&base_vha->list, &ha->vp_list); 2891 base_vha->host->irq = ha->pdev->irq; 2892 2893 /* Initialized the timer */ 2894 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2895 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2896 "Started qla2x00_timer with " 2897 "interval=%d.\n", WATCH_INTERVAL); 2898 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2899 "Detected hba at address=%p.\n", 2900 ha); 2901 2902 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2903 if (ha->fw_attributes & BIT_4) { 2904 int prot = 0, guard; 2905 base_vha->flags.difdix_supported = 1; 2906 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2907 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2908 if (ql2xenabledif == 1) 2909 prot = SHOST_DIX_TYPE0_PROTECTION; 2910 scsi_host_set_prot(host, 2911 prot | SHOST_DIF_TYPE1_PROTECTION 2912 | SHOST_DIF_TYPE2_PROTECTION 2913 | SHOST_DIF_TYPE3_PROTECTION 2914 | SHOST_DIX_TYPE1_PROTECTION 2915 | SHOST_DIX_TYPE2_PROTECTION 2916 | SHOST_DIX_TYPE3_PROTECTION); 2917 2918 guard = SHOST_DIX_GUARD_CRC; 2919 2920 if (IS_PI_IPGUARD_CAPABLE(ha) && 2921 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2922 guard |= SHOST_DIX_GUARD_IP; 2923 2924 scsi_host_set_guard(host, guard); 2925 } else 2926 base_vha->flags.difdix_supported = 0; 2927 } 2928 2929 ha->isp_ops->enable_intrs(ha); 2930 2931 if (IS_QLAFX00(ha)) { 2932 ret = qlafx00_fx_disc(base_vha, 2933 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2934 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2935 QLA_SG_ALL : 128; 2936 } 2937 2938 ret = scsi_add_host(host, &pdev->dev); 2939 if (ret) 2940 goto probe_failed; 2941 2942 base_vha->flags.init_done = 1; 2943 base_vha->flags.online = 1; 2944 ha->prev_minidump_failed = 0; 2945 2946 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2947 "Init done and hba is online.\n"); 2948 2949 if (qla_ini_mode_enabled(base_vha)) 2950 scsi_scan_host(host); 2951 else 2952 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2953 "skipping scsi_scan_host() for non-initiator port\n"); 2954 2955 qla2x00_alloc_sysfs_attr(base_vha); 2956 2957 if (IS_QLAFX00(ha)) { 2958 ret = qlafx00_fx_disc(base_vha, 2959 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2960 2961 /* Register system information */ 2962 ret = qlafx00_fx_disc(base_vha, 2963 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2964 } 2965 2966 qla2x00_init_host_attr(base_vha); 2967 2968 qla2x00_dfs_setup(base_vha); 2969 2970 ql_log(ql_log_info, base_vha, 0x00fb, 2971 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2972 ql_log(ql_log_info, base_vha, 0x00fc, 2973 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2974 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2975 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2976 base_vha->host_no, 2977 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2978 2979 qlt_add_target(ha, base_vha); 2980 2981 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2982 2983 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2984 return -ENODEV; 2985 2986 return 0; 2987 2988 probe_init_failed: 2989 qla2x00_free_req_que(ha, req); 2990 ha->req_q_map[0] = NULL; 2991 clear_bit(0, ha->req_qid_map); 2992 qla2x00_free_rsp_que(ha, rsp); 2993 ha->rsp_q_map[0] = NULL; 2994 clear_bit(0, ha->rsp_qid_map); 2995 ha->max_req_queues = ha->max_rsp_queues = 0; 2996 2997 probe_failed: 2998 if (base_vha->timer_active) 2999 qla2x00_stop_timer(base_vha); 3000 base_vha->flags.online = 0; 3001 if (ha->dpc_thread) { 3002 struct task_struct *t = ha->dpc_thread; 3003 3004 ha->dpc_thread = NULL; 3005 kthread_stop(t); 3006 } 3007 3008 qla2x00_free_device(base_vha); 3009 3010 scsi_host_put(base_vha->host); 3011 3012 probe_hw_failed: 3013 qla2x00_clear_drv_active(ha); 3014 3015 iospace_config_failed: 3016 if (IS_P3P_TYPE(ha)) { 3017 if (!ha->nx_pcibase) 3018 iounmap((device_reg_t *)ha->nx_pcibase); 3019 if (!ql2xdbwr) 3020 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3021 } else { 3022 if (ha->iobase) 3023 iounmap(ha->iobase); 3024 if (ha->cregbase) 3025 iounmap(ha->cregbase); 3026 } 3027 pci_release_selected_regions(ha->pdev, ha->bars); 3028 kfree(ha); 3029 ha = NULL; 3030 3031 probe_out: 3032 pci_disable_device(pdev); 3033 return ret; 3034 } 3035 3036 static void 3037 qla2x00_shutdown(struct pci_dev *pdev) 3038 { 3039 scsi_qla_host_t *vha; 3040 struct qla_hw_data *ha; 3041 3042 if (!atomic_read(&pdev->enable_cnt)) 3043 return; 3044 3045 vha = pci_get_drvdata(pdev); 3046 ha = vha->hw; 3047 3048 /* Notify ISPFX00 firmware */ 3049 if (IS_QLAFX00(ha)) 3050 qlafx00_driver_shutdown(vha, 20); 3051 3052 /* Turn-off FCE trace */ 3053 if (ha->flags.fce_enabled) { 3054 qla2x00_disable_fce_trace(vha, NULL, NULL); 3055 ha->flags.fce_enabled = 0; 3056 } 3057 3058 /* Turn-off EFT trace */ 3059 if (ha->eft) 3060 qla2x00_disable_eft_trace(vha); 3061 3062 /* Stop currently executing firmware. */ 3063 qla2x00_try_to_stop_firmware(vha); 3064 3065 /* Turn adapter off line */ 3066 vha->flags.online = 0; 3067 3068 /* turn-off interrupts on the card */ 3069 if (ha->interrupts_on) { 3070 vha->flags.init_done = 0; 3071 ha->isp_ops->disable_intrs(ha); 3072 } 3073 3074 qla2x00_free_irqs(vha); 3075 3076 qla2x00_free_fw_dump(ha); 3077 3078 pci_disable_pcie_error_reporting(pdev); 3079 pci_disable_device(pdev); 3080 } 3081 3082 /* Deletes all the virtual ports for a given ha */ 3083 static void 3084 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3085 { 3086 scsi_qla_host_t *vha; 3087 unsigned long flags; 3088 3089 mutex_lock(&ha->vport_lock); 3090 while (ha->cur_vport_count) { 3091 spin_lock_irqsave(&ha->vport_slock, flags); 3092 3093 BUG_ON(base_vha->list.next == &ha->vp_list); 3094 /* This assumes first entry in ha->vp_list is always base vha */ 3095 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3096 scsi_host_get(vha->host); 3097 3098 spin_unlock_irqrestore(&ha->vport_slock, flags); 3099 mutex_unlock(&ha->vport_lock); 3100 3101 fc_vport_terminate(vha->fc_vport); 3102 scsi_host_put(vha->host); 3103 3104 mutex_lock(&ha->vport_lock); 3105 } 3106 mutex_unlock(&ha->vport_lock); 3107 } 3108 3109 /* Stops all deferred work threads */ 3110 static void 3111 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3112 { 3113 /* Flush the work queue and remove it */ 3114 if (ha->wq) { 3115 flush_workqueue(ha->wq); 3116 destroy_workqueue(ha->wq); 3117 ha->wq = NULL; 3118 } 3119 3120 /* Cancel all work and destroy DPC workqueues */ 3121 if (ha->dpc_lp_wq) { 3122 cancel_work_sync(&ha->idc_aen); 3123 destroy_workqueue(ha->dpc_lp_wq); 3124 ha->dpc_lp_wq = NULL; 3125 } 3126 3127 if (ha->dpc_hp_wq) { 3128 cancel_work_sync(&ha->nic_core_reset); 3129 cancel_work_sync(&ha->idc_state_handler); 3130 cancel_work_sync(&ha->nic_core_unrecoverable); 3131 destroy_workqueue(ha->dpc_hp_wq); 3132 ha->dpc_hp_wq = NULL; 3133 } 3134 3135 /* Kill the kernel thread for this host */ 3136 if (ha->dpc_thread) { 3137 struct task_struct *t = ha->dpc_thread; 3138 3139 /* 3140 * qla2xxx_wake_dpc checks for ->dpc_thread 3141 * so we need to zero it out. 3142 */ 3143 ha->dpc_thread = NULL; 3144 kthread_stop(t); 3145 } 3146 } 3147 3148 static void 3149 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3150 { 3151 if (IS_QLA82XX(ha)) { 3152 3153 iounmap((device_reg_t *)ha->nx_pcibase); 3154 if (!ql2xdbwr) 3155 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3156 } else { 3157 if (ha->iobase) 3158 iounmap(ha->iobase); 3159 3160 if (ha->cregbase) 3161 iounmap(ha->cregbase); 3162 3163 if (ha->mqiobase) 3164 iounmap(ha->mqiobase); 3165 3166 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3167 iounmap(ha->msixbase); 3168 } 3169 } 3170 3171 static void 3172 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3173 { 3174 if (IS_QLA8044(ha)) { 3175 qla8044_idc_lock(ha); 3176 qla8044_clear_drv_active(ha); 3177 qla8044_idc_unlock(ha); 3178 } else if (IS_QLA82XX(ha)) { 3179 qla82xx_idc_lock(ha); 3180 qla82xx_clear_drv_active(ha); 3181 qla82xx_idc_unlock(ha); 3182 } 3183 } 3184 3185 static void 3186 qla2x00_remove_one(struct pci_dev *pdev) 3187 { 3188 scsi_qla_host_t *base_vha; 3189 struct qla_hw_data *ha; 3190 3191 base_vha = pci_get_drvdata(pdev); 3192 ha = base_vha->hw; 3193 3194 /* Indicate device removal to prevent future board_disable and wait 3195 * until any pending board_disable has completed. */ 3196 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3197 cancel_work_sync(&ha->board_disable); 3198 3199 /* 3200 * If the PCI device is disabled then there was a PCI-disconnect and 3201 * qla2x00_disable_board_on_pci_error has taken care of most of the 3202 * resources. 3203 */ 3204 if (!atomic_read(&pdev->enable_cnt)) { 3205 scsi_host_put(base_vha->host); 3206 kfree(ha); 3207 pci_set_drvdata(pdev, NULL); 3208 return; 3209 } 3210 3211 qla2x00_wait_for_hba_ready(base_vha); 3212 3213 /* if UNLOAD flag is already set, then continue unload, 3214 * where it was set first. 3215 */ 3216 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3217 return; 3218 3219 set_bit(UNLOADING, &base_vha->dpc_flags); 3220 3221 if (IS_QLAFX00(ha)) 3222 qlafx00_driver_shutdown(base_vha, 20); 3223 3224 qla2x00_delete_all_vps(ha, base_vha); 3225 3226 if (IS_QLA8031(ha)) { 3227 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3228 "Clearing fcoe driver presence.\n"); 3229 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3230 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3231 "Error while clearing DRV-Presence.\n"); 3232 } 3233 3234 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3235 3236 qla2x00_dfs_remove(base_vha); 3237 3238 qla84xx_put_chip(base_vha); 3239 3240 /* Laser should be disabled only for ISP2031 */ 3241 if (IS_QLA2031(ha)) 3242 qla83xx_disable_laser(base_vha); 3243 3244 /* Disable timer */ 3245 if (base_vha->timer_active) 3246 qla2x00_stop_timer(base_vha); 3247 3248 base_vha->flags.online = 0; 3249 3250 /* free DMA memory */ 3251 if (ha->exlogin_buf) 3252 qla2x00_free_exlogin_buffer(ha); 3253 3254 /* free DMA memory */ 3255 if (ha->exchoffld_buf) 3256 qla2x00_free_exchoffld_buffer(ha); 3257 3258 qla2x00_destroy_deferred_work(ha); 3259 3260 qlt_remove_target(ha, base_vha); 3261 3262 qla2x00_free_sysfs_attr(base_vha, true); 3263 3264 fc_remove_host(base_vha->host); 3265 3266 scsi_remove_host(base_vha->host); 3267 3268 qla2x00_free_device(base_vha); 3269 3270 qla2x00_clear_drv_active(ha); 3271 3272 scsi_host_put(base_vha->host); 3273 3274 qla2x00_unmap_iobases(ha); 3275 3276 pci_release_selected_regions(ha->pdev, ha->bars); 3277 kfree(ha); 3278 ha = NULL; 3279 3280 pci_disable_pcie_error_reporting(pdev); 3281 3282 pci_disable_device(pdev); 3283 } 3284 3285 static void 3286 qla2x00_free_device(scsi_qla_host_t *vha) 3287 { 3288 struct qla_hw_data *ha = vha->hw; 3289 3290 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3291 3292 /* Disable timer */ 3293 if (vha->timer_active) 3294 qla2x00_stop_timer(vha); 3295 3296 qla25xx_delete_queues(vha); 3297 3298 if (ha->flags.fce_enabled) 3299 qla2x00_disable_fce_trace(vha, NULL, NULL); 3300 3301 if (ha->eft) 3302 qla2x00_disable_eft_trace(vha); 3303 3304 /* Stop currently executing firmware. */ 3305 qla2x00_try_to_stop_firmware(vha); 3306 3307 vha->flags.online = 0; 3308 3309 /* turn-off interrupts on the card */ 3310 if (ha->interrupts_on) { 3311 vha->flags.init_done = 0; 3312 ha->isp_ops->disable_intrs(ha); 3313 } 3314 3315 qla2x00_free_irqs(vha); 3316 3317 qla2x00_free_fcports(vha); 3318 3319 qla2x00_mem_free(ha); 3320 3321 qla82xx_md_free(vha); 3322 3323 qla2x00_free_queues(ha); 3324 } 3325 3326 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3327 { 3328 fc_port_t *fcport, *tfcport; 3329 3330 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3331 list_del(&fcport->list); 3332 qla2x00_clear_loop_id(fcport); 3333 kfree(fcport); 3334 fcport = NULL; 3335 } 3336 } 3337 3338 static inline void 3339 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3340 int defer) 3341 { 3342 struct fc_rport *rport; 3343 scsi_qla_host_t *base_vha; 3344 unsigned long flags; 3345 3346 if (!fcport->rport) 3347 return; 3348 3349 rport = fcport->rport; 3350 if (defer) { 3351 base_vha = pci_get_drvdata(vha->hw->pdev); 3352 spin_lock_irqsave(vha->host->host_lock, flags); 3353 fcport->drport = rport; 3354 spin_unlock_irqrestore(vha->host->host_lock, flags); 3355 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3356 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3357 qla2xxx_wake_dpc(base_vha); 3358 } else { 3359 int now; 3360 if (rport) 3361 fc_remote_port_delete(rport); 3362 qlt_do_generation_tick(vha, &now); 3363 qlt_fc_port_deleted(vha, fcport, now); 3364 } 3365 } 3366 3367 /* 3368 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3369 * 3370 * Input: ha = adapter block pointer. fcport = port structure pointer. 3371 * 3372 * Return: None. 3373 * 3374 * Context: 3375 */ 3376 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3377 int do_login, int defer) 3378 { 3379 if (IS_QLAFX00(vha->hw)) { 3380 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3381 qla2x00_schedule_rport_del(vha, fcport, defer); 3382 return; 3383 } 3384 3385 if (atomic_read(&fcport->state) == FCS_ONLINE && 3386 vha->vp_idx == fcport->vha->vp_idx) { 3387 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3388 qla2x00_schedule_rport_del(vha, fcport, defer); 3389 } 3390 /* 3391 * We may need to retry the login, so don't change the state of the 3392 * port but do the retries. 3393 */ 3394 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3395 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3396 3397 if (!do_login) 3398 return; 3399 3400 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3401 3402 if (fcport->login_retry == 0) { 3403 fcport->login_retry = vha->hw->login_retry_count; 3404 3405 ql_dbg(ql_dbg_disc, vha, 0x2067, 3406 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3407 fcport->port_name, fcport->loop_id, fcport->login_retry); 3408 } 3409 } 3410 3411 /* 3412 * qla2x00_mark_all_devices_lost 3413 * Updates fcport state when device goes offline. 3414 * 3415 * Input: 3416 * ha = adapter block pointer. 3417 * fcport = port structure pointer. 3418 * 3419 * Return: 3420 * None. 3421 * 3422 * Context: 3423 */ 3424 void 3425 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3426 { 3427 fc_port_t *fcport; 3428 3429 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3430 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3431 continue; 3432 3433 /* 3434 * No point in marking the device as lost, if the device is 3435 * already DEAD. 3436 */ 3437 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3438 continue; 3439 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3440 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3441 if (defer) 3442 qla2x00_schedule_rport_del(vha, fcport, defer); 3443 else if (vha->vp_idx == fcport->vha->vp_idx) 3444 qla2x00_schedule_rport_del(vha, fcport, defer); 3445 } 3446 } 3447 } 3448 3449 /* 3450 * qla2x00_mem_alloc 3451 * Allocates adapter memory. 3452 * 3453 * Returns: 3454 * 0 = success. 3455 * !0 = failure. 3456 */ 3457 static int 3458 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3459 struct req_que **req, struct rsp_que **rsp) 3460 { 3461 char name[16]; 3462 3463 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3464 &ha->init_cb_dma, GFP_KERNEL); 3465 if (!ha->init_cb) 3466 goto fail; 3467 3468 if (qlt_mem_alloc(ha) < 0) 3469 goto fail_free_init_cb; 3470 3471 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3472 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3473 if (!ha->gid_list) 3474 goto fail_free_tgt_mem; 3475 3476 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3477 if (!ha->srb_mempool) 3478 goto fail_free_gid_list; 3479 3480 if (IS_P3P_TYPE(ha)) { 3481 /* Allocate cache for CT6 Ctx. */ 3482 if (!ctx_cachep) { 3483 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3484 sizeof(struct ct6_dsd), 0, 3485 SLAB_HWCACHE_ALIGN, NULL); 3486 if (!ctx_cachep) 3487 goto fail_free_gid_list; 3488 } 3489 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3490 ctx_cachep); 3491 if (!ha->ctx_mempool) 3492 goto fail_free_srb_mempool; 3493 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3494 "ctx_cachep=%p ctx_mempool=%p.\n", 3495 ctx_cachep, ha->ctx_mempool); 3496 } 3497 3498 /* Get memory for cached NVRAM */ 3499 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3500 if (!ha->nvram) 3501 goto fail_free_ctx_mempool; 3502 3503 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3504 ha->pdev->device); 3505 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3506 DMA_POOL_SIZE, 8, 0); 3507 if (!ha->s_dma_pool) 3508 goto fail_free_nvram; 3509 3510 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3511 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3512 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3513 3514 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3515 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3516 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3517 if (!ha->dl_dma_pool) { 3518 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3519 "Failed to allocate memory for dl_dma_pool.\n"); 3520 goto fail_s_dma_pool; 3521 } 3522 3523 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3524 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3525 if (!ha->fcp_cmnd_dma_pool) { 3526 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3527 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3528 goto fail_dl_dma_pool; 3529 } 3530 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3531 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3532 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3533 } 3534 3535 /* Allocate memory for SNS commands */ 3536 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3537 /* Get consistent memory allocated for SNS commands */ 3538 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3539 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3540 if (!ha->sns_cmd) 3541 goto fail_dma_pool; 3542 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3543 "sns_cmd: %p.\n", ha->sns_cmd); 3544 } else { 3545 /* Get consistent memory allocated for MS IOCB */ 3546 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3547 &ha->ms_iocb_dma); 3548 if (!ha->ms_iocb) 3549 goto fail_dma_pool; 3550 /* Get consistent memory allocated for CT SNS commands */ 3551 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3552 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3553 if (!ha->ct_sns) 3554 goto fail_free_ms_iocb; 3555 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3556 "ms_iocb=%p ct_sns=%p.\n", 3557 ha->ms_iocb, ha->ct_sns); 3558 } 3559 3560 /* Allocate memory for request ring */ 3561 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3562 if (!*req) { 3563 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3564 "Failed to allocate memory for req.\n"); 3565 goto fail_req; 3566 } 3567 (*req)->length = req_len; 3568 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3569 ((*req)->length + 1) * sizeof(request_t), 3570 &(*req)->dma, GFP_KERNEL); 3571 if (!(*req)->ring) { 3572 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3573 "Failed to allocate memory for req_ring.\n"); 3574 goto fail_req_ring; 3575 } 3576 /* Allocate memory for response ring */ 3577 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3578 if (!*rsp) { 3579 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3580 "Failed to allocate memory for rsp.\n"); 3581 goto fail_rsp; 3582 } 3583 (*rsp)->hw = ha; 3584 (*rsp)->length = rsp_len; 3585 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3586 ((*rsp)->length + 1) * sizeof(response_t), 3587 &(*rsp)->dma, GFP_KERNEL); 3588 if (!(*rsp)->ring) { 3589 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3590 "Failed to allocate memory for rsp_ring.\n"); 3591 goto fail_rsp_ring; 3592 } 3593 (*req)->rsp = *rsp; 3594 (*rsp)->req = *req; 3595 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3596 "req=%p req->length=%d req->ring=%p rsp=%p " 3597 "rsp->length=%d rsp->ring=%p.\n", 3598 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3599 (*rsp)->ring); 3600 /* Allocate memory for NVRAM data for vports */ 3601 if (ha->nvram_npiv_size) { 3602 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3603 ha->nvram_npiv_size, GFP_KERNEL); 3604 if (!ha->npiv_info) { 3605 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3606 "Failed to allocate memory for npiv_info.\n"); 3607 goto fail_npiv_info; 3608 } 3609 } else 3610 ha->npiv_info = NULL; 3611 3612 /* Get consistent memory allocated for EX-INIT-CB. */ 3613 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3614 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3615 &ha->ex_init_cb_dma); 3616 if (!ha->ex_init_cb) 3617 goto fail_ex_init_cb; 3618 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3619 "ex_init_cb=%p.\n", ha->ex_init_cb); 3620 } 3621 3622 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3623 3624 /* Get consistent memory allocated for Async Port-Database. */ 3625 if (!IS_FWI2_CAPABLE(ha)) { 3626 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3627 &ha->async_pd_dma); 3628 if (!ha->async_pd) 3629 goto fail_async_pd; 3630 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3631 "async_pd=%p.\n", ha->async_pd); 3632 } 3633 3634 INIT_LIST_HEAD(&ha->vp_list); 3635 3636 /* Allocate memory for our loop_id bitmap */ 3637 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3638 GFP_KERNEL); 3639 if (!ha->loop_id_map) 3640 goto fail_async_pd; 3641 else { 3642 qla2x00_set_reserved_loop_ids(ha); 3643 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3644 "loop_id_map=%p.\n", ha->loop_id_map); 3645 } 3646 3647 return 0; 3648 3649 fail_async_pd: 3650 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3651 fail_ex_init_cb: 3652 kfree(ha->npiv_info); 3653 fail_npiv_info: 3654 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3655 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3656 (*rsp)->ring = NULL; 3657 (*rsp)->dma = 0; 3658 fail_rsp_ring: 3659 kfree(*rsp); 3660 fail_rsp: 3661 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3662 sizeof(request_t), (*req)->ring, (*req)->dma); 3663 (*req)->ring = NULL; 3664 (*req)->dma = 0; 3665 fail_req_ring: 3666 kfree(*req); 3667 fail_req: 3668 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3669 ha->ct_sns, ha->ct_sns_dma); 3670 ha->ct_sns = NULL; 3671 ha->ct_sns_dma = 0; 3672 fail_free_ms_iocb: 3673 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3674 ha->ms_iocb = NULL; 3675 ha->ms_iocb_dma = 0; 3676 fail_dma_pool: 3677 if (IS_QLA82XX(ha) || ql2xenabledif) { 3678 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3679 ha->fcp_cmnd_dma_pool = NULL; 3680 } 3681 fail_dl_dma_pool: 3682 if (IS_QLA82XX(ha) || ql2xenabledif) { 3683 dma_pool_destroy(ha->dl_dma_pool); 3684 ha->dl_dma_pool = NULL; 3685 } 3686 fail_s_dma_pool: 3687 dma_pool_destroy(ha->s_dma_pool); 3688 ha->s_dma_pool = NULL; 3689 fail_free_nvram: 3690 kfree(ha->nvram); 3691 ha->nvram = NULL; 3692 fail_free_ctx_mempool: 3693 mempool_destroy(ha->ctx_mempool); 3694 ha->ctx_mempool = NULL; 3695 fail_free_srb_mempool: 3696 mempool_destroy(ha->srb_mempool); 3697 ha->srb_mempool = NULL; 3698 fail_free_gid_list: 3699 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3700 ha->gid_list, 3701 ha->gid_list_dma); 3702 ha->gid_list = NULL; 3703 ha->gid_list_dma = 0; 3704 fail_free_tgt_mem: 3705 qlt_mem_free(ha); 3706 fail_free_init_cb: 3707 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3708 ha->init_cb_dma); 3709 ha->init_cb = NULL; 3710 ha->init_cb_dma = 0; 3711 fail: 3712 ql_log(ql_log_fatal, NULL, 0x0030, 3713 "Memory allocation failure.\n"); 3714 return -ENOMEM; 3715 } 3716 3717 int 3718 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3719 { 3720 int rval; 3721 uint16_t size, max_cnt, temp; 3722 struct qla_hw_data *ha = vha->hw; 3723 3724 /* Return if we don't need to alloacate any extended logins */ 3725 if (!ql2xexlogins) 3726 return QLA_SUCCESS; 3727 3728 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3729 max_cnt = 0; 3730 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3731 if (rval != QLA_SUCCESS) { 3732 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3733 "Failed to get exlogin status.\n"); 3734 return rval; 3735 } 3736 3737 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3738 ha->exlogin_size = (size * temp); 3739 ql_log(ql_log_info, vha, 0xd024, 3740 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3741 max_cnt, size, temp); 3742 3743 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3744 ha->exlogin_size); 3745 3746 /* Get consistent memory for extended logins */ 3747 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 3748 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 3749 if (!ha->exlogin_buf) { 3750 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 3751 "Failed to allocate memory for exlogin_buf_dma.\n"); 3752 return -ENOMEM; 3753 } 3754 3755 /* Now configure the dma buffer */ 3756 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 3757 if (rval) { 3758 ql_log(ql_log_fatal, vha, 0x00cf, 3759 "Setup extended login buffer ****FAILED****.\n"); 3760 qla2x00_free_exlogin_buffer(ha); 3761 } 3762 3763 return rval; 3764 } 3765 3766 /* 3767 * qla2x00_free_exlogin_buffer 3768 * 3769 * Input: 3770 * ha = adapter block pointer 3771 */ 3772 void 3773 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 3774 { 3775 if (ha->exlogin_buf) { 3776 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 3777 ha->exlogin_buf, ha->exlogin_buf_dma); 3778 ha->exlogin_buf = NULL; 3779 ha->exlogin_size = 0; 3780 } 3781 } 3782 3783 int 3784 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 3785 { 3786 int rval; 3787 uint16_t size, max_cnt, temp; 3788 struct qla_hw_data *ha = vha->hw; 3789 3790 /* Return if we don't need to alloacate any extended logins */ 3791 if (!ql2xexchoffld) 3792 return QLA_SUCCESS; 3793 3794 ql_log(ql_log_info, vha, 0xd014, 3795 "Exchange offload count: %d.\n", ql2xexlogins); 3796 3797 max_cnt = 0; 3798 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 3799 if (rval != QLA_SUCCESS) { 3800 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 3801 "Failed to get exlogin status.\n"); 3802 return rval; 3803 } 3804 3805 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 3806 ha->exchoffld_size = (size * temp); 3807 ql_log(ql_log_info, vha, 0xd016, 3808 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 3809 max_cnt, size, temp); 3810 3811 ql_log(ql_log_info, vha, 0xd017, 3812 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 3813 3814 /* Get consistent memory for extended logins */ 3815 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 3816 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 3817 if (!ha->exchoffld_buf) { 3818 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 3819 "Failed to allocate memory for exchoffld_buf_dma.\n"); 3820 return -ENOMEM; 3821 } 3822 3823 /* Now configure the dma buffer */ 3824 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 3825 if (rval) { 3826 ql_log(ql_log_fatal, vha, 0xd02e, 3827 "Setup exchange offload buffer ****FAILED****.\n"); 3828 qla2x00_free_exchoffld_buffer(ha); 3829 } 3830 3831 return rval; 3832 } 3833 3834 /* 3835 * qla2x00_free_exchoffld_buffer 3836 * 3837 * Input: 3838 * ha = adapter block pointer 3839 */ 3840 void 3841 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 3842 { 3843 if (ha->exchoffld_buf) { 3844 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 3845 ha->exchoffld_buf, ha->exchoffld_buf_dma); 3846 ha->exchoffld_buf = NULL; 3847 ha->exchoffld_size = 0; 3848 } 3849 } 3850 3851 /* 3852 * qla2x00_free_fw_dump 3853 * Frees fw dump stuff. 3854 * 3855 * Input: 3856 * ha = adapter block pointer 3857 */ 3858 static void 3859 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3860 { 3861 if (ha->fce) 3862 dma_free_coherent(&ha->pdev->dev, 3863 FCE_SIZE, ha->fce, ha->fce_dma); 3864 3865 if (ha->eft) 3866 dma_free_coherent(&ha->pdev->dev, 3867 EFT_SIZE, ha->eft, ha->eft_dma); 3868 3869 if (ha->fw_dump) 3870 vfree(ha->fw_dump); 3871 if (ha->fw_dump_template) 3872 vfree(ha->fw_dump_template); 3873 3874 ha->fce = NULL; 3875 ha->fce_dma = 0; 3876 ha->eft = NULL; 3877 ha->eft_dma = 0; 3878 ha->fw_dumped = 0; 3879 ha->fw_dump_cap_flags = 0; 3880 ha->fw_dump_reading = 0; 3881 ha->fw_dump = NULL; 3882 ha->fw_dump_len = 0; 3883 ha->fw_dump_template = NULL; 3884 ha->fw_dump_template_len = 0; 3885 } 3886 3887 /* 3888 * qla2x00_mem_free 3889 * Frees all adapter allocated memory. 3890 * 3891 * Input: 3892 * ha = adapter block pointer. 3893 */ 3894 static void 3895 qla2x00_mem_free(struct qla_hw_data *ha) 3896 { 3897 qla2x00_free_fw_dump(ha); 3898 3899 if (ha->mctp_dump) 3900 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3901 ha->mctp_dump_dma); 3902 3903 if (ha->srb_mempool) 3904 mempool_destroy(ha->srb_mempool); 3905 3906 if (ha->dcbx_tlv) 3907 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3908 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3909 3910 if (ha->xgmac_data) 3911 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3912 ha->xgmac_data, ha->xgmac_data_dma); 3913 3914 if (ha->sns_cmd) 3915 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3916 ha->sns_cmd, ha->sns_cmd_dma); 3917 3918 if (ha->ct_sns) 3919 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3920 ha->ct_sns, ha->ct_sns_dma); 3921 3922 if (ha->sfp_data) 3923 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3924 3925 if (ha->ms_iocb) 3926 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3927 3928 if (ha->ex_init_cb) 3929 dma_pool_free(ha->s_dma_pool, 3930 ha->ex_init_cb, ha->ex_init_cb_dma); 3931 3932 if (ha->async_pd) 3933 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3934 3935 if (ha->s_dma_pool) 3936 dma_pool_destroy(ha->s_dma_pool); 3937 3938 if (ha->gid_list) 3939 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3940 ha->gid_list, ha->gid_list_dma); 3941 3942 if (IS_QLA82XX(ha)) { 3943 if (!list_empty(&ha->gbl_dsd_list)) { 3944 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3945 3946 /* clean up allocated prev pool */ 3947 list_for_each_entry_safe(dsd_ptr, 3948 tdsd_ptr, &ha->gbl_dsd_list, list) { 3949 dma_pool_free(ha->dl_dma_pool, 3950 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3951 list_del(&dsd_ptr->list); 3952 kfree(dsd_ptr); 3953 } 3954 } 3955 } 3956 3957 if (ha->dl_dma_pool) 3958 dma_pool_destroy(ha->dl_dma_pool); 3959 3960 if (ha->fcp_cmnd_dma_pool) 3961 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3962 3963 if (ha->ctx_mempool) 3964 mempool_destroy(ha->ctx_mempool); 3965 3966 qlt_mem_free(ha); 3967 3968 if (ha->init_cb) 3969 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3970 ha->init_cb, ha->init_cb_dma); 3971 vfree(ha->optrom_buffer); 3972 kfree(ha->nvram); 3973 kfree(ha->npiv_info); 3974 kfree(ha->swl); 3975 kfree(ha->loop_id_map); 3976 3977 ha->srb_mempool = NULL; 3978 ha->ctx_mempool = NULL; 3979 ha->sns_cmd = NULL; 3980 ha->sns_cmd_dma = 0; 3981 ha->ct_sns = NULL; 3982 ha->ct_sns_dma = 0; 3983 ha->ms_iocb = NULL; 3984 ha->ms_iocb_dma = 0; 3985 ha->init_cb = NULL; 3986 ha->init_cb_dma = 0; 3987 ha->ex_init_cb = NULL; 3988 ha->ex_init_cb_dma = 0; 3989 ha->async_pd = NULL; 3990 ha->async_pd_dma = 0; 3991 3992 ha->s_dma_pool = NULL; 3993 ha->dl_dma_pool = NULL; 3994 ha->fcp_cmnd_dma_pool = NULL; 3995 3996 ha->gid_list = NULL; 3997 ha->gid_list_dma = 0; 3998 3999 ha->tgt.atio_ring = NULL; 4000 ha->tgt.atio_dma = 0; 4001 ha->tgt.tgt_vp_map = NULL; 4002 } 4003 4004 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4005 struct qla_hw_data *ha) 4006 { 4007 struct Scsi_Host *host; 4008 struct scsi_qla_host *vha = NULL; 4009 4010 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4011 if (host == NULL) { 4012 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4013 "Failed to allocate host from the scsi layer, aborting.\n"); 4014 goto fail; 4015 } 4016 4017 /* Clear our data area */ 4018 vha = shost_priv(host); 4019 memset(vha, 0, sizeof(scsi_qla_host_t)); 4020 4021 vha->host = host; 4022 vha->host_no = host->host_no; 4023 vha->hw = ha; 4024 4025 INIT_LIST_HEAD(&vha->vp_fcports); 4026 INIT_LIST_HEAD(&vha->work_list); 4027 INIT_LIST_HEAD(&vha->list); 4028 INIT_LIST_HEAD(&vha->qla_cmd_list); 4029 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4030 INIT_LIST_HEAD(&vha->logo_list); 4031 INIT_LIST_HEAD(&vha->plogi_ack_list); 4032 4033 spin_lock_init(&vha->work_lock); 4034 spin_lock_init(&vha->cmd_list_lock); 4035 4036 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4037 ql_dbg(ql_dbg_init, vha, 0x0041, 4038 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4039 vha->host, vha->hw, vha, 4040 dev_name(&(ha->pdev->dev))); 4041 4042 return vha; 4043 4044 fail: 4045 return vha; 4046 } 4047 4048 static struct qla_work_evt * 4049 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4050 { 4051 struct qla_work_evt *e; 4052 uint8_t bail; 4053 4054 QLA_VHA_MARK_BUSY(vha, bail); 4055 if (bail) 4056 return NULL; 4057 4058 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4059 if (!e) { 4060 QLA_VHA_MARK_NOT_BUSY(vha); 4061 return NULL; 4062 } 4063 4064 INIT_LIST_HEAD(&e->list); 4065 e->type = type; 4066 e->flags = QLA_EVT_FLAG_FREE; 4067 return e; 4068 } 4069 4070 static int 4071 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4072 { 4073 unsigned long flags; 4074 4075 spin_lock_irqsave(&vha->work_lock, flags); 4076 list_add_tail(&e->list, &vha->work_list); 4077 spin_unlock_irqrestore(&vha->work_lock, flags); 4078 qla2xxx_wake_dpc(vha); 4079 4080 return QLA_SUCCESS; 4081 } 4082 4083 int 4084 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4085 u32 data) 4086 { 4087 struct qla_work_evt *e; 4088 4089 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4090 if (!e) 4091 return QLA_FUNCTION_FAILED; 4092 4093 e->u.aen.code = code; 4094 e->u.aen.data = data; 4095 return qla2x00_post_work(vha, e); 4096 } 4097 4098 int 4099 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4100 { 4101 struct qla_work_evt *e; 4102 4103 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4104 if (!e) 4105 return QLA_FUNCTION_FAILED; 4106 4107 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4108 return qla2x00_post_work(vha, e); 4109 } 4110 4111 #define qla2x00_post_async_work(name, type) \ 4112 int qla2x00_post_async_##name##_work( \ 4113 struct scsi_qla_host *vha, \ 4114 fc_port_t *fcport, uint16_t *data) \ 4115 { \ 4116 struct qla_work_evt *e; \ 4117 \ 4118 e = qla2x00_alloc_work(vha, type); \ 4119 if (!e) \ 4120 return QLA_FUNCTION_FAILED; \ 4121 \ 4122 e->u.logio.fcport = fcport; \ 4123 if (data) { \ 4124 e->u.logio.data[0] = data[0]; \ 4125 e->u.logio.data[1] = data[1]; \ 4126 } \ 4127 return qla2x00_post_work(vha, e); \ 4128 } 4129 4130 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4131 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 4132 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4133 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4134 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4135 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4136 4137 int 4138 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4139 { 4140 struct qla_work_evt *e; 4141 4142 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4143 if (!e) 4144 return QLA_FUNCTION_FAILED; 4145 4146 e->u.uevent.code = code; 4147 return qla2x00_post_work(vha, e); 4148 } 4149 4150 static void 4151 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4152 { 4153 char event_string[40]; 4154 char *envp[] = { event_string, NULL }; 4155 4156 switch (code) { 4157 case QLA_UEVENT_CODE_FW_DUMP: 4158 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4159 vha->host_no); 4160 break; 4161 default: 4162 /* do nothing */ 4163 break; 4164 } 4165 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4166 } 4167 4168 int 4169 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4170 uint32_t *data, int cnt) 4171 { 4172 struct qla_work_evt *e; 4173 4174 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4175 if (!e) 4176 return QLA_FUNCTION_FAILED; 4177 4178 e->u.aenfx.evtcode = evtcode; 4179 e->u.aenfx.count = cnt; 4180 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4181 return qla2x00_post_work(vha, e); 4182 } 4183 4184 void 4185 qla2x00_do_work(struct scsi_qla_host *vha) 4186 { 4187 struct qla_work_evt *e, *tmp; 4188 unsigned long flags; 4189 LIST_HEAD(work); 4190 4191 spin_lock_irqsave(&vha->work_lock, flags); 4192 list_splice_init(&vha->work_list, &work); 4193 spin_unlock_irqrestore(&vha->work_lock, flags); 4194 4195 list_for_each_entry_safe(e, tmp, &work, list) { 4196 list_del_init(&e->list); 4197 4198 switch (e->type) { 4199 case QLA_EVT_AEN: 4200 fc_host_post_event(vha->host, fc_get_event_number(), 4201 e->u.aen.code, e->u.aen.data); 4202 break; 4203 case QLA_EVT_IDC_ACK: 4204 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4205 break; 4206 case QLA_EVT_ASYNC_LOGIN: 4207 qla2x00_async_login(vha, e->u.logio.fcport, 4208 e->u.logio.data); 4209 break; 4210 case QLA_EVT_ASYNC_LOGIN_DONE: 4211 qla2x00_async_login_done(vha, e->u.logio.fcport, 4212 e->u.logio.data); 4213 break; 4214 case QLA_EVT_ASYNC_LOGOUT: 4215 qla2x00_async_logout(vha, e->u.logio.fcport); 4216 break; 4217 case QLA_EVT_ASYNC_LOGOUT_DONE: 4218 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4219 e->u.logio.data); 4220 break; 4221 case QLA_EVT_ASYNC_ADISC: 4222 qla2x00_async_adisc(vha, e->u.logio.fcport, 4223 e->u.logio.data); 4224 break; 4225 case QLA_EVT_ASYNC_ADISC_DONE: 4226 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4227 e->u.logio.data); 4228 break; 4229 case QLA_EVT_UEVENT: 4230 qla2x00_uevent_emit(vha, e->u.uevent.code); 4231 break; 4232 case QLA_EVT_AENFX: 4233 qlafx00_process_aen(vha, e); 4234 break; 4235 } 4236 if (e->flags & QLA_EVT_FLAG_FREE) 4237 kfree(e); 4238 4239 /* For each work completed decrement vha ref count */ 4240 QLA_VHA_MARK_NOT_BUSY(vha); 4241 } 4242 } 4243 4244 /* Relogins all the fcports of a vport 4245 * Context: dpc thread 4246 */ 4247 void qla2x00_relogin(struct scsi_qla_host *vha) 4248 { 4249 fc_port_t *fcport; 4250 int status; 4251 uint16_t next_loopid = 0; 4252 struct qla_hw_data *ha = vha->hw; 4253 uint16_t data[2]; 4254 4255 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4256 /* 4257 * If the port is not ONLINE then try to login 4258 * to it if we haven't run out of retries. 4259 */ 4260 if (atomic_read(&fcport->state) != FCS_ONLINE && 4261 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4262 fcport->login_retry--; 4263 if (fcport->flags & FCF_FABRIC_DEVICE) { 4264 if (fcport->flags & FCF_FCP2_DEVICE) 4265 ha->isp_ops->fabric_logout(vha, 4266 fcport->loop_id, 4267 fcport->d_id.b.domain, 4268 fcport->d_id.b.area, 4269 fcport->d_id.b.al_pa); 4270 4271 if (fcport->loop_id == FC_NO_LOOP_ID) { 4272 fcport->loop_id = next_loopid = 4273 ha->min_external_loopid; 4274 status = qla2x00_find_new_loop_id( 4275 vha, fcport); 4276 if (status != QLA_SUCCESS) { 4277 /* Ran out of IDs to use */ 4278 break; 4279 } 4280 } 4281 4282 if (IS_ALOGIO_CAPABLE(ha)) { 4283 fcport->flags |= FCF_ASYNC_SENT; 4284 data[0] = 0; 4285 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4286 status = qla2x00_post_async_login_work( 4287 vha, fcport, data); 4288 if (status == QLA_SUCCESS) 4289 continue; 4290 /* Attempt a retry. */ 4291 status = 1; 4292 } else { 4293 status = qla2x00_fabric_login(vha, 4294 fcport, &next_loopid); 4295 if (status == QLA_SUCCESS) { 4296 int status2; 4297 uint8_t opts; 4298 4299 opts = 0; 4300 if (fcport->flags & 4301 FCF_FCP2_DEVICE) 4302 opts |= BIT_1; 4303 status2 = 4304 qla2x00_get_port_database( 4305 vha, fcport, opts); 4306 if (status2 != QLA_SUCCESS) 4307 status = 1; 4308 } 4309 } 4310 } else 4311 status = qla2x00_local_device_login(vha, 4312 fcport); 4313 4314 if (status == QLA_SUCCESS) { 4315 fcport->old_loop_id = fcport->loop_id; 4316 4317 ql_dbg(ql_dbg_disc, vha, 0x2003, 4318 "Port login OK: logged in ID 0x%x.\n", 4319 fcport->loop_id); 4320 4321 qla2x00_update_fcport(vha, fcport); 4322 4323 } else if (status == 1) { 4324 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4325 /* retry the login again */ 4326 ql_dbg(ql_dbg_disc, vha, 0x2007, 4327 "Retrying %d login again loop_id 0x%x.\n", 4328 fcport->login_retry, fcport->loop_id); 4329 } else { 4330 fcport->login_retry = 0; 4331 } 4332 4333 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4334 qla2x00_clear_loop_id(fcport); 4335 } 4336 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4337 break; 4338 } 4339 } 4340 4341 /* Schedule work on any of the dpc-workqueues */ 4342 void 4343 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4344 { 4345 struct qla_hw_data *ha = base_vha->hw; 4346 4347 switch (work_code) { 4348 case MBA_IDC_AEN: /* 0x8200 */ 4349 if (ha->dpc_lp_wq) 4350 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4351 break; 4352 4353 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4354 if (!ha->flags.nic_core_reset_hdlr_active) { 4355 if (ha->dpc_hp_wq) 4356 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4357 } else 4358 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4359 "NIC Core reset is already active. Skip " 4360 "scheduling it again.\n"); 4361 break; 4362 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4363 if (ha->dpc_hp_wq) 4364 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4365 break; 4366 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4367 if (ha->dpc_hp_wq) 4368 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4369 break; 4370 default: 4371 ql_log(ql_log_warn, base_vha, 0xb05f, 4372 "Unknown work-code=0x%x.\n", work_code); 4373 } 4374 4375 return; 4376 } 4377 4378 /* Work: Perform NIC Core Unrecoverable state handling */ 4379 void 4380 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4381 { 4382 struct qla_hw_data *ha = 4383 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4384 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4385 uint32_t dev_state = 0; 4386 4387 qla83xx_idc_lock(base_vha, 0); 4388 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4389 qla83xx_reset_ownership(base_vha); 4390 if (ha->flags.nic_core_reset_owner) { 4391 ha->flags.nic_core_reset_owner = 0; 4392 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4393 QLA8XXX_DEV_FAILED); 4394 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4395 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4396 } 4397 qla83xx_idc_unlock(base_vha, 0); 4398 } 4399 4400 /* Work: Execute IDC state handler */ 4401 void 4402 qla83xx_idc_state_handler_work(struct work_struct *work) 4403 { 4404 struct qla_hw_data *ha = 4405 container_of(work, struct qla_hw_data, idc_state_handler); 4406 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4407 uint32_t dev_state = 0; 4408 4409 qla83xx_idc_lock(base_vha, 0); 4410 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4411 if (dev_state == QLA8XXX_DEV_FAILED || 4412 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4413 qla83xx_idc_state_handler(base_vha); 4414 qla83xx_idc_unlock(base_vha, 0); 4415 } 4416 4417 static int 4418 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4419 { 4420 int rval = QLA_SUCCESS; 4421 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4422 uint32_t heart_beat_counter1, heart_beat_counter2; 4423 4424 do { 4425 if (time_after(jiffies, heart_beat_wait)) { 4426 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4427 "Nic Core f/w is not alive.\n"); 4428 rval = QLA_FUNCTION_FAILED; 4429 break; 4430 } 4431 4432 qla83xx_idc_lock(base_vha, 0); 4433 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4434 &heart_beat_counter1); 4435 qla83xx_idc_unlock(base_vha, 0); 4436 msleep(100); 4437 qla83xx_idc_lock(base_vha, 0); 4438 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4439 &heart_beat_counter2); 4440 qla83xx_idc_unlock(base_vha, 0); 4441 } while (heart_beat_counter1 == heart_beat_counter2); 4442 4443 return rval; 4444 } 4445 4446 /* Work: Perform NIC Core Reset handling */ 4447 void 4448 qla83xx_nic_core_reset_work(struct work_struct *work) 4449 { 4450 struct qla_hw_data *ha = 4451 container_of(work, struct qla_hw_data, nic_core_reset); 4452 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4453 uint32_t dev_state = 0; 4454 4455 if (IS_QLA2031(ha)) { 4456 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4457 ql_log(ql_log_warn, base_vha, 0xb081, 4458 "Failed to dump mctp\n"); 4459 return; 4460 } 4461 4462 if (!ha->flags.nic_core_reset_hdlr_active) { 4463 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4464 qla83xx_idc_lock(base_vha, 0); 4465 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4466 &dev_state); 4467 qla83xx_idc_unlock(base_vha, 0); 4468 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4469 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4470 "Nic Core f/w is alive.\n"); 4471 return; 4472 } 4473 } 4474 4475 ha->flags.nic_core_reset_hdlr_active = 1; 4476 if (qla83xx_nic_core_reset(base_vha)) { 4477 /* NIC Core reset failed. */ 4478 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4479 "NIC Core reset failed.\n"); 4480 } 4481 ha->flags.nic_core_reset_hdlr_active = 0; 4482 } 4483 } 4484 4485 /* Work: Handle 8200 IDC aens */ 4486 void 4487 qla83xx_service_idc_aen(struct work_struct *work) 4488 { 4489 struct qla_hw_data *ha = 4490 container_of(work, struct qla_hw_data, idc_aen); 4491 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4492 uint32_t dev_state, idc_control; 4493 4494 qla83xx_idc_lock(base_vha, 0); 4495 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4496 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4497 qla83xx_idc_unlock(base_vha, 0); 4498 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4499 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4500 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4501 "Application requested NIC Core Reset.\n"); 4502 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4503 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4504 QLA_SUCCESS) { 4505 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4506 "Other protocol driver requested NIC Core Reset.\n"); 4507 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4508 } 4509 } else if (dev_state == QLA8XXX_DEV_FAILED || 4510 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4511 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4512 } 4513 } 4514 4515 static void 4516 qla83xx_wait_logic(void) 4517 { 4518 int i; 4519 4520 /* Yield CPU */ 4521 if (!in_interrupt()) { 4522 /* 4523 * Wait about 200ms before retrying again. 4524 * This controls the number of retries for single 4525 * lock operation. 4526 */ 4527 msleep(100); 4528 schedule(); 4529 } else { 4530 for (i = 0; i < 20; i++) 4531 cpu_relax(); /* This a nop instr on i386 */ 4532 } 4533 } 4534 4535 static int 4536 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4537 { 4538 int rval; 4539 uint32_t data; 4540 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4541 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4542 struct qla_hw_data *ha = base_vha->hw; 4543 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4544 "Trying force recovery of the IDC lock.\n"); 4545 4546 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4547 if (rval) 4548 return rval; 4549 4550 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4551 return QLA_SUCCESS; 4552 } else { 4553 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4554 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4555 data); 4556 if (rval) 4557 return rval; 4558 4559 msleep(200); 4560 4561 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4562 &data); 4563 if (rval) 4564 return rval; 4565 4566 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4567 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4568 ~(idc_lck_rcvry_stage_mask)); 4569 rval = qla83xx_wr_reg(base_vha, 4570 QLA83XX_IDC_LOCK_RECOVERY, data); 4571 if (rval) 4572 return rval; 4573 4574 /* Forcefully perform IDC UnLock */ 4575 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4576 &data); 4577 if (rval) 4578 return rval; 4579 /* Clear lock-id by setting 0xff */ 4580 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4581 0xff); 4582 if (rval) 4583 return rval; 4584 /* Clear lock-recovery by setting 0x0 */ 4585 rval = qla83xx_wr_reg(base_vha, 4586 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4587 if (rval) 4588 return rval; 4589 } else 4590 return QLA_SUCCESS; 4591 } 4592 4593 return rval; 4594 } 4595 4596 static int 4597 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4598 { 4599 int rval = QLA_SUCCESS; 4600 uint32_t o_drv_lockid, n_drv_lockid; 4601 unsigned long lock_recovery_timeout; 4602 4603 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4604 retry_lockid: 4605 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4606 if (rval) 4607 goto exit; 4608 4609 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4610 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4611 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4612 return QLA_SUCCESS; 4613 else 4614 return QLA_FUNCTION_FAILED; 4615 } 4616 4617 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4618 if (rval) 4619 goto exit; 4620 4621 if (o_drv_lockid == n_drv_lockid) { 4622 qla83xx_wait_logic(); 4623 goto retry_lockid; 4624 } else 4625 return QLA_SUCCESS; 4626 4627 exit: 4628 return rval; 4629 } 4630 4631 void 4632 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4633 { 4634 uint16_t options = (requester_id << 15) | BIT_6; 4635 uint32_t data; 4636 uint32_t lock_owner; 4637 struct qla_hw_data *ha = base_vha->hw; 4638 4639 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4640 retry_lock: 4641 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4642 == QLA_SUCCESS) { 4643 if (data) { 4644 /* Setting lock-id to our function-number */ 4645 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4646 ha->portnum); 4647 } else { 4648 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4649 &lock_owner); 4650 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4651 "Failed to acquire IDC lock, acquired by %d, " 4652 "retrying...\n", lock_owner); 4653 4654 /* Retry/Perform IDC-Lock recovery */ 4655 if (qla83xx_idc_lock_recovery(base_vha) 4656 == QLA_SUCCESS) { 4657 qla83xx_wait_logic(); 4658 goto retry_lock; 4659 } else 4660 ql_log(ql_log_warn, base_vha, 0xb075, 4661 "IDC Lock recovery FAILED.\n"); 4662 } 4663 4664 } 4665 4666 return; 4667 4668 /* XXX: IDC-lock implementation using access-control mbx */ 4669 retry_lock2: 4670 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4671 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4672 "Failed to acquire IDC lock. retrying...\n"); 4673 /* Retry/Perform IDC-Lock recovery */ 4674 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4675 qla83xx_wait_logic(); 4676 goto retry_lock2; 4677 } else 4678 ql_log(ql_log_warn, base_vha, 0xb076, 4679 "IDC Lock recovery FAILED.\n"); 4680 } 4681 4682 return; 4683 } 4684 4685 void 4686 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4687 { 4688 #if 0 4689 uint16_t options = (requester_id << 15) | BIT_7; 4690 #endif 4691 uint16_t retry; 4692 uint32_t data; 4693 struct qla_hw_data *ha = base_vha->hw; 4694 4695 /* IDC-unlock implementation using driver-unlock/lock-id 4696 * remote registers 4697 */ 4698 retry = 0; 4699 retry_unlock: 4700 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4701 == QLA_SUCCESS) { 4702 if (data == ha->portnum) { 4703 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4704 /* Clearing lock-id by setting 0xff */ 4705 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4706 } else if (retry < 10) { 4707 /* SV: XXX: IDC unlock retrying needed here? */ 4708 4709 /* Retry for IDC-unlock */ 4710 qla83xx_wait_logic(); 4711 retry++; 4712 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4713 "Failed to release IDC lock, retrying=%d\n", retry); 4714 goto retry_unlock; 4715 } 4716 } else if (retry < 10) { 4717 /* Retry for IDC-unlock */ 4718 qla83xx_wait_logic(); 4719 retry++; 4720 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4721 "Failed to read drv-lockid, retrying=%d\n", retry); 4722 goto retry_unlock; 4723 } 4724 4725 return; 4726 4727 #if 0 4728 /* XXX: IDC-unlock implementation using access-control mbx */ 4729 retry = 0; 4730 retry_unlock2: 4731 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4732 if (retry < 10) { 4733 /* Retry for IDC-unlock */ 4734 qla83xx_wait_logic(); 4735 retry++; 4736 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4737 "Failed to release IDC lock, retrying=%d\n", retry); 4738 goto retry_unlock2; 4739 } 4740 } 4741 4742 return; 4743 #endif 4744 } 4745 4746 int 4747 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4748 { 4749 int rval = QLA_SUCCESS; 4750 struct qla_hw_data *ha = vha->hw; 4751 uint32_t drv_presence; 4752 4753 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4754 if (rval == QLA_SUCCESS) { 4755 drv_presence |= (1 << ha->portnum); 4756 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4757 drv_presence); 4758 } 4759 4760 return rval; 4761 } 4762 4763 int 4764 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4765 { 4766 int rval = QLA_SUCCESS; 4767 4768 qla83xx_idc_lock(vha, 0); 4769 rval = __qla83xx_set_drv_presence(vha); 4770 qla83xx_idc_unlock(vha, 0); 4771 4772 return rval; 4773 } 4774 4775 int 4776 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4777 { 4778 int rval = QLA_SUCCESS; 4779 struct qla_hw_data *ha = vha->hw; 4780 uint32_t drv_presence; 4781 4782 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4783 if (rval == QLA_SUCCESS) { 4784 drv_presence &= ~(1 << ha->portnum); 4785 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4786 drv_presence); 4787 } 4788 4789 return rval; 4790 } 4791 4792 int 4793 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4794 { 4795 int rval = QLA_SUCCESS; 4796 4797 qla83xx_idc_lock(vha, 0); 4798 rval = __qla83xx_clear_drv_presence(vha); 4799 qla83xx_idc_unlock(vha, 0); 4800 4801 return rval; 4802 } 4803 4804 static void 4805 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4806 { 4807 struct qla_hw_data *ha = vha->hw; 4808 uint32_t drv_ack, drv_presence; 4809 unsigned long ack_timeout; 4810 4811 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4812 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4813 while (1) { 4814 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4815 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4816 if ((drv_ack & drv_presence) == drv_presence) 4817 break; 4818 4819 if (time_after_eq(jiffies, ack_timeout)) { 4820 ql_log(ql_log_warn, vha, 0xb067, 4821 "RESET ACK TIMEOUT! drv_presence=0x%x " 4822 "drv_ack=0x%x\n", drv_presence, drv_ack); 4823 /* 4824 * The function(s) which did not ack in time are forced 4825 * to withdraw any further participation in the IDC 4826 * reset. 4827 */ 4828 if (drv_ack != drv_presence) 4829 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4830 drv_ack); 4831 break; 4832 } 4833 4834 qla83xx_idc_unlock(vha, 0); 4835 msleep(1000); 4836 qla83xx_idc_lock(vha, 0); 4837 } 4838 4839 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4840 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4841 } 4842 4843 static int 4844 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4845 { 4846 int rval = QLA_SUCCESS; 4847 uint32_t idc_control; 4848 4849 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4850 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4851 4852 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4853 __qla83xx_get_idc_control(vha, &idc_control); 4854 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4855 __qla83xx_set_idc_control(vha, 0); 4856 4857 qla83xx_idc_unlock(vha, 0); 4858 rval = qla83xx_restart_nic_firmware(vha); 4859 qla83xx_idc_lock(vha, 0); 4860 4861 if (rval != QLA_SUCCESS) { 4862 ql_log(ql_log_fatal, vha, 0xb06a, 4863 "Failed to restart NIC f/w.\n"); 4864 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4865 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4866 } else { 4867 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4868 "Success in restarting nic f/w.\n"); 4869 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4870 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4871 } 4872 4873 return rval; 4874 } 4875 4876 /* Assumes idc_lock always held on entry */ 4877 int 4878 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4879 { 4880 struct qla_hw_data *ha = base_vha->hw; 4881 int rval = QLA_SUCCESS; 4882 unsigned long dev_init_timeout; 4883 uint32_t dev_state; 4884 4885 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4886 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4887 4888 while (1) { 4889 4890 if (time_after_eq(jiffies, dev_init_timeout)) { 4891 ql_log(ql_log_warn, base_vha, 0xb06e, 4892 "Initialization TIMEOUT!\n"); 4893 /* Init timeout. Disable further NIC Core 4894 * communication. 4895 */ 4896 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4897 QLA8XXX_DEV_FAILED); 4898 ql_log(ql_log_info, base_vha, 0xb06f, 4899 "HW State: FAILED.\n"); 4900 } 4901 4902 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4903 switch (dev_state) { 4904 case QLA8XXX_DEV_READY: 4905 if (ha->flags.nic_core_reset_owner) 4906 qla83xx_idc_audit(base_vha, 4907 IDC_AUDIT_COMPLETION); 4908 ha->flags.nic_core_reset_owner = 0; 4909 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4910 "Reset_owner reset by 0x%x.\n", 4911 ha->portnum); 4912 goto exit; 4913 case QLA8XXX_DEV_COLD: 4914 if (ha->flags.nic_core_reset_owner) 4915 rval = qla83xx_device_bootstrap(base_vha); 4916 else { 4917 /* Wait for AEN to change device-state */ 4918 qla83xx_idc_unlock(base_vha, 0); 4919 msleep(1000); 4920 qla83xx_idc_lock(base_vha, 0); 4921 } 4922 break; 4923 case QLA8XXX_DEV_INITIALIZING: 4924 /* Wait for AEN to change device-state */ 4925 qla83xx_idc_unlock(base_vha, 0); 4926 msleep(1000); 4927 qla83xx_idc_lock(base_vha, 0); 4928 break; 4929 case QLA8XXX_DEV_NEED_RESET: 4930 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4931 qla83xx_need_reset_handler(base_vha); 4932 else { 4933 /* Wait for AEN to change device-state */ 4934 qla83xx_idc_unlock(base_vha, 0); 4935 msleep(1000); 4936 qla83xx_idc_lock(base_vha, 0); 4937 } 4938 /* reset timeout value after need reset handler */ 4939 dev_init_timeout = jiffies + 4940 (ha->fcoe_dev_init_timeout * HZ); 4941 break; 4942 case QLA8XXX_DEV_NEED_QUIESCENT: 4943 /* XXX: DEBUG for now */ 4944 qla83xx_idc_unlock(base_vha, 0); 4945 msleep(1000); 4946 qla83xx_idc_lock(base_vha, 0); 4947 break; 4948 case QLA8XXX_DEV_QUIESCENT: 4949 /* XXX: DEBUG for now */ 4950 if (ha->flags.quiesce_owner) 4951 goto exit; 4952 4953 qla83xx_idc_unlock(base_vha, 0); 4954 msleep(1000); 4955 qla83xx_idc_lock(base_vha, 0); 4956 dev_init_timeout = jiffies + 4957 (ha->fcoe_dev_init_timeout * HZ); 4958 break; 4959 case QLA8XXX_DEV_FAILED: 4960 if (ha->flags.nic_core_reset_owner) 4961 qla83xx_idc_audit(base_vha, 4962 IDC_AUDIT_COMPLETION); 4963 ha->flags.nic_core_reset_owner = 0; 4964 __qla83xx_clear_drv_presence(base_vha); 4965 qla83xx_idc_unlock(base_vha, 0); 4966 qla8xxx_dev_failed_handler(base_vha); 4967 rval = QLA_FUNCTION_FAILED; 4968 qla83xx_idc_lock(base_vha, 0); 4969 goto exit; 4970 case QLA8XXX_BAD_VALUE: 4971 qla83xx_idc_unlock(base_vha, 0); 4972 msleep(1000); 4973 qla83xx_idc_lock(base_vha, 0); 4974 break; 4975 default: 4976 ql_log(ql_log_warn, base_vha, 0xb071, 4977 "Unknown Device State: %x.\n", dev_state); 4978 qla83xx_idc_unlock(base_vha, 0); 4979 qla8xxx_dev_failed_handler(base_vha); 4980 rval = QLA_FUNCTION_FAILED; 4981 qla83xx_idc_lock(base_vha, 0); 4982 goto exit; 4983 } 4984 } 4985 4986 exit: 4987 return rval; 4988 } 4989 4990 void 4991 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4992 { 4993 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4994 board_disable); 4995 struct pci_dev *pdev = ha->pdev; 4996 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4997 4998 /* if UNLOAD flag is already set, then continue unload, 4999 * where it was set first. 5000 */ 5001 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5002 return; 5003 5004 ql_log(ql_log_warn, base_vha, 0x015b, 5005 "Disabling adapter.\n"); 5006 5007 set_bit(UNLOADING, &base_vha->dpc_flags); 5008 5009 qla2x00_delete_all_vps(ha, base_vha); 5010 5011 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5012 5013 qla2x00_dfs_remove(base_vha); 5014 5015 qla84xx_put_chip(base_vha); 5016 5017 if (base_vha->timer_active) 5018 qla2x00_stop_timer(base_vha); 5019 5020 base_vha->flags.online = 0; 5021 5022 qla2x00_destroy_deferred_work(ha); 5023 5024 /* 5025 * Do not try to stop beacon blink as it will issue a mailbox 5026 * command. 5027 */ 5028 qla2x00_free_sysfs_attr(base_vha, false); 5029 5030 fc_remove_host(base_vha->host); 5031 5032 scsi_remove_host(base_vha->host); 5033 5034 base_vha->flags.init_done = 0; 5035 qla25xx_delete_queues(base_vha); 5036 qla2x00_free_irqs(base_vha); 5037 qla2x00_free_fcports(base_vha); 5038 qla2x00_mem_free(ha); 5039 qla82xx_md_free(base_vha); 5040 qla2x00_free_queues(ha); 5041 5042 qla2x00_unmap_iobases(ha); 5043 5044 pci_release_selected_regions(ha->pdev, ha->bars); 5045 pci_disable_pcie_error_reporting(pdev); 5046 pci_disable_device(pdev); 5047 5048 /* 5049 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5050 */ 5051 } 5052 5053 /************************************************************************** 5054 * qla2x00_do_dpc 5055 * This kernel thread is a task that is schedule by the interrupt handler 5056 * to perform the background processing for interrupts. 5057 * 5058 * Notes: 5059 * This task always run in the context of a kernel thread. It 5060 * is kick-off by the driver's detect code and starts up 5061 * up one per adapter. It immediately goes to sleep and waits for 5062 * some fibre event. When either the interrupt handler or 5063 * the timer routine detects a event it will one of the task 5064 * bits then wake us up. 5065 **************************************************************************/ 5066 static int 5067 qla2x00_do_dpc(void *data) 5068 { 5069 scsi_qla_host_t *base_vha; 5070 struct qla_hw_data *ha; 5071 5072 ha = (struct qla_hw_data *)data; 5073 base_vha = pci_get_drvdata(ha->pdev); 5074 5075 set_user_nice(current, MIN_NICE); 5076 5077 set_current_state(TASK_INTERRUPTIBLE); 5078 while (!kthread_should_stop()) { 5079 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5080 "DPC handler sleeping.\n"); 5081 5082 schedule(); 5083 5084 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5085 goto end_loop; 5086 5087 if (ha->flags.eeh_busy) { 5088 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5089 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5090 goto end_loop; 5091 } 5092 5093 ha->dpc_active = 1; 5094 5095 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5096 "DPC handler waking up, dpc_flags=0x%lx.\n", 5097 base_vha->dpc_flags); 5098 5099 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5100 break; 5101 5102 qla2x00_do_work(base_vha); 5103 5104 if (IS_P3P_TYPE(ha)) { 5105 if (IS_QLA8044(ha)) { 5106 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5107 &base_vha->dpc_flags)) { 5108 qla8044_idc_lock(ha); 5109 qla8044_wr_direct(base_vha, 5110 QLA8044_CRB_DEV_STATE_INDEX, 5111 QLA8XXX_DEV_FAILED); 5112 qla8044_idc_unlock(ha); 5113 ql_log(ql_log_info, base_vha, 0x4004, 5114 "HW State: FAILED.\n"); 5115 qla8044_device_state_handler(base_vha); 5116 continue; 5117 } 5118 5119 } else { 5120 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5121 &base_vha->dpc_flags)) { 5122 qla82xx_idc_lock(ha); 5123 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5124 QLA8XXX_DEV_FAILED); 5125 qla82xx_idc_unlock(ha); 5126 ql_log(ql_log_info, base_vha, 0x0151, 5127 "HW State: FAILED.\n"); 5128 qla82xx_device_state_handler(base_vha); 5129 continue; 5130 } 5131 } 5132 5133 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5134 &base_vha->dpc_flags)) { 5135 5136 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5137 "FCoE context reset scheduled.\n"); 5138 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5139 &base_vha->dpc_flags))) { 5140 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5141 /* FCoE-ctx reset failed. 5142 * Escalate to chip-reset 5143 */ 5144 set_bit(ISP_ABORT_NEEDED, 5145 &base_vha->dpc_flags); 5146 } 5147 clear_bit(ABORT_ISP_ACTIVE, 5148 &base_vha->dpc_flags); 5149 } 5150 5151 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5152 "FCoE context reset end.\n"); 5153 } 5154 } else if (IS_QLAFX00(ha)) { 5155 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5156 &base_vha->dpc_flags)) { 5157 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5158 "Firmware Reset Recovery\n"); 5159 if (qlafx00_reset_initialize(base_vha)) { 5160 /* Failed. Abort isp later. */ 5161 if (!test_bit(UNLOADING, 5162 &base_vha->dpc_flags)) { 5163 set_bit(ISP_UNRECOVERABLE, 5164 &base_vha->dpc_flags); 5165 ql_dbg(ql_dbg_dpc, base_vha, 5166 0x4021, 5167 "Reset Recovery Failed\n"); 5168 } 5169 } 5170 } 5171 5172 if (test_and_clear_bit(FX00_TARGET_SCAN, 5173 &base_vha->dpc_flags)) { 5174 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5175 "ISPFx00 Target Scan scheduled\n"); 5176 if (qlafx00_rescan_isp(base_vha)) { 5177 if (!test_bit(UNLOADING, 5178 &base_vha->dpc_flags)) 5179 set_bit(ISP_UNRECOVERABLE, 5180 &base_vha->dpc_flags); 5181 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5182 "ISPFx00 Target Scan Failed\n"); 5183 } 5184 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5185 "ISPFx00 Target Scan End\n"); 5186 } 5187 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5188 &base_vha->dpc_flags)) { 5189 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5190 "ISPFx00 Host Info resend scheduled\n"); 5191 qlafx00_fx_disc(base_vha, 5192 &base_vha->hw->mr.fcport, 5193 FXDISC_REG_HOST_INFO); 5194 } 5195 } 5196 5197 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5198 &base_vha->dpc_flags)) { 5199 5200 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5201 "ISP abort scheduled.\n"); 5202 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5203 &base_vha->dpc_flags))) { 5204 5205 if (ha->isp_ops->abort_isp(base_vha)) { 5206 /* failed. retry later */ 5207 set_bit(ISP_ABORT_NEEDED, 5208 &base_vha->dpc_flags); 5209 } 5210 clear_bit(ABORT_ISP_ACTIVE, 5211 &base_vha->dpc_flags); 5212 } 5213 5214 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5215 "ISP abort end.\n"); 5216 } 5217 5218 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5219 &base_vha->dpc_flags)) { 5220 qla2x00_update_fcports(base_vha); 5221 } 5222 5223 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 5224 int ret; 5225 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 5226 if (ret != QLA_SUCCESS) 5227 ql_log(ql_log_warn, base_vha, 0x121, 5228 "Failed to enable receiving of RSCN " 5229 "requests: 0x%x.\n", ret); 5230 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 5231 } 5232 5233 if (IS_QLAFX00(ha)) 5234 goto loop_resync_check; 5235 5236 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5237 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5238 "Quiescence mode scheduled.\n"); 5239 if (IS_P3P_TYPE(ha)) { 5240 if (IS_QLA82XX(ha)) 5241 qla82xx_device_state_handler(base_vha); 5242 if (IS_QLA8044(ha)) 5243 qla8044_device_state_handler(base_vha); 5244 clear_bit(ISP_QUIESCE_NEEDED, 5245 &base_vha->dpc_flags); 5246 if (!ha->flags.quiesce_owner) { 5247 qla2x00_perform_loop_resync(base_vha); 5248 if (IS_QLA82XX(ha)) { 5249 qla82xx_idc_lock(ha); 5250 qla82xx_clear_qsnt_ready( 5251 base_vha); 5252 qla82xx_idc_unlock(ha); 5253 } else if (IS_QLA8044(ha)) { 5254 qla8044_idc_lock(ha); 5255 qla8044_clear_qsnt_ready( 5256 base_vha); 5257 qla8044_idc_unlock(ha); 5258 } 5259 } 5260 } else { 5261 clear_bit(ISP_QUIESCE_NEEDED, 5262 &base_vha->dpc_flags); 5263 qla2x00_quiesce_io(base_vha); 5264 } 5265 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5266 "Quiescence mode end.\n"); 5267 } 5268 5269 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5270 &base_vha->dpc_flags) && 5271 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5272 5273 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5274 "Reset marker scheduled.\n"); 5275 qla2x00_rst_aen(base_vha); 5276 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5277 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5278 "Reset marker end.\n"); 5279 } 5280 5281 /* Retry each device up to login retry count */ 5282 if ((test_and_clear_bit(RELOGIN_NEEDED, 5283 &base_vha->dpc_flags)) && 5284 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5285 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5286 5287 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5288 "Relogin scheduled.\n"); 5289 qla2x00_relogin(base_vha); 5290 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5291 "Relogin end.\n"); 5292 } 5293 loop_resync_check: 5294 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5295 &base_vha->dpc_flags)) { 5296 5297 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5298 "Loop resync scheduled.\n"); 5299 5300 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5301 &base_vha->dpc_flags))) { 5302 5303 qla2x00_loop_resync(base_vha); 5304 5305 clear_bit(LOOP_RESYNC_ACTIVE, 5306 &base_vha->dpc_flags); 5307 } 5308 5309 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5310 "Loop resync end.\n"); 5311 } 5312 5313 if (IS_QLAFX00(ha)) 5314 goto intr_on_check; 5315 5316 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5317 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5318 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5319 qla2xxx_flash_npiv_conf(base_vha); 5320 } 5321 5322 intr_on_check: 5323 if (!ha->interrupts_on) 5324 ha->isp_ops->enable_intrs(ha); 5325 5326 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5327 &base_vha->dpc_flags)) { 5328 if (ha->beacon_blink_led == 1) 5329 ha->isp_ops->beacon_blink(base_vha); 5330 } 5331 5332 if (!IS_QLAFX00(ha)) 5333 qla2x00_do_dpc_all_vps(base_vha); 5334 5335 ha->dpc_active = 0; 5336 end_loop: 5337 set_current_state(TASK_INTERRUPTIBLE); 5338 } /* End of while(1) */ 5339 __set_current_state(TASK_RUNNING); 5340 5341 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5342 "DPC handler exiting.\n"); 5343 5344 /* 5345 * Make sure that nobody tries to wake us up again. 5346 */ 5347 ha->dpc_active = 0; 5348 5349 /* Cleanup any residual CTX SRBs. */ 5350 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5351 5352 return 0; 5353 } 5354 5355 void 5356 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5357 { 5358 struct qla_hw_data *ha = vha->hw; 5359 struct task_struct *t = ha->dpc_thread; 5360 5361 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5362 wake_up_process(t); 5363 } 5364 5365 /* 5366 * qla2x00_rst_aen 5367 * Processes asynchronous reset. 5368 * 5369 * Input: 5370 * ha = adapter block pointer. 5371 */ 5372 static void 5373 qla2x00_rst_aen(scsi_qla_host_t *vha) 5374 { 5375 if (vha->flags.online && !vha->flags.reset_active && 5376 !atomic_read(&vha->loop_down_timer) && 5377 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5378 do { 5379 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5380 5381 /* 5382 * Issue marker command only when we are going to start 5383 * the I/O. 5384 */ 5385 vha->marker_needed = 1; 5386 } while (!atomic_read(&vha->loop_down_timer) && 5387 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5388 } 5389 } 5390 5391 /************************************************************************** 5392 * qla2x00_timer 5393 * 5394 * Description: 5395 * One second timer 5396 * 5397 * Context: Interrupt 5398 ***************************************************************************/ 5399 void 5400 qla2x00_timer(scsi_qla_host_t *vha) 5401 { 5402 unsigned long cpu_flags = 0; 5403 int start_dpc = 0; 5404 int index; 5405 srb_t *sp; 5406 uint16_t w; 5407 struct qla_hw_data *ha = vha->hw; 5408 struct req_que *req; 5409 5410 if (ha->flags.eeh_busy) { 5411 ql_dbg(ql_dbg_timer, vha, 0x6000, 5412 "EEH = %d, restarting timer.\n", 5413 ha->flags.eeh_busy); 5414 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5415 return; 5416 } 5417 5418 /* 5419 * Hardware read to raise pending EEH errors during mailbox waits. If 5420 * the read returns -1 then disable the board. 5421 */ 5422 if (!pci_channel_offline(ha->pdev)) { 5423 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5424 qla2x00_check_reg16_for_disconnect(vha, w); 5425 } 5426 5427 /* Make sure qla82xx_watchdog is run only for physical port */ 5428 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5429 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5430 start_dpc++; 5431 if (IS_QLA82XX(ha)) 5432 qla82xx_watchdog(vha); 5433 else if (IS_QLA8044(ha)) 5434 qla8044_watchdog(vha); 5435 } 5436 5437 if (!vha->vp_idx && IS_QLAFX00(ha)) 5438 qlafx00_timer_routine(vha); 5439 5440 /* Loop down handler. */ 5441 if (atomic_read(&vha->loop_down_timer) > 0 && 5442 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5443 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5444 && vha->flags.online) { 5445 5446 if (atomic_read(&vha->loop_down_timer) == 5447 vha->loop_down_abort_time) { 5448 5449 ql_log(ql_log_info, vha, 0x6008, 5450 "Loop down - aborting the queues before time expires.\n"); 5451 5452 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5453 atomic_set(&vha->loop_state, LOOP_DEAD); 5454 5455 /* 5456 * Schedule an ISP abort to return any FCP2-device 5457 * commands. 5458 */ 5459 /* NPIV - scan physical port only */ 5460 if (!vha->vp_idx) { 5461 spin_lock_irqsave(&ha->hardware_lock, 5462 cpu_flags); 5463 req = ha->req_q_map[0]; 5464 for (index = 1; 5465 index < req->num_outstanding_cmds; 5466 index++) { 5467 fc_port_t *sfcp; 5468 5469 sp = req->outstanding_cmds[index]; 5470 if (!sp) 5471 continue; 5472 if (sp->type != SRB_SCSI_CMD) 5473 continue; 5474 sfcp = sp->fcport; 5475 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5476 continue; 5477 5478 if (IS_QLA82XX(ha)) 5479 set_bit(FCOE_CTX_RESET_NEEDED, 5480 &vha->dpc_flags); 5481 else 5482 set_bit(ISP_ABORT_NEEDED, 5483 &vha->dpc_flags); 5484 break; 5485 } 5486 spin_unlock_irqrestore(&ha->hardware_lock, 5487 cpu_flags); 5488 } 5489 start_dpc++; 5490 } 5491 5492 /* if the loop has been down for 4 minutes, reinit adapter */ 5493 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5494 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5495 ql_log(ql_log_warn, vha, 0x6009, 5496 "Loop down - aborting ISP.\n"); 5497 5498 if (IS_QLA82XX(ha)) 5499 set_bit(FCOE_CTX_RESET_NEEDED, 5500 &vha->dpc_flags); 5501 else 5502 set_bit(ISP_ABORT_NEEDED, 5503 &vha->dpc_flags); 5504 } 5505 } 5506 ql_dbg(ql_dbg_timer, vha, 0x600a, 5507 "Loop down - seconds remaining %d.\n", 5508 atomic_read(&vha->loop_down_timer)); 5509 } 5510 /* Check if beacon LED needs to be blinked for physical host only */ 5511 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5512 /* There is no beacon_blink function for ISP82xx */ 5513 if (!IS_P3P_TYPE(ha)) { 5514 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5515 start_dpc++; 5516 } 5517 } 5518 5519 /* Process any deferred work. */ 5520 if (!list_empty(&vha->work_list)) 5521 start_dpc++; 5522 5523 /* Schedule the DPC routine if needed */ 5524 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5525 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5526 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5527 start_dpc || 5528 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5529 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5530 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5531 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5532 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5533 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5534 ql_dbg(ql_dbg_timer, vha, 0x600b, 5535 "isp_abort_needed=%d loop_resync_needed=%d " 5536 "fcport_update_needed=%d start_dpc=%d " 5537 "reset_marker_needed=%d", 5538 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5539 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5540 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5541 start_dpc, 5542 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5543 ql_dbg(ql_dbg_timer, vha, 0x600c, 5544 "beacon_blink_needed=%d isp_unrecoverable=%d " 5545 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5546 "relogin_needed=%d.\n", 5547 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5548 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5549 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5550 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5551 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5552 qla2xxx_wake_dpc(vha); 5553 } 5554 5555 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5556 } 5557 5558 /* Firmware interface routines. */ 5559 5560 #define FW_BLOBS 11 5561 #define FW_ISP21XX 0 5562 #define FW_ISP22XX 1 5563 #define FW_ISP2300 2 5564 #define FW_ISP2322 3 5565 #define FW_ISP24XX 4 5566 #define FW_ISP25XX 5 5567 #define FW_ISP81XX 6 5568 #define FW_ISP82XX 7 5569 #define FW_ISP2031 8 5570 #define FW_ISP8031 9 5571 #define FW_ISP27XX 10 5572 5573 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5574 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5575 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5576 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5577 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5578 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5579 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5580 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5581 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5582 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5583 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5584 5585 5586 static DEFINE_MUTEX(qla_fw_lock); 5587 5588 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5589 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5590 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5591 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5592 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5593 { .name = FW_FILE_ISP24XX, }, 5594 { .name = FW_FILE_ISP25XX, }, 5595 { .name = FW_FILE_ISP81XX, }, 5596 { .name = FW_FILE_ISP82XX, }, 5597 { .name = FW_FILE_ISP2031, }, 5598 { .name = FW_FILE_ISP8031, }, 5599 { .name = FW_FILE_ISP27XX, }, 5600 }; 5601 5602 struct fw_blob * 5603 qla2x00_request_firmware(scsi_qla_host_t *vha) 5604 { 5605 struct qla_hw_data *ha = vha->hw; 5606 struct fw_blob *blob; 5607 5608 if (IS_QLA2100(ha)) { 5609 blob = &qla_fw_blobs[FW_ISP21XX]; 5610 } else if (IS_QLA2200(ha)) { 5611 blob = &qla_fw_blobs[FW_ISP22XX]; 5612 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5613 blob = &qla_fw_blobs[FW_ISP2300]; 5614 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5615 blob = &qla_fw_blobs[FW_ISP2322]; 5616 } else if (IS_QLA24XX_TYPE(ha)) { 5617 blob = &qla_fw_blobs[FW_ISP24XX]; 5618 } else if (IS_QLA25XX(ha)) { 5619 blob = &qla_fw_blobs[FW_ISP25XX]; 5620 } else if (IS_QLA81XX(ha)) { 5621 blob = &qla_fw_blobs[FW_ISP81XX]; 5622 } else if (IS_QLA82XX(ha)) { 5623 blob = &qla_fw_blobs[FW_ISP82XX]; 5624 } else if (IS_QLA2031(ha)) { 5625 blob = &qla_fw_blobs[FW_ISP2031]; 5626 } else if (IS_QLA8031(ha)) { 5627 blob = &qla_fw_blobs[FW_ISP8031]; 5628 } else if (IS_QLA27XX(ha)) { 5629 blob = &qla_fw_blobs[FW_ISP27XX]; 5630 } else { 5631 return NULL; 5632 } 5633 5634 mutex_lock(&qla_fw_lock); 5635 if (blob->fw) 5636 goto out; 5637 5638 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5639 ql_log(ql_log_warn, vha, 0x0063, 5640 "Failed to load firmware image (%s).\n", blob->name); 5641 blob->fw = NULL; 5642 blob = NULL; 5643 goto out; 5644 } 5645 5646 out: 5647 mutex_unlock(&qla_fw_lock); 5648 return blob; 5649 } 5650 5651 static void 5652 qla2x00_release_firmware(void) 5653 { 5654 int idx; 5655 5656 mutex_lock(&qla_fw_lock); 5657 for (idx = 0; idx < FW_BLOBS; idx++) 5658 release_firmware(qla_fw_blobs[idx].fw); 5659 mutex_unlock(&qla_fw_lock); 5660 } 5661 5662 static pci_ers_result_t 5663 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5664 { 5665 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5666 struct qla_hw_data *ha = vha->hw; 5667 5668 ql_dbg(ql_dbg_aer, vha, 0x9000, 5669 "PCI error detected, state %x.\n", state); 5670 5671 switch (state) { 5672 case pci_channel_io_normal: 5673 ha->flags.eeh_busy = 0; 5674 return PCI_ERS_RESULT_CAN_RECOVER; 5675 case pci_channel_io_frozen: 5676 ha->flags.eeh_busy = 1; 5677 /* For ISP82XX complete any pending mailbox cmd */ 5678 if (IS_QLA82XX(ha)) { 5679 ha->flags.isp82xx_fw_hung = 1; 5680 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5681 qla82xx_clear_pending_mbx(vha); 5682 } 5683 qla2x00_free_irqs(vha); 5684 pci_disable_device(pdev); 5685 /* Return back all IOs */ 5686 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5687 return PCI_ERS_RESULT_NEED_RESET; 5688 case pci_channel_io_perm_failure: 5689 ha->flags.pci_channel_io_perm_failure = 1; 5690 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5691 return PCI_ERS_RESULT_DISCONNECT; 5692 } 5693 return PCI_ERS_RESULT_NEED_RESET; 5694 } 5695 5696 static pci_ers_result_t 5697 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5698 { 5699 int risc_paused = 0; 5700 uint32_t stat; 5701 unsigned long flags; 5702 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5703 struct qla_hw_data *ha = base_vha->hw; 5704 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5705 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5706 5707 if (IS_QLA82XX(ha)) 5708 return PCI_ERS_RESULT_RECOVERED; 5709 5710 spin_lock_irqsave(&ha->hardware_lock, flags); 5711 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5712 stat = RD_REG_DWORD(®->hccr); 5713 if (stat & HCCR_RISC_PAUSE) 5714 risc_paused = 1; 5715 } else if (IS_QLA23XX(ha)) { 5716 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5717 if (stat & HSR_RISC_PAUSED) 5718 risc_paused = 1; 5719 } else if (IS_FWI2_CAPABLE(ha)) { 5720 stat = RD_REG_DWORD(®24->host_status); 5721 if (stat & HSRX_RISC_PAUSED) 5722 risc_paused = 1; 5723 } 5724 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5725 5726 if (risc_paused) { 5727 ql_log(ql_log_info, base_vha, 0x9003, 5728 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5729 ha->isp_ops->fw_dump(base_vha, 0); 5730 5731 return PCI_ERS_RESULT_NEED_RESET; 5732 } else 5733 return PCI_ERS_RESULT_RECOVERED; 5734 } 5735 5736 static uint32_t 5737 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5738 { 5739 uint32_t rval = QLA_FUNCTION_FAILED; 5740 uint32_t drv_active = 0; 5741 struct qla_hw_data *ha = base_vha->hw; 5742 int fn; 5743 struct pci_dev *other_pdev = NULL; 5744 5745 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5746 "Entered %s.\n", __func__); 5747 5748 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5749 5750 if (base_vha->flags.online) { 5751 /* Abort all outstanding commands, 5752 * so as to be requeued later */ 5753 qla2x00_abort_isp_cleanup(base_vha); 5754 } 5755 5756 5757 fn = PCI_FUNC(ha->pdev->devfn); 5758 while (fn > 0) { 5759 fn--; 5760 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5761 "Finding pci device at function = 0x%x.\n", fn); 5762 other_pdev = 5763 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5764 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5765 fn)); 5766 5767 if (!other_pdev) 5768 continue; 5769 if (atomic_read(&other_pdev->enable_cnt)) { 5770 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5771 "Found PCI func available and enable at 0x%x.\n", 5772 fn); 5773 pci_dev_put(other_pdev); 5774 break; 5775 } 5776 pci_dev_put(other_pdev); 5777 } 5778 5779 if (!fn) { 5780 /* Reset owner */ 5781 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5782 "This devfn is reset owner = 0x%x.\n", 5783 ha->pdev->devfn); 5784 qla82xx_idc_lock(ha); 5785 5786 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5787 QLA8XXX_DEV_INITIALIZING); 5788 5789 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5790 QLA82XX_IDC_VERSION); 5791 5792 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5793 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5794 "drv_active = 0x%x.\n", drv_active); 5795 5796 qla82xx_idc_unlock(ha); 5797 /* Reset if device is not already reset 5798 * drv_active would be 0 if a reset has already been done 5799 */ 5800 if (drv_active) 5801 rval = qla82xx_start_firmware(base_vha); 5802 else 5803 rval = QLA_SUCCESS; 5804 qla82xx_idc_lock(ha); 5805 5806 if (rval != QLA_SUCCESS) { 5807 ql_log(ql_log_info, base_vha, 0x900b, 5808 "HW State: FAILED.\n"); 5809 qla82xx_clear_drv_active(ha); 5810 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5811 QLA8XXX_DEV_FAILED); 5812 } else { 5813 ql_log(ql_log_info, base_vha, 0x900c, 5814 "HW State: READY.\n"); 5815 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5816 QLA8XXX_DEV_READY); 5817 qla82xx_idc_unlock(ha); 5818 ha->flags.isp82xx_fw_hung = 0; 5819 rval = qla82xx_restart_isp(base_vha); 5820 qla82xx_idc_lock(ha); 5821 /* Clear driver state register */ 5822 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5823 qla82xx_set_drv_active(base_vha); 5824 } 5825 qla82xx_idc_unlock(ha); 5826 } else { 5827 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5828 "This devfn is not reset owner = 0x%x.\n", 5829 ha->pdev->devfn); 5830 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5831 QLA8XXX_DEV_READY)) { 5832 ha->flags.isp82xx_fw_hung = 0; 5833 rval = qla82xx_restart_isp(base_vha); 5834 qla82xx_idc_lock(ha); 5835 qla82xx_set_drv_active(base_vha); 5836 qla82xx_idc_unlock(ha); 5837 } 5838 } 5839 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5840 5841 return rval; 5842 } 5843 5844 static pci_ers_result_t 5845 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5846 { 5847 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5848 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5849 struct qla_hw_data *ha = base_vha->hw; 5850 struct rsp_que *rsp; 5851 int rc, retries = 10; 5852 5853 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5854 "Slot Reset.\n"); 5855 5856 /* Workaround: qla2xxx driver which access hardware earlier 5857 * needs error state to be pci_channel_io_online. 5858 * Otherwise mailbox command timesout. 5859 */ 5860 pdev->error_state = pci_channel_io_normal; 5861 5862 pci_restore_state(pdev); 5863 5864 /* pci_restore_state() clears the saved_state flag of the device 5865 * save restored state which resets saved_state flag 5866 */ 5867 pci_save_state(pdev); 5868 5869 if (ha->mem_only) 5870 rc = pci_enable_device_mem(pdev); 5871 else 5872 rc = pci_enable_device(pdev); 5873 5874 if (rc) { 5875 ql_log(ql_log_warn, base_vha, 0x9005, 5876 "Can't re-enable PCI device after reset.\n"); 5877 goto exit_slot_reset; 5878 } 5879 5880 rsp = ha->rsp_q_map[0]; 5881 if (qla2x00_request_irqs(ha, rsp)) 5882 goto exit_slot_reset; 5883 5884 if (ha->isp_ops->pci_config(base_vha)) 5885 goto exit_slot_reset; 5886 5887 if (IS_QLA82XX(ha)) { 5888 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5889 ret = PCI_ERS_RESULT_RECOVERED; 5890 goto exit_slot_reset; 5891 } else 5892 goto exit_slot_reset; 5893 } 5894 5895 while (ha->flags.mbox_busy && retries--) 5896 msleep(1000); 5897 5898 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5899 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5900 ret = PCI_ERS_RESULT_RECOVERED; 5901 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5902 5903 5904 exit_slot_reset: 5905 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5906 "slot_reset return %x.\n", ret); 5907 5908 return ret; 5909 } 5910 5911 static void 5912 qla2xxx_pci_resume(struct pci_dev *pdev) 5913 { 5914 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5915 struct qla_hw_data *ha = base_vha->hw; 5916 int ret; 5917 5918 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5919 "pci_resume.\n"); 5920 5921 ret = qla2x00_wait_for_hba_online(base_vha); 5922 if (ret != QLA_SUCCESS) { 5923 ql_log(ql_log_fatal, base_vha, 0x9002, 5924 "The device failed to resume I/O from slot/link_reset.\n"); 5925 } 5926 5927 pci_cleanup_aer_uncorrect_error_status(pdev); 5928 5929 ha->flags.eeh_busy = 0; 5930 } 5931 5932 static void 5933 qla83xx_disable_laser(scsi_qla_host_t *vha) 5934 { 5935 uint32_t reg, data, fn; 5936 struct qla_hw_data *ha = vha->hw; 5937 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5938 5939 /* pci func #/port # */ 5940 ql_dbg(ql_dbg_init, vha, 0x004b, 5941 "Disabling Laser for hba: %p\n", vha); 5942 5943 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5944 (BIT_15|BIT_14|BIT_13|BIT_12)); 5945 5946 fn = (fn >> 12); 5947 5948 if (fn & 1) 5949 reg = PORT_1_2031; 5950 else 5951 reg = PORT_0_2031; 5952 5953 data = LASER_OFF_2031; 5954 5955 qla83xx_wr_reg(vha, reg, data); 5956 } 5957 5958 static const struct pci_error_handlers qla2xxx_err_handler = { 5959 .error_detected = qla2xxx_pci_error_detected, 5960 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5961 .slot_reset = qla2xxx_pci_slot_reset, 5962 .resume = qla2xxx_pci_resume, 5963 }; 5964 5965 static struct pci_device_id qla2xxx_pci_tbl[] = { 5966 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5967 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5968 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5969 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5970 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5971 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5972 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5973 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5974 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5975 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5976 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5985 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5986 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5987 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 5988 { 0 }, 5989 }; 5990 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5991 5992 static struct pci_driver qla2xxx_pci_driver = { 5993 .name = QLA2XXX_DRIVER_NAME, 5994 .driver = { 5995 .owner = THIS_MODULE, 5996 }, 5997 .id_table = qla2xxx_pci_tbl, 5998 .probe = qla2x00_probe_one, 5999 .remove = qla2x00_remove_one, 6000 .shutdown = qla2x00_shutdown, 6001 .err_handler = &qla2xxx_err_handler, 6002 }; 6003 6004 static const struct file_operations apidev_fops = { 6005 .owner = THIS_MODULE, 6006 .llseek = noop_llseek, 6007 }; 6008 6009 /** 6010 * qla2x00_module_init - Module initialization. 6011 **/ 6012 static int __init 6013 qla2x00_module_init(void) 6014 { 6015 int ret = 0; 6016 6017 /* Allocate cache for SRBs. */ 6018 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6019 SLAB_HWCACHE_ALIGN, NULL); 6020 if (srb_cachep == NULL) { 6021 ql_log(ql_log_fatal, NULL, 0x0001, 6022 "Unable to allocate SRB cache...Failing load!.\n"); 6023 return -ENOMEM; 6024 } 6025 6026 /* Initialize target kmem_cache and mem_pools */ 6027 ret = qlt_init(); 6028 if (ret < 0) { 6029 kmem_cache_destroy(srb_cachep); 6030 return ret; 6031 } else if (ret > 0) { 6032 /* 6033 * If initiator mode is explictly disabled by qlt_init(), 6034 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6035 * performing scsi_scan_target() during LOOP UP event. 6036 */ 6037 qla2xxx_transport_functions.disable_target_scan = 1; 6038 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6039 } 6040 6041 /* Derive version string. */ 6042 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6043 if (ql2xextended_error_logging) 6044 strcat(qla2x00_version_str, "-debug"); 6045 6046 qla2xxx_transport_template = 6047 fc_attach_transport(&qla2xxx_transport_functions); 6048 if (!qla2xxx_transport_template) { 6049 kmem_cache_destroy(srb_cachep); 6050 ql_log(ql_log_fatal, NULL, 0x0002, 6051 "fc_attach_transport failed...Failing load!.\n"); 6052 qlt_exit(); 6053 return -ENODEV; 6054 } 6055 6056 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6057 if (apidev_major < 0) { 6058 ql_log(ql_log_fatal, NULL, 0x0003, 6059 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6060 } 6061 6062 qla2xxx_transport_vport_template = 6063 fc_attach_transport(&qla2xxx_transport_vport_functions); 6064 if (!qla2xxx_transport_vport_template) { 6065 kmem_cache_destroy(srb_cachep); 6066 qlt_exit(); 6067 fc_release_transport(qla2xxx_transport_template); 6068 ql_log(ql_log_fatal, NULL, 0x0004, 6069 "fc_attach_transport vport failed...Failing load!.\n"); 6070 return -ENODEV; 6071 } 6072 ql_log(ql_log_info, NULL, 0x0005, 6073 "QLogic Fibre Channel HBA Driver: %s.\n", 6074 qla2x00_version_str); 6075 ret = pci_register_driver(&qla2xxx_pci_driver); 6076 if (ret) { 6077 kmem_cache_destroy(srb_cachep); 6078 qlt_exit(); 6079 fc_release_transport(qla2xxx_transport_template); 6080 fc_release_transport(qla2xxx_transport_vport_template); 6081 ql_log(ql_log_fatal, NULL, 0x0006, 6082 "pci_register_driver failed...ret=%d Failing load!.\n", 6083 ret); 6084 } 6085 return ret; 6086 } 6087 6088 /** 6089 * qla2x00_module_exit - Module cleanup. 6090 **/ 6091 static void __exit 6092 qla2x00_module_exit(void) 6093 { 6094 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6095 pci_unregister_driver(&qla2xxx_pci_driver); 6096 qla2x00_release_firmware(); 6097 kmem_cache_destroy(srb_cachep); 6098 qlt_exit(); 6099 if (ctx_cachep) 6100 kmem_cache_destroy(ctx_cachep); 6101 fc_release_transport(qla2xxx_transport_template); 6102 fc_release_transport(qla2xxx_transport_vport_template); 6103 } 6104 6105 module_init(qla2x00_module_init); 6106 module_exit(qla2x00_module_exit); 6107 6108 MODULE_AUTHOR("QLogic Corporation"); 6109 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6110 MODULE_LICENSE("GPL"); 6111 MODULE_VERSION(QLA2XXX_VERSION); 6112 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6113 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6114 MODULE_FIRMWARE(FW_FILE_ISP2300); 6115 MODULE_FIRMWARE(FW_FILE_ISP2322); 6116 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6117 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6118