1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 int ql2xfulldump_on_mpifail; 39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 41 "Set this to take full dump on MPI hang."); 42 43 int ql2xenforce_iocb_limit = 1; 44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 47 48 /* 49 * CT6 CTX allocation cache 50 */ 51 static struct kmem_cache *ctx_cachep; 52 /* 53 * error level for logging 54 */ 55 uint ql_errlev = 0x8001; 56 57 int ql2xsecenable; 58 module_param(ql2xsecenable, int, S_IRUGO); 59 MODULE_PARM_DESC(ql2xsecenable, 60 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 61 62 static int ql2xenableclass2; 63 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 64 MODULE_PARM_DESC(ql2xenableclass2, 65 "Specify if Class 2 operations are supported from the very " 66 "beginning. Default is 0 - class 2 not supported."); 67 68 69 int ql2xlogintimeout = 20; 70 module_param(ql2xlogintimeout, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xlogintimeout, 72 "Login timeout value in seconds."); 73 74 int qlport_down_retry; 75 module_param(qlport_down_retry, int, S_IRUGO); 76 MODULE_PARM_DESC(qlport_down_retry, 77 "Maximum number of command retries to a port that returns " 78 "a PORT-DOWN status."); 79 80 int ql2xplogiabsentdevice; 81 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(ql2xplogiabsentdevice, 83 "Option to enable PLOGI to devices that are not present after " 84 "a Fabric scan. This is needed for several broken switches. " 85 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 86 87 int ql2xloginretrycount; 88 module_param(ql2xloginretrycount, int, S_IRUGO); 89 MODULE_PARM_DESC(ql2xloginretrycount, 90 "Specify an alternate value for the NVRAM login retry count."); 91 92 int ql2xallocfwdump = 1; 93 module_param(ql2xallocfwdump, int, S_IRUGO); 94 MODULE_PARM_DESC(ql2xallocfwdump, 95 "Option to enable allocation of memory for a firmware dump " 96 "during HBA initialization. Memory allocation requirements " 97 "vary by ISP type. Default is 1 - allocate memory."); 98 99 int ql2xextended_error_logging; 100 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 101 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 102 MODULE_PARM_DESC(ql2xextended_error_logging, 103 "Option to enable extended error logging,\n" 104 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 105 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 106 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 107 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 108 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 109 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 110 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 111 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 112 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 113 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 114 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 115 "\t\t0x1e400000 - Preferred value for capturing essential " 116 "debug information (equivalent to old " 117 "ql2xextended_error_logging=1).\n" 118 "\t\tDo LOGICAL OR of the value to enable more than one level"); 119 120 int ql2xshiftctondsd = 6; 121 module_param(ql2xshiftctondsd, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xshiftctondsd, 123 "Set to control shifting of command type processing " 124 "based on total number of SG elements."); 125 126 int ql2xfdmienable = 1; 127 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 128 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 129 MODULE_PARM_DESC(ql2xfdmienable, 130 "Enables FDMI registrations. " 131 "0 - no FDMI registrations. " 132 "1 - provide FDMI registrations (default)."); 133 134 #define MAX_Q_DEPTH 64 135 static int ql2xmaxqdepth = MAX_Q_DEPTH; 136 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 137 MODULE_PARM_DESC(ql2xmaxqdepth, 138 "Maximum queue depth to set for each LUN. " 139 "Default is 64."); 140 141 int ql2xenabledif = 2; 142 module_param(ql2xenabledif, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xenabledif, 144 " Enable T10-CRC-DIF:\n" 145 " Default is 2.\n" 146 " 0 -- No DIF Support\n" 147 " 1 -- Enable DIF for all types\n" 148 " 2 -- Enable DIF for all types, except Type 0.\n"); 149 150 #if (IS_ENABLED(CONFIG_NVME_FC)) 151 int ql2xnvmeenable = 1; 152 #else 153 int ql2xnvmeenable; 154 #endif 155 module_param(ql2xnvmeenable, int, 0644); 156 MODULE_PARM_DESC(ql2xnvmeenable, 157 "Enables NVME support. " 158 "0 - no NVMe. Default is Y"); 159 160 int ql2xenablehba_err_chk = 2; 161 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 162 MODULE_PARM_DESC(ql2xenablehba_err_chk, 163 " Enable T10-CRC-DIF Error isolation by HBA:\n" 164 " Default is 2.\n" 165 " 0 -- Error isolation disabled\n" 166 " 1 -- Error isolation enabled only for DIX Type 0\n" 167 " 2 -- Error isolation enabled for all Types\n"); 168 169 int ql2xiidmaenable = 1; 170 module_param(ql2xiidmaenable, int, S_IRUGO); 171 MODULE_PARM_DESC(ql2xiidmaenable, 172 "Enables iIDMA settings " 173 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 174 175 int ql2xmqsupport = 1; 176 module_param(ql2xmqsupport, int, S_IRUGO); 177 MODULE_PARM_DESC(ql2xmqsupport, 178 "Enable on demand multiple queue pairs support " 179 "Default is 1 for supported. " 180 "Set it to 0 to turn off mq qpair support."); 181 182 int ql2xfwloadbin; 183 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 184 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 185 MODULE_PARM_DESC(ql2xfwloadbin, 186 "Option to specify location from which to load ISP firmware:.\n" 187 " 2 -- load firmware via the request_firmware() (hotplug).\n" 188 " interface.\n" 189 " 1 -- load firmware from flash.\n" 190 " 0 -- use default semantics.\n"); 191 192 int ql2xetsenable; 193 module_param(ql2xetsenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xetsenable, 195 "Enables firmware ETS burst." 196 "Default is 0 - skip ETS enablement."); 197 198 int ql2xdbwr = 1; 199 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdbwr, 201 "Option to specify scheme for request queue posting.\n" 202 " 0 -- Regular doorbell.\n" 203 " 1 -- CAMRAM doorbell (faster).\n"); 204 205 int ql2xgffidenable; 206 module_param(ql2xgffidenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xgffidenable, 208 "Enables GFF_ID checks of port type. " 209 "Default is 0 - Do not use GFF_ID information."); 210 211 int ql2xasynctmfenable = 1; 212 module_param(ql2xasynctmfenable, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xasynctmfenable, 214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 215 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 216 217 int ql2xdontresethba; 218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 219 MODULE_PARM_DESC(ql2xdontresethba, 220 "Option to specify reset behaviour.\n" 221 " 0 (Default) -- Reset on failure.\n" 222 " 1 -- Do not reset on failure.\n"); 223 224 uint64_t ql2xmaxlun = MAX_LUNS; 225 module_param(ql2xmaxlun, ullong, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmaxlun, 227 "Defines the maximum LU number to register with the SCSI " 228 "midlayer. Default is 65535."); 229 230 int ql2xmdcapmask = 0x1F; 231 module_param(ql2xmdcapmask, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdcapmask, 233 "Set the Minidump driver capture mask level. " 234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 235 236 int ql2xmdenable = 1; 237 module_param(ql2xmdenable, int, S_IRUGO); 238 MODULE_PARM_DESC(ql2xmdenable, 239 "Enable/disable MiniDump. " 240 "0 - MiniDump disabled. " 241 "1 (Default) - MiniDump enabled."); 242 243 int ql2xexlogins; 244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 245 MODULE_PARM_DESC(ql2xexlogins, 246 "Number of extended Logins. " 247 "0 (Default)- Disabled."); 248 249 int ql2xexchoffld = 1024; 250 module_param(ql2xexchoffld, uint, 0644); 251 MODULE_PARM_DESC(ql2xexchoffld, 252 "Number of target exchanges."); 253 254 int ql2xiniexchg = 1024; 255 module_param(ql2xiniexchg, uint, 0644); 256 MODULE_PARM_DESC(ql2xiniexchg, 257 "Number of initiator exchanges."); 258 259 int ql2xfwholdabts; 260 module_param(ql2xfwholdabts, int, S_IRUGO); 261 MODULE_PARM_DESC(ql2xfwholdabts, 262 "Allow FW to hold status IOCB until ABTS rsp received. " 263 "0 (Default) Do not set fw option. " 264 "1 - Set fw option to hold ABTS."); 265 266 int ql2xmvasynctoatio = 1; 267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 268 MODULE_PARM_DESC(ql2xmvasynctoatio, 269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 270 "0 (Default). Do not move IOCBs" 271 "1 - Move IOCBs."); 272 273 int ql2xautodetectsfp = 1; 274 module_param(ql2xautodetectsfp, int, 0444); 275 MODULE_PARM_DESC(ql2xautodetectsfp, 276 "Detect SFP range and set appropriate distance.\n" 277 "1 (Default): Enable\n"); 278 279 int ql2xenablemsix = 1; 280 module_param(ql2xenablemsix, int, 0444); 281 MODULE_PARM_DESC(ql2xenablemsix, 282 "Set to enable MSI or MSI-X interrupt mechanism.\n" 283 " Default is 1, enable MSI-X interrupt mechanism.\n" 284 " 0 -- enable traditional pin-based mechanism.\n" 285 " 1 -- enable MSI-X interrupt mechanism.\n" 286 " 2 -- enable MSI interrupt mechanism.\n"); 287 288 int qla2xuseresexchforels; 289 module_param(qla2xuseresexchforels, int, 0444); 290 MODULE_PARM_DESC(qla2xuseresexchforels, 291 "Reserve 1/2 of emergency exchanges for ELS.\n" 292 " 0 (default): disabled"); 293 294 static int ql2xprotmask; 295 module_param(ql2xprotmask, int, 0644); 296 MODULE_PARM_DESC(ql2xprotmask, 297 "Override DIF/DIX protection capabilities mask\n" 298 "Default is 0 which sets protection mask based on " 299 "capabilities reported by HBA firmware.\n"); 300 301 static int ql2xprotguard; 302 module_param(ql2xprotguard, int, 0644); 303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 304 " 0 -- Let HBA firmware decide\n" 305 " 1 -- Force T10 CRC\n" 306 " 2 -- Force IP checksum\n"); 307 308 int ql2xdifbundlinginternalbuffers; 309 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 311 "Force using internal buffers for DIF information\n" 312 "0 (Default). Based on check.\n" 313 "1 Force using internal buffers\n"); 314 315 int ql2xsmartsan; 316 module_param(ql2xsmartsan, int, 0444); 317 module_param_named(smartsan, ql2xsmartsan, int, 0444); 318 MODULE_PARM_DESC(ql2xsmartsan, 319 "Send SmartSAN Management Attributes for FDMI Registration." 320 " Default is 0 - No SmartSAN registration," 321 " 1 - Register SmartSAN Management Attributes."); 322 323 int ql2xrdpenable; 324 module_param(ql2xrdpenable, int, 0444); 325 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 326 MODULE_PARM_DESC(ql2xrdpenable, 327 "Enables RDP responses. " 328 "0 - no RDP responses (default). " 329 "1 - provide RDP responses."); 330 int ql2xabts_wait_nvme = 1; 331 module_param(ql2xabts_wait_nvme, int, 0444); 332 MODULE_PARM_DESC(ql2xabts_wait_nvme, 333 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 334 335 336 static void qla2x00_clear_drv_active(struct qla_hw_data *); 337 static void qla2x00_free_device(scsi_qla_host_t *); 338 static int qla2xxx_map_queues(struct Scsi_Host *shost); 339 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 340 341 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 342 module_param(ql2xnvme_queues, uint, S_IRUGO); 343 MODULE_PARM_DESC(ql2xnvme_queues, 344 "Number of NVMe Queues that can be configured.\n" 345 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 346 "1 - Minimum number of queues supported\n" 347 "8 - Default value"); 348 349 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 350 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 351 352 /* TODO Convert to inlines 353 * 354 * Timer routines 355 */ 356 357 __inline__ void 358 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 359 { 360 timer_setup(&vha->timer, qla2x00_timer, 0); 361 vha->timer.expires = jiffies + interval * HZ; 362 add_timer(&vha->timer); 363 vha->timer_active = 1; 364 } 365 366 static inline void 367 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 368 { 369 /* Currently used for 82XX only. */ 370 if (vha->device_flags & DFLG_DEV_FAILED) { 371 ql_dbg(ql_dbg_timer, vha, 0x600d, 372 "Device in a failed state, returning.\n"); 373 return; 374 } 375 376 mod_timer(&vha->timer, jiffies + interval * HZ); 377 } 378 379 static __inline__ void 380 qla2x00_stop_timer(scsi_qla_host_t *vha) 381 { 382 del_timer_sync(&vha->timer); 383 vha->timer_active = 0; 384 } 385 386 static int qla2x00_do_dpc(void *data); 387 388 static void qla2x00_rst_aen(scsi_qla_host_t *); 389 390 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 391 struct req_que **, struct rsp_que **); 392 static void qla2x00_free_fw_dump(struct qla_hw_data *); 393 static void qla2x00_mem_free(struct qla_hw_data *); 394 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 395 struct qla_qpair *qpair); 396 397 /* -------------------------------------------------------------------------- */ 398 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 399 struct rsp_que *rsp) 400 { 401 struct qla_hw_data *ha = vha->hw; 402 403 rsp->qpair = ha->base_qpair; 404 rsp->req = req; 405 ha->base_qpair->hw = ha; 406 ha->base_qpair->req = req; 407 ha->base_qpair->rsp = rsp; 408 ha->base_qpair->vha = vha; 409 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 410 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 411 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 412 ha->base_qpair->srb_mempool = ha->srb_mempool; 413 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 414 ha->base_qpair->enable_class_2 = ql2xenableclass2; 415 /* init qpair to this cpu. Will adjust at run time. */ 416 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 417 ha->base_qpair->pdev = ha->pdev; 418 419 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 420 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 421 } 422 423 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 424 struct rsp_que *rsp) 425 { 426 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 427 428 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 429 GFP_KERNEL); 430 if (!ha->req_q_map) { 431 ql_log(ql_log_fatal, vha, 0x003b, 432 "Unable to allocate memory for request queue ptrs.\n"); 433 goto fail_req_map; 434 } 435 436 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 437 GFP_KERNEL); 438 if (!ha->rsp_q_map) { 439 ql_log(ql_log_fatal, vha, 0x003c, 440 "Unable to allocate memory for response queue ptrs.\n"); 441 goto fail_rsp_map; 442 } 443 444 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 445 if (ha->base_qpair == NULL) { 446 ql_log(ql_log_warn, vha, 0x00e0, 447 "Failed to allocate base queue pair memory.\n"); 448 goto fail_base_qpair; 449 } 450 451 qla_init_base_qpair(vha, req, rsp); 452 453 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 454 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 455 GFP_KERNEL); 456 if (!ha->queue_pair_map) { 457 ql_log(ql_log_fatal, vha, 0x0180, 458 "Unable to allocate memory for queue pair ptrs.\n"); 459 goto fail_qpair_map; 460 } 461 } 462 463 /* 464 * Make sure we record at least the request and response queue zero in 465 * case we need to free them if part of the probe fails. 466 */ 467 ha->rsp_q_map[0] = rsp; 468 ha->req_q_map[0] = req; 469 set_bit(0, ha->rsp_qid_map); 470 set_bit(0, ha->req_qid_map); 471 return 0; 472 473 fail_qpair_map: 474 kfree(ha->base_qpair); 475 ha->base_qpair = NULL; 476 fail_base_qpair: 477 kfree(ha->rsp_q_map); 478 ha->rsp_q_map = NULL; 479 fail_rsp_map: 480 kfree(ha->req_q_map); 481 ha->req_q_map = NULL; 482 fail_req_map: 483 return -ENOMEM; 484 } 485 486 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 487 { 488 if (IS_QLAFX00(ha)) { 489 if (req && req->ring_fx00) 490 dma_free_coherent(&ha->pdev->dev, 491 (req->length_fx00 + 1) * sizeof(request_t), 492 req->ring_fx00, req->dma_fx00); 493 } else if (req && req->ring) 494 dma_free_coherent(&ha->pdev->dev, 495 (req->length + 1) * sizeof(request_t), 496 req->ring, req->dma); 497 498 if (req) 499 kfree(req->outstanding_cmds); 500 501 kfree(req); 502 } 503 504 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 505 { 506 if (IS_QLAFX00(ha)) { 507 if (rsp && rsp->ring_fx00) 508 dma_free_coherent(&ha->pdev->dev, 509 (rsp->length_fx00 + 1) * sizeof(request_t), 510 rsp->ring_fx00, rsp->dma_fx00); 511 } else if (rsp && rsp->ring) { 512 dma_free_coherent(&ha->pdev->dev, 513 (rsp->length + 1) * sizeof(response_t), 514 rsp->ring, rsp->dma); 515 } 516 kfree(rsp); 517 } 518 519 static void qla2x00_free_queues(struct qla_hw_data *ha) 520 { 521 struct req_que *req; 522 struct rsp_que *rsp; 523 int cnt; 524 unsigned long flags; 525 526 if (ha->queue_pair_map) { 527 kfree(ha->queue_pair_map); 528 ha->queue_pair_map = NULL; 529 } 530 if (ha->base_qpair) { 531 kfree(ha->base_qpair); 532 ha->base_qpair = NULL; 533 } 534 535 spin_lock_irqsave(&ha->hardware_lock, flags); 536 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 537 if (!test_bit(cnt, ha->req_qid_map)) 538 continue; 539 540 req = ha->req_q_map[cnt]; 541 clear_bit(cnt, ha->req_qid_map); 542 ha->req_q_map[cnt] = NULL; 543 544 spin_unlock_irqrestore(&ha->hardware_lock, flags); 545 qla2x00_free_req_que(ha, req); 546 spin_lock_irqsave(&ha->hardware_lock, flags); 547 } 548 spin_unlock_irqrestore(&ha->hardware_lock, flags); 549 550 kfree(ha->req_q_map); 551 ha->req_q_map = NULL; 552 553 554 spin_lock_irqsave(&ha->hardware_lock, flags); 555 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 556 if (!test_bit(cnt, ha->rsp_qid_map)) 557 continue; 558 559 rsp = ha->rsp_q_map[cnt]; 560 clear_bit(cnt, ha->rsp_qid_map); 561 ha->rsp_q_map[cnt] = NULL; 562 spin_unlock_irqrestore(&ha->hardware_lock, flags); 563 qla2x00_free_rsp_que(ha, rsp); 564 spin_lock_irqsave(&ha->hardware_lock, flags); 565 } 566 spin_unlock_irqrestore(&ha->hardware_lock, flags); 567 568 kfree(ha->rsp_q_map); 569 ha->rsp_q_map = NULL; 570 } 571 572 static char * 573 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 574 { 575 struct qla_hw_data *ha = vha->hw; 576 static const char *const pci_bus_modes[] = { 577 "33", "66", "100", "133", 578 }; 579 uint16_t pci_bus; 580 581 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 582 if (pci_bus) { 583 snprintf(str, str_len, "PCI-X (%s MHz)", 584 pci_bus_modes[pci_bus]); 585 } else { 586 pci_bus = (ha->pci_attr & BIT_8) >> 8; 587 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 588 } 589 590 return str; 591 } 592 593 static char * 594 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 595 { 596 static const char *const pci_bus_modes[] = { 597 "33", "66", "100", "133", 598 }; 599 struct qla_hw_data *ha = vha->hw; 600 uint32_t pci_bus; 601 602 if (pci_is_pcie(ha->pdev)) { 603 uint32_t lstat, lspeed, lwidth; 604 const char *speed_str; 605 606 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 607 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 608 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 609 610 switch (lspeed) { 611 case 1: 612 speed_str = "2.5GT/s"; 613 break; 614 case 2: 615 speed_str = "5.0GT/s"; 616 break; 617 case 3: 618 speed_str = "8.0GT/s"; 619 break; 620 case 4: 621 speed_str = "16.0GT/s"; 622 break; 623 default: 624 speed_str = "<unknown>"; 625 break; 626 } 627 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 628 629 return str; 630 } 631 632 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 633 if (pci_bus == 0 || pci_bus == 8) 634 snprintf(str, str_len, "PCI (%s MHz)", 635 pci_bus_modes[pci_bus >> 3]); 636 else 637 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 638 pci_bus & 4 ? 2 : 1, 639 pci_bus_modes[pci_bus & 3]); 640 641 return str; 642 } 643 644 static char * 645 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 646 { 647 char un_str[10]; 648 struct qla_hw_data *ha = vha->hw; 649 650 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 651 ha->fw_minor_version, ha->fw_subminor_version); 652 653 if (ha->fw_attributes & BIT_9) { 654 strcat(str, "FLX"); 655 return (str); 656 } 657 658 switch (ha->fw_attributes & 0xFF) { 659 case 0x7: 660 strcat(str, "EF"); 661 break; 662 case 0x17: 663 strcat(str, "TP"); 664 break; 665 case 0x37: 666 strcat(str, "IP"); 667 break; 668 case 0x77: 669 strcat(str, "VI"); 670 break; 671 default: 672 sprintf(un_str, "(%x)", ha->fw_attributes); 673 strcat(str, un_str); 674 break; 675 } 676 if (ha->fw_attributes & 0x100) 677 strcat(str, "X"); 678 679 return (str); 680 } 681 682 static char * 683 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 684 { 685 struct qla_hw_data *ha = vha->hw; 686 687 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 688 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 689 return str; 690 } 691 692 void qla2x00_sp_free_dma(srb_t *sp) 693 { 694 struct qla_hw_data *ha = sp->vha->hw; 695 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 696 697 if (sp->flags & SRB_DMA_VALID) { 698 scsi_dma_unmap(cmd); 699 sp->flags &= ~SRB_DMA_VALID; 700 } 701 702 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 703 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 704 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 705 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 706 } 707 708 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 709 /* List assured to be having elements */ 710 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 711 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 712 } 713 714 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 715 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 716 717 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 718 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 719 } 720 721 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 722 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 723 724 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 725 ctx1->fcp_cmnd_dma); 726 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 727 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 728 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 729 mempool_free(ctx1, ha->ctx_mempool); 730 } 731 } 732 733 void qla2x00_sp_compl(srb_t *sp, int res) 734 { 735 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 736 struct completion *comp = sp->comp; 737 738 /* kref: INIT */ 739 kref_put(&sp->cmd_kref, qla2x00_sp_release); 740 cmd->result = res; 741 sp->type = 0; 742 scsi_done(cmd); 743 if (comp) 744 complete(comp); 745 } 746 747 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 748 { 749 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 750 struct qla_hw_data *ha = sp->fcport->vha->hw; 751 752 if (sp->flags & SRB_DMA_VALID) { 753 scsi_dma_unmap(cmd); 754 sp->flags &= ~SRB_DMA_VALID; 755 } 756 757 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 758 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 759 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 760 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 761 } 762 763 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 764 /* List assured to be having elements */ 765 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 766 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 767 } 768 769 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 770 struct crc_context *difctx = sp->u.scmd.crc_ctx; 771 struct dsd_dma *dif_dsd, *nxt_dsd; 772 773 list_for_each_entry_safe(dif_dsd, nxt_dsd, 774 &difctx->ldif_dma_hndl_list, list) { 775 list_del(&dif_dsd->list); 776 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 777 dif_dsd->dsd_list_dma); 778 kfree(dif_dsd); 779 difctx->no_dif_bundl--; 780 } 781 782 list_for_each_entry_safe(dif_dsd, nxt_dsd, 783 &difctx->ldif_dsd_list, list) { 784 list_del(&dif_dsd->list); 785 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 786 dif_dsd->dsd_list_dma); 787 kfree(dif_dsd); 788 difctx->no_ldif_dsd--; 789 } 790 791 if (difctx->no_ldif_dsd) { 792 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 793 "%s: difctx->no_ldif_dsd=%x\n", 794 __func__, difctx->no_ldif_dsd); 795 } 796 797 if (difctx->no_dif_bundl) { 798 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 799 "%s: difctx->no_dif_bundl=%x\n", 800 __func__, difctx->no_dif_bundl); 801 } 802 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 803 } 804 805 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 806 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 807 808 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 809 ctx1->fcp_cmnd_dma); 810 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 811 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 812 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 813 mempool_free(ctx1, ha->ctx_mempool); 814 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 815 } 816 817 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 818 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 819 820 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 821 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 822 } 823 } 824 825 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 826 { 827 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 828 struct completion *comp = sp->comp; 829 830 /* ref: INIT */ 831 kref_put(&sp->cmd_kref, qla2x00_sp_release); 832 cmd->result = res; 833 sp->type = 0; 834 scsi_done(cmd); 835 if (comp) 836 complete(comp); 837 } 838 839 static int 840 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 841 { 842 scsi_qla_host_t *vha = shost_priv(host); 843 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 844 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 845 struct qla_hw_data *ha = vha->hw; 846 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 847 srb_t *sp; 848 int rval; 849 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 851 WARN_ON_ONCE(!rport)) { 852 cmd->result = DID_NO_CONNECT << 16; 853 goto qc24_fail_command; 854 } 855 856 if (ha->mqenable) { 857 uint32_t tag; 858 uint16_t hwq; 859 struct qla_qpair *qpair = NULL; 860 861 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 862 hwq = blk_mq_unique_tag_to_hwq(tag); 863 qpair = ha->queue_pair_map[hwq]; 864 865 if (qpair) 866 return qla2xxx_mqueuecommand(host, cmd, qpair); 867 } 868 869 if (ha->flags.eeh_busy) { 870 if (ha->flags.pci_channel_io_perm_failure) { 871 ql_dbg(ql_dbg_aer, vha, 0x9010, 872 "PCI Channel IO permanent failure, exiting " 873 "cmd=%p.\n", cmd); 874 cmd->result = DID_NO_CONNECT << 16; 875 } else { 876 ql_dbg(ql_dbg_aer, vha, 0x9011, 877 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 878 cmd->result = DID_REQUEUE << 16; 879 } 880 goto qc24_fail_command; 881 } 882 883 rval = fc_remote_port_chkready(rport); 884 if (rval) { 885 cmd->result = rval; 886 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 887 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 888 cmd, rval); 889 goto qc24_fail_command; 890 } 891 892 if (!vha->flags.difdix_supported && 893 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 894 ql_dbg(ql_dbg_io, vha, 0x3004, 895 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 896 cmd); 897 cmd->result = DID_NO_CONNECT << 16; 898 goto qc24_fail_command; 899 } 900 901 if (!fcport || fcport->deleted) { 902 cmd->result = DID_IMM_RETRY << 16; 903 goto qc24_fail_command; 904 } 905 906 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 907 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 908 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 909 ql_dbg(ql_dbg_io, vha, 0x3005, 910 "Returning DNC, fcport_state=%d loop_state=%d.\n", 911 atomic_read(&fcport->state), 912 atomic_read(&base_vha->loop_state)); 913 cmd->result = DID_NO_CONNECT << 16; 914 goto qc24_fail_command; 915 } 916 goto qc24_target_busy; 917 } 918 919 /* 920 * Return target busy if we've received a non-zero retry_delay_timer 921 * in a FCP_RSP. 922 */ 923 if (fcport->retry_delay_timestamp == 0) { 924 /* retry delay not set */ 925 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 926 fcport->retry_delay_timestamp = 0; 927 else 928 goto qc24_target_busy; 929 930 sp = scsi_cmd_priv(cmd); 931 /* ref: INIT */ 932 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 933 934 sp->u.scmd.cmd = cmd; 935 sp->type = SRB_SCSI_CMD; 936 sp->free = qla2x00_sp_free_dma; 937 sp->done = qla2x00_sp_compl; 938 939 rval = ha->isp_ops->start_scsi(sp); 940 if (rval != QLA_SUCCESS) { 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 943 goto qc24_host_busy_free_sp; 944 } 945 946 return 0; 947 948 qc24_host_busy_free_sp: 949 /* ref: INIT */ 950 kref_put(&sp->cmd_kref, qla2x00_sp_release); 951 952 qc24_target_busy: 953 return SCSI_MLQUEUE_TARGET_BUSY; 954 955 qc24_fail_command: 956 scsi_done(cmd); 957 958 return 0; 959 } 960 961 /* For MQ supported I/O */ 962 int 963 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 964 struct qla_qpair *qpair) 965 { 966 scsi_qla_host_t *vha = shost_priv(host); 967 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 968 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 969 struct qla_hw_data *ha = vha->hw; 970 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 971 srb_t *sp; 972 int rval; 973 974 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 975 if (rval) { 976 cmd->result = rval; 977 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 978 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 979 cmd, rval); 980 goto qc24_fail_command; 981 } 982 983 if (!qpair->online) { 984 ql_dbg(ql_dbg_io, vha, 0x3077, 985 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 986 cmd->result = DID_NO_CONNECT << 16; 987 goto qc24_fail_command; 988 } 989 990 if (!fcport || fcport->deleted) { 991 cmd->result = DID_IMM_RETRY << 16; 992 goto qc24_fail_command; 993 } 994 995 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 996 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 997 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 998 ql_dbg(ql_dbg_io, vha, 0x3077, 999 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1000 atomic_read(&fcport->state), 1001 atomic_read(&base_vha->loop_state)); 1002 cmd->result = DID_NO_CONNECT << 16; 1003 goto qc24_fail_command; 1004 } 1005 goto qc24_target_busy; 1006 } 1007 1008 /* 1009 * Return target busy if we've received a non-zero retry_delay_timer 1010 * in a FCP_RSP. 1011 */ 1012 if (fcport->retry_delay_timestamp == 0) { 1013 /* retry delay not set */ 1014 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1015 fcport->retry_delay_timestamp = 0; 1016 else 1017 goto qc24_target_busy; 1018 1019 sp = scsi_cmd_priv(cmd); 1020 /* ref: INIT */ 1021 qla2xxx_init_sp(sp, vha, qpair, fcport); 1022 1023 sp->u.scmd.cmd = cmd; 1024 sp->type = SRB_SCSI_CMD; 1025 sp->free = qla2xxx_qpair_sp_free_dma; 1026 sp->done = qla2xxx_qpair_sp_compl; 1027 1028 rval = ha->isp_ops->start_scsi_mq(sp); 1029 if (rval != QLA_SUCCESS) { 1030 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1031 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1032 goto qc24_host_busy_free_sp; 1033 } 1034 1035 return 0; 1036 1037 qc24_host_busy_free_sp: 1038 /* ref: INIT */ 1039 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1040 1041 qc24_target_busy: 1042 return SCSI_MLQUEUE_TARGET_BUSY; 1043 1044 qc24_fail_command: 1045 scsi_done(cmd); 1046 1047 return 0; 1048 } 1049 1050 /* 1051 * qla2x00_eh_wait_on_command 1052 * Waits for the command to be returned by the Firmware for some 1053 * max time. 1054 * 1055 * Input: 1056 * cmd = Scsi Command to wait on. 1057 * 1058 * Return: 1059 * Completed in time : QLA_SUCCESS 1060 * Did not complete in time : QLA_FUNCTION_FAILED 1061 */ 1062 static int 1063 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1064 { 1065 #define ABORT_POLLING_PERIOD 1000 1066 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1067 unsigned long wait_iter = ABORT_WAIT_ITER; 1068 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1069 struct qla_hw_data *ha = vha->hw; 1070 srb_t *sp = scsi_cmd_priv(cmd); 1071 int ret = QLA_SUCCESS; 1072 1073 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1074 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1075 "Return:eh_wait.\n"); 1076 return ret; 1077 } 1078 1079 while (sp->type && wait_iter--) 1080 msleep(ABORT_POLLING_PERIOD); 1081 if (sp->type) 1082 ret = QLA_FUNCTION_FAILED; 1083 1084 return ret; 1085 } 1086 1087 /* 1088 * qla2x00_wait_for_hba_online 1089 * Wait till the HBA is online after going through 1090 * <= MAX_RETRIES_OF_ISP_ABORT or 1091 * finally HBA is disabled ie marked offline 1092 * 1093 * Input: 1094 * ha - pointer to host adapter structure 1095 * 1096 * Note: 1097 * Does context switching-Release SPIN_LOCK 1098 * (if any) before calling this routine. 1099 * 1100 * Return: 1101 * Success (Adapter is online) : 0 1102 * Failed (Adapter is offline/disabled) : 1 1103 */ 1104 int 1105 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1106 { 1107 int return_status; 1108 unsigned long wait_online; 1109 struct qla_hw_data *ha = vha->hw; 1110 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1111 1112 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1113 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1114 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1115 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1116 ha->dpc_active) && time_before(jiffies, wait_online)) { 1117 1118 msleep(1000); 1119 } 1120 if (base_vha->flags.online) 1121 return_status = QLA_SUCCESS; 1122 else 1123 return_status = QLA_FUNCTION_FAILED; 1124 1125 return (return_status); 1126 } 1127 1128 static inline int test_fcport_count(scsi_qla_host_t *vha) 1129 { 1130 struct qla_hw_data *ha = vha->hw; 1131 unsigned long flags; 1132 int res; 1133 /* Return 0 = sleep, x=wake */ 1134 1135 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1136 ql_dbg(ql_dbg_init, vha, 0x00ec, 1137 "tgt %p, fcport_count=%d\n", 1138 vha, vha->fcport_count); 1139 res = (vha->fcport_count == 0); 1140 if (res) { 1141 struct fc_port *fcport; 1142 1143 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1144 if (fcport->deleted != QLA_SESS_DELETED) { 1145 /* session(s) may not be fully logged in 1146 * (ie fcport_count=0), but session 1147 * deletion thread(s) may be inflight. 1148 */ 1149 1150 res = 0; 1151 break; 1152 } 1153 } 1154 } 1155 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1156 1157 return res; 1158 } 1159 1160 /* 1161 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1162 * it has dependency on UNLOADING flag to stop device discovery 1163 */ 1164 void 1165 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1166 { 1167 u8 i; 1168 1169 qla2x00_mark_all_devices_lost(vha); 1170 1171 for (i = 0; i < 10; i++) { 1172 if (wait_event_timeout(vha->fcport_waitQ, 1173 test_fcport_count(vha), HZ) > 0) 1174 break; 1175 } 1176 1177 flush_workqueue(vha->hw->wq); 1178 } 1179 1180 /* 1181 * qla2x00_wait_for_hba_ready 1182 * Wait till the HBA is ready before doing driver unload 1183 * 1184 * Input: 1185 * ha - pointer to host adapter structure 1186 * 1187 * Note: 1188 * Does context switching-Release SPIN_LOCK 1189 * (if any) before calling this routine. 1190 * 1191 */ 1192 static void 1193 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1194 { 1195 struct qla_hw_data *ha = vha->hw; 1196 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1197 1198 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1199 ha->flags.mbox_busy) || 1200 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1201 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1202 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1203 break; 1204 msleep(1000); 1205 } 1206 } 1207 1208 int 1209 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1210 { 1211 int return_status; 1212 unsigned long wait_reset; 1213 struct qla_hw_data *ha = vha->hw; 1214 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1215 1216 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1217 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1218 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1219 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1220 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1221 1222 msleep(1000); 1223 1224 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1225 ha->flags.chip_reset_done) 1226 break; 1227 } 1228 if (ha->flags.chip_reset_done) 1229 return_status = QLA_SUCCESS; 1230 else 1231 return_status = QLA_FUNCTION_FAILED; 1232 1233 return return_status; 1234 } 1235 1236 /************************************************************************** 1237 * qla2xxx_eh_abort 1238 * 1239 * Description: 1240 * The abort function will abort the specified command. 1241 * 1242 * Input: 1243 * cmd = Linux SCSI command packet to be aborted. 1244 * 1245 * Returns: 1246 * Either SUCCESS or FAILED. 1247 * 1248 * Note: 1249 * Only return FAILED if command not returned by firmware. 1250 **************************************************************************/ 1251 static int 1252 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1253 { 1254 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1255 DECLARE_COMPLETION_ONSTACK(comp); 1256 srb_t *sp; 1257 int ret; 1258 unsigned int id; 1259 uint64_t lun; 1260 int rval; 1261 struct qla_hw_data *ha = vha->hw; 1262 uint32_t ratov_j; 1263 struct qla_qpair *qpair; 1264 unsigned long flags; 1265 int fast_fail_status = SUCCESS; 1266 1267 if (qla2x00_isp_reg_stat(ha)) { 1268 ql_log(ql_log_info, vha, 0x8042, 1269 "PCI/Register disconnect, exiting.\n"); 1270 qla_pci_set_eeh_busy(vha); 1271 return FAILED; 1272 } 1273 1274 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1275 ret = fc_block_scsi_eh(cmd); 1276 if (ret != 0) 1277 fast_fail_status = ret; 1278 1279 sp = scsi_cmd_priv(cmd); 1280 qpair = sp->qpair; 1281 1282 vha->cmd_timeout_cnt++; 1283 1284 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1285 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1286 1287 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1288 sp->comp = ∁ 1289 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1290 1291 1292 id = cmd->device->id; 1293 lun = cmd->device->lun; 1294 1295 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1296 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1297 vha->host_no, id, lun, sp, cmd, sp->handle); 1298 1299 /* 1300 * Abort will release the original Command/sp from FW. Let the 1301 * original command call scsi_done. In return, he will wakeup 1302 * this sleeping thread. 1303 */ 1304 rval = ha->isp_ops->abort_command(sp); 1305 1306 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1307 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1308 1309 /* Wait for the command completion. */ 1310 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1311 ratov_j = msecs_to_jiffies(ratov_j); 1312 switch (rval) { 1313 case QLA_SUCCESS: 1314 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1315 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1316 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1317 __func__, ha->r_a_tov/10); 1318 ret = FAILED; 1319 } else { 1320 ret = fast_fail_status; 1321 } 1322 break; 1323 default: 1324 ret = FAILED; 1325 break; 1326 } 1327 1328 sp->comp = NULL; 1329 1330 ql_log(ql_log_info, vha, 0x801c, 1331 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1332 vha->host_no, id, lun, ret); 1333 1334 return ret; 1335 } 1336 1337 /* 1338 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1339 */ 1340 int 1341 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1342 uint64_t l, enum nexus_wait_type type) 1343 { 1344 int cnt, match, status; 1345 unsigned long flags; 1346 struct qla_hw_data *ha = vha->hw; 1347 struct req_que *req; 1348 srb_t *sp; 1349 struct scsi_cmnd *cmd; 1350 1351 status = QLA_SUCCESS; 1352 1353 spin_lock_irqsave(&ha->hardware_lock, flags); 1354 req = vha->req; 1355 for (cnt = 1; status == QLA_SUCCESS && 1356 cnt < req->num_outstanding_cmds; cnt++) { 1357 sp = req->outstanding_cmds[cnt]; 1358 if (!sp) 1359 continue; 1360 if (sp->type != SRB_SCSI_CMD) 1361 continue; 1362 if (vha->vp_idx != sp->vha->vp_idx) 1363 continue; 1364 match = 0; 1365 cmd = GET_CMD_SP(sp); 1366 switch (type) { 1367 case WAIT_HOST: 1368 match = 1; 1369 break; 1370 case WAIT_TARGET: 1371 match = cmd->device->id == t; 1372 break; 1373 case WAIT_LUN: 1374 match = (cmd->device->id == t && 1375 cmd->device->lun == l); 1376 break; 1377 } 1378 if (!match) 1379 continue; 1380 1381 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1382 status = qla2x00_eh_wait_on_command(cmd); 1383 spin_lock_irqsave(&ha->hardware_lock, flags); 1384 } 1385 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1386 1387 return status; 1388 } 1389 1390 static char *reset_errors[] = { 1391 "HBA not online", 1392 "HBA not ready", 1393 "Task management failed", 1394 "Waiting for command completions", 1395 }; 1396 1397 static int 1398 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1399 { 1400 struct scsi_device *sdev = cmd->device; 1401 scsi_qla_host_t *vha = shost_priv(sdev->host); 1402 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1403 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1404 struct qla_hw_data *ha = vha->hw; 1405 int err; 1406 1407 if (qla2x00_isp_reg_stat(ha)) { 1408 ql_log(ql_log_info, vha, 0x803e, 1409 "PCI/Register disconnect, exiting.\n"); 1410 qla_pci_set_eeh_busy(vha); 1411 return FAILED; 1412 } 1413 1414 if (!fcport) { 1415 return FAILED; 1416 } 1417 1418 err = fc_block_rport(rport); 1419 if (err != 0) 1420 return err; 1421 1422 if (fcport->deleted) 1423 return SUCCESS; 1424 1425 ql_log(ql_log_info, vha, 0x8009, 1426 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1427 sdev->id, sdev->lun, cmd); 1428 1429 err = 0; 1430 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1431 ql_log(ql_log_warn, vha, 0x800a, 1432 "Wait for hba online failed for cmd=%p.\n", cmd); 1433 goto eh_reset_failed; 1434 } 1435 err = 2; 1436 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1437 != QLA_SUCCESS) { 1438 ql_log(ql_log_warn, vha, 0x800c, 1439 "do_reset failed for cmd=%p.\n", cmd); 1440 goto eh_reset_failed; 1441 } 1442 err = 3; 1443 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1444 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1445 ql_log(ql_log_warn, vha, 0x800d, 1446 "wait for pending cmds failed for cmd=%p.\n", cmd); 1447 goto eh_reset_failed; 1448 } 1449 1450 ql_log(ql_log_info, vha, 0x800e, 1451 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1452 vha->host_no, sdev->id, sdev->lun, cmd); 1453 1454 return SUCCESS; 1455 1456 eh_reset_failed: 1457 ql_log(ql_log_info, vha, 0x800f, 1458 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1459 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1460 cmd); 1461 vha->reset_cmd_err_cnt++; 1462 return FAILED; 1463 } 1464 1465 static int 1466 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1467 { 1468 struct scsi_device *sdev = cmd->device; 1469 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1470 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1471 struct qla_hw_data *ha = vha->hw; 1472 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1473 int err; 1474 1475 if (qla2x00_isp_reg_stat(ha)) { 1476 ql_log(ql_log_info, vha, 0x803f, 1477 "PCI/Register disconnect, exiting.\n"); 1478 qla_pci_set_eeh_busy(vha); 1479 return FAILED; 1480 } 1481 1482 if (!fcport) { 1483 return FAILED; 1484 } 1485 1486 err = fc_block_rport(rport); 1487 if (err != 0) 1488 return err; 1489 1490 if (fcport->deleted) 1491 return SUCCESS; 1492 1493 ql_log(ql_log_info, vha, 0x8009, 1494 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1495 sdev->id, cmd); 1496 1497 err = 0; 1498 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1499 ql_log(ql_log_warn, vha, 0x800a, 1500 "Wait for hba online failed for cmd=%p.\n", cmd); 1501 goto eh_reset_failed; 1502 } 1503 err = 2; 1504 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1505 ql_log(ql_log_warn, vha, 0x800c, 1506 "target_reset failed for cmd=%p.\n", cmd); 1507 goto eh_reset_failed; 1508 } 1509 err = 3; 1510 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1511 0, WAIT_TARGET) != QLA_SUCCESS) { 1512 ql_log(ql_log_warn, vha, 0x800d, 1513 "wait for pending cmds failed for cmd=%p.\n", cmd); 1514 goto eh_reset_failed; 1515 } 1516 1517 ql_log(ql_log_info, vha, 0x800e, 1518 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1519 vha->host_no, sdev->id, cmd); 1520 1521 return SUCCESS; 1522 1523 eh_reset_failed: 1524 ql_log(ql_log_info, vha, 0x800f, 1525 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1526 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1527 cmd); 1528 vha->reset_cmd_err_cnt++; 1529 return FAILED; 1530 } 1531 1532 /************************************************************************** 1533 * qla2xxx_eh_bus_reset 1534 * 1535 * Description: 1536 * The bus reset function will reset the bus and abort any executing 1537 * commands. 1538 * 1539 * Input: 1540 * cmd = Linux SCSI command packet of the command that cause the 1541 * bus reset. 1542 * 1543 * Returns: 1544 * SUCCESS/FAILURE (defined as macro in scsi.h). 1545 * 1546 **************************************************************************/ 1547 static int 1548 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1549 { 1550 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1551 int ret = FAILED; 1552 unsigned int id; 1553 uint64_t lun; 1554 struct qla_hw_data *ha = vha->hw; 1555 1556 if (qla2x00_isp_reg_stat(ha)) { 1557 ql_log(ql_log_info, vha, 0x8040, 1558 "PCI/Register disconnect, exiting.\n"); 1559 qla_pci_set_eeh_busy(vha); 1560 return FAILED; 1561 } 1562 1563 id = cmd->device->id; 1564 lun = cmd->device->lun; 1565 1566 if (qla2x00_chip_is_down(vha)) 1567 return ret; 1568 1569 ql_log(ql_log_info, vha, 0x8012, 1570 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1571 1572 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1573 ql_log(ql_log_fatal, vha, 0x8013, 1574 "Wait for hba online failed board disabled.\n"); 1575 goto eh_bus_reset_done; 1576 } 1577 1578 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1579 ret = SUCCESS; 1580 1581 if (ret == FAILED) 1582 goto eh_bus_reset_done; 1583 1584 /* Flush outstanding commands. */ 1585 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1586 QLA_SUCCESS) { 1587 ql_log(ql_log_warn, vha, 0x8014, 1588 "Wait for pending commands failed.\n"); 1589 ret = FAILED; 1590 } 1591 1592 eh_bus_reset_done: 1593 ql_log(ql_log_warn, vha, 0x802b, 1594 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1595 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1596 1597 return ret; 1598 } 1599 1600 /************************************************************************** 1601 * qla2xxx_eh_host_reset 1602 * 1603 * Description: 1604 * The reset function will reset the Adapter. 1605 * 1606 * Input: 1607 * cmd = Linux SCSI command packet of the command that cause the 1608 * adapter reset. 1609 * 1610 * Returns: 1611 * Either SUCCESS or FAILED. 1612 * 1613 * Note: 1614 **************************************************************************/ 1615 static int 1616 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1617 { 1618 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1619 struct qla_hw_data *ha = vha->hw; 1620 int ret = FAILED; 1621 unsigned int id; 1622 uint64_t lun; 1623 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1624 1625 if (qla2x00_isp_reg_stat(ha)) { 1626 ql_log(ql_log_info, vha, 0x8041, 1627 "PCI/Register disconnect, exiting.\n"); 1628 qla_pci_set_eeh_busy(vha); 1629 return SUCCESS; 1630 } 1631 1632 id = cmd->device->id; 1633 lun = cmd->device->lun; 1634 1635 ql_log(ql_log_info, vha, 0x8018, 1636 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1637 1638 /* 1639 * No point in issuing another reset if one is active. Also do not 1640 * attempt a reset if we are updating flash. 1641 */ 1642 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1643 goto eh_host_reset_lock; 1644 1645 if (vha != base_vha) { 1646 if (qla2x00_vp_abort_isp(vha)) 1647 goto eh_host_reset_lock; 1648 } else { 1649 if (IS_P3P_TYPE(vha->hw)) { 1650 if (!qla82xx_fcoe_ctx_reset(vha)) { 1651 /* Ctx reset success */ 1652 ret = SUCCESS; 1653 goto eh_host_reset_lock; 1654 } 1655 /* fall thru if ctx reset failed */ 1656 } 1657 if (ha->wq) 1658 flush_workqueue(ha->wq); 1659 1660 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1661 if (ha->isp_ops->abort_isp(base_vha)) { 1662 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1663 /* failed. schedule dpc to try */ 1664 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1665 1666 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1667 ql_log(ql_log_warn, vha, 0x802a, 1668 "wait for hba online failed.\n"); 1669 goto eh_host_reset_lock; 1670 } 1671 } 1672 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1673 } 1674 1675 /* Waiting for command to be returned to OS.*/ 1676 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1677 QLA_SUCCESS) 1678 ret = SUCCESS; 1679 1680 eh_host_reset_lock: 1681 ql_log(ql_log_info, vha, 0x8017, 1682 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1683 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1684 1685 return ret; 1686 } 1687 1688 /* 1689 * qla2x00_loop_reset 1690 * Issue loop reset. 1691 * 1692 * Input: 1693 * ha = adapter block pointer. 1694 * 1695 * Returns: 1696 * 0 = success 1697 */ 1698 int 1699 qla2x00_loop_reset(scsi_qla_host_t *vha) 1700 { 1701 int ret; 1702 struct qla_hw_data *ha = vha->hw; 1703 1704 if (IS_QLAFX00(ha)) 1705 return QLA_SUCCESS; 1706 1707 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1708 atomic_set(&vha->loop_state, LOOP_DOWN); 1709 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1710 qla2x00_mark_all_devices_lost(vha); 1711 ret = qla2x00_full_login_lip(vha); 1712 if (ret != QLA_SUCCESS) { 1713 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1714 "full_login_lip=%d.\n", ret); 1715 } 1716 } 1717 1718 if (ha->flags.enable_lip_reset) { 1719 ret = qla2x00_lip_reset(vha); 1720 if (ret != QLA_SUCCESS) 1721 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1722 "lip_reset failed (%d).\n", ret); 1723 } 1724 1725 /* Issue marker command only when we are going to start the I/O */ 1726 vha->marker_needed = 1; 1727 1728 return QLA_SUCCESS; 1729 } 1730 1731 /* 1732 * The caller must ensure that no completion interrupts will happen 1733 * while this function is in progress. 1734 */ 1735 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1736 unsigned long *flags) 1737 __releases(qp->qp_lock_ptr) 1738 __acquires(qp->qp_lock_ptr) 1739 { 1740 DECLARE_COMPLETION_ONSTACK(comp); 1741 scsi_qla_host_t *vha = qp->vha; 1742 struct qla_hw_data *ha = vha->hw; 1743 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1744 int rval; 1745 bool ret_cmd; 1746 uint32_t ratov_j; 1747 1748 lockdep_assert_held(qp->qp_lock_ptr); 1749 1750 if (qla2x00_chip_is_down(vha)) { 1751 sp->done(sp, res); 1752 return; 1753 } 1754 1755 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1756 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1757 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1758 !qla2x00_isp_reg_stat(ha))) { 1759 if (sp->comp) { 1760 sp->done(sp, res); 1761 return; 1762 } 1763 1764 sp->comp = ∁ 1765 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1766 1767 rval = ha->isp_ops->abort_command(sp); 1768 /* Wait for command completion. */ 1769 ret_cmd = false; 1770 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1771 ratov_j = msecs_to_jiffies(ratov_j); 1772 switch (rval) { 1773 case QLA_SUCCESS: 1774 if (wait_for_completion_timeout(&comp, ratov_j)) { 1775 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1776 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1777 __func__, ha->r_a_tov/10); 1778 ret_cmd = true; 1779 } 1780 /* else FW return SP to driver */ 1781 break; 1782 default: 1783 ret_cmd = true; 1784 break; 1785 } 1786 1787 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1788 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1789 sp->done(sp, res); 1790 } else { 1791 sp->done(sp, res); 1792 } 1793 } 1794 1795 /* 1796 * The caller must ensure that no completion interrupts will happen 1797 * while this function is in progress. 1798 */ 1799 static void 1800 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1801 { 1802 int cnt; 1803 unsigned long flags; 1804 srb_t *sp; 1805 scsi_qla_host_t *vha = qp->vha; 1806 struct qla_hw_data *ha = vha->hw; 1807 struct req_que *req; 1808 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1809 struct qla_tgt_cmd *cmd; 1810 1811 if (!ha->req_q_map) 1812 return; 1813 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1814 req = qp->req; 1815 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1816 sp = req->outstanding_cmds[cnt]; 1817 if (sp) { 1818 switch (sp->cmd_type) { 1819 case TYPE_SRB: 1820 qla2x00_abort_srb(qp, sp, res, &flags); 1821 break; 1822 case TYPE_TGT_CMD: 1823 if (!vha->hw->tgt.tgt_ops || !tgt || 1824 qla_ini_mode_enabled(vha)) { 1825 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1826 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1827 vha->dpc_flags); 1828 continue; 1829 } 1830 cmd = (struct qla_tgt_cmd *)sp; 1831 cmd->aborted = 1; 1832 break; 1833 case TYPE_TGT_TMCMD: 1834 /* Skip task management functions. */ 1835 break; 1836 default: 1837 break; 1838 } 1839 req->outstanding_cmds[cnt] = NULL; 1840 } 1841 } 1842 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1843 } 1844 1845 /* 1846 * The caller must ensure that no completion interrupts will happen 1847 * while this function is in progress. 1848 */ 1849 void 1850 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1851 { 1852 int que; 1853 struct qla_hw_data *ha = vha->hw; 1854 1855 /* Continue only if initialization complete. */ 1856 if (!ha->base_qpair) 1857 return; 1858 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1859 1860 if (!ha->queue_pair_map) 1861 return; 1862 for (que = 0; que < ha->max_qpairs; que++) { 1863 if (!ha->queue_pair_map[que]) 1864 continue; 1865 1866 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1867 } 1868 } 1869 1870 static int 1871 qla2xxx_slave_alloc(struct scsi_device *sdev) 1872 { 1873 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1874 1875 if (!rport || fc_remote_port_chkready(rport)) 1876 return -ENXIO; 1877 1878 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1879 1880 return 0; 1881 } 1882 1883 static int 1884 qla2xxx_slave_configure(struct scsi_device *sdev) 1885 { 1886 scsi_qla_host_t *vha = shost_priv(sdev->host); 1887 struct req_que *req = vha->req; 1888 1889 if (IS_T10_PI_CAPABLE(vha->hw)) 1890 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1891 1892 scsi_change_queue_depth(sdev, req->max_q_depth); 1893 return 0; 1894 } 1895 1896 static void 1897 qla2xxx_slave_destroy(struct scsi_device *sdev) 1898 { 1899 sdev->hostdata = NULL; 1900 } 1901 1902 /** 1903 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1904 * @ha: HA context 1905 * 1906 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1907 * supported addressing method. 1908 */ 1909 static void 1910 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1911 { 1912 /* Assume a 32bit DMA mask. */ 1913 ha->flags.enable_64bit_addressing = 0; 1914 1915 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1916 /* Any upper-dword bits set? */ 1917 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1918 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1919 /* Ok, a 64bit DMA mask is applicable. */ 1920 ha->flags.enable_64bit_addressing = 1; 1921 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1922 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1923 return; 1924 } 1925 } 1926 1927 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1928 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1929 } 1930 1931 static void 1932 qla2x00_enable_intrs(struct qla_hw_data *ha) 1933 { 1934 unsigned long flags = 0; 1935 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1936 1937 spin_lock_irqsave(&ha->hardware_lock, flags); 1938 ha->interrupts_on = 1; 1939 /* enable risc and host interrupts */ 1940 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1941 rd_reg_word(®->ictrl); 1942 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1943 1944 } 1945 1946 static void 1947 qla2x00_disable_intrs(struct qla_hw_data *ha) 1948 { 1949 unsigned long flags = 0; 1950 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1951 1952 spin_lock_irqsave(&ha->hardware_lock, flags); 1953 ha->interrupts_on = 0; 1954 /* disable risc and host interrupts */ 1955 wrt_reg_word(®->ictrl, 0); 1956 rd_reg_word(®->ictrl); 1957 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1958 } 1959 1960 static void 1961 qla24xx_enable_intrs(struct qla_hw_data *ha) 1962 { 1963 unsigned long flags = 0; 1964 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1965 1966 spin_lock_irqsave(&ha->hardware_lock, flags); 1967 ha->interrupts_on = 1; 1968 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1969 rd_reg_dword(®->ictrl); 1970 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1971 } 1972 1973 static void 1974 qla24xx_disable_intrs(struct qla_hw_data *ha) 1975 { 1976 unsigned long flags = 0; 1977 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1978 1979 if (IS_NOPOLLING_TYPE(ha)) 1980 return; 1981 spin_lock_irqsave(&ha->hardware_lock, flags); 1982 ha->interrupts_on = 0; 1983 wrt_reg_dword(®->ictrl, 0); 1984 rd_reg_dword(®->ictrl); 1985 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1986 } 1987 1988 static int 1989 qla2x00_iospace_config(struct qla_hw_data *ha) 1990 { 1991 resource_size_t pio; 1992 uint16_t msix; 1993 1994 if (pci_request_selected_regions(ha->pdev, ha->bars, 1995 QLA2XXX_DRIVER_NAME)) { 1996 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1997 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1998 pci_name(ha->pdev)); 1999 goto iospace_error_exit; 2000 } 2001 if (!(ha->bars & 1)) 2002 goto skip_pio; 2003 2004 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2005 pio = pci_resource_start(ha->pdev, 0); 2006 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2007 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2008 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2009 "Invalid pci I/O region size (%s).\n", 2010 pci_name(ha->pdev)); 2011 pio = 0; 2012 } 2013 } else { 2014 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2015 "Region #0 no a PIO resource (%s).\n", 2016 pci_name(ha->pdev)); 2017 pio = 0; 2018 } 2019 ha->pio_address = pio; 2020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2021 "PIO address=%llu.\n", 2022 (unsigned long long)ha->pio_address); 2023 2024 skip_pio: 2025 /* Use MMIO operations for all accesses. */ 2026 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2027 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2028 "Region #1 not an MMIO resource (%s), aborting.\n", 2029 pci_name(ha->pdev)); 2030 goto iospace_error_exit; 2031 } 2032 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2033 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2034 "Invalid PCI mem region size (%s), aborting.\n", 2035 pci_name(ha->pdev)); 2036 goto iospace_error_exit; 2037 } 2038 2039 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2040 if (!ha->iobase) { 2041 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2042 "Cannot remap MMIO (%s), aborting.\n", 2043 pci_name(ha->pdev)); 2044 goto iospace_error_exit; 2045 } 2046 2047 /* Determine queue resources */ 2048 ha->max_req_queues = ha->max_rsp_queues = 1; 2049 ha->msix_count = QLA_BASE_VECTORS; 2050 2051 /* Check if FW supports MQ or not */ 2052 if (!(ha->fw_attributes & BIT_6)) 2053 goto mqiobase_exit; 2054 2055 if (!ql2xmqsupport || !ql2xnvmeenable || 2056 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2057 goto mqiobase_exit; 2058 2059 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2060 pci_resource_len(ha->pdev, 3)); 2061 if (ha->mqiobase) { 2062 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2063 "MQIO Base=%p.\n", ha->mqiobase); 2064 /* Read MSIX vector size of the board */ 2065 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2066 ha->msix_count = msix + 1; 2067 /* Max queues are bounded by available msix vectors */ 2068 /* MB interrupt uses 1 vector */ 2069 ha->max_req_queues = ha->msix_count - 1; 2070 ha->max_rsp_queues = ha->max_req_queues; 2071 /* Queue pairs is the max value minus the base queue pair */ 2072 ha->max_qpairs = ha->max_rsp_queues - 1; 2073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2074 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2075 2076 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2077 "MSI-X vector count: %d.\n", ha->msix_count); 2078 } else 2079 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2080 "BAR 3 not enabled.\n"); 2081 2082 mqiobase_exit: 2083 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2084 "MSIX Count: %d.\n", ha->msix_count); 2085 return (0); 2086 2087 iospace_error_exit: 2088 return (-ENOMEM); 2089 } 2090 2091 2092 static int 2093 qla83xx_iospace_config(struct qla_hw_data *ha) 2094 { 2095 uint16_t msix; 2096 2097 if (pci_request_selected_regions(ha->pdev, ha->bars, 2098 QLA2XXX_DRIVER_NAME)) { 2099 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2100 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2101 pci_name(ha->pdev)); 2102 2103 goto iospace_error_exit; 2104 } 2105 2106 /* Use MMIO operations for all accesses. */ 2107 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2108 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2109 "Invalid pci I/O region size (%s).\n", 2110 pci_name(ha->pdev)); 2111 goto iospace_error_exit; 2112 } 2113 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2114 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2115 "Invalid PCI mem region size (%s), aborting\n", 2116 pci_name(ha->pdev)); 2117 goto iospace_error_exit; 2118 } 2119 2120 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2121 if (!ha->iobase) { 2122 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2123 "Cannot remap MMIO (%s), aborting.\n", 2124 pci_name(ha->pdev)); 2125 goto iospace_error_exit; 2126 } 2127 2128 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2129 /* 83XX 26XX always use MQ type access for queues 2130 * - mbar 2, a.k.a region 4 */ 2131 ha->max_req_queues = ha->max_rsp_queues = 1; 2132 ha->msix_count = QLA_BASE_VECTORS; 2133 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2134 pci_resource_len(ha->pdev, 4)); 2135 2136 if (!ha->mqiobase) { 2137 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2138 "BAR2/region4 not enabled\n"); 2139 goto mqiobase_exit; 2140 } 2141 2142 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2143 pci_resource_len(ha->pdev, 2)); 2144 if (ha->msixbase) { 2145 /* Read MSIX vector size of the board */ 2146 pci_read_config_word(ha->pdev, 2147 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2148 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2149 /* 2150 * By default, driver uses at least two msix vectors 2151 * (default & rspq) 2152 */ 2153 if (ql2xmqsupport || ql2xnvmeenable) { 2154 /* MB interrupt uses 1 vector */ 2155 ha->max_req_queues = ha->msix_count - 1; 2156 2157 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2158 if (QLA_TGT_MODE_ENABLED()) 2159 ha->max_req_queues--; 2160 2161 ha->max_rsp_queues = ha->max_req_queues; 2162 2163 /* Queue pairs is the max value minus 2164 * the base queue pair */ 2165 ha->max_qpairs = ha->max_req_queues - 1; 2166 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2167 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2168 } 2169 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2170 "MSI-X vector count: %d.\n", ha->msix_count); 2171 } else 2172 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2173 "BAR 1 not enabled.\n"); 2174 2175 mqiobase_exit: 2176 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2177 "MSIX Count: %d.\n", ha->msix_count); 2178 return 0; 2179 2180 iospace_error_exit: 2181 return -ENOMEM; 2182 } 2183 2184 static struct isp_operations qla2100_isp_ops = { 2185 .pci_config = qla2100_pci_config, 2186 .reset_chip = qla2x00_reset_chip, 2187 .chip_diag = qla2x00_chip_diag, 2188 .config_rings = qla2x00_config_rings, 2189 .reset_adapter = qla2x00_reset_adapter, 2190 .nvram_config = qla2x00_nvram_config, 2191 .update_fw_options = qla2x00_update_fw_options, 2192 .load_risc = qla2x00_load_risc, 2193 .pci_info_str = qla2x00_pci_info_str, 2194 .fw_version_str = qla2x00_fw_version_str, 2195 .intr_handler = qla2100_intr_handler, 2196 .enable_intrs = qla2x00_enable_intrs, 2197 .disable_intrs = qla2x00_disable_intrs, 2198 .abort_command = qla2x00_abort_command, 2199 .target_reset = qla2x00_abort_target, 2200 .lun_reset = qla2x00_lun_reset, 2201 .fabric_login = qla2x00_login_fabric, 2202 .fabric_logout = qla2x00_fabric_logout, 2203 .calc_req_entries = qla2x00_calc_iocbs_32, 2204 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2205 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2206 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2207 .read_nvram = qla2x00_read_nvram_data, 2208 .write_nvram = qla2x00_write_nvram_data, 2209 .fw_dump = qla2100_fw_dump, 2210 .beacon_on = NULL, 2211 .beacon_off = NULL, 2212 .beacon_blink = NULL, 2213 .read_optrom = qla2x00_read_optrom_data, 2214 .write_optrom = qla2x00_write_optrom_data, 2215 .get_flash_version = qla2x00_get_flash_version, 2216 .start_scsi = qla2x00_start_scsi, 2217 .start_scsi_mq = NULL, 2218 .abort_isp = qla2x00_abort_isp, 2219 .iospace_config = qla2x00_iospace_config, 2220 .initialize_adapter = qla2x00_initialize_adapter, 2221 }; 2222 2223 static struct isp_operations qla2300_isp_ops = { 2224 .pci_config = qla2300_pci_config, 2225 .reset_chip = qla2x00_reset_chip, 2226 .chip_diag = qla2x00_chip_diag, 2227 .config_rings = qla2x00_config_rings, 2228 .reset_adapter = qla2x00_reset_adapter, 2229 .nvram_config = qla2x00_nvram_config, 2230 .update_fw_options = qla2x00_update_fw_options, 2231 .load_risc = qla2x00_load_risc, 2232 .pci_info_str = qla2x00_pci_info_str, 2233 .fw_version_str = qla2x00_fw_version_str, 2234 .intr_handler = qla2300_intr_handler, 2235 .enable_intrs = qla2x00_enable_intrs, 2236 .disable_intrs = qla2x00_disable_intrs, 2237 .abort_command = qla2x00_abort_command, 2238 .target_reset = qla2x00_abort_target, 2239 .lun_reset = qla2x00_lun_reset, 2240 .fabric_login = qla2x00_login_fabric, 2241 .fabric_logout = qla2x00_fabric_logout, 2242 .calc_req_entries = qla2x00_calc_iocbs_32, 2243 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2244 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2245 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2246 .read_nvram = qla2x00_read_nvram_data, 2247 .write_nvram = qla2x00_write_nvram_data, 2248 .fw_dump = qla2300_fw_dump, 2249 .beacon_on = qla2x00_beacon_on, 2250 .beacon_off = qla2x00_beacon_off, 2251 .beacon_blink = qla2x00_beacon_blink, 2252 .read_optrom = qla2x00_read_optrom_data, 2253 .write_optrom = qla2x00_write_optrom_data, 2254 .get_flash_version = qla2x00_get_flash_version, 2255 .start_scsi = qla2x00_start_scsi, 2256 .start_scsi_mq = NULL, 2257 .abort_isp = qla2x00_abort_isp, 2258 .iospace_config = qla2x00_iospace_config, 2259 .initialize_adapter = qla2x00_initialize_adapter, 2260 }; 2261 2262 static struct isp_operations qla24xx_isp_ops = { 2263 .pci_config = qla24xx_pci_config, 2264 .reset_chip = qla24xx_reset_chip, 2265 .chip_diag = qla24xx_chip_diag, 2266 .config_rings = qla24xx_config_rings, 2267 .reset_adapter = qla24xx_reset_adapter, 2268 .nvram_config = qla24xx_nvram_config, 2269 .update_fw_options = qla24xx_update_fw_options, 2270 .load_risc = qla24xx_load_risc, 2271 .pci_info_str = qla24xx_pci_info_str, 2272 .fw_version_str = qla24xx_fw_version_str, 2273 .intr_handler = qla24xx_intr_handler, 2274 .enable_intrs = qla24xx_enable_intrs, 2275 .disable_intrs = qla24xx_disable_intrs, 2276 .abort_command = qla24xx_abort_command, 2277 .target_reset = qla24xx_abort_target, 2278 .lun_reset = qla24xx_lun_reset, 2279 .fabric_login = qla24xx_login_fabric, 2280 .fabric_logout = qla24xx_fabric_logout, 2281 .calc_req_entries = NULL, 2282 .build_iocbs = NULL, 2283 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2284 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2285 .read_nvram = qla24xx_read_nvram_data, 2286 .write_nvram = qla24xx_write_nvram_data, 2287 .fw_dump = qla24xx_fw_dump, 2288 .beacon_on = qla24xx_beacon_on, 2289 .beacon_off = qla24xx_beacon_off, 2290 .beacon_blink = qla24xx_beacon_blink, 2291 .read_optrom = qla24xx_read_optrom_data, 2292 .write_optrom = qla24xx_write_optrom_data, 2293 .get_flash_version = qla24xx_get_flash_version, 2294 .start_scsi = qla24xx_start_scsi, 2295 .start_scsi_mq = NULL, 2296 .abort_isp = qla2x00_abort_isp, 2297 .iospace_config = qla2x00_iospace_config, 2298 .initialize_adapter = qla2x00_initialize_adapter, 2299 }; 2300 2301 static struct isp_operations qla25xx_isp_ops = { 2302 .pci_config = qla25xx_pci_config, 2303 .reset_chip = qla24xx_reset_chip, 2304 .chip_diag = qla24xx_chip_diag, 2305 .config_rings = qla24xx_config_rings, 2306 .reset_adapter = qla24xx_reset_adapter, 2307 .nvram_config = qla24xx_nvram_config, 2308 .update_fw_options = qla24xx_update_fw_options, 2309 .load_risc = qla24xx_load_risc, 2310 .pci_info_str = qla24xx_pci_info_str, 2311 .fw_version_str = qla24xx_fw_version_str, 2312 .intr_handler = qla24xx_intr_handler, 2313 .enable_intrs = qla24xx_enable_intrs, 2314 .disable_intrs = qla24xx_disable_intrs, 2315 .abort_command = qla24xx_abort_command, 2316 .target_reset = qla24xx_abort_target, 2317 .lun_reset = qla24xx_lun_reset, 2318 .fabric_login = qla24xx_login_fabric, 2319 .fabric_logout = qla24xx_fabric_logout, 2320 .calc_req_entries = NULL, 2321 .build_iocbs = NULL, 2322 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2323 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2324 .read_nvram = qla25xx_read_nvram_data, 2325 .write_nvram = qla25xx_write_nvram_data, 2326 .fw_dump = qla25xx_fw_dump, 2327 .beacon_on = qla24xx_beacon_on, 2328 .beacon_off = qla24xx_beacon_off, 2329 .beacon_blink = qla24xx_beacon_blink, 2330 .read_optrom = qla25xx_read_optrom_data, 2331 .write_optrom = qla24xx_write_optrom_data, 2332 .get_flash_version = qla24xx_get_flash_version, 2333 .start_scsi = qla24xx_dif_start_scsi, 2334 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2335 .abort_isp = qla2x00_abort_isp, 2336 .iospace_config = qla2x00_iospace_config, 2337 .initialize_adapter = qla2x00_initialize_adapter, 2338 }; 2339 2340 static struct isp_operations qla81xx_isp_ops = { 2341 .pci_config = qla25xx_pci_config, 2342 .reset_chip = qla24xx_reset_chip, 2343 .chip_diag = qla24xx_chip_diag, 2344 .config_rings = qla24xx_config_rings, 2345 .reset_adapter = qla24xx_reset_adapter, 2346 .nvram_config = qla81xx_nvram_config, 2347 .update_fw_options = qla24xx_update_fw_options, 2348 .load_risc = qla81xx_load_risc, 2349 .pci_info_str = qla24xx_pci_info_str, 2350 .fw_version_str = qla24xx_fw_version_str, 2351 .intr_handler = qla24xx_intr_handler, 2352 .enable_intrs = qla24xx_enable_intrs, 2353 .disable_intrs = qla24xx_disable_intrs, 2354 .abort_command = qla24xx_abort_command, 2355 .target_reset = qla24xx_abort_target, 2356 .lun_reset = qla24xx_lun_reset, 2357 .fabric_login = qla24xx_login_fabric, 2358 .fabric_logout = qla24xx_fabric_logout, 2359 .calc_req_entries = NULL, 2360 .build_iocbs = NULL, 2361 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2362 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2363 .read_nvram = NULL, 2364 .write_nvram = NULL, 2365 .fw_dump = qla81xx_fw_dump, 2366 .beacon_on = qla24xx_beacon_on, 2367 .beacon_off = qla24xx_beacon_off, 2368 .beacon_blink = qla83xx_beacon_blink, 2369 .read_optrom = qla25xx_read_optrom_data, 2370 .write_optrom = qla24xx_write_optrom_data, 2371 .get_flash_version = qla24xx_get_flash_version, 2372 .start_scsi = qla24xx_dif_start_scsi, 2373 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2374 .abort_isp = qla2x00_abort_isp, 2375 .iospace_config = qla2x00_iospace_config, 2376 .initialize_adapter = qla2x00_initialize_adapter, 2377 }; 2378 2379 static struct isp_operations qla82xx_isp_ops = { 2380 .pci_config = qla82xx_pci_config, 2381 .reset_chip = qla82xx_reset_chip, 2382 .chip_diag = qla24xx_chip_diag, 2383 .config_rings = qla82xx_config_rings, 2384 .reset_adapter = qla24xx_reset_adapter, 2385 .nvram_config = qla81xx_nvram_config, 2386 .update_fw_options = qla24xx_update_fw_options, 2387 .load_risc = qla82xx_load_risc, 2388 .pci_info_str = qla24xx_pci_info_str, 2389 .fw_version_str = qla24xx_fw_version_str, 2390 .intr_handler = qla82xx_intr_handler, 2391 .enable_intrs = qla82xx_enable_intrs, 2392 .disable_intrs = qla82xx_disable_intrs, 2393 .abort_command = qla24xx_abort_command, 2394 .target_reset = qla24xx_abort_target, 2395 .lun_reset = qla24xx_lun_reset, 2396 .fabric_login = qla24xx_login_fabric, 2397 .fabric_logout = qla24xx_fabric_logout, 2398 .calc_req_entries = NULL, 2399 .build_iocbs = NULL, 2400 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2401 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2402 .read_nvram = qla24xx_read_nvram_data, 2403 .write_nvram = qla24xx_write_nvram_data, 2404 .fw_dump = qla82xx_fw_dump, 2405 .beacon_on = qla82xx_beacon_on, 2406 .beacon_off = qla82xx_beacon_off, 2407 .beacon_blink = NULL, 2408 .read_optrom = qla82xx_read_optrom_data, 2409 .write_optrom = qla82xx_write_optrom_data, 2410 .get_flash_version = qla82xx_get_flash_version, 2411 .start_scsi = qla82xx_start_scsi, 2412 .start_scsi_mq = NULL, 2413 .abort_isp = qla82xx_abort_isp, 2414 .iospace_config = qla82xx_iospace_config, 2415 .initialize_adapter = qla2x00_initialize_adapter, 2416 }; 2417 2418 static struct isp_operations qla8044_isp_ops = { 2419 .pci_config = qla82xx_pci_config, 2420 .reset_chip = qla82xx_reset_chip, 2421 .chip_diag = qla24xx_chip_diag, 2422 .config_rings = qla82xx_config_rings, 2423 .reset_adapter = qla24xx_reset_adapter, 2424 .nvram_config = qla81xx_nvram_config, 2425 .update_fw_options = qla24xx_update_fw_options, 2426 .load_risc = qla82xx_load_risc, 2427 .pci_info_str = qla24xx_pci_info_str, 2428 .fw_version_str = qla24xx_fw_version_str, 2429 .intr_handler = qla8044_intr_handler, 2430 .enable_intrs = qla82xx_enable_intrs, 2431 .disable_intrs = qla82xx_disable_intrs, 2432 .abort_command = qla24xx_abort_command, 2433 .target_reset = qla24xx_abort_target, 2434 .lun_reset = qla24xx_lun_reset, 2435 .fabric_login = qla24xx_login_fabric, 2436 .fabric_logout = qla24xx_fabric_logout, 2437 .calc_req_entries = NULL, 2438 .build_iocbs = NULL, 2439 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2440 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2441 .read_nvram = NULL, 2442 .write_nvram = NULL, 2443 .fw_dump = qla8044_fw_dump, 2444 .beacon_on = qla82xx_beacon_on, 2445 .beacon_off = qla82xx_beacon_off, 2446 .beacon_blink = NULL, 2447 .read_optrom = qla8044_read_optrom_data, 2448 .write_optrom = qla8044_write_optrom_data, 2449 .get_flash_version = qla82xx_get_flash_version, 2450 .start_scsi = qla82xx_start_scsi, 2451 .start_scsi_mq = NULL, 2452 .abort_isp = qla8044_abort_isp, 2453 .iospace_config = qla82xx_iospace_config, 2454 .initialize_adapter = qla2x00_initialize_adapter, 2455 }; 2456 2457 static struct isp_operations qla83xx_isp_ops = { 2458 .pci_config = qla25xx_pci_config, 2459 .reset_chip = qla24xx_reset_chip, 2460 .chip_diag = qla24xx_chip_diag, 2461 .config_rings = qla24xx_config_rings, 2462 .reset_adapter = qla24xx_reset_adapter, 2463 .nvram_config = qla81xx_nvram_config, 2464 .update_fw_options = qla24xx_update_fw_options, 2465 .load_risc = qla81xx_load_risc, 2466 .pci_info_str = qla24xx_pci_info_str, 2467 .fw_version_str = qla24xx_fw_version_str, 2468 .intr_handler = qla24xx_intr_handler, 2469 .enable_intrs = qla24xx_enable_intrs, 2470 .disable_intrs = qla24xx_disable_intrs, 2471 .abort_command = qla24xx_abort_command, 2472 .target_reset = qla24xx_abort_target, 2473 .lun_reset = qla24xx_lun_reset, 2474 .fabric_login = qla24xx_login_fabric, 2475 .fabric_logout = qla24xx_fabric_logout, 2476 .calc_req_entries = NULL, 2477 .build_iocbs = NULL, 2478 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2479 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2480 .read_nvram = NULL, 2481 .write_nvram = NULL, 2482 .fw_dump = qla83xx_fw_dump, 2483 .beacon_on = qla24xx_beacon_on, 2484 .beacon_off = qla24xx_beacon_off, 2485 .beacon_blink = qla83xx_beacon_blink, 2486 .read_optrom = qla25xx_read_optrom_data, 2487 .write_optrom = qla24xx_write_optrom_data, 2488 .get_flash_version = qla24xx_get_flash_version, 2489 .start_scsi = qla24xx_dif_start_scsi, 2490 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2491 .abort_isp = qla2x00_abort_isp, 2492 .iospace_config = qla83xx_iospace_config, 2493 .initialize_adapter = qla2x00_initialize_adapter, 2494 }; 2495 2496 static struct isp_operations qlafx00_isp_ops = { 2497 .pci_config = qlafx00_pci_config, 2498 .reset_chip = qlafx00_soft_reset, 2499 .chip_diag = qlafx00_chip_diag, 2500 .config_rings = qlafx00_config_rings, 2501 .reset_adapter = qlafx00_soft_reset, 2502 .nvram_config = NULL, 2503 .update_fw_options = NULL, 2504 .load_risc = NULL, 2505 .pci_info_str = qlafx00_pci_info_str, 2506 .fw_version_str = qlafx00_fw_version_str, 2507 .intr_handler = qlafx00_intr_handler, 2508 .enable_intrs = qlafx00_enable_intrs, 2509 .disable_intrs = qlafx00_disable_intrs, 2510 .abort_command = qla24xx_async_abort_command, 2511 .target_reset = qlafx00_abort_target, 2512 .lun_reset = qlafx00_lun_reset, 2513 .fabric_login = NULL, 2514 .fabric_logout = NULL, 2515 .calc_req_entries = NULL, 2516 .build_iocbs = NULL, 2517 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2518 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2519 .read_nvram = qla24xx_read_nvram_data, 2520 .write_nvram = qla24xx_write_nvram_data, 2521 .fw_dump = NULL, 2522 .beacon_on = qla24xx_beacon_on, 2523 .beacon_off = qla24xx_beacon_off, 2524 .beacon_blink = NULL, 2525 .read_optrom = qla24xx_read_optrom_data, 2526 .write_optrom = qla24xx_write_optrom_data, 2527 .get_flash_version = qla24xx_get_flash_version, 2528 .start_scsi = qlafx00_start_scsi, 2529 .start_scsi_mq = NULL, 2530 .abort_isp = qlafx00_abort_isp, 2531 .iospace_config = qlafx00_iospace_config, 2532 .initialize_adapter = qlafx00_initialize_adapter, 2533 }; 2534 2535 static struct isp_operations qla27xx_isp_ops = { 2536 .pci_config = qla25xx_pci_config, 2537 .reset_chip = qla24xx_reset_chip, 2538 .chip_diag = qla24xx_chip_diag, 2539 .config_rings = qla24xx_config_rings, 2540 .reset_adapter = qla24xx_reset_adapter, 2541 .nvram_config = qla81xx_nvram_config, 2542 .update_fw_options = qla24xx_update_fw_options, 2543 .load_risc = qla81xx_load_risc, 2544 .pci_info_str = qla24xx_pci_info_str, 2545 .fw_version_str = qla24xx_fw_version_str, 2546 .intr_handler = qla24xx_intr_handler, 2547 .enable_intrs = qla24xx_enable_intrs, 2548 .disable_intrs = qla24xx_disable_intrs, 2549 .abort_command = qla24xx_abort_command, 2550 .target_reset = qla24xx_abort_target, 2551 .lun_reset = qla24xx_lun_reset, 2552 .fabric_login = qla24xx_login_fabric, 2553 .fabric_logout = qla24xx_fabric_logout, 2554 .calc_req_entries = NULL, 2555 .build_iocbs = NULL, 2556 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2557 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2558 .read_nvram = NULL, 2559 .write_nvram = NULL, 2560 .fw_dump = qla27xx_fwdump, 2561 .mpi_fw_dump = qla27xx_mpi_fwdump, 2562 .beacon_on = qla24xx_beacon_on, 2563 .beacon_off = qla24xx_beacon_off, 2564 .beacon_blink = qla83xx_beacon_blink, 2565 .read_optrom = qla25xx_read_optrom_data, 2566 .write_optrom = qla24xx_write_optrom_data, 2567 .get_flash_version = qla24xx_get_flash_version, 2568 .start_scsi = qla24xx_dif_start_scsi, 2569 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2570 .abort_isp = qla2x00_abort_isp, 2571 .iospace_config = qla83xx_iospace_config, 2572 .initialize_adapter = qla2x00_initialize_adapter, 2573 }; 2574 2575 static inline void 2576 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2577 { 2578 ha->device_type = DT_EXTENDED_IDS; 2579 switch (ha->pdev->device) { 2580 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2581 ha->isp_type |= DT_ISP2100; 2582 ha->device_type &= ~DT_EXTENDED_IDS; 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2584 break; 2585 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2586 ha->isp_type |= DT_ISP2200; 2587 ha->device_type &= ~DT_EXTENDED_IDS; 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2591 ha->isp_type |= DT_ISP2300; 2592 ha->device_type |= DT_ZIO_SUPPORTED; 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2594 break; 2595 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2596 ha->isp_type |= DT_ISP2312; 2597 ha->device_type |= DT_ZIO_SUPPORTED; 2598 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2599 break; 2600 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2601 ha->isp_type |= DT_ISP2322; 2602 ha->device_type |= DT_ZIO_SUPPORTED; 2603 if (ha->pdev->subsystem_vendor == 0x1028 && 2604 ha->pdev->subsystem_device == 0x0170) 2605 ha->device_type |= DT_OEM_001; 2606 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2607 break; 2608 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2609 ha->isp_type |= DT_ISP6312; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2611 break; 2612 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2613 ha->isp_type |= DT_ISP6322; 2614 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2615 break; 2616 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2617 ha->isp_type |= DT_ISP2422; 2618 ha->device_type |= DT_ZIO_SUPPORTED; 2619 ha->device_type |= DT_FWI2; 2620 ha->device_type |= DT_IIDMA; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2622 break; 2623 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2624 ha->isp_type |= DT_ISP2432; 2625 ha->device_type |= DT_ZIO_SUPPORTED; 2626 ha->device_type |= DT_FWI2; 2627 ha->device_type |= DT_IIDMA; 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2629 break; 2630 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2631 ha->isp_type |= DT_ISP8432; 2632 ha->device_type |= DT_ZIO_SUPPORTED; 2633 ha->device_type |= DT_FWI2; 2634 ha->device_type |= DT_IIDMA; 2635 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2636 break; 2637 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2638 ha->isp_type |= DT_ISP5422; 2639 ha->device_type |= DT_FWI2; 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2643 ha->isp_type |= DT_ISP5432; 2644 ha->device_type |= DT_FWI2; 2645 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2646 break; 2647 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2648 ha->isp_type |= DT_ISP2532; 2649 ha->device_type |= DT_ZIO_SUPPORTED; 2650 ha->device_type |= DT_FWI2; 2651 ha->device_type |= DT_IIDMA; 2652 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2653 break; 2654 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2655 ha->isp_type |= DT_ISP8001; 2656 ha->device_type |= DT_ZIO_SUPPORTED; 2657 ha->device_type |= DT_FWI2; 2658 ha->device_type |= DT_IIDMA; 2659 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2660 break; 2661 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2662 ha->isp_type |= DT_ISP8021; 2663 ha->device_type |= DT_ZIO_SUPPORTED; 2664 ha->device_type |= DT_FWI2; 2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2666 /* Initialize 82XX ISP flags */ 2667 qla82xx_init_flags(ha); 2668 break; 2669 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2670 ha->isp_type |= DT_ISP8044; 2671 ha->device_type |= DT_ZIO_SUPPORTED; 2672 ha->device_type |= DT_FWI2; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2674 /* Initialize 82XX ISP flags */ 2675 qla82xx_init_flags(ha); 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2678 ha->isp_type |= DT_ISP2031; 2679 ha->device_type |= DT_ZIO_SUPPORTED; 2680 ha->device_type |= DT_FWI2; 2681 ha->device_type |= DT_IIDMA; 2682 ha->device_type |= DT_T10_PI; 2683 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2684 break; 2685 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2686 ha->isp_type |= DT_ISP8031; 2687 ha->device_type |= DT_ZIO_SUPPORTED; 2688 ha->device_type |= DT_FWI2; 2689 ha->device_type |= DT_IIDMA; 2690 ha->device_type |= DT_T10_PI; 2691 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2692 break; 2693 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2694 ha->isp_type |= DT_ISPFX00; 2695 break; 2696 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2697 ha->isp_type |= DT_ISP2071; 2698 ha->device_type |= DT_ZIO_SUPPORTED; 2699 ha->device_type |= DT_FWI2; 2700 ha->device_type |= DT_IIDMA; 2701 ha->device_type |= DT_T10_PI; 2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2703 break; 2704 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2705 ha->isp_type |= DT_ISP2271; 2706 ha->device_type |= DT_ZIO_SUPPORTED; 2707 ha->device_type |= DT_FWI2; 2708 ha->device_type |= DT_IIDMA; 2709 ha->device_type |= DT_T10_PI; 2710 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2711 break; 2712 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2713 ha->isp_type |= DT_ISP2261; 2714 ha->device_type |= DT_ZIO_SUPPORTED; 2715 ha->device_type |= DT_FWI2; 2716 ha->device_type |= DT_IIDMA; 2717 ha->device_type |= DT_T10_PI; 2718 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2719 break; 2720 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2721 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2722 ha->isp_type |= DT_ISP2081; 2723 ha->device_type |= DT_ZIO_SUPPORTED; 2724 ha->device_type |= DT_FWI2; 2725 ha->device_type |= DT_IIDMA; 2726 ha->device_type |= DT_T10_PI; 2727 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2728 break; 2729 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2730 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2731 ha->isp_type |= DT_ISP2281; 2732 ha->device_type |= DT_ZIO_SUPPORTED; 2733 ha->device_type |= DT_FWI2; 2734 ha->device_type |= DT_IIDMA; 2735 ha->device_type |= DT_T10_PI; 2736 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2737 break; 2738 } 2739 2740 if (IS_QLA82XX(ha)) 2741 ha->port_no = ha->portnum & 1; 2742 else { 2743 /* Get adapter physical port no from interrupt pin register. */ 2744 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2745 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2746 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2747 ha->port_no--; 2748 else 2749 ha->port_no = !(ha->port_no & 1); 2750 } 2751 2752 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2753 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2754 ha->device_type, ha->port_no, ha->fw_srisc_address); 2755 } 2756 2757 static void 2758 qla2xxx_scan_start(struct Scsi_Host *shost) 2759 { 2760 scsi_qla_host_t *vha = shost_priv(shost); 2761 2762 if (vha->hw->flags.running_gold_fw) 2763 return; 2764 2765 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2766 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2767 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2768 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2769 } 2770 2771 static int 2772 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2773 { 2774 scsi_qla_host_t *vha = shost_priv(shost); 2775 2776 if (test_bit(UNLOADING, &vha->dpc_flags)) 2777 return 1; 2778 if (!vha->host) 2779 return 1; 2780 if (time > vha->hw->loop_reset_delay * HZ) 2781 return 1; 2782 2783 return atomic_read(&vha->loop_state) == LOOP_READY; 2784 } 2785 2786 static void qla_heartbeat_work_fn(struct work_struct *work) 2787 { 2788 struct qla_hw_data *ha = container_of(work, 2789 struct qla_hw_data, heartbeat_work); 2790 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2791 2792 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2793 qla_no_op_mb(base_vha); 2794 } 2795 2796 static void qla2x00_iocb_work_fn(struct work_struct *work) 2797 { 2798 struct scsi_qla_host *vha = container_of(work, 2799 struct scsi_qla_host, iocb_work); 2800 struct qla_hw_data *ha = vha->hw; 2801 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2802 int i = 2; 2803 unsigned long flags; 2804 2805 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2806 return; 2807 2808 while (!list_empty(&vha->work_list) && i > 0) { 2809 qla2x00_do_work(vha); 2810 i--; 2811 } 2812 2813 spin_lock_irqsave(&vha->work_lock, flags); 2814 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2815 spin_unlock_irqrestore(&vha->work_lock, flags); 2816 } 2817 2818 /* 2819 * PCI driver interface 2820 */ 2821 static int 2822 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2823 { 2824 int ret = -ENODEV; 2825 struct Scsi_Host *host; 2826 scsi_qla_host_t *base_vha = NULL; 2827 struct qla_hw_data *ha; 2828 char pci_info[30]; 2829 char fw_str[30], wq_name[30]; 2830 struct scsi_host_template *sht; 2831 int bars, mem_only = 0; 2832 uint16_t req_length = 0, rsp_length = 0; 2833 struct req_que *req = NULL; 2834 struct rsp_que *rsp = NULL; 2835 int i; 2836 2837 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2838 sht = &qla2xxx_driver_template; 2839 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2840 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2841 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2842 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2843 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2844 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2845 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2846 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2847 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2848 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2849 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2850 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2851 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2852 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2853 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2854 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2855 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2856 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2857 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2858 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2859 mem_only = 1; 2860 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2861 "Mem only adapter.\n"); 2862 } 2863 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2864 "Bars=%d.\n", bars); 2865 2866 if (mem_only) { 2867 if (pci_enable_device_mem(pdev)) 2868 return ret; 2869 } else { 2870 if (pci_enable_device(pdev)) 2871 return ret; 2872 } 2873 2874 if (is_kdump_kernel()) { 2875 ql2xmqsupport = 0; 2876 ql2xallocfwdump = 0; 2877 } 2878 2879 /* This may fail but that's ok */ 2880 pci_enable_pcie_error_reporting(pdev); 2881 2882 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2883 if (!ha) { 2884 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2885 "Unable to allocate memory for ha.\n"); 2886 goto disable_device; 2887 } 2888 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2889 "Memory allocated for ha=%p.\n", ha); 2890 ha->pdev = pdev; 2891 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2892 spin_lock_init(&ha->tgt.q_full_lock); 2893 spin_lock_init(&ha->tgt.sess_lock); 2894 spin_lock_init(&ha->tgt.atio_lock); 2895 2896 spin_lock_init(&ha->sadb_lock); 2897 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2898 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2899 2900 spin_lock_init(&ha->sadb_fp_lock); 2901 2902 if (qla_edif_sadb_build_free_pool(ha)) { 2903 kfree(ha); 2904 goto disable_device; 2905 } 2906 2907 atomic_set(&ha->nvme_active_aen_cnt, 0); 2908 2909 /* Clear our data area */ 2910 ha->bars = bars; 2911 ha->mem_only = mem_only; 2912 spin_lock_init(&ha->hardware_lock); 2913 spin_lock_init(&ha->vport_slock); 2914 mutex_init(&ha->selflogin_lock); 2915 mutex_init(&ha->optrom_mutex); 2916 2917 /* Set ISP-type information. */ 2918 qla2x00_set_isp_flags(ha); 2919 2920 /* Set EEH reset type to fundamental if required by hba */ 2921 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2922 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2923 pdev->needs_freset = 1; 2924 2925 ha->prev_topology = 0; 2926 ha->init_cb_size = sizeof(init_cb_t); 2927 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2928 ha->optrom_size = OPTROM_SIZE_2300; 2929 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2930 atomic_set(&ha->num_pend_mbx_stage1, 0); 2931 atomic_set(&ha->num_pend_mbx_stage2, 0); 2932 atomic_set(&ha->num_pend_mbx_stage3, 0); 2933 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2934 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2935 2936 /* Assign ISP specific operations. */ 2937 if (IS_QLA2100(ha)) { 2938 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2939 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2940 req_length = REQUEST_ENTRY_CNT_2100; 2941 rsp_length = RESPONSE_ENTRY_CNT_2100; 2942 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2943 ha->gid_list_info_size = 4; 2944 ha->flash_conf_off = ~0; 2945 ha->flash_data_off = ~0; 2946 ha->nvram_conf_off = ~0; 2947 ha->nvram_data_off = ~0; 2948 ha->isp_ops = &qla2100_isp_ops; 2949 } else if (IS_QLA2200(ha)) { 2950 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2951 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2952 req_length = REQUEST_ENTRY_CNT_2200; 2953 rsp_length = RESPONSE_ENTRY_CNT_2100; 2954 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2955 ha->gid_list_info_size = 4; 2956 ha->flash_conf_off = ~0; 2957 ha->flash_data_off = ~0; 2958 ha->nvram_conf_off = ~0; 2959 ha->nvram_data_off = ~0; 2960 ha->isp_ops = &qla2100_isp_ops; 2961 } else if (IS_QLA23XX(ha)) { 2962 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2963 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2964 req_length = REQUEST_ENTRY_CNT_2200; 2965 rsp_length = RESPONSE_ENTRY_CNT_2300; 2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2967 ha->gid_list_info_size = 6; 2968 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2969 ha->optrom_size = OPTROM_SIZE_2322; 2970 ha->flash_conf_off = ~0; 2971 ha->flash_data_off = ~0; 2972 ha->nvram_conf_off = ~0; 2973 ha->nvram_data_off = ~0; 2974 ha->isp_ops = &qla2300_isp_ops; 2975 } else if (IS_QLA24XX_TYPE(ha)) { 2976 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2977 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2978 req_length = REQUEST_ENTRY_CNT_24XX; 2979 rsp_length = RESPONSE_ENTRY_CNT_2300; 2980 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2981 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2982 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2983 ha->gid_list_info_size = 8; 2984 ha->optrom_size = OPTROM_SIZE_24XX; 2985 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2986 ha->isp_ops = &qla24xx_isp_ops; 2987 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2988 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2989 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2990 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2991 } else if (IS_QLA25XX(ha)) { 2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2993 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2994 req_length = REQUEST_ENTRY_CNT_24XX; 2995 rsp_length = RESPONSE_ENTRY_CNT_2300; 2996 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2997 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2998 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2999 ha->gid_list_info_size = 8; 3000 ha->optrom_size = OPTROM_SIZE_25XX; 3001 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3002 ha->isp_ops = &qla25xx_isp_ops; 3003 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3004 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3005 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3006 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3007 } else if (IS_QLA81XX(ha)) { 3008 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3009 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3010 req_length = REQUEST_ENTRY_CNT_24XX; 3011 rsp_length = RESPONSE_ENTRY_CNT_2300; 3012 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3013 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3014 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3015 ha->gid_list_info_size = 8; 3016 ha->optrom_size = OPTROM_SIZE_81XX; 3017 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3018 ha->isp_ops = &qla81xx_isp_ops; 3019 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3020 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3021 ha->nvram_conf_off = ~0; 3022 ha->nvram_data_off = ~0; 3023 } else if (IS_QLA82XX(ha)) { 3024 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3025 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3026 req_length = REQUEST_ENTRY_CNT_82XX; 3027 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3028 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3029 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3030 ha->gid_list_info_size = 8; 3031 ha->optrom_size = OPTROM_SIZE_82XX; 3032 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3033 ha->isp_ops = &qla82xx_isp_ops; 3034 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3035 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3036 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3037 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3038 } else if (IS_QLA8044(ha)) { 3039 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3040 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3041 req_length = REQUEST_ENTRY_CNT_82XX; 3042 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3043 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3044 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3045 ha->gid_list_info_size = 8; 3046 ha->optrom_size = OPTROM_SIZE_83XX; 3047 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3048 ha->isp_ops = &qla8044_isp_ops; 3049 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3050 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3051 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3052 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3053 } else if (IS_QLA83XX(ha)) { 3054 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3055 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3056 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3057 req_length = REQUEST_ENTRY_CNT_83XX; 3058 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3059 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3060 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3061 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3062 ha->gid_list_info_size = 8; 3063 ha->optrom_size = OPTROM_SIZE_83XX; 3064 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3065 ha->isp_ops = &qla83xx_isp_ops; 3066 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3067 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3068 ha->nvram_conf_off = ~0; 3069 ha->nvram_data_off = ~0; 3070 } else if (IS_QLAFX00(ha)) { 3071 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3072 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3073 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3074 req_length = REQUEST_ENTRY_CNT_FX00; 3075 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3076 ha->isp_ops = &qlafx00_isp_ops; 3077 ha->port_down_retry_count = 30; /* default value */ 3078 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3079 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3080 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3081 ha->mr.fw_hbt_en = 1; 3082 ha->mr.host_info_resend = false; 3083 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3084 } else if (IS_QLA27XX(ha)) { 3085 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3086 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3087 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3088 req_length = REQUEST_ENTRY_CNT_83XX; 3089 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3090 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3091 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3092 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3093 ha->gid_list_info_size = 8; 3094 ha->optrom_size = OPTROM_SIZE_83XX; 3095 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3096 ha->isp_ops = &qla27xx_isp_ops; 3097 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3098 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3099 ha->nvram_conf_off = ~0; 3100 ha->nvram_data_off = ~0; 3101 } else if (IS_QLA28XX(ha)) { 3102 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3103 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3104 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3105 req_length = REQUEST_ENTRY_CNT_83XX; 3106 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3107 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3108 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3109 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3110 ha->gid_list_info_size = 8; 3111 ha->optrom_size = OPTROM_SIZE_28XX; 3112 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3113 ha->isp_ops = &qla27xx_isp_ops; 3114 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3115 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3116 ha->nvram_conf_off = ~0; 3117 ha->nvram_data_off = ~0; 3118 } 3119 3120 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3121 "mbx_count=%d, req_length=%d, " 3122 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3123 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3124 "max_fibre_devices=%d.\n", 3125 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3126 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3127 ha->nvram_npiv_size, ha->max_fibre_devices); 3128 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3129 "isp_ops=%p, flash_conf_off=%d, " 3130 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3131 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3132 ha->nvram_conf_off, ha->nvram_data_off); 3133 3134 /* Configure PCI I/O space */ 3135 ret = ha->isp_ops->iospace_config(ha); 3136 if (ret) 3137 goto iospace_config_failed; 3138 3139 ql_log_pci(ql_log_info, pdev, 0x001d, 3140 "Found an ISP%04X irq %d iobase 0x%p.\n", 3141 pdev->device, pdev->irq, ha->iobase); 3142 mutex_init(&ha->vport_lock); 3143 mutex_init(&ha->mq_lock); 3144 init_completion(&ha->mbx_cmd_comp); 3145 complete(&ha->mbx_cmd_comp); 3146 init_completion(&ha->mbx_intr_comp); 3147 init_completion(&ha->dcbx_comp); 3148 init_completion(&ha->lb_portup_comp); 3149 3150 set_bit(0, (unsigned long *) ha->vp_idx_map); 3151 3152 qla2x00_config_dma_addressing(ha); 3153 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3154 "64 Bit addressing is %s.\n", 3155 ha->flags.enable_64bit_addressing ? "enable" : 3156 "disable"); 3157 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3158 if (ret) { 3159 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3160 "Failed to allocate memory for adapter, aborting.\n"); 3161 3162 goto probe_hw_failed; 3163 } 3164 3165 req->max_q_depth = MAX_Q_DEPTH; 3166 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3167 req->max_q_depth = ql2xmaxqdepth; 3168 3169 3170 base_vha = qla2x00_create_host(sht, ha); 3171 if (!base_vha) { 3172 ret = -ENOMEM; 3173 goto probe_hw_failed; 3174 } 3175 3176 pci_set_drvdata(pdev, base_vha); 3177 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3178 3179 host = base_vha->host; 3180 base_vha->req = req; 3181 if (IS_QLA2XXX_MIDTYPE(ha)) 3182 base_vha->mgmt_svr_loop_id = 3183 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3184 else 3185 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3186 base_vha->vp_idx; 3187 3188 /* Setup fcport template structure. */ 3189 ha->mr.fcport.vha = base_vha; 3190 ha->mr.fcport.port_type = FCT_UNKNOWN; 3191 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3192 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3193 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3194 ha->mr.fcport.scan_state = 1; 3195 3196 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3197 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3198 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3199 3200 /* Set the SG table size based on ISP type */ 3201 if (!IS_FWI2_CAPABLE(ha)) { 3202 if (IS_QLA2100(ha)) 3203 host->sg_tablesize = 32; 3204 } else { 3205 if (!IS_QLA82XX(ha)) 3206 host->sg_tablesize = QLA_SG_ALL; 3207 } 3208 host->max_id = ha->max_fibre_devices; 3209 host->cmd_per_lun = 3; 3210 host->unique_id = host->host_no; 3211 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3212 host->max_cmd_len = 32; 3213 else 3214 host->max_cmd_len = MAX_CMDSZ; 3215 host->max_channel = MAX_BUSES - 1; 3216 /* Older HBAs support only 16-bit LUNs */ 3217 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3218 ql2xmaxlun > 0xffff) 3219 host->max_lun = 0xffff; 3220 else 3221 host->max_lun = ql2xmaxlun; 3222 host->transportt = qla2xxx_transport_template; 3223 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3224 3225 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3226 "max_id=%d this_id=%d " 3227 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3228 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3229 host->this_id, host->cmd_per_lun, host->unique_id, 3230 host->max_cmd_len, host->max_channel, host->max_lun, 3231 host->transportt, sht->vendor_id); 3232 3233 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3234 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3235 3236 /* Set up the irqs */ 3237 ret = qla2x00_request_irqs(ha, rsp); 3238 if (ret) 3239 goto probe_failed; 3240 3241 /* Alloc arrays of request and response ring ptrs */ 3242 ret = qla2x00_alloc_queues(ha, req, rsp); 3243 if (ret) { 3244 ql_log(ql_log_fatal, base_vha, 0x003d, 3245 "Failed to allocate memory for queue pointers..." 3246 "aborting.\n"); 3247 ret = -ENODEV; 3248 goto probe_failed; 3249 } 3250 3251 if (ha->mqenable) { 3252 /* number of hardware queues supported by blk/scsi-mq*/ 3253 host->nr_hw_queues = ha->max_qpairs; 3254 3255 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3256 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3257 } else { 3258 if (ql2xnvmeenable) { 3259 host->nr_hw_queues = ha->max_qpairs; 3260 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3261 "FC-NVMe support is enabled, HW queues=%d\n", 3262 host->nr_hw_queues); 3263 } else { 3264 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3265 "blk/scsi-mq disabled.\n"); 3266 } 3267 } 3268 3269 qlt_probe_one_stage1(base_vha, ha); 3270 3271 pci_save_state(pdev); 3272 3273 /* Assign back pointers */ 3274 rsp->req = req; 3275 req->rsp = rsp; 3276 3277 if (IS_QLAFX00(ha)) { 3278 ha->rsp_q_map[0] = rsp; 3279 ha->req_q_map[0] = req; 3280 set_bit(0, ha->req_qid_map); 3281 set_bit(0, ha->rsp_qid_map); 3282 } 3283 3284 /* FWI2-capable only. */ 3285 req->req_q_in = &ha->iobase->isp24.req_q_in; 3286 req->req_q_out = &ha->iobase->isp24.req_q_out; 3287 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3288 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3289 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3290 IS_QLA28XX(ha)) { 3291 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3292 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3293 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3294 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3295 } 3296 3297 if (IS_QLAFX00(ha)) { 3298 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3299 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3300 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3301 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3302 } 3303 3304 if (IS_P3P_TYPE(ha)) { 3305 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3306 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3307 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3308 } 3309 3310 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3311 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3312 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3313 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3314 "req->req_q_in=%p req->req_q_out=%p " 3315 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3316 req->req_q_in, req->req_q_out, 3317 rsp->rsp_q_in, rsp->rsp_q_out); 3318 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3319 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3320 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3321 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3322 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3323 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3324 3325 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3326 if (unlikely(!ha->wq)) { 3327 ret = -ENOMEM; 3328 goto probe_failed; 3329 } 3330 3331 if (ha->isp_ops->initialize_adapter(base_vha)) { 3332 ql_log(ql_log_fatal, base_vha, 0x00d6, 3333 "Failed to initialize adapter - Adapter flags %x.\n", 3334 base_vha->device_flags); 3335 3336 if (IS_QLA82XX(ha)) { 3337 qla82xx_idc_lock(ha); 3338 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3339 QLA8XXX_DEV_FAILED); 3340 qla82xx_idc_unlock(ha); 3341 ql_log(ql_log_fatal, base_vha, 0x00d7, 3342 "HW State: FAILED.\n"); 3343 } else if (IS_QLA8044(ha)) { 3344 qla8044_idc_lock(ha); 3345 qla8044_wr_direct(base_vha, 3346 QLA8044_CRB_DEV_STATE_INDEX, 3347 QLA8XXX_DEV_FAILED); 3348 qla8044_idc_unlock(ha); 3349 ql_log(ql_log_fatal, base_vha, 0x0150, 3350 "HW State: FAILED.\n"); 3351 } 3352 3353 ret = -ENODEV; 3354 goto probe_failed; 3355 } 3356 3357 if (IS_QLAFX00(ha)) 3358 host->can_queue = QLAFX00_MAX_CANQUEUE; 3359 else 3360 host->can_queue = req->num_outstanding_cmds - 10; 3361 3362 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3363 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3364 host->can_queue, base_vha->req, 3365 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3366 3367 /* Check if FW supports MQ or not for ISP25xx */ 3368 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3369 ha->mqenable = 0; 3370 3371 if (ha->mqenable) { 3372 bool startit = false; 3373 3374 if (QLA_TGT_MODE_ENABLED()) 3375 startit = false; 3376 3377 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3378 startit = true; 3379 3380 /* Create start of day qpairs for Block MQ */ 3381 for (i = 0; i < ha->max_qpairs; i++) 3382 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3383 } 3384 qla_init_iocb_limit(base_vha); 3385 3386 if (ha->flags.running_gold_fw) 3387 goto skip_dpc; 3388 3389 /* 3390 * Startup the kernel thread for this host adapter 3391 */ 3392 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3393 "%s_dpc", base_vha->host_str); 3394 if (IS_ERR(ha->dpc_thread)) { 3395 ql_log(ql_log_fatal, base_vha, 0x00ed, 3396 "Failed to start DPC thread.\n"); 3397 ret = PTR_ERR(ha->dpc_thread); 3398 ha->dpc_thread = NULL; 3399 goto probe_failed; 3400 } 3401 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3402 "DPC thread started successfully.\n"); 3403 3404 /* 3405 * If we're not coming up in initiator mode, we might sit for 3406 * a while without waking up the dpc thread, which leads to a 3407 * stuck process warning. So just kick the dpc once here and 3408 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3409 */ 3410 qla2xxx_wake_dpc(base_vha); 3411 3412 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3413 3414 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3415 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3416 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3417 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3418 3419 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3420 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3421 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3422 INIT_WORK(&ha->idc_state_handler, 3423 qla83xx_idc_state_handler_work); 3424 INIT_WORK(&ha->nic_core_unrecoverable, 3425 qla83xx_nic_core_unrecoverable_work); 3426 } 3427 3428 skip_dpc: 3429 list_add_tail(&base_vha->list, &ha->vp_list); 3430 base_vha->host->irq = ha->pdev->irq; 3431 3432 /* Initialized the timer */ 3433 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3434 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3435 "Started qla2x00_timer with " 3436 "interval=%d.\n", WATCH_INTERVAL); 3437 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3438 "Detected hba at address=%p.\n", 3439 ha); 3440 3441 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3442 if (ha->fw_attributes & BIT_4) { 3443 int prot = 0, guard; 3444 3445 base_vha->flags.difdix_supported = 1; 3446 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3447 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3448 if (ql2xenabledif == 1) 3449 prot = SHOST_DIX_TYPE0_PROTECTION; 3450 if (ql2xprotmask) 3451 scsi_host_set_prot(host, ql2xprotmask); 3452 else 3453 scsi_host_set_prot(host, 3454 prot | SHOST_DIF_TYPE1_PROTECTION 3455 | SHOST_DIF_TYPE2_PROTECTION 3456 | SHOST_DIF_TYPE3_PROTECTION 3457 | SHOST_DIX_TYPE1_PROTECTION 3458 | SHOST_DIX_TYPE2_PROTECTION 3459 | SHOST_DIX_TYPE3_PROTECTION); 3460 3461 guard = SHOST_DIX_GUARD_CRC; 3462 3463 if (IS_PI_IPGUARD_CAPABLE(ha) && 3464 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3465 guard |= SHOST_DIX_GUARD_IP; 3466 3467 if (ql2xprotguard) 3468 scsi_host_set_guard(host, ql2xprotguard); 3469 else 3470 scsi_host_set_guard(host, guard); 3471 } else 3472 base_vha->flags.difdix_supported = 0; 3473 } 3474 3475 ha->isp_ops->enable_intrs(ha); 3476 3477 if (IS_QLAFX00(ha)) { 3478 ret = qlafx00_fx_disc(base_vha, 3479 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3480 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3481 QLA_SG_ALL : 128; 3482 } 3483 3484 ret = scsi_add_host(host, &pdev->dev); 3485 if (ret) 3486 goto probe_failed; 3487 3488 base_vha->flags.init_done = 1; 3489 base_vha->flags.online = 1; 3490 ha->prev_minidump_failed = 0; 3491 3492 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3493 "Init done and hba is online.\n"); 3494 3495 if (qla_ini_mode_enabled(base_vha) || 3496 qla_dual_mode_enabled(base_vha)) 3497 scsi_scan_host(host); 3498 else 3499 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3500 "skipping scsi_scan_host() for non-initiator port\n"); 3501 3502 qla2x00_alloc_sysfs_attr(base_vha); 3503 3504 if (IS_QLAFX00(ha)) { 3505 ret = qlafx00_fx_disc(base_vha, 3506 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3507 3508 /* Register system information */ 3509 ret = qlafx00_fx_disc(base_vha, 3510 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3511 } 3512 3513 qla2x00_init_host_attr(base_vha); 3514 3515 qla2x00_dfs_setup(base_vha); 3516 3517 ql_log(ql_log_info, base_vha, 0x00fb, 3518 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3519 ql_log(ql_log_info, base_vha, 0x00fc, 3520 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3521 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3522 sizeof(pci_info)), 3523 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3524 base_vha->host_no, 3525 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3526 3527 qlt_add_target(ha, base_vha); 3528 3529 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3530 3531 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3532 return -ENODEV; 3533 3534 return 0; 3535 3536 probe_failed: 3537 qla_enode_stop(base_vha); 3538 qla_edb_stop(base_vha); 3539 if (base_vha->gnl.l) { 3540 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3541 base_vha->gnl.l, base_vha->gnl.ldma); 3542 base_vha->gnl.l = NULL; 3543 } 3544 3545 if (base_vha->timer_active) 3546 qla2x00_stop_timer(base_vha); 3547 base_vha->flags.online = 0; 3548 if (ha->dpc_thread) { 3549 struct task_struct *t = ha->dpc_thread; 3550 3551 ha->dpc_thread = NULL; 3552 kthread_stop(t); 3553 } 3554 3555 qla2x00_free_device(base_vha); 3556 scsi_host_put(base_vha->host); 3557 /* 3558 * Need to NULL out local req/rsp after 3559 * qla2x00_free_device => qla2x00_free_queues frees 3560 * what these are pointing to. Or else we'll 3561 * fall over below in qla2x00_free_req/rsp_que. 3562 */ 3563 req = NULL; 3564 rsp = NULL; 3565 3566 probe_hw_failed: 3567 qla2x00_mem_free(ha); 3568 qla2x00_free_req_que(ha, req); 3569 qla2x00_free_rsp_que(ha, rsp); 3570 qla2x00_clear_drv_active(ha); 3571 3572 iospace_config_failed: 3573 if (IS_P3P_TYPE(ha)) { 3574 if (!ha->nx_pcibase) 3575 iounmap((device_reg_t *)ha->nx_pcibase); 3576 if (!ql2xdbwr) 3577 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3578 } else { 3579 if (ha->iobase) 3580 iounmap(ha->iobase); 3581 if (ha->cregbase) 3582 iounmap(ha->cregbase); 3583 } 3584 pci_release_selected_regions(ha->pdev, ha->bars); 3585 kfree(ha); 3586 3587 disable_device: 3588 pci_disable_device(pdev); 3589 return ret; 3590 } 3591 3592 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3593 { 3594 scsi_qla_host_t *vp; 3595 unsigned long flags; 3596 struct qla_hw_data *ha; 3597 3598 if (!base_vha) 3599 return; 3600 3601 ha = base_vha->hw; 3602 3603 spin_lock_irqsave(&ha->vport_slock, flags); 3604 list_for_each_entry(vp, &ha->vp_list, list) 3605 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3606 3607 /* 3608 * Indicate device removal to prevent future board_disable 3609 * and wait until any pending board_disable has completed. 3610 */ 3611 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3612 spin_unlock_irqrestore(&ha->vport_slock, flags); 3613 } 3614 3615 static void 3616 qla2x00_shutdown(struct pci_dev *pdev) 3617 { 3618 scsi_qla_host_t *vha; 3619 struct qla_hw_data *ha; 3620 3621 vha = pci_get_drvdata(pdev); 3622 ha = vha->hw; 3623 3624 ql_log(ql_log_info, vha, 0xfffa, 3625 "Adapter shutdown\n"); 3626 3627 /* 3628 * Prevent future board_disable and wait 3629 * until any pending board_disable has completed. 3630 */ 3631 __qla_set_remove_flag(vha); 3632 cancel_work_sync(&ha->board_disable); 3633 3634 if (!atomic_read(&pdev->enable_cnt)) 3635 return; 3636 3637 /* Notify ISPFX00 firmware */ 3638 if (IS_QLAFX00(ha)) 3639 qlafx00_driver_shutdown(vha, 20); 3640 3641 /* Turn-off FCE trace */ 3642 if (ha->flags.fce_enabled) { 3643 qla2x00_disable_fce_trace(vha, NULL, NULL); 3644 ha->flags.fce_enabled = 0; 3645 } 3646 3647 /* Turn-off EFT trace */ 3648 if (ha->eft) 3649 qla2x00_disable_eft_trace(vha); 3650 3651 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3652 IS_QLA28XX(ha)) { 3653 if (ha->flags.fw_started) 3654 qla2x00_abort_isp_cleanup(vha); 3655 } else { 3656 /* Stop currently executing firmware. */ 3657 qla2x00_try_to_stop_firmware(vha); 3658 } 3659 3660 /* Disable timer */ 3661 if (vha->timer_active) 3662 qla2x00_stop_timer(vha); 3663 3664 /* Turn adapter off line */ 3665 vha->flags.online = 0; 3666 3667 /* turn-off interrupts on the card */ 3668 if (ha->interrupts_on) { 3669 vha->flags.init_done = 0; 3670 ha->isp_ops->disable_intrs(ha); 3671 } 3672 3673 qla2x00_free_irqs(vha); 3674 3675 qla2x00_free_fw_dump(ha); 3676 3677 pci_disable_device(pdev); 3678 ql_log(ql_log_info, vha, 0xfffe, 3679 "Adapter shutdown successfully.\n"); 3680 } 3681 3682 /* Deletes all the virtual ports for a given ha */ 3683 static void 3684 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3685 { 3686 scsi_qla_host_t *vha; 3687 unsigned long flags; 3688 3689 mutex_lock(&ha->vport_lock); 3690 while (ha->cur_vport_count) { 3691 spin_lock_irqsave(&ha->vport_slock, flags); 3692 3693 BUG_ON(base_vha->list.next == &ha->vp_list); 3694 /* This assumes first entry in ha->vp_list is always base vha */ 3695 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3696 scsi_host_get(vha->host); 3697 3698 spin_unlock_irqrestore(&ha->vport_slock, flags); 3699 mutex_unlock(&ha->vport_lock); 3700 3701 qla_nvme_delete(vha); 3702 3703 fc_vport_terminate(vha->fc_vport); 3704 scsi_host_put(vha->host); 3705 3706 mutex_lock(&ha->vport_lock); 3707 } 3708 mutex_unlock(&ha->vport_lock); 3709 } 3710 3711 /* Stops all deferred work threads */ 3712 static void 3713 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3714 { 3715 /* Cancel all work and destroy DPC workqueues */ 3716 if (ha->dpc_lp_wq) { 3717 cancel_work_sync(&ha->idc_aen); 3718 destroy_workqueue(ha->dpc_lp_wq); 3719 ha->dpc_lp_wq = NULL; 3720 } 3721 3722 if (ha->dpc_hp_wq) { 3723 cancel_work_sync(&ha->nic_core_reset); 3724 cancel_work_sync(&ha->idc_state_handler); 3725 cancel_work_sync(&ha->nic_core_unrecoverable); 3726 destroy_workqueue(ha->dpc_hp_wq); 3727 ha->dpc_hp_wq = NULL; 3728 } 3729 3730 /* Kill the kernel thread for this host */ 3731 if (ha->dpc_thread) { 3732 struct task_struct *t = ha->dpc_thread; 3733 3734 /* 3735 * qla2xxx_wake_dpc checks for ->dpc_thread 3736 * so we need to zero it out. 3737 */ 3738 ha->dpc_thread = NULL; 3739 kthread_stop(t); 3740 } 3741 } 3742 3743 static void 3744 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3745 { 3746 if (IS_QLA82XX(ha)) { 3747 3748 iounmap((device_reg_t *)ha->nx_pcibase); 3749 if (!ql2xdbwr) 3750 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3751 } else { 3752 if (ha->iobase) 3753 iounmap(ha->iobase); 3754 3755 if (ha->cregbase) 3756 iounmap(ha->cregbase); 3757 3758 if (ha->mqiobase) 3759 iounmap(ha->mqiobase); 3760 3761 if (ha->msixbase) 3762 iounmap(ha->msixbase); 3763 } 3764 } 3765 3766 static void 3767 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3768 { 3769 if (IS_QLA8044(ha)) { 3770 qla8044_idc_lock(ha); 3771 qla8044_clear_drv_active(ha); 3772 qla8044_idc_unlock(ha); 3773 } else if (IS_QLA82XX(ha)) { 3774 qla82xx_idc_lock(ha); 3775 qla82xx_clear_drv_active(ha); 3776 qla82xx_idc_unlock(ha); 3777 } 3778 } 3779 3780 static void 3781 qla2x00_remove_one(struct pci_dev *pdev) 3782 { 3783 scsi_qla_host_t *base_vha; 3784 struct qla_hw_data *ha; 3785 3786 base_vha = pci_get_drvdata(pdev); 3787 ha = base_vha->hw; 3788 ql_log(ql_log_info, base_vha, 0xb079, 3789 "Removing driver\n"); 3790 __qla_set_remove_flag(base_vha); 3791 cancel_work_sync(&ha->board_disable); 3792 3793 /* 3794 * If the PCI device is disabled then there was a PCI-disconnect and 3795 * qla2x00_disable_board_on_pci_error has taken care of most of the 3796 * resources. 3797 */ 3798 if (!atomic_read(&pdev->enable_cnt)) { 3799 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3800 base_vha->gnl.l, base_vha->gnl.ldma); 3801 base_vha->gnl.l = NULL; 3802 scsi_host_put(base_vha->host); 3803 kfree(ha); 3804 pci_set_drvdata(pdev, NULL); 3805 return; 3806 } 3807 qla2x00_wait_for_hba_ready(base_vha); 3808 3809 /* 3810 * if UNLOADING flag is already set, then continue unload, 3811 * where it was set first. 3812 */ 3813 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3814 return; 3815 3816 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3817 IS_QLA28XX(ha)) { 3818 if (ha->flags.fw_started) 3819 qla2x00_abort_isp_cleanup(base_vha); 3820 } else if (!IS_QLAFX00(ha)) { 3821 if (IS_QLA8031(ha)) { 3822 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3823 "Clearing fcoe driver presence.\n"); 3824 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3825 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3826 "Error while clearing DRV-Presence.\n"); 3827 } 3828 3829 qla2x00_try_to_stop_firmware(base_vha); 3830 } 3831 3832 qla2x00_wait_for_sess_deletion(base_vha); 3833 3834 qla_nvme_delete(base_vha); 3835 3836 dma_free_coherent(&ha->pdev->dev, 3837 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3838 3839 base_vha->gnl.l = NULL; 3840 qla_enode_stop(base_vha); 3841 qla_edb_stop(base_vha); 3842 3843 vfree(base_vha->scan.l); 3844 3845 if (IS_QLAFX00(ha)) 3846 qlafx00_driver_shutdown(base_vha, 20); 3847 3848 qla2x00_delete_all_vps(ha, base_vha); 3849 3850 qla2x00_dfs_remove(base_vha); 3851 3852 qla84xx_put_chip(base_vha); 3853 3854 /* Disable timer */ 3855 if (base_vha->timer_active) 3856 qla2x00_stop_timer(base_vha); 3857 3858 base_vha->flags.online = 0; 3859 3860 /* free DMA memory */ 3861 if (ha->exlogin_buf) 3862 qla2x00_free_exlogin_buffer(ha); 3863 3864 /* free DMA memory */ 3865 if (ha->exchoffld_buf) 3866 qla2x00_free_exchoffld_buffer(ha); 3867 3868 qla2x00_destroy_deferred_work(ha); 3869 3870 qlt_remove_target(ha, base_vha); 3871 3872 qla2x00_free_sysfs_attr(base_vha, true); 3873 3874 fc_remove_host(base_vha->host); 3875 3876 scsi_remove_host(base_vha->host); 3877 3878 qla2x00_free_device(base_vha); 3879 3880 qla2x00_clear_drv_active(ha); 3881 3882 scsi_host_put(base_vha->host); 3883 3884 qla2x00_unmap_iobases(ha); 3885 3886 pci_release_selected_regions(ha->pdev, ha->bars); 3887 kfree(ha); 3888 3889 pci_disable_pcie_error_reporting(pdev); 3890 3891 pci_disable_device(pdev); 3892 } 3893 3894 static inline void 3895 qla24xx_free_purex_list(struct purex_list *list) 3896 { 3897 struct purex_item *item, *next; 3898 ulong flags; 3899 3900 spin_lock_irqsave(&list->lock, flags); 3901 list_for_each_entry_safe(item, next, &list->head, list) { 3902 list_del(&item->list); 3903 if (item == &item->vha->default_item) 3904 continue; 3905 kfree(item); 3906 } 3907 spin_unlock_irqrestore(&list->lock, flags); 3908 } 3909 3910 static void 3911 qla2x00_free_device(scsi_qla_host_t *vha) 3912 { 3913 struct qla_hw_data *ha = vha->hw; 3914 3915 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3916 3917 /* Disable timer */ 3918 if (vha->timer_active) 3919 qla2x00_stop_timer(vha); 3920 3921 qla25xx_delete_queues(vha); 3922 vha->flags.online = 0; 3923 3924 /* turn-off interrupts on the card */ 3925 if (ha->interrupts_on) { 3926 vha->flags.init_done = 0; 3927 ha->isp_ops->disable_intrs(ha); 3928 } 3929 3930 qla2x00_free_fcports(vha); 3931 3932 qla2x00_free_irqs(vha); 3933 3934 /* Flush the work queue and remove it */ 3935 if (ha->wq) { 3936 flush_workqueue(ha->wq); 3937 destroy_workqueue(ha->wq); 3938 ha->wq = NULL; 3939 } 3940 3941 3942 qla24xx_free_purex_list(&vha->purex_list); 3943 3944 qla2x00_mem_free(ha); 3945 3946 qla82xx_md_free(vha); 3947 3948 qla_edif_sadb_release_free_pool(ha); 3949 qla_edif_sadb_release(ha); 3950 3951 qla2x00_free_queues(ha); 3952 } 3953 3954 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3955 { 3956 fc_port_t *fcport, *tfcport; 3957 3958 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3959 qla2x00_free_fcport(fcport); 3960 } 3961 3962 static inline void 3963 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3964 { 3965 int now; 3966 3967 if (!fcport->rport) 3968 return; 3969 3970 if (fcport->rport) { 3971 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3972 "%s %8phN. rport %p roles %x\n", 3973 __func__, fcport->port_name, fcport->rport, 3974 fcport->rport->roles); 3975 fc_remote_port_delete(fcport->rport); 3976 } 3977 qlt_do_generation_tick(vha, &now); 3978 } 3979 3980 /* 3981 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3982 * 3983 * Input: ha = adapter block pointer. fcport = port structure pointer. 3984 * 3985 * Return: None. 3986 * 3987 * Context: 3988 */ 3989 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3990 int do_login) 3991 { 3992 if (IS_QLAFX00(vha->hw)) { 3993 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3994 qla2x00_schedule_rport_del(vha, fcport); 3995 return; 3996 } 3997 3998 if (atomic_read(&fcport->state) == FCS_ONLINE && 3999 vha->vp_idx == fcport->vha->vp_idx) { 4000 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4001 qla2x00_schedule_rport_del(vha, fcport); 4002 } 4003 4004 /* 4005 * We may need to retry the login, so don't change the state of the 4006 * port but do the retries. 4007 */ 4008 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4009 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4010 4011 if (!do_login) 4012 return; 4013 4014 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4015 } 4016 4017 void 4018 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4019 { 4020 fc_port_t *fcport; 4021 4022 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4023 "Mark all dev lost\n"); 4024 4025 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4026 if (fcport->loop_id != FC_NO_LOOP_ID && 4027 (fcport->flags & FCF_FCP2_DEVICE) && 4028 fcport->port_type == FCT_TARGET && 4029 !qla2x00_reset_active(vha)) { 4030 ql_dbg(ql_dbg_disc, vha, 0x211a, 4031 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4032 fcport->flags, fcport->port_type, 4033 fcport->d_id.b24, fcport->port_name); 4034 continue; 4035 } 4036 fcport->scan_state = 0; 4037 qlt_schedule_sess_for_deletion(fcport); 4038 } 4039 } 4040 4041 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4042 { 4043 int i; 4044 4045 if (IS_FWI2_CAPABLE(ha)) 4046 return; 4047 4048 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4049 set_bit(i, ha->loop_id_map); 4050 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4051 set_bit(BROADCAST, ha->loop_id_map); 4052 } 4053 4054 /* 4055 * qla2x00_mem_alloc 4056 * Allocates adapter memory. 4057 * 4058 * Returns: 4059 * 0 = success. 4060 * !0 = failure. 4061 */ 4062 static int 4063 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4064 struct req_que **req, struct rsp_que **rsp) 4065 { 4066 char name[16]; 4067 int rc; 4068 4069 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4070 &ha->init_cb_dma, GFP_KERNEL); 4071 if (!ha->init_cb) 4072 goto fail; 4073 4074 rc = btree_init32(&ha->host_map); 4075 if (rc) 4076 goto fail_free_init_cb; 4077 4078 if (qlt_mem_alloc(ha) < 0) 4079 goto fail_free_btree; 4080 4081 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4082 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4083 if (!ha->gid_list) 4084 goto fail_free_tgt_mem; 4085 4086 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4087 if (!ha->srb_mempool) 4088 goto fail_free_gid_list; 4089 4090 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4091 /* Allocate cache for CT6 Ctx. */ 4092 if (!ctx_cachep) { 4093 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4094 sizeof(struct ct6_dsd), 0, 4095 SLAB_HWCACHE_ALIGN, NULL); 4096 if (!ctx_cachep) 4097 goto fail_free_srb_mempool; 4098 } 4099 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4100 ctx_cachep); 4101 if (!ha->ctx_mempool) 4102 goto fail_free_srb_mempool; 4103 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4104 "ctx_cachep=%p ctx_mempool=%p.\n", 4105 ctx_cachep, ha->ctx_mempool); 4106 } 4107 4108 /* Get memory for cached NVRAM */ 4109 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4110 if (!ha->nvram) 4111 goto fail_free_ctx_mempool; 4112 4113 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4114 ha->pdev->device); 4115 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4116 DMA_POOL_SIZE, 8, 0); 4117 if (!ha->s_dma_pool) 4118 goto fail_free_nvram; 4119 4120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4121 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4122 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4123 4124 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4125 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4126 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4127 if (!ha->dl_dma_pool) { 4128 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4129 "Failed to allocate memory for dl_dma_pool.\n"); 4130 goto fail_s_dma_pool; 4131 } 4132 4133 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4134 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4135 if (!ha->fcp_cmnd_dma_pool) { 4136 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4137 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4138 goto fail_dl_dma_pool; 4139 } 4140 4141 if (ql2xenabledif) { 4142 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4143 struct dsd_dma *dsd, *nxt; 4144 uint i; 4145 /* Creata a DMA pool of buffers for DIF bundling */ 4146 ha->dif_bundl_pool = dma_pool_create(name, 4147 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4148 if (!ha->dif_bundl_pool) { 4149 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4150 "%s: failed create dif_bundl_pool\n", 4151 __func__); 4152 goto fail_dif_bundl_dma_pool; 4153 } 4154 4155 INIT_LIST_HEAD(&ha->pool.good.head); 4156 INIT_LIST_HEAD(&ha->pool.unusable.head); 4157 ha->pool.good.count = 0; 4158 ha->pool.unusable.count = 0; 4159 for (i = 0; i < 128; i++) { 4160 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4161 if (!dsd) { 4162 ql_dbg_pci(ql_dbg_init, ha->pdev, 4163 0xe0ee, "%s: failed alloc dsd\n", 4164 __func__); 4165 return -ENOMEM; 4166 } 4167 ha->dif_bundle_kallocs++; 4168 4169 dsd->dsd_addr = dma_pool_alloc( 4170 ha->dif_bundl_pool, GFP_ATOMIC, 4171 &dsd->dsd_list_dma); 4172 if (!dsd->dsd_addr) { 4173 ql_dbg_pci(ql_dbg_init, ha->pdev, 4174 0xe0ee, 4175 "%s: failed alloc ->dsd_addr\n", 4176 __func__); 4177 kfree(dsd); 4178 ha->dif_bundle_kallocs--; 4179 continue; 4180 } 4181 ha->dif_bundle_dma_allocs++; 4182 4183 /* 4184 * if DMA buffer crosses 4G boundary, 4185 * put it on bad list 4186 */ 4187 if (MSD(dsd->dsd_list_dma) ^ 4188 MSD(dsd->dsd_list_dma + bufsize)) { 4189 list_add_tail(&dsd->list, 4190 &ha->pool.unusable.head); 4191 ha->pool.unusable.count++; 4192 } else { 4193 list_add_tail(&dsd->list, 4194 &ha->pool.good.head); 4195 ha->pool.good.count++; 4196 } 4197 } 4198 4199 /* return the good ones back to the pool */ 4200 list_for_each_entry_safe(dsd, nxt, 4201 &ha->pool.good.head, list) { 4202 list_del(&dsd->list); 4203 dma_pool_free(ha->dif_bundl_pool, 4204 dsd->dsd_addr, dsd->dsd_list_dma); 4205 ha->dif_bundle_dma_allocs--; 4206 kfree(dsd); 4207 ha->dif_bundle_kallocs--; 4208 } 4209 4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4211 "%s: dif dma pool (good=%u unusable=%u)\n", 4212 __func__, ha->pool.good.count, 4213 ha->pool.unusable.count); 4214 } 4215 4216 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4217 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4218 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4219 ha->dif_bundl_pool); 4220 } 4221 4222 /* Allocate memory for SNS commands */ 4223 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4224 /* Get consistent memory allocated for SNS commands */ 4225 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4226 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4227 if (!ha->sns_cmd) 4228 goto fail_dma_pool; 4229 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4230 "sns_cmd: %p.\n", ha->sns_cmd); 4231 } else { 4232 /* Get consistent memory allocated for MS IOCB */ 4233 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4234 &ha->ms_iocb_dma); 4235 if (!ha->ms_iocb) 4236 goto fail_dma_pool; 4237 /* Get consistent memory allocated for CT SNS commands */ 4238 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4239 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4240 if (!ha->ct_sns) 4241 goto fail_free_ms_iocb; 4242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4243 "ms_iocb=%p ct_sns=%p.\n", 4244 ha->ms_iocb, ha->ct_sns); 4245 } 4246 4247 /* Allocate memory for request ring */ 4248 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4249 if (!*req) { 4250 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4251 "Failed to allocate memory for req.\n"); 4252 goto fail_req; 4253 } 4254 (*req)->length = req_len; 4255 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4256 ((*req)->length + 1) * sizeof(request_t), 4257 &(*req)->dma, GFP_KERNEL); 4258 if (!(*req)->ring) { 4259 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4260 "Failed to allocate memory for req_ring.\n"); 4261 goto fail_req_ring; 4262 } 4263 /* Allocate memory for response ring */ 4264 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4265 if (!*rsp) { 4266 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4267 "Failed to allocate memory for rsp.\n"); 4268 goto fail_rsp; 4269 } 4270 (*rsp)->hw = ha; 4271 (*rsp)->length = rsp_len; 4272 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4273 ((*rsp)->length + 1) * sizeof(response_t), 4274 &(*rsp)->dma, GFP_KERNEL); 4275 if (!(*rsp)->ring) { 4276 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4277 "Failed to allocate memory for rsp_ring.\n"); 4278 goto fail_rsp_ring; 4279 } 4280 (*req)->rsp = *rsp; 4281 (*rsp)->req = *req; 4282 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4283 "req=%p req->length=%d req->ring=%p rsp=%p " 4284 "rsp->length=%d rsp->ring=%p.\n", 4285 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4286 (*rsp)->ring); 4287 /* Allocate memory for NVRAM data for vports */ 4288 if (ha->nvram_npiv_size) { 4289 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4290 sizeof(struct qla_npiv_entry), 4291 GFP_KERNEL); 4292 if (!ha->npiv_info) { 4293 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4294 "Failed to allocate memory for npiv_info.\n"); 4295 goto fail_npiv_info; 4296 } 4297 } else 4298 ha->npiv_info = NULL; 4299 4300 /* Get consistent memory allocated for EX-INIT-CB. */ 4301 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4302 IS_QLA28XX(ha)) { 4303 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4304 &ha->ex_init_cb_dma); 4305 if (!ha->ex_init_cb) 4306 goto fail_ex_init_cb; 4307 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4308 "ex_init_cb=%p.\n", ha->ex_init_cb); 4309 } 4310 4311 /* Get consistent memory allocated for Special Features-CB. */ 4312 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4313 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4314 &ha->sf_init_cb_dma); 4315 if (!ha->sf_init_cb) 4316 goto fail_sf_init_cb; 4317 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4318 "sf_init_cb=%p.\n", ha->sf_init_cb); 4319 } 4320 4321 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4322 4323 /* Get consistent memory allocated for Async Port-Database. */ 4324 if (!IS_FWI2_CAPABLE(ha)) { 4325 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4326 &ha->async_pd_dma); 4327 if (!ha->async_pd) 4328 goto fail_async_pd; 4329 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4330 "async_pd=%p.\n", ha->async_pd); 4331 } 4332 4333 INIT_LIST_HEAD(&ha->vp_list); 4334 4335 /* Allocate memory for our loop_id bitmap */ 4336 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4337 sizeof(long), 4338 GFP_KERNEL); 4339 if (!ha->loop_id_map) 4340 goto fail_loop_id_map; 4341 else { 4342 qla2x00_set_reserved_loop_ids(ha); 4343 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4344 "loop_id_map=%p.\n", ha->loop_id_map); 4345 } 4346 4347 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4348 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4349 if (!ha->sfp_data) { 4350 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4351 "Unable to allocate memory for SFP read-data.\n"); 4352 goto fail_sfp_data; 4353 } 4354 4355 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4356 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4357 GFP_KERNEL); 4358 if (!ha->flt) { 4359 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4360 "Unable to allocate memory for FLT.\n"); 4361 goto fail_flt_buffer; 4362 } 4363 4364 /* allocate the purex dma pool */ 4365 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4366 ELS_MAX_PAYLOAD, 8, 0); 4367 4368 if (!ha->purex_dma_pool) { 4369 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4370 "Unable to allocate purex_dma_pool.\n"); 4371 goto fail_flt; 4372 } 4373 4374 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4375 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4376 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4377 4378 if (!ha->elsrej.c) { 4379 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4380 "Alloc failed for els reject cmd.\n"); 4381 goto fail_elsrej; 4382 } 4383 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4384 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4385 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4386 return 0; 4387 4388 fail_elsrej: 4389 dma_pool_destroy(ha->purex_dma_pool); 4390 fail_flt: 4391 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4392 ha->flt, ha->flt_dma); 4393 4394 fail_flt_buffer: 4395 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4396 ha->sfp_data, ha->sfp_data_dma); 4397 fail_sfp_data: 4398 kfree(ha->loop_id_map); 4399 fail_loop_id_map: 4400 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4401 fail_async_pd: 4402 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4403 fail_sf_init_cb: 4404 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4405 fail_ex_init_cb: 4406 kfree(ha->npiv_info); 4407 fail_npiv_info: 4408 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4409 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4410 (*rsp)->ring = NULL; 4411 (*rsp)->dma = 0; 4412 fail_rsp_ring: 4413 kfree(*rsp); 4414 *rsp = NULL; 4415 fail_rsp: 4416 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4417 sizeof(request_t), (*req)->ring, (*req)->dma); 4418 (*req)->ring = NULL; 4419 (*req)->dma = 0; 4420 fail_req_ring: 4421 kfree(*req); 4422 *req = NULL; 4423 fail_req: 4424 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4425 ha->ct_sns, ha->ct_sns_dma); 4426 ha->ct_sns = NULL; 4427 ha->ct_sns_dma = 0; 4428 fail_free_ms_iocb: 4429 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4430 ha->ms_iocb = NULL; 4431 ha->ms_iocb_dma = 0; 4432 4433 if (ha->sns_cmd) 4434 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4435 ha->sns_cmd, ha->sns_cmd_dma); 4436 fail_dma_pool: 4437 if (ql2xenabledif) { 4438 struct dsd_dma *dsd, *nxt; 4439 4440 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4441 list) { 4442 list_del(&dsd->list); 4443 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4444 dsd->dsd_list_dma); 4445 ha->dif_bundle_dma_allocs--; 4446 kfree(dsd); 4447 ha->dif_bundle_kallocs--; 4448 ha->pool.unusable.count--; 4449 } 4450 dma_pool_destroy(ha->dif_bundl_pool); 4451 ha->dif_bundl_pool = NULL; 4452 } 4453 4454 fail_dif_bundl_dma_pool: 4455 if (IS_QLA82XX(ha) || ql2xenabledif) { 4456 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4457 ha->fcp_cmnd_dma_pool = NULL; 4458 } 4459 fail_dl_dma_pool: 4460 if (IS_QLA82XX(ha) || ql2xenabledif) { 4461 dma_pool_destroy(ha->dl_dma_pool); 4462 ha->dl_dma_pool = NULL; 4463 } 4464 fail_s_dma_pool: 4465 dma_pool_destroy(ha->s_dma_pool); 4466 ha->s_dma_pool = NULL; 4467 fail_free_nvram: 4468 kfree(ha->nvram); 4469 ha->nvram = NULL; 4470 fail_free_ctx_mempool: 4471 mempool_destroy(ha->ctx_mempool); 4472 ha->ctx_mempool = NULL; 4473 fail_free_srb_mempool: 4474 mempool_destroy(ha->srb_mempool); 4475 ha->srb_mempool = NULL; 4476 fail_free_gid_list: 4477 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4478 ha->gid_list, 4479 ha->gid_list_dma); 4480 ha->gid_list = NULL; 4481 ha->gid_list_dma = 0; 4482 fail_free_tgt_mem: 4483 qlt_mem_free(ha); 4484 fail_free_btree: 4485 btree_destroy32(&ha->host_map); 4486 fail_free_init_cb: 4487 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4488 ha->init_cb_dma); 4489 ha->init_cb = NULL; 4490 ha->init_cb_dma = 0; 4491 fail: 4492 ql_log(ql_log_fatal, NULL, 0x0030, 4493 "Memory allocation failure.\n"); 4494 return -ENOMEM; 4495 } 4496 4497 int 4498 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4499 { 4500 int rval; 4501 uint16_t size, max_cnt; 4502 uint32_t temp; 4503 struct qla_hw_data *ha = vha->hw; 4504 4505 /* Return if we don't need to alloacate any extended logins */ 4506 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4507 return QLA_SUCCESS; 4508 4509 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4510 return QLA_SUCCESS; 4511 4512 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4513 max_cnt = 0; 4514 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4515 if (rval != QLA_SUCCESS) { 4516 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4517 "Failed to get exlogin status.\n"); 4518 return rval; 4519 } 4520 4521 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4522 temp *= size; 4523 4524 if (temp != ha->exlogin_size) { 4525 qla2x00_free_exlogin_buffer(ha); 4526 ha->exlogin_size = temp; 4527 4528 ql_log(ql_log_info, vha, 0xd024, 4529 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4530 max_cnt, size, temp); 4531 4532 ql_log(ql_log_info, vha, 0xd025, 4533 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4534 4535 /* Get consistent memory for extended logins */ 4536 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4537 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4538 if (!ha->exlogin_buf) { 4539 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4540 "Failed to allocate memory for exlogin_buf_dma.\n"); 4541 return -ENOMEM; 4542 } 4543 } 4544 4545 /* Now configure the dma buffer */ 4546 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4547 if (rval) { 4548 ql_log(ql_log_fatal, vha, 0xd033, 4549 "Setup extended login buffer ****FAILED****.\n"); 4550 qla2x00_free_exlogin_buffer(ha); 4551 } 4552 4553 return rval; 4554 } 4555 4556 /* 4557 * qla2x00_free_exlogin_buffer 4558 * 4559 * Input: 4560 * ha = adapter block pointer 4561 */ 4562 void 4563 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4564 { 4565 if (ha->exlogin_buf) { 4566 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4567 ha->exlogin_buf, ha->exlogin_buf_dma); 4568 ha->exlogin_buf = NULL; 4569 ha->exlogin_size = 0; 4570 } 4571 } 4572 4573 static void 4574 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4575 { 4576 u32 temp; 4577 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4578 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4579 4580 if (max_cnt > vha->hw->max_exchg) 4581 max_cnt = vha->hw->max_exchg; 4582 4583 if (qla_ini_mode_enabled(vha)) { 4584 if (vha->ql2xiniexchg > max_cnt) 4585 vha->ql2xiniexchg = max_cnt; 4586 4587 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4588 *ret_cnt = vha->ql2xiniexchg; 4589 4590 } else if (qla_tgt_mode_enabled(vha)) { 4591 if (vha->ql2xexchoffld > max_cnt) { 4592 vha->ql2xexchoffld = max_cnt; 4593 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4594 } 4595 4596 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4597 *ret_cnt = vha->ql2xexchoffld; 4598 } else if (qla_dual_mode_enabled(vha)) { 4599 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4600 if (temp > max_cnt) { 4601 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4602 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4603 temp = max_cnt; 4604 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4605 } 4606 4607 if (temp > FW_DEF_EXCHANGES_CNT) 4608 *ret_cnt = temp; 4609 } 4610 } 4611 4612 int 4613 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4614 { 4615 int rval; 4616 u16 size, max_cnt; 4617 u32 actual_cnt, totsz; 4618 struct qla_hw_data *ha = vha->hw; 4619 4620 if (!ha->flags.exchoffld_enabled) 4621 return QLA_SUCCESS; 4622 4623 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4624 return QLA_SUCCESS; 4625 4626 max_cnt = 0; 4627 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4628 if (rval != QLA_SUCCESS) { 4629 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4630 "Failed to get exlogin status.\n"); 4631 return rval; 4632 } 4633 4634 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4635 ql_log(ql_log_info, vha, 0xd014, 4636 "Actual exchange offload count: %d.\n", actual_cnt); 4637 4638 totsz = actual_cnt * size; 4639 4640 if (totsz != ha->exchoffld_size) { 4641 qla2x00_free_exchoffld_buffer(ha); 4642 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4643 ha->exchoffld_size = 0; 4644 ha->flags.exchoffld_enabled = 0; 4645 return QLA_SUCCESS; 4646 } 4647 4648 ha->exchoffld_size = totsz; 4649 4650 ql_log(ql_log_info, vha, 0xd016, 4651 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4652 max_cnt, actual_cnt, size, totsz); 4653 4654 ql_log(ql_log_info, vha, 0xd017, 4655 "Exchange Buffers requested size = 0x%x\n", 4656 ha->exchoffld_size); 4657 4658 /* Get consistent memory for extended logins */ 4659 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4660 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4661 if (!ha->exchoffld_buf) { 4662 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4663 "Failed to allocate memory for Exchange Offload.\n"); 4664 4665 if (ha->max_exchg > 4666 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4667 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4668 } else if (ha->max_exchg > 4669 (FW_DEF_EXCHANGES_CNT + 512)) { 4670 ha->max_exchg -= 512; 4671 } else { 4672 ha->flags.exchoffld_enabled = 0; 4673 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4674 "Disabling Exchange offload due to lack of memory\n"); 4675 } 4676 ha->exchoffld_size = 0; 4677 4678 return -ENOMEM; 4679 } 4680 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4681 /* pathological case */ 4682 qla2x00_free_exchoffld_buffer(ha); 4683 ha->exchoffld_size = 0; 4684 ha->flags.exchoffld_enabled = 0; 4685 ql_log(ql_log_info, vha, 0xd016, 4686 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4687 ha->exchoffld_size, actual_cnt, size, totsz); 4688 return 0; 4689 } 4690 4691 /* Now configure the dma buffer */ 4692 rval = qla_set_exchoffld_mem_cfg(vha); 4693 if (rval) { 4694 ql_log(ql_log_fatal, vha, 0xd02e, 4695 "Setup exchange offload buffer ****FAILED****.\n"); 4696 qla2x00_free_exchoffld_buffer(ha); 4697 } else { 4698 /* re-adjust number of target exchange */ 4699 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4700 4701 if (qla_ini_mode_enabled(vha)) 4702 icb->exchange_count = 0; 4703 else 4704 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4705 } 4706 4707 return rval; 4708 } 4709 4710 /* 4711 * qla2x00_free_exchoffld_buffer 4712 * 4713 * Input: 4714 * ha = adapter block pointer 4715 */ 4716 void 4717 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4718 { 4719 if (ha->exchoffld_buf) { 4720 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4721 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4722 ha->exchoffld_buf = NULL; 4723 ha->exchoffld_size = 0; 4724 } 4725 } 4726 4727 /* 4728 * qla2x00_free_fw_dump 4729 * Frees fw dump stuff. 4730 * 4731 * Input: 4732 * ha = adapter block pointer 4733 */ 4734 static void 4735 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4736 { 4737 struct fwdt *fwdt = ha->fwdt; 4738 uint j; 4739 4740 if (ha->fce) 4741 dma_free_coherent(&ha->pdev->dev, 4742 FCE_SIZE, ha->fce, ha->fce_dma); 4743 4744 if (ha->eft) 4745 dma_free_coherent(&ha->pdev->dev, 4746 EFT_SIZE, ha->eft, ha->eft_dma); 4747 4748 vfree(ha->fw_dump); 4749 4750 ha->fce = NULL; 4751 ha->fce_dma = 0; 4752 ha->flags.fce_enabled = 0; 4753 ha->eft = NULL; 4754 ha->eft_dma = 0; 4755 ha->fw_dumped = false; 4756 ha->fw_dump_cap_flags = 0; 4757 ha->fw_dump_reading = 0; 4758 ha->fw_dump = NULL; 4759 ha->fw_dump_len = 0; 4760 4761 for (j = 0; j < 2; j++, fwdt++) { 4762 vfree(fwdt->template); 4763 fwdt->template = NULL; 4764 fwdt->length = 0; 4765 } 4766 } 4767 4768 /* 4769 * qla2x00_mem_free 4770 * Frees all adapter allocated memory. 4771 * 4772 * Input: 4773 * ha = adapter block pointer. 4774 */ 4775 static void 4776 qla2x00_mem_free(struct qla_hw_data *ha) 4777 { 4778 qla2x00_free_fw_dump(ha); 4779 4780 if (ha->mctp_dump) 4781 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4782 ha->mctp_dump_dma); 4783 ha->mctp_dump = NULL; 4784 4785 mempool_destroy(ha->srb_mempool); 4786 ha->srb_mempool = NULL; 4787 4788 if (ha->dcbx_tlv) 4789 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4790 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4791 ha->dcbx_tlv = NULL; 4792 4793 if (ha->xgmac_data) 4794 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4795 ha->xgmac_data, ha->xgmac_data_dma); 4796 ha->xgmac_data = NULL; 4797 4798 if (ha->sns_cmd) 4799 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4800 ha->sns_cmd, ha->sns_cmd_dma); 4801 ha->sns_cmd = NULL; 4802 ha->sns_cmd_dma = 0; 4803 4804 if (ha->ct_sns) 4805 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4806 ha->ct_sns, ha->ct_sns_dma); 4807 ha->ct_sns = NULL; 4808 ha->ct_sns_dma = 0; 4809 4810 if (ha->sfp_data) 4811 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4812 ha->sfp_data_dma); 4813 ha->sfp_data = NULL; 4814 4815 if (ha->flt) 4816 dma_free_coherent(&ha->pdev->dev, 4817 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4818 ha->flt, ha->flt_dma); 4819 ha->flt = NULL; 4820 ha->flt_dma = 0; 4821 4822 if (ha->ms_iocb) 4823 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4824 ha->ms_iocb = NULL; 4825 ha->ms_iocb_dma = 0; 4826 4827 if (ha->sf_init_cb) 4828 dma_pool_free(ha->s_dma_pool, 4829 ha->sf_init_cb, ha->sf_init_cb_dma); 4830 4831 if (ha->ex_init_cb) 4832 dma_pool_free(ha->s_dma_pool, 4833 ha->ex_init_cb, ha->ex_init_cb_dma); 4834 ha->ex_init_cb = NULL; 4835 ha->ex_init_cb_dma = 0; 4836 4837 if (ha->async_pd) 4838 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4839 ha->async_pd = NULL; 4840 ha->async_pd_dma = 0; 4841 4842 dma_pool_destroy(ha->s_dma_pool); 4843 ha->s_dma_pool = NULL; 4844 4845 if (ha->gid_list) 4846 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4847 ha->gid_list, ha->gid_list_dma); 4848 ha->gid_list = NULL; 4849 ha->gid_list_dma = 0; 4850 4851 if (IS_QLA82XX(ha)) { 4852 if (!list_empty(&ha->gbl_dsd_list)) { 4853 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4854 4855 /* clean up allocated prev pool */ 4856 list_for_each_entry_safe(dsd_ptr, 4857 tdsd_ptr, &ha->gbl_dsd_list, list) { 4858 dma_pool_free(ha->dl_dma_pool, 4859 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4860 list_del(&dsd_ptr->list); 4861 kfree(dsd_ptr); 4862 } 4863 } 4864 } 4865 4866 dma_pool_destroy(ha->dl_dma_pool); 4867 ha->dl_dma_pool = NULL; 4868 4869 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4870 ha->fcp_cmnd_dma_pool = NULL; 4871 4872 mempool_destroy(ha->ctx_mempool); 4873 ha->ctx_mempool = NULL; 4874 4875 if (ql2xenabledif && ha->dif_bundl_pool) { 4876 struct dsd_dma *dsd, *nxt; 4877 4878 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4879 list) { 4880 list_del(&dsd->list); 4881 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4882 dsd->dsd_list_dma); 4883 ha->dif_bundle_dma_allocs--; 4884 kfree(dsd); 4885 ha->dif_bundle_kallocs--; 4886 ha->pool.unusable.count--; 4887 } 4888 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4889 list_del(&dsd->list); 4890 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4891 dsd->dsd_list_dma); 4892 ha->dif_bundle_dma_allocs--; 4893 kfree(dsd); 4894 ha->dif_bundle_kallocs--; 4895 } 4896 } 4897 4898 dma_pool_destroy(ha->dif_bundl_pool); 4899 ha->dif_bundl_pool = NULL; 4900 4901 qlt_mem_free(ha); 4902 qla_remove_hostmap(ha); 4903 4904 if (ha->init_cb) 4905 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4906 ha->init_cb, ha->init_cb_dma); 4907 4908 dma_pool_destroy(ha->purex_dma_pool); 4909 ha->purex_dma_pool = NULL; 4910 4911 if (ha->elsrej.c) { 4912 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4913 ha->elsrej.c, ha->elsrej.cdma); 4914 ha->elsrej.c = NULL; 4915 } 4916 4917 ha->init_cb = NULL; 4918 ha->init_cb_dma = 0; 4919 4920 vfree(ha->optrom_buffer); 4921 ha->optrom_buffer = NULL; 4922 kfree(ha->nvram); 4923 ha->nvram = NULL; 4924 kfree(ha->npiv_info); 4925 ha->npiv_info = NULL; 4926 kfree(ha->swl); 4927 ha->swl = NULL; 4928 kfree(ha->loop_id_map); 4929 ha->sf_init_cb = NULL; 4930 ha->sf_init_cb_dma = 0; 4931 ha->loop_id_map = NULL; 4932 } 4933 4934 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4935 struct qla_hw_data *ha) 4936 { 4937 struct Scsi_Host *host; 4938 struct scsi_qla_host *vha = NULL; 4939 4940 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4941 if (!host) { 4942 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4943 "Failed to allocate host from the scsi layer, aborting.\n"); 4944 return NULL; 4945 } 4946 4947 /* Clear our data area */ 4948 vha = shost_priv(host); 4949 memset(vha, 0, sizeof(scsi_qla_host_t)); 4950 4951 vha->host = host; 4952 vha->host_no = host->host_no; 4953 vha->hw = ha; 4954 4955 vha->qlini_mode = ql2x_ini_mode; 4956 vha->ql2xexchoffld = ql2xexchoffld; 4957 vha->ql2xiniexchg = ql2xiniexchg; 4958 4959 INIT_LIST_HEAD(&vha->vp_fcports); 4960 INIT_LIST_HEAD(&vha->work_list); 4961 INIT_LIST_HEAD(&vha->list); 4962 INIT_LIST_HEAD(&vha->qla_cmd_list); 4963 INIT_LIST_HEAD(&vha->logo_list); 4964 INIT_LIST_HEAD(&vha->plogi_ack_list); 4965 INIT_LIST_HEAD(&vha->qp_list); 4966 INIT_LIST_HEAD(&vha->gnl.fcports); 4967 INIT_LIST_HEAD(&vha->gpnid_list); 4968 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4969 4970 INIT_LIST_HEAD(&vha->purex_list.head); 4971 spin_lock_init(&vha->purex_list.lock); 4972 4973 spin_lock_init(&vha->work_lock); 4974 spin_lock_init(&vha->cmd_list_lock); 4975 init_waitqueue_head(&vha->fcport_waitQ); 4976 init_waitqueue_head(&vha->vref_waitq); 4977 qla_enode_init(vha); 4978 qla_edb_init(vha); 4979 4980 4981 vha->gnl.size = sizeof(struct get_name_list_extended) * 4982 (ha->max_loop_id + 1); 4983 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4984 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4985 if (!vha->gnl.l) { 4986 ql_log(ql_log_fatal, vha, 0xd04a, 4987 "Alloc failed for name list.\n"); 4988 scsi_host_put(vha->host); 4989 return NULL; 4990 } 4991 4992 /* todo: what about ext login? */ 4993 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4994 vha->scan.l = vmalloc(vha->scan.size); 4995 if (!vha->scan.l) { 4996 ql_log(ql_log_fatal, vha, 0xd04a, 4997 "Alloc failed for scan database.\n"); 4998 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4999 vha->gnl.l, vha->gnl.ldma); 5000 vha->gnl.l = NULL; 5001 scsi_host_put(vha->host); 5002 return NULL; 5003 } 5004 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5005 5006 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5007 ql_dbg(ql_dbg_init, vha, 0x0041, 5008 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5009 vha->host, vha->hw, vha, 5010 dev_name(&(ha->pdev->dev))); 5011 5012 return vha; 5013 } 5014 5015 struct qla_work_evt * 5016 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5017 { 5018 struct qla_work_evt *e; 5019 uint8_t bail; 5020 5021 if (test_bit(UNLOADING, &vha->dpc_flags)) 5022 return NULL; 5023 5024 QLA_VHA_MARK_BUSY(vha, bail); 5025 if (bail) 5026 return NULL; 5027 5028 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5029 if (!e) { 5030 QLA_VHA_MARK_NOT_BUSY(vha); 5031 return NULL; 5032 } 5033 5034 INIT_LIST_HEAD(&e->list); 5035 e->type = type; 5036 e->flags = QLA_EVT_FLAG_FREE; 5037 return e; 5038 } 5039 5040 int 5041 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5042 { 5043 unsigned long flags; 5044 bool q = false; 5045 5046 spin_lock_irqsave(&vha->work_lock, flags); 5047 list_add_tail(&e->list, &vha->work_list); 5048 5049 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5050 q = true; 5051 5052 spin_unlock_irqrestore(&vha->work_lock, flags); 5053 5054 if (q) 5055 queue_work(vha->hw->wq, &vha->iocb_work); 5056 5057 return QLA_SUCCESS; 5058 } 5059 5060 int 5061 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5062 u32 data) 5063 { 5064 struct qla_work_evt *e; 5065 5066 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5067 if (!e) 5068 return QLA_FUNCTION_FAILED; 5069 5070 e->u.aen.code = code; 5071 e->u.aen.data = data; 5072 return qla2x00_post_work(vha, e); 5073 } 5074 5075 int 5076 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5077 { 5078 struct qla_work_evt *e; 5079 5080 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5081 if (!e) 5082 return QLA_FUNCTION_FAILED; 5083 5084 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5085 return qla2x00_post_work(vha, e); 5086 } 5087 5088 #define qla2x00_post_async_work(name, type) \ 5089 int qla2x00_post_async_##name##_work( \ 5090 struct scsi_qla_host *vha, \ 5091 fc_port_t *fcport, uint16_t *data) \ 5092 { \ 5093 struct qla_work_evt *e; \ 5094 \ 5095 e = qla2x00_alloc_work(vha, type); \ 5096 if (!e) \ 5097 return QLA_FUNCTION_FAILED; \ 5098 \ 5099 e->u.logio.fcport = fcport; \ 5100 if (data) { \ 5101 e->u.logio.data[0] = data[0]; \ 5102 e->u.logio.data[1] = data[1]; \ 5103 } \ 5104 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5105 return qla2x00_post_work(vha, e); \ 5106 } 5107 5108 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5109 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5110 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5111 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5112 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5113 5114 int 5115 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5116 { 5117 struct qla_work_evt *e; 5118 5119 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5120 if (!e) 5121 return QLA_FUNCTION_FAILED; 5122 5123 e->u.uevent.code = code; 5124 return qla2x00_post_work(vha, e); 5125 } 5126 5127 static void 5128 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5129 { 5130 char event_string[40]; 5131 char *envp[] = { event_string, NULL }; 5132 5133 switch (code) { 5134 case QLA_UEVENT_CODE_FW_DUMP: 5135 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5136 vha->host_no); 5137 break; 5138 default: 5139 /* do nothing */ 5140 break; 5141 } 5142 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5143 } 5144 5145 int 5146 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5147 uint32_t *data, int cnt) 5148 { 5149 struct qla_work_evt *e; 5150 5151 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5152 if (!e) 5153 return QLA_FUNCTION_FAILED; 5154 5155 e->u.aenfx.evtcode = evtcode; 5156 e->u.aenfx.count = cnt; 5157 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5158 return qla2x00_post_work(vha, e); 5159 } 5160 5161 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5162 { 5163 unsigned long flags; 5164 5165 if (IS_SW_RESV_ADDR(fcport->d_id)) 5166 return; 5167 5168 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5169 if (fcport->disc_state == DSC_UPD_FCPORT) { 5170 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5171 return; 5172 } 5173 fcport->jiffies_at_registration = jiffies; 5174 fcport->sec_since_registration = 0; 5175 fcport->next_disc_state = DSC_DELETED; 5176 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5177 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5178 5179 queue_work(system_unbound_wq, &fcport->reg_work); 5180 } 5181 5182 static 5183 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5184 { 5185 unsigned long flags; 5186 fc_port_t *fcport = NULL, *tfcp; 5187 struct qlt_plogi_ack_t *pla = 5188 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5189 uint8_t free_fcport = 0; 5190 5191 ql_dbg(ql_dbg_disc, vha, 0xffff, 5192 "%s %d %8phC enter\n", 5193 __func__, __LINE__, e->u.new_sess.port_name); 5194 5195 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5196 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5197 if (fcport) { 5198 fcport->d_id = e->u.new_sess.id; 5199 if (pla) { 5200 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5201 memcpy(fcport->node_name, 5202 pla->iocb.u.isp24.u.plogi.node_name, 5203 WWN_SIZE); 5204 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5205 /* we took an extra ref_count to prevent PLOGI ACK when 5206 * fcport/sess has not been created. 5207 */ 5208 pla->ref_count--; 5209 } 5210 } else { 5211 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5212 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5213 if (fcport) { 5214 fcport->d_id = e->u.new_sess.id; 5215 fcport->flags |= FCF_FABRIC_DEVICE; 5216 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5217 fcport->tgt_short_link_down_cnt = 0; 5218 5219 memcpy(fcport->port_name, e->u.new_sess.port_name, 5220 WWN_SIZE); 5221 5222 fcport->fc4_type = e->u.new_sess.fc4_type; 5223 if (NVME_PRIORITY(vha->hw, fcport)) 5224 fcport->do_prli_nvme = 1; 5225 else 5226 fcport->do_prli_nvme = 0; 5227 5228 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5229 fcport->dm_login_expire = jiffies + 5230 QLA_N2N_WAIT_TIME * HZ; 5231 fcport->fc4_type = FS_FC4TYPE_FCP; 5232 fcport->n2n_flag = 1; 5233 if (vha->flags.nvme_enabled) 5234 fcport->fc4_type |= FS_FC4TYPE_NVME; 5235 } 5236 5237 } else { 5238 ql_dbg(ql_dbg_disc, vha, 0xffff, 5239 "%s %8phC mem alloc fail.\n", 5240 __func__, e->u.new_sess.port_name); 5241 5242 if (pla) { 5243 list_del(&pla->list); 5244 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5245 } 5246 return; 5247 } 5248 5249 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5250 /* search again to make sure no one else got ahead */ 5251 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5252 e->u.new_sess.port_name, 1); 5253 if (tfcp) { 5254 /* should rarily happen */ 5255 ql_dbg(ql_dbg_disc, vha, 0xffff, 5256 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5257 __func__, tfcp->port_name, tfcp->disc_state, 5258 tfcp->fw_login_state); 5259 5260 free_fcport = 1; 5261 } else { 5262 list_add_tail(&fcport->list, &vha->vp_fcports); 5263 5264 } 5265 if (pla) { 5266 qlt_plogi_ack_link(vha, pla, fcport, 5267 QLT_PLOGI_LINK_SAME_WWN); 5268 pla->ref_count--; 5269 } 5270 } 5271 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5272 5273 if (fcport) { 5274 fcport->id_changed = 1; 5275 fcport->scan_state = QLA_FCPORT_FOUND; 5276 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5277 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5278 5279 if (pla) { 5280 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5281 u16 wd3_lo; 5282 5283 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5284 fcport->local = 0; 5285 fcport->loop_id = 5286 le16_to_cpu( 5287 pla->iocb.u.isp24.nport_handle); 5288 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5289 wd3_lo = 5290 le16_to_cpu( 5291 pla->iocb.u.isp24.u.prli.wd3_lo); 5292 5293 if (wd3_lo & BIT_7) 5294 fcport->conf_compl_supported = 1; 5295 5296 if ((wd3_lo & BIT_4) == 0) 5297 fcport->port_type = FCT_INITIATOR; 5298 else 5299 fcport->port_type = FCT_TARGET; 5300 } 5301 qlt_plogi_ack_unref(vha, pla); 5302 } else { 5303 fc_port_t *dfcp = NULL; 5304 5305 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5306 tfcp = qla2x00_find_fcport_by_nportid(vha, 5307 &e->u.new_sess.id, 1); 5308 if (tfcp && (tfcp != fcport)) { 5309 /* 5310 * We have a conflict fcport with same NportID. 5311 */ 5312 ql_dbg(ql_dbg_disc, vha, 0xffff, 5313 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5314 __func__, tfcp->port_name, tfcp->disc_state, 5315 tfcp->fw_login_state); 5316 5317 switch (tfcp->disc_state) { 5318 case DSC_DELETED: 5319 break; 5320 case DSC_DELETE_PEND: 5321 fcport->login_pause = 1; 5322 tfcp->conflict = fcport; 5323 break; 5324 default: 5325 fcport->login_pause = 1; 5326 tfcp->conflict = fcport; 5327 dfcp = tfcp; 5328 break; 5329 } 5330 } 5331 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5332 if (dfcp) 5333 qlt_schedule_sess_for_deletion(tfcp); 5334 5335 if (N2N_TOPO(vha->hw)) { 5336 fcport->flags &= ~FCF_FABRIC_DEVICE; 5337 fcport->keep_nport_handle = 1; 5338 if (vha->flags.nvme_enabled) { 5339 fcport->fc4_type = 5340 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5341 fcport->n2n_flag = 1; 5342 } 5343 fcport->fw_login_state = 0; 5344 5345 schedule_delayed_work(&vha->scan.scan_work, 5); 5346 } else { 5347 qla24xx_fcport_handle_login(vha, fcport); 5348 } 5349 } 5350 } 5351 5352 if (free_fcport) { 5353 qla2x00_free_fcport(fcport); 5354 if (pla) { 5355 list_del(&pla->list); 5356 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5357 } 5358 } 5359 } 5360 5361 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5362 { 5363 struct srb *sp = e->u.iosb.sp; 5364 int rval; 5365 5366 rval = qla2x00_start_sp(sp); 5367 if (rval != QLA_SUCCESS) { 5368 ql_dbg(ql_dbg_disc, vha, 0x2043, 5369 "%s: %s: Re-issue IOCB failed (%d).\n", 5370 __func__, sp->name, rval); 5371 qla24xx_sp_unmap(vha, sp); 5372 } 5373 } 5374 5375 void 5376 qla2x00_do_work(struct scsi_qla_host *vha) 5377 { 5378 struct qla_work_evt *e, *tmp; 5379 unsigned long flags; 5380 LIST_HEAD(work); 5381 int rc; 5382 5383 spin_lock_irqsave(&vha->work_lock, flags); 5384 list_splice_init(&vha->work_list, &work); 5385 spin_unlock_irqrestore(&vha->work_lock, flags); 5386 5387 list_for_each_entry_safe(e, tmp, &work, list) { 5388 rc = QLA_SUCCESS; 5389 switch (e->type) { 5390 case QLA_EVT_AEN: 5391 fc_host_post_event(vha->host, fc_get_event_number(), 5392 e->u.aen.code, e->u.aen.data); 5393 break; 5394 case QLA_EVT_IDC_ACK: 5395 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5396 break; 5397 case QLA_EVT_ASYNC_LOGIN: 5398 qla2x00_async_login(vha, e->u.logio.fcport, 5399 e->u.logio.data); 5400 break; 5401 case QLA_EVT_ASYNC_LOGOUT: 5402 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5403 break; 5404 case QLA_EVT_ASYNC_ADISC: 5405 qla2x00_async_adisc(vha, e->u.logio.fcport, 5406 e->u.logio.data); 5407 break; 5408 case QLA_EVT_UEVENT: 5409 qla2x00_uevent_emit(vha, e->u.uevent.code); 5410 break; 5411 case QLA_EVT_AENFX: 5412 qlafx00_process_aen(vha, e); 5413 break; 5414 case QLA_EVT_GPNID: 5415 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5416 break; 5417 case QLA_EVT_UNMAP: 5418 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5419 break; 5420 case QLA_EVT_RELOGIN: 5421 qla2x00_relogin(vha); 5422 break; 5423 case QLA_EVT_NEW_SESS: 5424 qla24xx_create_new_sess(vha, e); 5425 break; 5426 case QLA_EVT_GPDB: 5427 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5428 e->u.fcport.opt); 5429 break; 5430 case QLA_EVT_PRLI: 5431 qla24xx_async_prli(vha, e->u.fcport.fcport); 5432 break; 5433 case QLA_EVT_GPSC: 5434 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5435 break; 5436 case QLA_EVT_GNL: 5437 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5438 break; 5439 case QLA_EVT_NACK: 5440 qla24xx_do_nack_work(vha, e); 5441 break; 5442 case QLA_EVT_ASYNC_PRLO: 5443 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5444 break; 5445 case QLA_EVT_ASYNC_PRLO_DONE: 5446 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5447 e->u.logio.data); 5448 break; 5449 case QLA_EVT_GPNFT: 5450 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5451 e->u.gpnft.sp); 5452 break; 5453 case QLA_EVT_GPNFT_DONE: 5454 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5455 break; 5456 case QLA_EVT_GNNFT_DONE: 5457 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5458 break; 5459 case QLA_EVT_GNNID: 5460 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5461 break; 5462 case QLA_EVT_GFPNID: 5463 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5464 break; 5465 case QLA_EVT_SP_RETRY: 5466 qla_sp_retry(vha, e); 5467 break; 5468 case QLA_EVT_IIDMA: 5469 qla_do_iidma_work(vha, e->u.fcport.fcport); 5470 break; 5471 case QLA_EVT_ELS_PLOGI: 5472 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5473 e->u.fcport.fcport, false); 5474 break; 5475 case QLA_EVT_SA_REPLACE: 5476 qla24xx_issue_sa_replace_iocb(vha, e); 5477 break; 5478 } 5479 5480 if (rc == EAGAIN) { 5481 /* put 'work' at head of 'vha->work_list' */ 5482 spin_lock_irqsave(&vha->work_lock, flags); 5483 list_splice(&work, &vha->work_list); 5484 spin_unlock_irqrestore(&vha->work_lock, flags); 5485 break; 5486 } 5487 list_del_init(&e->list); 5488 if (e->flags & QLA_EVT_FLAG_FREE) 5489 kfree(e); 5490 5491 /* For each work completed decrement vha ref count */ 5492 QLA_VHA_MARK_NOT_BUSY(vha); 5493 } 5494 } 5495 5496 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5497 { 5498 struct qla_work_evt *e; 5499 5500 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5501 5502 if (!e) { 5503 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5504 return QLA_FUNCTION_FAILED; 5505 } 5506 5507 return qla2x00_post_work(vha, e); 5508 } 5509 5510 /* Relogins all the fcports of a vport 5511 * Context: dpc thread 5512 */ 5513 void qla2x00_relogin(struct scsi_qla_host *vha) 5514 { 5515 fc_port_t *fcport; 5516 int status, relogin_needed = 0; 5517 struct event_arg ea; 5518 5519 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5520 /* 5521 * If the port is not ONLINE then try to login 5522 * to it if we haven't run out of retries. 5523 */ 5524 if (atomic_read(&fcport->state) != FCS_ONLINE && 5525 fcport->login_retry) { 5526 if (fcport->scan_state != QLA_FCPORT_FOUND || 5527 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5528 fcport->disc_state == DSC_LOGIN_COMPLETE) 5529 continue; 5530 5531 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5532 fcport->disc_state == DSC_DELETE_PEND) { 5533 relogin_needed = 1; 5534 } else { 5535 if (vha->hw->current_topology != ISP_CFG_NL) { 5536 memset(&ea, 0, sizeof(ea)); 5537 ea.fcport = fcport; 5538 qla24xx_handle_relogin_event(vha, &ea); 5539 } else if (vha->hw->current_topology == 5540 ISP_CFG_NL && 5541 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5542 (void)qla24xx_fcport_handle_login(vha, 5543 fcport); 5544 } else if (vha->hw->current_topology == 5545 ISP_CFG_NL) { 5546 fcport->login_retry--; 5547 status = 5548 qla2x00_local_device_login(vha, 5549 fcport); 5550 if (status == QLA_SUCCESS) { 5551 fcport->old_loop_id = 5552 fcport->loop_id; 5553 ql_dbg(ql_dbg_disc, vha, 0x2003, 5554 "Port login OK: logged in ID 0x%x.\n", 5555 fcport->loop_id); 5556 qla2x00_update_fcport 5557 (vha, fcport); 5558 } else if (status == 1) { 5559 set_bit(RELOGIN_NEEDED, 5560 &vha->dpc_flags); 5561 /* retry the login again */ 5562 ql_dbg(ql_dbg_disc, vha, 0x2007, 5563 "Retrying %d login again loop_id 0x%x.\n", 5564 fcport->login_retry, 5565 fcport->loop_id); 5566 } else { 5567 fcport->login_retry = 0; 5568 } 5569 5570 if (fcport->login_retry == 0 && 5571 status != QLA_SUCCESS) 5572 qla2x00_clear_loop_id(fcport); 5573 } 5574 } 5575 } 5576 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5577 break; 5578 } 5579 5580 if (relogin_needed) 5581 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5582 5583 ql_dbg(ql_dbg_disc, vha, 0x400e, 5584 "Relogin end.\n"); 5585 } 5586 5587 /* Schedule work on any of the dpc-workqueues */ 5588 void 5589 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5590 { 5591 struct qla_hw_data *ha = base_vha->hw; 5592 5593 switch (work_code) { 5594 case MBA_IDC_AEN: /* 0x8200 */ 5595 if (ha->dpc_lp_wq) 5596 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5597 break; 5598 5599 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5600 if (!ha->flags.nic_core_reset_hdlr_active) { 5601 if (ha->dpc_hp_wq) 5602 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5603 } else 5604 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5605 "NIC Core reset is already active. Skip " 5606 "scheduling it again.\n"); 5607 break; 5608 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5609 if (ha->dpc_hp_wq) 5610 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5611 break; 5612 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5613 if (ha->dpc_hp_wq) 5614 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5615 break; 5616 default: 5617 ql_log(ql_log_warn, base_vha, 0xb05f, 5618 "Unknown work-code=0x%x.\n", work_code); 5619 } 5620 5621 return; 5622 } 5623 5624 /* Work: Perform NIC Core Unrecoverable state handling */ 5625 void 5626 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5627 { 5628 struct qla_hw_data *ha = 5629 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5630 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5631 uint32_t dev_state = 0; 5632 5633 qla83xx_idc_lock(base_vha, 0); 5634 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5635 qla83xx_reset_ownership(base_vha); 5636 if (ha->flags.nic_core_reset_owner) { 5637 ha->flags.nic_core_reset_owner = 0; 5638 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5639 QLA8XXX_DEV_FAILED); 5640 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5641 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5642 } 5643 qla83xx_idc_unlock(base_vha, 0); 5644 } 5645 5646 /* Work: Execute IDC state handler */ 5647 void 5648 qla83xx_idc_state_handler_work(struct work_struct *work) 5649 { 5650 struct qla_hw_data *ha = 5651 container_of(work, struct qla_hw_data, idc_state_handler); 5652 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5653 uint32_t dev_state = 0; 5654 5655 qla83xx_idc_lock(base_vha, 0); 5656 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5657 if (dev_state == QLA8XXX_DEV_FAILED || 5658 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5659 qla83xx_idc_state_handler(base_vha); 5660 qla83xx_idc_unlock(base_vha, 0); 5661 } 5662 5663 static int 5664 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5665 { 5666 int rval = QLA_SUCCESS; 5667 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5668 uint32_t heart_beat_counter1, heart_beat_counter2; 5669 5670 do { 5671 if (time_after(jiffies, heart_beat_wait)) { 5672 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5673 "Nic Core f/w is not alive.\n"); 5674 rval = QLA_FUNCTION_FAILED; 5675 break; 5676 } 5677 5678 qla83xx_idc_lock(base_vha, 0); 5679 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5680 &heart_beat_counter1); 5681 qla83xx_idc_unlock(base_vha, 0); 5682 msleep(100); 5683 qla83xx_idc_lock(base_vha, 0); 5684 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5685 &heart_beat_counter2); 5686 qla83xx_idc_unlock(base_vha, 0); 5687 } while (heart_beat_counter1 == heart_beat_counter2); 5688 5689 return rval; 5690 } 5691 5692 /* Work: Perform NIC Core Reset handling */ 5693 void 5694 qla83xx_nic_core_reset_work(struct work_struct *work) 5695 { 5696 struct qla_hw_data *ha = 5697 container_of(work, struct qla_hw_data, nic_core_reset); 5698 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5699 uint32_t dev_state = 0; 5700 5701 if (IS_QLA2031(ha)) { 5702 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5703 ql_log(ql_log_warn, base_vha, 0xb081, 5704 "Failed to dump mctp\n"); 5705 return; 5706 } 5707 5708 if (!ha->flags.nic_core_reset_hdlr_active) { 5709 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5710 qla83xx_idc_lock(base_vha, 0); 5711 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5712 &dev_state); 5713 qla83xx_idc_unlock(base_vha, 0); 5714 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5715 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5716 "Nic Core f/w is alive.\n"); 5717 return; 5718 } 5719 } 5720 5721 ha->flags.nic_core_reset_hdlr_active = 1; 5722 if (qla83xx_nic_core_reset(base_vha)) { 5723 /* NIC Core reset failed. */ 5724 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5725 "NIC Core reset failed.\n"); 5726 } 5727 ha->flags.nic_core_reset_hdlr_active = 0; 5728 } 5729 } 5730 5731 /* Work: Handle 8200 IDC aens */ 5732 void 5733 qla83xx_service_idc_aen(struct work_struct *work) 5734 { 5735 struct qla_hw_data *ha = 5736 container_of(work, struct qla_hw_data, idc_aen); 5737 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5738 uint32_t dev_state, idc_control; 5739 5740 qla83xx_idc_lock(base_vha, 0); 5741 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5742 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5743 qla83xx_idc_unlock(base_vha, 0); 5744 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5745 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5746 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5747 "Application requested NIC Core Reset.\n"); 5748 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5749 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5750 QLA_SUCCESS) { 5751 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5752 "Other protocol driver requested NIC Core Reset.\n"); 5753 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5754 } 5755 } else if (dev_state == QLA8XXX_DEV_FAILED || 5756 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5757 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5758 } 5759 } 5760 5761 /* 5762 * Control the frequency of IDC lock retries 5763 */ 5764 #define QLA83XX_WAIT_LOGIC_MS 100 5765 5766 static int 5767 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5768 { 5769 int rval; 5770 uint32_t data; 5771 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5772 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5773 struct qla_hw_data *ha = base_vha->hw; 5774 5775 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5776 "Trying force recovery of the IDC lock.\n"); 5777 5778 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5779 if (rval) 5780 return rval; 5781 5782 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5783 return QLA_SUCCESS; 5784 } else { 5785 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5786 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5787 data); 5788 if (rval) 5789 return rval; 5790 5791 msleep(200); 5792 5793 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5794 &data); 5795 if (rval) 5796 return rval; 5797 5798 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5799 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5800 ~(idc_lck_rcvry_stage_mask)); 5801 rval = qla83xx_wr_reg(base_vha, 5802 QLA83XX_IDC_LOCK_RECOVERY, data); 5803 if (rval) 5804 return rval; 5805 5806 /* Forcefully perform IDC UnLock */ 5807 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5808 &data); 5809 if (rval) 5810 return rval; 5811 /* Clear lock-id by setting 0xff */ 5812 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5813 0xff); 5814 if (rval) 5815 return rval; 5816 /* Clear lock-recovery by setting 0x0 */ 5817 rval = qla83xx_wr_reg(base_vha, 5818 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5819 if (rval) 5820 return rval; 5821 } else 5822 return QLA_SUCCESS; 5823 } 5824 5825 return rval; 5826 } 5827 5828 static int 5829 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5830 { 5831 int rval = QLA_SUCCESS; 5832 uint32_t o_drv_lockid, n_drv_lockid; 5833 unsigned long lock_recovery_timeout; 5834 5835 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5836 retry_lockid: 5837 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5838 if (rval) 5839 goto exit; 5840 5841 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5842 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5843 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5844 return QLA_SUCCESS; 5845 else 5846 return QLA_FUNCTION_FAILED; 5847 } 5848 5849 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5850 if (rval) 5851 goto exit; 5852 5853 if (o_drv_lockid == n_drv_lockid) { 5854 msleep(QLA83XX_WAIT_LOGIC_MS); 5855 goto retry_lockid; 5856 } else 5857 return QLA_SUCCESS; 5858 5859 exit: 5860 return rval; 5861 } 5862 5863 /* 5864 * Context: task, can sleep 5865 */ 5866 void 5867 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5868 { 5869 uint32_t data; 5870 uint32_t lock_owner; 5871 struct qla_hw_data *ha = base_vha->hw; 5872 5873 might_sleep(); 5874 5875 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5876 retry_lock: 5877 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5878 == QLA_SUCCESS) { 5879 if (data) { 5880 /* Setting lock-id to our function-number */ 5881 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5882 ha->portnum); 5883 } else { 5884 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5885 &lock_owner); 5886 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5887 "Failed to acquire IDC lock, acquired by %d, " 5888 "retrying...\n", lock_owner); 5889 5890 /* Retry/Perform IDC-Lock recovery */ 5891 if (qla83xx_idc_lock_recovery(base_vha) 5892 == QLA_SUCCESS) { 5893 msleep(QLA83XX_WAIT_LOGIC_MS); 5894 goto retry_lock; 5895 } else 5896 ql_log(ql_log_warn, base_vha, 0xb075, 5897 "IDC Lock recovery FAILED.\n"); 5898 } 5899 5900 } 5901 5902 return; 5903 } 5904 5905 static bool 5906 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5907 struct purex_entry_24xx *purex) 5908 { 5909 char fwstr[16]; 5910 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5911 struct port_database_24xx *pdb; 5912 5913 /* Domain Controller is always logged-out. */ 5914 /* if RDP request is not from Domain Controller: */ 5915 if (sid != 0xfffc01) 5916 return false; 5917 5918 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5919 5920 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5921 if (!pdb) { 5922 ql_dbg(ql_dbg_init, vha, 0x0181, 5923 "%s: Failed allocate pdb\n", __func__); 5924 } else if (qla24xx_get_port_database(vha, 5925 le16_to_cpu(purex->nport_handle), pdb)) { 5926 ql_dbg(ql_dbg_init, vha, 0x0181, 5927 "%s: Failed get pdb sid=%x\n", __func__, sid); 5928 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5929 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5930 ql_dbg(ql_dbg_init, vha, 0x0181, 5931 "%s: Port not logged in sid=%#x\n", __func__, sid); 5932 } else { 5933 /* RDP request is from logged in port */ 5934 kfree(pdb); 5935 return false; 5936 } 5937 kfree(pdb); 5938 5939 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5940 fwstr[strcspn(fwstr, " ")] = 0; 5941 /* if FW version allows RDP response length upto 2048 bytes: */ 5942 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5943 return false; 5944 5945 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5946 5947 /* RDP response length is to be reduced to maximum 256 bytes */ 5948 return true; 5949 } 5950 5951 /* 5952 * Function Name: qla24xx_process_purex_iocb 5953 * 5954 * Description: 5955 * Prepare a RDP response and send to Fabric switch 5956 * 5957 * PARAMETERS: 5958 * vha: SCSI qla host 5959 * purex: RDP request received by HBA 5960 */ 5961 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5962 struct purex_item *item) 5963 { 5964 struct qla_hw_data *ha = vha->hw; 5965 struct purex_entry_24xx *purex = 5966 (struct purex_entry_24xx *)&item->iocb; 5967 dma_addr_t rsp_els_dma; 5968 dma_addr_t rsp_payload_dma; 5969 dma_addr_t stat_dma; 5970 dma_addr_t sfp_dma; 5971 struct els_entry_24xx *rsp_els = NULL; 5972 struct rdp_rsp_payload *rsp_payload = NULL; 5973 struct link_statistics *stat = NULL; 5974 uint8_t *sfp = NULL; 5975 uint16_t sfp_flags = 0; 5976 uint rsp_payload_length = sizeof(*rsp_payload); 5977 int rval; 5978 5979 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5980 "%s: Enter\n", __func__); 5981 5982 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5983 "-------- ELS REQ -------\n"); 5984 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5985 purex, sizeof(*purex)); 5986 5987 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5988 rsp_payload_length = 5989 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5990 ql_dbg(ql_dbg_init, vha, 0x0181, 5991 "Reducing RSP payload length to %u bytes...\n", 5992 rsp_payload_length); 5993 } 5994 5995 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5996 &rsp_els_dma, GFP_KERNEL); 5997 if (!rsp_els) { 5998 ql_log(ql_log_warn, vha, 0x0183, 5999 "Failed allocate dma buffer ELS RSP.\n"); 6000 goto dealloc; 6001 } 6002 6003 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6004 &rsp_payload_dma, GFP_KERNEL); 6005 if (!rsp_payload) { 6006 ql_log(ql_log_warn, vha, 0x0184, 6007 "Failed allocate dma buffer ELS RSP payload.\n"); 6008 goto dealloc; 6009 } 6010 6011 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6012 &sfp_dma, GFP_KERNEL); 6013 6014 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6015 &stat_dma, GFP_KERNEL); 6016 6017 /* Prepare Response IOCB */ 6018 rsp_els->entry_type = ELS_IOCB_TYPE; 6019 rsp_els->entry_count = 1; 6020 rsp_els->sys_define = 0; 6021 rsp_els->entry_status = 0; 6022 rsp_els->handle = 0; 6023 rsp_els->nport_handle = purex->nport_handle; 6024 rsp_els->tx_dsd_count = cpu_to_le16(1); 6025 rsp_els->vp_index = purex->vp_idx; 6026 rsp_els->sof_type = EST_SOFI3; 6027 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6028 rsp_els->rx_dsd_count = 0; 6029 rsp_els->opcode = purex->els_frame_payload[0]; 6030 6031 rsp_els->d_id[0] = purex->s_id[0]; 6032 rsp_els->d_id[1] = purex->s_id[1]; 6033 rsp_els->d_id[2] = purex->s_id[2]; 6034 6035 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6036 rsp_els->rx_byte_count = 0; 6037 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6038 6039 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6040 rsp_els->tx_len = rsp_els->tx_byte_count; 6041 6042 rsp_els->rx_address = 0; 6043 rsp_els->rx_len = 0; 6044 6045 /* Prepare Response Payload */ 6046 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6047 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6048 sizeof(rsp_payload->hdr)); 6049 6050 /* Link service Request Info Descriptor */ 6051 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6052 rsp_payload->ls_req_info_desc.desc_len = 6053 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6054 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6055 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6056 6057 /* Link service Request Info Descriptor 2 */ 6058 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6059 rsp_payload->ls_req_info_desc2.desc_len = 6060 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6061 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6062 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6063 6064 6065 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6066 rsp_payload->sfp_diag_desc.desc_len = 6067 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6068 6069 if (sfp) { 6070 /* SFP Flags */ 6071 memset(sfp, 0, SFP_RTDI_LEN); 6072 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6073 if (!rval) { 6074 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6075 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6076 sfp_flags |= BIT_0; /* short wave */ 6077 else if (sfp[0] & BIT_1) 6078 sfp_flags |= BIT_1; /* long wave 1310nm */ 6079 else if (sfp[1] & BIT_4) 6080 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6081 } 6082 6083 /* SFP Type */ 6084 memset(sfp, 0, SFP_RTDI_LEN); 6085 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6086 if (!rval) { 6087 sfp_flags |= BIT_4; /* optical */ 6088 if (sfp[0] == 0x3) 6089 sfp_flags |= BIT_6; /* sfp+ */ 6090 } 6091 6092 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6093 6094 /* SFP Diagnostics */ 6095 memset(sfp, 0, SFP_RTDI_LEN); 6096 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6097 if (!rval) { 6098 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6099 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6100 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6101 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6102 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6103 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6104 } 6105 } 6106 6107 /* Port Speed Descriptor */ 6108 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6109 rsp_payload->port_speed_desc.desc_len = 6110 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6111 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6112 qla25xx_fdmi_port_speed_capability(ha)); 6113 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6114 qla25xx_fdmi_port_speed_currently(ha)); 6115 6116 /* Link Error Status Descriptor */ 6117 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6118 rsp_payload->ls_err_desc.desc_len = 6119 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6120 6121 if (stat) { 6122 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6123 if (!rval) { 6124 rsp_payload->ls_err_desc.link_fail_cnt = 6125 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6126 rsp_payload->ls_err_desc.loss_sync_cnt = 6127 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6128 rsp_payload->ls_err_desc.loss_sig_cnt = 6129 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6130 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6131 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6132 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6133 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6134 rsp_payload->ls_err_desc.inval_crc_cnt = 6135 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6136 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6137 } 6138 } 6139 6140 /* Portname Descriptor */ 6141 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6142 rsp_payload->port_name_diag_desc.desc_len = 6143 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6144 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6145 vha->node_name, 6146 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6147 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6148 vha->port_name, 6149 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6150 6151 /* F-Port Portname Descriptor */ 6152 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6153 rsp_payload->port_name_direct_desc.desc_len = 6154 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6155 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6156 vha->fabric_node_name, 6157 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6158 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6159 vha->fabric_port_name, 6160 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6161 6162 /* Bufer Credit Descriptor */ 6163 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6164 rsp_payload->buffer_credit_desc.desc_len = 6165 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6166 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6167 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6168 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6169 6170 if (ha->flags.plogi_template_valid) { 6171 uint32_t tmp = 6172 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6173 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6174 } 6175 6176 if (rsp_payload_length < sizeof(*rsp_payload)) 6177 goto send; 6178 6179 /* Optical Element Descriptor, Temperature */ 6180 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6181 rsp_payload->optical_elmt_desc[0].desc_len = 6182 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6183 /* Optical Element Descriptor, Voltage */ 6184 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6185 rsp_payload->optical_elmt_desc[1].desc_len = 6186 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6187 /* Optical Element Descriptor, Tx Bias Current */ 6188 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6189 rsp_payload->optical_elmt_desc[2].desc_len = 6190 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6191 /* Optical Element Descriptor, Tx Power */ 6192 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6193 rsp_payload->optical_elmt_desc[3].desc_len = 6194 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6195 /* Optical Element Descriptor, Rx Power */ 6196 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6197 rsp_payload->optical_elmt_desc[4].desc_len = 6198 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6199 6200 if (sfp) { 6201 memset(sfp, 0, SFP_RTDI_LEN); 6202 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6203 if (!rval) { 6204 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6205 6206 /* Optical Element Descriptor, Temperature */ 6207 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6208 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6209 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6210 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6211 rsp_payload->optical_elmt_desc[0].element_flags = 6212 cpu_to_be32(1 << 28); 6213 6214 /* Optical Element Descriptor, Voltage */ 6215 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6216 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6217 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6218 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6219 rsp_payload->optical_elmt_desc[1].element_flags = 6220 cpu_to_be32(2 << 28); 6221 6222 /* Optical Element Descriptor, Tx Bias Current */ 6223 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6224 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6225 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6226 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6227 rsp_payload->optical_elmt_desc[2].element_flags = 6228 cpu_to_be32(3 << 28); 6229 6230 /* Optical Element Descriptor, Tx Power */ 6231 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6232 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6233 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6234 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6235 rsp_payload->optical_elmt_desc[3].element_flags = 6236 cpu_to_be32(4 << 28); 6237 6238 /* Optical Element Descriptor, Rx Power */ 6239 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6240 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6241 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6242 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6243 rsp_payload->optical_elmt_desc[4].element_flags = 6244 cpu_to_be32(5 << 28); 6245 } 6246 6247 memset(sfp, 0, SFP_RTDI_LEN); 6248 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6249 if (!rval) { 6250 /* Temperature high/low alarm/warning */ 6251 rsp_payload->optical_elmt_desc[0].element_flags |= 6252 cpu_to_be32( 6253 (sfp[0] >> 7 & 1) << 3 | 6254 (sfp[0] >> 6 & 1) << 2 | 6255 (sfp[4] >> 7 & 1) << 1 | 6256 (sfp[4] >> 6 & 1) << 0); 6257 6258 /* Voltage high/low alarm/warning */ 6259 rsp_payload->optical_elmt_desc[1].element_flags |= 6260 cpu_to_be32( 6261 (sfp[0] >> 5 & 1) << 3 | 6262 (sfp[0] >> 4 & 1) << 2 | 6263 (sfp[4] >> 5 & 1) << 1 | 6264 (sfp[4] >> 4 & 1) << 0); 6265 6266 /* Tx Bias Current high/low alarm/warning */ 6267 rsp_payload->optical_elmt_desc[2].element_flags |= 6268 cpu_to_be32( 6269 (sfp[0] >> 3 & 1) << 3 | 6270 (sfp[0] >> 2 & 1) << 2 | 6271 (sfp[4] >> 3 & 1) << 1 | 6272 (sfp[4] >> 2 & 1) << 0); 6273 6274 /* Tx Power high/low alarm/warning */ 6275 rsp_payload->optical_elmt_desc[3].element_flags |= 6276 cpu_to_be32( 6277 (sfp[0] >> 1 & 1) << 3 | 6278 (sfp[0] >> 0 & 1) << 2 | 6279 (sfp[4] >> 1 & 1) << 1 | 6280 (sfp[4] >> 0 & 1) << 0); 6281 6282 /* Rx Power high/low alarm/warning */ 6283 rsp_payload->optical_elmt_desc[4].element_flags |= 6284 cpu_to_be32( 6285 (sfp[1] >> 7 & 1) << 3 | 6286 (sfp[1] >> 6 & 1) << 2 | 6287 (sfp[5] >> 7 & 1) << 1 | 6288 (sfp[5] >> 6 & 1) << 0); 6289 } 6290 } 6291 6292 /* Optical Product Data Descriptor */ 6293 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6294 rsp_payload->optical_prod_desc.desc_len = 6295 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6296 6297 if (sfp) { 6298 memset(sfp, 0, SFP_RTDI_LEN); 6299 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6300 if (!rval) { 6301 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6302 sfp + 0, 6303 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6304 memcpy(rsp_payload->optical_prod_desc.part_number, 6305 sfp + 20, 6306 sizeof(rsp_payload->optical_prod_desc.part_number)); 6307 memcpy(rsp_payload->optical_prod_desc.revision, 6308 sfp + 36, 6309 sizeof(rsp_payload->optical_prod_desc.revision)); 6310 memcpy(rsp_payload->optical_prod_desc.serial_number, 6311 sfp + 48, 6312 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6313 } 6314 6315 memset(sfp, 0, SFP_RTDI_LEN); 6316 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6317 if (!rval) { 6318 memcpy(rsp_payload->optical_prod_desc.date, 6319 sfp + 0, 6320 sizeof(rsp_payload->optical_prod_desc.date)); 6321 } 6322 } 6323 6324 send: 6325 ql_dbg(ql_dbg_init, vha, 0x0183, 6326 "Sending ELS Response to RDP Request...\n"); 6327 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6328 "-------- ELS RSP -------\n"); 6329 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6330 rsp_els, sizeof(*rsp_els)); 6331 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6332 "-------- ELS RSP PAYLOAD -------\n"); 6333 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6334 rsp_payload, rsp_payload_length); 6335 6336 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6337 6338 if (rval) { 6339 ql_log(ql_log_warn, vha, 0x0188, 6340 "%s: iocb failed to execute -> %x\n", __func__, rval); 6341 } else if (rsp_els->comp_status) { 6342 ql_log(ql_log_warn, vha, 0x0189, 6343 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6344 __func__, rsp_els->comp_status, 6345 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6346 } else { 6347 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6348 } 6349 6350 dealloc: 6351 if (stat) 6352 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6353 stat, stat_dma); 6354 if (sfp) 6355 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6356 sfp, sfp_dma); 6357 if (rsp_payload) 6358 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6359 rsp_payload, rsp_payload_dma); 6360 if (rsp_els) 6361 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6362 rsp_els, rsp_els_dma); 6363 } 6364 6365 void 6366 qla24xx_free_purex_item(struct purex_item *item) 6367 { 6368 if (item == &item->vha->default_item) 6369 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6370 else 6371 kfree(item); 6372 } 6373 6374 void qla24xx_process_purex_list(struct purex_list *list) 6375 { 6376 struct list_head head = LIST_HEAD_INIT(head); 6377 struct purex_item *item, *next; 6378 ulong flags; 6379 6380 spin_lock_irqsave(&list->lock, flags); 6381 list_splice_init(&list->head, &head); 6382 spin_unlock_irqrestore(&list->lock, flags); 6383 6384 list_for_each_entry_safe(item, next, &head, list) { 6385 list_del(&item->list); 6386 item->process_item(item->vha, item); 6387 qla24xx_free_purex_item(item); 6388 } 6389 } 6390 6391 /* 6392 * Context: task, can sleep 6393 */ 6394 void 6395 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6396 { 6397 #if 0 6398 uint16_t options = (requester_id << 15) | BIT_7; 6399 #endif 6400 uint16_t retry; 6401 uint32_t data; 6402 struct qla_hw_data *ha = base_vha->hw; 6403 6404 might_sleep(); 6405 6406 /* IDC-unlock implementation using driver-unlock/lock-id 6407 * remote registers 6408 */ 6409 retry = 0; 6410 retry_unlock: 6411 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6412 == QLA_SUCCESS) { 6413 if (data == ha->portnum) { 6414 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6415 /* Clearing lock-id by setting 0xff */ 6416 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6417 } else if (retry < 10) { 6418 /* SV: XXX: IDC unlock retrying needed here? */ 6419 6420 /* Retry for IDC-unlock */ 6421 msleep(QLA83XX_WAIT_LOGIC_MS); 6422 retry++; 6423 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6424 "Failed to release IDC lock, retrying=%d\n", retry); 6425 goto retry_unlock; 6426 } 6427 } else if (retry < 10) { 6428 /* Retry for IDC-unlock */ 6429 msleep(QLA83XX_WAIT_LOGIC_MS); 6430 retry++; 6431 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6432 "Failed to read drv-lockid, retrying=%d\n", retry); 6433 goto retry_unlock; 6434 } 6435 6436 return; 6437 6438 #if 0 6439 /* XXX: IDC-unlock implementation using access-control mbx */ 6440 retry = 0; 6441 retry_unlock2: 6442 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6443 if (retry < 10) { 6444 /* Retry for IDC-unlock */ 6445 msleep(QLA83XX_WAIT_LOGIC_MS); 6446 retry++; 6447 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6448 "Failed to release IDC lock, retrying=%d\n", retry); 6449 goto retry_unlock2; 6450 } 6451 } 6452 6453 return; 6454 #endif 6455 } 6456 6457 int 6458 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6459 { 6460 int rval = QLA_SUCCESS; 6461 struct qla_hw_data *ha = vha->hw; 6462 uint32_t drv_presence; 6463 6464 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6465 if (rval == QLA_SUCCESS) { 6466 drv_presence |= (1 << ha->portnum); 6467 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6468 drv_presence); 6469 } 6470 6471 return rval; 6472 } 6473 6474 int 6475 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6476 { 6477 int rval = QLA_SUCCESS; 6478 6479 qla83xx_idc_lock(vha, 0); 6480 rval = __qla83xx_set_drv_presence(vha); 6481 qla83xx_idc_unlock(vha, 0); 6482 6483 return rval; 6484 } 6485 6486 int 6487 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6488 { 6489 int rval = QLA_SUCCESS; 6490 struct qla_hw_data *ha = vha->hw; 6491 uint32_t drv_presence; 6492 6493 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6494 if (rval == QLA_SUCCESS) { 6495 drv_presence &= ~(1 << ha->portnum); 6496 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6497 drv_presence); 6498 } 6499 6500 return rval; 6501 } 6502 6503 int 6504 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6505 { 6506 int rval = QLA_SUCCESS; 6507 6508 qla83xx_idc_lock(vha, 0); 6509 rval = __qla83xx_clear_drv_presence(vha); 6510 qla83xx_idc_unlock(vha, 0); 6511 6512 return rval; 6513 } 6514 6515 static void 6516 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6517 { 6518 struct qla_hw_data *ha = vha->hw; 6519 uint32_t drv_ack, drv_presence; 6520 unsigned long ack_timeout; 6521 6522 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6523 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6524 while (1) { 6525 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6526 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6527 if ((drv_ack & drv_presence) == drv_presence) 6528 break; 6529 6530 if (time_after_eq(jiffies, ack_timeout)) { 6531 ql_log(ql_log_warn, vha, 0xb067, 6532 "RESET ACK TIMEOUT! drv_presence=0x%x " 6533 "drv_ack=0x%x\n", drv_presence, drv_ack); 6534 /* 6535 * The function(s) which did not ack in time are forced 6536 * to withdraw any further participation in the IDC 6537 * reset. 6538 */ 6539 if (drv_ack != drv_presence) 6540 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6541 drv_ack); 6542 break; 6543 } 6544 6545 qla83xx_idc_unlock(vha, 0); 6546 msleep(1000); 6547 qla83xx_idc_lock(vha, 0); 6548 } 6549 6550 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6551 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6552 } 6553 6554 static int 6555 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6556 { 6557 int rval = QLA_SUCCESS; 6558 uint32_t idc_control; 6559 6560 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6561 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6562 6563 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6564 __qla83xx_get_idc_control(vha, &idc_control); 6565 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6566 __qla83xx_set_idc_control(vha, 0); 6567 6568 qla83xx_idc_unlock(vha, 0); 6569 rval = qla83xx_restart_nic_firmware(vha); 6570 qla83xx_idc_lock(vha, 0); 6571 6572 if (rval != QLA_SUCCESS) { 6573 ql_log(ql_log_fatal, vha, 0xb06a, 6574 "Failed to restart NIC f/w.\n"); 6575 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6576 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6577 } else { 6578 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6579 "Success in restarting nic f/w.\n"); 6580 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6581 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6582 } 6583 6584 return rval; 6585 } 6586 6587 /* Assumes idc_lock always held on entry */ 6588 int 6589 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6590 { 6591 struct qla_hw_data *ha = base_vha->hw; 6592 int rval = QLA_SUCCESS; 6593 unsigned long dev_init_timeout; 6594 uint32_t dev_state; 6595 6596 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6597 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6598 6599 while (1) { 6600 6601 if (time_after_eq(jiffies, dev_init_timeout)) { 6602 ql_log(ql_log_warn, base_vha, 0xb06e, 6603 "Initialization TIMEOUT!\n"); 6604 /* Init timeout. Disable further NIC Core 6605 * communication. 6606 */ 6607 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6608 QLA8XXX_DEV_FAILED); 6609 ql_log(ql_log_info, base_vha, 0xb06f, 6610 "HW State: FAILED.\n"); 6611 } 6612 6613 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6614 switch (dev_state) { 6615 case QLA8XXX_DEV_READY: 6616 if (ha->flags.nic_core_reset_owner) 6617 qla83xx_idc_audit(base_vha, 6618 IDC_AUDIT_COMPLETION); 6619 ha->flags.nic_core_reset_owner = 0; 6620 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6621 "Reset_owner reset by 0x%x.\n", 6622 ha->portnum); 6623 goto exit; 6624 case QLA8XXX_DEV_COLD: 6625 if (ha->flags.nic_core_reset_owner) 6626 rval = qla83xx_device_bootstrap(base_vha); 6627 else { 6628 /* Wait for AEN to change device-state */ 6629 qla83xx_idc_unlock(base_vha, 0); 6630 msleep(1000); 6631 qla83xx_idc_lock(base_vha, 0); 6632 } 6633 break; 6634 case QLA8XXX_DEV_INITIALIZING: 6635 /* Wait for AEN to change device-state */ 6636 qla83xx_idc_unlock(base_vha, 0); 6637 msleep(1000); 6638 qla83xx_idc_lock(base_vha, 0); 6639 break; 6640 case QLA8XXX_DEV_NEED_RESET: 6641 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6642 qla83xx_need_reset_handler(base_vha); 6643 else { 6644 /* Wait for AEN to change device-state */ 6645 qla83xx_idc_unlock(base_vha, 0); 6646 msleep(1000); 6647 qla83xx_idc_lock(base_vha, 0); 6648 } 6649 /* reset timeout value after need reset handler */ 6650 dev_init_timeout = jiffies + 6651 (ha->fcoe_dev_init_timeout * HZ); 6652 break; 6653 case QLA8XXX_DEV_NEED_QUIESCENT: 6654 /* XXX: DEBUG for now */ 6655 qla83xx_idc_unlock(base_vha, 0); 6656 msleep(1000); 6657 qla83xx_idc_lock(base_vha, 0); 6658 break; 6659 case QLA8XXX_DEV_QUIESCENT: 6660 /* XXX: DEBUG for now */ 6661 if (ha->flags.quiesce_owner) 6662 goto exit; 6663 6664 qla83xx_idc_unlock(base_vha, 0); 6665 msleep(1000); 6666 qla83xx_idc_lock(base_vha, 0); 6667 dev_init_timeout = jiffies + 6668 (ha->fcoe_dev_init_timeout * HZ); 6669 break; 6670 case QLA8XXX_DEV_FAILED: 6671 if (ha->flags.nic_core_reset_owner) 6672 qla83xx_idc_audit(base_vha, 6673 IDC_AUDIT_COMPLETION); 6674 ha->flags.nic_core_reset_owner = 0; 6675 __qla83xx_clear_drv_presence(base_vha); 6676 qla83xx_idc_unlock(base_vha, 0); 6677 qla8xxx_dev_failed_handler(base_vha); 6678 rval = QLA_FUNCTION_FAILED; 6679 qla83xx_idc_lock(base_vha, 0); 6680 goto exit; 6681 case QLA8XXX_BAD_VALUE: 6682 qla83xx_idc_unlock(base_vha, 0); 6683 msleep(1000); 6684 qla83xx_idc_lock(base_vha, 0); 6685 break; 6686 default: 6687 ql_log(ql_log_warn, base_vha, 0xb071, 6688 "Unknown Device State: %x.\n", dev_state); 6689 qla83xx_idc_unlock(base_vha, 0); 6690 qla8xxx_dev_failed_handler(base_vha); 6691 rval = QLA_FUNCTION_FAILED; 6692 qla83xx_idc_lock(base_vha, 0); 6693 goto exit; 6694 } 6695 } 6696 6697 exit: 6698 return rval; 6699 } 6700 6701 void 6702 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6703 { 6704 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6705 board_disable); 6706 struct pci_dev *pdev = ha->pdev; 6707 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6708 6709 ql_log(ql_log_warn, base_vha, 0x015b, 6710 "Disabling adapter.\n"); 6711 6712 if (!atomic_read(&pdev->enable_cnt)) { 6713 ql_log(ql_log_info, base_vha, 0xfffc, 6714 "PCI device disabled, no action req for PCI error=%lx\n", 6715 base_vha->pci_flags); 6716 return; 6717 } 6718 6719 /* 6720 * if UNLOADING flag is already set, then continue unload, 6721 * where it was set first. 6722 */ 6723 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6724 return; 6725 6726 qla2x00_wait_for_sess_deletion(base_vha); 6727 6728 qla2x00_delete_all_vps(ha, base_vha); 6729 6730 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6731 6732 qla2x00_dfs_remove(base_vha); 6733 6734 qla84xx_put_chip(base_vha); 6735 6736 if (base_vha->timer_active) 6737 qla2x00_stop_timer(base_vha); 6738 6739 base_vha->flags.online = 0; 6740 6741 qla2x00_destroy_deferred_work(ha); 6742 6743 /* 6744 * Do not try to stop beacon blink as it will issue a mailbox 6745 * command. 6746 */ 6747 qla2x00_free_sysfs_attr(base_vha, false); 6748 6749 fc_remove_host(base_vha->host); 6750 6751 scsi_remove_host(base_vha->host); 6752 6753 base_vha->flags.init_done = 0; 6754 qla25xx_delete_queues(base_vha); 6755 qla2x00_free_fcports(base_vha); 6756 qla2x00_free_irqs(base_vha); 6757 qla2x00_mem_free(ha); 6758 qla82xx_md_free(base_vha); 6759 qla2x00_free_queues(ha); 6760 6761 qla2x00_unmap_iobases(ha); 6762 6763 pci_release_selected_regions(ha->pdev, ha->bars); 6764 pci_disable_pcie_error_reporting(pdev); 6765 pci_disable_device(pdev); 6766 6767 /* 6768 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6769 */ 6770 } 6771 6772 /************************************************************************** 6773 * qla2x00_do_dpc 6774 * This kernel thread is a task that is schedule by the interrupt handler 6775 * to perform the background processing for interrupts. 6776 * 6777 * Notes: 6778 * This task always run in the context of a kernel thread. It 6779 * is kick-off by the driver's detect code and starts up 6780 * up one per adapter. It immediately goes to sleep and waits for 6781 * some fibre event. When either the interrupt handler or 6782 * the timer routine detects a event it will one of the task 6783 * bits then wake us up. 6784 **************************************************************************/ 6785 static int 6786 qla2x00_do_dpc(void *data) 6787 { 6788 scsi_qla_host_t *base_vha; 6789 struct qla_hw_data *ha; 6790 uint32_t online; 6791 struct qla_qpair *qpair; 6792 6793 ha = (struct qla_hw_data *)data; 6794 base_vha = pci_get_drvdata(ha->pdev); 6795 6796 set_user_nice(current, MIN_NICE); 6797 6798 set_current_state(TASK_INTERRUPTIBLE); 6799 while (!kthread_should_stop()) { 6800 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6801 "DPC handler sleeping.\n"); 6802 6803 schedule(); 6804 6805 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6806 qla_pci_set_eeh_busy(base_vha); 6807 6808 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6809 goto end_loop; 6810 6811 if (ha->flags.eeh_busy) { 6812 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6813 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6814 goto end_loop; 6815 } 6816 6817 ha->dpc_active = 1; 6818 6819 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6820 "DPC handler waking up, dpc_flags=0x%lx.\n", 6821 base_vha->dpc_flags); 6822 6823 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6824 break; 6825 6826 if (IS_P3P_TYPE(ha)) { 6827 if (IS_QLA8044(ha)) { 6828 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6829 &base_vha->dpc_flags)) { 6830 qla8044_idc_lock(ha); 6831 qla8044_wr_direct(base_vha, 6832 QLA8044_CRB_DEV_STATE_INDEX, 6833 QLA8XXX_DEV_FAILED); 6834 qla8044_idc_unlock(ha); 6835 ql_log(ql_log_info, base_vha, 0x4004, 6836 "HW State: FAILED.\n"); 6837 qla8044_device_state_handler(base_vha); 6838 continue; 6839 } 6840 6841 } else { 6842 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6843 &base_vha->dpc_flags)) { 6844 qla82xx_idc_lock(ha); 6845 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6846 QLA8XXX_DEV_FAILED); 6847 qla82xx_idc_unlock(ha); 6848 ql_log(ql_log_info, base_vha, 0x0151, 6849 "HW State: FAILED.\n"); 6850 qla82xx_device_state_handler(base_vha); 6851 continue; 6852 } 6853 } 6854 6855 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6856 &base_vha->dpc_flags)) { 6857 6858 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6859 "FCoE context reset scheduled.\n"); 6860 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6861 &base_vha->dpc_flags))) { 6862 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6863 /* FCoE-ctx reset failed. 6864 * Escalate to chip-reset 6865 */ 6866 set_bit(ISP_ABORT_NEEDED, 6867 &base_vha->dpc_flags); 6868 } 6869 clear_bit(ABORT_ISP_ACTIVE, 6870 &base_vha->dpc_flags); 6871 } 6872 6873 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6874 "FCoE context reset end.\n"); 6875 } 6876 } else if (IS_QLAFX00(ha)) { 6877 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6878 &base_vha->dpc_flags)) { 6879 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6880 "Firmware Reset Recovery\n"); 6881 if (qlafx00_reset_initialize(base_vha)) { 6882 /* Failed. Abort isp later. */ 6883 if (!test_bit(UNLOADING, 6884 &base_vha->dpc_flags)) { 6885 set_bit(ISP_UNRECOVERABLE, 6886 &base_vha->dpc_flags); 6887 ql_dbg(ql_dbg_dpc, base_vha, 6888 0x4021, 6889 "Reset Recovery Failed\n"); 6890 } 6891 } 6892 } 6893 6894 if (test_and_clear_bit(FX00_TARGET_SCAN, 6895 &base_vha->dpc_flags)) { 6896 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6897 "ISPFx00 Target Scan scheduled\n"); 6898 if (qlafx00_rescan_isp(base_vha)) { 6899 if (!test_bit(UNLOADING, 6900 &base_vha->dpc_flags)) 6901 set_bit(ISP_UNRECOVERABLE, 6902 &base_vha->dpc_flags); 6903 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6904 "ISPFx00 Target Scan Failed\n"); 6905 } 6906 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6907 "ISPFx00 Target Scan End\n"); 6908 } 6909 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6910 &base_vha->dpc_flags)) { 6911 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6912 "ISPFx00 Host Info resend scheduled\n"); 6913 qlafx00_fx_disc(base_vha, 6914 &base_vha->hw->mr.fcport, 6915 FXDISC_REG_HOST_INFO); 6916 } 6917 } 6918 6919 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6920 &base_vha->dpc_flags)) { 6921 /* Semantic: 6922 * - NO-OP -- await next ISP-ABORT. Preferred method 6923 * to minimize disruptions that will occur 6924 * when a forced chip-reset occurs. 6925 * - Force -- ISP-ABORT scheduled. 6926 */ 6927 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6928 } 6929 6930 if (test_and_clear_bit 6931 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6932 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6933 bool do_reset = true; 6934 6935 switch (base_vha->qlini_mode) { 6936 case QLA2XXX_INI_MODE_ENABLED: 6937 break; 6938 case QLA2XXX_INI_MODE_DISABLED: 6939 if (!qla_tgt_mode_enabled(base_vha) && 6940 !ha->flags.fw_started) 6941 do_reset = false; 6942 break; 6943 case QLA2XXX_INI_MODE_DUAL: 6944 if (!qla_dual_mode_enabled(base_vha) && 6945 !ha->flags.fw_started) 6946 do_reset = false; 6947 break; 6948 default: 6949 break; 6950 } 6951 6952 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6953 &base_vha->dpc_flags))) { 6954 base_vha->flags.online = 1; 6955 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6956 "ISP abort scheduled.\n"); 6957 if (ha->isp_ops->abort_isp(base_vha)) { 6958 /* failed. retry later */ 6959 set_bit(ISP_ABORT_NEEDED, 6960 &base_vha->dpc_flags); 6961 } 6962 clear_bit(ABORT_ISP_ACTIVE, 6963 &base_vha->dpc_flags); 6964 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6965 "ISP abort end.\n"); 6966 } 6967 } 6968 6969 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6970 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6971 qla24xx_process_purex_list 6972 (&base_vha->purex_list); 6973 clear_bit(PROCESS_PUREX_IOCB, 6974 &base_vha->dpc_flags); 6975 } 6976 } 6977 6978 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6979 &base_vha->dpc_flags)) { 6980 qla2x00_update_fcports(base_vha); 6981 } 6982 6983 if (IS_QLAFX00(ha)) 6984 goto loop_resync_check; 6985 6986 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6987 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6988 "Quiescence mode scheduled.\n"); 6989 if (IS_P3P_TYPE(ha)) { 6990 if (IS_QLA82XX(ha)) 6991 qla82xx_device_state_handler(base_vha); 6992 if (IS_QLA8044(ha)) 6993 qla8044_device_state_handler(base_vha); 6994 clear_bit(ISP_QUIESCE_NEEDED, 6995 &base_vha->dpc_flags); 6996 if (!ha->flags.quiesce_owner) { 6997 qla2x00_perform_loop_resync(base_vha); 6998 if (IS_QLA82XX(ha)) { 6999 qla82xx_idc_lock(ha); 7000 qla82xx_clear_qsnt_ready( 7001 base_vha); 7002 qla82xx_idc_unlock(ha); 7003 } else if (IS_QLA8044(ha)) { 7004 qla8044_idc_lock(ha); 7005 qla8044_clear_qsnt_ready( 7006 base_vha); 7007 qla8044_idc_unlock(ha); 7008 } 7009 } 7010 } else { 7011 clear_bit(ISP_QUIESCE_NEEDED, 7012 &base_vha->dpc_flags); 7013 qla2x00_quiesce_io(base_vha); 7014 } 7015 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7016 "Quiescence mode end.\n"); 7017 } 7018 7019 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7020 &base_vha->dpc_flags) && 7021 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7022 7023 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7024 "Reset marker scheduled.\n"); 7025 qla2x00_rst_aen(base_vha); 7026 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7027 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7028 "Reset marker end.\n"); 7029 } 7030 7031 /* Retry each device up to login retry count */ 7032 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7033 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7034 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7035 7036 if (!base_vha->relogin_jif || 7037 time_after_eq(jiffies, base_vha->relogin_jif)) { 7038 base_vha->relogin_jif = jiffies + HZ; 7039 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7040 7041 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7042 "Relogin scheduled.\n"); 7043 qla24xx_post_relogin_work(base_vha); 7044 } 7045 } 7046 loop_resync_check: 7047 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 7048 &base_vha->dpc_flags)) { 7049 7050 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7051 "Loop resync scheduled.\n"); 7052 7053 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7054 &base_vha->dpc_flags))) { 7055 7056 qla2x00_loop_resync(base_vha); 7057 7058 clear_bit(LOOP_RESYNC_ACTIVE, 7059 &base_vha->dpc_flags); 7060 } 7061 7062 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7063 "Loop resync end.\n"); 7064 } 7065 7066 if (IS_QLAFX00(ha)) 7067 goto intr_on_check; 7068 7069 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7070 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7071 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7072 qla2xxx_flash_npiv_conf(base_vha); 7073 } 7074 7075 intr_on_check: 7076 if (!ha->interrupts_on) 7077 ha->isp_ops->enable_intrs(ha); 7078 7079 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7080 &base_vha->dpc_flags)) { 7081 if (ha->beacon_blink_led == 1) 7082 ha->isp_ops->beacon_blink(base_vha); 7083 } 7084 7085 /* qpair online check */ 7086 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7087 &base_vha->dpc_flags)) { 7088 if (ha->flags.eeh_busy || 7089 ha->flags.pci_channel_io_perm_failure) 7090 online = 0; 7091 else 7092 online = 1; 7093 7094 mutex_lock(&ha->mq_lock); 7095 list_for_each_entry(qpair, &base_vha->qp_list, 7096 qp_list_elem) 7097 qpair->online = online; 7098 mutex_unlock(&ha->mq_lock); 7099 } 7100 7101 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7102 &base_vha->dpc_flags)) { 7103 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7104 7105 if (threshold > ha->orig_fw_xcb_count) 7106 threshold = ha->orig_fw_xcb_count; 7107 7108 ql_log(ql_log_info, base_vha, 0xffffff, 7109 "SET ZIO Activity exchange threshold to %d.\n", 7110 threshold); 7111 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7112 ql_log(ql_log_info, base_vha, 0xffffff, 7113 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7114 threshold); 7115 } 7116 } 7117 7118 if (!IS_QLAFX00(ha)) 7119 qla2x00_do_dpc_all_vps(base_vha); 7120 7121 if (test_and_clear_bit(N2N_LINK_RESET, 7122 &base_vha->dpc_flags)) { 7123 qla2x00_lip_reset(base_vha); 7124 } 7125 7126 ha->dpc_active = 0; 7127 end_loop: 7128 set_current_state(TASK_INTERRUPTIBLE); 7129 } /* End of while(1) */ 7130 __set_current_state(TASK_RUNNING); 7131 7132 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7133 "DPC handler exiting.\n"); 7134 7135 /* 7136 * Make sure that nobody tries to wake us up again. 7137 */ 7138 ha->dpc_active = 0; 7139 7140 /* Cleanup any residual CTX SRBs. */ 7141 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7142 7143 return 0; 7144 } 7145 7146 void 7147 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7148 { 7149 struct qla_hw_data *ha = vha->hw; 7150 struct task_struct *t = ha->dpc_thread; 7151 7152 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7153 wake_up_process(t); 7154 } 7155 7156 /* 7157 * qla2x00_rst_aen 7158 * Processes asynchronous reset. 7159 * 7160 * Input: 7161 * ha = adapter block pointer. 7162 */ 7163 static void 7164 qla2x00_rst_aen(scsi_qla_host_t *vha) 7165 { 7166 if (vha->flags.online && !vha->flags.reset_active && 7167 !atomic_read(&vha->loop_down_timer) && 7168 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7169 do { 7170 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7171 7172 /* 7173 * Issue marker command only when we are going to start 7174 * the I/O. 7175 */ 7176 vha->marker_needed = 1; 7177 } while (!atomic_read(&vha->loop_down_timer) && 7178 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7179 } 7180 } 7181 7182 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7183 { 7184 struct qla_hw_data *ha = vha->hw; 7185 u32 cmpl_cnt; 7186 u16 i; 7187 bool do_heartbeat = false; 7188 7189 /* 7190 * Allow do_heartbeat only if we don’t have any active interrupts, 7191 * but there are still IOs outstanding with firmware. 7192 */ 7193 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7194 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7195 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7196 do_heartbeat = true; 7197 goto skip; 7198 } 7199 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7200 7201 for (i = 0; i < ha->max_qpairs; i++) { 7202 if (ha->queue_pair_map[i]) { 7203 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7204 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7205 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7206 do_heartbeat = true; 7207 break; 7208 } 7209 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7210 } 7211 } 7212 7213 skip: 7214 return do_heartbeat; 7215 } 7216 7217 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7218 { 7219 struct qla_hw_data *ha = vha->hw; 7220 7221 if (vha->vp_idx) 7222 return; 7223 7224 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7225 return; 7226 7227 /* 7228 * dpc thread cannot run if heartbeat is running at the same time. 7229 * We also do not want to starve heartbeat task. Therefore, do 7230 * heartbeat task at least once every 5 seconds. 7231 */ 7232 if (dpc_started && 7233 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7234 return; 7235 7236 if (qla_do_heartbeat(vha)) { 7237 ha->last_heartbeat_run_jiffies = jiffies; 7238 queue_work(ha->wq, &ha->heartbeat_work); 7239 } 7240 } 7241 7242 /************************************************************************** 7243 * qla2x00_timer 7244 * 7245 * Description: 7246 * One second timer 7247 * 7248 * Context: Interrupt 7249 ***************************************************************************/ 7250 void 7251 qla2x00_timer(struct timer_list *t) 7252 { 7253 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7254 unsigned long cpu_flags = 0; 7255 int start_dpc = 0; 7256 int index; 7257 srb_t *sp; 7258 uint16_t w; 7259 struct qla_hw_data *ha = vha->hw; 7260 struct req_que *req; 7261 unsigned long flags; 7262 fc_port_t *fcport = NULL; 7263 7264 if (ha->flags.eeh_busy) { 7265 ql_dbg(ql_dbg_timer, vha, 0x6000, 7266 "EEH = %d, restarting timer.\n", 7267 ha->flags.eeh_busy); 7268 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7269 return; 7270 } 7271 7272 /* 7273 * Hardware read to raise pending EEH errors during mailbox waits. If 7274 * the read returns -1 then disable the board. 7275 */ 7276 if (!pci_channel_offline(ha->pdev)) { 7277 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7278 qla2x00_check_reg16_for_disconnect(vha, w); 7279 } 7280 7281 /* Make sure qla82xx_watchdog is run only for physical port */ 7282 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7283 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7284 start_dpc++; 7285 if (IS_QLA82XX(ha)) 7286 qla82xx_watchdog(vha); 7287 else if (IS_QLA8044(ha)) 7288 qla8044_watchdog(vha); 7289 } 7290 7291 if (!vha->vp_idx && IS_QLAFX00(ha)) 7292 qlafx00_timer_routine(vha); 7293 7294 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7295 vha->link_down_time++; 7296 7297 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7298 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7299 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7300 fcport->tgt_link_down_time++; 7301 } 7302 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7303 7304 /* Loop down handler. */ 7305 if (atomic_read(&vha->loop_down_timer) > 0 && 7306 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7307 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7308 && vha->flags.online) { 7309 7310 if (atomic_read(&vha->loop_down_timer) == 7311 vha->loop_down_abort_time) { 7312 7313 ql_log(ql_log_info, vha, 0x6008, 7314 "Loop down - aborting the queues before time expires.\n"); 7315 7316 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7317 atomic_set(&vha->loop_state, LOOP_DEAD); 7318 7319 /* 7320 * Schedule an ISP abort to return any FCP2-device 7321 * commands. 7322 */ 7323 /* NPIV - scan physical port only */ 7324 if (!vha->vp_idx) { 7325 spin_lock_irqsave(&ha->hardware_lock, 7326 cpu_flags); 7327 req = ha->req_q_map[0]; 7328 for (index = 1; 7329 index < req->num_outstanding_cmds; 7330 index++) { 7331 fc_port_t *sfcp; 7332 7333 sp = req->outstanding_cmds[index]; 7334 if (!sp) 7335 continue; 7336 if (sp->cmd_type != TYPE_SRB) 7337 continue; 7338 if (sp->type != SRB_SCSI_CMD) 7339 continue; 7340 sfcp = sp->fcport; 7341 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7342 continue; 7343 7344 if (IS_QLA82XX(ha)) 7345 set_bit(FCOE_CTX_RESET_NEEDED, 7346 &vha->dpc_flags); 7347 else 7348 set_bit(ISP_ABORT_NEEDED, 7349 &vha->dpc_flags); 7350 break; 7351 } 7352 spin_unlock_irqrestore(&ha->hardware_lock, 7353 cpu_flags); 7354 } 7355 start_dpc++; 7356 } 7357 7358 /* if the loop has been down for 4 minutes, reinit adapter */ 7359 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7360 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7361 ql_log(ql_log_warn, vha, 0x6009, 7362 "Loop down - aborting ISP.\n"); 7363 7364 if (IS_QLA82XX(ha)) 7365 set_bit(FCOE_CTX_RESET_NEEDED, 7366 &vha->dpc_flags); 7367 else 7368 set_bit(ISP_ABORT_NEEDED, 7369 &vha->dpc_flags); 7370 } 7371 } 7372 ql_dbg(ql_dbg_timer, vha, 0x600a, 7373 "Loop down - seconds remaining %d.\n", 7374 atomic_read(&vha->loop_down_timer)); 7375 } 7376 /* Check if beacon LED needs to be blinked for physical host only */ 7377 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7378 /* There is no beacon_blink function for ISP82xx */ 7379 if (!IS_P3P_TYPE(ha)) { 7380 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7381 start_dpc++; 7382 } 7383 } 7384 7385 /* check if edif running */ 7386 if (vha->hw->flags.edif_enabled) 7387 qla_edif_timer(vha); 7388 7389 /* Process any deferred work. */ 7390 if (!list_empty(&vha->work_list)) { 7391 unsigned long flags; 7392 bool q = false; 7393 7394 spin_lock_irqsave(&vha->work_lock, flags); 7395 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7396 q = true; 7397 spin_unlock_irqrestore(&vha->work_lock, flags); 7398 if (q) 7399 queue_work(vha->hw->wq, &vha->iocb_work); 7400 } 7401 7402 /* 7403 * FC-NVME 7404 * see if the active AEN count has changed from what was last reported. 7405 */ 7406 index = atomic_read(&ha->nvme_active_aen_cnt); 7407 if (!vha->vp_idx && 7408 (index != ha->nvme_last_rptd_aen) && 7409 ha->zio_mode == QLA_ZIO_MODE_6 && 7410 !ha->flags.host_shutting_down) { 7411 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7412 ql_log(ql_log_info, vha, 0x3002, 7413 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7414 ha->nvme_last_rptd_aen); 7415 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7416 start_dpc++; 7417 } 7418 7419 if (!vha->vp_idx && 7420 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7421 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7422 ql_log(ql_log_info, vha, 0x3002, 7423 "Sched: Set ZIO exchange threshold to %d.\n", 7424 ha->last_zio_threshold); 7425 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7426 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7427 start_dpc++; 7428 } 7429 7430 /* borrowing w to signify dpc will run */ 7431 w = 0; 7432 /* Schedule the DPC routine if needed */ 7433 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7434 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7435 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7436 start_dpc || 7437 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7438 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7439 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7440 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7441 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7442 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7443 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7444 ql_dbg(ql_dbg_timer, vha, 0x600b, 7445 "isp_abort_needed=%d loop_resync_needed=%d " 7446 "fcport_update_needed=%d start_dpc=%d " 7447 "reset_marker_needed=%d", 7448 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7449 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7450 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7451 start_dpc, 7452 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7453 ql_dbg(ql_dbg_timer, vha, 0x600c, 7454 "beacon_blink_needed=%d isp_unrecoverable=%d " 7455 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7456 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7457 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7458 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7459 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7460 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7461 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7462 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7463 qla2xxx_wake_dpc(vha); 7464 w = 1; 7465 } 7466 7467 qla_heart_beat(vha, w); 7468 7469 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7470 } 7471 7472 /* Firmware interface routines. */ 7473 7474 #define FW_ISP21XX 0 7475 #define FW_ISP22XX 1 7476 #define FW_ISP2300 2 7477 #define FW_ISP2322 3 7478 #define FW_ISP24XX 4 7479 #define FW_ISP25XX 5 7480 #define FW_ISP81XX 6 7481 #define FW_ISP82XX 7 7482 #define FW_ISP2031 8 7483 #define FW_ISP8031 9 7484 #define FW_ISP27XX 10 7485 #define FW_ISP28XX 11 7486 7487 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7488 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7489 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7490 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7491 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7492 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7493 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7494 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7495 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7496 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7497 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7498 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7499 7500 7501 static DEFINE_MUTEX(qla_fw_lock); 7502 7503 static struct fw_blob qla_fw_blobs[] = { 7504 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7505 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7506 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7507 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7508 { .name = FW_FILE_ISP24XX, }, 7509 { .name = FW_FILE_ISP25XX, }, 7510 { .name = FW_FILE_ISP81XX, }, 7511 { .name = FW_FILE_ISP82XX, }, 7512 { .name = FW_FILE_ISP2031, }, 7513 { .name = FW_FILE_ISP8031, }, 7514 { .name = FW_FILE_ISP27XX, }, 7515 { .name = FW_FILE_ISP28XX, }, 7516 { .name = NULL, }, 7517 }; 7518 7519 struct fw_blob * 7520 qla2x00_request_firmware(scsi_qla_host_t *vha) 7521 { 7522 struct qla_hw_data *ha = vha->hw; 7523 struct fw_blob *blob; 7524 7525 if (IS_QLA2100(ha)) { 7526 blob = &qla_fw_blobs[FW_ISP21XX]; 7527 } else if (IS_QLA2200(ha)) { 7528 blob = &qla_fw_blobs[FW_ISP22XX]; 7529 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7530 blob = &qla_fw_blobs[FW_ISP2300]; 7531 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7532 blob = &qla_fw_blobs[FW_ISP2322]; 7533 } else if (IS_QLA24XX_TYPE(ha)) { 7534 blob = &qla_fw_blobs[FW_ISP24XX]; 7535 } else if (IS_QLA25XX(ha)) { 7536 blob = &qla_fw_blobs[FW_ISP25XX]; 7537 } else if (IS_QLA81XX(ha)) { 7538 blob = &qla_fw_blobs[FW_ISP81XX]; 7539 } else if (IS_QLA82XX(ha)) { 7540 blob = &qla_fw_blobs[FW_ISP82XX]; 7541 } else if (IS_QLA2031(ha)) { 7542 blob = &qla_fw_blobs[FW_ISP2031]; 7543 } else if (IS_QLA8031(ha)) { 7544 blob = &qla_fw_blobs[FW_ISP8031]; 7545 } else if (IS_QLA27XX(ha)) { 7546 blob = &qla_fw_blobs[FW_ISP27XX]; 7547 } else if (IS_QLA28XX(ha)) { 7548 blob = &qla_fw_blobs[FW_ISP28XX]; 7549 } else { 7550 return NULL; 7551 } 7552 7553 if (!blob->name) 7554 return NULL; 7555 7556 mutex_lock(&qla_fw_lock); 7557 if (blob->fw) 7558 goto out; 7559 7560 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7561 ql_log(ql_log_warn, vha, 0x0063, 7562 "Failed to load firmware image (%s).\n", blob->name); 7563 blob->fw = NULL; 7564 blob = NULL; 7565 } 7566 7567 out: 7568 mutex_unlock(&qla_fw_lock); 7569 return blob; 7570 } 7571 7572 static void 7573 qla2x00_release_firmware(void) 7574 { 7575 struct fw_blob *blob; 7576 7577 mutex_lock(&qla_fw_lock); 7578 for (blob = qla_fw_blobs; blob->name; blob++) 7579 release_firmware(blob->fw); 7580 mutex_unlock(&qla_fw_lock); 7581 } 7582 7583 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7584 { 7585 struct qla_hw_data *ha = vha->hw; 7586 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7587 struct qla_qpair *qpair = NULL; 7588 struct scsi_qla_host *vp, *tvp; 7589 fc_port_t *fcport; 7590 int i; 7591 unsigned long flags; 7592 7593 ql_dbg(ql_dbg_aer, vha, 0x9000, 7594 "%s\n", __func__); 7595 ha->chip_reset++; 7596 7597 ha->base_qpair->chip_reset = ha->chip_reset; 7598 for (i = 0; i < ha->max_qpairs; i++) { 7599 if (ha->queue_pair_map[i]) 7600 ha->queue_pair_map[i]->chip_reset = 7601 ha->base_qpair->chip_reset; 7602 } 7603 7604 /* 7605 * purge mailbox might take a while. Slot Reset/chip reset 7606 * will take care of the purge 7607 */ 7608 7609 mutex_lock(&ha->mq_lock); 7610 ha->base_qpair->online = 0; 7611 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7612 qpair->online = 0; 7613 wmb(); 7614 mutex_unlock(&ha->mq_lock); 7615 7616 qla2x00_mark_all_devices_lost(vha); 7617 7618 spin_lock_irqsave(&ha->vport_slock, flags); 7619 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7620 atomic_inc(&vp->vref_count); 7621 spin_unlock_irqrestore(&ha->vport_slock, flags); 7622 qla2x00_mark_all_devices_lost(vp); 7623 spin_lock_irqsave(&ha->vport_slock, flags); 7624 atomic_dec(&vp->vref_count); 7625 } 7626 spin_unlock_irqrestore(&ha->vport_slock, flags); 7627 7628 /* Clear all async request states across all VPs. */ 7629 list_for_each_entry(fcport, &vha->vp_fcports, list) 7630 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7631 7632 spin_lock_irqsave(&ha->vport_slock, flags); 7633 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7634 atomic_inc(&vp->vref_count); 7635 spin_unlock_irqrestore(&ha->vport_slock, flags); 7636 list_for_each_entry(fcport, &vp->vp_fcports, list) 7637 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7638 spin_lock_irqsave(&ha->vport_slock, flags); 7639 atomic_dec(&vp->vref_count); 7640 } 7641 spin_unlock_irqrestore(&ha->vport_slock, flags); 7642 } 7643 7644 7645 static pci_ers_result_t 7646 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7647 { 7648 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7649 struct qla_hw_data *ha = vha->hw; 7650 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7651 7652 ql_log(ql_log_warn, vha, 0x9000, 7653 "PCI error detected, state %x.\n", state); 7654 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7655 7656 if (!atomic_read(&pdev->enable_cnt)) { 7657 ql_log(ql_log_info, vha, 0xffff, 7658 "PCI device is disabled,state %x\n", state); 7659 ret = PCI_ERS_RESULT_NEED_RESET; 7660 goto out; 7661 } 7662 7663 switch (state) { 7664 case pci_channel_io_normal: 7665 qla_pci_set_eeh_busy(vha); 7666 if (ql2xmqsupport || ql2xnvmeenable) { 7667 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7668 qla2xxx_wake_dpc(vha); 7669 } 7670 ret = PCI_ERS_RESULT_CAN_RECOVER; 7671 break; 7672 case pci_channel_io_frozen: 7673 qla_pci_set_eeh_busy(vha); 7674 ret = PCI_ERS_RESULT_NEED_RESET; 7675 break; 7676 case pci_channel_io_perm_failure: 7677 ha->flags.pci_channel_io_perm_failure = 1; 7678 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7679 if (ql2xmqsupport || ql2xnvmeenable) { 7680 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7681 qla2xxx_wake_dpc(vha); 7682 } 7683 ret = PCI_ERS_RESULT_DISCONNECT; 7684 } 7685 out: 7686 ql_dbg(ql_dbg_aer, vha, 0x600d, 7687 "PCI error detected returning [%x].\n", ret); 7688 return ret; 7689 } 7690 7691 static pci_ers_result_t 7692 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7693 { 7694 int risc_paused = 0; 7695 uint32_t stat; 7696 unsigned long flags; 7697 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7698 struct qla_hw_data *ha = base_vha->hw; 7699 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7700 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7701 7702 ql_log(ql_log_warn, base_vha, 0x9000, 7703 "mmio enabled\n"); 7704 7705 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7706 7707 if (IS_QLA82XX(ha)) 7708 return PCI_ERS_RESULT_RECOVERED; 7709 7710 if (qla2x00_isp_reg_stat(ha)) { 7711 ql_log(ql_log_info, base_vha, 0x803f, 7712 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7713 goto out; 7714 } 7715 7716 spin_lock_irqsave(&ha->hardware_lock, flags); 7717 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7718 stat = rd_reg_word(®->hccr); 7719 if (stat & HCCR_RISC_PAUSE) 7720 risc_paused = 1; 7721 } else if (IS_QLA23XX(ha)) { 7722 stat = rd_reg_dword(®->u.isp2300.host_status); 7723 if (stat & HSR_RISC_PAUSED) 7724 risc_paused = 1; 7725 } else if (IS_FWI2_CAPABLE(ha)) { 7726 stat = rd_reg_dword(®24->host_status); 7727 if (stat & HSRX_RISC_PAUSED) 7728 risc_paused = 1; 7729 } 7730 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7731 7732 if (risc_paused) { 7733 ql_log(ql_log_info, base_vha, 0x9003, 7734 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7735 qla2xxx_dump_fw(base_vha); 7736 } 7737 out: 7738 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7739 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7740 "mmio enabled returning.\n"); 7741 return PCI_ERS_RESULT_NEED_RESET; 7742 } 7743 7744 static pci_ers_result_t 7745 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7746 { 7747 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7748 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7749 struct qla_hw_data *ha = base_vha->hw; 7750 int rc; 7751 struct qla_qpair *qpair = NULL; 7752 7753 ql_log(ql_log_warn, base_vha, 0x9004, 7754 "Slot Reset.\n"); 7755 7756 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7757 /* Workaround: qla2xxx driver which access hardware earlier 7758 * needs error state to be pci_channel_io_online. 7759 * Otherwise mailbox command timesout. 7760 */ 7761 pdev->error_state = pci_channel_io_normal; 7762 7763 pci_restore_state(pdev); 7764 7765 /* pci_restore_state() clears the saved_state flag of the device 7766 * save restored state which resets saved_state flag 7767 */ 7768 pci_save_state(pdev); 7769 7770 if (ha->mem_only) 7771 rc = pci_enable_device_mem(pdev); 7772 else 7773 rc = pci_enable_device(pdev); 7774 7775 if (rc) { 7776 ql_log(ql_log_warn, base_vha, 0x9005, 7777 "Can't re-enable PCI device after reset.\n"); 7778 goto exit_slot_reset; 7779 } 7780 7781 7782 if (ha->isp_ops->pci_config(base_vha)) 7783 goto exit_slot_reset; 7784 7785 mutex_lock(&ha->mq_lock); 7786 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7787 qpair->online = 1; 7788 mutex_unlock(&ha->mq_lock); 7789 7790 ha->flags.eeh_busy = 0; 7791 base_vha->flags.online = 1; 7792 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7793 ha->isp_ops->abort_isp(base_vha); 7794 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7795 7796 if (qla2x00_isp_reg_stat(ha)) { 7797 ha->flags.eeh_busy = 1; 7798 qla_pci_error_cleanup(base_vha); 7799 ql_log(ql_log_warn, base_vha, 0x9005, 7800 "Device unable to recover from PCI error.\n"); 7801 } else { 7802 ret = PCI_ERS_RESULT_RECOVERED; 7803 } 7804 7805 exit_slot_reset: 7806 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7807 "Slot Reset returning %x.\n", ret); 7808 7809 return ret; 7810 } 7811 7812 static void 7813 qla2xxx_pci_resume(struct pci_dev *pdev) 7814 { 7815 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7816 struct qla_hw_data *ha = base_vha->hw; 7817 int ret; 7818 7819 ql_log(ql_log_warn, base_vha, 0x900f, 7820 "Pci Resume.\n"); 7821 7822 7823 ret = qla2x00_wait_for_hba_online(base_vha); 7824 if (ret != QLA_SUCCESS) { 7825 ql_log(ql_log_fatal, base_vha, 0x9002, 7826 "The device failed to resume I/O from slot/link_reset.\n"); 7827 } 7828 ha->pci_error_state = QLA_PCI_RESUME; 7829 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7830 "Pci Resume returning.\n"); 7831 } 7832 7833 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7834 { 7835 struct qla_hw_data *ha = vha->hw; 7836 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7837 bool do_cleanup = false; 7838 unsigned long flags; 7839 7840 if (ha->flags.eeh_busy) 7841 return; 7842 7843 spin_lock_irqsave(&base_vha->work_lock, flags); 7844 if (!ha->flags.eeh_busy) { 7845 ha->flags.eeh_busy = 1; 7846 do_cleanup = true; 7847 } 7848 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7849 7850 if (do_cleanup) 7851 qla_pci_error_cleanup(base_vha); 7852 } 7853 7854 /* 7855 * this routine will schedule a task to pause IO from interrupt context 7856 * if caller sees a PCIE error event (register read = 0xf's) 7857 */ 7858 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7859 { 7860 struct qla_hw_data *ha = vha->hw; 7861 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7862 7863 if (ha->flags.eeh_busy) 7864 return; 7865 7866 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7867 qla2xxx_wake_dpc(base_vha); 7868 } 7869 7870 static void 7871 qla_pci_reset_prepare(struct pci_dev *pdev) 7872 { 7873 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7874 struct qla_hw_data *ha = base_vha->hw; 7875 struct qla_qpair *qpair; 7876 7877 ql_log(ql_log_warn, base_vha, 0xffff, 7878 "%s.\n", __func__); 7879 7880 /* 7881 * PCI FLR/function reset is about to reset the 7882 * slot. Stop the chip to stop all DMA access. 7883 * It is assumed that pci_reset_done will be called 7884 * after FLR to resume Chip operation. 7885 */ 7886 ha->flags.eeh_busy = 1; 7887 mutex_lock(&ha->mq_lock); 7888 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7889 qpair->online = 0; 7890 mutex_unlock(&ha->mq_lock); 7891 7892 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7893 qla2x00_abort_isp_cleanup(base_vha); 7894 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7895 } 7896 7897 static void 7898 qla_pci_reset_done(struct pci_dev *pdev) 7899 { 7900 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7901 struct qla_hw_data *ha = base_vha->hw; 7902 struct qla_qpair *qpair; 7903 7904 ql_log(ql_log_warn, base_vha, 0xffff, 7905 "%s.\n", __func__); 7906 7907 /* 7908 * FLR just completed by PCI layer. Resume adapter 7909 */ 7910 ha->flags.eeh_busy = 0; 7911 mutex_lock(&ha->mq_lock); 7912 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7913 qpair->online = 1; 7914 mutex_unlock(&ha->mq_lock); 7915 7916 base_vha->flags.online = 1; 7917 ha->isp_ops->abort_isp(base_vha); 7918 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7919 } 7920 7921 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7922 { 7923 int rc; 7924 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7925 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7926 7927 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7928 rc = blk_mq_map_queues(qmap); 7929 else 7930 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7931 return rc; 7932 } 7933 7934 struct scsi_host_template qla2xxx_driver_template = { 7935 .module = THIS_MODULE, 7936 .name = QLA2XXX_DRIVER_NAME, 7937 .queuecommand = qla2xxx_queuecommand, 7938 7939 .eh_timed_out = fc_eh_timed_out, 7940 .eh_abort_handler = qla2xxx_eh_abort, 7941 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 7942 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7943 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7944 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7945 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7946 7947 .slave_configure = qla2xxx_slave_configure, 7948 7949 .slave_alloc = qla2xxx_slave_alloc, 7950 .slave_destroy = qla2xxx_slave_destroy, 7951 .scan_finished = qla2xxx_scan_finished, 7952 .scan_start = qla2xxx_scan_start, 7953 .change_queue_depth = scsi_change_queue_depth, 7954 .map_queues = qla2xxx_map_queues, 7955 .this_id = -1, 7956 .cmd_per_lun = 3, 7957 .sg_tablesize = SG_ALL, 7958 7959 .max_sectors = 0xFFFF, 7960 .shost_groups = qla2x00_host_groups, 7961 7962 .supported_mode = MODE_INITIATOR, 7963 .track_queue_depth = 1, 7964 .cmd_size = sizeof(srb_t), 7965 }; 7966 7967 static const struct pci_error_handlers qla2xxx_err_handler = { 7968 .error_detected = qla2xxx_pci_error_detected, 7969 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7970 .slot_reset = qla2xxx_pci_slot_reset, 7971 .resume = qla2xxx_pci_resume, 7972 .reset_prepare = qla_pci_reset_prepare, 7973 .reset_done = qla_pci_reset_done, 7974 }; 7975 7976 static struct pci_device_id qla2xxx_pci_tbl[] = { 7977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7985 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7986 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7987 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7988 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7989 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7990 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7991 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7992 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7993 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7994 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7995 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7996 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7997 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7998 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7999 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8000 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8001 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8002 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8003 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8004 { 0 }, 8005 }; 8006 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8007 8008 static struct pci_driver qla2xxx_pci_driver = { 8009 .name = QLA2XXX_DRIVER_NAME, 8010 .driver = { 8011 .owner = THIS_MODULE, 8012 }, 8013 .id_table = qla2xxx_pci_tbl, 8014 .probe = qla2x00_probe_one, 8015 .remove = qla2x00_remove_one, 8016 .shutdown = qla2x00_shutdown, 8017 .err_handler = &qla2xxx_err_handler, 8018 }; 8019 8020 static const struct file_operations apidev_fops = { 8021 .owner = THIS_MODULE, 8022 .llseek = noop_llseek, 8023 }; 8024 8025 /** 8026 * qla2x00_module_init - Module initialization. 8027 **/ 8028 static int __init 8029 qla2x00_module_init(void) 8030 { 8031 int ret = 0; 8032 8033 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8034 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8035 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8036 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8037 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8038 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8039 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8040 BUILD_BUG_ON(sizeof(request_t) != 64); 8041 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8042 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8043 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8044 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8045 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8046 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8047 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8048 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8049 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8050 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8051 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8052 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8053 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8054 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8055 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8056 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8057 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8058 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8059 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8060 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8061 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8062 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8063 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8064 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8065 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8066 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8067 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8068 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8069 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8070 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8071 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8072 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8073 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8074 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8075 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8076 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8077 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8078 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8079 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8080 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8081 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8082 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8083 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8084 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8085 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8086 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8087 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8088 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8089 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8090 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8091 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8092 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8093 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8094 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8095 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8096 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8097 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8098 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8099 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8100 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8101 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8102 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8103 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8104 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8105 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8106 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8107 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8108 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8109 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8110 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8111 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8112 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8113 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8114 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8115 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8116 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8117 8118 /* Allocate cache for SRBs. */ 8119 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8120 SLAB_HWCACHE_ALIGN, NULL); 8121 if (srb_cachep == NULL) { 8122 ql_log(ql_log_fatal, NULL, 0x0001, 8123 "Unable to allocate SRB cache...Failing load!.\n"); 8124 return -ENOMEM; 8125 } 8126 8127 /* Initialize target kmem_cache and mem_pools */ 8128 ret = qlt_init(); 8129 if (ret < 0) { 8130 goto destroy_cache; 8131 } else if (ret > 0) { 8132 /* 8133 * If initiator mode is explictly disabled by qlt_init(), 8134 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8135 * performing scsi_scan_target() during LOOP UP event. 8136 */ 8137 qla2xxx_transport_functions.disable_target_scan = 1; 8138 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8139 } 8140 8141 /* Derive version string. */ 8142 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8143 if (ql2xextended_error_logging) 8144 strcat(qla2x00_version_str, "-debug"); 8145 if (ql2xextended_error_logging == 1) 8146 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8147 8148 qla2xxx_transport_template = 8149 fc_attach_transport(&qla2xxx_transport_functions); 8150 if (!qla2xxx_transport_template) { 8151 ql_log(ql_log_fatal, NULL, 0x0002, 8152 "fc_attach_transport failed...Failing load!.\n"); 8153 ret = -ENODEV; 8154 goto qlt_exit; 8155 } 8156 8157 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8158 if (apidev_major < 0) { 8159 ql_log(ql_log_fatal, NULL, 0x0003, 8160 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8161 } 8162 8163 qla2xxx_transport_vport_template = 8164 fc_attach_transport(&qla2xxx_transport_vport_functions); 8165 if (!qla2xxx_transport_vport_template) { 8166 ql_log(ql_log_fatal, NULL, 0x0004, 8167 "fc_attach_transport vport failed...Failing load!.\n"); 8168 ret = -ENODEV; 8169 goto unreg_chrdev; 8170 } 8171 ql_log(ql_log_info, NULL, 0x0005, 8172 "QLogic Fibre Channel HBA Driver: %s.\n", 8173 qla2x00_version_str); 8174 ret = pci_register_driver(&qla2xxx_pci_driver); 8175 if (ret) { 8176 ql_log(ql_log_fatal, NULL, 0x0006, 8177 "pci_register_driver failed...ret=%d Failing load!.\n", 8178 ret); 8179 goto release_vport_transport; 8180 } 8181 return ret; 8182 8183 release_vport_transport: 8184 fc_release_transport(qla2xxx_transport_vport_template); 8185 8186 unreg_chrdev: 8187 if (apidev_major >= 0) 8188 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8189 fc_release_transport(qla2xxx_transport_template); 8190 8191 qlt_exit: 8192 qlt_exit(); 8193 8194 destroy_cache: 8195 kmem_cache_destroy(srb_cachep); 8196 return ret; 8197 } 8198 8199 /** 8200 * qla2x00_module_exit - Module cleanup. 8201 **/ 8202 static void __exit 8203 qla2x00_module_exit(void) 8204 { 8205 pci_unregister_driver(&qla2xxx_pci_driver); 8206 qla2x00_release_firmware(); 8207 kmem_cache_destroy(ctx_cachep); 8208 fc_release_transport(qla2xxx_transport_vport_template); 8209 if (apidev_major >= 0) 8210 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8211 fc_release_transport(qla2xxx_transport_template); 8212 qlt_exit(); 8213 kmem_cache_destroy(srb_cachep); 8214 } 8215 8216 module_init(qla2x00_module_init); 8217 module_exit(qla2x00_module_exit); 8218 8219 MODULE_AUTHOR("QLogic Corporation"); 8220 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8221 MODULE_LICENSE("GPL"); 8222 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8223 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8224 MODULE_FIRMWARE(FW_FILE_ISP2300); 8225 MODULE_FIRMWARE(FW_FILE_ISP2322); 8226 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8227 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8228