1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101 int ql2xshiftctondsd = 6; 102 module_param(ql2xshiftctondsd, int, S_IRUGO); 103 MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107 int ql2xfdmienable=1; 108 module_param(ql2xfdmienable, int, S_IRUGO); 109 MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113 #define MAX_Q_DEPTH 32 114 static int ql2xmaxqdepth = MAX_Q_DEPTH; 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116 MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120 int ql2xenabledif = 2; 121 module_param(ql2xenabledif, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF:\n" 124 " Default is 2.\n" 125 " 0 -- No DIF Support\n" 126 " 1 -- Enable DIF for all types\n" 127 " 2 -- Enable DIF for all types, except Type 0.\n"); 128 129 int ql2xenablehba_err_chk = 2; 130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xenablehba_err_chk, 132 " Enable T10-CRC-DIF Error isolation by HBA:\n" 133 " Default is 2.\n" 134 " 0 -- Error isolation disabled\n" 135 " 1 -- Error isolation enabled only for DIX Type 0\n" 136 " 2 -- Error isolation enabled for all Types\n"); 137 138 int ql2xiidmaenable=1; 139 module_param(ql2xiidmaenable, int, S_IRUGO); 140 MODULE_PARM_DESC(ql2xiidmaenable, 141 "Enables iIDMA settings " 142 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 143 144 int ql2xmaxqueues = 1; 145 module_param(ql2xmaxqueues, int, S_IRUGO); 146 MODULE_PARM_DESC(ql2xmaxqueues, 147 "Enables MQ settings " 148 "Default is 1 for single queue. Set it to number " 149 "of queues in MQ mode."); 150 151 int ql2xmultique_tag; 152 module_param(ql2xmultique_tag, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xmultique_tag, 154 "Enables CPU affinity settings for the driver " 155 "Default is 0 for no affinity of request and response IO. " 156 "Set it to 1 to turn on the cpu affinity."); 157 158 int ql2xfwloadbin; 159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 160 MODULE_PARM_DESC(ql2xfwloadbin, 161 "Option to specify location from which to load ISP firmware:.\n" 162 " 2 -- load firmware via the request_firmware() (hotplug).\n" 163 " interface.\n" 164 " 1 -- load firmware from flash.\n" 165 " 0 -- use default semantics.\n"); 166 167 int ql2xetsenable; 168 module_param(ql2xetsenable, int, S_IRUGO); 169 MODULE_PARM_DESC(ql2xetsenable, 170 "Enables firmware ETS burst." 171 "Default is 0 - skip ETS enablement."); 172 173 int ql2xdbwr = 1; 174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 175 MODULE_PARM_DESC(ql2xdbwr, 176 "Option to specify scheme for request queue posting.\n" 177 " 0 -- Regular doorbell.\n" 178 " 1 -- CAMRAM doorbell (faster).\n"); 179 180 int ql2xtargetreset = 1; 181 module_param(ql2xtargetreset, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xtargetreset, 183 "Enable target reset." 184 "Default is 1 - use hw defaults."); 185 186 int ql2xgffidenable; 187 module_param(ql2xgffidenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xgffidenable, 189 "Enables GFF_ID checks of port type. " 190 "Default is 0 - Do not use GFF_ID information."); 191 192 int ql2xasynctmfenable; 193 module_param(ql2xasynctmfenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xasynctmfenable, 195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 196 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 197 198 int ql2xdontresethba; 199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdontresethba, 201 "Option to specify reset behaviour.\n" 202 " 0 (Default) -- Reset on failure.\n" 203 " 1 -- Do not reset on failure.\n"); 204 205 uint ql2xmaxlun = MAX_LUNS; 206 module_param(ql2xmaxlun, uint, S_IRUGO); 207 MODULE_PARM_DESC(ql2xmaxlun, 208 "Defines the maximum LU number to register with the SCSI " 209 "midlayer. Default is 65535."); 210 211 int ql2xmdcapmask = 0x1F; 212 module_param(ql2xmdcapmask, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xmdcapmask, 214 "Set the Minidump driver capture mask level. " 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 216 217 int ql2xmdenable = 1; 218 module_param(ql2xmdenable, int, S_IRUGO); 219 MODULE_PARM_DESC(ql2xmdenable, 220 "Enable/disable MiniDump. " 221 "0 - MiniDump disabled. " 222 "1 (Default) - MiniDump enabled."); 223 224 /* 225 * SCSI host template entry points 226 */ 227 static int qla2xxx_slave_configure(struct scsi_device * device); 228 static int qla2xxx_slave_alloc(struct scsi_device *); 229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 230 static void qla2xxx_scan_start(struct Scsi_Host *); 231 static void qla2xxx_slave_destroy(struct scsi_device *); 232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 233 static int qla2xxx_eh_abort(struct scsi_cmnd *); 234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 238 239 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 240 static int qla2x00_change_queue_type(struct scsi_device *, int); 241 static void qla2x00_free_device(scsi_qla_host_t *); 242 243 struct scsi_host_template qla2xxx_driver_template = { 244 .module = THIS_MODULE, 245 .name = QLA2XXX_DRIVER_NAME, 246 .queuecommand = qla2xxx_queuecommand, 247 248 .eh_abort_handler = qla2xxx_eh_abort, 249 .eh_device_reset_handler = qla2xxx_eh_device_reset, 250 .eh_target_reset_handler = qla2xxx_eh_target_reset, 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 252 .eh_host_reset_handler = qla2xxx_eh_host_reset, 253 254 .slave_configure = qla2xxx_slave_configure, 255 256 .slave_alloc = qla2xxx_slave_alloc, 257 .slave_destroy = qla2xxx_slave_destroy, 258 .scan_finished = qla2xxx_scan_finished, 259 .scan_start = qla2xxx_scan_start, 260 .change_queue_depth = qla2x00_change_queue_depth, 261 .change_queue_type = qla2x00_change_queue_type, 262 .this_id = -1, 263 .cmd_per_lun = 3, 264 .use_clustering = ENABLE_CLUSTERING, 265 .sg_tablesize = SG_ALL, 266 267 .max_sectors = 0xFFFF, 268 .shost_attrs = qla2x00_host_attrs, 269 270 .supported_mode = MODE_INITIATOR, 271 }; 272 273 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 274 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 275 276 /* TODO Convert to inlines 277 * 278 * Timer routines 279 */ 280 281 __inline__ void 282 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 283 { 284 init_timer(&vha->timer); 285 vha->timer.expires = jiffies + interval * HZ; 286 vha->timer.data = (unsigned long)vha; 287 vha->timer.function = (void (*)(unsigned long))func; 288 add_timer(&vha->timer); 289 vha->timer_active = 1; 290 } 291 292 static inline void 293 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 294 { 295 /* Currently used for 82XX only. */ 296 if (vha->device_flags & DFLG_DEV_FAILED) { 297 ql_dbg(ql_dbg_timer, vha, 0x600d, 298 "Device in a failed state, returning.\n"); 299 return; 300 } 301 302 mod_timer(&vha->timer, jiffies + interval * HZ); 303 } 304 305 static __inline__ void 306 qla2x00_stop_timer(scsi_qla_host_t *vha) 307 { 308 del_timer_sync(&vha->timer); 309 vha->timer_active = 0; 310 } 311 312 static int qla2x00_do_dpc(void *data); 313 314 static void qla2x00_rst_aen(scsi_qla_host_t *); 315 316 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 317 struct req_que **, struct rsp_que **); 318 static void qla2x00_free_fw_dump(struct qla_hw_data *); 319 static void qla2x00_mem_free(struct qla_hw_data *); 320 321 /* -------------------------------------------------------------------------- */ 322 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 323 struct rsp_que *rsp) 324 { 325 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 326 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 327 GFP_KERNEL); 328 if (!ha->req_q_map) { 329 ql_log(ql_log_fatal, vha, 0x003b, 330 "Unable to allocate memory for request queue ptrs.\n"); 331 goto fail_req_map; 332 } 333 334 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 335 GFP_KERNEL); 336 if (!ha->rsp_q_map) { 337 ql_log(ql_log_fatal, vha, 0x003c, 338 "Unable to allocate memory for response queue ptrs.\n"); 339 goto fail_rsp_map; 340 } 341 /* 342 * Make sure we record at least the request and response queue zero in 343 * case we need to free them if part of the probe fails. 344 */ 345 ha->rsp_q_map[0] = rsp; 346 ha->req_q_map[0] = req; 347 set_bit(0, ha->rsp_qid_map); 348 set_bit(0, ha->req_qid_map); 349 return 1; 350 351 fail_rsp_map: 352 kfree(ha->req_q_map); 353 ha->req_q_map = NULL; 354 fail_req_map: 355 return -ENOMEM; 356 } 357 358 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 359 { 360 if (IS_QLAFX00(ha)) { 361 if (req && req->ring_fx00) 362 dma_free_coherent(&ha->pdev->dev, 363 (req->length_fx00 + 1) * sizeof(request_t), 364 req->ring_fx00, req->dma_fx00); 365 } else if (req && req->ring) 366 dma_free_coherent(&ha->pdev->dev, 367 (req->length + 1) * sizeof(request_t), 368 req->ring, req->dma); 369 370 if (req) 371 kfree(req->outstanding_cmds); 372 373 kfree(req); 374 req = NULL; 375 } 376 377 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 378 { 379 if (IS_QLAFX00(ha)) { 380 if (rsp && rsp->ring) 381 dma_free_coherent(&ha->pdev->dev, 382 (rsp->length_fx00 + 1) * sizeof(request_t), 383 rsp->ring_fx00, rsp->dma_fx00); 384 } else if (rsp && rsp->ring) { 385 dma_free_coherent(&ha->pdev->dev, 386 (rsp->length + 1) * sizeof(response_t), 387 rsp->ring, rsp->dma); 388 } 389 kfree(rsp); 390 rsp = NULL; 391 } 392 393 static void qla2x00_free_queues(struct qla_hw_data *ha) 394 { 395 struct req_que *req; 396 struct rsp_que *rsp; 397 int cnt; 398 399 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 400 req = ha->req_q_map[cnt]; 401 qla2x00_free_req_que(ha, req); 402 } 403 kfree(ha->req_q_map); 404 ha->req_q_map = NULL; 405 406 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 407 rsp = ha->rsp_q_map[cnt]; 408 qla2x00_free_rsp_que(ha, rsp); 409 } 410 kfree(ha->rsp_q_map); 411 ha->rsp_q_map = NULL; 412 } 413 414 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 415 { 416 uint16_t options = 0; 417 int ques, req, ret; 418 struct qla_hw_data *ha = vha->hw; 419 420 if (!(ha->fw_attributes & BIT_6)) { 421 ql_log(ql_log_warn, vha, 0x00d8, 422 "Firmware is not multi-queue capable.\n"); 423 goto fail; 424 } 425 if (ql2xmultique_tag) { 426 /* create a request queue for IO */ 427 options |= BIT_7; 428 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 429 QLA_DEFAULT_QUE_QOS); 430 if (!req) { 431 ql_log(ql_log_warn, vha, 0x00e0, 432 "Failed to create request queue.\n"); 433 goto fail; 434 } 435 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 436 vha->req = ha->req_q_map[req]; 437 options |= BIT_1; 438 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 439 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 440 if (!ret) { 441 ql_log(ql_log_warn, vha, 0x00e8, 442 "Failed to create response queue.\n"); 443 goto fail2; 444 } 445 } 446 ha->flags.cpu_affinity_enabled = 1; 447 ql_dbg(ql_dbg_multiq, vha, 0xc007, 448 "CPU affinity mode enalbed, " 449 "no. of response queues:%d no. of request queues:%d.\n", 450 ha->max_rsp_queues, ha->max_req_queues); 451 ql_dbg(ql_dbg_init, vha, 0x00e9, 452 "CPU affinity mode enalbed, " 453 "no. of response queues:%d no. of request queues:%d.\n", 454 ha->max_rsp_queues, ha->max_req_queues); 455 } 456 return 0; 457 fail2: 458 qla25xx_delete_queues(vha); 459 destroy_workqueue(ha->wq); 460 ha->wq = NULL; 461 vha->req = ha->req_q_map[0]; 462 fail: 463 ha->mqenable = 0; 464 kfree(ha->req_q_map); 465 kfree(ha->rsp_q_map); 466 ha->max_req_queues = ha->max_rsp_queues = 1; 467 return 1; 468 } 469 470 static char * 471 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 472 { 473 struct qla_hw_data *ha = vha->hw; 474 static char *pci_bus_modes[] = { 475 "33", "66", "100", "133", 476 }; 477 uint16_t pci_bus; 478 479 strcpy(str, "PCI"); 480 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 481 if (pci_bus) { 482 strcat(str, "-X ("); 483 strcat(str, pci_bus_modes[pci_bus]); 484 } else { 485 pci_bus = (ha->pci_attr & BIT_8) >> 8; 486 strcat(str, " ("); 487 strcat(str, pci_bus_modes[pci_bus]); 488 } 489 strcat(str, " MHz)"); 490 491 return (str); 492 } 493 494 static char * 495 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 496 { 497 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 498 struct qla_hw_data *ha = vha->hw; 499 uint32_t pci_bus; 500 501 if (pci_is_pcie(ha->pdev)) { 502 char lwstr[6]; 503 uint32_t lstat, lspeed, lwidth; 504 505 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 506 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 507 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 508 509 strcpy(str, "PCIe ("); 510 switch (lspeed) { 511 case 1: 512 strcat(str, "2.5GT/s "); 513 break; 514 case 2: 515 strcat(str, "5.0GT/s "); 516 break; 517 case 3: 518 strcat(str, "8.0GT/s "); 519 break; 520 default: 521 strcat(str, "<unknown> "); 522 break; 523 } 524 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 525 strcat(str, lwstr); 526 527 return str; 528 } 529 530 strcpy(str, "PCI"); 531 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 532 if (pci_bus == 0 || pci_bus == 8) { 533 strcat(str, " ("); 534 strcat(str, pci_bus_modes[pci_bus >> 3]); 535 } else { 536 strcat(str, "-X "); 537 if (pci_bus & BIT_2) 538 strcat(str, "Mode 2"); 539 else 540 strcat(str, "Mode 1"); 541 strcat(str, " ("); 542 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 543 } 544 strcat(str, " MHz)"); 545 546 return str; 547 } 548 549 static char * 550 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 551 { 552 char un_str[10]; 553 struct qla_hw_data *ha = vha->hw; 554 555 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 556 ha->fw_minor_version, 557 ha->fw_subminor_version); 558 559 if (ha->fw_attributes & BIT_9) { 560 strcat(str, "FLX"); 561 return (str); 562 } 563 564 switch (ha->fw_attributes & 0xFF) { 565 case 0x7: 566 strcat(str, "EF"); 567 break; 568 case 0x17: 569 strcat(str, "TP"); 570 break; 571 case 0x37: 572 strcat(str, "IP"); 573 break; 574 case 0x77: 575 strcat(str, "VI"); 576 break; 577 default: 578 sprintf(un_str, "(%x)", ha->fw_attributes); 579 strcat(str, un_str); 580 break; 581 } 582 if (ha->fw_attributes & 0x100) 583 strcat(str, "X"); 584 585 return (str); 586 } 587 588 static char * 589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 590 { 591 struct qla_hw_data *ha = vha->hw; 592 593 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 595 return str; 596 } 597 598 void 599 qla2x00_sp_free_dma(void *vha, void *ptr) 600 { 601 srb_t *sp = (srb_t *)ptr; 602 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 603 struct qla_hw_data *ha = sp->fcport->vha->hw; 604 void *ctx = GET_CMD_CTX_SP(sp); 605 606 if (sp->flags & SRB_DMA_VALID) { 607 scsi_dma_unmap(cmd); 608 sp->flags &= ~SRB_DMA_VALID; 609 } 610 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 613 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 615 } 616 617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 618 /* List assured to be having elements */ 619 qla2x00_clean_dsd_pool(ha, sp); 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 621 } 622 623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 624 dma_pool_free(ha->dl_dma_pool, ctx, 625 ((struct crc_context *)ctx)->crc_ctx_dma); 626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 627 } 628 629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 631 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 633 ctx1->fcp_cmnd_dma); 634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 637 mempool_free(ctx1, ha->ctx_mempool); 638 ctx1 = NULL; 639 } 640 641 CMD_SP(cmd) = NULL; 642 qla2x00_rel_sp(sp->fcport->vha, sp); 643 } 644 645 static void 646 qla2x00_sp_compl(void *data, void *ptr, int res) 647 { 648 struct qla_hw_data *ha = (struct qla_hw_data *)data; 649 srb_t *sp = (srb_t *)ptr; 650 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 651 652 cmd->result = res; 653 654 if (atomic_read(&sp->ref_count) == 0) { 655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 657 sp, GET_CMD_SP(sp)); 658 if (ql2xextended_error_logging & ql_dbg_io) 659 BUG(); 660 return; 661 } 662 if (!atomic_dec_and_test(&sp->ref_count)) 663 return; 664 665 qla2x00_sp_free_dma(ha, sp); 666 cmd->scsi_done(cmd); 667 } 668 669 /* If we are SP1 here, we need to still take and release the host_lock as SP1 670 * does not have the changes necessary to avoid taking host->host_lock. 671 */ 672 static int 673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 674 { 675 scsi_qla_host_t *vha = shost_priv(host); 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 678 struct qla_hw_data *ha = vha->hw; 679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 680 srb_t *sp; 681 int rval; 682 683 if (ha->flags.eeh_busy) { 684 if (ha->flags.pci_channel_io_perm_failure) { 685 ql_dbg(ql_dbg_aer, vha, 0x9010, 686 "PCI Channel IO permanent failure, exiting " 687 "cmd=%p.\n", cmd); 688 cmd->result = DID_NO_CONNECT << 16; 689 } else { 690 ql_dbg(ql_dbg_aer, vha, 0x9011, 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 692 cmd->result = DID_REQUEUE << 16; 693 } 694 goto qc24_fail_command; 695 } 696 697 rval = fc_remote_port_chkready(rport); 698 if (rval) { 699 cmd->result = rval; 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 702 cmd, rval); 703 goto qc24_fail_command; 704 } 705 706 if (!vha->flags.difdix_supported && 707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 708 ql_dbg(ql_dbg_io, vha, 0x3004, 709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 710 cmd); 711 cmd->result = DID_NO_CONNECT << 16; 712 goto qc24_fail_command; 713 } 714 715 if (!fcport) { 716 cmd->result = DID_NO_CONNECT << 16; 717 goto qc24_fail_command; 718 } 719 720 if (atomic_read(&fcport->state) != FCS_ONLINE) { 721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 723 ql_dbg(ql_dbg_io, vha, 0x3005, 724 "Returning DNC, fcport_state=%d loop_state=%d.\n", 725 atomic_read(&fcport->state), 726 atomic_read(&base_vha->loop_state)); 727 cmd->result = DID_NO_CONNECT << 16; 728 goto qc24_fail_command; 729 } 730 goto qc24_target_busy; 731 } 732 733 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 734 if (!sp) 735 goto qc24_host_busy; 736 737 sp->u.scmd.cmd = cmd; 738 sp->type = SRB_SCSI_CMD; 739 atomic_set(&sp->ref_count, 1); 740 CMD_SP(cmd) = (void *)sp; 741 sp->free = qla2x00_sp_free_dma; 742 sp->done = qla2x00_sp_compl; 743 744 rval = ha->isp_ops->start_scsi(sp); 745 if (rval != QLA_SUCCESS) { 746 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 747 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 748 goto qc24_host_busy_free_sp; 749 } 750 751 return 0; 752 753 qc24_host_busy_free_sp: 754 qla2x00_sp_free_dma(ha, sp); 755 756 qc24_host_busy: 757 return SCSI_MLQUEUE_HOST_BUSY; 758 759 qc24_target_busy: 760 return SCSI_MLQUEUE_TARGET_BUSY; 761 762 qc24_fail_command: 763 cmd->scsi_done(cmd); 764 765 return 0; 766 } 767 768 /* 769 * qla2x00_eh_wait_on_command 770 * Waits for the command to be returned by the Firmware for some 771 * max time. 772 * 773 * Input: 774 * cmd = Scsi Command to wait on. 775 * 776 * Return: 777 * Not Found : 0 778 * Found : 1 779 */ 780 static int 781 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 782 { 783 #define ABORT_POLLING_PERIOD 1000 784 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 785 unsigned long wait_iter = ABORT_WAIT_ITER; 786 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 787 struct qla_hw_data *ha = vha->hw; 788 int ret = QLA_SUCCESS; 789 790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 791 ql_dbg(ql_dbg_taskm, vha, 0x8005, 792 "Return:eh_wait.\n"); 793 return ret; 794 } 795 796 while (CMD_SP(cmd) && wait_iter--) { 797 msleep(ABORT_POLLING_PERIOD); 798 } 799 if (CMD_SP(cmd)) 800 ret = QLA_FUNCTION_FAILED; 801 802 return ret; 803 } 804 805 /* 806 * qla2x00_wait_for_hba_online 807 * Wait till the HBA is online after going through 808 * <= MAX_RETRIES_OF_ISP_ABORT or 809 * finally HBA is disabled ie marked offline 810 * 811 * Input: 812 * ha - pointer to host adapter structure 813 * 814 * Note: 815 * Does context switching-Release SPIN_LOCK 816 * (if any) before calling this routine. 817 * 818 * Return: 819 * Success (Adapter is online) : 0 820 * Failed (Adapter is offline/disabled) : 1 821 */ 822 int 823 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 824 { 825 int return_status; 826 unsigned long wait_online; 827 struct qla_hw_data *ha = vha->hw; 828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 829 830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 834 ha->dpc_active) && time_before(jiffies, wait_online)) { 835 836 msleep(1000); 837 } 838 if (base_vha->flags.online) 839 return_status = QLA_SUCCESS; 840 else 841 return_status = QLA_FUNCTION_FAILED; 842 843 return (return_status); 844 } 845 846 /* 847 * qla2x00_wait_for_reset_ready 848 * Wait till the HBA is online after going through 849 * <= MAX_RETRIES_OF_ISP_ABORT or 850 * finally HBA is disabled ie marked offline or flash 851 * operations are in progress. 852 * 853 * Input: 854 * ha - pointer to host adapter structure 855 * 856 * Note: 857 * Does context switching-Release SPIN_LOCK 858 * (if any) before calling this routine. 859 * 860 * Return: 861 * Success (Adapter is online/no flash ops) : 0 862 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 863 */ 864 static int 865 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 866 { 867 int return_status; 868 unsigned long wait_online; 869 struct qla_hw_data *ha = vha->hw; 870 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 871 872 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 873 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 874 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 875 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 876 ha->optrom_state != QLA_SWAITING || 877 ha->dpc_active) && time_before(jiffies, wait_online)) 878 msleep(1000); 879 880 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 881 return_status = QLA_SUCCESS; 882 else 883 return_status = QLA_FUNCTION_FAILED; 884 885 ql_dbg(ql_dbg_taskm, vha, 0x8019, 886 "%s return status=%d.\n", __func__, return_status); 887 888 return return_status; 889 } 890 891 int 892 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 893 { 894 int return_status; 895 unsigned long wait_reset; 896 struct qla_hw_data *ha = vha->hw; 897 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 898 899 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 900 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 901 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 902 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 903 ha->dpc_active) && time_before(jiffies, wait_reset)) { 904 905 msleep(1000); 906 907 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 908 ha->flags.chip_reset_done) 909 break; 910 } 911 if (ha->flags.chip_reset_done) 912 return_status = QLA_SUCCESS; 913 else 914 return_status = QLA_FUNCTION_FAILED; 915 916 return return_status; 917 } 918 919 static void 920 sp_get(struct srb *sp) 921 { 922 atomic_inc(&sp->ref_count); 923 } 924 925 /************************************************************************** 926 * qla2xxx_eh_abort 927 * 928 * Description: 929 * The abort function will abort the specified command. 930 * 931 * Input: 932 * cmd = Linux SCSI command packet to be aborted. 933 * 934 * Returns: 935 * Either SUCCESS or FAILED. 936 * 937 * Note: 938 * Only return FAILED if command not returned by firmware. 939 **************************************************************************/ 940 static int 941 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 942 { 943 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 944 srb_t *sp; 945 int ret; 946 unsigned int id, lun; 947 unsigned long flags; 948 int wait = 0; 949 struct qla_hw_data *ha = vha->hw; 950 951 if (!CMD_SP(cmd)) 952 return SUCCESS; 953 954 ret = fc_block_scsi_eh(cmd); 955 if (ret != 0) 956 return ret; 957 ret = SUCCESS; 958 959 id = cmd->device->id; 960 lun = cmd->device->lun; 961 962 spin_lock_irqsave(&ha->hardware_lock, flags); 963 sp = (srb_t *) CMD_SP(cmd); 964 if (!sp) { 965 spin_unlock_irqrestore(&ha->hardware_lock, flags); 966 return SUCCESS; 967 } 968 969 ql_dbg(ql_dbg_taskm, vha, 0x8002, 970 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", 971 vha->host_no, id, lun, sp, cmd); 972 973 /* Get a reference to the sp and drop the lock.*/ 974 sp_get(sp); 975 976 spin_unlock_irqrestore(&ha->hardware_lock, flags); 977 if (ha->isp_ops->abort_command(sp)) { 978 ret = FAILED; 979 ql_dbg(ql_dbg_taskm, vha, 0x8003, 980 "Abort command mbx failed cmd=%p.\n", cmd); 981 } else { 982 ql_dbg(ql_dbg_taskm, vha, 0x8004, 983 "Abort command mbx success cmd=%p.\n", cmd); 984 wait = 1; 985 } 986 987 spin_lock_irqsave(&ha->hardware_lock, flags); 988 sp->done(ha, sp, 0); 989 spin_unlock_irqrestore(&ha->hardware_lock, flags); 990 991 /* Did the command return during mailbox execution? */ 992 if (ret == FAILED && !CMD_SP(cmd)) 993 ret = SUCCESS; 994 995 /* Wait for the command to be returned. */ 996 if (wait) { 997 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 998 ql_log(ql_log_warn, vha, 0x8006, 999 "Abort handler timed out cmd=%p.\n", cmd); 1000 ret = FAILED; 1001 } 1002 } 1003 1004 ql_log(ql_log_info, vha, 0x801c, 1005 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", 1006 vha->host_no, id, lun, wait, ret); 1007 1008 return ret; 1009 } 1010 1011 int 1012 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1013 unsigned int l, enum nexus_wait_type type) 1014 { 1015 int cnt, match, status; 1016 unsigned long flags; 1017 struct qla_hw_data *ha = vha->hw; 1018 struct req_que *req; 1019 srb_t *sp; 1020 struct scsi_cmnd *cmd; 1021 1022 status = QLA_SUCCESS; 1023 1024 spin_lock_irqsave(&ha->hardware_lock, flags); 1025 req = vha->req; 1026 for (cnt = 1; status == QLA_SUCCESS && 1027 cnt < req->num_outstanding_cmds; cnt++) { 1028 sp = req->outstanding_cmds[cnt]; 1029 if (!sp) 1030 continue; 1031 if (sp->type != SRB_SCSI_CMD) 1032 continue; 1033 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1034 continue; 1035 match = 0; 1036 cmd = GET_CMD_SP(sp); 1037 switch (type) { 1038 case WAIT_HOST: 1039 match = 1; 1040 break; 1041 case WAIT_TARGET: 1042 match = cmd->device->id == t; 1043 break; 1044 case WAIT_LUN: 1045 match = (cmd->device->id == t && 1046 cmd->device->lun == l); 1047 break; 1048 } 1049 if (!match) 1050 continue; 1051 1052 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1053 status = qla2x00_eh_wait_on_command(cmd); 1054 spin_lock_irqsave(&ha->hardware_lock, flags); 1055 } 1056 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1057 1058 return status; 1059 } 1060 1061 static char *reset_errors[] = { 1062 "HBA not online", 1063 "HBA not ready", 1064 "Task management failed", 1065 "Waiting for command completions", 1066 }; 1067 1068 static int 1069 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1070 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 1071 { 1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1073 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1074 int err; 1075 1076 if (!fcport) { 1077 return FAILED; 1078 } 1079 1080 err = fc_block_scsi_eh(cmd); 1081 if (err != 0) 1082 return err; 1083 1084 ql_log(ql_log_info, vha, 0x8009, 1085 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, 1086 cmd->device->id, cmd->device->lun, cmd); 1087 1088 err = 0; 1089 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1090 ql_log(ql_log_warn, vha, 0x800a, 1091 "Wait for hba online failed for cmd=%p.\n", cmd); 1092 goto eh_reset_failed; 1093 } 1094 err = 2; 1095 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1096 != QLA_SUCCESS) { 1097 ql_log(ql_log_warn, vha, 0x800c, 1098 "do_reset failed for cmd=%p.\n", cmd); 1099 goto eh_reset_failed; 1100 } 1101 err = 3; 1102 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1103 cmd->device->lun, type) != QLA_SUCCESS) { 1104 ql_log(ql_log_warn, vha, 0x800d, 1105 "wait for pending cmds failed for cmd=%p.\n", cmd); 1106 goto eh_reset_failed; 1107 } 1108 1109 ql_log(ql_log_info, vha, 0x800e, 1110 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, 1111 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1112 1113 return SUCCESS; 1114 1115 eh_reset_failed: 1116 ql_log(ql_log_info, vha, 0x800f, 1117 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, 1118 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1119 cmd); 1120 return FAILED; 1121 } 1122 1123 static int 1124 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1125 { 1126 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1127 struct qla_hw_data *ha = vha->hw; 1128 1129 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1130 ha->isp_ops->lun_reset); 1131 } 1132 1133 static int 1134 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1135 { 1136 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1137 struct qla_hw_data *ha = vha->hw; 1138 1139 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1140 ha->isp_ops->target_reset); 1141 } 1142 1143 /************************************************************************** 1144 * qla2xxx_eh_bus_reset 1145 * 1146 * Description: 1147 * The bus reset function will reset the bus and abort any executing 1148 * commands. 1149 * 1150 * Input: 1151 * cmd = Linux SCSI command packet of the command that cause the 1152 * bus reset. 1153 * 1154 * Returns: 1155 * SUCCESS/FAILURE (defined as macro in scsi.h). 1156 * 1157 **************************************************************************/ 1158 static int 1159 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1160 { 1161 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1162 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1163 int ret = FAILED; 1164 unsigned int id, lun; 1165 1166 id = cmd->device->id; 1167 lun = cmd->device->lun; 1168 1169 if (!fcport) { 1170 return ret; 1171 } 1172 1173 ret = fc_block_scsi_eh(cmd); 1174 if (ret != 0) 1175 return ret; 1176 ret = FAILED; 1177 1178 ql_log(ql_log_info, vha, 0x8012, 1179 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1180 1181 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1182 ql_log(ql_log_fatal, vha, 0x8013, 1183 "Wait for hba online failed board disabled.\n"); 1184 goto eh_bus_reset_done; 1185 } 1186 1187 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1188 ret = SUCCESS; 1189 1190 if (ret == FAILED) 1191 goto eh_bus_reset_done; 1192 1193 /* Flush outstanding commands. */ 1194 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1195 QLA_SUCCESS) { 1196 ql_log(ql_log_warn, vha, 0x8014, 1197 "Wait for pending commands failed.\n"); 1198 ret = FAILED; 1199 } 1200 1201 eh_bus_reset_done: 1202 ql_log(ql_log_warn, vha, 0x802b, 1203 "BUS RESET %s nexus=%ld:%d:%d.\n", 1204 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1205 1206 return ret; 1207 } 1208 1209 /************************************************************************** 1210 * qla2xxx_eh_host_reset 1211 * 1212 * Description: 1213 * The reset function will reset the Adapter. 1214 * 1215 * Input: 1216 * cmd = Linux SCSI command packet of the command that cause the 1217 * adapter reset. 1218 * 1219 * Returns: 1220 * Either SUCCESS or FAILED. 1221 * 1222 * Note: 1223 **************************************************************************/ 1224 static int 1225 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1226 { 1227 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1228 struct qla_hw_data *ha = vha->hw; 1229 int ret = FAILED; 1230 unsigned int id, lun; 1231 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1232 1233 id = cmd->device->id; 1234 lun = cmd->device->lun; 1235 1236 ql_log(ql_log_info, vha, 0x8018, 1237 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1238 1239 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1240 goto eh_host_reset_lock; 1241 1242 if (vha != base_vha) { 1243 if (qla2x00_vp_abort_isp(vha)) 1244 goto eh_host_reset_lock; 1245 } else { 1246 if (IS_P3P_TYPE(vha->hw)) { 1247 if (!qla82xx_fcoe_ctx_reset(vha)) { 1248 /* Ctx reset success */ 1249 ret = SUCCESS; 1250 goto eh_host_reset_lock; 1251 } 1252 /* fall thru if ctx reset failed */ 1253 } 1254 if (ha->wq) 1255 flush_workqueue(ha->wq); 1256 1257 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1258 if (ha->isp_ops->abort_isp(base_vha)) { 1259 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1260 /* failed. schedule dpc to try */ 1261 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1262 1263 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1264 ql_log(ql_log_warn, vha, 0x802a, 1265 "wait for hba online failed.\n"); 1266 goto eh_host_reset_lock; 1267 } 1268 } 1269 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1270 } 1271 1272 /* Waiting for command to be returned to OS.*/ 1273 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1274 QLA_SUCCESS) 1275 ret = SUCCESS; 1276 1277 eh_host_reset_lock: 1278 ql_log(ql_log_info, vha, 0x8017, 1279 "ADAPTER RESET %s nexus=%ld:%d:%d.\n", 1280 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1281 1282 return ret; 1283 } 1284 1285 /* 1286 * qla2x00_loop_reset 1287 * Issue loop reset. 1288 * 1289 * Input: 1290 * ha = adapter block pointer. 1291 * 1292 * Returns: 1293 * 0 = success 1294 */ 1295 int 1296 qla2x00_loop_reset(scsi_qla_host_t *vha) 1297 { 1298 int ret; 1299 struct fc_port *fcport; 1300 struct qla_hw_data *ha = vha->hw; 1301 1302 if (IS_QLAFX00(ha)) { 1303 return qlafx00_loop_reset(vha); 1304 } 1305 1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1307 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1308 if (fcport->port_type != FCT_TARGET) 1309 continue; 1310 1311 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1312 if (ret != QLA_SUCCESS) { 1313 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1314 "Bus Reset failed: Reset=%d " 1315 "d_id=%x.\n", ret, fcport->d_id.b24); 1316 } 1317 } 1318 } 1319 1320 1321 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1322 atomic_set(&vha->loop_state, LOOP_DOWN); 1323 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1324 qla2x00_mark_all_devices_lost(vha, 0); 1325 ret = qla2x00_full_login_lip(vha); 1326 if (ret != QLA_SUCCESS) { 1327 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1328 "full_login_lip=%d.\n", ret); 1329 } 1330 } 1331 1332 if (ha->flags.enable_lip_reset) { 1333 ret = qla2x00_lip_reset(vha); 1334 if (ret != QLA_SUCCESS) 1335 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1336 "lip_reset failed (%d).\n", ret); 1337 } 1338 1339 /* Issue marker command only when we are going to start the I/O */ 1340 vha->marker_needed = 1; 1341 1342 return QLA_SUCCESS; 1343 } 1344 1345 void 1346 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1347 { 1348 int que, cnt; 1349 unsigned long flags; 1350 srb_t *sp; 1351 struct qla_hw_data *ha = vha->hw; 1352 struct req_que *req; 1353 1354 spin_lock_irqsave(&ha->hardware_lock, flags); 1355 for (que = 0; que < ha->max_req_queues; que++) { 1356 req = ha->req_q_map[que]; 1357 if (!req) 1358 continue; 1359 if (!req->outstanding_cmds) 1360 continue; 1361 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1362 sp = req->outstanding_cmds[cnt]; 1363 if (sp) { 1364 req->outstanding_cmds[cnt] = NULL; 1365 sp->done(vha, sp, res); 1366 } 1367 } 1368 } 1369 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1370 } 1371 1372 static int 1373 qla2xxx_slave_alloc(struct scsi_device *sdev) 1374 { 1375 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1376 1377 if (!rport || fc_remote_port_chkready(rport)) 1378 return -ENXIO; 1379 1380 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1381 1382 return 0; 1383 } 1384 1385 static int 1386 qla2xxx_slave_configure(struct scsi_device *sdev) 1387 { 1388 scsi_qla_host_t *vha = shost_priv(sdev->host); 1389 struct req_que *req = vha->req; 1390 1391 if (IS_T10_PI_CAPABLE(vha->hw)) 1392 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1393 1394 if (sdev->tagged_supported) 1395 scsi_activate_tcq(sdev, req->max_q_depth); 1396 else 1397 scsi_deactivate_tcq(sdev, req->max_q_depth); 1398 return 0; 1399 } 1400 1401 static void 1402 qla2xxx_slave_destroy(struct scsi_device *sdev) 1403 { 1404 sdev->hostdata = NULL; 1405 } 1406 1407 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1408 { 1409 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1410 1411 if (!scsi_track_queue_full(sdev, qdepth)) 1412 return; 1413 1414 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1415 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", 1416 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1417 } 1418 1419 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1420 { 1421 fc_port_t *fcport = sdev->hostdata; 1422 struct scsi_qla_host *vha = fcport->vha; 1423 struct req_que *req = NULL; 1424 1425 req = vha->req; 1426 if (!req) 1427 return; 1428 1429 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1430 return; 1431 1432 if (sdev->ordered_tags) 1433 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1434 else 1435 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1436 1437 ql_dbg(ql_dbg_io, vha, 0x302a, 1438 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", 1439 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1440 } 1441 1442 static int 1443 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1444 { 1445 switch (reason) { 1446 case SCSI_QDEPTH_DEFAULT: 1447 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1448 break; 1449 case SCSI_QDEPTH_QFULL: 1450 qla2x00_handle_queue_full(sdev, qdepth); 1451 break; 1452 case SCSI_QDEPTH_RAMP_UP: 1453 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1454 break; 1455 default: 1456 return -EOPNOTSUPP; 1457 } 1458 1459 return sdev->queue_depth; 1460 } 1461 1462 static int 1463 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1464 { 1465 if (sdev->tagged_supported) { 1466 scsi_set_tag_type(sdev, tag_type); 1467 if (tag_type) 1468 scsi_activate_tcq(sdev, sdev->queue_depth); 1469 else 1470 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1471 } else 1472 tag_type = 0; 1473 1474 return tag_type; 1475 } 1476 1477 /** 1478 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1479 * @ha: HA context 1480 * 1481 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1482 * supported addressing method. 1483 */ 1484 static void 1485 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1486 { 1487 /* Assume a 32bit DMA mask. */ 1488 ha->flags.enable_64bit_addressing = 0; 1489 1490 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1491 /* Any upper-dword bits set? */ 1492 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1493 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1494 /* Ok, a 64bit DMA mask is applicable. */ 1495 ha->flags.enable_64bit_addressing = 1; 1496 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1497 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1498 return; 1499 } 1500 } 1501 1502 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1503 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1504 } 1505 1506 static void 1507 qla2x00_enable_intrs(struct qla_hw_data *ha) 1508 { 1509 unsigned long flags = 0; 1510 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1511 1512 spin_lock_irqsave(&ha->hardware_lock, flags); 1513 ha->interrupts_on = 1; 1514 /* enable risc and host interrupts */ 1515 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1516 RD_REG_WORD(®->ictrl); 1517 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1518 1519 } 1520 1521 static void 1522 qla2x00_disable_intrs(struct qla_hw_data *ha) 1523 { 1524 unsigned long flags = 0; 1525 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1526 1527 spin_lock_irqsave(&ha->hardware_lock, flags); 1528 ha->interrupts_on = 0; 1529 /* disable risc and host interrupts */ 1530 WRT_REG_WORD(®->ictrl, 0); 1531 RD_REG_WORD(®->ictrl); 1532 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1533 } 1534 1535 static void 1536 qla24xx_enable_intrs(struct qla_hw_data *ha) 1537 { 1538 unsigned long flags = 0; 1539 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1540 1541 spin_lock_irqsave(&ha->hardware_lock, flags); 1542 ha->interrupts_on = 1; 1543 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1544 RD_REG_DWORD(®->ictrl); 1545 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1546 } 1547 1548 static void 1549 qla24xx_disable_intrs(struct qla_hw_data *ha) 1550 { 1551 unsigned long flags = 0; 1552 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1553 1554 if (IS_NOPOLLING_TYPE(ha)) 1555 return; 1556 spin_lock_irqsave(&ha->hardware_lock, flags); 1557 ha->interrupts_on = 0; 1558 WRT_REG_DWORD(®->ictrl, 0); 1559 RD_REG_DWORD(®->ictrl); 1560 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1561 } 1562 1563 static int 1564 qla2x00_iospace_config(struct qla_hw_data *ha) 1565 { 1566 resource_size_t pio; 1567 uint16_t msix; 1568 int cpus; 1569 1570 if (pci_request_selected_regions(ha->pdev, ha->bars, 1571 QLA2XXX_DRIVER_NAME)) { 1572 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1573 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1574 pci_name(ha->pdev)); 1575 goto iospace_error_exit; 1576 } 1577 if (!(ha->bars & 1)) 1578 goto skip_pio; 1579 1580 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1581 pio = pci_resource_start(ha->pdev, 0); 1582 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1583 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1584 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1585 "Invalid pci I/O region size (%s).\n", 1586 pci_name(ha->pdev)); 1587 pio = 0; 1588 } 1589 } else { 1590 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1591 "Region #0 no a PIO resource (%s).\n", 1592 pci_name(ha->pdev)); 1593 pio = 0; 1594 } 1595 ha->pio_address = pio; 1596 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1597 "PIO address=%llu.\n", 1598 (unsigned long long)ha->pio_address); 1599 1600 skip_pio: 1601 /* Use MMIO operations for all accesses. */ 1602 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1603 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1604 "Region #1 not an MMIO resource (%s), aborting.\n", 1605 pci_name(ha->pdev)); 1606 goto iospace_error_exit; 1607 } 1608 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1609 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1610 "Invalid PCI mem region size (%s), aborting.\n", 1611 pci_name(ha->pdev)); 1612 goto iospace_error_exit; 1613 } 1614 1615 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1616 if (!ha->iobase) { 1617 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1618 "Cannot remap MMIO (%s), aborting.\n", 1619 pci_name(ha->pdev)); 1620 goto iospace_error_exit; 1621 } 1622 1623 /* Determine queue resources */ 1624 ha->max_req_queues = ha->max_rsp_queues = 1; 1625 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1626 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1627 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1628 goto mqiobase_exit; 1629 1630 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1631 pci_resource_len(ha->pdev, 3)); 1632 if (ha->mqiobase) { 1633 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1634 "MQIO Base=%p.\n", ha->mqiobase); 1635 /* Read MSIX vector size of the board */ 1636 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1637 ha->msix_count = msix; 1638 /* Max queues are bounded by available msix vectors */ 1639 /* queue 0 uses two msix vectors */ 1640 if (ql2xmultique_tag) { 1641 cpus = num_online_cpus(); 1642 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1643 (cpus + 1) : (ha->msix_count - 1); 1644 ha->max_req_queues = 2; 1645 } else if (ql2xmaxqueues > 1) { 1646 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1647 QLA_MQ_SIZE : ql2xmaxqueues; 1648 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1649 "QoS mode set, max no of request queues:%d.\n", 1650 ha->max_req_queues); 1651 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1652 "QoS mode set, max no of request queues:%d.\n", 1653 ha->max_req_queues); 1654 } 1655 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1656 "MSI-X vector count: %d.\n", msix); 1657 } else 1658 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1659 "BAR 3 not enabled.\n"); 1660 1661 mqiobase_exit: 1662 ha->msix_count = ha->max_rsp_queues + 1; 1663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1664 "MSIX Count:%d.\n", ha->msix_count); 1665 return (0); 1666 1667 iospace_error_exit: 1668 return (-ENOMEM); 1669 } 1670 1671 1672 static int 1673 qla83xx_iospace_config(struct qla_hw_data *ha) 1674 { 1675 uint16_t msix; 1676 int cpus; 1677 1678 if (pci_request_selected_regions(ha->pdev, ha->bars, 1679 QLA2XXX_DRIVER_NAME)) { 1680 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1681 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1682 pci_name(ha->pdev)); 1683 1684 goto iospace_error_exit; 1685 } 1686 1687 /* Use MMIO operations for all accesses. */ 1688 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1689 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1690 "Invalid pci I/O region size (%s).\n", 1691 pci_name(ha->pdev)); 1692 goto iospace_error_exit; 1693 } 1694 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1695 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1696 "Invalid PCI mem region size (%s), aborting\n", 1697 pci_name(ha->pdev)); 1698 goto iospace_error_exit; 1699 } 1700 1701 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1702 if (!ha->iobase) { 1703 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1704 "Cannot remap MMIO (%s), aborting.\n", 1705 pci_name(ha->pdev)); 1706 goto iospace_error_exit; 1707 } 1708 1709 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1710 /* 83XX 26XX always use MQ type access for queues 1711 * - mbar 2, a.k.a region 4 */ 1712 ha->max_req_queues = ha->max_rsp_queues = 1; 1713 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1714 pci_resource_len(ha->pdev, 4)); 1715 1716 if (!ha->mqiobase) { 1717 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1718 "BAR2/region4 not enabled\n"); 1719 goto mqiobase_exit; 1720 } 1721 1722 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1723 pci_resource_len(ha->pdev, 2)); 1724 if (ha->msixbase) { 1725 /* Read MSIX vector size of the board */ 1726 pci_read_config_word(ha->pdev, 1727 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1728 ha->msix_count = msix; 1729 /* Max queues are bounded by available msix vectors */ 1730 /* queue 0 uses two msix vectors */ 1731 if (ql2xmultique_tag) { 1732 cpus = num_online_cpus(); 1733 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1734 (cpus + 1) : (ha->msix_count - 1); 1735 ha->max_req_queues = 2; 1736 } else if (ql2xmaxqueues > 1) { 1737 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1738 QLA_MQ_SIZE : ql2xmaxqueues; 1739 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1740 "QoS mode set, max no of request queues:%d.\n", 1741 ha->max_req_queues); 1742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1743 "QoS mode set, max no of request queues:%d.\n", 1744 ha->max_req_queues); 1745 } 1746 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1747 "MSI-X vector count: %d.\n", msix); 1748 } else 1749 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1750 "BAR 1 not enabled.\n"); 1751 1752 mqiobase_exit: 1753 ha->msix_count = ha->max_rsp_queues + 1; 1754 1755 qlt_83xx_iospace_config(ha); 1756 1757 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1758 "MSIX Count:%d.\n", ha->msix_count); 1759 return 0; 1760 1761 iospace_error_exit: 1762 return -ENOMEM; 1763 } 1764 1765 static struct isp_operations qla2100_isp_ops = { 1766 .pci_config = qla2100_pci_config, 1767 .reset_chip = qla2x00_reset_chip, 1768 .chip_diag = qla2x00_chip_diag, 1769 .config_rings = qla2x00_config_rings, 1770 .reset_adapter = qla2x00_reset_adapter, 1771 .nvram_config = qla2x00_nvram_config, 1772 .update_fw_options = qla2x00_update_fw_options, 1773 .load_risc = qla2x00_load_risc, 1774 .pci_info_str = qla2x00_pci_info_str, 1775 .fw_version_str = qla2x00_fw_version_str, 1776 .intr_handler = qla2100_intr_handler, 1777 .enable_intrs = qla2x00_enable_intrs, 1778 .disable_intrs = qla2x00_disable_intrs, 1779 .abort_command = qla2x00_abort_command, 1780 .target_reset = qla2x00_abort_target, 1781 .lun_reset = qla2x00_lun_reset, 1782 .fabric_login = qla2x00_login_fabric, 1783 .fabric_logout = qla2x00_fabric_logout, 1784 .calc_req_entries = qla2x00_calc_iocbs_32, 1785 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1786 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1787 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1788 .read_nvram = qla2x00_read_nvram_data, 1789 .write_nvram = qla2x00_write_nvram_data, 1790 .fw_dump = qla2100_fw_dump, 1791 .beacon_on = NULL, 1792 .beacon_off = NULL, 1793 .beacon_blink = NULL, 1794 .read_optrom = qla2x00_read_optrom_data, 1795 .write_optrom = qla2x00_write_optrom_data, 1796 .get_flash_version = qla2x00_get_flash_version, 1797 .start_scsi = qla2x00_start_scsi, 1798 .abort_isp = qla2x00_abort_isp, 1799 .iospace_config = qla2x00_iospace_config, 1800 .initialize_adapter = qla2x00_initialize_adapter, 1801 }; 1802 1803 static struct isp_operations qla2300_isp_ops = { 1804 .pci_config = qla2300_pci_config, 1805 .reset_chip = qla2x00_reset_chip, 1806 .chip_diag = qla2x00_chip_diag, 1807 .config_rings = qla2x00_config_rings, 1808 .reset_adapter = qla2x00_reset_adapter, 1809 .nvram_config = qla2x00_nvram_config, 1810 .update_fw_options = qla2x00_update_fw_options, 1811 .load_risc = qla2x00_load_risc, 1812 .pci_info_str = qla2x00_pci_info_str, 1813 .fw_version_str = qla2x00_fw_version_str, 1814 .intr_handler = qla2300_intr_handler, 1815 .enable_intrs = qla2x00_enable_intrs, 1816 .disable_intrs = qla2x00_disable_intrs, 1817 .abort_command = qla2x00_abort_command, 1818 .target_reset = qla2x00_abort_target, 1819 .lun_reset = qla2x00_lun_reset, 1820 .fabric_login = qla2x00_login_fabric, 1821 .fabric_logout = qla2x00_fabric_logout, 1822 .calc_req_entries = qla2x00_calc_iocbs_32, 1823 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1824 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1825 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1826 .read_nvram = qla2x00_read_nvram_data, 1827 .write_nvram = qla2x00_write_nvram_data, 1828 .fw_dump = qla2300_fw_dump, 1829 .beacon_on = qla2x00_beacon_on, 1830 .beacon_off = qla2x00_beacon_off, 1831 .beacon_blink = qla2x00_beacon_blink, 1832 .read_optrom = qla2x00_read_optrom_data, 1833 .write_optrom = qla2x00_write_optrom_data, 1834 .get_flash_version = qla2x00_get_flash_version, 1835 .start_scsi = qla2x00_start_scsi, 1836 .abort_isp = qla2x00_abort_isp, 1837 .iospace_config = qla2x00_iospace_config, 1838 .initialize_adapter = qla2x00_initialize_adapter, 1839 }; 1840 1841 static struct isp_operations qla24xx_isp_ops = { 1842 .pci_config = qla24xx_pci_config, 1843 .reset_chip = qla24xx_reset_chip, 1844 .chip_diag = qla24xx_chip_diag, 1845 .config_rings = qla24xx_config_rings, 1846 .reset_adapter = qla24xx_reset_adapter, 1847 .nvram_config = qla24xx_nvram_config, 1848 .update_fw_options = qla24xx_update_fw_options, 1849 .load_risc = qla24xx_load_risc, 1850 .pci_info_str = qla24xx_pci_info_str, 1851 .fw_version_str = qla24xx_fw_version_str, 1852 .intr_handler = qla24xx_intr_handler, 1853 .enable_intrs = qla24xx_enable_intrs, 1854 .disable_intrs = qla24xx_disable_intrs, 1855 .abort_command = qla24xx_abort_command, 1856 .target_reset = qla24xx_abort_target, 1857 .lun_reset = qla24xx_lun_reset, 1858 .fabric_login = qla24xx_login_fabric, 1859 .fabric_logout = qla24xx_fabric_logout, 1860 .calc_req_entries = NULL, 1861 .build_iocbs = NULL, 1862 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1863 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1864 .read_nvram = qla24xx_read_nvram_data, 1865 .write_nvram = qla24xx_write_nvram_data, 1866 .fw_dump = qla24xx_fw_dump, 1867 .beacon_on = qla24xx_beacon_on, 1868 .beacon_off = qla24xx_beacon_off, 1869 .beacon_blink = qla24xx_beacon_blink, 1870 .read_optrom = qla24xx_read_optrom_data, 1871 .write_optrom = qla24xx_write_optrom_data, 1872 .get_flash_version = qla24xx_get_flash_version, 1873 .start_scsi = qla24xx_start_scsi, 1874 .abort_isp = qla2x00_abort_isp, 1875 .iospace_config = qla2x00_iospace_config, 1876 .initialize_adapter = qla2x00_initialize_adapter, 1877 }; 1878 1879 static struct isp_operations qla25xx_isp_ops = { 1880 .pci_config = qla25xx_pci_config, 1881 .reset_chip = qla24xx_reset_chip, 1882 .chip_diag = qla24xx_chip_diag, 1883 .config_rings = qla24xx_config_rings, 1884 .reset_adapter = qla24xx_reset_adapter, 1885 .nvram_config = qla24xx_nvram_config, 1886 .update_fw_options = qla24xx_update_fw_options, 1887 .load_risc = qla24xx_load_risc, 1888 .pci_info_str = qla24xx_pci_info_str, 1889 .fw_version_str = qla24xx_fw_version_str, 1890 .intr_handler = qla24xx_intr_handler, 1891 .enable_intrs = qla24xx_enable_intrs, 1892 .disable_intrs = qla24xx_disable_intrs, 1893 .abort_command = qla24xx_abort_command, 1894 .target_reset = qla24xx_abort_target, 1895 .lun_reset = qla24xx_lun_reset, 1896 .fabric_login = qla24xx_login_fabric, 1897 .fabric_logout = qla24xx_fabric_logout, 1898 .calc_req_entries = NULL, 1899 .build_iocbs = NULL, 1900 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1901 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1902 .read_nvram = qla25xx_read_nvram_data, 1903 .write_nvram = qla25xx_write_nvram_data, 1904 .fw_dump = qla25xx_fw_dump, 1905 .beacon_on = qla24xx_beacon_on, 1906 .beacon_off = qla24xx_beacon_off, 1907 .beacon_blink = qla24xx_beacon_blink, 1908 .read_optrom = qla25xx_read_optrom_data, 1909 .write_optrom = qla24xx_write_optrom_data, 1910 .get_flash_version = qla24xx_get_flash_version, 1911 .start_scsi = qla24xx_dif_start_scsi, 1912 .abort_isp = qla2x00_abort_isp, 1913 .iospace_config = qla2x00_iospace_config, 1914 .initialize_adapter = qla2x00_initialize_adapter, 1915 }; 1916 1917 static struct isp_operations qla81xx_isp_ops = { 1918 .pci_config = qla25xx_pci_config, 1919 .reset_chip = qla24xx_reset_chip, 1920 .chip_diag = qla24xx_chip_diag, 1921 .config_rings = qla24xx_config_rings, 1922 .reset_adapter = qla24xx_reset_adapter, 1923 .nvram_config = qla81xx_nvram_config, 1924 .update_fw_options = qla81xx_update_fw_options, 1925 .load_risc = qla81xx_load_risc, 1926 .pci_info_str = qla24xx_pci_info_str, 1927 .fw_version_str = qla24xx_fw_version_str, 1928 .intr_handler = qla24xx_intr_handler, 1929 .enable_intrs = qla24xx_enable_intrs, 1930 .disable_intrs = qla24xx_disable_intrs, 1931 .abort_command = qla24xx_abort_command, 1932 .target_reset = qla24xx_abort_target, 1933 .lun_reset = qla24xx_lun_reset, 1934 .fabric_login = qla24xx_login_fabric, 1935 .fabric_logout = qla24xx_fabric_logout, 1936 .calc_req_entries = NULL, 1937 .build_iocbs = NULL, 1938 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1939 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1940 .read_nvram = NULL, 1941 .write_nvram = NULL, 1942 .fw_dump = qla81xx_fw_dump, 1943 .beacon_on = qla24xx_beacon_on, 1944 .beacon_off = qla24xx_beacon_off, 1945 .beacon_blink = qla83xx_beacon_blink, 1946 .read_optrom = qla25xx_read_optrom_data, 1947 .write_optrom = qla24xx_write_optrom_data, 1948 .get_flash_version = qla24xx_get_flash_version, 1949 .start_scsi = qla24xx_dif_start_scsi, 1950 .abort_isp = qla2x00_abort_isp, 1951 .iospace_config = qla2x00_iospace_config, 1952 .initialize_adapter = qla2x00_initialize_adapter, 1953 }; 1954 1955 static struct isp_operations qla82xx_isp_ops = { 1956 .pci_config = qla82xx_pci_config, 1957 .reset_chip = qla82xx_reset_chip, 1958 .chip_diag = qla24xx_chip_diag, 1959 .config_rings = qla82xx_config_rings, 1960 .reset_adapter = qla24xx_reset_adapter, 1961 .nvram_config = qla81xx_nvram_config, 1962 .update_fw_options = qla24xx_update_fw_options, 1963 .load_risc = qla82xx_load_risc, 1964 .pci_info_str = qla24xx_pci_info_str, 1965 .fw_version_str = qla24xx_fw_version_str, 1966 .intr_handler = qla82xx_intr_handler, 1967 .enable_intrs = qla82xx_enable_intrs, 1968 .disable_intrs = qla82xx_disable_intrs, 1969 .abort_command = qla24xx_abort_command, 1970 .target_reset = qla24xx_abort_target, 1971 .lun_reset = qla24xx_lun_reset, 1972 .fabric_login = qla24xx_login_fabric, 1973 .fabric_logout = qla24xx_fabric_logout, 1974 .calc_req_entries = NULL, 1975 .build_iocbs = NULL, 1976 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1977 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1978 .read_nvram = qla24xx_read_nvram_data, 1979 .write_nvram = qla24xx_write_nvram_data, 1980 .fw_dump = qla82xx_fw_dump, 1981 .beacon_on = qla82xx_beacon_on, 1982 .beacon_off = qla82xx_beacon_off, 1983 .beacon_blink = NULL, 1984 .read_optrom = qla82xx_read_optrom_data, 1985 .write_optrom = qla82xx_write_optrom_data, 1986 .get_flash_version = qla82xx_get_flash_version, 1987 .start_scsi = qla82xx_start_scsi, 1988 .abort_isp = qla82xx_abort_isp, 1989 .iospace_config = qla82xx_iospace_config, 1990 .initialize_adapter = qla2x00_initialize_adapter, 1991 }; 1992 1993 static struct isp_operations qla8044_isp_ops = { 1994 .pci_config = qla82xx_pci_config, 1995 .reset_chip = qla82xx_reset_chip, 1996 .chip_diag = qla24xx_chip_diag, 1997 .config_rings = qla82xx_config_rings, 1998 .reset_adapter = qla24xx_reset_adapter, 1999 .nvram_config = qla81xx_nvram_config, 2000 .update_fw_options = qla24xx_update_fw_options, 2001 .load_risc = qla82xx_load_risc, 2002 .pci_info_str = qla24xx_pci_info_str, 2003 .fw_version_str = qla24xx_fw_version_str, 2004 .intr_handler = qla8044_intr_handler, 2005 .enable_intrs = qla82xx_enable_intrs, 2006 .disable_intrs = qla82xx_disable_intrs, 2007 .abort_command = qla24xx_abort_command, 2008 .target_reset = qla24xx_abort_target, 2009 .lun_reset = qla24xx_lun_reset, 2010 .fabric_login = qla24xx_login_fabric, 2011 .fabric_logout = qla24xx_fabric_logout, 2012 .calc_req_entries = NULL, 2013 .build_iocbs = NULL, 2014 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2015 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2016 .read_nvram = NULL, 2017 .write_nvram = NULL, 2018 .fw_dump = qla8044_fw_dump, 2019 .beacon_on = qla82xx_beacon_on, 2020 .beacon_off = qla82xx_beacon_off, 2021 .beacon_blink = NULL, 2022 .read_optrom = qla8044_read_optrom_data, 2023 .write_optrom = qla8044_write_optrom_data, 2024 .get_flash_version = qla82xx_get_flash_version, 2025 .start_scsi = qla82xx_start_scsi, 2026 .abort_isp = qla8044_abort_isp, 2027 .iospace_config = qla82xx_iospace_config, 2028 .initialize_adapter = qla2x00_initialize_adapter, 2029 }; 2030 2031 static struct isp_operations qla83xx_isp_ops = { 2032 .pci_config = qla25xx_pci_config, 2033 .reset_chip = qla24xx_reset_chip, 2034 .chip_diag = qla24xx_chip_diag, 2035 .config_rings = qla24xx_config_rings, 2036 .reset_adapter = qla24xx_reset_adapter, 2037 .nvram_config = qla81xx_nvram_config, 2038 .update_fw_options = qla81xx_update_fw_options, 2039 .load_risc = qla81xx_load_risc, 2040 .pci_info_str = qla24xx_pci_info_str, 2041 .fw_version_str = qla24xx_fw_version_str, 2042 .intr_handler = qla24xx_intr_handler, 2043 .enable_intrs = qla24xx_enable_intrs, 2044 .disable_intrs = qla24xx_disable_intrs, 2045 .abort_command = qla24xx_abort_command, 2046 .target_reset = qla24xx_abort_target, 2047 .lun_reset = qla24xx_lun_reset, 2048 .fabric_login = qla24xx_login_fabric, 2049 .fabric_logout = qla24xx_fabric_logout, 2050 .calc_req_entries = NULL, 2051 .build_iocbs = NULL, 2052 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2053 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2054 .read_nvram = NULL, 2055 .write_nvram = NULL, 2056 .fw_dump = qla83xx_fw_dump, 2057 .beacon_on = qla24xx_beacon_on, 2058 .beacon_off = qla24xx_beacon_off, 2059 .beacon_blink = qla83xx_beacon_blink, 2060 .read_optrom = qla25xx_read_optrom_data, 2061 .write_optrom = qla24xx_write_optrom_data, 2062 .get_flash_version = qla24xx_get_flash_version, 2063 .start_scsi = qla24xx_dif_start_scsi, 2064 .abort_isp = qla2x00_abort_isp, 2065 .iospace_config = qla83xx_iospace_config, 2066 .initialize_adapter = qla2x00_initialize_adapter, 2067 }; 2068 2069 static struct isp_operations qlafx00_isp_ops = { 2070 .pci_config = qlafx00_pci_config, 2071 .reset_chip = qlafx00_soft_reset, 2072 .chip_diag = qlafx00_chip_diag, 2073 .config_rings = qlafx00_config_rings, 2074 .reset_adapter = qlafx00_soft_reset, 2075 .nvram_config = NULL, 2076 .update_fw_options = NULL, 2077 .load_risc = NULL, 2078 .pci_info_str = qlafx00_pci_info_str, 2079 .fw_version_str = qlafx00_fw_version_str, 2080 .intr_handler = qlafx00_intr_handler, 2081 .enable_intrs = qlafx00_enable_intrs, 2082 .disable_intrs = qlafx00_disable_intrs, 2083 .abort_command = qla24xx_async_abort_command, 2084 .target_reset = qlafx00_abort_target, 2085 .lun_reset = qlafx00_lun_reset, 2086 .fabric_login = NULL, 2087 .fabric_logout = NULL, 2088 .calc_req_entries = NULL, 2089 .build_iocbs = NULL, 2090 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2091 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2092 .read_nvram = qla24xx_read_nvram_data, 2093 .write_nvram = qla24xx_write_nvram_data, 2094 .fw_dump = NULL, 2095 .beacon_on = qla24xx_beacon_on, 2096 .beacon_off = qla24xx_beacon_off, 2097 .beacon_blink = NULL, 2098 .read_optrom = qla24xx_read_optrom_data, 2099 .write_optrom = qla24xx_write_optrom_data, 2100 .get_flash_version = qla24xx_get_flash_version, 2101 .start_scsi = qlafx00_start_scsi, 2102 .abort_isp = qlafx00_abort_isp, 2103 .iospace_config = qlafx00_iospace_config, 2104 .initialize_adapter = qlafx00_initialize_adapter, 2105 }; 2106 2107 static struct isp_operations qla27xx_isp_ops = { 2108 .pci_config = qla25xx_pci_config, 2109 .reset_chip = qla24xx_reset_chip, 2110 .chip_diag = qla24xx_chip_diag, 2111 .config_rings = qla24xx_config_rings, 2112 .reset_adapter = qla24xx_reset_adapter, 2113 .nvram_config = qla81xx_nvram_config, 2114 .update_fw_options = qla81xx_update_fw_options, 2115 .load_risc = qla81xx_load_risc, 2116 .pci_info_str = qla24xx_pci_info_str, 2117 .fw_version_str = qla24xx_fw_version_str, 2118 .intr_handler = qla24xx_intr_handler, 2119 .enable_intrs = qla24xx_enable_intrs, 2120 .disable_intrs = qla24xx_disable_intrs, 2121 .abort_command = qla24xx_abort_command, 2122 .target_reset = qla24xx_abort_target, 2123 .lun_reset = qla24xx_lun_reset, 2124 .fabric_login = qla24xx_login_fabric, 2125 .fabric_logout = qla24xx_fabric_logout, 2126 .calc_req_entries = NULL, 2127 .build_iocbs = NULL, 2128 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2129 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2130 .read_nvram = NULL, 2131 .write_nvram = NULL, 2132 .fw_dump = qla27xx_fwdump, 2133 .beacon_on = qla24xx_beacon_on, 2134 .beacon_off = qla24xx_beacon_off, 2135 .beacon_blink = qla83xx_beacon_blink, 2136 .read_optrom = qla25xx_read_optrom_data, 2137 .write_optrom = qla24xx_write_optrom_data, 2138 .get_flash_version = qla24xx_get_flash_version, 2139 .start_scsi = qla24xx_dif_start_scsi, 2140 .abort_isp = qla2x00_abort_isp, 2141 .iospace_config = qla83xx_iospace_config, 2142 .initialize_adapter = qla2x00_initialize_adapter, 2143 }; 2144 2145 static inline void 2146 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2147 { 2148 ha->device_type = DT_EXTENDED_IDS; 2149 switch (ha->pdev->device) { 2150 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2151 ha->device_type |= DT_ISP2100; 2152 ha->device_type &= ~DT_EXTENDED_IDS; 2153 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2154 break; 2155 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2156 ha->device_type |= DT_ISP2200; 2157 ha->device_type &= ~DT_EXTENDED_IDS; 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2159 break; 2160 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2161 ha->device_type |= DT_ISP2300; 2162 ha->device_type |= DT_ZIO_SUPPORTED; 2163 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2164 break; 2165 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2166 ha->device_type |= DT_ISP2312; 2167 ha->device_type |= DT_ZIO_SUPPORTED; 2168 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2169 break; 2170 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2171 ha->device_type |= DT_ISP2322; 2172 ha->device_type |= DT_ZIO_SUPPORTED; 2173 if (ha->pdev->subsystem_vendor == 0x1028 && 2174 ha->pdev->subsystem_device == 0x0170) 2175 ha->device_type |= DT_OEM_001; 2176 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2177 break; 2178 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2179 ha->device_type |= DT_ISP6312; 2180 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2181 break; 2182 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2183 ha->device_type |= DT_ISP6322; 2184 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2185 break; 2186 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2187 ha->device_type |= DT_ISP2422; 2188 ha->device_type |= DT_ZIO_SUPPORTED; 2189 ha->device_type |= DT_FWI2; 2190 ha->device_type |= DT_IIDMA; 2191 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2192 break; 2193 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2194 ha->device_type |= DT_ISP2432; 2195 ha->device_type |= DT_ZIO_SUPPORTED; 2196 ha->device_type |= DT_FWI2; 2197 ha->device_type |= DT_IIDMA; 2198 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2199 break; 2200 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2201 ha->device_type |= DT_ISP8432; 2202 ha->device_type |= DT_ZIO_SUPPORTED; 2203 ha->device_type |= DT_FWI2; 2204 ha->device_type |= DT_IIDMA; 2205 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2206 break; 2207 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2208 ha->device_type |= DT_ISP5422; 2209 ha->device_type |= DT_FWI2; 2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2211 break; 2212 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2213 ha->device_type |= DT_ISP5432; 2214 ha->device_type |= DT_FWI2; 2215 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2216 break; 2217 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2218 ha->device_type |= DT_ISP2532; 2219 ha->device_type |= DT_ZIO_SUPPORTED; 2220 ha->device_type |= DT_FWI2; 2221 ha->device_type |= DT_IIDMA; 2222 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2223 break; 2224 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2225 ha->device_type |= DT_ISP8001; 2226 ha->device_type |= DT_ZIO_SUPPORTED; 2227 ha->device_type |= DT_FWI2; 2228 ha->device_type |= DT_IIDMA; 2229 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2230 break; 2231 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2232 ha->device_type |= DT_ISP8021; 2233 ha->device_type |= DT_ZIO_SUPPORTED; 2234 ha->device_type |= DT_FWI2; 2235 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2236 /* Initialize 82XX ISP flags */ 2237 qla82xx_init_flags(ha); 2238 break; 2239 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2240 ha->device_type |= DT_ISP8044; 2241 ha->device_type |= DT_ZIO_SUPPORTED; 2242 ha->device_type |= DT_FWI2; 2243 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2244 /* Initialize 82XX ISP flags */ 2245 qla82xx_init_flags(ha); 2246 break; 2247 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2248 ha->device_type |= DT_ISP2031; 2249 ha->device_type |= DT_ZIO_SUPPORTED; 2250 ha->device_type |= DT_FWI2; 2251 ha->device_type |= DT_IIDMA; 2252 ha->device_type |= DT_T10_PI; 2253 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2254 break; 2255 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2256 ha->device_type |= DT_ISP8031; 2257 ha->device_type |= DT_ZIO_SUPPORTED; 2258 ha->device_type |= DT_FWI2; 2259 ha->device_type |= DT_IIDMA; 2260 ha->device_type |= DT_T10_PI; 2261 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2262 break; 2263 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2264 ha->device_type |= DT_ISPFX00; 2265 break; 2266 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2267 ha->device_type |= DT_ISP2071; 2268 ha->device_type |= DT_ZIO_SUPPORTED; 2269 ha->device_type |= DT_FWI2; 2270 ha->device_type |= DT_IIDMA; 2271 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2272 break; 2273 } 2274 2275 if (IS_QLA82XX(ha)) 2276 ha->port_no = ha->portnum & 1; 2277 else { 2278 /* Get adapter physical port no from interrupt pin register. */ 2279 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2280 if (IS_QLA27XX(ha)) 2281 ha->port_no--; 2282 else 2283 ha->port_no = !(ha->port_no & 1); 2284 } 2285 2286 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2287 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2288 ha->device_type, ha->port_no, ha->fw_srisc_address); 2289 } 2290 2291 static void 2292 qla2xxx_scan_start(struct Scsi_Host *shost) 2293 { 2294 scsi_qla_host_t *vha = shost_priv(shost); 2295 2296 if (vha->hw->flags.running_gold_fw) 2297 return; 2298 2299 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2300 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2301 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2302 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2303 } 2304 2305 static int 2306 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2307 { 2308 scsi_qla_host_t *vha = shost_priv(shost); 2309 2310 if (!vha->host) 2311 return 1; 2312 if (time > vha->hw->loop_reset_delay * HZ) 2313 return 1; 2314 2315 return atomic_read(&vha->loop_state) == LOOP_READY; 2316 } 2317 2318 /* 2319 * PCI driver interface 2320 */ 2321 static int 2322 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2323 { 2324 int ret = -ENODEV; 2325 struct Scsi_Host *host; 2326 scsi_qla_host_t *base_vha = NULL; 2327 struct qla_hw_data *ha; 2328 char pci_info[30]; 2329 char fw_str[30], wq_name[30]; 2330 struct scsi_host_template *sht; 2331 int bars, mem_only = 0; 2332 uint16_t req_length = 0, rsp_length = 0; 2333 struct req_que *req = NULL; 2334 struct rsp_que *rsp = NULL; 2335 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2336 sht = &qla2xxx_driver_template; 2337 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2338 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2339 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2340 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2341 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2342 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2343 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2344 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071) { 2350 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2351 mem_only = 1; 2352 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2353 "Mem only adapter.\n"); 2354 } 2355 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2356 "Bars=%d.\n", bars); 2357 2358 if (mem_only) { 2359 if (pci_enable_device_mem(pdev)) 2360 goto probe_out; 2361 } else { 2362 if (pci_enable_device(pdev)) 2363 goto probe_out; 2364 } 2365 2366 /* This may fail but that's ok */ 2367 pci_enable_pcie_error_reporting(pdev); 2368 2369 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2370 if (!ha) { 2371 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2372 "Unable to allocate memory for ha.\n"); 2373 goto probe_out; 2374 } 2375 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2376 "Memory allocated for ha=%p.\n", ha); 2377 ha->pdev = pdev; 2378 ha->tgt.enable_class_2 = ql2xenableclass2; 2379 2380 /* Clear our data area */ 2381 ha->bars = bars; 2382 ha->mem_only = mem_only; 2383 spin_lock_init(&ha->hardware_lock); 2384 spin_lock_init(&ha->vport_slock); 2385 mutex_init(&ha->selflogin_lock); 2386 mutex_init(&ha->optrom_mutex); 2387 2388 /* Set ISP-type information. */ 2389 qla2x00_set_isp_flags(ha); 2390 2391 /* Set EEH reset type to fundamental if required by hba */ 2392 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2393 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2394 pdev->needs_freset = 1; 2395 2396 ha->prev_topology = 0; 2397 ha->init_cb_size = sizeof(init_cb_t); 2398 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2399 ha->optrom_size = OPTROM_SIZE_2300; 2400 2401 /* Assign ISP specific operations. */ 2402 if (IS_QLA2100(ha)) { 2403 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2404 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2405 req_length = REQUEST_ENTRY_CNT_2100; 2406 rsp_length = RESPONSE_ENTRY_CNT_2100; 2407 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2408 ha->gid_list_info_size = 4; 2409 ha->flash_conf_off = ~0; 2410 ha->flash_data_off = ~0; 2411 ha->nvram_conf_off = ~0; 2412 ha->nvram_data_off = ~0; 2413 ha->isp_ops = &qla2100_isp_ops; 2414 } else if (IS_QLA2200(ha)) { 2415 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2416 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2417 req_length = REQUEST_ENTRY_CNT_2200; 2418 rsp_length = RESPONSE_ENTRY_CNT_2100; 2419 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2420 ha->gid_list_info_size = 4; 2421 ha->flash_conf_off = ~0; 2422 ha->flash_data_off = ~0; 2423 ha->nvram_conf_off = ~0; 2424 ha->nvram_data_off = ~0; 2425 ha->isp_ops = &qla2100_isp_ops; 2426 } else if (IS_QLA23XX(ha)) { 2427 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2428 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2429 req_length = REQUEST_ENTRY_CNT_2200; 2430 rsp_length = RESPONSE_ENTRY_CNT_2300; 2431 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2432 ha->gid_list_info_size = 6; 2433 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2434 ha->optrom_size = OPTROM_SIZE_2322; 2435 ha->flash_conf_off = ~0; 2436 ha->flash_data_off = ~0; 2437 ha->nvram_conf_off = ~0; 2438 ha->nvram_data_off = ~0; 2439 ha->isp_ops = &qla2300_isp_ops; 2440 } else if (IS_QLA24XX_TYPE(ha)) { 2441 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2442 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2443 req_length = REQUEST_ENTRY_CNT_24XX; 2444 rsp_length = RESPONSE_ENTRY_CNT_2300; 2445 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2446 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2447 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2448 ha->gid_list_info_size = 8; 2449 ha->optrom_size = OPTROM_SIZE_24XX; 2450 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2451 ha->isp_ops = &qla24xx_isp_ops; 2452 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2453 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2454 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2455 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2456 } else if (IS_QLA25XX(ha)) { 2457 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2458 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2459 req_length = REQUEST_ENTRY_CNT_24XX; 2460 rsp_length = RESPONSE_ENTRY_CNT_2300; 2461 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2462 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2463 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2464 ha->gid_list_info_size = 8; 2465 ha->optrom_size = OPTROM_SIZE_25XX; 2466 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2467 ha->isp_ops = &qla25xx_isp_ops; 2468 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2469 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2470 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2471 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2472 } else if (IS_QLA81XX(ha)) { 2473 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2474 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2475 req_length = REQUEST_ENTRY_CNT_24XX; 2476 rsp_length = RESPONSE_ENTRY_CNT_2300; 2477 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2478 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2479 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2480 ha->gid_list_info_size = 8; 2481 ha->optrom_size = OPTROM_SIZE_81XX; 2482 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2483 ha->isp_ops = &qla81xx_isp_ops; 2484 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2485 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2486 ha->nvram_conf_off = ~0; 2487 ha->nvram_data_off = ~0; 2488 } else if (IS_QLA82XX(ha)) { 2489 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2490 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2491 req_length = REQUEST_ENTRY_CNT_82XX; 2492 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2493 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2494 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2495 ha->gid_list_info_size = 8; 2496 ha->optrom_size = OPTROM_SIZE_82XX; 2497 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2498 ha->isp_ops = &qla82xx_isp_ops; 2499 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2500 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2501 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2502 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2503 } else if (IS_QLA8044(ha)) { 2504 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2505 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2506 req_length = REQUEST_ENTRY_CNT_82XX; 2507 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2508 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2509 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2510 ha->gid_list_info_size = 8; 2511 ha->optrom_size = OPTROM_SIZE_83XX; 2512 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2513 ha->isp_ops = &qla8044_isp_ops; 2514 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2515 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2516 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2517 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2518 } else if (IS_QLA83XX(ha)) { 2519 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2520 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2521 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2522 req_length = REQUEST_ENTRY_CNT_24XX; 2523 rsp_length = RESPONSE_ENTRY_CNT_2300; 2524 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2525 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2526 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2527 ha->gid_list_info_size = 8; 2528 ha->optrom_size = OPTROM_SIZE_83XX; 2529 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2530 ha->isp_ops = &qla83xx_isp_ops; 2531 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2532 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2533 ha->nvram_conf_off = ~0; 2534 ha->nvram_data_off = ~0; 2535 } else if (IS_QLAFX00(ha)) { 2536 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2537 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2538 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2539 req_length = REQUEST_ENTRY_CNT_FX00; 2540 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2541 ha->isp_ops = &qlafx00_isp_ops; 2542 ha->port_down_retry_count = 30; /* default value */ 2543 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2544 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2545 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2546 ha->mr.fw_hbt_en = 1; 2547 ha->mr.host_info_resend = false; 2548 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2549 } else if (IS_QLA27XX(ha)) { 2550 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2551 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2552 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2553 req_length = REQUEST_ENTRY_CNT_24XX; 2554 rsp_length = RESPONSE_ENTRY_CNT_2300; 2555 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2556 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2557 ha->gid_list_info_size = 8; 2558 ha->optrom_size = OPTROM_SIZE_83XX; 2559 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2560 ha->isp_ops = &qla27xx_isp_ops; 2561 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2562 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2563 ha->nvram_conf_off = ~0; 2564 ha->nvram_data_off = ~0; 2565 } 2566 2567 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2568 "mbx_count=%d, req_length=%d, " 2569 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2570 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2571 "max_fibre_devices=%d.\n", 2572 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2573 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2574 ha->nvram_npiv_size, ha->max_fibre_devices); 2575 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2576 "isp_ops=%p, flash_conf_off=%d, " 2577 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2578 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2579 ha->nvram_conf_off, ha->nvram_data_off); 2580 2581 /* Configure PCI I/O space */ 2582 ret = ha->isp_ops->iospace_config(ha); 2583 if (ret) 2584 goto iospace_config_failed; 2585 2586 ql_log_pci(ql_log_info, pdev, 0x001d, 2587 "Found an ISP%04X irq %d iobase 0x%p.\n", 2588 pdev->device, pdev->irq, ha->iobase); 2589 mutex_init(&ha->vport_lock); 2590 init_completion(&ha->mbx_cmd_comp); 2591 complete(&ha->mbx_cmd_comp); 2592 init_completion(&ha->mbx_intr_comp); 2593 init_completion(&ha->dcbx_comp); 2594 init_completion(&ha->lb_portup_comp); 2595 2596 set_bit(0, (unsigned long *) ha->vp_idx_map); 2597 2598 qla2x00_config_dma_addressing(ha); 2599 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2600 "64 Bit addressing is %s.\n", 2601 ha->flags.enable_64bit_addressing ? "enable" : 2602 "disable"); 2603 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2604 if (ret) { 2605 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2606 "Failed to allocate memory for adapter, aborting.\n"); 2607 2608 goto probe_hw_failed; 2609 } 2610 2611 req->max_q_depth = MAX_Q_DEPTH; 2612 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2613 req->max_q_depth = ql2xmaxqdepth; 2614 2615 2616 base_vha = qla2x00_create_host(sht, ha); 2617 if (!base_vha) { 2618 ret = -ENOMEM; 2619 qla2x00_mem_free(ha); 2620 qla2x00_free_req_que(ha, req); 2621 qla2x00_free_rsp_que(ha, rsp); 2622 goto probe_hw_failed; 2623 } 2624 2625 pci_set_drvdata(pdev, base_vha); 2626 2627 host = base_vha->host; 2628 base_vha->req = req; 2629 if (IS_QLA2XXX_MIDTYPE(ha)) 2630 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2631 else 2632 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2633 base_vha->vp_idx; 2634 2635 /* Setup fcport template structure. */ 2636 ha->mr.fcport.vha = base_vha; 2637 ha->mr.fcport.port_type = FCT_UNKNOWN; 2638 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2639 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2640 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2641 ha->mr.fcport.scan_state = 1; 2642 2643 /* Set the SG table size based on ISP type */ 2644 if (!IS_FWI2_CAPABLE(ha)) { 2645 if (IS_QLA2100(ha)) 2646 host->sg_tablesize = 32; 2647 } else { 2648 if (!IS_QLA82XX(ha)) 2649 host->sg_tablesize = QLA_SG_ALL; 2650 } 2651 host->max_id = ha->max_fibre_devices; 2652 host->cmd_per_lun = 3; 2653 host->unique_id = host->host_no; 2654 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2655 host->max_cmd_len = 32; 2656 else 2657 host->max_cmd_len = MAX_CMDSZ; 2658 host->max_channel = MAX_BUSES - 1; 2659 host->max_lun = ql2xmaxlun; 2660 host->transportt = qla2xxx_transport_template; 2661 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2662 2663 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2664 "max_id=%d this_id=%d " 2665 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2666 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, 2667 host->this_id, host->cmd_per_lun, host->unique_id, 2668 host->max_cmd_len, host->max_channel, host->max_lun, 2669 host->transportt, sht->vendor_id); 2670 2671 que_init: 2672 /* Alloc arrays of request and response ring ptrs */ 2673 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2674 ql_log(ql_log_fatal, base_vha, 0x003d, 2675 "Failed to allocate memory for queue pointers..." 2676 "aborting.\n"); 2677 goto probe_init_failed; 2678 } 2679 2680 qlt_probe_one_stage1(base_vha, ha); 2681 2682 /* Set up the irqs */ 2683 ret = qla2x00_request_irqs(ha, rsp); 2684 if (ret) 2685 goto probe_init_failed; 2686 2687 pci_save_state(pdev); 2688 2689 /* Assign back pointers */ 2690 rsp->req = req; 2691 req->rsp = rsp; 2692 2693 if (IS_QLAFX00(ha)) { 2694 ha->rsp_q_map[0] = rsp; 2695 ha->req_q_map[0] = req; 2696 set_bit(0, ha->req_qid_map); 2697 set_bit(0, ha->rsp_qid_map); 2698 } 2699 2700 /* FWI2-capable only. */ 2701 req->req_q_in = &ha->iobase->isp24.req_q_in; 2702 req->req_q_out = &ha->iobase->isp24.req_q_out; 2703 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2704 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2705 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2706 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2707 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2708 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2709 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2710 } 2711 2712 if (IS_QLAFX00(ha)) { 2713 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2714 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2715 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2716 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2717 } 2718 2719 if (IS_P3P_TYPE(ha)) { 2720 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2721 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2722 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2723 } 2724 2725 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2726 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2727 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2728 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2729 "req->req_q_in=%p req->req_q_out=%p " 2730 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2731 req->req_q_in, req->req_q_out, 2732 rsp->rsp_q_in, rsp->rsp_q_out); 2733 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2734 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2735 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2736 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2737 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2738 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2739 2740 if (ha->isp_ops->initialize_adapter(base_vha)) { 2741 ql_log(ql_log_fatal, base_vha, 0x00d6, 2742 "Failed to initialize adapter - Adapter flags %x.\n", 2743 base_vha->device_flags); 2744 2745 if (IS_QLA82XX(ha)) { 2746 qla82xx_idc_lock(ha); 2747 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2748 QLA8XXX_DEV_FAILED); 2749 qla82xx_idc_unlock(ha); 2750 ql_log(ql_log_fatal, base_vha, 0x00d7, 2751 "HW State: FAILED.\n"); 2752 } else if (IS_QLA8044(ha)) { 2753 qla8044_idc_lock(ha); 2754 qla8044_wr_direct(base_vha, 2755 QLA8044_CRB_DEV_STATE_INDEX, 2756 QLA8XXX_DEV_FAILED); 2757 qla8044_idc_unlock(ha); 2758 ql_log(ql_log_fatal, base_vha, 0x0150, 2759 "HW State: FAILED.\n"); 2760 } 2761 2762 ret = -ENODEV; 2763 goto probe_failed; 2764 } 2765 2766 if (IS_QLAFX00(ha)) 2767 host->can_queue = QLAFX00_MAX_CANQUEUE; 2768 else 2769 host->can_queue = req->num_outstanding_cmds - 10; 2770 2771 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2772 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2773 host->can_queue, base_vha->req, 2774 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2775 2776 if (ha->mqenable) { 2777 if (qla25xx_setup_mode(base_vha)) { 2778 ql_log(ql_log_warn, base_vha, 0x00ec, 2779 "Failed to create queues, falling back to single queue mode.\n"); 2780 goto que_init; 2781 } 2782 } 2783 2784 if (ha->flags.running_gold_fw) 2785 goto skip_dpc; 2786 2787 /* 2788 * Startup the kernel thread for this host adapter 2789 */ 2790 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2791 "%s_dpc", base_vha->host_str); 2792 if (IS_ERR(ha->dpc_thread)) { 2793 ql_log(ql_log_fatal, base_vha, 0x00ed, 2794 "Failed to start DPC thread.\n"); 2795 ret = PTR_ERR(ha->dpc_thread); 2796 goto probe_failed; 2797 } 2798 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2799 "DPC thread started successfully.\n"); 2800 2801 /* 2802 * If we're not coming up in initiator mode, we might sit for 2803 * a while without waking up the dpc thread, which leads to a 2804 * stuck process warning. So just kick the dpc once here and 2805 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2806 */ 2807 qla2xxx_wake_dpc(base_vha); 2808 2809 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2810 2811 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2812 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2813 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2814 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2815 2816 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2817 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2818 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2819 INIT_WORK(&ha->idc_state_handler, 2820 qla83xx_idc_state_handler_work); 2821 INIT_WORK(&ha->nic_core_unrecoverable, 2822 qla83xx_nic_core_unrecoverable_work); 2823 } 2824 2825 skip_dpc: 2826 list_add_tail(&base_vha->list, &ha->vp_list); 2827 base_vha->host->irq = ha->pdev->irq; 2828 2829 /* Initialized the timer */ 2830 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2831 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2832 "Started qla2x00_timer with " 2833 "interval=%d.\n", WATCH_INTERVAL); 2834 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2835 "Detected hba at address=%p.\n", 2836 ha); 2837 2838 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2839 if (ha->fw_attributes & BIT_4) { 2840 int prot = 0, guard; 2841 base_vha->flags.difdix_supported = 1; 2842 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2843 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2844 if (ql2xenabledif == 1) 2845 prot = SHOST_DIX_TYPE0_PROTECTION; 2846 scsi_host_set_prot(host, 2847 prot | SHOST_DIF_TYPE1_PROTECTION 2848 | SHOST_DIF_TYPE2_PROTECTION 2849 | SHOST_DIF_TYPE3_PROTECTION 2850 | SHOST_DIX_TYPE1_PROTECTION 2851 | SHOST_DIX_TYPE2_PROTECTION 2852 | SHOST_DIX_TYPE3_PROTECTION); 2853 2854 guard = SHOST_DIX_GUARD_CRC; 2855 2856 if (IS_PI_IPGUARD_CAPABLE(ha) && 2857 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2858 guard |= SHOST_DIX_GUARD_IP; 2859 2860 scsi_host_set_guard(host, guard); 2861 } else 2862 base_vha->flags.difdix_supported = 0; 2863 } 2864 2865 ha->isp_ops->enable_intrs(ha); 2866 2867 if (IS_QLAFX00(ha)) { 2868 ret = qlafx00_fx_disc(base_vha, 2869 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2870 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2871 QLA_SG_ALL : 128; 2872 } 2873 2874 ret = scsi_add_host(host, &pdev->dev); 2875 if (ret) 2876 goto probe_failed; 2877 2878 base_vha->flags.init_done = 1; 2879 base_vha->flags.online = 1; 2880 2881 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2882 "Init done and hba is online.\n"); 2883 2884 if (qla_ini_mode_enabled(base_vha)) 2885 scsi_scan_host(host); 2886 else 2887 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2888 "skipping scsi_scan_host() for non-initiator port\n"); 2889 2890 qla2x00_alloc_sysfs_attr(base_vha); 2891 2892 if (IS_QLAFX00(ha)) { 2893 ret = qlafx00_fx_disc(base_vha, 2894 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2895 2896 /* Register system information */ 2897 ret = qlafx00_fx_disc(base_vha, 2898 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2899 } 2900 2901 qla2x00_init_host_attr(base_vha); 2902 2903 qla2x00_dfs_setup(base_vha); 2904 2905 ql_log(ql_log_info, base_vha, 0x00fb, 2906 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2907 ql_log(ql_log_info, base_vha, 0x00fc, 2908 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2909 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2910 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2911 base_vha->host_no, 2912 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2913 2914 qlt_add_target(ha, base_vha); 2915 2916 return 0; 2917 2918 probe_init_failed: 2919 qla2x00_free_req_que(ha, req); 2920 ha->req_q_map[0] = NULL; 2921 clear_bit(0, ha->req_qid_map); 2922 qla2x00_free_rsp_que(ha, rsp); 2923 ha->rsp_q_map[0] = NULL; 2924 clear_bit(0, ha->rsp_qid_map); 2925 ha->max_req_queues = ha->max_rsp_queues = 0; 2926 2927 probe_failed: 2928 if (base_vha->timer_active) 2929 qla2x00_stop_timer(base_vha); 2930 base_vha->flags.online = 0; 2931 if (ha->dpc_thread) { 2932 struct task_struct *t = ha->dpc_thread; 2933 2934 ha->dpc_thread = NULL; 2935 kthread_stop(t); 2936 } 2937 2938 qla2x00_free_device(base_vha); 2939 2940 scsi_host_put(base_vha->host); 2941 2942 probe_hw_failed: 2943 if (IS_QLA82XX(ha)) { 2944 qla82xx_idc_lock(ha); 2945 qla82xx_clear_drv_active(ha); 2946 qla82xx_idc_unlock(ha); 2947 } 2948 if (IS_QLA8044(ha)) { 2949 qla8044_idc_lock(ha); 2950 qla8044_clear_drv_active(ha); 2951 qla8044_idc_unlock(ha); 2952 } 2953 iospace_config_failed: 2954 if (IS_P3P_TYPE(ha)) { 2955 if (!ha->nx_pcibase) 2956 iounmap((device_reg_t *)ha->nx_pcibase); 2957 if (!ql2xdbwr) 2958 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 2959 } else { 2960 if (ha->iobase) 2961 iounmap(ha->iobase); 2962 if (ha->cregbase) 2963 iounmap(ha->cregbase); 2964 } 2965 pci_release_selected_regions(ha->pdev, ha->bars); 2966 kfree(ha); 2967 ha = NULL; 2968 2969 probe_out: 2970 pci_disable_device(pdev); 2971 return ret; 2972 } 2973 2974 static void 2975 qla2x00_shutdown(struct pci_dev *pdev) 2976 { 2977 scsi_qla_host_t *vha; 2978 struct qla_hw_data *ha; 2979 2980 if (!atomic_read(&pdev->enable_cnt)) 2981 return; 2982 2983 vha = pci_get_drvdata(pdev); 2984 ha = vha->hw; 2985 2986 /* Notify ISPFX00 firmware */ 2987 if (IS_QLAFX00(ha)) 2988 qlafx00_driver_shutdown(vha, 20); 2989 2990 /* Turn-off FCE trace */ 2991 if (ha->flags.fce_enabled) { 2992 qla2x00_disable_fce_trace(vha, NULL, NULL); 2993 ha->flags.fce_enabled = 0; 2994 } 2995 2996 /* Turn-off EFT trace */ 2997 if (ha->eft) 2998 qla2x00_disable_eft_trace(vha); 2999 3000 /* Stop currently executing firmware. */ 3001 qla2x00_try_to_stop_firmware(vha); 3002 3003 /* Turn adapter off line */ 3004 vha->flags.online = 0; 3005 3006 /* turn-off interrupts on the card */ 3007 if (ha->interrupts_on) { 3008 vha->flags.init_done = 0; 3009 ha->isp_ops->disable_intrs(ha); 3010 } 3011 3012 qla2x00_free_irqs(vha); 3013 3014 qla2x00_free_fw_dump(ha); 3015 } 3016 3017 /* Deletes all the virtual ports for a given ha */ 3018 static void 3019 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3020 { 3021 struct Scsi_Host *scsi_host; 3022 scsi_qla_host_t *vha; 3023 unsigned long flags; 3024 3025 mutex_lock(&ha->vport_lock); 3026 while (ha->cur_vport_count) { 3027 spin_lock_irqsave(&ha->vport_slock, flags); 3028 3029 BUG_ON(base_vha->list.next == &ha->vp_list); 3030 /* This assumes first entry in ha->vp_list is always base vha */ 3031 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3032 scsi_host = scsi_host_get(vha->host); 3033 3034 spin_unlock_irqrestore(&ha->vport_slock, flags); 3035 mutex_unlock(&ha->vport_lock); 3036 3037 fc_vport_terminate(vha->fc_vport); 3038 scsi_host_put(vha->host); 3039 3040 mutex_lock(&ha->vport_lock); 3041 } 3042 mutex_unlock(&ha->vport_lock); 3043 } 3044 3045 /* Stops all deferred work threads */ 3046 static void 3047 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3048 { 3049 /* Flush the work queue and remove it */ 3050 if (ha->wq) { 3051 flush_workqueue(ha->wq); 3052 destroy_workqueue(ha->wq); 3053 ha->wq = NULL; 3054 } 3055 3056 /* Cancel all work and destroy DPC workqueues */ 3057 if (ha->dpc_lp_wq) { 3058 cancel_work_sync(&ha->idc_aen); 3059 destroy_workqueue(ha->dpc_lp_wq); 3060 ha->dpc_lp_wq = NULL; 3061 } 3062 3063 if (ha->dpc_hp_wq) { 3064 cancel_work_sync(&ha->nic_core_reset); 3065 cancel_work_sync(&ha->idc_state_handler); 3066 cancel_work_sync(&ha->nic_core_unrecoverable); 3067 destroy_workqueue(ha->dpc_hp_wq); 3068 ha->dpc_hp_wq = NULL; 3069 } 3070 3071 /* Kill the kernel thread for this host */ 3072 if (ha->dpc_thread) { 3073 struct task_struct *t = ha->dpc_thread; 3074 3075 /* 3076 * qla2xxx_wake_dpc checks for ->dpc_thread 3077 * so we need to zero it out. 3078 */ 3079 ha->dpc_thread = NULL; 3080 kthread_stop(t); 3081 } 3082 } 3083 3084 static void 3085 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3086 { 3087 if (IS_QLA82XX(ha)) { 3088 3089 iounmap((device_reg_t *)ha->nx_pcibase); 3090 if (!ql2xdbwr) 3091 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3092 } else { 3093 if (ha->iobase) 3094 iounmap(ha->iobase); 3095 3096 if (ha->cregbase) 3097 iounmap(ha->cregbase); 3098 3099 if (ha->mqiobase) 3100 iounmap(ha->mqiobase); 3101 3102 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3103 iounmap(ha->msixbase); 3104 } 3105 } 3106 3107 static void 3108 qla2x00_clear_drv_active(scsi_qla_host_t *vha) 3109 { 3110 struct qla_hw_data *ha = vha->hw; 3111 3112 if (IS_QLA8044(ha)) { 3113 qla8044_idc_lock(ha); 3114 qla8044_clear_drv_active(ha); 3115 qla8044_idc_unlock(ha); 3116 } else if (IS_QLA82XX(ha)) { 3117 qla82xx_idc_lock(ha); 3118 qla82xx_clear_drv_active(ha); 3119 qla82xx_idc_unlock(ha); 3120 } 3121 } 3122 3123 static void 3124 qla2x00_remove_one(struct pci_dev *pdev) 3125 { 3126 scsi_qla_host_t *base_vha; 3127 struct qla_hw_data *ha; 3128 3129 /* 3130 * If the PCI device is disabled that means that probe failed and any 3131 * resources should be have cleaned up on probe exit. 3132 */ 3133 if (!atomic_read(&pdev->enable_cnt)) 3134 return; 3135 3136 base_vha = pci_get_drvdata(pdev); 3137 ha = base_vha->hw; 3138 3139 set_bit(UNLOADING, &base_vha->dpc_flags); 3140 3141 if (IS_QLAFX00(ha)) 3142 qlafx00_driver_shutdown(base_vha, 20); 3143 3144 qla2x00_delete_all_vps(ha, base_vha); 3145 3146 if (IS_QLA8031(ha)) { 3147 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3148 "Clearing fcoe driver presence.\n"); 3149 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3150 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3151 "Error while clearing DRV-Presence.\n"); 3152 } 3153 3154 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3155 3156 qla2x00_dfs_remove(base_vha); 3157 3158 qla84xx_put_chip(base_vha); 3159 3160 /* Disable timer */ 3161 if (base_vha->timer_active) 3162 qla2x00_stop_timer(base_vha); 3163 3164 base_vha->flags.online = 0; 3165 3166 qla2x00_destroy_deferred_work(ha); 3167 3168 qlt_remove_target(ha, base_vha); 3169 3170 qla2x00_free_sysfs_attr(base_vha, true); 3171 3172 fc_remove_host(base_vha->host); 3173 3174 scsi_remove_host(base_vha->host); 3175 3176 qla2x00_free_device(base_vha); 3177 3178 scsi_host_put(base_vha->host); 3179 3180 qla2x00_clear_drv_active(base_vha); 3181 3182 qla2x00_unmap_iobases(ha); 3183 3184 pci_release_selected_regions(ha->pdev, ha->bars); 3185 kfree(ha); 3186 ha = NULL; 3187 3188 pci_disable_pcie_error_reporting(pdev); 3189 3190 pci_disable_device(pdev); 3191 } 3192 3193 static void 3194 qla2x00_free_device(scsi_qla_host_t *vha) 3195 { 3196 struct qla_hw_data *ha = vha->hw; 3197 3198 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3199 3200 /* Disable timer */ 3201 if (vha->timer_active) 3202 qla2x00_stop_timer(vha); 3203 3204 qla25xx_delete_queues(vha); 3205 3206 if (ha->flags.fce_enabled) 3207 qla2x00_disable_fce_trace(vha, NULL, NULL); 3208 3209 if (ha->eft) 3210 qla2x00_disable_eft_trace(vha); 3211 3212 /* Stop currently executing firmware. */ 3213 qla2x00_try_to_stop_firmware(vha); 3214 3215 vha->flags.online = 0; 3216 3217 /* turn-off interrupts on the card */ 3218 if (ha->interrupts_on) { 3219 vha->flags.init_done = 0; 3220 ha->isp_ops->disable_intrs(ha); 3221 } 3222 3223 qla2x00_free_irqs(vha); 3224 3225 qla2x00_free_fcports(vha); 3226 3227 qla2x00_mem_free(ha); 3228 3229 qla82xx_md_free(vha); 3230 3231 qla2x00_free_queues(ha); 3232 } 3233 3234 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3235 { 3236 fc_port_t *fcport, *tfcport; 3237 3238 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3239 list_del(&fcport->list); 3240 qla2x00_clear_loop_id(fcport); 3241 kfree(fcport); 3242 fcport = NULL; 3243 } 3244 } 3245 3246 static inline void 3247 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3248 int defer) 3249 { 3250 struct fc_rport *rport; 3251 scsi_qla_host_t *base_vha; 3252 unsigned long flags; 3253 3254 if (!fcport->rport) 3255 return; 3256 3257 rport = fcport->rport; 3258 if (defer) { 3259 base_vha = pci_get_drvdata(vha->hw->pdev); 3260 spin_lock_irqsave(vha->host->host_lock, flags); 3261 fcport->drport = rport; 3262 spin_unlock_irqrestore(vha->host->host_lock, flags); 3263 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3264 qla2xxx_wake_dpc(base_vha); 3265 } else { 3266 fc_remote_port_delete(rport); 3267 qlt_fc_port_deleted(vha, fcport); 3268 } 3269 } 3270 3271 /* 3272 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3273 * 3274 * Input: ha = adapter block pointer. fcport = port structure pointer. 3275 * 3276 * Return: None. 3277 * 3278 * Context: 3279 */ 3280 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3281 int do_login, int defer) 3282 { 3283 if (IS_QLAFX00(vha->hw)) { 3284 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3285 qla2x00_schedule_rport_del(vha, fcport, defer); 3286 return; 3287 } 3288 3289 if (atomic_read(&fcport->state) == FCS_ONLINE && 3290 vha->vp_idx == fcport->vha->vp_idx) { 3291 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3292 qla2x00_schedule_rport_del(vha, fcport, defer); 3293 } 3294 /* 3295 * We may need to retry the login, so don't change the state of the 3296 * port but do the retries. 3297 */ 3298 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3299 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3300 3301 if (!do_login) 3302 return; 3303 3304 if (fcport->login_retry == 0) { 3305 fcport->login_retry = vha->hw->login_retry_count; 3306 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3307 3308 ql_dbg(ql_dbg_disc, vha, 0x2067, 3309 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3310 fcport->port_name, fcport->loop_id, fcport->login_retry); 3311 } 3312 } 3313 3314 /* 3315 * qla2x00_mark_all_devices_lost 3316 * Updates fcport state when device goes offline. 3317 * 3318 * Input: 3319 * ha = adapter block pointer. 3320 * fcport = port structure pointer. 3321 * 3322 * Return: 3323 * None. 3324 * 3325 * Context: 3326 */ 3327 void 3328 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3329 { 3330 fc_port_t *fcport; 3331 3332 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3333 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3334 continue; 3335 3336 /* 3337 * No point in marking the device as lost, if the device is 3338 * already DEAD. 3339 */ 3340 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3341 continue; 3342 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3343 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3344 if (defer) 3345 qla2x00_schedule_rport_del(vha, fcport, defer); 3346 else if (vha->vp_idx == fcport->vha->vp_idx) 3347 qla2x00_schedule_rport_del(vha, fcport, defer); 3348 } 3349 } 3350 } 3351 3352 /* 3353 * qla2x00_mem_alloc 3354 * Allocates adapter memory. 3355 * 3356 * Returns: 3357 * 0 = success. 3358 * !0 = failure. 3359 */ 3360 static int 3361 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3362 struct req_que **req, struct rsp_que **rsp) 3363 { 3364 char name[16]; 3365 3366 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3367 &ha->init_cb_dma, GFP_KERNEL); 3368 if (!ha->init_cb) 3369 goto fail; 3370 3371 if (qlt_mem_alloc(ha) < 0) 3372 goto fail_free_init_cb; 3373 3374 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3375 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3376 if (!ha->gid_list) 3377 goto fail_free_tgt_mem; 3378 3379 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3380 if (!ha->srb_mempool) 3381 goto fail_free_gid_list; 3382 3383 if (IS_P3P_TYPE(ha)) { 3384 /* Allocate cache for CT6 Ctx. */ 3385 if (!ctx_cachep) { 3386 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3387 sizeof(struct ct6_dsd), 0, 3388 SLAB_HWCACHE_ALIGN, NULL); 3389 if (!ctx_cachep) 3390 goto fail_free_gid_list; 3391 } 3392 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3393 ctx_cachep); 3394 if (!ha->ctx_mempool) 3395 goto fail_free_srb_mempool; 3396 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3397 "ctx_cachep=%p ctx_mempool=%p.\n", 3398 ctx_cachep, ha->ctx_mempool); 3399 } 3400 3401 /* Get memory for cached NVRAM */ 3402 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3403 if (!ha->nvram) 3404 goto fail_free_ctx_mempool; 3405 3406 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3407 ha->pdev->device); 3408 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3409 DMA_POOL_SIZE, 8, 0); 3410 if (!ha->s_dma_pool) 3411 goto fail_free_nvram; 3412 3413 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3414 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3415 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3416 3417 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3418 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3419 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3420 if (!ha->dl_dma_pool) { 3421 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3422 "Failed to allocate memory for dl_dma_pool.\n"); 3423 goto fail_s_dma_pool; 3424 } 3425 3426 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3427 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3428 if (!ha->fcp_cmnd_dma_pool) { 3429 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3430 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3431 goto fail_dl_dma_pool; 3432 } 3433 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3434 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3435 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3436 } 3437 3438 /* Allocate memory for SNS commands */ 3439 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3440 /* Get consistent memory allocated for SNS commands */ 3441 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3442 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3443 if (!ha->sns_cmd) 3444 goto fail_dma_pool; 3445 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3446 "sns_cmd: %p.\n", ha->sns_cmd); 3447 } else { 3448 /* Get consistent memory allocated for MS IOCB */ 3449 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3450 &ha->ms_iocb_dma); 3451 if (!ha->ms_iocb) 3452 goto fail_dma_pool; 3453 /* Get consistent memory allocated for CT SNS commands */ 3454 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3455 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3456 if (!ha->ct_sns) 3457 goto fail_free_ms_iocb; 3458 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3459 "ms_iocb=%p ct_sns=%p.\n", 3460 ha->ms_iocb, ha->ct_sns); 3461 } 3462 3463 /* Allocate memory for request ring */ 3464 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3465 if (!*req) { 3466 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3467 "Failed to allocate memory for req.\n"); 3468 goto fail_req; 3469 } 3470 (*req)->length = req_len; 3471 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3472 ((*req)->length + 1) * sizeof(request_t), 3473 &(*req)->dma, GFP_KERNEL); 3474 if (!(*req)->ring) { 3475 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3476 "Failed to allocate memory for req_ring.\n"); 3477 goto fail_req_ring; 3478 } 3479 /* Allocate memory for response ring */ 3480 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3481 if (!*rsp) { 3482 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3483 "Failed to allocate memory for rsp.\n"); 3484 goto fail_rsp; 3485 } 3486 (*rsp)->hw = ha; 3487 (*rsp)->length = rsp_len; 3488 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3489 ((*rsp)->length + 1) * sizeof(response_t), 3490 &(*rsp)->dma, GFP_KERNEL); 3491 if (!(*rsp)->ring) { 3492 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3493 "Failed to allocate memory for rsp_ring.\n"); 3494 goto fail_rsp_ring; 3495 } 3496 (*req)->rsp = *rsp; 3497 (*rsp)->req = *req; 3498 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3499 "req=%p req->length=%d req->ring=%p rsp=%p " 3500 "rsp->length=%d rsp->ring=%p.\n", 3501 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3502 (*rsp)->ring); 3503 /* Allocate memory for NVRAM data for vports */ 3504 if (ha->nvram_npiv_size) { 3505 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3506 ha->nvram_npiv_size, GFP_KERNEL); 3507 if (!ha->npiv_info) { 3508 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3509 "Failed to allocate memory for npiv_info.\n"); 3510 goto fail_npiv_info; 3511 } 3512 } else 3513 ha->npiv_info = NULL; 3514 3515 /* Get consistent memory allocated for EX-INIT-CB. */ 3516 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3517 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3518 &ha->ex_init_cb_dma); 3519 if (!ha->ex_init_cb) 3520 goto fail_ex_init_cb; 3521 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3522 "ex_init_cb=%p.\n", ha->ex_init_cb); 3523 } 3524 3525 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3526 3527 /* Get consistent memory allocated for Async Port-Database. */ 3528 if (!IS_FWI2_CAPABLE(ha)) { 3529 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3530 &ha->async_pd_dma); 3531 if (!ha->async_pd) 3532 goto fail_async_pd; 3533 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3534 "async_pd=%p.\n", ha->async_pd); 3535 } 3536 3537 INIT_LIST_HEAD(&ha->vp_list); 3538 3539 /* Allocate memory for our loop_id bitmap */ 3540 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3541 GFP_KERNEL); 3542 if (!ha->loop_id_map) 3543 goto fail_async_pd; 3544 else { 3545 qla2x00_set_reserved_loop_ids(ha); 3546 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3547 "loop_id_map=%p.\n", ha->loop_id_map); 3548 } 3549 3550 return 0; 3551 3552 fail_async_pd: 3553 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3554 fail_ex_init_cb: 3555 kfree(ha->npiv_info); 3556 fail_npiv_info: 3557 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3558 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3559 (*rsp)->ring = NULL; 3560 (*rsp)->dma = 0; 3561 fail_rsp_ring: 3562 kfree(*rsp); 3563 fail_rsp: 3564 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3565 sizeof(request_t), (*req)->ring, (*req)->dma); 3566 (*req)->ring = NULL; 3567 (*req)->dma = 0; 3568 fail_req_ring: 3569 kfree(*req); 3570 fail_req: 3571 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3572 ha->ct_sns, ha->ct_sns_dma); 3573 ha->ct_sns = NULL; 3574 ha->ct_sns_dma = 0; 3575 fail_free_ms_iocb: 3576 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3577 ha->ms_iocb = NULL; 3578 ha->ms_iocb_dma = 0; 3579 fail_dma_pool: 3580 if (IS_QLA82XX(ha) || ql2xenabledif) { 3581 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3582 ha->fcp_cmnd_dma_pool = NULL; 3583 } 3584 fail_dl_dma_pool: 3585 if (IS_QLA82XX(ha) || ql2xenabledif) { 3586 dma_pool_destroy(ha->dl_dma_pool); 3587 ha->dl_dma_pool = NULL; 3588 } 3589 fail_s_dma_pool: 3590 dma_pool_destroy(ha->s_dma_pool); 3591 ha->s_dma_pool = NULL; 3592 fail_free_nvram: 3593 kfree(ha->nvram); 3594 ha->nvram = NULL; 3595 fail_free_ctx_mempool: 3596 mempool_destroy(ha->ctx_mempool); 3597 ha->ctx_mempool = NULL; 3598 fail_free_srb_mempool: 3599 mempool_destroy(ha->srb_mempool); 3600 ha->srb_mempool = NULL; 3601 fail_free_gid_list: 3602 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3603 ha->gid_list, 3604 ha->gid_list_dma); 3605 ha->gid_list = NULL; 3606 ha->gid_list_dma = 0; 3607 fail_free_tgt_mem: 3608 qlt_mem_free(ha); 3609 fail_free_init_cb: 3610 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3611 ha->init_cb_dma); 3612 ha->init_cb = NULL; 3613 ha->init_cb_dma = 0; 3614 fail: 3615 ql_log(ql_log_fatal, NULL, 0x0030, 3616 "Memory allocation failure.\n"); 3617 return -ENOMEM; 3618 } 3619 3620 /* 3621 * qla2x00_free_fw_dump 3622 * Frees fw dump stuff. 3623 * 3624 * Input: 3625 * ha = adapter block pointer 3626 */ 3627 static void 3628 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3629 { 3630 if (ha->fce) 3631 dma_free_coherent(&ha->pdev->dev, 3632 FCE_SIZE, ha->fce, ha->fce_dma); 3633 3634 if (ha->eft) 3635 dma_free_coherent(&ha->pdev->dev, 3636 EFT_SIZE, ha->eft, ha->eft_dma); 3637 3638 if (ha->fw_dump) 3639 vfree(ha->fw_dump); 3640 if (ha->fw_dump_template) 3641 vfree(ha->fw_dump_template); 3642 3643 ha->fce = NULL; 3644 ha->fce_dma = 0; 3645 ha->eft = NULL; 3646 ha->eft_dma = 0; 3647 ha->fw_dumped = 0; 3648 ha->fw_dump_reading = 0; 3649 ha->fw_dump = NULL; 3650 ha->fw_dump_len = 0; 3651 ha->fw_dump_template = NULL; 3652 ha->fw_dump_template_len = 0; 3653 } 3654 3655 /* 3656 * qla2x00_mem_free 3657 * Frees all adapter allocated memory. 3658 * 3659 * Input: 3660 * ha = adapter block pointer. 3661 */ 3662 static void 3663 qla2x00_mem_free(struct qla_hw_data *ha) 3664 { 3665 qla2x00_free_fw_dump(ha); 3666 3667 if (ha->mctp_dump) 3668 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3669 ha->mctp_dump_dma); 3670 3671 if (ha->srb_mempool) 3672 mempool_destroy(ha->srb_mempool); 3673 3674 if (ha->dcbx_tlv) 3675 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3676 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3677 3678 if (ha->xgmac_data) 3679 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3680 ha->xgmac_data, ha->xgmac_data_dma); 3681 3682 if (ha->sns_cmd) 3683 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3684 ha->sns_cmd, ha->sns_cmd_dma); 3685 3686 if (ha->ct_sns) 3687 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3688 ha->ct_sns, ha->ct_sns_dma); 3689 3690 if (ha->sfp_data) 3691 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3692 3693 if (ha->ms_iocb) 3694 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3695 3696 if (ha->ex_init_cb) 3697 dma_pool_free(ha->s_dma_pool, 3698 ha->ex_init_cb, ha->ex_init_cb_dma); 3699 3700 if (ha->async_pd) 3701 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3702 3703 if (ha->s_dma_pool) 3704 dma_pool_destroy(ha->s_dma_pool); 3705 3706 if (ha->gid_list) 3707 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3708 ha->gid_list, ha->gid_list_dma); 3709 3710 if (IS_QLA82XX(ha)) { 3711 if (!list_empty(&ha->gbl_dsd_list)) { 3712 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3713 3714 /* clean up allocated prev pool */ 3715 list_for_each_entry_safe(dsd_ptr, 3716 tdsd_ptr, &ha->gbl_dsd_list, list) { 3717 dma_pool_free(ha->dl_dma_pool, 3718 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3719 list_del(&dsd_ptr->list); 3720 kfree(dsd_ptr); 3721 } 3722 } 3723 } 3724 3725 if (ha->dl_dma_pool) 3726 dma_pool_destroy(ha->dl_dma_pool); 3727 3728 if (ha->fcp_cmnd_dma_pool) 3729 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3730 3731 if (ha->ctx_mempool) 3732 mempool_destroy(ha->ctx_mempool); 3733 3734 qlt_mem_free(ha); 3735 3736 if (ha->init_cb) 3737 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3738 ha->init_cb, ha->init_cb_dma); 3739 vfree(ha->optrom_buffer); 3740 kfree(ha->nvram); 3741 kfree(ha->npiv_info); 3742 kfree(ha->swl); 3743 kfree(ha->loop_id_map); 3744 3745 ha->srb_mempool = NULL; 3746 ha->ctx_mempool = NULL; 3747 ha->sns_cmd = NULL; 3748 ha->sns_cmd_dma = 0; 3749 ha->ct_sns = NULL; 3750 ha->ct_sns_dma = 0; 3751 ha->ms_iocb = NULL; 3752 ha->ms_iocb_dma = 0; 3753 ha->init_cb = NULL; 3754 ha->init_cb_dma = 0; 3755 ha->ex_init_cb = NULL; 3756 ha->ex_init_cb_dma = 0; 3757 ha->async_pd = NULL; 3758 ha->async_pd_dma = 0; 3759 3760 ha->s_dma_pool = NULL; 3761 ha->dl_dma_pool = NULL; 3762 ha->fcp_cmnd_dma_pool = NULL; 3763 3764 ha->gid_list = NULL; 3765 ha->gid_list_dma = 0; 3766 3767 ha->tgt.atio_ring = NULL; 3768 ha->tgt.atio_dma = 0; 3769 ha->tgt.tgt_vp_map = NULL; 3770 } 3771 3772 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3773 struct qla_hw_data *ha) 3774 { 3775 struct Scsi_Host *host; 3776 struct scsi_qla_host *vha = NULL; 3777 3778 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3779 if (host == NULL) { 3780 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3781 "Failed to allocate host from the scsi layer, aborting.\n"); 3782 goto fail; 3783 } 3784 3785 /* Clear our data area */ 3786 vha = shost_priv(host); 3787 memset(vha, 0, sizeof(scsi_qla_host_t)); 3788 3789 vha->host = host; 3790 vha->host_no = host->host_no; 3791 vha->hw = ha; 3792 3793 INIT_LIST_HEAD(&vha->vp_fcports); 3794 INIT_LIST_HEAD(&vha->work_list); 3795 INIT_LIST_HEAD(&vha->list); 3796 3797 spin_lock_init(&vha->work_lock); 3798 3799 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3800 ql_dbg(ql_dbg_init, vha, 0x0041, 3801 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3802 vha->host, vha->hw, vha, 3803 dev_name(&(ha->pdev->dev))); 3804 3805 return vha; 3806 3807 fail: 3808 return vha; 3809 } 3810 3811 static struct qla_work_evt * 3812 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3813 { 3814 struct qla_work_evt *e; 3815 uint8_t bail; 3816 3817 QLA_VHA_MARK_BUSY(vha, bail); 3818 if (bail) 3819 return NULL; 3820 3821 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3822 if (!e) { 3823 QLA_VHA_MARK_NOT_BUSY(vha); 3824 return NULL; 3825 } 3826 3827 INIT_LIST_HEAD(&e->list); 3828 e->type = type; 3829 e->flags = QLA_EVT_FLAG_FREE; 3830 return e; 3831 } 3832 3833 static int 3834 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3835 { 3836 unsigned long flags; 3837 3838 spin_lock_irqsave(&vha->work_lock, flags); 3839 list_add_tail(&e->list, &vha->work_list); 3840 spin_unlock_irqrestore(&vha->work_lock, flags); 3841 qla2xxx_wake_dpc(vha); 3842 3843 return QLA_SUCCESS; 3844 } 3845 3846 int 3847 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3848 u32 data) 3849 { 3850 struct qla_work_evt *e; 3851 3852 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3853 if (!e) 3854 return QLA_FUNCTION_FAILED; 3855 3856 e->u.aen.code = code; 3857 e->u.aen.data = data; 3858 return qla2x00_post_work(vha, e); 3859 } 3860 3861 int 3862 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3863 { 3864 struct qla_work_evt *e; 3865 3866 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3867 if (!e) 3868 return QLA_FUNCTION_FAILED; 3869 3870 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3871 return qla2x00_post_work(vha, e); 3872 } 3873 3874 #define qla2x00_post_async_work(name, type) \ 3875 int qla2x00_post_async_##name##_work( \ 3876 struct scsi_qla_host *vha, \ 3877 fc_port_t *fcport, uint16_t *data) \ 3878 { \ 3879 struct qla_work_evt *e; \ 3880 \ 3881 e = qla2x00_alloc_work(vha, type); \ 3882 if (!e) \ 3883 return QLA_FUNCTION_FAILED; \ 3884 \ 3885 e->u.logio.fcport = fcport; \ 3886 if (data) { \ 3887 e->u.logio.data[0] = data[0]; \ 3888 e->u.logio.data[1] = data[1]; \ 3889 } \ 3890 return qla2x00_post_work(vha, e); \ 3891 } 3892 3893 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3894 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3895 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3896 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3897 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3898 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3899 3900 int 3901 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3902 { 3903 struct qla_work_evt *e; 3904 3905 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3906 if (!e) 3907 return QLA_FUNCTION_FAILED; 3908 3909 e->u.uevent.code = code; 3910 return qla2x00_post_work(vha, e); 3911 } 3912 3913 static void 3914 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3915 { 3916 char event_string[40]; 3917 char *envp[] = { event_string, NULL }; 3918 3919 switch (code) { 3920 case QLA_UEVENT_CODE_FW_DUMP: 3921 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3922 vha->host_no); 3923 break; 3924 default: 3925 /* do nothing */ 3926 break; 3927 } 3928 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3929 } 3930 3931 int 3932 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 3933 uint32_t *data, int cnt) 3934 { 3935 struct qla_work_evt *e; 3936 3937 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 3938 if (!e) 3939 return QLA_FUNCTION_FAILED; 3940 3941 e->u.aenfx.evtcode = evtcode; 3942 e->u.aenfx.count = cnt; 3943 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 3944 return qla2x00_post_work(vha, e); 3945 } 3946 3947 void 3948 qla2x00_do_work(struct scsi_qla_host *vha) 3949 { 3950 struct qla_work_evt *e, *tmp; 3951 unsigned long flags; 3952 LIST_HEAD(work); 3953 3954 spin_lock_irqsave(&vha->work_lock, flags); 3955 list_splice_init(&vha->work_list, &work); 3956 spin_unlock_irqrestore(&vha->work_lock, flags); 3957 3958 list_for_each_entry_safe(e, tmp, &work, list) { 3959 list_del_init(&e->list); 3960 3961 switch (e->type) { 3962 case QLA_EVT_AEN: 3963 fc_host_post_event(vha->host, fc_get_event_number(), 3964 e->u.aen.code, e->u.aen.data); 3965 break; 3966 case QLA_EVT_IDC_ACK: 3967 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3968 break; 3969 case QLA_EVT_ASYNC_LOGIN: 3970 qla2x00_async_login(vha, e->u.logio.fcport, 3971 e->u.logio.data); 3972 break; 3973 case QLA_EVT_ASYNC_LOGIN_DONE: 3974 qla2x00_async_login_done(vha, e->u.logio.fcport, 3975 e->u.logio.data); 3976 break; 3977 case QLA_EVT_ASYNC_LOGOUT: 3978 qla2x00_async_logout(vha, e->u.logio.fcport); 3979 break; 3980 case QLA_EVT_ASYNC_LOGOUT_DONE: 3981 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3982 e->u.logio.data); 3983 break; 3984 case QLA_EVT_ASYNC_ADISC: 3985 qla2x00_async_adisc(vha, e->u.logio.fcport, 3986 e->u.logio.data); 3987 break; 3988 case QLA_EVT_ASYNC_ADISC_DONE: 3989 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3990 e->u.logio.data); 3991 break; 3992 case QLA_EVT_UEVENT: 3993 qla2x00_uevent_emit(vha, e->u.uevent.code); 3994 break; 3995 case QLA_EVT_AENFX: 3996 qlafx00_process_aen(vha, e); 3997 break; 3998 } 3999 if (e->flags & QLA_EVT_FLAG_FREE) 4000 kfree(e); 4001 4002 /* For each work completed decrement vha ref count */ 4003 QLA_VHA_MARK_NOT_BUSY(vha); 4004 } 4005 } 4006 4007 /* Relogins all the fcports of a vport 4008 * Context: dpc thread 4009 */ 4010 void qla2x00_relogin(struct scsi_qla_host *vha) 4011 { 4012 fc_port_t *fcport; 4013 int status; 4014 uint16_t next_loopid = 0; 4015 struct qla_hw_data *ha = vha->hw; 4016 uint16_t data[2]; 4017 4018 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4019 /* 4020 * If the port is not ONLINE then try to login 4021 * to it if we haven't run out of retries. 4022 */ 4023 if (atomic_read(&fcport->state) != FCS_ONLINE && 4024 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4025 fcport->login_retry--; 4026 if (fcport->flags & FCF_FABRIC_DEVICE) { 4027 if (fcport->flags & FCF_FCP2_DEVICE) 4028 ha->isp_ops->fabric_logout(vha, 4029 fcport->loop_id, 4030 fcport->d_id.b.domain, 4031 fcport->d_id.b.area, 4032 fcport->d_id.b.al_pa); 4033 4034 if (fcport->loop_id == FC_NO_LOOP_ID) { 4035 fcport->loop_id = next_loopid = 4036 ha->min_external_loopid; 4037 status = qla2x00_find_new_loop_id( 4038 vha, fcport); 4039 if (status != QLA_SUCCESS) { 4040 /* Ran out of IDs to use */ 4041 break; 4042 } 4043 } 4044 4045 if (IS_ALOGIO_CAPABLE(ha)) { 4046 fcport->flags |= FCF_ASYNC_SENT; 4047 data[0] = 0; 4048 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4049 status = qla2x00_post_async_login_work( 4050 vha, fcport, data); 4051 if (status == QLA_SUCCESS) 4052 continue; 4053 /* Attempt a retry. */ 4054 status = 1; 4055 } else { 4056 status = qla2x00_fabric_login(vha, 4057 fcport, &next_loopid); 4058 if (status == QLA_SUCCESS) { 4059 int status2; 4060 uint8_t opts; 4061 4062 opts = 0; 4063 if (fcport->flags & 4064 FCF_FCP2_DEVICE) 4065 opts |= BIT_1; 4066 status2 = 4067 qla2x00_get_port_database( 4068 vha, fcport, opts); 4069 if (status2 != QLA_SUCCESS) 4070 status = 1; 4071 } 4072 } 4073 } else 4074 status = qla2x00_local_device_login(vha, 4075 fcport); 4076 4077 if (status == QLA_SUCCESS) { 4078 fcport->old_loop_id = fcport->loop_id; 4079 4080 ql_dbg(ql_dbg_disc, vha, 0x2003, 4081 "Port login OK: logged in ID 0x%x.\n", 4082 fcport->loop_id); 4083 4084 qla2x00_update_fcport(vha, fcport); 4085 4086 } else if (status == 1) { 4087 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4088 /* retry the login again */ 4089 ql_dbg(ql_dbg_disc, vha, 0x2007, 4090 "Retrying %d login again loop_id 0x%x.\n", 4091 fcport->login_retry, fcport->loop_id); 4092 } else { 4093 fcport->login_retry = 0; 4094 } 4095 4096 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4097 qla2x00_clear_loop_id(fcport); 4098 } 4099 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4100 break; 4101 } 4102 } 4103 4104 /* Schedule work on any of the dpc-workqueues */ 4105 void 4106 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4107 { 4108 struct qla_hw_data *ha = base_vha->hw; 4109 4110 switch (work_code) { 4111 case MBA_IDC_AEN: /* 0x8200 */ 4112 if (ha->dpc_lp_wq) 4113 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4114 break; 4115 4116 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4117 if (!ha->flags.nic_core_reset_hdlr_active) { 4118 if (ha->dpc_hp_wq) 4119 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4120 } else 4121 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4122 "NIC Core reset is already active. Skip " 4123 "scheduling it again.\n"); 4124 break; 4125 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4126 if (ha->dpc_hp_wq) 4127 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4128 break; 4129 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4130 if (ha->dpc_hp_wq) 4131 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4132 break; 4133 default: 4134 ql_log(ql_log_warn, base_vha, 0xb05f, 4135 "Unknow work-code=0x%x.\n", work_code); 4136 } 4137 4138 return; 4139 } 4140 4141 /* Work: Perform NIC Core Unrecoverable state handling */ 4142 void 4143 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4144 { 4145 struct qla_hw_data *ha = 4146 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4147 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4148 uint32_t dev_state = 0; 4149 4150 qla83xx_idc_lock(base_vha, 0); 4151 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4152 qla83xx_reset_ownership(base_vha); 4153 if (ha->flags.nic_core_reset_owner) { 4154 ha->flags.nic_core_reset_owner = 0; 4155 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4156 QLA8XXX_DEV_FAILED); 4157 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4158 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4159 } 4160 qla83xx_idc_unlock(base_vha, 0); 4161 } 4162 4163 /* Work: Execute IDC state handler */ 4164 void 4165 qla83xx_idc_state_handler_work(struct work_struct *work) 4166 { 4167 struct qla_hw_data *ha = 4168 container_of(work, struct qla_hw_data, idc_state_handler); 4169 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4170 uint32_t dev_state = 0; 4171 4172 qla83xx_idc_lock(base_vha, 0); 4173 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4174 if (dev_state == QLA8XXX_DEV_FAILED || 4175 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4176 qla83xx_idc_state_handler(base_vha); 4177 qla83xx_idc_unlock(base_vha, 0); 4178 } 4179 4180 static int 4181 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4182 { 4183 int rval = QLA_SUCCESS; 4184 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4185 uint32_t heart_beat_counter1, heart_beat_counter2; 4186 4187 do { 4188 if (time_after(jiffies, heart_beat_wait)) { 4189 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4190 "Nic Core f/w is not alive.\n"); 4191 rval = QLA_FUNCTION_FAILED; 4192 break; 4193 } 4194 4195 qla83xx_idc_lock(base_vha, 0); 4196 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4197 &heart_beat_counter1); 4198 qla83xx_idc_unlock(base_vha, 0); 4199 msleep(100); 4200 qla83xx_idc_lock(base_vha, 0); 4201 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4202 &heart_beat_counter2); 4203 qla83xx_idc_unlock(base_vha, 0); 4204 } while (heart_beat_counter1 == heart_beat_counter2); 4205 4206 return rval; 4207 } 4208 4209 /* Work: Perform NIC Core Reset handling */ 4210 void 4211 qla83xx_nic_core_reset_work(struct work_struct *work) 4212 { 4213 struct qla_hw_data *ha = 4214 container_of(work, struct qla_hw_data, nic_core_reset); 4215 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4216 uint32_t dev_state = 0; 4217 4218 if (IS_QLA2031(ha)) { 4219 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4220 ql_log(ql_log_warn, base_vha, 0xb081, 4221 "Failed to dump mctp\n"); 4222 return; 4223 } 4224 4225 if (!ha->flags.nic_core_reset_hdlr_active) { 4226 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4227 qla83xx_idc_lock(base_vha, 0); 4228 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4229 &dev_state); 4230 qla83xx_idc_unlock(base_vha, 0); 4231 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4232 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4233 "Nic Core f/w is alive.\n"); 4234 return; 4235 } 4236 } 4237 4238 ha->flags.nic_core_reset_hdlr_active = 1; 4239 if (qla83xx_nic_core_reset(base_vha)) { 4240 /* NIC Core reset failed. */ 4241 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4242 "NIC Core reset failed.\n"); 4243 } 4244 ha->flags.nic_core_reset_hdlr_active = 0; 4245 } 4246 } 4247 4248 /* Work: Handle 8200 IDC aens */ 4249 void 4250 qla83xx_service_idc_aen(struct work_struct *work) 4251 { 4252 struct qla_hw_data *ha = 4253 container_of(work, struct qla_hw_data, idc_aen); 4254 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4255 uint32_t dev_state, idc_control; 4256 4257 qla83xx_idc_lock(base_vha, 0); 4258 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4259 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4260 qla83xx_idc_unlock(base_vha, 0); 4261 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4262 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4263 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4264 "Application requested NIC Core Reset.\n"); 4265 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4266 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4267 QLA_SUCCESS) { 4268 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4269 "Other protocol driver requested NIC Core Reset.\n"); 4270 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4271 } 4272 } else if (dev_state == QLA8XXX_DEV_FAILED || 4273 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4274 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4275 } 4276 } 4277 4278 static void 4279 qla83xx_wait_logic(void) 4280 { 4281 int i; 4282 4283 /* Yield CPU */ 4284 if (!in_interrupt()) { 4285 /* 4286 * Wait about 200ms before retrying again. 4287 * This controls the number of retries for single 4288 * lock operation. 4289 */ 4290 msleep(100); 4291 schedule(); 4292 } else { 4293 for (i = 0; i < 20; i++) 4294 cpu_relax(); /* This a nop instr on i386 */ 4295 } 4296 } 4297 4298 static int 4299 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4300 { 4301 int rval; 4302 uint32_t data; 4303 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4304 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4305 struct qla_hw_data *ha = base_vha->hw; 4306 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4307 "Trying force recovery of the IDC lock.\n"); 4308 4309 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4310 if (rval) 4311 return rval; 4312 4313 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4314 return QLA_SUCCESS; 4315 } else { 4316 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4317 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4318 data); 4319 if (rval) 4320 return rval; 4321 4322 msleep(200); 4323 4324 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4325 &data); 4326 if (rval) 4327 return rval; 4328 4329 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4330 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4331 ~(idc_lck_rcvry_stage_mask)); 4332 rval = qla83xx_wr_reg(base_vha, 4333 QLA83XX_IDC_LOCK_RECOVERY, data); 4334 if (rval) 4335 return rval; 4336 4337 /* Forcefully perform IDC UnLock */ 4338 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4339 &data); 4340 if (rval) 4341 return rval; 4342 /* Clear lock-id by setting 0xff */ 4343 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4344 0xff); 4345 if (rval) 4346 return rval; 4347 /* Clear lock-recovery by setting 0x0 */ 4348 rval = qla83xx_wr_reg(base_vha, 4349 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4350 if (rval) 4351 return rval; 4352 } else 4353 return QLA_SUCCESS; 4354 } 4355 4356 return rval; 4357 } 4358 4359 static int 4360 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4361 { 4362 int rval = QLA_SUCCESS; 4363 uint32_t o_drv_lockid, n_drv_lockid; 4364 unsigned long lock_recovery_timeout; 4365 4366 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4367 retry_lockid: 4368 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4369 if (rval) 4370 goto exit; 4371 4372 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4373 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4374 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4375 return QLA_SUCCESS; 4376 else 4377 return QLA_FUNCTION_FAILED; 4378 } 4379 4380 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4381 if (rval) 4382 goto exit; 4383 4384 if (o_drv_lockid == n_drv_lockid) { 4385 qla83xx_wait_logic(); 4386 goto retry_lockid; 4387 } else 4388 return QLA_SUCCESS; 4389 4390 exit: 4391 return rval; 4392 } 4393 4394 void 4395 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4396 { 4397 uint16_t options = (requester_id << 15) | BIT_6; 4398 uint32_t data; 4399 uint32_t lock_owner; 4400 struct qla_hw_data *ha = base_vha->hw; 4401 4402 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4403 retry_lock: 4404 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4405 == QLA_SUCCESS) { 4406 if (data) { 4407 /* Setting lock-id to our function-number */ 4408 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4409 ha->portnum); 4410 } else { 4411 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4412 &lock_owner); 4413 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4414 "Failed to acquire IDC lock, acquired by %d, " 4415 "retrying...\n", lock_owner); 4416 4417 /* Retry/Perform IDC-Lock recovery */ 4418 if (qla83xx_idc_lock_recovery(base_vha) 4419 == QLA_SUCCESS) { 4420 qla83xx_wait_logic(); 4421 goto retry_lock; 4422 } else 4423 ql_log(ql_log_warn, base_vha, 0xb075, 4424 "IDC Lock recovery FAILED.\n"); 4425 } 4426 4427 } 4428 4429 return; 4430 4431 /* XXX: IDC-lock implementation using access-control mbx */ 4432 retry_lock2: 4433 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4434 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4435 "Failed to acquire IDC lock. retrying...\n"); 4436 /* Retry/Perform IDC-Lock recovery */ 4437 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4438 qla83xx_wait_logic(); 4439 goto retry_lock2; 4440 } else 4441 ql_log(ql_log_warn, base_vha, 0xb076, 4442 "IDC Lock recovery FAILED.\n"); 4443 } 4444 4445 return; 4446 } 4447 4448 void 4449 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4450 { 4451 uint16_t options = (requester_id << 15) | BIT_7, retry; 4452 uint32_t data; 4453 struct qla_hw_data *ha = base_vha->hw; 4454 4455 /* IDC-unlock implementation using driver-unlock/lock-id 4456 * remote registers 4457 */ 4458 retry = 0; 4459 retry_unlock: 4460 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4461 == QLA_SUCCESS) { 4462 if (data == ha->portnum) { 4463 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4464 /* Clearing lock-id by setting 0xff */ 4465 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4466 } else if (retry < 10) { 4467 /* SV: XXX: IDC unlock retrying needed here? */ 4468 4469 /* Retry for IDC-unlock */ 4470 qla83xx_wait_logic(); 4471 retry++; 4472 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4473 "Failed to release IDC lock, retyring=%d\n", retry); 4474 goto retry_unlock; 4475 } 4476 } else if (retry < 10) { 4477 /* Retry for IDC-unlock */ 4478 qla83xx_wait_logic(); 4479 retry++; 4480 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4481 "Failed to read drv-lockid, retyring=%d\n", retry); 4482 goto retry_unlock; 4483 } 4484 4485 return; 4486 4487 /* XXX: IDC-unlock implementation using access-control mbx */ 4488 retry = 0; 4489 retry_unlock2: 4490 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4491 if (retry < 10) { 4492 /* Retry for IDC-unlock */ 4493 qla83xx_wait_logic(); 4494 retry++; 4495 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4496 "Failed to release IDC lock, retyring=%d\n", retry); 4497 goto retry_unlock2; 4498 } 4499 } 4500 4501 return; 4502 } 4503 4504 int 4505 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4506 { 4507 int rval = QLA_SUCCESS; 4508 struct qla_hw_data *ha = vha->hw; 4509 uint32_t drv_presence; 4510 4511 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4512 if (rval == QLA_SUCCESS) { 4513 drv_presence |= (1 << ha->portnum); 4514 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4515 drv_presence); 4516 } 4517 4518 return rval; 4519 } 4520 4521 int 4522 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4523 { 4524 int rval = QLA_SUCCESS; 4525 4526 qla83xx_idc_lock(vha, 0); 4527 rval = __qla83xx_set_drv_presence(vha); 4528 qla83xx_idc_unlock(vha, 0); 4529 4530 return rval; 4531 } 4532 4533 int 4534 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4535 { 4536 int rval = QLA_SUCCESS; 4537 struct qla_hw_data *ha = vha->hw; 4538 uint32_t drv_presence; 4539 4540 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4541 if (rval == QLA_SUCCESS) { 4542 drv_presence &= ~(1 << ha->portnum); 4543 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4544 drv_presence); 4545 } 4546 4547 return rval; 4548 } 4549 4550 int 4551 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4552 { 4553 int rval = QLA_SUCCESS; 4554 4555 qla83xx_idc_lock(vha, 0); 4556 rval = __qla83xx_clear_drv_presence(vha); 4557 qla83xx_idc_unlock(vha, 0); 4558 4559 return rval; 4560 } 4561 4562 static void 4563 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4564 { 4565 struct qla_hw_data *ha = vha->hw; 4566 uint32_t drv_ack, drv_presence; 4567 unsigned long ack_timeout; 4568 4569 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4570 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4571 while (1) { 4572 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4573 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4574 if ((drv_ack & drv_presence) == drv_presence) 4575 break; 4576 4577 if (time_after_eq(jiffies, ack_timeout)) { 4578 ql_log(ql_log_warn, vha, 0xb067, 4579 "RESET ACK TIMEOUT! drv_presence=0x%x " 4580 "drv_ack=0x%x\n", drv_presence, drv_ack); 4581 /* 4582 * The function(s) which did not ack in time are forced 4583 * to withdraw any further participation in the IDC 4584 * reset. 4585 */ 4586 if (drv_ack != drv_presence) 4587 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4588 drv_ack); 4589 break; 4590 } 4591 4592 qla83xx_idc_unlock(vha, 0); 4593 msleep(1000); 4594 qla83xx_idc_lock(vha, 0); 4595 } 4596 4597 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4598 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4599 } 4600 4601 static int 4602 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4603 { 4604 int rval = QLA_SUCCESS; 4605 uint32_t idc_control; 4606 4607 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4608 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4609 4610 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4611 __qla83xx_get_idc_control(vha, &idc_control); 4612 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4613 __qla83xx_set_idc_control(vha, 0); 4614 4615 qla83xx_idc_unlock(vha, 0); 4616 rval = qla83xx_restart_nic_firmware(vha); 4617 qla83xx_idc_lock(vha, 0); 4618 4619 if (rval != QLA_SUCCESS) { 4620 ql_log(ql_log_fatal, vha, 0xb06a, 4621 "Failed to restart NIC f/w.\n"); 4622 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4623 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4624 } else { 4625 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4626 "Success in restarting nic f/w.\n"); 4627 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4628 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4629 } 4630 4631 return rval; 4632 } 4633 4634 /* Assumes idc_lock always held on entry */ 4635 int 4636 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4637 { 4638 struct qla_hw_data *ha = base_vha->hw; 4639 int rval = QLA_SUCCESS; 4640 unsigned long dev_init_timeout; 4641 uint32_t dev_state; 4642 4643 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4644 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4645 4646 while (1) { 4647 4648 if (time_after_eq(jiffies, dev_init_timeout)) { 4649 ql_log(ql_log_warn, base_vha, 0xb06e, 4650 "Initialization TIMEOUT!\n"); 4651 /* Init timeout. Disable further NIC Core 4652 * communication. 4653 */ 4654 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4655 QLA8XXX_DEV_FAILED); 4656 ql_log(ql_log_info, base_vha, 0xb06f, 4657 "HW State: FAILED.\n"); 4658 } 4659 4660 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4661 switch (dev_state) { 4662 case QLA8XXX_DEV_READY: 4663 if (ha->flags.nic_core_reset_owner) 4664 qla83xx_idc_audit(base_vha, 4665 IDC_AUDIT_COMPLETION); 4666 ha->flags.nic_core_reset_owner = 0; 4667 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4668 "Reset_owner reset by 0x%x.\n", 4669 ha->portnum); 4670 goto exit; 4671 case QLA8XXX_DEV_COLD: 4672 if (ha->flags.nic_core_reset_owner) 4673 rval = qla83xx_device_bootstrap(base_vha); 4674 else { 4675 /* Wait for AEN to change device-state */ 4676 qla83xx_idc_unlock(base_vha, 0); 4677 msleep(1000); 4678 qla83xx_idc_lock(base_vha, 0); 4679 } 4680 break; 4681 case QLA8XXX_DEV_INITIALIZING: 4682 /* Wait for AEN to change device-state */ 4683 qla83xx_idc_unlock(base_vha, 0); 4684 msleep(1000); 4685 qla83xx_idc_lock(base_vha, 0); 4686 break; 4687 case QLA8XXX_DEV_NEED_RESET: 4688 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4689 qla83xx_need_reset_handler(base_vha); 4690 else { 4691 /* Wait for AEN to change device-state */ 4692 qla83xx_idc_unlock(base_vha, 0); 4693 msleep(1000); 4694 qla83xx_idc_lock(base_vha, 0); 4695 } 4696 /* reset timeout value after need reset handler */ 4697 dev_init_timeout = jiffies + 4698 (ha->fcoe_dev_init_timeout * HZ); 4699 break; 4700 case QLA8XXX_DEV_NEED_QUIESCENT: 4701 /* XXX: DEBUG for now */ 4702 qla83xx_idc_unlock(base_vha, 0); 4703 msleep(1000); 4704 qla83xx_idc_lock(base_vha, 0); 4705 break; 4706 case QLA8XXX_DEV_QUIESCENT: 4707 /* XXX: DEBUG for now */ 4708 if (ha->flags.quiesce_owner) 4709 goto exit; 4710 4711 qla83xx_idc_unlock(base_vha, 0); 4712 msleep(1000); 4713 qla83xx_idc_lock(base_vha, 0); 4714 dev_init_timeout = jiffies + 4715 (ha->fcoe_dev_init_timeout * HZ); 4716 break; 4717 case QLA8XXX_DEV_FAILED: 4718 if (ha->flags.nic_core_reset_owner) 4719 qla83xx_idc_audit(base_vha, 4720 IDC_AUDIT_COMPLETION); 4721 ha->flags.nic_core_reset_owner = 0; 4722 __qla83xx_clear_drv_presence(base_vha); 4723 qla83xx_idc_unlock(base_vha, 0); 4724 qla8xxx_dev_failed_handler(base_vha); 4725 rval = QLA_FUNCTION_FAILED; 4726 qla83xx_idc_lock(base_vha, 0); 4727 goto exit; 4728 case QLA8XXX_BAD_VALUE: 4729 qla83xx_idc_unlock(base_vha, 0); 4730 msleep(1000); 4731 qla83xx_idc_lock(base_vha, 0); 4732 break; 4733 default: 4734 ql_log(ql_log_warn, base_vha, 0xb071, 4735 "Unknow Device State: %x.\n", dev_state); 4736 qla83xx_idc_unlock(base_vha, 0); 4737 qla8xxx_dev_failed_handler(base_vha); 4738 rval = QLA_FUNCTION_FAILED; 4739 qla83xx_idc_lock(base_vha, 0); 4740 goto exit; 4741 } 4742 } 4743 4744 exit: 4745 return rval; 4746 } 4747 4748 void 4749 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4750 { 4751 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4752 board_disable); 4753 struct pci_dev *pdev = ha->pdev; 4754 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4755 4756 ql_log(ql_log_warn, base_vha, 0x015b, 4757 "Disabling adapter.\n"); 4758 4759 set_bit(UNLOADING, &base_vha->dpc_flags); 4760 4761 qla2x00_delete_all_vps(ha, base_vha); 4762 4763 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4764 4765 qla2x00_dfs_remove(base_vha); 4766 4767 qla84xx_put_chip(base_vha); 4768 4769 if (base_vha->timer_active) 4770 qla2x00_stop_timer(base_vha); 4771 4772 base_vha->flags.online = 0; 4773 4774 qla2x00_destroy_deferred_work(ha); 4775 4776 /* 4777 * Do not try to stop beacon blink as it will issue a mailbox 4778 * command. 4779 */ 4780 qla2x00_free_sysfs_attr(base_vha, false); 4781 4782 fc_remove_host(base_vha->host); 4783 4784 scsi_remove_host(base_vha->host); 4785 4786 base_vha->flags.init_done = 0; 4787 qla25xx_delete_queues(base_vha); 4788 qla2x00_free_irqs(base_vha); 4789 qla2x00_free_fcports(base_vha); 4790 qla2x00_mem_free(ha); 4791 qla82xx_md_free(base_vha); 4792 qla2x00_free_queues(ha); 4793 4794 scsi_host_put(base_vha->host); 4795 4796 qla2x00_unmap_iobases(ha); 4797 4798 pci_release_selected_regions(ha->pdev, ha->bars); 4799 kfree(ha); 4800 ha = NULL; 4801 4802 pci_disable_pcie_error_reporting(pdev); 4803 pci_disable_device(pdev); 4804 pci_set_drvdata(pdev, NULL); 4805 4806 } 4807 4808 /************************************************************************** 4809 * qla2x00_do_dpc 4810 * This kernel thread is a task that is schedule by the interrupt handler 4811 * to perform the background processing for interrupts. 4812 * 4813 * Notes: 4814 * This task always run in the context of a kernel thread. It 4815 * is kick-off by the driver's detect code and starts up 4816 * up one per adapter. It immediately goes to sleep and waits for 4817 * some fibre event. When either the interrupt handler or 4818 * the timer routine detects a event it will one of the task 4819 * bits then wake us up. 4820 **************************************************************************/ 4821 static int 4822 qla2x00_do_dpc(void *data) 4823 { 4824 int rval; 4825 scsi_qla_host_t *base_vha; 4826 struct qla_hw_data *ha; 4827 4828 ha = (struct qla_hw_data *)data; 4829 base_vha = pci_get_drvdata(ha->pdev); 4830 4831 set_user_nice(current, -20); 4832 4833 set_current_state(TASK_INTERRUPTIBLE); 4834 while (!kthread_should_stop()) { 4835 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4836 "DPC handler sleeping.\n"); 4837 4838 schedule(); 4839 __set_current_state(TASK_RUNNING); 4840 4841 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4842 goto end_loop; 4843 4844 if (ha->flags.eeh_busy) { 4845 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4846 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4847 goto end_loop; 4848 } 4849 4850 ha->dpc_active = 1; 4851 4852 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4853 "DPC handler waking up, dpc_flags=0x%lx.\n", 4854 base_vha->dpc_flags); 4855 4856 qla2x00_do_work(base_vha); 4857 4858 if (IS_P3P_TYPE(ha)) { 4859 if (IS_QLA8044(ha)) { 4860 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4861 &base_vha->dpc_flags)) { 4862 qla8044_idc_lock(ha); 4863 qla8044_wr_direct(base_vha, 4864 QLA8044_CRB_DEV_STATE_INDEX, 4865 QLA8XXX_DEV_FAILED); 4866 qla8044_idc_unlock(ha); 4867 ql_log(ql_log_info, base_vha, 0x4004, 4868 "HW State: FAILED.\n"); 4869 qla8044_device_state_handler(base_vha); 4870 continue; 4871 } 4872 4873 } else { 4874 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4875 &base_vha->dpc_flags)) { 4876 qla82xx_idc_lock(ha); 4877 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4878 QLA8XXX_DEV_FAILED); 4879 qla82xx_idc_unlock(ha); 4880 ql_log(ql_log_info, base_vha, 0x0151, 4881 "HW State: FAILED.\n"); 4882 qla82xx_device_state_handler(base_vha); 4883 continue; 4884 } 4885 } 4886 4887 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 4888 &base_vha->dpc_flags)) { 4889 4890 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 4891 "FCoE context reset scheduled.\n"); 4892 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4893 &base_vha->dpc_flags))) { 4894 if (qla82xx_fcoe_ctx_reset(base_vha)) { 4895 /* FCoE-ctx reset failed. 4896 * Escalate to chip-reset 4897 */ 4898 set_bit(ISP_ABORT_NEEDED, 4899 &base_vha->dpc_flags); 4900 } 4901 clear_bit(ABORT_ISP_ACTIVE, 4902 &base_vha->dpc_flags); 4903 } 4904 4905 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 4906 "FCoE context reset end.\n"); 4907 } 4908 } else if (IS_QLAFX00(ha)) { 4909 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4910 &base_vha->dpc_flags)) { 4911 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 4912 "Firmware Reset Recovery\n"); 4913 if (qlafx00_reset_initialize(base_vha)) { 4914 /* Failed. Abort isp later. */ 4915 if (!test_bit(UNLOADING, 4916 &base_vha->dpc_flags)) 4917 set_bit(ISP_UNRECOVERABLE, 4918 &base_vha->dpc_flags); 4919 ql_dbg(ql_dbg_dpc, base_vha, 4920 0x4021, 4921 "Reset Recovery Failed\n"); 4922 } 4923 } 4924 4925 if (test_and_clear_bit(FX00_TARGET_SCAN, 4926 &base_vha->dpc_flags)) { 4927 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 4928 "ISPFx00 Target Scan scheduled\n"); 4929 if (qlafx00_rescan_isp(base_vha)) { 4930 if (!test_bit(UNLOADING, 4931 &base_vha->dpc_flags)) 4932 set_bit(ISP_UNRECOVERABLE, 4933 &base_vha->dpc_flags); 4934 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 4935 "ISPFx00 Target Scan Failed\n"); 4936 } 4937 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 4938 "ISPFx00 Target Scan End\n"); 4939 } 4940 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 4941 &base_vha->dpc_flags)) { 4942 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 4943 "ISPFx00 Host Info resend scheduled\n"); 4944 qlafx00_fx_disc(base_vha, 4945 &base_vha->hw->mr.fcport, 4946 FXDISC_REG_HOST_INFO); 4947 } 4948 } 4949 4950 if (test_and_clear_bit(ISP_ABORT_NEEDED, 4951 &base_vha->dpc_flags)) { 4952 4953 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 4954 "ISP abort scheduled.\n"); 4955 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4956 &base_vha->dpc_flags))) { 4957 4958 if (ha->isp_ops->abort_isp(base_vha)) { 4959 /* failed. retry later */ 4960 set_bit(ISP_ABORT_NEEDED, 4961 &base_vha->dpc_flags); 4962 } 4963 clear_bit(ABORT_ISP_ACTIVE, 4964 &base_vha->dpc_flags); 4965 } 4966 4967 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 4968 "ISP abort end.\n"); 4969 } 4970 4971 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 4972 &base_vha->dpc_flags)) { 4973 qla2x00_update_fcports(base_vha); 4974 } 4975 4976 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 4977 int ret; 4978 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 4979 if (ret != QLA_SUCCESS) 4980 ql_log(ql_log_warn, base_vha, 0x121, 4981 "Failed to enable receiving of RSCN " 4982 "requests: 0x%x.\n", ret); 4983 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 4984 } 4985 4986 if (IS_QLAFX00(ha)) 4987 goto loop_resync_check; 4988 4989 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 4990 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 4991 "Quiescence mode scheduled.\n"); 4992 if (IS_P3P_TYPE(ha)) { 4993 if (IS_QLA82XX(ha)) 4994 qla82xx_device_state_handler(base_vha); 4995 if (IS_QLA8044(ha)) 4996 qla8044_device_state_handler(base_vha); 4997 clear_bit(ISP_QUIESCE_NEEDED, 4998 &base_vha->dpc_flags); 4999 if (!ha->flags.quiesce_owner) { 5000 qla2x00_perform_loop_resync(base_vha); 5001 if (IS_QLA82XX(ha)) { 5002 qla82xx_idc_lock(ha); 5003 qla82xx_clear_qsnt_ready( 5004 base_vha); 5005 qla82xx_idc_unlock(ha); 5006 } else if (IS_QLA8044(ha)) { 5007 qla8044_idc_lock(ha); 5008 qla8044_clear_qsnt_ready( 5009 base_vha); 5010 qla8044_idc_unlock(ha); 5011 } 5012 } 5013 } else { 5014 clear_bit(ISP_QUIESCE_NEEDED, 5015 &base_vha->dpc_flags); 5016 qla2x00_quiesce_io(base_vha); 5017 } 5018 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5019 "Quiescence mode end.\n"); 5020 } 5021 5022 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5023 &base_vha->dpc_flags) && 5024 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5025 5026 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5027 "Reset marker scheduled.\n"); 5028 qla2x00_rst_aen(base_vha); 5029 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5030 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5031 "Reset marker end.\n"); 5032 } 5033 5034 /* Retry each device up to login retry count */ 5035 if ((test_and_clear_bit(RELOGIN_NEEDED, 5036 &base_vha->dpc_flags)) && 5037 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5038 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5039 5040 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5041 "Relogin scheduled.\n"); 5042 qla2x00_relogin(base_vha); 5043 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5044 "Relogin end.\n"); 5045 } 5046 loop_resync_check: 5047 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5048 &base_vha->dpc_flags)) { 5049 5050 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5051 "Loop resync scheduled.\n"); 5052 5053 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5054 &base_vha->dpc_flags))) { 5055 5056 rval = qla2x00_loop_resync(base_vha); 5057 5058 clear_bit(LOOP_RESYNC_ACTIVE, 5059 &base_vha->dpc_flags); 5060 } 5061 5062 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5063 "Loop resync end.\n"); 5064 } 5065 5066 if (IS_QLAFX00(ha)) 5067 goto intr_on_check; 5068 5069 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5070 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5071 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5072 qla2xxx_flash_npiv_conf(base_vha); 5073 } 5074 5075 intr_on_check: 5076 if (!ha->interrupts_on) 5077 ha->isp_ops->enable_intrs(ha); 5078 5079 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5080 &base_vha->dpc_flags)) 5081 ha->isp_ops->beacon_blink(base_vha); 5082 5083 if (!IS_QLAFX00(ha)) 5084 qla2x00_do_dpc_all_vps(base_vha); 5085 5086 ha->dpc_active = 0; 5087 end_loop: 5088 set_current_state(TASK_INTERRUPTIBLE); 5089 } /* End of while(1) */ 5090 __set_current_state(TASK_RUNNING); 5091 5092 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5093 "DPC handler exiting.\n"); 5094 5095 /* 5096 * Make sure that nobody tries to wake us up again. 5097 */ 5098 ha->dpc_active = 0; 5099 5100 /* Cleanup any residual CTX SRBs. */ 5101 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5102 5103 return 0; 5104 } 5105 5106 void 5107 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5108 { 5109 struct qla_hw_data *ha = vha->hw; 5110 struct task_struct *t = ha->dpc_thread; 5111 5112 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5113 wake_up_process(t); 5114 } 5115 5116 /* 5117 * qla2x00_rst_aen 5118 * Processes asynchronous reset. 5119 * 5120 * Input: 5121 * ha = adapter block pointer. 5122 */ 5123 static void 5124 qla2x00_rst_aen(scsi_qla_host_t *vha) 5125 { 5126 if (vha->flags.online && !vha->flags.reset_active && 5127 !atomic_read(&vha->loop_down_timer) && 5128 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5129 do { 5130 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5131 5132 /* 5133 * Issue marker command only when we are going to start 5134 * the I/O. 5135 */ 5136 vha->marker_needed = 1; 5137 } while (!atomic_read(&vha->loop_down_timer) && 5138 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5139 } 5140 } 5141 5142 /************************************************************************** 5143 * qla2x00_timer 5144 * 5145 * Description: 5146 * One second timer 5147 * 5148 * Context: Interrupt 5149 ***************************************************************************/ 5150 void 5151 qla2x00_timer(scsi_qla_host_t *vha) 5152 { 5153 unsigned long cpu_flags = 0; 5154 int start_dpc = 0; 5155 int index; 5156 srb_t *sp; 5157 uint16_t w; 5158 struct qla_hw_data *ha = vha->hw; 5159 struct req_que *req; 5160 5161 if (ha->flags.eeh_busy) { 5162 ql_dbg(ql_dbg_timer, vha, 0x6000, 5163 "EEH = %d, restarting timer.\n", 5164 ha->flags.eeh_busy); 5165 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5166 return; 5167 } 5168 5169 /* 5170 * Hardware read to raise pending EEH errors during mailbox waits. If 5171 * the read returns -1 then disable the board. 5172 */ 5173 if (!pci_channel_offline(ha->pdev)) { 5174 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5175 if (w == 0xffff) 5176 /* 5177 * Schedule this on the default system workqueue so that 5178 * all the adapter workqueues and the DPC thread can be 5179 * shutdown cleanly. 5180 */ 5181 schedule_work(&ha->board_disable); 5182 } 5183 5184 /* Make sure qla82xx_watchdog is run only for physical port */ 5185 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5186 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5187 start_dpc++; 5188 if (IS_QLA82XX(ha)) 5189 qla82xx_watchdog(vha); 5190 else if (IS_QLA8044(ha)) 5191 qla8044_watchdog(vha); 5192 } 5193 5194 if (!vha->vp_idx && IS_QLAFX00(ha)) 5195 qlafx00_timer_routine(vha); 5196 5197 /* Loop down handler. */ 5198 if (atomic_read(&vha->loop_down_timer) > 0 && 5199 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5200 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5201 && vha->flags.online) { 5202 5203 if (atomic_read(&vha->loop_down_timer) == 5204 vha->loop_down_abort_time) { 5205 5206 ql_log(ql_log_info, vha, 0x6008, 5207 "Loop down - aborting the queues before time expires.\n"); 5208 5209 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5210 atomic_set(&vha->loop_state, LOOP_DEAD); 5211 5212 /* 5213 * Schedule an ISP abort to return any FCP2-device 5214 * commands. 5215 */ 5216 /* NPIV - scan physical port only */ 5217 if (!vha->vp_idx) { 5218 spin_lock_irqsave(&ha->hardware_lock, 5219 cpu_flags); 5220 req = ha->req_q_map[0]; 5221 for (index = 1; 5222 index < req->num_outstanding_cmds; 5223 index++) { 5224 fc_port_t *sfcp; 5225 5226 sp = req->outstanding_cmds[index]; 5227 if (!sp) 5228 continue; 5229 if (sp->type != SRB_SCSI_CMD) 5230 continue; 5231 sfcp = sp->fcport; 5232 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5233 continue; 5234 5235 if (IS_QLA82XX(ha)) 5236 set_bit(FCOE_CTX_RESET_NEEDED, 5237 &vha->dpc_flags); 5238 else 5239 set_bit(ISP_ABORT_NEEDED, 5240 &vha->dpc_flags); 5241 break; 5242 } 5243 spin_unlock_irqrestore(&ha->hardware_lock, 5244 cpu_flags); 5245 } 5246 start_dpc++; 5247 } 5248 5249 /* if the loop has been down for 4 minutes, reinit adapter */ 5250 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5251 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5252 ql_log(ql_log_warn, vha, 0x6009, 5253 "Loop down - aborting ISP.\n"); 5254 5255 if (IS_QLA82XX(ha)) 5256 set_bit(FCOE_CTX_RESET_NEEDED, 5257 &vha->dpc_flags); 5258 else 5259 set_bit(ISP_ABORT_NEEDED, 5260 &vha->dpc_flags); 5261 } 5262 } 5263 ql_dbg(ql_dbg_timer, vha, 0x600a, 5264 "Loop down - seconds remaining %d.\n", 5265 atomic_read(&vha->loop_down_timer)); 5266 } 5267 /* Check if beacon LED needs to be blinked for physical host only */ 5268 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5269 /* There is no beacon_blink function for ISP82xx */ 5270 if (!IS_P3P_TYPE(ha)) { 5271 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5272 start_dpc++; 5273 } 5274 } 5275 5276 /* Process any deferred work. */ 5277 if (!list_empty(&vha->work_list)) 5278 start_dpc++; 5279 5280 /* Schedule the DPC routine if needed */ 5281 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5282 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5283 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5284 start_dpc || 5285 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5286 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5287 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5288 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5289 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5290 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5291 ql_dbg(ql_dbg_timer, vha, 0x600b, 5292 "isp_abort_needed=%d loop_resync_needed=%d " 5293 "fcport_update_needed=%d start_dpc=%d " 5294 "reset_marker_needed=%d", 5295 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5296 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5297 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5298 start_dpc, 5299 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5300 ql_dbg(ql_dbg_timer, vha, 0x600c, 5301 "beacon_blink_needed=%d isp_unrecoverable=%d " 5302 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5303 "relogin_needed=%d.\n", 5304 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5305 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5306 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5307 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5308 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5309 qla2xxx_wake_dpc(vha); 5310 } 5311 5312 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5313 } 5314 5315 /* Firmware interface routines. */ 5316 5317 #define FW_BLOBS 11 5318 #define FW_ISP21XX 0 5319 #define FW_ISP22XX 1 5320 #define FW_ISP2300 2 5321 #define FW_ISP2322 3 5322 #define FW_ISP24XX 4 5323 #define FW_ISP25XX 5 5324 #define FW_ISP81XX 6 5325 #define FW_ISP82XX 7 5326 #define FW_ISP2031 8 5327 #define FW_ISP8031 9 5328 #define FW_ISP2071 10 5329 5330 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5331 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5332 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5333 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5334 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5335 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5336 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5337 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5338 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5339 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5340 #define FW_FILE_ISP2071 "ql2700_fw.bin" 5341 5342 5343 static DEFINE_MUTEX(qla_fw_lock); 5344 5345 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5346 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5347 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5348 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5349 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5350 { .name = FW_FILE_ISP24XX, }, 5351 { .name = FW_FILE_ISP25XX, }, 5352 { .name = FW_FILE_ISP81XX, }, 5353 { .name = FW_FILE_ISP82XX, }, 5354 { .name = FW_FILE_ISP2031, }, 5355 { .name = FW_FILE_ISP8031, }, 5356 { .name = FW_FILE_ISP2071, }, 5357 }; 5358 5359 struct fw_blob * 5360 qla2x00_request_firmware(scsi_qla_host_t *vha) 5361 { 5362 struct qla_hw_data *ha = vha->hw; 5363 struct fw_blob *blob; 5364 5365 if (IS_QLA2100(ha)) { 5366 blob = &qla_fw_blobs[FW_ISP21XX]; 5367 } else if (IS_QLA2200(ha)) { 5368 blob = &qla_fw_blobs[FW_ISP22XX]; 5369 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5370 blob = &qla_fw_blobs[FW_ISP2300]; 5371 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5372 blob = &qla_fw_blobs[FW_ISP2322]; 5373 } else if (IS_QLA24XX_TYPE(ha)) { 5374 blob = &qla_fw_blobs[FW_ISP24XX]; 5375 } else if (IS_QLA25XX(ha)) { 5376 blob = &qla_fw_blobs[FW_ISP25XX]; 5377 } else if (IS_QLA81XX(ha)) { 5378 blob = &qla_fw_blobs[FW_ISP81XX]; 5379 } else if (IS_QLA82XX(ha)) { 5380 blob = &qla_fw_blobs[FW_ISP82XX]; 5381 } else if (IS_QLA2031(ha)) { 5382 blob = &qla_fw_blobs[FW_ISP2031]; 5383 } else if (IS_QLA8031(ha)) { 5384 blob = &qla_fw_blobs[FW_ISP8031]; 5385 } else if (IS_QLA2071(ha)) { 5386 blob = &qla_fw_blobs[FW_ISP2071]; 5387 } else { 5388 return NULL; 5389 } 5390 5391 mutex_lock(&qla_fw_lock); 5392 if (blob->fw) 5393 goto out; 5394 5395 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5396 ql_log(ql_log_warn, vha, 0x0063, 5397 "Failed to load firmware image (%s).\n", blob->name); 5398 blob->fw = NULL; 5399 blob = NULL; 5400 goto out; 5401 } 5402 5403 out: 5404 mutex_unlock(&qla_fw_lock); 5405 return blob; 5406 } 5407 5408 static void 5409 qla2x00_release_firmware(void) 5410 { 5411 int idx; 5412 5413 mutex_lock(&qla_fw_lock); 5414 for (idx = 0; idx < FW_BLOBS; idx++) 5415 release_firmware(qla_fw_blobs[idx].fw); 5416 mutex_unlock(&qla_fw_lock); 5417 } 5418 5419 static pci_ers_result_t 5420 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5421 { 5422 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5423 struct qla_hw_data *ha = vha->hw; 5424 5425 ql_dbg(ql_dbg_aer, vha, 0x9000, 5426 "PCI error detected, state %x.\n", state); 5427 5428 switch (state) { 5429 case pci_channel_io_normal: 5430 ha->flags.eeh_busy = 0; 5431 return PCI_ERS_RESULT_CAN_RECOVER; 5432 case pci_channel_io_frozen: 5433 ha->flags.eeh_busy = 1; 5434 /* For ISP82XX complete any pending mailbox cmd */ 5435 if (IS_QLA82XX(ha)) { 5436 ha->flags.isp82xx_fw_hung = 1; 5437 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5438 qla82xx_clear_pending_mbx(vha); 5439 } 5440 qla2x00_free_irqs(vha); 5441 pci_disable_device(pdev); 5442 /* Return back all IOs */ 5443 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5444 return PCI_ERS_RESULT_NEED_RESET; 5445 case pci_channel_io_perm_failure: 5446 ha->flags.pci_channel_io_perm_failure = 1; 5447 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5448 return PCI_ERS_RESULT_DISCONNECT; 5449 } 5450 return PCI_ERS_RESULT_NEED_RESET; 5451 } 5452 5453 static pci_ers_result_t 5454 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5455 { 5456 int risc_paused = 0; 5457 uint32_t stat; 5458 unsigned long flags; 5459 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5460 struct qla_hw_data *ha = base_vha->hw; 5461 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5462 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5463 5464 if (IS_QLA82XX(ha)) 5465 return PCI_ERS_RESULT_RECOVERED; 5466 5467 spin_lock_irqsave(&ha->hardware_lock, flags); 5468 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5469 stat = RD_REG_DWORD(®->hccr); 5470 if (stat & HCCR_RISC_PAUSE) 5471 risc_paused = 1; 5472 } else if (IS_QLA23XX(ha)) { 5473 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5474 if (stat & HSR_RISC_PAUSED) 5475 risc_paused = 1; 5476 } else if (IS_FWI2_CAPABLE(ha)) { 5477 stat = RD_REG_DWORD(®24->host_status); 5478 if (stat & HSRX_RISC_PAUSED) 5479 risc_paused = 1; 5480 } 5481 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5482 5483 if (risc_paused) { 5484 ql_log(ql_log_info, base_vha, 0x9003, 5485 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5486 ha->isp_ops->fw_dump(base_vha, 0); 5487 5488 return PCI_ERS_RESULT_NEED_RESET; 5489 } else 5490 return PCI_ERS_RESULT_RECOVERED; 5491 } 5492 5493 static uint32_t 5494 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5495 { 5496 uint32_t rval = QLA_FUNCTION_FAILED; 5497 uint32_t drv_active = 0; 5498 struct qla_hw_data *ha = base_vha->hw; 5499 int fn; 5500 struct pci_dev *other_pdev = NULL; 5501 5502 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5503 "Entered %s.\n", __func__); 5504 5505 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5506 5507 if (base_vha->flags.online) { 5508 /* Abort all outstanding commands, 5509 * so as to be requeued later */ 5510 qla2x00_abort_isp_cleanup(base_vha); 5511 } 5512 5513 5514 fn = PCI_FUNC(ha->pdev->devfn); 5515 while (fn > 0) { 5516 fn--; 5517 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5518 "Finding pci device at function = 0x%x.\n", fn); 5519 other_pdev = 5520 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5521 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5522 fn)); 5523 5524 if (!other_pdev) 5525 continue; 5526 if (atomic_read(&other_pdev->enable_cnt)) { 5527 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5528 "Found PCI func available and enable at 0x%x.\n", 5529 fn); 5530 pci_dev_put(other_pdev); 5531 break; 5532 } 5533 pci_dev_put(other_pdev); 5534 } 5535 5536 if (!fn) { 5537 /* Reset owner */ 5538 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5539 "This devfn is reset owner = 0x%x.\n", 5540 ha->pdev->devfn); 5541 qla82xx_idc_lock(ha); 5542 5543 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5544 QLA8XXX_DEV_INITIALIZING); 5545 5546 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5547 QLA82XX_IDC_VERSION); 5548 5549 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5550 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5551 "drv_active = 0x%x.\n", drv_active); 5552 5553 qla82xx_idc_unlock(ha); 5554 /* Reset if device is not already reset 5555 * drv_active would be 0 if a reset has already been done 5556 */ 5557 if (drv_active) 5558 rval = qla82xx_start_firmware(base_vha); 5559 else 5560 rval = QLA_SUCCESS; 5561 qla82xx_idc_lock(ha); 5562 5563 if (rval != QLA_SUCCESS) { 5564 ql_log(ql_log_info, base_vha, 0x900b, 5565 "HW State: FAILED.\n"); 5566 qla82xx_clear_drv_active(ha); 5567 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5568 QLA8XXX_DEV_FAILED); 5569 } else { 5570 ql_log(ql_log_info, base_vha, 0x900c, 5571 "HW State: READY.\n"); 5572 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5573 QLA8XXX_DEV_READY); 5574 qla82xx_idc_unlock(ha); 5575 ha->flags.isp82xx_fw_hung = 0; 5576 rval = qla82xx_restart_isp(base_vha); 5577 qla82xx_idc_lock(ha); 5578 /* Clear driver state register */ 5579 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5580 qla82xx_set_drv_active(base_vha); 5581 } 5582 qla82xx_idc_unlock(ha); 5583 } else { 5584 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5585 "This devfn is not reset owner = 0x%x.\n", 5586 ha->pdev->devfn); 5587 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5588 QLA8XXX_DEV_READY)) { 5589 ha->flags.isp82xx_fw_hung = 0; 5590 rval = qla82xx_restart_isp(base_vha); 5591 qla82xx_idc_lock(ha); 5592 qla82xx_set_drv_active(base_vha); 5593 qla82xx_idc_unlock(ha); 5594 } 5595 } 5596 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5597 5598 return rval; 5599 } 5600 5601 static pci_ers_result_t 5602 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5603 { 5604 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5605 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5606 struct qla_hw_data *ha = base_vha->hw; 5607 struct rsp_que *rsp; 5608 int rc, retries = 10; 5609 5610 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5611 "Slot Reset.\n"); 5612 5613 /* Workaround: qla2xxx driver which access hardware earlier 5614 * needs error state to be pci_channel_io_online. 5615 * Otherwise mailbox command timesout. 5616 */ 5617 pdev->error_state = pci_channel_io_normal; 5618 5619 pci_restore_state(pdev); 5620 5621 /* pci_restore_state() clears the saved_state flag of the device 5622 * save restored state which resets saved_state flag 5623 */ 5624 pci_save_state(pdev); 5625 5626 if (ha->mem_only) 5627 rc = pci_enable_device_mem(pdev); 5628 else 5629 rc = pci_enable_device(pdev); 5630 5631 if (rc) { 5632 ql_log(ql_log_warn, base_vha, 0x9005, 5633 "Can't re-enable PCI device after reset.\n"); 5634 goto exit_slot_reset; 5635 } 5636 5637 rsp = ha->rsp_q_map[0]; 5638 if (qla2x00_request_irqs(ha, rsp)) 5639 goto exit_slot_reset; 5640 5641 if (ha->isp_ops->pci_config(base_vha)) 5642 goto exit_slot_reset; 5643 5644 if (IS_QLA82XX(ha)) { 5645 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5646 ret = PCI_ERS_RESULT_RECOVERED; 5647 goto exit_slot_reset; 5648 } else 5649 goto exit_slot_reset; 5650 } 5651 5652 while (ha->flags.mbox_busy && retries--) 5653 msleep(1000); 5654 5655 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5656 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5657 ret = PCI_ERS_RESULT_RECOVERED; 5658 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5659 5660 5661 exit_slot_reset: 5662 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5663 "slot_reset return %x.\n", ret); 5664 5665 return ret; 5666 } 5667 5668 static void 5669 qla2xxx_pci_resume(struct pci_dev *pdev) 5670 { 5671 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5672 struct qla_hw_data *ha = base_vha->hw; 5673 int ret; 5674 5675 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5676 "pci_resume.\n"); 5677 5678 ret = qla2x00_wait_for_hba_online(base_vha); 5679 if (ret != QLA_SUCCESS) { 5680 ql_log(ql_log_fatal, base_vha, 0x9002, 5681 "The device failed to resume I/O from slot/link_reset.\n"); 5682 } 5683 5684 pci_cleanup_aer_uncorrect_error_status(pdev); 5685 5686 ha->flags.eeh_busy = 0; 5687 } 5688 5689 static const struct pci_error_handlers qla2xxx_err_handler = { 5690 .error_detected = qla2xxx_pci_error_detected, 5691 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5692 .slot_reset = qla2xxx_pci_slot_reset, 5693 .resume = qla2xxx_pci_resume, 5694 }; 5695 5696 static struct pci_device_id qla2xxx_pci_tbl[] = { 5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5717 { 0 }, 5718 }; 5719 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5720 5721 static struct pci_driver qla2xxx_pci_driver = { 5722 .name = QLA2XXX_DRIVER_NAME, 5723 .driver = { 5724 .owner = THIS_MODULE, 5725 }, 5726 .id_table = qla2xxx_pci_tbl, 5727 .probe = qla2x00_probe_one, 5728 .remove = qla2x00_remove_one, 5729 .shutdown = qla2x00_shutdown, 5730 .err_handler = &qla2xxx_err_handler, 5731 }; 5732 5733 static const struct file_operations apidev_fops = { 5734 .owner = THIS_MODULE, 5735 .llseek = noop_llseek, 5736 }; 5737 5738 /** 5739 * qla2x00_module_init - Module initialization. 5740 **/ 5741 static int __init 5742 qla2x00_module_init(void) 5743 { 5744 int ret = 0; 5745 5746 /* Allocate cache for SRBs. */ 5747 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5748 SLAB_HWCACHE_ALIGN, NULL); 5749 if (srb_cachep == NULL) { 5750 ql_log(ql_log_fatal, NULL, 0x0001, 5751 "Unable to allocate SRB cache...Failing load!.\n"); 5752 return -ENOMEM; 5753 } 5754 5755 /* Initialize target kmem_cache and mem_pools */ 5756 ret = qlt_init(); 5757 if (ret < 0) { 5758 kmem_cache_destroy(srb_cachep); 5759 return ret; 5760 } else if (ret > 0) { 5761 /* 5762 * If initiator mode is explictly disabled by qlt_init(), 5763 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5764 * performing scsi_scan_target() during LOOP UP event. 5765 */ 5766 qla2xxx_transport_functions.disable_target_scan = 1; 5767 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5768 } 5769 5770 /* Derive version string. */ 5771 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5772 if (ql2xextended_error_logging) 5773 strcat(qla2x00_version_str, "-debug"); 5774 5775 qla2xxx_transport_template = 5776 fc_attach_transport(&qla2xxx_transport_functions); 5777 if (!qla2xxx_transport_template) { 5778 kmem_cache_destroy(srb_cachep); 5779 ql_log(ql_log_fatal, NULL, 0x0002, 5780 "fc_attach_transport failed...Failing load!.\n"); 5781 qlt_exit(); 5782 return -ENODEV; 5783 } 5784 5785 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5786 if (apidev_major < 0) { 5787 ql_log(ql_log_fatal, NULL, 0x0003, 5788 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5789 } 5790 5791 qla2xxx_transport_vport_template = 5792 fc_attach_transport(&qla2xxx_transport_vport_functions); 5793 if (!qla2xxx_transport_vport_template) { 5794 kmem_cache_destroy(srb_cachep); 5795 qlt_exit(); 5796 fc_release_transport(qla2xxx_transport_template); 5797 ql_log(ql_log_fatal, NULL, 0x0004, 5798 "fc_attach_transport vport failed...Failing load!.\n"); 5799 return -ENODEV; 5800 } 5801 ql_log(ql_log_info, NULL, 0x0005, 5802 "QLogic Fibre Channel HBA Driver: %s.\n", 5803 qla2x00_version_str); 5804 ret = pci_register_driver(&qla2xxx_pci_driver); 5805 if (ret) { 5806 kmem_cache_destroy(srb_cachep); 5807 qlt_exit(); 5808 fc_release_transport(qla2xxx_transport_template); 5809 fc_release_transport(qla2xxx_transport_vport_template); 5810 ql_log(ql_log_fatal, NULL, 0x0006, 5811 "pci_register_driver failed...ret=%d Failing load!.\n", 5812 ret); 5813 } 5814 return ret; 5815 } 5816 5817 /** 5818 * qla2x00_module_exit - Module cleanup. 5819 **/ 5820 static void __exit 5821 qla2x00_module_exit(void) 5822 { 5823 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5824 pci_unregister_driver(&qla2xxx_pci_driver); 5825 qla2x00_release_firmware(); 5826 kmem_cache_destroy(srb_cachep); 5827 qlt_exit(); 5828 if (ctx_cachep) 5829 kmem_cache_destroy(ctx_cachep); 5830 fc_release_transport(qla2xxx_transport_template); 5831 fc_release_transport(qla2xxx_transport_vport_template); 5832 } 5833 5834 module_init(qla2x00_module_init); 5835 module_exit(qla2x00_module_exit); 5836 5837 MODULE_AUTHOR("QLogic Corporation"); 5838 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5839 MODULE_LICENSE("GPL"); 5840 MODULE_VERSION(QLA2XXX_VERSION); 5841 MODULE_FIRMWARE(FW_FILE_ISP21XX); 5842 MODULE_FIRMWARE(FW_FILE_ISP22XX); 5843 MODULE_FIRMWARE(FW_FILE_ISP2300); 5844 MODULE_FIRMWARE(FW_FILE_ISP2322); 5845 MODULE_FIRMWARE(FW_FILE_ISP24XX); 5846 MODULE_FIRMWARE(FW_FILE_ISP25XX); 5847