1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 32 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 32."); 122 123 int ql2xenabledif = 2; 124 module_param(ql2xenabledif, int, S_IRUGO); 125 MODULE_PARM_DESC(ql2xenabledif, 126 " Enable T10-CRC-DIF:\n" 127 " Default is 2.\n" 128 " 0 -- No DIF Support\n" 129 " 1 -- Enable DIF for all types\n" 130 " 2 -- Enable DIF for all types, except Type 0.\n"); 131 132 int ql2xenablehba_err_chk = 2; 133 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 134 MODULE_PARM_DESC(ql2xenablehba_err_chk, 135 " Enable T10-CRC-DIF Error isolation by HBA:\n" 136 " Default is 2.\n" 137 " 0 -- Error isolation disabled\n" 138 " 1 -- Error isolation enabled only for DIX Type 0\n" 139 " 2 -- Error isolation enabled for all Types\n"); 140 141 int ql2xiidmaenable=1; 142 module_param(ql2xiidmaenable, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xiidmaenable, 144 "Enables iIDMA settings " 145 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 146 147 int ql2xmqsupport = 1; 148 module_param(ql2xmqsupport, int, S_IRUGO); 149 MODULE_PARM_DESC(ql2xmqsupport, 150 "Enable on demand multiple queue pairs support " 151 "Default is 1 for supported. " 152 "Set it to 0 to turn off mq qpair support."); 153 154 int ql2xfwloadbin; 155 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 156 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 157 MODULE_PARM_DESC(ql2xfwloadbin, 158 "Option to specify location from which to load ISP firmware:.\n" 159 " 2 -- load firmware via the request_firmware() (hotplug).\n" 160 " interface.\n" 161 " 1 -- load firmware from flash.\n" 162 " 0 -- use default semantics.\n"); 163 164 int ql2xetsenable; 165 module_param(ql2xetsenable, int, S_IRUGO); 166 MODULE_PARM_DESC(ql2xetsenable, 167 "Enables firmware ETS burst." 168 "Default is 0 - skip ETS enablement."); 169 170 int ql2xdbwr = 1; 171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xdbwr, 173 "Option to specify scheme for request queue posting.\n" 174 " 0 -- Regular doorbell.\n" 175 " 1 -- CAMRAM doorbell (faster).\n"); 176 177 int ql2xtargetreset = 1; 178 module_param(ql2xtargetreset, int, S_IRUGO); 179 MODULE_PARM_DESC(ql2xtargetreset, 180 "Enable target reset." 181 "Default is 1 - use hw defaults."); 182 183 int ql2xgffidenable; 184 module_param(ql2xgffidenable, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xgffidenable, 186 "Enables GFF_ID checks of port type. " 187 "Default is 0 - Do not use GFF_ID information."); 188 189 int ql2xasynctmfenable; 190 module_param(ql2xasynctmfenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xasynctmfenable, 192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 193 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 194 195 int ql2xdontresethba; 196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 197 MODULE_PARM_DESC(ql2xdontresethba, 198 "Option to specify reset behaviour.\n" 199 " 0 (Default) -- Reset on failure.\n" 200 " 1 -- Do not reset on failure.\n"); 201 202 uint64_t ql2xmaxlun = MAX_LUNS; 203 module_param(ql2xmaxlun, ullong, S_IRUGO); 204 MODULE_PARM_DESC(ql2xmaxlun, 205 "Defines the maximum LU number to register with the SCSI " 206 "midlayer. Default is 65535."); 207 208 int ql2xmdcapmask = 0x1F; 209 module_param(ql2xmdcapmask, int, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmdcapmask, 211 "Set the Minidump driver capture mask level. " 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 213 214 int ql2xmdenable = 1; 215 module_param(ql2xmdenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdenable, 217 "Enable/disable MiniDump. " 218 "0 - MiniDump disabled. " 219 "1 (Default) - MiniDump enabled."); 220 221 int ql2xexlogins = 0; 222 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 223 MODULE_PARM_DESC(ql2xexlogins, 224 "Number of extended Logins. " 225 "0 (Default)- Disabled."); 226 227 int ql2xexchoffld = 0; 228 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xexchoffld, 230 "Number of exchanges to offload. " 231 "0 (Default)- Disabled."); 232 233 int ql2xfwholdabts = 0; 234 module_param(ql2xfwholdabts, int, S_IRUGO); 235 MODULE_PARM_DESC(ql2xfwholdabts, 236 "Allow FW to hold status IOCB until ABTS rsp received. " 237 "0 (Default) Do not set fw option. " 238 "1 - Set fw option to hold ABTS."); 239 240 int ql2xmvasynctoatio = 1; 241 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 242 MODULE_PARM_DESC(ql2xmvasynctoatio, 243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 244 "0 (Default). Do not move IOCBs" 245 "1 - Move IOCBs."); 246 247 /* 248 * SCSI host template entry points 249 */ 250 static int qla2xxx_slave_configure(struct scsi_device * device); 251 static int qla2xxx_slave_alloc(struct scsi_device *); 252 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 253 static void qla2xxx_scan_start(struct Scsi_Host *); 254 static void qla2xxx_slave_destroy(struct scsi_device *); 255 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 256 static int qla2xxx_eh_abort(struct scsi_cmnd *); 257 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 258 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 259 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 260 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 261 262 static void qla2x00_clear_drv_active(struct qla_hw_data *); 263 static void qla2x00_free_device(scsi_qla_host_t *); 264 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 265 static int qla2xxx_map_queues(struct Scsi_Host *shost); 266 267 struct scsi_host_template qla2xxx_driver_template = { 268 .module = THIS_MODULE, 269 .name = QLA2XXX_DRIVER_NAME, 270 .queuecommand = qla2xxx_queuecommand, 271 272 .eh_timed_out = fc_eh_timed_out, 273 .eh_abort_handler = qla2xxx_eh_abort, 274 .eh_device_reset_handler = qla2xxx_eh_device_reset, 275 .eh_target_reset_handler = qla2xxx_eh_target_reset, 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 277 .eh_host_reset_handler = qla2xxx_eh_host_reset, 278 279 .slave_configure = qla2xxx_slave_configure, 280 281 .slave_alloc = qla2xxx_slave_alloc, 282 .slave_destroy = qla2xxx_slave_destroy, 283 .scan_finished = qla2xxx_scan_finished, 284 .scan_start = qla2xxx_scan_start, 285 .change_queue_depth = scsi_change_queue_depth, 286 .map_queues = qla2xxx_map_queues, 287 .this_id = -1, 288 .cmd_per_lun = 3, 289 .use_clustering = ENABLE_CLUSTERING, 290 .sg_tablesize = SG_ALL, 291 292 .max_sectors = 0xFFFF, 293 .shost_attrs = qla2x00_host_attrs, 294 295 .supported_mode = MODE_INITIATOR, 296 .track_queue_depth = 1, 297 }; 298 299 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 300 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 301 302 /* TODO Convert to inlines 303 * 304 * Timer routines 305 */ 306 307 __inline__ void 308 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 309 { 310 init_timer(&vha->timer); 311 vha->timer.expires = jiffies + interval * HZ; 312 vha->timer.data = (unsigned long)vha; 313 vha->timer.function = (void (*)(unsigned long))func; 314 add_timer(&vha->timer); 315 vha->timer_active = 1; 316 } 317 318 static inline void 319 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 320 { 321 /* Currently used for 82XX only. */ 322 if (vha->device_flags & DFLG_DEV_FAILED) { 323 ql_dbg(ql_dbg_timer, vha, 0x600d, 324 "Device in a failed state, returning.\n"); 325 return; 326 } 327 328 mod_timer(&vha->timer, jiffies + interval * HZ); 329 } 330 331 static __inline__ void 332 qla2x00_stop_timer(scsi_qla_host_t *vha) 333 { 334 del_timer_sync(&vha->timer); 335 vha->timer_active = 0; 336 } 337 338 static int qla2x00_do_dpc(void *data); 339 340 static void qla2x00_rst_aen(scsi_qla_host_t *); 341 342 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 343 struct req_que **, struct rsp_que **); 344 static void qla2x00_free_fw_dump(struct qla_hw_data *); 345 static void qla2x00_mem_free(struct qla_hw_data *); 346 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 347 struct qla_qpair *qpair); 348 349 /* -------------------------------------------------------------------------- */ 350 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 351 struct rsp_que *rsp) 352 { 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 355 GFP_KERNEL); 356 if (!ha->req_q_map) { 357 ql_log(ql_log_fatal, vha, 0x003b, 358 "Unable to allocate memory for request queue ptrs.\n"); 359 goto fail_req_map; 360 } 361 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 363 GFP_KERNEL); 364 if (!ha->rsp_q_map) { 365 ql_log(ql_log_fatal, vha, 0x003c, 366 "Unable to allocate memory for response queue ptrs.\n"); 367 goto fail_rsp_map; 368 } 369 370 if (ql2xmqsupport && ha->max_qpairs) { 371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 372 GFP_KERNEL); 373 if (!ha->queue_pair_map) { 374 ql_log(ql_log_fatal, vha, 0x0180, 375 "Unable to allocate memory for queue pair ptrs.\n"); 376 goto fail_qpair_map; 377 } 378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 379 if (ha->base_qpair == NULL) { 380 ql_log(ql_log_warn, vha, 0x0182, 381 "Failed to allocate base queue pair memory.\n"); 382 goto fail_base_qpair; 383 } 384 ha->base_qpair->req = req; 385 ha->base_qpair->rsp = rsp; 386 } 387 388 /* 389 * Make sure we record at least the request and response queue zero in 390 * case we need to free them if part of the probe fails. 391 */ 392 ha->rsp_q_map[0] = rsp; 393 ha->req_q_map[0] = req; 394 set_bit(0, ha->rsp_qid_map); 395 set_bit(0, ha->req_qid_map); 396 return 1; 397 398 fail_base_qpair: 399 kfree(ha->queue_pair_map); 400 fail_qpair_map: 401 kfree(ha->rsp_q_map); 402 ha->rsp_q_map = NULL; 403 fail_rsp_map: 404 kfree(ha->req_q_map); 405 ha->req_q_map = NULL; 406 fail_req_map: 407 return -ENOMEM; 408 } 409 410 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 411 { 412 if (IS_QLAFX00(ha)) { 413 if (req && req->ring_fx00) 414 dma_free_coherent(&ha->pdev->dev, 415 (req->length_fx00 + 1) * sizeof(request_t), 416 req->ring_fx00, req->dma_fx00); 417 } else if (req && req->ring) 418 dma_free_coherent(&ha->pdev->dev, 419 (req->length + 1) * sizeof(request_t), 420 req->ring, req->dma); 421 422 if (req) 423 kfree(req->outstanding_cmds); 424 425 kfree(req); 426 req = NULL; 427 } 428 429 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 430 { 431 if (IS_QLAFX00(ha)) { 432 if (rsp && rsp->ring) 433 dma_free_coherent(&ha->pdev->dev, 434 (rsp->length_fx00 + 1) * sizeof(request_t), 435 rsp->ring_fx00, rsp->dma_fx00); 436 } else if (rsp && rsp->ring) { 437 dma_free_coherent(&ha->pdev->dev, 438 (rsp->length + 1) * sizeof(response_t), 439 rsp->ring, rsp->dma); 440 } 441 kfree(rsp); 442 rsp = NULL; 443 } 444 445 static void qla2x00_free_queues(struct qla_hw_data *ha) 446 { 447 struct req_que *req; 448 struct rsp_que *rsp; 449 int cnt; 450 unsigned long flags; 451 452 spin_lock_irqsave(&ha->hardware_lock, flags); 453 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 454 if (!test_bit(cnt, ha->req_qid_map)) 455 continue; 456 457 req = ha->req_q_map[cnt]; 458 clear_bit(cnt, ha->req_qid_map); 459 ha->req_q_map[cnt] = NULL; 460 461 spin_unlock_irqrestore(&ha->hardware_lock, flags); 462 qla2x00_free_req_que(ha, req); 463 spin_lock_irqsave(&ha->hardware_lock, flags); 464 } 465 spin_unlock_irqrestore(&ha->hardware_lock, flags); 466 467 kfree(ha->req_q_map); 468 ha->req_q_map = NULL; 469 470 471 spin_lock_irqsave(&ha->hardware_lock, flags); 472 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 473 if (!test_bit(cnt, ha->rsp_qid_map)) 474 continue; 475 476 rsp = ha->rsp_q_map[cnt]; 477 clear_bit(cnt, ha->rsp_qid_map); 478 ha->rsp_q_map[cnt] = NULL; 479 spin_unlock_irqrestore(&ha->hardware_lock, flags); 480 qla2x00_free_rsp_que(ha, rsp); 481 spin_lock_irqsave(&ha->hardware_lock, flags); 482 } 483 spin_unlock_irqrestore(&ha->hardware_lock, flags); 484 485 kfree(ha->rsp_q_map); 486 ha->rsp_q_map = NULL; 487 } 488 489 static char * 490 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 491 { 492 struct qla_hw_data *ha = vha->hw; 493 static char *pci_bus_modes[] = { 494 "33", "66", "100", "133", 495 }; 496 uint16_t pci_bus; 497 498 strcpy(str, "PCI"); 499 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 500 if (pci_bus) { 501 strcat(str, "-X ("); 502 strcat(str, pci_bus_modes[pci_bus]); 503 } else { 504 pci_bus = (ha->pci_attr & BIT_8) >> 8; 505 strcat(str, " ("); 506 strcat(str, pci_bus_modes[pci_bus]); 507 } 508 strcat(str, " MHz)"); 509 510 return (str); 511 } 512 513 static char * 514 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 515 { 516 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 517 struct qla_hw_data *ha = vha->hw; 518 uint32_t pci_bus; 519 520 if (pci_is_pcie(ha->pdev)) { 521 char lwstr[6]; 522 uint32_t lstat, lspeed, lwidth; 523 524 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 525 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 526 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 527 528 strcpy(str, "PCIe ("); 529 switch (lspeed) { 530 case 1: 531 strcat(str, "2.5GT/s "); 532 break; 533 case 2: 534 strcat(str, "5.0GT/s "); 535 break; 536 case 3: 537 strcat(str, "8.0GT/s "); 538 break; 539 default: 540 strcat(str, "<unknown> "); 541 break; 542 } 543 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 544 strcat(str, lwstr); 545 546 return str; 547 } 548 549 strcpy(str, "PCI"); 550 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 551 if (pci_bus == 0 || pci_bus == 8) { 552 strcat(str, " ("); 553 strcat(str, pci_bus_modes[pci_bus >> 3]); 554 } else { 555 strcat(str, "-X "); 556 if (pci_bus & BIT_2) 557 strcat(str, "Mode 2"); 558 else 559 strcat(str, "Mode 1"); 560 strcat(str, " ("); 561 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 562 } 563 strcat(str, " MHz)"); 564 565 return str; 566 } 567 568 static char * 569 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 570 { 571 char un_str[10]; 572 struct qla_hw_data *ha = vha->hw; 573 574 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 575 ha->fw_minor_version, ha->fw_subminor_version); 576 577 if (ha->fw_attributes & BIT_9) { 578 strcat(str, "FLX"); 579 return (str); 580 } 581 582 switch (ha->fw_attributes & 0xFF) { 583 case 0x7: 584 strcat(str, "EF"); 585 break; 586 case 0x17: 587 strcat(str, "TP"); 588 break; 589 case 0x37: 590 strcat(str, "IP"); 591 break; 592 case 0x77: 593 strcat(str, "VI"); 594 break; 595 default: 596 sprintf(un_str, "(%x)", ha->fw_attributes); 597 strcat(str, un_str); 598 break; 599 } 600 if (ha->fw_attributes & 0x100) 601 strcat(str, "X"); 602 603 return (str); 604 } 605 606 static char * 607 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 608 { 609 struct qla_hw_data *ha = vha->hw; 610 611 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 612 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 613 return str; 614 } 615 616 void 617 qla2x00_sp_free_dma(void *ptr) 618 { 619 srb_t *sp = ptr; 620 struct qla_hw_data *ha = sp->vha->hw; 621 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 622 void *ctx = GET_CMD_CTX_SP(sp); 623 624 if (sp->flags & SRB_DMA_VALID) { 625 scsi_dma_unmap(cmd); 626 sp->flags &= ~SRB_DMA_VALID; 627 } 628 629 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 630 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 631 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 632 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 633 } 634 635 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 636 /* List assured to be having elements */ 637 qla2x00_clean_dsd_pool(ha, sp, NULL); 638 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 639 } 640 641 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 642 dma_pool_free(ha->dl_dma_pool, ctx, 643 ((struct crc_context *)ctx)->crc_ctx_dma); 644 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 645 } 646 647 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 648 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 649 650 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 651 ctx1->fcp_cmnd_dma); 652 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 653 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 654 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 655 mempool_free(ctx1, ha->ctx_mempool); 656 ctx1 = NULL; 657 } 658 659 CMD_SP(cmd) = NULL; 660 qla2x00_rel_sp(sp); 661 } 662 663 void 664 qla2x00_sp_compl(void *ptr, int res) 665 { 666 srb_t *sp = ptr; 667 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 668 669 cmd->result = res; 670 671 if (atomic_read(&sp->ref_count) == 0) { 672 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 673 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 674 sp, GET_CMD_SP(sp)); 675 if (ql2xextended_error_logging & ql_dbg_io) 676 WARN_ON(atomic_read(&sp->ref_count) == 0); 677 return; 678 } 679 if (!atomic_dec_and_test(&sp->ref_count)) 680 return; 681 682 qla2x00_sp_free_dma(sp); 683 cmd->scsi_done(cmd); 684 } 685 686 void 687 qla2xxx_qpair_sp_free_dma(void *ptr) 688 { 689 srb_t *sp = (srb_t *)ptr; 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 691 struct qla_hw_data *ha = sp->fcport->vha->hw; 692 void *ctx = GET_CMD_CTX_SP(sp); 693 694 if (sp->flags & SRB_DMA_VALID) { 695 scsi_dma_unmap(cmd); 696 sp->flags &= ~SRB_DMA_VALID; 697 } 698 699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 701 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 703 } 704 705 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 706 /* List assured to be having elements */ 707 qla2x00_clean_dsd_pool(ha, sp, NULL); 708 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 709 } 710 711 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 712 dma_pool_free(ha->dl_dma_pool, ctx, 713 ((struct crc_context *)ctx)->crc_ctx_dma); 714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 715 } 716 717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 718 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 719 720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 721 ctx1->fcp_cmnd_dma); 722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 725 mempool_free(ctx1, ha->ctx_mempool); 726 } 727 728 CMD_SP(cmd) = NULL; 729 qla2xxx_rel_qpair_sp(sp->qpair, sp); 730 } 731 732 void 733 qla2xxx_qpair_sp_compl(void *ptr, int res) 734 { 735 srb_t *sp = ptr; 736 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 737 738 cmd->result = res; 739 740 if (atomic_read(&sp->ref_count) == 0) { 741 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 742 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 743 sp, GET_CMD_SP(sp)); 744 if (ql2xextended_error_logging & ql_dbg_io) 745 WARN_ON(atomic_read(&sp->ref_count) == 0); 746 return; 747 } 748 if (!atomic_dec_and_test(&sp->ref_count)) 749 return; 750 751 qla2xxx_qpair_sp_free_dma(sp); 752 cmd->scsi_done(cmd); 753 } 754 755 /* If we are SP1 here, we need to still take and release the host_lock as SP1 756 * does not have the changes necessary to avoid taking host->host_lock. 757 */ 758 static int 759 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 760 { 761 scsi_qla_host_t *vha = shost_priv(host); 762 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 763 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 764 struct qla_hw_data *ha = vha->hw; 765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 766 srb_t *sp; 767 int rval; 768 struct qla_qpair *qpair = NULL; 769 uint32_t tag; 770 uint16_t hwq; 771 772 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 773 cmd->result = DID_NO_CONNECT << 16; 774 goto qc24_fail_command; 775 } 776 777 if (ha->mqenable) { 778 if (shost_use_blk_mq(vha->host)) { 779 tag = blk_mq_unique_tag(cmd->request); 780 hwq = blk_mq_unique_tag_to_hwq(tag); 781 qpair = ha->queue_pair_map[hwq]; 782 } else if (vha->vp_idx && vha->qpair) { 783 qpair = vha->qpair; 784 } 785 786 if (qpair) 787 return qla2xxx_mqueuecommand(host, cmd, qpair); 788 } 789 790 if (ha->flags.eeh_busy) { 791 if (ha->flags.pci_channel_io_perm_failure) { 792 ql_dbg(ql_dbg_aer, vha, 0x9010, 793 "PCI Channel IO permanent failure, exiting " 794 "cmd=%p.\n", cmd); 795 cmd->result = DID_NO_CONNECT << 16; 796 } else { 797 ql_dbg(ql_dbg_aer, vha, 0x9011, 798 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 799 cmd->result = DID_REQUEUE << 16; 800 } 801 goto qc24_fail_command; 802 } 803 804 rval = fc_remote_port_chkready(rport); 805 if (rval) { 806 cmd->result = rval; 807 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 808 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 809 cmd, rval); 810 goto qc24_fail_command; 811 } 812 813 if (!vha->flags.difdix_supported && 814 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 815 ql_dbg(ql_dbg_io, vha, 0x3004, 816 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 817 cmd); 818 cmd->result = DID_NO_CONNECT << 16; 819 goto qc24_fail_command; 820 } 821 822 if (!fcport) { 823 cmd->result = DID_NO_CONNECT << 16; 824 goto qc24_fail_command; 825 } 826 827 if (atomic_read(&fcport->state) != FCS_ONLINE) { 828 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 829 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 830 ql_dbg(ql_dbg_io, vha, 0x3005, 831 "Returning DNC, fcport_state=%d loop_state=%d.\n", 832 atomic_read(&fcport->state), 833 atomic_read(&base_vha->loop_state)); 834 cmd->result = DID_NO_CONNECT << 16; 835 goto qc24_fail_command; 836 } 837 goto qc24_target_busy; 838 } 839 840 /* 841 * Return target busy if we've received a non-zero retry_delay_timer 842 * in a FCP_RSP. 843 */ 844 if (fcport->retry_delay_timestamp == 0) { 845 /* retry delay not set */ 846 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 847 fcport->retry_delay_timestamp = 0; 848 else 849 goto qc24_target_busy; 850 851 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 852 if (!sp) 853 goto qc24_host_busy; 854 855 sp->u.scmd.cmd = cmd; 856 sp->type = SRB_SCSI_CMD; 857 atomic_set(&sp->ref_count, 1); 858 CMD_SP(cmd) = (void *)sp; 859 sp->free = qla2x00_sp_free_dma; 860 sp->done = qla2x00_sp_compl; 861 862 rval = ha->isp_ops->start_scsi(sp); 863 if (rval != QLA_SUCCESS) { 864 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 865 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 866 goto qc24_host_busy_free_sp; 867 } 868 869 return 0; 870 871 qc24_host_busy_free_sp: 872 qla2x00_sp_free_dma(sp); 873 874 qc24_host_busy: 875 return SCSI_MLQUEUE_HOST_BUSY; 876 877 qc24_target_busy: 878 return SCSI_MLQUEUE_TARGET_BUSY; 879 880 qc24_fail_command: 881 cmd->scsi_done(cmd); 882 883 return 0; 884 } 885 886 /* For MQ supported I/O */ 887 int 888 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 889 struct qla_qpair *qpair) 890 { 891 scsi_qla_host_t *vha = shost_priv(host); 892 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 893 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 894 struct qla_hw_data *ha = vha->hw; 895 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 896 srb_t *sp; 897 int rval; 898 899 rval = fc_remote_port_chkready(rport); 900 if (rval) { 901 cmd->result = rval; 902 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 903 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 904 cmd, rval); 905 goto qc24_fail_command; 906 } 907 908 if (!fcport) { 909 cmd->result = DID_NO_CONNECT << 16; 910 goto qc24_fail_command; 911 } 912 913 if (atomic_read(&fcport->state) != FCS_ONLINE) { 914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 916 ql_dbg(ql_dbg_io, vha, 0x3077, 917 "Returning DNC, fcport_state=%d loop_state=%d.\n", 918 atomic_read(&fcport->state), 919 atomic_read(&base_vha->loop_state)); 920 cmd->result = DID_NO_CONNECT << 16; 921 goto qc24_fail_command; 922 } 923 goto qc24_target_busy; 924 } 925 926 /* 927 * Return target busy if we've received a non-zero retry_delay_timer 928 * in a FCP_RSP. 929 */ 930 if (fcport->retry_delay_timestamp == 0) { 931 /* retry delay not set */ 932 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 933 fcport->retry_delay_timestamp = 0; 934 else 935 goto qc24_target_busy; 936 937 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 938 if (!sp) 939 goto qc24_host_busy; 940 941 sp->u.scmd.cmd = cmd; 942 sp->type = SRB_SCSI_CMD; 943 atomic_set(&sp->ref_count, 1); 944 CMD_SP(cmd) = (void *)sp; 945 sp->free = qla2xxx_qpair_sp_free_dma; 946 sp->done = qla2xxx_qpair_sp_compl; 947 sp->qpair = qpair; 948 949 rval = ha->isp_ops->start_scsi_mq(sp); 950 if (rval != QLA_SUCCESS) { 951 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 952 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 953 if (rval == QLA_INTERFACE_ERROR) 954 goto qc24_fail_command; 955 goto qc24_host_busy_free_sp; 956 } 957 958 return 0; 959 960 qc24_host_busy_free_sp: 961 qla2xxx_qpair_sp_free_dma(sp); 962 963 qc24_host_busy: 964 return SCSI_MLQUEUE_HOST_BUSY; 965 966 qc24_target_busy: 967 return SCSI_MLQUEUE_TARGET_BUSY; 968 969 qc24_fail_command: 970 cmd->scsi_done(cmd); 971 972 return 0; 973 } 974 975 /* 976 * qla2x00_eh_wait_on_command 977 * Waits for the command to be returned by the Firmware for some 978 * max time. 979 * 980 * Input: 981 * cmd = Scsi Command to wait on. 982 * 983 * Return: 984 * Not Found : 0 985 * Found : 1 986 */ 987 static int 988 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 989 { 990 #define ABORT_POLLING_PERIOD 1000 991 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 992 unsigned long wait_iter = ABORT_WAIT_ITER; 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 994 struct qla_hw_data *ha = vha->hw; 995 int ret = QLA_SUCCESS; 996 997 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 998 ql_dbg(ql_dbg_taskm, vha, 0x8005, 999 "Return:eh_wait.\n"); 1000 return ret; 1001 } 1002 1003 while (CMD_SP(cmd) && wait_iter--) { 1004 msleep(ABORT_POLLING_PERIOD); 1005 } 1006 if (CMD_SP(cmd)) 1007 ret = QLA_FUNCTION_FAILED; 1008 1009 return ret; 1010 } 1011 1012 /* 1013 * qla2x00_wait_for_hba_online 1014 * Wait till the HBA is online after going through 1015 * <= MAX_RETRIES_OF_ISP_ABORT or 1016 * finally HBA is disabled ie marked offline 1017 * 1018 * Input: 1019 * ha - pointer to host adapter structure 1020 * 1021 * Note: 1022 * Does context switching-Release SPIN_LOCK 1023 * (if any) before calling this routine. 1024 * 1025 * Return: 1026 * Success (Adapter is online) : 0 1027 * Failed (Adapter is offline/disabled) : 1 1028 */ 1029 int 1030 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1031 { 1032 int return_status; 1033 unsigned long wait_online; 1034 struct qla_hw_data *ha = vha->hw; 1035 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1036 1037 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1038 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1039 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1040 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1041 ha->dpc_active) && time_before(jiffies, wait_online)) { 1042 1043 msleep(1000); 1044 } 1045 if (base_vha->flags.online) 1046 return_status = QLA_SUCCESS; 1047 else 1048 return_status = QLA_FUNCTION_FAILED; 1049 1050 return (return_status); 1051 } 1052 1053 static inline int test_fcport_count(scsi_qla_host_t *vha) 1054 { 1055 struct qla_hw_data *ha = vha->hw; 1056 unsigned long flags; 1057 int res; 1058 1059 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1060 ql_dbg(ql_dbg_init, vha, 0xffff, 1061 "tgt %p, fcport_count=%d\n", 1062 vha, vha->fcport_count); 1063 res = (vha->fcport_count == 0); 1064 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1065 1066 return res; 1067 } 1068 1069 /* 1070 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1071 * it has dependency on UNLOADING flag to stop device discovery 1072 */ 1073 static void 1074 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1075 { 1076 qla2x00_mark_all_devices_lost(vha, 0); 1077 1078 wait_event(vha->fcport_waitQ, test_fcport_count(vha)); 1079 } 1080 1081 /* 1082 * qla2x00_wait_for_hba_ready 1083 * Wait till the HBA is ready before doing driver unload 1084 * 1085 * Input: 1086 * ha - pointer to host adapter structure 1087 * 1088 * Note: 1089 * Does context switching-Release SPIN_LOCK 1090 * (if any) before calling this routine. 1091 * 1092 */ 1093 static void 1094 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1095 { 1096 struct qla_hw_data *ha = vha->hw; 1097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1098 1099 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1100 ha->flags.mbox_busy) || 1101 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1102 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1103 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1104 break; 1105 msleep(1000); 1106 } 1107 } 1108 1109 int 1110 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1111 { 1112 int return_status; 1113 unsigned long wait_reset; 1114 struct qla_hw_data *ha = vha->hw; 1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1116 1117 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1121 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1122 1123 msleep(1000); 1124 1125 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1126 ha->flags.chip_reset_done) 1127 break; 1128 } 1129 if (ha->flags.chip_reset_done) 1130 return_status = QLA_SUCCESS; 1131 else 1132 return_status = QLA_FUNCTION_FAILED; 1133 1134 return return_status; 1135 } 1136 1137 static void 1138 sp_get(struct srb *sp) 1139 { 1140 atomic_inc(&sp->ref_count); 1141 } 1142 1143 #define ISP_REG_DISCONNECT 0xffffffffU 1144 /************************************************************************** 1145 * qla2x00_isp_reg_stat 1146 * 1147 * Description: 1148 * Read the host status register of ISP before aborting the command. 1149 * 1150 * Input: 1151 * ha = pointer to host adapter structure. 1152 * 1153 * 1154 * Returns: 1155 * Either true or false. 1156 * 1157 * Note: Return true if there is register disconnect. 1158 **************************************************************************/ 1159 static inline 1160 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1161 { 1162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1163 1164 return ((RD_REG_DWORD(®->host_status)) == ISP_REG_DISCONNECT); 1165 } 1166 1167 /************************************************************************** 1168 * qla2xxx_eh_abort 1169 * 1170 * Description: 1171 * The abort function will abort the specified command. 1172 * 1173 * Input: 1174 * cmd = Linux SCSI command packet to be aborted. 1175 * 1176 * Returns: 1177 * Either SUCCESS or FAILED. 1178 * 1179 * Note: 1180 * Only return FAILED if command not returned by firmware. 1181 **************************************************************************/ 1182 static int 1183 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1184 { 1185 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1186 srb_t *sp; 1187 int ret; 1188 unsigned int id; 1189 uint64_t lun; 1190 unsigned long flags; 1191 int rval, wait = 0; 1192 struct qla_hw_data *ha = vha->hw; 1193 1194 if (qla2x00_isp_reg_stat(ha)) { 1195 ql_log(ql_log_info, vha, 0x8042, 1196 "PCI/Register disconnect, exiting.\n"); 1197 return FAILED; 1198 } 1199 if (!CMD_SP(cmd)) 1200 return SUCCESS; 1201 1202 ret = fc_block_scsi_eh(cmd); 1203 if (ret != 0) 1204 return ret; 1205 ret = SUCCESS; 1206 1207 id = cmd->device->id; 1208 lun = cmd->device->lun; 1209 1210 spin_lock_irqsave(&ha->hardware_lock, flags); 1211 sp = (srb_t *) CMD_SP(cmd); 1212 if (!sp) { 1213 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1214 return SUCCESS; 1215 } 1216 1217 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1218 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1219 vha->host_no, id, lun, sp, cmd, sp->handle); 1220 1221 /* Get a reference to the sp and drop the lock.*/ 1222 sp_get(sp); 1223 1224 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1225 rval = ha->isp_ops->abort_command(sp); 1226 if (rval) { 1227 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1228 ret = SUCCESS; 1229 else 1230 ret = FAILED; 1231 1232 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1233 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1234 } else { 1235 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1236 "Abort command mbx success cmd=%p.\n", cmd); 1237 wait = 1; 1238 } 1239 1240 spin_lock_irqsave(&ha->hardware_lock, flags); 1241 sp->done(sp, 0); 1242 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1243 1244 /* Did the command return during mailbox execution? */ 1245 if (ret == FAILED && !CMD_SP(cmd)) 1246 ret = SUCCESS; 1247 1248 /* Wait for the command to be returned. */ 1249 if (wait) { 1250 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1251 ql_log(ql_log_warn, vha, 0x8006, 1252 "Abort handler timed out cmd=%p.\n", cmd); 1253 ret = FAILED; 1254 } 1255 } 1256 1257 ql_log(ql_log_info, vha, 0x801c, 1258 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1259 vha->host_no, id, lun, wait, ret); 1260 1261 return ret; 1262 } 1263 1264 int 1265 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1266 uint64_t l, enum nexus_wait_type type) 1267 { 1268 int cnt, match, status; 1269 unsigned long flags; 1270 struct qla_hw_data *ha = vha->hw; 1271 struct req_que *req; 1272 srb_t *sp; 1273 struct scsi_cmnd *cmd; 1274 1275 status = QLA_SUCCESS; 1276 1277 spin_lock_irqsave(&ha->hardware_lock, flags); 1278 req = vha->req; 1279 for (cnt = 1; status == QLA_SUCCESS && 1280 cnt < req->num_outstanding_cmds; cnt++) { 1281 sp = req->outstanding_cmds[cnt]; 1282 if (!sp) 1283 continue; 1284 if (sp->type != SRB_SCSI_CMD) 1285 continue; 1286 if (vha->vp_idx != sp->vha->vp_idx) 1287 continue; 1288 match = 0; 1289 cmd = GET_CMD_SP(sp); 1290 switch (type) { 1291 case WAIT_HOST: 1292 match = 1; 1293 break; 1294 case WAIT_TARGET: 1295 match = cmd->device->id == t; 1296 break; 1297 case WAIT_LUN: 1298 match = (cmd->device->id == t && 1299 cmd->device->lun == l); 1300 break; 1301 } 1302 if (!match) 1303 continue; 1304 1305 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1306 status = qla2x00_eh_wait_on_command(cmd); 1307 spin_lock_irqsave(&ha->hardware_lock, flags); 1308 } 1309 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1310 1311 return status; 1312 } 1313 1314 static char *reset_errors[] = { 1315 "HBA not online", 1316 "HBA not ready", 1317 "Task management failed", 1318 "Waiting for command completions", 1319 }; 1320 1321 static int 1322 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1323 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1324 { 1325 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1326 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1327 int err; 1328 1329 if (!fcport) { 1330 return FAILED; 1331 } 1332 1333 err = fc_block_scsi_eh(cmd); 1334 if (err != 0) 1335 return err; 1336 1337 ql_log(ql_log_info, vha, 0x8009, 1338 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1339 cmd->device->id, cmd->device->lun, cmd); 1340 1341 err = 0; 1342 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1343 ql_log(ql_log_warn, vha, 0x800a, 1344 "Wait for hba online failed for cmd=%p.\n", cmd); 1345 goto eh_reset_failed; 1346 } 1347 err = 2; 1348 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1349 != QLA_SUCCESS) { 1350 ql_log(ql_log_warn, vha, 0x800c, 1351 "do_reset failed for cmd=%p.\n", cmd); 1352 goto eh_reset_failed; 1353 } 1354 err = 3; 1355 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1356 cmd->device->lun, type) != QLA_SUCCESS) { 1357 ql_log(ql_log_warn, vha, 0x800d, 1358 "wait for pending cmds failed for cmd=%p.\n", cmd); 1359 goto eh_reset_failed; 1360 } 1361 1362 ql_log(ql_log_info, vha, 0x800e, 1363 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1364 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1365 1366 return SUCCESS; 1367 1368 eh_reset_failed: 1369 ql_log(ql_log_info, vha, 0x800f, 1370 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1371 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1372 cmd); 1373 return FAILED; 1374 } 1375 1376 static int 1377 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1378 { 1379 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1380 struct qla_hw_data *ha = vha->hw; 1381 1382 if (qla2x00_isp_reg_stat(ha)) { 1383 ql_log(ql_log_info, vha, 0x803e, 1384 "PCI/Register disconnect, exiting.\n"); 1385 return FAILED; 1386 } 1387 1388 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1389 ha->isp_ops->lun_reset); 1390 } 1391 1392 static int 1393 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1394 { 1395 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1396 struct qla_hw_data *ha = vha->hw; 1397 1398 if (qla2x00_isp_reg_stat(ha)) { 1399 ql_log(ql_log_info, vha, 0x803f, 1400 "PCI/Register disconnect, exiting.\n"); 1401 return FAILED; 1402 } 1403 1404 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1405 ha->isp_ops->target_reset); 1406 } 1407 1408 /************************************************************************** 1409 * qla2xxx_eh_bus_reset 1410 * 1411 * Description: 1412 * The bus reset function will reset the bus and abort any executing 1413 * commands. 1414 * 1415 * Input: 1416 * cmd = Linux SCSI command packet of the command that cause the 1417 * bus reset. 1418 * 1419 * Returns: 1420 * SUCCESS/FAILURE (defined as macro in scsi.h). 1421 * 1422 **************************************************************************/ 1423 static int 1424 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1425 { 1426 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1427 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1428 int ret = FAILED; 1429 unsigned int id; 1430 uint64_t lun; 1431 struct qla_hw_data *ha = vha->hw; 1432 1433 if (qla2x00_isp_reg_stat(ha)) { 1434 ql_log(ql_log_info, vha, 0x8040, 1435 "PCI/Register disconnect, exiting.\n"); 1436 return FAILED; 1437 } 1438 1439 id = cmd->device->id; 1440 lun = cmd->device->lun; 1441 1442 if (!fcport) { 1443 return ret; 1444 } 1445 1446 ret = fc_block_scsi_eh(cmd); 1447 if (ret != 0) 1448 return ret; 1449 ret = FAILED; 1450 1451 ql_log(ql_log_info, vha, 0x8012, 1452 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1453 1454 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1455 ql_log(ql_log_fatal, vha, 0x8013, 1456 "Wait for hba online failed board disabled.\n"); 1457 goto eh_bus_reset_done; 1458 } 1459 1460 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1461 ret = SUCCESS; 1462 1463 if (ret == FAILED) 1464 goto eh_bus_reset_done; 1465 1466 /* Flush outstanding commands. */ 1467 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1468 QLA_SUCCESS) { 1469 ql_log(ql_log_warn, vha, 0x8014, 1470 "Wait for pending commands failed.\n"); 1471 ret = FAILED; 1472 } 1473 1474 eh_bus_reset_done: 1475 ql_log(ql_log_warn, vha, 0x802b, 1476 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1477 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1478 1479 return ret; 1480 } 1481 1482 /************************************************************************** 1483 * qla2xxx_eh_host_reset 1484 * 1485 * Description: 1486 * The reset function will reset the Adapter. 1487 * 1488 * Input: 1489 * cmd = Linux SCSI command packet of the command that cause the 1490 * adapter reset. 1491 * 1492 * Returns: 1493 * Either SUCCESS or FAILED. 1494 * 1495 * Note: 1496 **************************************************************************/ 1497 static int 1498 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1499 { 1500 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1501 struct qla_hw_data *ha = vha->hw; 1502 int ret = FAILED; 1503 unsigned int id; 1504 uint64_t lun; 1505 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1506 1507 if (qla2x00_isp_reg_stat(ha)) { 1508 ql_log(ql_log_info, vha, 0x8041, 1509 "PCI/Register disconnect, exiting.\n"); 1510 schedule_work(&ha->board_disable); 1511 return SUCCESS; 1512 } 1513 1514 id = cmd->device->id; 1515 lun = cmd->device->lun; 1516 1517 ql_log(ql_log_info, vha, 0x8018, 1518 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1519 1520 /* 1521 * No point in issuing another reset if one is active. Also do not 1522 * attempt a reset if we are updating flash. 1523 */ 1524 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1525 goto eh_host_reset_lock; 1526 1527 if (vha != base_vha) { 1528 if (qla2x00_vp_abort_isp(vha)) 1529 goto eh_host_reset_lock; 1530 } else { 1531 if (IS_P3P_TYPE(vha->hw)) { 1532 if (!qla82xx_fcoe_ctx_reset(vha)) { 1533 /* Ctx reset success */ 1534 ret = SUCCESS; 1535 goto eh_host_reset_lock; 1536 } 1537 /* fall thru if ctx reset failed */ 1538 } 1539 if (ha->wq) 1540 flush_workqueue(ha->wq); 1541 1542 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1543 if (ha->isp_ops->abort_isp(base_vha)) { 1544 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1545 /* failed. schedule dpc to try */ 1546 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1547 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1549 ql_log(ql_log_warn, vha, 0x802a, 1550 "wait for hba online failed.\n"); 1551 goto eh_host_reset_lock; 1552 } 1553 } 1554 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1555 } 1556 1557 /* Waiting for command to be returned to OS.*/ 1558 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1559 QLA_SUCCESS) 1560 ret = SUCCESS; 1561 1562 eh_host_reset_lock: 1563 ql_log(ql_log_info, vha, 0x8017, 1564 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1565 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1566 1567 return ret; 1568 } 1569 1570 /* 1571 * qla2x00_loop_reset 1572 * Issue loop reset. 1573 * 1574 * Input: 1575 * ha = adapter block pointer. 1576 * 1577 * Returns: 1578 * 0 = success 1579 */ 1580 int 1581 qla2x00_loop_reset(scsi_qla_host_t *vha) 1582 { 1583 int ret; 1584 struct fc_port *fcport; 1585 struct qla_hw_data *ha = vha->hw; 1586 1587 if (IS_QLAFX00(ha)) { 1588 return qlafx00_loop_reset(vha); 1589 } 1590 1591 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1592 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1593 if (fcport->port_type != FCT_TARGET) 1594 continue; 1595 1596 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1597 if (ret != QLA_SUCCESS) { 1598 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1599 "Bus Reset failed: Reset=%d " 1600 "d_id=%x.\n", ret, fcport->d_id.b24); 1601 } 1602 } 1603 } 1604 1605 1606 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1607 atomic_set(&vha->loop_state, LOOP_DOWN); 1608 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1609 qla2x00_mark_all_devices_lost(vha, 0); 1610 ret = qla2x00_full_login_lip(vha); 1611 if (ret != QLA_SUCCESS) { 1612 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1613 "full_login_lip=%d.\n", ret); 1614 } 1615 } 1616 1617 if (ha->flags.enable_lip_reset) { 1618 ret = qla2x00_lip_reset(vha); 1619 if (ret != QLA_SUCCESS) 1620 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1621 "lip_reset failed (%d).\n", ret); 1622 } 1623 1624 /* Issue marker command only when we are going to start the I/O */ 1625 vha->marker_needed = 1; 1626 1627 return QLA_SUCCESS; 1628 } 1629 1630 void 1631 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1632 { 1633 int que, cnt; 1634 unsigned long flags; 1635 srb_t *sp; 1636 struct qla_hw_data *ha = vha->hw; 1637 struct req_que *req; 1638 1639 qlt_host_reset_handler(ha); 1640 1641 spin_lock_irqsave(&ha->hardware_lock, flags); 1642 for (que = 0; que < ha->max_req_queues; que++) { 1643 req = ha->req_q_map[que]; 1644 if (!req) 1645 continue; 1646 if (!req->outstanding_cmds) 1647 continue; 1648 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1649 sp = req->outstanding_cmds[cnt]; 1650 if (sp) { 1651 /* Don't abort commands in adapter during EEH 1652 * recovery as it's not accessible/responding. 1653 */ 1654 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy) { 1655 /* Get a reference to the sp and drop the lock. 1656 * The reference ensures this sp->done() call 1657 * - and not the call in qla2xxx_eh_abort() - 1658 * ends the SCSI command (with result 'res'). 1659 */ 1660 sp_get(sp); 1661 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1662 qla2xxx_eh_abort(GET_CMD_SP(sp)); 1663 spin_lock_irqsave(&ha->hardware_lock, flags); 1664 } 1665 req->outstanding_cmds[cnt] = NULL; 1666 sp->done(sp, res); 1667 } 1668 } 1669 } 1670 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1671 } 1672 1673 static int 1674 qla2xxx_slave_alloc(struct scsi_device *sdev) 1675 { 1676 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1677 1678 if (!rport || fc_remote_port_chkready(rport)) 1679 return -ENXIO; 1680 1681 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1682 1683 return 0; 1684 } 1685 1686 static int 1687 qla2xxx_slave_configure(struct scsi_device *sdev) 1688 { 1689 scsi_qla_host_t *vha = shost_priv(sdev->host); 1690 struct req_que *req = vha->req; 1691 1692 if (IS_T10_PI_CAPABLE(vha->hw)) 1693 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1694 1695 scsi_change_queue_depth(sdev, req->max_q_depth); 1696 return 0; 1697 } 1698 1699 static void 1700 qla2xxx_slave_destroy(struct scsi_device *sdev) 1701 { 1702 sdev->hostdata = NULL; 1703 } 1704 1705 /** 1706 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1707 * @ha: HA context 1708 * 1709 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1710 * supported addressing method. 1711 */ 1712 static void 1713 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1714 { 1715 /* Assume a 32bit DMA mask. */ 1716 ha->flags.enable_64bit_addressing = 0; 1717 1718 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1719 /* Any upper-dword bits set? */ 1720 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1721 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1722 /* Ok, a 64bit DMA mask is applicable. */ 1723 ha->flags.enable_64bit_addressing = 1; 1724 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1725 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1726 return; 1727 } 1728 } 1729 1730 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1731 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1732 } 1733 1734 static void 1735 qla2x00_enable_intrs(struct qla_hw_data *ha) 1736 { 1737 unsigned long flags = 0; 1738 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1739 1740 spin_lock_irqsave(&ha->hardware_lock, flags); 1741 ha->interrupts_on = 1; 1742 /* enable risc and host interrupts */ 1743 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1744 RD_REG_WORD(®->ictrl); 1745 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1746 1747 } 1748 1749 static void 1750 qla2x00_disable_intrs(struct qla_hw_data *ha) 1751 { 1752 unsigned long flags = 0; 1753 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1754 1755 spin_lock_irqsave(&ha->hardware_lock, flags); 1756 ha->interrupts_on = 0; 1757 /* disable risc and host interrupts */ 1758 WRT_REG_WORD(®->ictrl, 0); 1759 RD_REG_WORD(®->ictrl); 1760 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1761 } 1762 1763 static void 1764 qla24xx_enable_intrs(struct qla_hw_data *ha) 1765 { 1766 unsigned long flags = 0; 1767 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1768 1769 spin_lock_irqsave(&ha->hardware_lock, flags); 1770 ha->interrupts_on = 1; 1771 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1772 RD_REG_DWORD(®->ictrl); 1773 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1774 } 1775 1776 static void 1777 qla24xx_disable_intrs(struct qla_hw_data *ha) 1778 { 1779 unsigned long flags = 0; 1780 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1781 1782 if (IS_NOPOLLING_TYPE(ha)) 1783 return; 1784 spin_lock_irqsave(&ha->hardware_lock, flags); 1785 ha->interrupts_on = 0; 1786 WRT_REG_DWORD(®->ictrl, 0); 1787 RD_REG_DWORD(®->ictrl); 1788 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1789 } 1790 1791 static int 1792 qla2x00_iospace_config(struct qla_hw_data *ha) 1793 { 1794 resource_size_t pio; 1795 uint16_t msix; 1796 1797 if (pci_request_selected_regions(ha->pdev, ha->bars, 1798 QLA2XXX_DRIVER_NAME)) { 1799 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1800 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1801 pci_name(ha->pdev)); 1802 goto iospace_error_exit; 1803 } 1804 if (!(ha->bars & 1)) 1805 goto skip_pio; 1806 1807 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1808 pio = pci_resource_start(ha->pdev, 0); 1809 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1810 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1811 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1812 "Invalid pci I/O region size (%s).\n", 1813 pci_name(ha->pdev)); 1814 pio = 0; 1815 } 1816 } else { 1817 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1818 "Region #0 no a PIO resource (%s).\n", 1819 pci_name(ha->pdev)); 1820 pio = 0; 1821 } 1822 ha->pio_address = pio; 1823 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1824 "PIO address=%llu.\n", 1825 (unsigned long long)ha->pio_address); 1826 1827 skip_pio: 1828 /* Use MMIO operations for all accesses. */ 1829 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1830 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1831 "Region #1 not an MMIO resource (%s), aborting.\n", 1832 pci_name(ha->pdev)); 1833 goto iospace_error_exit; 1834 } 1835 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1836 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1837 "Invalid PCI mem region size (%s), aborting.\n", 1838 pci_name(ha->pdev)); 1839 goto iospace_error_exit; 1840 } 1841 1842 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1843 if (!ha->iobase) { 1844 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1845 "Cannot remap MMIO (%s), aborting.\n", 1846 pci_name(ha->pdev)); 1847 goto iospace_error_exit; 1848 } 1849 1850 /* Determine queue resources */ 1851 ha->max_req_queues = ha->max_rsp_queues = 1; 1852 ha->msix_count = QLA_BASE_VECTORS; 1853 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1854 goto mqiobase_exit; 1855 1856 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1857 pci_resource_len(ha->pdev, 3)); 1858 if (ha->mqiobase) { 1859 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1860 "MQIO Base=%p.\n", ha->mqiobase); 1861 /* Read MSIX vector size of the board */ 1862 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1863 ha->msix_count = msix + 1; 1864 /* Max queues are bounded by available msix vectors */ 1865 /* MB interrupt uses 1 vector */ 1866 ha->max_req_queues = ha->msix_count - 1; 1867 ha->max_rsp_queues = ha->max_req_queues; 1868 /* Queue pairs is the max value minus the base queue pair */ 1869 ha->max_qpairs = ha->max_rsp_queues - 1; 1870 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 1871 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1872 1873 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1874 "MSI-X vector count: %d.\n", ha->msix_count); 1875 } else 1876 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1877 "BAR 3 not enabled.\n"); 1878 1879 mqiobase_exit: 1880 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1881 "MSIX Count: %d.\n", ha->msix_count); 1882 return (0); 1883 1884 iospace_error_exit: 1885 return (-ENOMEM); 1886 } 1887 1888 1889 static int 1890 qla83xx_iospace_config(struct qla_hw_data *ha) 1891 { 1892 uint16_t msix; 1893 1894 if (pci_request_selected_regions(ha->pdev, ha->bars, 1895 QLA2XXX_DRIVER_NAME)) { 1896 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1897 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1898 pci_name(ha->pdev)); 1899 1900 goto iospace_error_exit; 1901 } 1902 1903 /* Use MMIO operations for all accesses. */ 1904 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1905 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1906 "Invalid pci I/O region size (%s).\n", 1907 pci_name(ha->pdev)); 1908 goto iospace_error_exit; 1909 } 1910 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1912 "Invalid PCI mem region size (%s), aborting\n", 1913 pci_name(ha->pdev)); 1914 goto iospace_error_exit; 1915 } 1916 1917 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1918 if (!ha->iobase) { 1919 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1920 "Cannot remap MMIO (%s), aborting.\n", 1921 pci_name(ha->pdev)); 1922 goto iospace_error_exit; 1923 } 1924 1925 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1926 /* 83XX 26XX always use MQ type access for queues 1927 * - mbar 2, a.k.a region 4 */ 1928 ha->max_req_queues = ha->max_rsp_queues = 1; 1929 ha->msix_count = QLA_BASE_VECTORS; 1930 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1931 pci_resource_len(ha->pdev, 4)); 1932 1933 if (!ha->mqiobase) { 1934 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1935 "BAR2/region4 not enabled\n"); 1936 goto mqiobase_exit; 1937 } 1938 1939 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1940 pci_resource_len(ha->pdev, 2)); 1941 if (ha->msixbase) { 1942 /* Read MSIX vector size of the board */ 1943 pci_read_config_word(ha->pdev, 1944 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1945 ha->msix_count = msix + 1; 1946 /* 1947 * By default, driver uses at least two msix vectors 1948 * (default & rspq) 1949 */ 1950 if (ql2xmqsupport) { 1951 /* MB interrupt uses 1 vector */ 1952 ha->max_req_queues = ha->msix_count - 1; 1953 1954 /* ATIOQ needs 1 vector. That's 1 less QPair */ 1955 if (QLA_TGT_MODE_ENABLED()) 1956 ha->max_req_queues--; 1957 1958 ha->max_rsp_queues = ha->max_req_queues; 1959 1960 /* Queue pairs is the max value minus 1961 * the base queue pair */ 1962 ha->max_qpairs = ha->max_req_queues - 1; 1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190, 1964 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1965 } 1966 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1967 "MSI-X vector count: %d.\n", ha->msix_count); 1968 } else 1969 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1970 "BAR 1 not enabled.\n"); 1971 1972 mqiobase_exit: 1973 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1974 "MSIX Count: %d.\n", ha->msix_count); 1975 return 0; 1976 1977 iospace_error_exit: 1978 return -ENOMEM; 1979 } 1980 1981 static struct isp_operations qla2100_isp_ops = { 1982 .pci_config = qla2100_pci_config, 1983 .reset_chip = qla2x00_reset_chip, 1984 .chip_diag = qla2x00_chip_diag, 1985 .config_rings = qla2x00_config_rings, 1986 .reset_adapter = qla2x00_reset_adapter, 1987 .nvram_config = qla2x00_nvram_config, 1988 .update_fw_options = qla2x00_update_fw_options, 1989 .load_risc = qla2x00_load_risc, 1990 .pci_info_str = qla2x00_pci_info_str, 1991 .fw_version_str = qla2x00_fw_version_str, 1992 .intr_handler = qla2100_intr_handler, 1993 .enable_intrs = qla2x00_enable_intrs, 1994 .disable_intrs = qla2x00_disable_intrs, 1995 .abort_command = qla2x00_abort_command, 1996 .target_reset = qla2x00_abort_target, 1997 .lun_reset = qla2x00_lun_reset, 1998 .fabric_login = qla2x00_login_fabric, 1999 .fabric_logout = qla2x00_fabric_logout, 2000 .calc_req_entries = qla2x00_calc_iocbs_32, 2001 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2002 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2003 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2004 .read_nvram = qla2x00_read_nvram_data, 2005 .write_nvram = qla2x00_write_nvram_data, 2006 .fw_dump = qla2100_fw_dump, 2007 .beacon_on = NULL, 2008 .beacon_off = NULL, 2009 .beacon_blink = NULL, 2010 .read_optrom = qla2x00_read_optrom_data, 2011 .write_optrom = qla2x00_write_optrom_data, 2012 .get_flash_version = qla2x00_get_flash_version, 2013 .start_scsi = qla2x00_start_scsi, 2014 .start_scsi_mq = NULL, 2015 .abort_isp = qla2x00_abort_isp, 2016 .iospace_config = qla2x00_iospace_config, 2017 .initialize_adapter = qla2x00_initialize_adapter, 2018 }; 2019 2020 static struct isp_operations qla2300_isp_ops = { 2021 .pci_config = qla2300_pci_config, 2022 .reset_chip = qla2x00_reset_chip, 2023 .chip_diag = qla2x00_chip_diag, 2024 .config_rings = qla2x00_config_rings, 2025 .reset_adapter = qla2x00_reset_adapter, 2026 .nvram_config = qla2x00_nvram_config, 2027 .update_fw_options = qla2x00_update_fw_options, 2028 .load_risc = qla2x00_load_risc, 2029 .pci_info_str = qla2x00_pci_info_str, 2030 .fw_version_str = qla2x00_fw_version_str, 2031 .intr_handler = qla2300_intr_handler, 2032 .enable_intrs = qla2x00_enable_intrs, 2033 .disable_intrs = qla2x00_disable_intrs, 2034 .abort_command = qla2x00_abort_command, 2035 .target_reset = qla2x00_abort_target, 2036 .lun_reset = qla2x00_lun_reset, 2037 .fabric_login = qla2x00_login_fabric, 2038 .fabric_logout = qla2x00_fabric_logout, 2039 .calc_req_entries = qla2x00_calc_iocbs_32, 2040 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2041 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2042 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2043 .read_nvram = qla2x00_read_nvram_data, 2044 .write_nvram = qla2x00_write_nvram_data, 2045 .fw_dump = qla2300_fw_dump, 2046 .beacon_on = qla2x00_beacon_on, 2047 .beacon_off = qla2x00_beacon_off, 2048 .beacon_blink = qla2x00_beacon_blink, 2049 .read_optrom = qla2x00_read_optrom_data, 2050 .write_optrom = qla2x00_write_optrom_data, 2051 .get_flash_version = qla2x00_get_flash_version, 2052 .start_scsi = qla2x00_start_scsi, 2053 .start_scsi_mq = NULL, 2054 .abort_isp = qla2x00_abort_isp, 2055 .iospace_config = qla2x00_iospace_config, 2056 .initialize_adapter = qla2x00_initialize_adapter, 2057 }; 2058 2059 static struct isp_operations qla24xx_isp_ops = { 2060 .pci_config = qla24xx_pci_config, 2061 .reset_chip = qla24xx_reset_chip, 2062 .chip_diag = qla24xx_chip_diag, 2063 .config_rings = qla24xx_config_rings, 2064 .reset_adapter = qla24xx_reset_adapter, 2065 .nvram_config = qla24xx_nvram_config, 2066 .update_fw_options = qla24xx_update_fw_options, 2067 .load_risc = qla24xx_load_risc, 2068 .pci_info_str = qla24xx_pci_info_str, 2069 .fw_version_str = qla24xx_fw_version_str, 2070 .intr_handler = qla24xx_intr_handler, 2071 .enable_intrs = qla24xx_enable_intrs, 2072 .disable_intrs = qla24xx_disable_intrs, 2073 .abort_command = qla24xx_abort_command, 2074 .target_reset = qla24xx_abort_target, 2075 .lun_reset = qla24xx_lun_reset, 2076 .fabric_login = qla24xx_login_fabric, 2077 .fabric_logout = qla24xx_fabric_logout, 2078 .calc_req_entries = NULL, 2079 .build_iocbs = NULL, 2080 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2081 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2082 .read_nvram = qla24xx_read_nvram_data, 2083 .write_nvram = qla24xx_write_nvram_data, 2084 .fw_dump = qla24xx_fw_dump, 2085 .beacon_on = qla24xx_beacon_on, 2086 .beacon_off = qla24xx_beacon_off, 2087 .beacon_blink = qla24xx_beacon_blink, 2088 .read_optrom = qla24xx_read_optrom_data, 2089 .write_optrom = qla24xx_write_optrom_data, 2090 .get_flash_version = qla24xx_get_flash_version, 2091 .start_scsi = qla24xx_start_scsi, 2092 .start_scsi_mq = NULL, 2093 .abort_isp = qla2x00_abort_isp, 2094 .iospace_config = qla2x00_iospace_config, 2095 .initialize_adapter = qla2x00_initialize_adapter, 2096 }; 2097 2098 static struct isp_operations qla25xx_isp_ops = { 2099 .pci_config = qla25xx_pci_config, 2100 .reset_chip = qla24xx_reset_chip, 2101 .chip_diag = qla24xx_chip_diag, 2102 .config_rings = qla24xx_config_rings, 2103 .reset_adapter = qla24xx_reset_adapter, 2104 .nvram_config = qla24xx_nvram_config, 2105 .update_fw_options = qla24xx_update_fw_options, 2106 .load_risc = qla24xx_load_risc, 2107 .pci_info_str = qla24xx_pci_info_str, 2108 .fw_version_str = qla24xx_fw_version_str, 2109 .intr_handler = qla24xx_intr_handler, 2110 .enable_intrs = qla24xx_enable_intrs, 2111 .disable_intrs = qla24xx_disable_intrs, 2112 .abort_command = qla24xx_abort_command, 2113 .target_reset = qla24xx_abort_target, 2114 .lun_reset = qla24xx_lun_reset, 2115 .fabric_login = qla24xx_login_fabric, 2116 .fabric_logout = qla24xx_fabric_logout, 2117 .calc_req_entries = NULL, 2118 .build_iocbs = NULL, 2119 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2120 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2121 .read_nvram = qla25xx_read_nvram_data, 2122 .write_nvram = qla25xx_write_nvram_data, 2123 .fw_dump = qla25xx_fw_dump, 2124 .beacon_on = qla24xx_beacon_on, 2125 .beacon_off = qla24xx_beacon_off, 2126 .beacon_blink = qla24xx_beacon_blink, 2127 .read_optrom = qla25xx_read_optrom_data, 2128 .write_optrom = qla24xx_write_optrom_data, 2129 .get_flash_version = qla24xx_get_flash_version, 2130 .start_scsi = qla24xx_dif_start_scsi, 2131 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2132 .abort_isp = qla2x00_abort_isp, 2133 .iospace_config = qla2x00_iospace_config, 2134 .initialize_adapter = qla2x00_initialize_adapter, 2135 }; 2136 2137 static struct isp_operations qla81xx_isp_ops = { 2138 .pci_config = qla25xx_pci_config, 2139 .reset_chip = qla24xx_reset_chip, 2140 .chip_diag = qla24xx_chip_diag, 2141 .config_rings = qla24xx_config_rings, 2142 .reset_adapter = qla24xx_reset_adapter, 2143 .nvram_config = qla81xx_nvram_config, 2144 .update_fw_options = qla81xx_update_fw_options, 2145 .load_risc = qla81xx_load_risc, 2146 .pci_info_str = qla24xx_pci_info_str, 2147 .fw_version_str = qla24xx_fw_version_str, 2148 .intr_handler = qla24xx_intr_handler, 2149 .enable_intrs = qla24xx_enable_intrs, 2150 .disable_intrs = qla24xx_disable_intrs, 2151 .abort_command = qla24xx_abort_command, 2152 .target_reset = qla24xx_abort_target, 2153 .lun_reset = qla24xx_lun_reset, 2154 .fabric_login = qla24xx_login_fabric, 2155 .fabric_logout = qla24xx_fabric_logout, 2156 .calc_req_entries = NULL, 2157 .build_iocbs = NULL, 2158 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2159 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2160 .read_nvram = NULL, 2161 .write_nvram = NULL, 2162 .fw_dump = qla81xx_fw_dump, 2163 .beacon_on = qla24xx_beacon_on, 2164 .beacon_off = qla24xx_beacon_off, 2165 .beacon_blink = qla83xx_beacon_blink, 2166 .read_optrom = qla25xx_read_optrom_data, 2167 .write_optrom = qla24xx_write_optrom_data, 2168 .get_flash_version = qla24xx_get_flash_version, 2169 .start_scsi = qla24xx_dif_start_scsi, 2170 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2171 .abort_isp = qla2x00_abort_isp, 2172 .iospace_config = qla2x00_iospace_config, 2173 .initialize_adapter = qla2x00_initialize_adapter, 2174 }; 2175 2176 static struct isp_operations qla82xx_isp_ops = { 2177 .pci_config = qla82xx_pci_config, 2178 .reset_chip = qla82xx_reset_chip, 2179 .chip_diag = qla24xx_chip_diag, 2180 .config_rings = qla82xx_config_rings, 2181 .reset_adapter = qla24xx_reset_adapter, 2182 .nvram_config = qla81xx_nvram_config, 2183 .update_fw_options = qla24xx_update_fw_options, 2184 .load_risc = qla82xx_load_risc, 2185 .pci_info_str = qla24xx_pci_info_str, 2186 .fw_version_str = qla24xx_fw_version_str, 2187 .intr_handler = qla82xx_intr_handler, 2188 .enable_intrs = qla82xx_enable_intrs, 2189 .disable_intrs = qla82xx_disable_intrs, 2190 .abort_command = qla24xx_abort_command, 2191 .target_reset = qla24xx_abort_target, 2192 .lun_reset = qla24xx_lun_reset, 2193 .fabric_login = qla24xx_login_fabric, 2194 .fabric_logout = qla24xx_fabric_logout, 2195 .calc_req_entries = NULL, 2196 .build_iocbs = NULL, 2197 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2198 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2199 .read_nvram = qla24xx_read_nvram_data, 2200 .write_nvram = qla24xx_write_nvram_data, 2201 .fw_dump = qla82xx_fw_dump, 2202 .beacon_on = qla82xx_beacon_on, 2203 .beacon_off = qla82xx_beacon_off, 2204 .beacon_blink = NULL, 2205 .read_optrom = qla82xx_read_optrom_data, 2206 .write_optrom = qla82xx_write_optrom_data, 2207 .get_flash_version = qla82xx_get_flash_version, 2208 .start_scsi = qla82xx_start_scsi, 2209 .start_scsi_mq = NULL, 2210 .abort_isp = qla82xx_abort_isp, 2211 .iospace_config = qla82xx_iospace_config, 2212 .initialize_adapter = qla2x00_initialize_adapter, 2213 }; 2214 2215 static struct isp_operations qla8044_isp_ops = { 2216 .pci_config = qla82xx_pci_config, 2217 .reset_chip = qla82xx_reset_chip, 2218 .chip_diag = qla24xx_chip_diag, 2219 .config_rings = qla82xx_config_rings, 2220 .reset_adapter = qla24xx_reset_adapter, 2221 .nvram_config = qla81xx_nvram_config, 2222 .update_fw_options = qla24xx_update_fw_options, 2223 .load_risc = qla82xx_load_risc, 2224 .pci_info_str = qla24xx_pci_info_str, 2225 .fw_version_str = qla24xx_fw_version_str, 2226 .intr_handler = qla8044_intr_handler, 2227 .enable_intrs = qla82xx_enable_intrs, 2228 .disable_intrs = qla82xx_disable_intrs, 2229 .abort_command = qla24xx_abort_command, 2230 .target_reset = qla24xx_abort_target, 2231 .lun_reset = qla24xx_lun_reset, 2232 .fabric_login = qla24xx_login_fabric, 2233 .fabric_logout = qla24xx_fabric_logout, 2234 .calc_req_entries = NULL, 2235 .build_iocbs = NULL, 2236 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2237 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2238 .read_nvram = NULL, 2239 .write_nvram = NULL, 2240 .fw_dump = qla8044_fw_dump, 2241 .beacon_on = qla82xx_beacon_on, 2242 .beacon_off = qla82xx_beacon_off, 2243 .beacon_blink = NULL, 2244 .read_optrom = qla8044_read_optrom_data, 2245 .write_optrom = qla8044_write_optrom_data, 2246 .get_flash_version = qla82xx_get_flash_version, 2247 .start_scsi = qla82xx_start_scsi, 2248 .start_scsi_mq = NULL, 2249 .abort_isp = qla8044_abort_isp, 2250 .iospace_config = qla82xx_iospace_config, 2251 .initialize_adapter = qla2x00_initialize_adapter, 2252 }; 2253 2254 static struct isp_operations qla83xx_isp_ops = { 2255 .pci_config = qla25xx_pci_config, 2256 .reset_chip = qla24xx_reset_chip, 2257 .chip_diag = qla24xx_chip_diag, 2258 .config_rings = qla24xx_config_rings, 2259 .reset_adapter = qla24xx_reset_adapter, 2260 .nvram_config = qla81xx_nvram_config, 2261 .update_fw_options = qla81xx_update_fw_options, 2262 .load_risc = qla81xx_load_risc, 2263 .pci_info_str = qla24xx_pci_info_str, 2264 .fw_version_str = qla24xx_fw_version_str, 2265 .intr_handler = qla24xx_intr_handler, 2266 .enable_intrs = qla24xx_enable_intrs, 2267 .disable_intrs = qla24xx_disable_intrs, 2268 .abort_command = qla24xx_abort_command, 2269 .target_reset = qla24xx_abort_target, 2270 .lun_reset = qla24xx_lun_reset, 2271 .fabric_login = qla24xx_login_fabric, 2272 .fabric_logout = qla24xx_fabric_logout, 2273 .calc_req_entries = NULL, 2274 .build_iocbs = NULL, 2275 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2276 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2277 .read_nvram = NULL, 2278 .write_nvram = NULL, 2279 .fw_dump = qla83xx_fw_dump, 2280 .beacon_on = qla24xx_beacon_on, 2281 .beacon_off = qla24xx_beacon_off, 2282 .beacon_blink = qla83xx_beacon_blink, 2283 .read_optrom = qla25xx_read_optrom_data, 2284 .write_optrom = qla24xx_write_optrom_data, 2285 .get_flash_version = qla24xx_get_flash_version, 2286 .start_scsi = qla24xx_dif_start_scsi, 2287 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2288 .abort_isp = qla2x00_abort_isp, 2289 .iospace_config = qla83xx_iospace_config, 2290 .initialize_adapter = qla2x00_initialize_adapter, 2291 }; 2292 2293 static struct isp_operations qlafx00_isp_ops = { 2294 .pci_config = qlafx00_pci_config, 2295 .reset_chip = qlafx00_soft_reset, 2296 .chip_diag = qlafx00_chip_diag, 2297 .config_rings = qlafx00_config_rings, 2298 .reset_adapter = qlafx00_soft_reset, 2299 .nvram_config = NULL, 2300 .update_fw_options = NULL, 2301 .load_risc = NULL, 2302 .pci_info_str = qlafx00_pci_info_str, 2303 .fw_version_str = qlafx00_fw_version_str, 2304 .intr_handler = qlafx00_intr_handler, 2305 .enable_intrs = qlafx00_enable_intrs, 2306 .disable_intrs = qlafx00_disable_intrs, 2307 .abort_command = qla24xx_async_abort_command, 2308 .target_reset = qlafx00_abort_target, 2309 .lun_reset = qlafx00_lun_reset, 2310 .fabric_login = NULL, 2311 .fabric_logout = NULL, 2312 .calc_req_entries = NULL, 2313 .build_iocbs = NULL, 2314 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2315 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2316 .read_nvram = qla24xx_read_nvram_data, 2317 .write_nvram = qla24xx_write_nvram_data, 2318 .fw_dump = NULL, 2319 .beacon_on = qla24xx_beacon_on, 2320 .beacon_off = qla24xx_beacon_off, 2321 .beacon_blink = NULL, 2322 .read_optrom = qla24xx_read_optrom_data, 2323 .write_optrom = qla24xx_write_optrom_data, 2324 .get_flash_version = qla24xx_get_flash_version, 2325 .start_scsi = qlafx00_start_scsi, 2326 .start_scsi_mq = NULL, 2327 .abort_isp = qlafx00_abort_isp, 2328 .iospace_config = qlafx00_iospace_config, 2329 .initialize_adapter = qlafx00_initialize_adapter, 2330 }; 2331 2332 static struct isp_operations qla27xx_isp_ops = { 2333 .pci_config = qla25xx_pci_config, 2334 .reset_chip = qla24xx_reset_chip, 2335 .chip_diag = qla24xx_chip_diag, 2336 .config_rings = qla24xx_config_rings, 2337 .reset_adapter = qla24xx_reset_adapter, 2338 .nvram_config = qla81xx_nvram_config, 2339 .update_fw_options = qla81xx_update_fw_options, 2340 .load_risc = qla81xx_load_risc, 2341 .pci_info_str = qla24xx_pci_info_str, 2342 .fw_version_str = qla24xx_fw_version_str, 2343 .intr_handler = qla24xx_intr_handler, 2344 .enable_intrs = qla24xx_enable_intrs, 2345 .disable_intrs = qla24xx_disable_intrs, 2346 .abort_command = qla24xx_abort_command, 2347 .target_reset = qla24xx_abort_target, 2348 .lun_reset = qla24xx_lun_reset, 2349 .fabric_login = qla24xx_login_fabric, 2350 .fabric_logout = qla24xx_fabric_logout, 2351 .calc_req_entries = NULL, 2352 .build_iocbs = NULL, 2353 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2354 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2355 .read_nvram = NULL, 2356 .write_nvram = NULL, 2357 .fw_dump = qla27xx_fwdump, 2358 .beacon_on = qla24xx_beacon_on, 2359 .beacon_off = qla24xx_beacon_off, 2360 .beacon_blink = qla83xx_beacon_blink, 2361 .read_optrom = qla25xx_read_optrom_data, 2362 .write_optrom = qla24xx_write_optrom_data, 2363 .get_flash_version = qla24xx_get_flash_version, 2364 .start_scsi = qla24xx_dif_start_scsi, 2365 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2366 .abort_isp = qla2x00_abort_isp, 2367 .iospace_config = qla83xx_iospace_config, 2368 .initialize_adapter = qla2x00_initialize_adapter, 2369 }; 2370 2371 static inline void 2372 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2373 { 2374 ha->device_type = DT_EXTENDED_IDS; 2375 switch (ha->pdev->device) { 2376 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2377 ha->isp_type |= DT_ISP2100; 2378 ha->device_type &= ~DT_EXTENDED_IDS; 2379 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2380 break; 2381 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2382 ha->isp_type |= DT_ISP2200; 2383 ha->device_type &= ~DT_EXTENDED_IDS; 2384 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2385 break; 2386 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2387 ha->isp_type |= DT_ISP2300; 2388 ha->device_type |= DT_ZIO_SUPPORTED; 2389 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2390 break; 2391 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2392 ha->isp_type |= DT_ISP2312; 2393 ha->device_type |= DT_ZIO_SUPPORTED; 2394 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2395 break; 2396 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2397 ha->isp_type |= DT_ISP2322; 2398 ha->device_type |= DT_ZIO_SUPPORTED; 2399 if (ha->pdev->subsystem_vendor == 0x1028 && 2400 ha->pdev->subsystem_device == 0x0170) 2401 ha->device_type |= DT_OEM_001; 2402 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2403 break; 2404 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2405 ha->isp_type |= DT_ISP6312; 2406 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2407 break; 2408 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2409 ha->isp_type |= DT_ISP6322; 2410 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2411 break; 2412 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2413 ha->isp_type |= DT_ISP2422; 2414 ha->device_type |= DT_ZIO_SUPPORTED; 2415 ha->device_type |= DT_FWI2; 2416 ha->device_type |= DT_IIDMA; 2417 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2418 break; 2419 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2420 ha->isp_type |= DT_ISP2432; 2421 ha->device_type |= DT_ZIO_SUPPORTED; 2422 ha->device_type |= DT_FWI2; 2423 ha->device_type |= DT_IIDMA; 2424 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2425 break; 2426 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2427 ha->isp_type |= DT_ISP8432; 2428 ha->device_type |= DT_ZIO_SUPPORTED; 2429 ha->device_type |= DT_FWI2; 2430 ha->device_type |= DT_IIDMA; 2431 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2432 break; 2433 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2434 ha->isp_type |= DT_ISP5422; 2435 ha->device_type |= DT_FWI2; 2436 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2437 break; 2438 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2439 ha->isp_type |= DT_ISP5432; 2440 ha->device_type |= DT_FWI2; 2441 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2442 break; 2443 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2444 ha->isp_type |= DT_ISP2532; 2445 ha->device_type |= DT_ZIO_SUPPORTED; 2446 ha->device_type |= DT_FWI2; 2447 ha->device_type |= DT_IIDMA; 2448 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2449 break; 2450 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2451 ha->isp_type |= DT_ISP8001; 2452 ha->device_type |= DT_ZIO_SUPPORTED; 2453 ha->device_type |= DT_FWI2; 2454 ha->device_type |= DT_IIDMA; 2455 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2456 break; 2457 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2458 ha->isp_type |= DT_ISP8021; 2459 ha->device_type |= DT_ZIO_SUPPORTED; 2460 ha->device_type |= DT_FWI2; 2461 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2462 /* Initialize 82XX ISP flags */ 2463 qla82xx_init_flags(ha); 2464 break; 2465 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2466 ha->isp_type |= DT_ISP8044; 2467 ha->device_type |= DT_ZIO_SUPPORTED; 2468 ha->device_type |= DT_FWI2; 2469 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2470 /* Initialize 82XX ISP flags */ 2471 qla82xx_init_flags(ha); 2472 break; 2473 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2474 ha->isp_type |= DT_ISP2031; 2475 ha->device_type |= DT_ZIO_SUPPORTED; 2476 ha->device_type |= DT_FWI2; 2477 ha->device_type |= DT_IIDMA; 2478 ha->device_type |= DT_T10_PI; 2479 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2480 break; 2481 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2482 ha->isp_type |= DT_ISP8031; 2483 ha->device_type |= DT_ZIO_SUPPORTED; 2484 ha->device_type |= DT_FWI2; 2485 ha->device_type |= DT_IIDMA; 2486 ha->device_type |= DT_T10_PI; 2487 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2488 break; 2489 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2490 ha->isp_type |= DT_ISPFX00; 2491 break; 2492 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2493 ha->isp_type |= DT_ISP2071; 2494 ha->device_type |= DT_ZIO_SUPPORTED; 2495 ha->device_type |= DT_FWI2; 2496 ha->device_type |= DT_IIDMA; 2497 ha->device_type |= DT_T10_PI; 2498 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2499 break; 2500 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2501 ha->isp_type |= DT_ISP2271; 2502 ha->device_type |= DT_ZIO_SUPPORTED; 2503 ha->device_type |= DT_FWI2; 2504 ha->device_type |= DT_IIDMA; 2505 ha->device_type |= DT_T10_PI; 2506 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2507 break; 2508 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2509 ha->isp_type |= DT_ISP2261; 2510 ha->device_type |= DT_ZIO_SUPPORTED; 2511 ha->device_type |= DT_FWI2; 2512 ha->device_type |= DT_IIDMA; 2513 ha->device_type |= DT_T10_PI; 2514 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2515 break; 2516 } 2517 2518 if (IS_QLA82XX(ha)) 2519 ha->port_no = ha->portnum & 1; 2520 else { 2521 /* Get adapter physical port no from interrupt pin register. */ 2522 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2523 if (IS_QLA27XX(ha)) 2524 ha->port_no--; 2525 else 2526 ha->port_no = !(ha->port_no & 1); 2527 } 2528 2529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2530 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2531 ha->device_type, ha->port_no, ha->fw_srisc_address); 2532 } 2533 2534 static void 2535 qla2xxx_scan_start(struct Scsi_Host *shost) 2536 { 2537 scsi_qla_host_t *vha = shost_priv(shost); 2538 2539 if (vha->hw->flags.running_gold_fw) 2540 return; 2541 2542 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2543 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2544 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2545 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2546 } 2547 2548 static int 2549 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2550 { 2551 scsi_qla_host_t *vha = shost_priv(shost); 2552 2553 if (test_bit(UNLOADING, &vha->dpc_flags)) 2554 return 1; 2555 if (!vha->host) 2556 return 1; 2557 if (time > vha->hw->loop_reset_delay * HZ) 2558 return 1; 2559 2560 return atomic_read(&vha->loop_state) == LOOP_READY; 2561 } 2562 2563 /* 2564 * PCI driver interface 2565 */ 2566 static int 2567 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2568 { 2569 int ret = -ENODEV; 2570 struct Scsi_Host *host; 2571 scsi_qla_host_t *base_vha = NULL; 2572 struct qla_hw_data *ha; 2573 char pci_info[30]; 2574 char fw_str[30], wq_name[30]; 2575 struct scsi_host_template *sht; 2576 int bars, mem_only = 0; 2577 uint16_t req_length = 0, rsp_length = 0; 2578 struct req_que *req = NULL; 2579 struct rsp_que *rsp = NULL; 2580 int i; 2581 2582 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2583 sht = &qla2xxx_driver_template; 2584 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2585 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2586 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2587 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2588 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2589 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2590 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2591 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2592 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2593 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2594 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2595 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2596 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2597 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2598 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2599 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2600 mem_only = 1; 2601 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2602 "Mem only adapter.\n"); 2603 } 2604 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2605 "Bars=%d.\n", bars); 2606 2607 if (mem_only) { 2608 if (pci_enable_device_mem(pdev)) 2609 goto probe_out; 2610 } else { 2611 if (pci_enable_device(pdev)) 2612 goto probe_out; 2613 } 2614 2615 /* This may fail but that's ok */ 2616 pci_enable_pcie_error_reporting(pdev); 2617 2618 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2619 if (!ha) { 2620 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2621 "Unable to allocate memory for ha.\n"); 2622 goto probe_out; 2623 } 2624 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2625 "Memory allocated for ha=%p.\n", ha); 2626 ha->pdev = pdev; 2627 ha->tgt.enable_class_2 = ql2xenableclass2; 2628 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2629 spin_lock_init(&ha->tgt.q_full_lock); 2630 spin_lock_init(&ha->tgt.sess_lock); 2631 spin_lock_init(&ha->tgt.atio_lock); 2632 2633 2634 /* Clear our data area */ 2635 ha->bars = bars; 2636 ha->mem_only = mem_only; 2637 spin_lock_init(&ha->hardware_lock); 2638 spin_lock_init(&ha->vport_slock); 2639 mutex_init(&ha->selflogin_lock); 2640 mutex_init(&ha->optrom_mutex); 2641 2642 /* Set ISP-type information. */ 2643 qla2x00_set_isp_flags(ha); 2644 2645 /* Set EEH reset type to fundamental if required by hba */ 2646 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2647 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2648 pdev->needs_freset = 1; 2649 2650 ha->prev_topology = 0; 2651 ha->init_cb_size = sizeof(init_cb_t); 2652 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2653 ha->optrom_size = OPTROM_SIZE_2300; 2654 2655 /* Assign ISP specific operations. */ 2656 if (IS_QLA2100(ha)) { 2657 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2658 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2659 req_length = REQUEST_ENTRY_CNT_2100; 2660 rsp_length = RESPONSE_ENTRY_CNT_2100; 2661 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2662 ha->gid_list_info_size = 4; 2663 ha->flash_conf_off = ~0; 2664 ha->flash_data_off = ~0; 2665 ha->nvram_conf_off = ~0; 2666 ha->nvram_data_off = ~0; 2667 ha->isp_ops = &qla2100_isp_ops; 2668 } else if (IS_QLA2200(ha)) { 2669 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2670 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2671 req_length = REQUEST_ENTRY_CNT_2200; 2672 rsp_length = RESPONSE_ENTRY_CNT_2100; 2673 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2674 ha->gid_list_info_size = 4; 2675 ha->flash_conf_off = ~0; 2676 ha->flash_data_off = ~0; 2677 ha->nvram_conf_off = ~0; 2678 ha->nvram_data_off = ~0; 2679 ha->isp_ops = &qla2100_isp_ops; 2680 } else if (IS_QLA23XX(ha)) { 2681 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2682 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2683 req_length = REQUEST_ENTRY_CNT_2200; 2684 rsp_length = RESPONSE_ENTRY_CNT_2300; 2685 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2686 ha->gid_list_info_size = 6; 2687 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2688 ha->optrom_size = OPTROM_SIZE_2322; 2689 ha->flash_conf_off = ~0; 2690 ha->flash_data_off = ~0; 2691 ha->nvram_conf_off = ~0; 2692 ha->nvram_data_off = ~0; 2693 ha->isp_ops = &qla2300_isp_ops; 2694 } else if (IS_QLA24XX_TYPE(ha)) { 2695 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2696 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2697 req_length = REQUEST_ENTRY_CNT_24XX; 2698 rsp_length = RESPONSE_ENTRY_CNT_2300; 2699 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2700 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2701 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2702 ha->gid_list_info_size = 8; 2703 ha->optrom_size = OPTROM_SIZE_24XX; 2704 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2705 ha->isp_ops = &qla24xx_isp_ops; 2706 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2707 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2708 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2709 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2710 } else if (IS_QLA25XX(ha)) { 2711 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2712 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2713 req_length = REQUEST_ENTRY_CNT_24XX; 2714 rsp_length = RESPONSE_ENTRY_CNT_2300; 2715 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2716 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2717 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2718 ha->gid_list_info_size = 8; 2719 ha->optrom_size = OPTROM_SIZE_25XX; 2720 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2721 ha->isp_ops = &qla25xx_isp_ops; 2722 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2723 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2724 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2725 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2726 } else if (IS_QLA81XX(ha)) { 2727 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2728 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2729 req_length = REQUEST_ENTRY_CNT_24XX; 2730 rsp_length = RESPONSE_ENTRY_CNT_2300; 2731 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2732 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2733 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2734 ha->gid_list_info_size = 8; 2735 ha->optrom_size = OPTROM_SIZE_81XX; 2736 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2737 ha->isp_ops = &qla81xx_isp_ops; 2738 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2739 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2740 ha->nvram_conf_off = ~0; 2741 ha->nvram_data_off = ~0; 2742 } else if (IS_QLA82XX(ha)) { 2743 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2744 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2745 req_length = REQUEST_ENTRY_CNT_82XX; 2746 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2747 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2748 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2749 ha->gid_list_info_size = 8; 2750 ha->optrom_size = OPTROM_SIZE_82XX; 2751 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2752 ha->isp_ops = &qla82xx_isp_ops; 2753 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2754 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2755 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2756 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2757 } else if (IS_QLA8044(ha)) { 2758 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2759 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2760 req_length = REQUEST_ENTRY_CNT_82XX; 2761 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2762 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2763 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2764 ha->gid_list_info_size = 8; 2765 ha->optrom_size = OPTROM_SIZE_83XX; 2766 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2767 ha->isp_ops = &qla8044_isp_ops; 2768 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2769 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2770 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2771 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2772 } else if (IS_QLA83XX(ha)) { 2773 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2774 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2775 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2776 req_length = REQUEST_ENTRY_CNT_83XX; 2777 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2778 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2779 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2780 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2781 ha->gid_list_info_size = 8; 2782 ha->optrom_size = OPTROM_SIZE_83XX; 2783 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2784 ha->isp_ops = &qla83xx_isp_ops; 2785 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2786 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2787 ha->nvram_conf_off = ~0; 2788 ha->nvram_data_off = ~0; 2789 } else if (IS_QLAFX00(ha)) { 2790 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2791 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2792 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2793 req_length = REQUEST_ENTRY_CNT_FX00; 2794 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2795 ha->isp_ops = &qlafx00_isp_ops; 2796 ha->port_down_retry_count = 30; /* default value */ 2797 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2798 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2799 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2800 ha->mr.fw_hbt_en = 1; 2801 ha->mr.host_info_resend = false; 2802 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2803 } else if (IS_QLA27XX(ha)) { 2804 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2805 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2806 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2807 req_length = REQUEST_ENTRY_CNT_83XX; 2808 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2809 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2810 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2811 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2812 ha->gid_list_info_size = 8; 2813 ha->optrom_size = OPTROM_SIZE_83XX; 2814 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2815 ha->isp_ops = &qla27xx_isp_ops; 2816 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2817 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2818 ha->nvram_conf_off = ~0; 2819 ha->nvram_data_off = ~0; 2820 } 2821 2822 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2823 "mbx_count=%d, req_length=%d, " 2824 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2825 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2826 "max_fibre_devices=%d.\n", 2827 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2828 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2829 ha->nvram_npiv_size, ha->max_fibre_devices); 2830 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2831 "isp_ops=%p, flash_conf_off=%d, " 2832 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2833 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2834 ha->nvram_conf_off, ha->nvram_data_off); 2835 2836 /* Configure PCI I/O space */ 2837 ret = ha->isp_ops->iospace_config(ha); 2838 if (ret) 2839 goto iospace_config_failed; 2840 2841 ql_log_pci(ql_log_info, pdev, 0x001d, 2842 "Found an ISP%04X irq %d iobase 0x%p.\n", 2843 pdev->device, pdev->irq, ha->iobase); 2844 mutex_init(&ha->vport_lock); 2845 mutex_init(&ha->mq_lock); 2846 init_completion(&ha->mbx_cmd_comp); 2847 complete(&ha->mbx_cmd_comp); 2848 init_completion(&ha->mbx_intr_comp); 2849 init_completion(&ha->dcbx_comp); 2850 init_completion(&ha->lb_portup_comp); 2851 2852 set_bit(0, (unsigned long *) ha->vp_idx_map); 2853 2854 qla2x00_config_dma_addressing(ha); 2855 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2856 "64 Bit addressing is %s.\n", 2857 ha->flags.enable_64bit_addressing ? "enable" : 2858 "disable"); 2859 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2860 if (ret) { 2861 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2862 "Failed to allocate memory for adapter, aborting.\n"); 2863 2864 goto probe_hw_failed; 2865 } 2866 2867 req->max_q_depth = MAX_Q_DEPTH; 2868 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2869 req->max_q_depth = ql2xmaxqdepth; 2870 2871 2872 base_vha = qla2x00_create_host(sht, ha); 2873 if (!base_vha) { 2874 ret = -ENOMEM; 2875 qla2x00_mem_free(ha); 2876 qla2x00_free_req_que(ha, req); 2877 qla2x00_free_rsp_que(ha, rsp); 2878 goto probe_hw_failed; 2879 } 2880 2881 pci_set_drvdata(pdev, base_vha); 2882 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2883 2884 host = base_vha->host; 2885 base_vha->req = req; 2886 if (IS_QLA2XXX_MIDTYPE(ha)) 2887 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2888 else 2889 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2890 base_vha->vp_idx; 2891 2892 /* Setup fcport template structure. */ 2893 ha->mr.fcport.vha = base_vha; 2894 ha->mr.fcport.port_type = FCT_UNKNOWN; 2895 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2896 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2897 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2898 ha->mr.fcport.scan_state = 1; 2899 2900 /* Set the SG table size based on ISP type */ 2901 if (!IS_FWI2_CAPABLE(ha)) { 2902 if (IS_QLA2100(ha)) 2903 host->sg_tablesize = 32; 2904 } else { 2905 if (!IS_QLA82XX(ha)) 2906 host->sg_tablesize = QLA_SG_ALL; 2907 } 2908 host->max_id = ha->max_fibre_devices; 2909 host->cmd_per_lun = 3; 2910 host->unique_id = host->host_no; 2911 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2912 host->max_cmd_len = 32; 2913 else 2914 host->max_cmd_len = MAX_CMDSZ; 2915 host->max_channel = MAX_BUSES - 1; 2916 /* Older HBAs support only 16-bit LUNs */ 2917 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2918 ql2xmaxlun > 0xffff) 2919 host->max_lun = 0xffff; 2920 else 2921 host->max_lun = ql2xmaxlun; 2922 host->transportt = qla2xxx_transport_template; 2923 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2924 2925 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2926 "max_id=%d this_id=%d " 2927 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2928 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2929 host->this_id, host->cmd_per_lun, host->unique_id, 2930 host->max_cmd_len, host->max_channel, host->max_lun, 2931 host->transportt, sht->vendor_id); 2932 2933 /* Set up the irqs */ 2934 ret = qla2x00_request_irqs(ha, rsp); 2935 if (ret) 2936 goto probe_init_failed; 2937 2938 /* Alloc arrays of request and response ring ptrs */ 2939 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2940 ql_log(ql_log_fatal, base_vha, 0x003d, 2941 "Failed to allocate memory for queue pointers..." 2942 "aborting.\n"); 2943 goto probe_init_failed; 2944 } 2945 2946 if (ha->mqenable && shost_use_blk_mq(host)) { 2947 /* number of hardware queues supported by blk/scsi-mq*/ 2948 host->nr_hw_queues = ha->max_qpairs; 2949 2950 ql_dbg(ql_dbg_init, base_vha, 0x0192, 2951 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 2952 } else 2953 ql_dbg(ql_dbg_init, base_vha, 0x0193, 2954 "blk/scsi-mq disabled.\n"); 2955 2956 qlt_probe_one_stage1(base_vha, ha); 2957 2958 pci_save_state(pdev); 2959 2960 /* Assign back pointers */ 2961 rsp->req = req; 2962 req->rsp = rsp; 2963 2964 if (IS_QLAFX00(ha)) { 2965 ha->rsp_q_map[0] = rsp; 2966 ha->req_q_map[0] = req; 2967 set_bit(0, ha->req_qid_map); 2968 set_bit(0, ha->rsp_qid_map); 2969 } 2970 2971 /* FWI2-capable only. */ 2972 req->req_q_in = &ha->iobase->isp24.req_q_in; 2973 req->req_q_out = &ha->iobase->isp24.req_q_out; 2974 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2975 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2976 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2977 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2978 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2979 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2980 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2981 } 2982 2983 if (IS_QLAFX00(ha)) { 2984 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2985 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2986 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2987 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2988 } 2989 2990 if (IS_P3P_TYPE(ha)) { 2991 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2992 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2993 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2994 } 2995 2996 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2997 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2998 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2999 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3000 "req->req_q_in=%p req->req_q_out=%p " 3001 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3002 req->req_q_in, req->req_q_out, 3003 rsp->rsp_q_in, rsp->rsp_q_out); 3004 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3005 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3006 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3007 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3008 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3009 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3010 3011 if (ha->isp_ops->initialize_adapter(base_vha)) { 3012 ql_log(ql_log_fatal, base_vha, 0x00d6, 3013 "Failed to initialize adapter - Adapter flags %x.\n", 3014 base_vha->device_flags); 3015 3016 if (IS_QLA82XX(ha)) { 3017 qla82xx_idc_lock(ha); 3018 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3019 QLA8XXX_DEV_FAILED); 3020 qla82xx_idc_unlock(ha); 3021 ql_log(ql_log_fatal, base_vha, 0x00d7, 3022 "HW State: FAILED.\n"); 3023 } else if (IS_QLA8044(ha)) { 3024 qla8044_idc_lock(ha); 3025 qla8044_wr_direct(base_vha, 3026 QLA8044_CRB_DEV_STATE_INDEX, 3027 QLA8XXX_DEV_FAILED); 3028 qla8044_idc_unlock(ha); 3029 ql_log(ql_log_fatal, base_vha, 0x0150, 3030 "HW State: FAILED.\n"); 3031 } 3032 3033 ret = -ENODEV; 3034 goto probe_failed; 3035 } 3036 3037 if (IS_QLAFX00(ha)) 3038 host->can_queue = QLAFX00_MAX_CANQUEUE; 3039 else 3040 host->can_queue = req->num_outstanding_cmds - 10; 3041 3042 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3043 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3044 host->can_queue, base_vha->req, 3045 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3046 3047 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) { 3048 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 3049 /* Create start of day qpairs for Block MQ */ 3050 if (shost_use_blk_mq(host)) { 3051 for (i = 0; i < ha->max_qpairs; i++) 3052 qla2xxx_create_qpair(base_vha, 5, 0); 3053 } 3054 } 3055 3056 if (ha->flags.running_gold_fw) 3057 goto skip_dpc; 3058 3059 /* 3060 * Startup the kernel thread for this host adapter 3061 */ 3062 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3063 "%s_dpc", base_vha->host_str); 3064 if (IS_ERR(ha->dpc_thread)) { 3065 ql_log(ql_log_fatal, base_vha, 0x00ed, 3066 "Failed to start DPC thread.\n"); 3067 ret = PTR_ERR(ha->dpc_thread); 3068 goto probe_failed; 3069 } 3070 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3071 "DPC thread started successfully.\n"); 3072 3073 /* 3074 * If we're not coming up in initiator mode, we might sit for 3075 * a while without waking up the dpc thread, which leads to a 3076 * stuck process warning. So just kick the dpc once here and 3077 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3078 */ 3079 qla2xxx_wake_dpc(base_vha); 3080 3081 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3082 3083 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3084 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3085 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3086 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3087 3088 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3089 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3090 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3091 INIT_WORK(&ha->idc_state_handler, 3092 qla83xx_idc_state_handler_work); 3093 INIT_WORK(&ha->nic_core_unrecoverable, 3094 qla83xx_nic_core_unrecoverable_work); 3095 } 3096 3097 skip_dpc: 3098 list_add_tail(&base_vha->list, &ha->vp_list); 3099 base_vha->host->irq = ha->pdev->irq; 3100 3101 /* Initialized the timer */ 3102 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 3103 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3104 "Started qla2x00_timer with " 3105 "interval=%d.\n", WATCH_INTERVAL); 3106 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3107 "Detected hba at address=%p.\n", 3108 ha); 3109 3110 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3111 if (ha->fw_attributes & BIT_4) { 3112 int prot = 0, guard; 3113 base_vha->flags.difdix_supported = 1; 3114 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3115 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3116 if (ql2xenabledif == 1) 3117 prot = SHOST_DIX_TYPE0_PROTECTION; 3118 scsi_host_set_prot(host, 3119 prot | SHOST_DIF_TYPE1_PROTECTION 3120 | SHOST_DIF_TYPE2_PROTECTION 3121 | SHOST_DIF_TYPE3_PROTECTION 3122 | SHOST_DIX_TYPE1_PROTECTION 3123 | SHOST_DIX_TYPE2_PROTECTION 3124 | SHOST_DIX_TYPE3_PROTECTION); 3125 3126 guard = SHOST_DIX_GUARD_CRC; 3127 3128 if (IS_PI_IPGUARD_CAPABLE(ha) && 3129 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3130 guard |= SHOST_DIX_GUARD_IP; 3131 3132 scsi_host_set_guard(host, guard); 3133 } else 3134 base_vha->flags.difdix_supported = 0; 3135 } 3136 3137 ha->isp_ops->enable_intrs(ha); 3138 3139 if (IS_QLAFX00(ha)) { 3140 ret = qlafx00_fx_disc(base_vha, 3141 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3142 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3143 QLA_SG_ALL : 128; 3144 } 3145 3146 ret = scsi_add_host(host, &pdev->dev); 3147 if (ret) 3148 goto probe_failed; 3149 3150 base_vha->flags.init_done = 1; 3151 base_vha->flags.online = 1; 3152 ha->prev_minidump_failed = 0; 3153 3154 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3155 "Init done and hba is online.\n"); 3156 3157 if (qla_ini_mode_enabled(base_vha) || 3158 qla_dual_mode_enabled(base_vha)) 3159 scsi_scan_host(host); 3160 else 3161 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3162 "skipping scsi_scan_host() for non-initiator port\n"); 3163 3164 qla2x00_alloc_sysfs_attr(base_vha); 3165 3166 if (IS_QLAFX00(ha)) { 3167 ret = qlafx00_fx_disc(base_vha, 3168 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3169 3170 /* Register system information */ 3171 ret = qlafx00_fx_disc(base_vha, 3172 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3173 } 3174 3175 qla2x00_init_host_attr(base_vha); 3176 3177 qla2x00_dfs_setup(base_vha); 3178 3179 ql_log(ql_log_info, base_vha, 0x00fb, 3180 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3181 ql_log(ql_log_info, base_vha, 0x00fc, 3182 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3183 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3184 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3185 base_vha->host_no, 3186 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3187 3188 qlt_add_target(ha, base_vha); 3189 3190 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3191 3192 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3193 return -ENODEV; 3194 3195 return 0; 3196 3197 probe_init_failed: 3198 qla2x00_free_req_que(ha, req); 3199 ha->req_q_map[0] = NULL; 3200 clear_bit(0, ha->req_qid_map); 3201 qla2x00_free_rsp_que(ha, rsp); 3202 ha->rsp_q_map[0] = NULL; 3203 clear_bit(0, ha->rsp_qid_map); 3204 ha->max_req_queues = ha->max_rsp_queues = 0; 3205 3206 probe_failed: 3207 if (base_vha->timer_active) 3208 qla2x00_stop_timer(base_vha); 3209 base_vha->flags.online = 0; 3210 if (ha->dpc_thread) { 3211 struct task_struct *t = ha->dpc_thread; 3212 3213 ha->dpc_thread = NULL; 3214 kthread_stop(t); 3215 } 3216 3217 qla2x00_free_device(base_vha); 3218 3219 scsi_host_put(base_vha->host); 3220 3221 probe_hw_failed: 3222 qla2x00_clear_drv_active(ha); 3223 3224 iospace_config_failed: 3225 if (IS_P3P_TYPE(ha)) { 3226 if (!ha->nx_pcibase) 3227 iounmap((device_reg_t *)ha->nx_pcibase); 3228 if (!ql2xdbwr) 3229 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3230 } else { 3231 if (ha->iobase) 3232 iounmap(ha->iobase); 3233 if (ha->cregbase) 3234 iounmap(ha->cregbase); 3235 } 3236 pci_release_selected_regions(ha->pdev, ha->bars); 3237 kfree(ha); 3238 ha = NULL; 3239 3240 probe_out: 3241 pci_disable_device(pdev); 3242 return ret; 3243 } 3244 3245 static void 3246 qla2x00_shutdown(struct pci_dev *pdev) 3247 { 3248 scsi_qla_host_t *vha; 3249 struct qla_hw_data *ha; 3250 3251 if (!atomic_read(&pdev->enable_cnt)) 3252 return; 3253 3254 vha = pci_get_drvdata(pdev); 3255 ha = vha->hw; 3256 3257 /* Notify ISPFX00 firmware */ 3258 if (IS_QLAFX00(ha)) 3259 qlafx00_driver_shutdown(vha, 20); 3260 3261 /* Turn-off FCE trace */ 3262 if (ha->flags.fce_enabled) { 3263 qla2x00_disable_fce_trace(vha, NULL, NULL); 3264 ha->flags.fce_enabled = 0; 3265 } 3266 3267 /* Turn-off EFT trace */ 3268 if (ha->eft) 3269 qla2x00_disable_eft_trace(vha); 3270 3271 /* Stop currently executing firmware. */ 3272 qla2x00_try_to_stop_firmware(vha); 3273 3274 /* Turn adapter off line */ 3275 vha->flags.online = 0; 3276 3277 /* turn-off interrupts on the card */ 3278 if (ha->interrupts_on) { 3279 vha->flags.init_done = 0; 3280 ha->isp_ops->disable_intrs(ha); 3281 } 3282 3283 qla2x00_free_irqs(vha); 3284 3285 qla2x00_free_fw_dump(ha); 3286 3287 pci_disable_pcie_error_reporting(pdev); 3288 pci_disable_device(pdev); 3289 } 3290 3291 /* Deletes all the virtual ports for a given ha */ 3292 static void 3293 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3294 { 3295 scsi_qla_host_t *vha; 3296 unsigned long flags; 3297 3298 mutex_lock(&ha->vport_lock); 3299 while (ha->cur_vport_count) { 3300 spin_lock_irqsave(&ha->vport_slock, flags); 3301 3302 BUG_ON(base_vha->list.next == &ha->vp_list); 3303 /* This assumes first entry in ha->vp_list is always base vha */ 3304 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3305 scsi_host_get(vha->host); 3306 3307 spin_unlock_irqrestore(&ha->vport_slock, flags); 3308 mutex_unlock(&ha->vport_lock); 3309 3310 fc_vport_terminate(vha->fc_vport); 3311 scsi_host_put(vha->host); 3312 3313 mutex_lock(&ha->vport_lock); 3314 } 3315 mutex_unlock(&ha->vport_lock); 3316 } 3317 3318 /* Stops all deferred work threads */ 3319 static void 3320 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3321 { 3322 /* Cancel all work and destroy DPC workqueues */ 3323 if (ha->dpc_lp_wq) { 3324 cancel_work_sync(&ha->idc_aen); 3325 destroy_workqueue(ha->dpc_lp_wq); 3326 ha->dpc_lp_wq = NULL; 3327 } 3328 3329 if (ha->dpc_hp_wq) { 3330 cancel_work_sync(&ha->nic_core_reset); 3331 cancel_work_sync(&ha->idc_state_handler); 3332 cancel_work_sync(&ha->nic_core_unrecoverable); 3333 destroy_workqueue(ha->dpc_hp_wq); 3334 ha->dpc_hp_wq = NULL; 3335 } 3336 3337 /* Kill the kernel thread for this host */ 3338 if (ha->dpc_thread) { 3339 struct task_struct *t = ha->dpc_thread; 3340 3341 /* 3342 * qla2xxx_wake_dpc checks for ->dpc_thread 3343 * so we need to zero it out. 3344 */ 3345 ha->dpc_thread = NULL; 3346 kthread_stop(t); 3347 } 3348 } 3349 3350 static void 3351 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3352 { 3353 if (IS_QLA82XX(ha)) { 3354 3355 iounmap((device_reg_t *)ha->nx_pcibase); 3356 if (!ql2xdbwr) 3357 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3358 } else { 3359 if (ha->iobase) 3360 iounmap(ha->iobase); 3361 3362 if (ha->cregbase) 3363 iounmap(ha->cregbase); 3364 3365 if (ha->mqiobase) 3366 iounmap(ha->mqiobase); 3367 3368 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3369 iounmap(ha->msixbase); 3370 } 3371 } 3372 3373 static void 3374 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3375 { 3376 if (IS_QLA8044(ha)) { 3377 qla8044_idc_lock(ha); 3378 qla8044_clear_drv_active(ha); 3379 qla8044_idc_unlock(ha); 3380 } else if (IS_QLA82XX(ha)) { 3381 qla82xx_idc_lock(ha); 3382 qla82xx_clear_drv_active(ha); 3383 qla82xx_idc_unlock(ha); 3384 } 3385 } 3386 3387 static void 3388 qla2x00_remove_one(struct pci_dev *pdev) 3389 { 3390 scsi_qla_host_t *base_vha; 3391 struct qla_hw_data *ha; 3392 3393 base_vha = pci_get_drvdata(pdev); 3394 ha = base_vha->hw; 3395 3396 /* Indicate device removal to prevent future board_disable and wait 3397 * until any pending board_disable has completed. */ 3398 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3399 cancel_work_sync(&ha->board_disable); 3400 3401 /* 3402 * If the PCI device is disabled then there was a PCI-disconnect and 3403 * qla2x00_disable_board_on_pci_error has taken care of most of the 3404 * resources. 3405 */ 3406 if (!atomic_read(&pdev->enable_cnt)) { 3407 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3408 base_vha->gnl.l, base_vha->gnl.ldma); 3409 3410 scsi_host_put(base_vha->host); 3411 kfree(ha); 3412 pci_set_drvdata(pdev, NULL); 3413 return; 3414 } 3415 qla2x00_wait_for_hba_ready(base_vha); 3416 3417 /* 3418 * if UNLOAD flag is already set, then continue unload, 3419 * where it was set first. 3420 */ 3421 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3422 return; 3423 3424 set_bit(UNLOADING, &base_vha->dpc_flags); 3425 dma_free_coherent(&ha->pdev->dev, 3426 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3427 3428 if (IS_QLAFX00(ha)) 3429 qlafx00_driver_shutdown(base_vha, 20); 3430 3431 qla2x00_delete_all_vps(ha, base_vha); 3432 3433 if (IS_QLA8031(ha)) { 3434 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3435 "Clearing fcoe driver presence.\n"); 3436 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3437 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3438 "Error while clearing DRV-Presence.\n"); 3439 } 3440 3441 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3442 3443 qla2x00_dfs_remove(base_vha); 3444 3445 qla84xx_put_chip(base_vha); 3446 3447 /* Laser should be disabled only for ISP2031 */ 3448 if (IS_QLA2031(ha)) 3449 qla83xx_disable_laser(base_vha); 3450 3451 /* Disable timer */ 3452 if (base_vha->timer_active) 3453 qla2x00_stop_timer(base_vha); 3454 3455 base_vha->flags.online = 0; 3456 3457 /* free DMA memory */ 3458 if (ha->exlogin_buf) 3459 qla2x00_free_exlogin_buffer(ha); 3460 3461 /* free DMA memory */ 3462 if (ha->exchoffld_buf) 3463 qla2x00_free_exchoffld_buffer(ha); 3464 3465 qla2x00_destroy_deferred_work(ha); 3466 3467 qlt_remove_target(ha, base_vha); 3468 3469 qla2x00_free_sysfs_attr(base_vha, true); 3470 3471 fc_remove_host(base_vha->host); 3472 3473 scsi_remove_host(base_vha->host); 3474 3475 qla2x00_free_device(base_vha); 3476 3477 qla2x00_clear_drv_active(ha); 3478 3479 scsi_host_put(base_vha->host); 3480 3481 qla2x00_unmap_iobases(ha); 3482 3483 pci_release_selected_regions(ha->pdev, ha->bars); 3484 kfree(ha); 3485 ha = NULL; 3486 3487 pci_disable_pcie_error_reporting(pdev); 3488 3489 pci_disable_device(pdev); 3490 } 3491 3492 static void 3493 qla2x00_free_device(scsi_qla_host_t *vha) 3494 { 3495 struct qla_hw_data *ha = vha->hw; 3496 3497 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3498 3499 /* Disable timer */ 3500 if (vha->timer_active) 3501 qla2x00_stop_timer(vha); 3502 3503 qla25xx_delete_queues(vha); 3504 3505 if (ha->flags.fce_enabled) 3506 qla2x00_disable_fce_trace(vha, NULL, NULL); 3507 3508 if (ha->eft) 3509 qla2x00_disable_eft_trace(vha); 3510 3511 /* Stop currently executing firmware. */ 3512 qla2x00_try_to_stop_firmware(vha); 3513 3514 vha->flags.online = 0; 3515 3516 /* turn-off interrupts on the card */ 3517 if (ha->interrupts_on) { 3518 vha->flags.init_done = 0; 3519 ha->isp_ops->disable_intrs(ha); 3520 } 3521 3522 qla2x00_free_fcports(vha); 3523 3524 qla2x00_free_irqs(vha); 3525 3526 /* Flush the work queue and remove it */ 3527 if (ha->wq) { 3528 flush_workqueue(ha->wq); 3529 destroy_workqueue(ha->wq); 3530 ha->wq = NULL; 3531 } 3532 3533 3534 qla2x00_mem_free(ha); 3535 3536 qla82xx_md_free(vha); 3537 3538 qla2x00_free_queues(ha); 3539 } 3540 3541 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3542 { 3543 fc_port_t *fcport, *tfcport; 3544 3545 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3546 list_del(&fcport->list); 3547 qla2x00_clear_loop_id(fcport); 3548 kfree(fcport); 3549 fcport = NULL; 3550 } 3551 } 3552 3553 static inline void 3554 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3555 int defer) 3556 { 3557 struct fc_rport *rport; 3558 scsi_qla_host_t *base_vha; 3559 unsigned long flags; 3560 3561 if (!fcport->rport) 3562 return; 3563 3564 rport = fcport->rport; 3565 if (defer) { 3566 base_vha = pci_get_drvdata(vha->hw->pdev); 3567 spin_lock_irqsave(vha->host->host_lock, flags); 3568 fcport->drport = rport; 3569 spin_unlock_irqrestore(vha->host->host_lock, flags); 3570 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3571 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3572 qla2xxx_wake_dpc(base_vha); 3573 } else { 3574 int now; 3575 if (rport) { 3576 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 3577 "%s %8phN. rport %p roles %x \n", 3578 __func__, fcport->port_name, rport, 3579 rport->roles); 3580 fc_remote_port_delete(rport); 3581 } 3582 qlt_do_generation_tick(vha, &now); 3583 } 3584 } 3585 3586 /* 3587 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3588 * 3589 * Input: ha = adapter block pointer. fcport = port structure pointer. 3590 * 3591 * Return: None. 3592 * 3593 * Context: 3594 */ 3595 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3596 int do_login, int defer) 3597 { 3598 if (IS_QLAFX00(vha->hw)) { 3599 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3600 qla2x00_schedule_rport_del(vha, fcport, defer); 3601 return; 3602 } 3603 3604 if (atomic_read(&fcport->state) == FCS_ONLINE && 3605 vha->vp_idx == fcport->vha->vp_idx) { 3606 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3607 qla2x00_schedule_rport_del(vha, fcport, defer); 3608 } 3609 /* 3610 * We may need to retry the login, so don't change the state of the 3611 * port but do the retries. 3612 */ 3613 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3614 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3615 3616 if (!do_login) 3617 return; 3618 3619 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3620 3621 if (fcport->login_retry == 0) { 3622 fcport->login_retry = vha->hw->login_retry_count; 3623 3624 ql_dbg(ql_dbg_disc, vha, 0x2067, 3625 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3626 fcport->port_name, fcport->loop_id, fcport->login_retry); 3627 } 3628 } 3629 3630 /* 3631 * qla2x00_mark_all_devices_lost 3632 * Updates fcport state when device goes offline. 3633 * 3634 * Input: 3635 * ha = adapter block pointer. 3636 * fcport = port structure pointer. 3637 * 3638 * Return: 3639 * None. 3640 * 3641 * Context: 3642 */ 3643 void 3644 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3645 { 3646 fc_port_t *fcport; 3647 3648 ql_dbg(ql_dbg_disc, vha, 0xffff, 3649 "Mark all dev lost\n"); 3650 3651 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3652 fcport->scan_state = 0; 3653 qlt_schedule_sess_for_deletion_lock(fcport); 3654 3655 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3656 continue; 3657 3658 /* 3659 * No point in marking the device as lost, if the device is 3660 * already DEAD. 3661 */ 3662 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3663 continue; 3664 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3665 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3666 if (defer) 3667 qla2x00_schedule_rport_del(vha, fcport, defer); 3668 else if (vha->vp_idx == fcport->vha->vp_idx) 3669 qla2x00_schedule_rport_del(vha, fcport, defer); 3670 } 3671 } 3672 } 3673 3674 /* 3675 * qla2x00_mem_alloc 3676 * Allocates adapter memory. 3677 * 3678 * Returns: 3679 * 0 = success. 3680 * !0 = failure. 3681 */ 3682 static int 3683 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3684 struct req_que **req, struct rsp_que **rsp) 3685 { 3686 char name[16]; 3687 3688 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3689 &ha->init_cb_dma, GFP_KERNEL); 3690 if (!ha->init_cb) 3691 goto fail; 3692 3693 if (qlt_mem_alloc(ha) < 0) 3694 goto fail_free_init_cb; 3695 3696 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3697 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3698 if (!ha->gid_list) 3699 goto fail_free_tgt_mem; 3700 3701 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3702 if (!ha->srb_mempool) 3703 goto fail_free_gid_list; 3704 3705 if (IS_P3P_TYPE(ha)) { 3706 /* Allocate cache for CT6 Ctx. */ 3707 if (!ctx_cachep) { 3708 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3709 sizeof(struct ct6_dsd), 0, 3710 SLAB_HWCACHE_ALIGN, NULL); 3711 if (!ctx_cachep) 3712 goto fail_free_srb_mempool; 3713 } 3714 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3715 ctx_cachep); 3716 if (!ha->ctx_mempool) 3717 goto fail_free_srb_mempool; 3718 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3719 "ctx_cachep=%p ctx_mempool=%p.\n", 3720 ctx_cachep, ha->ctx_mempool); 3721 } 3722 3723 /* Get memory for cached NVRAM */ 3724 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3725 if (!ha->nvram) 3726 goto fail_free_ctx_mempool; 3727 3728 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3729 ha->pdev->device); 3730 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3731 DMA_POOL_SIZE, 8, 0); 3732 if (!ha->s_dma_pool) 3733 goto fail_free_nvram; 3734 3735 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3736 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3737 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3738 3739 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3740 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3741 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3742 if (!ha->dl_dma_pool) { 3743 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3744 "Failed to allocate memory for dl_dma_pool.\n"); 3745 goto fail_s_dma_pool; 3746 } 3747 3748 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3749 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3750 if (!ha->fcp_cmnd_dma_pool) { 3751 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3752 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3753 goto fail_dl_dma_pool; 3754 } 3755 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3756 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3757 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3758 } 3759 3760 /* Allocate memory for SNS commands */ 3761 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3762 /* Get consistent memory allocated for SNS commands */ 3763 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3764 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3765 if (!ha->sns_cmd) 3766 goto fail_dma_pool; 3767 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3768 "sns_cmd: %p.\n", ha->sns_cmd); 3769 } else { 3770 /* Get consistent memory allocated for MS IOCB */ 3771 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3772 &ha->ms_iocb_dma); 3773 if (!ha->ms_iocb) 3774 goto fail_dma_pool; 3775 /* Get consistent memory allocated for CT SNS commands */ 3776 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3777 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3778 if (!ha->ct_sns) 3779 goto fail_free_ms_iocb; 3780 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3781 "ms_iocb=%p ct_sns=%p.\n", 3782 ha->ms_iocb, ha->ct_sns); 3783 } 3784 3785 /* Allocate memory for request ring */ 3786 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3787 if (!*req) { 3788 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3789 "Failed to allocate memory for req.\n"); 3790 goto fail_req; 3791 } 3792 (*req)->length = req_len; 3793 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3794 ((*req)->length + 1) * sizeof(request_t), 3795 &(*req)->dma, GFP_KERNEL); 3796 if (!(*req)->ring) { 3797 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3798 "Failed to allocate memory for req_ring.\n"); 3799 goto fail_req_ring; 3800 } 3801 /* Allocate memory for response ring */ 3802 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3803 if (!*rsp) { 3804 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3805 "Failed to allocate memory for rsp.\n"); 3806 goto fail_rsp; 3807 } 3808 (*rsp)->hw = ha; 3809 (*rsp)->length = rsp_len; 3810 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3811 ((*rsp)->length + 1) * sizeof(response_t), 3812 &(*rsp)->dma, GFP_KERNEL); 3813 if (!(*rsp)->ring) { 3814 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3815 "Failed to allocate memory for rsp_ring.\n"); 3816 goto fail_rsp_ring; 3817 } 3818 (*req)->rsp = *rsp; 3819 (*rsp)->req = *req; 3820 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3821 "req=%p req->length=%d req->ring=%p rsp=%p " 3822 "rsp->length=%d rsp->ring=%p.\n", 3823 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3824 (*rsp)->ring); 3825 /* Allocate memory for NVRAM data for vports */ 3826 if (ha->nvram_npiv_size) { 3827 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3828 ha->nvram_npiv_size, GFP_KERNEL); 3829 if (!ha->npiv_info) { 3830 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3831 "Failed to allocate memory for npiv_info.\n"); 3832 goto fail_npiv_info; 3833 } 3834 } else 3835 ha->npiv_info = NULL; 3836 3837 /* Get consistent memory allocated for EX-INIT-CB. */ 3838 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3839 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3840 &ha->ex_init_cb_dma); 3841 if (!ha->ex_init_cb) 3842 goto fail_ex_init_cb; 3843 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3844 "ex_init_cb=%p.\n", ha->ex_init_cb); 3845 } 3846 3847 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3848 3849 /* Get consistent memory allocated for Async Port-Database. */ 3850 if (!IS_FWI2_CAPABLE(ha)) { 3851 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3852 &ha->async_pd_dma); 3853 if (!ha->async_pd) 3854 goto fail_async_pd; 3855 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3856 "async_pd=%p.\n", ha->async_pd); 3857 } 3858 3859 INIT_LIST_HEAD(&ha->vp_list); 3860 3861 /* Allocate memory for our loop_id bitmap */ 3862 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3863 GFP_KERNEL); 3864 if (!ha->loop_id_map) 3865 goto fail_loop_id_map; 3866 else { 3867 qla2x00_set_reserved_loop_ids(ha); 3868 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3869 "loop_id_map=%p.\n", ha->loop_id_map); 3870 } 3871 3872 return 0; 3873 3874 fail_loop_id_map: 3875 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3876 fail_async_pd: 3877 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3878 fail_ex_init_cb: 3879 kfree(ha->npiv_info); 3880 fail_npiv_info: 3881 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3882 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3883 (*rsp)->ring = NULL; 3884 (*rsp)->dma = 0; 3885 fail_rsp_ring: 3886 kfree(*rsp); 3887 fail_rsp: 3888 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3889 sizeof(request_t), (*req)->ring, (*req)->dma); 3890 (*req)->ring = NULL; 3891 (*req)->dma = 0; 3892 fail_req_ring: 3893 kfree(*req); 3894 fail_req: 3895 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3896 ha->ct_sns, ha->ct_sns_dma); 3897 ha->ct_sns = NULL; 3898 ha->ct_sns_dma = 0; 3899 fail_free_ms_iocb: 3900 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3901 ha->ms_iocb = NULL; 3902 ha->ms_iocb_dma = 0; 3903 3904 if (ha->sns_cmd) 3905 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3906 ha->sns_cmd, ha->sns_cmd_dma); 3907 fail_dma_pool: 3908 if (IS_QLA82XX(ha) || ql2xenabledif) { 3909 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3910 ha->fcp_cmnd_dma_pool = NULL; 3911 } 3912 fail_dl_dma_pool: 3913 if (IS_QLA82XX(ha) || ql2xenabledif) { 3914 dma_pool_destroy(ha->dl_dma_pool); 3915 ha->dl_dma_pool = NULL; 3916 } 3917 fail_s_dma_pool: 3918 dma_pool_destroy(ha->s_dma_pool); 3919 ha->s_dma_pool = NULL; 3920 fail_free_nvram: 3921 kfree(ha->nvram); 3922 ha->nvram = NULL; 3923 fail_free_ctx_mempool: 3924 if (ha->ctx_mempool) 3925 mempool_destroy(ha->ctx_mempool); 3926 ha->ctx_mempool = NULL; 3927 fail_free_srb_mempool: 3928 if (ha->srb_mempool) 3929 mempool_destroy(ha->srb_mempool); 3930 ha->srb_mempool = NULL; 3931 fail_free_gid_list: 3932 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3933 ha->gid_list, 3934 ha->gid_list_dma); 3935 ha->gid_list = NULL; 3936 ha->gid_list_dma = 0; 3937 fail_free_tgt_mem: 3938 qlt_mem_free(ha); 3939 fail_free_init_cb: 3940 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3941 ha->init_cb_dma); 3942 ha->init_cb = NULL; 3943 ha->init_cb_dma = 0; 3944 fail: 3945 ql_log(ql_log_fatal, NULL, 0x0030, 3946 "Memory allocation failure.\n"); 3947 return -ENOMEM; 3948 } 3949 3950 int 3951 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3952 { 3953 int rval; 3954 uint16_t size, max_cnt, temp; 3955 struct qla_hw_data *ha = vha->hw; 3956 3957 /* Return if we don't need to alloacate any extended logins */ 3958 if (!ql2xexlogins) 3959 return QLA_SUCCESS; 3960 3961 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3962 max_cnt = 0; 3963 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3964 if (rval != QLA_SUCCESS) { 3965 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3966 "Failed to get exlogin status.\n"); 3967 return rval; 3968 } 3969 3970 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3971 ha->exlogin_size = (size * temp); 3972 ql_log(ql_log_info, vha, 0xd024, 3973 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3974 max_cnt, size, temp); 3975 3976 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3977 ha->exlogin_size); 3978 3979 /* Get consistent memory for extended logins */ 3980 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 3981 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 3982 if (!ha->exlogin_buf) { 3983 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 3984 "Failed to allocate memory for exlogin_buf_dma.\n"); 3985 return -ENOMEM; 3986 } 3987 3988 /* Now configure the dma buffer */ 3989 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 3990 if (rval) { 3991 ql_log(ql_log_fatal, vha, 0x00cf, 3992 "Setup extended login buffer ****FAILED****.\n"); 3993 qla2x00_free_exlogin_buffer(ha); 3994 } 3995 3996 return rval; 3997 } 3998 3999 /* 4000 * qla2x00_free_exlogin_buffer 4001 * 4002 * Input: 4003 * ha = adapter block pointer 4004 */ 4005 void 4006 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4007 { 4008 if (ha->exlogin_buf) { 4009 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4010 ha->exlogin_buf, ha->exlogin_buf_dma); 4011 ha->exlogin_buf = NULL; 4012 ha->exlogin_size = 0; 4013 } 4014 } 4015 4016 int 4017 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4018 { 4019 int rval; 4020 uint16_t size, max_cnt, temp; 4021 struct qla_hw_data *ha = vha->hw; 4022 4023 /* Return if we don't need to alloacate any extended logins */ 4024 if (!ql2xexchoffld) 4025 return QLA_SUCCESS; 4026 4027 ql_log(ql_log_info, vha, 0xd014, 4028 "Exchange offload count: %d.\n", ql2xexlogins); 4029 4030 max_cnt = 0; 4031 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4032 if (rval != QLA_SUCCESS) { 4033 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4034 "Failed to get exlogin status.\n"); 4035 return rval; 4036 } 4037 4038 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 4039 ha->exchoffld_size = (size * temp); 4040 ql_log(ql_log_info, vha, 0xd016, 4041 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 4042 max_cnt, size, temp); 4043 4044 ql_log(ql_log_info, vha, 0xd017, 4045 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 4046 4047 /* Get consistent memory for extended logins */ 4048 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4049 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4050 if (!ha->exchoffld_buf) { 4051 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4052 "Failed to allocate memory for exchoffld_buf_dma.\n"); 4053 return -ENOMEM; 4054 } 4055 4056 /* Now configure the dma buffer */ 4057 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 4058 if (rval) { 4059 ql_log(ql_log_fatal, vha, 0xd02e, 4060 "Setup exchange offload buffer ****FAILED****.\n"); 4061 qla2x00_free_exchoffld_buffer(ha); 4062 } 4063 4064 return rval; 4065 } 4066 4067 /* 4068 * qla2x00_free_exchoffld_buffer 4069 * 4070 * Input: 4071 * ha = adapter block pointer 4072 */ 4073 void 4074 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4075 { 4076 if (ha->exchoffld_buf) { 4077 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4078 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4079 ha->exchoffld_buf = NULL; 4080 ha->exchoffld_size = 0; 4081 } 4082 } 4083 4084 /* 4085 * qla2x00_free_fw_dump 4086 * Frees fw dump stuff. 4087 * 4088 * Input: 4089 * ha = adapter block pointer 4090 */ 4091 static void 4092 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4093 { 4094 if (ha->fce) 4095 dma_free_coherent(&ha->pdev->dev, 4096 FCE_SIZE, ha->fce, ha->fce_dma); 4097 4098 if (ha->eft) 4099 dma_free_coherent(&ha->pdev->dev, 4100 EFT_SIZE, ha->eft, ha->eft_dma); 4101 4102 if (ha->fw_dump) 4103 vfree(ha->fw_dump); 4104 if (ha->fw_dump_template) 4105 vfree(ha->fw_dump_template); 4106 4107 ha->fce = NULL; 4108 ha->fce_dma = 0; 4109 ha->eft = NULL; 4110 ha->eft_dma = 0; 4111 ha->fw_dumped = 0; 4112 ha->fw_dump_cap_flags = 0; 4113 ha->fw_dump_reading = 0; 4114 ha->fw_dump = NULL; 4115 ha->fw_dump_len = 0; 4116 ha->fw_dump_template = NULL; 4117 ha->fw_dump_template_len = 0; 4118 } 4119 4120 /* 4121 * qla2x00_mem_free 4122 * Frees all adapter allocated memory. 4123 * 4124 * Input: 4125 * ha = adapter block pointer. 4126 */ 4127 static void 4128 qla2x00_mem_free(struct qla_hw_data *ha) 4129 { 4130 qla2x00_free_fw_dump(ha); 4131 4132 if (ha->mctp_dump) 4133 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4134 ha->mctp_dump_dma); 4135 4136 if (ha->srb_mempool) 4137 mempool_destroy(ha->srb_mempool); 4138 4139 if (ha->dcbx_tlv) 4140 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4141 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4142 4143 if (ha->xgmac_data) 4144 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4145 ha->xgmac_data, ha->xgmac_data_dma); 4146 4147 if (ha->sns_cmd) 4148 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4149 ha->sns_cmd, ha->sns_cmd_dma); 4150 4151 if (ha->ct_sns) 4152 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4153 ha->ct_sns, ha->ct_sns_dma); 4154 4155 if (ha->sfp_data) 4156 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 4157 4158 if (ha->ms_iocb) 4159 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4160 4161 if (ha->ex_init_cb) 4162 dma_pool_free(ha->s_dma_pool, 4163 ha->ex_init_cb, ha->ex_init_cb_dma); 4164 4165 if (ha->async_pd) 4166 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4167 4168 if (ha->s_dma_pool) 4169 dma_pool_destroy(ha->s_dma_pool); 4170 4171 if (ha->gid_list) 4172 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4173 ha->gid_list, ha->gid_list_dma); 4174 4175 if (IS_QLA82XX(ha)) { 4176 if (!list_empty(&ha->gbl_dsd_list)) { 4177 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4178 4179 /* clean up allocated prev pool */ 4180 list_for_each_entry_safe(dsd_ptr, 4181 tdsd_ptr, &ha->gbl_dsd_list, list) { 4182 dma_pool_free(ha->dl_dma_pool, 4183 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4184 list_del(&dsd_ptr->list); 4185 kfree(dsd_ptr); 4186 } 4187 } 4188 } 4189 4190 if (ha->dl_dma_pool) 4191 dma_pool_destroy(ha->dl_dma_pool); 4192 4193 if (ha->fcp_cmnd_dma_pool) 4194 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4195 4196 if (ha->ctx_mempool) 4197 mempool_destroy(ha->ctx_mempool); 4198 4199 qlt_mem_free(ha); 4200 4201 if (ha->init_cb) 4202 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4203 ha->init_cb, ha->init_cb_dma); 4204 vfree(ha->optrom_buffer); 4205 kfree(ha->nvram); 4206 kfree(ha->npiv_info); 4207 kfree(ha->swl); 4208 kfree(ha->loop_id_map); 4209 4210 ha->srb_mempool = NULL; 4211 ha->ctx_mempool = NULL; 4212 ha->sns_cmd = NULL; 4213 ha->sns_cmd_dma = 0; 4214 ha->ct_sns = NULL; 4215 ha->ct_sns_dma = 0; 4216 ha->ms_iocb = NULL; 4217 ha->ms_iocb_dma = 0; 4218 ha->init_cb = NULL; 4219 ha->init_cb_dma = 0; 4220 ha->ex_init_cb = NULL; 4221 ha->ex_init_cb_dma = 0; 4222 ha->async_pd = NULL; 4223 ha->async_pd_dma = 0; 4224 4225 ha->s_dma_pool = NULL; 4226 ha->dl_dma_pool = NULL; 4227 ha->fcp_cmnd_dma_pool = NULL; 4228 4229 ha->gid_list = NULL; 4230 ha->gid_list_dma = 0; 4231 4232 ha->tgt.atio_ring = NULL; 4233 ha->tgt.atio_dma = 0; 4234 ha->tgt.tgt_vp_map = NULL; 4235 } 4236 4237 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4238 struct qla_hw_data *ha) 4239 { 4240 struct Scsi_Host *host; 4241 struct scsi_qla_host *vha = NULL; 4242 4243 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4244 if (!host) { 4245 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4246 "Failed to allocate host from the scsi layer, aborting.\n"); 4247 return NULL; 4248 } 4249 4250 /* Clear our data area */ 4251 vha = shost_priv(host); 4252 memset(vha, 0, sizeof(scsi_qla_host_t)); 4253 4254 vha->host = host; 4255 vha->host_no = host->host_no; 4256 vha->hw = ha; 4257 4258 INIT_LIST_HEAD(&vha->vp_fcports); 4259 INIT_LIST_HEAD(&vha->work_list); 4260 INIT_LIST_HEAD(&vha->list); 4261 INIT_LIST_HEAD(&vha->qla_cmd_list); 4262 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4263 INIT_LIST_HEAD(&vha->logo_list); 4264 INIT_LIST_HEAD(&vha->plogi_ack_list); 4265 INIT_LIST_HEAD(&vha->qp_list); 4266 INIT_LIST_HEAD(&vha->gnl.fcports); 4267 4268 spin_lock_init(&vha->work_lock); 4269 spin_lock_init(&vha->cmd_list_lock); 4270 init_waitqueue_head(&vha->fcport_waitQ); 4271 4272 vha->gnl.size = sizeof(struct get_name_list_extended) * 4273 (ha->max_loop_id + 1); 4274 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4275 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4276 if (!vha->gnl.l) { 4277 ql_log(ql_log_fatal, vha, 0xffff, 4278 "Alloc failed for name list.\n"); 4279 scsi_remove_host(vha->host); 4280 return NULL; 4281 } 4282 4283 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4284 ql_dbg(ql_dbg_init, vha, 0x0041, 4285 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4286 vha->host, vha->hw, vha, 4287 dev_name(&(ha->pdev->dev))); 4288 4289 return vha; 4290 } 4291 4292 struct qla_work_evt * 4293 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4294 { 4295 struct qla_work_evt *e; 4296 uint8_t bail; 4297 4298 QLA_VHA_MARK_BUSY(vha, bail); 4299 if (bail) 4300 return NULL; 4301 4302 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4303 if (!e) { 4304 QLA_VHA_MARK_NOT_BUSY(vha); 4305 return NULL; 4306 } 4307 4308 INIT_LIST_HEAD(&e->list); 4309 e->type = type; 4310 e->flags = QLA_EVT_FLAG_FREE; 4311 return e; 4312 } 4313 4314 int 4315 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4316 { 4317 unsigned long flags; 4318 4319 spin_lock_irqsave(&vha->work_lock, flags); 4320 list_add_tail(&e->list, &vha->work_list); 4321 spin_unlock_irqrestore(&vha->work_lock, flags); 4322 qla2xxx_wake_dpc(vha); 4323 4324 return QLA_SUCCESS; 4325 } 4326 4327 int 4328 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4329 u32 data) 4330 { 4331 struct qla_work_evt *e; 4332 4333 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4334 if (!e) 4335 return QLA_FUNCTION_FAILED; 4336 4337 e->u.aen.code = code; 4338 e->u.aen.data = data; 4339 return qla2x00_post_work(vha, e); 4340 } 4341 4342 int 4343 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4344 { 4345 struct qla_work_evt *e; 4346 4347 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4348 if (!e) 4349 return QLA_FUNCTION_FAILED; 4350 4351 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4352 return qla2x00_post_work(vha, e); 4353 } 4354 4355 #define qla2x00_post_async_work(name, type) \ 4356 int qla2x00_post_async_##name##_work( \ 4357 struct scsi_qla_host *vha, \ 4358 fc_port_t *fcport, uint16_t *data) \ 4359 { \ 4360 struct qla_work_evt *e; \ 4361 \ 4362 e = qla2x00_alloc_work(vha, type); \ 4363 if (!e) \ 4364 return QLA_FUNCTION_FAILED; \ 4365 \ 4366 e->u.logio.fcport = fcport; \ 4367 if (data) { \ 4368 e->u.logio.data[0] = data[0]; \ 4369 e->u.logio.data[1] = data[1]; \ 4370 } \ 4371 return qla2x00_post_work(vha, e); \ 4372 } 4373 4374 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4375 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4376 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4377 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4378 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4379 4380 int 4381 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4382 { 4383 struct qla_work_evt *e; 4384 4385 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4386 if (!e) 4387 return QLA_FUNCTION_FAILED; 4388 4389 e->u.uevent.code = code; 4390 return qla2x00_post_work(vha, e); 4391 } 4392 4393 static void 4394 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4395 { 4396 char event_string[40]; 4397 char *envp[] = { event_string, NULL }; 4398 4399 switch (code) { 4400 case QLA_UEVENT_CODE_FW_DUMP: 4401 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4402 vha->host_no); 4403 break; 4404 default: 4405 /* do nothing */ 4406 break; 4407 } 4408 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4409 } 4410 4411 int 4412 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4413 uint32_t *data, int cnt) 4414 { 4415 struct qla_work_evt *e; 4416 4417 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4418 if (!e) 4419 return QLA_FUNCTION_FAILED; 4420 4421 e->u.aenfx.evtcode = evtcode; 4422 e->u.aenfx.count = cnt; 4423 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4424 return qla2x00_post_work(vha, e); 4425 } 4426 4427 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4428 { 4429 struct qla_work_evt *e; 4430 4431 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4432 if (!e) 4433 return QLA_FUNCTION_FAILED; 4434 4435 e->u.fcport.fcport = fcport; 4436 return qla2x00_post_work(vha, e); 4437 } 4438 4439 static 4440 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4441 { 4442 unsigned long flags; 4443 fc_port_t *fcport = NULL; 4444 struct qlt_plogi_ack_t *pla = 4445 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4446 4447 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4448 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4449 if (fcport) { 4450 fcport->d_id = e->u.new_sess.id; 4451 if (pla) { 4452 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4453 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4454 /* we took an extra ref_count to prevent PLOGI ACK when 4455 * fcport/sess has not been created. 4456 */ 4457 pla->ref_count--; 4458 } 4459 } else { 4460 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4461 if (fcport) { 4462 fcport->d_id = e->u.new_sess.id; 4463 fcport->scan_state = QLA_FCPORT_FOUND; 4464 fcport->flags |= FCF_FABRIC_DEVICE; 4465 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4466 4467 memcpy(fcport->port_name, e->u.new_sess.port_name, 4468 WWN_SIZE); 4469 list_add_tail(&fcport->list, &vha->vp_fcports); 4470 4471 if (pla) { 4472 qlt_plogi_ack_link(vha, pla, fcport, 4473 QLT_PLOGI_LINK_SAME_WWN); 4474 pla->ref_count--; 4475 } 4476 } 4477 } 4478 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4479 4480 if (fcport) { 4481 if (pla) 4482 qlt_plogi_ack_unref(vha, pla); 4483 else 4484 qla24xx_async_gnl(vha, fcport); 4485 } 4486 } 4487 4488 void 4489 qla2x00_do_work(struct scsi_qla_host *vha) 4490 { 4491 struct qla_work_evt *e, *tmp; 4492 unsigned long flags; 4493 LIST_HEAD(work); 4494 4495 spin_lock_irqsave(&vha->work_lock, flags); 4496 list_splice_init(&vha->work_list, &work); 4497 spin_unlock_irqrestore(&vha->work_lock, flags); 4498 4499 list_for_each_entry_safe(e, tmp, &work, list) { 4500 list_del_init(&e->list); 4501 4502 switch (e->type) { 4503 case QLA_EVT_AEN: 4504 fc_host_post_event(vha->host, fc_get_event_number(), 4505 e->u.aen.code, e->u.aen.data); 4506 break; 4507 case QLA_EVT_IDC_ACK: 4508 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4509 break; 4510 case QLA_EVT_ASYNC_LOGIN: 4511 qla2x00_async_login(vha, e->u.logio.fcport, 4512 e->u.logio.data); 4513 break; 4514 case QLA_EVT_ASYNC_LOGOUT: 4515 qla2x00_async_logout(vha, e->u.logio.fcport); 4516 break; 4517 case QLA_EVT_ASYNC_LOGOUT_DONE: 4518 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4519 e->u.logio.data); 4520 break; 4521 case QLA_EVT_ASYNC_ADISC: 4522 qla2x00_async_adisc(vha, e->u.logio.fcport, 4523 e->u.logio.data); 4524 break; 4525 case QLA_EVT_ASYNC_ADISC_DONE: 4526 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4527 e->u.logio.data); 4528 break; 4529 case QLA_EVT_UEVENT: 4530 qla2x00_uevent_emit(vha, e->u.uevent.code); 4531 break; 4532 case QLA_EVT_AENFX: 4533 qlafx00_process_aen(vha, e); 4534 break; 4535 case QLA_EVT_GIDPN: 4536 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 4537 break; 4538 case QLA_EVT_GPNID: 4539 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 4540 break; 4541 case QLA_EVT_GPNID_DONE: 4542 qla24xx_async_gpnid_done(vha, e->u.iosb.sp); 4543 break; 4544 case QLA_EVT_NEW_SESS: 4545 qla24xx_create_new_sess(vha, e); 4546 break; 4547 case QLA_EVT_GPDB: 4548 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 4549 e->u.fcport.opt); 4550 break; 4551 case QLA_EVT_GPSC: 4552 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 4553 break; 4554 case QLA_EVT_UPD_FCPORT: 4555 qla2x00_update_fcport(vha, e->u.fcport.fcport); 4556 break; 4557 case QLA_EVT_GNL: 4558 qla24xx_async_gnl(vha, e->u.fcport.fcport); 4559 break; 4560 case QLA_EVT_NACK: 4561 qla24xx_do_nack_work(vha, e); 4562 break; 4563 } 4564 if (e->flags & QLA_EVT_FLAG_FREE) 4565 kfree(e); 4566 4567 /* For each work completed decrement vha ref count */ 4568 QLA_VHA_MARK_NOT_BUSY(vha); 4569 } 4570 } 4571 4572 /* Relogins all the fcports of a vport 4573 * Context: dpc thread 4574 */ 4575 void qla2x00_relogin(struct scsi_qla_host *vha) 4576 { 4577 fc_port_t *fcport; 4578 int status; 4579 struct event_arg ea; 4580 4581 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4582 /* 4583 * If the port is not ONLINE then try to login 4584 * to it if we haven't run out of retries. 4585 */ 4586 if (atomic_read(&fcport->state) != FCS_ONLINE && 4587 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4588 fcport->login_retry--; 4589 if (fcport->flags & FCF_FABRIC_DEVICE) { 4590 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 4591 "%s %8phC DS %d LS %d\n", __func__, 4592 fcport->port_name, fcport->disc_state, 4593 fcport->fw_login_state); 4594 memset(&ea, 0, sizeof(ea)); 4595 ea.event = FCME_RELOGIN; 4596 ea.fcport = fcport; 4597 qla2x00_fcport_event_handler(vha, &ea); 4598 } else { 4599 status = qla2x00_local_device_login(vha, 4600 fcport); 4601 if (status == QLA_SUCCESS) { 4602 fcport->old_loop_id = fcport->loop_id; 4603 ql_dbg(ql_dbg_disc, vha, 0x2003, 4604 "Port login OK: logged in ID 0x%x.\n", 4605 fcport->loop_id); 4606 qla2x00_update_fcport(vha, fcport); 4607 } else if (status == 1) { 4608 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4609 /* retry the login again */ 4610 ql_dbg(ql_dbg_disc, vha, 0x2007, 4611 "Retrying %d login again loop_id 0x%x.\n", 4612 fcport->login_retry, 4613 fcport->loop_id); 4614 } else { 4615 fcport->login_retry = 0; 4616 } 4617 4618 if (fcport->login_retry == 0 && 4619 status != QLA_SUCCESS) 4620 qla2x00_clear_loop_id(fcport); 4621 } 4622 } 4623 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4624 break; 4625 } 4626 } 4627 4628 /* Schedule work on any of the dpc-workqueues */ 4629 void 4630 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4631 { 4632 struct qla_hw_data *ha = base_vha->hw; 4633 4634 switch (work_code) { 4635 case MBA_IDC_AEN: /* 0x8200 */ 4636 if (ha->dpc_lp_wq) 4637 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4638 break; 4639 4640 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4641 if (!ha->flags.nic_core_reset_hdlr_active) { 4642 if (ha->dpc_hp_wq) 4643 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4644 } else 4645 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4646 "NIC Core reset is already active. Skip " 4647 "scheduling it again.\n"); 4648 break; 4649 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4650 if (ha->dpc_hp_wq) 4651 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4652 break; 4653 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4654 if (ha->dpc_hp_wq) 4655 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4656 break; 4657 default: 4658 ql_log(ql_log_warn, base_vha, 0xb05f, 4659 "Unknown work-code=0x%x.\n", work_code); 4660 } 4661 4662 return; 4663 } 4664 4665 /* Work: Perform NIC Core Unrecoverable state handling */ 4666 void 4667 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4668 { 4669 struct qla_hw_data *ha = 4670 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4671 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4672 uint32_t dev_state = 0; 4673 4674 qla83xx_idc_lock(base_vha, 0); 4675 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4676 qla83xx_reset_ownership(base_vha); 4677 if (ha->flags.nic_core_reset_owner) { 4678 ha->flags.nic_core_reset_owner = 0; 4679 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4680 QLA8XXX_DEV_FAILED); 4681 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4682 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4683 } 4684 qla83xx_idc_unlock(base_vha, 0); 4685 } 4686 4687 /* Work: Execute IDC state handler */ 4688 void 4689 qla83xx_idc_state_handler_work(struct work_struct *work) 4690 { 4691 struct qla_hw_data *ha = 4692 container_of(work, struct qla_hw_data, idc_state_handler); 4693 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4694 uint32_t dev_state = 0; 4695 4696 qla83xx_idc_lock(base_vha, 0); 4697 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4698 if (dev_state == QLA8XXX_DEV_FAILED || 4699 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4700 qla83xx_idc_state_handler(base_vha); 4701 qla83xx_idc_unlock(base_vha, 0); 4702 } 4703 4704 static int 4705 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4706 { 4707 int rval = QLA_SUCCESS; 4708 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4709 uint32_t heart_beat_counter1, heart_beat_counter2; 4710 4711 do { 4712 if (time_after(jiffies, heart_beat_wait)) { 4713 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4714 "Nic Core f/w is not alive.\n"); 4715 rval = QLA_FUNCTION_FAILED; 4716 break; 4717 } 4718 4719 qla83xx_idc_lock(base_vha, 0); 4720 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4721 &heart_beat_counter1); 4722 qla83xx_idc_unlock(base_vha, 0); 4723 msleep(100); 4724 qla83xx_idc_lock(base_vha, 0); 4725 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4726 &heart_beat_counter2); 4727 qla83xx_idc_unlock(base_vha, 0); 4728 } while (heart_beat_counter1 == heart_beat_counter2); 4729 4730 return rval; 4731 } 4732 4733 /* Work: Perform NIC Core Reset handling */ 4734 void 4735 qla83xx_nic_core_reset_work(struct work_struct *work) 4736 { 4737 struct qla_hw_data *ha = 4738 container_of(work, struct qla_hw_data, nic_core_reset); 4739 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4740 uint32_t dev_state = 0; 4741 4742 if (IS_QLA2031(ha)) { 4743 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4744 ql_log(ql_log_warn, base_vha, 0xb081, 4745 "Failed to dump mctp\n"); 4746 return; 4747 } 4748 4749 if (!ha->flags.nic_core_reset_hdlr_active) { 4750 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4751 qla83xx_idc_lock(base_vha, 0); 4752 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4753 &dev_state); 4754 qla83xx_idc_unlock(base_vha, 0); 4755 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4756 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4757 "Nic Core f/w is alive.\n"); 4758 return; 4759 } 4760 } 4761 4762 ha->flags.nic_core_reset_hdlr_active = 1; 4763 if (qla83xx_nic_core_reset(base_vha)) { 4764 /* NIC Core reset failed. */ 4765 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4766 "NIC Core reset failed.\n"); 4767 } 4768 ha->flags.nic_core_reset_hdlr_active = 0; 4769 } 4770 } 4771 4772 /* Work: Handle 8200 IDC aens */ 4773 void 4774 qla83xx_service_idc_aen(struct work_struct *work) 4775 { 4776 struct qla_hw_data *ha = 4777 container_of(work, struct qla_hw_data, idc_aen); 4778 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4779 uint32_t dev_state, idc_control; 4780 4781 qla83xx_idc_lock(base_vha, 0); 4782 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4783 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4784 qla83xx_idc_unlock(base_vha, 0); 4785 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4786 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4787 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4788 "Application requested NIC Core Reset.\n"); 4789 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4790 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4791 QLA_SUCCESS) { 4792 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4793 "Other protocol driver requested NIC Core Reset.\n"); 4794 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4795 } 4796 } else if (dev_state == QLA8XXX_DEV_FAILED || 4797 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4798 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4799 } 4800 } 4801 4802 static void 4803 qla83xx_wait_logic(void) 4804 { 4805 int i; 4806 4807 /* Yield CPU */ 4808 if (!in_interrupt()) { 4809 /* 4810 * Wait about 200ms before retrying again. 4811 * This controls the number of retries for single 4812 * lock operation. 4813 */ 4814 msleep(100); 4815 schedule(); 4816 } else { 4817 for (i = 0; i < 20; i++) 4818 cpu_relax(); /* This a nop instr on i386 */ 4819 } 4820 } 4821 4822 static int 4823 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4824 { 4825 int rval; 4826 uint32_t data; 4827 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4828 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4829 struct qla_hw_data *ha = base_vha->hw; 4830 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4831 "Trying force recovery of the IDC lock.\n"); 4832 4833 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4834 if (rval) 4835 return rval; 4836 4837 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4838 return QLA_SUCCESS; 4839 } else { 4840 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4841 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4842 data); 4843 if (rval) 4844 return rval; 4845 4846 msleep(200); 4847 4848 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4849 &data); 4850 if (rval) 4851 return rval; 4852 4853 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4854 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4855 ~(idc_lck_rcvry_stage_mask)); 4856 rval = qla83xx_wr_reg(base_vha, 4857 QLA83XX_IDC_LOCK_RECOVERY, data); 4858 if (rval) 4859 return rval; 4860 4861 /* Forcefully perform IDC UnLock */ 4862 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4863 &data); 4864 if (rval) 4865 return rval; 4866 /* Clear lock-id by setting 0xff */ 4867 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4868 0xff); 4869 if (rval) 4870 return rval; 4871 /* Clear lock-recovery by setting 0x0 */ 4872 rval = qla83xx_wr_reg(base_vha, 4873 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4874 if (rval) 4875 return rval; 4876 } else 4877 return QLA_SUCCESS; 4878 } 4879 4880 return rval; 4881 } 4882 4883 static int 4884 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4885 { 4886 int rval = QLA_SUCCESS; 4887 uint32_t o_drv_lockid, n_drv_lockid; 4888 unsigned long lock_recovery_timeout; 4889 4890 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4891 retry_lockid: 4892 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4893 if (rval) 4894 goto exit; 4895 4896 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4897 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4898 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4899 return QLA_SUCCESS; 4900 else 4901 return QLA_FUNCTION_FAILED; 4902 } 4903 4904 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4905 if (rval) 4906 goto exit; 4907 4908 if (o_drv_lockid == n_drv_lockid) { 4909 qla83xx_wait_logic(); 4910 goto retry_lockid; 4911 } else 4912 return QLA_SUCCESS; 4913 4914 exit: 4915 return rval; 4916 } 4917 4918 void 4919 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4920 { 4921 uint16_t options = (requester_id << 15) | BIT_6; 4922 uint32_t data; 4923 uint32_t lock_owner; 4924 struct qla_hw_data *ha = base_vha->hw; 4925 4926 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4927 retry_lock: 4928 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4929 == QLA_SUCCESS) { 4930 if (data) { 4931 /* Setting lock-id to our function-number */ 4932 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4933 ha->portnum); 4934 } else { 4935 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4936 &lock_owner); 4937 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4938 "Failed to acquire IDC lock, acquired by %d, " 4939 "retrying...\n", lock_owner); 4940 4941 /* Retry/Perform IDC-Lock recovery */ 4942 if (qla83xx_idc_lock_recovery(base_vha) 4943 == QLA_SUCCESS) { 4944 qla83xx_wait_logic(); 4945 goto retry_lock; 4946 } else 4947 ql_log(ql_log_warn, base_vha, 0xb075, 4948 "IDC Lock recovery FAILED.\n"); 4949 } 4950 4951 } 4952 4953 return; 4954 4955 /* XXX: IDC-lock implementation using access-control mbx */ 4956 retry_lock2: 4957 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4958 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4959 "Failed to acquire IDC lock. retrying...\n"); 4960 /* Retry/Perform IDC-Lock recovery */ 4961 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4962 qla83xx_wait_logic(); 4963 goto retry_lock2; 4964 } else 4965 ql_log(ql_log_warn, base_vha, 0xb076, 4966 "IDC Lock recovery FAILED.\n"); 4967 } 4968 4969 return; 4970 } 4971 4972 void 4973 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4974 { 4975 #if 0 4976 uint16_t options = (requester_id << 15) | BIT_7; 4977 #endif 4978 uint16_t retry; 4979 uint32_t data; 4980 struct qla_hw_data *ha = base_vha->hw; 4981 4982 /* IDC-unlock implementation using driver-unlock/lock-id 4983 * remote registers 4984 */ 4985 retry = 0; 4986 retry_unlock: 4987 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4988 == QLA_SUCCESS) { 4989 if (data == ha->portnum) { 4990 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4991 /* Clearing lock-id by setting 0xff */ 4992 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4993 } else if (retry < 10) { 4994 /* SV: XXX: IDC unlock retrying needed here? */ 4995 4996 /* Retry for IDC-unlock */ 4997 qla83xx_wait_logic(); 4998 retry++; 4999 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5000 "Failed to release IDC lock, retrying=%d\n", retry); 5001 goto retry_unlock; 5002 } 5003 } else if (retry < 10) { 5004 /* Retry for IDC-unlock */ 5005 qla83xx_wait_logic(); 5006 retry++; 5007 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5008 "Failed to read drv-lockid, retrying=%d\n", retry); 5009 goto retry_unlock; 5010 } 5011 5012 return; 5013 5014 #if 0 5015 /* XXX: IDC-unlock implementation using access-control mbx */ 5016 retry = 0; 5017 retry_unlock2: 5018 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5019 if (retry < 10) { 5020 /* Retry for IDC-unlock */ 5021 qla83xx_wait_logic(); 5022 retry++; 5023 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5024 "Failed to release IDC lock, retrying=%d\n", retry); 5025 goto retry_unlock2; 5026 } 5027 } 5028 5029 return; 5030 #endif 5031 } 5032 5033 int 5034 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5035 { 5036 int rval = QLA_SUCCESS; 5037 struct qla_hw_data *ha = vha->hw; 5038 uint32_t drv_presence; 5039 5040 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5041 if (rval == QLA_SUCCESS) { 5042 drv_presence |= (1 << ha->portnum); 5043 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5044 drv_presence); 5045 } 5046 5047 return rval; 5048 } 5049 5050 int 5051 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5052 { 5053 int rval = QLA_SUCCESS; 5054 5055 qla83xx_idc_lock(vha, 0); 5056 rval = __qla83xx_set_drv_presence(vha); 5057 qla83xx_idc_unlock(vha, 0); 5058 5059 return rval; 5060 } 5061 5062 int 5063 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5064 { 5065 int rval = QLA_SUCCESS; 5066 struct qla_hw_data *ha = vha->hw; 5067 uint32_t drv_presence; 5068 5069 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5070 if (rval == QLA_SUCCESS) { 5071 drv_presence &= ~(1 << ha->portnum); 5072 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5073 drv_presence); 5074 } 5075 5076 return rval; 5077 } 5078 5079 int 5080 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5081 { 5082 int rval = QLA_SUCCESS; 5083 5084 qla83xx_idc_lock(vha, 0); 5085 rval = __qla83xx_clear_drv_presence(vha); 5086 qla83xx_idc_unlock(vha, 0); 5087 5088 return rval; 5089 } 5090 5091 static void 5092 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5093 { 5094 struct qla_hw_data *ha = vha->hw; 5095 uint32_t drv_ack, drv_presence; 5096 unsigned long ack_timeout; 5097 5098 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5099 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5100 while (1) { 5101 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5102 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5103 if ((drv_ack & drv_presence) == drv_presence) 5104 break; 5105 5106 if (time_after_eq(jiffies, ack_timeout)) { 5107 ql_log(ql_log_warn, vha, 0xb067, 5108 "RESET ACK TIMEOUT! drv_presence=0x%x " 5109 "drv_ack=0x%x\n", drv_presence, drv_ack); 5110 /* 5111 * The function(s) which did not ack in time are forced 5112 * to withdraw any further participation in the IDC 5113 * reset. 5114 */ 5115 if (drv_ack != drv_presence) 5116 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5117 drv_ack); 5118 break; 5119 } 5120 5121 qla83xx_idc_unlock(vha, 0); 5122 msleep(1000); 5123 qla83xx_idc_lock(vha, 0); 5124 } 5125 5126 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5127 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5128 } 5129 5130 static int 5131 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5132 { 5133 int rval = QLA_SUCCESS; 5134 uint32_t idc_control; 5135 5136 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5137 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5138 5139 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5140 __qla83xx_get_idc_control(vha, &idc_control); 5141 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5142 __qla83xx_set_idc_control(vha, 0); 5143 5144 qla83xx_idc_unlock(vha, 0); 5145 rval = qla83xx_restart_nic_firmware(vha); 5146 qla83xx_idc_lock(vha, 0); 5147 5148 if (rval != QLA_SUCCESS) { 5149 ql_log(ql_log_fatal, vha, 0xb06a, 5150 "Failed to restart NIC f/w.\n"); 5151 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5152 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5153 } else { 5154 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5155 "Success in restarting nic f/w.\n"); 5156 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5157 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5158 } 5159 5160 return rval; 5161 } 5162 5163 /* Assumes idc_lock always held on entry */ 5164 int 5165 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5166 { 5167 struct qla_hw_data *ha = base_vha->hw; 5168 int rval = QLA_SUCCESS; 5169 unsigned long dev_init_timeout; 5170 uint32_t dev_state; 5171 5172 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5173 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5174 5175 while (1) { 5176 5177 if (time_after_eq(jiffies, dev_init_timeout)) { 5178 ql_log(ql_log_warn, base_vha, 0xb06e, 5179 "Initialization TIMEOUT!\n"); 5180 /* Init timeout. Disable further NIC Core 5181 * communication. 5182 */ 5183 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5184 QLA8XXX_DEV_FAILED); 5185 ql_log(ql_log_info, base_vha, 0xb06f, 5186 "HW State: FAILED.\n"); 5187 } 5188 5189 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5190 switch (dev_state) { 5191 case QLA8XXX_DEV_READY: 5192 if (ha->flags.nic_core_reset_owner) 5193 qla83xx_idc_audit(base_vha, 5194 IDC_AUDIT_COMPLETION); 5195 ha->flags.nic_core_reset_owner = 0; 5196 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5197 "Reset_owner reset by 0x%x.\n", 5198 ha->portnum); 5199 goto exit; 5200 case QLA8XXX_DEV_COLD: 5201 if (ha->flags.nic_core_reset_owner) 5202 rval = qla83xx_device_bootstrap(base_vha); 5203 else { 5204 /* Wait for AEN to change device-state */ 5205 qla83xx_idc_unlock(base_vha, 0); 5206 msleep(1000); 5207 qla83xx_idc_lock(base_vha, 0); 5208 } 5209 break; 5210 case QLA8XXX_DEV_INITIALIZING: 5211 /* Wait for AEN to change device-state */ 5212 qla83xx_idc_unlock(base_vha, 0); 5213 msleep(1000); 5214 qla83xx_idc_lock(base_vha, 0); 5215 break; 5216 case QLA8XXX_DEV_NEED_RESET: 5217 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5218 qla83xx_need_reset_handler(base_vha); 5219 else { 5220 /* Wait for AEN to change device-state */ 5221 qla83xx_idc_unlock(base_vha, 0); 5222 msleep(1000); 5223 qla83xx_idc_lock(base_vha, 0); 5224 } 5225 /* reset timeout value after need reset handler */ 5226 dev_init_timeout = jiffies + 5227 (ha->fcoe_dev_init_timeout * HZ); 5228 break; 5229 case QLA8XXX_DEV_NEED_QUIESCENT: 5230 /* XXX: DEBUG for now */ 5231 qla83xx_idc_unlock(base_vha, 0); 5232 msleep(1000); 5233 qla83xx_idc_lock(base_vha, 0); 5234 break; 5235 case QLA8XXX_DEV_QUIESCENT: 5236 /* XXX: DEBUG for now */ 5237 if (ha->flags.quiesce_owner) 5238 goto exit; 5239 5240 qla83xx_idc_unlock(base_vha, 0); 5241 msleep(1000); 5242 qla83xx_idc_lock(base_vha, 0); 5243 dev_init_timeout = jiffies + 5244 (ha->fcoe_dev_init_timeout * HZ); 5245 break; 5246 case QLA8XXX_DEV_FAILED: 5247 if (ha->flags.nic_core_reset_owner) 5248 qla83xx_idc_audit(base_vha, 5249 IDC_AUDIT_COMPLETION); 5250 ha->flags.nic_core_reset_owner = 0; 5251 __qla83xx_clear_drv_presence(base_vha); 5252 qla83xx_idc_unlock(base_vha, 0); 5253 qla8xxx_dev_failed_handler(base_vha); 5254 rval = QLA_FUNCTION_FAILED; 5255 qla83xx_idc_lock(base_vha, 0); 5256 goto exit; 5257 case QLA8XXX_BAD_VALUE: 5258 qla83xx_idc_unlock(base_vha, 0); 5259 msleep(1000); 5260 qla83xx_idc_lock(base_vha, 0); 5261 break; 5262 default: 5263 ql_log(ql_log_warn, base_vha, 0xb071, 5264 "Unknown Device State: %x.\n", dev_state); 5265 qla83xx_idc_unlock(base_vha, 0); 5266 qla8xxx_dev_failed_handler(base_vha); 5267 rval = QLA_FUNCTION_FAILED; 5268 qla83xx_idc_lock(base_vha, 0); 5269 goto exit; 5270 } 5271 } 5272 5273 exit: 5274 return rval; 5275 } 5276 5277 void 5278 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5279 { 5280 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5281 board_disable); 5282 struct pci_dev *pdev = ha->pdev; 5283 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5284 5285 /* 5286 * if UNLOAD flag is already set, then continue unload, 5287 * where it was set first. 5288 */ 5289 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5290 return; 5291 5292 ql_log(ql_log_warn, base_vha, 0x015b, 5293 "Disabling adapter.\n"); 5294 5295 qla2x00_wait_for_sess_deletion(base_vha); 5296 5297 set_bit(UNLOADING, &base_vha->dpc_flags); 5298 5299 qla2x00_delete_all_vps(ha, base_vha); 5300 5301 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5302 5303 qla2x00_dfs_remove(base_vha); 5304 5305 qla84xx_put_chip(base_vha); 5306 5307 if (base_vha->timer_active) 5308 qla2x00_stop_timer(base_vha); 5309 5310 base_vha->flags.online = 0; 5311 5312 qla2x00_destroy_deferred_work(ha); 5313 5314 /* 5315 * Do not try to stop beacon blink as it will issue a mailbox 5316 * command. 5317 */ 5318 qla2x00_free_sysfs_attr(base_vha, false); 5319 5320 fc_remove_host(base_vha->host); 5321 5322 scsi_remove_host(base_vha->host); 5323 5324 base_vha->flags.init_done = 0; 5325 qla25xx_delete_queues(base_vha); 5326 qla2x00_free_fcports(base_vha); 5327 qla2x00_free_irqs(base_vha); 5328 qla2x00_mem_free(ha); 5329 qla82xx_md_free(base_vha); 5330 qla2x00_free_queues(ha); 5331 5332 qla2x00_unmap_iobases(ha); 5333 5334 pci_release_selected_regions(ha->pdev, ha->bars); 5335 pci_disable_pcie_error_reporting(pdev); 5336 pci_disable_device(pdev); 5337 5338 /* 5339 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5340 */ 5341 } 5342 5343 /************************************************************************** 5344 * qla2x00_do_dpc 5345 * This kernel thread is a task that is schedule by the interrupt handler 5346 * to perform the background processing for interrupts. 5347 * 5348 * Notes: 5349 * This task always run in the context of a kernel thread. It 5350 * is kick-off by the driver's detect code and starts up 5351 * up one per adapter. It immediately goes to sleep and waits for 5352 * some fibre event. When either the interrupt handler or 5353 * the timer routine detects a event it will one of the task 5354 * bits then wake us up. 5355 **************************************************************************/ 5356 static int 5357 qla2x00_do_dpc(void *data) 5358 { 5359 scsi_qla_host_t *base_vha; 5360 struct qla_hw_data *ha; 5361 uint32_t online; 5362 struct qla_qpair *qpair; 5363 5364 ha = (struct qla_hw_data *)data; 5365 base_vha = pci_get_drvdata(ha->pdev); 5366 5367 set_user_nice(current, MIN_NICE); 5368 5369 set_current_state(TASK_INTERRUPTIBLE); 5370 while (!kthread_should_stop()) { 5371 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5372 "DPC handler sleeping.\n"); 5373 5374 schedule(); 5375 5376 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5377 goto end_loop; 5378 5379 if (ha->flags.eeh_busy) { 5380 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5381 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5382 goto end_loop; 5383 } 5384 5385 ha->dpc_active = 1; 5386 5387 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5388 "DPC handler waking up, dpc_flags=0x%lx.\n", 5389 base_vha->dpc_flags); 5390 5391 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5392 break; 5393 5394 qla2x00_do_work(base_vha); 5395 5396 if (IS_P3P_TYPE(ha)) { 5397 if (IS_QLA8044(ha)) { 5398 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5399 &base_vha->dpc_flags)) { 5400 qla8044_idc_lock(ha); 5401 qla8044_wr_direct(base_vha, 5402 QLA8044_CRB_DEV_STATE_INDEX, 5403 QLA8XXX_DEV_FAILED); 5404 qla8044_idc_unlock(ha); 5405 ql_log(ql_log_info, base_vha, 0x4004, 5406 "HW State: FAILED.\n"); 5407 qla8044_device_state_handler(base_vha); 5408 continue; 5409 } 5410 5411 } else { 5412 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5413 &base_vha->dpc_flags)) { 5414 qla82xx_idc_lock(ha); 5415 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5416 QLA8XXX_DEV_FAILED); 5417 qla82xx_idc_unlock(ha); 5418 ql_log(ql_log_info, base_vha, 0x0151, 5419 "HW State: FAILED.\n"); 5420 qla82xx_device_state_handler(base_vha); 5421 continue; 5422 } 5423 } 5424 5425 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5426 &base_vha->dpc_flags)) { 5427 5428 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5429 "FCoE context reset scheduled.\n"); 5430 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5431 &base_vha->dpc_flags))) { 5432 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5433 /* FCoE-ctx reset failed. 5434 * Escalate to chip-reset 5435 */ 5436 set_bit(ISP_ABORT_NEEDED, 5437 &base_vha->dpc_flags); 5438 } 5439 clear_bit(ABORT_ISP_ACTIVE, 5440 &base_vha->dpc_flags); 5441 } 5442 5443 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5444 "FCoE context reset end.\n"); 5445 } 5446 } else if (IS_QLAFX00(ha)) { 5447 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5448 &base_vha->dpc_flags)) { 5449 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5450 "Firmware Reset Recovery\n"); 5451 if (qlafx00_reset_initialize(base_vha)) { 5452 /* Failed. Abort isp later. */ 5453 if (!test_bit(UNLOADING, 5454 &base_vha->dpc_flags)) { 5455 set_bit(ISP_UNRECOVERABLE, 5456 &base_vha->dpc_flags); 5457 ql_dbg(ql_dbg_dpc, base_vha, 5458 0x4021, 5459 "Reset Recovery Failed\n"); 5460 } 5461 } 5462 } 5463 5464 if (test_and_clear_bit(FX00_TARGET_SCAN, 5465 &base_vha->dpc_flags)) { 5466 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5467 "ISPFx00 Target Scan scheduled\n"); 5468 if (qlafx00_rescan_isp(base_vha)) { 5469 if (!test_bit(UNLOADING, 5470 &base_vha->dpc_flags)) 5471 set_bit(ISP_UNRECOVERABLE, 5472 &base_vha->dpc_flags); 5473 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5474 "ISPFx00 Target Scan Failed\n"); 5475 } 5476 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5477 "ISPFx00 Target Scan End\n"); 5478 } 5479 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5480 &base_vha->dpc_flags)) { 5481 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5482 "ISPFx00 Host Info resend scheduled\n"); 5483 qlafx00_fx_disc(base_vha, 5484 &base_vha->hw->mr.fcport, 5485 FXDISC_REG_HOST_INFO); 5486 } 5487 } 5488 5489 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5490 &base_vha->dpc_flags)) { 5491 5492 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5493 "ISP abort scheduled.\n"); 5494 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5495 &base_vha->dpc_flags))) { 5496 5497 if (ha->isp_ops->abort_isp(base_vha)) { 5498 /* failed. retry later */ 5499 set_bit(ISP_ABORT_NEEDED, 5500 &base_vha->dpc_flags); 5501 } 5502 clear_bit(ABORT_ISP_ACTIVE, 5503 &base_vha->dpc_flags); 5504 } 5505 5506 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5507 "ISP abort end.\n"); 5508 } 5509 5510 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5511 &base_vha->dpc_flags)) { 5512 qla2x00_update_fcports(base_vha); 5513 } 5514 5515 if (IS_QLAFX00(ha)) 5516 goto loop_resync_check; 5517 5518 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5519 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5520 "Quiescence mode scheduled.\n"); 5521 if (IS_P3P_TYPE(ha)) { 5522 if (IS_QLA82XX(ha)) 5523 qla82xx_device_state_handler(base_vha); 5524 if (IS_QLA8044(ha)) 5525 qla8044_device_state_handler(base_vha); 5526 clear_bit(ISP_QUIESCE_NEEDED, 5527 &base_vha->dpc_flags); 5528 if (!ha->flags.quiesce_owner) { 5529 qla2x00_perform_loop_resync(base_vha); 5530 if (IS_QLA82XX(ha)) { 5531 qla82xx_idc_lock(ha); 5532 qla82xx_clear_qsnt_ready( 5533 base_vha); 5534 qla82xx_idc_unlock(ha); 5535 } else if (IS_QLA8044(ha)) { 5536 qla8044_idc_lock(ha); 5537 qla8044_clear_qsnt_ready( 5538 base_vha); 5539 qla8044_idc_unlock(ha); 5540 } 5541 } 5542 } else { 5543 clear_bit(ISP_QUIESCE_NEEDED, 5544 &base_vha->dpc_flags); 5545 qla2x00_quiesce_io(base_vha); 5546 } 5547 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5548 "Quiescence mode end.\n"); 5549 } 5550 5551 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5552 &base_vha->dpc_flags) && 5553 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5554 5555 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5556 "Reset marker scheduled.\n"); 5557 qla2x00_rst_aen(base_vha); 5558 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5559 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5560 "Reset marker end.\n"); 5561 } 5562 5563 /* Retry each device up to login retry count */ 5564 if ((test_and_clear_bit(RELOGIN_NEEDED, 5565 &base_vha->dpc_flags)) && 5566 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5567 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5568 5569 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5570 "Relogin scheduled.\n"); 5571 qla2x00_relogin(base_vha); 5572 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5573 "Relogin end.\n"); 5574 } 5575 loop_resync_check: 5576 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5577 &base_vha->dpc_flags)) { 5578 5579 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5580 "Loop resync scheduled.\n"); 5581 5582 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5583 &base_vha->dpc_flags))) { 5584 5585 qla2x00_loop_resync(base_vha); 5586 5587 clear_bit(LOOP_RESYNC_ACTIVE, 5588 &base_vha->dpc_flags); 5589 } 5590 5591 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5592 "Loop resync end.\n"); 5593 } 5594 5595 if (IS_QLAFX00(ha)) 5596 goto intr_on_check; 5597 5598 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5599 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5600 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5601 qla2xxx_flash_npiv_conf(base_vha); 5602 } 5603 5604 intr_on_check: 5605 if (!ha->interrupts_on) 5606 ha->isp_ops->enable_intrs(ha); 5607 5608 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5609 &base_vha->dpc_flags)) { 5610 if (ha->beacon_blink_led == 1) 5611 ha->isp_ops->beacon_blink(base_vha); 5612 } 5613 5614 /* qpair online check */ 5615 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 5616 &base_vha->dpc_flags)) { 5617 if (ha->flags.eeh_busy || 5618 ha->flags.pci_channel_io_perm_failure) 5619 online = 0; 5620 else 5621 online = 1; 5622 5623 mutex_lock(&ha->mq_lock); 5624 list_for_each_entry(qpair, &base_vha->qp_list, 5625 qp_list_elem) 5626 qpair->online = online; 5627 mutex_unlock(&ha->mq_lock); 5628 } 5629 5630 if (!IS_QLAFX00(ha)) 5631 qla2x00_do_dpc_all_vps(base_vha); 5632 5633 ha->dpc_active = 0; 5634 end_loop: 5635 set_current_state(TASK_INTERRUPTIBLE); 5636 } /* End of while(1) */ 5637 __set_current_state(TASK_RUNNING); 5638 5639 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5640 "DPC handler exiting.\n"); 5641 5642 /* 5643 * Make sure that nobody tries to wake us up again. 5644 */ 5645 ha->dpc_active = 0; 5646 5647 /* Cleanup any residual CTX SRBs. */ 5648 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5649 5650 return 0; 5651 } 5652 5653 void 5654 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5655 { 5656 struct qla_hw_data *ha = vha->hw; 5657 struct task_struct *t = ha->dpc_thread; 5658 5659 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5660 wake_up_process(t); 5661 } 5662 5663 /* 5664 * qla2x00_rst_aen 5665 * Processes asynchronous reset. 5666 * 5667 * Input: 5668 * ha = adapter block pointer. 5669 */ 5670 static void 5671 qla2x00_rst_aen(scsi_qla_host_t *vha) 5672 { 5673 if (vha->flags.online && !vha->flags.reset_active && 5674 !atomic_read(&vha->loop_down_timer) && 5675 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5676 do { 5677 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5678 5679 /* 5680 * Issue marker command only when we are going to start 5681 * the I/O. 5682 */ 5683 vha->marker_needed = 1; 5684 } while (!atomic_read(&vha->loop_down_timer) && 5685 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5686 } 5687 } 5688 5689 /************************************************************************** 5690 * qla2x00_timer 5691 * 5692 * Description: 5693 * One second timer 5694 * 5695 * Context: Interrupt 5696 ***************************************************************************/ 5697 void 5698 qla2x00_timer(scsi_qla_host_t *vha) 5699 { 5700 unsigned long cpu_flags = 0; 5701 int start_dpc = 0; 5702 int index; 5703 srb_t *sp; 5704 uint16_t w; 5705 struct qla_hw_data *ha = vha->hw; 5706 struct req_que *req; 5707 5708 if (ha->flags.eeh_busy) { 5709 ql_dbg(ql_dbg_timer, vha, 0x6000, 5710 "EEH = %d, restarting timer.\n", 5711 ha->flags.eeh_busy); 5712 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5713 return; 5714 } 5715 5716 /* 5717 * Hardware read to raise pending EEH errors during mailbox waits. If 5718 * the read returns -1 then disable the board. 5719 */ 5720 if (!pci_channel_offline(ha->pdev)) { 5721 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5722 qla2x00_check_reg16_for_disconnect(vha, w); 5723 } 5724 5725 /* Make sure qla82xx_watchdog is run only for physical port */ 5726 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5727 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5728 start_dpc++; 5729 if (IS_QLA82XX(ha)) 5730 qla82xx_watchdog(vha); 5731 else if (IS_QLA8044(ha)) 5732 qla8044_watchdog(vha); 5733 } 5734 5735 if (!vha->vp_idx && IS_QLAFX00(ha)) 5736 qlafx00_timer_routine(vha); 5737 5738 /* Loop down handler. */ 5739 if (atomic_read(&vha->loop_down_timer) > 0 && 5740 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5741 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5742 && vha->flags.online) { 5743 5744 if (atomic_read(&vha->loop_down_timer) == 5745 vha->loop_down_abort_time) { 5746 5747 ql_log(ql_log_info, vha, 0x6008, 5748 "Loop down - aborting the queues before time expires.\n"); 5749 5750 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5751 atomic_set(&vha->loop_state, LOOP_DEAD); 5752 5753 /* 5754 * Schedule an ISP abort to return any FCP2-device 5755 * commands. 5756 */ 5757 /* NPIV - scan physical port only */ 5758 if (!vha->vp_idx) { 5759 spin_lock_irqsave(&ha->hardware_lock, 5760 cpu_flags); 5761 req = ha->req_q_map[0]; 5762 for (index = 1; 5763 index < req->num_outstanding_cmds; 5764 index++) { 5765 fc_port_t *sfcp; 5766 5767 sp = req->outstanding_cmds[index]; 5768 if (!sp) 5769 continue; 5770 if (sp->type != SRB_SCSI_CMD) 5771 continue; 5772 sfcp = sp->fcport; 5773 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5774 continue; 5775 5776 if (IS_QLA82XX(ha)) 5777 set_bit(FCOE_CTX_RESET_NEEDED, 5778 &vha->dpc_flags); 5779 else 5780 set_bit(ISP_ABORT_NEEDED, 5781 &vha->dpc_flags); 5782 break; 5783 } 5784 spin_unlock_irqrestore(&ha->hardware_lock, 5785 cpu_flags); 5786 } 5787 start_dpc++; 5788 } 5789 5790 /* if the loop has been down for 4 minutes, reinit adapter */ 5791 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5792 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5793 ql_log(ql_log_warn, vha, 0x6009, 5794 "Loop down - aborting ISP.\n"); 5795 5796 if (IS_QLA82XX(ha)) 5797 set_bit(FCOE_CTX_RESET_NEEDED, 5798 &vha->dpc_flags); 5799 else 5800 set_bit(ISP_ABORT_NEEDED, 5801 &vha->dpc_flags); 5802 } 5803 } 5804 ql_dbg(ql_dbg_timer, vha, 0x600a, 5805 "Loop down - seconds remaining %d.\n", 5806 atomic_read(&vha->loop_down_timer)); 5807 } 5808 /* Check if beacon LED needs to be blinked for physical host only */ 5809 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5810 /* There is no beacon_blink function for ISP82xx */ 5811 if (!IS_P3P_TYPE(ha)) { 5812 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5813 start_dpc++; 5814 } 5815 } 5816 5817 /* Process any deferred work. */ 5818 if (!list_empty(&vha->work_list)) 5819 start_dpc++; 5820 5821 /* Schedule the DPC routine if needed */ 5822 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5823 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5824 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5825 start_dpc || 5826 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5827 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5828 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5829 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5830 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5831 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5832 ql_dbg(ql_dbg_timer, vha, 0x600b, 5833 "isp_abort_needed=%d loop_resync_needed=%d " 5834 "fcport_update_needed=%d start_dpc=%d " 5835 "reset_marker_needed=%d", 5836 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5837 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5838 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5839 start_dpc, 5840 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5841 ql_dbg(ql_dbg_timer, vha, 0x600c, 5842 "beacon_blink_needed=%d isp_unrecoverable=%d " 5843 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5844 "relogin_needed=%d.\n", 5845 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5846 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5847 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5848 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5849 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5850 qla2xxx_wake_dpc(vha); 5851 } 5852 5853 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5854 } 5855 5856 /* Firmware interface routines. */ 5857 5858 #define FW_BLOBS 11 5859 #define FW_ISP21XX 0 5860 #define FW_ISP22XX 1 5861 #define FW_ISP2300 2 5862 #define FW_ISP2322 3 5863 #define FW_ISP24XX 4 5864 #define FW_ISP25XX 5 5865 #define FW_ISP81XX 6 5866 #define FW_ISP82XX 7 5867 #define FW_ISP2031 8 5868 #define FW_ISP8031 9 5869 #define FW_ISP27XX 10 5870 5871 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5872 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5873 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5874 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5875 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5876 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5877 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5878 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5879 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5880 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5881 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5882 5883 5884 static DEFINE_MUTEX(qla_fw_lock); 5885 5886 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5887 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5888 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5889 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5890 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5891 { .name = FW_FILE_ISP24XX, }, 5892 { .name = FW_FILE_ISP25XX, }, 5893 { .name = FW_FILE_ISP81XX, }, 5894 { .name = FW_FILE_ISP82XX, }, 5895 { .name = FW_FILE_ISP2031, }, 5896 { .name = FW_FILE_ISP8031, }, 5897 { .name = FW_FILE_ISP27XX, }, 5898 }; 5899 5900 struct fw_blob * 5901 qla2x00_request_firmware(scsi_qla_host_t *vha) 5902 { 5903 struct qla_hw_data *ha = vha->hw; 5904 struct fw_blob *blob; 5905 5906 if (IS_QLA2100(ha)) { 5907 blob = &qla_fw_blobs[FW_ISP21XX]; 5908 } else if (IS_QLA2200(ha)) { 5909 blob = &qla_fw_blobs[FW_ISP22XX]; 5910 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5911 blob = &qla_fw_blobs[FW_ISP2300]; 5912 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5913 blob = &qla_fw_blobs[FW_ISP2322]; 5914 } else if (IS_QLA24XX_TYPE(ha)) { 5915 blob = &qla_fw_blobs[FW_ISP24XX]; 5916 } else if (IS_QLA25XX(ha)) { 5917 blob = &qla_fw_blobs[FW_ISP25XX]; 5918 } else if (IS_QLA81XX(ha)) { 5919 blob = &qla_fw_blobs[FW_ISP81XX]; 5920 } else if (IS_QLA82XX(ha)) { 5921 blob = &qla_fw_blobs[FW_ISP82XX]; 5922 } else if (IS_QLA2031(ha)) { 5923 blob = &qla_fw_blobs[FW_ISP2031]; 5924 } else if (IS_QLA8031(ha)) { 5925 blob = &qla_fw_blobs[FW_ISP8031]; 5926 } else if (IS_QLA27XX(ha)) { 5927 blob = &qla_fw_blobs[FW_ISP27XX]; 5928 } else { 5929 return NULL; 5930 } 5931 5932 mutex_lock(&qla_fw_lock); 5933 if (blob->fw) 5934 goto out; 5935 5936 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5937 ql_log(ql_log_warn, vha, 0x0063, 5938 "Failed to load firmware image (%s).\n", blob->name); 5939 blob->fw = NULL; 5940 blob = NULL; 5941 goto out; 5942 } 5943 5944 out: 5945 mutex_unlock(&qla_fw_lock); 5946 return blob; 5947 } 5948 5949 static void 5950 qla2x00_release_firmware(void) 5951 { 5952 int idx; 5953 5954 mutex_lock(&qla_fw_lock); 5955 for (idx = 0; idx < FW_BLOBS; idx++) 5956 release_firmware(qla_fw_blobs[idx].fw); 5957 mutex_unlock(&qla_fw_lock); 5958 } 5959 5960 static pci_ers_result_t 5961 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5962 { 5963 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5964 struct qla_hw_data *ha = vha->hw; 5965 5966 ql_dbg(ql_dbg_aer, vha, 0x9000, 5967 "PCI error detected, state %x.\n", state); 5968 5969 switch (state) { 5970 case pci_channel_io_normal: 5971 ha->flags.eeh_busy = 0; 5972 if (ql2xmqsupport) { 5973 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5974 qla2xxx_wake_dpc(vha); 5975 } 5976 return PCI_ERS_RESULT_CAN_RECOVER; 5977 case pci_channel_io_frozen: 5978 ha->flags.eeh_busy = 1; 5979 /* For ISP82XX complete any pending mailbox cmd */ 5980 if (IS_QLA82XX(ha)) { 5981 ha->flags.isp82xx_fw_hung = 1; 5982 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5983 qla82xx_clear_pending_mbx(vha); 5984 } 5985 qla2x00_free_irqs(vha); 5986 pci_disable_device(pdev); 5987 /* Return back all IOs */ 5988 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5989 if (ql2xmqsupport) { 5990 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5991 qla2xxx_wake_dpc(vha); 5992 } 5993 return PCI_ERS_RESULT_NEED_RESET; 5994 case pci_channel_io_perm_failure: 5995 ha->flags.pci_channel_io_perm_failure = 1; 5996 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5997 if (ql2xmqsupport) { 5998 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5999 qla2xxx_wake_dpc(vha); 6000 } 6001 return PCI_ERS_RESULT_DISCONNECT; 6002 } 6003 return PCI_ERS_RESULT_NEED_RESET; 6004 } 6005 6006 static pci_ers_result_t 6007 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6008 { 6009 int risc_paused = 0; 6010 uint32_t stat; 6011 unsigned long flags; 6012 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6013 struct qla_hw_data *ha = base_vha->hw; 6014 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6015 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6016 6017 if (IS_QLA82XX(ha)) 6018 return PCI_ERS_RESULT_RECOVERED; 6019 6020 spin_lock_irqsave(&ha->hardware_lock, flags); 6021 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6022 stat = RD_REG_DWORD(®->hccr); 6023 if (stat & HCCR_RISC_PAUSE) 6024 risc_paused = 1; 6025 } else if (IS_QLA23XX(ha)) { 6026 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6027 if (stat & HSR_RISC_PAUSED) 6028 risc_paused = 1; 6029 } else if (IS_FWI2_CAPABLE(ha)) { 6030 stat = RD_REG_DWORD(®24->host_status); 6031 if (stat & HSRX_RISC_PAUSED) 6032 risc_paused = 1; 6033 } 6034 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6035 6036 if (risc_paused) { 6037 ql_log(ql_log_info, base_vha, 0x9003, 6038 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6039 ha->isp_ops->fw_dump(base_vha, 0); 6040 6041 return PCI_ERS_RESULT_NEED_RESET; 6042 } else 6043 return PCI_ERS_RESULT_RECOVERED; 6044 } 6045 6046 static uint32_t 6047 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6048 { 6049 uint32_t rval = QLA_FUNCTION_FAILED; 6050 uint32_t drv_active = 0; 6051 struct qla_hw_data *ha = base_vha->hw; 6052 int fn; 6053 struct pci_dev *other_pdev = NULL; 6054 6055 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6056 "Entered %s.\n", __func__); 6057 6058 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6059 6060 if (base_vha->flags.online) { 6061 /* Abort all outstanding commands, 6062 * so as to be requeued later */ 6063 qla2x00_abort_isp_cleanup(base_vha); 6064 } 6065 6066 6067 fn = PCI_FUNC(ha->pdev->devfn); 6068 while (fn > 0) { 6069 fn--; 6070 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6071 "Finding pci device at function = 0x%x.\n", fn); 6072 other_pdev = 6073 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6074 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6075 fn)); 6076 6077 if (!other_pdev) 6078 continue; 6079 if (atomic_read(&other_pdev->enable_cnt)) { 6080 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6081 "Found PCI func available and enable at 0x%x.\n", 6082 fn); 6083 pci_dev_put(other_pdev); 6084 break; 6085 } 6086 pci_dev_put(other_pdev); 6087 } 6088 6089 if (!fn) { 6090 /* Reset owner */ 6091 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6092 "This devfn is reset owner = 0x%x.\n", 6093 ha->pdev->devfn); 6094 qla82xx_idc_lock(ha); 6095 6096 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6097 QLA8XXX_DEV_INITIALIZING); 6098 6099 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6100 QLA82XX_IDC_VERSION); 6101 6102 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6103 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6104 "drv_active = 0x%x.\n", drv_active); 6105 6106 qla82xx_idc_unlock(ha); 6107 /* Reset if device is not already reset 6108 * drv_active would be 0 if a reset has already been done 6109 */ 6110 if (drv_active) 6111 rval = qla82xx_start_firmware(base_vha); 6112 else 6113 rval = QLA_SUCCESS; 6114 qla82xx_idc_lock(ha); 6115 6116 if (rval != QLA_SUCCESS) { 6117 ql_log(ql_log_info, base_vha, 0x900b, 6118 "HW State: FAILED.\n"); 6119 qla82xx_clear_drv_active(ha); 6120 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6121 QLA8XXX_DEV_FAILED); 6122 } else { 6123 ql_log(ql_log_info, base_vha, 0x900c, 6124 "HW State: READY.\n"); 6125 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6126 QLA8XXX_DEV_READY); 6127 qla82xx_idc_unlock(ha); 6128 ha->flags.isp82xx_fw_hung = 0; 6129 rval = qla82xx_restart_isp(base_vha); 6130 qla82xx_idc_lock(ha); 6131 /* Clear driver state register */ 6132 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6133 qla82xx_set_drv_active(base_vha); 6134 } 6135 qla82xx_idc_unlock(ha); 6136 } else { 6137 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6138 "This devfn is not reset owner = 0x%x.\n", 6139 ha->pdev->devfn); 6140 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6141 QLA8XXX_DEV_READY)) { 6142 ha->flags.isp82xx_fw_hung = 0; 6143 rval = qla82xx_restart_isp(base_vha); 6144 qla82xx_idc_lock(ha); 6145 qla82xx_set_drv_active(base_vha); 6146 qla82xx_idc_unlock(ha); 6147 } 6148 } 6149 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6150 6151 return rval; 6152 } 6153 6154 static pci_ers_result_t 6155 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6156 { 6157 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6158 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6159 struct qla_hw_data *ha = base_vha->hw; 6160 struct rsp_que *rsp; 6161 int rc, retries = 10; 6162 6163 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6164 "Slot Reset.\n"); 6165 6166 /* Workaround: qla2xxx driver which access hardware earlier 6167 * needs error state to be pci_channel_io_online. 6168 * Otherwise mailbox command timesout. 6169 */ 6170 pdev->error_state = pci_channel_io_normal; 6171 6172 pci_restore_state(pdev); 6173 6174 /* pci_restore_state() clears the saved_state flag of the device 6175 * save restored state which resets saved_state flag 6176 */ 6177 pci_save_state(pdev); 6178 6179 if (ha->mem_only) 6180 rc = pci_enable_device_mem(pdev); 6181 else 6182 rc = pci_enable_device(pdev); 6183 6184 if (rc) { 6185 ql_log(ql_log_warn, base_vha, 0x9005, 6186 "Can't re-enable PCI device after reset.\n"); 6187 goto exit_slot_reset; 6188 } 6189 6190 rsp = ha->rsp_q_map[0]; 6191 if (qla2x00_request_irqs(ha, rsp)) 6192 goto exit_slot_reset; 6193 6194 if (ha->isp_ops->pci_config(base_vha)) 6195 goto exit_slot_reset; 6196 6197 if (IS_QLA82XX(ha)) { 6198 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6199 ret = PCI_ERS_RESULT_RECOVERED; 6200 goto exit_slot_reset; 6201 } else 6202 goto exit_slot_reset; 6203 } 6204 6205 while (ha->flags.mbox_busy && retries--) 6206 msleep(1000); 6207 6208 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6209 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6210 ret = PCI_ERS_RESULT_RECOVERED; 6211 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6212 6213 6214 exit_slot_reset: 6215 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6216 "slot_reset return %x.\n", ret); 6217 6218 return ret; 6219 } 6220 6221 static void 6222 qla2xxx_pci_resume(struct pci_dev *pdev) 6223 { 6224 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6225 struct qla_hw_data *ha = base_vha->hw; 6226 int ret; 6227 6228 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6229 "pci_resume.\n"); 6230 6231 ret = qla2x00_wait_for_hba_online(base_vha); 6232 if (ret != QLA_SUCCESS) { 6233 ql_log(ql_log_fatal, base_vha, 0x9002, 6234 "The device failed to resume I/O from slot/link_reset.\n"); 6235 } 6236 6237 pci_cleanup_aer_uncorrect_error_status(pdev); 6238 6239 ha->flags.eeh_busy = 0; 6240 } 6241 6242 static void 6243 qla83xx_disable_laser(scsi_qla_host_t *vha) 6244 { 6245 uint32_t reg, data, fn; 6246 struct qla_hw_data *ha = vha->hw; 6247 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 6248 6249 /* pci func #/port # */ 6250 ql_dbg(ql_dbg_init, vha, 0x004b, 6251 "Disabling Laser for hba: %p\n", vha); 6252 6253 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 6254 (BIT_15|BIT_14|BIT_13|BIT_12)); 6255 6256 fn = (fn >> 12); 6257 6258 if (fn & 1) 6259 reg = PORT_1_2031; 6260 else 6261 reg = PORT_0_2031; 6262 6263 data = LASER_OFF_2031; 6264 6265 qla83xx_wr_reg(vha, reg, data); 6266 } 6267 6268 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6269 { 6270 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6271 6272 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6273 } 6274 6275 static const struct pci_error_handlers qla2xxx_err_handler = { 6276 .error_detected = qla2xxx_pci_error_detected, 6277 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6278 .slot_reset = qla2xxx_pci_slot_reset, 6279 .resume = qla2xxx_pci_resume, 6280 }; 6281 6282 static struct pci_device_id qla2xxx_pci_tbl[] = { 6283 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6284 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6285 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6286 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6287 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6288 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6289 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6290 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6291 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6292 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6293 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6294 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6295 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6296 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6297 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6298 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6299 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6300 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6301 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6302 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6303 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6304 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6305 { 0 }, 6306 }; 6307 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6308 6309 static struct pci_driver qla2xxx_pci_driver = { 6310 .name = QLA2XXX_DRIVER_NAME, 6311 .driver = { 6312 .owner = THIS_MODULE, 6313 }, 6314 .id_table = qla2xxx_pci_tbl, 6315 .probe = qla2x00_probe_one, 6316 .remove = qla2x00_remove_one, 6317 .shutdown = qla2x00_shutdown, 6318 .err_handler = &qla2xxx_err_handler, 6319 }; 6320 6321 static const struct file_operations apidev_fops = { 6322 .owner = THIS_MODULE, 6323 .llseek = noop_llseek, 6324 }; 6325 6326 /** 6327 * qla2x00_module_init - Module initialization. 6328 **/ 6329 static int __init 6330 qla2x00_module_init(void) 6331 { 6332 int ret = 0; 6333 6334 /* Allocate cache for SRBs. */ 6335 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6336 SLAB_HWCACHE_ALIGN, NULL); 6337 if (srb_cachep == NULL) { 6338 ql_log(ql_log_fatal, NULL, 0x0001, 6339 "Unable to allocate SRB cache...Failing load!.\n"); 6340 return -ENOMEM; 6341 } 6342 6343 /* Initialize target kmem_cache and mem_pools */ 6344 ret = qlt_init(); 6345 if (ret < 0) { 6346 kmem_cache_destroy(srb_cachep); 6347 return ret; 6348 } else if (ret > 0) { 6349 /* 6350 * If initiator mode is explictly disabled by qlt_init(), 6351 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6352 * performing scsi_scan_target() during LOOP UP event. 6353 */ 6354 qla2xxx_transport_functions.disable_target_scan = 1; 6355 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6356 } 6357 6358 /* Derive version string. */ 6359 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6360 if (ql2xextended_error_logging) 6361 strcat(qla2x00_version_str, "-debug"); 6362 6363 qla2xxx_transport_template = 6364 fc_attach_transport(&qla2xxx_transport_functions); 6365 if (!qla2xxx_transport_template) { 6366 kmem_cache_destroy(srb_cachep); 6367 ql_log(ql_log_fatal, NULL, 0x0002, 6368 "fc_attach_transport failed...Failing load!.\n"); 6369 qlt_exit(); 6370 return -ENODEV; 6371 } 6372 6373 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6374 if (apidev_major < 0) { 6375 ql_log(ql_log_fatal, NULL, 0x0003, 6376 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6377 } 6378 6379 qla2xxx_transport_vport_template = 6380 fc_attach_transport(&qla2xxx_transport_vport_functions); 6381 if (!qla2xxx_transport_vport_template) { 6382 kmem_cache_destroy(srb_cachep); 6383 qlt_exit(); 6384 fc_release_transport(qla2xxx_transport_template); 6385 ql_log(ql_log_fatal, NULL, 0x0004, 6386 "fc_attach_transport vport failed...Failing load!.\n"); 6387 return -ENODEV; 6388 } 6389 ql_log(ql_log_info, NULL, 0x0005, 6390 "QLogic Fibre Channel HBA Driver: %s.\n", 6391 qla2x00_version_str); 6392 ret = pci_register_driver(&qla2xxx_pci_driver); 6393 if (ret) { 6394 kmem_cache_destroy(srb_cachep); 6395 qlt_exit(); 6396 fc_release_transport(qla2xxx_transport_template); 6397 fc_release_transport(qla2xxx_transport_vport_template); 6398 ql_log(ql_log_fatal, NULL, 0x0006, 6399 "pci_register_driver failed...ret=%d Failing load!.\n", 6400 ret); 6401 } 6402 return ret; 6403 } 6404 6405 /** 6406 * qla2x00_module_exit - Module cleanup. 6407 **/ 6408 static void __exit 6409 qla2x00_module_exit(void) 6410 { 6411 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6412 pci_unregister_driver(&qla2xxx_pci_driver); 6413 qla2x00_release_firmware(); 6414 kmem_cache_destroy(srb_cachep); 6415 qlt_exit(); 6416 if (ctx_cachep) 6417 kmem_cache_destroy(ctx_cachep); 6418 fc_release_transport(qla2xxx_transport_template); 6419 fc_release_transport(qla2xxx_transport_vport_template); 6420 } 6421 6422 module_init(qla2x00_module_init); 6423 module_exit(qla2x00_module_exit); 6424 6425 MODULE_AUTHOR("QLogic Corporation"); 6426 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6427 MODULE_LICENSE("GPL"); 6428 MODULE_VERSION(QLA2XXX_VERSION); 6429 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6430 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6431 MODULE_FIRMWARE(FW_FILE_ISP2300); 6432 MODULE_FIRMWARE(FW_FILE_ISP2322); 6433 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6434 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6435