1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101 int ql2xshiftctondsd = 6; 102 module_param(ql2xshiftctondsd, int, S_IRUGO); 103 MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107 int ql2xfdmienable=1; 108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 109 MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113 #define MAX_Q_DEPTH 32 114 static int ql2xmaxqdepth = MAX_Q_DEPTH; 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116 MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120 int ql2xenabledif = 2; 121 module_param(ql2xenabledif, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF:\n" 124 " Default is 2.\n" 125 " 0 -- No DIF Support\n" 126 " 1 -- Enable DIF for all types\n" 127 " 2 -- Enable DIF for all types, except Type 0.\n"); 128 129 int ql2xenablehba_err_chk = 2; 130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xenablehba_err_chk, 132 " Enable T10-CRC-DIF Error isolation by HBA:\n" 133 " Default is 2.\n" 134 " 0 -- Error isolation disabled\n" 135 " 1 -- Error isolation enabled only for DIX Type 0\n" 136 " 2 -- Error isolation enabled for all Types\n"); 137 138 int ql2xiidmaenable=1; 139 module_param(ql2xiidmaenable, int, S_IRUGO); 140 MODULE_PARM_DESC(ql2xiidmaenable, 141 "Enables iIDMA settings " 142 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 143 144 int ql2xmaxqueues = 1; 145 module_param(ql2xmaxqueues, int, S_IRUGO); 146 MODULE_PARM_DESC(ql2xmaxqueues, 147 "Enables MQ settings " 148 "Default is 1 for single queue. Set it to number " 149 "of queues in MQ mode."); 150 151 int ql2xmultique_tag; 152 module_param(ql2xmultique_tag, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xmultique_tag, 154 "Enables CPU affinity settings for the driver " 155 "Default is 0 for no affinity of request and response IO. " 156 "Set it to 1 to turn on the cpu affinity."); 157 158 int ql2xfwloadbin; 159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 160 MODULE_PARM_DESC(ql2xfwloadbin, 161 "Option to specify location from which to load ISP firmware:.\n" 162 " 2 -- load firmware via the request_firmware() (hotplug).\n" 163 " interface.\n" 164 " 1 -- load firmware from flash.\n" 165 " 0 -- use default semantics.\n"); 166 167 int ql2xetsenable; 168 module_param(ql2xetsenable, int, S_IRUGO); 169 MODULE_PARM_DESC(ql2xetsenable, 170 "Enables firmware ETS burst." 171 "Default is 0 - skip ETS enablement."); 172 173 int ql2xdbwr = 1; 174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 175 MODULE_PARM_DESC(ql2xdbwr, 176 "Option to specify scheme for request queue posting.\n" 177 " 0 -- Regular doorbell.\n" 178 " 1 -- CAMRAM doorbell (faster).\n"); 179 180 int ql2xtargetreset = 1; 181 module_param(ql2xtargetreset, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xtargetreset, 183 "Enable target reset." 184 "Default is 1 - use hw defaults."); 185 186 int ql2xgffidenable; 187 module_param(ql2xgffidenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xgffidenable, 189 "Enables GFF_ID checks of port type. " 190 "Default is 0 - Do not use GFF_ID information."); 191 192 int ql2xasynctmfenable; 193 module_param(ql2xasynctmfenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xasynctmfenable, 195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 196 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 197 198 int ql2xdontresethba; 199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdontresethba, 201 "Option to specify reset behaviour.\n" 202 " 0 (Default) -- Reset on failure.\n" 203 " 1 -- Do not reset on failure.\n"); 204 205 uint64_t ql2xmaxlun = MAX_LUNS; 206 module_param(ql2xmaxlun, ullong, S_IRUGO); 207 MODULE_PARM_DESC(ql2xmaxlun, 208 "Defines the maximum LU number to register with the SCSI " 209 "midlayer. Default is 65535."); 210 211 int ql2xmdcapmask = 0x1F; 212 module_param(ql2xmdcapmask, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xmdcapmask, 214 "Set the Minidump driver capture mask level. " 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 216 217 int ql2xmdenable = 1; 218 module_param(ql2xmdenable, int, S_IRUGO); 219 MODULE_PARM_DESC(ql2xmdenable, 220 "Enable/disable MiniDump. " 221 "0 - MiniDump disabled. " 222 "1 (Default) - MiniDump enabled."); 223 224 /* 225 * SCSI host template entry points 226 */ 227 static int qla2xxx_slave_configure(struct scsi_device * device); 228 static int qla2xxx_slave_alloc(struct scsi_device *); 229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 230 static void qla2xxx_scan_start(struct Scsi_Host *); 231 static void qla2xxx_slave_destroy(struct scsi_device *); 232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 233 static int qla2xxx_eh_abort(struct scsi_cmnd *); 234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 238 239 static void qla2x00_clear_drv_active(struct qla_hw_data *); 240 static void qla2x00_free_device(scsi_qla_host_t *); 241 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 242 243 struct scsi_host_template qla2xxx_driver_template = { 244 .module = THIS_MODULE, 245 .name = QLA2XXX_DRIVER_NAME, 246 .queuecommand = qla2xxx_queuecommand, 247 248 .eh_abort_handler = qla2xxx_eh_abort, 249 .eh_device_reset_handler = qla2xxx_eh_device_reset, 250 .eh_target_reset_handler = qla2xxx_eh_target_reset, 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 252 .eh_host_reset_handler = qla2xxx_eh_host_reset, 253 254 .slave_configure = qla2xxx_slave_configure, 255 256 .slave_alloc = qla2xxx_slave_alloc, 257 .slave_destroy = qla2xxx_slave_destroy, 258 .scan_finished = qla2xxx_scan_finished, 259 .scan_start = qla2xxx_scan_start, 260 .change_queue_depth = scsi_change_queue_depth, 261 .this_id = -1, 262 .cmd_per_lun = 3, 263 .use_clustering = ENABLE_CLUSTERING, 264 .sg_tablesize = SG_ALL, 265 266 .max_sectors = 0xFFFF, 267 .shost_attrs = qla2x00_host_attrs, 268 269 .supported_mode = MODE_INITIATOR, 270 .use_blk_tags = 1, 271 .track_queue_depth = 1, 272 }; 273 274 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 275 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 276 277 /* TODO Convert to inlines 278 * 279 * Timer routines 280 */ 281 282 __inline__ void 283 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 284 { 285 init_timer(&vha->timer); 286 vha->timer.expires = jiffies + interval * HZ; 287 vha->timer.data = (unsigned long)vha; 288 vha->timer.function = (void (*)(unsigned long))func; 289 add_timer(&vha->timer); 290 vha->timer_active = 1; 291 } 292 293 static inline void 294 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 295 { 296 /* Currently used for 82XX only. */ 297 if (vha->device_flags & DFLG_DEV_FAILED) { 298 ql_dbg(ql_dbg_timer, vha, 0x600d, 299 "Device in a failed state, returning.\n"); 300 return; 301 } 302 303 mod_timer(&vha->timer, jiffies + interval * HZ); 304 } 305 306 static __inline__ void 307 qla2x00_stop_timer(scsi_qla_host_t *vha) 308 { 309 del_timer_sync(&vha->timer); 310 vha->timer_active = 0; 311 } 312 313 static int qla2x00_do_dpc(void *data); 314 315 static void qla2x00_rst_aen(scsi_qla_host_t *); 316 317 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 318 struct req_que **, struct rsp_que **); 319 static void qla2x00_free_fw_dump(struct qla_hw_data *); 320 static void qla2x00_mem_free(struct qla_hw_data *); 321 322 /* -------------------------------------------------------------------------- */ 323 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 324 struct rsp_que *rsp) 325 { 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 328 GFP_KERNEL); 329 if (!ha->req_q_map) { 330 ql_log(ql_log_fatal, vha, 0x003b, 331 "Unable to allocate memory for request queue ptrs.\n"); 332 goto fail_req_map; 333 } 334 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 336 GFP_KERNEL); 337 if (!ha->rsp_q_map) { 338 ql_log(ql_log_fatal, vha, 0x003c, 339 "Unable to allocate memory for response queue ptrs.\n"); 340 goto fail_rsp_map; 341 } 342 /* 343 * Make sure we record at least the request and response queue zero in 344 * case we need to free them if part of the probe fails. 345 */ 346 ha->rsp_q_map[0] = rsp; 347 ha->req_q_map[0] = req; 348 set_bit(0, ha->rsp_qid_map); 349 set_bit(0, ha->req_qid_map); 350 return 1; 351 352 fail_rsp_map: 353 kfree(ha->req_q_map); 354 ha->req_q_map = NULL; 355 fail_req_map: 356 return -ENOMEM; 357 } 358 359 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 360 { 361 if (IS_QLAFX00(ha)) { 362 if (req && req->ring_fx00) 363 dma_free_coherent(&ha->pdev->dev, 364 (req->length_fx00 + 1) * sizeof(request_t), 365 req->ring_fx00, req->dma_fx00); 366 } else if (req && req->ring) 367 dma_free_coherent(&ha->pdev->dev, 368 (req->length + 1) * sizeof(request_t), 369 req->ring, req->dma); 370 371 if (req) 372 kfree(req->outstanding_cmds); 373 374 kfree(req); 375 req = NULL; 376 } 377 378 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 379 { 380 if (IS_QLAFX00(ha)) { 381 if (rsp && rsp->ring) 382 dma_free_coherent(&ha->pdev->dev, 383 (rsp->length_fx00 + 1) * sizeof(request_t), 384 rsp->ring_fx00, rsp->dma_fx00); 385 } else if (rsp && rsp->ring) { 386 dma_free_coherent(&ha->pdev->dev, 387 (rsp->length + 1) * sizeof(response_t), 388 rsp->ring, rsp->dma); 389 } 390 kfree(rsp); 391 rsp = NULL; 392 } 393 394 static void qla2x00_free_queues(struct qla_hw_data *ha) 395 { 396 struct req_que *req; 397 struct rsp_que *rsp; 398 int cnt; 399 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 401 req = ha->req_q_map[cnt]; 402 qla2x00_free_req_que(ha, req); 403 } 404 kfree(ha->req_q_map); 405 ha->req_q_map = NULL; 406 407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 408 rsp = ha->rsp_q_map[cnt]; 409 qla2x00_free_rsp_que(ha, rsp); 410 } 411 kfree(ha->rsp_q_map); 412 ha->rsp_q_map = NULL; 413 } 414 415 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 416 { 417 uint16_t options = 0; 418 int ques, req, ret; 419 struct qla_hw_data *ha = vha->hw; 420 421 if (!(ha->fw_attributes & BIT_6)) { 422 ql_log(ql_log_warn, vha, 0x00d8, 423 "Firmware is not multi-queue capable.\n"); 424 goto fail; 425 } 426 if (ql2xmultique_tag) { 427 /* create a request queue for IO */ 428 options |= BIT_7; 429 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 430 QLA_DEFAULT_QUE_QOS); 431 if (!req) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to create request queue.\n"); 434 goto fail; 435 } 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 437 vha->req = ha->req_q_map[req]; 438 options |= BIT_1; 439 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 441 if (!ret) { 442 ql_log(ql_log_warn, vha, 0x00e8, 443 "Failed to create response queue.\n"); 444 goto fail2; 445 } 446 } 447 ha->flags.cpu_affinity_enabled = 1; 448 ql_dbg(ql_dbg_multiq, vha, 0xc007, 449 "CPU affinity mode enabled, " 450 "no. of response queues:%d no. of request queues:%d.\n", 451 ha->max_rsp_queues, ha->max_req_queues); 452 ql_dbg(ql_dbg_init, vha, 0x00e9, 453 "CPU affinity mode enabled, " 454 "no. of response queues:%d no. of request queues:%d.\n", 455 ha->max_rsp_queues, ha->max_req_queues); 456 } 457 return 0; 458 fail2: 459 qla25xx_delete_queues(vha); 460 destroy_workqueue(ha->wq); 461 ha->wq = NULL; 462 vha->req = ha->req_q_map[0]; 463 fail: 464 ha->mqenable = 0; 465 kfree(ha->req_q_map); 466 kfree(ha->rsp_q_map); 467 ha->max_req_queues = ha->max_rsp_queues = 1; 468 return 1; 469 } 470 471 static char * 472 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 473 { 474 struct qla_hw_data *ha = vha->hw; 475 static char *pci_bus_modes[] = { 476 "33", "66", "100", "133", 477 }; 478 uint16_t pci_bus; 479 480 strcpy(str, "PCI"); 481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 482 if (pci_bus) { 483 strcat(str, "-X ("); 484 strcat(str, pci_bus_modes[pci_bus]); 485 } else { 486 pci_bus = (ha->pci_attr & BIT_8) >> 8; 487 strcat(str, " ("); 488 strcat(str, pci_bus_modes[pci_bus]); 489 } 490 strcat(str, " MHz)"); 491 492 return (str); 493 } 494 495 static char * 496 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 497 { 498 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 499 struct qla_hw_data *ha = vha->hw; 500 uint32_t pci_bus; 501 502 if (pci_is_pcie(ha->pdev)) { 503 char lwstr[6]; 504 uint32_t lstat, lspeed, lwidth; 505 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 507 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 509 510 strcpy(str, "PCIe ("); 511 switch (lspeed) { 512 case 1: 513 strcat(str, "2.5GT/s "); 514 break; 515 case 2: 516 strcat(str, "5.0GT/s "); 517 break; 518 case 3: 519 strcat(str, "8.0GT/s "); 520 break; 521 default: 522 strcat(str, "<unknown> "); 523 break; 524 } 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 526 strcat(str, lwstr); 527 528 return str; 529 } 530 531 strcpy(str, "PCI"); 532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 533 if (pci_bus == 0 || pci_bus == 8) { 534 strcat(str, " ("); 535 strcat(str, pci_bus_modes[pci_bus >> 3]); 536 } else { 537 strcat(str, "-X "); 538 if (pci_bus & BIT_2) 539 strcat(str, "Mode 2"); 540 else 541 strcat(str, "Mode 1"); 542 strcat(str, " ("); 543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 544 } 545 strcat(str, " MHz)"); 546 547 return str; 548 } 549 550 static char * 551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 552 { 553 char un_str[10]; 554 struct qla_hw_data *ha = vha->hw; 555 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 557 ha->fw_minor_version, ha->fw_subminor_version); 558 559 if (ha->fw_attributes & BIT_9) { 560 strcat(str, "FLX"); 561 return (str); 562 } 563 564 switch (ha->fw_attributes & 0xFF) { 565 case 0x7: 566 strcat(str, "EF"); 567 break; 568 case 0x17: 569 strcat(str, "TP"); 570 break; 571 case 0x37: 572 strcat(str, "IP"); 573 break; 574 case 0x77: 575 strcat(str, "VI"); 576 break; 577 default: 578 sprintf(un_str, "(%x)", ha->fw_attributes); 579 strcat(str, un_str); 580 break; 581 } 582 if (ha->fw_attributes & 0x100) 583 strcat(str, "X"); 584 585 return (str); 586 } 587 588 static char * 589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 590 { 591 struct qla_hw_data *ha = vha->hw; 592 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 595 return str; 596 } 597 598 void 599 qla2x00_sp_free_dma(void *vha, void *ptr) 600 { 601 srb_t *sp = (srb_t *)ptr; 602 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 603 struct qla_hw_data *ha = sp->fcport->vha->hw; 604 void *ctx = GET_CMD_CTX_SP(sp); 605 606 if (sp->flags & SRB_DMA_VALID) { 607 scsi_dma_unmap(cmd); 608 sp->flags &= ~SRB_DMA_VALID; 609 } 610 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 613 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 615 } 616 617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 618 /* List assured to be having elements */ 619 qla2x00_clean_dsd_pool(ha, sp, NULL); 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 621 } 622 623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 624 dma_pool_free(ha->dl_dma_pool, ctx, 625 ((struct crc_context *)ctx)->crc_ctx_dma); 626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 627 } 628 629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 631 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 633 ctx1->fcp_cmnd_dma); 634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 637 mempool_free(ctx1, ha->ctx_mempool); 638 ctx1 = NULL; 639 } 640 641 CMD_SP(cmd) = NULL; 642 qla2x00_rel_sp(sp->fcport->vha, sp); 643 } 644 645 static void 646 qla2x00_sp_compl(void *data, void *ptr, int res) 647 { 648 struct qla_hw_data *ha = (struct qla_hw_data *)data; 649 srb_t *sp = (srb_t *)ptr; 650 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 651 652 cmd->result = res; 653 654 if (atomic_read(&sp->ref_count) == 0) { 655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 657 sp, GET_CMD_SP(sp)); 658 if (ql2xextended_error_logging & ql_dbg_io) 659 WARN_ON(atomic_read(&sp->ref_count) == 0); 660 return; 661 } 662 if (!atomic_dec_and_test(&sp->ref_count)) 663 return; 664 665 qla2x00_sp_free_dma(ha, sp); 666 cmd->scsi_done(cmd); 667 } 668 669 /* If we are SP1 here, we need to still take and release the host_lock as SP1 670 * does not have the changes necessary to avoid taking host->host_lock. 671 */ 672 static int 673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 674 { 675 scsi_qla_host_t *vha = shost_priv(host); 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 678 struct qla_hw_data *ha = vha->hw; 679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 680 srb_t *sp; 681 int rval; 682 683 if (ha->flags.eeh_busy) { 684 if (ha->flags.pci_channel_io_perm_failure) { 685 ql_dbg(ql_dbg_aer, vha, 0x9010, 686 "PCI Channel IO permanent failure, exiting " 687 "cmd=%p.\n", cmd); 688 cmd->result = DID_NO_CONNECT << 16; 689 } else { 690 ql_dbg(ql_dbg_aer, vha, 0x9011, 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 692 cmd->result = DID_REQUEUE << 16; 693 } 694 goto qc24_fail_command; 695 } 696 697 rval = fc_remote_port_chkready(rport); 698 if (rval) { 699 cmd->result = rval; 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 702 cmd, rval); 703 goto qc24_fail_command; 704 } 705 706 if (!vha->flags.difdix_supported && 707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 708 ql_dbg(ql_dbg_io, vha, 0x3004, 709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 710 cmd); 711 cmd->result = DID_NO_CONNECT << 16; 712 goto qc24_fail_command; 713 } 714 715 if (!fcport) { 716 cmd->result = DID_NO_CONNECT << 16; 717 goto qc24_fail_command; 718 } 719 720 if (atomic_read(&fcport->state) != FCS_ONLINE) { 721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 723 ql_dbg(ql_dbg_io, vha, 0x3005, 724 "Returning DNC, fcport_state=%d loop_state=%d.\n", 725 atomic_read(&fcport->state), 726 atomic_read(&base_vha->loop_state)); 727 cmd->result = DID_NO_CONNECT << 16; 728 goto qc24_fail_command; 729 } 730 goto qc24_target_busy; 731 } 732 733 /* 734 * Return target busy if we've received a non-zero retry_delay_timer 735 * in a FCP_RSP. 736 */ 737 if (fcport->retry_delay_timestamp == 0) { 738 /* retry delay not set */ 739 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 740 fcport->retry_delay_timestamp = 0; 741 else 742 goto qc24_target_busy; 743 744 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 745 if (!sp) 746 goto qc24_host_busy; 747 748 sp->u.scmd.cmd = cmd; 749 sp->type = SRB_SCSI_CMD; 750 atomic_set(&sp->ref_count, 1); 751 CMD_SP(cmd) = (void *)sp; 752 sp->free = qla2x00_sp_free_dma; 753 sp->done = qla2x00_sp_compl; 754 755 rval = ha->isp_ops->start_scsi(sp); 756 if (rval != QLA_SUCCESS) { 757 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 758 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 759 goto qc24_host_busy_free_sp; 760 } 761 762 return 0; 763 764 qc24_host_busy_free_sp: 765 qla2x00_sp_free_dma(ha, sp); 766 767 qc24_host_busy: 768 return SCSI_MLQUEUE_HOST_BUSY; 769 770 qc24_target_busy: 771 return SCSI_MLQUEUE_TARGET_BUSY; 772 773 qc24_fail_command: 774 cmd->scsi_done(cmd); 775 776 return 0; 777 } 778 779 /* 780 * qla2x00_eh_wait_on_command 781 * Waits for the command to be returned by the Firmware for some 782 * max time. 783 * 784 * Input: 785 * cmd = Scsi Command to wait on. 786 * 787 * Return: 788 * Not Found : 0 789 * Found : 1 790 */ 791 static int 792 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 793 { 794 #define ABORT_POLLING_PERIOD 1000 795 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 796 unsigned long wait_iter = ABORT_WAIT_ITER; 797 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 798 struct qla_hw_data *ha = vha->hw; 799 int ret = QLA_SUCCESS; 800 801 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 802 ql_dbg(ql_dbg_taskm, vha, 0x8005, 803 "Return:eh_wait.\n"); 804 return ret; 805 } 806 807 while (CMD_SP(cmd) && wait_iter--) { 808 msleep(ABORT_POLLING_PERIOD); 809 } 810 if (CMD_SP(cmd)) 811 ret = QLA_FUNCTION_FAILED; 812 813 return ret; 814 } 815 816 /* 817 * qla2x00_wait_for_hba_online 818 * Wait till the HBA is online after going through 819 * <= MAX_RETRIES_OF_ISP_ABORT or 820 * finally HBA is disabled ie marked offline 821 * 822 * Input: 823 * ha - pointer to host adapter structure 824 * 825 * Note: 826 * Does context switching-Release SPIN_LOCK 827 * (if any) before calling this routine. 828 * 829 * Return: 830 * Success (Adapter is online) : 0 831 * Failed (Adapter is offline/disabled) : 1 832 */ 833 int 834 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 835 { 836 int return_status; 837 unsigned long wait_online; 838 struct qla_hw_data *ha = vha->hw; 839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 840 841 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 842 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 843 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 844 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 845 ha->dpc_active) && time_before(jiffies, wait_online)) { 846 847 msleep(1000); 848 } 849 if (base_vha->flags.online) 850 return_status = QLA_SUCCESS; 851 else 852 return_status = QLA_FUNCTION_FAILED; 853 854 return (return_status); 855 } 856 857 /* 858 * qla2x00_wait_for_hba_ready 859 * Wait till the HBA is ready before doing driver unload 860 * 861 * Input: 862 * ha - pointer to host adapter structure 863 * 864 * Note: 865 * Does context switching-Release SPIN_LOCK 866 * (if any) before calling this routine. 867 * 868 */ 869 static void 870 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 871 { 872 struct qla_hw_data *ha = vha->hw; 873 874 while (((qla2x00_reset_active(vha)) || ha->dpc_active || 875 ha->flags.mbox_busy) || 876 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 877 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) 878 msleep(1000); 879 } 880 881 int 882 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 883 { 884 int return_status; 885 unsigned long wait_reset; 886 struct qla_hw_data *ha = vha->hw; 887 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 888 889 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 890 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 891 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 892 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 893 ha->dpc_active) && time_before(jiffies, wait_reset)) { 894 895 msleep(1000); 896 897 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 898 ha->flags.chip_reset_done) 899 break; 900 } 901 if (ha->flags.chip_reset_done) 902 return_status = QLA_SUCCESS; 903 else 904 return_status = QLA_FUNCTION_FAILED; 905 906 return return_status; 907 } 908 909 static void 910 sp_get(struct srb *sp) 911 { 912 atomic_inc(&sp->ref_count); 913 } 914 915 /************************************************************************** 916 * qla2xxx_eh_abort 917 * 918 * Description: 919 * The abort function will abort the specified command. 920 * 921 * Input: 922 * cmd = Linux SCSI command packet to be aborted. 923 * 924 * Returns: 925 * Either SUCCESS or FAILED. 926 * 927 * Note: 928 * Only return FAILED if command not returned by firmware. 929 **************************************************************************/ 930 static int 931 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 932 { 933 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 934 srb_t *sp; 935 int ret; 936 unsigned int id; 937 uint64_t lun; 938 unsigned long flags; 939 int rval, wait = 0; 940 struct qla_hw_data *ha = vha->hw; 941 942 if (!CMD_SP(cmd)) 943 return SUCCESS; 944 945 ret = fc_block_scsi_eh(cmd); 946 if (ret != 0) 947 return ret; 948 ret = SUCCESS; 949 950 id = cmd->device->id; 951 lun = cmd->device->lun; 952 953 spin_lock_irqsave(&ha->hardware_lock, flags); 954 sp = (srb_t *) CMD_SP(cmd); 955 if (!sp) { 956 spin_unlock_irqrestore(&ha->hardware_lock, flags); 957 return SUCCESS; 958 } 959 960 ql_dbg(ql_dbg_taskm, vha, 0x8002, 961 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 962 vha->host_no, id, lun, sp, cmd, sp->handle); 963 964 /* Get a reference to the sp and drop the lock.*/ 965 sp_get(sp); 966 967 spin_unlock_irqrestore(&ha->hardware_lock, flags); 968 rval = ha->isp_ops->abort_command(sp); 969 if (rval) { 970 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 971 ret = SUCCESS; 972 else 973 ret = FAILED; 974 975 ql_dbg(ql_dbg_taskm, vha, 0x8003, 976 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 977 } else { 978 ql_dbg(ql_dbg_taskm, vha, 0x8004, 979 "Abort command mbx success cmd=%p.\n", cmd); 980 wait = 1; 981 } 982 983 spin_lock_irqsave(&ha->hardware_lock, flags); 984 sp->done(ha, sp, 0); 985 spin_unlock_irqrestore(&ha->hardware_lock, flags); 986 987 /* Did the command return during mailbox execution? */ 988 if (ret == FAILED && !CMD_SP(cmd)) 989 ret = SUCCESS; 990 991 /* Wait for the command to be returned. */ 992 if (wait) { 993 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 994 ql_log(ql_log_warn, vha, 0x8006, 995 "Abort handler timed out cmd=%p.\n", cmd); 996 ret = FAILED; 997 } 998 } 999 1000 ql_log(ql_log_info, vha, 0x801c, 1001 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1002 vha->host_no, id, lun, wait, ret); 1003 1004 return ret; 1005 } 1006 1007 int 1008 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1009 uint64_t l, enum nexus_wait_type type) 1010 { 1011 int cnt, match, status; 1012 unsigned long flags; 1013 struct qla_hw_data *ha = vha->hw; 1014 struct req_que *req; 1015 srb_t *sp; 1016 struct scsi_cmnd *cmd; 1017 1018 status = QLA_SUCCESS; 1019 1020 spin_lock_irqsave(&ha->hardware_lock, flags); 1021 req = vha->req; 1022 for (cnt = 1; status == QLA_SUCCESS && 1023 cnt < req->num_outstanding_cmds; cnt++) { 1024 sp = req->outstanding_cmds[cnt]; 1025 if (!sp) 1026 continue; 1027 if (sp->type != SRB_SCSI_CMD) 1028 continue; 1029 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1030 continue; 1031 match = 0; 1032 cmd = GET_CMD_SP(sp); 1033 switch (type) { 1034 case WAIT_HOST: 1035 match = 1; 1036 break; 1037 case WAIT_TARGET: 1038 match = cmd->device->id == t; 1039 break; 1040 case WAIT_LUN: 1041 match = (cmd->device->id == t && 1042 cmd->device->lun == l); 1043 break; 1044 } 1045 if (!match) 1046 continue; 1047 1048 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1049 status = qla2x00_eh_wait_on_command(cmd); 1050 spin_lock_irqsave(&ha->hardware_lock, flags); 1051 } 1052 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1053 1054 return status; 1055 } 1056 1057 static char *reset_errors[] = { 1058 "HBA not online", 1059 "HBA not ready", 1060 "Task management failed", 1061 "Waiting for command completions", 1062 }; 1063 1064 static int 1065 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1066 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1067 { 1068 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1069 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1070 int err; 1071 1072 if (!fcport) { 1073 return FAILED; 1074 } 1075 1076 err = fc_block_scsi_eh(cmd); 1077 if (err != 0) 1078 return err; 1079 1080 ql_log(ql_log_info, vha, 0x8009, 1081 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1082 cmd->device->id, cmd->device->lun, cmd); 1083 1084 err = 0; 1085 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1086 ql_log(ql_log_warn, vha, 0x800a, 1087 "Wait for hba online failed for cmd=%p.\n", cmd); 1088 goto eh_reset_failed; 1089 } 1090 err = 2; 1091 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1092 != QLA_SUCCESS) { 1093 ql_log(ql_log_warn, vha, 0x800c, 1094 "do_reset failed for cmd=%p.\n", cmd); 1095 goto eh_reset_failed; 1096 } 1097 err = 3; 1098 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1099 cmd->device->lun, type) != QLA_SUCCESS) { 1100 ql_log(ql_log_warn, vha, 0x800d, 1101 "wait for pending cmds failed for cmd=%p.\n", cmd); 1102 goto eh_reset_failed; 1103 } 1104 1105 ql_log(ql_log_info, vha, 0x800e, 1106 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1107 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1108 1109 return SUCCESS; 1110 1111 eh_reset_failed: 1112 ql_log(ql_log_info, vha, 0x800f, 1113 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1114 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1115 cmd); 1116 return FAILED; 1117 } 1118 1119 static int 1120 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1121 { 1122 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1123 struct qla_hw_data *ha = vha->hw; 1124 1125 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1126 ha->isp_ops->lun_reset); 1127 } 1128 1129 static int 1130 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1131 { 1132 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1133 struct qla_hw_data *ha = vha->hw; 1134 1135 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1136 ha->isp_ops->target_reset); 1137 } 1138 1139 /************************************************************************** 1140 * qla2xxx_eh_bus_reset 1141 * 1142 * Description: 1143 * The bus reset function will reset the bus and abort any executing 1144 * commands. 1145 * 1146 * Input: 1147 * cmd = Linux SCSI command packet of the command that cause the 1148 * bus reset. 1149 * 1150 * Returns: 1151 * SUCCESS/FAILURE (defined as macro in scsi.h). 1152 * 1153 **************************************************************************/ 1154 static int 1155 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1156 { 1157 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1158 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1159 int ret = FAILED; 1160 unsigned int id; 1161 uint64_t lun; 1162 1163 id = cmd->device->id; 1164 lun = cmd->device->lun; 1165 1166 if (!fcport) { 1167 return ret; 1168 } 1169 1170 ret = fc_block_scsi_eh(cmd); 1171 if (ret != 0) 1172 return ret; 1173 ret = FAILED; 1174 1175 ql_log(ql_log_info, vha, 0x8012, 1176 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1177 1178 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1179 ql_log(ql_log_fatal, vha, 0x8013, 1180 "Wait for hba online failed board disabled.\n"); 1181 goto eh_bus_reset_done; 1182 } 1183 1184 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1185 ret = SUCCESS; 1186 1187 if (ret == FAILED) 1188 goto eh_bus_reset_done; 1189 1190 /* Flush outstanding commands. */ 1191 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1192 QLA_SUCCESS) { 1193 ql_log(ql_log_warn, vha, 0x8014, 1194 "Wait for pending commands failed.\n"); 1195 ret = FAILED; 1196 } 1197 1198 eh_bus_reset_done: 1199 ql_log(ql_log_warn, vha, 0x802b, 1200 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1201 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1202 1203 return ret; 1204 } 1205 1206 /************************************************************************** 1207 * qla2xxx_eh_host_reset 1208 * 1209 * Description: 1210 * The reset function will reset the Adapter. 1211 * 1212 * Input: 1213 * cmd = Linux SCSI command packet of the command that cause the 1214 * adapter reset. 1215 * 1216 * Returns: 1217 * Either SUCCESS or FAILED. 1218 * 1219 * Note: 1220 **************************************************************************/ 1221 static int 1222 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1223 { 1224 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1225 struct qla_hw_data *ha = vha->hw; 1226 int ret = FAILED; 1227 unsigned int id; 1228 uint64_t lun; 1229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1230 1231 id = cmd->device->id; 1232 lun = cmd->device->lun; 1233 1234 ql_log(ql_log_info, vha, 0x8018, 1235 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1236 1237 /* 1238 * No point in issuing another reset if one is active. Also do not 1239 * attempt a reset if we are updating flash. 1240 */ 1241 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1242 goto eh_host_reset_lock; 1243 1244 if (vha != base_vha) { 1245 if (qla2x00_vp_abort_isp(vha)) 1246 goto eh_host_reset_lock; 1247 } else { 1248 if (IS_P3P_TYPE(vha->hw)) { 1249 if (!qla82xx_fcoe_ctx_reset(vha)) { 1250 /* Ctx reset success */ 1251 ret = SUCCESS; 1252 goto eh_host_reset_lock; 1253 } 1254 /* fall thru if ctx reset failed */ 1255 } 1256 if (ha->wq) 1257 flush_workqueue(ha->wq); 1258 1259 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1260 if (ha->isp_ops->abort_isp(base_vha)) { 1261 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1262 /* failed. schedule dpc to try */ 1263 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1264 1265 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1266 ql_log(ql_log_warn, vha, 0x802a, 1267 "wait for hba online failed.\n"); 1268 goto eh_host_reset_lock; 1269 } 1270 } 1271 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1272 } 1273 1274 /* Waiting for command to be returned to OS.*/ 1275 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1276 QLA_SUCCESS) 1277 ret = SUCCESS; 1278 1279 eh_host_reset_lock: 1280 ql_log(ql_log_info, vha, 0x8017, 1281 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1282 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1283 1284 return ret; 1285 } 1286 1287 /* 1288 * qla2x00_loop_reset 1289 * Issue loop reset. 1290 * 1291 * Input: 1292 * ha = adapter block pointer. 1293 * 1294 * Returns: 1295 * 0 = success 1296 */ 1297 int 1298 qla2x00_loop_reset(scsi_qla_host_t *vha) 1299 { 1300 int ret; 1301 struct fc_port *fcport; 1302 struct qla_hw_data *ha = vha->hw; 1303 1304 if (IS_QLAFX00(ha)) { 1305 return qlafx00_loop_reset(vha); 1306 } 1307 1308 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1309 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1310 if (fcport->port_type != FCT_TARGET) 1311 continue; 1312 1313 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1314 if (ret != QLA_SUCCESS) { 1315 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1316 "Bus Reset failed: Reset=%d " 1317 "d_id=%x.\n", ret, fcport->d_id.b24); 1318 } 1319 } 1320 } 1321 1322 1323 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1324 atomic_set(&vha->loop_state, LOOP_DOWN); 1325 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1326 qla2x00_mark_all_devices_lost(vha, 0); 1327 ret = qla2x00_full_login_lip(vha); 1328 if (ret != QLA_SUCCESS) { 1329 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1330 "full_login_lip=%d.\n", ret); 1331 } 1332 } 1333 1334 if (ha->flags.enable_lip_reset) { 1335 ret = qla2x00_lip_reset(vha); 1336 if (ret != QLA_SUCCESS) 1337 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1338 "lip_reset failed (%d).\n", ret); 1339 } 1340 1341 /* Issue marker command only when we are going to start the I/O */ 1342 vha->marker_needed = 1; 1343 1344 return QLA_SUCCESS; 1345 } 1346 1347 void 1348 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1349 { 1350 int que, cnt; 1351 unsigned long flags; 1352 srb_t *sp; 1353 struct qla_hw_data *ha = vha->hw; 1354 struct req_que *req; 1355 1356 qlt_host_reset_handler(ha); 1357 1358 spin_lock_irqsave(&ha->hardware_lock, flags); 1359 for (que = 0; que < ha->max_req_queues; que++) { 1360 req = ha->req_q_map[que]; 1361 if (!req) 1362 continue; 1363 if (!req->outstanding_cmds) 1364 continue; 1365 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1366 sp = req->outstanding_cmds[cnt]; 1367 if (sp) { 1368 req->outstanding_cmds[cnt] = NULL; 1369 sp->done(vha, sp, res); 1370 } 1371 } 1372 } 1373 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1374 } 1375 1376 static int 1377 qla2xxx_slave_alloc(struct scsi_device *sdev) 1378 { 1379 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1380 1381 if (!rport || fc_remote_port_chkready(rport)) 1382 return -ENXIO; 1383 1384 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1385 1386 return 0; 1387 } 1388 1389 static int 1390 qla2xxx_slave_configure(struct scsi_device *sdev) 1391 { 1392 scsi_qla_host_t *vha = shost_priv(sdev->host); 1393 struct req_que *req = vha->req; 1394 1395 if (IS_T10_PI_CAPABLE(vha->hw)) 1396 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1397 1398 scsi_change_queue_depth(sdev, req->max_q_depth); 1399 return 0; 1400 } 1401 1402 static void 1403 qla2xxx_slave_destroy(struct scsi_device *sdev) 1404 { 1405 sdev->hostdata = NULL; 1406 } 1407 1408 /** 1409 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1410 * @ha: HA context 1411 * 1412 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1413 * supported addressing method. 1414 */ 1415 static void 1416 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1417 { 1418 /* Assume a 32bit DMA mask. */ 1419 ha->flags.enable_64bit_addressing = 0; 1420 1421 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1422 /* Any upper-dword bits set? */ 1423 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1424 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1425 /* Ok, a 64bit DMA mask is applicable. */ 1426 ha->flags.enable_64bit_addressing = 1; 1427 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1428 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1429 return; 1430 } 1431 } 1432 1433 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1434 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1435 } 1436 1437 static void 1438 qla2x00_enable_intrs(struct qla_hw_data *ha) 1439 { 1440 unsigned long flags = 0; 1441 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1442 1443 spin_lock_irqsave(&ha->hardware_lock, flags); 1444 ha->interrupts_on = 1; 1445 /* enable risc and host interrupts */ 1446 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1447 RD_REG_WORD(®->ictrl); 1448 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1449 1450 } 1451 1452 static void 1453 qla2x00_disable_intrs(struct qla_hw_data *ha) 1454 { 1455 unsigned long flags = 0; 1456 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1457 1458 spin_lock_irqsave(&ha->hardware_lock, flags); 1459 ha->interrupts_on = 0; 1460 /* disable risc and host interrupts */ 1461 WRT_REG_WORD(®->ictrl, 0); 1462 RD_REG_WORD(®->ictrl); 1463 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1464 } 1465 1466 static void 1467 qla24xx_enable_intrs(struct qla_hw_data *ha) 1468 { 1469 unsigned long flags = 0; 1470 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1471 1472 spin_lock_irqsave(&ha->hardware_lock, flags); 1473 ha->interrupts_on = 1; 1474 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1475 RD_REG_DWORD(®->ictrl); 1476 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1477 } 1478 1479 static void 1480 qla24xx_disable_intrs(struct qla_hw_data *ha) 1481 { 1482 unsigned long flags = 0; 1483 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1484 1485 if (IS_NOPOLLING_TYPE(ha)) 1486 return; 1487 spin_lock_irqsave(&ha->hardware_lock, flags); 1488 ha->interrupts_on = 0; 1489 WRT_REG_DWORD(®->ictrl, 0); 1490 RD_REG_DWORD(®->ictrl); 1491 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1492 } 1493 1494 static int 1495 qla2x00_iospace_config(struct qla_hw_data *ha) 1496 { 1497 resource_size_t pio; 1498 uint16_t msix; 1499 int cpus; 1500 1501 if (pci_request_selected_regions(ha->pdev, ha->bars, 1502 QLA2XXX_DRIVER_NAME)) { 1503 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1504 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1505 pci_name(ha->pdev)); 1506 goto iospace_error_exit; 1507 } 1508 if (!(ha->bars & 1)) 1509 goto skip_pio; 1510 1511 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1512 pio = pci_resource_start(ha->pdev, 0); 1513 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1514 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1515 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1516 "Invalid pci I/O region size (%s).\n", 1517 pci_name(ha->pdev)); 1518 pio = 0; 1519 } 1520 } else { 1521 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1522 "Region #0 no a PIO resource (%s).\n", 1523 pci_name(ha->pdev)); 1524 pio = 0; 1525 } 1526 ha->pio_address = pio; 1527 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1528 "PIO address=%llu.\n", 1529 (unsigned long long)ha->pio_address); 1530 1531 skip_pio: 1532 /* Use MMIO operations for all accesses. */ 1533 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1534 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1535 "Region #1 not an MMIO resource (%s), aborting.\n", 1536 pci_name(ha->pdev)); 1537 goto iospace_error_exit; 1538 } 1539 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1540 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1541 "Invalid PCI mem region size (%s), aborting.\n", 1542 pci_name(ha->pdev)); 1543 goto iospace_error_exit; 1544 } 1545 1546 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1547 if (!ha->iobase) { 1548 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1549 "Cannot remap MMIO (%s), aborting.\n", 1550 pci_name(ha->pdev)); 1551 goto iospace_error_exit; 1552 } 1553 1554 /* Determine queue resources */ 1555 ha->max_req_queues = ha->max_rsp_queues = 1; 1556 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1557 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1558 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1559 goto mqiobase_exit; 1560 1561 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1562 pci_resource_len(ha->pdev, 3)); 1563 if (ha->mqiobase) { 1564 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1565 "MQIO Base=%p.\n", ha->mqiobase); 1566 /* Read MSIX vector size of the board */ 1567 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1568 ha->msix_count = msix; 1569 /* Max queues are bounded by available msix vectors */ 1570 /* queue 0 uses two msix vectors */ 1571 if (ql2xmultique_tag) { 1572 cpus = num_online_cpus(); 1573 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1574 (cpus + 1) : (ha->msix_count - 1); 1575 ha->max_req_queues = 2; 1576 } else if (ql2xmaxqueues > 1) { 1577 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1578 QLA_MQ_SIZE : ql2xmaxqueues; 1579 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1580 "QoS mode set, max no of request queues:%d.\n", 1581 ha->max_req_queues); 1582 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1583 "QoS mode set, max no of request queues:%d.\n", 1584 ha->max_req_queues); 1585 } 1586 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1587 "MSI-X vector count: %d.\n", msix); 1588 } else 1589 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1590 "BAR 3 not enabled.\n"); 1591 1592 mqiobase_exit: 1593 ha->msix_count = ha->max_rsp_queues + 1; 1594 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1595 "MSIX Count:%d.\n", ha->msix_count); 1596 return (0); 1597 1598 iospace_error_exit: 1599 return (-ENOMEM); 1600 } 1601 1602 1603 static int 1604 qla83xx_iospace_config(struct qla_hw_data *ha) 1605 { 1606 uint16_t msix; 1607 int cpus; 1608 1609 if (pci_request_selected_regions(ha->pdev, ha->bars, 1610 QLA2XXX_DRIVER_NAME)) { 1611 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1612 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1613 pci_name(ha->pdev)); 1614 1615 goto iospace_error_exit; 1616 } 1617 1618 /* Use MMIO operations for all accesses. */ 1619 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1620 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1621 "Invalid pci I/O region size (%s).\n", 1622 pci_name(ha->pdev)); 1623 goto iospace_error_exit; 1624 } 1625 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1626 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1627 "Invalid PCI mem region size (%s), aborting\n", 1628 pci_name(ha->pdev)); 1629 goto iospace_error_exit; 1630 } 1631 1632 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1633 if (!ha->iobase) { 1634 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1635 "Cannot remap MMIO (%s), aborting.\n", 1636 pci_name(ha->pdev)); 1637 goto iospace_error_exit; 1638 } 1639 1640 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1641 /* 83XX 26XX always use MQ type access for queues 1642 * - mbar 2, a.k.a region 4 */ 1643 ha->max_req_queues = ha->max_rsp_queues = 1; 1644 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1645 pci_resource_len(ha->pdev, 4)); 1646 1647 if (!ha->mqiobase) { 1648 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1649 "BAR2/region4 not enabled\n"); 1650 goto mqiobase_exit; 1651 } 1652 1653 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1654 pci_resource_len(ha->pdev, 2)); 1655 if (ha->msixbase) { 1656 /* Read MSIX vector size of the board */ 1657 pci_read_config_word(ha->pdev, 1658 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1659 ha->msix_count = msix; 1660 /* Max queues are bounded by available msix vectors */ 1661 /* queue 0 uses two msix vectors */ 1662 if (ql2xmultique_tag) { 1663 cpus = num_online_cpus(); 1664 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1665 (cpus + 1) : (ha->msix_count - 1); 1666 ha->max_req_queues = 2; 1667 } else if (ql2xmaxqueues > 1) { 1668 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1669 QLA_MQ_SIZE : ql2xmaxqueues; 1670 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1671 "QoS mode set, max no of request queues:%d.\n", 1672 ha->max_req_queues); 1673 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1674 "QoS mode set, max no of request queues:%d.\n", 1675 ha->max_req_queues); 1676 } 1677 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1678 "MSI-X vector count: %d.\n", msix); 1679 } else 1680 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1681 "BAR 1 not enabled.\n"); 1682 1683 mqiobase_exit: 1684 ha->msix_count = ha->max_rsp_queues + 1; 1685 1686 qlt_83xx_iospace_config(ha); 1687 1688 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1689 "MSIX Count:%d.\n", ha->msix_count); 1690 return 0; 1691 1692 iospace_error_exit: 1693 return -ENOMEM; 1694 } 1695 1696 static struct isp_operations qla2100_isp_ops = { 1697 .pci_config = qla2100_pci_config, 1698 .reset_chip = qla2x00_reset_chip, 1699 .chip_diag = qla2x00_chip_diag, 1700 .config_rings = qla2x00_config_rings, 1701 .reset_adapter = qla2x00_reset_adapter, 1702 .nvram_config = qla2x00_nvram_config, 1703 .update_fw_options = qla2x00_update_fw_options, 1704 .load_risc = qla2x00_load_risc, 1705 .pci_info_str = qla2x00_pci_info_str, 1706 .fw_version_str = qla2x00_fw_version_str, 1707 .intr_handler = qla2100_intr_handler, 1708 .enable_intrs = qla2x00_enable_intrs, 1709 .disable_intrs = qla2x00_disable_intrs, 1710 .abort_command = qla2x00_abort_command, 1711 .target_reset = qla2x00_abort_target, 1712 .lun_reset = qla2x00_lun_reset, 1713 .fabric_login = qla2x00_login_fabric, 1714 .fabric_logout = qla2x00_fabric_logout, 1715 .calc_req_entries = qla2x00_calc_iocbs_32, 1716 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1717 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1718 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1719 .read_nvram = qla2x00_read_nvram_data, 1720 .write_nvram = qla2x00_write_nvram_data, 1721 .fw_dump = qla2100_fw_dump, 1722 .beacon_on = NULL, 1723 .beacon_off = NULL, 1724 .beacon_blink = NULL, 1725 .read_optrom = qla2x00_read_optrom_data, 1726 .write_optrom = qla2x00_write_optrom_data, 1727 .get_flash_version = qla2x00_get_flash_version, 1728 .start_scsi = qla2x00_start_scsi, 1729 .abort_isp = qla2x00_abort_isp, 1730 .iospace_config = qla2x00_iospace_config, 1731 .initialize_adapter = qla2x00_initialize_adapter, 1732 }; 1733 1734 static struct isp_operations qla2300_isp_ops = { 1735 .pci_config = qla2300_pci_config, 1736 .reset_chip = qla2x00_reset_chip, 1737 .chip_diag = qla2x00_chip_diag, 1738 .config_rings = qla2x00_config_rings, 1739 .reset_adapter = qla2x00_reset_adapter, 1740 .nvram_config = qla2x00_nvram_config, 1741 .update_fw_options = qla2x00_update_fw_options, 1742 .load_risc = qla2x00_load_risc, 1743 .pci_info_str = qla2x00_pci_info_str, 1744 .fw_version_str = qla2x00_fw_version_str, 1745 .intr_handler = qla2300_intr_handler, 1746 .enable_intrs = qla2x00_enable_intrs, 1747 .disable_intrs = qla2x00_disable_intrs, 1748 .abort_command = qla2x00_abort_command, 1749 .target_reset = qla2x00_abort_target, 1750 .lun_reset = qla2x00_lun_reset, 1751 .fabric_login = qla2x00_login_fabric, 1752 .fabric_logout = qla2x00_fabric_logout, 1753 .calc_req_entries = qla2x00_calc_iocbs_32, 1754 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1755 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1756 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1757 .read_nvram = qla2x00_read_nvram_data, 1758 .write_nvram = qla2x00_write_nvram_data, 1759 .fw_dump = qla2300_fw_dump, 1760 .beacon_on = qla2x00_beacon_on, 1761 .beacon_off = qla2x00_beacon_off, 1762 .beacon_blink = qla2x00_beacon_blink, 1763 .read_optrom = qla2x00_read_optrom_data, 1764 .write_optrom = qla2x00_write_optrom_data, 1765 .get_flash_version = qla2x00_get_flash_version, 1766 .start_scsi = qla2x00_start_scsi, 1767 .abort_isp = qla2x00_abort_isp, 1768 .iospace_config = qla2x00_iospace_config, 1769 .initialize_adapter = qla2x00_initialize_adapter, 1770 }; 1771 1772 static struct isp_operations qla24xx_isp_ops = { 1773 .pci_config = qla24xx_pci_config, 1774 .reset_chip = qla24xx_reset_chip, 1775 .chip_diag = qla24xx_chip_diag, 1776 .config_rings = qla24xx_config_rings, 1777 .reset_adapter = qla24xx_reset_adapter, 1778 .nvram_config = qla24xx_nvram_config, 1779 .update_fw_options = qla24xx_update_fw_options, 1780 .load_risc = qla24xx_load_risc, 1781 .pci_info_str = qla24xx_pci_info_str, 1782 .fw_version_str = qla24xx_fw_version_str, 1783 .intr_handler = qla24xx_intr_handler, 1784 .enable_intrs = qla24xx_enable_intrs, 1785 .disable_intrs = qla24xx_disable_intrs, 1786 .abort_command = qla24xx_abort_command, 1787 .target_reset = qla24xx_abort_target, 1788 .lun_reset = qla24xx_lun_reset, 1789 .fabric_login = qla24xx_login_fabric, 1790 .fabric_logout = qla24xx_fabric_logout, 1791 .calc_req_entries = NULL, 1792 .build_iocbs = NULL, 1793 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1794 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1795 .read_nvram = qla24xx_read_nvram_data, 1796 .write_nvram = qla24xx_write_nvram_data, 1797 .fw_dump = qla24xx_fw_dump, 1798 .beacon_on = qla24xx_beacon_on, 1799 .beacon_off = qla24xx_beacon_off, 1800 .beacon_blink = qla24xx_beacon_blink, 1801 .read_optrom = qla24xx_read_optrom_data, 1802 .write_optrom = qla24xx_write_optrom_data, 1803 .get_flash_version = qla24xx_get_flash_version, 1804 .start_scsi = qla24xx_start_scsi, 1805 .abort_isp = qla2x00_abort_isp, 1806 .iospace_config = qla2x00_iospace_config, 1807 .initialize_adapter = qla2x00_initialize_adapter, 1808 }; 1809 1810 static struct isp_operations qla25xx_isp_ops = { 1811 .pci_config = qla25xx_pci_config, 1812 .reset_chip = qla24xx_reset_chip, 1813 .chip_diag = qla24xx_chip_diag, 1814 .config_rings = qla24xx_config_rings, 1815 .reset_adapter = qla24xx_reset_adapter, 1816 .nvram_config = qla24xx_nvram_config, 1817 .update_fw_options = qla24xx_update_fw_options, 1818 .load_risc = qla24xx_load_risc, 1819 .pci_info_str = qla24xx_pci_info_str, 1820 .fw_version_str = qla24xx_fw_version_str, 1821 .intr_handler = qla24xx_intr_handler, 1822 .enable_intrs = qla24xx_enable_intrs, 1823 .disable_intrs = qla24xx_disable_intrs, 1824 .abort_command = qla24xx_abort_command, 1825 .target_reset = qla24xx_abort_target, 1826 .lun_reset = qla24xx_lun_reset, 1827 .fabric_login = qla24xx_login_fabric, 1828 .fabric_logout = qla24xx_fabric_logout, 1829 .calc_req_entries = NULL, 1830 .build_iocbs = NULL, 1831 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1832 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1833 .read_nvram = qla25xx_read_nvram_data, 1834 .write_nvram = qla25xx_write_nvram_data, 1835 .fw_dump = qla25xx_fw_dump, 1836 .beacon_on = qla24xx_beacon_on, 1837 .beacon_off = qla24xx_beacon_off, 1838 .beacon_blink = qla24xx_beacon_blink, 1839 .read_optrom = qla25xx_read_optrom_data, 1840 .write_optrom = qla24xx_write_optrom_data, 1841 .get_flash_version = qla24xx_get_flash_version, 1842 .start_scsi = qla24xx_dif_start_scsi, 1843 .abort_isp = qla2x00_abort_isp, 1844 .iospace_config = qla2x00_iospace_config, 1845 .initialize_adapter = qla2x00_initialize_adapter, 1846 }; 1847 1848 static struct isp_operations qla81xx_isp_ops = { 1849 .pci_config = qla25xx_pci_config, 1850 .reset_chip = qla24xx_reset_chip, 1851 .chip_diag = qla24xx_chip_diag, 1852 .config_rings = qla24xx_config_rings, 1853 .reset_adapter = qla24xx_reset_adapter, 1854 .nvram_config = qla81xx_nvram_config, 1855 .update_fw_options = qla81xx_update_fw_options, 1856 .load_risc = qla81xx_load_risc, 1857 .pci_info_str = qla24xx_pci_info_str, 1858 .fw_version_str = qla24xx_fw_version_str, 1859 .intr_handler = qla24xx_intr_handler, 1860 .enable_intrs = qla24xx_enable_intrs, 1861 .disable_intrs = qla24xx_disable_intrs, 1862 .abort_command = qla24xx_abort_command, 1863 .target_reset = qla24xx_abort_target, 1864 .lun_reset = qla24xx_lun_reset, 1865 .fabric_login = qla24xx_login_fabric, 1866 .fabric_logout = qla24xx_fabric_logout, 1867 .calc_req_entries = NULL, 1868 .build_iocbs = NULL, 1869 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1870 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1871 .read_nvram = NULL, 1872 .write_nvram = NULL, 1873 .fw_dump = qla81xx_fw_dump, 1874 .beacon_on = qla24xx_beacon_on, 1875 .beacon_off = qla24xx_beacon_off, 1876 .beacon_blink = qla83xx_beacon_blink, 1877 .read_optrom = qla25xx_read_optrom_data, 1878 .write_optrom = qla24xx_write_optrom_data, 1879 .get_flash_version = qla24xx_get_flash_version, 1880 .start_scsi = qla24xx_dif_start_scsi, 1881 .abort_isp = qla2x00_abort_isp, 1882 .iospace_config = qla2x00_iospace_config, 1883 .initialize_adapter = qla2x00_initialize_adapter, 1884 }; 1885 1886 static struct isp_operations qla82xx_isp_ops = { 1887 .pci_config = qla82xx_pci_config, 1888 .reset_chip = qla82xx_reset_chip, 1889 .chip_diag = qla24xx_chip_diag, 1890 .config_rings = qla82xx_config_rings, 1891 .reset_adapter = qla24xx_reset_adapter, 1892 .nvram_config = qla81xx_nvram_config, 1893 .update_fw_options = qla24xx_update_fw_options, 1894 .load_risc = qla82xx_load_risc, 1895 .pci_info_str = qla24xx_pci_info_str, 1896 .fw_version_str = qla24xx_fw_version_str, 1897 .intr_handler = qla82xx_intr_handler, 1898 .enable_intrs = qla82xx_enable_intrs, 1899 .disable_intrs = qla82xx_disable_intrs, 1900 .abort_command = qla24xx_abort_command, 1901 .target_reset = qla24xx_abort_target, 1902 .lun_reset = qla24xx_lun_reset, 1903 .fabric_login = qla24xx_login_fabric, 1904 .fabric_logout = qla24xx_fabric_logout, 1905 .calc_req_entries = NULL, 1906 .build_iocbs = NULL, 1907 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1908 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1909 .read_nvram = qla24xx_read_nvram_data, 1910 .write_nvram = qla24xx_write_nvram_data, 1911 .fw_dump = qla82xx_fw_dump, 1912 .beacon_on = qla82xx_beacon_on, 1913 .beacon_off = qla82xx_beacon_off, 1914 .beacon_blink = NULL, 1915 .read_optrom = qla82xx_read_optrom_data, 1916 .write_optrom = qla82xx_write_optrom_data, 1917 .get_flash_version = qla82xx_get_flash_version, 1918 .start_scsi = qla82xx_start_scsi, 1919 .abort_isp = qla82xx_abort_isp, 1920 .iospace_config = qla82xx_iospace_config, 1921 .initialize_adapter = qla2x00_initialize_adapter, 1922 }; 1923 1924 static struct isp_operations qla8044_isp_ops = { 1925 .pci_config = qla82xx_pci_config, 1926 .reset_chip = qla82xx_reset_chip, 1927 .chip_diag = qla24xx_chip_diag, 1928 .config_rings = qla82xx_config_rings, 1929 .reset_adapter = qla24xx_reset_adapter, 1930 .nvram_config = qla81xx_nvram_config, 1931 .update_fw_options = qla24xx_update_fw_options, 1932 .load_risc = qla82xx_load_risc, 1933 .pci_info_str = qla24xx_pci_info_str, 1934 .fw_version_str = qla24xx_fw_version_str, 1935 .intr_handler = qla8044_intr_handler, 1936 .enable_intrs = qla82xx_enable_intrs, 1937 .disable_intrs = qla82xx_disable_intrs, 1938 .abort_command = qla24xx_abort_command, 1939 .target_reset = qla24xx_abort_target, 1940 .lun_reset = qla24xx_lun_reset, 1941 .fabric_login = qla24xx_login_fabric, 1942 .fabric_logout = qla24xx_fabric_logout, 1943 .calc_req_entries = NULL, 1944 .build_iocbs = NULL, 1945 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1946 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1947 .read_nvram = NULL, 1948 .write_nvram = NULL, 1949 .fw_dump = qla8044_fw_dump, 1950 .beacon_on = qla82xx_beacon_on, 1951 .beacon_off = qla82xx_beacon_off, 1952 .beacon_blink = NULL, 1953 .read_optrom = qla8044_read_optrom_data, 1954 .write_optrom = qla8044_write_optrom_data, 1955 .get_flash_version = qla82xx_get_flash_version, 1956 .start_scsi = qla82xx_start_scsi, 1957 .abort_isp = qla8044_abort_isp, 1958 .iospace_config = qla82xx_iospace_config, 1959 .initialize_adapter = qla2x00_initialize_adapter, 1960 }; 1961 1962 static struct isp_operations qla83xx_isp_ops = { 1963 .pci_config = qla25xx_pci_config, 1964 .reset_chip = qla24xx_reset_chip, 1965 .chip_diag = qla24xx_chip_diag, 1966 .config_rings = qla24xx_config_rings, 1967 .reset_adapter = qla24xx_reset_adapter, 1968 .nvram_config = qla81xx_nvram_config, 1969 .update_fw_options = qla81xx_update_fw_options, 1970 .load_risc = qla81xx_load_risc, 1971 .pci_info_str = qla24xx_pci_info_str, 1972 .fw_version_str = qla24xx_fw_version_str, 1973 .intr_handler = qla24xx_intr_handler, 1974 .enable_intrs = qla24xx_enable_intrs, 1975 .disable_intrs = qla24xx_disable_intrs, 1976 .abort_command = qla24xx_abort_command, 1977 .target_reset = qla24xx_abort_target, 1978 .lun_reset = qla24xx_lun_reset, 1979 .fabric_login = qla24xx_login_fabric, 1980 .fabric_logout = qla24xx_fabric_logout, 1981 .calc_req_entries = NULL, 1982 .build_iocbs = NULL, 1983 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1984 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1985 .read_nvram = NULL, 1986 .write_nvram = NULL, 1987 .fw_dump = qla83xx_fw_dump, 1988 .beacon_on = qla24xx_beacon_on, 1989 .beacon_off = qla24xx_beacon_off, 1990 .beacon_blink = qla83xx_beacon_blink, 1991 .read_optrom = qla25xx_read_optrom_data, 1992 .write_optrom = qla24xx_write_optrom_data, 1993 .get_flash_version = qla24xx_get_flash_version, 1994 .start_scsi = qla24xx_dif_start_scsi, 1995 .abort_isp = qla2x00_abort_isp, 1996 .iospace_config = qla83xx_iospace_config, 1997 .initialize_adapter = qla2x00_initialize_adapter, 1998 }; 1999 2000 static struct isp_operations qlafx00_isp_ops = { 2001 .pci_config = qlafx00_pci_config, 2002 .reset_chip = qlafx00_soft_reset, 2003 .chip_diag = qlafx00_chip_diag, 2004 .config_rings = qlafx00_config_rings, 2005 .reset_adapter = qlafx00_soft_reset, 2006 .nvram_config = NULL, 2007 .update_fw_options = NULL, 2008 .load_risc = NULL, 2009 .pci_info_str = qlafx00_pci_info_str, 2010 .fw_version_str = qlafx00_fw_version_str, 2011 .intr_handler = qlafx00_intr_handler, 2012 .enable_intrs = qlafx00_enable_intrs, 2013 .disable_intrs = qlafx00_disable_intrs, 2014 .abort_command = qla24xx_async_abort_command, 2015 .target_reset = qlafx00_abort_target, 2016 .lun_reset = qlafx00_lun_reset, 2017 .fabric_login = NULL, 2018 .fabric_logout = NULL, 2019 .calc_req_entries = NULL, 2020 .build_iocbs = NULL, 2021 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2022 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2023 .read_nvram = qla24xx_read_nvram_data, 2024 .write_nvram = qla24xx_write_nvram_data, 2025 .fw_dump = NULL, 2026 .beacon_on = qla24xx_beacon_on, 2027 .beacon_off = qla24xx_beacon_off, 2028 .beacon_blink = NULL, 2029 .read_optrom = qla24xx_read_optrom_data, 2030 .write_optrom = qla24xx_write_optrom_data, 2031 .get_flash_version = qla24xx_get_flash_version, 2032 .start_scsi = qlafx00_start_scsi, 2033 .abort_isp = qlafx00_abort_isp, 2034 .iospace_config = qlafx00_iospace_config, 2035 .initialize_adapter = qlafx00_initialize_adapter, 2036 }; 2037 2038 static struct isp_operations qla27xx_isp_ops = { 2039 .pci_config = qla25xx_pci_config, 2040 .reset_chip = qla24xx_reset_chip, 2041 .chip_diag = qla24xx_chip_diag, 2042 .config_rings = qla24xx_config_rings, 2043 .reset_adapter = qla24xx_reset_adapter, 2044 .nvram_config = qla81xx_nvram_config, 2045 .update_fw_options = qla81xx_update_fw_options, 2046 .load_risc = qla81xx_load_risc, 2047 .pci_info_str = qla24xx_pci_info_str, 2048 .fw_version_str = qla24xx_fw_version_str, 2049 .intr_handler = qla24xx_intr_handler, 2050 .enable_intrs = qla24xx_enable_intrs, 2051 .disable_intrs = qla24xx_disable_intrs, 2052 .abort_command = qla24xx_abort_command, 2053 .target_reset = qla24xx_abort_target, 2054 .lun_reset = qla24xx_lun_reset, 2055 .fabric_login = qla24xx_login_fabric, 2056 .fabric_logout = qla24xx_fabric_logout, 2057 .calc_req_entries = NULL, 2058 .build_iocbs = NULL, 2059 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2060 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2061 .read_nvram = NULL, 2062 .write_nvram = NULL, 2063 .fw_dump = qla27xx_fwdump, 2064 .beacon_on = qla24xx_beacon_on, 2065 .beacon_off = qla24xx_beacon_off, 2066 .beacon_blink = qla83xx_beacon_blink, 2067 .read_optrom = qla25xx_read_optrom_data, 2068 .write_optrom = qla24xx_write_optrom_data, 2069 .get_flash_version = qla24xx_get_flash_version, 2070 .start_scsi = qla24xx_dif_start_scsi, 2071 .abort_isp = qla2x00_abort_isp, 2072 .iospace_config = qla83xx_iospace_config, 2073 .initialize_adapter = qla2x00_initialize_adapter, 2074 }; 2075 2076 static inline void 2077 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2078 { 2079 ha->device_type = DT_EXTENDED_IDS; 2080 switch (ha->pdev->device) { 2081 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2082 ha->device_type |= DT_ISP2100; 2083 ha->device_type &= ~DT_EXTENDED_IDS; 2084 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2085 break; 2086 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2087 ha->device_type |= DT_ISP2200; 2088 ha->device_type &= ~DT_EXTENDED_IDS; 2089 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2090 break; 2091 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2092 ha->device_type |= DT_ISP2300; 2093 ha->device_type |= DT_ZIO_SUPPORTED; 2094 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2095 break; 2096 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2097 ha->device_type |= DT_ISP2312; 2098 ha->device_type |= DT_ZIO_SUPPORTED; 2099 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2100 break; 2101 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2102 ha->device_type |= DT_ISP2322; 2103 ha->device_type |= DT_ZIO_SUPPORTED; 2104 if (ha->pdev->subsystem_vendor == 0x1028 && 2105 ha->pdev->subsystem_device == 0x0170) 2106 ha->device_type |= DT_OEM_001; 2107 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2108 break; 2109 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2110 ha->device_type |= DT_ISP6312; 2111 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2112 break; 2113 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2114 ha->device_type |= DT_ISP6322; 2115 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2116 break; 2117 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2118 ha->device_type |= DT_ISP2422; 2119 ha->device_type |= DT_ZIO_SUPPORTED; 2120 ha->device_type |= DT_FWI2; 2121 ha->device_type |= DT_IIDMA; 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2123 break; 2124 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2125 ha->device_type |= DT_ISP2432; 2126 ha->device_type |= DT_ZIO_SUPPORTED; 2127 ha->device_type |= DT_FWI2; 2128 ha->device_type |= DT_IIDMA; 2129 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2130 break; 2131 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2132 ha->device_type |= DT_ISP8432; 2133 ha->device_type |= DT_ZIO_SUPPORTED; 2134 ha->device_type |= DT_FWI2; 2135 ha->device_type |= DT_IIDMA; 2136 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2137 break; 2138 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2139 ha->device_type |= DT_ISP5422; 2140 ha->device_type |= DT_FWI2; 2141 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2142 break; 2143 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2144 ha->device_type |= DT_ISP5432; 2145 ha->device_type |= DT_FWI2; 2146 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2147 break; 2148 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2149 ha->device_type |= DT_ISP2532; 2150 ha->device_type |= DT_ZIO_SUPPORTED; 2151 ha->device_type |= DT_FWI2; 2152 ha->device_type |= DT_IIDMA; 2153 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2154 break; 2155 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2156 ha->device_type |= DT_ISP8001; 2157 ha->device_type |= DT_ZIO_SUPPORTED; 2158 ha->device_type |= DT_FWI2; 2159 ha->device_type |= DT_IIDMA; 2160 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2161 break; 2162 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2163 ha->device_type |= DT_ISP8021; 2164 ha->device_type |= DT_ZIO_SUPPORTED; 2165 ha->device_type |= DT_FWI2; 2166 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2167 /* Initialize 82XX ISP flags */ 2168 qla82xx_init_flags(ha); 2169 break; 2170 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2171 ha->device_type |= DT_ISP8044; 2172 ha->device_type |= DT_ZIO_SUPPORTED; 2173 ha->device_type |= DT_FWI2; 2174 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2175 /* Initialize 82XX ISP flags */ 2176 qla82xx_init_flags(ha); 2177 break; 2178 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2179 ha->device_type |= DT_ISP2031; 2180 ha->device_type |= DT_ZIO_SUPPORTED; 2181 ha->device_type |= DT_FWI2; 2182 ha->device_type |= DT_IIDMA; 2183 ha->device_type |= DT_T10_PI; 2184 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2185 break; 2186 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2187 ha->device_type |= DT_ISP8031; 2188 ha->device_type |= DT_ZIO_SUPPORTED; 2189 ha->device_type |= DT_FWI2; 2190 ha->device_type |= DT_IIDMA; 2191 ha->device_type |= DT_T10_PI; 2192 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2193 break; 2194 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2195 ha->device_type |= DT_ISPFX00; 2196 break; 2197 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2198 ha->device_type |= DT_ISP2071; 2199 ha->device_type |= DT_ZIO_SUPPORTED; 2200 ha->device_type |= DT_FWI2; 2201 ha->device_type |= DT_IIDMA; 2202 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2203 break; 2204 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2205 ha->device_type |= DT_ISP2271; 2206 ha->device_type |= DT_ZIO_SUPPORTED; 2207 ha->device_type |= DT_FWI2; 2208 ha->device_type |= DT_IIDMA; 2209 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2210 break; 2211 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2212 ha->device_type |= DT_ISP2261; 2213 ha->device_type |= DT_ZIO_SUPPORTED; 2214 ha->device_type |= DT_FWI2; 2215 ha->device_type |= DT_IIDMA; 2216 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2217 break; 2218 } 2219 2220 if (IS_QLA82XX(ha)) 2221 ha->port_no = ha->portnum & 1; 2222 else { 2223 /* Get adapter physical port no from interrupt pin register. */ 2224 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2225 if (IS_QLA27XX(ha)) 2226 ha->port_no--; 2227 else 2228 ha->port_no = !(ha->port_no & 1); 2229 } 2230 2231 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2232 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2233 ha->device_type, ha->port_no, ha->fw_srisc_address); 2234 } 2235 2236 static void 2237 qla2xxx_scan_start(struct Scsi_Host *shost) 2238 { 2239 scsi_qla_host_t *vha = shost_priv(shost); 2240 2241 if (vha->hw->flags.running_gold_fw) 2242 return; 2243 2244 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2245 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2246 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2247 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2248 } 2249 2250 static int 2251 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2252 { 2253 scsi_qla_host_t *vha = shost_priv(shost); 2254 2255 if (!vha->host) 2256 return 1; 2257 if (time > vha->hw->loop_reset_delay * HZ) 2258 return 1; 2259 2260 return atomic_read(&vha->loop_state) == LOOP_READY; 2261 } 2262 2263 /* 2264 * PCI driver interface 2265 */ 2266 static int 2267 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2268 { 2269 int ret = -ENODEV; 2270 struct Scsi_Host *host; 2271 scsi_qla_host_t *base_vha = NULL; 2272 struct qla_hw_data *ha; 2273 char pci_info[30]; 2274 char fw_str[30], wq_name[30]; 2275 struct scsi_host_template *sht; 2276 int bars, mem_only = 0; 2277 uint16_t req_length = 0, rsp_length = 0; 2278 struct req_que *req = NULL; 2279 struct rsp_que *rsp = NULL; 2280 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2281 sht = &qla2xxx_driver_template; 2282 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2283 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2284 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2285 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2286 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2297 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2298 mem_only = 1; 2299 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2300 "Mem only adapter.\n"); 2301 } 2302 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2303 "Bars=%d.\n", bars); 2304 2305 if (mem_only) { 2306 if (pci_enable_device_mem(pdev)) 2307 goto probe_out; 2308 } else { 2309 if (pci_enable_device(pdev)) 2310 goto probe_out; 2311 } 2312 2313 /* This may fail but that's ok */ 2314 pci_enable_pcie_error_reporting(pdev); 2315 2316 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2317 if (!ha) { 2318 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2319 "Unable to allocate memory for ha.\n"); 2320 goto probe_out; 2321 } 2322 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2323 "Memory allocated for ha=%p.\n", ha); 2324 ha->pdev = pdev; 2325 ha->tgt.enable_class_2 = ql2xenableclass2; 2326 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2327 spin_lock_init(&ha->tgt.q_full_lock); 2328 2329 /* Clear our data area */ 2330 ha->bars = bars; 2331 ha->mem_only = mem_only; 2332 spin_lock_init(&ha->hardware_lock); 2333 spin_lock_init(&ha->vport_slock); 2334 mutex_init(&ha->selflogin_lock); 2335 mutex_init(&ha->optrom_mutex); 2336 2337 /* Set ISP-type information. */ 2338 qla2x00_set_isp_flags(ha); 2339 2340 /* Set EEH reset type to fundamental if required by hba */ 2341 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2342 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2343 pdev->needs_freset = 1; 2344 2345 ha->prev_topology = 0; 2346 ha->init_cb_size = sizeof(init_cb_t); 2347 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2348 ha->optrom_size = OPTROM_SIZE_2300; 2349 2350 /* Assign ISP specific operations. */ 2351 if (IS_QLA2100(ha)) { 2352 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2353 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2354 req_length = REQUEST_ENTRY_CNT_2100; 2355 rsp_length = RESPONSE_ENTRY_CNT_2100; 2356 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2357 ha->gid_list_info_size = 4; 2358 ha->flash_conf_off = ~0; 2359 ha->flash_data_off = ~0; 2360 ha->nvram_conf_off = ~0; 2361 ha->nvram_data_off = ~0; 2362 ha->isp_ops = &qla2100_isp_ops; 2363 } else if (IS_QLA2200(ha)) { 2364 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2365 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2366 req_length = REQUEST_ENTRY_CNT_2200; 2367 rsp_length = RESPONSE_ENTRY_CNT_2100; 2368 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2369 ha->gid_list_info_size = 4; 2370 ha->flash_conf_off = ~0; 2371 ha->flash_data_off = ~0; 2372 ha->nvram_conf_off = ~0; 2373 ha->nvram_data_off = ~0; 2374 ha->isp_ops = &qla2100_isp_ops; 2375 } else if (IS_QLA23XX(ha)) { 2376 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2377 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2378 req_length = REQUEST_ENTRY_CNT_2200; 2379 rsp_length = RESPONSE_ENTRY_CNT_2300; 2380 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2381 ha->gid_list_info_size = 6; 2382 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2383 ha->optrom_size = OPTROM_SIZE_2322; 2384 ha->flash_conf_off = ~0; 2385 ha->flash_data_off = ~0; 2386 ha->nvram_conf_off = ~0; 2387 ha->nvram_data_off = ~0; 2388 ha->isp_ops = &qla2300_isp_ops; 2389 } else if (IS_QLA24XX_TYPE(ha)) { 2390 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2391 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2392 req_length = REQUEST_ENTRY_CNT_24XX; 2393 rsp_length = RESPONSE_ENTRY_CNT_2300; 2394 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2395 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2396 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2397 ha->gid_list_info_size = 8; 2398 ha->optrom_size = OPTROM_SIZE_24XX; 2399 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2400 ha->isp_ops = &qla24xx_isp_ops; 2401 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2402 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2403 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2404 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2405 } else if (IS_QLA25XX(ha)) { 2406 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2407 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2408 req_length = REQUEST_ENTRY_CNT_24XX; 2409 rsp_length = RESPONSE_ENTRY_CNT_2300; 2410 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2411 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2412 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2413 ha->gid_list_info_size = 8; 2414 ha->optrom_size = OPTROM_SIZE_25XX; 2415 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2416 ha->isp_ops = &qla25xx_isp_ops; 2417 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2418 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2419 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2420 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2421 } else if (IS_QLA81XX(ha)) { 2422 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2423 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2424 req_length = REQUEST_ENTRY_CNT_24XX; 2425 rsp_length = RESPONSE_ENTRY_CNT_2300; 2426 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2427 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2428 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2429 ha->gid_list_info_size = 8; 2430 ha->optrom_size = OPTROM_SIZE_81XX; 2431 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2432 ha->isp_ops = &qla81xx_isp_ops; 2433 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2434 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2435 ha->nvram_conf_off = ~0; 2436 ha->nvram_data_off = ~0; 2437 } else if (IS_QLA82XX(ha)) { 2438 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2439 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2440 req_length = REQUEST_ENTRY_CNT_82XX; 2441 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2442 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2443 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2444 ha->gid_list_info_size = 8; 2445 ha->optrom_size = OPTROM_SIZE_82XX; 2446 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2447 ha->isp_ops = &qla82xx_isp_ops; 2448 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2449 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2450 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2451 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2452 } else if (IS_QLA8044(ha)) { 2453 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2454 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2455 req_length = REQUEST_ENTRY_CNT_82XX; 2456 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2457 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2458 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2459 ha->gid_list_info_size = 8; 2460 ha->optrom_size = OPTROM_SIZE_83XX; 2461 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2462 ha->isp_ops = &qla8044_isp_ops; 2463 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2464 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2465 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2466 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2467 } else if (IS_QLA83XX(ha)) { 2468 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2469 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2470 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2471 req_length = REQUEST_ENTRY_CNT_83XX; 2472 rsp_length = RESPONSE_ENTRY_CNT_2300; 2473 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2474 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2475 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2476 ha->gid_list_info_size = 8; 2477 ha->optrom_size = OPTROM_SIZE_83XX; 2478 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2479 ha->isp_ops = &qla83xx_isp_ops; 2480 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2481 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2482 ha->nvram_conf_off = ~0; 2483 ha->nvram_data_off = ~0; 2484 } else if (IS_QLAFX00(ha)) { 2485 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2486 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2487 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2488 req_length = REQUEST_ENTRY_CNT_FX00; 2489 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2490 ha->isp_ops = &qlafx00_isp_ops; 2491 ha->port_down_retry_count = 30; /* default value */ 2492 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2493 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2494 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2495 ha->mr.fw_hbt_en = 1; 2496 ha->mr.host_info_resend = false; 2497 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2498 } else if (IS_QLA27XX(ha)) { 2499 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2500 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2501 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2502 req_length = REQUEST_ENTRY_CNT_24XX; 2503 rsp_length = RESPONSE_ENTRY_CNT_2300; 2504 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2505 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2506 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2507 ha->gid_list_info_size = 8; 2508 ha->optrom_size = OPTROM_SIZE_83XX; 2509 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2510 ha->isp_ops = &qla27xx_isp_ops; 2511 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2512 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2513 ha->nvram_conf_off = ~0; 2514 ha->nvram_data_off = ~0; 2515 } 2516 2517 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2518 "mbx_count=%d, req_length=%d, " 2519 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2520 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2521 "max_fibre_devices=%d.\n", 2522 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2523 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2524 ha->nvram_npiv_size, ha->max_fibre_devices); 2525 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2526 "isp_ops=%p, flash_conf_off=%d, " 2527 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2528 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2529 ha->nvram_conf_off, ha->nvram_data_off); 2530 2531 /* Configure PCI I/O space */ 2532 ret = ha->isp_ops->iospace_config(ha); 2533 if (ret) 2534 goto iospace_config_failed; 2535 2536 ql_log_pci(ql_log_info, pdev, 0x001d, 2537 "Found an ISP%04X irq %d iobase 0x%p.\n", 2538 pdev->device, pdev->irq, ha->iobase); 2539 mutex_init(&ha->vport_lock); 2540 init_completion(&ha->mbx_cmd_comp); 2541 complete(&ha->mbx_cmd_comp); 2542 init_completion(&ha->mbx_intr_comp); 2543 init_completion(&ha->dcbx_comp); 2544 init_completion(&ha->lb_portup_comp); 2545 2546 set_bit(0, (unsigned long *) ha->vp_idx_map); 2547 2548 qla2x00_config_dma_addressing(ha); 2549 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2550 "64 Bit addressing is %s.\n", 2551 ha->flags.enable_64bit_addressing ? "enable" : 2552 "disable"); 2553 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2554 if (ret) { 2555 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2556 "Failed to allocate memory for adapter, aborting.\n"); 2557 2558 goto probe_hw_failed; 2559 } 2560 2561 req->max_q_depth = MAX_Q_DEPTH; 2562 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2563 req->max_q_depth = ql2xmaxqdepth; 2564 2565 2566 base_vha = qla2x00_create_host(sht, ha); 2567 if (!base_vha) { 2568 ret = -ENOMEM; 2569 qla2x00_mem_free(ha); 2570 qla2x00_free_req_que(ha, req); 2571 qla2x00_free_rsp_que(ha, rsp); 2572 goto probe_hw_failed; 2573 } 2574 2575 pci_set_drvdata(pdev, base_vha); 2576 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2577 2578 host = base_vha->host; 2579 base_vha->req = req; 2580 if (IS_QLA2XXX_MIDTYPE(ha)) 2581 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2582 else 2583 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2584 base_vha->vp_idx; 2585 2586 /* Setup fcport template structure. */ 2587 ha->mr.fcport.vha = base_vha; 2588 ha->mr.fcport.port_type = FCT_UNKNOWN; 2589 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2590 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2591 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2592 ha->mr.fcport.scan_state = 1; 2593 2594 /* Set the SG table size based on ISP type */ 2595 if (!IS_FWI2_CAPABLE(ha)) { 2596 if (IS_QLA2100(ha)) 2597 host->sg_tablesize = 32; 2598 } else { 2599 if (!IS_QLA82XX(ha)) 2600 host->sg_tablesize = QLA_SG_ALL; 2601 } 2602 host->max_id = ha->max_fibre_devices; 2603 host->cmd_per_lun = 3; 2604 host->unique_id = host->host_no; 2605 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2606 host->max_cmd_len = 32; 2607 else 2608 host->max_cmd_len = MAX_CMDSZ; 2609 host->max_channel = MAX_BUSES - 1; 2610 /* Older HBAs support only 16-bit LUNs */ 2611 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2612 ql2xmaxlun > 0xffff) 2613 host->max_lun = 0xffff; 2614 else 2615 host->max_lun = ql2xmaxlun; 2616 host->transportt = qla2xxx_transport_template; 2617 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2618 2619 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2620 "max_id=%d this_id=%d " 2621 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2622 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2623 host->this_id, host->cmd_per_lun, host->unique_id, 2624 host->max_cmd_len, host->max_channel, host->max_lun, 2625 host->transportt, sht->vendor_id); 2626 2627 que_init: 2628 /* Alloc arrays of request and response ring ptrs */ 2629 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2630 ql_log(ql_log_fatal, base_vha, 0x003d, 2631 "Failed to allocate memory for queue pointers..." 2632 "aborting.\n"); 2633 goto probe_init_failed; 2634 } 2635 2636 qlt_probe_one_stage1(base_vha, ha); 2637 2638 /* Set up the irqs */ 2639 ret = qla2x00_request_irqs(ha, rsp); 2640 if (ret) 2641 goto probe_init_failed; 2642 2643 pci_save_state(pdev); 2644 2645 /* Assign back pointers */ 2646 rsp->req = req; 2647 req->rsp = rsp; 2648 2649 if (IS_QLAFX00(ha)) { 2650 ha->rsp_q_map[0] = rsp; 2651 ha->req_q_map[0] = req; 2652 set_bit(0, ha->req_qid_map); 2653 set_bit(0, ha->rsp_qid_map); 2654 } 2655 2656 /* FWI2-capable only. */ 2657 req->req_q_in = &ha->iobase->isp24.req_q_in; 2658 req->req_q_out = &ha->iobase->isp24.req_q_out; 2659 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2660 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2661 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2662 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2663 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2664 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2665 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2666 } 2667 2668 if (IS_QLAFX00(ha)) { 2669 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2670 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2671 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2672 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2673 } 2674 2675 if (IS_P3P_TYPE(ha)) { 2676 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2677 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2678 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2679 } 2680 2681 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2682 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2683 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2684 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2685 "req->req_q_in=%p req->req_q_out=%p " 2686 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2687 req->req_q_in, req->req_q_out, 2688 rsp->rsp_q_in, rsp->rsp_q_out); 2689 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2690 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2691 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2692 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2693 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2694 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2695 2696 if (ha->isp_ops->initialize_adapter(base_vha)) { 2697 ql_log(ql_log_fatal, base_vha, 0x00d6, 2698 "Failed to initialize adapter - Adapter flags %x.\n", 2699 base_vha->device_flags); 2700 2701 if (IS_QLA82XX(ha)) { 2702 qla82xx_idc_lock(ha); 2703 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2704 QLA8XXX_DEV_FAILED); 2705 qla82xx_idc_unlock(ha); 2706 ql_log(ql_log_fatal, base_vha, 0x00d7, 2707 "HW State: FAILED.\n"); 2708 } else if (IS_QLA8044(ha)) { 2709 qla8044_idc_lock(ha); 2710 qla8044_wr_direct(base_vha, 2711 QLA8044_CRB_DEV_STATE_INDEX, 2712 QLA8XXX_DEV_FAILED); 2713 qla8044_idc_unlock(ha); 2714 ql_log(ql_log_fatal, base_vha, 0x0150, 2715 "HW State: FAILED.\n"); 2716 } 2717 2718 ret = -ENODEV; 2719 goto probe_failed; 2720 } 2721 2722 if (IS_QLAFX00(ha)) 2723 host->can_queue = QLAFX00_MAX_CANQUEUE; 2724 else 2725 host->can_queue = req->num_outstanding_cmds - 10; 2726 2727 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2728 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2729 host->can_queue, base_vha->req, 2730 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2731 2732 if (ha->mqenable) { 2733 if (qla25xx_setup_mode(base_vha)) { 2734 ql_log(ql_log_warn, base_vha, 0x00ec, 2735 "Failed to create queues, falling back to single queue mode.\n"); 2736 goto que_init; 2737 } 2738 } 2739 2740 if (ha->flags.running_gold_fw) 2741 goto skip_dpc; 2742 2743 /* 2744 * Startup the kernel thread for this host adapter 2745 */ 2746 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2747 "%s_dpc", base_vha->host_str); 2748 if (IS_ERR(ha->dpc_thread)) { 2749 ql_log(ql_log_fatal, base_vha, 0x00ed, 2750 "Failed to start DPC thread.\n"); 2751 ret = PTR_ERR(ha->dpc_thread); 2752 goto probe_failed; 2753 } 2754 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2755 "DPC thread started successfully.\n"); 2756 2757 /* 2758 * If we're not coming up in initiator mode, we might sit for 2759 * a while without waking up the dpc thread, which leads to a 2760 * stuck process warning. So just kick the dpc once here and 2761 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2762 */ 2763 qla2xxx_wake_dpc(base_vha); 2764 2765 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2766 2767 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2768 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2769 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2770 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2771 2772 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2773 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2774 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2775 INIT_WORK(&ha->idc_state_handler, 2776 qla83xx_idc_state_handler_work); 2777 INIT_WORK(&ha->nic_core_unrecoverable, 2778 qla83xx_nic_core_unrecoverable_work); 2779 } 2780 2781 skip_dpc: 2782 list_add_tail(&base_vha->list, &ha->vp_list); 2783 base_vha->host->irq = ha->pdev->irq; 2784 2785 /* Initialized the timer */ 2786 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2787 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2788 "Started qla2x00_timer with " 2789 "interval=%d.\n", WATCH_INTERVAL); 2790 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2791 "Detected hba at address=%p.\n", 2792 ha); 2793 2794 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2795 if (ha->fw_attributes & BIT_4) { 2796 int prot = 0, guard; 2797 base_vha->flags.difdix_supported = 1; 2798 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2799 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2800 if (ql2xenabledif == 1) 2801 prot = SHOST_DIX_TYPE0_PROTECTION; 2802 scsi_host_set_prot(host, 2803 prot | SHOST_DIF_TYPE1_PROTECTION 2804 | SHOST_DIF_TYPE2_PROTECTION 2805 | SHOST_DIF_TYPE3_PROTECTION 2806 | SHOST_DIX_TYPE1_PROTECTION 2807 | SHOST_DIX_TYPE2_PROTECTION 2808 | SHOST_DIX_TYPE3_PROTECTION); 2809 2810 guard = SHOST_DIX_GUARD_CRC; 2811 2812 if (IS_PI_IPGUARD_CAPABLE(ha) && 2813 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2814 guard |= SHOST_DIX_GUARD_IP; 2815 2816 scsi_host_set_guard(host, guard); 2817 } else 2818 base_vha->flags.difdix_supported = 0; 2819 } 2820 2821 ha->isp_ops->enable_intrs(ha); 2822 2823 if (IS_QLAFX00(ha)) { 2824 ret = qlafx00_fx_disc(base_vha, 2825 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2826 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2827 QLA_SG_ALL : 128; 2828 } 2829 2830 ret = scsi_add_host(host, &pdev->dev); 2831 if (ret) 2832 goto probe_failed; 2833 2834 base_vha->flags.init_done = 1; 2835 base_vha->flags.online = 1; 2836 ha->prev_minidump_failed = 0; 2837 2838 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2839 "Init done and hba is online.\n"); 2840 2841 if (qla_ini_mode_enabled(base_vha)) 2842 scsi_scan_host(host); 2843 else 2844 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2845 "skipping scsi_scan_host() for non-initiator port\n"); 2846 2847 qla2x00_alloc_sysfs_attr(base_vha); 2848 2849 if (IS_QLAFX00(ha)) { 2850 ret = qlafx00_fx_disc(base_vha, 2851 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2852 2853 /* Register system information */ 2854 ret = qlafx00_fx_disc(base_vha, 2855 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2856 } 2857 2858 qla2x00_init_host_attr(base_vha); 2859 2860 qla2x00_dfs_setup(base_vha); 2861 2862 ql_log(ql_log_info, base_vha, 0x00fb, 2863 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2864 ql_log(ql_log_info, base_vha, 0x00fc, 2865 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2866 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2867 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2868 base_vha->host_no, 2869 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2870 2871 qlt_add_target(ha, base_vha); 2872 2873 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2874 return 0; 2875 2876 probe_init_failed: 2877 qla2x00_free_req_que(ha, req); 2878 ha->req_q_map[0] = NULL; 2879 clear_bit(0, ha->req_qid_map); 2880 qla2x00_free_rsp_que(ha, rsp); 2881 ha->rsp_q_map[0] = NULL; 2882 clear_bit(0, ha->rsp_qid_map); 2883 ha->max_req_queues = ha->max_rsp_queues = 0; 2884 2885 probe_failed: 2886 if (base_vha->timer_active) 2887 qla2x00_stop_timer(base_vha); 2888 base_vha->flags.online = 0; 2889 if (ha->dpc_thread) { 2890 struct task_struct *t = ha->dpc_thread; 2891 2892 ha->dpc_thread = NULL; 2893 kthread_stop(t); 2894 } 2895 2896 qla2x00_free_device(base_vha); 2897 2898 scsi_host_put(base_vha->host); 2899 2900 probe_hw_failed: 2901 qla2x00_clear_drv_active(ha); 2902 2903 iospace_config_failed: 2904 if (IS_P3P_TYPE(ha)) { 2905 if (!ha->nx_pcibase) 2906 iounmap((device_reg_t *)ha->nx_pcibase); 2907 if (!ql2xdbwr) 2908 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 2909 } else { 2910 if (ha->iobase) 2911 iounmap(ha->iobase); 2912 if (ha->cregbase) 2913 iounmap(ha->cregbase); 2914 } 2915 pci_release_selected_regions(ha->pdev, ha->bars); 2916 kfree(ha); 2917 ha = NULL; 2918 2919 probe_out: 2920 pci_disable_device(pdev); 2921 return ret; 2922 } 2923 2924 static void 2925 qla2x00_shutdown(struct pci_dev *pdev) 2926 { 2927 scsi_qla_host_t *vha; 2928 struct qla_hw_data *ha; 2929 2930 if (!atomic_read(&pdev->enable_cnt)) 2931 return; 2932 2933 vha = pci_get_drvdata(pdev); 2934 ha = vha->hw; 2935 2936 /* Notify ISPFX00 firmware */ 2937 if (IS_QLAFX00(ha)) 2938 qlafx00_driver_shutdown(vha, 20); 2939 2940 /* Turn-off FCE trace */ 2941 if (ha->flags.fce_enabled) { 2942 qla2x00_disable_fce_trace(vha, NULL, NULL); 2943 ha->flags.fce_enabled = 0; 2944 } 2945 2946 /* Turn-off EFT trace */ 2947 if (ha->eft) 2948 qla2x00_disable_eft_trace(vha); 2949 2950 /* Stop currently executing firmware. */ 2951 qla2x00_try_to_stop_firmware(vha); 2952 2953 /* Turn adapter off line */ 2954 vha->flags.online = 0; 2955 2956 /* turn-off interrupts on the card */ 2957 if (ha->interrupts_on) { 2958 vha->flags.init_done = 0; 2959 ha->isp_ops->disable_intrs(ha); 2960 } 2961 2962 qla2x00_free_irqs(vha); 2963 2964 qla2x00_free_fw_dump(ha); 2965 2966 pci_disable_pcie_error_reporting(pdev); 2967 pci_disable_device(pdev); 2968 } 2969 2970 /* Deletes all the virtual ports for a given ha */ 2971 static void 2972 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 2973 { 2974 scsi_qla_host_t *vha; 2975 unsigned long flags; 2976 2977 mutex_lock(&ha->vport_lock); 2978 while (ha->cur_vport_count) { 2979 spin_lock_irqsave(&ha->vport_slock, flags); 2980 2981 BUG_ON(base_vha->list.next == &ha->vp_list); 2982 /* This assumes first entry in ha->vp_list is always base vha */ 2983 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2984 scsi_host_get(vha->host); 2985 2986 spin_unlock_irqrestore(&ha->vport_slock, flags); 2987 mutex_unlock(&ha->vport_lock); 2988 2989 fc_vport_terminate(vha->fc_vport); 2990 scsi_host_put(vha->host); 2991 2992 mutex_lock(&ha->vport_lock); 2993 } 2994 mutex_unlock(&ha->vport_lock); 2995 } 2996 2997 /* Stops all deferred work threads */ 2998 static void 2999 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3000 { 3001 /* Flush the work queue and remove it */ 3002 if (ha->wq) { 3003 flush_workqueue(ha->wq); 3004 destroy_workqueue(ha->wq); 3005 ha->wq = NULL; 3006 } 3007 3008 /* Cancel all work and destroy DPC workqueues */ 3009 if (ha->dpc_lp_wq) { 3010 cancel_work_sync(&ha->idc_aen); 3011 destroy_workqueue(ha->dpc_lp_wq); 3012 ha->dpc_lp_wq = NULL; 3013 } 3014 3015 if (ha->dpc_hp_wq) { 3016 cancel_work_sync(&ha->nic_core_reset); 3017 cancel_work_sync(&ha->idc_state_handler); 3018 cancel_work_sync(&ha->nic_core_unrecoverable); 3019 destroy_workqueue(ha->dpc_hp_wq); 3020 ha->dpc_hp_wq = NULL; 3021 } 3022 3023 /* Kill the kernel thread for this host */ 3024 if (ha->dpc_thread) { 3025 struct task_struct *t = ha->dpc_thread; 3026 3027 /* 3028 * qla2xxx_wake_dpc checks for ->dpc_thread 3029 * so we need to zero it out. 3030 */ 3031 ha->dpc_thread = NULL; 3032 kthread_stop(t); 3033 } 3034 } 3035 3036 static void 3037 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3038 { 3039 if (IS_QLA82XX(ha)) { 3040 3041 iounmap((device_reg_t *)ha->nx_pcibase); 3042 if (!ql2xdbwr) 3043 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3044 } else { 3045 if (ha->iobase) 3046 iounmap(ha->iobase); 3047 3048 if (ha->cregbase) 3049 iounmap(ha->cregbase); 3050 3051 if (ha->mqiobase) 3052 iounmap(ha->mqiobase); 3053 3054 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3055 iounmap(ha->msixbase); 3056 } 3057 } 3058 3059 static void 3060 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3061 { 3062 if (IS_QLA8044(ha)) { 3063 qla8044_idc_lock(ha); 3064 qla8044_clear_drv_active(ha); 3065 qla8044_idc_unlock(ha); 3066 } else if (IS_QLA82XX(ha)) { 3067 qla82xx_idc_lock(ha); 3068 qla82xx_clear_drv_active(ha); 3069 qla82xx_idc_unlock(ha); 3070 } 3071 } 3072 3073 static void 3074 qla2x00_remove_one(struct pci_dev *pdev) 3075 { 3076 scsi_qla_host_t *base_vha; 3077 struct qla_hw_data *ha; 3078 3079 base_vha = pci_get_drvdata(pdev); 3080 ha = base_vha->hw; 3081 3082 /* Indicate device removal to prevent future board_disable and wait 3083 * until any pending board_disable has completed. */ 3084 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3085 cancel_work_sync(&ha->board_disable); 3086 3087 /* 3088 * If the PCI device is disabled then there was a PCI-disconnect and 3089 * qla2x00_disable_board_on_pci_error has taken care of most of the 3090 * resources. 3091 */ 3092 if (!atomic_read(&pdev->enable_cnt)) { 3093 scsi_host_put(base_vha->host); 3094 kfree(ha); 3095 pci_set_drvdata(pdev, NULL); 3096 return; 3097 } 3098 3099 qla2x00_wait_for_hba_ready(base_vha); 3100 3101 set_bit(UNLOADING, &base_vha->dpc_flags); 3102 3103 if (IS_QLAFX00(ha)) 3104 qlafx00_driver_shutdown(base_vha, 20); 3105 3106 qla2x00_delete_all_vps(ha, base_vha); 3107 3108 if (IS_QLA8031(ha)) { 3109 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3110 "Clearing fcoe driver presence.\n"); 3111 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3112 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3113 "Error while clearing DRV-Presence.\n"); 3114 } 3115 3116 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3117 3118 qla2x00_dfs_remove(base_vha); 3119 3120 qla84xx_put_chip(base_vha); 3121 3122 /* Laser should be disabled only for ISP2031 */ 3123 if (IS_QLA2031(ha)) 3124 qla83xx_disable_laser(base_vha); 3125 3126 /* Disable timer */ 3127 if (base_vha->timer_active) 3128 qla2x00_stop_timer(base_vha); 3129 3130 base_vha->flags.online = 0; 3131 3132 qla2x00_destroy_deferred_work(ha); 3133 3134 qlt_remove_target(ha, base_vha); 3135 3136 qla2x00_free_sysfs_attr(base_vha, true); 3137 3138 fc_remove_host(base_vha->host); 3139 3140 scsi_remove_host(base_vha->host); 3141 3142 qla2x00_free_device(base_vha); 3143 3144 qla2x00_clear_drv_active(ha); 3145 3146 scsi_host_put(base_vha->host); 3147 3148 qla2x00_unmap_iobases(ha); 3149 3150 pci_release_selected_regions(ha->pdev, ha->bars); 3151 kfree(ha); 3152 ha = NULL; 3153 3154 pci_disable_pcie_error_reporting(pdev); 3155 3156 pci_disable_device(pdev); 3157 } 3158 3159 static void 3160 qla2x00_free_device(scsi_qla_host_t *vha) 3161 { 3162 struct qla_hw_data *ha = vha->hw; 3163 3164 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3165 3166 /* Disable timer */ 3167 if (vha->timer_active) 3168 qla2x00_stop_timer(vha); 3169 3170 qla25xx_delete_queues(vha); 3171 3172 if (ha->flags.fce_enabled) 3173 qla2x00_disable_fce_trace(vha, NULL, NULL); 3174 3175 if (ha->eft) 3176 qla2x00_disable_eft_trace(vha); 3177 3178 /* Stop currently executing firmware. */ 3179 qla2x00_try_to_stop_firmware(vha); 3180 3181 vha->flags.online = 0; 3182 3183 /* turn-off interrupts on the card */ 3184 if (ha->interrupts_on) { 3185 vha->flags.init_done = 0; 3186 ha->isp_ops->disable_intrs(ha); 3187 } 3188 3189 qla2x00_free_irqs(vha); 3190 3191 qla2x00_free_fcports(vha); 3192 3193 qla2x00_mem_free(ha); 3194 3195 qla82xx_md_free(vha); 3196 3197 qla2x00_free_queues(ha); 3198 } 3199 3200 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3201 { 3202 fc_port_t *fcport, *tfcport; 3203 3204 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3205 list_del(&fcport->list); 3206 qla2x00_clear_loop_id(fcport); 3207 kfree(fcport); 3208 fcport = NULL; 3209 } 3210 } 3211 3212 static inline void 3213 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3214 int defer) 3215 { 3216 struct fc_rport *rport; 3217 scsi_qla_host_t *base_vha; 3218 unsigned long flags; 3219 3220 if (!fcport->rport) 3221 return; 3222 3223 rport = fcport->rport; 3224 if (defer) { 3225 base_vha = pci_get_drvdata(vha->hw->pdev); 3226 spin_lock_irqsave(vha->host->host_lock, flags); 3227 fcport->drport = rport; 3228 spin_unlock_irqrestore(vha->host->host_lock, flags); 3229 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3230 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3231 qla2xxx_wake_dpc(base_vha); 3232 } else { 3233 int now; 3234 if (rport) 3235 fc_remote_port_delete(rport); 3236 qlt_do_generation_tick(vha, &now); 3237 qlt_fc_port_deleted(vha, fcport, now); 3238 } 3239 } 3240 3241 /* 3242 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3243 * 3244 * Input: ha = adapter block pointer. fcport = port structure pointer. 3245 * 3246 * Return: None. 3247 * 3248 * Context: 3249 */ 3250 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3251 int do_login, int defer) 3252 { 3253 if (IS_QLAFX00(vha->hw)) { 3254 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3255 qla2x00_schedule_rport_del(vha, fcport, defer); 3256 return; 3257 } 3258 3259 if (atomic_read(&fcport->state) == FCS_ONLINE && 3260 vha->vp_idx == fcport->vha->vp_idx) { 3261 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3262 qla2x00_schedule_rport_del(vha, fcport, defer); 3263 } 3264 /* 3265 * We may need to retry the login, so don't change the state of the 3266 * port but do the retries. 3267 */ 3268 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3269 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3270 3271 if (!do_login) 3272 return; 3273 3274 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3275 3276 if (fcport->login_retry == 0) { 3277 fcport->login_retry = vha->hw->login_retry_count; 3278 3279 ql_dbg(ql_dbg_disc, vha, 0x2067, 3280 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3281 fcport->port_name, fcport->loop_id, fcport->login_retry); 3282 } 3283 } 3284 3285 /* 3286 * qla2x00_mark_all_devices_lost 3287 * Updates fcport state when device goes offline. 3288 * 3289 * Input: 3290 * ha = adapter block pointer. 3291 * fcport = port structure pointer. 3292 * 3293 * Return: 3294 * None. 3295 * 3296 * Context: 3297 */ 3298 void 3299 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3300 { 3301 fc_port_t *fcport; 3302 3303 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3304 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3305 continue; 3306 3307 /* 3308 * No point in marking the device as lost, if the device is 3309 * already DEAD. 3310 */ 3311 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3312 continue; 3313 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3314 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3315 if (defer) 3316 qla2x00_schedule_rport_del(vha, fcport, defer); 3317 else if (vha->vp_idx == fcport->vha->vp_idx) 3318 qla2x00_schedule_rport_del(vha, fcport, defer); 3319 } 3320 } 3321 } 3322 3323 /* 3324 * qla2x00_mem_alloc 3325 * Allocates adapter memory. 3326 * 3327 * Returns: 3328 * 0 = success. 3329 * !0 = failure. 3330 */ 3331 static int 3332 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3333 struct req_que **req, struct rsp_que **rsp) 3334 { 3335 char name[16]; 3336 3337 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3338 &ha->init_cb_dma, GFP_KERNEL); 3339 if (!ha->init_cb) 3340 goto fail; 3341 3342 if (qlt_mem_alloc(ha) < 0) 3343 goto fail_free_init_cb; 3344 3345 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3346 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3347 if (!ha->gid_list) 3348 goto fail_free_tgt_mem; 3349 3350 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3351 if (!ha->srb_mempool) 3352 goto fail_free_gid_list; 3353 3354 if (IS_P3P_TYPE(ha)) { 3355 /* Allocate cache for CT6 Ctx. */ 3356 if (!ctx_cachep) { 3357 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3358 sizeof(struct ct6_dsd), 0, 3359 SLAB_HWCACHE_ALIGN, NULL); 3360 if (!ctx_cachep) 3361 goto fail_free_gid_list; 3362 } 3363 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3364 ctx_cachep); 3365 if (!ha->ctx_mempool) 3366 goto fail_free_srb_mempool; 3367 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3368 "ctx_cachep=%p ctx_mempool=%p.\n", 3369 ctx_cachep, ha->ctx_mempool); 3370 } 3371 3372 /* Get memory for cached NVRAM */ 3373 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3374 if (!ha->nvram) 3375 goto fail_free_ctx_mempool; 3376 3377 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3378 ha->pdev->device); 3379 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3380 DMA_POOL_SIZE, 8, 0); 3381 if (!ha->s_dma_pool) 3382 goto fail_free_nvram; 3383 3384 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3385 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3386 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3387 3388 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3389 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3390 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3391 if (!ha->dl_dma_pool) { 3392 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3393 "Failed to allocate memory for dl_dma_pool.\n"); 3394 goto fail_s_dma_pool; 3395 } 3396 3397 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3398 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3399 if (!ha->fcp_cmnd_dma_pool) { 3400 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3401 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3402 goto fail_dl_dma_pool; 3403 } 3404 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3405 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3406 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3407 } 3408 3409 /* Allocate memory for SNS commands */ 3410 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3411 /* Get consistent memory allocated for SNS commands */ 3412 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3413 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3414 if (!ha->sns_cmd) 3415 goto fail_dma_pool; 3416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3417 "sns_cmd: %p.\n", ha->sns_cmd); 3418 } else { 3419 /* Get consistent memory allocated for MS IOCB */ 3420 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3421 &ha->ms_iocb_dma); 3422 if (!ha->ms_iocb) 3423 goto fail_dma_pool; 3424 /* Get consistent memory allocated for CT SNS commands */ 3425 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3426 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3427 if (!ha->ct_sns) 3428 goto fail_free_ms_iocb; 3429 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3430 "ms_iocb=%p ct_sns=%p.\n", 3431 ha->ms_iocb, ha->ct_sns); 3432 } 3433 3434 /* Allocate memory for request ring */ 3435 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3436 if (!*req) { 3437 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3438 "Failed to allocate memory for req.\n"); 3439 goto fail_req; 3440 } 3441 (*req)->length = req_len; 3442 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3443 ((*req)->length + 1) * sizeof(request_t), 3444 &(*req)->dma, GFP_KERNEL); 3445 if (!(*req)->ring) { 3446 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3447 "Failed to allocate memory for req_ring.\n"); 3448 goto fail_req_ring; 3449 } 3450 /* Allocate memory for response ring */ 3451 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3452 if (!*rsp) { 3453 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3454 "Failed to allocate memory for rsp.\n"); 3455 goto fail_rsp; 3456 } 3457 (*rsp)->hw = ha; 3458 (*rsp)->length = rsp_len; 3459 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3460 ((*rsp)->length + 1) * sizeof(response_t), 3461 &(*rsp)->dma, GFP_KERNEL); 3462 if (!(*rsp)->ring) { 3463 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3464 "Failed to allocate memory for rsp_ring.\n"); 3465 goto fail_rsp_ring; 3466 } 3467 (*req)->rsp = *rsp; 3468 (*rsp)->req = *req; 3469 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3470 "req=%p req->length=%d req->ring=%p rsp=%p " 3471 "rsp->length=%d rsp->ring=%p.\n", 3472 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3473 (*rsp)->ring); 3474 /* Allocate memory for NVRAM data for vports */ 3475 if (ha->nvram_npiv_size) { 3476 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3477 ha->nvram_npiv_size, GFP_KERNEL); 3478 if (!ha->npiv_info) { 3479 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3480 "Failed to allocate memory for npiv_info.\n"); 3481 goto fail_npiv_info; 3482 } 3483 } else 3484 ha->npiv_info = NULL; 3485 3486 /* Get consistent memory allocated for EX-INIT-CB. */ 3487 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3488 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3489 &ha->ex_init_cb_dma); 3490 if (!ha->ex_init_cb) 3491 goto fail_ex_init_cb; 3492 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3493 "ex_init_cb=%p.\n", ha->ex_init_cb); 3494 } 3495 3496 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3497 3498 /* Get consistent memory allocated for Async Port-Database. */ 3499 if (!IS_FWI2_CAPABLE(ha)) { 3500 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3501 &ha->async_pd_dma); 3502 if (!ha->async_pd) 3503 goto fail_async_pd; 3504 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3505 "async_pd=%p.\n", ha->async_pd); 3506 } 3507 3508 INIT_LIST_HEAD(&ha->vp_list); 3509 3510 /* Allocate memory for our loop_id bitmap */ 3511 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3512 GFP_KERNEL); 3513 if (!ha->loop_id_map) 3514 goto fail_async_pd; 3515 else { 3516 qla2x00_set_reserved_loop_ids(ha); 3517 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3518 "loop_id_map=%p.\n", ha->loop_id_map); 3519 } 3520 3521 return 0; 3522 3523 fail_async_pd: 3524 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3525 fail_ex_init_cb: 3526 kfree(ha->npiv_info); 3527 fail_npiv_info: 3528 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3529 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3530 (*rsp)->ring = NULL; 3531 (*rsp)->dma = 0; 3532 fail_rsp_ring: 3533 kfree(*rsp); 3534 fail_rsp: 3535 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3536 sizeof(request_t), (*req)->ring, (*req)->dma); 3537 (*req)->ring = NULL; 3538 (*req)->dma = 0; 3539 fail_req_ring: 3540 kfree(*req); 3541 fail_req: 3542 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3543 ha->ct_sns, ha->ct_sns_dma); 3544 ha->ct_sns = NULL; 3545 ha->ct_sns_dma = 0; 3546 fail_free_ms_iocb: 3547 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3548 ha->ms_iocb = NULL; 3549 ha->ms_iocb_dma = 0; 3550 fail_dma_pool: 3551 if (IS_QLA82XX(ha) || ql2xenabledif) { 3552 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3553 ha->fcp_cmnd_dma_pool = NULL; 3554 } 3555 fail_dl_dma_pool: 3556 if (IS_QLA82XX(ha) || ql2xenabledif) { 3557 dma_pool_destroy(ha->dl_dma_pool); 3558 ha->dl_dma_pool = NULL; 3559 } 3560 fail_s_dma_pool: 3561 dma_pool_destroy(ha->s_dma_pool); 3562 ha->s_dma_pool = NULL; 3563 fail_free_nvram: 3564 kfree(ha->nvram); 3565 ha->nvram = NULL; 3566 fail_free_ctx_mempool: 3567 mempool_destroy(ha->ctx_mempool); 3568 ha->ctx_mempool = NULL; 3569 fail_free_srb_mempool: 3570 mempool_destroy(ha->srb_mempool); 3571 ha->srb_mempool = NULL; 3572 fail_free_gid_list: 3573 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3574 ha->gid_list, 3575 ha->gid_list_dma); 3576 ha->gid_list = NULL; 3577 ha->gid_list_dma = 0; 3578 fail_free_tgt_mem: 3579 qlt_mem_free(ha); 3580 fail_free_init_cb: 3581 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3582 ha->init_cb_dma); 3583 ha->init_cb = NULL; 3584 ha->init_cb_dma = 0; 3585 fail: 3586 ql_log(ql_log_fatal, NULL, 0x0030, 3587 "Memory allocation failure.\n"); 3588 return -ENOMEM; 3589 } 3590 3591 /* 3592 * qla2x00_free_fw_dump 3593 * Frees fw dump stuff. 3594 * 3595 * Input: 3596 * ha = adapter block pointer 3597 */ 3598 static void 3599 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3600 { 3601 if (ha->fce) 3602 dma_free_coherent(&ha->pdev->dev, 3603 FCE_SIZE, ha->fce, ha->fce_dma); 3604 3605 if (ha->eft) 3606 dma_free_coherent(&ha->pdev->dev, 3607 EFT_SIZE, ha->eft, ha->eft_dma); 3608 3609 if (ha->fw_dump) 3610 vfree(ha->fw_dump); 3611 if (ha->fw_dump_template) 3612 vfree(ha->fw_dump_template); 3613 3614 ha->fce = NULL; 3615 ha->fce_dma = 0; 3616 ha->eft = NULL; 3617 ha->eft_dma = 0; 3618 ha->fw_dumped = 0; 3619 ha->fw_dump_cap_flags = 0; 3620 ha->fw_dump_reading = 0; 3621 ha->fw_dump = NULL; 3622 ha->fw_dump_len = 0; 3623 ha->fw_dump_template = NULL; 3624 ha->fw_dump_template_len = 0; 3625 } 3626 3627 /* 3628 * qla2x00_mem_free 3629 * Frees all adapter allocated memory. 3630 * 3631 * Input: 3632 * ha = adapter block pointer. 3633 */ 3634 static void 3635 qla2x00_mem_free(struct qla_hw_data *ha) 3636 { 3637 qla2x00_free_fw_dump(ha); 3638 3639 if (ha->mctp_dump) 3640 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3641 ha->mctp_dump_dma); 3642 3643 if (ha->srb_mempool) 3644 mempool_destroy(ha->srb_mempool); 3645 3646 if (ha->dcbx_tlv) 3647 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3648 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3649 3650 if (ha->xgmac_data) 3651 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3652 ha->xgmac_data, ha->xgmac_data_dma); 3653 3654 if (ha->sns_cmd) 3655 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3656 ha->sns_cmd, ha->sns_cmd_dma); 3657 3658 if (ha->ct_sns) 3659 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3660 ha->ct_sns, ha->ct_sns_dma); 3661 3662 if (ha->sfp_data) 3663 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3664 3665 if (ha->ms_iocb) 3666 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3667 3668 if (ha->ex_init_cb) 3669 dma_pool_free(ha->s_dma_pool, 3670 ha->ex_init_cb, ha->ex_init_cb_dma); 3671 3672 if (ha->async_pd) 3673 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3674 3675 if (ha->s_dma_pool) 3676 dma_pool_destroy(ha->s_dma_pool); 3677 3678 if (ha->gid_list) 3679 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3680 ha->gid_list, ha->gid_list_dma); 3681 3682 if (IS_QLA82XX(ha)) { 3683 if (!list_empty(&ha->gbl_dsd_list)) { 3684 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3685 3686 /* clean up allocated prev pool */ 3687 list_for_each_entry_safe(dsd_ptr, 3688 tdsd_ptr, &ha->gbl_dsd_list, list) { 3689 dma_pool_free(ha->dl_dma_pool, 3690 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3691 list_del(&dsd_ptr->list); 3692 kfree(dsd_ptr); 3693 } 3694 } 3695 } 3696 3697 if (ha->dl_dma_pool) 3698 dma_pool_destroy(ha->dl_dma_pool); 3699 3700 if (ha->fcp_cmnd_dma_pool) 3701 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3702 3703 if (ha->ctx_mempool) 3704 mempool_destroy(ha->ctx_mempool); 3705 3706 qlt_mem_free(ha); 3707 3708 if (ha->init_cb) 3709 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3710 ha->init_cb, ha->init_cb_dma); 3711 vfree(ha->optrom_buffer); 3712 kfree(ha->nvram); 3713 kfree(ha->npiv_info); 3714 kfree(ha->swl); 3715 kfree(ha->loop_id_map); 3716 3717 ha->srb_mempool = NULL; 3718 ha->ctx_mempool = NULL; 3719 ha->sns_cmd = NULL; 3720 ha->sns_cmd_dma = 0; 3721 ha->ct_sns = NULL; 3722 ha->ct_sns_dma = 0; 3723 ha->ms_iocb = NULL; 3724 ha->ms_iocb_dma = 0; 3725 ha->init_cb = NULL; 3726 ha->init_cb_dma = 0; 3727 ha->ex_init_cb = NULL; 3728 ha->ex_init_cb_dma = 0; 3729 ha->async_pd = NULL; 3730 ha->async_pd_dma = 0; 3731 3732 ha->s_dma_pool = NULL; 3733 ha->dl_dma_pool = NULL; 3734 ha->fcp_cmnd_dma_pool = NULL; 3735 3736 ha->gid_list = NULL; 3737 ha->gid_list_dma = 0; 3738 3739 ha->tgt.atio_ring = NULL; 3740 ha->tgt.atio_dma = 0; 3741 ha->tgt.tgt_vp_map = NULL; 3742 } 3743 3744 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3745 struct qla_hw_data *ha) 3746 { 3747 struct Scsi_Host *host; 3748 struct scsi_qla_host *vha = NULL; 3749 3750 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3751 if (host == NULL) { 3752 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3753 "Failed to allocate host from the scsi layer, aborting.\n"); 3754 goto fail; 3755 } 3756 3757 /* Clear our data area */ 3758 vha = shost_priv(host); 3759 memset(vha, 0, sizeof(scsi_qla_host_t)); 3760 3761 vha->host = host; 3762 vha->host_no = host->host_no; 3763 vha->hw = ha; 3764 3765 INIT_LIST_HEAD(&vha->vp_fcports); 3766 INIT_LIST_HEAD(&vha->work_list); 3767 INIT_LIST_HEAD(&vha->list); 3768 INIT_LIST_HEAD(&vha->qla_cmd_list); 3769 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 3770 3771 spin_lock_init(&vha->work_lock); 3772 spin_lock_init(&vha->cmd_list_lock); 3773 3774 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3775 ql_dbg(ql_dbg_init, vha, 0x0041, 3776 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3777 vha->host, vha->hw, vha, 3778 dev_name(&(ha->pdev->dev))); 3779 3780 return vha; 3781 3782 fail: 3783 return vha; 3784 } 3785 3786 static struct qla_work_evt * 3787 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3788 { 3789 struct qla_work_evt *e; 3790 uint8_t bail; 3791 3792 QLA_VHA_MARK_BUSY(vha, bail); 3793 if (bail) 3794 return NULL; 3795 3796 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3797 if (!e) { 3798 QLA_VHA_MARK_NOT_BUSY(vha); 3799 return NULL; 3800 } 3801 3802 INIT_LIST_HEAD(&e->list); 3803 e->type = type; 3804 e->flags = QLA_EVT_FLAG_FREE; 3805 return e; 3806 } 3807 3808 static int 3809 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3810 { 3811 unsigned long flags; 3812 3813 spin_lock_irqsave(&vha->work_lock, flags); 3814 list_add_tail(&e->list, &vha->work_list); 3815 spin_unlock_irqrestore(&vha->work_lock, flags); 3816 qla2xxx_wake_dpc(vha); 3817 3818 return QLA_SUCCESS; 3819 } 3820 3821 int 3822 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3823 u32 data) 3824 { 3825 struct qla_work_evt *e; 3826 3827 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3828 if (!e) 3829 return QLA_FUNCTION_FAILED; 3830 3831 e->u.aen.code = code; 3832 e->u.aen.data = data; 3833 return qla2x00_post_work(vha, e); 3834 } 3835 3836 int 3837 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3838 { 3839 struct qla_work_evt *e; 3840 3841 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3842 if (!e) 3843 return QLA_FUNCTION_FAILED; 3844 3845 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3846 return qla2x00_post_work(vha, e); 3847 } 3848 3849 #define qla2x00_post_async_work(name, type) \ 3850 int qla2x00_post_async_##name##_work( \ 3851 struct scsi_qla_host *vha, \ 3852 fc_port_t *fcport, uint16_t *data) \ 3853 { \ 3854 struct qla_work_evt *e; \ 3855 \ 3856 e = qla2x00_alloc_work(vha, type); \ 3857 if (!e) \ 3858 return QLA_FUNCTION_FAILED; \ 3859 \ 3860 e->u.logio.fcport = fcport; \ 3861 if (data) { \ 3862 e->u.logio.data[0] = data[0]; \ 3863 e->u.logio.data[1] = data[1]; \ 3864 } \ 3865 return qla2x00_post_work(vha, e); \ 3866 } 3867 3868 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3869 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3870 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3871 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3872 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3873 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3874 3875 int 3876 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3877 { 3878 struct qla_work_evt *e; 3879 3880 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3881 if (!e) 3882 return QLA_FUNCTION_FAILED; 3883 3884 e->u.uevent.code = code; 3885 return qla2x00_post_work(vha, e); 3886 } 3887 3888 static void 3889 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3890 { 3891 char event_string[40]; 3892 char *envp[] = { event_string, NULL }; 3893 3894 switch (code) { 3895 case QLA_UEVENT_CODE_FW_DUMP: 3896 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3897 vha->host_no); 3898 break; 3899 default: 3900 /* do nothing */ 3901 break; 3902 } 3903 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3904 } 3905 3906 int 3907 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 3908 uint32_t *data, int cnt) 3909 { 3910 struct qla_work_evt *e; 3911 3912 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 3913 if (!e) 3914 return QLA_FUNCTION_FAILED; 3915 3916 e->u.aenfx.evtcode = evtcode; 3917 e->u.aenfx.count = cnt; 3918 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 3919 return qla2x00_post_work(vha, e); 3920 } 3921 3922 void 3923 qla2x00_do_work(struct scsi_qla_host *vha) 3924 { 3925 struct qla_work_evt *e, *tmp; 3926 unsigned long flags; 3927 LIST_HEAD(work); 3928 3929 spin_lock_irqsave(&vha->work_lock, flags); 3930 list_splice_init(&vha->work_list, &work); 3931 spin_unlock_irqrestore(&vha->work_lock, flags); 3932 3933 list_for_each_entry_safe(e, tmp, &work, list) { 3934 list_del_init(&e->list); 3935 3936 switch (e->type) { 3937 case QLA_EVT_AEN: 3938 fc_host_post_event(vha->host, fc_get_event_number(), 3939 e->u.aen.code, e->u.aen.data); 3940 break; 3941 case QLA_EVT_IDC_ACK: 3942 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3943 break; 3944 case QLA_EVT_ASYNC_LOGIN: 3945 qla2x00_async_login(vha, e->u.logio.fcport, 3946 e->u.logio.data); 3947 break; 3948 case QLA_EVT_ASYNC_LOGIN_DONE: 3949 qla2x00_async_login_done(vha, e->u.logio.fcport, 3950 e->u.logio.data); 3951 break; 3952 case QLA_EVT_ASYNC_LOGOUT: 3953 qla2x00_async_logout(vha, e->u.logio.fcport); 3954 break; 3955 case QLA_EVT_ASYNC_LOGOUT_DONE: 3956 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3957 e->u.logio.data); 3958 break; 3959 case QLA_EVT_ASYNC_ADISC: 3960 qla2x00_async_adisc(vha, e->u.logio.fcport, 3961 e->u.logio.data); 3962 break; 3963 case QLA_EVT_ASYNC_ADISC_DONE: 3964 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3965 e->u.logio.data); 3966 break; 3967 case QLA_EVT_UEVENT: 3968 qla2x00_uevent_emit(vha, e->u.uevent.code); 3969 break; 3970 case QLA_EVT_AENFX: 3971 qlafx00_process_aen(vha, e); 3972 break; 3973 } 3974 if (e->flags & QLA_EVT_FLAG_FREE) 3975 kfree(e); 3976 3977 /* For each work completed decrement vha ref count */ 3978 QLA_VHA_MARK_NOT_BUSY(vha); 3979 } 3980 } 3981 3982 /* Relogins all the fcports of a vport 3983 * Context: dpc thread 3984 */ 3985 void qla2x00_relogin(struct scsi_qla_host *vha) 3986 { 3987 fc_port_t *fcport; 3988 int status; 3989 uint16_t next_loopid = 0; 3990 struct qla_hw_data *ha = vha->hw; 3991 uint16_t data[2]; 3992 3993 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3994 /* 3995 * If the port is not ONLINE then try to login 3996 * to it if we haven't run out of retries. 3997 */ 3998 if (atomic_read(&fcport->state) != FCS_ONLINE && 3999 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4000 fcport->login_retry--; 4001 if (fcport->flags & FCF_FABRIC_DEVICE) { 4002 if (fcport->flags & FCF_FCP2_DEVICE) 4003 ha->isp_ops->fabric_logout(vha, 4004 fcport->loop_id, 4005 fcport->d_id.b.domain, 4006 fcport->d_id.b.area, 4007 fcport->d_id.b.al_pa); 4008 4009 if (fcport->loop_id == FC_NO_LOOP_ID) { 4010 fcport->loop_id = next_loopid = 4011 ha->min_external_loopid; 4012 status = qla2x00_find_new_loop_id( 4013 vha, fcport); 4014 if (status != QLA_SUCCESS) { 4015 /* Ran out of IDs to use */ 4016 break; 4017 } 4018 } 4019 4020 if (IS_ALOGIO_CAPABLE(ha)) { 4021 fcport->flags |= FCF_ASYNC_SENT; 4022 data[0] = 0; 4023 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4024 status = qla2x00_post_async_login_work( 4025 vha, fcport, data); 4026 if (status == QLA_SUCCESS) 4027 continue; 4028 /* Attempt a retry. */ 4029 status = 1; 4030 } else { 4031 status = qla2x00_fabric_login(vha, 4032 fcport, &next_loopid); 4033 if (status == QLA_SUCCESS) { 4034 int status2; 4035 uint8_t opts; 4036 4037 opts = 0; 4038 if (fcport->flags & 4039 FCF_FCP2_DEVICE) 4040 opts |= BIT_1; 4041 status2 = 4042 qla2x00_get_port_database( 4043 vha, fcport, opts); 4044 if (status2 != QLA_SUCCESS) 4045 status = 1; 4046 } 4047 } 4048 } else 4049 status = qla2x00_local_device_login(vha, 4050 fcport); 4051 4052 if (status == QLA_SUCCESS) { 4053 fcport->old_loop_id = fcport->loop_id; 4054 4055 ql_dbg(ql_dbg_disc, vha, 0x2003, 4056 "Port login OK: logged in ID 0x%x.\n", 4057 fcport->loop_id); 4058 4059 qla2x00_update_fcport(vha, fcport); 4060 4061 } else if (status == 1) { 4062 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4063 /* retry the login again */ 4064 ql_dbg(ql_dbg_disc, vha, 0x2007, 4065 "Retrying %d login again loop_id 0x%x.\n", 4066 fcport->login_retry, fcport->loop_id); 4067 } else { 4068 fcport->login_retry = 0; 4069 } 4070 4071 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4072 qla2x00_clear_loop_id(fcport); 4073 } 4074 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4075 break; 4076 } 4077 } 4078 4079 /* Schedule work on any of the dpc-workqueues */ 4080 void 4081 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4082 { 4083 struct qla_hw_data *ha = base_vha->hw; 4084 4085 switch (work_code) { 4086 case MBA_IDC_AEN: /* 0x8200 */ 4087 if (ha->dpc_lp_wq) 4088 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4089 break; 4090 4091 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4092 if (!ha->flags.nic_core_reset_hdlr_active) { 4093 if (ha->dpc_hp_wq) 4094 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4095 } else 4096 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4097 "NIC Core reset is already active. Skip " 4098 "scheduling it again.\n"); 4099 break; 4100 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4101 if (ha->dpc_hp_wq) 4102 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4103 break; 4104 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4105 if (ha->dpc_hp_wq) 4106 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4107 break; 4108 default: 4109 ql_log(ql_log_warn, base_vha, 0xb05f, 4110 "Unknown work-code=0x%x.\n", work_code); 4111 } 4112 4113 return; 4114 } 4115 4116 /* Work: Perform NIC Core Unrecoverable state handling */ 4117 void 4118 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4119 { 4120 struct qla_hw_data *ha = 4121 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4122 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4123 uint32_t dev_state = 0; 4124 4125 qla83xx_idc_lock(base_vha, 0); 4126 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4127 qla83xx_reset_ownership(base_vha); 4128 if (ha->flags.nic_core_reset_owner) { 4129 ha->flags.nic_core_reset_owner = 0; 4130 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4131 QLA8XXX_DEV_FAILED); 4132 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4133 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4134 } 4135 qla83xx_idc_unlock(base_vha, 0); 4136 } 4137 4138 /* Work: Execute IDC state handler */ 4139 void 4140 qla83xx_idc_state_handler_work(struct work_struct *work) 4141 { 4142 struct qla_hw_data *ha = 4143 container_of(work, struct qla_hw_data, idc_state_handler); 4144 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4145 uint32_t dev_state = 0; 4146 4147 qla83xx_idc_lock(base_vha, 0); 4148 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4149 if (dev_state == QLA8XXX_DEV_FAILED || 4150 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4151 qla83xx_idc_state_handler(base_vha); 4152 qla83xx_idc_unlock(base_vha, 0); 4153 } 4154 4155 static int 4156 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4157 { 4158 int rval = QLA_SUCCESS; 4159 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4160 uint32_t heart_beat_counter1, heart_beat_counter2; 4161 4162 do { 4163 if (time_after(jiffies, heart_beat_wait)) { 4164 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4165 "Nic Core f/w is not alive.\n"); 4166 rval = QLA_FUNCTION_FAILED; 4167 break; 4168 } 4169 4170 qla83xx_idc_lock(base_vha, 0); 4171 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4172 &heart_beat_counter1); 4173 qla83xx_idc_unlock(base_vha, 0); 4174 msleep(100); 4175 qla83xx_idc_lock(base_vha, 0); 4176 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4177 &heart_beat_counter2); 4178 qla83xx_idc_unlock(base_vha, 0); 4179 } while (heart_beat_counter1 == heart_beat_counter2); 4180 4181 return rval; 4182 } 4183 4184 /* Work: Perform NIC Core Reset handling */ 4185 void 4186 qla83xx_nic_core_reset_work(struct work_struct *work) 4187 { 4188 struct qla_hw_data *ha = 4189 container_of(work, struct qla_hw_data, nic_core_reset); 4190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4191 uint32_t dev_state = 0; 4192 4193 if (IS_QLA2031(ha)) { 4194 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4195 ql_log(ql_log_warn, base_vha, 0xb081, 4196 "Failed to dump mctp\n"); 4197 return; 4198 } 4199 4200 if (!ha->flags.nic_core_reset_hdlr_active) { 4201 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4202 qla83xx_idc_lock(base_vha, 0); 4203 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4204 &dev_state); 4205 qla83xx_idc_unlock(base_vha, 0); 4206 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4207 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4208 "Nic Core f/w is alive.\n"); 4209 return; 4210 } 4211 } 4212 4213 ha->flags.nic_core_reset_hdlr_active = 1; 4214 if (qla83xx_nic_core_reset(base_vha)) { 4215 /* NIC Core reset failed. */ 4216 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4217 "NIC Core reset failed.\n"); 4218 } 4219 ha->flags.nic_core_reset_hdlr_active = 0; 4220 } 4221 } 4222 4223 /* Work: Handle 8200 IDC aens */ 4224 void 4225 qla83xx_service_idc_aen(struct work_struct *work) 4226 { 4227 struct qla_hw_data *ha = 4228 container_of(work, struct qla_hw_data, idc_aen); 4229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4230 uint32_t dev_state, idc_control; 4231 4232 qla83xx_idc_lock(base_vha, 0); 4233 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4234 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4235 qla83xx_idc_unlock(base_vha, 0); 4236 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4237 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4238 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4239 "Application requested NIC Core Reset.\n"); 4240 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4241 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4242 QLA_SUCCESS) { 4243 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4244 "Other protocol driver requested NIC Core Reset.\n"); 4245 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4246 } 4247 } else if (dev_state == QLA8XXX_DEV_FAILED || 4248 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4249 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4250 } 4251 } 4252 4253 static void 4254 qla83xx_wait_logic(void) 4255 { 4256 int i; 4257 4258 /* Yield CPU */ 4259 if (!in_interrupt()) { 4260 /* 4261 * Wait about 200ms before retrying again. 4262 * This controls the number of retries for single 4263 * lock operation. 4264 */ 4265 msleep(100); 4266 schedule(); 4267 } else { 4268 for (i = 0; i < 20; i++) 4269 cpu_relax(); /* This a nop instr on i386 */ 4270 } 4271 } 4272 4273 static int 4274 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4275 { 4276 int rval; 4277 uint32_t data; 4278 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4279 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4280 struct qla_hw_data *ha = base_vha->hw; 4281 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4282 "Trying force recovery of the IDC lock.\n"); 4283 4284 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4285 if (rval) 4286 return rval; 4287 4288 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4289 return QLA_SUCCESS; 4290 } else { 4291 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4292 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4293 data); 4294 if (rval) 4295 return rval; 4296 4297 msleep(200); 4298 4299 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4300 &data); 4301 if (rval) 4302 return rval; 4303 4304 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4305 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4306 ~(idc_lck_rcvry_stage_mask)); 4307 rval = qla83xx_wr_reg(base_vha, 4308 QLA83XX_IDC_LOCK_RECOVERY, data); 4309 if (rval) 4310 return rval; 4311 4312 /* Forcefully perform IDC UnLock */ 4313 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4314 &data); 4315 if (rval) 4316 return rval; 4317 /* Clear lock-id by setting 0xff */ 4318 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4319 0xff); 4320 if (rval) 4321 return rval; 4322 /* Clear lock-recovery by setting 0x0 */ 4323 rval = qla83xx_wr_reg(base_vha, 4324 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4325 if (rval) 4326 return rval; 4327 } else 4328 return QLA_SUCCESS; 4329 } 4330 4331 return rval; 4332 } 4333 4334 static int 4335 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4336 { 4337 int rval = QLA_SUCCESS; 4338 uint32_t o_drv_lockid, n_drv_lockid; 4339 unsigned long lock_recovery_timeout; 4340 4341 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4342 retry_lockid: 4343 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4344 if (rval) 4345 goto exit; 4346 4347 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4348 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4349 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4350 return QLA_SUCCESS; 4351 else 4352 return QLA_FUNCTION_FAILED; 4353 } 4354 4355 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4356 if (rval) 4357 goto exit; 4358 4359 if (o_drv_lockid == n_drv_lockid) { 4360 qla83xx_wait_logic(); 4361 goto retry_lockid; 4362 } else 4363 return QLA_SUCCESS; 4364 4365 exit: 4366 return rval; 4367 } 4368 4369 void 4370 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4371 { 4372 uint16_t options = (requester_id << 15) | BIT_6; 4373 uint32_t data; 4374 uint32_t lock_owner; 4375 struct qla_hw_data *ha = base_vha->hw; 4376 4377 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4378 retry_lock: 4379 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4380 == QLA_SUCCESS) { 4381 if (data) { 4382 /* Setting lock-id to our function-number */ 4383 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4384 ha->portnum); 4385 } else { 4386 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4387 &lock_owner); 4388 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4389 "Failed to acquire IDC lock, acquired by %d, " 4390 "retrying...\n", lock_owner); 4391 4392 /* Retry/Perform IDC-Lock recovery */ 4393 if (qla83xx_idc_lock_recovery(base_vha) 4394 == QLA_SUCCESS) { 4395 qla83xx_wait_logic(); 4396 goto retry_lock; 4397 } else 4398 ql_log(ql_log_warn, base_vha, 0xb075, 4399 "IDC Lock recovery FAILED.\n"); 4400 } 4401 4402 } 4403 4404 return; 4405 4406 /* XXX: IDC-lock implementation using access-control mbx */ 4407 retry_lock2: 4408 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4409 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4410 "Failed to acquire IDC lock. retrying...\n"); 4411 /* Retry/Perform IDC-Lock recovery */ 4412 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4413 qla83xx_wait_logic(); 4414 goto retry_lock2; 4415 } else 4416 ql_log(ql_log_warn, base_vha, 0xb076, 4417 "IDC Lock recovery FAILED.\n"); 4418 } 4419 4420 return; 4421 } 4422 4423 void 4424 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4425 { 4426 #if 0 4427 uint16_t options = (requester_id << 15) | BIT_7; 4428 #endif 4429 uint16_t retry; 4430 uint32_t data; 4431 struct qla_hw_data *ha = base_vha->hw; 4432 4433 /* IDC-unlock implementation using driver-unlock/lock-id 4434 * remote registers 4435 */ 4436 retry = 0; 4437 retry_unlock: 4438 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4439 == QLA_SUCCESS) { 4440 if (data == ha->portnum) { 4441 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4442 /* Clearing lock-id by setting 0xff */ 4443 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4444 } else if (retry < 10) { 4445 /* SV: XXX: IDC unlock retrying needed here? */ 4446 4447 /* Retry for IDC-unlock */ 4448 qla83xx_wait_logic(); 4449 retry++; 4450 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4451 "Failed to release IDC lock, retyring=%d\n", retry); 4452 goto retry_unlock; 4453 } 4454 } else if (retry < 10) { 4455 /* Retry for IDC-unlock */ 4456 qla83xx_wait_logic(); 4457 retry++; 4458 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4459 "Failed to read drv-lockid, retyring=%d\n", retry); 4460 goto retry_unlock; 4461 } 4462 4463 return; 4464 4465 #if 0 4466 /* XXX: IDC-unlock implementation using access-control mbx */ 4467 retry = 0; 4468 retry_unlock2: 4469 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4470 if (retry < 10) { 4471 /* Retry for IDC-unlock */ 4472 qla83xx_wait_logic(); 4473 retry++; 4474 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4475 "Failed to release IDC lock, retyring=%d\n", retry); 4476 goto retry_unlock2; 4477 } 4478 } 4479 4480 return; 4481 #endif 4482 } 4483 4484 int 4485 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4486 { 4487 int rval = QLA_SUCCESS; 4488 struct qla_hw_data *ha = vha->hw; 4489 uint32_t drv_presence; 4490 4491 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4492 if (rval == QLA_SUCCESS) { 4493 drv_presence |= (1 << ha->portnum); 4494 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4495 drv_presence); 4496 } 4497 4498 return rval; 4499 } 4500 4501 int 4502 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4503 { 4504 int rval = QLA_SUCCESS; 4505 4506 qla83xx_idc_lock(vha, 0); 4507 rval = __qla83xx_set_drv_presence(vha); 4508 qla83xx_idc_unlock(vha, 0); 4509 4510 return rval; 4511 } 4512 4513 int 4514 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4515 { 4516 int rval = QLA_SUCCESS; 4517 struct qla_hw_data *ha = vha->hw; 4518 uint32_t drv_presence; 4519 4520 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4521 if (rval == QLA_SUCCESS) { 4522 drv_presence &= ~(1 << ha->portnum); 4523 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4524 drv_presence); 4525 } 4526 4527 return rval; 4528 } 4529 4530 int 4531 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4532 { 4533 int rval = QLA_SUCCESS; 4534 4535 qla83xx_idc_lock(vha, 0); 4536 rval = __qla83xx_clear_drv_presence(vha); 4537 qla83xx_idc_unlock(vha, 0); 4538 4539 return rval; 4540 } 4541 4542 static void 4543 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4544 { 4545 struct qla_hw_data *ha = vha->hw; 4546 uint32_t drv_ack, drv_presence; 4547 unsigned long ack_timeout; 4548 4549 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4550 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4551 while (1) { 4552 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4553 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4554 if ((drv_ack & drv_presence) == drv_presence) 4555 break; 4556 4557 if (time_after_eq(jiffies, ack_timeout)) { 4558 ql_log(ql_log_warn, vha, 0xb067, 4559 "RESET ACK TIMEOUT! drv_presence=0x%x " 4560 "drv_ack=0x%x\n", drv_presence, drv_ack); 4561 /* 4562 * The function(s) which did not ack in time are forced 4563 * to withdraw any further participation in the IDC 4564 * reset. 4565 */ 4566 if (drv_ack != drv_presence) 4567 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4568 drv_ack); 4569 break; 4570 } 4571 4572 qla83xx_idc_unlock(vha, 0); 4573 msleep(1000); 4574 qla83xx_idc_lock(vha, 0); 4575 } 4576 4577 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4578 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4579 } 4580 4581 static int 4582 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4583 { 4584 int rval = QLA_SUCCESS; 4585 uint32_t idc_control; 4586 4587 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4588 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4589 4590 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4591 __qla83xx_get_idc_control(vha, &idc_control); 4592 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4593 __qla83xx_set_idc_control(vha, 0); 4594 4595 qla83xx_idc_unlock(vha, 0); 4596 rval = qla83xx_restart_nic_firmware(vha); 4597 qla83xx_idc_lock(vha, 0); 4598 4599 if (rval != QLA_SUCCESS) { 4600 ql_log(ql_log_fatal, vha, 0xb06a, 4601 "Failed to restart NIC f/w.\n"); 4602 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4603 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4604 } else { 4605 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4606 "Success in restarting nic f/w.\n"); 4607 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4608 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4609 } 4610 4611 return rval; 4612 } 4613 4614 /* Assumes idc_lock always held on entry */ 4615 int 4616 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4617 { 4618 struct qla_hw_data *ha = base_vha->hw; 4619 int rval = QLA_SUCCESS; 4620 unsigned long dev_init_timeout; 4621 uint32_t dev_state; 4622 4623 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4624 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4625 4626 while (1) { 4627 4628 if (time_after_eq(jiffies, dev_init_timeout)) { 4629 ql_log(ql_log_warn, base_vha, 0xb06e, 4630 "Initialization TIMEOUT!\n"); 4631 /* Init timeout. Disable further NIC Core 4632 * communication. 4633 */ 4634 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4635 QLA8XXX_DEV_FAILED); 4636 ql_log(ql_log_info, base_vha, 0xb06f, 4637 "HW State: FAILED.\n"); 4638 } 4639 4640 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4641 switch (dev_state) { 4642 case QLA8XXX_DEV_READY: 4643 if (ha->flags.nic_core_reset_owner) 4644 qla83xx_idc_audit(base_vha, 4645 IDC_AUDIT_COMPLETION); 4646 ha->flags.nic_core_reset_owner = 0; 4647 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4648 "Reset_owner reset by 0x%x.\n", 4649 ha->portnum); 4650 goto exit; 4651 case QLA8XXX_DEV_COLD: 4652 if (ha->flags.nic_core_reset_owner) 4653 rval = qla83xx_device_bootstrap(base_vha); 4654 else { 4655 /* Wait for AEN to change device-state */ 4656 qla83xx_idc_unlock(base_vha, 0); 4657 msleep(1000); 4658 qla83xx_idc_lock(base_vha, 0); 4659 } 4660 break; 4661 case QLA8XXX_DEV_INITIALIZING: 4662 /* Wait for AEN to change device-state */ 4663 qla83xx_idc_unlock(base_vha, 0); 4664 msleep(1000); 4665 qla83xx_idc_lock(base_vha, 0); 4666 break; 4667 case QLA8XXX_DEV_NEED_RESET: 4668 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4669 qla83xx_need_reset_handler(base_vha); 4670 else { 4671 /* Wait for AEN to change device-state */ 4672 qla83xx_idc_unlock(base_vha, 0); 4673 msleep(1000); 4674 qla83xx_idc_lock(base_vha, 0); 4675 } 4676 /* reset timeout value after need reset handler */ 4677 dev_init_timeout = jiffies + 4678 (ha->fcoe_dev_init_timeout * HZ); 4679 break; 4680 case QLA8XXX_DEV_NEED_QUIESCENT: 4681 /* XXX: DEBUG for now */ 4682 qla83xx_idc_unlock(base_vha, 0); 4683 msleep(1000); 4684 qla83xx_idc_lock(base_vha, 0); 4685 break; 4686 case QLA8XXX_DEV_QUIESCENT: 4687 /* XXX: DEBUG for now */ 4688 if (ha->flags.quiesce_owner) 4689 goto exit; 4690 4691 qla83xx_idc_unlock(base_vha, 0); 4692 msleep(1000); 4693 qla83xx_idc_lock(base_vha, 0); 4694 dev_init_timeout = jiffies + 4695 (ha->fcoe_dev_init_timeout * HZ); 4696 break; 4697 case QLA8XXX_DEV_FAILED: 4698 if (ha->flags.nic_core_reset_owner) 4699 qla83xx_idc_audit(base_vha, 4700 IDC_AUDIT_COMPLETION); 4701 ha->flags.nic_core_reset_owner = 0; 4702 __qla83xx_clear_drv_presence(base_vha); 4703 qla83xx_idc_unlock(base_vha, 0); 4704 qla8xxx_dev_failed_handler(base_vha); 4705 rval = QLA_FUNCTION_FAILED; 4706 qla83xx_idc_lock(base_vha, 0); 4707 goto exit; 4708 case QLA8XXX_BAD_VALUE: 4709 qla83xx_idc_unlock(base_vha, 0); 4710 msleep(1000); 4711 qla83xx_idc_lock(base_vha, 0); 4712 break; 4713 default: 4714 ql_log(ql_log_warn, base_vha, 0xb071, 4715 "Unknown Device State: %x.\n", dev_state); 4716 qla83xx_idc_unlock(base_vha, 0); 4717 qla8xxx_dev_failed_handler(base_vha); 4718 rval = QLA_FUNCTION_FAILED; 4719 qla83xx_idc_lock(base_vha, 0); 4720 goto exit; 4721 } 4722 } 4723 4724 exit: 4725 return rval; 4726 } 4727 4728 void 4729 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4730 { 4731 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4732 board_disable); 4733 struct pci_dev *pdev = ha->pdev; 4734 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4735 4736 ql_log(ql_log_warn, base_vha, 0x015b, 4737 "Disabling adapter.\n"); 4738 4739 set_bit(UNLOADING, &base_vha->dpc_flags); 4740 4741 qla2x00_delete_all_vps(ha, base_vha); 4742 4743 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4744 4745 qla2x00_dfs_remove(base_vha); 4746 4747 qla84xx_put_chip(base_vha); 4748 4749 if (base_vha->timer_active) 4750 qla2x00_stop_timer(base_vha); 4751 4752 base_vha->flags.online = 0; 4753 4754 qla2x00_destroy_deferred_work(ha); 4755 4756 /* 4757 * Do not try to stop beacon blink as it will issue a mailbox 4758 * command. 4759 */ 4760 qla2x00_free_sysfs_attr(base_vha, false); 4761 4762 fc_remove_host(base_vha->host); 4763 4764 scsi_remove_host(base_vha->host); 4765 4766 base_vha->flags.init_done = 0; 4767 qla25xx_delete_queues(base_vha); 4768 qla2x00_free_irqs(base_vha); 4769 qla2x00_free_fcports(base_vha); 4770 qla2x00_mem_free(ha); 4771 qla82xx_md_free(base_vha); 4772 qla2x00_free_queues(ha); 4773 4774 qla2x00_unmap_iobases(ha); 4775 4776 pci_release_selected_regions(ha->pdev, ha->bars); 4777 pci_disable_pcie_error_reporting(pdev); 4778 pci_disable_device(pdev); 4779 4780 /* 4781 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 4782 */ 4783 } 4784 4785 /************************************************************************** 4786 * qla2x00_do_dpc 4787 * This kernel thread is a task that is schedule by the interrupt handler 4788 * to perform the background processing for interrupts. 4789 * 4790 * Notes: 4791 * This task always run in the context of a kernel thread. It 4792 * is kick-off by the driver's detect code and starts up 4793 * up one per adapter. It immediately goes to sleep and waits for 4794 * some fibre event. When either the interrupt handler or 4795 * the timer routine detects a event it will one of the task 4796 * bits then wake us up. 4797 **************************************************************************/ 4798 static int 4799 qla2x00_do_dpc(void *data) 4800 { 4801 scsi_qla_host_t *base_vha; 4802 struct qla_hw_data *ha; 4803 4804 ha = (struct qla_hw_data *)data; 4805 base_vha = pci_get_drvdata(ha->pdev); 4806 4807 set_user_nice(current, MIN_NICE); 4808 4809 set_current_state(TASK_INTERRUPTIBLE); 4810 while (!kthread_should_stop()) { 4811 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4812 "DPC handler sleeping.\n"); 4813 4814 schedule(); 4815 4816 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4817 goto end_loop; 4818 4819 if (ha->flags.eeh_busy) { 4820 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4821 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4822 goto end_loop; 4823 } 4824 4825 ha->dpc_active = 1; 4826 4827 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4828 "DPC handler waking up, dpc_flags=0x%lx.\n", 4829 base_vha->dpc_flags); 4830 4831 qla2x00_do_work(base_vha); 4832 4833 if (IS_P3P_TYPE(ha)) { 4834 if (IS_QLA8044(ha)) { 4835 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4836 &base_vha->dpc_flags)) { 4837 qla8044_idc_lock(ha); 4838 qla8044_wr_direct(base_vha, 4839 QLA8044_CRB_DEV_STATE_INDEX, 4840 QLA8XXX_DEV_FAILED); 4841 qla8044_idc_unlock(ha); 4842 ql_log(ql_log_info, base_vha, 0x4004, 4843 "HW State: FAILED.\n"); 4844 qla8044_device_state_handler(base_vha); 4845 continue; 4846 } 4847 4848 } else { 4849 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4850 &base_vha->dpc_flags)) { 4851 qla82xx_idc_lock(ha); 4852 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4853 QLA8XXX_DEV_FAILED); 4854 qla82xx_idc_unlock(ha); 4855 ql_log(ql_log_info, base_vha, 0x0151, 4856 "HW State: FAILED.\n"); 4857 qla82xx_device_state_handler(base_vha); 4858 continue; 4859 } 4860 } 4861 4862 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 4863 &base_vha->dpc_flags)) { 4864 4865 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 4866 "FCoE context reset scheduled.\n"); 4867 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4868 &base_vha->dpc_flags))) { 4869 if (qla82xx_fcoe_ctx_reset(base_vha)) { 4870 /* FCoE-ctx reset failed. 4871 * Escalate to chip-reset 4872 */ 4873 set_bit(ISP_ABORT_NEEDED, 4874 &base_vha->dpc_flags); 4875 } 4876 clear_bit(ABORT_ISP_ACTIVE, 4877 &base_vha->dpc_flags); 4878 } 4879 4880 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 4881 "FCoE context reset end.\n"); 4882 } 4883 } else if (IS_QLAFX00(ha)) { 4884 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4885 &base_vha->dpc_flags)) { 4886 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 4887 "Firmware Reset Recovery\n"); 4888 if (qlafx00_reset_initialize(base_vha)) { 4889 /* Failed. Abort isp later. */ 4890 if (!test_bit(UNLOADING, 4891 &base_vha->dpc_flags)) { 4892 set_bit(ISP_UNRECOVERABLE, 4893 &base_vha->dpc_flags); 4894 ql_dbg(ql_dbg_dpc, base_vha, 4895 0x4021, 4896 "Reset Recovery Failed\n"); 4897 } 4898 } 4899 } 4900 4901 if (test_and_clear_bit(FX00_TARGET_SCAN, 4902 &base_vha->dpc_flags)) { 4903 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 4904 "ISPFx00 Target Scan scheduled\n"); 4905 if (qlafx00_rescan_isp(base_vha)) { 4906 if (!test_bit(UNLOADING, 4907 &base_vha->dpc_flags)) 4908 set_bit(ISP_UNRECOVERABLE, 4909 &base_vha->dpc_flags); 4910 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 4911 "ISPFx00 Target Scan Failed\n"); 4912 } 4913 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 4914 "ISPFx00 Target Scan End\n"); 4915 } 4916 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 4917 &base_vha->dpc_flags)) { 4918 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 4919 "ISPFx00 Host Info resend scheduled\n"); 4920 qlafx00_fx_disc(base_vha, 4921 &base_vha->hw->mr.fcport, 4922 FXDISC_REG_HOST_INFO); 4923 } 4924 } 4925 4926 if (test_and_clear_bit(ISP_ABORT_NEEDED, 4927 &base_vha->dpc_flags)) { 4928 4929 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 4930 "ISP abort scheduled.\n"); 4931 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4932 &base_vha->dpc_flags))) { 4933 4934 if (ha->isp_ops->abort_isp(base_vha)) { 4935 /* failed. retry later */ 4936 set_bit(ISP_ABORT_NEEDED, 4937 &base_vha->dpc_flags); 4938 } 4939 clear_bit(ABORT_ISP_ACTIVE, 4940 &base_vha->dpc_flags); 4941 } 4942 4943 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 4944 "ISP abort end.\n"); 4945 } 4946 4947 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 4948 &base_vha->dpc_flags)) { 4949 qla2x00_update_fcports(base_vha); 4950 } 4951 4952 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 4953 int ret; 4954 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 4955 if (ret != QLA_SUCCESS) 4956 ql_log(ql_log_warn, base_vha, 0x121, 4957 "Failed to enable receiving of RSCN " 4958 "requests: 0x%x.\n", ret); 4959 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 4960 } 4961 4962 if (IS_QLAFX00(ha)) 4963 goto loop_resync_check; 4964 4965 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 4966 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 4967 "Quiescence mode scheduled.\n"); 4968 if (IS_P3P_TYPE(ha)) { 4969 if (IS_QLA82XX(ha)) 4970 qla82xx_device_state_handler(base_vha); 4971 if (IS_QLA8044(ha)) 4972 qla8044_device_state_handler(base_vha); 4973 clear_bit(ISP_QUIESCE_NEEDED, 4974 &base_vha->dpc_flags); 4975 if (!ha->flags.quiesce_owner) { 4976 qla2x00_perform_loop_resync(base_vha); 4977 if (IS_QLA82XX(ha)) { 4978 qla82xx_idc_lock(ha); 4979 qla82xx_clear_qsnt_ready( 4980 base_vha); 4981 qla82xx_idc_unlock(ha); 4982 } else if (IS_QLA8044(ha)) { 4983 qla8044_idc_lock(ha); 4984 qla8044_clear_qsnt_ready( 4985 base_vha); 4986 qla8044_idc_unlock(ha); 4987 } 4988 } 4989 } else { 4990 clear_bit(ISP_QUIESCE_NEEDED, 4991 &base_vha->dpc_flags); 4992 qla2x00_quiesce_io(base_vha); 4993 } 4994 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 4995 "Quiescence mode end.\n"); 4996 } 4997 4998 if (test_and_clear_bit(RESET_MARKER_NEEDED, 4999 &base_vha->dpc_flags) && 5000 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5001 5002 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5003 "Reset marker scheduled.\n"); 5004 qla2x00_rst_aen(base_vha); 5005 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5006 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5007 "Reset marker end.\n"); 5008 } 5009 5010 /* Retry each device up to login retry count */ 5011 if ((test_and_clear_bit(RELOGIN_NEEDED, 5012 &base_vha->dpc_flags)) && 5013 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5014 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5015 5016 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5017 "Relogin scheduled.\n"); 5018 qla2x00_relogin(base_vha); 5019 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5020 "Relogin end.\n"); 5021 } 5022 loop_resync_check: 5023 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5024 &base_vha->dpc_flags)) { 5025 5026 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5027 "Loop resync scheduled.\n"); 5028 5029 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5030 &base_vha->dpc_flags))) { 5031 5032 qla2x00_loop_resync(base_vha); 5033 5034 clear_bit(LOOP_RESYNC_ACTIVE, 5035 &base_vha->dpc_flags); 5036 } 5037 5038 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5039 "Loop resync end.\n"); 5040 } 5041 5042 if (IS_QLAFX00(ha)) 5043 goto intr_on_check; 5044 5045 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5046 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5047 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5048 qla2xxx_flash_npiv_conf(base_vha); 5049 } 5050 5051 intr_on_check: 5052 if (!ha->interrupts_on) 5053 ha->isp_ops->enable_intrs(ha); 5054 5055 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5056 &base_vha->dpc_flags)) { 5057 if (ha->beacon_blink_led == 1) 5058 ha->isp_ops->beacon_blink(base_vha); 5059 } 5060 5061 if (!IS_QLAFX00(ha)) 5062 qla2x00_do_dpc_all_vps(base_vha); 5063 5064 ha->dpc_active = 0; 5065 end_loop: 5066 set_current_state(TASK_INTERRUPTIBLE); 5067 } /* End of while(1) */ 5068 __set_current_state(TASK_RUNNING); 5069 5070 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5071 "DPC handler exiting.\n"); 5072 5073 /* 5074 * Make sure that nobody tries to wake us up again. 5075 */ 5076 ha->dpc_active = 0; 5077 5078 /* Cleanup any residual CTX SRBs. */ 5079 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5080 5081 return 0; 5082 } 5083 5084 void 5085 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5086 { 5087 struct qla_hw_data *ha = vha->hw; 5088 struct task_struct *t = ha->dpc_thread; 5089 5090 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5091 wake_up_process(t); 5092 } 5093 5094 /* 5095 * qla2x00_rst_aen 5096 * Processes asynchronous reset. 5097 * 5098 * Input: 5099 * ha = adapter block pointer. 5100 */ 5101 static void 5102 qla2x00_rst_aen(scsi_qla_host_t *vha) 5103 { 5104 if (vha->flags.online && !vha->flags.reset_active && 5105 !atomic_read(&vha->loop_down_timer) && 5106 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5107 do { 5108 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5109 5110 /* 5111 * Issue marker command only when we are going to start 5112 * the I/O. 5113 */ 5114 vha->marker_needed = 1; 5115 } while (!atomic_read(&vha->loop_down_timer) && 5116 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5117 } 5118 } 5119 5120 /************************************************************************** 5121 * qla2x00_timer 5122 * 5123 * Description: 5124 * One second timer 5125 * 5126 * Context: Interrupt 5127 ***************************************************************************/ 5128 void 5129 qla2x00_timer(scsi_qla_host_t *vha) 5130 { 5131 unsigned long cpu_flags = 0; 5132 int start_dpc = 0; 5133 int index; 5134 srb_t *sp; 5135 uint16_t w; 5136 struct qla_hw_data *ha = vha->hw; 5137 struct req_que *req; 5138 5139 if (ha->flags.eeh_busy) { 5140 ql_dbg(ql_dbg_timer, vha, 0x6000, 5141 "EEH = %d, restarting timer.\n", 5142 ha->flags.eeh_busy); 5143 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5144 return; 5145 } 5146 5147 /* 5148 * Hardware read to raise pending EEH errors during mailbox waits. If 5149 * the read returns -1 then disable the board. 5150 */ 5151 if (!pci_channel_offline(ha->pdev)) { 5152 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5153 qla2x00_check_reg16_for_disconnect(vha, w); 5154 } 5155 5156 /* Make sure qla82xx_watchdog is run only for physical port */ 5157 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5158 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5159 start_dpc++; 5160 if (IS_QLA82XX(ha)) 5161 qla82xx_watchdog(vha); 5162 else if (IS_QLA8044(ha)) 5163 qla8044_watchdog(vha); 5164 } 5165 5166 if (!vha->vp_idx && IS_QLAFX00(ha)) 5167 qlafx00_timer_routine(vha); 5168 5169 /* Loop down handler. */ 5170 if (atomic_read(&vha->loop_down_timer) > 0 && 5171 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5172 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5173 && vha->flags.online) { 5174 5175 if (atomic_read(&vha->loop_down_timer) == 5176 vha->loop_down_abort_time) { 5177 5178 ql_log(ql_log_info, vha, 0x6008, 5179 "Loop down - aborting the queues before time expires.\n"); 5180 5181 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5182 atomic_set(&vha->loop_state, LOOP_DEAD); 5183 5184 /* 5185 * Schedule an ISP abort to return any FCP2-device 5186 * commands. 5187 */ 5188 /* NPIV - scan physical port only */ 5189 if (!vha->vp_idx) { 5190 spin_lock_irqsave(&ha->hardware_lock, 5191 cpu_flags); 5192 req = ha->req_q_map[0]; 5193 for (index = 1; 5194 index < req->num_outstanding_cmds; 5195 index++) { 5196 fc_port_t *sfcp; 5197 5198 sp = req->outstanding_cmds[index]; 5199 if (!sp) 5200 continue; 5201 if (sp->type != SRB_SCSI_CMD) 5202 continue; 5203 sfcp = sp->fcport; 5204 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5205 continue; 5206 5207 if (IS_QLA82XX(ha)) 5208 set_bit(FCOE_CTX_RESET_NEEDED, 5209 &vha->dpc_flags); 5210 else 5211 set_bit(ISP_ABORT_NEEDED, 5212 &vha->dpc_flags); 5213 break; 5214 } 5215 spin_unlock_irqrestore(&ha->hardware_lock, 5216 cpu_flags); 5217 } 5218 start_dpc++; 5219 } 5220 5221 /* if the loop has been down for 4 minutes, reinit adapter */ 5222 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5223 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5224 ql_log(ql_log_warn, vha, 0x6009, 5225 "Loop down - aborting ISP.\n"); 5226 5227 if (IS_QLA82XX(ha)) 5228 set_bit(FCOE_CTX_RESET_NEEDED, 5229 &vha->dpc_flags); 5230 else 5231 set_bit(ISP_ABORT_NEEDED, 5232 &vha->dpc_flags); 5233 } 5234 } 5235 ql_dbg(ql_dbg_timer, vha, 0x600a, 5236 "Loop down - seconds remaining %d.\n", 5237 atomic_read(&vha->loop_down_timer)); 5238 } 5239 /* Check if beacon LED needs to be blinked for physical host only */ 5240 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5241 /* There is no beacon_blink function for ISP82xx */ 5242 if (!IS_P3P_TYPE(ha)) { 5243 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5244 start_dpc++; 5245 } 5246 } 5247 5248 /* Process any deferred work. */ 5249 if (!list_empty(&vha->work_list)) 5250 start_dpc++; 5251 5252 /* Schedule the DPC routine if needed */ 5253 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5254 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5255 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5256 start_dpc || 5257 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5258 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5259 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5260 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5261 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5262 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5263 ql_dbg(ql_dbg_timer, vha, 0x600b, 5264 "isp_abort_needed=%d loop_resync_needed=%d " 5265 "fcport_update_needed=%d start_dpc=%d " 5266 "reset_marker_needed=%d", 5267 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5268 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5269 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5270 start_dpc, 5271 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5272 ql_dbg(ql_dbg_timer, vha, 0x600c, 5273 "beacon_blink_needed=%d isp_unrecoverable=%d " 5274 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5275 "relogin_needed=%d.\n", 5276 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5277 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5278 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5279 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5280 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5281 qla2xxx_wake_dpc(vha); 5282 } 5283 5284 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5285 } 5286 5287 /* Firmware interface routines. */ 5288 5289 #define FW_BLOBS 11 5290 #define FW_ISP21XX 0 5291 #define FW_ISP22XX 1 5292 #define FW_ISP2300 2 5293 #define FW_ISP2322 3 5294 #define FW_ISP24XX 4 5295 #define FW_ISP25XX 5 5296 #define FW_ISP81XX 6 5297 #define FW_ISP82XX 7 5298 #define FW_ISP2031 8 5299 #define FW_ISP8031 9 5300 #define FW_ISP27XX 10 5301 5302 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5303 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5304 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5305 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5306 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5307 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5308 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5309 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5310 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5311 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5312 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5313 5314 5315 static DEFINE_MUTEX(qla_fw_lock); 5316 5317 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5318 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5319 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5320 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5321 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5322 { .name = FW_FILE_ISP24XX, }, 5323 { .name = FW_FILE_ISP25XX, }, 5324 { .name = FW_FILE_ISP81XX, }, 5325 { .name = FW_FILE_ISP82XX, }, 5326 { .name = FW_FILE_ISP2031, }, 5327 { .name = FW_FILE_ISP8031, }, 5328 { .name = FW_FILE_ISP27XX, }, 5329 }; 5330 5331 struct fw_blob * 5332 qla2x00_request_firmware(scsi_qla_host_t *vha) 5333 { 5334 struct qla_hw_data *ha = vha->hw; 5335 struct fw_blob *blob; 5336 5337 if (IS_QLA2100(ha)) { 5338 blob = &qla_fw_blobs[FW_ISP21XX]; 5339 } else if (IS_QLA2200(ha)) { 5340 blob = &qla_fw_blobs[FW_ISP22XX]; 5341 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5342 blob = &qla_fw_blobs[FW_ISP2300]; 5343 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5344 blob = &qla_fw_blobs[FW_ISP2322]; 5345 } else if (IS_QLA24XX_TYPE(ha)) { 5346 blob = &qla_fw_blobs[FW_ISP24XX]; 5347 } else if (IS_QLA25XX(ha)) { 5348 blob = &qla_fw_blobs[FW_ISP25XX]; 5349 } else if (IS_QLA81XX(ha)) { 5350 blob = &qla_fw_blobs[FW_ISP81XX]; 5351 } else if (IS_QLA82XX(ha)) { 5352 blob = &qla_fw_blobs[FW_ISP82XX]; 5353 } else if (IS_QLA2031(ha)) { 5354 blob = &qla_fw_blobs[FW_ISP2031]; 5355 } else if (IS_QLA8031(ha)) { 5356 blob = &qla_fw_blobs[FW_ISP8031]; 5357 } else if (IS_QLA27XX(ha)) { 5358 blob = &qla_fw_blobs[FW_ISP27XX]; 5359 } else { 5360 return NULL; 5361 } 5362 5363 mutex_lock(&qla_fw_lock); 5364 if (blob->fw) 5365 goto out; 5366 5367 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5368 ql_log(ql_log_warn, vha, 0x0063, 5369 "Failed to load firmware image (%s).\n", blob->name); 5370 blob->fw = NULL; 5371 blob = NULL; 5372 goto out; 5373 } 5374 5375 out: 5376 mutex_unlock(&qla_fw_lock); 5377 return blob; 5378 } 5379 5380 static void 5381 qla2x00_release_firmware(void) 5382 { 5383 int idx; 5384 5385 mutex_lock(&qla_fw_lock); 5386 for (idx = 0; idx < FW_BLOBS; idx++) 5387 release_firmware(qla_fw_blobs[idx].fw); 5388 mutex_unlock(&qla_fw_lock); 5389 } 5390 5391 static pci_ers_result_t 5392 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5393 { 5394 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5395 struct qla_hw_data *ha = vha->hw; 5396 5397 ql_dbg(ql_dbg_aer, vha, 0x9000, 5398 "PCI error detected, state %x.\n", state); 5399 5400 switch (state) { 5401 case pci_channel_io_normal: 5402 ha->flags.eeh_busy = 0; 5403 return PCI_ERS_RESULT_CAN_RECOVER; 5404 case pci_channel_io_frozen: 5405 ha->flags.eeh_busy = 1; 5406 /* For ISP82XX complete any pending mailbox cmd */ 5407 if (IS_QLA82XX(ha)) { 5408 ha->flags.isp82xx_fw_hung = 1; 5409 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5410 qla82xx_clear_pending_mbx(vha); 5411 } 5412 qla2x00_free_irqs(vha); 5413 pci_disable_device(pdev); 5414 /* Return back all IOs */ 5415 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5416 return PCI_ERS_RESULT_NEED_RESET; 5417 case pci_channel_io_perm_failure: 5418 ha->flags.pci_channel_io_perm_failure = 1; 5419 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5420 return PCI_ERS_RESULT_DISCONNECT; 5421 } 5422 return PCI_ERS_RESULT_NEED_RESET; 5423 } 5424 5425 static pci_ers_result_t 5426 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5427 { 5428 int risc_paused = 0; 5429 uint32_t stat; 5430 unsigned long flags; 5431 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5432 struct qla_hw_data *ha = base_vha->hw; 5433 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5434 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5435 5436 if (IS_QLA82XX(ha)) 5437 return PCI_ERS_RESULT_RECOVERED; 5438 5439 spin_lock_irqsave(&ha->hardware_lock, flags); 5440 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5441 stat = RD_REG_DWORD(®->hccr); 5442 if (stat & HCCR_RISC_PAUSE) 5443 risc_paused = 1; 5444 } else if (IS_QLA23XX(ha)) { 5445 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5446 if (stat & HSR_RISC_PAUSED) 5447 risc_paused = 1; 5448 } else if (IS_FWI2_CAPABLE(ha)) { 5449 stat = RD_REG_DWORD(®24->host_status); 5450 if (stat & HSRX_RISC_PAUSED) 5451 risc_paused = 1; 5452 } 5453 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5454 5455 if (risc_paused) { 5456 ql_log(ql_log_info, base_vha, 0x9003, 5457 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5458 ha->isp_ops->fw_dump(base_vha, 0); 5459 5460 return PCI_ERS_RESULT_NEED_RESET; 5461 } else 5462 return PCI_ERS_RESULT_RECOVERED; 5463 } 5464 5465 static uint32_t 5466 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5467 { 5468 uint32_t rval = QLA_FUNCTION_FAILED; 5469 uint32_t drv_active = 0; 5470 struct qla_hw_data *ha = base_vha->hw; 5471 int fn; 5472 struct pci_dev *other_pdev = NULL; 5473 5474 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5475 "Entered %s.\n", __func__); 5476 5477 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5478 5479 if (base_vha->flags.online) { 5480 /* Abort all outstanding commands, 5481 * so as to be requeued later */ 5482 qla2x00_abort_isp_cleanup(base_vha); 5483 } 5484 5485 5486 fn = PCI_FUNC(ha->pdev->devfn); 5487 while (fn > 0) { 5488 fn--; 5489 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5490 "Finding pci device at function = 0x%x.\n", fn); 5491 other_pdev = 5492 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5493 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5494 fn)); 5495 5496 if (!other_pdev) 5497 continue; 5498 if (atomic_read(&other_pdev->enable_cnt)) { 5499 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5500 "Found PCI func available and enable at 0x%x.\n", 5501 fn); 5502 pci_dev_put(other_pdev); 5503 break; 5504 } 5505 pci_dev_put(other_pdev); 5506 } 5507 5508 if (!fn) { 5509 /* Reset owner */ 5510 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5511 "This devfn is reset owner = 0x%x.\n", 5512 ha->pdev->devfn); 5513 qla82xx_idc_lock(ha); 5514 5515 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5516 QLA8XXX_DEV_INITIALIZING); 5517 5518 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5519 QLA82XX_IDC_VERSION); 5520 5521 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5522 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5523 "drv_active = 0x%x.\n", drv_active); 5524 5525 qla82xx_idc_unlock(ha); 5526 /* Reset if device is not already reset 5527 * drv_active would be 0 if a reset has already been done 5528 */ 5529 if (drv_active) 5530 rval = qla82xx_start_firmware(base_vha); 5531 else 5532 rval = QLA_SUCCESS; 5533 qla82xx_idc_lock(ha); 5534 5535 if (rval != QLA_SUCCESS) { 5536 ql_log(ql_log_info, base_vha, 0x900b, 5537 "HW State: FAILED.\n"); 5538 qla82xx_clear_drv_active(ha); 5539 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5540 QLA8XXX_DEV_FAILED); 5541 } else { 5542 ql_log(ql_log_info, base_vha, 0x900c, 5543 "HW State: READY.\n"); 5544 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5545 QLA8XXX_DEV_READY); 5546 qla82xx_idc_unlock(ha); 5547 ha->flags.isp82xx_fw_hung = 0; 5548 rval = qla82xx_restart_isp(base_vha); 5549 qla82xx_idc_lock(ha); 5550 /* Clear driver state register */ 5551 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5552 qla82xx_set_drv_active(base_vha); 5553 } 5554 qla82xx_idc_unlock(ha); 5555 } else { 5556 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5557 "This devfn is not reset owner = 0x%x.\n", 5558 ha->pdev->devfn); 5559 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5560 QLA8XXX_DEV_READY)) { 5561 ha->flags.isp82xx_fw_hung = 0; 5562 rval = qla82xx_restart_isp(base_vha); 5563 qla82xx_idc_lock(ha); 5564 qla82xx_set_drv_active(base_vha); 5565 qla82xx_idc_unlock(ha); 5566 } 5567 } 5568 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5569 5570 return rval; 5571 } 5572 5573 static pci_ers_result_t 5574 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5575 { 5576 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5577 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5578 struct qla_hw_data *ha = base_vha->hw; 5579 struct rsp_que *rsp; 5580 int rc, retries = 10; 5581 5582 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5583 "Slot Reset.\n"); 5584 5585 /* Workaround: qla2xxx driver which access hardware earlier 5586 * needs error state to be pci_channel_io_online. 5587 * Otherwise mailbox command timesout. 5588 */ 5589 pdev->error_state = pci_channel_io_normal; 5590 5591 pci_restore_state(pdev); 5592 5593 /* pci_restore_state() clears the saved_state flag of the device 5594 * save restored state which resets saved_state flag 5595 */ 5596 pci_save_state(pdev); 5597 5598 if (ha->mem_only) 5599 rc = pci_enable_device_mem(pdev); 5600 else 5601 rc = pci_enable_device(pdev); 5602 5603 if (rc) { 5604 ql_log(ql_log_warn, base_vha, 0x9005, 5605 "Can't re-enable PCI device after reset.\n"); 5606 goto exit_slot_reset; 5607 } 5608 5609 rsp = ha->rsp_q_map[0]; 5610 if (qla2x00_request_irqs(ha, rsp)) 5611 goto exit_slot_reset; 5612 5613 if (ha->isp_ops->pci_config(base_vha)) 5614 goto exit_slot_reset; 5615 5616 if (IS_QLA82XX(ha)) { 5617 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5618 ret = PCI_ERS_RESULT_RECOVERED; 5619 goto exit_slot_reset; 5620 } else 5621 goto exit_slot_reset; 5622 } 5623 5624 while (ha->flags.mbox_busy && retries--) 5625 msleep(1000); 5626 5627 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5628 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5629 ret = PCI_ERS_RESULT_RECOVERED; 5630 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5631 5632 5633 exit_slot_reset: 5634 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5635 "slot_reset return %x.\n", ret); 5636 5637 return ret; 5638 } 5639 5640 static void 5641 qla2xxx_pci_resume(struct pci_dev *pdev) 5642 { 5643 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5644 struct qla_hw_data *ha = base_vha->hw; 5645 int ret; 5646 5647 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5648 "pci_resume.\n"); 5649 5650 ret = qla2x00_wait_for_hba_online(base_vha); 5651 if (ret != QLA_SUCCESS) { 5652 ql_log(ql_log_fatal, base_vha, 0x9002, 5653 "The device failed to resume I/O from slot/link_reset.\n"); 5654 } 5655 5656 pci_cleanup_aer_uncorrect_error_status(pdev); 5657 5658 ha->flags.eeh_busy = 0; 5659 } 5660 5661 static void 5662 qla83xx_disable_laser(scsi_qla_host_t *vha) 5663 { 5664 uint32_t reg, data, fn; 5665 struct qla_hw_data *ha = vha->hw; 5666 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5667 5668 /* pci func #/port # */ 5669 ql_dbg(ql_dbg_init, vha, 0x004b, 5670 "Disabling Laser for hba: %p\n", vha); 5671 5672 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5673 (BIT_15|BIT_14|BIT_13|BIT_12)); 5674 5675 fn = (fn >> 12); 5676 5677 if (fn & 1) 5678 reg = PORT_1_2031; 5679 else 5680 reg = PORT_0_2031; 5681 5682 data = LASER_OFF_2031; 5683 5684 qla83xx_wr_reg(vha, reg, data); 5685 } 5686 5687 static const struct pci_error_handlers qla2xxx_err_handler = { 5688 .error_detected = qla2xxx_pci_error_detected, 5689 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5690 .slot_reset = qla2xxx_pci_slot_reset, 5691 .resume = qla2xxx_pci_resume, 5692 }; 5693 5694 static struct pci_device_id qla2xxx_pci_tbl[] = { 5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 5717 { 0 }, 5718 }; 5719 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5720 5721 static struct pci_driver qla2xxx_pci_driver = { 5722 .name = QLA2XXX_DRIVER_NAME, 5723 .driver = { 5724 .owner = THIS_MODULE, 5725 }, 5726 .id_table = qla2xxx_pci_tbl, 5727 .probe = qla2x00_probe_one, 5728 .remove = qla2x00_remove_one, 5729 .shutdown = qla2x00_shutdown, 5730 .err_handler = &qla2xxx_err_handler, 5731 }; 5732 5733 static const struct file_operations apidev_fops = { 5734 .owner = THIS_MODULE, 5735 .llseek = noop_llseek, 5736 }; 5737 5738 /** 5739 * qla2x00_module_init - Module initialization. 5740 **/ 5741 static int __init 5742 qla2x00_module_init(void) 5743 { 5744 int ret = 0; 5745 5746 /* Allocate cache for SRBs. */ 5747 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5748 SLAB_HWCACHE_ALIGN, NULL); 5749 if (srb_cachep == NULL) { 5750 ql_log(ql_log_fatal, NULL, 0x0001, 5751 "Unable to allocate SRB cache...Failing load!.\n"); 5752 return -ENOMEM; 5753 } 5754 5755 /* Initialize target kmem_cache and mem_pools */ 5756 ret = qlt_init(); 5757 if (ret < 0) { 5758 kmem_cache_destroy(srb_cachep); 5759 return ret; 5760 } else if (ret > 0) { 5761 /* 5762 * If initiator mode is explictly disabled by qlt_init(), 5763 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5764 * performing scsi_scan_target() during LOOP UP event. 5765 */ 5766 qla2xxx_transport_functions.disable_target_scan = 1; 5767 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5768 } 5769 5770 /* Derive version string. */ 5771 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5772 if (ql2xextended_error_logging) 5773 strcat(qla2x00_version_str, "-debug"); 5774 5775 qla2xxx_transport_template = 5776 fc_attach_transport(&qla2xxx_transport_functions); 5777 if (!qla2xxx_transport_template) { 5778 kmem_cache_destroy(srb_cachep); 5779 ql_log(ql_log_fatal, NULL, 0x0002, 5780 "fc_attach_transport failed...Failing load!.\n"); 5781 qlt_exit(); 5782 return -ENODEV; 5783 } 5784 5785 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5786 if (apidev_major < 0) { 5787 ql_log(ql_log_fatal, NULL, 0x0003, 5788 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5789 } 5790 5791 qla2xxx_transport_vport_template = 5792 fc_attach_transport(&qla2xxx_transport_vport_functions); 5793 if (!qla2xxx_transport_vport_template) { 5794 kmem_cache_destroy(srb_cachep); 5795 qlt_exit(); 5796 fc_release_transport(qla2xxx_transport_template); 5797 ql_log(ql_log_fatal, NULL, 0x0004, 5798 "fc_attach_transport vport failed...Failing load!.\n"); 5799 return -ENODEV; 5800 } 5801 ql_log(ql_log_info, NULL, 0x0005, 5802 "QLogic Fibre Channel HBA Driver: %s.\n", 5803 qla2x00_version_str); 5804 ret = pci_register_driver(&qla2xxx_pci_driver); 5805 if (ret) { 5806 kmem_cache_destroy(srb_cachep); 5807 qlt_exit(); 5808 fc_release_transport(qla2xxx_transport_template); 5809 fc_release_transport(qla2xxx_transport_vport_template); 5810 ql_log(ql_log_fatal, NULL, 0x0006, 5811 "pci_register_driver failed...ret=%d Failing load!.\n", 5812 ret); 5813 } 5814 return ret; 5815 } 5816 5817 /** 5818 * qla2x00_module_exit - Module cleanup. 5819 **/ 5820 static void __exit 5821 qla2x00_module_exit(void) 5822 { 5823 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5824 pci_unregister_driver(&qla2xxx_pci_driver); 5825 qla2x00_release_firmware(); 5826 kmem_cache_destroy(srb_cachep); 5827 qlt_exit(); 5828 if (ctx_cachep) 5829 kmem_cache_destroy(ctx_cachep); 5830 fc_release_transport(qla2xxx_transport_template); 5831 fc_release_transport(qla2xxx_transport_vport_template); 5832 } 5833 5834 module_init(qla2x00_module_init); 5835 module_exit(qla2x00_module_exit); 5836 5837 MODULE_AUTHOR("QLogic Corporation"); 5838 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5839 MODULE_LICENSE("GPL"); 5840 MODULE_VERSION(QLA2XXX_VERSION); 5841 MODULE_FIRMWARE(FW_FILE_ISP21XX); 5842 MODULE_FIRMWARE(FW_FILE_ISP22XX); 5843 MODULE_FIRMWARE(FW_FILE_ISP2300); 5844 MODULE_FIRMWARE(FW_FILE_ISP2322); 5845 MODULE_FIRMWARE(FW_FILE_ISP24XX); 5846 MODULE_FIRMWARE(FW_FILE_ISP25XX); 5847 MODULE_FIRMWARE(FW_FILE_ISP2031); 5848 MODULE_FIRMWARE(FW_FILE_ISP8031); 5849 MODULE_FIRMWARE(FW_FILE_ISP27XX); 5850