1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 int ql2xfulldump_on_mpifail; 39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 41 "Set this to take full dump on MPI hang."); 42 43 int ql2xenforce_iocb_limit = 1; 44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 47 48 /* 49 * CT6 CTX allocation cache 50 */ 51 static struct kmem_cache *ctx_cachep; 52 /* 53 * error level for logging 54 */ 55 uint ql_errlev = 0x8001; 56 57 int ql2xsecenable; 58 module_param(ql2xsecenable, int, S_IRUGO); 59 MODULE_PARM_DESC(ql2xsecenable, 60 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 61 62 static int ql2xenableclass2; 63 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 64 MODULE_PARM_DESC(ql2xenableclass2, 65 "Specify if Class 2 operations are supported from the very " 66 "beginning. Default is 0 - class 2 not supported."); 67 68 69 int ql2xlogintimeout = 20; 70 module_param(ql2xlogintimeout, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xlogintimeout, 72 "Login timeout value in seconds."); 73 74 int qlport_down_retry; 75 module_param(qlport_down_retry, int, S_IRUGO); 76 MODULE_PARM_DESC(qlport_down_retry, 77 "Maximum number of command retries to a port that returns " 78 "a PORT-DOWN status."); 79 80 int ql2xplogiabsentdevice; 81 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(ql2xplogiabsentdevice, 83 "Option to enable PLOGI to devices that are not present after " 84 "a Fabric scan. This is needed for several broken switches. " 85 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 86 87 int ql2xloginretrycount; 88 module_param(ql2xloginretrycount, int, S_IRUGO); 89 MODULE_PARM_DESC(ql2xloginretrycount, 90 "Specify an alternate value for the NVRAM login retry count."); 91 92 int ql2xallocfwdump = 1; 93 module_param(ql2xallocfwdump, int, S_IRUGO); 94 MODULE_PARM_DESC(ql2xallocfwdump, 95 "Option to enable allocation of memory for a firmware dump " 96 "during HBA initialization. Memory allocation requirements " 97 "vary by ISP type. Default is 1 - allocate memory."); 98 99 int ql2xextended_error_logging; 100 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 101 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 102 MODULE_PARM_DESC(ql2xextended_error_logging, 103 "Option to enable extended error logging,\n" 104 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 105 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 106 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 107 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 108 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 109 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 110 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 111 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 112 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 113 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 114 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 115 "\t\t0x1e400000 - Preferred value for capturing essential " 116 "debug information (equivalent to old " 117 "ql2xextended_error_logging=1).\n" 118 "\t\tDo LOGICAL OR of the value to enable more than one level"); 119 120 int ql2xshiftctondsd = 6; 121 module_param(ql2xshiftctondsd, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xshiftctondsd, 123 "Set to control shifting of command type processing " 124 "based on total number of SG elements."); 125 126 int ql2xfdmienable = 1; 127 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 128 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 129 MODULE_PARM_DESC(ql2xfdmienable, 130 "Enables FDMI registrations. " 131 "0 - no FDMI registrations. " 132 "1 - provide FDMI registrations (default)."); 133 134 #define MAX_Q_DEPTH 64 135 static int ql2xmaxqdepth = MAX_Q_DEPTH; 136 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 137 MODULE_PARM_DESC(ql2xmaxqdepth, 138 "Maximum queue depth to set for each LUN. " 139 "Default is 64."); 140 141 int ql2xenabledif = 2; 142 module_param(ql2xenabledif, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xenabledif, 144 " Enable T10-CRC-DIF:\n" 145 " Default is 2.\n" 146 " 0 -- No DIF Support\n" 147 " 1 -- Enable DIF for all types\n" 148 " 2 -- Enable DIF for all types, except Type 0.\n"); 149 150 #if (IS_ENABLED(CONFIG_NVME_FC)) 151 int ql2xnvmeenable = 1; 152 #else 153 int ql2xnvmeenable; 154 #endif 155 module_param(ql2xnvmeenable, int, 0644); 156 MODULE_PARM_DESC(ql2xnvmeenable, 157 "Enables NVME support. " 158 "0 - no NVMe. Default is Y"); 159 160 int ql2xenablehba_err_chk = 2; 161 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 162 MODULE_PARM_DESC(ql2xenablehba_err_chk, 163 " Enable T10-CRC-DIF Error isolation by HBA:\n" 164 " Default is 2.\n" 165 " 0 -- Error isolation disabled\n" 166 " 1 -- Error isolation enabled only for DIX Type 0\n" 167 " 2 -- Error isolation enabled for all Types\n"); 168 169 int ql2xiidmaenable = 1; 170 module_param(ql2xiidmaenable, int, S_IRUGO); 171 MODULE_PARM_DESC(ql2xiidmaenable, 172 "Enables iIDMA settings " 173 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 174 175 int ql2xmqsupport = 1; 176 module_param(ql2xmqsupport, int, S_IRUGO); 177 MODULE_PARM_DESC(ql2xmqsupport, 178 "Enable on demand multiple queue pairs support " 179 "Default is 1 for supported. " 180 "Set it to 0 to turn off mq qpair support."); 181 182 int ql2xfwloadbin; 183 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 184 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 185 MODULE_PARM_DESC(ql2xfwloadbin, 186 "Option to specify location from which to load ISP firmware:.\n" 187 " 2 -- load firmware via the request_firmware() (hotplug).\n" 188 " interface.\n" 189 " 1 -- load firmware from flash.\n" 190 " 0 -- use default semantics.\n"); 191 192 int ql2xetsenable; 193 module_param(ql2xetsenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xetsenable, 195 "Enables firmware ETS burst." 196 "Default is 0 - skip ETS enablement."); 197 198 int ql2xdbwr = 1; 199 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdbwr, 201 "Option to specify scheme for request queue posting.\n" 202 " 0 -- Regular doorbell.\n" 203 " 1 -- CAMRAM doorbell (faster).\n"); 204 205 int ql2xgffidenable; 206 module_param(ql2xgffidenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xgffidenable, 208 "Enables GFF_ID checks of port type. " 209 "Default is 0 - Do not use GFF_ID information."); 210 211 int ql2xasynctmfenable = 1; 212 module_param(ql2xasynctmfenable, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xasynctmfenable, 214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 215 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 216 217 int ql2xdontresethba; 218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 219 MODULE_PARM_DESC(ql2xdontresethba, 220 "Option to specify reset behaviour.\n" 221 " 0 (Default) -- Reset on failure.\n" 222 " 1 -- Do not reset on failure.\n"); 223 224 uint64_t ql2xmaxlun = MAX_LUNS; 225 module_param(ql2xmaxlun, ullong, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmaxlun, 227 "Defines the maximum LU number to register with the SCSI " 228 "midlayer. Default is 65535."); 229 230 int ql2xmdcapmask = 0x1F; 231 module_param(ql2xmdcapmask, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdcapmask, 233 "Set the Minidump driver capture mask level. " 234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 235 236 int ql2xmdenable = 1; 237 module_param(ql2xmdenable, int, S_IRUGO); 238 MODULE_PARM_DESC(ql2xmdenable, 239 "Enable/disable MiniDump. " 240 "0 - MiniDump disabled. " 241 "1 (Default) - MiniDump enabled."); 242 243 int ql2xexlogins; 244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 245 MODULE_PARM_DESC(ql2xexlogins, 246 "Number of extended Logins. " 247 "0 (Default)- Disabled."); 248 249 int ql2xexchoffld = 1024; 250 module_param(ql2xexchoffld, uint, 0644); 251 MODULE_PARM_DESC(ql2xexchoffld, 252 "Number of target exchanges."); 253 254 int ql2xiniexchg = 1024; 255 module_param(ql2xiniexchg, uint, 0644); 256 MODULE_PARM_DESC(ql2xiniexchg, 257 "Number of initiator exchanges."); 258 259 int ql2xfwholdabts; 260 module_param(ql2xfwholdabts, int, S_IRUGO); 261 MODULE_PARM_DESC(ql2xfwholdabts, 262 "Allow FW to hold status IOCB until ABTS rsp received. " 263 "0 (Default) Do not set fw option. " 264 "1 - Set fw option to hold ABTS."); 265 266 int ql2xmvasynctoatio = 1; 267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 268 MODULE_PARM_DESC(ql2xmvasynctoatio, 269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 270 "0 (Default). Do not move IOCBs" 271 "1 - Move IOCBs."); 272 273 int ql2xautodetectsfp = 1; 274 module_param(ql2xautodetectsfp, int, 0444); 275 MODULE_PARM_DESC(ql2xautodetectsfp, 276 "Detect SFP range and set appropriate distance.\n" 277 "1 (Default): Enable\n"); 278 279 int ql2xenablemsix = 1; 280 module_param(ql2xenablemsix, int, 0444); 281 MODULE_PARM_DESC(ql2xenablemsix, 282 "Set to enable MSI or MSI-X interrupt mechanism.\n" 283 " Default is 1, enable MSI-X interrupt mechanism.\n" 284 " 0 -- enable traditional pin-based mechanism.\n" 285 " 1 -- enable MSI-X interrupt mechanism.\n" 286 " 2 -- enable MSI interrupt mechanism.\n"); 287 288 int qla2xuseresexchforels; 289 module_param(qla2xuseresexchforels, int, 0444); 290 MODULE_PARM_DESC(qla2xuseresexchforels, 291 "Reserve 1/2 of emergency exchanges for ELS.\n" 292 " 0 (default): disabled"); 293 294 static int ql2xprotmask; 295 module_param(ql2xprotmask, int, 0644); 296 MODULE_PARM_DESC(ql2xprotmask, 297 "Override DIF/DIX protection capabilities mask\n" 298 "Default is 0 which sets protection mask based on " 299 "capabilities reported by HBA firmware.\n"); 300 301 static int ql2xprotguard; 302 module_param(ql2xprotguard, int, 0644); 303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 304 " 0 -- Let HBA firmware decide\n" 305 " 1 -- Force T10 CRC\n" 306 " 2 -- Force IP checksum\n"); 307 308 int ql2xdifbundlinginternalbuffers; 309 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 311 "Force using internal buffers for DIF information\n" 312 "0 (Default). Based on check.\n" 313 "1 Force using internal buffers\n"); 314 315 int ql2xsmartsan; 316 module_param(ql2xsmartsan, int, 0444); 317 module_param_named(smartsan, ql2xsmartsan, int, 0444); 318 MODULE_PARM_DESC(ql2xsmartsan, 319 "Send SmartSAN Management Attributes for FDMI Registration." 320 " Default is 0 - No SmartSAN registration," 321 " 1 - Register SmartSAN Management Attributes."); 322 323 int ql2xrdpenable; 324 module_param(ql2xrdpenable, int, 0444); 325 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 326 MODULE_PARM_DESC(ql2xrdpenable, 327 "Enables RDP responses. " 328 "0 - no RDP responses (default). " 329 "1 - provide RDP responses."); 330 int ql2xabts_wait_nvme = 1; 331 module_param(ql2xabts_wait_nvme, int, 0444); 332 MODULE_PARM_DESC(ql2xabts_wait_nvme, 333 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 334 335 336 static void qla2x00_clear_drv_active(struct qla_hw_data *); 337 static void qla2x00_free_device(scsi_qla_host_t *); 338 static int qla2xxx_map_queues(struct Scsi_Host *shost); 339 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 340 341 342 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 343 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 344 345 /* TODO Convert to inlines 346 * 347 * Timer routines 348 */ 349 350 __inline__ void 351 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 352 { 353 timer_setup(&vha->timer, qla2x00_timer, 0); 354 vha->timer.expires = jiffies + interval * HZ; 355 add_timer(&vha->timer); 356 vha->timer_active = 1; 357 } 358 359 static inline void 360 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 361 { 362 /* Currently used for 82XX only. */ 363 if (vha->device_flags & DFLG_DEV_FAILED) { 364 ql_dbg(ql_dbg_timer, vha, 0x600d, 365 "Device in a failed state, returning.\n"); 366 return; 367 } 368 369 mod_timer(&vha->timer, jiffies + interval * HZ); 370 } 371 372 static __inline__ void 373 qla2x00_stop_timer(scsi_qla_host_t *vha) 374 { 375 del_timer_sync(&vha->timer); 376 vha->timer_active = 0; 377 } 378 379 static int qla2x00_do_dpc(void *data); 380 381 static void qla2x00_rst_aen(scsi_qla_host_t *); 382 383 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 384 struct req_que **, struct rsp_que **); 385 static void qla2x00_free_fw_dump(struct qla_hw_data *); 386 static void qla2x00_mem_free(struct qla_hw_data *); 387 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 388 struct qla_qpair *qpair); 389 390 /* -------------------------------------------------------------------------- */ 391 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 392 struct rsp_que *rsp) 393 { 394 struct qla_hw_data *ha = vha->hw; 395 396 rsp->qpair = ha->base_qpair; 397 rsp->req = req; 398 ha->base_qpair->hw = ha; 399 ha->base_qpair->req = req; 400 ha->base_qpair->rsp = rsp; 401 ha->base_qpair->vha = vha; 402 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 403 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 404 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 405 ha->base_qpair->srb_mempool = ha->srb_mempool; 406 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 407 ha->base_qpair->enable_class_2 = ql2xenableclass2; 408 /* init qpair to this cpu. Will adjust at run time. */ 409 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 410 ha->base_qpair->pdev = ha->pdev; 411 412 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 413 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 414 } 415 416 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 417 struct rsp_que *rsp) 418 { 419 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 420 421 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 422 GFP_KERNEL); 423 if (!ha->req_q_map) { 424 ql_log(ql_log_fatal, vha, 0x003b, 425 "Unable to allocate memory for request queue ptrs.\n"); 426 goto fail_req_map; 427 } 428 429 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 430 GFP_KERNEL); 431 if (!ha->rsp_q_map) { 432 ql_log(ql_log_fatal, vha, 0x003c, 433 "Unable to allocate memory for response queue ptrs.\n"); 434 goto fail_rsp_map; 435 } 436 437 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 438 if (ha->base_qpair == NULL) { 439 ql_log(ql_log_warn, vha, 0x00e0, 440 "Failed to allocate base queue pair memory.\n"); 441 goto fail_base_qpair; 442 } 443 444 qla_init_base_qpair(vha, req, rsp); 445 446 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 447 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 448 GFP_KERNEL); 449 if (!ha->queue_pair_map) { 450 ql_log(ql_log_fatal, vha, 0x0180, 451 "Unable to allocate memory for queue pair ptrs.\n"); 452 goto fail_qpair_map; 453 } 454 } 455 456 /* 457 * Make sure we record at least the request and response queue zero in 458 * case we need to free them if part of the probe fails. 459 */ 460 ha->rsp_q_map[0] = rsp; 461 ha->req_q_map[0] = req; 462 set_bit(0, ha->rsp_qid_map); 463 set_bit(0, ha->req_qid_map); 464 return 0; 465 466 fail_qpair_map: 467 kfree(ha->base_qpair); 468 ha->base_qpair = NULL; 469 fail_base_qpair: 470 kfree(ha->rsp_q_map); 471 ha->rsp_q_map = NULL; 472 fail_rsp_map: 473 kfree(ha->req_q_map); 474 ha->req_q_map = NULL; 475 fail_req_map: 476 return -ENOMEM; 477 } 478 479 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 480 { 481 if (IS_QLAFX00(ha)) { 482 if (req && req->ring_fx00) 483 dma_free_coherent(&ha->pdev->dev, 484 (req->length_fx00 + 1) * sizeof(request_t), 485 req->ring_fx00, req->dma_fx00); 486 } else if (req && req->ring) 487 dma_free_coherent(&ha->pdev->dev, 488 (req->length + 1) * sizeof(request_t), 489 req->ring, req->dma); 490 491 if (req) 492 kfree(req->outstanding_cmds); 493 494 kfree(req); 495 } 496 497 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 498 { 499 if (IS_QLAFX00(ha)) { 500 if (rsp && rsp->ring_fx00) 501 dma_free_coherent(&ha->pdev->dev, 502 (rsp->length_fx00 + 1) * sizeof(request_t), 503 rsp->ring_fx00, rsp->dma_fx00); 504 } else if (rsp && rsp->ring) { 505 dma_free_coherent(&ha->pdev->dev, 506 (rsp->length + 1) * sizeof(response_t), 507 rsp->ring, rsp->dma); 508 } 509 kfree(rsp); 510 } 511 512 static void qla2x00_free_queues(struct qla_hw_data *ha) 513 { 514 struct req_que *req; 515 struct rsp_que *rsp; 516 int cnt; 517 unsigned long flags; 518 519 if (ha->queue_pair_map) { 520 kfree(ha->queue_pair_map); 521 ha->queue_pair_map = NULL; 522 } 523 if (ha->base_qpair) { 524 kfree(ha->base_qpair); 525 ha->base_qpair = NULL; 526 } 527 528 spin_lock_irqsave(&ha->hardware_lock, flags); 529 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 530 if (!test_bit(cnt, ha->req_qid_map)) 531 continue; 532 533 req = ha->req_q_map[cnt]; 534 clear_bit(cnt, ha->req_qid_map); 535 ha->req_q_map[cnt] = NULL; 536 537 spin_unlock_irqrestore(&ha->hardware_lock, flags); 538 qla2x00_free_req_que(ha, req); 539 spin_lock_irqsave(&ha->hardware_lock, flags); 540 } 541 spin_unlock_irqrestore(&ha->hardware_lock, flags); 542 543 kfree(ha->req_q_map); 544 ha->req_q_map = NULL; 545 546 547 spin_lock_irqsave(&ha->hardware_lock, flags); 548 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 549 if (!test_bit(cnt, ha->rsp_qid_map)) 550 continue; 551 552 rsp = ha->rsp_q_map[cnt]; 553 clear_bit(cnt, ha->rsp_qid_map); 554 ha->rsp_q_map[cnt] = NULL; 555 spin_unlock_irqrestore(&ha->hardware_lock, flags); 556 qla2x00_free_rsp_que(ha, rsp); 557 spin_lock_irqsave(&ha->hardware_lock, flags); 558 } 559 spin_unlock_irqrestore(&ha->hardware_lock, flags); 560 561 kfree(ha->rsp_q_map); 562 ha->rsp_q_map = NULL; 563 } 564 565 static char * 566 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 567 { 568 struct qla_hw_data *ha = vha->hw; 569 static const char *const pci_bus_modes[] = { 570 "33", "66", "100", "133", 571 }; 572 uint16_t pci_bus; 573 574 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 575 if (pci_bus) { 576 snprintf(str, str_len, "PCI-X (%s MHz)", 577 pci_bus_modes[pci_bus]); 578 } else { 579 pci_bus = (ha->pci_attr & BIT_8) >> 8; 580 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 581 } 582 583 return str; 584 } 585 586 static char * 587 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 588 { 589 static const char *const pci_bus_modes[] = { 590 "33", "66", "100", "133", 591 }; 592 struct qla_hw_data *ha = vha->hw; 593 uint32_t pci_bus; 594 595 if (pci_is_pcie(ha->pdev)) { 596 uint32_t lstat, lspeed, lwidth; 597 const char *speed_str; 598 599 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 600 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 601 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 602 603 switch (lspeed) { 604 case 1: 605 speed_str = "2.5GT/s"; 606 break; 607 case 2: 608 speed_str = "5.0GT/s"; 609 break; 610 case 3: 611 speed_str = "8.0GT/s"; 612 break; 613 case 4: 614 speed_str = "16.0GT/s"; 615 break; 616 default: 617 speed_str = "<unknown>"; 618 break; 619 } 620 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 621 622 return str; 623 } 624 625 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 626 if (pci_bus == 0 || pci_bus == 8) 627 snprintf(str, str_len, "PCI (%s MHz)", 628 pci_bus_modes[pci_bus >> 3]); 629 else 630 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 631 pci_bus & 4 ? 2 : 1, 632 pci_bus_modes[pci_bus & 3]); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void qla2x00_sp_free_dma(srb_t *sp) 686 { 687 struct qla_hw_data *ha = sp->vha->hw; 688 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 689 690 if (sp->flags & SRB_DMA_VALID) { 691 scsi_dma_unmap(cmd); 692 sp->flags &= ~SRB_DMA_VALID; 693 } 694 695 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 696 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 697 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 698 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 699 } 700 701 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 702 /* List assured to be having elements */ 703 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 704 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 705 } 706 707 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 708 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 709 710 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 711 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 712 } 713 714 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 715 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 716 717 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 718 ctx1->fcp_cmnd_dma); 719 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 720 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 721 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 722 mempool_free(ctx1, ha->ctx_mempool); 723 } 724 } 725 726 void qla2x00_sp_compl(srb_t *sp, int res) 727 { 728 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 729 struct completion *comp = sp->comp; 730 731 sp->free(sp); 732 cmd->result = res; 733 CMD_SP(cmd) = NULL; 734 scsi_done(cmd); 735 if (comp) 736 complete(comp); 737 } 738 739 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 740 { 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 742 struct qla_hw_data *ha = sp->fcport->vha->hw; 743 744 if (sp->flags & SRB_DMA_VALID) { 745 scsi_dma_unmap(cmd); 746 sp->flags &= ~SRB_DMA_VALID; 747 } 748 749 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 750 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 751 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 752 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 753 } 754 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 756 /* List assured to be having elements */ 757 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 759 } 760 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 762 struct crc_context *difctx = sp->u.scmd.crc_ctx; 763 struct dsd_dma *dif_dsd, *nxt_dsd; 764 765 list_for_each_entry_safe(dif_dsd, nxt_dsd, 766 &difctx->ldif_dma_hndl_list, list) { 767 list_del(&dif_dsd->list); 768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 769 dif_dsd->dsd_list_dma); 770 kfree(dif_dsd); 771 difctx->no_dif_bundl--; 772 } 773 774 list_for_each_entry_safe(dif_dsd, nxt_dsd, 775 &difctx->ldif_dsd_list, list) { 776 list_del(&dif_dsd->list); 777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 778 dif_dsd->dsd_list_dma); 779 kfree(dif_dsd); 780 difctx->no_ldif_dsd--; 781 } 782 783 if (difctx->no_ldif_dsd) { 784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 785 "%s: difctx->no_ldif_dsd=%x\n", 786 __func__, difctx->no_ldif_dsd); 787 } 788 789 if (difctx->no_dif_bundl) { 790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 791 "%s: difctx->no_dif_bundl=%x\n", 792 __func__, difctx->no_dif_bundl); 793 } 794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 795 } 796 797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 798 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 799 800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 801 ctx1->fcp_cmnd_dma); 802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 805 mempool_free(ctx1, ha->ctx_mempool); 806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 807 } 808 809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 810 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 811 812 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 814 } 815 } 816 817 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 818 { 819 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 820 struct completion *comp = sp->comp; 821 822 sp->free(sp); 823 cmd->result = res; 824 CMD_SP(cmd) = NULL; 825 scsi_done(cmd); 826 if (comp) 827 complete(comp); 828 } 829 830 static int 831 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 832 { 833 scsi_qla_host_t *vha = shost_priv(host); 834 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 835 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 836 struct qla_hw_data *ha = vha->hw; 837 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 838 srb_t *sp; 839 int rval; 840 841 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 842 WARN_ON_ONCE(!rport)) { 843 cmd->result = DID_NO_CONNECT << 16; 844 goto qc24_fail_command; 845 } 846 847 if (ha->mqenable) { 848 uint32_t tag; 849 uint16_t hwq; 850 struct qla_qpair *qpair = NULL; 851 852 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 853 hwq = blk_mq_unique_tag_to_hwq(tag); 854 qpair = ha->queue_pair_map[hwq]; 855 856 if (qpair) 857 return qla2xxx_mqueuecommand(host, cmd, qpair); 858 } 859 860 if (ha->flags.eeh_busy) { 861 if (ha->flags.pci_channel_io_perm_failure) { 862 ql_dbg(ql_dbg_aer, vha, 0x9010, 863 "PCI Channel IO permanent failure, exiting " 864 "cmd=%p.\n", cmd); 865 cmd->result = DID_NO_CONNECT << 16; 866 } else { 867 ql_dbg(ql_dbg_aer, vha, 0x9011, 868 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 869 cmd->result = DID_REQUEUE << 16; 870 } 871 goto qc24_fail_command; 872 } 873 874 rval = fc_remote_port_chkready(rport); 875 if (rval) { 876 cmd->result = rval; 877 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 878 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 879 cmd, rval); 880 goto qc24_fail_command; 881 } 882 883 if (!vha->flags.difdix_supported && 884 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 885 ql_dbg(ql_dbg_io, vha, 0x3004, 886 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 887 cmd); 888 cmd->result = DID_NO_CONNECT << 16; 889 goto qc24_fail_command; 890 } 891 892 if (!fcport || fcport->deleted) { 893 cmd->result = DID_IMM_RETRY << 16; 894 goto qc24_fail_command; 895 } 896 897 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 898 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 899 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 900 ql_dbg(ql_dbg_io, vha, 0x3005, 901 "Returning DNC, fcport_state=%d loop_state=%d.\n", 902 atomic_read(&fcport->state), 903 atomic_read(&base_vha->loop_state)); 904 cmd->result = DID_NO_CONNECT << 16; 905 goto qc24_fail_command; 906 } 907 goto qc24_target_busy; 908 } 909 910 /* 911 * Return target busy if we've received a non-zero retry_delay_timer 912 * in a FCP_RSP. 913 */ 914 if (fcport->retry_delay_timestamp == 0) { 915 /* retry delay not set */ 916 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 917 fcport->retry_delay_timestamp = 0; 918 else 919 goto qc24_target_busy; 920 921 sp = scsi_cmd_priv(cmd); 922 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 923 924 sp->u.scmd.cmd = cmd; 925 sp->type = SRB_SCSI_CMD; 926 927 CMD_SP(cmd) = (void *)sp; 928 sp->free = qla2x00_sp_free_dma; 929 sp->done = qla2x00_sp_compl; 930 931 rval = ha->isp_ops->start_scsi(sp); 932 if (rval != QLA_SUCCESS) { 933 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 934 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 935 goto qc24_host_busy_free_sp; 936 } 937 938 return 0; 939 940 qc24_host_busy_free_sp: 941 sp->free(sp); 942 943 qc24_target_busy: 944 return SCSI_MLQUEUE_TARGET_BUSY; 945 946 qc24_fail_command: 947 scsi_done(cmd); 948 949 return 0; 950 } 951 952 /* For MQ supported I/O */ 953 int 954 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 955 struct qla_qpair *qpair) 956 { 957 scsi_qla_host_t *vha = shost_priv(host); 958 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 959 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 960 struct qla_hw_data *ha = vha->hw; 961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 962 srb_t *sp; 963 int rval; 964 965 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 966 if (rval) { 967 cmd->result = rval; 968 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 969 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 970 cmd, rval); 971 goto qc24_fail_command; 972 } 973 974 if (!qpair->online) { 975 ql_dbg(ql_dbg_io, vha, 0x3077, 976 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 977 cmd->result = DID_NO_CONNECT << 16; 978 goto qc24_fail_command; 979 } 980 981 if (!fcport || fcport->deleted) { 982 cmd->result = DID_IMM_RETRY << 16; 983 goto qc24_fail_command; 984 } 985 986 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 987 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 988 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 989 ql_dbg(ql_dbg_io, vha, 0x3077, 990 "Returning DNC, fcport_state=%d loop_state=%d.\n", 991 atomic_read(&fcport->state), 992 atomic_read(&base_vha->loop_state)); 993 cmd->result = DID_NO_CONNECT << 16; 994 goto qc24_fail_command; 995 } 996 goto qc24_target_busy; 997 } 998 999 /* 1000 * Return target busy if we've received a non-zero retry_delay_timer 1001 * in a FCP_RSP. 1002 */ 1003 if (fcport->retry_delay_timestamp == 0) { 1004 /* retry delay not set */ 1005 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1006 fcport->retry_delay_timestamp = 0; 1007 else 1008 goto qc24_target_busy; 1009 1010 sp = scsi_cmd_priv(cmd); 1011 qla2xxx_init_sp(sp, vha, qpair, fcport); 1012 1013 sp->u.scmd.cmd = cmd; 1014 sp->type = SRB_SCSI_CMD; 1015 CMD_SP(cmd) = (void *)sp; 1016 sp->free = qla2xxx_qpair_sp_free_dma; 1017 sp->done = qla2xxx_qpair_sp_compl; 1018 1019 rval = ha->isp_ops->start_scsi_mq(sp); 1020 if (rval != QLA_SUCCESS) { 1021 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1022 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1023 goto qc24_host_busy_free_sp; 1024 } 1025 1026 return 0; 1027 1028 qc24_host_busy_free_sp: 1029 sp->free(sp); 1030 1031 qc24_target_busy: 1032 return SCSI_MLQUEUE_TARGET_BUSY; 1033 1034 qc24_fail_command: 1035 scsi_done(cmd); 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * qla2x00_eh_wait_on_command 1042 * Waits for the command to be returned by the Firmware for some 1043 * max time. 1044 * 1045 * Input: 1046 * cmd = Scsi Command to wait on. 1047 * 1048 * Return: 1049 * Completed in time : QLA_SUCCESS 1050 * Did not complete in time : QLA_FUNCTION_FAILED 1051 */ 1052 static int 1053 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1054 { 1055 #define ABORT_POLLING_PERIOD 1000 1056 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1057 unsigned long wait_iter = ABORT_WAIT_ITER; 1058 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1059 struct qla_hw_data *ha = vha->hw; 1060 int ret = QLA_SUCCESS; 1061 1062 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1063 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1064 "Return:eh_wait.\n"); 1065 return ret; 1066 } 1067 1068 while (CMD_SP(cmd) && wait_iter--) { 1069 msleep(ABORT_POLLING_PERIOD); 1070 } 1071 if (CMD_SP(cmd)) 1072 ret = QLA_FUNCTION_FAILED; 1073 1074 return ret; 1075 } 1076 1077 /* 1078 * qla2x00_wait_for_hba_online 1079 * Wait till the HBA is online after going through 1080 * <= MAX_RETRIES_OF_ISP_ABORT or 1081 * finally HBA is disabled ie marked offline 1082 * 1083 * Input: 1084 * ha - pointer to host adapter structure 1085 * 1086 * Note: 1087 * Does context switching-Release SPIN_LOCK 1088 * (if any) before calling this routine. 1089 * 1090 * Return: 1091 * Success (Adapter is online) : 0 1092 * Failed (Adapter is offline/disabled) : 1 1093 */ 1094 int 1095 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1096 { 1097 int return_status; 1098 unsigned long wait_online; 1099 struct qla_hw_data *ha = vha->hw; 1100 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1101 1102 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1103 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1104 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1105 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1106 ha->dpc_active) && time_before(jiffies, wait_online)) { 1107 1108 msleep(1000); 1109 } 1110 if (base_vha->flags.online) 1111 return_status = QLA_SUCCESS; 1112 else 1113 return_status = QLA_FUNCTION_FAILED; 1114 1115 return (return_status); 1116 } 1117 1118 static inline int test_fcport_count(scsi_qla_host_t *vha) 1119 { 1120 struct qla_hw_data *ha = vha->hw; 1121 unsigned long flags; 1122 int res; 1123 /* Return 0 = sleep, x=wake */ 1124 1125 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1126 ql_dbg(ql_dbg_init, vha, 0x00ec, 1127 "tgt %p, fcport_count=%d\n", 1128 vha, vha->fcport_count); 1129 res = (vha->fcport_count == 0); 1130 if (res) { 1131 struct fc_port *fcport; 1132 1133 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1134 if (fcport->deleted != QLA_SESS_DELETED) { 1135 /* session(s) may not be fully logged in 1136 * (ie fcport_count=0), but session 1137 * deletion thread(s) may be inflight. 1138 */ 1139 1140 res = 0; 1141 break; 1142 } 1143 } 1144 } 1145 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1146 1147 return res; 1148 } 1149 1150 /* 1151 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1152 * it has dependency on UNLOADING flag to stop device discovery 1153 */ 1154 void 1155 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1156 { 1157 u8 i; 1158 1159 qla2x00_mark_all_devices_lost(vha); 1160 1161 for (i = 0; i < 10; i++) { 1162 if (wait_event_timeout(vha->fcport_waitQ, 1163 test_fcport_count(vha), HZ) > 0) 1164 break; 1165 } 1166 1167 flush_workqueue(vha->hw->wq); 1168 } 1169 1170 /* 1171 * qla2x00_wait_for_hba_ready 1172 * Wait till the HBA is ready before doing driver unload 1173 * 1174 * Input: 1175 * ha - pointer to host adapter structure 1176 * 1177 * Note: 1178 * Does context switching-Release SPIN_LOCK 1179 * (if any) before calling this routine. 1180 * 1181 */ 1182 static void 1183 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1184 { 1185 struct qla_hw_data *ha = vha->hw; 1186 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1187 1188 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1189 ha->flags.mbox_busy) || 1190 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1191 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1192 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1193 break; 1194 msleep(1000); 1195 } 1196 } 1197 1198 int 1199 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1200 { 1201 int return_status; 1202 unsigned long wait_reset; 1203 struct qla_hw_data *ha = vha->hw; 1204 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1205 1206 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1207 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1208 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1209 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1210 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1211 1212 msleep(1000); 1213 1214 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1215 ha->flags.chip_reset_done) 1216 break; 1217 } 1218 if (ha->flags.chip_reset_done) 1219 return_status = QLA_SUCCESS; 1220 else 1221 return_status = QLA_FUNCTION_FAILED; 1222 1223 return return_status; 1224 } 1225 1226 /************************************************************************** 1227 * qla2xxx_eh_abort 1228 * 1229 * Description: 1230 * The abort function will abort the specified command. 1231 * 1232 * Input: 1233 * cmd = Linux SCSI command packet to be aborted. 1234 * 1235 * Returns: 1236 * Either SUCCESS or FAILED. 1237 * 1238 * Note: 1239 * Only return FAILED if command not returned by firmware. 1240 **************************************************************************/ 1241 static int 1242 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1243 { 1244 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1245 DECLARE_COMPLETION_ONSTACK(comp); 1246 srb_t *sp; 1247 int ret; 1248 unsigned int id; 1249 uint64_t lun; 1250 int rval; 1251 struct qla_hw_data *ha = vha->hw; 1252 uint32_t ratov_j; 1253 struct qla_qpair *qpair; 1254 unsigned long flags; 1255 int fast_fail_status = SUCCESS; 1256 1257 if (qla2x00_isp_reg_stat(ha)) { 1258 ql_log(ql_log_info, vha, 0x8042, 1259 "PCI/Register disconnect, exiting.\n"); 1260 qla_pci_set_eeh_busy(vha); 1261 return FAILED; 1262 } 1263 1264 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1265 ret = fc_block_scsi_eh(cmd); 1266 if (ret != 0) 1267 fast_fail_status = ret; 1268 1269 sp = scsi_cmd_priv(cmd); 1270 qpair = sp->qpair; 1271 1272 vha->cmd_timeout_cnt++; 1273 1274 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1275 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1276 1277 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1278 sp->comp = ∁ 1279 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1280 1281 1282 id = cmd->device->id; 1283 lun = cmd->device->lun; 1284 1285 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1286 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1287 vha->host_no, id, lun, sp, cmd, sp->handle); 1288 1289 /* 1290 * Abort will release the original Command/sp from FW. Let the 1291 * original command call scsi_done. In return, he will wakeup 1292 * this sleeping thread. 1293 */ 1294 rval = ha->isp_ops->abort_command(sp); 1295 1296 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1297 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1298 1299 /* Wait for the command completion. */ 1300 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1301 ratov_j = msecs_to_jiffies(ratov_j); 1302 switch (rval) { 1303 case QLA_SUCCESS: 1304 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1305 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1306 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1307 __func__, ha->r_a_tov/10); 1308 ret = FAILED; 1309 } else { 1310 ret = fast_fail_status; 1311 } 1312 break; 1313 default: 1314 ret = FAILED; 1315 break; 1316 } 1317 1318 sp->comp = NULL; 1319 1320 ql_log(ql_log_info, vha, 0x801c, 1321 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1322 vha->host_no, id, lun, ret); 1323 1324 return ret; 1325 } 1326 1327 /* 1328 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1329 */ 1330 int 1331 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1332 uint64_t l, enum nexus_wait_type type) 1333 { 1334 int cnt, match, status; 1335 unsigned long flags; 1336 struct qla_hw_data *ha = vha->hw; 1337 struct req_que *req; 1338 srb_t *sp; 1339 struct scsi_cmnd *cmd; 1340 1341 status = QLA_SUCCESS; 1342 1343 spin_lock_irqsave(&ha->hardware_lock, flags); 1344 req = vha->req; 1345 for (cnt = 1; status == QLA_SUCCESS && 1346 cnt < req->num_outstanding_cmds; cnt++) { 1347 sp = req->outstanding_cmds[cnt]; 1348 if (!sp) 1349 continue; 1350 if (sp->type != SRB_SCSI_CMD) 1351 continue; 1352 if (vha->vp_idx != sp->vha->vp_idx) 1353 continue; 1354 match = 0; 1355 cmd = GET_CMD_SP(sp); 1356 switch (type) { 1357 case WAIT_HOST: 1358 match = 1; 1359 break; 1360 case WAIT_TARGET: 1361 match = cmd->device->id == t; 1362 break; 1363 case WAIT_LUN: 1364 match = (cmd->device->id == t && 1365 cmd->device->lun == l); 1366 break; 1367 } 1368 if (!match) 1369 continue; 1370 1371 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1372 status = qla2x00_eh_wait_on_command(cmd); 1373 spin_lock_irqsave(&ha->hardware_lock, flags); 1374 } 1375 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1376 1377 return status; 1378 } 1379 1380 static char *reset_errors[] = { 1381 "HBA not online", 1382 "HBA not ready", 1383 "Task management failed", 1384 "Waiting for command completions", 1385 }; 1386 1387 static int 1388 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1389 { 1390 struct scsi_device *sdev = cmd->device; 1391 scsi_qla_host_t *vha = shost_priv(sdev->host); 1392 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1393 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1394 struct qla_hw_data *ha = vha->hw; 1395 int err; 1396 1397 if (qla2x00_isp_reg_stat(ha)) { 1398 ql_log(ql_log_info, vha, 0x803e, 1399 "PCI/Register disconnect, exiting.\n"); 1400 qla_pci_set_eeh_busy(vha); 1401 return FAILED; 1402 } 1403 1404 if (!fcport) { 1405 return FAILED; 1406 } 1407 1408 err = fc_block_rport(rport); 1409 if (err != 0) 1410 return err; 1411 1412 if (fcport->deleted) 1413 return SUCCESS; 1414 1415 ql_log(ql_log_info, vha, 0x8009, 1416 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1417 sdev->id, sdev->lun, cmd); 1418 1419 err = 0; 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1421 ql_log(ql_log_warn, vha, 0x800a, 1422 "Wait for hba online failed for cmd=%p.\n", cmd); 1423 goto eh_reset_failed; 1424 } 1425 err = 2; 1426 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1427 != QLA_SUCCESS) { 1428 ql_log(ql_log_warn, vha, 0x800c, 1429 "do_reset failed for cmd=%p.\n", cmd); 1430 goto eh_reset_failed; 1431 } 1432 err = 3; 1433 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1434 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1435 ql_log(ql_log_warn, vha, 0x800d, 1436 "wait for pending cmds failed for cmd=%p.\n", cmd); 1437 goto eh_reset_failed; 1438 } 1439 1440 ql_log(ql_log_info, vha, 0x800e, 1441 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1442 vha->host_no, sdev->id, sdev->lun, cmd); 1443 1444 return SUCCESS; 1445 1446 eh_reset_failed: 1447 ql_log(ql_log_info, vha, 0x800f, 1448 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1449 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1450 cmd); 1451 vha->reset_cmd_err_cnt++; 1452 return FAILED; 1453 } 1454 1455 static int 1456 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1457 { 1458 struct scsi_device *sdev = cmd->device; 1459 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1460 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1461 struct qla_hw_data *ha = vha->hw; 1462 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1463 int err; 1464 1465 if (qla2x00_isp_reg_stat(ha)) { 1466 ql_log(ql_log_info, vha, 0x803f, 1467 "PCI/Register disconnect, exiting.\n"); 1468 qla_pci_set_eeh_busy(vha); 1469 return FAILED; 1470 } 1471 1472 if (!fcport) { 1473 return FAILED; 1474 } 1475 1476 err = fc_block_rport(rport); 1477 if (err != 0) 1478 return err; 1479 1480 if (fcport->deleted) 1481 return SUCCESS; 1482 1483 ql_log(ql_log_info, vha, 0x8009, 1484 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1485 sdev->id, cmd); 1486 1487 err = 0; 1488 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1489 ql_log(ql_log_warn, vha, 0x800a, 1490 "Wait for hba online failed for cmd=%p.\n", cmd); 1491 goto eh_reset_failed; 1492 } 1493 err = 2; 1494 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1495 ql_log(ql_log_warn, vha, 0x800c, 1496 "target_reset failed for cmd=%p.\n", cmd); 1497 goto eh_reset_failed; 1498 } 1499 err = 3; 1500 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1501 0, WAIT_TARGET) != QLA_SUCCESS) { 1502 ql_log(ql_log_warn, vha, 0x800d, 1503 "wait for pending cmds failed for cmd=%p.\n", cmd); 1504 goto eh_reset_failed; 1505 } 1506 1507 ql_log(ql_log_info, vha, 0x800e, 1508 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1509 vha->host_no, sdev->id, cmd); 1510 1511 return SUCCESS; 1512 1513 eh_reset_failed: 1514 ql_log(ql_log_info, vha, 0x800f, 1515 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1516 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1517 cmd); 1518 vha->reset_cmd_err_cnt++; 1519 return FAILED; 1520 } 1521 1522 /************************************************************************** 1523 * qla2xxx_eh_bus_reset 1524 * 1525 * Description: 1526 * The bus reset function will reset the bus and abort any executing 1527 * commands. 1528 * 1529 * Input: 1530 * cmd = Linux SCSI command packet of the command that cause the 1531 * bus reset. 1532 * 1533 * Returns: 1534 * SUCCESS/FAILURE (defined as macro in scsi.h). 1535 * 1536 **************************************************************************/ 1537 static int 1538 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1539 { 1540 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1541 int ret = FAILED; 1542 unsigned int id; 1543 uint64_t lun; 1544 struct qla_hw_data *ha = vha->hw; 1545 1546 if (qla2x00_isp_reg_stat(ha)) { 1547 ql_log(ql_log_info, vha, 0x8040, 1548 "PCI/Register disconnect, exiting.\n"); 1549 qla_pci_set_eeh_busy(vha); 1550 return FAILED; 1551 } 1552 1553 id = cmd->device->id; 1554 lun = cmd->device->lun; 1555 1556 if (qla2x00_chip_is_down(vha)) 1557 return ret; 1558 1559 ql_log(ql_log_info, vha, 0x8012, 1560 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1561 1562 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1563 ql_log(ql_log_fatal, vha, 0x8013, 1564 "Wait for hba online failed board disabled.\n"); 1565 goto eh_bus_reset_done; 1566 } 1567 1568 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1569 ret = SUCCESS; 1570 1571 if (ret == FAILED) 1572 goto eh_bus_reset_done; 1573 1574 /* Flush outstanding commands. */ 1575 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1576 QLA_SUCCESS) { 1577 ql_log(ql_log_warn, vha, 0x8014, 1578 "Wait for pending commands failed.\n"); 1579 ret = FAILED; 1580 } 1581 1582 eh_bus_reset_done: 1583 ql_log(ql_log_warn, vha, 0x802b, 1584 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1585 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1586 1587 return ret; 1588 } 1589 1590 /************************************************************************** 1591 * qla2xxx_eh_host_reset 1592 * 1593 * Description: 1594 * The reset function will reset the Adapter. 1595 * 1596 * Input: 1597 * cmd = Linux SCSI command packet of the command that cause the 1598 * adapter reset. 1599 * 1600 * Returns: 1601 * Either SUCCESS or FAILED. 1602 * 1603 * Note: 1604 **************************************************************************/ 1605 static int 1606 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1607 { 1608 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1609 struct qla_hw_data *ha = vha->hw; 1610 int ret = FAILED; 1611 unsigned int id; 1612 uint64_t lun; 1613 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1614 1615 if (qla2x00_isp_reg_stat(ha)) { 1616 ql_log(ql_log_info, vha, 0x8041, 1617 "PCI/Register disconnect, exiting.\n"); 1618 qla_pci_set_eeh_busy(vha); 1619 return SUCCESS; 1620 } 1621 1622 id = cmd->device->id; 1623 lun = cmd->device->lun; 1624 1625 ql_log(ql_log_info, vha, 0x8018, 1626 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1627 1628 /* 1629 * No point in issuing another reset if one is active. Also do not 1630 * attempt a reset if we are updating flash. 1631 */ 1632 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1633 goto eh_host_reset_lock; 1634 1635 if (vha != base_vha) { 1636 if (qla2x00_vp_abort_isp(vha)) 1637 goto eh_host_reset_lock; 1638 } else { 1639 if (IS_P3P_TYPE(vha->hw)) { 1640 if (!qla82xx_fcoe_ctx_reset(vha)) { 1641 /* Ctx reset success */ 1642 ret = SUCCESS; 1643 goto eh_host_reset_lock; 1644 } 1645 /* fall thru if ctx reset failed */ 1646 } 1647 if (ha->wq) 1648 flush_workqueue(ha->wq); 1649 1650 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1651 if (ha->isp_ops->abort_isp(base_vha)) { 1652 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1653 /* failed. schedule dpc to try */ 1654 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1655 1656 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1657 ql_log(ql_log_warn, vha, 0x802a, 1658 "wait for hba online failed.\n"); 1659 goto eh_host_reset_lock; 1660 } 1661 } 1662 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1663 } 1664 1665 /* Waiting for command to be returned to OS.*/ 1666 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1667 QLA_SUCCESS) 1668 ret = SUCCESS; 1669 1670 eh_host_reset_lock: 1671 ql_log(ql_log_info, vha, 0x8017, 1672 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1673 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1674 1675 return ret; 1676 } 1677 1678 /* 1679 * qla2x00_loop_reset 1680 * Issue loop reset. 1681 * 1682 * Input: 1683 * ha = adapter block pointer. 1684 * 1685 * Returns: 1686 * 0 = success 1687 */ 1688 int 1689 qla2x00_loop_reset(scsi_qla_host_t *vha) 1690 { 1691 int ret; 1692 struct qla_hw_data *ha = vha->hw; 1693 1694 if (IS_QLAFX00(ha)) 1695 return QLA_SUCCESS; 1696 1697 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1698 atomic_set(&vha->loop_state, LOOP_DOWN); 1699 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1700 qla2x00_mark_all_devices_lost(vha); 1701 ret = qla2x00_full_login_lip(vha); 1702 if (ret != QLA_SUCCESS) { 1703 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1704 "full_login_lip=%d.\n", ret); 1705 } 1706 } 1707 1708 if (ha->flags.enable_lip_reset) { 1709 ret = qla2x00_lip_reset(vha); 1710 if (ret != QLA_SUCCESS) 1711 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1712 "lip_reset failed (%d).\n", ret); 1713 } 1714 1715 /* Issue marker command only when we are going to start the I/O */ 1716 vha->marker_needed = 1; 1717 1718 return QLA_SUCCESS; 1719 } 1720 1721 /* 1722 * The caller must ensure that no completion interrupts will happen 1723 * while this function is in progress. 1724 */ 1725 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1726 unsigned long *flags) 1727 __releases(qp->qp_lock_ptr) 1728 __acquires(qp->qp_lock_ptr) 1729 { 1730 DECLARE_COMPLETION_ONSTACK(comp); 1731 scsi_qla_host_t *vha = qp->vha; 1732 struct qla_hw_data *ha = vha->hw; 1733 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1734 int rval; 1735 bool ret_cmd; 1736 uint32_t ratov_j; 1737 1738 lockdep_assert_held(qp->qp_lock_ptr); 1739 1740 if (qla2x00_chip_is_down(vha)) { 1741 sp->done(sp, res); 1742 return; 1743 } 1744 1745 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1746 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1747 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1748 !qla2x00_isp_reg_stat(ha))) { 1749 if (sp->comp) { 1750 sp->done(sp, res); 1751 return; 1752 } 1753 1754 sp->comp = ∁ 1755 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1756 1757 rval = ha->isp_ops->abort_command(sp); 1758 /* Wait for command completion. */ 1759 ret_cmd = false; 1760 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1761 ratov_j = msecs_to_jiffies(ratov_j); 1762 switch (rval) { 1763 case QLA_SUCCESS: 1764 if (wait_for_completion_timeout(&comp, ratov_j)) { 1765 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1766 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1767 __func__, ha->r_a_tov/10); 1768 ret_cmd = true; 1769 } 1770 /* else FW return SP to driver */ 1771 break; 1772 default: 1773 ret_cmd = true; 1774 break; 1775 } 1776 1777 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1778 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1779 sp->done(sp, res); 1780 } else { 1781 sp->done(sp, res); 1782 } 1783 } 1784 1785 /* 1786 * The caller must ensure that no completion interrupts will happen 1787 * while this function is in progress. 1788 */ 1789 static void 1790 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1791 { 1792 int cnt; 1793 unsigned long flags; 1794 srb_t *sp; 1795 scsi_qla_host_t *vha = qp->vha; 1796 struct qla_hw_data *ha = vha->hw; 1797 struct req_que *req; 1798 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1799 struct qla_tgt_cmd *cmd; 1800 1801 if (!ha->req_q_map) 1802 return; 1803 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1804 req = qp->req; 1805 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1806 sp = req->outstanding_cmds[cnt]; 1807 if (sp) { 1808 switch (sp->cmd_type) { 1809 case TYPE_SRB: 1810 qla2x00_abort_srb(qp, sp, res, &flags); 1811 break; 1812 case TYPE_TGT_CMD: 1813 if (!vha->hw->tgt.tgt_ops || !tgt || 1814 qla_ini_mode_enabled(vha)) { 1815 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1816 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1817 vha->dpc_flags); 1818 continue; 1819 } 1820 cmd = (struct qla_tgt_cmd *)sp; 1821 cmd->aborted = 1; 1822 break; 1823 case TYPE_TGT_TMCMD: 1824 /* Skip task management functions. */ 1825 break; 1826 default: 1827 break; 1828 } 1829 req->outstanding_cmds[cnt] = NULL; 1830 } 1831 } 1832 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1833 } 1834 1835 /* 1836 * The caller must ensure that no completion interrupts will happen 1837 * while this function is in progress. 1838 */ 1839 void 1840 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1841 { 1842 int que; 1843 struct qla_hw_data *ha = vha->hw; 1844 1845 /* Continue only if initialization complete. */ 1846 if (!ha->base_qpair) 1847 return; 1848 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1849 1850 if (!ha->queue_pair_map) 1851 return; 1852 for (que = 0; que < ha->max_qpairs; que++) { 1853 if (!ha->queue_pair_map[que]) 1854 continue; 1855 1856 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1857 } 1858 } 1859 1860 static int 1861 qla2xxx_slave_alloc(struct scsi_device *sdev) 1862 { 1863 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1864 1865 if (!rport || fc_remote_port_chkready(rport)) 1866 return -ENXIO; 1867 1868 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1869 1870 return 0; 1871 } 1872 1873 static int 1874 qla2xxx_slave_configure(struct scsi_device *sdev) 1875 { 1876 scsi_qla_host_t *vha = shost_priv(sdev->host); 1877 struct req_que *req = vha->req; 1878 1879 if (IS_T10_PI_CAPABLE(vha->hw)) 1880 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1881 1882 scsi_change_queue_depth(sdev, req->max_q_depth); 1883 return 0; 1884 } 1885 1886 static void 1887 qla2xxx_slave_destroy(struct scsi_device *sdev) 1888 { 1889 sdev->hostdata = NULL; 1890 } 1891 1892 /** 1893 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1894 * @ha: HA context 1895 * 1896 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1897 * supported addressing method. 1898 */ 1899 static void 1900 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1901 { 1902 /* Assume a 32bit DMA mask. */ 1903 ha->flags.enable_64bit_addressing = 0; 1904 1905 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1906 /* Any upper-dword bits set? */ 1907 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1908 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1909 /* Ok, a 64bit DMA mask is applicable. */ 1910 ha->flags.enable_64bit_addressing = 1; 1911 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1912 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1913 return; 1914 } 1915 } 1916 1917 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1918 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1919 } 1920 1921 static void 1922 qla2x00_enable_intrs(struct qla_hw_data *ha) 1923 { 1924 unsigned long flags = 0; 1925 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1926 1927 spin_lock_irqsave(&ha->hardware_lock, flags); 1928 ha->interrupts_on = 1; 1929 /* enable risc and host interrupts */ 1930 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1931 rd_reg_word(®->ictrl); 1932 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1933 1934 } 1935 1936 static void 1937 qla2x00_disable_intrs(struct qla_hw_data *ha) 1938 { 1939 unsigned long flags = 0; 1940 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1941 1942 spin_lock_irqsave(&ha->hardware_lock, flags); 1943 ha->interrupts_on = 0; 1944 /* disable risc and host interrupts */ 1945 wrt_reg_word(®->ictrl, 0); 1946 rd_reg_word(®->ictrl); 1947 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1948 } 1949 1950 static void 1951 qla24xx_enable_intrs(struct qla_hw_data *ha) 1952 { 1953 unsigned long flags = 0; 1954 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1955 1956 spin_lock_irqsave(&ha->hardware_lock, flags); 1957 ha->interrupts_on = 1; 1958 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1959 rd_reg_dword(®->ictrl); 1960 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1961 } 1962 1963 static void 1964 qla24xx_disable_intrs(struct qla_hw_data *ha) 1965 { 1966 unsigned long flags = 0; 1967 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1968 1969 if (IS_NOPOLLING_TYPE(ha)) 1970 return; 1971 spin_lock_irqsave(&ha->hardware_lock, flags); 1972 ha->interrupts_on = 0; 1973 wrt_reg_dword(®->ictrl, 0); 1974 rd_reg_dword(®->ictrl); 1975 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1976 } 1977 1978 static int 1979 qla2x00_iospace_config(struct qla_hw_data *ha) 1980 { 1981 resource_size_t pio; 1982 uint16_t msix; 1983 1984 if (pci_request_selected_regions(ha->pdev, ha->bars, 1985 QLA2XXX_DRIVER_NAME)) { 1986 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1987 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1988 pci_name(ha->pdev)); 1989 goto iospace_error_exit; 1990 } 1991 if (!(ha->bars & 1)) 1992 goto skip_pio; 1993 1994 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1995 pio = pci_resource_start(ha->pdev, 0); 1996 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1997 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1998 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1999 "Invalid pci I/O region size (%s).\n", 2000 pci_name(ha->pdev)); 2001 pio = 0; 2002 } 2003 } else { 2004 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2005 "Region #0 no a PIO resource (%s).\n", 2006 pci_name(ha->pdev)); 2007 pio = 0; 2008 } 2009 ha->pio_address = pio; 2010 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2011 "PIO address=%llu.\n", 2012 (unsigned long long)ha->pio_address); 2013 2014 skip_pio: 2015 /* Use MMIO operations for all accesses. */ 2016 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2017 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2018 "Region #1 not an MMIO resource (%s), aborting.\n", 2019 pci_name(ha->pdev)); 2020 goto iospace_error_exit; 2021 } 2022 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2023 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2024 "Invalid PCI mem region size (%s), aborting.\n", 2025 pci_name(ha->pdev)); 2026 goto iospace_error_exit; 2027 } 2028 2029 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2030 if (!ha->iobase) { 2031 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2032 "Cannot remap MMIO (%s), aborting.\n", 2033 pci_name(ha->pdev)); 2034 goto iospace_error_exit; 2035 } 2036 2037 /* Determine queue resources */ 2038 ha->max_req_queues = ha->max_rsp_queues = 1; 2039 ha->msix_count = QLA_BASE_VECTORS; 2040 2041 /* Check if FW supports MQ or not */ 2042 if (!(ha->fw_attributes & BIT_6)) 2043 goto mqiobase_exit; 2044 2045 if (!ql2xmqsupport || !ql2xnvmeenable || 2046 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2047 goto mqiobase_exit; 2048 2049 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2050 pci_resource_len(ha->pdev, 3)); 2051 if (ha->mqiobase) { 2052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2053 "MQIO Base=%p.\n", ha->mqiobase); 2054 /* Read MSIX vector size of the board */ 2055 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2056 ha->msix_count = msix + 1; 2057 /* Max queues are bounded by available msix vectors */ 2058 /* MB interrupt uses 1 vector */ 2059 ha->max_req_queues = ha->msix_count - 1; 2060 ha->max_rsp_queues = ha->max_req_queues; 2061 /* Queue pairs is the max value minus the base queue pair */ 2062 ha->max_qpairs = ha->max_rsp_queues - 1; 2063 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2064 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2065 2066 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2067 "MSI-X vector count: %d.\n", ha->msix_count); 2068 } else 2069 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2070 "BAR 3 not enabled.\n"); 2071 2072 mqiobase_exit: 2073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2074 "MSIX Count: %d.\n", ha->msix_count); 2075 return (0); 2076 2077 iospace_error_exit: 2078 return (-ENOMEM); 2079 } 2080 2081 2082 static int 2083 qla83xx_iospace_config(struct qla_hw_data *ha) 2084 { 2085 uint16_t msix; 2086 2087 if (pci_request_selected_regions(ha->pdev, ha->bars, 2088 QLA2XXX_DRIVER_NAME)) { 2089 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2090 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2091 pci_name(ha->pdev)); 2092 2093 goto iospace_error_exit; 2094 } 2095 2096 /* Use MMIO operations for all accesses. */ 2097 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2098 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2099 "Invalid pci I/O region size (%s).\n", 2100 pci_name(ha->pdev)); 2101 goto iospace_error_exit; 2102 } 2103 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2104 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2105 "Invalid PCI mem region size (%s), aborting\n", 2106 pci_name(ha->pdev)); 2107 goto iospace_error_exit; 2108 } 2109 2110 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2111 if (!ha->iobase) { 2112 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2113 "Cannot remap MMIO (%s), aborting.\n", 2114 pci_name(ha->pdev)); 2115 goto iospace_error_exit; 2116 } 2117 2118 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2119 /* 83XX 26XX always use MQ type access for queues 2120 * - mbar 2, a.k.a region 4 */ 2121 ha->max_req_queues = ha->max_rsp_queues = 1; 2122 ha->msix_count = QLA_BASE_VECTORS; 2123 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2124 pci_resource_len(ha->pdev, 4)); 2125 2126 if (!ha->mqiobase) { 2127 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2128 "BAR2/region4 not enabled\n"); 2129 goto mqiobase_exit; 2130 } 2131 2132 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2133 pci_resource_len(ha->pdev, 2)); 2134 if (ha->msixbase) { 2135 /* Read MSIX vector size of the board */ 2136 pci_read_config_word(ha->pdev, 2137 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2138 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2139 /* 2140 * By default, driver uses at least two msix vectors 2141 * (default & rspq) 2142 */ 2143 if (ql2xmqsupport || ql2xnvmeenable) { 2144 /* MB interrupt uses 1 vector */ 2145 ha->max_req_queues = ha->msix_count - 1; 2146 2147 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2148 if (QLA_TGT_MODE_ENABLED()) 2149 ha->max_req_queues--; 2150 2151 ha->max_rsp_queues = ha->max_req_queues; 2152 2153 /* Queue pairs is the max value minus 2154 * the base queue pair */ 2155 ha->max_qpairs = ha->max_req_queues - 1; 2156 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2157 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2158 } 2159 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2160 "MSI-X vector count: %d.\n", ha->msix_count); 2161 } else 2162 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2163 "BAR 1 not enabled.\n"); 2164 2165 mqiobase_exit: 2166 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2167 "MSIX Count: %d.\n", ha->msix_count); 2168 return 0; 2169 2170 iospace_error_exit: 2171 return -ENOMEM; 2172 } 2173 2174 static struct isp_operations qla2100_isp_ops = { 2175 .pci_config = qla2100_pci_config, 2176 .reset_chip = qla2x00_reset_chip, 2177 .chip_diag = qla2x00_chip_diag, 2178 .config_rings = qla2x00_config_rings, 2179 .reset_adapter = qla2x00_reset_adapter, 2180 .nvram_config = qla2x00_nvram_config, 2181 .update_fw_options = qla2x00_update_fw_options, 2182 .load_risc = qla2x00_load_risc, 2183 .pci_info_str = qla2x00_pci_info_str, 2184 .fw_version_str = qla2x00_fw_version_str, 2185 .intr_handler = qla2100_intr_handler, 2186 .enable_intrs = qla2x00_enable_intrs, 2187 .disable_intrs = qla2x00_disable_intrs, 2188 .abort_command = qla2x00_abort_command, 2189 .target_reset = qla2x00_abort_target, 2190 .lun_reset = qla2x00_lun_reset, 2191 .fabric_login = qla2x00_login_fabric, 2192 .fabric_logout = qla2x00_fabric_logout, 2193 .calc_req_entries = qla2x00_calc_iocbs_32, 2194 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2195 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2196 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2197 .read_nvram = qla2x00_read_nvram_data, 2198 .write_nvram = qla2x00_write_nvram_data, 2199 .fw_dump = qla2100_fw_dump, 2200 .beacon_on = NULL, 2201 .beacon_off = NULL, 2202 .beacon_blink = NULL, 2203 .read_optrom = qla2x00_read_optrom_data, 2204 .write_optrom = qla2x00_write_optrom_data, 2205 .get_flash_version = qla2x00_get_flash_version, 2206 .start_scsi = qla2x00_start_scsi, 2207 .start_scsi_mq = NULL, 2208 .abort_isp = qla2x00_abort_isp, 2209 .iospace_config = qla2x00_iospace_config, 2210 .initialize_adapter = qla2x00_initialize_adapter, 2211 }; 2212 2213 static struct isp_operations qla2300_isp_ops = { 2214 .pci_config = qla2300_pci_config, 2215 .reset_chip = qla2x00_reset_chip, 2216 .chip_diag = qla2x00_chip_diag, 2217 .config_rings = qla2x00_config_rings, 2218 .reset_adapter = qla2x00_reset_adapter, 2219 .nvram_config = qla2x00_nvram_config, 2220 .update_fw_options = qla2x00_update_fw_options, 2221 .load_risc = qla2x00_load_risc, 2222 .pci_info_str = qla2x00_pci_info_str, 2223 .fw_version_str = qla2x00_fw_version_str, 2224 .intr_handler = qla2300_intr_handler, 2225 .enable_intrs = qla2x00_enable_intrs, 2226 .disable_intrs = qla2x00_disable_intrs, 2227 .abort_command = qla2x00_abort_command, 2228 .target_reset = qla2x00_abort_target, 2229 .lun_reset = qla2x00_lun_reset, 2230 .fabric_login = qla2x00_login_fabric, 2231 .fabric_logout = qla2x00_fabric_logout, 2232 .calc_req_entries = qla2x00_calc_iocbs_32, 2233 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2234 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2235 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2236 .read_nvram = qla2x00_read_nvram_data, 2237 .write_nvram = qla2x00_write_nvram_data, 2238 .fw_dump = qla2300_fw_dump, 2239 .beacon_on = qla2x00_beacon_on, 2240 .beacon_off = qla2x00_beacon_off, 2241 .beacon_blink = qla2x00_beacon_blink, 2242 .read_optrom = qla2x00_read_optrom_data, 2243 .write_optrom = qla2x00_write_optrom_data, 2244 .get_flash_version = qla2x00_get_flash_version, 2245 .start_scsi = qla2x00_start_scsi, 2246 .start_scsi_mq = NULL, 2247 .abort_isp = qla2x00_abort_isp, 2248 .iospace_config = qla2x00_iospace_config, 2249 .initialize_adapter = qla2x00_initialize_adapter, 2250 }; 2251 2252 static struct isp_operations qla24xx_isp_ops = { 2253 .pci_config = qla24xx_pci_config, 2254 .reset_chip = qla24xx_reset_chip, 2255 .chip_diag = qla24xx_chip_diag, 2256 .config_rings = qla24xx_config_rings, 2257 .reset_adapter = qla24xx_reset_adapter, 2258 .nvram_config = qla24xx_nvram_config, 2259 .update_fw_options = qla24xx_update_fw_options, 2260 .load_risc = qla24xx_load_risc, 2261 .pci_info_str = qla24xx_pci_info_str, 2262 .fw_version_str = qla24xx_fw_version_str, 2263 .intr_handler = qla24xx_intr_handler, 2264 .enable_intrs = qla24xx_enable_intrs, 2265 .disable_intrs = qla24xx_disable_intrs, 2266 .abort_command = qla24xx_abort_command, 2267 .target_reset = qla24xx_abort_target, 2268 .lun_reset = qla24xx_lun_reset, 2269 .fabric_login = qla24xx_login_fabric, 2270 .fabric_logout = qla24xx_fabric_logout, 2271 .calc_req_entries = NULL, 2272 .build_iocbs = NULL, 2273 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2274 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2275 .read_nvram = qla24xx_read_nvram_data, 2276 .write_nvram = qla24xx_write_nvram_data, 2277 .fw_dump = qla24xx_fw_dump, 2278 .beacon_on = qla24xx_beacon_on, 2279 .beacon_off = qla24xx_beacon_off, 2280 .beacon_blink = qla24xx_beacon_blink, 2281 .read_optrom = qla24xx_read_optrom_data, 2282 .write_optrom = qla24xx_write_optrom_data, 2283 .get_flash_version = qla24xx_get_flash_version, 2284 .start_scsi = qla24xx_start_scsi, 2285 .start_scsi_mq = NULL, 2286 .abort_isp = qla2x00_abort_isp, 2287 .iospace_config = qla2x00_iospace_config, 2288 .initialize_adapter = qla2x00_initialize_adapter, 2289 }; 2290 2291 static struct isp_operations qla25xx_isp_ops = { 2292 .pci_config = qla25xx_pci_config, 2293 .reset_chip = qla24xx_reset_chip, 2294 .chip_diag = qla24xx_chip_diag, 2295 .config_rings = qla24xx_config_rings, 2296 .reset_adapter = qla24xx_reset_adapter, 2297 .nvram_config = qla24xx_nvram_config, 2298 .update_fw_options = qla24xx_update_fw_options, 2299 .load_risc = qla24xx_load_risc, 2300 .pci_info_str = qla24xx_pci_info_str, 2301 .fw_version_str = qla24xx_fw_version_str, 2302 .intr_handler = qla24xx_intr_handler, 2303 .enable_intrs = qla24xx_enable_intrs, 2304 .disable_intrs = qla24xx_disable_intrs, 2305 .abort_command = qla24xx_abort_command, 2306 .target_reset = qla24xx_abort_target, 2307 .lun_reset = qla24xx_lun_reset, 2308 .fabric_login = qla24xx_login_fabric, 2309 .fabric_logout = qla24xx_fabric_logout, 2310 .calc_req_entries = NULL, 2311 .build_iocbs = NULL, 2312 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2313 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2314 .read_nvram = qla25xx_read_nvram_data, 2315 .write_nvram = qla25xx_write_nvram_data, 2316 .fw_dump = qla25xx_fw_dump, 2317 .beacon_on = qla24xx_beacon_on, 2318 .beacon_off = qla24xx_beacon_off, 2319 .beacon_blink = qla24xx_beacon_blink, 2320 .read_optrom = qla25xx_read_optrom_data, 2321 .write_optrom = qla24xx_write_optrom_data, 2322 .get_flash_version = qla24xx_get_flash_version, 2323 .start_scsi = qla24xx_dif_start_scsi, 2324 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2325 .abort_isp = qla2x00_abort_isp, 2326 .iospace_config = qla2x00_iospace_config, 2327 .initialize_adapter = qla2x00_initialize_adapter, 2328 }; 2329 2330 static struct isp_operations qla81xx_isp_ops = { 2331 .pci_config = qla25xx_pci_config, 2332 .reset_chip = qla24xx_reset_chip, 2333 .chip_diag = qla24xx_chip_diag, 2334 .config_rings = qla24xx_config_rings, 2335 .reset_adapter = qla24xx_reset_adapter, 2336 .nvram_config = qla81xx_nvram_config, 2337 .update_fw_options = qla24xx_update_fw_options, 2338 .load_risc = qla81xx_load_risc, 2339 .pci_info_str = qla24xx_pci_info_str, 2340 .fw_version_str = qla24xx_fw_version_str, 2341 .intr_handler = qla24xx_intr_handler, 2342 .enable_intrs = qla24xx_enable_intrs, 2343 .disable_intrs = qla24xx_disable_intrs, 2344 .abort_command = qla24xx_abort_command, 2345 .target_reset = qla24xx_abort_target, 2346 .lun_reset = qla24xx_lun_reset, 2347 .fabric_login = qla24xx_login_fabric, 2348 .fabric_logout = qla24xx_fabric_logout, 2349 .calc_req_entries = NULL, 2350 .build_iocbs = NULL, 2351 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2352 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2353 .read_nvram = NULL, 2354 .write_nvram = NULL, 2355 .fw_dump = qla81xx_fw_dump, 2356 .beacon_on = qla24xx_beacon_on, 2357 .beacon_off = qla24xx_beacon_off, 2358 .beacon_blink = qla83xx_beacon_blink, 2359 .read_optrom = qla25xx_read_optrom_data, 2360 .write_optrom = qla24xx_write_optrom_data, 2361 .get_flash_version = qla24xx_get_flash_version, 2362 .start_scsi = qla24xx_dif_start_scsi, 2363 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2364 .abort_isp = qla2x00_abort_isp, 2365 .iospace_config = qla2x00_iospace_config, 2366 .initialize_adapter = qla2x00_initialize_adapter, 2367 }; 2368 2369 static struct isp_operations qla82xx_isp_ops = { 2370 .pci_config = qla82xx_pci_config, 2371 .reset_chip = qla82xx_reset_chip, 2372 .chip_diag = qla24xx_chip_diag, 2373 .config_rings = qla82xx_config_rings, 2374 .reset_adapter = qla24xx_reset_adapter, 2375 .nvram_config = qla81xx_nvram_config, 2376 .update_fw_options = qla24xx_update_fw_options, 2377 .load_risc = qla82xx_load_risc, 2378 .pci_info_str = qla24xx_pci_info_str, 2379 .fw_version_str = qla24xx_fw_version_str, 2380 .intr_handler = qla82xx_intr_handler, 2381 .enable_intrs = qla82xx_enable_intrs, 2382 .disable_intrs = qla82xx_disable_intrs, 2383 .abort_command = qla24xx_abort_command, 2384 .target_reset = qla24xx_abort_target, 2385 .lun_reset = qla24xx_lun_reset, 2386 .fabric_login = qla24xx_login_fabric, 2387 .fabric_logout = qla24xx_fabric_logout, 2388 .calc_req_entries = NULL, 2389 .build_iocbs = NULL, 2390 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2391 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2392 .read_nvram = qla24xx_read_nvram_data, 2393 .write_nvram = qla24xx_write_nvram_data, 2394 .fw_dump = qla82xx_fw_dump, 2395 .beacon_on = qla82xx_beacon_on, 2396 .beacon_off = qla82xx_beacon_off, 2397 .beacon_blink = NULL, 2398 .read_optrom = qla82xx_read_optrom_data, 2399 .write_optrom = qla82xx_write_optrom_data, 2400 .get_flash_version = qla82xx_get_flash_version, 2401 .start_scsi = qla82xx_start_scsi, 2402 .start_scsi_mq = NULL, 2403 .abort_isp = qla82xx_abort_isp, 2404 .iospace_config = qla82xx_iospace_config, 2405 .initialize_adapter = qla2x00_initialize_adapter, 2406 }; 2407 2408 static struct isp_operations qla8044_isp_ops = { 2409 .pci_config = qla82xx_pci_config, 2410 .reset_chip = qla82xx_reset_chip, 2411 .chip_diag = qla24xx_chip_diag, 2412 .config_rings = qla82xx_config_rings, 2413 .reset_adapter = qla24xx_reset_adapter, 2414 .nvram_config = qla81xx_nvram_config, 2415 .update_fw_options = qla24xx_update_fw_options, 2416 .load_risc = qla82xx_load_risc, 2417 .pci_info_str = qla24xx_pci_info_str, 2418 .fw_version_str = qla24xx_fw_version_str, 2419 .intr_handler = qla8044_intr_handler, 2420 .enable_intrs = qla82xx_enable_intrs, 2421 .disable_intrs = qla82xx_disable_intrs, 2422 .abort_command = qla24xx_abort_command, 2423 .target_reset = qla24xx_abort_target, 2424 .lun_reset = qla24xx_lun_reset, 2425 .fabric_login = qla24xx_login_fabric, 2426 .fabric_logout = qla24xx_fabric_logout, 2427 .calc_req_entries = NULL, 2428 .build_iocbs = NULL, 2429 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2430 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2431 .read_nvram = NULL, 2432 .write_nvram = NULL, 2433 .fw_dump = qla8044_fw_dump, 2434 .beacon_on = qla82xx_beacon_on, 2435 .beacon_off = qla82xx_beacon_off, 2436 .beacon_blink = NULL, 2437 .read_optrom = qla8044_read_optrom_data, 2438 .write_optrom = qla8044_write_optrom_data, 2439 .get_flash_version = qla82xx_get_flash_version, 2440 .start_scsi = qla82xx_start_scsi, 2441 .start_scsi_mq = NULL, 2442 .abort_isp = qla8044_abort_isp, 2443 .iospace_config = qla82xx_iospace_config, 2444 .initialize_adapter = qla2x00_initialize_adapter, 2445 }; 2446 2447 static struct isp_operations qla83xx_isp_ops = { 2448 .pci_config = qla25xx_pci_config, 2449 .reset_chip = qla24xx_reset_chip, 2450 .chip_diag = qla24xx_chip_diag, 2451 .config_rings = qla24xx_config_rings, 2452 .reset_adapter = qla24xx_reset_adapter, 2453 .nvram_config = qla81xx_nvram_config, 2454 .update_fw_options = qla24xx_update_fw_options, 2455 .load_risc = qla81xx_load_risc, 2456 .pci_info_str = qla24xx_pci_info_str, 2457 .fw_version_str = qla24xx_fw_version_str, 2458 .intr_handler = qla24xx_intr_handler, 2459 .enable_intrs = qla24xx_enable_intrs, 2460 .disable_intrs = qla24xx_disable_intrs, 2461 .abort_command = qla24xx_abort_command, 2462 .target_reset = qla24xx_abort_target, 2463 .lun_reset = qla24xx_lun_reset, 2464 .fabric_login = qla24xx_login_fabric, 2465 .fabric_logout = qla24xx_fabric_logout, 2466 .calc_req_entries = NULL, 2467 .build_iocbs = NULL, 2468 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2469 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2470 .read_nvram = NULL, 2471 .write_nvram = NULL, 2472 .fw_dump = qla83xx_fw_dump, 2473 .beacon_on = qla24xx_beacon_on, 2474 .beacon_off = qla24xx_beacon_off, 2475 .beacon_blink = qla83xx_beacon_blink, 2476 .read_optrom = qla25xx_read_optrom_data, 2477 .write_optrom = qla24xx_write_optrom_data, 2478 .get_flash_version = qla24xx_get_flash_version, 2479 .start_scsi = qla24xx_dif_start_scsi, 2480 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2481 .abort_isp = qla2x00_abort_isp, 2482 .iospace_config = qla83xx_iospace_config, 2483 .initialize_adapter = qla2x00_initialize_adapter, 2484 }; 2485 2486 static struct isp_operations qlafx00_isp_ops = { 2487 .pci_config = qlafx00_pci_config, 2488 .reset_chip = qlafx00_soft_reset, 2489 .chip_diag = qlafx00_chip_diag, 2490 .config_rings = qlafx00_config_rings, 2491 .reset_adapter = qlafx00_soft_reset, 2492 .nvram_config = NULL, 2493 .update_fw_options = NULL, 2494 .load_risc = NULL, 2495 .pci_info_str = qlafx00_pci_info_str, 2496 .fw_version_str = qlafx00_fw_version_str, 2497 .intr_handler = qlafx00_intr_handler, 2498 .enable_intrs = qlafx00_enable_intrs, 2499 .disable_intrs = qlafx00_disable_intrs, 2500 .abort_command = qla24xx_async_abort_command, 2501 .target_reset = qlafx00_abort_target, 2502 .lun_reset = qlafx00_lun_reset, 2503 .fabric_login = NULL, 2504 .fabric_logout = NULL, 2505 .calc_req_entries = NULL, 2506 .build_iocbs = NULL, 2507 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2508 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2509 .read_nvram = qla24xx_read_nvram_data, 2510 .write_nvram = qla24xx_write_nvram_data, 2511 .fw_dump = NULL, 2512 .beacon_on = qla24xx_beacon_on, 2513 .beacon_off = qla24xx_beacon_off, 2514 .beacon_blink = NULL, 2515 .read_optrom = qla24xx_read_optrom_data, 2516 .write_optrom = qla24xx_write_optrom_data, 2517 .get_flash_version = qla24xx_get_flash_version, 2518 .start_scsi = qlafx00_start_scsi, 2519 .start_scsi_mq = NULL, 2520 .abort_isp = qlafx00_abort_isp, 2521 .iospace_config = qlafx00_iospace_config, 2522 .initialize_adapter = qlafx00_initialize_adapter, 2523 }; 2524 2525 static struct isp_operations qla27xx_isp_ops = { 2526 .pci_config = qla25xx_pci_config, 2527 .reset_chip = qla24xx_reset_chip, 2528 .chip_diag = qla24xx_chip_diag, 2529 .config_rings = qla24xx_config_rings, 2530 .reset_adapter = qla24xx_reset_adapter, 2531 .nvram_config = qla81xx_nvram_config, 2532 .update_fw_options = qla24xx_update_fw_options, 2533 .load_risc = qla81xx_load_risc, 2534 .pci_info_str = qla24xx_pci_info_str, 2535 .fw_version_str = qla24xx_fw_version_str, 2536 .intr_handler = qla24xx_intr_handler, 2537 .enable_intrs = qla24xx_enable_intrs, 2538 .disable_intrs = qla24xx_disable_intrs, 2539 .abort_command = qla24xx_abort_command, 2540 .target_reset = qla24xx_abort_target, 2541 .lun_reset = qla24xx_lun_reset, 2542 .fabric_login = qla24xx_login_fabric, 2543 .fabric_logout = qla24xx_fabric_logout, 2544 .calc_req_entries = NULL, 2545 .build_iocbs = NULL, 2546 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2547 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2548 .read_nvram = NULL, 2549 .write_nvram = NULL, 2550 .fw_dump = qla27xx_fwdump, 2551 .mpi_fw_dump = qla27xx_mpi_fwdump, 2552 .beacon_on = qla24xx_beacon_on, 2553 .beacon_off = qla24xx_beacon_off, 2554 .beacon_blink = qla83xx_beacon_blink, 2555 .read_optrom = qla25xx_read_optrom_data, 2556 .write_optrom = qla24xx_write_optrom_data, 2557 .get_flash_version = qla24xx_get_flash_version, 2558 .start_scsi = qla24xx_dif_start_scsi, 2559 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2560 .abort_isp = qla2x00_abort_isp, 2561 .iospace_config = qla83xx_iospace_config, 2562 .initialize_adapter = qla2x00_initialize_adapter, 2563 }; 2564 2565 static inline void 2566 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2567 { 2568 ha->device_type = DT_EXTENDED_IDS; 2569 switch (ha->pdev->device) { 2570 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2571 ha->isp_type |= DT_ISP2100; 2572 ha->device_type &= ~DT_EXTENDED_IDS; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2576 ha->isp_type |= DT_ISP2200; 2577 ha->device_type &= ~DT_EXTENDED_IDS; 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2579 break; 2580 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2581 ha->isp_type |= DT_ISP2300; 2582 ha->device_type |= DT_ZIO_SUPPORTED; 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2584 break; 2585 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2586 ha->isp_type |= DT_ISP2312; 2587 ha->device_type |= DT_ZIO_SUPPORTED; 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2591 ha->isp_type |= DT_ISP2322; 2592 ha->device_type |= DT_ZIO_SUPPORTED; 2593 if (ha->pdev->subsystem_vendor == 0x1028 && 2594 ha->pdev->subsystem_device == 0x0170) 2595 ha->device_type |= DT_OEM_001; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2599 ha->isp_type |= DT_ISP6312; 2600 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2601 break; 2602 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2603 ha->isp_type |= DT_ISP6322; 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2607 ha->isp_type |= DT_ISP2422; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->device_type |= DT_IIDMA; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2614 ha->isp_type |= DT_ISP2432; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->device_type |= DT_IIDMA; 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2619 break; 2620 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2621 ha->isp_type |= DT_ISP8432; 2622 ha->device_type |= DT_ZIO_SUPPORTED; 2623 ha->device_type |= DT_FWI2; 2624 ha->device_type |= DT_IIDMA; 2625 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2626 break; 2627 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2628 ha->isp_type |= DT_ISP5422; 2629 ha->device_type |= DT_FWI2; 2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2631 break; 2632 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2633 ha->isp_type |= DT_ISP5432; 2634 ha->device_type |= DT_FWI2; 2635 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2636 break; 2637 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2638 ha->isp_type |= DT_ISP2532; 2639 ha->device_type |= DT_ZIO_SUPPORTED; 2640 ha->device_type |= DT_FWI2; 2641 ha->device_type |= DT_IIDMA; 2642 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2645 ha->isp_type |= DT_ISP8001; 2646 ha->device_type |= DT_ZIO_SUPPORTED; 2647 ha->device_type |= DT_FWI2; 2648 ha->device_type |= DT_IIDMA; 2649 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2650 break; 2651 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2652 ha->isp_type |= DT_ISP8021; 2653 ha->device_type |= DT_ZIO_SUPPORTED; 2654 ha->device_type |= DT_FWI2; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 /* Initialize 82XX ISP flags */ 2657 qla82xx_init_flags(ha); 2658 break; 2659 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2660 ha->isp_type |= DT_ISP8044; 2661 ha->device_type |= DT_ZIO_SUPPORTED; 2662 ha->device_type |= DT_FWI2; 2663 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2664 /* Initialize 82XX ISP flags */ 2665 qla82xx_init_flags(ha); 2666 break; 2667 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2668 ha->isp_type |= DT_ISP2031; 2669 ha->device_type |= DT_ZIO_SUPPORTED; 2670 ha->device_type |= DT_FWI2; 2671 ha->device_type |= DT_IIDMA; 2672 ha->device_type |= DT_T10_PI; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2674 break; 2675 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2676 ha->isp_type |= DT_ISP8031; 2677 ha->device_type |= DT_ZIO_SUPPORTED; 2678 ha->device_type |= DT_FWI2; 2679 ha->device_type |= DT_IIDMA; 2680 ha->device_type |= DT_T10_PI; 2681 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2682 break; 2683 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2684 ha->isp_type |= DT_ISPFX00; 2685 break; 2686 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2687 ha->isp_type |= DT_ISP2071; 2688 ha->device_type |= DT_ZIO_SUPPORTED; 2689 ha->device_type |= DT_FWI2; 2690 ha->device_type |= DT_IIDMA; 2691 ha->device_type |= DT_T10_PI; 2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2693 break; 2694 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2695 ha->isp_type |= DT_ISP2271; 2696 ha->device_type |= DT_ZIO_SUPPORTED; 2697 ha->device_type |= DT_FWI2; 2698 ha->device_type |= DT_IIDMA; 2699 ha->device_type |= DT_T10_PI; 2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2701 break; 2702 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2703 ha->isp_type |= DT_ISP2261; 2704 ha->device_type |= DT_ZIO_SUPPORTED; 2705 ha->device_type |= DT_FWI2; 2706 ha->device_type |= DT_IIDMA; 2707 ha->device_type |= DT_T10_PI; 2708 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2709 break; 2710 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2711 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2712 ha->isp_type |= DT_ISP2081; 2713 ha->device_type |= DT_ZIO_SUPPORTED; 2714 ha->device_type |= DT_FWI2; 2715 ha->device_type |= DT_IIDMA; 2716 ha->device_type |= DT_T10_PI; 2717 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2718 break; 2719 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2720 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2721 ha->isp_type |= DT_ISP2281; 2722 ha->device_type |= DT_ZIO_SUPPORTED; 2723 ha->device_type |= DT_FWI2; 2724 ha->device_type |= DT_IIDMA; 2725 ha->device_type |= DT_T10_PI; 2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2727 break; 2728 } 2729 2730 if (IS_QLA82XX(ha)) 2731 ha->port_no = ha->portnum & 1; 2732 else { 2733 /* Get adapter physical port no from interrupt pin register. */ 2734 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2735 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2736 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2737 ha->port_no--; 2738 else 2739 ha->port_no = !(ha->port_no & 1); 2740 } 2741 2742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2743 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2744 ha->device_type, ha->port_no, ha->fw_srisc_address); 2745 } 2746 2747 static void 2748 qla2xxx_scan_start(struct Scsi_Host *shost) 2749 { 2750 scsi_qla_host_t *vha = shost_priv(shost); 2751 2752 if (vha->hw->flags.running_gold_fw) 2753 return; 2754 2755 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2756 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2757 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2758 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2759 } 2760 2761 static int 2762 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2763 { 2764 scsi_qla_host_t *vha = shost_priv(shost); 2765 2766 if (test_bit(UNLOADING, &vha->dpc_flags)) 2767 return 1; 2768 if (!vha->host) 2769 return 1; 2770 if (time > vha->hw->loop_reset_delay * HZ) 2771 return 1; 2772 2773 return atomic_read(&vha->loop_state) == LOOP_READY; 2774 } 2775 2776 static void qla_heartbeat_work_fn(struct work_struct *work) 2777 { 2778 struct qla_hw_data *ha = container_of(work, 2779 struct qla_hw_data, heartbeat_work); 2780 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2781 2782 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2783 qla_no_op_mb(base_vha); 2784 } 2785 2786 static void qla2x00_iocb_work_fn(struct work_struct *work) 2787 { 2788 struct scsi_qla_host *vha = container_of(work, 2789 struct scsi_qla_host, iocb_work); 2790 struct qla_hw_data *ha = vha->hw; 2791 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2792 int i = 2; 2793 unsigned long flags; 2794 2795 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2796 return; 2797 2798 while (!list_empty(&vha->work_list) && i > 0) { 2799 qla2x00_do_work(vha); 2800 i--; 2801 } 2802 2803 spin_lock_irqsave(&vha->work_lock, flags); 2804 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2805 spin_unlock_irqrestore(&vha->work_lock, flags); 2806 } 2807 2808 /* 2809 * PCI driver interface 2810 */ 2811 static int 2812 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2813 { 2814 int ret = -ENODEV; 2815 struct Scsi_Host *host; 2816 scsi_qla_host_t *base_vha = NULL; 2817 struct qla_hw_data *ha; 2818 char pci_info[30]; 2819 char fw_str[30], wq_name[30]; 2820 struct scsi_host_template *sht; 2821 int bars, mem_only = 0; 2822 uint16_t req_length = 0, rsp_length = 0; 2823 struct req_que *req = NULL; 2824 struct rsp_que *rsp = NULL; 2825 int i; 2826 2827 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2828 sht = &qla2xxx_driver_template; 2829 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2830 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2831 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2832 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2833 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2834 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2835 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2836 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2837 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2838 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2839 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2840 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2841 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2842 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2843 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2844 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2845 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2846 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2847 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2848 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2849 mem_only = 1; 2850 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2851 "Mem only adapter.\n"); 2852 } 2853 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2854 "Bars=%d.\n", bars); 2855 2856 if (mem_only) { 2857 if (pci_enable_device_mem(pdev)) 2858 return ret; 2859 } else { 2860 if (pci_enable_device(pdev)) 2861 return ret; 2862 } 2863 2864 if (is_kdump_kernel()) { 2865 ql2xmqsupport = 0; 2866 ql2xallocfwdump = 0; 2867 } 2868 2869 /* This may fail but that's ok */ 2870 pci_enable_pcie_error_reporting(pdev); 2871 2872 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2873 if (!ha) { 2874 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2875 "Unable to allocate memory for ha.\n"); 2876 goto disable_device; 2877 } 2878 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2879 "Memory allocated for ha=%p.\n", ha); 2880 ha->pdev = pdev; 2881 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2882 spin_lock_init(&ha->tgt.q_full_lock); 2883 spin_lock_init(&ha->tgt.sess_lock); 2884 spin_lock_init(&ha->tgt.atio_lock); 2885 2886 spin_lock_init(&ha->sadb_lock); 2887 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2888 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2889 2890 spin_lock_init(&ha->sadb_fp_lock); 2891 2892 if (qla_edif_sadb_build_free_pool(ha)) { 2893 kfree(ha); 2894 goto disable_device; 2895 } 2896 2897 atomic_set(&ha->nvme_active_aen_cnt, 0); 2898 2899 /* Clear our data area */ 2900 ha->bars = bars; 2901 ha->mem_only = mem_only; 2902 spin_lock_init(&ha->hardware_lock); 2903 spin_lock_init(&ha->vport_slock); 2904 mutex_init(&ha->selflogin_lock); 2905 mutex_init(&ha->optrom_mutex); 2906 2907 /* Set ISP-type information. */ 2908 qla2x00_set_isp_flags(ha); 2909 2910 /* Set EEH reset type to fundamental if required by hba */ 2911 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2912 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2913 pdev->needs_freset = 1; 2914 2915 ha->prev_topology = 0; 2916 ha->init_cb_size = sizeof(init_cb_t); 2917 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2918 ha->optrom_size = OPTROM_SIZE_2300; 2919 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2920 atomic_set(&ha->num_pend_mbx_stage1, 0); 2921 atomic_set(&ha->num_pend_mbx_stage2, 0); 2922 atomic_set(&ha->num_pend_mbx_stage3, 0); 2923 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2924 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2925 2926 /* Assign ISP specific operations. */ 2927 if (IS_QLA2100(ha)) { 2928 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2929 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2930 req_length = REQUEST_ENTRY_CNT_2100; 2931 rsp_length = RESPONSE_ENTRY_CNT_2100; 2932 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2933 ha->gid_list_info_size = 4; 2934 ha->flash_conf_off = ~0; 2935 ha->flash_data_off = ~0; 2936 ha->nvram_conf_off = ~0; 2937 ha->nvram_data_off = ~0; 2938 ha->isp_ops = &qla2100_isp_ops; 2939 } else if (IS_QLA2200(ha)) { 2940 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2941 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2942 req_length = REQUEST_ENTRY_CNT_2200; 2943 rsp_length = RESPONSE_ENTRY_CNT_2100; 2944 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2945 ha->gid_list_info_size = 4; 2946 ha->flash_conf_off = ~0; 2947 ha->flash_data_off = ~0; 2948 ha->nvram_conf_off = ~0; 2949 ha->nvram_data_off = ~0; 2950 ha->isp_ops = &qla2100_isp_ops; 2951 } else if (IS_QLA23XX(ha)) { 2952 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2953 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2954 req_length = REQUEST_ENTRY_CNT_2200; 2955 rsp_length = RESPONSE_ENTRY_CNT_2300; 2956 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2957 ha->gid_list_info_size = 6; 2958 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2959 ha->optrom_size = OPTROM_SIZE_2322; 2960 ha->flash_conf_off = ~0; 2961 ha->flash_data_off = ~0; 2962 ha->nvram_conf_off = ~0; 2963 ha->nvram_data_off = ~0; 2964 ha->isp_ops = &qla2300_isp_ops; 2965 } else if (IS_QLA24XX_TYPE(ha)) { 2966 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2967 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2968 req_length = REQUEST_ENTRY_CNT_24XX; 2969 rsp_length = RESPONSE_ENTRY_CNT_2300; 2970 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2971 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2972 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2973 ha->gid_list_info_size = 8; 2974 ha->optrom_size = OPTROM_SIZE_24XX; 2975 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2976 ha->isp_ops = &qla24xx_isp_ops; 2977 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2978 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2979 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2980 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2981 } else if (IS_QLA25XX(ha)) { 2982 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2983 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2984 req_length = REQUEST_ENTRY_CNT_24XX; 2985 rsp_length = RESPONSE_ENTRY_CNT_2300; 2986 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2987 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2988 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2989 ha->gid_list_info_size = 8; 2990 ha->optrom_size = OPTROM_SIZE_25XX; 2991 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2992 ha->isp_ops = &qla25xx_isp_ops; 2993 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2994 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2995 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2996 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2997 } else if (IS_QLA81XX(ha)) { 2998 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2999 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3000 req_length = REQUEST_ENTRY_CNT_24XX; 3001 rsp_length = RESPONSE_ENTRY_CNT_2300; 3002 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3003 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3004 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3005 ha->gid_list_info_size = 8; 3006 ha->optrom_size = OPTROM_SIZE_81XX; 3007 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3008 ha->isp_ops = &qla81xx_isp_ops; 3009 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3010 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3011 ha->nvram_conf_off = ~0; 3012 ha->nvram_data_off = ~0; 3013 } else if (IS_QLA82XX(ha)) { 3014 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3015 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3016 req_length = REQUEST_ENTRY_CNT_82XX; 3017 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3018 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3019 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3020 ha->gid_list_info_size = 8; 3021 ha->optrom_size = OPTROM_SIZE_82XX; 3022 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3023 ha->isp_ops = &qla82xx_isp_ops; 3024 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3025 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3026 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3027 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3028 } else if (IS_QLA8044(ha)) { 3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3030 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3031 req_length = REQUEST_ENTRY_CNT_82XX; 3032 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3033 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3034 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3035 ha->gid_list_info_size = 8; 3036 ha->optrom_size = OPTROM_SIZE_83XX; 3037 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3038 ha->isp_ops = &qla8044_isp_ops; 3039 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3040 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3041 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3042 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3043 } else if (IS_QLA83XX(ha)) { 3044 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3045 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3046 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3047 req_length = REQUEST_ENTRY_CNT_83XX; 3048 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3049 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3050 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3051 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3052 ha->gid_list_info_size = 8; 3053 ha->optrom_size = OPTROM_SIZE_83XX; 3054 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3055 ha->isp_ops = &qla83xx_isp_ops; 3056 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3057 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3058 ha->nvram_conf_off = ~0; 3059 ha->nvram_data_off = ~0; 3060 } else if (IS_QLAFX00(ha)) { 3061 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3062 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3063 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3064 req_length = REQUEST_ENTRY_CNT_FX00; 3065 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3066 ha->isp_ops = &qlafx00_isp_ops; 3067 ha->port_down_retry_count = 30; /* default value */ 3068 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3069 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3070 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3071 ha->mr.fw_hbt_en = 1; 3072 ha->mr.host_info_resend = false; 3073 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3074 } else if (IS_QLA27XX(ha)) { 3075 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3076 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3077 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3078 req_length = REQUEST_ENTRY_CNT_83XX; 3079 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3080 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3081 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3082 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3083 ha->gid_list_info_size = 8; 3084 ha->optrom_size = OPTROM_SIZE_83XX; 3085 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3086 ha->isp_ops = &qla27xx_isp_ops; 3087 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3088 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3089 ha->nvram_conf_off = ~0; 3090 ha->nvram_data_off = ~0; 3091 } else if (IS_QLA28XX(ha)) { 3092 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3093 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3094 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3095 req_length = REQUEST_ENTRY_CNT_83XX; 3096 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3097 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3098 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3099 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3100 ha->gid_list_info_size = 8; 3101 ha->optrom_size = OPTROM_SIZE_28XX; 3102 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3103 ha->isp_ops = &qla27xx_isp_ops; 3104 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3105 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3106 ha->nvram_conf_off = ~0; 3107 ha->nvram_data_off = ~0; 3108 } 3109 3110 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3111 "mbx_count=%d, req_length=%d, " 3112 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3113 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3114 "max_fibre_devices=%d.\n", 3115 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3116 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3117 ha->nvram_npiv_size, ha->max_fibre_devices); 3118 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3119 "isp_ops=%p, flash_conf_off=%d, " 3120 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3121 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3122 ha->nvram_conf_off, ha->nvram_data_off); 3123 3124 /* Configure PCI I/O space */ 3125 ret = ha->isp_ops->iospace_config(ha); 3126 if (ret) 3127 goto iospace_config_failed; 3128 3129 ql_log_pci(ql_log_info, pdev, 0x001d, 3130 "Found an ISP%04X irq %d iobase 0x%p.\n", 3131 pdev->device, pdev->irq, ha->iobase); 3132 mutex_init(&ha->vport_lock); 3133 mutex_init(&ha->mq_lock); 3134 init_completion(&ha->mbx_cmd_comp); 3135 complete(&ha->mbx_cmd_comp); 3136 init_completion(&ha->mbx_intr_comp); 3137 init_completion(&ha->dcbx_comp); 3138 init_completion(&ha->lb_portup_comp); 3139 3140 set_bit(0, (unsigned long *) ha->vp_idx_map); 3141 3142 qla2x00_config_dma_addressing(ha); 3143 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3144 "64 Bit addressing is %s.\n", 3145 ha->flags.enable_64bit_addressing ? "enable" : 3146 "disable"); 3147 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3148 if (ret) { 3149 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3150 "Failed to allocate memory for adapter, aborting.\n"); 3151 3152 goto probe_hw_failed; 3153 } 3154 3155 req->max_q_depth = MAX_Q_DEPTH; 3156 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3157 req->max_q_depth = ql2xmaxqdepth; 3158 3159 3160 base_vha = qla2x00_create_host(sht, ha); 3161 if (!base_vha) { 3162 ret = -ENOMEM; 3163 goto probe_hw_failed; 3164 } 3165 3166 pci_set_drvdata(pdev, base_vha); 3167 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3168 3169 host = base_vha->host; 3170 base_vha->req = req; 3171 if (IS_QLA2XXX_MIDTYPE(ha)) 3172 base_vha->mgmt_svr_loop_id = 3173 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3174 else 3175 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3176 base_vha->vp_idx; 3177 3178 /* Setup fcport template structure. */ 3179 ha->mr.fcport.vha = base_vha; 3180 ha->mr.fcport.port_type = FCT_UNKNOWN; 3181 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3182 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3183 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3184 ha->mr.fcport.scan_state = 1; 3185 3186 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3187 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3188 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3189 3190 /* Set the SG table size based on ISP type */ 3191 if (!IS_FWI2_CAPABLE(ha)) { 3192 if (IS_QLA2100(ha)) 3193 host->sg_tablesize = 32; 3194 } else { 3195 if (!IS_QLA82XX(ha)) 3196 host->sg_tablesize = QLA_SG_ALL; 3197 } 3198 host->max_id = ha->max_fibre_devices; 3199 host->cmd_per_lun = 3; 3200 host->unique_id = host->host_no; 3201 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3202 host->max_cmd_len = 32; 3203 else 3204 host->max_cmd_len = MAX_CMDSZ; 3205 host->max_channel = MAX_BUSES - 1; 3206 /* Older HBAs support only 16-bit LUNs */ 3207 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3208 ql2xmaxlun > 0xffff) 3209 host->max_lun = 0xffff; 3210 else 3211 host->max_lun = ql2xmaxlun; 3212 host->transportt = qla2xxx_transport_template; 3213 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3214 3215 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3216 "max_id=%d this_id=%d " 3217 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3218 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3219 host->this_id, host->cmd_per_lun, host->unique_id, 3220 host->max_cmd_len, host->max_channel, host->max_lun, 3221 host->transportt, sht->vendor_id); 3222 3223 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3224 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3225 3226 /* Set up the irqs */ 3227 ret = qla2x00_request_irqs(ha, rsp); 3228 if (ret) 3229 goto probe_failed; 3230 3231 /* Alloc arrays of request and response ring ptrs */ 3232 ret = qla2x00_alloc_queues(ha, req, rsp); 3233 if (ret) { 3234 ql_log(ql_log_fatal, base_vha, 0x003d, 3235 "Failed to allocate memory for queue pointers..." 3236 "aborting.\n"); 3237 ret = -ENODEV; 3238 goto probe_failed; 3239 } 3240 3241 if (ha->mqenable) { 3242 /* number of hardware queues supported by blk/scsi-mq*/ 3243 host->nr_hw_queues = ha->max_qpairs; 3244 3245 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3246 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3247 } else { 3248 if (ql2xnvmeenable) { 3249 host->nr_hw_queues = ha->max_qpairs; 3250 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3251 "FC-NVMe support is enabled, HW queues=%d\n", 3252 host->nr_hw_queues); 3253 } else { 3254 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3255 "blk/scsi-mq disabled.\n"); 3256 } 3257 } 3258 3259 qlt_probe_one_stage1(base_vha, ha); 3260 3261 pci_save_state(pdev); 3262 3263 /* Assign back pointers */ 3264 rsp->req = req; 3265 req->rsp = rsp; 3266 3267 if (IS_QLAFX00(ha)) { 3268 ha->rsp_q_map[0] = rsp; 3269 ha->req_q_map[0] = req; 3270 set_bit(0, ha->req_qid_map); 3271 set_bit(0, ha->rsp_qid_map); 3272 } 3273 3274 /* FWI2-capable only. */ 3275 req->req_q_in = &ha->iobase->isp24.req_q_in; 3276 req->req_q_out = &ha->iobase->isp24.req_q_out; 3277 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3278 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3279 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3280 IS_QLA28XX(ha)) { 3281 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3282 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3283 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3284 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3285 } 3286 3287 if (IS_QLAFX00(ha)) { 3288 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3289 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3290 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3291 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3292 } 3293 3294 if (IS_P3P_TYPE(ha)) { 3295 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3296 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3297 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3298 } 3299 3300 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3301 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3302 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3303 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3304 "req->req_q_in=%p req->req_q_out=%p " 3305 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3306 req->req_q_in, req->req_q_out, 3307 rsp->rsp_q_in, rsp->rsp_q_out); 3308 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3309 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3310 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3311 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3312 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3313 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3314 3315 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3316 if (unlikely(!ha->wq)) { 3317 ret = -ENOMEM; 3318 goto probe_failed; 3319 } 3320 3321 if (ha->isp_ops->initialize_adapter(base_vha)) { 3322 ql_log(ql_log_fatal, base_vha, 0x00d6, 3323 "Failed to initialize adapter - Adapter flags %x.\n", 3324 base_vha->device_flags); 3325 3326 if (IS_QLA82XX(ha)) { 3327 qla82xx_idc_lock(ha); 3328 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3329 QLA8XXX_DEV_FAILED); 3330 qla82xx_idc_unlock(ha); 3331 ql_log(ql_log_fatal, base_vha, 0x00d7, 3332 "HW State: FAILED.\n"); 3333 } else if (IS_QLA8044(ha)) { 3334 qla8044_idc_lock(ha); 3335 qla8044_wr_direct(base_vha, 3336 QLA8044_CRB_DEV_STATE_INDEX, 3337 QLA8XXX_DEV_FAILED); 3338 qla8044_idc_unlock(ha); 3339 ql_log(ql_log_fatal, base_vha, 0x0150, 3340 "HW State: FAILED.\n"); 3341 } 3342 3343 ret = -ENODEV; 3344 goto probe_failed; 3345 } 3346 3347 if (IS_QLAFX00(ha)) 3348 host->can_queue = QLAFX00_MAX_CANQUEUE; 3349 else 3350 host->can_queue = req->num_outstanding_cmds - 10; 3351 3352 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3353 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3354 host->can_queue, base_vha->req, 3355 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3356 3357 /* Check if FW supports MQ or not for ISP25xx */ 3358 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3359 ha->mqenable = 0; 3360 3361 if (ha->mqenable) { 3362 bool startit = false; 3363 3364 if (QLA_TGT_MODE_ENABLED()) 3365 startit = false; 3366 3367 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3368 startit = true; 3369 3370 /* Create start of day qpairs for Block MQ */ 3371 for (i = 0; i < ha->max_qpairs; i++) 3372 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3373 } 3374 qla_init_iocb_limit(base_vha); 3375 3376 if (ha->flags.running_gold_fw) 3377 goto skip_dpc; 3378 3379 /* 3380 * Startup the kernel thread for this host adapter 3381 */ 3382 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3383 "%s_dpc", base_vha->host_str); 3384 if (IS_ERR(ha->dpc_thread)) { 3385 ql_log(ql_log_fatal, base_vha, 0x00ed, 3386 "Failed to start DPC thread.\n"); 3387 ret = PTR_ERR(ha->dpc_thread); 3388 ha->dpc_thread = NULL; 3389 goto probe_failed; 3390 } 3391 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3392 "DPC thread started successfully.\n"); 3393 3394 /* 3395 * If we're not coming up in initiator mode, we might sit for 3396 * a while without waking up the dpc thread, which leads to a 3397 * stuck process warning. So just kick the dpc once here and 3398 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3399 */ 3400 qla2xxx_wake_dpc(base_vha); 3401 3402 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3403 3404 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3405 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3406 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3407 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3408 3409 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3410 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3411 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3412 INIT_WORK(&ha->idc_state_handler, 3413 qla83xx_idc_state_handler_work); 3414 INIT_WORK(&ha->nic_core_unrecoverable, 3415 qla83xx_nic_core_unrecoverable_work); 3416 } 3417 3418 skip_dpc: 3419 list_add_tail(&base_vha->list, &ha->vp_list); 3420 base_vha->host->irq = ha->pdev->irq; 3421 3422 /* Initialized the timer */ 3423 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3424 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3425 "Started qla2x00_timer with " 3426 "interval=%d.\n", WATCH_INTERVAL); 3427 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3428 "Detected hba at address=%p.\n", 3429 ha); 3430 3431 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3432 if (ha->fw_attributes & BIT_4) { 3433 int prot = 0, guard; 3434 3435 base_vha->flags.difdix_supported = 1; 3436 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3437 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3438 if (ql2xenabledif == 1) 3439 prot = SHOST_DIX_TYPE0_PROTECTION; 3440 if (ql2xprotmask) 3441 scsi_host_set_prot(host, ql2xprotmask); 3442 else 3443 scsi_host_set_prot(host, 3444 prot | SHOST_DIF_TYPE1_PROTECTION 3445 | SHOST_DIF_TYPE2_PROTECTION 3446 | SHOST_DIF_TYPE3_PROTECTION 3447 | SHOST_DIX_TYPE1_PROTECTION 3448 | SHOST_DIX_TYPE2_PROTECTION 3449 | SHOST_DIX_TYPE3_PROTECTION); 3450 3451 guard = SHOST_DIX_GUARD_CRC; 3452 3453 if (IS_PI_IPGUARD_CAPABLE(ha) && 3454 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3455 guard |= SHOST_DIX_GUARD_IP; 3456 3457 if (ql2xprotguard) 3458 scsi_host_set_guard(host, ql2xprotguard); 3459 else 3460 scsi_host_set_guard(host, guard); 3461 } else 3462 base_vha->flags.difdix_supported = 0; 3463 } 3464 3465 ha->isp_ops->enable_intrs(ha); 3466 3467 if (IS_QLAFX00(ha)) { 3468 ret = qlafx00_fx_disc(base_vha, 3469 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3470 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3471 QLA_SG_ALL : 128; 3472 } 3473 3474 ret = scsi_add_host(host, &pdev->dev); 3475 if (ret) 3476 goto probe_failed; 3477 3478 base_vha->flags.init_done = 1; 3479 base_vha->flags.online = 1; 3480 ha->prev_minidump_failed = 0; 3481 3482 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3483 "Init done and hba is online.\n"); 3484 3485 if (qla_ini_mode_enabled(base_vha) || 3486 qla_dual_mode_enabled(base_vha)) 3487 scsi_scan_host(host); 3488 else 3489 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3490 "skipping scsi_scan_host() for non-initiator port\n"); 3491 3492 qla2x00_alloc_sysfs_attr(base_vha); 3493 3494 if (IS_QLAFX00(ha)) { 3495 ret = qlafx00_fx_disc(base_vha, 3496 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3497 3498 /* Register system information */ 3499 ret = qlafx00_fx_disc(base_vha, 3500 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3501 } 3502 3503 qla2x00_init_host_attr(base_vha); 3504 3505 qla2x00_dfs_setup(base_vha); 3506 3507 ql_log(ql_log_info, base_vha, 0x00fb, 3508 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3509 ql_log(ql_log_info, base_vha, 0x00fc, 3510 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3511 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3512 sizeof(pci_info)), 3513 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3514 base_vha->host_no, 3515 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3516 3517 qlt_add_target(ha, base_vha); 3518 3519 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3520 3521 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3522 return -ENODEV; 3523 3524 return 0; 3525 3526 probe_failed: 3527 qla_enode_stop(base_vha); 3528 qla_edb_stop(base_vha); 3529 if (base_vha->gnl.l) { 3530 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3531 base_vha->gnl.l, base_vha->gnl.ldma); 3532 base_vha->gnl.l = NULL; 3533 } 3534 3535 if (base_vha->timer_active) 3536 qla2x00_stop_timer(base_vha); 3537 base_vha->flags.online = 0; 3538 if (ha->dpc_thread) { 3539 struct task_struct *t = ha->dpc_thread; 3540 3541 ha->dpc_thread = NULL; 3542 kthread_stop(t); 3543 } 3544 3545 qla2x00_free_device(base_vha); 3546 scsi_host_put(base_vha->host); 3547 /* 3548 * Need to NULL out local req/rsp after 3549 * qla2x00_free_device => qla2x00_free_queues frees 3550 * what these are pointing to. Or else we'll 3551 * fall over below in qla2x00_free_req/rsp_que. 3552 */ 3553 req = NULL; 3554 rsp = NULL; 3555 3556 probe_hw_failed: 3557 qla2x00_mem_free(ha); 3558 qla2x00_free_req_que(ha, req); 3559 qla2x00_free_rsp_que(ha, rsp); 3560 qla2x00_clear_drv_active(ha); 3561 3562 iospace_config_failed: 3563 if (IS_P3P_TYPE(ha)) { 3564 if (!ha->nx_pcibase) 3565 iounmap((device_reg_t *)ha->nx_pcibase); 3566 if (!ql2xdbwr) 3567 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3568 } else { 3569 if (ha->iobase) 3570 iounmap(ha->iobase); 3571 if (ha->cregbase) 3572 iounmap(ha->cregbase); 3573 } 3574 pci_release_selected_regions(ha->pdev, ha->bars); 3575 kfree(ha); 3576 3577 disable_device: 3578 pci_disable_device(pdev); 3579 return ret; 3580 } 3581 3582 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3583 { 3584 scsi_qla_host_t *vp; 3585 unsigned long flags; 3586 struct qla_hw_data *ha; 3587 3588 if (!base_vha) 3589 return; 3590 3591 ha = base_vha->hw; 3592 3593 spin_lock_irqsave(&ha->vport_slock, flags); 3594 list_for_each_entry(vp, &ha->vp_list, list) 3595 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3596 3597 /* 3598 * Indicate device removal to prevent future board_disable 3599 * and wait until any pending board_disable has completed. 3600 */ 3601 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3602 spin_unlock_irqrestore(&ha->vport_slock, flags); 3603 } 3604 3605 static void 3606 qla2x00_shutdown(struct pci_dev *pdev) 3607 { 3608 scsi_qla_host_t *vha; 3609 struct qla_hw_data *ha; 3610 3611 vha = pci_get_drvdata(pdev); 3612 ha = vha->hw; 3613 3614 ql_log(ql_log_info, vha, 0xfffa, 3615 "Adapter shutdown\n"); 3616 3617 /* 3618 * Prevent future board_disable and wait 3619 * until any pending board_disable has completed. 3620 */ 3621 __qla_set_remove_flag(vha); 3622 cancel_work_sync(&ha->board_disable); 3623 3624 if (!atomic_read(&pdev->enable_cnt)) 3625 return; 3626 3627 /* Notify ISPFX00 firmware */ 3628 if (IS_QLAFX00(ha)) 3629 qlafx00_driver_shutdown(vha, 20); 3630 3631 /* Turn-off FCE trace */ 3632 if (ha->flags.fce_enabled) { 3633 qla2x00_disable_fce_trace(vha, NULL, NULL); 3634 ha->flags.fce_enabled = 0; 3635 } 3636 3637 /* Turn-off EFT trace */ 3638 if (ha->eft) 3639 qla2x00_disable_eft_trace(vha); 3640 3641 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3642 IS_QLA28XX(ha)) { 3643 if (ha->flags.fw_started) 3644 qla2x00_abort_isp_cleanup(vha); 3645 } else { 3646 /* Stop currently executing firmware. */ 3647 qla2x00_try_to_stop_firmware(vha); 3648 } 3649 3650 /* Disable timer */ 3651 if (vha->timer_active) 3652 qla2x00_stop_timer(vha); 3653 3654 /* Turn adapter off line */ 3655 vha->flags.online = 0; 3656 3657 /* turn-off interrupts on the card */ 3658 if (ha->interrupts_on) { 3659 vha->flags.init_done = 0; 3660 ha->isp_ops->disable_intrs(ha); 3661 } 3662 3663 qla2x00_free_irqs(vha); 3664 3665 qla2x00_free_fw_dump(ha); 3666 3667 pci_disable_device(pdev); 3668 ql_log(ql_log_info, vha, 0xfffe, 3669 "Adapter shutdown successfully.\n"); 3670 } 3671 3672 /* Deletes all the virtual ports for a given ha */ 3673 static void 3674 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3675 { 3676 scsi_qla_host_t *vha; 3677 unsigned long flags; 3678 3679 mutex_lock(&ha->vport_lock); 3680 while (ha->cur_vport_count) { 3681 spin_lock_irqsave(&ha->vport_slock, flags); 3682 3683 BUG_ON(base_vha->list.next == &ha->vp_list); 3684 /* This assumes first entry in ha->vp_list is always base vha */ 3685 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3686 scsi_host_get(vha->host); 3687 3688 spin_unlock_irqrestore(&ha->vport_slock, flags); 3689 mutex_unlock(&ha->vport_lock); 3690 3691 qla_nvme_delete(vha); 3692 3693 fc_vport_terminate(vha->fc_vport); 3694 scsi_host_put(vha->host); 3695 3696 mutex_lock(&ha->vport_lock); 3697 } 3698 mutex_unlock(&ha->vport_lock); 3699 } 3700 3701 /* Stops all deferred work threads */ 3702 static void 3703 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3704 { 3705 /* Cancel all work and destroy DPC workqueues */ 3706 if (ha->dpc_lp_wq) { 3707 cancel_work_sync(&ha->idc_aen); 3708 destroy_workqueue(ha->dpc_lp_wq); 3709 ha->dpc_lp_wq = NULL; 3710 } 3711 3712 if (ha->dpc_hp_wq) { 3713 cancel_work_sync(&ha->nic_core_reset); 3714 cancel_work_sync(&ha->idc_state_handler); 3715 cancel_work_sync(&ha->nic_core_unrecoverable); 3716 destroy_workqueue(ha->dpc_hp_wq); 3717 ha->dpc_hp_wq = NULL; 3718 } 3719 3720 /* Kill the kernel thread for this host */ 3721 if (ha->dpc_thread) { 3722 struct task_struct *t = ha->dpc_thread; 3723 3724 /* 3725 * qla2xxx_wake_dpc checks for ->dpc_thread 3726 * so we need to zero it out. 3727 */ 3728 ha->dpc_thread = NULL; 3729 kthread_stop(t); 3730 } 3731 } 3732 3733 static void 3734 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3735 { 3736 if (IS_QLA82XX(ha)) { 3737 3738 iounmap((device_reg_t *)ha->nx_pcibase); 3739 if (!ql2xdbwr) 3740 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3741 } else { 3742 if (ha->iobase) 3743 iounmap(ha->iobase); 3744 3745 if (ha->cregbase) 3746 iounmap(ha->cregbase); 3747 3748 if (ha->mqiobase) 3749 iounmap(ha->mqiobase); 3750 3751 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3752 ha->msixbase) 3753 iounmap(ha->msixbase); 3754 } 3755 } 3756 3757 static void 3758 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3759 { 3760 if (IS_QLA8044(ha)) { 3761 qla8044_idc_lock(ha); 3762 qla8044_clear_drv_active(ha); 3763 qla8044_idc_unlock(ha); 3764 } else if (IS_QLA82XX(ha)) { 3765 qla82xx_idc_lock(ha); 3766 qla82xx_clear_drv_active(ha); 3767 qla82xx_idc_unlock(ha); 3768 } 3769 } 3770 3771 static void 3772 qla2x00_remove_one(struct pci_dev *pdev) 3773 { 3774 scsi_qla_host_t *base_vha; 3775 struct qla_hw_data *ha; 3776 3777 base_vha = pci_get_drvdata(pdev); 3778 ha = base_vha->hw; 3779 ql_log(ql_log_info, base_vha, 0xb079, 3780 "Removing driver\n"); 3781 __qla_set_remove_flag(base_vha); 3782 cancel_work_sync(&ha->board_disable); 3783 3784 /* 3785 * If the PCI device is disabled then there was a PCI-disconnect and 3786 * qla2x00_disable_board_on_pci_error has taken care of most of the 3787 * resources. 3788 */ 3789 if (!atomic_read(&pdev->enable_cnt)) { 3790 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3791 base_vha->gnl.l, base_vha->gnl.ldma); 3792 base_vha->gnl.l = NULL; 3793 scsi_host_put(base_vha->host); 3794 kfree(ha); 3795 pci_set_drvdata(pdev, NULL); 3796 return; 3797 } 3798 qla2x00_wait_for_hba_ready(base_vha); 3799 3800 /* 3801 * if UNLOADING flag is already set, then continue unload, 3802 * where it was set first. 3803 */ 3804 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3805 return; 3806 3807 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3808 IS_QLA28XX(ha)) { 3809 if (ha->flags.fw_started) 3810 qla2x00_abort_isp_cleanup(base_vha); 3811 } else if (!IS_QLAFX00(ha)) { 3812 if (IS_QLA8031(ha)) { 3813 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3814 "Clearing fcoe driver presence.\n"); 3815 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3816 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3817 "Error while clearing DRV-Presence.\n"); 3818 } 3819 3820 qla2x00_try_to_stop_firmware(base_vha); 3821 } 3822 3823 qla2x00_wait_for_sess_deletion(base_vha); 3824 3825 qla_nvme_delete(base_vha); 3826 3827 dma_free_coherent(&ha->pdev->dev, 3828 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3829 3830 base_vha->gnl.l = NULL; 3831 qla_enode_stop(base_vha); 3832 qla_edb_stop(base_vha); 3833 3834 vfree(base_vha->scan.l); 3835 3836 if (IS_QLAFX00(ha)) 3837 qlafx00_driver_shutdown(base_vha, 20); 3838 3839 qla2x00_delete_all_vps(ha, base_vha); 3840 3841 qla2x00_dfs_remove(base_vha); 3842 3843 qla84xx_put_chip(base_vha); 3844 3845 /* Disable timer */ 3846 if (base_vha->timer_active) 3847 qla2x00_stop_timer(base_vha); 3848 3849 base_vha->flags.online = 0; 3850 3851 /* free DMA memory */ 3852 if (ha->exlogin_buf) 3853 qla2x00_free_exlogin_buffer(ha); 3854 3855 /* free DMA memory */ 3856 if (ha->exchoffld_buf) 3857 qla2x00_free_exchoffld_buffer(ha); 3858 3859 qla2x00_destroy_deferred_work(ha); 3860 3861 qlt_remove_target(ha, base_vha); 3862 3863 qla2x00_free_sysfs_attr(base_vha, true); 3864 3865 fc_remove_host(base_vha->host); 3866 3867 scsi_remove_host(base_vha->host); 3868 3869 qla2x00_free_device(base_vha); 3870 3871 qla2x00_clear_drv_active(ha); 3872 3873 scsi_host_put(base_vha->host); 3874 3875 qla2x00_unmap_iobases(ha); 3876 3877 pci_release_selected_regions(ha->pdev, ha->bars); 3878 kfree(ha); 3879 3880 pci_disable_pcie_error_reporting(pdev); 3881 3882 pci_disable_device(pdev); 3883 } 3884 3885 static inline void 3886 qla24xx_free_purex_list(struct purex_list *list) 3887 { 3888 struct purex_item *item, *next; 3889 ulong flags; 3890 3891 spin_lock_irqsave(&list->lock, flags); 3892 list_for_each_entry_safe(item, next, &list->head, list) { 3893 list_del(&item->list); 3894 kfree(item); 3895 } 3896 spin_unlock_irqrestore(&list->lock, flags); 3897 } 3898 3899 static void 3900 qla2x00_free_device(scsi_qla_host_t *vha) 3901 { 3902 struct qla_hw_data *ha = vha->hw; 3903 3904 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3905 3906 /* Disable timer */ 3907 if (vha->timer_active) 3908 qla2x00_stop_timer(vha); 3909 3910 qla25xx_delete_queues(vha); 3911 vha->flags.online = 0; 3912 3913 /* turn-off interrupts on the card */ 3914 if (ha->interrupts_on) { 3915 vha->flags.init_done = 0; 3916 ha->isp_ops->disable_intrs(ha); 3917 } 3918 3919 qla2x00_free_fcports(vha); 3920 3921 qla2x00_free_irqs(vha); 3922 3923 /* Flush the work queue and remove it */ 3924 if (ha->wq) { 3925 flush_workqueue(ha->wq); 3926 destroy_workqueue(ha->wq); 3927 ha->wq = NULL; 3928 } 3929 3930 3931 qla24xx_free_purex_list(&vha->purex_list); 3932 3933 qla2x00_mem_free(ha); 3934 3935 qla82xx_md_free(vha); 3936 3937 qla_edif_sadb_release_free_pool(ha); 3938 qla_edif_sadb_release(ha); 3939 3940 qla2x00_free_queues(ha); 3941 } 3942 3943 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3944 { 3945 fc_port_t *fcport, *tfcport; 3946 3947 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3948 qla2x00_free_fcport(fcport); 3949 } 3950 3951 static inline void 3952 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3953 { 3954 int now; 3955 3956 if (!fcport->rport) 3957 return; 3958 3959 if (fcport->rport) { 3960 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3961 "%s %8phN. rport %p roles %x\n", 3962 __func__, fcport->port_name, fcport->rport, 3963 fcport->rport->roles); 3964 fc_remote_port_delete(fcport->rport); 3965 } 3966 qlt_do_generation_tick(vha, &now); 3967 } 3968 3969 /* 3970 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3971 * 3972 * Input: ha = adapter block pointer. fcport = port structure pointer. 3973 * 3974 * Return: None. 3975 * 3976 * Context: 3977 */ 3978 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3979 int do_login) 3980 { 3981 if (IS_QLAFX00(vha->hw)) { 3982 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3983 qla2x00_schedule_rport_del(vha, fcport); 3984 return; 3985 } 3986 3987 if (atomic_read(&fcport->state) == FCS_ONLINE && 3988 vha->vp_idx == fcport->vha->vp_idx) { 3989 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3990 qla2x00_schedule_rport_del(vha, fcport); 3991 } 3992 3993 /* 3994 * We may need to retry the login, so don't change the state of the 3995 * port but do the retries. 3996 */ 3997 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3998 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3999 4000 if (!do_login) 4001 return; 4002 4003 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4004 } 4005 4006 void 4007 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4008 { 4009 fc_port_t *fcport; 4010 4011 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4012 "Mark all dev lost\n"); 4013 4014 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4015 if (fcport->loop_id != FC_NO_LOOP_ID && 4016 (fcport->flags & FCF_FCP2_DEVICE) && 4017 fcport->port_type == FCT_TARGET && 4018 !qla2x00_reset_active(vha)) { 4019 ql_dbg(ql_dbg_disc, vha, 0x211a, 4020 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4021 fcport->flags, fcport->port_type, 4022 fcport->d_id.b24, fcport->port_name); 4023 continue; 4024 } 4025 fcport->scan_state = 0; 4026 qlt_schedule_sess_for_deletion(fcport); 4027 } 4028 } 4029 4030 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4031 { 4032 int i; 4033 4034 if (IS_FWI2_CAPABLE(ha)) 4035 return; 4036 4037 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4038 set_bit(i, ha->loop_id_map); 4039 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4040 set_bit(BROADCAST, ha->loop_id_map); 4041 } 4042 4043 /* 4044 * qla2x00_mem_alloc 4045 * Allocates adapter memory. 4046 * 4047 * Returns: 4048 * 0 = success. 4049 * !0 = failure. 4050 */ 4051 static int 4052 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4053 struct req_que **req, struct rsp_que **rsp) 4054 { 4055 char name[16]; 4056 int rc; 4057 4058 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4059 &ha->init_cb_dma, GFP_KERNEL); 4060 if (!ha->init_cb) 4061 goto fail; 4062 4063 rc = btree_init32(&ha->host_map); 4064 if (rc) 4065 goto fail_free_init_cb; 4066 4067 if (qlt_mem_alloc(ha) < 0) 4068 goto fail_free_btree; 4069 4070 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4071 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4072 if (!ha->gid_list) 4073 goto fail_free_tgt_mem; 4074 4075 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4076 if (!ha->srb_mempool) 4077 goto fail_free_gid_list; 4078 4079 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4080 /* Allocate cache for CT6 Ctx. */ 4081 if (!ctx_cachep) { 4082 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4083 sizeof(struct ct6_dsd), 0, 4084 SLAB_HWCACHE_ALIGN, NULL); 4085 if (!ctx_cachep) 4086 goto fail_free_srb_mempool; 4087 } 4088 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4089 ctx_cachep); 4090 if (!ha->ctx_mempool) 4091 goto fail_free_srb_mempool; 4092 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4093 "ctx_cachep=%p ctx_mempool=%p.\n", 4094 ctx_cachep, ha->ctx_mempool); 4095 } 4096 4097 /* Get memory for cached NVRAM */ 4098 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4099 if (!ha->nvram) 4100 goto fail_free_ctx_mempool; 4101 4102 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4103 ha->pdev->device); 4104 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4105 DMA_POOL_SIZE, 8, 0); 4106 if (!ha->s_dma_pool) 4107 goto fail_free_nvram; 4108 4109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4110 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4111 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4112 4113 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4114 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4115 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4116 if (!ha->dl_dma_pool) { 4117 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4118 "Failed to allocate memory for dl_dma_pool.\n"); 4119 goto fail_s_dma_pool; 4120 } 4121 4122 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4123 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4124 if (!ha->fcp_cmnd_dma_pool) { 4125 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4126 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4127 goto fail_dl_dma_pool; 4128 } 4129 4130 if (ql2xenabledif) { 4131 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4132 struct dsd_dma *dsd, *nxt; 4133 uint i; 4134 /* Creata a DMA pool of buffers for DIF bundling */ 4135 ha->dif_bundl_pool = dma_pool_create(name, 4136 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4137 if (!ha->dif_bundl_pool) { 4138 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4139 "%s: failed create dif_bundl_pool\n", 4140 __func__); 4141 goto fail_dif_bundl_dma_pool; 4142 } 4143 4144 INIT_LIST_HEAD(&ha->pool.good.head); 4145 INIT_LIST_HEAD(&ha->pool.unusable.head); 4146 ha->pool.good.count = 0; 4147 ha->pool.unusable.count = 0; 4148 for (i = 0; i < 128; i++) { 4149 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4150 if (!dsd) { 4151 ql_dbg_pci(ql_dbg_init, ha->pdev, 4152 0xe0ee, "%s: failed alloc dsd\n", 4153 __func__); 4154 return -ENOMEM; 4155 } 4156 ha->dif_bundle_kallocs++; 4157 4158 dsd->dsd_addr = dma_pool_alloc( 4159 ha->dif_bundl_pool, GFP_ATOMIC, 4160 &dsd->dsd_list_dma); 4161 if (!dsd->dsd_addr) { 4162 ql_dbg_pci(ql_dbg_init, ha->pdev, 4163 0xe0ee, 4164 "%s: failed alloc ->dsd_addr\n", 4165 __func__); 4166 kfree(dsd); 4167 ha->dif_bundle_kallocs--; 4168 continue; 4169 } 4170 ha->dif_bundle_dma_allocs++; 4171 4172 /* 4173 * if DMA buffer crosses 4G boundary, 4174 * put it on bad list 4175 */ 4176 if (MSD(dsd->dsd_list_dma) ^ 4177 MSD(dsd->dsd_list_dma + bufsize)) { 4178 list_add_tail(&dsd->list, 4179 &ha->pool.unusable.head); 4180 ha->pool.unusable.count++; 4181 } else { 4182 list_add_tail(&dsd->list, 4183 &ha->pool.good.head); 4184 ha->pool.good.count++; 4185 } 4186 } 4187 4188 /* return the good ones back to the pool */ 4189 list_for_each_entry_safe(dsd, nxt, 4190 &ha->pool.good.head, list) { 4191 list_del(&dsd->list); 4192 dma_pool_free(ha->dif_bundl_pool, 4193 dsd->dsd_addr, dsd->dsd_list_dma); 4194 ha->dif_bundle_dma_allocs--; 4195 kfree(dsd); 4196 ha->dif_bundle_kallocs--; 4197 } 4198 4199 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4200 "%s: dif dma pool (good=%u unusable=%u)\n", 4201 __func__, ha->pool.good.count, 4202 ha->pool.unusable.count); 4203 } 4204 4205 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4206 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4207 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4208 ha->dif_bundl_pool); 4209 } 4210 4211 /* Allocate memory for SNS commands */ 4212 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4213 /* Get consistent memory allocated for SNS commands */ 4214 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4215 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4216 if (!ha->sns_cmd) 4217 goto fail_dma_pool; 4218 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4219 "sns_cmd: %p.\n", ha->sns_cmd); 4220 } else { 4221 /* Get consistent memory allocated for MS IOCB */ 4222 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4223 &ha->ms_iocb_dma); 4224 if (!ha->ms_iocb) 4225 goto fail_dma_pool; 4226 /* Get consistent memory allocated for CT SNS commands */ 4227 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4228 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4229 if (!ha->ct_sns) 4230 goto fail_free_ms_iocb; 4231 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4232 "ms_iocb=%p ct_sns=%p.\n", 4233 ha->ms_iocb, ha->ct_sns); 4234 } 4235 4236 /* Allocate memory for request ring */ 4237 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4238 if (!*req) { 4239 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4240 "Failed to allocate memory for req.\n"); 4241 goto fail_req; 4242 } 4243 (*req)->length = req_len; 4244 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4245 ((*req)->length + 1) * sizeof(request_t), 4246 &(*req)->dma, GFP_KERNEL); 4247 if (!(*req)->ring) { 4248 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4249 "Failed to allocate memory for req_ring.\n"); 4250 goto fail_req_ring; 4251 } 4252 /* Allocate memory for response ring */ 4253 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4254 if (!*rsp) { 4255 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4256 "Failed to allocate memory for rsp.\n"); 4257 goto fail_rsp; 4258 } 4259 (*rsp)->hw = ha; 4260 (*rsp)->length = rsp_len; 4261 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4262 ((*rsp)->length + 1) * sizeof(response_t), 4263 &(*rsp)->dma, GFP_KERNEL); 4264 if (!(*rsp)->ring) { 4265 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4266 "Failed to allocate memory for rsp_ring.\n"); 4267 goto fail_rsp_ring; 4268 } 4269 (*req)->rsp = *rsp; 4270 (*rsp)->req = *req; 4271 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4272 "req=%p req->length=%d req->ring=%p rsp=%p " 4273 "rsp->length=%d rsp->ring=%p.\n", 4274 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4275 (*rsp)->ring); 4276 /* Allocate memory for NVRAM data for vports */ 4277 if (ha->nvram_npiv_size) { 4278 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4279 sizeof(struct qla_npiv_entry), 4280 GFP_KERNEL); 4281 if (!ha->npiv_info) { 4282 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4283 "Failed to allocate memory for npiv_info.\n"); 4284 goto fail_npiv_info; 4285 } 4286 } else 4287 ha->npiv_info = NULL; 4288 4289 /* Get consistent memory allocated for EX-INIT-CB. */ 4290 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4291 IS_QLA28XX(ha)) { 4292 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4293 &ha->ex_init_cb_dma); 4294 if (!ha->ex_init_cb) 4295 goto fail_ex_init_cb; 4296 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4297 "ex_init_cb=%p.\n", ha->ex_init_cb); 4298 } 4299 4300 /* Get consistent memory allocated for Special Features-CB. */ 4301 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4302 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4303 &ha->sf_init_cb_dma); 4304 if (!ha->sf_init_cb) 4305 goto fail_sf_init_cb; 4306 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4307 "sf_init_cb=%p.\n", ha->sf_init_cb); 4308 } 4309 4310 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4311 4312 /* Get consistent memory allocated for Async Port-Database. */ 4313 if (!IS_FWI2_CAPABLE(ha)) { 4314 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4315 &ha->async_pd_dma); 4316 if (!ha->async_pd) 4317 goto fail_async_pd; 4318 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4319 "async_pd=%p.\n", ha->async_pd); 4320 } 4321 4322 INIT_LIST_HEAD(&ha->vp_list); 4323 4324 /* Allocate memory for our loop_id bitmap */ 4325 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4326 sizeof(long), 4327 GFP_KERNEL); 4328 if (!ha->loop_id_map) 4329 goto fail_loop_id_map; 4330 else { 4331 qla2x00_set_reserved_loop_ids(ha); 4332 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4333 "loop_id_map=%p.\n", ha->loop_id_map); 4334 } 4335 4336 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4337 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4338 if (!ha->sfp_data) { 4339 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4340 "Unable to allocate memory for SFP read-data.\n"); 4341 goto fail_sfp_data; 4342 } 4343 4344 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4345 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4346 GFP_KERNEL); 4347 if (!ha->flt) { 4348 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4349 "Unable to allocate memory for FLT.\n"); 4350 goto fail_flt_buffer; 4351 } 4352 4353 /* allocate the purex dma pool */ 4354 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4355 ELS_MAX_PAYLOAD, 8, 0); 4356 4357 if (!ha->purex_dma_pool) { 4358 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4359 "Unable to allocate purex_dma_pool.\n"); 4360 goto fail_flt; 4361 } 4362 4363 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4364 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4365 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4366 4367 if (!ha->elsrej.c) { 4368 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4369 "Alloc failed for els reject cmd.\n"); 4370 goto fail_elsrej; 4371 } 4372 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4373 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4374 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4375 return 0; 4376 4377 fail_elsrej: 4378 dma_pool_destroy(ha->purex_dma_pool); 4379 fail_flt: 4380 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4381 ha->flt, ha->flt_dma); 4382 4383 fail_flt_buffer: 4384 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4385 ha->sfp_data, ha->sfp_data_dma); 4386 fail_sfp_data: 4387 kfree(ha->loop_id_map); 4388 fail_loop_id_map: 4389 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4390 fail_async_pd: 4391 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4392 fail_sf_init_cb: 4393 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4394 fail_ex_init_cb: 4395 kfree(ha->npiv_info); 4396 fail_npiv_info: 4397 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4398 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4399 (*rsp)->ring = NULL; 4400 (*rsp)->dma = 0; 4401 fail_rsp_ring: 4402 kfree(*rsp); 4403 *rsp = NULL; 4404 fail_rsp: 4405 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4406 sizeof(request_t), (*req)->ring, (*req)->dma); 4407 (*req)->ring = NULL; 4408 (*req)->dma = 0; 4409 fail_req_ring: 4410 kfree(*req); 4411 *req = NULL; 4412 fail_req: 4413 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4414 ha->ct_sns, ha->ct_sns_dma); 4415 ha->ct_sns = NULL; 4416 ha->ct_sns_dma = 0; 4417 fail_free_ms_iocb: 4418 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4419 ha->ms_iocb = NULL; 4420 ha->ms_iocb_dma = 0; 4421 4422 if (ha->sns_cmd) 4423 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4424 ha->sns_cmd, ha->sns_cmd_dma); 4425 fail_dma_pool: 4426 if (ql2xenabledif) { 4427 struct dsd_dma *dsd, *nxt; 4428 4429 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4430 list) { 4431 list_del(&dsd->list); 4432 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4433 dsd->dsd_list_dma); 4434 ha->dif_bundle_dma_allocs--; 4435 kfree(dsd); 4436 ha->dif_bundle_kallocs--; 4437 ha->pool.unusable.count--; 4438 } 4439 dma_pool_destroy(ha->dif_bundl_pool); 4440 ha->dif_bundl_pool = NULL; 4441 } 4442 4443 fail_dif_bundl_dma_pool: 4444 if (IS_QLA82XX(ha) || ql2xenabledif) { 4445 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4446 ha->fcp_cmnd_dma_pool = NULL; 4447 } 4448 fail_dl_dma_pool: 4449 if (IS_QLA82XX(ha) || ql2xenabledif) { 4450 dma_pool_destroy(ha->dl_dma_pool); 4451 ha->dl_dma_pool = NULL; 4452 } 4453 fail_s_dma_pool: 4454 dma_pool_destroy(ha->s_dma_pool); 4455 ha->s_dma_pool = NULL; 4456 fail_free_nvram: 4457 kfree(ha->nvram); 4458 ha->nvram = NULL; 4459 fail_free_ctx_mempool: 4460 mempool_destroy(ha->ctx_mempool); 4461 ha->ctx_mempool = NULL; 4462 fail_free_srb_mempool: 4463 mempool_destroy(ha->srb_mempool); 4464 ha->srb_mempool = NULL; 4465 fail_free_gid_list: 4466 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4467 ha->gid_list, 4468 ha->gid_list_dma); 4469 ha->gid_list = NULL; 4470 ha->gid_list_dma = 0; 4471 fail_free_tgt_mem: 4472 qlt_mem_free(ha); 4473 fail_free_btree: 4474 btree_destroy32(&ha->host_map); 4475 fail_free_init_cb: 4476 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4477 ha->init_cb_dma); 4478 ha->init_cb = NULL; 4479 ha->init_cb_dma = 0; 4480 fail: 4481 ql_log(ql_log_fatal, NULL, 0x0030, 4482 "Memory allocation failure.\n"); 4483 return -ENOMEM; 4484 } 4485 4486 int 4487 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4488 { 4489 int rval; 4490 uint16_t size, max_cnt; 4491 uint32_t temp; 4492 struct qla_hw_data *ha = vha->hw; 4493 4494 /* Return if we don't need to alloacate any extended logins */ 4495 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4496 return QLA_SUCCESS; 4497 4498 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4499 return QLA_SUCCESS; 4500 4501 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4502 max_cnt = 0; 4503 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4504 if (rval != QLA_SUCCESS) { 4505 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4506 "Failed to get exlogin status.\n"); 4507 return rval; 4508 } 4509 4510 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4511 temp *= size; 4512 4513 if (temp != ha->exlogin_size) { 4514 qla2x00_free_exlogin_buffer(ha); 4515 ha->exlogin_size = temp; 4516 4517 ql_log(ql_log_info, vha, 0xd024, 4518 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4519 max_cnt, size, temp); 4520 4521 ql_log(ql_log_info, vha, 0xd025, 4522 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4523 4524 /* Get consistent memory for extended logins */ 4525 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4526 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4527 if (!ha->exlogin_buf) { 4528 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4529 "Failed to allocate memory for exlogin_buf_dma.\n"); 4530 return -ENOMEM; 4531 } 4532 } 4533 4534 /* Now configure the dma buffer */ 4535 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4536 if (rval) { 4537 ql_log(ql_log_fatal, vha, 0xd033, 4538 "Setup extended login buffer ****FAILED****.\n"); 4539 qla2x00_free_exlogin_buffer(ha); 4540 } 4541 4542 return rval; 4543 } 4544 4545 /* 4546 * qla2x00_free_exlogin_buffer 4547 * 4548 * Input: 4549 * ha = adapter block pointer 4550 */ 4551 void 4552 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4553 { 4554 if (ha->exlogin_buf) { 4555 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4556 ha->exlogin_buf, ha->exlogin_buf_dma); 4557 ha->exlogin_buf = NULL; 4558 ha->exlogin_size = 0; 4559 } 4560 } 4561 4562 static void 4563 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4564 { 4565 u32 temp; 4566 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4567 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4568 4569 if (max_cnt > vha->hw->max_exchg) 4570 max_cnt = vha->hw->max_exchg; 4571 4572 if (qla_ini_mode_enabled(vha)) { 4573 if (vha->ql2xiniexchg > max_cnt) 4574 vha->ql2xiniexchg = max_cnt; 4575 4576 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4577 *ret_cnt = vha->ql2xiniexchg; 4578 4579 } else if (qla_tgt_mode_enabled(vha)) { 4580 if (vha->ql2xexchoffld > max_cnt) { 4581 vha->ql2xexchoffld = max_cnt; 4582 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4583 } 4584 4585 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4586 *ret_cnt = vha->ql2xexchoffld; 4587 } else if (qla_dual_mode_enabled(vha)) { 4588 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4589 if (temp > max_cnt) { 4590 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4591 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4592 temp = max_cnt; 4593 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4594 } 4595 4596 if (temp > FW_DEF_EXCHANGES_CNT) 4597 *ret_cnt = temp; 4598 } 4599 } 4600 4601 int 4602 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4603 { 4604 int rval; 4605 u16 size, max_cnt; 4606 u32 actual_cnt, totsz; 4607 struct qla_hw_data *ha = vha->hw; 4608 4609 if (!ha->flags.exchoffld_enabled) 4610 return QLA_SUCCESS; 4611 4612 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4613 return QLA_SUCCESS; 4614 4615 max_cnt = 0; 4616 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4617 if (rval != QLA_SUCCESS) { 4618 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4619 "Failed to get exlogin status.\n"); 4620 return rval; 4621 } 4622 4623 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4624 ql_log(ql_log_info, vha, 0xd014, 4625 "Actual exchange offload count: %d.\n", actual_cnt); 4626 4627 totsz = actual_cnt * size; 4628 4629 if (totsz != ha->exchoffld_size) { 4630 qla2x00_free_exchoffld_buffer(ha); 4631 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4632 ha->exchoffld_size = 0; 4633 ha->flags.exchoffld_enabled = 0; 4634 return QLA_SUCCESS; 4635 } 4636 4637 ha->exchoffld_size = totsz; 4638 4639 ql_log(ql_log_info, vha, 0xd016, 4640 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4641 max_cnt, actual_cnt, size, totsz); 4642 4643 ql_log(ql_log_info, vha, 0xd017, 4644 "Exchange Buffers requested size = 0x%x\n", 4645 ha->exchoffld_size); 4646 4647 /* Get consistent memory for extended logins */ 4648 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4649 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4650 if (!ha->exchoffld_buf) { 4651 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4652 "Failed to allocate memory for Exchange Offload.\n"); 4653 4654 if (ha->max_exchg > 4655 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4656 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4657 } else if (ha->max_exchg > 4658 (FW_DEF_EXCHANGES_CNT + 512)) { 4659 ha->max_exchg -= 512; 4660 } else { 4661 ha->flags.exchoffld_enabled = 0; 4662 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4663 "Disabling Exchange offload due to lack of memory\n"); 4664 } 4665 ha->exchoffld_size = 0; 4666 4667 return -ENOMEM; 4668 } 4669 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4670 /* pathological case */ 4671 qla2x00_free_exchoffld_buffer(ha); 4672 ha->exchoffld_size = 0; 4673 ha->flags.exchoffld_enabled = 0; 4674 ql_log(ql_log_info, vha, 0xd016, 4675 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4676 ha->exchoffld_size, actual_cnt, size, totsz); 4677 return 0; 4678 } 4679 4680 /* Now configure the dma buffer */ 4681 rval = qla_set_exchoffld_mem_cfg(vha); 4682 if (rval) { 4683 ql_log(ql_log_fatal, vha, 0xd02e, 4684 "Setup exchange offload buffer ****FAILED****.\n"); 4685 qla2x00_free_exchoffld_buffer(ha); 4686 } else { 4687 /* re-adjust number of target exchange */ 4688 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4689 4690 if (qla_ini_mode_enabled(vha)) 4691 icb->exchange_count = 0; 4692 else 4693 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4694 } 4695 4696 return rval; 4697 } 4698 4699 /* 4700 * qla2x00_free_exchoffld_buffer 4701 * 4702 * Input: 4703 * ha = adapter block pointer 4704 */ 4705 void 4706 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4707 { 4708 if (ha->exchoffld_buf) { 4709 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4710 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4711 ha->exchoffld_buf = NULL; 4712 ha->exchoffld_size = 0; 4713 } 4714 } 4715 4716 /* 4717 * qla2x00_free_fw_dump 4718 * Frees fw dump stuff. 4719 * 4720 * Input: 4721 * ha = adapter block pointer 4722 */ 4723 static void 4724 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4725 { 4726 struct fwdt *fwdt = ha->fwdt; 4727 uint j; 4728 4729 if (ha->fce) 4730 dma_free_coherent(&ha->pdev->dev, 4731 FCE_SIZE, ha->fce, ha->fce_dma); 4732 4733 if (ha->eft) 4734 dma_free_coherent(&ha->pdev->dev, 4735 EFT_SIZE, ha->eft, ha->eft_dma); 4736 4737 vfree(ha->fw_dump); 4738 4739 ha->fce = NULL; 4740 ha->fce_dma = 0; 4741 ha->flags.fce_enabled = 0; 4742 ha->eft = NULL; 4743 ha->eft_dma = 0; 4744 ha->fw_dumped = false; 4745 ha->fw_dump_cap_flags = 0; 4746 ha->fw_dump_reading = 0; 4747 ha->fw_dump = NULL; 4748 ha->fw_dump_len = 0; 4749 4750 for (j = 0; j < 2; j++, fwdt++) { 4751 vfree(fwdt->template); 4752 fwdt->template = NULL; 4753 fwdt->length = 0; 4754 } 4755 } 4756 4757 /* 4758 * qla2x00_mem_free 4759 * Frees all adapter allocated memory. 4760 * 4761 * Input: 4762 * ha = adapter block pointer. 4763 */ 4764 static void 4765 qla2x00_mem_free(struct qla_hw_data *ha) 4766 { 4767 qla2x00_free_fw_dump(ha); 4768 4769 if (ha->mctp_dump) 4770 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4771 ha->mctp_dump_dma); 4772 ha->mctp_dump = NULL; 4773 4774 mempool_destroy(ha->srb_mempool); 4775 ha->srb_mempool = NULL; 4776 4777 if (ha->dcbx_tlv) 4778 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4779 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4780 ha->dcbx_tlv = NULL; 4781 4782 if (ha->xgmac_data) 4783 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4784 ha->xgmac_data, ha->xgmac_data_dma); 4785 ha->xgmac_data = NULL; 4786 4787 if (ha->sns_cmd) 4788 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4789 ha->sns_cmd, ha->sns_cmd_dma); 4790 ha->sns_cmd = NULL; 4791 ha->sns_cmd_dma = 0; 4792 4793 if (ha->ct_sns) 4794 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4795 ha->ct_sns, ha->ct_sns_dma); 4796 ha->ct_sns = NULL; 4797 ha->ct_sns_dma = 0; 4798 4799 if (ha->sfp_data) 4800 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4801 ha->sfp_data_dma); 4802 ha->sfp_data = NULL; 4803 4804 if (ha->flt) 4805 dma_free_coherent(&ha->pdev->dev, 4806 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4807 ha->flt, ha->flt_dma); 4808 ha->flt = NULL; 4809 ha->flt_dma = 0; 4810 4811 if (ha->ms_iocb) 4812 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4813 ha->ms_iocb = NULL; 4814 ha->ms_iocb_dma = 0; 4815 4816 if (ha->sf_init_cb) 4817 dma_pool_free(ha->s_dma_pool, 4818 ha->sf_init_cb, ha->sf_init_cb_dma); 4819 4820 if (ha->ex_init_cb) 4821 dma_pool_free(ha->s_dma_pool, 4822 ha->ex_init_cb, ha->ex_init_cb_dma); 4823 ha->ex_init_cb = NULL; 4824 ha->ex_init_cb_dma = 0; 4825 4826 if (ha->async_pd) 4827 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4828 ha->async_pd = NULL; 4829 ha->async_pd_dma = 0; 4830 4831 dma_pool_destroy(ha->s_dma_pool); 4832 ha->s_dma_pool = NULL; 4833 4834 if (ha->gid_list) 4835 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4836 ha->gid_list, ha->gid_list_dma); 4837 ha->gid_list = NULL; 4838 ha->gid_list_dma = 0; 4839 4840 if (IS_QLA82XX(ha)) { 4841 if (!list_empty(&ha->gbl_dsd_list)) { 4842 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4843 4844 /* clean up allocated prev pool */ 4845 list_for_each_entry_safe(dsd_ptr, 4846 tdsd_ptr, &ha->gbl_dsd_list, list) { 4847 dma_pool_free(ha->dl_dma_pool, 4848 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4849 list_del(&dsd_ptr->list); 4850 kfree(dsd_ptr); 4851 } 4852 } 4853 } 4854 4855 dma_pool_destroy(ha->dl_dma_pool); 4856 ha->dl_dma_pool = NULL; 4857 4858 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4859 ha->fcp_cmnd_dma_pool = NULL; 4860 4861 mempool_destroy(ha->ctx_mempool); 4862 ha->ctx_mempool = NULL; 4863 4864 if (ql2xenabledif && ha->dif_bundl_pool) { 4865 struct dsd_dma *dsd, *nxt; 4866 4867 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4868 list) { 4869 list_del(&dsd->list); 4870 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4871 dsd->dsd_list_dma); 4872 ha->dif_bundle_dma_allocs--; 4873 kfree(dsd); 4874 ha->dif_bundle_kallocs--; 4875 ha->pool.unusable.count--; 4876 } 4877 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4878 list_del(&dsd->list); 4879 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4880 dsd->dsd_list_dma); 4881 ha->dif_bundle_dma_allocs--; 4882 kfree(dsd); 4883 ha->dif_bundle_kallocs--; 4884 } 4885 } 4886 4887 dma_pool_destroy(ha->dif_bundl_pool); 4888 ha->dif_bundl_pool = NULL; 4889 4890 qlt_mem_free(ha); 4891 qla_remove_hostmap(ha); 4892 4893 if (ha->init_cb) 4894 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4895 ha->init_cb, ha->init_cb_dma); 4896 4897 dma_pool_destroy(ha->purex_dma_pool); 4898 ha->purex_dma_pool = NULL; 4899 4900 if (ha->elsrej.c) { 4901 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4902 ha->elsrej.c, ha->elsrej.cdma); 4903 ha->elsrej.c = NULL; 4904 } 4905 4906 ha->init_cb = NULL; 4907 ha->init_cb_dma = 0; 4908 4909 vfree(ha->optrom_buffer); 4910 ha->optrom_buffer = NULL; 4911 kfree(ha->nvram); 4912 ha->nvram = NULL; 4913 kfree(ha->npiv_info); 4914 ha->npiv_info = NULL; 4915 kfree(ha->swl); 4916 ha->swl = NULL; 4917 kfree(ha->loop_id_map); 4918 ha->sf_init_cb = NULL; 4919 ha->sf_init_cb_dma = 0; 4920 ha->loop_id_map = NULL; 4921 } 4922 4923 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4924 struct qla_hw_data *ha) 4925 { 4926 struct Scsi_Host *host; 4927 struct scsi_qla_host *vha = NULL; 4928 4929 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4930 if (!host) { 4931 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4932 "Failed to allocate host from the scsi layer, aborting.\n"); 4933 return NULL; 4934 } 4935 4936 /* Clear our data area */ 4937 vha = shost_priv(host); 4938 memset(vha, 0, sizeof(scsi_qla_host_t)); 4939 4940 vha->host = host; 4941 vha->host_no = host->host_no; 4942 vha->hw = ha; 4943 4944 vha->qlini_mode = ql2x_ini_mode; 4945 vha->ql2xexchoffld = ql2xexchoffld; 4946 vha->ql2xiniexchg = ql2xiniexchg; 4947 4948 INIT_LIST_HEAD(&vha->vp_fcports); 4949 INIT_LIST_HEAD(&vha->work_list); 4950 INIT_LIST_HEAD(&vha->list); 4951 INIT_LIST_HEAD(&vha->qla_cmd_list); 4952 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4953 INIT_LIST_HEAD(&vha->logo_list); 4954 INIT_LIST_HEAD(&vha->plogi_ack_list); 4955 INIT_LIST_HEAD(&vha->qp_list); 4956 INIT_LIST_HEAD(&vha->gnl.fcports); 4957 INIT_LIST_HEAD(&vha->gpnid_list); 4958 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4959 4960 INIT_LIST_HEAD(&vha->purex_list.head); 4961 spin_lock_init(&vha->purex_list.lock); 4962 4963 spin_lock_init(&vha->work_lock); 4964 spin_lock_init(&vha->cmd_list_lock); 4965 init_waitqueue_head(&vha->fcport_waitQ); 4966 init_waitqueue_head(&vha->vref_waitq); 4967 qla_enode_init(vha); 4968 qla_edb_init(vha); 4969 4970 4971 vha->gnl.size = sizeof(struct get_name_list_extended) * 4972 (ha->max_loop_id + 1); 4973 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4974 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4975 if (!vha->gnl.l) { 4976 ql_log(ql_log_fatal, vha, 0xd04a, 4977 "Alloc failed for name list.\n"); 4978 scsi_host_put(vha->host); 4979 return NULL; 4980 } 4981 4982 /* todo: what about ext login? */ 4983 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4984 vha->scan.l = vmalloc(vha->scan.size); 4985 if (!vha->scan.l) { 4986 ql_log(ql_log_fatal, vha, 0xd04a, 4987 "Alloc failed for scan database.\n"); 4988 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4989 vha->gnl.l, vha->gnl.ldma); 4990 vha->gnl.l = NULL; 4991 scsi_host_put(vha->host); 4992 return NULL; 4993 } 4994 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4995 4996 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 4997 ql_dbg(ql_dbg_init, vha, 0x0041, 4998 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4999 vha->host, vha->hw, vha, 5000 dev_name(&(ha->pdev->dev))); 5001 5002 return vha; 5003 } 5004 5005 struct qla_work_evt * 5006 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5007 { 5008 struct qla_work_evt *e; 5009 uint8_t bail; 5010 5011 if (test_bit(UNLOADING, &vha->dpc_flags)) 5012 return NULL; 5013 5014 QLA_VHA_MARK_BUSY(vha, bail); 5015 if (bail) 5016 return NULL; 5017 5018 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5019 if (!e) { 5020 QLA_VHA_MARK_NOT_BUSY(vha); 5021 return NULL; 5022 } 5023 5024 INIT_LIST_HEAD(&e->list); 5025 e->type = type; 5026 e->flags = QLA_EVT_FLAG_FREE; 5027 return e; 5028 } 5029 5030 int 5031 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5032 { 5033 unsigned long flags; 5034 bool q = false; 5035 5036 spin_lock_irqsave(&vha->work_lock, flags); 5037 list_add_tail(&e->list, &vha->work_list); 5038 5039 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5040 q = true; 5041 5042 spin_unlock_irqrestore(&vha->work_lock, flags); 5043 5044 if (q) 5045 queue_work(vha->hw->wq, &vha->iocb_work); 5046 5047 return QLA_SUCCESS; 5048 } 5049 5050 int 5051 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5052 u32 data) 5053 { 5054 struct qla_work_evt *e; 5055 5056 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5057 if (!e) 5058 return QLA_FUNCTION_FAILED; 5059 5060 e->u.aen.code = code; 5061 e->u.aen.data = data; 5062 return qla2x00_post_work(vha, e); 5063 } 5064 5065 int 5066 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5067 { 5068 struct qla_work_evt *e; 5069 5070 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5071 if (!e) 5072 return QLA_FUNCTION_FAILED; 5073 5074 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5075 return qla2x00_post_work(vha, e); 5076 } 5077 5078 #define qla2x00_post_async_work(name, type) \ 5079 int qla2x00_post_async_##name##_work( \ 5080 struct scsi_qla_host *vha, \ 5081 fc_port_t *fcport, uint16_t *data) \ 5082 { \ 5083 struct qla_work_evt *e; \ 5084 \ 5085 e = qla2x00_alloc_work(vha, type); \ 5086 if (!e) \ 5087 return QLA_FUNCTION_FAILED; \ 5088 \ 5089 e->u.logio.fcport = fcport; \ 5090 if (data) { \ 5091 e->u.logio.data[0] = data[0]; \ 5092 e->u.logio.data[1] = data[1]; \ 5093 } \ 5094 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5095 return qla2x00_post_work(vha, e); \ 5096 } 5097 5098 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5099 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5100 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5101 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5102 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5103 5104 int 5105 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5106 { 5107 struct qla_work_evt *e; 5108 5109 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5110 if (!e) 5111 return QLA_FUNCTION_FAILED; 5112 5113 e->u.uevent.code = code; 5114 return qla2x00_post_work(vha, e); 5115 } 5116 5117 static void 5118 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5119 { 5120 char event_string[40]; 5121 char *envp[] = { event_string, NULL }; 5122 5123 switch (code) { 5124 case QLA_UEVENT_CODE_FW_DUMP: 5125 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5126 vha->host_no); 5127 break; 5128 default: 5129 /* do nothing */ 5130 break; 5131 } 5132 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5133 } 5134 5135 int 5136 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5137 uint32_t *data, int cnt) 5138 { 5139 struct qla_work_evt *e; 5140 5141 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5142 if (!e) 5143 return QLA_FUNCTION_FAILED; 5144 5145 e->u.aenfx.evtcode = evtcode; 5146 e->u.aenfx.count = cnt; 5147 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5148 return qla2x00_post_work(vha, e); 5149 } 5150 5151 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5152 { 5153 unsigned long flags; 5154 5155 if (IS_SW_RESV_ADDR(fcport->d_id)) 5156 return; 5157 5158 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5159 if (fcport->disc_state == DSC_UPD_FCPORT) { 5160 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5161 return; 5162 } 5163 fcport->jiffies_at_registration = jiffies; 5164 fcport->sec_since_registration = 0; 5165 fcport->next_disc_state = DSC_DELETED; 5166 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5167 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5168 5169 queue_work(system_unbound_wq, &fcport->reg_work); 5170 } 5171 5172 static 5173 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5174 { 5175 unsigned long flags; 5176 fc_port_t *fcport = NULL, *tfcp; 5177 struct qlt_plogi_ack_t *pla = 5178 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5179 uint8_t free_fcport = 0; 5180 5181 ql_dbg(ql_dbg_disc, vha, 0xffff, 5182 "%s %d %8phC enter\n", 5183 __func__, __LINE__, e->u.new_sess.port_name); 5184 5185 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5186 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5187 if (fcport) { 5188 fcport->d_id = e->u.new_sess.id; 5189 if (pla) { 5190 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5191 memcpy(fcport->node_name, 5192 pla->iocb.u.isp24.u.plogi.node_name, 5193 WWN_SIZE); 5194 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5195 /* we took an extra ref_count to prevent PLOGI ACK when 5196 * fcport/sess has not been created. 5197 */ 5198 pla->ref_count--; 5199 } 5200 } else { 5201 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5202 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5203 if (fcport) { 5204 fcport->d_id = e->u.new_sess.id; 5205 fcport->flags |= FCF_FABRIC_DEVICE; 5206 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5207 fcport->tgt_short_link_down_cnt = 0; 5208 5209 memcpy(fcport->port_name, e->u.new_sess.port_name, 5210 WWN_SIZE); 5211 5212 fcport->fc4_type = e->u.new_sess.fc4_type; 5213 if (NVME_PRIORITY(vha->hw, fcport)) 5214 fcport->do_prli_nvme = 1; 5215 else 5216 fcport->do_prli_nvme = 0; 5217 5218 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5219 fcport->dm_login_expire = jiffies + 5220 QLA_N2N_WAIT_TIME * HZ; 5221 fcport->fc4_type = FS_FC4TYPE_FCP; 5222 fcport->n2n_flag = 1; 5223 if (vha->flags.nvme_enabled) 5224 fcport->fc4_type |= FS_FC4TYPE_NVME; 5225 } 5226 5227 } else { 5228 ql_dbg(ql_dbg_disc, vha, 0xffff, 5229 "%s %8phC mem alloc fail.\n", 5230 __func__, e->u.new_sess.port_name); 5231 5232 if (pla) { 5233 list_del(&pla->list); 5234 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5235 } 5236 return; 5237 } 5238 5239 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5240 /* search again to make sure no one else got ahead */ 5241 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5242 e->u.new_sess.port_name, 1); 5243 if (tfcp) { 5244 /* should rarily happen */ 5245 ql_dbg(ql_dbg_disc, vha, 0xffff, 5246 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5247 __func__, tfcp->port_name, tfcp->disc_state, 5248 tfcp->fw_login_state); 5249 5250 free_fcport = 1; 5251 } else { 5252 list_add_tail(&fcport->list, &vha->vp_fcports); 5253 5254 } 5255 if (pla) { 5256 qlt_plogi_ack_link(vha, pla, fcport, 5257 QLT_PLOGI_LINK_SAME_WWN); 5258 pla->ref_count--; 5259 } 5260 } 5261 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5262 5263 if (fcport) { 5264 fcport->id_changed = 1; 5265 fcport->scan_state = QLA_FCPORT_FOUND; 5266 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5267 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5268 5269 if (pla) { 5270 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5271 u16 wd3_lo; 5272 5273 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5274 fcport->local = 0; 5275 fcport->loop_id = 5276 le16_to_cpu( 5277 pla->iocb.u.isp24.nport_handle); 5278 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5279 wd3_lo = 5280 le16_to_cpu( 5281 pla->iocb.u.isp24.u.prli.wd3_lo); 5282 5283 if (wd3_lo & BIT_7) 5284 fcport->conf_compl_supported = 1; 5285 5286 if ((wd3_lo & BIT_4) == 0) 5287 fcport->port_type = FCT_INITIATOR; 5288 else 5289 fcport->port_type = FCT_TARGET; 5290 } 5291 qlt_plogi_ack_unref(vha, pla); 5292 } else { 5293 fc_port_t *dfcp = NULL; 5294 5295 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5296 tfcp = qla2x00_find_fcport_by_nportid(vha, 5297 &e->u.new_sess.id, 1); 5298 if (tfcp && (tfcp != fcport)) { 5299 /* 5300 * We have a conflict fcport with same NportID. 5301 */ 5302 ql_dbg(ql_dbg_disc, vha, 0xffff, 5303 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5304 __func__, tfcp->port_name, tfcp->disc_state, 5305 tfcp->fw_login_state); 5306 5307 switch (tfcp->disc_state) { 5308 case DSC_DELETED: 5309 break; 5310 case DSC_DELETE_PEND: 5311 fcport->login_pause = 1; 5312 tfcp->conflict = fcport; 5313 break; 5314 default: 5315 fcport->login_pause = 1; 5316 tfcp->conflict = fcport; 5317 dfcp = tfcp; 5318 break; 5319 } 5320 } 5321 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5322 if (dfcp) 5323 qlt_schedule_sess_for_deletion(tfcp); 5324 5325 if (N2N_TOPO(vha->hw)) { 5326 fcport->flags &= ~FCF_FABRIC_DEVICE; 5327 fcport->keep_nport_handle = 1; 5328 if (vha->flags.nvme_enabled) { 5329 fcport->fc4_type = 5330 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5331 fcport->n2n_flag = 1; 5332 } 5333 fcport->fw_login_state = 0; 5334 5335 schedule_delayed_work(&vha->scan.scan_work, 5); 5336 } else { 5337 qla24xx_fcport_handle_login(vha, fcport); 5338 } 5339 } 5340 } 5341 5342 if (free_fcport) { 5343 qla2x00_free_fcport(fcport); 5344 if (pla) { 5345 list_del(&pla->list); 5346 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5347 } 5348 } 5349 } 5350 5351 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5352 { 5353 struct srb *sp = e->u.iosb.sp; 5354 int rval; 5355 5356 rval = qla2x00_start_sp(sp); 5357 if (rval != QLA_SUCCESS) { 5358 ql_dbg(ql_dbg_disc, vha, 0x2043, 5359 "%s: %s: Re-issue IOCB failed (%d).\n", 5360 __func__, sp->name, rval); 5361 qla24xx_sp_unmap(vha, sp); 5362 } 5363 } 5364 5365 void 5366 qla2x00_do_work(struct scsi_qla_host *vha) 5367 { 5368 struct qla_work_evt *e, *tmp; 5369 unsigned long flags; 5370 LIST_HEAD(work); 5371 int rc; 5372 5373 spin_lock_irqsave(&vha->work_lock, flags); 5374 list_splice_init(&vha->work_list, &work); 5375 spin_unlock_irqrestore(&vha->work_lock, flags); 5376 5377 list_for_each_entry_safe(e, tmp, &work, list) { 5378 rc = QLA_SUCCESS; 5379 switch (e->type) { 5380 case QLA_EVT_AEN: 5381 fc_host_post_event(vha->host, fc_get_event_number(), 5382 e->u.aen.code, e->u.aen.data); 5383 break; 5384 case QLA_EVT_IDC_ACK: 5385 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5386 break; 5387 case QLA_EVT_ASYNC_LOGIN: 5388 qla2x00_async_login(vha, e->u.logio.fcport, 5389 e->u.logio.data); 5390 break; 5391 case QLA_EVT_ASYNC_LOGOUT: 5392 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5393 break; 5394 case QLA_EVT_ASYNC_ADISC: 5395 qla2x00_async_adisc(vha, e->u.logio.fcport, 5396 e->u.logio.data); 5397 break; 5398 case QLA_EVT_UEVENT: 5399 qla2x00_uevent_emit(vha, e->u.uevent.code); 5400 break; 5401 case QLA_EVT_AENFX: 5402 qlafx00_process_aen(vha, e); 5403 break; 5404 case QLA_EVT_GPNID: 5405 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5406 break; 5407 case QLA_EVT_UNMAP: 5408 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5409 break; 5410 case QLA_EVT_RELOGIN: 5411 qla2x00_relogin(vha); 5412 break; 5413 case QLA_EVT_NEW_SESS: 5414 qla24xx_create_new_sess(vha, e); 5415 break; 5416 case QLA_EVT_GPDB: 5417 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5418 e->u.fcport.opt); 5419 break; 5420 case QLA_EVT_PRLI: 5421 qla24xx_async_prli(vha, e->u.fcport.fcport); 5422 break; 5423 case QLA_EVT_GPSC: 5424 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5425 break; 5426 case QLA_EVT_GNL: 5427 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5428 break; 5429 case QLA_EVT_NACK: 5430 qla24xx_do_nack_work(vha, e); 5431 break; 5432 case QLA_EVT_ASYNC_PRLO: 5433 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5434 break; 5435 case QLA_EVT_ASYNC_PRLO_DONE: 5436 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5437 e->u.logio.data); 5438 break; 5439 case QLA_EVT_GPNFT: 5440 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5441 e->u.gpnft.sp); 5442 break; 5443 case QLA_EVT_GPNFT_DONE: 5444 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5445 break; 5446 case QLA_EVT_GNNFT_DONE: 5447 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5448 break; 5449 case QLA_EVT_GNNID: 5450 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5451 break; 5452 case QLA_EVT_GFPNID: 5453 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5454 break; 5455 case QLA_EVT_SP_RETRY: 5456 qla_sp_retry(vha, e); 5457 break; 5458 case QLA_EVT_IIDMA: 5459 qla_do_iidma_work(vha, e->u.fcport.fcport); 5460 break; 5461 case QLA_EVT_ELS_PLOGI: 5462 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5463 e->u.fcport.fcport, false); 5464 break; 5465 case QLA_EVT_SA_REPLACE: 5466 qla24xx_issue_sa_replace_iocb(vha, e); 5467 break; 5468 } 5469 5470 if (rc == EAGAIN) { 5471 /* put 'work' at head of 'vha->work_list' */ 5472 spin_lock_irqsave(&vha->work_lock, flags); 5473 list_splice(&work, &vha->work_list); 5474 spin_unlock_irqrestore(&vha->work_lock, flags); 5475 break; 5476 } 5477 list_del_init(&e->list); 5478 if (e->flags & QLA_EVT_FLAG_FREE) 5479 kfree(e); 5480 5481 /* For each work completed decrement vha ref count */ 5482 QLA_VHA_MARK_NOT_BUSY(vha); 5483 } 5484 } 5485 5486 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5487 { 5488 struct qla_work_evt *e; 5489 5490 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5491 5492 if (!e) { 5493 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5494 return QLA_FUNCTION_FAILED; 5495 } 5496 5497 return qla2x00_post_work(vha, e); 5498 } 5499 5500 /* Relogins all the fcports of a vport 5501 * Context: dpc thread 5502 */ 5503 void qla2x00_relogin(struct scsi_qla_host *vha) 5504 { 5505 fc_port_t *fcport; 5506 int status, relogin_needed = 0; 5507 struct event_arg ea; 5508 5509 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5510 /* 5511 * If the port is not ONLINE then try to login 5512 * to it if we haven't run out of retries. 5513 */ 5514 if (atomic_read(&fcport->state) != FCS_ONLINE && 5515 fcport->login_retry) { 5516 if (fcport->scan_state != QLA_FCPORT_FOUND || 5517 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5518 fcport->disc_state == DSC_LOGIN_COMPLETE) 5519 continue; 5520 5521 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5522 fcport->disc_state == DSC_DELETE_PEND) { 5523 relogin_needed = 1; 5524 } else { 5525 if (vha->hw->current_topology != ISP_CFG_NL) { 5526 memset(&ea, 0, sizeof(ea)); 5527 ea.fcport = fcport; 5528 qla24xx_handle_relogin_event(vha, &ea); 5529 } else if (vha->hw->current_topology == 5530 ISP_CFG_NL) { 5531 fcport->login_retry--; 5532 status = 5533 qla2x00_local_device_login(vha, 5534 fcport); 5535 if (status == QLA_SUCCESS) { 5536 fcport->old_loop_id = 5537 fcport->loop_id; 5538 ql_dbg(ql_dbg_disc, vha, 0x2003, 5539 "Port login OK: logged in ID 0x%x.\n", 5540 fcport->loop_id); 5541 qla2x00_update_fcport 5542 (vha, fcport); 5543 } else if (status == 1) { 5544 set_bit(RELOGIN_NEEDED, 5545 &vha->dpc_flags); 5546 /* retry the login again */ 5547 ql_dbg(ql_dbg_disc, vha, 0x2007, 5548 "Retrying %d login again loop_id 0x%x.\n", 5549 fcport->login_retry, 5550 fcport->loop_id); 5551 } else { 5552 fcport->login_retry = 0; 5553 } 5554 5555 if (fcport->login_retry == 0 && 5556 status != QLA_SUCCESS) 5557 qla2x00_clear_loop_id(fcport); 5558 } 5559 } 5560 } 5561 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5562 break; 5563 } 5564 5565 if (relogin_needed) 5566 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5567 5568 ql_dbg(ql_dbg_disc, vha, 0x400e, 5569 "Relogin end.\n"); 5570 } 5571 5572 /* Schedule work on any of the dpc-workqueues */ 5573 void 5574 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5575 { 5576 struct qla_hw_data *ha = base_vha->hw; 5577 5578 switch (work_code) { 5579 case MBA_IDC_AEN: /* 0x8200 */ 5580 if (ha->dpc_lp_wq) 5581 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5582 break; 5583 5584 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5585 if (!ha->flags.nic_core_reset_hdlr_active) { 5586 if (ha->dpc_hp_wq) 5587 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5588 } else 5589 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5590 "NIC Core reset is already active. Skip " 5591 "scheduling it again.\n"); 5592 break; 5593 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5594 if (ha->dpc_hp_wq) 5595 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5596 break; 5597 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5598 if (ha->dpc_hp_wq) 5599 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5600 break; 5601 default: 5602 ql_log(ql_log_warn, base_vha, 0xb05f, 5603 "Unknown work-code=0x%x.\n", work_code); 5604 } 5605 5606 return; 5607 } 5608 5609 /* Work: Perform NIC Core Unrecoverable state handling */ 5610 void 5611 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5612 { 5613 struct qla_hw_data *ha = 5614 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5615 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5616 uint32_t dev_state = 0; 5617 5618 qla83xx_idc_lock(base_vha, 0); 5619 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5620 qla83xx_reset_ownership(base_vha); 5621 if (ha->flags.nic_core_reset_owner) { 5622 ha->flags.nic_core_reset_owner = 0; 5623 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5624 QLA8XXX_DEV_FAILED); 5625 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5626 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5627 } 5628 qla83xx_idc_unlock(base_vha, 0); 5629 } 5630 5631 /* Work: Execute IDC state handler */ 5632 void 5633 qla83xx_idc_state_handler_work(struct work_struct *work) 5634 { 5635 struct qla_hw_data *ha = 5636 container_of(work, struct qla_hw_data, idc_state_handler); 5637 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5638 uint32_t dev_state = 0; 5639 5640 qla83xx_idc_lock(base_vha, 0); 5641 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5642 if (dev_state == QLA8XXX_DEV_FAILED || 5643 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5644 qla83xx_idc_state_handler(base_vha); 5645 qla83xx_idc_unlock(base_vha, 0); 5646 } 5647 5648 static int 5649 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5650 { 5651 int rval = QLA_SUCCESS; 5652 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5653 uint32_t heart_beat_counter1, heart_beat_counter2; 5654 5655 do { 5656 if (time_after(jiffies, heart_beat_wait)) { 5657 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5658 "Nic Core f/w is not alive.\n"); 5659 rval = QLA_FUNCTION_FAILED; 5660 break; 5661 } 5662 5663 qla83xx_idc_lock(base_vha, 0); 5664 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5665 &heart_beat_counter1); 5666 qla83xx_idc_unlock(base_vha, 0); 5667 msleep(100); 5668 qla83xx_idc_lock(base_vha, 0); 5669 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5670 &heart_beat_counter2); 5671 qla83xx_idc_unlock(base_vha, 0); 5672 } while (heart_beat_counter1 == heart_beat_counter2); 5673 5674 return rval; 5675 } 5676 5677 /* Work: Perform NIC Core Reset handling */ 5678 void 5679 qla83xx_nic_core_reset_work(struct work_struct *work) 5680 { 5681 struct qla_hw_data *ha = 5682 container_of(work, struct qla_hw_data, nic_core_reset); 5683 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5684 uint32_t dev_state = 0; 5685 5686 if (IS_QLA2031(ha)) { 5687 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5688 ql_log(ql_log_warn, base_vha, 0xb081, 5689 "Failed to dump mctp\n"); 5690 return; 5691 } 5692 5693 if (!ha->flags.nic_core_reset_hdlr_active) { 5694 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5695 qla83xx_idc_lock(base_vha, 0); 5696 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5697 &dev_state); 5698 qla83xx_idc_unlock(base_vha, 0); 5699 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5700 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5701 "Nic Core f/w is alive.\n"); 5702 return; 5703 } 5704 } 5705 5706 ha->flags.nic_core_reset_hdlr_active = 1; 5707 if (qla83xx_nic_core_reset(base_vha)) { 5708 /* NIC Core reset failed. */ 5709 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5710 "NIC Core reset failed.\n"); 5711 } 5712 ha->flags.nic_core_reset_hdlr_active = 0; 5713 } 5714 } 5715 5716 /* Work: Handle 8200 IDC aens */ 5717 void 5718 qla83xx_service_idc_aen(struct work_struct *work) 5719 { 5720 struct qla_hw_data *ha = 5721 container_of(work, struct qla_hw_data, idc_aen); 5722 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5723 uint32_t dev_state, idc_control; 5724 5725 qla83xx_idc_lock(base_vha, 0); 5726 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5727 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5728 qla83xx_idc_unlock(base_vha, 0); 5729 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5730 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5731 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5732 "Application requested NIC Core Reset.\n"); 5733 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5734 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5735 QLA_SUCCESS) { 5736 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5737 "Other protocol driver requested NIC Core Reset.\n"); 5738 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5739 } 5740 } else if (dev_state == QLA8XXX_DEV_FAILED || 5741 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5742 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5743 } 5744 } 5745 5746 /* 5747 * Control the frequency of IDC lock retries 5748 */ 5749 #define QLA83XX_WAIT_LOGIC_MS 100 5750 5751 static int 5752 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5753 { 5754 int rval; 5755 uint32_t data; 5756 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5757 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5758 struct qla_hw_data *ha = base_vha->hw; 5759 5760 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5761 "Trying force recovery of the IDC lock.\n"); 5762 5763 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5764 if (rval) 5765 return rval; 5766 5767 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5768 return QLA_SUCCESS; 5769 } else { 5770 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5771 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5772 data); 5773 if (rval) 5774 return rval; 5775 5776 msleep(200); 5777 5778 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5779 &data); 5780 if (rval) 5781 return rval; 5782 5783 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5784 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5785 ~(idc_lck_rcvry_stage_mask)); 5786 rval = qla83xx_wr_reg(base_vha, 5787 QLA83XX_IDC_LOCK_RECOVERY, data); 5788 if (rval) 5789 return rval; 5790 5791 /* Forcefully perform IDC UnLock */ 5792 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5793 &data); 5794 if (rval) 5795 return rval; 5796 /* Clear lock-id by setting 0xff */ 5797 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5798 0xff); 5799 if (rval) 5800 return rval; 5801 /* Clear lock-recovery by setting 0x0 */ 5802 rval = qla83xx_wr_reg(base_vha, 5803 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5804 if (rval) 5805 return rval; 5806 } else 5807 return QLA_SUCCESS; 5808 } 5809 5810 return rval; 5811 } 5812 5813 static int 5814 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5815 { 5816 int rval = QLA_SUCCESS; 5817 uint32_t o_drv_lockid, n_drv_lockid; 5818 unsigned long lock_recovery_timeout; 5819 5820 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5821 retry_lockid: 5822 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5823 if (rval) 5824 goto exit; 5825 5826 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5827 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5828 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5829 return QLA_SUCCESS; 5830 else 5831 return QLA_FUNCTION_FAILED; 5832 } 5833 5834 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5835 if (rval) 5836 goto exit; 5837 5838 if (o_drv_lockid == n_drv_lockid) { 5839 msleep(QLA83XX_WAIT_LOGIC_MS); 5840 goto retry_lockid; 5841 } else 5842 return QLA_SUCCESS; 5843 5844 exit: 5845 return rval; 5846 } 5847 5848 /* 5849 * Context: task, can sleep 5850 */ 5851 void 5852 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5853 { 5854 uint32_t data; 5855 uint32_t lock_owner; 5856 struct qla_hw_data *ha = base_vha->hw; 5857 5858 might_sleep(); 5859 5860 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5861 retry_lock: 5862 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5863 == QLA_SUCCESS) { 5864 if (data) { 5865 /* Setting lock-id to our function-number */ 5866 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5867 ha->portnum); 5868 } else { 5869 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5870 &lock_owner); 5871 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5872 "Failed to acquire IDC lock, acquired by %d, " 5873 "retrying...\n", lock_owner); 5874 5875 /* Retry/Perform IDC-Lock recovery */ 5876 if (qla83xx_idc_lock_recovery(base_vha) 5877 == QLA_SUCCESS) { 5878 msleep(QLA83XX_WAIT_LOGIC_MS); 5879 goto retry_lock; 5880 } else 5881 ql_log(ql_log_warn, base_vha, 0xb075, 5882 "IDC Lock recovery FAILED.\n"); 5883 } 5884 5885 } 5886 5887 return; 5888 } 5889 5890 static bool 5891 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5892 struct purex_entry_24xx *purex) 5893 { 5894 char fwstr[16]; 5895 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5896 struct port_database_24xx *pdb; 5897 5898 /* Domain Controller is always logged-out. */ 5899 /* if RDP request is not from Domain Controller: */ 5900 if (sid != 0xfffc01) 5901 return false; 5902 5903 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5904 5905 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5906 if (!pdb) { 5907 ql_dbg(ql_dbg_init, vha, 0x0181, 5908 "%s: Failed allocate pdb\n", __func__); 5909 } else if (qla24xx_get_port_database(vha, 5910 le16_to_cpu(purex->nport_handle), pdb)) { 5911 ql_dbg(ql_dbg_init, vha, 0x0181, 5912 "%s: Failed get pdb sid=%x\n", __func__, sid); 5913 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5914 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5915 ql_dbg(ql_dbg_init, vha, 0x0181, 5916 "%s: Port not logged in sid=%#x\n", __func__, sid); 5917 } else { 5918 /* RDP request is from logged in port */ 5919 kfree(pdb); 5920 return false; 5921 } 5922 kfree(pdb); 5923 5924 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5925 fwstr[strcspn(fwstr, " ")] = 0; 5926 /* if FW version allows RDP response length upto 2048 bytes: */ 5927 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5928 return false; 5929 5930 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5931 5932 /* RDP response length is to be reduced to maximum 256 bytes */ 5933 return true; 5934 } 5935 5936 /* 5937 * Function Name: qla24xx_process_purex_iocb 5938 * 5939 * Description: 5940 * Prepare a RDP response and send to Fabric switch 5941 * 5942 * PARAMETERS: 5943 * vha: SCSI qla host 5944 * purex: RDP request received by HBA 5945 */ 5946 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5947 struct purex_item *item) 5948 { 5949 struct qla_hw_data *ha = vha->hw; 5950 struct purex_entry_24xx *purex = 5951 (struct purex_entry_24xx *)&item->iocb; 5952 dma_addr_t rsp_els_dma; 5953 dma_addr_t rsp_payload_dma; 5954 dma_addr_t stat_dma; 5955 dma_addr_t sfp_dma; 5956 struct els_entry_24xx *rsp_els = NULL; 5957 struct rdp_rsp_payload *rsp_payload = NULL; 5958 struct link_statistics *stat = NULL; 5959 uint8_t *sfp = NULL; 5960 uint16_t sfp_flags = 0; 5961 uint rsp_payload_length = sizeof(*rsp_payload); 5962 int rval; 5963 5964 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5965 "%s: Enter\n", __func__); 5966 5967 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5968 "-------- ELS REQ -------\n"); 5969 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5970 purex, sizeof(*purex)); 5971 5972 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5973 rsp_payload_length = 5974 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5975 ql_dbg(ql_dbg_init, vha, 0x0181, 5976 "Reducing RSP payload length to %u bytes...\n", 5977 rsp_payload_length); 5978 } 5979 5980 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5981 &rsp_els_dma, GFP_KERNEL); 5982 if (!rsp_els) { 5983 ql_log(ql_log_warn, vha, 0x0183, 5984 "Failed allocate dma buffer ELS RSP.\n"); 5985 goto dealloc; 5986 } 5987 5988 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5989 &rsp_payload_dma, GFP_KERNEL); 5990 if (!rsp_payload) { 5991 ql_log(ql_log_warn, vha, 0x0184, 5992 "Failed allocate dma buffer ELS RSP payload.\n"); 5993 goto dealloc; 5994 } 5995 5996 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5997 &sfp_dma, GFP_KERNEL); 5998 5999 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6000 &stat_dma, GFP_KERNEL); 6001 6002 /* Prepare Response IOCB */ 6003 rsp_els->entry_type = ELS_IOCB_TYPE; 6004 rsp_els->entry_count = 1; 6005 rsp_els->sys_define = 0; 6006 rsp_els->entry_status = 0; 6007 rsp_els->handle = 0; 6008 rsp_els->nport_handle = purex->nport_handle; 6009 rsp_els->tx_dsd_count = cpu_to_le16(1); 6010 rsp_els->vp_index = purex->vp_idx; 6011 rsp_els->sof_type = EST_SOFI3; 6012 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6013 rsp_els->rx_dsd_count = 0; 6014 rsp_els->opcode = purex->els_frame_payload[0]; 6015 6016 rsp_els->d_id[0] = purex->s_id[0]; 6017 rsp_els->d_id[1] = purex->s_id[1]; 6018 rsp_els->d_id[2] = purex->s_id[2]; 6019 6020 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6021 rsp_els->rx_byte_count = 0; 6022 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6023 6024 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6025 rsp_els->tx_len = rsp_els->tx_byte_count; 6026 6027 rsp_els->rx_address = 0; 6028 rsp_els->rx_len = 0; 6029 6030 /* Prepare Response Payload */ 6031 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6032 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6033 sizeof(rsp_payload->hdr)); 6034 6035 /* Link service Request Info Descriptor */ 6036 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6037 rsp_payload->ls_req_info_desc.desc_len = 6038 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6039 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6040 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6041 6042 /* Link service Request Info Descriptor 2 */ 6043 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6044 rsp_payload->ls_req_info_desc2.desc_len = 6045 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6046 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6047 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6048 6049 6050 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6051 rsp_payload->sfp_diag_desc.desc_len = 6052 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6053 6054 if (sfp) { 6055 /* SFP Flags */ 6056 memset(sfp, 0, SFP_RTDI_LEN); 6057 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6058 if (!rval) { 6059 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6060 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6061 sfp_flags |= BIT_0; /* short wave */ 6062 else if (sfp[0] & BIT_1) 6063 sfp_flags |= BIT_1; /* long wave 1310nm */ 6064 else if (sfp[1] & BIT_4) 6065 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6066 } 6067 6068 /* SFP Type */ 6069 memset(sfp, 0, SFP_RTDI_LEN); 6070 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6071 if (!rval) { 6072 sfp_flags |= BIT_4; /* optical */ 6073 if (sfp[0] == 0x3) 6074 sfp_flags |= BIT_6; /* sfp+ */ 6075 } 6076 6077 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6078 6079 /* SFP Diagnostics */ 6080 memset(sfp, 0, SFP_RTDI_LEN); 6081 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6082 if (!rval) { 6083 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6084 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6085 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6086 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6087 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6088 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6089 } 6090 } 6091 6092 /* Port Speed Descriptor */ 6093 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6094 rsp_payload->port_speed_desc.desc_len = 6095 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6096 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6097 qla25xx_fdmi_port_speed_capability(ha)); 6098 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6099 qla25xx_fdmi_port_speed_currently(ha)); 6100 6101 /* Link Error Status Descriptor */ 6102 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6103 rsp_payload->ls_err_desc.desc_len = 6104 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6105 6106 if (stat) { 6107 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6108 if (!rval) { 6109 rsp_payload->ls_err_desc.link_fail_cnt = 6110 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6111 rsp_payload->ls_err_desc.loss_sync_cnt = 6112 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6113 rsp_payload->ls_err_desc.loss_sig_cnt = 6114 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6115 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6116 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6117 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6118 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6119 rsp_payload->ls_err_desc.inval_crc_cnt = 6120 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6121 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6122 } 6123 } 6124 6125 /* Portname Descriptor */ 6126 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6127 rsp_payload->port_name_diag_desc.desc_len = 6128 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6129 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6130 vha->node_name, 6131 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6132 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6133 vha->port_name, 6134 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6135 6136 /* F-Port Portname Descriptor */ 6137 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6138 rsp_payload->port_name_direct_desc.desc_len = 6139 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6140 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6141 vha->fabric_node_name, 6142 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6143 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6144 vha->fabric_port_name, 6145 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6146 6147 /* Bufer Credit Descriptor */ 6148 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6149 rsp_payload->buffer_credit_desc.desc_len = 6150 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6151 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6152 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6153 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6154 6155 if (ha->flags.plogi_template_valid) { 6156 uint32_t tmp = 6157 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6158 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6159 } 6160 6161 if (rsp_payload_length < sizeof(*rsp_payload)) 6162 goto send; 6163 6164 /* Optical Element Descriptor, Temperature */ 6165 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6166 rsp_payload->optical_elmt_desc[0].desc_len = 6167 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6168 /* Optical Element Descriptor, Voltage */ 6169 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6170 rsp_payload->optical_elmt_desc[1].desc_len = 6171 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6172 /* Optical Element Descriptor, Tx Bias Current */ 6173 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6174 rsp_payload->optical_elmt_desc[2].desc_len = 6175 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6176 /* Optical Element Descriptor, Tx Power */ 6177 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6178 rsp_payload->optical_elmt_desc[3].desc_len = 6179 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6180 /* Optical Element Descriptor, Rx Power */ 6181 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6182 rsp_payload->optical_elmt_desc[4].desc_len = 6183 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6184 6185 if (sfp) { 6186 memset(sfp, 0, SFP_RTDI_LEN); 6187 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6188 if (!rval) { 6189 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6190 6191 /* Optical Element Descriptor, Temperature */ 6192 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6193 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6194 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6195 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6196 rsp_payload->optical_elmt_desc[0].element_flags = 6197 cpu_to_be32(1 << 28); 6198 6199 /* Optical Element Descriptor, Voltage */ 6200 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6201 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6202 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6203 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6204 rsp_payload->optical_elmt_desc[1].element_flags = 6205 cpu_to_be32(2 << 28); 6206 6207 /* Optical Element Descriptor, Tx Bias Current */ 6208 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6209 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6210 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6211 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6212 rsp_payload->optical_elmt_desc[2].element_flags = 6213 cpu_to_be32(3 << 28); 6214 6215 /* Optical Element Descriptor, Tx Power */ 6216 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6217 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6218 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6219 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6220 rsp_payload->optical_elmt_desc[3].element_flags = 6221 cpu_to_be32(4 << 28); 6222 6223 /* Optical Element Descriptor, Rx Power */ 6224 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6225 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6226 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6227 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6228 rsp_payload->optical_elmt_desc[4].element_flags = 6229 cpu_to_be32(5 << 28); 6230 } 6231 6232 memset(sfp, 0, SFP_RTDI_LEN); 6233 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6234 if (!rval) { 6235 /* Temperature high/low alarm/warning */ 6236 rsp_payload->optical_elmt_desc[0].element_flags |= 6237 cpu_to_be32( 6238 (sfp[0] >> 7 & 1) << 3 | 6239 (sfp[0] >> 6 & 1) << 2 | 6240 (sfp[4] >> 7 & 1) << 1 | 6241 (sfp[4] >> 6 & 1) << 0); 6242 6243 /* Voltage high/low alarm/warning */ 6244 rsp_payload->optical_elmt_desc[1].element_flags |= 6245 cpu_to_be32( 6246 (sfp[0] >> 5 & 1) << 3 | 6247 (sfp[0] >> 4 & 1) << 2 | 6248 (sfp[4] >> 5 & 1) << 1 | 6249 (sfp[4] >> 4 & 1) << 0); 6250 6251 /* Tx Bias Current high/low alarm/warning */ 6252 rsp_payload->optical_elmt_desc[2].element_flags |= 6253 cpu_to_be32( 6254 (sfp[0] >> 3 & 1) << 3 | 6255 (sfp[0] >> 2 & 1) << 2 | 6256 (sfp[4] >> 3 & 1) << 1 | 6257 (sfp[4] >> 2 & 1) << 0); 6258 6259 /* Tx Power high/low alarm/warning */ 6260 rsp_payload->optical_elmt_desc[3].element_flags |= 6261 cpu_to_be32( 6262 (sfp[0] >> 1 & 1) << 3 | 6263 (sfp[0] >> 0 & 1) << 2 | 6264 (sfp[4] >> 1 & 1) << 1 | 6265 (sfp[4] >> 0 & 1) << 0); 6266 6267 /* Rx Power high/low alarm/warning */ 6268 rsp_payload->optical_elmt_desc[4].element_flags |= 6269 cpu_to_be32( 6270 (sfp[1] >> 7 & 1) << 3 | 6271 (sfp[1] >> 6 & 1) << 2 | 6272 (sfp[5] >> 7 & 1) << 1 | 6273 (sfp[5] >> 6 & 1) << 0); 6274 } 6275 } 6276 6277 /* Optical Product Data Descriptor */ 6278 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6279 rsp_payload->optical_prod_desc.desc_len = 6280 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6281 6282 if (sfp) { 6283 memset(sfp, 0, SFP_RTDI_LEN); 6284 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6285 if (!rval) { 6286 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6287 sfp + 0, 6288 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6289 memcpy(rsp_payload->optical_prod_desc.part_number, 6290 sfp + 20, 6291 sizeof(rsp_payload->optical_prod_desc.part_number)); 6292 memcpy(rsp_payload->optical_prod_desc.revision, 6293 sfp + 36, 6294 sizeof(rsp_payload->optical_prod_desc.revision)); 6295 memcpy(rsp_payload->optical_prod_desc.serial_number, 6296 sfp + 48, 6297 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6298 } 6299 6300 memset(sfp, 0, SFP_RTDI_LEN); 6301 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6302 if (!rval) { 6303 memcpy(rsp_payload->optical_prod_desc.date, 6304 sfp + 0, 6305 sizeof(rsp_payload->optical_prod_desc.date)); 6306 } 6307 } 6308 6309 send: 6310 ql_dbg(ql_dbg_init, vha, 0x0183, 6311 "Sending ELS Response to RDP Request...\n"); 6312 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6313 "-------- ELS RSP -------\n"); 6314 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6315 rsp_els, sizeof(*rsp_els)); 6316 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6317 "-------- ELS RSP PAYLOAD -------\n"); 6318 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6319 rsp_payload, rsp_payload_length); 6320 6321 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6322 6323 if (rval) { 6324 ql_log(ql_log_warn, vha, 0x0188, 6325 "%s: iocb failed to execute -> %x\n", __func__, rval); 6326 } else if (rsp_els->comp_status) { 6327 ql_log(ql_log_warn, vha, 0x0189, 6328 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6329 __func__, rsp_els->comp_status, 6330 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6331 } else { 6332 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6333 } 6334 6335 dealloc: 6336 if (stat) 6337 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6338 stat, stat_dma); 6339 if (sfp) 6340 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6341 sfp, sfp_dma); 6342 if (rsp_payload) 6343 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6344 rsp_payload, rsp_payload_dma); 6345 if (rsp_els) 6346 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6347 rsp_els, rsp_els_dma); 6348 } 6349 6350 void 6351 qla24xx_free_purex_item(struct purex_item *item) 6352 { 6353 if (item == &item->vha->default_item) 6354 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6355 else 6356 kfree(item); 6357 } 6358 6359 void qla24xx_process_purex_list(struct purex_list *list) 6360 { 6361 struct list_head head = LIST_HEAD_INIT(head); 6362 struct purex_item *item, *next; 6363 ulong flags; 6364 6365 spin_lock_irqsave(&list->lock, flags); 6366 list_splice_init(&list->head, &head); 6367 spin_unlock_irqrestore(&list->lock, flags); 6368 6369 list_for_each_entry_safe(item, next, &head, list) { 6370 list_del(&item->list); 6371 item->process_item(item->vha, item); 6372 qla24xx_free_purex_item(item); 6373 } 6374 } 6375 6376 /* 6377 * Context: task, can sleep 6378 */ 6379 void 6380 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6381 { 6382 #if 0 6383 uint16_t options = (requester_id << 15) | BIT_7; 6384 #endif 6385 uint16_t retry; 6386 uint32_t data; 6387 struct qla_hw_data *ha = base_vha->hw; 6388 6389 might_sleep(); 6390 6391 /* IDC-unlock implementation using driver-unlock/lock-id 6392 * remote registers 6393 */ 6394 retry = 0; 6395 retry_unlock: 6396 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6397 == QLA_SUCCESS) { 6398 if (data == ha->portnum) { 6399 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6400 /* Clearing lock-id by setting 0xff */ 6401 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6402 } else if (retry < 10) { 6403 /* SV: XXX: IDC unlock retrying needed here? */ 6404 6405 /* Retry for IDC-unlock */ 6406 msleep(QLA83XX_WAIT_LOGIC_MS); 6407 retry++; 6408 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6409 "Failed to release IDC lock, retrying=%d\n", retry); 6410 goto retry_unlock; 6411 } 6412 } else if (retry < 10) { 6413 /* Retry for IDC-unlock */ 6414 msleep(QLA83XX_WAIT_LOGIC_MS); 6415 retry++; 6416 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6417 "Failed to read drv-lockid, retrying=%d\n", retry); 6418 goto retry_unlock; 6419 } 6420 6421 return; 6422 6423 #if 0 6424 /* XXX: IDC-unlock implementation using access-control mbx */ 6425 retry = 0; 6426 retry_unlock2: 6427 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6428 if (retry < 10) { 6429 /* Retry for IDC-unlock */ 6430 msleep(QLA83XX_WAIT_LOGIC_MS); 6431 retry++; 6432 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6433 "Failed to release IDC lock, retrying=%d\n", retry); 6434 goto retry_unlock2; 6435 } 6436 } 6437 6438 return; 6439 #endif 6440 } 6441 6442 int 6443 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6444 { 6445 int rval = QLA_SUCCESS; 6446 struct qla_hw_data *ha = vha->hw; 6447 uint32_t drv_presence; 6448 6449 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6450 if (rval == QLA_SUCCESS) { 6451 drv_presence |= (1 << ha->portnum); 6452 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6453 drv_presence); 6454 } 6455 6456 return rval; 6457 } 6458 6459 int 6460 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6461 { 6462 int rval = QLA_SUCCESS; 6463 6464 qla83xx_idc_lock(vha, 0); 6465 rval = __qla83xx_set_drv_presence(vha); 6466 qla83xx_idc_unlock(vha, 0); 6467 6468 return rval; 6469 } 6470 6471 int 6472 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6473 { 6474 int rval = QLA_SUCCESS; 6475 struct qla_hw_data *ha = vha->hw; 6476 uint32_t drv_presence; 6477 6478 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6479 if (rval == QLA_SUCCESS) { 6480 drv_presence &= ~(1 << ha->portnum); 6481 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6482 drv_presence); 6483 } 6484 6485 return rval; 6486 } 6487 6488 int 6489 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6490 { 6491 int rval = QLA_SUCCESS; 6492 6493 qla83xx_idc_lock(vha, 0); 6494 rval = __qla83xx_clear_drv_presence(vha); 6495 qla83xx_idc_unlock(vha, 0); 6496 6497 return rval; 6498 } 6499 6500 static void 6501 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6502 { 6503 struct qla_hw_data *ha = vha->hw; 6504 uint32_t drv_ack, drv_presence; 6505 unsigned long ack_timeout; 6506 6507 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6508 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6509 while (1) { 6510 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6511 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6512 if ((drv_ack & drv_presence) == drv_presence) 6513 break; 6514 6515 if (time_after_eq(jiffies, ack_timeout)) { 6516 ql_log(ql_log_warn, vha, 0xb067, 6517 "RESET ACK TIMEOUT! drv_presence=0x%x " 6518 "drv_ack=0x%x\n", drv_presence, drv_ack); 6519 /* 6520 * The function(s) which did not ack in time are forced 6521 * to withdraw any further participation in the IDC 6522 * reset. 6523 */ 6524 if (drv_ack != drv_presence) 6525 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6526 drv_ack); 6527 break; 6528 } 6529 6530 qla83xx_idc_unlock(vha, 0); 6531 msleep(1000); 6532 qla83xx_idc_lock(vha, 0); 6533 } 6534 6535 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6536 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6537 } 6538 6539 static int 6540 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6541 { 6542 int rval = QLA_SUCCESS; 6543 uint32_t idc_control; 6544 6545 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6546 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6547 6548 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6549 __qla83xx_get_idc_control(vha, &idc_control); 6550 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6551 __qla83xx_set_idc_control(vha, 0); 6552 6553 qla83xx_idc_unlock(vha, 0); 6554 rval = qla83xx_restart_nic_firmware(vha); 6555 qla83xx_idc_lock(vha, 0); 6556 6557 if (rval != QLA_SUCCESS) { 6558 ql_log(ql_log_fatal, vha, 0xb06a, 6559 "Failed to restart NIC f/w.\n"); 6560 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6561 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6562 } else { 6563 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6564 "Success in restarting nic f/w.\n"); 6565 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6566 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6567 } 6568 6569 return rval; 6570 } 6571 6572 /* Assumes idc_lock always held on entry */ 6573 int 6574 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6575 { 6576 struct qla_hw_data *ha = base_vha->hw; 6577 int rval = QLA_SUCCESS; 6578 unsigned long dev_init_timeout; 6579 uint32_t dev_state; 6580 6581 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6582 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6583 6584 while (1) { 6585 6586 if (time_after_eq(jiffies, dev_init_timeout)) { 6587 ql_log(ql_log_warn, base_vha, 0xb06e, 6588 "Initialization TIMEOUT!\n"); 6589 /* Init timeout. Disable further NIC Core 6590 * communication. 6591 */ 6592 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6593 QLA8XXX_DEV_FAILED); 6594 ql_log(ql_log_info, base_vha, 0xb06f, 6595 "HW State: FAILED.\n"); 6596 } 6597 6598 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6599 switch (dev_state) { 6600 case QLA8XXX_DEV_READY: 6601 if (ha->flags.nic_core_reset_owner) 6602 qla83xx_idc_audit(base_vha, 6603 IDC_AUDIT_COMPLETION); 6604 ha->flags.nic_core_reset_owner = 0; 6605 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6606 "Reset_owner reset by 0x%x.\n", 6607 ha->portnum); 6608 goto exit; 6609 case QLA8XXX_DEV_COLD: 6610 if (ha->flags.nic_core_reset_owner) 6611 rval = qla83xx_device_bootstrap(base_vha); 6612 else { 6613 /* Wait for AEN to change device-state */ 6614 qla83xx_idc_unlock(base_vha, 0); 6615 msleep(1000); 6616 qla83xx_idc_lock(base_vha, 0); 6617 } 6618 break; 6619 case QLA8XXX_DEV_INITIALIZING: 6620 /* Wait for AEN to change device-state */ 6621 qla83xx_idc_unlock(base_vha, 0); 6622 msleep(1000); 6623 qla83xx_idc_lock(base_vha, 0); 6624 break; 6625 case QLA8XXX_DEV_NEED_RESET: 6626 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6627 qla83xx_need_reset_handler(base_vha); 6628 else { 6629 /* Wait for AEN to change device-state */ 6630 qla83xx_idc_unlock(base_vha, 0); 6631 msleep(1000); 6632 qla83xx_idc_lock(base_vha, 0); 6633 } 6634 /* reset timeout value after need reset handler */ 6635 dev_init_timeout = jiffies + 6636 (ha->fcoe_dev_init_timeout * HZ); 6637 break; 6638 case QLA8XXX_DEV_NEED_QUIESCENT: 6639 /* XXX: DEBUG for now */ 6640 qla83xx_idc_unlock(base_vha, 0); 6641 msleep(1000); 6642 qla83xx_idc_lock(base_vha, 0); 6643 break; 6644 case QLA8XXX_DEV_QUIESCENT: 6645 /* XXX: DEBUG for now */ 6646 if (ha->flags.quiesce_owner) 6647 goto exit; 6648 6649 qla83xx_idc_unlock(base_vha, 0); 6650 msleep(1000); 6651 qla83xx_idc_lock(base_vha, 0); 6652 dev_init_timeout = jiffies + 6653 (ha->fcoe_dev_init_timeout * HZ); 6654 break; 6655 case QLA8XXX_DEV_FAILED: 6656 if (ha->flags.nic_core_reset_owner) 6657 qla83xx_idc_audit(base_vha, 6658 IDC_AUDIT_COMPLETION); 6659 ha->flags.nic_core_reset_owner = 0; 6660 __qla83xx_clear_drv_presence(base_vha); 6661 qla83xx_idc_unlock(base_vha, 0); 6662 qla8xxx_dev_failed_handler(base_vha); 6663 rval = QLA_FUNCTION_FAILED; 6664 qla83xx_idc_lock(base_vha, 0); 6665 goto exit; 6666 case QLA8XXX_BAD_VALUE: 6667 qla83xx_idc_unlock(base_vha, 0); 6668 msleep(1000); 6669 qla83xx_idc_lock(base_vha, 0); 6670 break; 6671 default: 6672 ql_log(ql_log_warn, base_vha, 0xb071, 6673 "Unknown Device State: %x.\n", dev_state); 6674 qla83xx_idc_unlock(base_vha, 0); 6675 qla8xxx_dev_failed_handler(base_vha); 6676 rval = QLA_FUNCTION_FAILED; 6677 qla83xx_idc_lock(base_vha, 0); 6678 goto exit; 6679 } 6680 } 6681 6682 exit: 6683 return rval; 6684 } 6685 6686 void 6687 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6688 { 6689 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6690 board_disable); 6691 struct pci_dev *pdev = ha->pdev; 6692 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6693 6694 ql_log(ql_log_warn, base_vha, 0x015b, 6695 "Disabling adapter.\n"); 6696 6697 if (!atomic_read(&pdev->enable_cnt)) { 6698 ql_log(ql_log_info, base_vha, 0xfffc, 6699 "PCI device disabled, no action req for PCI error=%lx\n", 6700 base_vha->pci_flags); 6701 return; 6702 } 6703 6704 /* 6705 * if UNLOADING flag is already set, then continue unload, 6706 * where it was set first. 6707 */ 6708 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6709 return; 6710 6711 qla2x00_wait_for_sess_deletion(base_vha); 6712 6713 qla2x00_delete_all_vps(ha, base_vha); 6714 6715 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6716 6717 qla2x00_dfs_remove(base_vha); 6718 6719 qla84xx_put_chip(base_vha); 6720 6721 if (base_vha->timer_active) 6722 qla2x00_stop_timer(base_vha); 6723 6724 base_vha->flags.online = 0; 6725 6726 qla2x00_destroy_deferred_work(ha); 6727 6728 /* 6729 * Do not try to stop beacon blink as it will issue a mailbox 6730 * command. 6731 */ 6732 qla2x00_free_sysfs_attr(base_vha, false); 6733 6734 fc_remove_host(base_vha->host); 6735 6736 scsi_remove_host(base_vha->host); 6737 6738 base_vha->flags.init_done = 0; 6739 qla25xx_delete_queues(base_vha); 6740 qla2x00_free_fcports(base_vha); 6741 qla2x00_free_irqs(base_vha); 6742 qla2x00_mem_free(ha); 6743 qla82xx_md_free(base_vha); 6744 qla2x00_free_queues(ha); 6745 6746 qla2x00_unmap_iobases(ha); 6747 6748 pci_release_selected_regions(ha->pdev, ha->bars); 6749 pci_disable_pcie_error_reporting(pdev); 6750 pci_disable_device(pdev); 6751 6752 /* 6753 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6754 */ 6755 } 6756 6757 /************************************************************************** 6758 * qla2x00_do_dpc 6759 * This kernel thread is a task that is schedule by the interrupt handler 6760 * to perform the background processing for interrupts. 6761 * 6762 * Notes: 6763 * This task always run in the context of a kernel thread. It 6764 * is kick-off by the driver's detect code and starts up 6765 * up one per adapter. It immediately goes to sleep and waits for 6766 * some fibre event. When either the interrupt handler or 6767 * the timer routine detects a event it will one of the task 6768 * bits then wake us up. 6769 **************************************************************************/ 6770 static int 6771 qla2x00_do_dpc(void *data) 6772 { 6773 scsi_qla_host_t *base_vha; 6774 struct qla_hw_data *ha; 6775 uint32_t online; 6776 struct qla_qpair *qpair; 6777 6778 ha = (struct qla_hw_data *)data; 6779 base_vha = pci_get_drvdata(ha->pdev); 6780 6781 set_user_nice(current, MIN_NICE); 6782 6783 set_current_state(TASK_INTERRUPTIBLE); 6784 while (!kthread_should_stop()) { 6785 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6786 "DPC handler sleeping.\n"); 6787 6788 schedule(); 6789 6790 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6791 qla_pci_set_eeh_busy(base_vha); 6792 6793 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6794 goto end_loop; 6795 6796 if (ha->flags.eeh_busy) { 6797 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6798 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6799 goto end_loop; 6800 } 6801 6802 ha->dpc_active = 1; 6803 6804 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6805 "DPC handler waking up, dpc_flags=0x%lx.\n", 6806 base_vha->dpc_flags); 6807 6808 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6809 break; 6810 6811 if (IS_P3P_TYPE(ha)) { 6812 if (IS_QLA8044(ha)) { 6813 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6814 &base_vha->dpc_flags)) { 6815 qla8044_idc_lock(ha); 6816 qla8044_wr_direct(base_vha, 6817 QLA8044_CRB_DEV_STATE_INDEX, 6818 QLA8XXX_DEV_FAILED); 6819 qla8044_idc_unlock(ha); 6820 ql_log(ql_log_info, base_vha, 0x4004, 6821 "HW State: FAILED.\n"); 6822 qla8044_device_state_handler(base_vha); 6823 continue; 6824 } 6825 6826 } else { 6827 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6828 &base_vha->dpc_flags)) { 6829 qla82xx_idc_lock(ha); 6830 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6831 QLA8XXX_DEV_FAILED); 6832 qla82xx_idc_unlock(ha); 6833 ql_log(ql_log_info, base_vha, 0x0151, 6834 "HW State: FAILED.\n"); 6835 qla82xx_device_state_handler(base_vha); 6836 continue; 6837 } 6838 } 6839 6840 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6841 &base_vha->dpc_flags)) { 6842 6843 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6844 "FCoE context reset scheduled.\n"); 6845 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6846 &base_vha->dpc_flags))) { 6847 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6848 /* FCoE-ctx reset failed. 6849 * Escalate to chip-reset 6850 */ 6851 set_bit(ISP_ABORT_NEEDED, 6852 &base_vha->dpc_flags); 6853 } 6854 clear_bit(ABORT_ISP_ACTIVE, 6855 &base_vha->dpc_flags); 6856 } 6857 6858 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6859 "FCoE context reset end.\n"); 6860 } 6861 } else if (IS_QLAFX00(ha)) { 6862 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6863 &base_vha->dpc_flags)) { 6864 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6865 "Firmware Reset Recovery\n"); 6866 if (qlafx00_reset_initialize(base_vha)) { 6867 /* Failed. Abort isp later. */ 6868 if (!test_bit(UNLOADING, 6869 &base_vha->dpc_flags)) { 6870 set_bit(ISP_UNRECOVERABLE, 6871 &base_vha->dpc_flags); 6872 ql_dbg(ql_dbg_dpc, base_vha, 6873 0x4021, 6874 "Reset Recovery Failed\n"); 6875 } 6876 } 6877 } 6878 6879 if (test_and_clear_bit(FX00_TARGET_SCAN, 6880 &base_vha->dpc_flags)) { 6881 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6882 "ISPFx00 Target Scan scheduled\n"); 6883 if (qlafx00_rescan_isp(base_vha)) { 6884 if (!test_bit(UNLOADING, 6885 &base_vha->dpc_flags)) 6886 set_bit(ISP_UNRECOVERABLE, 6887 &base_vha->dpc_flags); 6888 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6889 "ISPFx00 Target Scan Failed\n"); 6890 } 6891 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6892 "ISPFx00 Target Scan End\n"); 6893 } 6894 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6895 &base_vha->dpc_flags)) { 6896 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6897 "ISPFx00 Host Info resend scheduled\n"); 6898 qlafx00_fx_disc(base_vha, 6899 &base_vha->hw->mr.fcport, 6900 FXDISC_REG_HOST_INFO); 6901 } 6902 } 6903 6904 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6905 &base_vha->dpc_flags)) { 6906 /* Semantic: 6907 * - NO-OP -- await next ISP-ABORT. Preferred method 6908 * to minimize disruptions that will occur 6909 * when a forced chip-reset occurs. 6910 * - Force -- ISP-ABORT scheduled. 6911 */ 6912 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6913 } 6914 6915 if (test_and_clear_bit 6916 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6917 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6918 bool do_reset = true; 6919 6920 switch (base_vha->qlini_mode) { 6921 case QLA2XXX_INI_MODE_ENABLED: 6922 break; 6923 case QLA2XXX_INI_MODE_DISABLED: 6924 if (!qla_tgt_mode_enabled(base_vha) && 6925 !ha->flags.fw_started) 6926 do_reset = false; 6927 break; 6928 case QLA2XXX_INI_MODE_DUAL: 6929 if (!qla_dual_mode_enabled(base_vha) && 6930 !ha->flags.fw_started) 6931 do_reset = false; 6932 break; 6933 default: 6934 break; 6935 } 6936 6937 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6938 &base_vha->dpc_flags))) { 6939 base_vha->flags.online = 1; 6940 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6941 "ISP abort scheduled.\n"); 6942 if (ha->isp_ops->abort_isp(base_vha)) { 6943 /* failed. retry later */ 6944 set_bit(ISP_ABORT_NEEDED, 6945 &base_vha->dpc_flags); 6946 } 6947 clear_bit(ABORT_ISP_ACTIVE, 6948 &base_vha->dpc_flags); 6949 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6950 "ISP abort end.\n"); 6951 } 6952 } 6953 6954 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6955 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6956 qla24xx_process_purex_list 6957 (&base_vha->purex_list); 6958 clear_bit(PROCESS_PUREX_IOCB, 6959 &base_vha->dpc_flags); 6960 } 6961 } 6962 6963 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6964 &base_vha->dpc_flags)) { 6965 qla2x00_update_fcports(base_vha); 6966 } 6967 6968 if (IS_QLAFX00(ha)) 6969 goto loop_resync_check; 6970 6971 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6972 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6973 "Quiescence mode scheduled.\n"); 6974 if (IS_P3P_TYPE(ha)) { 6975 if (IS_QLA82XX(ha)) 6976 qla82xx_device_state_handler(base_vha); 6977 if (IS_QLA8044(ha)) 6978 qla8044_device_state_handler(base_vha); 6979 clear_bit(ISP_QUIESCE_NEEDED, 6980 &base_vha->dpc_flags); 6981 if (!ha->flags.quiesce_owner) { 6982 qla2x00_perform_loop_resync(base_vha); 6983 if (IS_QLA82XX(ha)) { 6984 qla82xx_idc_lock(ha); 6985 qla82xx_clear_qsnt_ready( 6986 base_vha); 6987 qla82xx_idc_unlock(ha); 6988 } else if (IS_QLA8044(ha)) { 6989 qla8044_idc_lock(ha); 6990 qla8044_clear_qsnt_ready( 6991 base_vha); 6992 qla8044_idc_unlock(ha); 6993 } 6994 } 6995 } else { 6996 clear_bit(ISP_QUIESCE_NEEDED, 6997 &base_vha->dpc_flags); 6998 qla2x00_quiesce_io(base_vha); 6999 } 7000 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7001 "Quiescence mode end.\n"); 7002 } 7003 7004 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7005 &base_vha->dpc_flags) && 7006 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7007 7008 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7009 "Reset marker scheduled.\n"); 7010 qla2x00_rst_aen(base_vha); 7011 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7012 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7013 "Reset marker end.\n"); 7014 } 7015 7016 /* Retry each device up to login retry count */ 7017 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7018 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7019 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7020 7021 if (!base_vha->relogin_jif || 7022 time_after_eq(jiffies, base_vha->relogin_jif)) { 7023 base_vha->relogin_jif = jiffies + HZ; 7024 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7025 7026 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7027 "Relogin scheduled.\n"); 7028 qla24xx_post_relogin_work(base_vha); 7029 } 7030 } 7031 loop_resync_check: 7032 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 7033 &base_vha->dpc_flags)) { 7034 7035 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7036 "Loop resync scheduled.\n"); 7037 7038 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7039 &base_vha->dpc_flags))) { 7040 7041 qla2x00_loop_resync(base_vha); 7042 7043 clear_bit(LOOP_RESYNC_ACTIVE, 7044 &base_vha->dpc_flags); 7045 } 7046 7047 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7048 "Loop resync end.\n"); 7049 } 7050 7051 if (IS_QLAFX00(ha)) 7052 goto intr_on_check; 7053 7054 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7055 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7056 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7057 qla2xxx_flash_npiv_conf(base_vha); 7058 } 7059 7060 intr_on_check: 7061 if (!ha->interrupts_on) 7062 ha->isp_ops->enable_intrs(ha); 7063 7064 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7065 &base_vha->dpc_flags)) { 7066 if (ha->beacon_blink_led == 1) 7067 ha->isp_ops->beacon_blink(base_vha); 7068 } 7069 7070 /* qpair online check */ 7071 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7072 &base_vha->dpc_flags)) { 7073 if (ha->flags.eeh_busy || 7074 ha->flags.pci_channel_io_perm_failure) 7075 online = 0; 7076 else 7077 online = 1; 7078 7079 mutex_lock(&ha->mq_lock); 7080 list_for_each_entry(qpair, &base_vha->qp_list, 7081 qp_list_elem) 7082 qpair->online = online; 7083 mutex_unlock(&ha->mq_lock); 7084 } 7085 7086 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7087 &base_vha->dpc_flags)) { 7088 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7089 7090 if (threshold > ha->orig_fw_xcb_count) 7091 threshold = ha->orig_fw_xcb_count; 7092 7093 ql_log(ql_log_info, base_vha, 0xffffff, 7094 "SET ZIO Activity exchange threshold to %d.\n", 7095 threshold); 7096 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7097 ql_log(ql_log_info, base_vha, 0xffffff, 7098 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7099 threshold); 7100 } 7101 } 7102 7103 if (!IS_QLAFX00(ha)) 7104 qla2x00_do_dpc_all_vps(base_vha); 7105 7106 if (test_and_clear_bit(N2N_LINK_RESET, 7107 &base_vha->dpc_flags)) { 7108 qla2x00_lip_reset(base_vha); 7109 } 7110 7111 ha->dpc_active = 0; 7112 end_loop: 7113 set_current_state(TASK_INTERRUPTIBLE); 7114 } /* End of while(1) */ 7115 __set_current_state(TASK_RUNNING); 7116 7117 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7118 "DPC handler exiting.\n"); 7119 7120 /* 7121 * Make sure that nobody tries to wake us up again. 7122 */ 7123 ha->dpc_active = 0; 7124 7125 /* Cleanup any residual CTX SRBs. */ 7126 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7127 7128 return 0; 7129 } 7130 7131 void 7132 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7133 { 7134 struct qla_hw_data *ha = vha->hw; 7135 struct task_struct *t = ha->dpc_thread; 7136 7137 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7138 wake_up_process(t); 7139 } 7140 7141 /* 7142 * qla2x00_rst_aen 7143 * Processes asynchronous reset. 7144 * 7145 * Input: 7146 * ha = adapter block pointer. 7147 */ 7148 static void 7149 qla2x00_rst_aen(scsi_qla_host_t *vha) 7150 { 7151 if (vha->flags.online && !vha->flags.reset_active && 7152 !atomic_read(&vha->loop_down_timer) && 7153 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7154 do { 7155 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7156 7157 /* 7158 * Issue marker command only when we are going to start 7159 * the I/O. 7160 */ 7161 vha->marker_needed = 1; 7162 } while (!atomic_read(&vha->loop_down_timer) && 7163 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7164 } 7165 } 7166 7167 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7168 { 7169 struct qla_hw_data *ha = vha->hw; 7170 u32 cmpl_cnt; 7171 u16 i; 7172 bool do_heartbeat = false; 7173 7174 /* 7175 * Allow do_heartbeat only if we don’t have any active interrupts, 7176 * but there are still IOs outstanding with firmware. 7177 */ 7178 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7179 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7180 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7181 do_heartbeat = true; 7182 goto skip; 7183 } 7184 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7185 7186 for (i = 0; i < ha->max_qpairs; i++) { 7187 if (ha->queue_pair_map[i]) { 7188 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7189 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7190 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7191 do_heartbeat = true; 7192 break; 7193 } 7194 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7195 } 7196 } 7197 7198 skip: 7199 return do_heartbeat; 7200 } 7201 7202 static void qla_heart_beat(struct scsi_qla_host *vha) 7203 { 7204 struct qla_hw_data *ha = vha->hw; 7205 7206 if (vha->vp_idx) 7207 return; 7208 7209 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7210 return; 7211 7212 if (qla_do_heartbeat(vha)) 7213 queue_work(ha->wq, &ha->heartbeat_work); 7214 } 7215 7216 /************************************************************************** 7217 * qla2x00_timer 7218 * 7219 * Description: 7220 * One second timer 7221 * 7222 * Context: Interrupt 7223 ***************************************************************************/ 7224 void 7225 qla2x00_timer(struct timer_list *t) 7226 { 7227 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7228 unsigned long cpu_flags = 0; 7229 int start_dpc = 0; 7230 int index; 7231 srb_t *sp; 7232 uint16_t w; 7233 struct qla_hw_data *ha = vha->hw; 7234 struct req_que *req; 7235 unsigned long flags; 7236 fc_port_t *fcport = NULL; 7237 7238 if (ha->flags.eeh_busy) { 7239 ql_dbg(ql_dbg_timer, vha, 0x6000, 7240 "EEH = %d, restarting timer.\n", 7241 ha->flags.eeh_busy); 7242 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7243 return; 7244 } 7245 7246 /* 7247 * Hardware read to raise pending EEH errors during mailbox waits. If 7248 * the read returns -1 then disable the board. 7249 */ 7250 if (!pci_channel_offline(ha->pdev)) { 7251 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7252 qla2x00_check_reg16_for_disconnect(vha, w); 7253 } 7254 7255 /* Make sure qla82xx_watchdog is run only for physical port */ 7256 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7257 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7258 start_dpc++; 7259 if (IS_QLA82XX(ha)) 7260 qla82xx_watchdog(vha); 7261 else if (IS_QLA8044(ha)) 7262 qla8044_watchdog(vha); 7263 } 7264 7265 if (!vha->vp_idx && IS_QLAFX00(ha)) 7266 qlafx00_timer_routine(vha); 7267 7268 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7269 vha->link_down_time++; 7270 7271 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7272 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7273 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7274 fcport->tgt_link_down_time++; 7275 } 7276 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7277 7278 /* Loop down handler. */ 7279 if (atomic_read(&vha->loop_down_timer) > 0 && 7280 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7281 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7282 && vha->flags.online) { 7283 7284 if (atomic_read(&vha->loop_down_timer) == 7285 vha->loop_down_abort_time) { 7286 7287 ql_log(ql_log_info, vha, 0x6008, 7288 "Loop down - aborting the queues before time expires.\n"); 7289 7290 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7291 atomic_set(&vha->loop_state, LOOP_DEAD); 7292 7293 /* 7294 * Schedule an ISP abort to return any FCP2-device 7295 * commands. 7296 */ 7297 /* NPIV - scan physical port only */ 7298 if (!vha->vp_idx) { 7299 spin_lock_irqsave(&ha->hardware_lock, 7300 cpu_flags); 7301 req = ha->req_q_map[0]; 7302 for (index = 1; 7303 index < req->num_outstanding_cmds; 7304 index++) { 7305 fc_port_t *sfcp; 7306 7307 sp = req->outstanding_cmds[index]; 7308 if (!sp) 7309 continue; 7310 if (sp->cmd_type != TYPE_SRB) 7311 continue; 7312 if (sp->type != SRB_SCSI_CMD) 7313 continue; 7314 sfcp = sp->fcport; 7315 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7316 continue; 7317 7318 if (IS_QLA82XX(ha)) 7319 set_bit(FCOE_CTX_RESET_NEEDED, 7320 &vha->dpc_flags); 7321 else 7322 set_bit(ISP_ABORT_NEEDED, 7323 &vha->dpc_flags); 7324 break; 7325 } 7326 spin_unlock_irqrestore(&ha->hardware_lock, 7327 cpu_flags); 7328 } 7329 start_dpc++; 7330 } 7331 7332 /* if the loop has been down for 4 minutes, reinit adapter */ 7333 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7334 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7335 ql_log(ql_log_warn, vha, 0x6009, 7336 "Loop down - aborting ISP.\n"); 7337 7338 if (IS_QLA82XX(ha)) 7339 set_bit(FCOE_CTX_RESET_NEEDED, 7340 &vha->dpc_flags); 7341 else 7342 set_bit(ISP_ABORT_NEEDED, 7343 &vha->dpc_flags); 7344 } 7345 } 7346 ql_dbg(ql_dbg_timer, vha, 0x600a, 7347 "Loop down - seconds remaining %d.\n", 7348 atomic_read(&vha->loop_down_timer)); 7349 } 7350 /* Check if beacon LED needs to be blinked for physical host only */ 7351 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7352 /* There is no beacon_blink function for ISP82xx */ 7353 if (!IS_P3P_TYPE(ha)) { 7354 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7355 start_dpc++; 7356 } 7357 } 7358 7359 /* check if edif running */ 7360 if (vha->hw->flags.edif_enabled) 7361 qla_edif_timer(vha); 7362 7363 /* Process any deferred work. */ 7364 if (!list_empty(&vha->work_list)) { 7365 unsigned long flags; 7366 bool q = false; 7367 7368 spin_lock_irqsave(&vha->work_lock, flags); 7369 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7370 q = true; 7371 spin_unlock_irqrestore(&vha->work_lock, flags); 7372 if (q) 7373 queue_work(vha->hw->wq, &vha->iocb_work); 7374 } 7375 7376 /* 7377 * FC-NVME 7378 * see if the active AEN count has changed from what was last reported. 7379 */ 7380 index = atomic_read(&ha->nvme_active_aen_cnt); 7381 if (!vha->vp_idx && 7382 (index != ha->nvme_last_rptd_aen) && 7383 ha->zio_mode == QLA_ZIO_MODE_6 && 7384 !ha->flags.host_shutting_down) { 7385 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7386 ql_log(ql_log_info, vha, 0x3002, 7387 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7388 ha->nvme_last_rptd_aen); 7389 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7390 start_dpc++; 7391 } 7392 7393 if (!vha->vp_idx && 7394 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7395 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7396 ql_log(ql_log_info, vha, 0x3002, 7397 "Sched: Set ZIO exchange threshold to %d.\n", 7398 ha->last_zio_threshold); 7399 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7400 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7401 start_dpc++; 7402 } 7403 7404 /* Schedule the DPC routine if needed */ 7405 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7406 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7407 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7408 start_dpc || 7409 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7410 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7411 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7412 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7413 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7414 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7415 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7416 ql_dbg(ql_dbg_timer, vha, 0x600b, 7417 "isp_abort_needed=%d loop_resync_needed=%d " 7418 "fcport_update_needed=%d start_dpc=%d " 7419 "reset_marker_needed=%d", 7420 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7421 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7422 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7423 start_dpc, 7424 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7425 ql_dbg(ql_dbg_timer, vha, 0x600c, 7426 "beacon_blink_needed=%d isp_unrecoverable=%d " 7427 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7428 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7429 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7430 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7431 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7432 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7433 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7434 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7435 qla2xxx_wake_dpc(vha); 7436 } 7437 7438 qla_heart_beat(vha); 7439 7440 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7441 } 7442 7443 /* Firmware interface routines. */ 7444 7445 #define FW_ISP21XX 0 7446 #define FW_ISP22XX 1 7447 #define FW_ISP2300 2 7448 #define FW_ISP2322 3 7449 #define FW_ISP24XX 4 7450 #define FW_ISP25XX 5 7451 #define FW_ISP81XX 6 7452 #define FW_ISP82XX 7 7453 #define FW_ISP2031 8 7454 #define FW_ISP8031 9 7455 #define FW_ISP27XX 10 7456 #define FW_ISP28XX 11 7457 7458 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7459 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7460 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7461 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7462 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7463 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7464 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7465 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7466 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7467 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7468 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7469 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7470 7471 7472 static DEFINE_MUTEX(qla_fw_lock); 7473 7474 static struct fw_blob qla_fw_blobs[] = { 7475 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7476 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7477 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7478 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7479 { .name = FW_FILE_ISP24XX, }, 7480 { .name = FW_FILE_ISP25XX, }, 7481 { .name = FW_FILE_ISP81XX, }, 7482 { .name = FW_FILE_ISP82XX, }, 7483 { .name = FW_FILE_ISP2031, }, 7484 { .name = FW_FILE_ISP8031, }, 7485 { .name = FW_FILE_ISP27XX, }, 7486 { .name = FW_FILE_ISP28XX, }, 7487 { .name = NULL, }, 7488 }; 7489 7490 struct fw_blob * 7491 qla2x00_request_firmware(scsi_qla_host_t *vha) 7492 { 7493 struct qla_hw_data *ha = vha->hw; 7494 struct fw_blob *blob; 7495 7496 if (IS_QLA2100(ha)) { 7497 blob = &qla_fw_blobs[FW_ISP21XX]; 7498 } else if (IS_QLA2200(ha)) { 7499 blob = &qla_fw_blobs[FW_ISP22XX]; 7500 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7501 blob = &qla_fw_blobs[FW_ISP2300]; 7502 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7503 blob = &qla_fw_blobs[FW_ISP2322]; 7504 } else if (IS_QLA24XX_TYPE(ha)) { 7505 blob = &qla_fw_blobs[FW_ISP24XX]; 7506 } else if (IS_QLA25XX(ha)) { 7507 blob = &qla_fw_blobs[FW_ISP25XX]; 7508 } else if (IS_QLA81XX(ha)) { 7509 blob = &qla_fw_blobs[FW_ISP81XX]; 7510 } else if (IS_QLA82XX(ha)) { 7511 blob = &qla_fw_blobs[FW_ISP82XX]; 7512 } else if (IS_QLA2031(ha)) { 7513 blob = &qla_fw_blobs[FW_ISP2031]; 7514 } else if (IS_QLA8031(ha)) { 7515 blob = &qla_fw_blobs[FW_ISP8031]; 7516 } else if (IS_QLA27XX(ha)) { 7517 blob = &qla_fw_blobs[FW_ISP27XX]; 7518 } else if (IS_QLA28XX(ha)) { 7519 blob = &qla_fw_blobs[FW_ISP28XX]; 7520 } else { 7521 return NULL; 7522 } 7523 7524 if (!blob->name) 7525 return NULL; 7526 7527 mutex_lock(&qla_fw_lock); 7528 if (blob->fw) 7529 goto out; 7530 7531 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7532 ql_log(ql_log_warn, vha, 0x0063, 7533 "Failed to load firmware image (%s).\n", blob->name); 7534 blob->fw = NULL; 7535 blob = NULL; 7536 } 7537 7538 out: 7539 mutex_unlock(&qla_fw_lock); 7540 return blob; 7541 } 7542 7543 static void 7544 qla2x00_release_firmware(void) 7545 { 7546 struct fw_blob *blob; 7547 7548 mutex_lock(&qla_fw_lock); 7549 for (blob = qla_fw_blobs; blob->name; blob++) 7550 release_firmware(blob->fw); 7551 mutex_unlock(&qla_fw_lock); 7552 } 7553 7554 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7555 { 7556 struct qla_hw_data *ha = vha->hw; 7557 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7558 struct qla_qpair *qpair = NULL; 7559 struct scsi_qla_host *vp, *tvp; 7560 fc_port_t *fcport; 7561 int i; 7562 unsigned long flags; 7563 7564 ql_dbg(ql_dbg_aer, vha, 0x9000, 7565 "%s\n", __func__); 7566 ha->chip_reset++; 7567 7568 ha->base_qpair->chip_reset = ha->chip_reset; 7569 for (i = 0; i < ha->max_qpairs; i++) { 7570 if (ha->queue_pair_map[i]) 7571 ha->queue_pair_map[i]->chip_reset = 7572 ha->base_qpair->chip_reset; 7573 } 7574 7575 /* 7576 * purge mailbox might take a while. Slot Reset/chip reset 7577 * will take care of the purge 7578 */ 7579 7580 mutex_lock(&ha->mq_lock); 7581 ha->base_qpair->online = 0; 7582 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7583 qpair->online = 0; 7584 wmb(); 7585 mutex_unlock(&ha->mq_lock); 7586 7587 qla2x00_mark_all_devices_lost(vha); 7588 7589 spin_lock_irqsave(&ha->vport_slock, flags); 7590 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7591 atomic_inc(&vp->vref_count); 7592 spin_unlock_irqrestore(&ha->vport_slock, flags); 7593 qla2x00_mark_all_devices_lost(vp); 7594 spin_lock_irqsave(&ha->vport_slock, flags); 7595 atomic_dec(&vp->vref_count); 7596 } 7597 spin_unlock_irqrestore(&ha->vport_slock, flags); 7598 7599 /* Clear all async request states across all VPs. */ 7600 list_for_each_entry(fcport, &vha->vp_fcports, list) 7601 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7602 7603 spin_lock_irqsave(&ha->vport_slock, flags); 7604 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7605 atomic_inc(&vp->vref_count); 7606 spin_unlock_irqrestore(&ha->vport_slock, flags); 7607 list_for_each_entry(fcport, &vp->vp_fcports, list) 7608 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7609 spin_lock_irqsave(&ha->vport_slock, flags); 7610 atomic_dec(&vp->vref_count); 7611 } 7612 spin_unlock_irqrestore(&ha->vport_slock, flags); 7613 } 7614 7615 7616 static pci_ers_result_t 7617 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7618 { 7619 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7620 struct qla_hw_data *ha = vha->hw; 7621 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7622 7623 ql_log(ql_log_warn, vha, 0x9000, 7624 "PCI error detected, state %x.\n", state); 7625 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7626 7627 if (!atomic_read(&pdev->enable_cnt)) { 7628 ql_log(ql_log_info, vha, 0xffff, 7629 "PCI device is disabled,state %x\n", state); 7630 ret = PCI_ERS_RESULT_NEED_RESET; 7631 goto out; 7632 } 7633 7634 switch (state) { 7635 case pci_channel_io_normal: 7636 ha->flags.eeh_busy = 0; 7637 if (ql2xmqsupport || ql2xnvmeenable) { 7638 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7639 qla2xxx_wake_dpc(vha); 7640 } 7641 ret = PCI_ERS_RESULT_CAN_RECOVER; 7642 break; 7643 case pci_channel_io_frozen: 7644 qla_pci_set_eeh_busy(vha); 7645 ret = PCI_ERS_RESULT_NEED_RESET; 7646 break; 7647 case pci_channel_io_perm_failure: 7648 ha->flags.pci_channel_io_perm_failure = 1; 7649 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7650 if (ql2xmqsupport || ql2xnvmeenable) { 7651 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7652 qla2xxx_wake_dpc(vha); 7653 } 7654 ret = PCI_ERS_RESULT_DISCONNECT; 7655 } 7656 out: 7657 ql_dbg(ql_dbg_aer, vha, 0x600d, 7658 "PCI error detected returning [%x].\n", ret); 7659 return ret; 7660 } 7661 7662 static pci_ers_result_t 7663 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7664 { 7665 int risc_paused = 0; 7666 uint32_t stat; 7667 unsigned long flags; 7668 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7669 struct qla_hw_data *ha = base_vha->hw; 7670 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7671 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7672 7673 ql_log(ql_log_warn, base_vha, 0x9000, 7674 "mmio enabled\n"); 7675 7676 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7677 if (IS_QLA82XX(ha)) 7678 return PCI_ERS_RESULT_RECOVERED; 7679 7680 spin_lock_irqsave(&ha->hardware_lock, flags); 7681 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7682 stat = rd_reg_word(®->hccr); 7683 if (stat & HCCR_RISC_PAUSE) 7684 risc_paused = 1; 7685 } else if (IS_QLA23XX(ha)) { 7686 stat = rd_reg_dword(®->u.isp2300.host_status); 7687 if (stat & HSR_RISC_PAUSED) 7688 risc_paused = 1; 7689 } else if (IS_FWI2_CAPABLE(ha)) { 7690 stat = rd_reg_dword(®24->host_status); 7691 if (stat & HSRX_RISC_PAUSED) 7692 risc_paused = 1; 7693 } 7694 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7695 7696 if (risc_paused) { 7697 ql_log(ql_log_info, base_vha, 0x9003, 7698 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7699 qla2xxx_dump_fw(base_vha); 7700 } 7701 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7702 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7703 "mmio enabled returning.\n"); 7704 return PCI_ERS_RESULT_NEED_RESET; 7705 } 7706 7707 static pci_ers_result_t 7708 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7709 { 7710 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7711 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7712 struct qla_hw_data *ha = base_vha->hw; 7713 int rc; 7714 struct qla_qpair *qpair = NULL; 7715 7716 ql_log(ql_log_warn, base_vha, 0x9004, 7717 "Slot Reset.\n"); 7718 7719 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7720 /* Workaround: qla2xxx driver which access hardware earlier 7721 * needs error state to be pci_channel_io_online. 7722 * Otherwise mailbox command timesout. 7723 */ 7724 pdev->error_state = pci_channel_io_normal; 7725 7726 pci_restore_state(pdev); 7727 7728 /* pci_restore_state() clears the saved_state flag of the device 7729 * save restored state which resets saved_state flag 7730 */ 7731 pci_save_state(pdev); 7732 7733 if (ha->mem_only) 7734 rc = pci_enable_device_mem(pdev); 7735 else 7736 rc = pci_enable_device(pdev); 7737 7738 if (rc) { 7739 ql_log(ql_log_warn, base_vha, 0x9005, 7740 "Can't re-enable PCI device after reset.\n"); 7741 goto exit_slot_reset; 7742 } 7743 7744 7745 if (ha->isp_ops->pci_config(base_vha)) 7746 goto exit_slot_reset; 7747 7748 mutex_lock(&ha->mq_lock); 7749 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7750 qpair->online = 1; 7751 mutex_unlock(&ha->mq_lock); 7752 7753 ha->flags.eeh_busy = 0; 7754 base_vha->flags.online = 1; 7755 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7756 ha->isp_ops->abort_isp(base_vha); 7757 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7758 7759 if (qla2x00_isp_reg_stat(ha)) { 7760 ha->flags.eeh_busy = 1; 7761 qla_pci_error_cleanup(base_vha); 7762 ql_log(ql_log_warn, base_vha, 0x9005, 7763 "Device unable to recover from PCI error.\n"); 7764 } else { 7765 ret = PCI_ERS_RESULT_RECOVERED; 7766 } 7767 7768 exit_slot_reset: 7769 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7770 "Slot Reset returning %x.\n", ret); 7771 7772 return ret; 7773 } 7774 7775 static void 7776 qla2xxx_pci_resume(struct pci_dev *pdev) 7777 { 7778 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7779 struct qla_hw_data *ha = base_vha->hw; 7780 int ret; 7781 7782 ql_log(ql_log_warn, base_vha, 0x900f, 7783 "Pci Resume.\n"); 7784 7785 7786 ret = qla2x00_wait_for_hba_online(base_vha); 7787 if (ret != QLA_SUCCESS) { 7788 ql_log(ql_log_fatal, base_vha, 0x9002, 7789 "The device failed to resume I/O from slot/link_reset.\n"); 7790 } 7791 ha->pci_error_state = QLA_PCI_RESUME; 7792 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7793 "Pci Resume returning.\n"); 7794 } 7795 7796 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7797 { 7798 struct qla_hw_data *ha = vha->hw; 7799 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7800 bool do_cleanup = false; 7801 unsigned long flags; 7802 7803 if (ha->flags.eeh_busy) 7804 return; 7805 7806 spin_lock_irqsave(&base_vha->work_lock, flags); 7807 if (!ha->flags.eeh_busy) { 7808 ha->flags.eeh_busy = 1; 7809 do_cleanup = true; 7810 } 7811 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7812 7813 if (do_cleanup) 7814 qla_pci_error_cleanup(base_vha); 7815 } 7816 7817 /* 7818 * this routine will schedule a task to pause IO from interrupt context 7819 * if caller sees a PCIE error event (register read = 0xf's) 7820 */ 7821 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7822 { 7823 struct qla_hw_data *ha = vha->hw; 7824 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7825 7826 if (ha->flags.eeh_busy) 7827 return; 7828 7829 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7830 qla2xxx_wake_dpc(base_vha); 7831 } 7832 7833 static void 7834 qla_pci_reset_prepare(struct pci_dev *pdev) 7835 { 7836 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7837 struct qla_hw_data *ha = base_vha->hw; 7838 struct qla_qpair *qpair; 7839 7840 ql_log(ql_log_warn, base_vha, 0xffff, 7841 "%s.\n", __func__); 7842 7843 /* 7844 * PCI FLR/function reset is about to reset the 7845 * slot. Stop the chip to stop all DMA access. 7846 * It is assumed that pci_reset_done will be called 7847 * after FLR to resume Chip operation. 7848 */ 7849 ha->flags.eeh_busy = 1; 7850 mutex_lock(&ha->mq_lock); 7851 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7852 qpair->online = 0; 7853 mutex_unlock(&ha->mq_lock); 7854 7855 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7856 qla2x00_abort_isp_cleanup(base_vha); 7857 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7858 } 7859 7860 static void 7861 qla_pci_reset_done(struct pci_dev *pdev) 7862 { 7863 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7864 struct qla_hw_data *ha = base_vha->hw; 7865 struct qla_qpair *qpair; 7866 7867 ql_log(ql_log_warn, base_vha, 0xffff, 7868 "%s.\n", __func__); 7869 7870 /* 7871 * FLR just completed by PCI layer. Resume adapter 7872 */ 7873 ha->flags.eeh_busy = 0; 7874 mutex_lock(&ha->mq_lock); 7875 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7876 qpair->online = 1; 7877 mutex_unlock(&ha->mq_lock); 7878 7879 base_vha->flags.online = 1; 7880 ha->isp_ops->abort_isp(base_vha); 7881 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7882 } 7883 7884 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7885 { 7886 int rc; 7887 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7888 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7889 7890 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7891 rc = blk_mq_map_queues(qmap); 7892 else 7893 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7894 return rc; 7895 } 7896 7897 struct scsi_host_template qla2xxx_driver_template = { 7898 .module = THIS_MODULE, 7899 .name = QLA2XXX_DRIVER_NAME, 7900 .queuecommand = qla2xxx_queuecommand, 7901 7902 .eh_timed_out = fc_eh_timed_out, 7903 .eh_abort_handler = qla2xxx_eh_abort, 7904 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 7905 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7906 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7907 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7908 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7909 7910 .slave_configure = qla2xxx_slave_configure, 7911 7912 .slave_alloc = qla2xxx_slave_alloc, 7913 .slave_destroy = qla2xxx_slave_destroy, 7914 .scan_finished = qla2xxx_scan_finished, 7915 .scan_start = qla2xxx_scan_start, 7916 .change_queue_depth = scsi_change_queue_depth, 7917 .map_queues = qla2xxx_map_queues, 7918 .this_id = -1, 7919 .cmd_per_lun = 3, 7920 .sg_tablesize = SG_ALL, 7921 7922 .max_sectors = 0xFFFF, 7923 .shost_groups = qla2x00_host_groups, 7924 7925 .supported_mode = MODE_INITIATOR, 7926 .track_queue_depth = 1, 7927 .cmd_size = sizeof(srb_t), 7928 }; 7929 7930 static const struct pci_error_handlers qla2xxx_err_handler = { 7931 .error_detected = qla2xxx_pci_error_detected, 7932 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7933 .slot_reset = qla2xxx_pci_slot_reset, 7934 .resume = qla2xxx_pci_resume, 7935 .reset_prepare = qla_pci_reset_prepare, 7936 .reset_done = qla_pci_reset_done, 7937 }; 7938 7939 static struct pci_device_id qla2xxx_pci_tbl[] = { 7940 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7941 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7942 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7943 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7944 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7945 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7946 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7947 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7948 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7949 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7950 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7951 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7952 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7953 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7954 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7955 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7956 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7957 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7958 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7959 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7960 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7961 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7962 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7963 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7964 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7965 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7966 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7967 { 0 }, 7968 }; 7969 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7970 7971 static struct pci_driver qla2xxx_pci_driver = { 7972 .name = QLA2XXX_DRIVER_NAME, 7973 .driver = { 7974 .owner = THIS_MODULE, 7975 }, 7976 .id_table = qla2xxx_pci_tbl, 7977 .probe = qla2x00_probe_one, 7978 .remove = qla2x00_remove_one, 7979 .shutdown = qla2x00_shutdown, 7980 .err_handler = &qla2xxx_err_handler, 7981 }; 7982 7983 static const struct file_operations apidev_fops = { 7984 .owner = THIS_MODULE, 7985 .llseek = noop_llseek, 7986 }; 7987 7988 /** 7989 * qla2x00_module_init - Module initialization. 7990 **/ 7991 static int __init 7992 qla2x00_module_init(void) 7993 { 7994 int ret = 0; 7995 7996 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 7997 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7998 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7999 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8000 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8001 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8002 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8003 BUILD_BUG_ON(sizeof(request_t) != 64); 8004 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8005 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8006 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8007 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8008 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8009 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8010 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8011 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8012 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8013 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8014 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8015 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8016 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8017 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8018 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8019 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8020 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8021 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8022 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8023 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8024 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8025 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8026 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8027 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8028 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8029 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8030 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8031 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8032 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8033 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8034 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8035 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8036 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8037 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8038 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8039 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8040 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8041 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8042 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8043 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8044 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8045 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8046 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8047 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8048 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8049 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8050 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8051 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8052 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8053 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8054 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8055 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8056 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8057 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8058 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8059 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8060 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8061 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8062 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8063 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8064 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8065 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8066 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8067 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8068 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8069 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8070 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8071 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8072 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8073 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8074 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8075 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8076 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8077 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8078 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8079 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8080 8081 /* Allocate cache for SRBs. */ 8082 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8083 SLAB_HWCACHE_ALIGN, NULL); 8084 if (srb_cachep == NULL) { 8085 ql_log(ql_log_fatal, NULL, 0x0001, 8086 "Unable to allocate SRB cache...Failing load!.\n"); 8087 return -ENOMEM; 8088 } 8089 8090 /* Initialize target kmem_cache and mem_pools */ 8091 ret = qlt_init(); 8092 if (ret < 0) { 8093 goto destroy_cache; 8094 } else if (ret > 0) { 8095 /* 8096 * If initiator mode is explictly disabled by qlt_init(), 8097 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8098 * performing scsi_scan_target() during LOOP UP event. 8099 */ 8100 qla2xxx_transport_functions.disable_target_scan = 1; 8101 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8102 } 8103 8104 /* Derive version string. */ 8105 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8106 if (ql2xextended_error_logging) 8107 strcat(qla2x00_version_str, "-debug"); 8108 if (ql2xextended_error_logging == 1) 8109 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8110 8111 qla2xxx_transport_template = 8112 fc_attach_transport(&qla2xxx_transport_functions); 8113 if (!qla2xxx_transport_template) { 8114 ql_log(ql_log_fatal, NULL, 0x0002, 8115 "fc_attach_transport failed...Failing load!.\n"); 8116 ret = -ENODEV; 8117 goto qlt_exit; 8118 } 8119 8120 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8121 if (apidev_major < 0) { 8122 ql_log(ql_log_fatal, NULL, 0x0003, 8123 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8124 } 8125 8126 qla2xxx_transport_vport_template = 8127 fc_attach_transport(&qla2xxx_transport_vport_functions); 8128 if (!qla2xxx_transport_vport_template) { 8129 ql_log(ql_log_fatal, NULL, 0x0004, 8130 "fc_attach_transport vport failed...Failing load!.\n"); 8131 ret = -ENODEV; 8132 goto unreg_chrdev; 8133 } 8134 ql_log(ql_log_info, NULL, 0x0005, 8135 "QLogic Fibre Channel HBA Driver: %s.\n", 8136 qla2x00_version_str); 8137 ret = pci_register_driver(&qla2xxx_pci_driver); 8138 if (ret) { 8139 ql_log(ql_log_fatal, NULL, 0x0006, 8140 "pci_register_driver failed...ret=%d Failing load!.\n", 8141 ret); 8142 goto release_vport_transport; 8143 } 8144 return ret; 8145 8146 release_vport_transport: 8147 fc_release_transport(qla2xxx_transport_vport_template); 8148 8149 unreg_chrdev: 8150 if (apidev_major >= 0) 8151 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8152 fc_release_transport(qla2xxx_transport_template); 8153 8154 qlt_exit: 8155 qlt_exit(); 8156 8157 destroy_cache: 8158 kmem_cache_destroy(srb_cachep); 8159 return ret; 8160 } 8161 8162 /** 8163 * qla2x00_module_exit - Module cleanup. 8164 **/ 8165 static void __exit 8166 qla2x00_module_exit(void) 8167 { 8168 pci_unregister_driver(&qla2xxx_pci_driver); 8169 qla2x00_release_firmware(); 8170 kmem_cache_destroy(ctx_cachep); 8171 fc_release_transport(qla2xxx_transport_vport_template); 8172 if (apidev_major >= 0) 8173 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8174 fc_release_transport(qla2xxx_transport_template); 8175 qlt_exit(); 8176 kmem_cache_destroy(srb_cachep); 8177 } 8178 8179 module_init(qla2x00_module_init); 8180 module_exit(qla2x00_module_exit); 8181 8182 MODULE_AUTHOR("QLogic Corporation"); 8183 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8184 MODULE_LICENSE("GPL"); 8185 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8186 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8187 MODULE_FIRMWARE(FW_FILE_ISP2300); 8188 MODULE_FIRMWARE(FW_FILE_ISP2322); 8189 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8190 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8191