1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 364 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 365 366 /* TODO Convert to inlines 367 * 368 * Timer routines 369 */ 370 371 __inline__ void 372 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 373 { 374 timer_setup(&vha->timer, qla2x00_timer, 0); 375 vha->timer.expires = jiffies + interval * HZ; 376 add_timer(&vha->timer); 377 vha->timer_active = 1; 378 } 379 380 static inline void 381 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 382 { 383 /* Currently used for 82XX only. */ 384 if (vha->device_flags & DFLG_DEV_FAILED) { 385 ql_dbg(ql_dbg_timer, vha, 0x600d, 386 "Device in a failed state, returning.\n"); 387 return; 388 } 389 390 mod_timer(&vha->timer, jiffies + interval * HZ); 391 } 392 393 static __inline__ void 394 qla2x00_stop_timer(scsi_qla_host_t *vha) 395 { 396 del_timer_sync(&vha->timer); 397 vha->timer_active = 0; 398 } 399 400 static int qla2x00_do_dpc(void *data); 401 402 static void qla2x00_rst_aen(scsi_qla_host_t *); 403 404 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 405 struct req_que **, struct rsp_que **); 406 static void qla2x00_free_fw_dump(struct qla_hw_data *); 407 static void qla2x00_mem_free(struct qla_hw_data *); 408 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 409 struct qla_qpair *qpair); 410 411 /* -------------------------------------------------------------------------- */ 412 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 413 struct rsp_que *rsp) 414 { 415 struct qla_hw_data *ha = vha->hw; 416 417 rsp->qpair = ha->base_qpair; 418 rsp->req = req; 419 ha->base_qpair->hw = ha; 420 ha->base_qpair->req = req; 421 ha->base_qpair->rsp = rsp; 422 ha->base_qpair->vha = vha; 423 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 424 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 425 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 426 ha->base_qpair->srb_mempool = ha->srb_mempool; 427 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 428 ha->base_qpair->enable_class_2 = ql2xenableclass2; 429 /* init qpair to this cpu. Will adjust at run time. */ 430 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 431 ha->base_qpair->pdev = ha->pdev; 432 433 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 434 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 435 } 436 437 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 438 struct rsp_que *rsp) 439 { 440 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 441 442 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 443 GFP_KERNEL); 444 if (!ha->req_q_map) { 445 ql_log(ql_log_fatal, vha, 0x003b, 446 "Unable to allocate memory for request queue ptrs.\n"); 447 goto fail_req_map; 448 } 449 450 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 451 GFP_KERNEL); 452 if (!ha->rsp_q_map) { 453 ql_log(ql_log_fatal, vha, 0x003c, 454 "Unable to allocate memory for response queue ptrs.\n"); 455 goto fail_rsp_map; 456 } 457 458 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 459 if (ha->base_qpair == NULL) { 460 ql_log(ql_log_warn, vha, 0x00e0, 461 "Failed to allocate base queue pair memory.\n"); 462 goto fail_base_qpair; 463 } 464 465 qla_init_base_qpair(vha, req, rsp); 466 467 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 468 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 469 GFP_KERNEL); 470 if (!ha->queue_pair_map) { 471 ql_log(ql_log_fatal, vha, 0x0180, 472 "Unable to allocate memory for queue pair ptrs.\n"); 473 goto fail_qpair_map; 474 } 475 } 476 477 /* 478 * Make sure we record at least the request and response queue zero in 479 * case we need to free them if part of the probe fails. 480 */ 481 ha->rsp_q_map[0] = rsp; 482 ha->req_q_map[0] = req; 483 set_bit(0, ha->rsp_qid_map); 484 set_bit(0, ha->req_qid_map); 485 return 0; 486 487 fail_qpair_map: 488 kfree(ha->base_qpair); 489 ha->base_qpair = NULL; 490 fail_base_qpair: 491 kfree(ha->rsp_q_map); 492 ha->rsp_q_map = NULL; 493 fail_rsp_map: 494 kfree(ha->req_q_map); 495 ha->req_q_map = NULL; 496 fail_req_map: 497 return -ENOMEM; 498 } 499 500 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 501 { 502 if (IS_QLAFX00(ha)) { 503 if (req && req->ring_fx00) 504 dma_free_coherent(&ha->pdev->dev, 505 (req->length_fx00 + 1) * sizeof(request_t), 506 req->ring_fx00, req->dma_fx00); 507 } else if (req && req->ring) 508 dma_free_coherent(&ha->pdev->dev, 509 (req->length + 1) * sizeof(request_t), 510 req->ring, req->dma); 511 512 if (req) 513 kfree(req->outstanding_cmds); 514 515 kfree(req); 516 } 517 518 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 519 { 520 if (IS_QLAFX00(ha)) { 521 if (rsp && rsp->ring_fx00) 522 dma_free_coherent(&ha->pdev->dev, 523 (rsp->length_fx00 + 1) * sizeof(request_t), 524 rsp->ring_fx00, rsp->dma_fx00); 525 } else if (rsp && rsp->ring) { 526 dma_free_coherent(&ha->pdev->dev, 527 (rsp->length + 1) * sizeof(response_t), 528 rsp->ring, rsp->dma); 529 } 530 kfree(rsp); 531 } 532 533 static void qla2x00_free_queues(struct qla_hw_data *ha) 534 { 535 struct req_que *req; 536 struct rsp_que *rsp; 537 int cnt; 538 unsigned long flags; 539 540 if (ha->queue_pair_map) { 541 kfree(ha->queue_pair_map); 542 ha->queue_pair_map = NULL; 543 } 544 if (ha->base_qpair) { 545 kfree(ha->base_qpair); 546 ha->base_qpair = NULL; 547 } 548 549 spin_lock_irqsave(&ha->hardware_lock, flags); 550 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 551 if (!test_bit(cnt, ha->req_qid_map)) 552 continue; 553 554 req = ha->req_q_map[cnt]; 555 clear_bit(cnt, ha->req_qid_map); 556 ha->req_q_map[cnt] = NULL; 557 558 spin_unlock_irqrestore(&ha->hardware_lock, flags); 559 qla2x00_free_req_que(ha, req); 560 spin_lock_irqsave(&ha->hardware_lock, flags); 561 } 562 spin_unlock_irqrestore(&ha->hardware_lock, flags); 563 564 kfree(ha->req_q_map); 565 ha->req_q_map = NULL; 566 567 568 spin_lock_irqsave(&ha->hardware_lock, flags); 569 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 570 if (!test_bit(cnt, ha->rsp_qid_map)) 571 continue; 572 573 rsp = ha->rsp_q_map[cnt]; 574 clear_bit(cnt, ha->rsp_qid_map); 575 ha->rsp_q_map[cnt] = NULL; 576 spin_unlock_irqrestore(&ha->hardware_lock, flags); 577 qla2x00_free_rsp_que(ha, rsp); 578 spin_lock_irqsave(&ha->hardware_lock, flags); 579 } 580 spin_unlock_irqrestore(&ha->hardware_lock, flags); 581 582 kfree(ha->rsp_q_map); 583 ha->rsp_q_map = NULL; 584 } 585 586 static char * 587 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 588 { 589 struct qla_hw_data *ha = vha->hw; 590 static const char *const pci_bus_modes[] = { 591 "33", "66", "100", "133", 592 }; 593 uint16_t pci_bus; 594 595 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 596 if (pci_bus) { 597 snprintf(str, str_len, "PCI-X (%s MHz)", 598 pci_bus_modes[pci_bus]); 599 } else { 600 pci_bus = (ha->pci_attr & BIT_8) >> 8; 601 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 602 } 603 604 return str; 605 } 606 607 static char * 608 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 609 { 610 static const char *const pci_bus_modes[] = { 611 "33", "66", "100", "133", 612 }; 613 struct qla_hw_data *ha = vha->hw; 614 uint32_t pci_bus; 615 616 if (pci_is_pcie(ha->pdev)) { 617 uint32_t lstat, lspeed, lwidth; 618 const char *speed_str; 619 620 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 621 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 622 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 623 624 switch (lspeed) { 625 case 1: 626 speed_str = "2.5GT/s"; 627 break; 628 case 2: 629 speed_str = "5.0GT/s"; 630 break; 631 case 3: 632 speed_str = "8.0GT/s"; 633 break; 634 case 4: 635 speed_str = "16.0GT/s"; 636 break; 637 default: 638 speed_str = "<unknown>"; 639 break; 640 } 641 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 642 643 return str; 644 } 645 646 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 647 if (pci_bus == 0 || pci_bus == 8) 648 snprintf(str, str_len, "PCI (%s MHz)", 649 pci_bus_modes[pci_bus >> 3]); 650 else 651 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 652 pci_bus & 4 ? 2 : 1, 653 pci_bus_modes[pci_bus & 3]); 654 655 return str; 656 } 657 658 static char * 659 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 660 { 661 char un_str[10]; 662 struct qla_hw_data *ha = vha->hw; 663 664 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 665 ha->fw_minor_version, ha->fw_subminor_version); 666 667 if (ha->fw_attributes & BIT_9) { 668 strcat(str, "FLX"); 669 return (str); 670 } 671 672 switch (ha->fw_attributes & 0xFF) { 673 case 0x7: 674 strcat(str, "EF"); 675 break; 676 case 0x17: 677 strcat(str, "TP"); 678 break; 679 case 0x37: 680 strcat(str, "IP"); 681 break; 682 case 0x77: 683 strcat(str, "VI"); 684 break; 685 default: 686 sprintf(un_str, "(%x)", ha->fw_attributes); 687 strcat(str, un_str); 688 break; 689 } 690 if (ha->fw_attributes & 0x100) 691 strcat(str, "X"); 692 693 return (str); 694 } 695 696 static char * 697 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 698 { 699 struct qla_hw_data *ha = vha->hw; 700 701 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 702 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 703 return str; 704 } 705 706 void qla2x00_sp_free_dma(srb_t *sp) 707 { 708 struct qla_hw_data *ha = sp->vha->hw; 709 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 710 711 if (sp->flags & SRB_DMA_VALID) { 712 scsi_dma_unmap(cmd); 713 sp->flags &= ~SRB_DMA_VALID; 714 } 715 716 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 717 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 718 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 719 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 720 } 721 722 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 723 /* List assured to be having elements */ 724 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 725 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 726 } 727 728 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 729 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 730 731 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 732 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 736 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 737 738 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 739 ctx1->fcp_cmnd_dma); 740 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 741 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 742 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 743 mempool_free(ctx1, ha->ctx_mempool); 744 } 745 } 746 747 void qla2x00_sp_compl(srb_t *sp, int res) 748 { 749 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 750 struct completion *comp = sp->comp; 751 752 /* kref: INIT */ 753 kref_put(&sp->cmd_kref, qla2x00_sp_release); 754 cmd->result = res; 755 sp->type = 0; 756 scsi_done(cmd); 757 if (comp) 758 complete(comp); 759 } 760 761 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 762 { 763 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 764 struct qla_hw_data *ha = sp->fcport->vha->hw; 765 766 if (sp->flags & SRB_DMA_VALID) { 767 scsi_dma_unmap(cmd); 768 sp->flags &= ~SRB_DMA_VALID; 769 } 770 771 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 772 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 773 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 774 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 775 } 776 777 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 778 /* List assured to be having elements */ 779 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 780 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 781 } 782 783 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 784 struct crc_context *difctx = sp->u.scmd.crc_ctx; 785 struct dsd_dma *dif_dsd, *nxt_dsd; 786 787 list_for_each_entry_safe(dif_dsd, nxt_dsd, 788 &difctx->ldif_dma_hndl_list, list) { 789 list_del(&dif_dsd->list); 790 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 791 dif_dsd->dsd_list_dma); 792 kfree(dif_dsd); 793 difctx->no_dif_bundl--; 794 } 795 796 list_for_each_entry_safe(dif_dsd, nxt_dsd, 797 &difctx->ldif_dsd_list, list) { 798 list_del(&dif_dsd->list); 799 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 800 dif_dsd->dsd_list_dma); 801 kfree(dif_dsd); 802 difctx->no_ldif_dsd--; 803 } 804 805 if (difctx->no_ldif_dsd) { 806 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 807 "%s: difctx->no_ldif_dsd=%x\n", 808 __func__, difctx->no_ldif_dsd); 809 } 810 811 if (difctx->no_dif_bundl) { 812 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 813 "%s: difctx->no_dif_bundl=%x\n", 814 __func__, difctx->no_dif_bundl); 815 } 816 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 817 } 818 819 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 820 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 821 822 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 823 ctx1->fcp_cmnd_dma); 824 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 825 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 826 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 827 mempool_free(ctx1, ha->ctx_mempool); 828 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 829 } 830 831 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 832 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 833 834 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 835 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 836 } 837 } 838 839 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 840 { 841 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 842 struct completion *comp = sp->comp; 843 844 /* ref: INIT */ 845 kref_put(&sp->cmd_kref, qla2x00_sp_release); 846 cmd->result = res; 847 sp->type = 0; 848 scsi_done(cmd); 849 if (comp) 850 complete(comp); 851 } 852 853 static int 854 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 855 { 856 scsi_qla_host_t *vha = shost_priv(host); 857 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 858 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 859 struct qla_hw_data *ha = vha->hw; 860 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 861 srb_t *sp; 862 int rval; 863 864 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 865 WARN_ON_ONCE(!rport)) { 866 cmd->result = DID_NO_CONNECT << 16; 867 goto qc24_fail_command; 868 } 869 870 if (ha->mqenable) { 871 uint32_t tag; 872 uint16_t hwq; 873 struct qla_qpair *qpair = NULL; 874 875 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 876 hwq = blk_mq_unique_tag_to_hwq(tag); 877 qpair = ha->queue_pair_map[hwq]; 878 879 if (qpair) 880 return qla2xxx_mqueuecommand(host, cmd, qpair); 881 } 882 883 if (ha->flags.eeh_busy) { 884 if (ha->flags.pci_channel_io_perm_failure) { 885 ql_dbg(ql_dbg_aer, vha, 0x9010, 886 "PCI Channel IO permanent failure, exiting " 887 "cmd=%p.\n", cmd); 888 cmd->result = DID_NO_CONNECT << 16; 889 } else { 890 ql_dbg(ql_dbg_aer, vha, 0x9011, 891 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 892 cmd->result = DID_REQUEUE << 16; 893 } 894 goto qc24_fail_command; 895 } 896 897 rval = fc_remote_port_chkready(rport); 898 if (rval) { 899 cmd->result = rval; 900 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 901 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 902 cmd, rval); 903 goto qc24_fail_command; 904 } 905 906 if (!vha->flags.difdix_supported && 907 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 908 ql_dbg(ql_dbg_io, vha, 0x3004, 909 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 910 cmd); 911 cmd->result = DID_NO_CONNECT << 16; 912 goto qc24_fail_command; 913 } 914 915 if (!fcport || fcport->deleted) { 916 cmd->result = DID_IMM_RETRY << 16; 917 goto qc24_fail_command; 918 } 919 920 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 921 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 922 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 923 ql_dbg(ql_dbg_io, vha, 0x3005, 924 "Returning DNC, fcport_state=%d loop_state=%d.\n", 925 atomic_read(&fcport->state), 926 atomic_read(&base_vha->loop_state)); 927 cmd->result = DID_NO_CONNECT << 16; 928 goto qc24_fail_command; 929 } 930 goto qc24_target_busy; 931 } 932 933 /* 934 * Return target busy if we've received a non-zero retry_delay_timer 935 * in a FCP_RSP. 936 */ 937 if (fcport->retry_delay_timestamp == 0) { 938 /* retry delay not set */ 939 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 940 fcport->retry_delay_timestamp = 0; 941 else 942 goto qc24_target_busy; 943 944 sp = scsi_cmd_priv(cmd); 945 /* ref: INIT */ 946 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 947 948 sp->u.scmd.cmd = cmd; 949 sp->type = SRB_SCSI_CMD; 950 sp->free = qla2x00_sp_free_dma; 951 sp->done = qla2x00_sp_compl; 952 953 rval = ha->isp_ops->start_scsi(sp); 954 if (rval != QLA_SUCCESS) { 955 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 956 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 957 goto qc24_host_busy_free_sp; 958 } 959 960 return 0; 961 962 qc24_host_busy_free_sp: 963 /* ref: INIT */ 964 kref_put(&sp->cmd_kref, qla2x00_sp_release); 965 966 qc24_target_busy: 967 return SCSI_MLQUEUE_TARGET_BUSY; 968 969 qc24_fail_command: 970 scsi_done(cmd); 971 972 return 0; 973 } 974 975 /* For MQ supported I/O */ 976 int 977 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 978 struct qla_qpair *qpair) 979 { 980 scsi_qla_host_t *vha = shost_priv(host); 981 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 982 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 983 struct qla_hw_data *ha = vha->hw; 984 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 985 srb_t *sp; 986 int rval; 987 988 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 989 if (rval) { 990 cmd->result = rval; 991 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 992 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 993 cmd, rval); 994 goto qc24_fail_command; 995 } 996 997 if (!qpair->online) { 998 ql_dbg(ql_dbg_io, vha, 0x3077, 999 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1000 cmd->result = DID_NO_CONNECT << 16; 1001 goto qc24_fail_command; 1002 } 1003 1004 if (!fcport || fcport->deleted) { 1005 cmd->result = DID_IMM_RETRY << 16; 1006 goto qc24_fail_command; 1007 } 1008 1009 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1010 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1011 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1012 ql_dbg(ql_dbg_io, vha, 0x3077, 1013 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1014 atomic_read(&fcport->state), 1015 atomic_read(&base_vha->loop_state)); 1016 cmd->result = DID_NO_CONNECT << 16; 1017 goto qc24_fail_command; 1018 } 1019 goto qc24_target_busy; 1020 } 1021 1022 /* 1023 * Return target busy if we've received a non-zero retry_delay_timer 1024 * in a FCP_RSP. 1025 */ 1026 if (fcport->retry_delay_timestamp == 0) { 1027 /* retry delay not set */ 1028 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1029 fcport->retry_delay_timestamp = 0; 1030 else 1031 goto qc24_target_busy; 1032 1033 sp = scsi_cmd_priv(cmd); 1034 /* ref: INIT */ 1035 qla2xxx_init_sp(sp, vha, qpair, fcport); 1036 1037 sp->u.scmd.cmd = cmd; 1038 sp->type = SRB_SCSI_CMD; 1039 sp->free = qla2xxx_qpair_sp_free_dma; 1040 sp->done = qla2xxx_qpair_sp_compl; 1041 1042 rval = ha->isp_ops->start_scsi_mq(sp); 1043 if (rval != QLA_SUCCESS) { 1044 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1045 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1046 goto qc24_host_busy_free_sp; 1047 } 1048 1049 return 0; 1050 1051 qc24_host_busy_free_sp: 1052 /* ref: INIT */ 1053 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1054 1055 qc24_target_busy: 1056 return SCSI_MLQUEUE_TARGET_BUSY; 1057 1058 qc24_fail_command: 1059 scsi_done(cmd); 1060 1061 return 0; 1062 } 1063 1064 /* 1065 * qla2x00_eh_wait_on_command 1066 * Waits for the command to be returned by the Firmware for some 1067 * max time. 1068 * 1069 * Input: 1070 * cmd = Scsi Command to wait on. 1071 * 1072 * Return: 1073 * Completed in time : QLA_SUCCESS 1074 * Did not complete in time : QLA_FUNCTION_FAILED 1075 */ 1076 static int 1077 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1078 { 1079 #define ABORT_POLLING_PERIOD 1000 1080 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1081 unsigned long wait_iter = ABORT_WAIT_ITER; 1082 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1083 struct qla_hw_data *ha = vha->hw; 1084 srb_t *sp = scsi_cmd_priv(cmd); 1085 int ret = QLA_SUCCESS; 1086 1087 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1088 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1089 "Return:eh_wait.\n"); 1090 return ret; 1091 } 1092 1093 while (sp->type && wait_iter--) 1094 msleep(ABORT_POLLING_PERIOD); 1095 if (sp->type) 1096 ret = QLA_FUNCTION_FAILED; 1097 1098 return ret; 1099 } 1100 1101 /* 1102 * qla2x00_wait_for_hba_online 1103 * Wait till the HBA is online after going through 1104 * <= MAX_RETRIES_OF_ISP_ABORT or 1105 * finally HBA is disabled ie marked offline 1106 * 1107 * Input: 1108 * ha - pointer to host adapter structure 1109 * 1110 * Note: 1111 * Does context switching-Release SPIN_LOCK 1112 * (if any) before calling this routine. 1113 * 1114 * Return: 1115 * Success (Adapter is online) : 0 1116 * Failed (Adapter is offline/disabled) : 1 1117 */ 1118 int 1119 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1120 { 1121 int return_status; 1122 unsigned long wait_online; 1123 struct qla_hw_data *ha = vha->hw; 1124 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1125 1126 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1127 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1128 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1129 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1130 ha->dpc_active) && time_before(jiffies, wait_online)) { 1131 1132 msleep(1000); 1133 } 1134 if (base_vha->flags.online) 1135 return_status = QLA_SUCCESS; 1136 else 1137 return_status = QLA_FUNCTION_FAILED; 1138 1139 return (return_status); 1140 } 1141 1142 static inline int test_fcport_count(scsi_qla_host_t *vha) 1143 { 1144 struct qla_hw_data *ha = vha->hw; 1145 unsigned long flags; 1146 int res; 1147 /* Return 0 = sleep, x=wake */ 1148 1149 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1150 ql_dbg(ql_dbg_init, vha, 0x00ec, 1151 "tgt %p, fcport_count=%d\n", 1152 vha, vha->fcport_count); 1153 res = (vha->fcport_count == 0); 1154 if (res) { 1155 struct fc_port *fcport; 1156 1157 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1158 if (fcport->deleted != QLA_SESS_DELETED) { 1159 /* session(s) may not be fully logged in 1160 * (ie fcport_count=0), but session 1161 * deletion thread(s) may be inflight. 1162 */ 1163 1164 res = 0; 1165 break; 1166 } 1167 } 1168 } 1169 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1170 1171 return res; 1172 } 1173 1174 /* 1175 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1176 * it has dependency on UNLOADING flag to stop device discovery 1177 */ 1178 void 1179 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1180 { 1181 u8 i; 1182 1183 qla2x00_mark_all_devices_lost(vha); 1184 1185 for (i = 0; i < 10; i++) { 1186 if (wait_event_timeout(vha->fcport_waitQ, 1187 test_fcport_count(vha), HZ) > 0) 1188 break; 1189 } 1190 1191 flush_workqueue(vha->hw->wq); 1192 } 1193 1194 /* 1195 * qla2x00_wait_for_hba_ready 1196 * Wait till the HBA is ready before doing driver unload 1197 * 1198 * Input: 1199 * ha - pointer to host adapter structure 1200 * 1201 * Note: 1202 * Does context switching-Release SPIN_LOCK 1203 * (if any) before calling this routine. 1204 * 1205 */ 1206 static void 1207 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1208 { 1209 struct qla_hw_data *ha = vha->hw; 1210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1211 1212 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1213 ha->flags.mbox_busy) || 1214 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1215 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1216 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1217 break; 1218 msleep(1000); 1219 } 1220 } 1221 1222 int 1223 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1224 { 1225 int return_status; 1226 unsigned long wait_reset; 1227 struct qla_hw_data *ha = vha->hw; 1228 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1229 1230 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1231 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1232 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1233 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1234 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1235 1236 msleep(1000); 1237 1238 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1239 ha->flags.chip_reset_done) 1240 break; 1241 } 1242 if (ha->flags.chip_reset_done) 1243 return_status = QLA_SUCCESS; 1244 else 1245 return_status = QLA_FUNCTION_FAILED; 1246 1247 return return_status; 1248 } 1249 1250 /************************************************************************** 1251 * qla2xxx_eh_abort 1252 * 1253 * Description: 1254 * The abort function will abort the specified command. 1255 * 1256 * Input: 1257 * cmd = Linux SCSI command packet to be aborted. 1258 * 1259 * Returns: 1260 * Either SUCCESS or FAILED. 1261 * 1262 * Note: 1263 * Only return FAILED if command not returned by firmware. 1264 **************************************************************************/ 1265 static int 1266 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1267 { 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1269 DECLARE_COMPLETION_ONSTACK(comp); 1270 srb_t *sp; 1271 int ret; 1272 unsigned int id; 1273 uint64_t lun; 1274 int rval; 1275 struct qla_hw_data *ha = vha->hw; 1276 uint32_t ratov_j; 1277 struct qla_qpair *qpair; 1278 unsigned long flags; 1279 int fast_fail_status = SUCCESS; 1280 1281 if (qla2x00_isp_reg_stat(ha)) { 1282 ql_log(ql_log_info, vha, 0x8042, 1283 "PCI/Register disconnect, exiting.\n"); 1284 qla_pci_set_eeh_busy(vha); 1285 return FAILED; 1286 } 1287 1288 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1289 ret = fc_block_scsi_eh(cmd); 1290 if (ret != 0) 1291 fast_fail_status = ret; 1292 1293 sp = scsi_cmd_priv(cmd); 1294 qpair = sp->qpair; 1295 1296 vha->cmd_timeout_cnt++; 1297 1298 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1299 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1300 1301 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1302 sp->comp = ∁ 1303 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1304 1305 1306 id = cmd->device->id; 1307 lun = cmd->device->lun; 1308 1309 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1310 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1311 vha->host_no, id, lun, sp, cmd, sp->handle); 1312 1313 /* 1314 * Abort will release the original Command/sp from FW. Let the 1315 * original command call scsi_done. In return, he will wakeup 1316 * this sleeping thread. 1317 */ 1318 rval = ha->isp_ops->abort_command(sp); 1319 1320 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1321 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1322 1323 /* Wait for the command completion. */ 1324 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1325 ratov_j = msecs_to_jiffies(ratov_j); 1326 switch (rval) { 1327 case QLA_SUCCESS: 1328 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1329 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1330 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1331 __func__, ha->r_a_tov/10); 1332 ret = FAILED; 1333 } else { 1334 ret = fast_fail_status; 1335 } 1336 break; 1337 default: 1338 ret = FAILED; 1339 break; 1340 } 1341 1342 sp->comp = NULL; 1343 1344 ql_log(ql_log_info, vha, 0x801c, 1345 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1346 vha->host_no, id, lun, ret); 1347 1348 return ret; 1349 } 1350 1351 /* 1352 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1353 */ 1354 static int 1355 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1356 uint64_t l, enum nexus_wait_type type) 1357 { 1358 int cnt, match, status; 1359 unsigned long flags; 1360 scsi_qla_host_t *vha = qpair->vha; 1361 struct req_que *req = qpair->req; 1362 srb_t *sp; 1363 struct scsi_cmnd *cmd; 1364 1365 status = QLA_SUCCESS; 1366 1367 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1368 for (cnt = 1; status == QLA_SUCCESS && 1369 cnt < req->num_outstanding_cmds; cnt++) { 1370 sp = req->outstanding_cmds[cnt]; 1371 if (!sp) 1372 continue; 1373 if (sp->type != SRB_SCSI_CMD) 1374 continue; 1375 if (vha->vp_idx != sp->vha->vp_idx) 1376 continue; 1377 match = 0; 1378 cmd = GET_CMD_SP(sp); 1379 switch (type) { 1380 case WAIT_HOST: 1381 match = 1; 1382 break; 1383 case WAIT_TARGET: 1384 match = cmd->device->id == t; 1385 break; 1386 case WAIT_LUN: 1387 match = (cmd->device->id == t && 1388 cmd->device->lun == l); 1389 break; 1390 } 1391 if (!match) 1392 continue; 1393 1394 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1395 status = qla2x00_eh_wait_on_command(cmd); 1396 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1397 } 1398 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1399 1400 return status; 1401 } 1402 1403 int 1404 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1405 uint64_t l, enum nexus_wait_type type) 1406 { 1407 struct qla_qpair *qpair; 1408 struct qla_hw_data *ha = vha->hw; 1409 int i, status = QLA_SUCCESS; 1410 1411 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1412 type); 1413 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1414 qpair = ha->queue_pair_map[i]; 1415 if (!qpair) 1416 continue; 1417 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1418 type); 1419 } 1420 return status; 1421 } 1422 1423 static char *reset_errors[] = { 1424 "HBA not online", 1425 "HBA not ready", 1426 "Task management failed", 1427 "Waiting for command completions", 1428 }; 1429 1430 static int 1431 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1432 { 1433 struct scsi_device *sdev = cmd->device; 1434 scsi_qla_host_t *vha = shost_priv(sdev->host); 1435 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1436 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1437 struct qla_hw_data *ha = vha->hw; 1438 int err; 1439 1440 if (qla2x00_isp_reg_stat(ha)) { 1441 ql_log(ql_log_info, vha, 0x803e, 1442 "PCI/Register disconnect, exiting.\n"); 1443 qla_pci_set_eeh_busy(vha); 1444 return FAILED; 1445 } 1446 1447 if (!fcport) { 1448 return FAILED; 1449 } 1450 1451 err = fc_block_rport(rport); 1452 if (err != 0) 1453 return err; 1454 1455 if (fcport->deleted) 1456 return FAILED; 1457 1458 ql_log(ql_log_info, vha, 0x8009, 1459 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1460 sdev->id, sdev->lun, cmd); 1461 1462 err = 0; 1463 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1464 ql_log(ql_log_warn, vha, 0x800a, 1465 "Wait for hba online failed for cmd=%p.\n", cmd); 1466 goto eh_reset_failed; 1467 } 1468 err = 2; 1469 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1470 != QLA_SUCCESS) { 1471 ql_log(ql_log_warn, vha, 0x800c, 1472 "do_reset failed for cmd=%p.\n", cmd); 1473 goto eh_reset_failed; 1474 } 1475 err = 3; 1476 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1477 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1478 ql_log(ql_log_warn, vha, 0x800d, 1479 "wait for pending cmds failed for cmd=%p.\n", cmd); 1480 goto eh_reset_failed; 1481 } 1482 1483 ql_log(ql_log_info, vha, 0x800e, 1484 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1485 vha->host_no, sdev->id, sdev->lun, cmd); 1486 1487 return SUCCESS; 1488 1489 eh_reset_failed: 1490 ql_log(ql_log_info, vha, 0x800f, 1491 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1492 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1493 cmd); 1494 vha->reset_cmd_err_cnt++; 1495 return FAILED; 1496 } 1497 1498 static int 1499 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1500 { 1501 struct scsi_device *sdev = cmd->device; 1502 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1503 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1504 struct qla_hw_data *ha = vha->hw; 1505 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1506 int err; 1507 1508 if (qla2x00_isp_reg_stat(ha)) { 1509 ql_log(ql_log_info, vha, 0x803f, 1510 "PCI/Register disconnect, exiting.\n"); 1511 qla_pci_set_eeh_busy(vha); 1512 return FAILED; 1513 } 1514 1515 if (!fcport) { 1516 return FAILED; 1517 } 1518 1519 err = fc_block_rport(rport); 1520 if (err != 0) 1521 return err; 1522 1523 if (fcport->deleted) 1524 return FAILED; 1525 1526 ql_log(ql_log_info, vha, 0x8009, 1527 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1528 sdev->id, cmd); 1529 1530 err = 0; 1531 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1532 ql_log(ql_log_warn, vha, 0x800a, 1533 "Wait for hba online failed for cmd=%p.\n", cmd); 1534 goto eh_reset_failed; 1535 } 1536 err = 2; 1537 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1538 ql_log(ql_log_warn, vha, 0x800c, 1539 "target_reset failed for cmd=%p.\n", cmd); 1540 goto eh_reset_failed; 1541 } 1542 err = 3; 1543 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1544 0, WAIT_TARGET) != QLA_SUCCESS) { 1545 ql_log(ql_log_warn, vha, 0x800d, 1546 "wait for pending cmds failed for cmd=%p.\n", cmd); 1547 goto eh_reset_failed; 1548 } 1549 1550 ql_log(ql_log_info, vha, 0x800e, 1551 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1552 vha->host_no, sdev->id, cmd); 1553 1554 return SUCCESS; 1555 1556 eh_reset_failed: 1557 ql_log(ql_log_info, vha, 0x800f, 1558 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1559 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1560 cmd); 1561 vha->reset_cmd_err_cnt++; 1562 return FAILED; 1563 } 1564 1565 /************************************************************************** 1566 * qla2xxx_eh_bus_reset 1567 * 1568 * Description: 1569 * The bus reset function will reset the bus and abort any executing 1570 * commands. 1571 * 1572 * Input: 1573 * cmd = Linux SCSI command packet of the command that cause the 1574 * bus reset. 1575 * 1576 * Returns: 1577 * SUCCESS/FAILURE (defined as macro in scsi.h). 1578 * 1579 **************************************************************************/ 1580 static int 1581 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1582 { 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1584 int ret = FAILED; 1585 unsigned int id; 1586 uint64_t lun; 1587 struct qla_hw_data *ha = vha->hw; 1588 1589 if (qla2x00_isp_reg_stat(ha)) { 1590 ql_log(ql_log_info, vha, 0x8040, 1591 "PCI/Register disconnect, exiting.\n"); 1592 qla_pci_set_eeh_busy(vha); 1593 return FAILED; 1594 } 1595 1596 id = cmd->device->id; 1597 lun = cmd->device->lun; 1598 1599 if (qla2x00_chip_is_down(vha)) 1600 return ret; 1601 1602 ql_log(ql_log_info, vha, 0x8012, 1603 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1604 1605 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1606 ql_log(ql_log_fatal, vha, 0x8013, 1607 "Wait for hba online failed board disabled.\n"); 1608 goto eh_bus_reset_done; 1609 } 1610 1611 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1612 ret = SUCCESS; 1613 1614 if (ret == FAILED) 1615 goto eh_bus_reset_done; 1616 1617 /* Flush outstanding commands. */ 1618 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1619 QLA_SUCCESS) { 1620 ql_log(ql_log_warn, vha, 0x8014, 1621 "Wait for pending commands failed.\n"); 1622 ret = FAILED; 1623 } 1624 1625 eh_bus_reset_done: 1626 ql_log(ql_log_warn, vha, 0x802b, 1627 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1628 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1629 1630 return ret; 1631 } 1632 1633 /************************************************************************** 1634 * qla2xxx_eh_host_reset 1635 * 1636 * Description: 1637 * The reset function will reset the Adapter. 1638 * 1639 * Input: 1640 * cmd = Linux SCSI command packet of the command that cause the 1641 * adapter reset. 1642 * 1643 * Returns: 1644 * Either SUCCESS or FAILED. 1645 * 1646 * Note: 1647 **************************************************************************/ 1648 static int 1649 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1650 { 1651 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1652 struct qla_hw_data *ha = vha->hw; 1653 int ret = FAILED; 1654 unsigned int id; 1655 uint64_t lun; 1656 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1657 1658 if (qla2x00_isp_reg_stat(ha)) { 1659 ql_log(ql_log_info, vha, 0x8041, 1660 "PCI/Register disconnect, exiting.\n"); 1661 qla_pci_set_eeh_busy(vha); 1662 return SUCCESS; 1663 } 1664 1665 id = cmd->device->id; 1666 lun = cmd->device->lun; 1667 1668 ql_log(ql_log_info, vha, 0x8018, 1669 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1670 1671 /* 1672 * No point in issuing another reset if one is active. Also do not 1673 * attempt a reset if we are updating flash. 1674 */ 1675 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1676 goto eh_host_reset_lock; 1677 1678 if (vha != base_vha) { 1679 if (qla2x00_vp_abort_isp(vha)) 1680 goto eh_host_reset_lock; 1681 } else { 1682 if (IS_P3P_TYPE(vha->hw)) { 1683 if (!qla82xx_fcoe_ctx_reset(vha)) { 1684 /* Ctx reset success */ 1685 ret = SUCCESS; 1686 goto eh_host_reset_lock; 1687 } 1688 /* fall thru if ctx reset failed */ 1689 } 1690 if (ha->wq) 1691 flush_workqueue(ha->wq); 1692 1693 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1694 if (ha->isp_ops->abort_isp(base_vha)) { 1695 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1696 /* failed. schedule dpc to try */ 1697 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1698 1699 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1700 ql_log(ql_log_warn, vha, 0x802a, 1701 "wait for hba online failed.\n"); 1702 goto eh_host_reset_lock; 1703 } 1704 } 1705 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1706 } 1707 1708 /* Waiting for command to be returned to OS.*/ 1709 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1710 QLA_SUCCESS) 1711 ret = SUCCESS; 1712 1713 eh_host_reset_lock: 1714 ql_log(ql_log_info, vha, 0x8017, 1715 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1716 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1717 1718 return ret; 1719 } 1720 1721 /* 1722 * qla2x00_loop_reset 1723 * Issue loop reset. 1724 * 1725 * Input: 1726 * ha = adapter block pointer. 1727 * 1728 * Returns: 1729 * 0 = success 1730 */ 1731 int 1732 qla2x00_loop_reset(scsi_qla_host_t *vha) 1733 { 1734 int ret; 1735 struct qla_hw_data *ha = vha->hw; 1736 1737 if (IS_QLAFX00(ha)) 1738 return QLA_SUCCESS; 1739 1740 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1741 atomic_set(&vha->loop_state, LOOP_DOWN); 1742 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1743 qla2x00_mark_all_devices_lost(vha); 1744 ret = qla2x00_full_login_lip(vha); 1745 if (ret != QLA_SUCCESS) { 1746 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1747 "full_login_lip=%d.\n", ret); 1748 } 1749 } 1750 1751 if (ha->flags.enable_lip_reset) { 1752 ret = qla2x00_lip_reset(vha); 1753 if (ret != QLA_SUCCESS) 1754 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1755 "lip_reset failed (%d).\n", ret); 1756 } 1757 1758 /* Issue marker command only when we are going to start the I/O */ 1759 vha->marker_needed = 1; 1760 1761 return QLA_SUCCESS; 1762 } 1763 1764 /* 1765 * The caller must ensure that no completion interrupts will happen 1766 * while this function is in progress. 1767 */ 1768 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1769 unsigned long *flags) 1770 __releases(qp->qp_lock_ptr) 1771 __acquires(qp->qp_lock_ptr) 1772 { 1773 DECLARE_COMPLETION_ONSTACK(comp); 1774 scsi_qla_host_t *vha = qp->vha; 1775 struct qla_hw_data *ha = vha->hw; 1776 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1777 int rval; 1778 bool ret_cmd; 1779 uint32_t ratov_j; 1780 1781 lockdep_assert_held(qp->qp_lock_ptr); 1782 1783 if (qla2x00_chip_is_down(vha)) { 1784 sp->done(sp, res); 1785 return; 1786 } 1787 1788 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1789 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1790 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1791 !qla2x00_isp_reg_stat(ha))) { 1792 if (sp->comp) { 1793 sp->done(sp, res); 1794 return; 1795 } 1796 1797 sp->comp = ∁ 1798 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1799 1800 rval = ha->isp_ops->abort_command(sp); 1801 /* Wait for command completion. */ 1802 ret_cmd = false; 1803 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1804 ratov_j = msecs_to_jiffies(ratov_j); 1805 switch (rval) { 1806 case QLA_SUCCESS: 1807 if (wait_for_completion_timeout(&comp, ratov_j)) { 1808 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1809 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1810 __func__, ha->r_a_tov/10); 1811 ret_cmd = true; 1812 } 1813 /* else FW return SP to driver */ 1814 break; 1815 default: 1816 ret_cmd = true; 1817 break; 1818 } 1819 1820 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1821 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1822 sp->done(sp, res); 1823 } else { 1824 sp->done(sp, res); 1825 } 1826 } 1827 1828 /* 1829 * The caller must ensure that no completion interrupts will happen 1830 * while this function is in progress. 1831 */ 1832 static void 1833 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1834 { 1835 int cnt; 1836 unsigned long flags; 1837 srb_t *sp; 1838 scsi_qla_host_t *vha = qp->vha; 1839 struct qla_hw_data *ha = vha->hw; 1840 struct req_que *req; 1841 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1842 struct qla_tgt_cmd *cmd; 1843 1844 if (!ha->req_q_map) 1845 return; 1846 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1847 req = qp->req; 1848 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1849 sp = req->outstanding_cmds[cnt]; 1850 if (sp) { 1851 switch (sp->cmd_type) { 1852 case TYPE_SRB: 1853 qla2x00_abort_srb(qp, sp, res, &flags); 1854 break; 1855 case TYPE_TGT_CMD: 1856 if (!vha->hw->tgt.tgt_ops || !tgt || 1857 qla_ini_mode_enabled(vha)) { 1858 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1859 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1860 vha->dpc_flags); 1861 continue; 1862 } 1863 cmd = (struct qla_tgt_cmd *)sp; 1864 cmd->aborted = 1; 1865 break; 1866 case TYPE_TGT_TMCMD: 1867 /* Skip task management functions. */ 1868 break; 1869 default: 1870 break; 1871 } 1872 req->outstanding_cmds[cnt] = NULL; 1873 } 1874 } 1875 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1876 } 1877 1878 /* 1879 * The caller must ensure that no completion interrupts will happen 1880 * while this function is in progress. 1881 */ 1882 void 1883 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1884 { 1885 int que; 1886 struct qla_hw_data *ha = vha->hw; 1887 1888 /* Continue only if initialization complete. */ 1889 if (!ha->base_qpair) 1890 return; 1891 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1892 1893 if (!ha->queue_pair_map) 1894 return; 1895 for (que = 0; que < ha->max_qpairs; que++) { 1896 if (!ha->queue_pair_map[que]) 1897 continue; 1898 1899 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1900 } 1901 } 1902 1903 static int 1904 qla2xxx_slave_alloc(struct scsi_device *sdev) 1905 { 1906 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1907 1908 if (!rport || fc_remote_port_chkready(rport)) 1909 return -ENXIO; 1910 1911 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1912 1913 return 0; 1914 } 1915 1916 static int 1917 qla2xxx_slave_configure(struct scsi_device *sdev) 1918 { 1919 scsi_qla_host_t *vha = shost_priv(sdev->host); 1920 struct req_que *req = vha->req; 1921 1922 if (IS_T10_PI_CAPABLE(vha->hw)) 1923 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1924 1925 scsi_change_queue_depth(sdev, req->max_q_depth); 1926 return 0; 1927 } 1928 1929 static void 1930 qla2xxx_slave_destroy(struct scsi_device *sdev) 1931 { 1932 sdev->hostdata = NULL; 1933 } 1934 1935 /** 1936 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1937 * @ha: HA context 1938 * 1939 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1940 * supported addressing method. 1941 */ 1942 static void 1943 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1944 { 1945 /* Assume a 32bit DMA mask. */ 1946 ha->flags.enable_64bit_addressing = 0; 1947 1948 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1949 /* Any upper-dword bits set? */ 1950 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1951 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1952 /* Ok, a 64bit DMA mask is applicable. */ 1953 ha->flags.enable_64bit_addressing = 1; 1954 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1955 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1956 return; 1957 } 1958 } 1959 1960 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1961 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1962 } 1963 1964 static void 1965 qla2x00_enable_intrs(struct qla_hw_data *ha) 1966 { 1967 unsigned long flags = 0; 1968 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1969 1970 spin_lock_irqsave(&ha->hardware_lock, flags); 1971 ha->interrupts_on = 1; 1972 /* enable risc and host interrupts */ 1973 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1974 rd_reg_word(®->ictrl); 1975 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1976 1977 } 1978 1979 static void 1980 qla2x00_disable_intrs(struct qla_hw_data *ha) 1981 { 1982 unsigned long flags = 0; 1983 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1984 1985 spin_lock_irqsave(&ha->hardware_lock, flags); 1986 ha->interrupts_on = 0; 1987 /* disable risc and host interrupts */ 1988 wrt_reg_word(®->ictrl, 0); 1989 rd_reg_word(®->ictrl); 1990 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1991 } 1992 1993 static void 1994 qla24xx_enable_intrs(struct qla_hw_data *ha) 1995 { 1996 unsigned long flags = 0; 1997 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1998 1999 spin_lock_irqsave(&ha->hardware_lock, flags); 2000 ha->interrupts_on = 1; 2001 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2002 rd_reg_dword(®->ictrl); 2003 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2004 } 2005 2006 static void 2007 qla24xx_disable_intrs(struct qla_hw_data *ha) 2008 { 2009 unsigned long flags = 0; 2010 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2011 2012 if (IS_NOPOLLING_TYPE(ha)) 2013 return; 2014 spin_lock_irqsave(&ha->hardware_lock, flags); 2015 ha->interrupts_on = 0; 2016 wrt_reg_dword(®->ictrl, 0); 2017 rd_reg_dword(®->ictrl); 2018 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2019 } 2020 2021 static int 2022 qla2x00_iospace_config(struct qla_hw_data *ha) 2023 { 2024 resource_size_t pio; 2025 uint16_t msix; 2026 2027 if (pci_request_selected_regions(ha->pdev, ha->bars, 2028 QLA2XXX_DRIVER_NAME)) { 2029 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2030 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2031 pci_name(ha->pdev)); 2032 goto iospace_error_exit; 2033 } 2034 if (!(ha->bars & 1)) 2035 goto skip_pio; 2036 2037 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2038 pio = pci_resource_start(ha->pdev, 0); 2039 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2040 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2041 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2042 "Invalid pci I/O region size (%s).\n", 2043 pci_name(ha->pdev)); 2044 pio = 0; 2045 } 2046 } else { 2047 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2048 "Region #0 no a PIO resource (%s).\n", 2049 pci_name(ha->pdev)); 2050 pio = 0; 2051 } 2052 ha->pio_address = pio; 2053 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2054 "PIO address=%llu.\n", 2055 (unsigned long long)ha->pio_address); 2056 2057 skip_pio: 2058 /* Use MMIO operations for all accesses. */ 2059 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2061 "Region #1 not an MMIO resource (%s), aborting.\n", 2062 pci_name(ha->pdev)); 2063 goto iospace_error_exit; 2064 } 2065 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2066 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2067 "Invalid PCI mem region size (%s), aborting.\n", 2068 pci_name(ha->pdev)); 2069 goto iospace_error_exit; 2070 } 2071 2072 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2073 if (!ha->iobase) { 2074 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2075 "Cannot remap MMIO (%s), aborting.\n", 2076 pci_name(ha->pdev)); 2077 goto iospace_error_exit; 2078 } 2079 2080 /* Determine queue resources */ 2081 ha->max_req_queues = ha->max_rsp_queues = 1; 2082 ha->msix_count = QLA_BASE_VECTORS; 2083 2084 /* Check if FW supports MQ or not */ 2085 if (!(ha->fw_attributes & BIT_6)) 2086 goto mqiobase_exit; 2087 2088 if (!ql2xmqsupport || !ql2xnvmeenable || 2089 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2090 goto mqiobase_exit; 2091 2092 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2093 pci_resource_len(ha->pdev, 3)); 2094 if (ha->mqiobase) { 2095 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2096 "MQIO Base=%p.\n", ha->mqiobase); 2097 /* Read MSIX vector size of the board */ 2098 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2099 ha->msix_count = msix + 1; 2100 /* Max queues are bounded by available msix vectors */ 2101 /* MB interrupt uses 1 vector */ 2102 ha->max_req_queues = ha->msix_count - 1; 2103 ha->max_rsp_queues = ha->max_req_queues; 2104 /* Queue pairs is the max value minus the base queue pair */ 2105 ha->max_qpairs = ha->max_rsp_queues - 1; 2106 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2107 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2108 2109 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2110 "MSI-X vector count: %d.\n", ha->msix_count); 2111 } else 2112 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2113 "BAR 3 not enabled.\n"); 2114 2115 mqiobase_exit: 2116 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2117 "MSIX Count: %d.\n", ha->msix_count); 2118 return (0); 2119 2120 iospace_error_exit: 2121 return (-ENOMEM); 2122 } 2123 2124 2125 static int 2126 qla83xx_iospace_config(struct qla_hw_data *ha) 2127 { 2128 uint16_t msix; 2129 2130 if (pci_request_selected_regions(ha->pdev, ha->bars, 2131 QLA2XXX_DRIVER_NAME)) { 2132 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2133 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2134 pci_name(ha->pdev)); 2135 2136 goto iospace_error_exit; 2137 } 2138 2139 /* Use MMIO operations for all accesses. */ 2140 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2141 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2142 "Invalid pci I/O region size (%s).\n", 2143 pci_name(ha->pdev)); 2144 goto iospace_error_exit; 2145 } 2146 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2147 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2148 "Invalid PCI mem region size (%s), aborting\n", 2149 pci_name(ha->pdev)); 2150 goto iospace_error_exit; 2151 } 2152 2153 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2154 if (!ha->iobase) { 2155 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2156 "Cannot remap MMIO (%s), aborting.\n", 2157 pci_name(ha->pdev)); 2158 goto iospace_error_exit; 2159 } 2160 2161 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2162 /* 83XX 26XX always use MQ type access for queues 2163 * - mbar 2, a.k.a region 4 */ 2164 ha->max_req_queues = ha->max_rsp_queues = 1; 2165 ha->msix_count = QLA_BASE_VECTORS; 2166 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2167 pci_resource_len(ha->pdev, 4)); 2168 2169 if (!ha->mqiobase) { 2170 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2171 "BAR2/region4 not enabled\n"); 2172 goto mqiobase_exit; 2173 } 2174 2175 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2176 pci_resource_len(ha->pdev, 2)); 2177 if (ha->msixbase) { 2178 /* Read MSIX vector size of the board */ 2179 pci_read_config_word(ha->pdev, 2180 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2181 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2182 /* 2183 * By default, driver uses at least two msix vectors 2184 * (default & rspq) 2185 */ 2186 if (ql2xmqsupport || ql2xnvmeenable) { 2187 /* MB interrupt uses 1 vector */ 2188 ha->max_req_queues = ha->msix_count - 1; 2189 2190 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2191 if (QLA_TGT_MODE_ENABLED()) 2192 ha->max_req_queues--; 2193 2194 ha->max_rsp_queues = ha->max_req_queues; 2195 2196 /* Queue pairs is the max value minus 2197 * the base queue pair */ 2198 ha->max_qpairs = ha->max_req_queues - 1; 2199 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2200 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2201 } 2202 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2203 "MSI-X vector count: %d.\n", ha->msix_count); 2204 } else 2205 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2206 "BAR 1 not enabled.\n"); 2207 2208 mqiobase_exit: 2209 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2210 "MSIX Count: %d.\n", ha->msix_count); 2211 return 0; 2212 2213 iospace_error_exit: 2214 return -ENOMEM; 2215 } 2216 2217 static struct isp_operations qla2100_isp_ops = { 2218 .pci_config = qla2100_pci_config, 2219 .reset_chip = qla2x00_reset_chip, 2220 .chip_diag = qla2x00_chip_diag, 2221 .config_rings = qla2x00_config_rings, 2222 .reset_adapter = qla2x00_reset_adapter, 2223 .nvram_config = qla2x00_nvram_config, 2224 .update_fw_options = qla2x00_update_fw_options, 2225 .load_risc = qla2x00_load_risc, 2226 .pci_info_str = qla2x00_pci_info_str, 2227 .fw_version_str = qla2x00_fw_version_str, 2228 .intr_handler = qla2100_intr_handler, 2229 .enable_intrs = qla2x00_enable_intrs, 2230 .disable_intrs = qla2x00_disable_intrs, 2231 .abort_command = qla2x00_abort_command, 2232 .target_reset = qla2x00_abort_target, 2233 .lun_reset = qla2x00_lun_reset, 2234 .fabric_login = qla2x00_login_fabric, 2235 .fabric_logout = qla2x00_fabric_logout, 2236 .calc_req_entries = qla2x00_calc_iocbs_32, 2237 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2238 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2239 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2240 .read_nvram = qla2x00_read_nvram_data, 2241 .write_nvram = qla2x00_write_nvram_data, 2242 .fw_dump = qla2100_fw_dump, 2243 .beacon_on = NULL, 2244 .beacon_off = NULL, 2245 .beacon_blink = NULL, 2246 .read_optrom = qla2x00_read_optrom_data, 2247 .write_optrom = qla2x00_write_optrom_data, 2248 .get_flash_version = qla2x00_get_flash_version, 2249 .start_scsi = qla2x00_start_scsi, 2250 .start_scsi_mq = NULL, 2251 .abort_isp = qla2x00_abort_isp, 2252 .iospace_config = qla2x00_iospace_config, 2253 .initialize_adapter = qla2x00_initialize_adapter, 2254 }; 2255 2256 static struct isp_operations qla2300_isp_ops = { 2257 .pci_config = qla2300_pci_config, 2258 .reset_chip = qla2x00_reset_chip, 2259 .chip_diag = qla2x00_chip_diag, 2260 .config_rings = qla2x00_config_rings, 2261 .reset_adapter = qla2x00_reset_adapter, 2262 .nvram_config = qla2x00_nvram_config, 2263 .update_fw_options = qla2x00_update_fw_options, 2264 .load_risc = qla2x00_load_risc, 2265 .pci_info_str = qla2x00_pci_info_str, 2266 .fw_version_str = qla2x00_fw_version_str, 2267 .intr_handler = qla2300_intr_handler, 2268 .enable_intrs = qla2x00_enable_intrs, 2269 .disable_intrs = qla2x00_disable_intrs, 2270 .abort_command = qla2x00_abort_command, 2271 .target_reset = qla2x00_abort_target, 2272 .lun_reset = qla2x00_lun_reset, 2273 .fabric_login = qla2x00_login_fabric, 2274 .fabric_logout = qla2x00_fabric_logout, 2275 .calc_req_entries = qla2x00_calc_iocbs_32, 2276 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2277 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2278 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2279 .read_nvram = qla2x00_read_nvram_data, 2280 .write_nvram = qla2x00_write_nvram_data, 2281 .fw_dump = qla2300_fw_dump, 2282 .beacon_on = qla2x00_beacon_on, 2283 .beacon_off = qla2x00_beacon_off, 2284 .beacon_blink = qla2x00_beacon_blink, 2285 .read_optrom = qla2x00_read_optrom_data, 2286 .write_optrom = qla2x00_write_optrom_data, 2287 .get_flash_version = qla2x00_get_flash_version, 2288 .start_scsi = qla2x00_start_scsi, 2289 .start_scsi_mq = NULL, 2290 .abort_isp = qla2x00_abort_isp, 2291 .iospace_config = qla2x00_iospace_config, 2292 .initialize_adapter = qla2x00_initialize_adapter, 2293 }; 2294 2295 static struct isp_operations qla24xx_isp_ops = { 2296 .pci_config = qla24xx_pci_config, 2297 .reset_chip = qla24xx_reset_chip, 2298 .chip_diag = qla24xx_chip_diag, 2299 .config_rings = qla24xx_config_rings, 2300 .reset_adapter = qla24xx_reset_adapter, 2301 .nvram_config = qla24xx_nvram_config, 2302 .update_fw_options = qla24xx_update_fw_options, 2303 .load_risc = qla24xx_load_risc, 2304 .pci_info_str = qla24xx_pci_info_str, 2305 .fw_version_str = qla24xx_fw_version_str, 2306 .intr_handler = qla24xx_intr_handler, 2307 .enable_intrs = qla24xx_enable_intrs, 2308 .disable_intrs = qla24xx_disable_intrs, 2309 .abort_command = qla24xx_abort_command, 2310 .target_reset = qla24xx_abort_target, 2311 .lun_reset = qla24xx_lun_reset, 2312 .fabric_login = qla24xx_login_fabric, 2313 .fabric_logout = qla24xx_fabric_logout, 2314 .calc_req_entries = NULL, 2315 .build_iocbs = NULL, 2316 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2317 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2318 .read_nvram = qla24xx_read_nvram_data, 2319 .write_nvram = qla24xx_write_nvram_data, 2320 .fw_dump = qla24xx_fw_dump, 2321 .beacon_on = qla24xx_beacon_on, 2322 .beacon_off = qla24xx_beacon_off, 2323 .beacon_blink = qla24xx_beacon_blink, 2324 .read_optrom = qla24xx_read_optrom_data, 2325 .write_optrom = qla24xx_write_optrom_data, 2326 .get_flash_version = qla24xx_get_flash_version, 2327 .start_scsi = qla24xx_start_scsi, 2328 .start_scsi_mq = NULL, 2329 .abort_isp = qla2x00_abort_isp, 2330 .iospace_config = qla2x00_iospace_config, 2331 .initialize_adapter = qla2x00_initialize_adapter, 2332 }; 2333 2334 static struct isp_operations qla25xx_isp_ops = { 2335 .pci_config = qla25xx_pci_config, 2336 .reset_chip = qla24xx_reset_chip, 2337 .chip_diag = qla24xx_chip_diag, 2338 .config_rings = qla24xx_config_rings, 2339 .reset_adapter = qla24xx_reset_adapter, 2340 .nvram_config = qla24xx_nvram_config, 2341 .update_fw_options = qla24xx_update_fw_options, 2342 .load_risc = qla24xx_load_risc, 2343 .pci_info_str = qla24xx_pci_info_str, 2344 .fw_version_str = qla24xx_fw_version_str, 2345 .intr_handler = qla24xx_intr_handler, 2346 .enable_intrs = qla24xx_enable_intrs, 2347 .disable_intrs = qla24xx_disable_intrs, 2348 .abort_command = qla24xx_abort_command, 2349 .target_reset = qla24xx_abort_target, 2350 .lun_reset = qla24xx_lun_reset, 2351 .fabric_login = qla24xx_login_fabric, 2352 .fabric_logout = qla24xx_fabric_logout, 2353 .calc_req_entries = NULL, 2354 .build_iocbs = NULL, 2355 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2356 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2357 .read_nvram = qla25xx_read_nvram_data, 2358 .write_nvram = qla25xx_write_nvram_data, 2359 .fw_dump = qla25xx_fw_dump, 2360 .beacon_on = qla24xx_beacon_on, 2361 .beacon_off = qla24xx_beacon_off, 2362 .beacon_blink = qla24xx_beacon_blink, 2363 .read_optrom = qla25xx_read_optrom_data, 2364 .write_optrom = qla24xx_write_optrom_data, 2365 .get_flash_version = qla24xx_get_flash_version, 2366 .start_scsi = qla24xx_dif_start_scsi, 2367 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2368 .abort_isp = qla2x00_abort_isp, 2369 .iospace_config = qla2x00_iospace_config, 2370 .initialize_adapter = qla2x00_initialize_adapter, 2371 }; 2372 2373 static struct isp_operations qla81xx_isp_ops = { 2374 .pci_config = qla25xx_pci_config, 2375 .reset_chip = qla24xx_reset_chip, 2376 .chip_diag = qla24xx_chip_diag, 2377 .config_rings = qla24xx_config_rings, 2378 .reset_adapter = qla24xx_reset_adapter, 2379 .nvram_config = qla81xx_nvram_config, 2380 .update_fw_options = qla24xx_update_fw_options, 2381 .load_risc = qla81xx_load_risc, 2382 .pci_info_str = qla24xx_pci_info_str, 2383 .fw_version_str = qla24xx_fw_version_str, 2384 .intr_handler = qla24xx_intr_handler, 2385 .enable_intrs = qla24xx_enable_intrs, 2386 .disable_intrs = qla24xx_disable_intrs, 2387 .abort_command = qla24xx_abort_command, 2388 .target_reset = qla24xx_abort_target, 2389 .lun_reset = qla24xx_lun_reset, 2390 .fabric_login = qla24xx_login_fabric, 2391 .fabric_logout = qla24xx_fabric_logout, 2392 .calc_req_entries = NULL, 2393 .build_iocbs = NULL, 2394 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2395 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2396 .read_nvram = NULL, 2397 .write_nvram = NULL, 2398 .fw_dump = qla81xx_fw_dump, 2399 .beacon_on = qla24xx_beacon_on, 2400 .beacon_off = qla24xx_beacon_off, 2401 .beacon_blink = qla83xx_beacon_blink, 2402 .read_optrom = qla25xx_read_optrom_data, 2403 .write_optrom = qla24xx_write_optrom_data, 2404 .get_flash_version = qla24xx_get_flash_version, 2405 .start_scsi = qla24xx_dif_start_scsi, 2406 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2407 .abort_isp = qla2x00_abort_isp, 2408 .iospace_config = qla2x00_iospace_config, 2409 .initialize_adapter = qla2x00_initialize_adapter, 2410 }; 2411 2412 static struct isp_operations qla82xx_isp_ops = { 2413 .pci_config = qla82xx_pci_config, 2414 .reset_chip = qla82xx_reset_chip, 2415 .chip_diag = qla24xx_chip_diag, 2416 .config_rings = qla82xx_config_rings, 2417 .reset_adapter = qla24xx_reset_adapter, 2418 .nvram_config = qla81xx_nvram_config, 2419 .update_fw_options = qla24xx_update_fw_options, 2420 .load_risc = qla82xx_load_risc, 2421 .pci_info_str = qla24xx_pci_info_str, 2422 .fw_version_str = qla24xx_fw_version_str, 2423 .intr_handler = qla82xx_intr_handler, 2424 .enable_intrs = qla82xx_enable_intrs, 2425 .disable_intrs = qla82xx_disable_intrs, 2426 .abort_command = qla24xx_abort_command, 2427 .target_reset = qla24xx_abort_target, 2428 .lun_reset = qla24xx_lun_reset, 2429 .fabric_login = qla24xx_login_fabric, 2430 .fabric_logout = qla24xx_fabric_logout, 2431 .calc_req_entries = NULL, 2432 .build_iocbs = NULL, 2433 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2434 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2435 .read_nvram = qla24xx_read_nvram_data, 2436 .write_nvram = qla24xx_write_nvram_data, 2437 .fw_dump = qla82xx_fw_dump, 2438 .beacon_on = qla82xx_beacon_on, 2439 .beacon_off = qla82xx_beacon_off, 2440 .beacon_blink = NULL, 2441 .read_optrom = qla82xx_read_optrom_data, 2442 .write_optrom = qla82xx_write_optrom_data, 2443 .get_flash_version = qla82xx_get_flash_version, 2444 .start_scsi = qla82xx_start_scsi, 2445 .start_scsi_mq = NULL, 2446 .abort_isp = qla82xx_abort_isp, 2447 .iospace_config = qla82xx_iospace_config, 2448 .initialize_adapter = qla2x00_initialize_adapter, 2449 }; 2450 2451 static struct isp_operations qla8044_isp_ops = { 2452 .pci_config = qla82xx_pci_config, 2453 .reset_chip = qla82xx_reset_chip, 2454 .chip_diag = qla24xx_chip_diag, 2455 .config_rings = qla82xx_config_rings, 2456 .reset_adapter = qla24xx_reset_adapter, 2457 .nvram_config = qla81xx_nvram_config, 2458 .update_fw_options = qla24xx_update_fw_options, 2459 .load_risc = qla82xx_load_risc, 2460 .pci_info_str = qla24xx_pci_info_str, 2461 .fw_version_str = qla24xx_fw_version_str, 2462 .intr_handler = qla8044_intr_handler, 2463 .enable_intrs = qla82xx_enable_intrs, 2464 .disable_intrs = qla82xx_disable_intrs, 2465 .abort_command = qla24xx_abort_command, 2466 .target_reset = qla24xx_abort_target, 2467 .lun_reset = qla24xx_lun_reset, 2468 .fabric_login = qla24xx_login_fabric, 2469 .fabric_logout = qla24xx_fabric_logout, 2470 .calc_req_entries = NULL, 2471 .build_iocbs = NULL, 2472 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2473 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2474 .read_nvram = NULL, 2475 .write_nvram = NULL, 2476 .fw_dump = qla8044_fw_dump, 2477 .beacon_on = qla82xx_beacon_on, 2478 .beacon_off = qla82xx_beacon_off, 2479 .beacon_blink = NULL, 2480 .read_optrom = qla8044_read_optrom_data, 2481 .write_optrom = qla8044_write_optrom_data, 2482 .get_flash_version = qla82xx_get_flash_version, 2483 .start_scsi = qla82xx_start_scsi, 2484 .start_scsi_mq = NULL, 2485 .abort_isp = qla8044_abort_isp, 2486 .iospace_config = qla82xx_iospace_config, 2487 .initialize_adapter = qla2x00_initialize_adapter, 2488 }; 2489 2490 static struct isp_operations qla83xx_isp_ops = { 2491 .pci_config = qla25xx_pci_config, 2492 .reset_chip = qla24xx_reset_chip, 2493 .chip_diag = qla24xx_chip_diag, 2494 .config_rings = qla24xx_config_rings, 2495 .reset_adapter = qla24xx_reset_adapter, 2496 .nvram_config = qla81xx_nvram_config, 2497 .update_fw_options = qla24xx_update_fw_options, 2498 .load_risc = qla81xx_load_risc, 2499 .pci_info_str = qla24xx_pci_info_str, 2500 .fw_version_str = qla24xx_fw_version_str, 2501 .intr_handler = qla24xx_intr_handler, 2502 .enable_intrs = qla24xx_enable_intrs, 2503 .disable_intrs = qla24xx_disable_intrs, 2504 .abort_command = qla24xx_abort_command, 2505 .target_reset = qla24xx_abort_target, 2506 .lun_reset = qla24xx_lun_reset, 2507 .fabric_login = qla24xx_login_fabric, 2508 .fabric_logout = qla24xx_fabric_logout, 2509 .calc_req_entries = NULL, 2510 .build_iocbs = NULL, 2511 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2512 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2513 .read_nvram = NULL, 2514 .write_nvram = NULL, 2515 .fw_dump = qla83xx_fw_dump, 2516 .beacon_on = qla24xx_beacon_on, 2517 .beacon_off = qla24xx_beacon_off, 2518 .beacon_blink = qla83xx_beacon_blink, 2519 .read_optrom = qla25xx_read_optrom_data, 2520 .write_optrom = qla24xx_write_optrom_data, 2521 .get_flash_version = qla24xx_get_flash_version, 2522 .start_scsi = qla24xx_dif_start_scsi, 2523 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2524 .abort_isp = qla2x00_abort_isp, 2525 .iospace_config = qla83xx_iospace_config, 2526 .initialize_adapter = qla2x00_initialize_adapter, 2527 }; 2528 2529 static struct isp_operations qlafx00_isp_ops = { 2530 .pci_config = qlafx00_pci_config, 2531 .reset_chip = qlafx00_soft_reset, 2532 .chip_diag = qlafx00_chip_diag, 2533 .config_rings = qlafx00_config_rings, 2534 .reset_adapter = qlafx00_soft_reset, 2535 .nvram_config = NULL, 2536 .update_fw_options = NULL, 2537 .load_risc = NULL, 2538 .pci_info_str = qlafx00_pci_info_str, 2539 .fw_version_str = qlafx00_fw_version_str, 2540 .intr_handler = qlafx00_intr_handler, 2541 .enable_intrs = qlafx00_enable_intrs, 2542 .disable_intrs = qlafx00_disable_intrs, 2543 .abort_command = qla24xx_async_abort_command, 2544 .target_reset = qlafx00_abort_target, 2545 .lun_reset = qlafx00_lun_reset, 2546 .fabric_login = NULL, 2547 .fabric_logout = NULL, 2548 .calc_req_entries = NULL, 2549 .build_iocbs = NULL, 2550 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2551 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2552 .read_nvram = qla24xx_read_nvram_data, 2553 .write_nvram = qla24xx_write_nvram_data, 2554 .fw_dump = NULL, 2555 .beacon_on = qla24xx_beacon_on, 2556 .beacon_off = qla24xx_beacon_off, 2557 .beacon_blink = NULL, 2558 .read_optrom = qla24xx_read_optrom_data, 2559 .write_optrom = qla24xx_write_optrom_data, 2560 .get_flash_version = qla24xx_get_flash_version, 2561 .start_scsi = qlafx00_start_scsi, 2562 .start_scsi_mq = NULL, 2563 .abort_isp = qlafx00_abort_isp, 2564 .iospace_config = qlafx00_iospace_config, 2565 .initialize_adapter = qlafx00_initialize_adapter, 2566 }; 2567 2568 static struct isp_operations qla27xx_isp_ops = { 2569 .pci_config = qla25xx_pci_config, 2570 .reset_chip = qla24xx_reset_chip, 2571 .chip_diag = qla24xx_chip_diag, 2572 .config_rings = qla24xx_config_rings, 2573 .reset_adapter = qla24xx_reset_adapter, 2574 .nvram_config = qla81xx_nvram_config, 2575 .update_fw_options = qla24xx_update_fw_options, 2576 .load_risc = qla81xx_load_risc, 2577 .pci_info_str = qla24xx_pci_info_str, 2578 .fw_version_str = qla24xx_fw_version_str, 2579 .intr_handler = qla24xx_intr_handler, 2580 .enable_intrs = qla24xx_enable_intrs, 2581 .disable_intrs = qla24xx_disable_intrs, 2582 .abort_command = qla24xx_abort_command, 2583 .target_reset = qla24xx_abort_target, 2584 .lun_reset = qla24xx_lun_reset, 2585 .fabric_login = qla24xx_login_fabric, 2586 .fabric_logout = qla24xx_fabric_logout, 2587 .calc_req_entries = NULL, 2588 .build_iocbs = NULL, 2589 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2590 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2591 .read_nvram = NULL, 2592 .write_nvram = NULL, 2593 .fw_dump = qla27xx_fwdump, 2594 .mpi_fw_dump = qla27xx_mpi_fwdump, 2595 .beacon_on = qla24xx_beacon_on, 2596 .beacon_off = qla24xx_beacon_off, 2597 .beacon_blink = qla83xx_beacon_blink, 2598 .read_optrom = qla25xx_read_optrom_data, 2599 .write_optrom = qla24xx_write_optrom_data, 2600 .get_flash_version = qla24xx_get_flash_version, 2601 .start_scsi = qla24xx_dif_start_scsi, 2602 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2603 .abort_isp = qla2x00_abort_isp, 2604 .iospace_config = qla83xx_iospace_config, 2605 .initialize_adapter = qla2x00_initialize_adapter, 2606 }; 2607 2608 static inline void 2609 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2610 { 2611 ha->device_type = DT_EXTENDED_IDS; 2612 switch (ha->pdev->device) { 2613 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2614 ha->isp_type |= DT_ISP2100; 2615 ha->device_type &= ~DT_EXTENDED_IDS; 2616 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2617 break; 2618 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2619 ha->isp_type |= DT_ISP2200; 2620 ha->device_type &= ~DT_EXTENDED_IDS; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2622 break; 2623 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2624 ha->isp_type |= DT_ISP2300; 2625 ha->device_type |= DT_ZIO_SUPPORTED; 2626 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2627 break; 2628 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2629 ha->isp_type |= DT_ISP2312; 2630 ha->device_type |= DT_ZIO_SUPPORTED; 2631 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2632 break; 2633 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2634 ha->isp_type |= DT_ISP2322; 2635 ha->device_type |= DT_ZIO_SUPPORTED; 2636 if (ha->pdev->subsystem_vendor == 0x1028 && 2637 ha->pdev->subsystem_device == 0x0170) 2638 ha->device_type |= DT_OEM_001; 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2640 break; 2641 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2642 ha->isp_type |= DT_ISP6312; 2643 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2644 break; 2645 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2646 ha->isp_type |= DT_ISP6322; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2648 break; 2649 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2650 ha->isp_type |= DT_ISP2422; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->device_type |= DT_FWI2; 2653 ha->device_type |= DT_IIDMA; 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2655 break; 2656 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2657 ha->isp_type |= DT_ISP2432; 2658 ha->device_type |= DT_ZIO_SUPPORTED; 2659 ha->device_type |= DT_FWI2; 2660 ha->device_type |= DT_IIDMA; 2661 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2662 break; 2663 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2664 ha->isp_type |= DT_ISP8432; 2665 ha->device_type |= DT_ZIO_SUPPORTED; 2666 ha->device_type |= DT_FWI2; 2667 ha->device_type |= DT_IIDMA; 2668 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2669 break; 2670 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2671 ha->isp_type |= DT_ISP5422; 2672 ha->device_type |= DT_FWI2; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2674 break; 2675 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2676 ha->isp_type |= DT_ISP5432; 2677 ha->device_type |= DT_FWI2; 2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2679 break; 2680 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2681 ha->isp_type |= DT_ISP2532; 2682 ha->device_type |= DT_ZIO_SUPPORTED; 2683 ha->device_type |= DT_FWI2; 2684 ha->device_type |= DT_IIDMA; 2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2686 break; 2687 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2688 ha->isp_type |= DT_ISP8001; 2689 ha->device_type |= DT_ZIO_SUPPORTED; 2690 ha->device_type |= DT_FWI2; 2691 ha->device_type |= DT_IIDMA; 2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2693 break; 2694 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2695 ha->isp_type |= DT_ISP8021; 2696 ha->device_type |= DT_ZIO_SUPPORTED; 2697 ha->device_type |= DT_FWI2; 2698 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2699 /* Initialize 82XX ISP flags */ 2700 qla82xx_init_flags(ha); 2701 break; 2702 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2703 ha->isp_type |= DT_ISP8044; 2704 ha->device_type |= DT_ZIO_SUPPORTED; 2705 ha->device_type |= DT_FWI2; 2706 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2707 /* Initialize 82XX ISP flags */ 2708 qla82xx_init_flags(ha); 2709 break; 2710 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2711 ha->isp_type |= DT_ISP2031; 2712 ha->device_type |= DT_ZIO_SUPPORTED; 2713 ha->device_type |= DT_FWI2; 2714 ha->device_type |= DT_IIDMA; 2715 ha->device_type |= DT_T10_PI; 2716 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2717 break; 2718 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2719 ha->isp_type |= DT_ISP8031; 2720 ha->device_type |= DT_ZIO_SUPPORTED; 2721 ha->device_type |= DT_FWI2; 2722 ha->device_type |= DT_IIDMA; 2723 ha->device_type |= DT_T10_PI; 2724 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2725 break; 2726 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2727 ha->isp_type |= DT_ISPFX00; 2728 break; 2729 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2730 ha->isp_type |= DT_ISP2071; 2731 ha->device_type |= DT_ZIO_SUPPORTED; 2732 ha->device_type |= DT_FWI2; 2733 ha->device_type |= DT_IIDMA; 2734 ha->device_type |= DT_T10_PI; 2735 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2736 break; 2737 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2738 ha->isp_type |= DT_ISP2271; 2739 ha->device_type |= DT_ZIO_SUPPORTED; 2740 ha->device_type |= DT_FWI2; 2741 ha->device_type |= DT_IIDMA; 2742 ha->device_type |= DT_T10_PI; 2743 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2744 break; 2745 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2746 ha->isp_type |= DT_ISP2261; 2747 ha->device_type |= DT_ZIO_SUPPORTED; 2748 ha->device_type |= DT_FWI2; 2749 ha->device_type |= DT_IIDMA; 2750 ha->device_type |= DT_T10_PI; 2751 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2752 break; 2753 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2754 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2755 ha->isp_type |= DT_ISP2081; 2756 ha->device_type |= DT_ZIO_SUPPORTED; 2757 ha->device_type |= DT_FWI2; 2758 ha->device_type |= DT_IIDMA; 2759 ha->device_type |= DT_T10_PI; 2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2761 break; 2762 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2763 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2764 ha->isp_type |= DT_ISP2281; 2765 ha->device_type |= DT_ZIO_SUPPORTED; 2766 ha->device_type |= DT_FWI2; 2767 ha->device_type |= DT_IIDMA; 2768 ha->device_type |= DT_T10_PI; 2769 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2770 break; 2771 } 2772 2773 if (IS_QLA82XX(ha)) 2774 ha->port_no = ha->portnum & 1; 2775 else { 2776 /* Get adapter physical port no from interrupt pin register. */ 2777 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2778 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2779 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2780 ha->port_no--; 2781 else 2782 ha->port_no = !(ha->port_no & 1); 2783 } 2784 2785 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2786 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2787 ha->device_type, ha->port_no, ha->fw_srisc_address); 2788 } 2789 2790 static void 2791 qla2xxx_scan_start(struct Scsi_Host *shost) 2792 { 2793 scsi_qla_host_t *vha = shost_priv(shost); 2794 2795 if (vha->hw->flags.running_gold_fw) 2796 return; 2797 2798 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2799 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2800 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2801 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2802 } 2803 2804 static int 2805 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2806 { 2807 scsi_qla_host_t *vha = shost_priv(shost); 2808 2809 if (test_bit(UNLOADING, &vha->dpc_flags)) 2810 return 1; 2811 if (!vha->host) 2812 return 1; 2813 if (time > vha->hw->loop_reset_delay * HZ) 2814 return 1; 2815 2816 return atomic_read(&vha->loop_state) == LOOP_READY; 2817 } 2818 2819 static void qla_heartbeat_work_fn(struct work_struct *work) 2820 { 2821 struct qla_hw_data *ha = container_of(work, 2822 struct qla_hw_data, heartbeat_work); 2823 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2824 2825 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2826 qla_no_op_mb(base_vha); 2827 } 2828 2829 static void qla2x00_iocb_work_fn(struct work_struct *work) 2830 { 2831 struct scsi_qla_host *vha = container_of(work, 2832 struct scsi_qla_host, iocb_work); 2833 struct qla_hw_data *ha = vha->hw; 2834 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2835 int i = 2; 2836 unsigned long flags; 2837 2838 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2839 return; 2840 2841 while (!list_empty(&vha->work_list) && i > 0) { 2842 qla2x00_do_work(vha); 2843 i--; 2844 } 2845 2846 spin_lock_irqsave(&vha->work_lock, flags); 2847 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2848 spin_unlock_irqrestore(&vha->work_lock, flags); 2849 } 2850 2851 static void 2852 qla_trace_init(void) 2853 { 2854 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2855 if (!qla_trc_array) { 2856 ql_log(ql_log_fatal, NULL, 0x0001, 2857 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2858 return; 2859 } 2860 2861 QLA_TRACE_ENABLE(qla_trc_array); 2862 } 2863 2864 static void 2865 qla_trace_uninit(void) 2866 { 2867 if (!qla_trc_array) 2868 return; 2869 trace_array_put(qla_trc_array); 2870 } 2871 2872 /* 2873 * PCI driver interface 2874 */ 2875 static int 2876 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2877 { 2878 int ret = -ENODEV; 2879 struct Scsi_Host *host; 2880 scsi_qla_host_t *base_vha = NULL; 2881 struct qla_hw_data *ha; 2882 char pci_info[30]; 2883 char fw_str[30], wq_name[30]; 2884 struct scsi_host_template *sht; 2885 int bars, mem_only = 0; 2886 uint16_t req_length = 0, rsp_length = 0; 2887 struct req_que *req = NULL; 2888 struct rsp_que *rsp = NULL; 2889 int i; 2890 2891 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2892 sht = &qla2xxx_driver_template; 2893 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2894 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2895 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2896 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2897 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2898 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2899 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2900 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2901 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2902 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2903 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2904 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2905 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2906 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2907 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2908 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2909 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2910 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2911 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2912 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2913 mem_only = 1; 2914 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2915 "Mem only adapter.\n"); 2916 } 2917 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2918 "Bars=%d.\n", bars); 2919 2920 if (mem_only) { 2921 if (pci_enable_device_mem(pdev)) 2922 return ret; 2923 } else { 2924 if (pci_enable_device(pdev)) 2925 return ret; 2926 } 2927 2928 if (is_kdump_kernel()) { 2929 ql2xmqsupport = 0; 2930 ql2xallocfwdump = 0; 2931 } 2932 2933 /* This may fail but that's ok */ 2934 pci_enable_pcie_error_reporting(pdev); 2935 2936 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2937 if (!ha) { 2938 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2939 "Unable to allocate memory for ha.\n"); 2940 goto disable_device; 2941 } 2942 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2943 "Memory allocated for ha=%p.\n", ha); 2944 ha->pdev = pdev; 2945 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2946 spin_lock_init(&ha->tgt.q_full_lock); 2947 spin_lock_init(&ha->tgt.sess_lock); 2948 spin_lock_init(&ha->tgt.atio_lock); 2949 2950 spin_lock_init(&ha->sadb_lock); 2951 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2952 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2953 2954 spin_lock_init(&ha->sadb_fp_lock); 2955 2956 if (qla_edif_sadb_build_free_pool(ha)) { 2957 kfree(ha); 2958 goto disable_device; 2959 } 2960 2961 atomic_set(&ha->nvme_active_aen_cnt, 0); 2962 2963 /* Clear our data area */ 2964 ha->bars = bars; 2965 ha->mem_only = mem_only; 2966 spin_lock_init(&ha->hardware_lock); 2967 spin_lock_init(&ha->vport_slock); 2968 mutex_init(&ha->selflogin_lock); 2969 mutex_init(&ha->optrom_mutex); 2970 2971 /* Set ISP-type information. */ 2972 qla2x00_set_isp_flags(ha); 2973 2974 /* Set EEH reset type to fundamental if required by hba */ 2975 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2976 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2977 pdev->needs_freset = 1; 2978 2979 ha->prev_topology = 0; 2980 ha->init_cb_size = sizeof(init_cb_t); 2981 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2982 ha->optrom_size = OPTROM_SIZE_2300; 2983 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2984 atomic_set(&ha->num_pend_mbx_stage1, 0); 2985 atomic_set(&ha->num_pend_mbx_stage2, 0); 2986 atomic_set(&ha->num_pend_mbx_stage3, 0); 2987 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2988 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2989 2990 /* Assign ISP specific operations. */ 2991 if (IS_QLA2100(ha)) { 2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2993 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2994 req_length = REQUEST_ENTRY_CNT_2100; 2995 rsp_length = RESPONSE_ENTRY_CNT_2100; 2996 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2997 ha->gid_list_info_size = 4; 2998 ha->flash_conf_off = ~0; 2999 ha->flash_data_off = ~0; 3000 ha->nvram_conf_off = ~0; 3001 ha->nvram_data_off = ~0; 3002 ha->isp_ops = &qla2100_isp_ops; 3003 } else if (IS_QLA2200(ha)) { 3004 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3005 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3006 req_length = REQUEST_ENTRY_CNT_2200; 3007 rsp_length = RESPONSE_ENTRY_CNT_2100; 3008 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3009 ha->gid_list_info_size = 4; 3010 ha->flash_conf_off = ~0; 3011 ha->flash_data_off = ~0; 3012 ha->nvram_conf_off = ~0; 3013 ha->nvram_data_off = ~0; 3014 ha->isp_ops = &qla2100_isp_ops; 3015 } else if (IS_QLA23XX(ha)) { 3016 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3017 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3018 req_length = REQUEST_ENTRY_CNT_2200; 3019 rsp_length = RESPONSE_ENTRY_CNT_2300; 3020 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3021 ha->gid_list_info_size = 6; 3022 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3023 ha->optrom_size = OPTROM_SIZE_2322; 3024 ha->flash_conf_off = ~0; 3025 ha->flash_data_off = ~0; 3026 ha->nvram_conf_off = ~0; 3027 ha->nvram_data_off = ~0; 3028 ha->isp_ops = &qla2300_isp_ops; 3029 } else if (IS_QLA24XX_TYPE(ha)) { 3030 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3031 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3032 req_length = REQUEST_ENTRY_CNT_24XX; 3033 rsp_length = RESPONSE_ENTRY_CNT_2300; 3034 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3035 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3036 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3037 ha->gid_list_info_size = 8; 3038 ha->optrom_size = OPTROM_SIZE_24XX; 3039 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3040 ha->isp_ops = &qla24xx_isp_ops; 3041 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3042 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3043 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3044 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3045 } else if (IS_QLA25XX(ha)) { 3046 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3047 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3048 req_length = REQUEST_ENTRY_CNT_24XX; 3049 rsp_length = RESPONSE_ENTRY_CNT_2300; 3050 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3051 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3052 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3053 ha->gid_list_info_size = 8; 3054 ha->optrom_size = OPTROM_SIZE_25XX; 3055 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3056 ha->isp_ops = &qla25xx_isp_ops; 3057 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3058 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3059 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3060 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3061 } else if (IS_QLA81XX(ha)) { 3062 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3063 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3064 req_length = REQUEST_ENTRY_CNT_24XX; 3065 rsp_length = RESPONSE_ENTRY_CNT_2300; 3066 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3067 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3068 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3069 ha->gid_list_info_size = 8; 3070 ha->optrom_size = OPTROM_SIZE_81XX; 3071 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3072 ha->isp_ops = &qla81xx_isp_ops; 3073 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3074 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3075 ha->nvram_conf_off = ~0; 3076 ha->nvram_data_off = ~0; 3077 } else if (IS_QLA82XX(ha)) { 3078 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3079 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3080 req_length = REQUEST_ENTRY_CNT_82XX; 3081 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3082 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3083 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3084 ha->gid_list_info_size = 8; 3085 ha->optrom_size = OPTROM_SIZE_82XX; 3086 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3087 ha->isp_ops = &qla82xx_isp_ops; 3088 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3089 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3090 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3091 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3092 } else if (IS_QLA8044(ha)) { 3093 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3094 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3095 req_length = REQUEST_ENTRY_CNT_82XX; 3096 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3097 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3098 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3099 ha->gid_list_info_size = 8; 3100 ha->optrom_size = OPTROM_SIZE_83XX; 3101 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3102 ha->isp_ops = &qla8044_isp_ops; 3103 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3104 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3105 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3106 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3107 } else if (IS_QLA83XX(ha)) { 3108 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3109 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3110 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3111 req_length = REQUEST_ENTRY_CNT_83XX; 3112 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3113 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3114 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3115 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3116 ha->gid_list_info_size = 8; 3117 ha->optrom_size = OPTROM_SIZE_83XX; 3118 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3119 ha->isp_ops = &qla83xx_isp_ops; 3120 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3121 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3122 ha->nvram_conf_off = ~0; 3123 ha->nvram_data_off = ~0; 3124 } else if (IS_QLAFX00(ha)) { 3125 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3126 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3127 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3128 req_length = REQUEST_ENTRY_CNT_FX00; 3129 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3130 ha->isp_ops = &qlafx00_isp_ops; 3131 ha->port_down_retry_count = 30; /* default value */ 3132 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3133 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3134 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3135 ha->mr.fw_hbt_en = 1; 3136 ha->mr.host_info_resend = false; 3137 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3138 } else if (IS_QLA27XX(ha)) { 3139 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3140 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3141 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3142 req_length = REQUEST_ENTRY_CNT_83XX; 3143 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3144 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3145 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3146 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3147 ha->gid_list_info_size = 8; 3148 ha->optrom_size = OPTROM_SIZE_83XX; 3149 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3150 ha->isp_ops = &qla27xx_isp_ops; 3151 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3152 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3153 ha->nvram_conf_off = ~0; 3154 ha->nvram_data_off = ~0; 3155 } else if (IS_QLA28XX(ha)) { 3156 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3157 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3158 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3159 req_length = REQUEST_ENTRY_CNT_83XX; 3160 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3161 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3162 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3163 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3164 ha->gid_list_info_size = 8; 3165 ha->optrom_size = OPTROM_SIZE_28XX; 3166 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3167 ha->isp_ops = &qla27xx_isp_ops; 3168 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3169 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3170 ha->nvram_conf_off = ~0; 3171 ha->nvram_data_off = ~0; 3172 } 3173 3174 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3175 "mbx_count=%d, req_length=%d, " 3176 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3177 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3178 "max_fibre_devices=%d.\n", 3179 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3180 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3181 ha->nvram_npiv_size, ha->max_fibre_devices); 3182 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3183 "isp_ops=%p, flash_conf_off=%d, " 3184 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3185 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3186 ha->nvram_conf_off, ha->nvram_data_off); 3187 3188 /* Configure PCI I/O space */ 3189 ret = ha->isp_ops->iospace_config(ha); 3190 if (ret) 3191 goto iospace_config_failed; 3192 3193 ql_log_pci(ql_log_info, pdev, 0x001d, 3194 "Found an ISP%04X irq %d iobase 0x%p.\n", 3195 pdev->device, pdev->irq, ha->iobase); 3196 mutex_init(&ha->vport_lock); 3197 mutex_init(&ha->mq_lock); 3198 init_completion(&ha->mbx_cmd_comp); 3199 complete(&ha->mbx_cmd_comp); 3200 init_completion(&ha->mbx_intr_comp); 3201 init_completion(&ha->dcbx_comp); 3202 init_completion(&ha->lb_portup_comp); 3203 3204 set_bit(0, (unsigned long *) ha->vp_idx_map); 3205 3206 qla2x00_config_dma_addressing(ha); 3207 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3208 "64 Bit addressing is %s.\n", 3209 ha->flags.enable_64bit_addressing ? "enable" : 3210 "disable"); 3211 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3212 if (ret) { 3213 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3214 "Failed to allocate memory for adapter, aborting.\n"); 3215 3216 goto probe_hw_failed; 3217 } 3218 3219 req->max_q_depth = MAX_Q_DEPTH; 3220 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3221 req->max_q_depth = ql2xmaxqdepth; 3222 3223 3224 base_vha = qla2x00_create_host(sht, ha); 3225 if (!base_vha) { 3226 ret = -ENOMEM; 3227 goto probe_hw_failed; 3228 } 3229 3230 pci_set_drvdata(pdev, base_vha); 3231 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3232 3233 host = base_vha->host; 3234 base_vha->req = req; 3235 if (IS_QLA2XXX_MIDTYPE(ha)) 3236 base_vha->mgmt_svr_loop_id = 3237 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3238 else 3239 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3240 base_vha->vp_idx; 3241 3242 /* Setup fcport template structure. */ 3243 ha->mr.fcport.vha = base_vha; 3244 ha->mr.fcport.port_type = FCT_UNKNOWN; 3245 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3246 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3247 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3248 ha->mr.fcport.scan_state = 1; 3249 3250 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3251 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3252 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3253 3254 /* Set the SG table size based on ISP type */ 3255 if (!IS_FWI2_CAPABLE(ha)) { 3256 if (IS_QLA2100(ha)) 3257 host->sg_tablesize = 32; 3258 } else { 3259 if (!IS_QLA82XX(ha)) 3260 host->sg_tablesize = QLA_SG_ALL; 3261 } 3262 host->max_id = ha->max_fibre_devices; 3263 host->cmd_per_lun = 3; 3264 host->unique_id = host->host_no; 3265 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3266 host->max_cmd_len = 32; 3267 else 3268 host->max_cmd_len = MAX_CMDSZ; 3269 host->max_channel = MAX_BUSES - 1; 3270 /* Older HBAs support only 16-bit LUNs */ 3271 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3272 ql2xmaxlun > 0xffff) 3273 host->max_lun = 0xffff; 3274 else 3275 host->max_lun = ql2xmaxlun; 3276 host->transportt = qla2xxx_transport_template; 3277 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3278 3279 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3280 "max_id=%d this_id=%d " 3281 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3282 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3283 host->this_id, host->cmd_per_lun, host->unique_id, 3284 host->max_cmd_len, host->max_channel, host->max_lun, 3285 host->transportt, sht->vendor_id); 3286 3287 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3288 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3289 3290 /* Set up the irqs */ 3291 ret = qla2x00_request_irqs(ha, rsp); 3292 if (ret) 3293 goto probe_failed; 3294 3295 /* Alloc arrays of request and response ring ptrs */ 3296 ret = qla2x00_alloc_queues(ha, req, rsp); 3297 if (ret) { 3298 ql_log(ql_log_fatal, base_vha, 0x003d, 3299 "Failed to allocate memory for queue pointers..." 3300 "aborting.\n"); 3301 ret = -ENODEV; 3302 goto probe_failed; 3303 } 3304 3305 if (ha->mqenable) { 3306 /* number of hardware queues supported by blk/scsi-mq*/ 3307 host->nr_hw_queues = ha->max_qpairs; 3308 3309 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3310 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3311 } else { 3312 if (ql2xnvmeenable) { 3313 host->nr_hw_queues = ha->max_qpairs; 3314 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3315 "FC-NVMe support is enabled, HW queues=%d\n", 3316 host->nr_hw_queues); 3317 } else { 3318 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3319 "blk/scsi-mq disabled.\n"); 3320 } 3321 } 3322 3323 qlt_probe_one_stage1(base_vha, ha); 3324 3325 pci_save_state(pdev); 3326 3327 /* Assign back pointers */ 3328 rsp->req = req; 3329 req->rsp = rsp; 3330 3331 if (IS_QLAFX00(ha)) { 3332 ha->rsp_q_map[0] = rsp; 3333 ha->req_q_map[0] = req; 3334 set_bit(0, ha->req_qid_map); 3335 set_bit(0, ha->rsp_qid_map); 3336 } 3337 3338 /* FWI2-capable only. */ 3339 req->req_q_in = &ha->iobase->isp24.req_q_in; 3340 req->req_q_out = &ha->iobase->isp24.req_q_out; 3341 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3342 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3343 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3344 IS_QLA28XX(ha)) { 3345 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3346 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3347 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3348 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3349 } 3350 3351 if (IS_QLAFX00(ha)) { 3352 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3353 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3354 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3355 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3356 } 3357 3358 if (IS_P3P_TYPE(ha)) { 3359 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3360 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3361 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3362 } 3363 3364 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3365 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3366 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3367 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3368 "req->req_q_in=%p req->req_q_out=%p " 3369 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3370 req->req_q_in, req->req_q_out, 3371 rsp->rsp_q_in, rsp->rsp_q_out); 3372 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3373 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3374 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3375 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3376 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3377 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3378 3379 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3380 if (unlikely(!ha->wq)) { 3381 ret = -ENOMEM; 3382 goto probe_failed; 3383 } 3384 3385 if (ha->isp_ops->initialize_adapter(base_vha)) { 3386 ql_log(ql_log_fatal, base_vha, 0x00d6, 3387 "Failed to initialize adapter - Adapter flags %x.\n", 3388 base_vha->device_flags); 3389 3390 if (IS_QLA82XX(ha)) { 3391 qla82xx_idc_lock(ha); 3392 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3393 QLA8XXX_DEV_FAILED); 3394 qla82xx_idc_unlock(ha); 3395 ql_log(ql_log_fatal, base_vha, 0x00d7, 3396 "HW State: FAILED.\n"); 3397 } else if (IS_QLA8044(ha)) { 3398 qla8044_idc_lock(ha); 3399 qla8044_wr_direct(base_vha, 3400 QLA8044_CRB_DEV_STATE_INDEX, 3401 QLA8XXX_DEV_FAILED); 3402 qla8044_idc_unlock(ha); 3403 ql_log(ql_log_fatal, base_vha, 0x0150, 3404 "HW State: FAILED.\n"); 3405 } 3406 3407 ret = -ENODEV; 3408 goto probe_failed; 3409 } 3410 3411 if (IS_QLAFX00(ha)) 3412 host->can_queue = QLAFX00_MAX_CANQUEUE; 3413 else 3414 host->can_queue = req->num_outstanding_cmds - 10; 3415 3416 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3417 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3418 host->can_queue, base_vha->req, 3419 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3420 3421 /* Check if FW supports MQ or not for ISP25xx */ 3422 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3423 ha->mqenable = 0; 3424 3425 if (ha->mqenable) { 3426 bool startit = false; 3427 3428 if (QLA_TGT_MODE_ENABLED()) 3429 startit = false; 3430 3431 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3432 startit = true; 3433 3434 /* Create start of day qpairs for Block MQ */ 3435 for (i = 0; i < ha->max_qpairs; i++) 3436 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3437 } 3438 qla_init_iocb_limit(base_vha); 3439 3440 if (ha->flags.running_gold_fw) 3441 goto skip_dpc; 3442 3443 /* 3444 * Startup the kernel thread for this host adapter 3445 */ 3446 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3447 "%s_dpc", base_vha->host_str); 3448 if (IS_ERR(ha->dpc_thread)) { 3449 ql_log(ql_log_fatal, base_vha, 0x00ed, 3450 "Failed to start DPC thread.\n"); 3451 ret = PTR_ERR(ha->dpc_thread); 3452 ha->dpc_thread = NULL; 3453 goto probe_failed; 3454 } 3455 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3456 "DPC thread started successfully.\n"); 3457 3458 /* 3459 * If we're not coming up in initiator mode, we might sit for 3460 * a while without waking up the dpc thread, which leads to a 3461 * stuck process warning. So just kick the dpc once here and 3462 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3463 */ 3464 qla2xxx_wake_dpc(base_vha); 3465 3466 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3467 3468 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3469 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3470 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3471 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3472 3473 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3474 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3475 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3476 INIT_WORK(&ha->idc_state_handler, 3477 qla83xx_idc_state_handler_work); 3478 INIT_WORK(&ha->nic_core_unrecoverable, 3479 qla83xx_nic_core_unrecoverable_work); 3480 } 3481 3482 skip_dpc: 3483 list_add_tail(&base_vha->list, &ha->vp_list); 3484 base_vha->host->irq = ha->pdev->irq; 3485 3486 /* Initialized the timer */ 3487 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3488 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3489 "Started qla2x00_timer with " 3490 "interval=%d.\n", WATCH_INTERVAL); 3491 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3492 "Detected hba at address=%p.\n", 3493 ha); 3494 3495 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3496 if (ha->fw_attributes & BIT_4) { 3497 int prot = 0, guard; 3498 3499 base_vha->flags.difdix_supported = 1; 3500 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3501 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3502 if (ql2xenabledif == 1) 3503 prot = SHOST_DIX_TYPE0_PROTECTION; 3504 if (ql2xprotmask) 3505 scsi_host_set_prot(host, ql2xprotmask); 3506 else 3507 scsi_host_set_prot(host, 3508 prot | SHOST_DIF_TYPE1_PROTECTION 3509 | SHOST_DIF_TYPE2_PROTECTION 3510 | SHOST_DIF_TYPE3_PROTECTION 3511 | SHOST_DIX_TYPE1_PROTECTION 3512 | SHOST_DIX_TYPE2_PROTECTION 3513 | SHOST_DIX_TYPE3_PROTECTION); 3514 3515 guard = SHOST_DIX_GUARD_CRC; 3516 3517 if (IS_PI_IPGUARD_CAPABLE(ha) && 3518 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3519 guard |= SHOST_DIX_GUARD_IP; 3520 3521 if (ql2xprotguard) 3522 scsi_host_set_guard(host, ql2xprotguard); 3523 else 3524 scsi_host_set_guard(host, guard); 3525 } else 3526 base_vha->flags.difdix_supported = 0; 3527 } 3528 3529 ha->isp_ops->enable_intrs(ha); 3530 3531 if (IS_QLAFX00(ha)) { 3532 ret = qlafx00_fx_disc(base_vha, 3533 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3534 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3535 QLA_SG_ALL : 128; 3536 } 3537 3538 ret = scsi_add_host(host, &pdev->dev); 3539 if (ret) 3540 goto probe_failed; 3541 3542 base_vha->flags.init_done = 1; 3543 base_vha->flags.online = 1; 3544 ha->prev_minidump_failed = 0; 3545 3546 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3547 "Init done and hba is online.\n"); 3548 3549 if (qla_ini_mode_enabled(base_vha) || 3550 qla_dual_mode_enabled(base_vha)) 3551 scsi_scan_host(host); 3552 else 3553 ql_log(ql_log_info, base_vha, 0x0122, 3554 "skipping scsi_scan_host() for non-initiator port\n"); 3555 3556 qla2x00_alloc_sysfs_attr(base_vha); 3557 3558 if (IS_QLAFX00(ha)) { 3559 ret = qlafx00_fx_disc(base_vha, 3560 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3561 3562 /* Register system information */ 3563 ret = qlafx00_fx_disc(base_vha, 3564 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3565 } 3566 3567 qla2x00_init_host_attr(base_vha); 3568 3569 qla2x00_dfs_setup(base_vha); 3570 3571 ql_log(ql_log_info, base_vha, 0x00fb, 3572 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3573 ql_log(ql_log_info, base_vha, 0x00fc, 3574 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3575 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3576 sizeof(pci_info)), 3577 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3578 base_vha->host_no, 3579 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3580 3581 qlt_add_target(ha, base_vha); 3582 3583 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3584 3585 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3586 return -ENODEV; 3587 3588 return 0; 3589 3590 probe_failed: 3591 qla_enode_stop(base_vha); 3592 qla_edb_stop(base_vha); 3593 if (base_vha->gnl.l) { 3594 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3595 base_vha->gnl.l, base_vha->gnl.ldma); 3596 base_vha->gnl.l = NULL; 3597 } 3598 3599 if (base_vha->timer_active) 3600 qla2x00_stop_timer(base_vha); 3601 base_vha->flags.online = 0; 3602 if (ha->dpc_thread) { 3603 struct task_struct *t = ha->dpc_thread; 3604 3605 ha->dpc_thread = NULL; 3606 kthread_stop(t); 3607 } 3608 3609 qla2x00_free_device(base_vha); 3610 scsi_host_put(base_vha->host); 3611 /* 3612 * Need to NULL out local req/rsp after 3613 * qla2x00_free_device => qla2x00_free_queues frees 3614 * what these are pointing to. Or else we'll 3615 * fall over below in qla2x00_free_req/rsp_que. 3616 */ 3617 req = NULL; 3618 rsp = NULL; 3619 3620 probe_hw_failed: 3621 qla2x00_mem_free(ha); 3622 qla2x00_free_req_que(ha, req); 3623 qla2x00_free_rsp_que(ha, rsp); 3624 qla2x00_clear_drv_active(ha); 3625 3626 iospace_config_failed: 3627 if (IS_P3P_TYPE(ha)) { 3628 if (!ha->nx_pcibase) 3629 iounmap((device_reg_t *)ha->nx_pcibase); 3630 if (!ql2xdbwr) 3631 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3632 } else { 3633 if (ha->iobase) 3634 iounmap(ha->iobase); 3635 if (ha->cregbase) 3636 iounmap(ha->cregbase); 3637 } 3638 pci_release_selected_regions(ha->pdev, ha->bars); 3639 kfree(ha); 3640 3641 disable_device: 3642 pci_disable_device(pdev); 3643 return ret; 3644 } 3645 3646 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3647 { 3648 scsi_qla_host_t *vp; 3649 unsigned long flags; 3650 struct qla_hw_data *ha; 3651 3652 if (!base_vha) 3653 return; 3654 3655 ha = base_vha->hw; 3656 3657 spin_lock_irqsave(&ha->vport_slock, flags); 3658 list_for_each_entry(vp, &ha->vp_list, list) 3659 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3660 3661 /* 3662 * Indicate device removal to prevent future board_disable 3663 * and wait until any pending board_disable has completed. 3664 */ 3665 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3666 spin_unlock_irqrestore(&ha->vport_slock, flags); 3667 } 3668 3669 static void 3670 qla2x00_shutdown(struct pci_dev *pdev) 3671 { 3672 scsi_qla_host_t *vha; 3673 struct qla_hw_data *ha; 3674 3675 vha = pci_get_drvdata(pdev); 3676 ha = vha->hw; 3677 3678 ql_log(ql_log_info, vha, 0xfffa, 3679 "Adapter shutdown\n"); 3680 3681 /* 3682 * Prevent future board_disable and wait 3683 * until any pending board_disable has completed. 3684 */ 3685 __qla_set_remove_flag(vha); 3686 cancel_work_sync(&ha->board_disable); 3687 3688 if (!atomic_read(&pdev->enable_cnt)) 3689 return; 3690 3691 /* Notify ISPFX00 firmware */ 3692 if (IS_QLAFX00(ha)) 3693 qlafx00_driver_shutdown(vha, 20); 3694 3695 /* Turn-off FCE trace */ 3696 if (ha->flags.fce_enabled) { 3697 qla2x00_disable_fce_trace(vha, NULL, NULL); 3698 ha->flags.fce_enabled = 0; 3699 } 3700 3701 /* Turn-off EFT trace */ 3702 if (ha->eft) 3703 qla2x00_disable_eft_trace(vha); 3704 3705 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3706 IS_QLA28XX(ha)) { 3707 if (ha->flags.fw_started) 3708 qla2x00_abort_isp_cleanup(vha); 3709 } else { 3710 /* Stop currently executing firmware. */ 3711 qla2x00_try_to_stop_firmware(vha); 3712 } 3713 3714 /* Disable timer */ 3715 if (vha->timer_active) 3716 qla2x00_stop_timer(vha); 3717 3718 /* Turn adapter off line */ 3719 vha->flags.online = 0; 3720 3721 /* turn-off interrupts on the card */ 3722 if (ha->interrupts_on) { 3723 vha->flags.init_done = 0; 3724 ha->isp_ops->disable_intrs(ha); 3725 } 3726 3727 qla2x00_free_irqs(vha); 3728 3729 qla2x00_free_fw_dump(ha); 3730 3731 pci_disable_device(pdev); 3732 ql_log(ql_log_info, vha, 0xfffe, 3733 "Adapter shutdown successfully.\n"); 3734 } 3735 3736 /* Deletes all the virtual ports for a given ha */ 3737 static void 3738 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3739 { 3740 scsi_qla_host_t *vha; 3741 unsigned long flags; 3742 3743 mutex_lock(&ha->vport_lock); 3744 while (ha->cur_vport_count) { 3745 spin_lock_irqsave(&ha->vport_slock, flags); 3746 3747 BUG_ON(base_vha->list.next == &ha->vp_list); 3748 /* This assumes first entry in ha->vp_list is always base vha */ 3749 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3750 scsi_host_get(vha->host); 3751 3752 spin_unlock_irqrestore(&ha->vport_slock, flags); 3753 mutex_unlock(&ha->vport_lock); 3754 3755 qla_nvme_delete(vha); 3756 3757 fc_vport_terminate(vha->fc_vport); 3758 scsi_host_put(vha->host); 3759 3760 mutex_lock(&ha->vport_lock); 3761 } 3762 mutex_unlock(&ha->vport_lock); 3763 } 3764 3765 /* Stops all deferred work threads */ 3766 static void 3767 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3768 { 3769 /* Cancel all work and destroy DPC workqueues */ 3770 if (ha->dpc_lp_wq) { 3771 cancel_work_sync(&ha->idc_aen); 3772 destroy_workqueue(ha->dpc_lp_wq); 3773 ha->dpc_lp_wq = NULL; 3774 } 3775 3776 if (ha->dpc_hp_wq) { 3777 cancel_work_sync(&ha->nic_core_reset); 3778 cancel_work_sync(&ha->idc_state_handler); 3779 cancel_work_sync(&ha->nic_core_unrecoverable); 3780 destroy_workqueue(ha->dpc_hp_wq); 3781 ha->dpc_hp_wq = NULL; 3782 } 3783 3784 /* Kill the kernel thread for this host */ 3785 if (ha->dpc_thread) { 3786 struct task_struct *t = ha->dpc_thread; 3787 3788 /* 3789 * qla2xxx_wake_dpc checks for ->dpc_thread 3790 * so we need to zero it out. 3791 */ 3792 ha->dpc_thread = NULL; 3793 kthread_stop(t); 3794 } 3795 } 3796 3797 static void 3798 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3799 { 3800 if (IS_QLA82XX(ha)) { 3801 3802 iounmap((device_reg_t *)ha->nx_pcibase); 3803 if (!ql2xdbwr) 3804 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3805 } else { 3806 if (ha->iobase) 3807 iounmap(ha->iobase); 3808 3809 if (ha->cregbase) 3810 iounmap(ha->cregbase); 3811 3812 if (ha->mqiobase) 3813 iounmap(ha->mqiobase); 3814 3815 if (ha->msixbase) 3816 iounmap(ha->msixbase); 3817 } 3818 } 3819 3820 static void 3821 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3822 { 3823 if (IS_QLA8044(ha)) { 3824 qla8044_idc_lock(ha); 3825 qla8044_clear_drv_active(ha); 3826 qla8044_idc_unlock(ha); 3827 } else if (IS_QLA82XX(ha)) { 3828 qla82xx_idc_lock(ha); 3829 qla82xx_clear_drv_active(ha); 3830 qla82xx_idc_unlock(ha); 3831 } 3832 } 3833 3834 static void 3835 qla2x00_remove_one(struct pci_dev *pdev) 3836 { 3837 scsi_qla_host_t *base_vha; 3838 struct qla_hw_data *ha; 3839 3840 base_vha = pci_get_drvdata(pdev); 3841 ha = base_vha->hw; 3842 ql_log(ql_log_info, base_vha, 0xb079, 3843 "Removing driver\n"); 3844 __qla_set_remove_flag(base_vha); 3845 cancel_work_sync(&ha->board_disable); 3846 3847 /* 3848 * If the PCI device is disabled then there was a PCI-disconnect and 3849 * qla2x00_disable_board_on_pci_error has taken care of most of the 3850 * resources. 3851 */ 3852 if (!atomic_read(&pdev->enable_cnt)) { 3853 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3854 base_vha->gnl.l, base_vha->gnl.ldma); 3855 base_vha->gnl.l = NULL; 3856 scsi_host_put(base_vha->host); 3857 kfree(ha); 3858 pci_set_drvdata(pdev, NULL); 3859 return; 3860 } 3861 qla2x00_wait_for_hba_ready(base_vha); 3862 3863 /* 3864 * if UNLOADING flag is already set, then continue unload, 3865 * where it was set first. 3866 */ 3867 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3868 return; 3869 3870 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3871 IS_QLA28XX(ha)) { 3872 if (ha->flags.fw_started) 3873 qla2x00_abort_isp_cleanup(base_vha); 3874 } else if (!IS_QLAFX00(ha)) { 3875 if (IS_QLA8031(ha)) { 3876 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3877 "Clearing fcoe driver presence.\n"); 3878 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3879 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3880 "Error while clearing DRV-Presence.\n"); 3881 } 3882 3883 qla2x00_try_to_stop_firmware(base_vha); 3884 } 3885 3886 qla2x00_wait_for_sess_deletion(base_vha); 3887 3888 qla_nvme_delete(base_vha); 3889 3890 dma_free_coherent(&ha->pdev->dev, 3891 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3892 3893 base_vha->gnl.l = NULL; 3894 qla_enode_stop(base_vha); 3895 qla_edb_stop(base_vha); 3896 3897 vfree(base_vha->scan.l); 3898 3899 if (IS_QLAFX00(ha)) 3900 qlafx00_driver_shutdown(base_vha, 20); 3901 3902 qla2x00_delete_all_vps(ha, base_vha); 3903 3904 qla2x00_dfs_remove(base_vha); 3905 3906 qla84xx_put_chip(base_vha); 3907 3908 /* Disable timer */ 3909 if (base_vha->timer_active) 3910 qla2x00_stop_timer(base_vha); 3911 3912 base_vha->flags.online = 0; 3913 3914 /* free DMA memory */ 3915 if (ha->exlogin_buf) 3916 qla2x00_free_exlogin_buffer(ha); 3917 3918 /* free DMA memory */ 3919 if (ha->exchoffld_buf) 3920 qla2x00_free_exchoffld_buffer(ha); 3921 3922 qla2x00_destroy_deferred_work(ha); 3923 3924 qlt_remove_target(ha, base_vha); 3925 3926 qla2x00_free_sysfs_attr(base_vha, true); 3927 3928 fc_remove_host(base_vha->host); 3929 3930 scsi_remove_host(base_vha->host); 3931 3932 qla2x00_free_device(base_vha); 3933 3934 qla2x00_clear_drv_active(ha); 3935 3936 scsi_host_put(base_vha->host); 3937 3938 qla2x00_unmap_iobases(ha); 3939 3940 pci_release_selected_regions(ha->pdev, ha->bars); 3941 kfree(ha); 3942 3943 pci_disable_pcie_error_reporting(pdev); 3944 3945 pci_disable_device(pdev); 3946 } 3947 3948 static inline void 3949 qla24xx_free_purex_list(struct purex_list *list) 3950 { 3951 struct purex_item *item, *next; 3952 ulong flags; 3953 3954 spin_lock_irqsave(&list->lock, flags); 3955 list_for_each_entry_safe(item, next, &list->head, list) { 3956 list_del(&item->list); 3957 if (item == &item->vha->default_item) 3958 continue; 3959 kfree(item); 3960 } 3961 spin_unlock_irqrestore(&list->lock, flags); 3962 } 3963 3964 static void 3965 qla2x00_free_device(scsi_qla_host_t *vha) 3966 { 3967 struct qla_hw_data *ha = vha->hw; 3968 3969 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3970 3971 /* Disable timer */ 3972 if (vha->timer_active) 3973 qla2x00_stop_timer(vha); 3974 3975 qla25xx_delete_queues(vha); 3976 vha->flags.online = 0; 3977 3978 /* turn-off interrupts on the card */ 3979 if (ha->interrupts_on) { 3980 vha->flags.init_done = 0; 3981 ha->isp_ops->disable_intrs(ha); 3982 } 3983 3984 qla2x00_free_fcports(vha); 3985 3986 qla2x00_free_irqs(vha); 3987 3988 /* Flush the work queue and remove it */ 3989 if (ha->wq) { 3990 destroy_workqueue(ha->wq); 3991 ha->wq = NULL; 3992 } 3993 3994 3995 qla24xx_free_purex_list(&vha->purex_list); 3996 3997 qla2x00_mem_free(ha); 3998 3999 qla82xx_md_free(vha); 4000 4001 qla_edif_sadb_release_free_pool(ha); 4002 qla_edif_sadb_release(ha); 4003 4004 qla2x00_free_queues(ha); 4005 } 4006 4007 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4008 { 4009 fc_port_t *fcport, *tfcport; 4010 4011 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4012 qla2x00_free_fcport(fcport); 4013 } 4014 4015 static inline void 4016 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4017 { 4018 int now; 4019 4020 if (!fcport->rport) 4021 return; 4022 4023 if (fcport->rport) { 4024 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4025 "%s %8phN. rport %p roles %x\n", 4026 __func__, fcport->port_name, fcport->rport, 4027 fcport->rport->roles); 4028 fc_remote_port_delete(fcport->rport); 4029 } 4030 qlt_do_generation_tick(vha, &now); 4031 } 4032 4033 /* 4034 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4035 * 4036 * Input: ha = adapter block pointer. fcport = port structure pointer. 4037 * 4038 * Return: None. 4039 * 4040 * Context: 4041 */ 4042 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4043 int do_login) 4044 { 4045 if (IS_QLAFX00(vha->hw)) { 4046 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4047 qla2x00_schedule_rport_del(vha, fcport); 4048 return; 4049 } 4050 4051 if (atomic_read(&fcport->state) == FCS_ONLINE && 4052 vha->vp_idx == fcport->vha->vp_idx) { 4053 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4054 qla2x00_schedule_rport_del(vha, fcport); 4055 } 4056 4057 /* 4058 * We may need to retry the login, so don't change the state of the 4059 * port but do the retries. 4060 */ 4061 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4062 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4063 4064 if (!do_login) 4065 return; 4066 4067 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4068 } 4069 4070 void 4071 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4072 { 4073 fc_port_t *fcport; 4074 4075 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4076 "Mark all dev lost\n"); 4077 4078 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4079 if (fcport->loop_id != FC_NO_LOOP_ID && 4080 (fcport->flags & FCF_FCP2_DEVICE) && 4081 fcport->port_type == FCT_TARGET && 4082 !qla2x00_reset_active(vha)) { 4083 ql_dbg(ql_dbg_disc, vha, 0x211a, 4084 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4085 fcport->flags, fcport->port_type, 4086 fcport->d_id.b24, fcport->port_name); 4087 continue; 4088 } 4089 fcport->scan_state = 0; 4090 qlt_schedule_sess_for_deletion(fcport); 4091 } 4092 } 4093 4094 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4095 { 4096 int i; 4097 4098 if (IS_FWI2_CAPABLE(ha)) 4099 return; 4100 4101 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4102 set_bit(i, ha->loop_id_map); 4103 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4104 set_bit(BROADCAST, ha->loop_id_map); 4105 } 4106 4107 /* 4108 * qla2x00_mem_alloc 4109 * Allocates adapter memory. 4110 * 4111 * Returns: 4112 * 0 = success. 4113 * !0 = failure. 4114 */ 4115 static int 4116 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4117 struct req_que **req, struct rsp_que **rsp) 4118 { 4119 char name[16]; 4120 int rc; 4121 4122 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4123 &ha->init_cb_dma, GFP_KERNEL); 4124 if (!ha->init_cb) 4125 goto fail; 4126 4127 rc = btree_init32(&ha->host_map); 4128 if (rc) 4129 goto fail_free_init_cb; 4130 4131 if (qlt_mem_alloc(ha) < 0) 4132 goto fail_free_btree; 4133 4134 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4135 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4136 if (!ha->gid_list) 4137 goto fail_free_tgt_mem; 4138 4139 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4140 if (!ha->srb_mempool) 4141 goto fail_free_gid_list; 4142 4143 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4144 /* Allocate cache for CT6 Ctx. */ 4145 if (!ctx_cachep) { 4146 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4147 sizeof(struct ct6_dsd), 0, 4148 SLAB_HWCACHE_ALIGN, NULL); 4149 if (!ctx_cachep) 4150 goto fail_free_srb_mempool; 4151 } 4152 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4153 ctx_cachep); 4154 if (!ha->ctx_mempool) 4155 goto fail_free_srb_mempool; 4156 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4157 "ctx_cachep=%p ctx_mempool=%p.\n", 4158 ctx_cachep, ha->ctx_mempool); 4159 } 4160 4161 /* Get memory for cached NVRAM */ 4162 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4163 if (!ha->nvram) 4164 goto fail_free_ctx_mempool; 4165 4166 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4167 ha->pdev->device); 4168 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4169 DMA_POOL_SIZE, 8, 0); 4170 if (!ha->s_dma_pool) 4171 goto fail_free_nvram; 4172 4173 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4174 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4175 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4176 4177 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4178 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4179 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4180 if (!ha->dl_dma_pool) { 4181 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4182 "Failed to allocate memory for dl_dma_pool.\n"); 4183 goto fail_s_dma_pool; 4184 } 4185 4186 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4187 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4188 if (!ha->fcp_cmnd_dma_pool) { 4189 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4190 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4191 goto fail_dl_dma_pool; 4192 } 4193 4194 if (ql2xenabledif) { 4195 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4196 struct dsd_dma *dsd, *nxt; 4197 uint i; 4198 /* Creata a DMA pool of buffers for DIF bundling */ 4199 ha->dif_bundl_pool = dma_pool_create(name, 4200 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4201 if (!ha->dif_bundl_pool) { 4202 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4203 "%s: failed create dif_bundl_pool\n", 4204 __func__); 4205 goto fail_dif_bundl_dma_pool; 4206 } 4207 4208 INIT_LIST_HEAD(&ha->pool.good.head); 4209 INIT_LIST_HEAD(&ha->pool.unusable.head); 4210 ha->pool.good.count = 0; 4211 ha->pool.unusable.count = 0; 4212 for (i = 0; i < 128; i++) { 4213 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4214 if (!dsd) { 4215 ql_dbg_pci(ql_dbg_init, ha->pdev, 4216 0xe0ee, "%s: failed alloc dsd\n", 4217 __func__); 4218 return -ENOMEM; 4219 } 4220 ha->dif_bundle_kallocs++; 4221 4222 dsd->dsd_addr = dma_pool_alloc( 4223 ha->dif_bundl_pool, GFP_ATOMIC, 4224 &dsd->dsd_list_dma); 4225 if (!dsd->dsd_addr) { 4226 ql_dbg_pci(ql_dbg_init, ha->pdev, 4227 0xe0ee, 4228 "%s: failed alloc ->dsd_addr\n", 4229 __func__); 4230 kfree(dsd); 4231 ha->dif_bundle_kallocs--; 4232 continue; 4233 } 4234 ha->dif_bundle_dma_allocs++; 4235 4236 /* 4237 * if DMA buffer crosses 4G boundary, 4238 * put it on bad list 4239 */ 4240 if (MSD(dsd->dsd_list_dma) ^ 4241 MSD(dsd->dsd_list_dma + bufsize)) { 4242 list_add_tail(&dsd->list, 4243 &ha->pool.unusable.head); 4244 ha->pool.unusable.count++; 4245 } else { 4246 list_add_tail(&dsd->list, 4247 &ha->pool.good.head); 4248 ha->pool.good.count++; 4249 } 4250 } 4251 4252 /* return the good ones back to the pool */ 4253 list_for_each_entry_safe(dsd, nxt, 4254 &ha->pool.good.head, list) { 4255 list_del(&dsd->list); 4256 dma_pool_free(ha->dif_bundl_pool, 4257 dsd->dsd_addr, dsd->dsd_list_dma); 4258 ha->dif_bundle_dma_allocs--; 4259 kfree(dsd); 4260 ha->dif_bundle_kallocs--; 4261 } 4262 4263 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4264 "%s: dif dma pool (good=%u unusable=%u)\n", 4265 __func__, ha->pool.good.count, 4266 ha->pool.unusable.count); 4267 } 4268 4269 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4270 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4271 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4272 ha->dif_bundl_pool); 4273 } 4274 4275 /* Allocate memory for SNS commands */ 4276 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4277 /* Get consistent memory allocated for SNS commands */ 4278 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4279 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4280 if (!ha->sns_cmd) 4281 goto fail_dma_pool; 4282 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4283 "sns_cmd: %p.\n", ha->sns_cmd); 4284 } else { 4285 /* Get consistent memory allocated for MS IOCB */ 4286 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4287 &ha->ms_iocb_dma); 4288 if (!ha->ms_iocb) 4289 goto fail_dma_pool; 4290 /* Get consistent memory allocated for CT SNS commands */ 4291 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4292 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4293 if (!ha->ct_sns) 4294 goto fail_free_ms_iocb; 4295 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4296 "ms_iocb=%p ct_sns=%p.\n", 4297 ha->ms_iocb, ha->ct_sns); 4298 } 4299 4300 /* Allocate memory for request ring */ 4301 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4302 if (!*req) { 4303 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4304 "Failed to allocate memory for req.\n"); 4305 goto fail_req; 4306 } 4307 (*req)->length = req_len; 4308 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4309 ((*req)->length + 1) * sizeof(request_t), 4310 &(*req)->dma, GFP_KERNEL); 4311 if (!(*req)->ring) { 4312 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4313 "Failed to allocate memory for req_ring.\n"); 4314 goto fail_req_ring; 4315 } 4316 /* Allocate memory for response ring */ 4317 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4318 if (!*rsp) { 4319 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4320 "Failed to allocate memory for rsp.\n"); 4321 goto fail_rsp; 4322 } 4323 (*rsp)->hw = ha; 4324 (*rsp)->length = rsp_len; 4325 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4326 ((*rsp)->length + 1) * sizeof(response_t), 4327 &(*rsp)->dma, GFP_KERNEL); 4328 if (!(*rsp)->ring) { 4329 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4330 "Failed to allocate memory for rsp_ring.\n"); 4331 goto fail_rsp_ring; 4332 } 4333 (*req)->rsp = *rsp; 4334 (*rsp)->req = *req; 4335 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4336 "req=%p req->length=%d req->ring=%p rsp=%p " 4337 "rsp->length=%d rsp->ring=%p.\n", 4338 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4339 (*rsp)->ring); 4340 /* Allocate memory for NVRAM data for vports */ 4341 if (ha->nvram_npiv_size) { 4342 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4343 sizeof(struct qla_npiv_entry), 4344 GFP_KERNEL); 4345 if (!ha->npiv_info) { 4346 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4347 "Failed to allocate memory for npiv_info.\n"); 4348 goto fail_npiv_info; 4349 } 4350 } else 4351 ha->npiv_info = NULL; 4352 4353 /* Get consistent memory allocated for EX-INIT-CB. */ 4354 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4355 IS_QLA28XX(ha)) { 4356 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4357 &ha->ex_init_cb_dma); 4358 if (!ha->ex_init_cb) 4359 goto fail_ex_init_cb; 4360 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4361 "ex_init_cb=%p.\n", ha->ex_init_cb); 4362 } 4363 4364 /* Get consistent memory allocated for Special Features-CB. */ 4365 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4366 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4367 &ha->sf_init_cb_dma); 4368 if (!ha->sf_init_cb) 4369 goto fail_sf_init_cb; 4370 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4371 "sf_init_cb=%p.\n", ha->sf_init_cb); 4372 } 4373 4374 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4375 4376 /* Get consistent memory allocated for Async Port-Database. */ 4377 if (!IS_FWI2_CAPABLE(ha)) { 4378 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4379 &ha->async_pd_dma); 4380 if (!ha->async_pd) 4381 goto fail_async_pd; 4382 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4383 "async_pd=%p.\n", ha->async_pd); 4384 } 4385 4386 INIT_LIST_HEAD(&ha->vp_list); 4387 4388 /* Allocate memory for our loop_id bitmap */ 4389 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4390 sizeof(long), 4391 GFP_KERNEL); 4392 if (!ha->loop_id_map) 4393 goto fail_loop_id_map; 4394 else { 4395 qla2x00_set_reserved_loop_ids(ha); 4396 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4397 "loop_id_map=%p.\n", ha->loop_id_map); 4398 } 4399 4400 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4401 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4402 if (!ha->sfp_data) { 4403 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4404 "Unable to allocate memory for SFP read-data.\n"); 4405 goto fail_sfp_data; 4406 } 4407 4408 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4409 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4410 GFP_KERNEL); 4411 if (!ha->flt) { 4412 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4413 "Unable to allocate memory for FLT.\n"); 4414 goto fail_flt_buffer; 4415 } 4416 4417 /* allocate the purex dma pool */ 4418 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4419 ELS_MAX_PAYLOAD, 8, 0); 4420 4421 if (!ha->purex_dma_pool) { 4422 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4423 "Unable to allocate purex_dma_pool.\n"); 4424 goto fail_flt; 4425 } 4426 4427 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4428 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4429 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4430 4431 if (!ha->elsrej.c) { 4432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4433 "Alloc failed for els reject cmd.\n"); 4434 goto fail_elsrej; 4435 } 4436 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4437 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4438 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4439 return 0; 4440 4441 fail_elsrej: 4442 dma_pool_destroy(ha->purex_dma_pool); 4443 fail_flt: 4444 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4445 ha->flt, ha->flt_dma); 4446 4447 fail_flt_buffer: 4448 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4449 ha->sfp_data, ha->sfp_data_dma); 4450 fail_sfp_data: 4451 kfree(ha->loop_id_map); 4452 fail_loop_id_map: 4453 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4454 fail_async_pd: 4455 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4456 fail_sf_init_cb: 4457 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4458 fail_ex_init_cb: 4459 kfree(ha->npiv_info); 4460 fail_npiv_info: 4461 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4462 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4463 (*rsp)->ring = NULL; 4464 (*rsp)->dma = 0; 4465 fail_rsp_ring: 4466 kfree(*rsp); 4467 *rsp = NULL; 4468 fail_rsp: 4469 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4470 sizeof(request_t), (*req)->ring, (*req)->dma); 4471 (*req)->ring = NULL; 4472 (*req)->dma = 0; 4473 fail_req_ring: 4474 kfree(*req); 4475 *req = NULL; 4476 fail_req: 4477 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4478 ha->ct_sns, ha->ct_sns_dma); 4479 ha->ct_sns = NULL; 4480 ha->ct_sns_dma = 0; 4481 fail_free_ms_iocb: 4482 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4483 ha->ms_iocb = NULL; 4484 ha->ms_iocb_dma = 0; 4485 4486 if (ha->sns_cmd) 4487 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4488 ha->sns_cmd, ha->sns_cmd_dma); 4489 fail_dma_pool: 4490 if (ql2xenabledif) { 4491 struct dsd_dma *dsd, *nxt; 4492 4493 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4494 list) { 4495 list_del(&dsd->list); 4496 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4497 dsd->dsd_list_dma); 4498 ha->dif_bundle_dma_allocs--; 4499 kfree(dsd); 4500 ha->dif_bundle_kallocs--; 4501 ha->pool.unusable.count--; 4502 } 4503 dma_pool_destroy(ha->dif_bundl_pool); 4504 ha->dif_bundl_pool = NULL; 4505 } 4506 4507 fail_dif_bundl_dma_pool: 4508 if (IS_QLA82XX(ha) || ql2xenabledif) { 4509 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4510 ha->fcp_cmnd_dma_pool = NULL; 4511 } 4512 fail_dl_dma_pool: 4513 if (IS_QLA82XX(ha) || ql2xenabledif) { 4514 dma_pool_destroy(ha->dl_dma_pool); 4515 ha->dl_dma_pool = NULL; 4516 } 4517 fail_s_dma_pool: 4518 dma_pool_destroy(ha->s_dma_pool); 4519 ha->s_dma_pool = NULL; 4520 fail_free_nvram: 4521 kfree(ha->nvram); 4522 ha->nvram = NULL; 4523 fail_free_ctx_mempool: 4524 mempool_destroy(ha->ctx_mempool); 4525 ha->ctx_mempool = NULL; 4526 fail_free_srb_mempool: 4527 mempool_destroy(ha->srb_mempool); 4528 ha->srb_mempool = NULL; 4529 fail_free_gid_list: 4530 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4531 ha->gid_list, 4532 ha->gid_list_dma); 4533 ha->gid_list = NULL; 4534 ha->gid_list_dma = 0; 4535 fail_free_tgt_mem: 4536 qlt_mem_free(ha); 4537 fail_free_btree: 4538 btree_destroy32(&ha->host_map); 4539 fail_free_init_cb: 4540 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4541 ha->init_cb_dma); 4542 ha->init_cb = NULL; 4543 ha->init_cb_dma = 0; 4544 fail: 4545 ql_log(ql_log_fatal, NULL, 0x0030, 4546 "Memory allocation failure.\n"); 4547 return -ENOMEM; 4548 } 4549 4550 int 4551 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4552 { 4553 int rval; 4554 uint16_t size, max_cnt; 4555 uint32_t temp; 4556 struct qla_hw_data *ha = vha->hw; 4557 4558 /* Return if we don't need to alloacate any extended logins */ 4559 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4560 return QLA_SUCCESS; 4561 4562 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4563 return QLA_SUCCESS; 4564 4565 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4566 max_cnt = 0; 4567 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4568 if (rval != QLA_SUCCESS) { 4569 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4570 "Failed to get exlogin status.\n"); 4571 return rval; 4572 } 4573 4574 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4575 temp *= size; 4576 4577 if (temp != ha->exlogin_size) { 4578 qla2x00_free_exlogin_buffer(ha); 4579 ha->exlogin_size = temp; 4580 4581 ql_log(ql_log_info, vha, 0xd024, 4582 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4583 max_cnt, size, temp); 4584 4585 ql_log(ql_log_info, vha, 0xd025, 4586 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4587 4588 /* Get consistent memory for extended logins */ 4589 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4590 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4591 if (!ha->exlogin_buf) { 4592 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4593 "Failed to allocate memory for exlogin_buf_dma.\n"); 4594 return -ENOMEM; 4595 } 4596 } 4597 4598 /* Now configure the dma buffer */ 4599 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4600 if (rval) { 4601 ql_log(ql_log_fatal, vha, 0xd033, 4602 "Setup extended login buffer ****FAILED****.\n"); 4603 qla2x00_free_exlogin_buffer(ha); 4604 } 4605 4606 return rval; 4607 } 4608 4609 /* 4610 * qla2x00_free_exlogin_buffer 4611 * 4612 * Input: 4613 * ha = adapter block pointer 4614 */ 4615 void 4616 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4617 { 4618 if (ha->exlogin_buf) { 4619 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4620 ha->exlogin_buf, ha->exlogin_buf_dma); 4621 ha->exlogin_buf = NULL; 4622 ha->exlogin_size = 0; 4623 } 4624 } 4625 4626 static void 4627 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4628 { 4629 u32 temp; 4630 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4631 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4632 4633 if (max_cnt > vha->hw->max_exchg) 4634 max_cnt = vha->hw->max_exchg; 4635 4636 if (qla_ini_mode_enabled(vha)) { 4637 if (vha->ql2xiniexchg > max_cnt) 4638 vha->ql2xiniexchg = max_cnt; 4639 4640 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4641 *ret_cnt = vha->ql2xiniexchg; 4642 4643 } else if (qla_tgt_mode_enabled(vha)) { 4644 if (vha->ql2xexchoffld > max_cnt) { 4645 vha->ql2xexchoffld = max_cnt; 4646 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4647 } 4648 4649 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4650 *ret_cnt = vha->ql2xexchoffld; 4651 } else if (qla_dual_mode_enabled(vha)) { 4652 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4653 if (temp > max_cnt) { 4654 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4655 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4656 temp = max_cnt; 4657 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4658 } 4659 4660 if (temp > FW_DEF_EXCHANGES_CNT) 4661 *ret_cnt = temp; 4662 } 4663 } 4664 4665 int 4666 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4667 { 4668 int rval; 4669 u16 size, max_cnt; 4670 u32 actual_cnt, totsz; 4671 struct qla_hw_data *ha = vha->hw; 4672 4673 if (!ha->flags.exchoffld_enabled) 4674 return QLA_SUCCESS; 4675 4676 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4677 return QLA_SUCCESS; 4678 4679 max_cnt = 0; 4680 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4681 if (rval != QLA_SUCCESS) { 4682 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4683 "Failed to get exlogin status.\n"); 4684 return rval; 4685 } 4686 4687 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4688 ql_log(ql_log_info, vha, 0xd014, 4689 "Actual exchange offload count: %d.\n", actual_cnt); 4690 4691 totsz = actual_cnt * size; 4692 4693 if (totsz != ha->exchoffld_size) { 4694 qla2x00_free_exchoffld_buffer(ha); 4695 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4696 ha->exchoffld_size = 0; 4697 ha->flags.exchoffld_enabled = 0; 4698 return QLA_SUCCESS; 4699 } 4700 4701 ha->exchoffld_size = totsz; 4702 4703 ql_log(ql_log_info, vha, 0xd016, 4704 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4705 max_cnt, actual_cnt, size, totsz); 4706 4707 ql_log(ql_log_info, vha, 0xd017, 4708 "Exchange Buffers requested size = 0x%x\n", 4709 ha->exchoffld_size); 4710 4711 /* Get consistent memory for extended logins */ 4712 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4713 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4714 if (!ha->exchoffld_buf) { 4715 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4716 "Failed to allocate memory for Exchange Offload.\n"); 4717 4718 if (ha->max_exchg > 4719 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4720 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4721 } else if (ha->max_exchg > 4722 (FW_DEF_EXCHANGES_CNT + 512)) { 4723 ha->max_exchg -= 512; 4724 } else { 4725 ha->flags.exchoffld_enabled = 0; 4726 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4727 "Disabling Exchange offload due to lack of memory\n"); 4728 } 4729 ha->exchoffld_size = 0; 4730 4731 return -ENOMEM; 4732 } 4733 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4734 /* pathological case */ 4735 qla2x00_free_exchoffld_buffer(ha); 4736 ha->exchoffld_size = 0; 4737 ha->flags.exchoffld_enabled = 0; 4738 ql_log(ql_log_info, vha, 0xd016, 4739 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4740 ha->exchoffld_size, actual_cnt, size, totsz); 4741 return 0; 4742 } 4743 4744 /* Now configure the dma buffer */ 4745 rval = qla_set_exchoffld_mem_cfg(vha); 4746 if (rval) { 4747 ql_log(ql_log_fatal, vha, 0xd02e, 4748 "Setup exchange offload buffer ****FAILED****.\n"); 4749 qla2x00_free_exchoffld_buffer(ha); 4750 } else { 4751 /* re-adjust number of target exchange */ 4752 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4753 4754 if (qla_ini_mode_enabled(vha)) 4755 icb->exchange_count = 0; 4756 else 4757 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4758 } 4759 4760 return rval; 4761 } 4762 4763 /* 4764 * qla2x00_free_exchoffld_buffer 4765 * 4766 * Input: 4767 * ha = adapter block pointer 4768 */ 4769 void 4770 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4771 { 4772 if (ha->exchoffld_buf) { 4773 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4774 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4775 ha->exchoffld_buf = NULL; 4776 ha->exchoffld_size = 0; 4777 } 4778 } 4779 4780 /* 4781 * qla2x00_free_fw_dump 4782 * Frees fw dump stuff. 4783 * 4784 * Input: 4785 * ha = adapter block pointer 4786 */ 4787 static void 4788 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4789 { 4790 struct fwdt *fwdt = ha->fwdt; 4791 uint j; 4792 4793 if (ha->fce) 4794 dma_free_coherent(&ha->pdev->dev, 4795 FCE_SIZE, ha->fce, ha->fce_dma); 4796 4797 if (ha->eft) 4798 dma_free_coherent(&ha->pdev->dev, 4799 EFT_SIZE, ha->eft, ha->eft_dma); 4800 4801 vfree(ha->fw_dump); 4802 4803 ha->fce = NULL; 4804 ha->fce_dma = 0; 4805 ha->flags.fce_enabled = 0; 4806 ha->eft = NULL; 4807 ha->eft_dma = 0; 4808 ha->fw_dumped = false; 4809 ha->fw_dump_cap_flags = 0; 4810 ha->fw_dump_reading = 0; 4811 ha->fw_dump = NULL; 4812 ha->fw_dump_len = 0; 4813 4814 for (j = 0; j < 2; j++, fwdt++) { 4815 vfree(fwdt->template); 4816 fwdt->template = NULL; 4817 fwdt->length = 0; 4818 } 4819 } 4820 4821 /* 4822 * qla2x00_mem_free 4823 * Frees all adapter allocated memory. 4824 * 4825 * Input: 4826 * ha = adapter block pointer. 4827 */ 4828 static void 4829 qla2x00_mem_free(struct qla_hw_data *ha) 4830 { 4831 qla2x00_free_fw_dump(ha); 4832 4833 if (ha->mctp_dump) 4834 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4835 ha->mctp_dump_dma); 4836 ha->mctp_dump = NULL; 4837 4838 mempool_destroy(ha->srb_mempool); 4839 ha->srb_mempool = NULL; 4840 4841 if (ha->dcbx_tlv) 4842 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4843 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4844 ha->dcbx_tlv = NULL; 4845 4846 if (ha->xgmac_data) 4847 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4848 ha->xgmac_data, ha->xgmac_data_dma); 4849 ha->xgmac_data = NULL; 4850 4851 if (ha->sns_cmd) 4852 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4853 ha->sns_cmd, ha->sns_cmd_dma); 4854 ha->sns_cmd = NULL; 4855 ha->sns_cmd_dma = 0; 4856 4857 if (ha->ct_sns) 4858 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4859 ha->ct_sns, ha->ct_sns_dma); 4860 ha->ct_sns = NULL; 4861 ha->ct_sns_dma = 0; 4862 4863 if (ha->sfp_data) 4864 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4865 ha->sfp_data_dma); 4866 ha->sfp_data = NULL; 4867 4868 if (ha->flt) 4869 dma_free_coherent(&ha->pdev->dev, 4870 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4871 ha->flt, ha->flt_dma); 4872 ha->flt = NULL; 4873 ha->flt_dma = 0; 4874 4875 if (ha->ms_iocb) 4876 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4877 ha->ms_iocb = NULL; 4878 ha->ms_iocb_dma = 0; 4879 4880 if (ha->sf_init_cb) 4881 dma_pool_free(ha->s_dma_pool, 4882 ha->sf_init_cb, ha->sf_init_cb_dma); 4883 4884 if (ha->ex_init_cb) 4885 dma_pool_free(ha->s_dma_pool, 4886 ha->ex_init_cb, ha->ex_init_cb_dma); 4887 ha->ex_init_cb = NULL; 4888 ha->ex_init_cb_dma = 0; 4889 4890 if (ha->async_pd) 4891 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4892 ha->async_pd = NULL; 4893 ha->async_pd_dma = 0; 4894 4895 dma_pool_destroy(ha->s_dma_pool); 4896 ha->s_dma_pool = NULL; 4897 4898 if (ha->gid_list) 4899 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4900 ha->gid_list, ha->gid_list_dma); 4901 ha->gid_list = NULL; 4902 ha->gid_list_dma = 0; 4903 4904 if (IS_QLA82XX(ha)) { 4905 if (!list_empty(&ha->gbl_dsd_list)) { 4906 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4907 4908 /* clean up allocated prev pool */ 4909 list_for_each_entry_safe(dsd_ptr, 4910 tdsd_ptr, &ha->gbl_dsd_list, list) { 4911 dma_pool_free(ha->dl_dma_pool, 4912 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4913 list_del(&dsd_ptr->list); 4914 kfree(dsd_ptr); 4915 } 4916 } 4917 } 4918 4919 dma_pool_destroy(ha->dl_dma_pool); 4920 ha->dl_dma_pool = NULL; 4921 4922 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4923 ha->fcp_cmnd_dma_pool = NULL; 4924 4925 mempool_destroy(ha->ctx_mempool); 4926 ha->ctx_mempool = NULL; 4927 4928 if (ql2xenabledif && ha->dif_bundl_pool) { 4929 struct dsd_dma *dsd, *nxt; 4930 4931 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4932 list) { 4933 list_del(&dsd->list); 4934 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4935 dsd->dsd_list_dma); 4936 ha->dif_bundle_dma_allocs--; 4937 kfree(dsd); 4938 ha->dif_bundle_kallocs--; 4939 ha->pool.unusable.count--; 4940 } 4941 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4942 list_del(&dsd->list); 4943 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4944 dsd->dsd_list_dma); 4945 ha->dif_bundle_dma_allocs--; 4946 kfree(dsd); 4947 ha->dif_bundle_kallocs--; 4948 } 4949 } 4950 4951 dma_pool_destroy(ha->dif_bundl_pool); 4952 ha->dif_bundl_pool = NULL; 4953 4954 qlt_mem_free(ha); 4955 qla_remove_hostmap(ha); 4956 4957 if (ha->init_cb) 4958 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4959 ha->init_cb, ha->init_cb_dma); 4960 4961 dma_pool_destroy(ha->purex_dma_pool); 4962 ha->purex_dma_pool = NULL; 4963 4964 if (ha->elsrej.c) { 4965 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4966 ha->elsrej.c, ha->elsrej.cdma); 4967 ha->elsrej.c = NULL; 4968 } 4969 4970 ha->init_cb = NULL; 4971 ha->init_cb_dma = 0; 4972 4973 vfree(ha->optrom_buffer); 4974 ha->optrom_buffer = NULL; 4975 kfree(ha->nvram); 4976 ha->nvram = NULL; 4977 kfree(ha->npiv_info); 4978 ha->npiv_info = NULL; 4979 kfree(ha->swl); 4980 ha->swl = NULL; 4981 kfree(ha->loop_id_map); 4982 ha->sf_init_cb = NULL; 4983 ha->sf_init_cb_dma = 0; 4984 ha->loop_id_map = NULL; 4985 } 4986 4987 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4988 struct qla_hw_data *ha) 4989 { 4990 struct Scsi_Host *host; 4991 struct scsi_qla_host *vha = NULL; 4992 4993 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4994 if (!host) { 4995 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4996 "Failed to allocate host from the scsi layer, aborting.\n"); 4997 return NULL; 4998 } 4999 5000 /* Clear our data area */ 5001 vha = shost_priv(host); 5002 memset(vha, 0, sizeof(scsi_qla_host_t)); 5003 5004 vha->host = host; 5005 vha->host_no = host->host_no; 5006 vha->hw = ha; 5007 5008 vha->qlini_mode = ql2x_ini_mode; 5009 vha->ql2xexchoffld = ql2xexchoffld; 5010 vha->ql2xiniexchg = ql2xiniexchg; 5011 5012 INIT_LIST_HEAD(&vha->vp_fcports); 5013 INIT_LIST_HEAD(&vha->work_list); 5014 INIT_LIST_HEAD(&vha->list); 5015 INIT_LIST_HEAD(&vha->qla_cmd_list); 5016 INIT_LIST_HEAD(&vha->logo_list); 5017 INIT_LIST_HEAD(&vha->plogi_ack_list); 5018 INIT_LIST_HEAD(&vha->qp_list); 5019 INIT_LIST_HEAD(&vha->gnl.fcports); 5020 INIT_LIST_HEAD(&vha->gpnid_list); 5021 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5022 5023 INIT_LIST_HEAD(&vha->purex_list.head); 5024 spin_lock_init(&vha->purex_list.lock); 5025 5026 spin_lock_init(&vha->work_lock); 5027 spin_lock_init(&vha->cmd_list_lock); 5028 init_waitqueue_head(&vha->fcport_waitQ); 5029 init_waitqueue_head(&vha->vref_waitq); 5030 qla_enode_init(vha); 5031 qla_edb_init(vha); 5032 5033 5034 vha->gnl.size = sizeof(struct get_name_list_extended) * 5035 (ha->max_loop_id + 1); 5036 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5037 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5038 if (!vha->gnl.l) { 5039 ql_log(ql_log_fatal, vha, 0xd04a, 5040 "Alloc failed for name list.\n"); 5041 scsi_host_put(vha->host); 5042 return NULL; 5043 } 5044 5045 /* todo: what about ext login? */ 5046 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5047 vha->scan.l = vmalloc(vha->scan.size); 5048 if (!vha->scan.l) { 5049 ql_log(ql_log_fatal, vha, 0xd04a, 5050 "Alloc failed for scan database.\n"); 5051 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5052 vha->gnl.l, vha->gnl.ldma); 5053 vha->gnl.l = NULL; 5054 scsi_host_put(vha->host); 5055 return NULL; 5056 } 5057 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5058 5059 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5060 ql_dbg(ql_dbg_init, vha, 0x0041, 5061 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5062 vha->host, vha->hw, vha, 5063 dev_name(&(ha->pdev->dev))); 5064 5065 return vha; 5066 } 5067 5068 struct qla_work_evt * 5069 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5070 { 5071 struct qla_work_evt *e; 5072 uint8_t bail; 5073 5074 if (test_bit(UNLOADING, &vha->dpc_flags)) 5075 return NULL; 5076 5077 QLA_VHA_MARK_BUSY(vha, bail); 5078 if (bail) 5079 return NULL; 5080 5081 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5082 if (!e) { 5083 QLA_VHA_MARK_NOT_BUSY(vha); 5084 return NULL; 5085 } 5086 5087 INIT_LIST_HEAD(&e->list); 5088 e->type = type; 5089 e->flags = QLA_EVT_FLAG_FREE; 5090 return e; 5091 } 5092 5093 int 5094 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5095 { 5096 unsigned long flags; 5097 bool q = false; 5098 5099 spin_lock_irqsave(&vha->work_lock, flags); 5100 list_add_tail(&e->list, &vha->work_list); 5101 5102 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5103 q = true; 5104 5105 spin_unlock_irqrestore(&vha->work_lock, flags); 5106 5107 if (q) 5108 queue_work(vha->hw->wq, &vha->iocb_work); 5109 5110 return QLA_SUCCESS; 5111 } 5112 5113 int 5114 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5115 u32 data) 5116 { 5117 struct qla_work_evt *e; 5118 5119 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5120 if (!e) 5121 return QLA_FUNCTION_FAILED; 5122 5123 e->u.aen.code = code; 5124 e->u.aen.data = data; 5125 return qla2x00_post_work(vha, e); 5126 } 5127 5128 int 5129 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5130 { 5131 struct qla_work_evt *e; 5132 5133 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5134 if (!e) 5135 return QLA_FUNCTION_FAILED; 5136 5137 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5138 return qla2x00_post_work(vha, e); 5139 } 5140 5141 #define qla2x00_post_async_work(name, type) \ 5142 int qla2x00_post_async_##name##_work( \ 5143 struct scsi_qla_host *vha, \ 5144 fc_port_t *fcport, uint16_t *data) \ 5145 { \ 5146 struct qla_work_evt *e; \ 5147 \ 5148 e = qla2x00_alloc_work(vha, type); \ 5149 if (!e) \ 5150 return QLA_FUNCTION_FAILED; \ 5151 \ 5152 e->u.logio.fcport = fcport; \ 5153 if (data) { \ 5154 e->u.logio.data[0] = data[0]; \ 5155 e->u.logio.data[1] = data[1]; \ 5156 } \ 5157 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5158 return qla2x00_post_work(vha, e); \ 5159 } 5160 5161 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5162 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5163 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5164 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5165 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5166 5167 int 5168 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5169 { 5170 struct qla_work_evt *e; 5171 5172 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5173 if (!e) 5174 return QLA_FUNCTION_FAILED; 5175 5176 e->u.uevent.code = code; 5177 return qla2x00_post_work(vha, e); 5178 } 5179 5180 static void 5181 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5182 { 5183 char event_string[40]; 5184 char *envp[] = { event_string, NULL }; 5185 5186 switch (code) { 5187 case QLA_UEVENT_CODE_FW_DUMP: 5188 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5189 vha->host_no); 5190 break; 5191 default: 5192 /* do nothing */ 5193 break; 5194 } 5195 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5196 } 5197 5198 int 5199 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5200 uint32_t *data, int cnt) 5201 { 5202 struct qla_work_evt *e; 5203 5204 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5205 if (!e) 5206 return QLA_FUNCTION_FAILED; 5207 5208 e->u.aenfx.evtcode = evtcode; 5209 e->u.aenfx.count = cnt; 5210 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5211 return qla2x00_post_work(vha, e); 5212 } 5213 5214 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5215 { 5216 unsigned long flags; 5217 5218 if (IS_SW_RESV_ADDR(fcport->d_id)) 5219 return; 5220 5221 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5222 if (fcport->disc_state == DSC_UPD_FCPORT) { 5223 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5224 return; 5225 } 5226 fcport->jiffies_at_registration = jiffies; 5227 fcport->sec_since_registration = 0; 5228 fcport->next_disc_state = DSC_DELETED; 5229 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5230 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5231 5232 queue_work(system_unbound_wq, &fcport->reg_work); 5233 } 5234 5235 static 5236 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5237 { 5238 unsigned long flags; 5239 fc_port_t *fcport = NULL, *tfcp; 5240 struct qlt_plogi_ack_t *pla = 5241 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5242 uint8_t free_fcport = 0; 5243 5244 ql_dbg(ql_dbg_disc, vha, 0xffff, 5245 "%s %d %8phC enter\n", 5246 __func__, __LINE__, e->u.new_sess.port_name); 5247 5248 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5249 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5250 if (fcport) { 5251 fcport->d_id = e->u.new_sess.id; 5252 if (pla) { 5253 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5254 memcpy(fcport->node_name, 5255 pla->iocb.u.isp24.u.plogi.node_name, 5256 WWN_SIZE); 5257 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5258 /* we took an extra ref_count to prevent PLOGI ACK when 5259 * fcport/sess has not been created. 5260 */ 5261 pla->ref_count--; 5262 } 5263 } else { 5264 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5265 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5266 if (fcport) { 5267 fcport->d_id = e->u.new_sess.id; 5268 fcport->flags |= FCF_FABRIC_DEVICE; 5269 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5270 fcport->tgt_short_link_down_cnt = 0; 5271 5272 memcpy(fcport->port_name, e->u.new_sess.port_name, 5273 WWN_SIZE); 5274 5275 fcport->fc4_type = e->u.new_sess.fc4_type; 5276 if (NVME_PRIORITY(vha->hw, fcport)) 5277 fcport->do_prli_nvme = 1; 5278 else 5279 fcport->do_prli_nvme = 0; 5280 5281 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5282 fcport->dm_login_expire = jiffies + 5283 QLA_N2N_WAIT_TIME * HZ; 5284 fcport->fc4_type = FS_FC4TYPE_FCP; 5285 fcport->n2n_flag = 1; 5286 if (vha->flags.nvme_enabled) 5287 fcport->fc4_type |= FS_FC4TYPE_NVME; 5288 } 5289 5290 } else { 5291 ql_dbg(ql_dbg_disc, vha, 0xffff, 5292 "%s %8phC mem alloc fail.\n", 5293 __func__, e->u.new_sess.port_name); 5294 5295 if (pla) { 5296 list_del(&pla->list); 5297 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5298 } 5299 return; 5300 } 5301 5302 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5303 /* search again to make sure no one else got ahead */ 5304 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5305 e->u.new_sess.port_name, 1); 5306 if (tfcp) { 5307 /* should rarily happen */ 5308 ql_dbg(ql_dbg_disc, vha, 0xffff, 5309 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5310 __func__, tfcp->port_name, tfcp->disc_state, 5311 tfcp->fw_login_state); 5312 5313 free_fcport = 1; 5314 } else { 5315 list_add_tail(&fcport->list, &vha->vp_fcports); 5316 5317 } 5318 if (pla) { 5319 qlt_plogi_ack_link(vha, pla, fcport, 5320 QLT_PLOGI_LINK_SAME_WWN); 5321 pla->ref_count--; 5322 } 5323 } 5324 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5325 5326 if (fcport) { 5327 fcport->id_changed = 1; 5328 fcport->scan_state = QLA_FCPORT_FOUND; 5329 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5330 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5331 5332 if (pla) { 5333 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5334 u16 wd3_lo; 5335 5336 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5337 fcport->local = 0; 5338 fcport->loop_id = 5339 le16_to_cpu( 5340 pla->iocb.u.isp24.nport_handle); 5341 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5342 wd3_lo = 5343 le16_to_cpu( 5344 pla->iocb.u.isp24.u.prli.wd3_lo); 5345 5346 if (wd3_lo & BIT_7) 5347 fcport->conf_compl_supported = 1; 5348 5349 if ((wd3_lo & BIT_4) == 0) 5350 fcport->port_type = FCT_INITIATOR; 5351 else 5352 fcport->port_type = FCT_TARGET; 5353 } 5354 qlt_plogi_ack_unref(vha, pla); 5355 } else { 5356 fc_port_t *dfcp = NULL; 5357 5358 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5359 tfcp = qla2x00_find_fcport_by_nportid(vha, 5360 &e->u.new_sess.id, 1); 5361 if (tfcp && (tfcp != fcport)) { 5362 /* 5363 * We have a conflict fcport with same NportID. 5364 */ 5365 ql_dbg(ql_dbg_disc, vha, 0xffff, 5366 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5367 __func__, tfcp->port_name, tfcp->disc_state, 5368 tfcp->fw_login_state); 5369 5370 switch (tfcp->disc_state) { 5371 case DSC_DELETED: 5372 break; 5373 case DSC_DELETE_PEND: 5374 fcport->login_pause = 1; 5375 tfcp->conflict = fcport; 5376 break; 5377 default: 5378 fcport->login_pause = 1; 5379 tfcp->conflict = fcport; 5380 dfcp = tfcp; 5381 break; 5382 } 5383 } 5384 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5385 if (dfcp) 5386 qlt_schedule_sess_for_deletion(tfcp); 5387 5388 if (N2N_TOPO(vha->hw)) { 5389 fcport->flags &= ~FCF_FABRIC_DEVICE; 5390 fcport->keep_nport_handle = 1; 5391 if (vha->flags.nvme_enabled) { 5392 fcport->fc4_type = 5393 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5394 fcport->n2n_flag = 1; 5395 } 5396 fcport->fw_login_state = 0; 5397 5398 schedule_delayed_work(&vha->scan.scan_work, 5); 5399 } else { 5400 qla24xx_fcport_handle_login(vha, fcport); 5401 } 5402 } 5403 } 5404 5405 if (free_fcport) { 5406 qla2x00_free_fcport(fcport); 5407 if (pla) { 5408 list_del(&pla->list); 5409 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5410 } 5411 } 5412 } 5413 5414 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5415 { 5416 struct srb *sp = e->u.iosb.sp; 5417 int rval; 5418 5419 rval = qla2x00_start_sp(sp); 5420 if (rval != QLA_SUCCESS) { 5421 ql_dbg(ql_dbg_disc, vha, 0x2043, 5422 "%s: %s: Re-issue IOCB failed (%d).\n", 5423 __func__, sp->name, rval); 5424 qla24xx_sp_unmap(vha, sp); 5425 } 5426 } 5427 5428 void 5429 qla2x00_do_work(struct scsi_qla_host *vha) 5430 { 5431 struct qla_work_evt *e, *tmp; 5432 unsigned long flags; 5433 LIST_HEAD(work); 5434 int rc; 5435 5436 spin_lock_irqsave(&vha->work_lock, flags); 5437 list_splice_init(&vha->work_list, &work); 5438 spin_unlock_irqrestore(&vha->work_lock, flags); 5439 5440 list_for_each_entry_safe(e, tmp, &work, list) { 5441 rc = QLA_SUCCESS; 5442 switch (e->type) { 5443 case QLA_EVT_AEN: 5444 fc_host_post_event(vha->host, fc_get_event_number(), 5445 e->u.aen.code, e->u.aen.data); 5446 break; 5447 case QLA_EVT_IDC_ACK: 5448 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5449 break; 5450 case QLA_EVT_ASYNC_LOGIN: 5451 qla2x00_async_login(vha, e->u.logio.fcport, 5452 e->u.logio.data); 5453 break; 5454 case QLA_EVT_ASYNC_LOGOUT: 5455 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5456 break; 5457 case QLA_EVT_ASYNC_ADISC: 5458 qla2x00_async_adisc(vha, e->u.logio.fcport, 5459 e->u.logio.data); 5460 break; 5461 case QLA_EVT_UEVENT: 5462 qla2x00_uevent_emit(vha, e->u.uevent.code); 5463 break; 5464 case QLA_EVT_AENFX: 5465 qlafx00_process_aen(vha, e); 5466 break; 5467 case QLA_EVT_GPNID: 5468 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5469 break; 5470 case QLA_EVT_UNMAP: 5471 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5472 break; 5473 case QLA_EVT_RELOGIN: 5474 qla2x00_relogin(vha); 5475 break; 5476 case QLA_EVT_NEW_SESS: 5477 qla24xx_create_new_sess(vha, e); 5478 break; 5479 case QLA_EVT_GPDB: 5480 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5481 e->u.fcport.opt); 5482 break; 5483 case QLA_EVT_PRLI: 5484 qla24xx_async_prli(vha, e->u.fcport.fcport); 5485 break; 5486 case QLA_EVT_GPSC: 5487 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5488 break; 5489 case QLA_EVT_GNL: 5490 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5491 break; 5492 case QLA_EVT_NACK: 5493 qla24xx_do_nack_work(vha, e); 5494 break; 5495 case QLA_EVT_ASYNC_PRLO: 5496 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5497 break; 5498 case QLA_EVT_ASYNC_PRLO_DONE: 5499 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5500 e->u.logio.data); 5501 break; 5502 case QLA_EVT_GPNFT: 5503 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5504 e->u.gpnft.sp); 5505 break; 5506 case QLA_EVT_GPNFT_DONE: 5507 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5508 break; 5509 case QLA_EVT_GNNFT_DONE: 5510 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5511 break; 5512 case QLA_EVT_GNNID: 5513 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5514 break; 5515 case QLA_EVT_GFPNID: 5516 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5517 break; 5518 case QLA_EVT_SP_RETRY: 5519 qla_sp_retry(vha, e); 5520 break; 5521 case QLA_EVT_IIDMA: 5522 qla_do_iidma_work(vha, e->u.fcport.fcport); 5523 break; 5524 case QLA_EVT_ELS_PLOGI: 5525 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5526 e->u.fcport.fcport, false); 5527 break; 5528 case QLA_EVT_SA_REPLACE: 5529 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5530 break; 5531 } 5532 5533 if (rc == EAGAIN) { 5534 /* put 'work' at head of 'vha->work_list' */ 5535 spin_lock_irqsave(&vha->work_lock, flags); 5536 list_splice(&work, &vha->work_list); 5537 spin_unlock_irqrestore(&vha->work_lock, flags); 5538 break; 5539 } 5540 list_del_init(&e->list); 5541 if (e->flags & QLA_EVT_FLAG_FREE) 5542 kfree(e); 5543 5544 /* For each work completed decrement vha ref count */ 5545 QLA_VHA_MARK_NOT_BUSY(vha); 5546 } 5547 } 5548 5549 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5550 { 5551 struct qla_work_evt *e; 5552 5553 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5554 5555 if (!e) { 5556 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5557 return QLA_FUNCTION_FAILED; 5558 } 5559 5560 return qla2x00_post_work(vha, e); 5561 } 5562 5563 /* Relogins all the fcports of a vport 5564 * Context: dpc thread 5565 */ 5566 void qla2x00_relogin(struct scsi_qla_host *vha) 5567 { 5568 fc_port_t *fcport; 5569 int status, relogin_needed = 0; 5570 struct event_arg ea; 5571 5572 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5573 /* 5574 * If the port is not ONLINE then try to login 5575 * to it if we haven't run out of retries. 5576 */ 5577 if (atomic_read(&fcport->state) != FCS_ONLINE && 5578 fcport->login_retry) { 5579 if (fcport->scan_state != QLA_FCPORT_FOUND || 5580 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5581 fcport->disc_state == DSC_LOGIN_COMPLETE) 5582 continue; 5583 5584 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5585 fcport->disc_state == DSC_DELETE_PEND) { 5586 relogin_needed = 1; 5587 } else { 5588 if (vha->hw->current_topology != ISP_CFG_NL) { 5589 memset(&ea, 0, sizeof(ea)); 5590 ea.fcport = fcport; 5591 qla24xx_handle_relogin_event(vha, &ea); 5592 } else if (vha->hw->current_topology == 5593 ISP_CFG_NL && 5594 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5595 (void)qla24xx_fcport_handle_login(vha, 5596 fcport); 5597 } else if (vha->hw->current_topology == 5598 ISP_CFG_NL) { 5599 fcport->login_retry--; 5600 status = 5601 qla2x00_local_device_login(vha, 5602 fcport); 5603 if (status == QLA_SUCCESS) { 5604 fcport->old_loop_id = 5605 fcport->loop_id; 5606 ql_dbg(ql_dbg_disc, vha, 0x2003, 5607 "Port login OK: logged in ID 0x%x.\n", 5608 fcport->loop_id); 5609 qla2x00_update_fcport 5610 (vha, fcport); 5611 } else if (status == 1) { 5612 set_bit(RELOGIN_NEEDED, 5613 &vha->dpc_flags); 5614 /* retry the login again */ 5615 ql_dbg(ql_dbg_disc, vha, 0x2007, 5616 "Retrying %d login again loop_id 0x%x.\n", 5617 fcport->login_retry, 5618 fcport->loop_id); 5619 } else { 5620 fcport->login_retry = 0; 5621 } 5622 5623 if (fcport->login_retry == 0 && 5624 status != QLA_SUCCESS) 5625 qla2x00_clear_loop_id(fcport); 5626 } 5627 } 5628 } 5629 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5630 break; 5631 } 5632 5633 if (relogin_needed) 5634 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5635 5636 ql_dbg(ql_dbg_disc, vha, 0x400e, 5637 "Relogin end.\n"); 5638 } 5639 5640 /* Schedule work on any of the dpc-workqueues */ 5641 void 5642 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5643 { 5644 struct qla_hw_data *ha = base_vha->hw; 5645 5646 switch (work_code) { 5647 case MBA_IDC_AEN: /* 0x8200 */ 5648 if (ha->dpc_lp_wq) 5649 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5650 break; 5651 5652 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5653 if (!ha->flags.nic_core_reset_hdlr_active) { 5654 if (ha->dpc_hp_wq) 5655 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5656 } else 5657 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5658 "NIC Core reset is already active. Skip " 5659 "scheduling it again.\n"); 5660 break; 5661 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5662 if (ha->dpc_hp_wq) 5663 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5664 break; 5665 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5666 if (ha->dpc_hp_wq) 5667 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5668 break; 5669 default: 5670 ql_log(ql_log_warn, base_vha, 0xb05f, 5671 "Unknown work-code=0x%x.\n", work_code); 5672 } 5673 5674 return; 5675 } 5676 5677 /* Work: Perform NIC Core Unrecoverable state handling */ 5678 void 5679 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5680 { 5681 struct qla_hw_data *ha = 5682 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5683 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5684 uint32_t dev_state = 0; 5685 5686 qla83xx_idc_lock(base_vha, 0); 5687 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5688 qla83xx_reset_ownership(base_vha); 5689 if (ha->flags.nic_core_reset_owner) { 5690 ha->flags.nic_core_reset_owner = 0; 5691 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5692 QLA8XXX_DEV_FAILED); 5693 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5694 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5695 } 5696 qla83xx_idc_unlock(base_vha, 0); 5697 } 5698 5699 /* Work: Execute IDC state handler */ 5700 void 5701 qla83xx_idc_state_handler_work(struct work_struct *work) 5702 { 5703 struct qla_hw_data *ha = 5704 container_of(work, struct qla_hw_data, idc_state_handler); 5705 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5706 uint32_t dev_state = 0; 5707 5708 qla83xx_idc_lock(base_vha, 0); 5709 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5710 if (dev_state == QLA8XXX_DEV_FAILED || 5711 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5712 qla83xx_idc_state_handler(base_vha); 5713 qla83xx_idc_unlock(base_vha, 0); 5714 } 5715 5716 static int 5717 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5718 { 5719 int rval = QLA_SUCCESS; 5720 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5721 uint32_t heart_beat_counter1, heart_beat_counter2; 5722 5723 do { 5724 if (time_after(jiffies, heart_beat_wait)) { 5725 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5726 "Nic Core f/w is not alive.\n"); 5727 rval = QLA_FUNCTION_FAILED; 5728 break; 5729 } 5730 5731 qla83xx_idc_lock(base_vha, 0); 5732 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5733 &heart_beat_counter1); 5734 qla83xx_idc_unlock(base_vha, 0); 5735 msleep(100); 5736 qla83xx_idc_lock(base_vha, 0); 5737 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5738 &heart_beat_counter2); 5739 qla83xx_idc_unlock(base_vha, 0); 5740 } while (heart_beat_counter1 == heart_beat_counter2); 5741 5742 return rval; 5743 } 5744 5745 /* Work: Perform NIC Core Reset handling */ 5746 void 5747 qla83xx_nic_core_reset_work(struct work_struct *work) 5748 { 5749 struct qla_hw_data *ha = 5750 container_of(work, struct qla_hw_data, nic_core_reset); 5751 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5752 uint32_t dev_state = 0; 5753 5754 if (IS_QLA2031(ha)) { 5755 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5756 ql_log(ql_log_warn, base_vha, 0xb081, 5757 "Failed to dump mctp\n"); 5758 return; 5759 } 5760 5761 if (!ha->flags.nic_core_reset_hdlr_active) { 5762 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5763 qla83xx_idc_lock(base_vha, 0); 5764 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5765 &dev_state); 5766 qla83xx_idc_unlock(base_vha, 0); 5767 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5768 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5769 "Nic Core f/w is alive.\n"); 5770 return; 5771 } 5772 } 5773 5774 ha->flags.nic_core_reset_hdlr_active = 1; 5775 if (qla83xx_nic_core_reset(base_vha)) { 5776 /* NIC Core reset failed. */ 5777 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5778 "NIC Core reset failed.\n"); 5779 } 5780 ha->flags.nic_core_reset_hdlr_active = 0; 5781 } 5782 } 5783 5784 /* Work: Handle 8200 IDC aens */ 5785 void 5786 qla83xx_service_idc_aen(struct work_struct *work) 5787 { 5788 struct qla_hw_data *ha = 5789 container_of(work, struct qla_hw_data, idc_aen); 5790 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5791 uint32_t dev_state, idc_control; 5792 5793 qla83xx_idc_lock(base_vha, 0); 5794 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5795 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5796 qla83xx_idc_unlock(base_vha, 0); 5797 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5798 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5799 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5800 "Application requested NIC Core Reset.\n"); 5801 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5802 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5803 QLA_SUCCESS) { 5804 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5805 "Other protocol driver requested NIC Core Reset.\n"); 5806 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5807 } 5808 } else if (dev_state == QLA8XXX_DEV_FAILED || 5809 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5810 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5811 } 5812 } 5813 5814 /* 5815 * Control the frequency of IDC lock retries 5816 */ 5817 #define QLA83XX_WAIT_LOGIC_MS 100 5818 5819 static int 5820 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5821 { 5822 int rval; 5823 uint32_t data; 5824 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5825 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5826 struct qla_hw_data *ha = base_vha->hw; 5827 5828 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5829 "Trying force recovery of the IDC lock.\n"); 5830 5831 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5832 if (rval) 5833 return rval; 5834 5835 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5836 return QLA_SUCCESS; 5837 } else { 5838 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5839 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5840 data); 5841 if (rval) 5842 return rval; 5843 5844 msleep(200); 5845 5846 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5847 &data); 5848 if (rval) 5849 return rval; 5850 5851 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5852 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5853 ~(idc_lck_rcvry_stage_mask)); 5854 rval = qla83xx_wr_reg(base_vha, 5855 QLA83XX_IDC_LOCK_RECOVERY, data); 5856 if (rval) 5857 return rval; 5858 5859 /* Forcefully perform IDC UnLock */ 5860 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5861 &data); 5862 if (rval) 5863 return rval; 5864 /* Clear lock-id by setting 0xff */ 5865 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5866 0xff); 5867 if (rval) 5868 return rval; 5869 /* Clear lock-recovery by setting 0x0 */ 5870 rval = qla83xx_wr_reg(base_vha, 5871 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5872 if (rval) 5873 return rval; 5874 } else 5875 return QLA_SUCCESS; 5876 } 5877 5878 return rval; 5879 } 5880 5881 static int 5882 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5883 { 5884 int rval = QLA_SUCCESS; 5885 uint32_t o_drv_lockid, n_drv_lockid; 5886 unsigned long lock_recovery_timeout; 5887 5888 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5889 retry_lockid: 5890 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5891 if (rval) 5892 goto exit; 5893 5894 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5895 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5896 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5897 return QLA_SUCCESS; 5898 else 5899 return QLA_FUNCTION_FAILED; 5900 } 5901 5902 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5903 if (rval) 5904 goto exit; 5905 5906 if (o_drv_lockid == n_drv_lockid) { 5907 msleep(QLA83XX_WAIT_LOGIC_MS); 5908 goto retry_lockid; 5909 } else 5910 return QLA_SUCCESS; 5911 5912 exit: 5913 return rval; 5914 } 5915 5916 /* 5917 * Context: task, can sleep 5918 */ 5919 void 5920 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5921 { 5922 uint32_t data; 5923 uint32_t lock_owner; 5924 struct qla_hw_data *ha = base_vha->hw; 5925 5926 might_sleep(); 5927 5928 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5929 retry_lock: 5930 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5931 == QLA_SUCCESS) { 5932 if (data) { 5933 /* Setting lock-id to our function-number */ 5934 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5935 ha->portnum); 5936 } else { 5937 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5938 &lock_owner); 5939 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5940 "Failed to acquire IDC lock, acquired by %d, " 5941 "retrying...\n", lock_owner); 5942 5943 /* Retry/Perform IDC-Lock recovery */ 5944 if (qla83xx_idc_lock_recovery(base_vha) 5945 == QLA_SUCCESS) { 5946 msleep(QLA83XX_WAIT_LOGIC_MS); 5947 goto retry_lock; 5948 } else 5949 ql_log(ql_log_warn, base_vha, 0xb075, 5950 "IDC Lock recovery FAILED.\n"); 5951 } 5952 5953 } 5954 5955 return; 5956 } 5957 5958 static bool 5959 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5960 struct purex_entry_24xx *purex) 5961 { 5962 char fwstr[16]; 5963 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5964 struct port_database_24xx *pdb; 5965 5966 /* Domain Controller is always logged-out. */ 5967 /* if RDP request is not from Domain Controller: */ 5968 if (sid != 0xfffc01) 5969 return false; 5970 5971 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5972 5973 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5974 if (!pdb) { 5975 ql_dbg(ql_dbg_init, vha, 0x0181, 5976 "%s: Failed allocate pdb\n", __func__); 5977 } else if (qla24xx_get_port_database(vha, 5978 le16_to_cpu(purex->nport_handle), pdb)) { 5979 ql_dbg(ql_dbg_init, vha, 0x0181, 5980 "%s: Failed get pdb sid=%x\n", __func__, sid); 5981 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5982 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5983 ql_dbg(ql_dbg_init, vha, 0x0181, 5984 "%s: Port not logged in sid=%#x\n", __func__, sid); 5985 } else { 5986 /* RDP request is from logged in port */ 5987 kfree(pdb); 5988 return false; 5989 } 5990 kfree(pdb); 5991 5992 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5993 fwstr[strcspn(fwstr, " ")] = 0; 5994 /* if FW version allows RDP response length upto 2048 bytes: */ 5995 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5996 return false; 5997 5998 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5999 6000 /* RDP response length is to be reduced to maximum 256 bytes */ 6001 return true; 6002 } 6003 6004 /* 6005 * Function Name: qla24xx_process_purex_iocb 6006 * 6007 * Description: 6008 * Prepare a RDP response and send to Fabric switch 6009 * 6010 * PARAMETERS: 6011 * vha: SCSI qla host 6012 * purex: RDP request received by HBA 6013 */ 6014 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6015 struct purex_item *item) 6016 { 6017 struct qla_hw_data *ha = vha->hw; 6018 struct purex_entry_24xx *purex = 6019 (struct purex_entry_24xx *)&item->iocb; 6020 dma_addr_t rsp_els_dma; 6021 dma_addr_t rsp_payload_dma; 6022 dma_addr_t stat_dma; 6023 dma_addr_t sfp_dma; 6024 struct els_entry_24xx *rsp_els = NULL; 6025 struct rdp_rsp_payload *rsp_payload = NULL; 6026 struct link_statistics *stat = NULL; 6027 uint8_t *sfp = NULL; 6028 uint16_t sfp_flags = 0; 6029 uint rsp_payload_length = sizeof(*rsp_payload); 6030 int rval; 6031 6032 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6033 "%s: Enter\n", __func__); 6034 6035 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6036 "-------- ELS REQ -------\n"); 6037 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6038 purex, sizeof(*purex)); 6039 6040 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6041 rsp_payload_length = 6042 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6043 ql_dbg(ql_dbg_init, vha, 0x0181, 6044 "Reducing RSP payload length to %u bytes...\n", 6045 rsp_payload_length); 6046 } 6047 6048 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6049 &rsp_els_dma, GFP_KERNEL); 6050 if (!rsp_els) { 6051 ql_log(ql_log_warn, vha, 0x0183, 6052 "Failed allocate dma buffer ELS RSP.\n"); 6053 goto dealloc; 6054 } 6055 6056 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6057 &rsp_payload_dma, GFP_KERNEL); 6058 if (!rsp_payload) { 6059 ql_log(ql_log_warn, vha, 0x0184, 6060 "Failed allocate dma buffer ELS RSP payload.\n"); 6061 goto dealloc; 6062 } 6063 6064 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6065 &sfp_dma, GFP_KERNEL); 6066 6067 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6068 &stat_dma, GFP_KERNEL); 6069 6070 /* Prepare Response IOCB */ 6071 rsp_els->entry_type = ELS_IOCB_TYPE; 6072 rsp_els->entry_count = 1; 6073 rsp_els->sys_define = 0; 6074 rsp_els->entry_status = 0; 6075 rsp_els->handle = 0; 6076 rsp_els->nport_handle = purex->nport_handle; 6077 rsp_els->tx_dsd_count = cpu_to_le16(1); 6078 rsp_els->vp_index = purex->vp_idx; 6079 rsp_els->sof_type = EST_SOFI3; 6080 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6081 rsp_els->rx_dsd_count = 0; 6082 rsp_els->opcode = purex->els_frame_payload[0]; 6083 6084 rsp_els->d_id[0] = purex->s_id[0]; 6085 rsp_els->d_id[1] = purex->s_id[1]; 6086 rsp_els->d_id[2] = purex->s_id[2]; 6087 6088 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6089 rsp_els->rx_byte_count = 0; 6090 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6091 6092 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6093 rsp_els->tx_len = rsp_els->tx_byte_count; 6094 6095 rsp_els->rx_address = 0; 6096 rsp_els->rx_len = 0; 6097 6098 /* Prepare Response Payload */ 6099 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6100 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6101 sizeof(rsp_payload->hdr)); 6102 6103 /* Link service Request Info Descriptor */ 6104 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6105 rsp_payload->ls_req_info_desc.desc_len = 6106 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6107 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6108 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6109 6110 /* Link service Request Info Descriptor 2 */ 6111 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6112 rsp_payload->ls_req_info_desc2.desc_len = 6113 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6114 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6115 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6116 6117 6118 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6119 rsp_payload->sfp_diag_desc.desc_len = 6120 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6121 6122 if (sfp) { 6123 /* SFP Flags */ 6124 memset(sfp, 0, SFP_RTDI_LEN); 6125 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6126 if (!rval) { 6127 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6128 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6129 sfp_flags |= BIT_0; /* short wave */ 6130 else if (sfp[0] & BIT_1) 6131 sfp_flags |= BIT_1; /* long wave 1310nm */ 6132 else if (sfp[1] & BIT_4) 6133 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6134 } 6135 6136 /* SFP Type */ 6137 memset(sfp, 0, SFP_RTDI_LEN); 6138 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6139 if (!rval) { 6140 sfp_flags |= BIT_4; /* optical */ 6141 if (sfp[0] == 0x3) 6142 sfp_flags |= BIT_6; /* sfp+ */ 6143 } 6144 6145 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6146 6147 /* SFP Diagnostics */ 6148 memset(sfp, 0, SFP_RTDI_LEN); 6149 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6150 if (!rval) { 6151 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6152 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6153 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6154 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6155 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6156 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6157 } 6158 } 6159 6160 /* Port Speed Descriptor */ 6161 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6162 rsp_payload->port_speed_desc.desc_len = 6163 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6164 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6165 qla25xx_fdmi_port_speed_capability(ha)); 6166 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6167 qla25xx_fdmi_port_speed_currently(ha)); 6168 6169 /* Link Error Status Descriptor */ 6170 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6171 rsp_payload->ls_err_desc.desc_len = 6172 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6173 6174 if (stat) { 6175 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6176 if (!rval) { 6177 rsp_payload->ls_err_desc.link_fail_cnt = 6178 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6179 rsp_payload->ls_err_desc.loss_sync_cnt = 6180 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6181 rsp_payload->ls_err_desc.loss_sig_cnt = 6182 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6183 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6184 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6185 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6186 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6187 rsp_payload->ls_err_desc.inval_crc_cnt = 6188 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6189 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6190 } 6191 } 6192 6193 /* Portname Descriptor */ 6194 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6195 rsp_payload->port_name_diag_desc.desc_len = 6196 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6197 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6198 vha->node_name, 6199 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6200 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6201 vha->port_name, 6202 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6203 6204 /* F-Port Portname Descriptor */ 6205 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6206 rsp_payload->port_name_direct_desc.desc_len = 6207 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6208 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6209 vha->fabric_node_name, 6210 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6211 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6212 vha->fabric_port_name, 6213 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6214 6215 /* Bufer Credit Descriptor */ 6216 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6217 rsp_payload->buffer_credit_desc.desc_len = 6218 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6219 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6220 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6221 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6222 6223 if (ha->flags.plogi_template_valid) { 6224 uint32_t tmp = 6225 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6226 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6227 } 6228 6229 if (rsp_payload_length < sizeof(*rsp_payload)) 6230 goto send; 6231 6232 /* Optical Element Descriptor, Temperature */ 6233 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6234 rsp_payload->optical_elmt_desc[0].desc_len = 6235 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6236 /* Optical Element Descriptor, Voltage */ 6237 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6238 rsp_payload->optical_elmt_desc[1].desc_len = 6239 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6240 /* Optical Element Descriptor, Tx Bias Current */ 6241 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6242 rsp_payload->optical_elmt_desc[2].desc_len = 6243 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6244 /* Optical Element Descriptor, Tx Power */ 6245 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6246 rsp_payload->optical_elmt_desc[3].desc_len = 6247 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6248 /* Optical Element Descriptor, Rx Power */ 6249 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6250 rsp_payload->optical_elmt_desc[4].desc_len = 6251 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6252 6253 if (sfp) { 6254 memset(sfp, 0, SFP_RTDI_LEN); 6255 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6256 if (!rval) { 6257 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6258 6259 /* Optical Element Descriptor, Temperature */ 6260 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6261 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6262 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6263 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6264 rsp_payload->optical_elmt_desc[0].element_flags = 6265 cpu_to_be32(1 << 28); 6266 6267 /* Optical Element Descriptor, Voltage */ 6268 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6269 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6270 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6271 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6272 rsp_payload->optical_elmt_desc[1].element_flags = 6273 cpu_to_be32(2 << 28); 6274 6275 /* Optical Element Descriptor, Tx Bias Current */ 6276 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6277 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6278 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6279 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6280 rsp_payload->optical_elmt_desc[2].element_flags = 6281 cpu_to_be32(3 << 28); 6282 6283 /* Optical Element Descriptor, Tx Power */ 6284 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6285 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6286 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6287 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6288 rsp_payload->optical_elmt_desc[3].element_flags = 6289 cpu_to_be32(4 << 28); 6290 6291 /* Optical Element Descriptor, Rx Power */ 6292 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6293 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6294 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6295 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6296 rsp_payload->optical_elmt_desc[4].element_flags = 6297 cpu_to_be32(5 << 28); 6298 } 6299 6300 memset(sfp, 0, SFP_RTDI_LEN); 6301 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6302 if (!rval) { 6303 /* Temperature high/low alarm/warning */ 6304 rsp_payload->optical_elmt_desc[0].element_flags |= 6305 cpu_to_be32( 6306 (sfp[0] >> 7 & 1) << 3 | 6307 (sfp[0] >> 6 & 1) << 2 | 6308 (sfp[4] >> 7 & 1) << 1 | 6309 (sfp[4] >> 6 & 1) << 0); 6310 6311 /* Voltage high/low alarm/warning */ 6312 rsp_payload->optical_elmt_desc[1].element_flags |= 6313 cpu_to_be32( 6314 (sfp[0] >> 5 & 1) << 3 | 6315 (sfp[0] >> 4 & 1) << 2 | 6316 (sfp[4] >> 5 & 1) << 1 | 6317 (sfp[4] >> 4 & 1) << 0); 6318 6319 /* Tx Bias Current high/low alarm/warning */ 6320 rsp_payload->optical_elmt_desc[2].element_flags |= 6321 cpu_to_be32( 6322 (sfp[0] >> 3 & 1) << 3 | 6323 (sfp[0] >> 2 & 1) << 2 | 6324 (sfp[4] >> 3 & 1) << 1 | 6325 (sfp[4] >> 2 & 1) << 0); 6326 6327 /* Tx Power high/low alarm/warning */ 6328 rsp_payload->optical_elmt_desc[3].element_flags |= 6329 cpu_to_be32( 6330 (sfp[0] >> 1 & 1) << 3 | 6331 (sfp[0] >> 0 & 1) << 2 | 6332 (sfp[4] >> 1 & 1) << 1 | 6333 (sfp[4] >> 0 & 1) << 0); 6334 6335 /* Rx Power high/low alarm/warning */ 6336 rsp_payload->optical_elmt_desc[4].element_flags |= 6337 cpu_to_be32( 6338 (sfp[1] >> 7 & 1) << 3 | 6339 (sfp[1] >> 6 & 1) << 2 | 6340 (sfp[5] >> 7 & 1) << 1 | 6341 (sfp[5] >> 6 & 1) << 0); 6342 } 6343 } 6344 6345 /* Optical Product Data Descriptor */ 6346 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6347 rsp_payload->optical_prod_desc.desc_len = 6348 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6349 6350 if (sfp) { 6351 memset(sfp, 0, SFP_RTDI_LEN); 6352 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6353 if (!rval) { 6354 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6355 sfp + 0, 6356 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6357 memcpy(rsp_payload->optical_prod_desc.part_number, 6358 sfp + 20, 6359 sizeof(rsp_payload->optical_prod_desc.part_number)); 6360 memcpy(rsp_payload->optical_prod_desc.revision, 6361 sfp + 36, 6362 sizeof(rsp_payload->optical_prod_desc.revision)); 6363 memcpy(rsp_payload->optical_prod_desc.serial_number, 6364 sfp + 48, 6365 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6366 } 6367 6368 memset(sfp, 0, SFP_RTDI_LEN); 6369 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6370 if (!rval) { 6371 memcpy(rsp_payload->optical_prod_desc.date, 6372 sfp + 0, 6373 sizeof(rsp_payload->optical_prod_desc.date)); 6374 } 6375 } 6376 6377 send: 6378 ql_dbg(ql_dbg_init, vha, 0x0183, 6379 "Sending ELS Response to RDP Request...\n"); 6380 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6381 "-------- ELS RSP -------\n"); 6382 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6383 rsp_els, sizeof(*rsp_els)); 6384 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6385 "-------- ELS RSP PAYLOAD -------\n"); 6386 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6387 rsp_payload, rsp_payload_length); 6388 6389 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6390 6391 if (rval) { 6392 ql_log(ql_log_warn, vha, 0x0188, 6393 "%s: iocb failed to execute -> %x\n", __func__, rval); 6394 } else if (rsp_els->comp_status) { 6395 ql_log(ql_log_warn, vha, 0x0189, 6396 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6397 __func__, rsp_els->comp_status, 6398 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6399 } else { 6400 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6401 } 6402 6403 dealloc: 6404 if (stat) 6405 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6406 stat, stat_dma); 6407 if (sfp) 6408 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6409 sfp, sfp_dma); 6410 if (rsp_payload) 6411 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6412 rsp_payload, rsp_payload_dma); 6413 if (rsp_els) 6414 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6415 rsp_els, rsp_els_dma); 6416 } 6417 6418 void 6419 qla24xx_free_purex_item(struct purex_item *item) 6420 { 6421 if (item == &item->vha->default_item) 6422 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6423 else 6424 kfree(item); 6425 } 6426 6427 void qla24xx_process_purex_list(struct purex_list *list) 6428 { 6429 struct list_head head = LIST_HEAD_INIT(head); 6430 struct purex_item *item, *next; 6431 ulong flags; 6432 6433 spin_lock_irqsave(&list->lock, flags); 6434 list_splice_init(&list->head, &head); 6435 spin_unlock_irqrestore(&list->lock, flags); 6436 6437 list_for_each_entry_safe(item, next, &head, list) { 6438 list_del(&item->list); 6439 item->process_item(item->vha, item); 6440 qla24xx_free_purex_item(item); 6441 } 6442 } 6443 6444 /* 6445 * Context: task, can sleep 6446 */ 6447 void 6448 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6449 { 6450 #if 0 6451 uint16_t options = (requester_id << 15) | BIT_7; 6452 #endif 6453 uint16_t retry; 6454 uint32_t data; 6455 struct qla_hw_data *ha = base_vha->hw; 6456 6457 might_sleep(); 6458 6459 /* IDC-unlock implementation using driver-unlock/lock-id 6460 * remote registers 6461 */ 6462 retry = 0; 6463 retry_unlock: 6464 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6465 == QLA_SUCCESS) { 6466 if (data == ha->portnum) { 6467 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6468 /* Clearing lock-id by setting 0xff */ 6469 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6470 } else if (retry < 10) { 6471 /* SV: XXX: IDC unlock retrying needed here? */ 6472 6473 /* Retry for IDC-unlock */ 6474 msleep(QLA83XX_WAIT_LOGIC_MS); 6475 retry++; 6476 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6477 "Failed to release IDC lock, retrying=%d\n", retry); 6478 goto retry_unlock; 6479 } 6480 } else if (retry < 10) { 6481 /* Retry for IDC-unlock */ 6482 msleep(QLA83XX_WAIT_LOGIC_MS); 6483 retry++; 6484 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6485 "Failed to read drv-lockid, retrying=%d\n", retry); 6486 goto retry_unlock; 6487 } 6488 6489 return; 6490 6491 #if 0 6492 /* XXX: IDC-unlock implementation using access-control mbx */ 6493 retry = 0; 6494 retry_unlock2: 6495 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6496 if (retry < 10) { 6497 /* Retry for IDC-unlock */ 6498 msleep(QLA83XX_WAIT_LOGIC_MS); 6499 retry++; 6500 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6501 "Failed to release IDC lock, retrying=%d\n", retry); 6502 goto retry_unlock2; 6503 } 6504 } 6505 6506 return; 6507 #endif 6508 } 6509 6510 int 6511 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6512 { 6513 int rval = QLA_SUCCESS; 6514 struct qla_hw_data *ha = vha->hw; 6515 uint32_t drv_presence; 6516 6517 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6518 if (rval == QLA_SUCCESS) { 6519 drv_presence |= (1 << ha->portnum); 6520 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6521 drv_presence); 6522 } 6523 6524 return rval; 6525 } 6526 6527 int 6528 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6529 { 6530 int rval = QLA_SUCCESS; 6531 6532 qla83xx_idc_lock(vha, 0); 6533 rval = __qla83xx_set_drv_presence(vha); 6534 qla83xx_idc_unlock(vha, 0); 6535 6536 return rval; 6537 } 6538 6539 int 6540 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6541 { 6542 int rval = QLA_SUCCESS; 6543 struct qla_hw_data *ha = vha->hw; 6544 uint32_t drv_presence; 6545 6546 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6547 if (rval == QLA_SUCCESS) { 6548 drv_presence &= ~(1 << ha->portnum); 6549 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6550 drv_presence); 6551 } 6552 6553 return rval; 6554 } 6555 6556 int 6557 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6558 { 6559 int rval = QLA_SUCCESS; 6560 6561 qla83xx_idc_lock(vha, 0); 6562 rval = __qla83xx_clear_drv_presence(vha); 6563 qla83xx_idc_unlock(vha, 0); 6564 6565 return rval; 6566 } 6567 6568 static void 6569 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6570 { 6571 struct qla_hw_data *ha = vha->hw; 6572 uint32_t drv_ack, drv_presence; 6573 unsigned long ack_timeout; 6574 6575 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6576 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6577 while (1) { 6578 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6579 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6580 if ((drv_ack & drv_presence) == drv_presence) 6581 break; 6582 6583 if (time_after_eq(jiffies, ack_timeout)) { 6584 ql_log(ql_log_warn, vha, 0xb067, 6585 "RESET ACK TIMEOUT! drv_presence=0x%x " 6586 "drv_ack=0x%x\n", drv_presence, drv_ack); 6587 /* 6588 * The function(s) which did not ack in time are forced 6589 * to withdraw any further participation in the IDC 6590 * reset. 6591 */ 6592 if (drv_ack != drv_presence) 6593 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6594 drv_ack); 6595 break; 6596 } 6597 6598 qla83xx_idc_unlock(vha, 0); 6599 msleep(1000); 6600 qla83xx_idc_lock(vha, 0); 6601 } 6602 6603 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6604 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6605 } 6606 6607 static int 6608 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6609 { 6610 int rval = QLA_SUCCESS; 6611 uint32_t idc_control; 6612 6613 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6614 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6615 6616 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6617 __qla83xx_get_idc_control(vha, &idc_control); 6618 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6619 __qla83xx_set_idc_control(vha, 0); 6620 6621 qla83xx_idc_unlock(vha, 0); 6622 rval = qla83xx_restart_nic_firmware(vha); 6623 qla83xx_idc_lock(vha, 0); 6624 6625 if (rval != QLA_SUCCESS) { 6626 ql_log(ql_log_fatal, vha, 0xb06a, 6627 "Failed to restart NIC f/w.\n"); 6628 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6629 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6630 } else { 6631 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6632 "Success in restarting nic f/w.\n"); 6633 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6634 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6635 } 6636 6637 return rval; 6638 } 6639 6640 /* Assumes idc_lock always held on entry */ 6641 int 6642 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6643 { 6644 struct qla_hw_data *ha = base_vha->hw; 6645 int rval = QLA_SUCCESS; 6646 unsigned long dev_init_timeout; 6647 uint32_t dev_state; 6648 6649 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6650 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6651 6652 while (1) { 6653 6654 if (time_after_eq(jiffies, dev_init_timeout)) { 6655 ql_log(ql_log_warn, base_vha, 0xb06e, 6656 "Initialization TIMEOUT!\n"); 6657 /* Init timeout. Disable further NIC Core 6658 * communication. 6659 */ 6660 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6661 QLA8XXX_DEV_FAILED); 6662 ql_log(ql_log_info, base_vha, 0xb06f, 6663 "HW State: FAILED.\n"); 6664 } 6665 6666 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6667 switch (dev_state) { 6668 case QLA8XXX_DEV_READY: 6669 if (ha->flags.nic_core_reset_owner) 6670 qla83xx_idc_audit(base_vha, 6671 IDC_AUDIT_COMPLETION); 6672 ha->flags.nic_core_reset_owner = 0; 6673 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6674 "Reset_owner reset by 0x%x.\n", 6675 ha->portnum); 6676 goto exit; 6677 case QLA8XXX_DEV_COLD: 6678 if (ha->flags.nic_core_reset_owner) 6679 rval = qla83xx_device_bootstrap(base_vha); 6680 else { 6681 /* Wait for AEN to change device-state */ 6682 qla83xx_idc_unlock(base_vha, 0); 6683 msleep(1000); 6684 qla83xx_idc_lock(base_vha, 0); 6685 } 6686 break; 6687 case QLA8XXX_DEV_INITIALIZING: 6688 /* Wait for AEN to change device-state */ 6689 qla83xx_idc_unlock(base_vha, 0); 6690 msleep(1000); 6691 qla83xx_idc_lock(base_vha, 0); 6692 break; 6693 case QLA8XXX_DEV_NEED_RESET: 6694 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6695 qla83xx_need_reset_handler(base_vha); 6696 else { 6697 /* Wait for AEN to change device-state */ 6698 qla83xx_idc_unlock(base_vha, 0); 6699 msleep(1000); 6700 qla83xx_idc_lock(base_vha, 0); 6701 } 6702 /* reset timeout value after need reset handler */ 6703 dev_init_timeout = jiffies + 6704 (ha->fcoe_dev_init_timeout * HZ); 6705 break; 6706 case QLA8XXX_DEV_NEED_QUIESCENT: 6707 /* XXX: DEBUG for now */ 6708 qla83xx_idc_unlock(base_vha, 0); 6709 msleep(1000); 6710 qla83xx_idc_lock(base_vha, 0); 6711 break; 6712 case QLA8XXX_DEV_QUIESCENT: 6713 /* XXX: DEBUG for now */ 6714 if (ha->flags.quiesce_owner) 6715 goto exit; 6716 6717 qla83xx_idc_unlock(base_vha, 0); 6718 msleep(1000); 6719 qla83xx_idc_lock(base_vha, 0); 6720 dev_init_timeout = jiffies + 6721 (ha->fcoe_dev_init_timeout * HZ); 6722 break; 6723 case QLA8XXX_DEV_FAILED: 6724 if (ha->flags.nic_core_reset_owner) 6725 qla83xx_idc_audit(base_vha, 6726 IDC_AUDIT_COMPLETION); 6727 ha->flags.nic_core_reset_owner = 0; 6728 __qla83xx_clear_drv_presence(base_vha); 6729 qla83xx_idc_unlock(base_vha, 0); 6730 qla8xxx_dev_failed_handler(base_vha); 6731 rval = QLA_FUNCTION_FAILED; 6732 qla83xx_idc_lock(base_vha, 0); 6733 goto exit; 6734 case QLA8XXX_BAD_VALUE: 6735 qla83xx_idc_unlock(base_vha, 0); 6736 msleep(1000); 6737 qla83xx_idc_lock(base_vha, 0); 6738 break; 6739 default: 6740 ql_log(ql_log_warn, base_vha, 0xb071, 6741 "Unknown Device State: %x.\n", dev_state); 6742 qla83xx_idc_unlock(base_vha, 0); 6743 qla8xxx_dev_failed_handler(base_vha); 6744 rval = QLA_FUNCTION_FAILED; 6745 qla83xx_idc_lock(base_vha, 0); 6746 goto exit; 6747 } 6748 } 6749 6750 exit: 6751 return rval; 6752 } 6753 6754 void 6755 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6756 { 6757 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6758 board_disable); 6759 struct pci_dev *pdev = ha->pdev; 6760 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6761 6762 ql_log(ql_log_warn, base_vha, 0x015b, 6763 "Disabling adapter.\n"); 6764 6765 if (!atomic_read(&pdev->enable_cnt)) { 6766 ql_log(ql_log_info, base_vha, 0xfffc, 6767 "PCI device disabled, no action req for PCI error=%lx\n", 6768 base_vha->pci_flags); 6769 return; 6770 } 6771 6772 /* 6773 * if UNLOADING flag is already set, then continue unload, 6774 * where it was set first. 6775 */ 6776 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6777 return; 6778 6779 qla2x00_wait_for_sess_deletion(base_vha); 6780 6781 qla2x00_delete_all_vps(ha, base_vha); 6782 6783 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6784 6785 qla2x00_dfs_remove(base_vha); 6786 6787 qla84xx_put_chip(base_vha); 6788 6789 if (base_vha->timer_active) 6790 qla2x00_stop_timer(base_vha); 6791 6792 base_vha->flags.online = 0; 6793 6794 qla2x00_destroy_deferred_work(ha); 6795 6796 /* 6797 * Do not try to stop beacon blink as it will issue a mailbox 6798 * command. 6799 */ 6800 qla2x00_free_sysfs_attr(base_vha, false); 6801 6802 fc_remove_host(base_vha->host); 6803 6804 scsi_remove_host(base_vha->host); 6805 6806 base_vha->flags.init_done = 0; 6807 qla25xx_delete_queues(base_vha); 6808 qla2x00_free_fcports(base_vha); 6809 qla2x00_free_irqs(base_vha); 6810 qla2x00_mem_free(ha); 6811 qla82xx_md_free(base_vha); 6812 qla2x00_free_queues(ha); 6813 6814 qla2x00_unmap_iobases(ha); 6815 6816 pci_release_selected_regions(ha->pdev, ha->bars); 6817 pci_disable_pcie_error_reporting(pdev); 6818 pci_disable_device(pdev); 6819 6820 /* 6821 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6822 */ 6823 } 6824 6825 /************************************************************************** 6826 * qla2x00_do_dpc 6827 * This kernel thread is a task that is schedule by the interrupt handler 6828 * to perform the background processing for interrupts. 6829 * 6830 * Notes: 6831 * This task always run in the context of a kernel thread. It 6832 * is kick-off by the driver's detect code and starts up 6833 * up one per adapter. It immediately goes to sleep and waits for 6834 * some fibre event. When either the interrupt handler or 6835 * the timer routine detects a event it will one of the task 6836 * bits then wake us up. 6837 **************************************************************************/ 6838 static int 6839 qla2x00_do_dpc(void *data) 6840 { 6841 scsi_qla_host_t *base_vha; 6842 struct qla_hw_data *ha; 6843 uint32_t online; 6844 struct qla_qpair *qpair; 6845 6846 ha = (struct qla_hw_data *)data; 6847 base_vha = pci_get_drvdata(ha->pdev); 6848 6849 set_user_nice(current, MIN_NICE); 6850 6851 set_current_state(TASK_INTERRUPTIBLE); 6852 while (!kthread_should_stop()) { 6853 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6854 "DPC handler sleeping.\n"); 6855 6856 schedule(); 6857 6858 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6859 qla_pci_set_eeh_busy(base_vha); 6860 6861 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6862 goto end_loop; 6863 6864 if (ha->flags.eeh_busy) { 6865 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6866 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6867 goto end_loop; 6868 } 6869 6870 ha->dpc_active = 1; 6871 6872 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6873 "DPC handler waking up, dpc_flags=0x%lx.\n", 6874 base_vha->dpc_flags); 6875 6876 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6877 break; 6878 6879 if (IS_P3P_TYPE(ha)) { 6880 if (IS_QLA8044(ha)) { 6881 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6882 &base_vha->dpc_flags)) { 6883 qla8044_idc_lock(ha); 6884 qla8044_wr_direct(base_vha, 6885 QLA8044_CRB_DEV_STATE_INDEX, 6886 QLA8XXX_DEV_FAILED); 6887 qla8044_idc_unlock(ha); 6888 ql_log(ql_log_info, base_vha, 0x4004, 6889 "HW State: FAILED.\n"); 6890 qla8044_device_state_handler(base_vha); 6891 continue; 6892 } 6893 6894 } else { 6895 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6896 &base_vha->dpc_flags)) { 6897 qla82xx_idc_lock(ha); 6898 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6899 QLA8XXX_DEV_FAILED); 6900 qla82xx_idc_unlock(ha); 6901 ql_log(ql_log_info, base_vha, 0x0151, 6902 "HW State: FAILED.\n"); 6903 qla82xx_device_state_handler(base_vha); 6904 continue; 6905 } 6906 } 6907 6908 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6909 &base_vha->dpc_flags)) { 6910 6911 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6912 "FCoE context reset scheduled.\n"); 6913 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6914 &base_vha->dpc_flags))) { 6915 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6916 /* FCoE-ctx reset failed. 6917 * Escalate to chip-reset 6918 */ 6919 set_bit(ISP_ABORT_NEEDED, 6920 &base_vha->dpc_flags); 6921 } 6922 clear_bit(ABORT_ISP_ACTIVE, 6923 &base_vha->dpc_flags); 6924 } 6925 6926 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6927 "FCoE context reset end.\n"); 6928 } 6929 } else if (IS_QLAFX00(ha)) { 6930 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6931 &base_vha->dpc_flags)) { 6932 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6933 "Firmware Reset Recovery\n"); 6934 if (qlafx00_reset_initialize(base_vha)) { 6935 /* Failed. Abort isp later. */ 6936 if (!test_bit(UNLOADING, 6937 &base_vha->dpc_flags)) { 6938 set_bit(ISP_UNRECOVERABLE, 6939 &base_vha->dpc_flags); 6940 ql_dbg(ql_dbg_dpc, base_vha, 6941 0x4021, 6942 "Reset Recovery Failed\n"); 6943 } 6944 } 6945 } 6946 6947 if (test_and_clear_bit(FX00_TARGET_SCAN, 6948 &base_vha->dpc_flags)) { 6949 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6950 "ISPFx00 Target Scan scheduled\n"); 6951 if (qlafx00_rescan_isp(base_vha)) { 6952 if (!test_bit(UNLOADING, 6953 &base_vha->dpc_flags)) 6954 set_bit(ISP_UNRECOVERABLE, 6955 &base_vha->dpc_flags); 6956 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6957 "ISPFx00 Target Scan Failed\n"); 6958 } 6959 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6960 "ISPFx00 Target Scan End\n"); 6961 } 6962 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6963 &base_vha->dpc_flags)) { 6964 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6965 "ISPFx00 Host Info resend scheduled\n"); 6966 qlafx00_fx_disc(base_vha, 6967 &base_vha->hw->mr.fcport, 6968 FXDISC_REG_HOST_INFO); 6969 } 6970 } 6971 6972 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6973 &base_vha->dpc_flags)) { 6974 /* Semantic: 6975 * - NO-OP -- await next ISP-ABORT. Preferred method 6976 * to minimize disruptions that will occur 6977 * when a forced chip-reset occurs. 6978 * - Force -- ISP-ABORT scheduled. 6979 */ 6980 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6981 } 6982 6983 if (test_and_clear_bit 6984 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6985 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6986 bool do_reset = true; 6987 6988 switch (base_vha->qlini_mode) { 6989 case QLA2XXX_INI_MODE_ENABLED: 6990 break; 6991 case QLA2XXX_INI_MODE_DISABLED: 6992 if (!qla_tgt_mode_enabled(base_vha) && 6993 !ha->flags.fw_started) 6994 do_reset = false; 6995 break; 6996 case QLA2XXX_INI_MODE_DUAL: 6997 if (!qla_dual_mode_enabled(base_vha) && 6998 !ha->flags.fw_started) 6999 do_reset = false; 7000 break; 7001 default: 7002 break; 7003 } 7004 7005 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7006 &base_vha->dpc_flags))) { 7007 base_vha->flags.online = 1; 7008 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7009 "ISP abort scheduled.\n"); 7010 if (ha->isp_ops->abort_isp(base_vha)) { 7011 /* failed. retry later */ 7012 set_bit(ISP_ABORT_NEEDED, 7013 &base_vha->dpc_flags); 7014 } 7015 clear_bit(ABORT_ISP_ACTIVE, 7016 &base_vha->dpc_flags); 7017 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7018 "ISP abort end.\n"); 7019 } 7020 } 7021 7022 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7023 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7024 qla24xx_process_purex_list 7025 (&base_vha->purex_list); 7026 clear_bit(PROCESS_PUREX_IOCB, 7027 &base_vha->dpc_flags); 7028 } 7029 } 7030 7031 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 7032 &base_vha->dpc_flags)) { 7033 qla2x00_update_fcports(base_vha); 7034 } 7035 7036 if (IS_QLAFX00(ha)) 7037 goto loop_resync_check; 7038 7039 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7040 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7041 "Quiescence mode scheduled.\n"); 7042 if (IS_P3P_TYPE(ha)) { 7043 if (IS_QLA82XX(ha)) 7044 qla82xx_device_state_handler(base_vha); 7045 if (IS_QLA8044(ha)) 7046 qla8044_device_state_handler(base_vha); 7047 clear_bit(ISP_QUIESCE_NEEDED, 7048 &base_vha->dpc_flags); 7049 if (!ha->flags.quiesce_owner) { 7050 qla2x00_perform_loop_resync(base_vha); 7051 if (IS_QLA82XX(ha)) { 7052 qla82xx_idc_lock(ha); 7053 qla82xx_clear_qsnt_ready( 7054 base_vha); 7055 qla82xx_idc_unlock(ha); 7056 } else if (IS_QLA8044(ha)) { 7057 qla8044_idc_lock(ha); 7058 qla8044_clear_qsnt_ready( 7059 base_vha); 7060 qla8044_idc_unlock(ha); 7061 } 7062 } 7063 } else { 7064 clear_bit(ISP_QUIESCE_NEEDED, 7065 &base_vha->dpc_flags); 7066 qla2x00_quiesce_io(base_vha); 7067 } 7068 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7069 "Quiescence mode end.\n"); 7070 } 7071 7072 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7073 &base_vha->dpc_flags) && 7074 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7075 7076 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7077 "Reset marker scheduled.\n"); 7078 qla2x00_rst_aen(base_vha); 7079 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7080 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7081 "Reset marker end.\n"); 7082 } 7083 7084 /* Retry each device up to login retry count */ 7085 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7086 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7087 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7088 7089 if (!base_vha->relogin_jif || 7090 time_after_eq(jiffies, base_vha->relogin_jif)) { 7091 base_vha->relogin_jif = jiffies + HZ; 7092 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7093 7094 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7095 "Relogin scheduled.\n"); 7096 qla24xx_post_relogin_work(base_vha); 7097 } 7098 } 7099 loop_resync_check: 7100 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 7101 &base_vha->dpc_flags)) { 7102 7103 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7104 "Loop resync scheduled.\n"); 7105 7106 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7107 &base_vha->dpc_flags))) { 7108 7109 qla2x00_loop_resync(base_vha); 7110 7111 clear_bit(LOOP_RESYNC_ACTIVE, 7112 &base_vha->dpc_flags); 7113 } 7114 7115 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7116 "Loop resync end.\n"); 7117 } 7118 7119 if (IS_QLAFX00(ha)) 7120 goto intr_on_check; 7121 7122 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7123 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7124 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7125 qla2xxx_flash_npiv_conf(base_vha); 7126 } 7127 7128 intr_on_check: 7129 if (!ha->interrupts_on) 7130 ha->isp_ops->enable_intrs(ha); 7131 7132 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7133 &base_vha->dpc_flags)) { 7134 if (ha->beacon_blink_led == 1) 7135 ha->isp_ops->beacon_blink(base_vha); 7136 } 7137 7138 /* qpair online check */ 7139 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7140 &base_vha->dpc_flags)) { 7141 if (ha->flags.eeh_busy || 7142 ha->flags.pci_channel_io_perm_failure) 7143 online = 0; 7144 else 7145 online = 1; 7146 7147 mutex_lock(&ha->mq_lock); 7148 list_for_each_entry(qpair, &base_vha->qp_list, 7149 qp_list_elem) 7150 qpair->online = online; 7151 mutex_unlock(&ha->mq_lock); 7152 } 7153 7154 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7155 &base_vha->dpc_flags)) { 7156 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7157 7158 if (threshold > ha->orig_fw_xcb_count) 7159 threshold = ha->orig_fw_xcb_count; 7160 7161 ql_log(ql_log_info, base_vha, 0xffffff, 7162 "SET ZIO Activity exchange threshold to %d.\n", 7163 threshold); 7164 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7165 ql_log(ql_log_info, base_vha, 0xffffff, 7166 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7167 threshold); 7168 } 7169 } 7170 7171 if (!IS_QLAFX00(ha)) 7172 qla2x00_do_dpc_all_vps(base_vha); 7173 7174 if (test_and_clear_bit(N2N_LINK_RESET, 7175 &base_vha->dpc_flags)) { 7176 qla2x00_lip_reset(base_vha); 7177 } 7178 7179 ha->dpc_active = 0; 7180 end_loop: 7181 set_current_state(TASK_INTERRUPTIBLE); 7182 } /* End of while(1) */ 7183 __set_current_state(TASK_RUNNING); 7184 7185 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7186 "DPC handler exiting.\n"); 7187 7188 /* 7189 * Make sure that nobody tries to wake us up again. 7190 */ 7191 ha->dpc_active = 0; 7192 7193 /* Cleanup any residual CTX SRBs. */ 7194 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7195 7196 return 0; 7197 } 7198 7199 void 7200 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7201 { 7202 struct qla_hw_data *ha = vha->hw; 7203 struct task_struct *t = ha->dpc_thread; 7204 7205 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7206 wake_up_process(t); 7207 } 7208 7209 /* 7210 * qla2x00_rst_aen 7211 * Processes asynchronous reset. 7212 * 7213 * Input: 7214 * ha = adapter block pointer. 7215 */ 7216 static void 7217 qla2x00_rst_aen(scsi_qla_host_t *vha) 7218 { 7219 if (vha->flags.online && !vha->flags.reset_active && 7220 !atomic_read(&vha->loop_down_timer) && 7221 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7222 do { 7223 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7224 7225 /* 7226 * Issue marker command only when we are going to start 7227 * the I/O. 7228 */ 7229 vha->marker_needed = 1; 7230 } while (!atomic_read(&vha->loop_down_timer) && 7231 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7232 } 7233 } 7234 7235 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7236 { 7237 struct qla_hw_data *ha = vha->hw; 7238 u32 cmpl_cnt; 7239 u16 i; 7240 bool do_heartbeat = false; 7241 7242 /* 7243 * Allow do_heartbeat only if we don’t have any active interrupts, 7244 * but there are still IOs outstanding with firmware. 7245 */ 7246 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7247 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7248 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7249 do_heartbeat = true; 7250 goto skip; 7251 } 7252 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7253 7254 for (i = 0; i < ha->max_qpairs; i++) { 7255 if (ha->queue_pair_map[i]) { 7256 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7257 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7258 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7259 do_heartbeat = true; 7260 break; 7261 } 7262 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7263 } 7264 } 7265 7266 skip: 7267 return do_heartbeat; 7268 } 7269 7270 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7271 { 7272 struct qla_hw_data *ha = vha->hw; 7273 7274 if (vha->vp_idx) 7275 return; 7276 7277 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7278 return; 7279 7280 /* 7281 * dpc thread cannot run if heartbeat is running at the same time. 7282 * We also do not want to starve heartbeat task. Therefore, do 7283 * heartbeat task at least once every 5 seconds. 7284 */ 7285 if (dpc_started && 7286 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7287 return; 7288 7289 if (qla_do_heartbeat(vha)) { 7290 ha->last_heartbeat_run_jiffies = jiffies; 7291 queue_work(ha->wq, &ha->heartbeat_work); 7292 } 7293 } 7294 7295 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7296 { 7297 struct qla_hw_data *ha = vha->hw; 7298 7299 if (!ha->flags.eeh_busy) 7300 return; 7301 if (ha->pci_error_state) 7302 /* system is trying to recover */ 7303 return; 7304 7305 /* 7306 * Current system is not handling PCIE error. At this point, this is 7307 * best effort to wind down the adapter. 7308 */ 7309 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7310 !ha->flags.eeh_flush) { 7311 ql_log(ql_log_info, vha, 0x9009, 7312 "PCI Error detected, attempting to reset hardware.\n"); 7313 7314 ha->isp_ops->reset_chip(vha); 7315 ha->isp_ops->disable_intrs(ha); 7316 7317 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7318 ha->eeh_jif = jiffies; 7319 7320 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7321 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7322 pci_clear_master(ha->pdev); 7323 7324 /* flush all command */ 7325 qla2x00_abort_isp_cleanup(vha); 7326 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7327 7328 ql_log(ql_log_info, vha, 0x900a, 7329 "PCI Error handling complete, all IOs aborted.\n"); 7330 } 7331 } 7332 7333 /************************************************************************** 7334 * qla2x00_timer 7335 * 7336 * Description: 7337 * One second timer 7338 * 7339 * Context: Interrupt 7340 ***************************************************************************/ 7341 void 7342 qla2x00_timer(struct timer_list *t) 7343 { 7344 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7345 unsigned long cpu_flags = 0; 7346 int start_dpc = 0; 7347 int index; 7348 srb_t *sp; 7349 uint16_t w; 7350 struct qla_hw_data *ha = vha->hw; 7351 struct req_que *req; 7352 unsigned long flags; 7353 fc_port_t *fcport = NULL; 7354 7355 if (ha->flags.eeh_busy) { 7356 qla_wind_down_chip(vha); 7357 7358 ql_dbg(ql_dbg_timer, vha, 0x6000, 7359 "EEH = %d, restarting timer.\n", 7360 ha->flags.eeh_busy); 7361 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7362 return; 7363 } 7364 7365 /* 7366 * Hardware read to raise pending EEH errors during mailbox waits. If 7367 * the read returns -1 then disable the board. 7368 */ 7369 if (!pci_channel_offline(ha->pdev)) { 7370 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7371 qla2x00_check_reg16_for_disconnect(vha, w); 7372 } 7373 7374 /* Make sure qla82xx_watchdog is run only for physical port */ 7375 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7376 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7377 start_dpc++; 7378 if (IS_QLA82XX(ha)) 7379 qla82xx_watchdog(vha); 7380 else if (IS_QLA8044(ha)) 7381 qla8044_watchdog(vha); 7382 } 7383 7384 if (!vha->vp_idx && IS_QLAFX00(ha)) 7385 qlafx00_timer_routine(vha); 7386 7387 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7388 vha->link_down_time++; 7389 7390 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7391 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7392 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7393 fcport->tgt_link_down_time++; 7394 } 7395 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7396 7397 /* Loop down handler. */ 7398 if (atomic_read(&vha->loop_down_timer) > 0 && 7399 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7400 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7401 && vha->flags.online) { 7402 7403 if (atomic_read(&vha->loop_down_timer) == 7404 vha->loop_down_abort_time) { 7405 7406 ql_log(ql_log_info, vha, 0x6008, 7407 "Loop down - aborting the queues before time expires.\n"); 7408 7409 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7410 atomic_set(&vha->loop_state, LOOP_DEAD); 7411 7412 /* 7413 * Schedule an ISP abort to return any FCP2-device 7414 * commands. 7415 */ 7416 /* NPIV - scan physical port only */ 7417 if (!vha->vp_idx) { 7418 spin_lock_irqsave(&ha->hardware_lock, 7419 cpu_flags); 7420 req = ha->req_q_map[0]; 7421 for (index = 1; 7422 index < req->num_outstanding_cmds; 7423 index++) { 7424 fc_port_t *sfcp; 7425 7426 sp = req->outstanding_cmds[index]; 7427 if (!sp) 7428 continue; 7429 if (sp->cmd_type != TYPE_SRB) 7430 continue; 7431 if (sp->type != SRB_SCSI_CMD) 7432 continue; 7433 sfcp = sp->fcport; 7434 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7435 continue; 7436 7437 if (IS_QLA82XX(ha)) 7438 set_bit(FCOE_CTX_RESET_NEEDED, 7439 &vha->dpc_flags); 7440 else 7441 set_bit(ISP_ABORT_NEEDED, 7442 &vha->dpc_flags); 7443 break; 7444 } 7445 spin_unlock_irqrestore(&ha->hardware_lock, 7446 cpu_flags); 7447 } 7448 start_dpc++; 7449 } 7450 7451 /* if the loop has been down for 4 minutes, reinit adapter */ 7452 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7453 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7454 ql_log(ql_log_warn, vha, 0x6009, 7455 "Loop down - aborting ISP.\n"); 7456 7457 if (IS_QLA82XX(ha)) 7458 set_bit(FCOE_CTX_RESET_NEEDED, 7459 &vha->dpc_flags); 7460 else 7461 set_bit(ISP_ABORT_NEEDED, 7462 &vha->dpc_flags); 7463 } 7464 } 7465 ql_dbg(ql_dbg_timer, vha, 0x600a, 7466 "Loop down - seconds remaining %d.\n", 7467 atomic_read(&vha->loop_down_timer)); 7468 } 7469 /* Check if beacon LED needs to be blinked for physical host only */ 7470 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7471 /* There is no beacon_blink function for ISP82xx */ 7472 if (!IS_P3P_TYPE(ha)) { 7473 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7474 start_dpc++; 7475 } 7476 } 7477 7478 /* check if edif running */ 7479 if (vha->hw->flags.edif_enabled) 7480 qla_edif_timer(vha); 7481 7482 /* Process any deferred work. */ 7483 if (!list_empty(&vha->work_list)) { 7484 unsigned long flags; 7485 bool q = false; 7486 7487 spin_lock_irqsave(&vha->work_lock, flags); 7488 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7489 q = true; 7490 spin_unlock_irqrestore(&vha->work_lock, flags); 7491 if (q) 7492 queue_work(vha->hw->wq, &vha->iocb_work); 7493 } 7494 7495 /* 7496 * FC-NVME 7497 * see if the active AEN count has changed from what was last reported. 7498 */ 7499 index = atomic_read(&ha->nvme_active_aen_cnt); 7500 if (!vha->vp_idx && 7501 (index != ha->nvme_last_rptd_aen) && 7502 ha->zio_mode == QLA_ZIO_MODE_6 && 7503 !ha->flags.host_shutting_down) { 7504 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7505 ql_log(ql_log_info, vha, 0x3002, 7506 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7507 ha->nvme_last_rptd_aen); 7508 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7509 start_dpc++; 7510 } 7511 7512 if (!vha->vp_idx && 7513 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7514 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7515 ql_log(ql_log_info, vha, 0x3002, 7516 "Sched: Set ZIO exchange threshold to %d.\n", 7517 ha->last_zio_threshold); 7518 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7519 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7520 start_dpc++; 7521 } 7522 7523 /* borrowing w to signify dpc will run */ 7524 w = 0; 7525 /* Schedule the DPC routine if needed */ 7526 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7527 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7528 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7529 start_dpc || 7530 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7531 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7532 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7533 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7534 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7535 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7536 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7537 ql_dbg(ql_dbg_timer, vha, 0x600b, 7538 "isp_abort_needed=%d loop_resync_needed=%d " 7539 "fcport_update_needed=%d start_dpc=%d " 7540 "reset_marker_needed=%d", 7541 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7542 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7543 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7544 start_dpc, 7545 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7546 ql_dbg(ql_dbg_timer, vha, 0x600c, 7547 "beacon_blink_needed=%d isp_unrecoverable=%d " 7548 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7549 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7550 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7551 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7552 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7553 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7554 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7555 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7556 qla2xxx_wake_dpc(vha); 7557 w = 1; 7558 } 7559 7560 qla_heart_beat(vha, w); 7561 7562 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7563 } 7564 7565 /* Firmware interface routines. */ 7566 7567 #define FW_ISP21XX 0 7568 #define FW_ISP22XX 1 7569 #define FW_ISP2300 2 7570 #define FW_ISP2322 3 7571 #define FW_ISP24XX 4 7572 #define FW_ISP25XX 5 7573 #define FW_ISP81XX 6 7574 #define FW_ISP82XX 7 7575 #define FW_ISP2031 8 7576 #define FW_ISP8031 9 7577 #define FW_ISP27XX 10 7578 #define FW_ISP28XX 11 7579 7580 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7581 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7582 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7583 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7584 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7585 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7586 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7587 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7588 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7589 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7590 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7591 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7592 7593 7594 static DEFINE_MUTEX(qla_fw_lock); 7595 7596 static struct fw_blob qla_fw_blobs[] = { 7597 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7598 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7599 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7600 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7601 { .name = FW_FILE_ISP24XX, }, 7602 { .name = FW_FILE_ISP25XX, }, 7603 { .name = FW_FILE_ISP81XX, }, 7604 { .name = FW_FILE_ISP82XX, }, 7605 { .name = FW_FILE_ISP2031, }, 7606 { .name = FW_FILE_ISP8031, }, 7607 { .name = FW_FILE_ISP27XX, }, 7608 { .name = FW_FILE_ISP28XX, }, 7609 { .name = NULL, }, 7610 }; 7611 7612 struct fw_blob * 7613 qla2x00_request_firmware(scsi_qla_host_t *vha) 7614 { 7615 struct qla_hw_data *ha = vha->hw; 7616 struct fw_blob *blob; 7617 7618 if (IS_QLA2100(ha)) { 7619 blob = &qla_fw_blobs[FW_ISP21XX]; 7620 } else if (IS_QLA2200(ha)) { 7621 blob = &qla_fw_blobs[FW_ISP22XX]; 7622 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7623 blob = &qla_fw_blobs[FW_ISP2300]; 7624 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7625 blob = &qla_fw_blobs[FW_ISP2322]; 7626 } else if (IS_QLA24XX_TYPE(ha)) { 7627 blob = &qla_fw_blobs[FW_ISP24XX]; 7628 } else if (IS_QLA25XX(ha)) { 7629 blob = &qla_fw_blobs[FW_ISP25XX]; 7630 } else if (IS_QLA81XX(ha)) { 7631 blob = &qla_fw_blobs[FW_ISP81XX]; 7632 } else if (IS_QLA82XX(ha)) { 7633 blob = &qla_fw_blobs[FW_ISP82XX]; 7634 } else if (IS_QLA2031(ha)) { 7635 blob = &qla_fw_blobs[FW_ISP2031]; 7636 } else if (IS_QLA8031(ha)) { 7637 blob = &qla_fw_blobs[FW_ISP8031]; 7638 } else if (IS_QLA27XX(ha)) { 7639 blob = &qla_fw_blobs[FW_ISP27XX]; 7640 } else if (IS_QLA28XX(ha)) { 7641 blob = &qla_fw_blobs[FW_ISP28XX]; 7642 } else { 7643 return NULL; 7644 } 7645 7646 if (!blob->name) 7647 return NULL; 7648 7649 mutex_lock(&qla_fw_lock); 7650 if (blob->fw) 7651 goto out; 7652 7653 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7654 ql_log(ql_log_warn, vha, 0x0063, 7655 "Failed to load firmware image (%s).\n", blob->name); 7656 blob->fw = NULL; 7657 blob = NULL; 7658 } 7659 7660 out: 7661 mutex_unlock(&qla_fw_lock); 7662 return blob; 7663 } 7664 7665 static void 7666 qla2x00_release_firmware(void) 7667 { 7668 struct fw_blob *blob; 7669 7670 mutex_lock(&qla_fw_lock); 7671 for (blob = qla_fw_blobs; blob->name; blob++) 7672 release_firmware(blob->fw); 7673 mutex_unlock(&qla_fw_lock); 7674 } 7675 7676 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7677 { 7678 struct qla_hw_data *ha = vha->hw; 7679 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7680 struct qla_qpair *qpair = NULL; 7681 struct scsi_qla_host *vp, *tvp; 7682 fc_port_t *fcport; 7683 int i; 7684 unsigned long flags; 7685 7686 ql_dbg(ql_dbg_aer, vha, 0x9000, 7687 "%s\n", __func__); 7688 ha->chip_reset++; 7689 7690 ha->base_qpair->chip_reset = ha->chip_reset; 7691 for (i = 0; i < ha->max_qpairs; i++) { 7692 if (ha->queue_pair_map[i]) 7693 ha->queue_pair_map[i]->chip_reset = 7694 ha->base_qpair->chip_reset; 7695 } 7696 7697 /* 7698 * purge mailbox might take a while. Slot Reset/chip reset 7699 * will take care of the purge 7700 */ 7701 7702 mutex_lock(&ha->mq_lock); 7703 ha->base_qpair->online = 0; 7704 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7705 qpair->online = 0; 7706 wmb(); 7707 mutex_unlock(&ha->mq_lock); 7708 7709 qla2x00_mark_all_devices_lost(vha); 7710 7711 spin_lock_irqsave(&ha->vport_slock, flags); 7712 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7713 atomic_inc(&vp->vref_count); 7714 spin_unlock_irqrestore(&ha->vport_slock, flags); 7715 qla2x00_mark_all_devices_lost(vp); 7716 spin_lock_irqsave(&ha->vport_slock, flags); 7717 atomic_dec(&vp->vref_count); 7718 } 7719 spin_unlock_irqrestore(&ha->vport_slock, flags); 7720 7721 /* Clear all async request states across all VPs. */ 7722 list_for_each_entry(fcport, &vha->vp_fcports, list) 7723 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7724 7725 spin_lock_irqsave(&ha->vport_slock, flags); 7726 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7727 atomic_inc(&vp->vref_count); 7728 spin_unlock_irqrestore(&ha->vport_slock, flags); 7729 list_for_each_entry(fcport, &vp->vp_fcports, list) 7730 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7731 spin_lock_irqsave(&ha->vport_slock, flags); 7732 atomic_dec(&vp->vref_count); 7733 } 7734 spin_unlock_irqrestore(&ha->vport_slock, flags); 7735 } 7736 7737 7738 static pci_ers_result_t 7739 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7740 { 7741 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7742 struct qla_hw_data *ha = vha->hw; 7743 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7744 7745 ql_log(ql_log_warn, vha, 0x9000, 7746 "PCI error detected, state %x.\n", state); 7747 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7748 7749 if (!atomic_read(&pdev->enable_cnt)) { 7750 ql_log(ql_log_info, vha, 0xffff, 7751 "PCI device is disabled,state %x\n", state); 7752 ret = PCI_ERS_RESULT_NEED_RESET; 7753 goto out; 7754 } 7755 7756 switch (state) { 7757 case pci_channel_io_normal: 7758 qla_pci_set_eeh_busy(vha); 7759 if (ql2xmqsupport || ql2xnvmeenable) { 7760 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7761 qla2xxx_wake_dpc(vha); 7762 } 7763 ret = PCI_ERS_RESULT_CAN_RECOVER; 7764 break; 7765 case pci_channel_io_frozen: 7766 qla_pci_set_eeh_busy(vha); 7767 ret = PCI_ERS_RESULT_NEED_RESET; 7768 break; 7769 case pci_channel_io_perm_failure: 7770 ha->flags.pci_channel_io_perm_failure = 1; 7771 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7772 if (ql2xmqsupport || ql2xnvmeenable) { 7773 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7774 qla2xxx_wake_dpc(vha); 7775 } 7776 ret = PCI_ERS_RESULT_DISCONNECT; 7777 } 7778 out: 7779 ql_dbg(ql_dbg_aer, vha, 0x600d, 7780 "PCI error detected returning [%x].\n", ret); 7781 return ret; 7782 } 7783 7784 static pci_ers_result_t 7785 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7786 { 7787 int risc_paused = 0; 7788 uint32_t stat; 7789 unsigned long flags; 7790 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7791 struct qla_hw_data *ha = base_vha->hw; 7792 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7793 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7794 7795 ql_log(ql_log_warn, base_vha, 0x9000, 7796 "mmio enabled\n"); 7797 7798 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7799 7800 if (IS_QLA82XX(ha)) 7801 return PCI_ERS_RESULT_RECOVERED; 7802 7803 if (qla2x00_isp_reg_stat(ha)) { 7804 ql_log(ql_log_info, base_vha, 0x803f, 7805 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7806 goto out; 7807 } 7808 7809 spin_lock_irqsave(&ha->hardware_lock, flags); 7810 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7811 stat = rd_reg_word(®->hccr); 7812 if (stat & HCCR_RISC_PAUSE) 7813 risc_paused = 1; 7814 } else if (IS_QLA23XX(ha)) { 7815 stat = rd_reg_dword(®->u.isp2300.host_status); 7816 if (stat & HSR_RISC_PAUSED) 7817 risc_paused = 1; 7818 } else if (IS_FWI2_CAPABLE(ha)) { 7819 stat = rd_reg_dword(®24->host_status); 7820 if (stat & HSRX_RISC_PAUSED) 7821 risc_paused = 1; 7822 } 7823 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7824 7825 if (risc_paused) { 7826 ql_log(ql_log_info, base_vha, 0x9003, 7827 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7828 qla2xxx_dump_fw(base_vha); 7829 } 7830 out: 7831 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7832 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7833 "mmio enabled returning.\n"); 7834 return PCI_ERS_RESULT_NEED_RESET; 7835 } 7836 7837 static pci_ers_result_t 7838 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7839 { 7840 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7841 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7842 struct qla_hw_data *ha = base_vha->hw; 7843 int rc; 7844 struct qla_qpair *qpair = NULL; 7845 7846 ql_log(ql_log_warn, base_vha, 0x9004, 7847 "Slot Reset.\n"); 7848 7849 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7850 /* Workaround: qla2xxx driver which access hardware earlier 7851 * needs error state to be pci_channel_io_online. 7852 * Otherwise mailbox command timesout. 7853 */ 7854 pdev->error_state = pci_channel_io_normal; 7855 7856 pci_restore_state(pdev); 7857 7858 /* pci_restore_state() clears the saved_state flag of the device 7859 * save restored state which resets saved_state flag 7860 */ 7861 pci_save_state(pdev); 7862 7863 if (ha->mem_only) 7864 rc = pci_enable_device_mem(pdev); 7865 else 7866 rc = pci_enable_device(pdev); 7867 7868 if (rc) { 7869 ql_log(ql_log_warn, base_vha, 0x9005, 7870 "Can't re-enable PCI device after reset.\n"); 7871 goto exit_slot_reset; 7872 } 7873 7874 7875 if (ha->isp_ops->pci_config(base_vha)) 7876 goto exit_slot_reset; 7877 7878 mutex_lock(&ha->mq_lock); 7879 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7880 qpair->online = 1; 7881 mutex_unlock(&ha->mq_lock); 7882 7883 ha->flags.eeh_busy = 0; 7884 base_vha->flags.online = 1; 7885 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7886 ha->isp_ops->abort_isp(base_vha); 7887 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7888 7889 if (qla2x00_isp_reg_stat(ha)) { 7890 ha->flags.eeh_busy = 1; 7891 qla_pci_error_cleanup(base_vha); 7892 ql_log(ql_log_warn, base_vha, 0x9005, 7893 "Device unable to recover from PCI error.\n"); 7894 } else { 7895 ret = PCI_ERS_RESULT_RECOVERED; 7896 } 7897 7898 exit_slot_reset: 7899 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7900 "Slot Reset returning %x.\n", ret); 7901 7902 return ret; 7903 } 7904 7905 static void 7906 qla2xxx_pci_resume(struct pci_dev *pdev) 7907 { 7908 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7909 struct qla_hw_data *ha = base_vha->hw; 7910 int ret; 7911 7912 ql_log(ql_log_warn, base_vha, 0x900f, 7913 "Pci Resume.\n"); 7914 7915 7916 ret = qla2x00_wait_for_hba_online(base_vha); 7917 if (ret != QLA_SUCCESS) { 7918 ql_log(ql_log_fatal, base_vha, 0x9002, 7919 "The device failed to resume I/O from slot/link_reset.\n"); 7920 } 7921 ha->pci_error_state = QLA_PCI_RESUME; 7922 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7923 "Pci Resume returning.\n"); 7924 } 7925 7926 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7927 { 7928 struct qla_hw_data *ha = vha->hw; 7929 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7930 bool do_cleanup = false; 7931 unsigned long flags; 7932 7933 if (ha->flags.eeh_busy) 7934 return; 7935 7936 spin_lock_irqsave(&base_vha->work_lock, flags); 7937 if (!ha->flags.eeh_busy) { 7938 ha->eeh_jif = jiffies; 7939 ha->flags.eeh_flush = 0; 7940 7941 ha->flags.eeh_busy = 1; 7942 do_cleanup = true; 7943 } 7944 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7945 7946 if (do_cleanup) 7947 qla_pci_error_cleanup(base_vha); 7948 } 7949 7950 /* 7951 * this routine will schedule a task to pause IO from interrupt context 7952 * if caller sees a PCIE error event (register read = 0xf's) 7953 */ 7954 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7955 { 7956 struct qla_hw_data *ha = vha->hw; 7957 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7958 7959 if (ha->flags.eeh_busy) 7960 return; 7961 7962 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7963 qla2xxx_wake_dpc(base_vha); 7964 } 7965 7966 static void 7967 qla_pci_reset_prepare(struct pci_dev *pdev) 7968 { 7969 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7970 struct qla_hw_data *ha = base_vha->hw; 7971 struct qla_qpair *qpair; 7972 7973 ql_log(ql_log_warn, base_vha, 0xffff, 7974 "%s.\n", __func__); 7975 7976 /* 7977 * PCI FLR/function reset is about to reset the 7978 * slot. Stop the chip to stop all DMA access. 7979 * It is assumed that pci_reset_done will be called 7980 * after FLR to resume Chip operation. 7981 */ 7982 ha->flags.eeh_busy = 1; 7983 mutex_lock(&ha->mq_lock); 7984 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7985 qpair->online = 0; 7986 mutex_unlock(&ha->mq_lock); 7987 7988 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7989 qla2x00_abort_isp_cleanup(base_vha); 7990 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7991 } 7992 7993 static void 7994 qla_pci_reset_done(struct pci_dev *pdev) 7995 { 7996 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7997 struct qla_hw_data *ha = base_vha->hw; 7998 struct qla_qpair *qpair; 7999 8000 ql_log(ql_log_warn, base_vha, 0xffff, 8001 "%s.\n", __func__); 8002 8003 /* 8004 * FLR just completed by PCI layer. Resume adapter 8005 */ 8006 ha->flags.eeh_busy = 0; 8007 mutex_lock(&ha->mq_lock); 8008 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8009 qpair->online = 1; 8010 mutex_unlock(&ha->mq_lock); 8011 8012 base_vha->flags.online = 1; 8013 ha->isp_ops->abort_isp(base_vha); 8014 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8015 } 8016 8017 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8018 { 8019 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8020 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8021 8022 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8023 blk_mq_map_queues(qmap); 8024 else 8025 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8026 } 8027 8028 struct scsi_host_template qla2xxx_driver_template = { 8029 .module = THIS_MODULE, 8030 .name = QLA2XXX_DRIVER_NAME, 8031 .queuecommand = qla2xxx_queuecommand, 8032 8033 .eh_timed_out = fc_eh_timed_out, 8034 .eh_abort_handler = qla2xxx_eh_abort, 8035 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8036 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8037 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8038 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8039 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8040 8041 .slave_configure = qla2xxx_slave_configure, 8042 8043 .slave_alloc = qla2xxx_slave_alloc, 8044 .slave_destroy = qla2xxx_slave_destroy, 8045 .scan_finished = qla2xxx_scan_finished, 8046 .scan_start = qla2xxx_scan_start, 8047 .change_queue_depth = scsi_change_queue_depth, 8048 .map_queues = qla2xxx_map_queues, 8049 .this_id = -1, 8050 .cmd_per_lun = 3, 8051 .sg_tablesize = SG_ALL, 8052 8053 .max_sectors = 0xFFFF, 8054 .shost_groups = qla2x00_host_groups, 8055 8056 .supported_mode = MODE_INITIATOR, 8057 .track_queue_depth = 1, 8058 .cmd_size = sizeof(srb_t), 8059 }; 8060 8061 static const struct pci_error_handlers qla2xxx_err_handler = { 8062 .error_detected = qla2xxx_pci_error_detected, 8063 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8064 .slot_reset = qla2xxx_pci_slot_reset, 8065 .resume = qla2xxx_pci_resume, 8066 .reset_prepare = qla_pci_reset_prepare, 8067 .reset_done = qla_pci_reset_done, 8068 }; 8069 8070 static struct pci_device_id qla2xxx_pci_tbl[] = { 8071 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8072 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8073 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8074 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8075 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8076 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8077 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8078 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8079 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8080 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8081 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8082 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8083 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8084 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8085 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8086 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8087 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8088 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8089 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8090 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8091 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8092 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8095 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8096 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8098 { 0 }, 8099 }; 8100 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8101 8102 static struct pci_driver qla2xxx_pci_driver = { 8103 .name = QLA2XXX_DRIVER_NAME, 8104 .driver = { 8105 .owner = THIS_MODULE, 8106 }, 8107 .id_table = qla2xxx_pci_tbl, 8108 .probe = qla2x00_probe_one, 8109 .remove = qla2x00_remove_one, 8110 .shutdown = qla2x00_shutdown, 8111 .err_handler = &qla2xxx_err_handler, 8112 }; 8113 8114 static const struct file_operations apidev_fops = { 8115 .owner = THIS_MODULE, 8116 .llseek = noop_llseek, 8117 }; 8118 8119 /** 8120 * qla2x00_module_init - Module initialization. 8121 **/ 8122 static int __init 8123 qla2x00_module_init(void) 8124 { 8125 int ret = 0; 8126 8127 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8128 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8129 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8130 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8131 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8132 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8133 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8134 BUILD_BUG_ON(sizeof(request_t) != 64); 8135 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8136 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8137 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8138 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8139 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8140 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8141 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8142 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8143 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8144 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8145 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8146 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8147 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8148 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8149 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8150 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8151 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8152 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8153 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8154 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8155 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8156 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8157 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8158 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8159 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8160 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8161 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8162 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8163 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8164 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8165 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8166 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8167 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8168 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8169 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8170 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8171 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8172 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8173 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8174 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8175 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8176 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8177 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8178 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8179 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8180 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8181 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8182 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8183 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8184 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8185 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8186 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8187 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8188 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8189 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8190 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8191 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8192 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8193 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8194 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8195 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8196 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8197 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8198 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8199 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8200 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8201 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8202 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8203 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8204 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8205 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8206 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8207 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8208 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8209 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8210 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8211 8212 qla_trace_init(); 8213 8214 /* Allocate cache for SRBs. */ 8215 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8216 SLAB_HWCACHE_ALIGN, NULL); 8217 if (srb_cachep == NULL) { 8218 ql_log(ql_log_fatal, NULL, 0x0001, 8219 "Unable to allocate SRB cache...Failing load!.\n"); 8220 return -ENOMEM; 8221 } 8222 8223 /* Initialize target kmem_cache and mem_pools */ 8224 ret = qlt_init(); 8225 if (ret < 0) { 8226 goto destroy_cache; 8227 } else if (ret > 0) { 8228 /* 8229 * If initiator mode is explictly disabled by qlt_init(), 8230 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8231 * performing scsi_scan_target() during LOOP UP event. 8232 */ 8233 qla2xxx_transport_functions.disable_target_scan = 1; 8234 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8235 } 8236 8237 /* Derive version string. */ 8238 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8239 if (ql2xextended_error_logging) 8240 strcat(qla2x00_version_str, "-debug"); 8241 if (ql2xextended_error_logging == 1) 8242 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8243 8244 qla2xxx_transport_template = 8245 fc_attach_transport(&qla2xxx_transport_functions); 8246 if (!qla2xxx_transport_template) { 8247 ql_log(ql_log_fatal, NULL, 0x0002, 8248 "fc_attach_transport failed...Failing load!.\n"); 8249 ret = -ENODEV; 8250 goto qlt_exit; 8251 } 8252 8253 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8254 if (apidev_major < 0) { 8255 ql_log(ql_log_fatal, NULL, 0x0003, 8256 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8257 } 8258 8259 qla2xxx_transport_vport_template = 8260 fc_attach_transport(&qla2xxx_transport_vport_functions); 8261 if (!qla2xxx_transport_vport_template) { 8262 ql_log(ql_log_fatal, NULL, 0x0004, 8263 "fc_attach_transport vport failed...Failing load!.\n"); 8264 ret = -ENODEV; 8265 goto unreg_chrdev; 8266 } 8267 ql_log(ql_log_info, NULL, 0x0005, 8268 "QLogic Fibre Channel HBA Driver: %s.\n", 8269 qla2x00_version_str); 8270 ret = pci_register_driver(&qla2xxx_pci_driver); 8271 if (ret) { 8272 ql_log(ql_log_fatal, NULL, 0x0006, 8273 "pci_register_driver failed...ret=%d Failing load!.\n", 8274 ret); 8275 goto release_vport_transport; 8276 } 8277 return ret; 8278 8279 release_vport_transport: 8280 fc_release_transport(qla2xxx_transport_vport_template); 8281 8282 unreg_chrdev: 8283 if (apidev_major >= 0) 8284 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8285 fc_release_transport(qla2xxx_transport_template); 8286 8287 qlt_exit: 8288 qlt_exit(); 8289 8290 destroy_cache: 8291 kmem_cache_destroy(srb_cachep); 8292 8293 qla_trace_uninit(); 8294 return ret; 8295 } 8296 8297 /** 8298 * qla2x00_module_exit - Module cleanup. 8299 **/ 8300 static void __exit 8301 qla2x00_module_exit(void) 8302 { 8303 pci_unregister_driver(&qla2xxx_pci_driver); 8304 qla2x00_release_firmware(); 8305 kmem_cache_destroy(ctx_cachep); 8306 fc_release_transport(qla2xxx_transport_vport_template); 8307 if (apidev_major >= 0) 8308 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8309 fc_release_transport(qla2xxx_transport_template); 8310 qlt_exit(); 8311 kmem_cache_destroy(srb_cachep); 8312 qla_trace_uninit(); 8313 } 8314 8315 module_init(qla2x00_module_init); 8316 module_exit(qla2x00_module_exit); 8317 8318 MODULE_AUTHOR("QLogic Corporation"); 8319 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8320 MODULE_LICENSE("GPL"); 8321 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8322 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8323 MODULE_FIRMWARE(FW_FILE_ISP2300); 8324 MODULE_FIRMWARE(FW_FILE_ISP2322); 8325 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8326 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8327