1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 struct scsi_host_template qla2xxx_driver_template = { 307 .module = THIS_MODULE, 308 .name = QLA2XXX_DRIVER_NAME, 309 .queuecommand = qla2xxx_queuecommand, 310 311 .eh_timed_out = fc_eh_timed_out, 312 .eh_abort_handler = qla2xxx_eh_abort, 313 .eh_device_reset_handler = qla2xxx_eh_device_reset, 314 .eh_target_reset_handler = qla2xxx_eh_target_reset, 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 316 .eh_host_reset_handler = qla2xxx_eh_host_reset, 317 318 .slave_configure = qla2xxx_slave_configure, 319 320 .slave_alloc = qla2xxx_slave_alloc, 321 .slave_destroy = qla2xxx_slave_destroy, 322 .scan_finished = qla2xxx_scan_finished, 323 .scan_start = qla2xxx_scan_start, 324 .change_queue_depth = scsi_change_queue_depth, 325 .map_queues = qla2xxx_map_queues, 326 .this_id = -1, 327 .cmd_per_lun = 3, 328 .use_clustering = ENABLE_CLUSTERING, 329 .sg_tablesize = SG_ALL, 330 331 .max_sectors = 0xFFFF, 332 .shost_attrs = qla2x00_host_attrs, 333 334 .supported_mode = MODE_INITIATOR, 335 .track_queue_depth = 1, 336 }; 337 338 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 339 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 340 341 /* TODO Convert to inlines 342 * 343 * Timer routines 344 */ 345 346 __inline__ void 347 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 348 { 349 timer_setup(&vha->timer, qla2x00_timer, 0); 350 vha->timer.expires = jiffies + interval * HZ; 351 add_timer(&vha->timer); 352 vha->timer_active = 1; 353 } 354 355 static inline void 356 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 357 { 358 /* Currently used for 82XX only. */ 359 if (vha->device_flags & DFLG_DEV_FAILED) { 360 ql_dbg(ql_dbg_timer, vha, 0x600d, 361 "Device in a failed state, returning.\n"); 362 return; 363 } 364 365 mod_timer(&vha->timer, jiffies + interval * HZ); 366 } 367 368 static __inline__ void 369 qla2x00_stop_timer(scsi_qla_host_t *vha) 370 { 371 del_timer_sync(&vha->timer); 372 vha->timer_active = 0; 373 } 374 375 static int qla2x00_do_dpc(void *data); 376 377 static void qla2x00_rst_aen(scsi_qla_host_t *); 378 379 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 380 struct req_que **, struct rsp_que **); 381 static void qla2x00_free_fw_dump(struct qla_hw_data *); 382 static void qla2x00_mem_free(struct qla_hw_data *); 383 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 384 struct qla_qpair *qpair); 385 386 /* -------------------------------------------------------------------------- */ 387 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 388 struct rsp_que *rsp) 389 { 390 struct qla_hw_data *ha = vha->hw; 391 rsp->qpair = ha->base_qpair; 392 rsp->req = req; 393 ha->base_qpair->req = req; 394 ha->base_qpair->rsp = rsp; 395 ha->base_qpair->vha = vha; 396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 399 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 400 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list); 401 ha->base_qpair->enable_class_2 = ql2xenableclass2; 402 /* init qpair to this cpu. Will adjust at run time. */ 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 404 ha->base_qpair->pdev = ha->pdev; 405 406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 408 } 409 410 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 414 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 415 GFP_KERNEL); 416 if (!ha->req_q_map) { 417 ql_log(ql_log_fatal, vha, 0x003b, 418 "Unable to allocate memory for request queue ptrs.\n"); 419 goto fail_req_map; 420 } 421 422 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 423 GFP_KERNEL); 424 if (!ha->rsp_q_map) { 425 ql_log(ql_log_fatal, vha, 0x003c, 426 "Unable to allocate memory for response queue ptrs.\n"); 427 goto fail_rsp_map; 428 } 429 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 431 if (ha->base_qpair == NULL) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to allocate base queue pair memory.\n"); 434 goto fail_base_qpair; 435 } 436 437 qla_init_base_qpair(vha, req, rsp); 438 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 441 GFP_KERNEL); 442 if (!ha->queue_pair_map) { 443 ql_log(ql_log_fatal, vha, 0x0180, 444 "Unable to allocate memory for queue pair ptrs.\n"); 445 goto fail_qpair_map; 446 } 447 } 448 449 /* 450 * Make sure we record at least the request and response queue zero in 451 * case we need to free them if part of the probe fails. 452 */ 453 ha->rsp_q_map[0] = rsp; 454 ha->req_q_map[0] = req; 455 set_bit(0, ha->rsp_qid_map); 456 set_bit(0, ha->req_qid_map); 457 return 1; 458 459 fail_qpair_map: 460 kfree(ha->base_qpair); 461 ha->base_qpair = NULL; 462 fail_base_qpair: 463 kfree(ha->rsp_q_map); 464 ha->rsp_q_map = NULL; 465 fail_rsp_map: 466 kfree(ha->req_q_map); 467 ha->req_q_map = NULL; 468 fail_req_map: 469 return -ENOMEM; 470 } 471 472 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 473 { 474 if (IS_QLAFX00(ha)) { 475 if (req && req->ring_fx00) 476 dma_free_coherent(&ha->pdev->dev, 477 (req->length_fx00 + 1) * sizeof(request_t), 478 req->ring_fx00, req->dma_fx00); 479 } else if (req && req->ring) 480 dma_free_coherent(&ha->pdev->dev, 481 (req->length + 1) * sizeof(request_t), 482 req->ring, req->dma); 483 484 if (req) 485 kfree(req->outstanding_cmds); 486 487 kfree(req); 488 } 489 490 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 491 { 492 if (IS_QLAFX00(ha)) { 493 if (rsp && rsp->ring) 494 dma_free_coherent(&ha->pdev->dev, 495 (rsp->length_fx00 + 1) * sizeof(request_t), 496 rsp->ring_fx00, rsp->dma_fx00); 497 } else if (rsp && rsp->ring) { 498 dma_free_coherent(&ha->pdev->dev, 499 (rsp->length + 1) * sizeof(response_t), 500 rsp->ring, rsp->dma); 501 } 502 kfree(rsp); 503 } 504 505 static void qla2x00_free_queues(struct qla_hw_data *ha) 506 { 507 struct req_que *req; 508 struct rsp_que *rsp; 509 int cnt; 510 unsigned long flags; 511 512 if (ha->queue_pair_map) { 513 kfree(ha->queue_pair_map); 514 ha->queue_pair_map = NULL; 515 } 516 if (ha->base_qpair) { 517 kfree(ha->base_qpair); 518 ha->base_qpair = NULL; 519 } 520 521 spin_lock_irqsave(&ha->hardware_lock, flags); 522 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 523 if (!test_bit(cnt, ha->req_qid_map)) 524 continue; 525 526 req = ha->req_q_map[cnt]; 527 clear_bit(cnt, ha->req_qid_map); 528 ha->req_q_map[cnt] = NULL; 529 530 spin_unlock_irqrestore(&ha->hardware_lock, flags); 531 qla2x00_free_req_que(ha, req); 532 spin_lock_irqsave(&ha->hardware_lock, flags); 533 } 534 spin_unlock_irqrestore(&ha->hardware_lock, flags); 535 536 kfree(ha->req_q_map); 537 ha->req_q_map = NULL; 538 539 540 spin_lock_irqsave(&ha->hardware_lock, flags); 541 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 542 if (!test_bit(cnt, ha->rsp_qid_map)) 543 continue; 544 545 rsp = ha->rsp_q_map[cnt]; 546 clear_bit(cnt, ha->rsp_qid_map); 547 ha->rsp_q_map[cnt] = NULL; 548 spin_unlock_irqrestore(&ha->hardware_lock, flags); 549 qla2x00_free_rsp_que(ha, rsp); 550 spin_lock_irqsave(&ha->hardware_lock, flags); 551 } 552 spin_unlock_irqrestore(&ha->hardware_lock, flags); 553 554 kfree(ha->rsp_q_map); 555 ha->rsp_q_map = NULL; 556 } 557 558 static char * 559 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 560 { 561 struct qla_hw_data *ha = vha->hw; 562 static char *pci_bus_modes[] = { 563 "33", "66", "100", "133", 564 }; 565 uint16_t pci_bus; 566 567 strcpy(str, "PCI"); 568 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 569 if (pci_bus) { 570 strcat(str, "-X ("); 571 strcat(str, pci_bus_modes[pci_bus]); 572 } else { 573 pci_bus = (ha->pci_attr & BIT_8) >> 8; 574 strcat(str, " ("); 575 strcat(str, pci_bus_modes[pci_bus]); 576 } 577 strcat(str, " MHz)"); 578 579 return (str); 580 } 581 582 static char * 583 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 584 { 585 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 586 struct qla_hw_data *ha = vha->hw; 587 uint32_t pci_bus; 588 589 if (pci_is_pcie(ha->pdev)) { 590 char lwstr[6]; 591 uint32_t lstat, lspeed, lwidth; 592 593 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 594 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 595 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 596 597 strcpy(str, "PCIe ("); 598 switch (lspeed) { 599 case 1: 600 strcat(str, "2.5GT/s "); 601 break; 602 case 2: 603 strcat(str, "5.0GT/s "); 604 break; 605 case 3: 606 strcat(str, "8.0GT/s "); 607 break; 608 default: 609 strcat(str, "<unknown> "); 610 break; 611 } 612 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 613 strcat(str, lwstr); 614 615 return str; 616 } 617 618 strcpy(str, "PCI"); 619 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 620 if (pci_bus == 0 || pci_bus == 8) { 621 strcat(str, " ("); 622 strcat(str, pci_bus_modes[pci_bus >> 3]); 623 } else { 624 strcat(str, "-X "); 625 if (pci_bus & BIT_2) 626 strcat(str, "Mode 2"); 627 else 628 strcat(str, "Mode 1"); 629 strcat(str, " ("); 630 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 631 } 632 strcat(str, " MHz)"); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void 686 qla2x00_sp_free_dma(void *ptr) 687 { 688 srb_t *sp = ptr; 689 struct qla_hw_data *ha = sp->vha->hw; 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 691 void *ctx = GET_CMD_CTX_SP(sp); 692 693 if (sp->flags & SRB_DMA_VALID) { 694 scsi_dma_unmap(cmd); 695 sp->flags &= ~SRB_DMA_VALID; 696 } 697 698 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 699 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 700 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 701 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 702 } 703 704 if (!ctx) 705 goto end; 706 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 708 /* List assured to be having elements */ 709 qla2x00_clean_dsd_pool(ha, ctx); 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 711 } 712 713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 714 struct crc_context *ctx0 = ctx; 715 716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 718 } 719 720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 721 struct ct6_dsd *ctx1 = ctx; 722 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 724 ctx1->fcp_cmnd_dma); 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 728 mempool_free(ctx1, ha->ctx_mempool); 729 } 730 731 end: 732 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 733 CMD_SP(cmd) = NULL; 734 qla2x00_rel_sp(sp); 735 } 736 } 737 738 void 739 qla2x00_sp_compl(void *ptr, int res) 740 { 741 srb_t *sp = ptr; 742 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 743 744 cmd->result = res; 745 746 if (atomic_read(&sp->ref_count) == 0) { 747 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 748 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 749 sp, GET_CMD_SP(sp)); 750 if (ql2xextended_error_logging & ql_dbg_io) 751 WARN_ON(atomic_read(&sp->ref_count) == 0); 752 return; 753 } 754 if (!atomic_dec_and_test(&sp->ref_count)) 755 return; 756 757 sp->free(sp); 758 cmd->scsi_done(cmd); 759 } 760 761 void 762 qla2xxx_qpair_sp_free_dma(void *ptr) 763 { 764 srb_t *sp = (srb_t *)ptr; 765 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 766 struct qla_hw_data *ha = sp->fcport->vha->hw; 767 void *ctx = GET_CMD_CTX_SP(sp); 768 769 if (sp->flags & SRB_DMA_VALID) { 770 scsi_dma_unmap(cmd); 771 sp->flags &= ~SRB_DMA_VALID; 772 } 773 774 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 775 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 776 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 777 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 778 } 779 780 if (!ctx) 781 goto end; 782 783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 784 /* List assured to be having elements */ 785 qla2x00_clean_dsd_pool(ha, ctx); 786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 787 } 788 789 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 790 struct crc_context *ctx0 = ctx; 791 792 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 793 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 794 } 795 796 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 797 struct ct6_dsd *ctx1 = ctx; 798 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 799 ctx1->fcp_cmnd_dma); 800 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 801 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 802 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 803 mempool_free(ctx1, ha->ctx_mempool); 804 } 805 end: 806 CMD_SP(cmd) = NULL; 807 qla2xxx_rel_qpair_sp(sp->qpair, sp); 808 } 809 810 void 811 qla2xxx_qpair_sp_compl(void *ptr, int res) 812 { 813 srb_t *sp = ptr; 814 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 815 816 cmd->result = res; 817 818 if (atomic_read(&sp->ref_count) == 0) { 819 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 820 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 821 sp, GET_CMD_SP(sp)); 822 if (ql2xextended_error_logging & ql_dbg_io) 823 WARN_ON(atomic_read(&sp->ref_count) == 0); 824 return; 825 } 826 if (!atomic_dec_and_test(&sp->ref_count)) 827 return; 828 829 sp->free(sp); 830 cmd->scsi_done(cmd); 831 } 832 833 /* If we are SP1 here, we need to still take and release the host_lock as SP1 834 * does not have the changes necessary to avoid taking host->host_lock. 835 */ 836 static int 837 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 838 { 839 scsi_qla_host_t *vha = shost_priv(host); 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 842 struct qla_hw_data *ha = vha->hw; 843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 844 srb_t *sp; 845 int rval; 846 struct qla_qpair *qpair = NULL; 847 uint32_t tag; 848 uint16_t hwq; 849 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 851 cmd->result = DID_NO_CONNECT << 16; 852 goto qc24_fail_command; 853 } 854 855 if (ha->mqenable) { 856 if (shost_use_blk_mq(vha->host)) { 857 tag = blk_mq_unique_tag(cmd->request); 858 hwq = blk_mq_unique_tag_to_hwq(tag); 859 qpair = ha->queue_pair_map[hwq]; 860 } else if (vha->vp_idx && vha->qpair) { 861 qpair = vha->qpair; 862 } 863 864 if (qpair) 865 return qla2xxx_mqueuecommand(host, cmd, qpair); 866 } 867 868 if (ha->flags.eeh_busy) { 869 if (ha->flags.pci_channel_io_perm_failure) { 870 ql_dbg(ql_dbg_aer, vha, 0x9010, 871 "PCI Channel IO permanent failure, exiting " 872 "cmd=%p.\n", cmd); 873 cmd->result = DID_NO_CONNECT << 16; 874 } else { 875 ql_dbg(ql_dbg_aer, vha, 0x9011, 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 877 cmd->result = DID_REQUEUE << 16; 878 } 879 goto qc24_fail_command; 880 } 881 882 rval = fc_remote_port_chkready(rport); 883 if (rval) { 884 cmd->result = rval; 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 887 cmd, rval); 888 goto qc24_fail_command; 889 } 890 891 if (!vha->flags.difdix_supported && 892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 893 ql_dbg(ql_dbg_io, vha, 0x3004, 894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 895 cmd); 896 cmd->result = DID_NO_CONNECT << 16; 897 goto qc24_fail_command; 898 } 899 900 if (!fcport) { 901 cmd->result = DID_NO_CONNECT << 16; 902 goto qc24_fail_command; 903 } 904 905 if (atomic_read(&fcport->state) != FCS_ONLINE) { 906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 908 ql_dbg(ql_dbg_io, vha, 0x3005, 909 "Returning DNC, fcport_state=%d loop_state=%d.\n", 910 atomic_read(&fcport->state), 911 atomic_read(&base_vha->loop_state)); 912 cmd->result = DID_NO_CONNECT << 16; 913 goto qc24_fail_command; 914 } 915 goto qc24_target_busy; 916 } 917 918 /* 919 * Return target busy if we've received a non-zero retry_delay_timer 920 * in a FCP_RSP. 921 */ 922 if (fcport->retry_delay_timestamp == 0) { 923 /* retry delay not set */ 924 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 925 fcport->retry_delay_timestamp = 0; 926 else 927 goto qc24_target_busy; 928 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 930 if (!sp) 931 goto qc24_host_busy; 932 933 sp->u.scmd.cmd = cmd; 934 sp->type = SRB_SCSI_CMD; 935 atomic_set(&sp->ref_count, 1); 936 CMD_SP(cmd) = (void *)sp; 937 sp->free = qla2x00_sp_free_dma; 938 sp->done = qla2x00_sp_compl; 939 940 rval = ha->isp_ops->start_scsi(sp); 941 if (rval != QLA_SUCCESS) { 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 944 goto qc24_host_busy_free_sp; 945 } 946 947 return 0; 948 949 qc24_host_busy_free_sp: 950 sp->free(sp); 951 952 qc24_host_busy: 953 return SCSI_MLQUEUE_HOST_BUSY; 954 955 qc24_target_busy: 956 return SCSI_MLQUEUE_TARGET_BUSY; 957 958 qc24_fail_command: 959 cmd->scsi_done(cmd); 960 961 return 0; 962 } 963 964 /* For MQ supported I/O */ 965 int 966 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 967 struct qla_qpair *qpair) 968 { 969 scsi_qla_host_t *vha = shost_priv(host); 970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 972 struct qla_hw_data *ha = vha->hw; 973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 974 srb_t *sp; 975 int rval; 976 977 rval = fc_remote_port_chkready(rport); 978 if (rval) { 979 cmd->result = rval; 980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 982 cmd, rval); 983 goto qc24_fail_command; 984 } 985 986 if (!fcport) { 987 cmd->result = DID_NO_CONNECT << 16; 988 goto qc24_fail_command; 989 } 990 991 if (atomic_read(&fcport->state) != FCS_ONLINE) { 992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 994 ql_dbg(ql_dbg_io, vha, 0x3077, 995 "Returning DNC, fcport_state=%d loop_state=%d.\n", 996 atomic_read(&fcport->state), 997 atomic_read(&base_vha->loop_state)); 998 cmd->result = DID_NO_CONNECT << 16; 999 goto qc24_fail_command; 1000 } 1001 goto qc24_target_busy; 1002 } 1003 1004 /* 1005 * Return target busy if we've received a non-zero retry_delay_timer 1006 * in a FCP_RSP. 1007 */ 1008 if (fcport->retry_delay_timestamp == 0) { 1009 /* retry delay not set */ 1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1011 fcport->retry_delay_timestamp = 0; 1012 else 1013 goto qc24_target_busy; 1014 1015 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1016 if (!sp) 1017 goto qc24_host_busy; 1018 1019 sp->u.scmd.cmd = cmd; 1020 sp->type = SRB_SCSI_CMD; 1021 atomic_set(&sp->ref_count, 1); 1022 CMD_SP(cmd) = (void *)sp; 1023 sp->free = qla2xxx_qpair_sp_free_dma; 1024 sp->done = qla2xxx_qpair_sp_compl; 1025 sp->qpair = qpair; 1026 1027 rval = ha->isp_ops->start_scsi_mq(sp); 1028 if (rval != QLA_SUCCESS) { 1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1031 if (rval == QLA_INTERFACE_ERROR) 1032 goto qc24_fail_command; 1033 goto qc24_host_busy_free_sp; 1034 } 1035 1036 return 0; 1037 1038 qc24_host_busy_free_sp: 1039 sp->free(sp); 1040 1041 qc24_host_busy: 1042 return SCSI_MLQUEUE_HOST_BUSY; 1043 1044 qc24_target_busy: 1045 return SCSI_MLQUEUE_TARGET_BUSY; 1046 1047 qc24_fail_command: 1048 cmd->scsi_done(cmd); 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * qla2x00_eh_wait_on_command 1055 * Waits for the command to be returned by the Firmware for some 1056 * max time. 1057 * 1058 * Input: 1059 * cmd = Scsi Command to wait on. 1060 * 1061 * Return: 1062 * Not Found : 0 1063 * Found : 1 1064 */ 1065 static int 1066 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1067 { 1068 #define ABORT_POLLING_PERIOD 1000 1069 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1070 unsigned long wait_iter = ABORT_WAIT_ITER; 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1072 struct qla_hw_data *ha = vha->hw; 1073 int ret = QLA_SUCCESS; 1074 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1077 "Return:eh_wait.\n"); 1078 return ret; 1079 } 1080 1081 while (CMD_SP(cmd) && wait_iter--) { 1082 msleep(ABORT_POLLING_PERIOD); 1083 } 1084 if (CMD_SP(cmd)) 1085 ret = QLA_FUNCTION_FAILED; 1086 1087 return ret; 1088 } 1089 1090 /* 1091 * qla2x00_wait_for_hba_online 1092 * Wait till the HBA is online after going through 1093 * <= MAX_RETRIES_OF_ISP_ABORT or 1094 * finally HBA is disabled ie marked offline 1095 * 1096 * Input: 1097 * ha - pointer to host adapter structure 1098 * 1099 * Note: 1100 * Does context switching-Release SPIN_LOCK 1101 * (if any) before calling this routine. 1102 * 1103 * Return: 1104 * Success (Adapter is online) : 0 1105 * Failed (Adapter is offline/disabled) : 1 1106 */ 1107 int 1108 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1109 { 1110 int return_status; 1111 unsigned long wait_online; 1112 struct qla_hw_data *ha = vha->hw; 1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1114 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1119 ha->dpc_active) && time_before(jiffies, wait_online)) { 1120 1121 msleep(1000); 1122 } 1123 if (base_vha->flags.online) 1124 return_status = QLA_SUCCESS; 1125 else 1126 return_status = QLA_FUNCTION_FAILED; 1127 1128 return (return_status); 1129 } 1130 1131 static inline int test_fcport_count(scsi_qla_host_t *vha) 1132 { 1133 struct qla_hw_data *ha = vha->hw; 1134 unsigned long flags; 1135 int res; 1136 1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1138 ql_dbg(ql_dbg_init, vha, 0x00ec, 1139 "tgt %p, fcport_count=%d\n", 1140 vha, vha->fcport_count); 1141 res = (vha->fcport_count == 0); 1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1143 1144 return res; 1145 } 1146 1147 /* 1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1149 * it has dependency on UNLOADING flag to stop device discovery 1150 */ 1151 static void 1152 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1153 { 1154 qla2x00_mark_all_devices_lost(vha, 0); 1155 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1157 } 1158 1159 /* 1160 * qla2x00_wait_for_hba_ready 1161 * Wait till the HBA is ready before doing driver unload 1162 * 1163 * Input: 1164 * ha - pointer to host adapter structure 1165 * 1166 * Note: 1167 * Does context switching-Release SPIN_LOCK 1168 * (if any) before calling this routine. 1169 * 1170 */ 1171 static void 1172 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1173 { 1174 struct qla_hw_data *ha = vha->hw; 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1176 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1178 ha->flags.mbox_busy) || 1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1181 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1182 break; 1183 msleep(1000); 1184 } 1185 } 1186 1187 int 1188 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1189 { 1190 int return_status; 1191 unsigned long wait_reset; 1192 struct qla_hw_data *ha = vha->hw; 1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1194 1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1199 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1200 1201 msleep(1000); 1202 1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1204 ha->flags.chip_reset_done) 1205 break; 1206 } 1207 if (ha->flags.chip_reset_done) 1208 return_status = QLA_SUCCESS; 1209 else 1210 return_status = QLA_FUNCTION_FAILED; 1211 1212 return return_status; 1213 } 1214 1215 static void 1216 sp_get(struct srb *sp) 1217 { 1218 atomic_inc(&sp->ref_count); 1219 } 1220 1221 #define ISP_REG_DISCONNECT 0xffffffffU 1222 /************************************************************************** 1223 * qla2x00_isp_reg_stat 1224 * 1225 * Description: 1226 * Read the host status register of ISP before aborting the command. 1227 * 1228 * Input: 1229 * ha = pointer to host adapter structure. 1230 * 1231 * 1232 * Returns: 1233 * Either true or false. 1234 * 1235 * Note: Return true if there is register disconnect. 1236 **************************************************************************/ 1237 static inline 1238 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1239 { 1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1241 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1242 1243 if (IS_P3P_TYPE(ha)) 1244 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1245 else 1246 return ((RD_REG_DWORD(®->host_status)) == 1247 ISP_REG_DISCONNECT); 1248 } 1249 1250 /************************************************************************** 1251 * qla2xxx_eh_abort 1252 * 1253 * Description: 1254 * The abort function will abort the specified command. 1255 * 1256 * Input: 1257 * cmd = Linux SCSI command packet to be aborted. 1258 * 1259 * Returns: 1260 * Either SUCCESS or FAILED. 1261 * 1262 * Note: 1263 * Only return FAILED if command not returned by firmware. 1264 **************************************************************************/ 1265 static int 1266 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1267 { 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1269 srb_t *sp; 1270 int ret; 1271 unsigned int id; 1272 uint64_t lun; 1273 unsigned long flags; 1274 int rval, wait = 0; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 if (qla2x00_isp_reg_stat(ha)) { 1278 ql_log(ql_log_info, vha, 0x8042, 1279 "PCI/Register disconnect, exiting.\n"); 1280 return FAILED; 1281 } 1282 if (!CMD_SP(cmd)) 1283 return SUCCESS; 1284 1285 ret = fc_block_scsi_eh(cmd); 1286 if (ret != 0) 1287 return ret; 1288 ret = SUCCESS; 1289 1290 id = cmd->device->id; 1291 lun = cmd->device->lun; 1292 1293 spin_lock_irqsave(&ha->hardware_lock, flags); 1294 sp = (srb_t *) CMD_SP(cmd); 1295 if (!sp) { 1296 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1297 return SUCCESS; 1298 } 1299 1300 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1302 vha->host_no, id, lun, sp, cmd, sp->handle); 1303 1304 /* Get a reference to the sp and drop the lock.*/ 1305 sp_get(sp); 1306 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1308 rval = ha->isp_ops->abort_command(sp); 1309 if (rval) { 1310 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1311 ret = SUCCESS; 1312 else 1313 ret = FAILED; 1314 1315 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1316 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1317 } else { 1318 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1319 "Abort command mbx success cmd=%p.\n", cmd); 1320 wait = 1; 1321 } 1322 1323 spin_lock_irqsave(&ha->hardware_lock, flags); 1324 sp->done(sp, 0); 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1326 1327 /* Did the command return during mailbox execution? */ 1328 if (ret == FAILED && !CMD_SP(cmd)) 1329 ret = SUCCESS; 1330 1331 /* Wait for the command to be returned. */ 1332 if (wait) { 1333 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1334 ql_log(ql_log_warn, vha, 0x8006, 1335 "Abort handler timed out cmd=%p.\n", cmd); 1336 ret = FAILED; 1337 } 1338 } 1339 1340 ql_log(ql_log_info, vha, 0x801c, 1341 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1342 vha->host_no, id, lun, wait, ret); 1343 1344 return ret; 1345 } 1346 1347 int 1348 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1349 uint64_t l, enum nexus_wait_type type) 1350 { 1351 int cnt, match, status; 1352 unsigned long flags; 1353 struct qla_hw_data *ha = vha->hw; 1354 struct req_que *req; 1355 srb_t *sp; 1356 struct scsi_cmnd *cmd; 1357 1358 status = QLA_SUCCESS; 1359 1360 spin_lock_irqsave(&ha->hardware_lock, flags); 1361 req = vha->req; 1362 for (cnt = 1; status == QLA_SUCCESS && 1363 cnt < req->num_outstanding_cmds; cnt++) { 1364 sp = req->outstanding_cmds[cnt]; 1365 if (!sp) 1366 continue; 1367 if (sp->type != SRB_SCSI_CMD) 1368 continue; 1369 if (vha->vp_idx != sp->vha->vp_idx) 1370 continue; 1371 match = 0; 1372 cmd = GET_CMD_SP(sp); 1373 switch (type) { 1374 case WAIT_HOST: 1375 match = 1; 1376 break; 1377 case WAIT_TARGET: 1378 match = cmd->device->id == t; 1379 break; 1380 case WAIT_LUN: 1381 match = (cmd->device->id == t && 1382 cmd->device->lun == l); 1383 break; 1384 } 1385 if (!match) 1386 continue; 1387 1388 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1389 status = qla2x00_eh_wait_on_command(cmd); 1390 spin_lock_irqsave(&ha->hardware_lock, flags); 1391 } 1392 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1393 1394 return status; 1395 } 1396 1397 static char *reset_errors[] = { 1398 "HBA not online", 1399 "HBA not ready", 1400 "Task management failed", 1401 "Waiting for command completions", 1402 }; 1403 1404 static int 1405 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1406 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1407 { 1408 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1409 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1410 int err; 1411 1412 if (!fcport) { 1413 return FAILED; 1414 } 1415 1416 err = fc_block_scsi_eh(cmd); 1417 if (err != 0) 1418 return err; 1419 1420 ql_log(ql_log_info, vha, 0x8009, 1421 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1422 cmd->device->id, cmd->device->lun, cmd); 1423 1424 err = 0; 1425 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1426 ql_log(ql_log_warn, vha, 0x800a, 1427 "Wait for hba online failed for cmd=%p.\n", cmd); 1428 goto eh_reset_failed; 1429 } 1430 err = 2; 1431 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1432 != QLA_SUCCESS) { 1433 ql_log(ql_log_warn, vha, 0x800c, 1434 "do_reset failed for cmd=%p.\n", cmd); 1435 goto eh_reset_failed; 1436 } 1437 err = 3; 1438 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1439 cmd->device->lun, type) != QLA_SUCCESS) { 1440 ql_log(ql_log_warn, vha, 0x800d, 1441 "wait for pending cmds failed for cmd=%p.\n", cmd); 1442 goto eh_reset_failed; 1443 } 1444 1445 ql_log(ql_log_info, vha, 0x800e, 1446 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1447 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1448 1449 return SUCCESS; 1450 1451 eh_reset_failed: 1452 ql_log(ql_log_info, vha, 0x800f, 1453 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1454 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1455 cmd); 1456 return FAILED; 1457 } 1458 1459 static int 1460 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1461 { 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1463 struct qla_hw_data *ha = vha->hw; 1464 1465 if (qla2x00_isp_reg_stat(ha)) { 1466 ql_log(ql_log_info, vha, 0x803e, 1467 "PCI/Register disconnect, exiting.\n"); 1468 return FAILED; 1469 } 1470 1471 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1472 ha->isp_ops->lun_reset); 1473 } 1474 1475 static int 1476 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1477 { 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1479 struct qla_hw_data *ha = vha->hw; 1480 1481 if (qla2x00_isp_reg_stat(ha)) { 1482 ql_log(ql_log_info, vha, 0x803f, 1483 "PCI/Register disconnect, exiting.\n"); 1484 return FAILED; 1485 } 1486 1487 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1488 ha->isp_ops->target_reset); 1489 } 1490 1491 /************************************************************************** 1492 * qla2xxx_eh_bus_reset 1493 * 1494 * Description: 1495 * The bus reset function will reset the bus and abort any executing 1496 * commands. 1497 * 1498 * Input: 1499 * cmd = Linux SCSI command packet of the command that cause the 1500 * bus reset. 1501 * 1502 * Returns: 1503 * SUCCESS/FAILURE (defined as macro in scsi.h). 1504 * 1505 **************************************************************************/ 1506 static int 1507 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1508 { 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1510 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1511 int ret = FAILED; 1512 unsigned int id; 1513 uint64_t lun; 1514 struct qla_hw_data *ha = vha->hw; 1515 1516 if (qla2x00_isp_reg_stat(ha)) { 1517 ql_log(ql_log_info, vha, 0x8040, 1518 "PCI/Register disconnect, exiting.\n"); 1519 return FAILED; 1520 } 1521 1522 id = cmd->device->id; 1523 lun = cmd->device->lun; 1524 1525 if (!fcport) { 1526 return ret; 1527 } 1528 1529 ret = fc_block_scsi_eh(cmd); 1530 if (ret != 0) 1531 return ret; 1532 ret = FAILED; 1533 1534 ql_log(ql_log_info, vha, 0x8012, 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1536 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1538 ql_log(ql_log_fatal, vha, 0x8013, 1539 "Wait for hba online failed board disabled.\n"); 1540 goto eh_bus_reset_done; 1541 } 1542 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1544 ret = SUCCESS; 1545 1546 if (ret == FAILED) 1547 goto eh_bus_reset_done; 1548 1549 /* Flush outstanding commands. */ 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1551 QLA_SUCCESS) { 1552 ql_log(ql_log_warn, vha, 0x8014, 1553 "Wait for pending commands failed.\n"); 1554 ret = FAILED; 1555 } 1556 1557 eh_bus_reset_done: 1558 ql_log(ql_log_warn, vha, 0x802b, 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1561 1562 return ret; 1563 } 1564 1565 /************************************************************************** 1566 * qla2xxx_eh_host_reset 1567 * 1568 * Description: 1569 * The reset function will reset the Adapter. 1570 * 1571 * Input: 1572 * cmd = Linux SCSI command packet of the command that cause the 1573 * adapter reset. 1574 * 1575 * Returns: 1576 * Either SUCCESS or FAILED. 1577 * 1578 * Note: 1579 **************************************************************************/ 1580 static int 1581 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1582 { 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1584 struct qla_hw_data *ha = vha->hw; 1585 int ret = FAILED; 1586 unsigned int id; 1587 uint64_t lun; 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1589 1590 if (qla2x00_isp_reg_stat(ha)) { 1591 ql_log(ql_log_info, vha, 0x8041, 1592 "PCI/Register disconnect, exiting.\n"); 1593 schedule_work(&ha->board_disable); 1594 return SUCCESS; 1595 } 1596 1597 id = cmd->device->id; 1598 lun = cmd->device->lun; 1599 1600 ql_log(ql_log_info, vha, 0x8018, 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1602 1603 /* 1604 * No point in issuing another reset if one is active. Also do not 1605 * attempt a reset if we are updating flash. 1606 */ 1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1608 goto eh_host_reset_lock; 1609 1610 if (vha != base_vha) { 1611 if (qla2x00_vp_abort_isp(vha)) 1612 goto eh_host_reset_lock; 1613 } else { 1614 if (IS_P3P_TYPE(vha->hw)) { 1615 if (!qla82xx_fcoe_ctx_reset(vha)) { 1616 /* Ctx reset success */ 1617 ret = SUCCESS; 1618 goto eh_host_reset_lock; 1619 } 1620 /* fall thru if ctx reset failed */ 1621 } 1622 if (ha->wq) 1623 flush_workqueue(ha->wq); 1624 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 if (ha->isp_ops->abort_isp(base_vha)) { 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1628 /* failed. schedule dpc to try */ 1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1630 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1632 ql_log(ql_log_warn, vha, 0x802a, 1633 "wait for hba online failed.\n"); 1634 goto eh_host_reset_lock; 1635 } 1636 } 1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1638 } 1639 1640 /* Waiting for command to be returned to OS.*/ 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1642 QLA_SUCCESS) 1643 ret = SUCCESS; 1644 1645 eh_host_reset_lock: 1646 ql_log(ql_log_info, vha, 0x8017, 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1649 1650 return ret; 1651 } 1652 1653 /* 1654 * qla2x00_loop_reset 1655 * Issue loop reset. 1656 * 1657 * Input: 1658 * ha = adapter block pointer. 1659 * 1660 * Returns: 1661 * 0 = success 1662 */ 1663 int 1664 qla2x00_loop_reset(scsi_qla_host_t *vha) 1665 { 1666 int ret; 1667 struct fc_port *fcport; 1668 struct qla_hw_data *ha = vha->hw; 1669 1670 if (IS_QLAFX00(ha)) { 1671 return qlafx00_loop_reset(vha); 1672 } 1673 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1676 if (fcport->port_type != FCT_TARGET) 1677 continue; 1678 1679 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1680 if (ret != QLA_SUCCESS) { 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1682 "Bus Reset failed: Reset=%d " 1683 "d_id=%x.\n", ret, fcport->d_id.b24); 1684 } 1685 } 1686 } 1687 1688 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1690 atomic_set(&vha->loop_state, LOOP_DOWN); 1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1692 qla2x00_mark_all_devices_lost(vha, 0); 1693 ret = qla2x00_full_login_lip(vha); 1694 if (ret != QLA_SUCCESS) { 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1696 "full_login_lip=%d.\n", ret); 1697 } 1698 } 1699 1700 if (ha->flags.enable_lip_reset) { 1701 ret = qla2x00_lip_reset(vha); 1702 if (ret != QLA_SUCCESS) 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1704 "lip_reset failed (%d).\n", ret); 1705 } 1706 1707 /* Issue marker command only when we are going to start the I/O */ 1708 vha->marker_needed = 1; 1709 1710 return QLA_SUCCESS; 1711 } 1712 1713 static void 1714 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1715 { 1716 int cnt, status; 1717 unsigned long flags; 1718 srb_t *sp; 1719 scsi_qla_host_t *vha = qp->vha; 1720 struct qla_hw_data *ha = vha->hw; 1721 struct req_que *req; 1722 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1723 struct qla_tgt_cmd *cmd; 1724 uint8_t trace = 0; 1725 1726 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1727 req = qp->req; 1728 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1729 sp = req->outstanding_cmds[cnt]; 1730 if (sp) { 1731 req->outstanding_cmds[cnt] = NULL; 1732 if (sp->cmd_type == TYPE_SRB) { 1733 if (sp->type == SRB_NVME_CMD || 1734 sp->type == SRB_NVME_LS) { 1735 sp_get(sp); 1736 spin_unlock_irqrestore(qp->qp_lock_ptr, 1737 flags); 1738 qla_nvme_abort(ha, sp); 1739 spin_lock_irqsave(qp->qp_lock_ptr, 1740 flags); 1741 } else if (GET_CMD_SP(sp) && 1742 !ha->flags.eeh_busy && 1743 (!test_bit(ABORT_ISP_ACTIVE, 1744 &vha->dpc_flags)) && 1745 (sp->type == SRB_SCSI_CMD)) { 1746 /* 1747 * Don't abort commands in 1748 * adapter during EEH 1749 * recovery as it's not 1750 * accessible/responding. 1751 * 1752 * Get a reference to the sp 1753 * and drop the lock. The 1754 * reference ensures this 1755 * sp->done() call and not the 1756 * call in qla2xxx_eh_abort() 1757 * ends the SCSI command (with 1758 * result 'res'). 1759 */ 1760 sp_get(sp); 1761 spin_unlock_irqrestore(qp->qp_lock_ptr, 1762 flags); 1763 status = qla2xxx_eh_abort( 1764 GET_CMD_SP(sp)); 1765 spin_lock_irqsave(qp->qp_lock_ptr, 1766 flags); 1767 /* 1768 * Get rid of extra reference 1769 * if immediate exit from 1770 * ql2xxx_eh_abort 1771 */ 1772 if (status == FAILED && 1773 (qla2x00_isp_reg_stat(ha))) 1774 atomic_dec( 1775 &sp->ref_count); 1776 } 1777 sp->done(sp, res); 1778 } else { 1779 if (!vha->hw->tgt.tgt_ops || !tgt || 1780 qla_ini_mode_enabled(vha)) { 1781 if (!trace) 1782 ql_dbg(ql_dbg_tgt_mgt, 1783 vha, 0xf003, 1784 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1785 vha->dpc_flags); 1786 continue; 1787 } 1788 cmd = (struct qla_tgt_cmd *)sp; 1789 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1790 } 1791 } 1792 } 1793 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1794 } 1795 1796 void 1797 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1798 { 1799 int que; 1800 struct qla_hw_data *ha = vha->hw; 1801 1802 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1803 1804 for (que = 0; que < ha->max_qpairs; que++) { 1805 if (!ha->queue_pair_map[que]) 1806 continue; 1807 1808 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1809 } 1810 } 1811 1812 static int 1813 qla2xxx_slave_alloc(struct scsi_device *sdev) 1814 { 1815 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1816 1817 if (!rport || fc_remote_port_chkready(rport)) 1818 return -ENXIO; 1819 1820 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1821 1822 return 0; 1823 } 1824 1825 static int 1826 qla2xxx_slave_configure(struct scsi_device *sdev) 1827 { 1828 scsi_qla_host_t *vha = shost_priv(sdev->host); 1829 struct req_que *req = vha->req; 1830 1831 if (IS_T10_PI_CAPABLE(vha->hw)) 1832 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1833 1834 scsi_change_queue_depth(sdev, req->max_q_depth); 1835 return 0; 1836 } 1837 1838 static void 1839 qla2xxx_slave_destroy(struct scsi_device *sdev) 1840 { 1841 sdev->hostdata = NULL; 1842 } 1843 1844 /** 1845 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1846 * @ha: HA context 1847 * 1848 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1849 * supported addressing method. 1850 */ 1851 static void 1852 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1853 { 1854 /* Assume a 32bit DMA mask. */ 1855 ha->flags.enable_64bit_addressing = 0; 1856 1857 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1858 /* Any upper-dword bits set? */ 1859 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1860 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1861 /* Ok, a 64bit DMA mask is applicable. */ 1862 ha->flags.enable_64bit_addressing = 1; 1863 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1864 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1865 return; 1866 } 1867 } 1868 1869 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1870 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1871 } 1872 1873 static void 1874 qla2x00_enable_intrs(struct qla_hw_data *ha) 1875 { 1876 unsigned long flags = 0; 1877 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1878 1879 spin_lock_irqsave(&ha->hardware_lock, flags); 1880 ha->interrupts_on = 1; 1881 /* enable risc and host interrupts */ 1882 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1883 RD_REG_WORD(®->ictrl); 1884 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1885 1886 } 1887 1888 static void 1889 qla2x00_disable_intrs(struct qla_hw_data *ha) 1890 { 1891 unsigned long flags = 0; 1892 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1893 1894 spin_lock_irqsave(&ha->hardware_lock, flags); 1895 ha->interrupts_on = 0; 1896 /* disable risc and host interrupts */ 1897 WRT_REG_WORD(®->ictrl, 0); 1898 RD_REG_WORD(®->ictrl); 1899 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1900 } 1901 1902 static void 1903 qla24xx_enable_intrs(struct qla_hw_data *ha) 1904 { 1905 unsigned long flags = 0; 1906 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1907 1908 spin_lock_irqsave(&ha->hardware_lock, flags); 1909 ha->interrupts_on = 1; 1910 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1911 RD_REG_DWORD(®->ictrl); 1912 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1913 } 1914 1915 static void 1916 qla24xx_disable_intrs(struct qla_hw_data *ha) 1917 { 1918 unsigned long flags = 0; 1919 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1920 1921 if (IS_NOPOLLING_TYPE(ha)) 1922 return; 1923 spin_lock_irqsave(&ha->hardware_lock, flags); 1924 ha->interrupts_on = 0; 1925 WRT_REG_DWORD(®->ictrl, 0); 1926 RD_REG_DWORD(®->ictrl); 1927 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1928 } 1929 1930 static int 1931 qla2x00_iospace_config(struct qla_hw_data *ha) 1932 { 1933 resource_size_t pio; 1934 uint16_t msix; 1935 1936 if (pci_request_selected_regions(ha->pdev, ha->bars, 1937 QLA2XXX_DRIVER_NAME)) { 1938 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1939 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1940 pci_name(ha->pdev)); 1941 goto iospace_error_exit; 1942 } 1943 if (!(ha->bars & 1)) 1944 goto skip_pio; 1945 1946 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1947 pio = pci_resource_start(ha->pdev, 0); 1948 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1949 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1950 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1951 "Invalid pci I/O region size (%s).\n", 1952 pci_name(ha->pdev)); 1953 pio = 0; 1954 } 1955 } else { 1956 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1957 "Region #0 no a PIO resource (%s).\n", 1958 pci_name(ha->pdev)); 1959 pio = 0; 1960 } 1961 ha->pio_address = pio; 1962 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1963 "PIO address=%llu.\n", 1964 (unsigned long long)ha->pio_address); 1965 1966 skip_pio: 1967 /* Use MMIO operations for all accesses. */ 1968 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1969 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1970 "Region #1 not an MMIO resource (%s), aborting.\n", 1971 pci_name(ha->pdev)); 1972 goto iospace_error_exit; 1973 } 1974 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1976 "Invalid PCI mem region size (%s), aborting.\n", 1977 pci_name(ha->pdev)); 1978 goto iospace_error_exit; 1979 } 1980 1981 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1982 if (!ha->iobase) { 1983 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1984 "Cannot remap MMIO (%s), aborting.\n", 1985 pci_name(ha->pdev)); 1986 goto iospace_error_exit; 1987 } 1988 1989 /* Determine queue resources */ 1990 ha->max_req_queues = ha->max_rsp_queues = 1; 1991 ha->msix_count = QLA_BASE_VECTORS; 1992 if (!ql2xmqsupport || !ql2xnvmeenable || 1993 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1994 goto mqiobase_exit; 1995 1996 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1997 pci_resource_len(ha->pdev, 3)); 1998 if (ha->mqiobase) { 1999 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2000 "MQIO Base=%p.\n", ha->mqiobase); 2001 /* Read MSIX vector size of the board */ 2002 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2003 ha->msix_count = msix + 1; 2004 /* Max queues are bounded by available msix vectors */ 2005 /* MB interrupt uses 1 vector */ 2006 ha->max_req_queues = ha->msix_count - 1; 2007 ha->max_rsp_queues = ha->max_req_queues; 2008 /* Queue pairs is the max value minus the base queue pair */ 2009 ha->max_qpairs = ha->max_rsp_queues - 1; 2010 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2011 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2012 2013 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2014 "MSI-X vector count: %d.\n", ha->msix_count); 2015 } else 2016 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2017 "BAR 3 not enabled.\n"); 2018 2019 mqiobase_exit: 2020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2021 "MSIX Count: %d.\n", ha->msix_count); 2022 return (0); 2023 2024 iospace_error_exit: 2025 return (-ENOMEM); 2026 } 2027 2028 2029 static int 2030 qla83xx_iospace_config(struct qla_hw_data *ha) 2031 { 2032 uint16_t msix; 2033 2034 if (pci_request_selected_regions(ha->pdev, ha->bars, 2035 QLA2XXX_DRIVER_NAME)) { 2036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2037 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2038 pci_name(ha->pdev)); 2039 2040 goto iospace_error_exit; 2041 } 2042 2043 /* Use MMIO operations for all accesses. */ 2044 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2045 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2046 "Invalid pci I/O region size (%s).\n", 2047 pci_name(ha->pdev)); 2048 goto iospace_error_exit; 2049 } 2050 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2051 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2052 "Invalid PCI mem region size (%s), aborting\n", 2053 pci_name(ha->pdev)); 2054 goto iospace_error_exit; 2055 } 2056 2057 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2058 if (!ha->iobase) { 2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2060 "Cannot remap MMIO (%s), aborting.\n", 2061 pci_name(ha->pdev)); 2062 goto iospace_error_exit; 2063 } 2064 2065 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2066 /* 83XX 26XX always use MQ type access for queues 2067 * - mbar 2, a.k.a region 4 */ 2068 ha->max_req_queues = ha->max_rsp_queues = 1; 2069 ha->msix_count = QLA_BASE_VECTORS; 2070 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2071 pci_resource_len(ha->pdev, 4)); 2072 2073 if (!ha->mqiobase) { 2074 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2075 "BAR2/region4 not enabled\n"); 2076 goto mqiobase_exit; 2077 } 2078 2079 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2080 pci_resource_len(ha->pdev, 2)); 2081 if (ha->msixbase) { 2082 /* Read MSIX vector size of the board */ 2083 pci_read_config_word(ha->pdev, 2084 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2085 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2086 /* 2087 * By default, driver uses at least two msix vectors 2088 * (default & rspq) 2089 */ 2090 if (ql2xmqsupport || ql2xnvmeenable) { 2091 /* MB interrupt uses 1 vector */ 2092 ha->max_req_queues = ha->msix_count - 1; 2093 2094 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2095 if (QLA_TGT_MODE_ENABLED()) 2096 ha->max_req_queues--; 2097 2098 ha->max_rsp_queues = ha->max_req_queues; 2099 2100 /* Queue pairs is the max value minus 2101 * the base queue pair */ 2102 ha->max_qpairs = ha->max_req_queues - 1; 2103 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2104 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2105 } 2106 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2107 "MSI-X vector count: %d.\n", ha->msix_count); 2108 } else 2109 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2110 "BAR 1 not enabled.\n"); 2111 2112 mqiobase_exit: 2113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2114 "MSIX Count: %d.\n", ha->msix_count); 2115 return 0; 2116 2117 iospace_error_exit: 2118 return -ENOMEM; 2119 } 2120 2121 static struct isp_operations qla2100_isp_ops = { 2122 .pci_config = qla2100_pci_config, 2123 .reset_chip = qla2x00_reset_chip, 2124 .chip_diag = qla2x00_chip_diag, 2125 .config_rings = qla2x00_config_rings, 2126 .reset_adapter = qla2x00_reset_adapter, 2127 .nvram_config = qla2x00_nvram_config, 2128 .update_fw_options = qla2x00_update_fw_options, 2129 .load_risc = qla2x00_load_risc, 2130 .pci_info_str = qla2x00_pci_info_str, 2131 .fw_version_str = qla2x00_fw_version_str, 2132 .intr_handler = qla2100_intr_handler, 2133 .enable_intrs = qla2x00_enable_intrs, 2134 .disable_intrs = qla2x00_disable_intrs, 2135 .abort_command = qla2x00_abort_command, 2136 .target_reset = qla2x00_abort_target, 2137 .lun_reset = qla2x00_lun_reset, 2138 .fabric_login = qla2x00_login_fabric, 2139 .fabric_logout = qla2x00_fabric_logout, 2140 .calc_req_entries = qla2x00_calc_iocbs_32, 2141 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2142 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2143 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2144 .read_nvram = qla2x00_read_nvram_data, 2145 .write_nvram = qla2x00_write_nvram_data, 2146 .fw_dump = qla2100_fw_dump, 2147 .beacon_on = NULL, 2148 .beacon_off = NULL, 2149 .beacon_blink = NULL, 2150 .read_optrom = qla2x00_read_optrom_data, 2151 .write_optrom = qla2x00_write_optrom_data, 2152 .get_flash_version = qla2x00_get_flash_version, 2153 .start_scsi = qla2x00_start_scsi, 2154 .start_scsi_mq = NULL, 2155 .abort_isp = qla2x00_abort_isp, 2156 .iospace_config = qla2x00_iospace_config, 2157 .initialize_adapter = qla2x00_initialize_adapter, 2158 }; 2159 2160 static struct isp_operations qla2300_isp_ops = { 2161 .pci_config = qla2300_pci_config, 2162 .reset_chip = qla2x00_reset_chip, 2163 .chip_diag = qla2x00_chip_diag, 2164 .config_rings = qla2x00_config_rings, 2165 .reset_adapter = qla2x00_reset_adapter, 2166 .nvram_config = qla2x00_nvram_config, 2167 .update_fw_options = qla2x00_update_fw_options, 2168 .load_risc = qla2x00_load_risc, 2169 .pci_info_str = qla2x00_pci_info_str, 2170 .fw_version_str = qla2x00_fw_version_str, 2171 .intr_handler = qla2300_intr_handler, 2172 .enable_intrs = qla2x00_enable_intrs, 2173 .disable_intrs = qla2x00_disable_intrs, 2174 .abort_command = qla2x00_abort_command, 2175 .target_reset = qla2x00_abort_target, 2176 .lun_reset = qla2x00_lun_reset, 2177 .fabric_login = qla2x00_login_fabric, 2178 .fabric_logout = qla2x00_fabric_logout, 2179 .calc_req_entries = qla2x00_calc_iocbs_32, 2180 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2181 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2182 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2183 .read_nvram = qla2x00_read_nvram_data, 2184 .write_nvram = qla2x00_write_nvram_data, 2185 .fw_dump = qla2300_fw_dump, 2186 .beacon_on = qla2x00_beacon_on, 2187 .beacon_off = qla2x00_beacon_off, 2188 .beacon_blink = qla2x00_beacon_blink, 2189 .read_optrom = qla2x00_read_optrom_data, 2190 .write_optrom = qla2x00_write_optrom_data, 2191 .get_flash_version = qla2x00_get_flash_version, 2192 .start_scsi = qla2x00_start_scsi, 2193 .start_scsi_mq = NULL, 2194 .abort_isp = qla2x00_abort_isp, 2195 .iospace_config = qla2x00_iospace_config, 2196 .initialize_adapter = qla2x00_initialize_adapter, 2197 }; 2198 2199 static struct isp_operations qla24xx_isp_ops = { 2200 .pci_config = qla24xx_pci_config, 2201 .reset_chip = qla24xx_reset_chip, 2202 .chip_diag = qla24xx_chip_diag, 2203 .config_rings = qla24xx_config_rings, 2204 .reset_adapter = qla24xx_reset_adapter, 2205 .nvram_config = qla24xx_nvram_config, 2206 .update_fw_options = qla24xx_update_fw_options, 2207 .load_risc = qla24xx_load_risc, 2208 .pci_info_str = qla24xx_pci_info_str, 2209 .fw_version_str = qla24xx_fw_version_str, 2210 .intr_handler = qla24xx_intr_handler, 2211 .enable_intrs = qla24xx_enable_intrs, 2212 .disable_intrs = qla24xx_disable_intrs, 2213 .abort_command = qla24xx_abort_command, 2214 .target_reset = qla24xx_abort_target, 2215 .lun_reset = qla24xx_lun_reset, 2216 .fabric_login = qla24xx_login_fabric, 2217 .fabric_logout = qla24xx_fabric_logout, 2218 .calc_req_entries = NULL, 2219 .build_iocbs = NULL, 2220 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2221 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2222 .read_nvram = qla24xx_read_nvram_data, 2223 .write_nvram = qla24xx_write_nvram_data, 2224 .fw_dump = qla24xx_fw_dump, 2225 .beacon_on = qla24xx_beacon_on, 2226 .beacon_off = qla24xx_beacon_off, 2227 .beacon_blink = qla24xx_beacon_blink, 2228 .read_optrom = qla24xx_read_optrom_data, 2229 .write_optrom = qla24xx_write_optrom_data, 2230 .get_flash_version = qla24xx_get_flash_version, 2231 .start_scsi = qla24xx_start_scsi, 2232 .start_scsi_mq = NULL, 2233 .abort_isp = qla2x00_abort_isp, 2234 .iospace_config = qla2x00_iospace_config, 2235 .initialize_adapter = qla2x00_initialize_adapter, 2236 }; 2237 2238 static struct isp_operations qla25xx_isp_ops = { 2239 .pci_config = qla25xx_pci_config, 2240 .reset_chip = qla24xx_reset_chip, 2241 .chip_diag = qla24xx_chip_diag, 2242 .config_rings = qla24xx_config_rings, 2243 .reset_adapter = qla24xx_reset_adapter, 2244 .nvram_config = qla24xx_nvram_config, 2245 .update_fw_options = qla24xx_update_fw_options, 2246 .load_risc = qla24xx_load_risc, 2247 .pci_info_str = qla24xx_pci_info_str, 2248 .fw_version_str = qla24xx_fw_version_str, 2249 .intr_handler = qla24xx_intr_handler, 2250 .enable_intrs = qla24xx_enable_intrs, 2251 .disable_intrs = qla24xx_disable_intrs, 2252 .abort_command = qla24xx_abort_command, 2253 .target_reset = qla24xx_abort_target, 2254 .lun_reset = qla24xx_lun_reset, 2255 .fabric_login = qla24xx_login_fabric, 2256 .fabric_logout = qla24xx_fabric_logout, 2257 .calc_req_entries = NULL, 2258 .build_iocbs = NULL, 2259 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2260 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2261 .read_nvram = qla25xx_read_nvram_data, 2262 .write_nvram = qla25xx_write_nvram_data, 2263 .fw_dump = qla25xx_fw_dump, 2264 .beacon_on = qla24xx_beacon_on, 2265 .beacon_off = qla24xx_beacon_off, 2266 .beacon_blink = qla24xx_beacon_blink, 2267 .read_optrom = qla25xx_read_optrom_data, 2268 .write_optrom = qla24xx_write_optrom_data, 2269 .get_flash_version = qla24xx_get_flash_version, 2270 .start_scsi = qla24xx_dif_start_scsi, 2271 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2272 .abort_isp = qla2x00_abort_isp, 2273 .iospace_config = qla2x00_iospace_config, 2274 .initialize_adapter = qla2x00_initialize_adapter, 2275 }; 2276 2277 static struct isp_operations qla81xx_isp_ops = { 2278 .pci_config = qla25xx_pci_config, 2279 .reset_chip = qla24xx_reset_chip, 2280 .chip_diag = qla24xx_chip_diag, 2281 .config_rings = qla24xx_config_rings, 2282 .reset_adapter = qla24xx_reset_adapter, 2283 .nvram_config = qla81xx_nvram_config, 2284 .update_fw_options = qla81xx_update_fw_options, 2285 .load_risc = qla81xx_load_risc, 2286 .pci_info_str = qla24xx_pci_info_str, 2287 .fw_version_str = qla24xx_fw_version_str, 2288 .intr_handler = qla24xx_intr_handler, 2289 .enable_intrs = qla24xx_enable_intrs, 2290 .disable_intrs = qla24xx_disable_intrs, 2291 .abort_command = qla24xx_abort_command, 2292 .target_reset = qla24xx_abort_target, 2293 .lun_reset = qla24xx_lun_reset, 2294 .fabric_login = qla24xx_login_fabric, 2295 .fabric_logout = qla24xx_fabric_logout, 2296 .calc_req_entries = NULL, 2297 .build_iocbs = NULL, 2298 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2299 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2300 .read_nvram = NULL, 2301 .write_nvram = NULL, 2302 .fw_dump = qla81xx_fw_dump, 2303 .beacon_on = qla24xx_beacon_on, 2304 .beacon_off = qla24xx_beacon_off, 2305 .beacon_blink = qla83xx_beacon_blink, 2306 .read_optrom = qla25xx_read_optrom_data, 2307 .write_optrom = qla24xx_write_optrom_data, 2308 .get_flash_version = qla24xx_get_flash_version, 2309 .start_scsi = qla24xx_dif_start_scsi, 2310 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2311 .abort_isp = qla2x00_abort_isp, 2312 .iospace_config = qla2x00_iospace_config, 2313 .initialize_adapter = qla2x00_initialize_adapter, 2314 }; 2315 2316 static struct isp_operations qla82xx_isp_ops = { 2317 .pci_config = qla82xx_pci_config, 2318 .reset_chip = qla82xx_reset_chip, 2319 .chip_diag = qla24xx_chip_diag, 2320 .config_rings = qla82xx_config_rings, 2321 .reset_adapter = qla24xx_reset_adapter, 2322 .nvram_config = qla81xx_nvram_config, 2323 .update_fw_options = qla24xx_update_fw_options, 2324 .load_risc = qla82xx_load_risc, 2325 .pci_info_str = qla24xx_pci_info_str, 2326 .fw_version_str = qla24xx_fw_version_str, 2327 .intr_handler = qla82xx_intr_handler, 2328 .enable_intrs = qla82xx_enable_intrs, 2329 .disable_intrs = qla82xx_disable_intrs, 2330 .abort_command = qla24xx_abort_command, 2331 .target_reset = qla24xx_abort_target, 2332 .lun_reset = qla24xx_lun_reset, 2333 .fabric_login = qla24xx_login_fabric, 2334 .fabric_logout = qla24xx_fabric_logout, 2335 .calc_req_entries = NULL, 2336 .build_iocbs = NULL, 2337 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2338 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2339 .read_nvram = qla24xx_read_nvram_data, 2340 .write_nvram = qla24xx_write_nvram_data, 2341 .fw_dump = qla82xx_fw_dump, 2342 .beacon_on = qla82xx_beacon_on, 2343 .beacon_off = qla82xx_beacon_off, 2344 .beacon_blink = NULL, 2345 .read_optrom = qla82xx_read_optrom_data, 2346 .write_optrom = qla82xx_write_optrom_data, 2347 .get_flash_version = qla82xx_get_flash_version, 2348 .start_scsi = qla82xx_start_scsi, 2349 .start_scsi_mq = NULL, 2350 .abort_isp = qla82xx_abort_isp, 2351 .iospace_config = qla82xx_iospace_config, 2352 .initialize_adapter = qla2x00_initialize_adapter, 2353 }; 2354 2355 static struct isp_operations qla8044_isp_ops = { 2356 .pci_config = qla82xx_pci_config, 2357 .reset_chip = qla82xx_reset_chip, 2358 .chip_diag = qla24xx_chip_diag, 2359 .config_rings = qla82xx_config_rings, 2360 .reset_adapter = qla24xx_reset_adapter, 2361 .nvram_config = qla81xx_nvram_config, 2362 .update_fw_options = qla24xx_update_fw_options, 2363 .load_risc = qla82xx_load_risc, 2364 .pci_info_str = qla24xx_pci_info_str, 2365 .fw_version_str = qla24xx_fw_version_str, 2366 .intr_handler = qla8044_intr_handler, 2367 .enable_intrs = qla82xx_enable_intrs, 2368 .disable_intrs = qla82xx_disable_intrs, 2369 .abort_command = qla24xx_abort_command, 2370 .target_reset = qla24xx_abort_target, 2371 .lun_reset = qla24xx_lun_reset, 2372 .fabric_login = qla24xx_login_fabric, 2373 .fabric_logout = qla24xx_fabric_logout, 2374 .calc_req_entries = NULL, 2375 .build_iocbs = NULL, 2376 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2377 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2378 .read_nvram = NULL, 2379 .write_nvram = NULL, 2380 .fw_dump = qla8044_fw_dump, 2381 .beacon_on = qla82xx_beacon_on, 2382 .beacon_off = qla82xx_beacon_off, 2383 .beacon_blink = NULL, 2384 .read_optrom = qla8044_read_optrom_data, 2385 .write_optrom = qla8044_write_optrom_data, 2386 .get_flash_version = qla82xx_get_flash_version, 2387 .start_scsi = qla82xx_start_scsi, 2388 .start_scsi_mq = NULL, 2389 .abort_isp = qla8044_abort_isp, 2390 .iospace_config = qla82xx_iospace_config, 2391 .initialize_adapter = qla2x00_initialize_adapter, 2392 }; 2393 2394 static struct isp_operations qla83xx_isp_ops = { 2395 .pci_config = qla25xx_pci_config, 2396 .reset_chip = qla24xx_reset_chip, 2397 .chip_diag = qla24xx_chip_diag, 2398 .config_rings = qla24xx_config_rings, 2399 .reset_adapter = qla24xx_reset_adapter, 2400 .nvram_config = qla81xx_nvram_config, 2401 .update_fw_options = qla81xx_update_fw_options, 2402 .load_risc = qla81xx_load_risc, 2403 .pci_info_str = qla24xx_pci_info_str, 2404 .fw_version_str = qla24xx_fw_version_str, 2405 .intr_handler = qla24xx_intr_handler, 2406 .enable_intrs = qla24xx_enable_intrs, 2407 .disable_intrs = qla24xx_disable_intrs, 2408 .abort_command = qla24xx_abort_command, 2409 .target_reset = qla24xx_abort_target, 2410 .lun_reset = qla24xx_lun_reset, 2411 .fabric_login = qla24xx_login_fabric, 2412 .fabric_logout = qla24xx_fabric_logout, 2413 .calc_req_entries = NULL, 2414 .build_iocbs = NULL, 2415 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2416 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2417 .read_nvram = NULL, 2418 .write_nvram = NULL, 2419 .fw_dump = qla83xx_fw_dump, 2420 .beacon_on = qla24xx_beacon_on, 2421 .beacon_off = qla24xx_beacon_off, 2422 .beacon_blink = qla83xx_beacon_blink, 2423 .read_optrom = qla25xx_read_optrom_data, 2424 .write_optrom = qla24xx_write_optrom_data, 2425 .get_flash_version = qla24xx_get_flash_version, 2426 .start_scsi = qla24xx_dif_start_scsi, 2427 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2428 .abort_isp = qla2x00_abort_isp, 2429 .iospace_config = qla83xx_iospace_config, 2430 .initialize_adapter = qla2x00_initialize_adapter, 2431 }; 2432 2433 static struct isp_operations qlafx00_isp_ops = { 2434 .pci_config = qlafx00_pci_config, 2435 .reset_chip = qlafx00_soft_reset, 2436 .chip_diag = qlafx00_chip_diag, 2437 .config_rings = qlafx00_config_rings, 2438 .reset_adapter = qlafx00_soft_reset, 2439 .nvram_config = NULL, 2440 .update_fw_options = NULL, 2441 .load_risc = NULL, 2442 .pci_info_str = qlafx00_pci_info_str, 2443 .fw_version_str = qlafx00_fw_version_str, 2444 .intr_handler = qlafx00_intr_handler, 2445 .enable_intrs = qlafx00_enable_intrs, 2446 .disable_intrs = qlafx00_disable_intrs, 2447 .abort_command = qla24xx_async_abort_command, 2448 .target_reset = qlafx00_abort_target, 2449 .lun_reset = qlafx00_lun_reset, 2450 .fabric_login = NULL, 2451 .fabric_logout = NULL, 2452 .calc_req_entries = NULL, 2453 .build_iocbs = NULL, 2454 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2455 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2456 .read_nvram = qla24xx_read_nvram_data, 2457 .write_nvram = qla24xx_write_nvram_data, 2458 .fw_dump = NULL, 2459 .beacon_on = qla24xx_beacon_on, 2460 .beacon_off = qla24xx_beacon_off, 2461 .beacon_blink = NULL, 2462 .read_optrom = qla24xx_read_optrom_data, 2463 .write_optrom = qla24xx_write_optrom_data, 2464 .get_flash_version = qla24xx_get_flash_version, 2465 .start_scsi = qlafx00_start_scsi, 2466 .start_scsi_mq = NULL, 2467 .abort_isp = qlafx00_abort_isp, 2468 .iospace_config = qlafx00_iospace_config, 2469 .initialize_adapter = qlafx00_initialize_adapter, 2470 }; 2471 2472 static struct isp_operations qla27xx_isp_ops = { 2473 .pci_config = qla25xx_pci_config, 2474 .reset_chip = qla24xx_reset_chip, 2475 .chip_diag = qla24xx_chip_diag, 2476 .config_rings = qla24xx_config_rings, 2477 .reset_adapter = qla24xx_reset_adapter, 2478 .nvram_config = qla81xx_nvram_config, 2479 .update_fw_options = qla81xx_update_fw_options, 2480 .load_risc = qla81xx_load_risc, 2481 .pci_info_str = qla24xx_pci_info_str, 2482 .fw_version_str = qla24xx_fw_version_str, 2483 .intr_handler = qla24xx_intr_handler, 2484 .enable_intrs = qla24xx_enable_intrs, 2485 .disable_intrs = qla24xx_disable_intrs, 2486 .abort_command = qla24xx_abort_command, 2487 .target_reset = qla24xx_abort_target, 2488 .lun_reset = qla24xx_lun_reset, 2489 .fabric_login = qla24xx_login_fabric, 2490 .fabric_logout = qla24xx_fabric_logout, 2491 .calc_req_entries = NULL, 2492 .build_iocbs = NULL, 2493 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2494 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2495 .read_nvram = NULL, 2496 .write_nvram = NULL, 2497 .fw_dump = qla27xx_fwdump, 2498 .beacon_on = qla24xx_beacon_on, 2499 .beacon_off = qla24xx_beacon_off, 2500 .beacon_blink = qla83xx_beacon_blink, 2501 .read_optrom = qla25xx_read_optrom_data, 2502 .write_optrom = qla24xx_write_optrom_data, 2503 .get_flash_version = qla24xx_get_flash_version, 2504 .start_scsi = qla24xx_dif_start_scsi, 2505 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2506 .abort_isp = qla2x00_abort_isp, 2507 .iospace_config = qla83xx_iospace_config, 2508 .initialize_adapter = qla2x00_initialize_adapter, 2509 }; 2510 2511 static inline void 2512 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2513 { 2514 ha->device_type = DT_EXTENDED_IDS; 2515 switch (ha->pdev->device) { 2516 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2517 ha->isp_type |= DT_ISP2100; 2518 ha->device_type &= ~DT_EXTENDED_IDS; 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2520 break; 2521 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2522 ha->isp_type |= DT_ISP2200; 2523 ha->device_type &= ~DT_EXTENDED_IDS; 2524 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2525 break; 2526 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2527 ha->isp_type |= DT_ISP2300; 2528 ha->device_type |= DT_ZIO_SUPPORTED; 2529 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2530 break; 2531 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2532 ha->isp_type |= DT_ISP2312; 2533 ha->device_type |= DT_ZIO_SUPPORTED; 2534 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2535 break; 2536 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2537 ha->isp_type |= DT_ISP2322; 2538 ha->device_type |= DT_ZIO_SUPPORTED; 2539 if (ha->pdev->subsystem_vendor == 0x1028 && 2540 ha->pdev->subsystem_device == 0x0170) 2541 ha->device_type |= DT_OEM_001; 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2543 break; 2544 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2545 ha->isp_type |= DT_ISP6312; 2546 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2547 break; 2548 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2549 ha->isp_type |= DT_ISP6322; 2550 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2551 break; 2552 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2553 ha->isp_type |= DT_ISP2422; 2554 ha->device_type |= DT_ZIO_SUPPORTED; 2555 ha->device_type |= DT_FWI2; 2556 ha->device_type |= DT_IIDMA; 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2558 break; 2559 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2560 ha->isp_type |= DT_ISP2432; 2561 ha->device_type |= DT_ZIO_SUPPORTED; 2562 ha->device_type |= DT_FWI2; 2563 ha->device_type |= DT_IIDMA; 2564 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2565 break; 2566 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2567 ha->isp_type |= DT_ISP8432; 2568 ha->device_type |= DT_ZIO_SUPPORTED; 2569 ha->device_type |= DT_FWI2; 2570 ha->device_type |= DT_IIDMA; 2571 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2572 break; 2573 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2574 ha->isp_type |= DT_ISP5422; 2575 ha->device_type |= DT_FWI2; 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2577 break; 2578 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2579 ha->isp_type |= DT_ISP5432; 2580 ha->device_type |= DT_FWI2; 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2582 break; 2583 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2584 ha->isp_type |= DT_ISP2532; 2585 ha->device_type |= DT_ZIO_SUPPORTED; 2586 ha->device_type |= DT_FWI2; 2587 ha->device_type |= DT_IIDMA; 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2591 ha->isp_type |= DT_ISP8001; 2592 ha->device_type |= DT_ZIO_SUPPORTED; 2593 ha->device_type |= DT_FWI2; 2594 ha->device_type |= DT_IIDMA; 2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2596 break; 2597 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2598 ha->isp_type |= DT_ISP8021; 2599 ha->device_type |= DT_ZIO_SUPPORTED; 2600 ha->device_type |= DT_FWI2; 2601 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2602 /* Initialize 82XX ISP flags */ 2603 qla82xx_init_flags(ha); 2604 break; 2605 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2606 ha->isp_type |= DT_ISP8044; 2607 ha->device_type |= DT_ZIO_SUPPORTED; 2608 ha->device_type |= DT_FWI2; 2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2610 /* Initialize 82XX ISP flags */ 2611 qla82xx_init_flags(ha); 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2614 ha->isp_type |= DT_ISP2031; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->device_type |= DT_IIDMA; 2618 ha->device_type |= DT_T10_PI; 2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2620 break; 2621 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2622 ha->isp_type |= DT_ISP8031; 2623 ha->device_type |= DT_ZIO_SUPPORTED; 2624 ha->device_type |= DT_FWI2; 2625 ha->device_type |= DT_IIDMA; 2626 ha->device_type |= DT_T10_PI; 2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2628 break; 2629 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2630 ha->isp_type |= DT_ISPFX00; 2631 break; 2632 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2633 ha->isp_type |= DT_ISP2071; 2634 ha->device_type |= DT_ZIO_SUPPORTED; 2635 ha->device_type |= DT_FWI2; 2636 ha->device_type |= DT_IIDMA; 2637 ha->device_type |= DT_T10_PI; 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2639 break; 2640 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2641 ha->isp_type |= DT_ISP2271; 2642 ha->device_type |= DT_ZIO_SUPPORTED; 2643 ha->device_type |= DT_FWI2; 2644 ha->device_type |= DT_IIDMA; 2645 ha->device_type |= DT_T10_PI; 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2647 break; 2648 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2649 ha->isp_type |= DT_ISP2261; 2650 ha->device_type |= DT_ZIO_SUPPORTED; 2651 ha->device_type |= DT_FWI2; 2652 ha->device_type |= DT_IIDMA; 2653 ha->device_type |= DT_T10_PI; 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2655 break; 2656 } 2657 2658 if (IS_QLA82XX(ha)) 2659 ha->port_no = ha->portnum & 1; 2660 else { 2661 /* Get adapter physical port no from interrupt pin register. */ 2662 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2663 if (IS_QLA27XX(ha)) 2664 ha->port_no--; 2665 else 2666 ha->port_no = !(ha->port_no & 1); 2667 } 2668 2669 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2670 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2671 ha->device_type, ha->port_no, ha->fw_srisc_address); 2672 } 2673 2674 static void 2675 qla2xxx_scan_start(struct Scsi_Host *shost) 2676 { 2677 scsi_qla_host_t *vha = shost_priv(shost); 2678 2679 if (vha->hw->flags.running_gold_fw) 2680 return; 2681 2682 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2683 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2684 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2685 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2686 } 2687 2688 static int 2689 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2690 { 2691 scsi_qla_host_t *vha = shost_priv(shost); 2692 2693 if (test_bit(UNLOADING, &vha->dpc_flags)) 2694 return 1; 2695 if (!vha->host) 2696 return 1; 2697 if (time > vha->hw->loop_reset_delay * HZ) 2698 return 1; 2699 2700 return atomic_read(&vha->loop_state) == LOOP_READY; 2701 } 2702 2703 static void qla2x00_iocb_work_fn(struct work_struct *work) 2704 { 2705 struct scsi_qla_host *vha = container_of(work, 2706 struct scsi_qla_host, iocb_work); 2707 struct qla_hw_data *ha = vha->hw; 2708 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2709 int i = 20; 2710 unsigned long flags; 2711 2712 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2713 return; 2714 2715 while (!list_empty(&vha->work_list) && i > 0) { 2716 qla2x00_do_work(vha); 2717 i--; 2718 } 2719 2720 spin_lock_irqsave(&vha->work_lock, flags); 2721 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2722 spin_unlock_irqrestore(&vha->work_lock, flags); 2723 } 2724 2725 /* 2726 * PCI driver interface 2727 */ 2728 static int 2729 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2730 { 2731 int ret = -ENODEV; 2732 struct Scsi_Host *host; 2733 scsi_qla_host_t *base_vha = NULL; 2734 struct qla_hw_data *ha; 2735 char pci_info[30]; 2736 char fw_str[30], wq_name[30]; 2737 struct scsi_host_template *sht; 2738 int bars, mem_only = 0; 2739 uint16_t req_length = 0, rsp_length = 0; 2740 struct req_que *req = NULL; 2741 struct rsp_que *rsp = NULL; 2742 int i; 2743 2744 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2745 sht = &qla2xxx_driver_template; 2746 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2747 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2748 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2761 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2762 mem_only = 1; 2763 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2764 "Mem only adapter.\n"); 2765 } 2766 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2767 "Bars=%d.\n", bars); 2768 2769 if (mem_only) { 2770 if (pci_enable_device_mem(pdev)) 2771 return ret; 2772 } else { 2773 if (pci_enable_device(pdev)) 2774 return ret; 2775 } 2776 2777 /* This may fail but that's ok */ 2778 pci_enable_pcie_error_reporting(pdev); 2779 2780 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2781 if (!ha) { 2782 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2783 "Unable to allocate memory for ha.\n"); 2784 goto disable_device; 2785 } 2786 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2787 "Memory allocated for ha=%p.\n", ha); 2788 ha->pdev = pdev; 2789 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2790 spin_lock_init(&ha->tgt.q_full_lock); 2791 spin_lock_init(&ha->tgt.sess_lock); 2792 spin_lock_init(&ha->tgt.atio_lock); 2793 2794 atomic_set(&ha->nvme_active_aen_cnt, 0); 2795 2796 /* Clear our data area */ 2797 ha->bars = bars; 2798 ha->mem_only = mem_only; 2799 spin_lock_init(&ha->hardware_lock); 2800 spin_lock_init(&ha->vport_slock); 2801 mutex_init(&ha->selflogin_lock); 2802 mutex_init(&ha->optrom_mutex); 2803 2804 /* Set ISP-type information. */ 2805 qla2x00_set_isp_flags(ha); 2806 2807 /* Set EEH reset type to fundamental if required by hba */ 2808 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2809 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2810 pdev->needs_freset = 1; 2811 2812 ha->prev_topology = 0; 2813 ha->init_cb_size = sizeof(init_cb_t); 2814 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2815 ha->optrom_size = OPTROM_SIZE_2300; 2816 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2817 2818 /* Assign ISP specific operations. */ 2819 if (IS_QLA2100(ha)) { 2820 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2821 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2822 req_length = REQUEST_ENTRY_CNT_2100; 2823 rsp_length = RESPONSE_ENTRY_CNT_2100; 2824 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2825 ha->gid_list_info_size = 4; 2826 ha->flash_conf_off = ~0; 2827 ha->flash_data_off = ~0; 2828 ha->nvram_conf_off = ~0; 2829 ha->nvram_data_off = ~0; 2830 ha->isp_ops = &qla2100_isp_ops; 2831 } else if (IS_QLA2200(ha)) { 2832 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2833 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2834 req_length = REQUEST_ENTRY_CNT_2200; 2835 rsp_length = RESPONSE_ENTRY_CNT_2100; 2836 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2837 ha->gid_list_info_size = 4; 2838 ha->flash_conf_off = ~0; 2839 ha->flash_data_off = ~0; 2840 ha->nvram_conf_off = ~0; 2841 ha->nvram_data_off = ~0; 2842 ha->isp_ops = &qla2100_isp_ops; 2843 } else if (IS_QLA23XX(ha)) { 2844 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2845 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2846 req_length = REQUEST_ENTRY_CNT_2200; 2847 rsp_length = RESPONSE_ENTRY_CNT_2300; 2848 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2849 ha->gid_list_info_size = 6; 2850 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2851 ha->optrom_size = OPTROM_SIZE_2322; 2852 ha->flash_conf_off = ~0; 2853 ha->flash_data_off = ~0; 2854 ha->nvram_conf_off = ~0; 2855 ha->nvram_data_off = ~0; 2856 ha->isp_ops = &qla2300_isp_ops; 2857 } else if (IS_QLA24XX_TYPE(ha)) { 2858 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2859 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2860 req_length = REQUEST_ENTRY_CNT_24XX; 2861 rsp_length = RESPONSE_ENTRY_CNT_2300; 2862 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2863 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2864 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2865 ha->gid_list_info_size = 8; 2866 ha->optrom_size = OPTROM_SIZE_24XX; 2867 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2868 ha->isp_ops = &qla24xx_isp_ops; 2869 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2870 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2871 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2872 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2873 } else if (IS_QLA25XX(ha)) { 2874 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2875 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2876 req_length = REQUEST_ENTRY_CNT_24XX; 2877 rsp_length = RESPONSE_ENTRY_CNT_2300; 2878 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2879 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2880 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2881 ha->gid_list_info_size = 8; 2882 ha->optrom_size = OPTROM_SIZE_25XX; 2883 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2884 ha->isp_ops = &qla25xx_isp_ops; 2885 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2886 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2887 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2888 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2889 } else if (IS_QLA81XX(ha)) { 2890 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2891 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2892 req_length = REQUEST_ENTRY_CNT_24XX; 2893 rsp_length = RESPONSE_ENTRY_CNT_2300; 2894 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2895 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2896 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2897 ha->gid_list_info_size = 8; 2898 ha->optrom_size = OPTROM_SIZE_81XX; 2899 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2900 ha->isp_ops = &qla81xx_isp_ops; 2901 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2902 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2903 ha->nvram_conf_off = ~0; 2904 ha->nvram_data_off = ~0; 2905 } else if (IS_QLA82XX(ha)) { 2906 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2907 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2908 req_length = REQUEST_ENTRY_CNT_82XX; 2909 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2911 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2912 ha->gid_list_info_size = 8; 2913 ha->optrom_size = OPTROM_SIZE_82XX; 2914 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2915 ha->isp_ops = &qla82xx_isp_ops; 2916 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2917 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2918 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2919 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2920 } else if (IS_QLA8044(ha)) { 2921 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2922 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2923 req_length = REQUEST_ENTRY_CNT_82XX; 2924 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2925 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2926 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2927 ha->gid_list_info_size = 8; 2928 ha->optrom_size = OPTROM_SIZE_83XX; 2929 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2930 ha->isp_ops = &qla8044_isp_ops; 2931 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2932 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2933 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2934 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2935 } else if (IS_QLA83XX(ha)) { 2936 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2937 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2938 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2939 req_length = REQUEST_ENTRY_CNT_83XX; 2940 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2941 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2942 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2943 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2944 ha->gid_list_info_size = 8; 2945 ha->optrom_size = OPTROM_SIZE_83XX; 2946 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2947 ha->isp_ops = &qla83xx_isp_ops; 2948 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2949 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2950 ha->nvram_conf_off = ~0; 2951 ha->nvram_data_off = ~0; 2952 } else if (IS_QLAFX00(ha)) { 2953 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2954 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2955 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2956 req_length = REQUEST_ENTRY_CNT_FX00; 2957 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2958 ha->isp_ops = &qlafx00_isp_ops; 2959 ha->port_down_retry_count = 30; /* default value */ 2960 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2961 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2962 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2963 ha->mr.fw_hbt_en = 1; 2964 ha->mr.host_info_resend = false; 2965 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2966 } else if (IS_QLA27XX(ha)) { 2967 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2968 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2969 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2970 req_length = REQUEST_ENTRY_CNT_83XX; 2971 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2972 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2973 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2974 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2975 ha->gid_list_info_size = 8; 2976 ha->optrom_size = OPTROM_SIZE_83XX; 2977 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2978 ha->isp_ops = &qla27xx_isp_ops; 2979 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2980 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2981 ha->nvram_conf_off = ~0; 2982 ha->nvram_data_off = ~0; 2983 } 2984 2985 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2986 "mbx_count=%d, req_length=%d, " 2987 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2988 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2989 "max_fibre_devices=%d.\n", 2990 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2991 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2992 ha->nvram_npiv_size, ha->max_fibre_devices); 2993 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2994 "isp_ops=%p, flash_conf_off=%d, " 2995 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2996 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2997 ha->nvram_conf_off, ha->nvram_data_off); 2998 2999 /* Configure PCI I/O space */ 3000 ret = ha->isp_ops->iospace_config(ha); 3001 if (ret) 3002 goto iospace_config_failed; 3003 3004 ql_log_pci(ql_log_info, pdev, 0x001d, 3005 "Found an ISP%04X irq %d iobase 0x%p.\n", 3006 pdev->device, pdev->irq, ha->iobase); 3007 mutex_init(&ha->vport_lock); 3008 mutex_init(&ha->mq_lock); 3009 init_completion(&ha->mbx_cmd_comp); 3010 complete(&ha->mbx_cmd_comp); 3011 init_completion(&ha->mbx_intr_comp); 3012 init_completion(&ha->dcbx_comp); 3013 init_completion(&ha->lb_portup_comp); 3014 3015 set_bit(0, (unsigned long *) ha->vp_idx_map); 3016 3017 qla2x00_config_dma_addressing(ha); 3018 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3019 "64 Bit addressing is %s.\n", 3020 ha->flags.enable_64bit_addressing ? "enable" : 3021 "disable"); 3022 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3023 if (ret) { 3024 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3025 "Failed to allocate memory for adapter, aborting.\n"); 3026 3027 goto probe_hw_failed; 3028 } 3029 3030 req->max_q_depth = MAX_Q_DEPTH; 3031 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3032 req->max_q_depth = ql2xmaxqdepth; 3033 3034 3035 base_vha = qla2x00_create_host(sht, ha); 3036 if (!base_vha) { 3037 ret = -ENOMEM; 3038 goto probe_hw_failed; 3039 } 3040 3041 pci_set_drvdata(pdev, base_vha); 3042 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3043 3044 host = base_vha->host; 3045 base_vha->req = req; 3046 if (IS_QLA2XXX_MIDTYPE(ha)) 3047 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER; 3048 else 3049 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3050 base_vha->vp_idx; 3051 3052 /* Setup fcport template structure. */ 3053 ha->mr.fcport.vha = base_vha; 3054 ha->mr.fcport.port_type = FCT_UNKNOWN; 3055 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3056 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3057 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3058 ha->mr.fcport.scan_state = 1; 3059 3060 /* Set the SG table size based on ISP type */ 3061 if (!IS_FWI2_CAPABLE(ha)) { 3062 if (IS_QLA2100(ha)) 3063 host->sg_tablesize = 32; 3064 } else { 3065 if (!IS_QLA82XX(ha)) 3066 host->sg_tablesize = QLA_SG_ALL; 3067 } 3068 host->max_id = ha->max_fibre_devices; 3069 host->cmd_per_lun = 3; 3070 host->unique_id = host->host_no; 3071 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3072 host->max_cmd_len = 32; 3073 else 3074 host->max_cmd_len = MAX_CMDSZ; 3075 host->max_channel = MAX_BUSES - 1; 3076 /* Older HBAs support only 16-bit LUNs */ 3077 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3078 ql2xmaxlun > 0xffff) 3079 host->max_lun = 0xffff; 3080 else 3081 host->max_lun = ql2xmaxlun; 3082 host->transportt = qla2xxx_transport_template; 3083 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3084 3085 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3086 "max_id=%d this_id=%d " 3087 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3088 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3089 host->this_id, host->cmd_per_lun, host->unique_id, 3090 host->max_cmd_len, host->max_channel, host->max_lun, 3091 host->transportt, sht->vendor_id); 3092 3093 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3094 3095 /* Set up the irqs */ 3096 ret = qla2x00_request_irqs(ha, rsp); 3097 if (ret) 3098 goto probe_hw_failed; 3099 3100 /* Alloc arrays of request and response ring ptrs */ 3101 if (!qla2x00_alloc_queues(ha, req, rsp)) { 3102 ql_log(ql_log_fatal, base_vha, 0x003d, 3103 "Failed to allocate memory for queue pointers..." 3104 "aborting.\n"); 3105 goto probe_init_failed; 3106 } 3107 3108 if (ha->mqenable && shost_use_blk_mq(host)) { 3109 /* number of hardware queues supported by blk/scsi-mq*/ 3110 host->nr_hw_queues = ha->max_qpairs; 3111 3112 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3113 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3114 } else { 3115 if (ql2xnvmeenable) { 3116 host->nr_hw_queues = ha->max_qpairs; 3117 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3118 "FC-NVMe support is enabled, HW queues=%d\n", 3119 host->nr_hw_queues); 3120 } else { 3121 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3122 "blk/scsi-mq disabled.\n"); 3123 } 3124 } 3125 3126 qlt_probe_one_stage1(base_vha, ha); 3127 3128 pci_save_state(pdev); 3129 3130 /* Assign back pointers */ 3131 rsp->req = req; 3132 req->rsp = rsp; 3133 3134 if (IS_QLAFX00(ha)) { 3135 ha->rsp_q_map[0] = rsp; 3136 ha->req_q_map[0] = req; 3137 set_bit(0, ha->req_qid_map); 3138 set_bit(0, ha->rsp_qid_map); 3139 } 3140 3141 /* FWI2-capable only. */ 3142 req->req_q_in = &ha->iobase->isp24.req_q_in; 3143 req->req_q_out = &ha->iobase->isp24.req_q_out; 3144 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3145 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3146 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3147 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3148 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3149 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3150 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3151 } 3152 3153 if (IS_QLAFX00(ha)) { 3154 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3155 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3156 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3157 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3158 } 3159 3160 if (IS_P3P_TYPE(ha)) { 3161 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3162 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3163 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3164 } 3165 3166 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3167 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3168 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3169 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3170 "req->req_q_in=%p req->req_q_out=%p " 3171 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3172 req->req_q_in, req->req_q_out, 3173 rsp->rsp_q_in, rsp->rsp_q_out); 3174 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3175 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3176 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3177 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3178 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3179 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3180 3181 if (ha->isp_ops->initialize_adapter(base_vha)) { 3182 ql_log(ql_log_fatal, base_vha, 0x00d6, 3183 "Failed to initialize adapter - Adapter flags %x.\n", 3184 base_vha->device_flags); 3185 3186 if (IS_QLA82XX(ha)) { 3187 qla82xx_idc_lock(ha); 3188 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3189 QLA8XXX_DEV_FAILED); 3190 qla82xx_idc_unlock(ha); 3191 ql_log(ql_log_fatal, base_vha, 0x00d7, 3192 "HW State: FAILED.\n"); 3193 } else if (IS_QLA8044(ha)) { 3194 qla8044_idc_lock(ha); 3195 qla8044_wr_direct(base_vha, 3196 QLA8044_CRB_DEV_STATE_INDEX, 3197 QLA8XXX_DEV_FAILED); 3198 qla8044_idc_unlock(ha); 3199 ql_log(ql_log_fatal, base_vha, 0x0150, 3200 "HW State: FAILED.\n"); 3201 } 3202 3203 ret = -ENODEV; 3204 goto probe_failed; 3205 } 3206 3207 if (IS_QLAFX00(ha)) 3208 host->can_queue = QLAFX00_MAX_CANQUEUE; 3209 else 3210 host->can_queue = req->num_outstanding_cmds - 10; 3211 3212 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3213 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3214 host->can_queue, base_vha->req, 3215 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3216 3217 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3218 3219 if (ha->mqenable) { 3220 bool mq = false; 3221 bool startit = false; 3222 3223 if (QLA_TGT_MODE_ENABLED()) { 3224 mq = true; 3225 startit = false; 3226 } 3227 3228 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3229 shost_use_blk_mq(host)) { 3230 mq = true; 3231 startit = true; 3232 } 3233 3234 if (mq) { 3235 /* Create start of day qpairs for Block MQ */ 3236 for (i = 0; i < ha->max_qpairs; i++) 3237 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3238 } 3239 } 3240 3241 if (ha->flags.running_gold_fw) 3242 goto skip_dpc; 3243 3244 /* 3245 * Startup the kernel thread for this host adapter 3246 */ 3247 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3248 "%s_dpc", base_vha->host_str); 3249 if (IS_ERR(ha->dpc_thread)) { 3250 ql_log(ql_log_fatal, base_vha, 0x00ed, 3251 "Failed to start DPC thread.\n"); 3252 ret = PTR_ERR(ha->dpc_thread); 3253 ha->dpc_thread = NULL; 3254 goto probe_failed; 3255 } 3256 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3257 "DPC thread started successfully.\n"); 3258 3259 /* 3260 * If we're not coming up in initiator mode, we might sit for 3261 * a while without waking up the dpc thread, which leads to a 3262 * stuck process warning. So just kick the dpc once here and 3263 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3264 */ 3265 qla2xxx_wake_dpc(base_vha); 3266 3267 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3268 3269 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3270 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3271 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3272 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3273 3274 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3275 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3276 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3277 INIT_WORK(&ha->idc_state_handler, 3278 qla83xx_idc_state_handler_work); 3279 INIT_WORK(&ha->nic_core_unrecoverable, 3280 qla83xx_nic_core_unrecoverable_work); 3281 } 3282 3283 skip_dpc: 3284 list_add_tail(&base_vha->list, &ha->vp_list); 3285 base_vha->host->irq = ha->pdev->irq; 3286 3287 /* Initialized the timer */ 3288 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3289 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3290 "Started qla2x00_timer with " 3291 "interval=%d.\n", WATCH_INTERVAL); 3292 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3293 "Detected hba at address=%p.\n", 3294 ha); 3295 3296 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3297 if (ha->fw_attributes & BIT_4) { 3298 int prot = 0, guard; 3299 base_vha->flags.difdix_supported = 1; 3300 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3301 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3302 if (ql2xenabledif == 1) 3303 prot = SHOST_DIX_TYPE0_PROTECTION; 3304 scsi_host_set_prot(host, 3305 prot | SHOST_DIF_TYPE1_PROTECTION 3306 | SHOST_DIF_TYPE2_PROTECTION 3307 | SHOST_DIF_TYPE3_PROTECTION 3308 | SHOST_DIX_TYPE1_PROTECTION 3309 | SHOST_DIX_TYPE2_PROTECTION 3310 | SHOST_DIX_TYPE3_PROTECTION); 3311 3312 guard = SHOST_DIX_GUARD_CRC; 3313 3314 if (IS_PI_IPGUARD_CAPABLE(ha) && 3315 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3316 guard |= SHOST_DIX_GUARD_IP; 3317 3318 scsi_host_set_guard(host, guard); 3319 } else 3320 base_vha->flags.difdix_supported = 0; 3321 } 3322 3323 ha->isp_ops->enable_intrs(ha); 3324 3325 if (IS_QLAFX00(ha)) { 3326 ret = qlafx00_fx_disc(base_vha, 3327 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3328 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3329 QLA_SG_ALL : 128; 3330 } 3331 3332 ret = scsi_add_host(host, &pdev->dev); 3333 if (ret) 3334 goto probe_failed; 3335 3336 base_vha->flags.init_done = 1; 3337 base_vha->flags.online = 1; 3338 ha->prev_minidump_failed = 0; 3339 3340 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3341 "Init done and hba is online.\n"); 3342 3343 if (qla_ini_mode_enabled(base_vha) || 3344 qla_dual_mode_enabled(base_vha)) 3345 scsi_scan_host(host); 3346 else 3347 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3348 "skipping scsi_scan_host() for non-initiator port\n"); 3349 3350 qla2x00_alloc_sysfs_attr(base_vha); 3351 3352 if (IS_QLAFX00(ha)) { 3353 ret = qlafx00_fx_disc(base_vha, 3354 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3355 3356 /* Register system information */ 3357 ret = qlafx00_fx_disc(base_vha, 3358 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3359 } 3360 3361 qla2x00_init_host_attr(base_vha); 3362 3363 qla2x00_dfs_setup(base_vha); 3364 3365 ql_log(ql_log_info, base_vha, 0x00fb, 3366 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3367 ql_log(ql_log_info, base_vha, 0x00fc, 3368 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3369 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3370 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3371 base_vha->host_no, 3372 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3373 3374 qlt_add_target(ha, base_vha); 3375 3376 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3377 3378 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3379 return -ENODEV; 3380 3381 if (ha->flags.detected_lr_sfp) { 3382 ql_log(ql_log_info, base_vha, 0xffff, 3383 "Reset chip to pick up LR SFP setting\n"); 3384 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3385 qla2xxx_wake_dpc(base_vha); 3386 } 3387 3388 return 0; 3389 3390 probe_init_failed: 3391 qla2x00_free_req_que(ha, req); 3392 ha->req_q_map[0] = NULL; 3393 clear_bit(0, ha->req_qid_map); 3394 qla2x00_free_rsp_que(ha, rsp); 3395 ha->rsp_q_map[0] = NULL; 3396 clear_bit(0, ha->rsp_qid_map); 3397 ha->max_req_queues = ha->max_rsp_queues = 0; 3398 3399 probe_failed: 3400 if (base_vha->timer_active) 3401 qla2x00_stop_timer(base_vha); 3402 base_vha->flags.online = 0; 3403 if (ha->dpc_thread) { 3404 struct task_struct *t = ha->dpc_thread; 3405 3406 ha->dpc_thread = NULL; 3407 kthread_stop(t); 3408 } 3409 3410 qla2x00_free_device(base_vha); 3411 3412 scsi_host_put(base_vha->host); 3413 3414 probe_hw_failed: 3415 qla2x00_mem_free(ha); 3416 qla2x00_free_req_que(ha, req); 3417 qla2x00_free_rsp_que(ha, rsp); 3418 qla2x00_clear_drv_active(ha); 3419 3420 iospace_config_failed: 3421 if (IS_P3P_TYPE(ha)) { 3422 if (!ha->nx_pcibase) 3423 iounmap((device_reg_t *)ha->nx_pcibase); 3424 if (!ql2xdbwr) 3425 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3426 } else { 3427 if (ha->iobase) 3428 iounmap(ha->iobase); 3429 if (ha->cregbase) 3430 iounmap(ha->cregbase); 3431 } 3432 pci_release_selected_regions(ha->pdev, ha->bars); 3433 kfree(ha); 3434 3435 disable_device: 3436 pci_disable_device(pdev); 3437 return ret; 3438 } 3439 3440 static void 3441 qla2x00_shutdown(struct pci_dev *pdev) 3442 { 3443 scsi_qla_host_t *vha; 3444 struct qla_hw_data *ha; 3445 3446 vha = pci_get_drvdata(pdev); 3447 ha = vha->hw; 3448 3449 ql_log(ql_log_info, vha, 0xfffa, 3450 "Adapter shutdown\n"); 3451 3452 /* 3453 * Prevent future board_disable and wait 3454 * until any pending board_disable has completed. 3455 */ 3456 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3457 cancel_work_sync(&ha->board_disable); 3458 3459 if (!atomic_read(&pdev->enable_cnt)) 3460 return; 3461 3462 /* Notify ISPFX00 firmware */ 3463 if (IS_QLAFX00(ha)) 3464 qlafx00_driver_shutdown(vha, 20); 3465 3466 /* Turn-off FCE trace */ 3467 if (ha->flags.fce_enabled) { 3468 qla2x00_disable_fce_trace(vha, NULL, NULL); 3469 ha->flags.fce_enabled = 0; 3470 } 3471 3472 /* Turn-off EFT trace */ 3473 if (ha->eft) 3474 qla2x00_disable_eft_trace(vha); 3475 3476 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3477 if (ha->flags.fw_started) 3478 qla2x00_abort_isp_cleanup(vha); 3479 } else { 3480 /* Stop currently executing firmware. */ 3481 qla2x00_try_to_stop_firmware(vha); 3482 } 3483 3484 /* Turn adapter off line */ 3485 vha->flags.online = 0; 3486 3487 /* turn-off interrupts on the card */ 3488 if (ha->interrupts_on) { 3489 vha->flags.init_done = 0; 3490 ha->isp_ops->disable_intrs(ha); 3491 } 3492 3493 qla2x00_free_irqs(vha); 3494 3495 qla2x00_free_fw_dump(ha); 3496 3497 pci_disable_device(pdev); 3498 ql_log(ql_log_info, vha, 0xfffe, 3499 "Adapter shutdown successfully.\n"); 3500 } 3501 3502 /* Deletes all the virtual ports for a given ha */ 3503 static void 3504 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3505 { 3506 scsi_qla_host_t *vha; 3507 unsigned long flags; 3508 3509 mutex_lock(&ha->vport_lock); 3510 while (ha->cur_vport_count) { 3511 spin_lock_irqsave(&ha->vport_slock, flags); 3512 3513 BUG_ON(base_vha->list.next == &ha->vp_list); 3514 /* This assumes first entry in ha->vp_list is always base vha */ 3515 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3516 scsi_host_get(vha->host); 3517 3518 spin_unlock_irqrestore(&ha->vport_slock, flags); 3519 mutex_unlock(&ha->vport_lock); 3520 3521 fc_vport_terminate(vha->fc_vport); 3522 scsi_host_put(vha->host); 3523 3524 mutex_lock(&ha->vport_lock); 3525 } 3526 mutex_unlock(&ha->vport_lock); 3527 } 3528 3529 /* Stops all deferred work threads */ 3530 static void 3531 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3532 { 3533 /* Cancel all work and destroy DPC workqueues */ 3534 if (ha->dpc_lp_wq) { 3535 cancel_work_sync(&ha->idc_aen); 3536 destroy_workqueue(ha->dpc_lp_wq); 3537 ha->dpc_lp_wq = NULL; 3538 } 3539 3540 if (ha->dpc_hp_wq) { 3541 cancel_work_sync(&ha->nic_core_reset); 3542 cancel_work_sync(&ha->idc_state_handler); 3543 cancel_work_sync(&ha->nic_core_unrecoverable); 3544 destroy_workqueue(ha->dpc_hp_wq); 3545 ha->dpc_hp_wq = NULL; 3546 } 3547 3548 /* Kill the kernel thread for this host */ 3549 if (ha->dpc_thread) { 3550 struct task_struct *t = ha->dpc_thread; 3551 3552 /* 3553 * qla2xxx_wake_dpc checks for ->dpc_thread 3554 * so we need to zero it out. 3555 */ 3556 ha->dpc_thread = NULL; 3557 kthread_stop(t); 3558 } 3559 } 3560 3561 static void 3562 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3563 { 3564 if (IS_QLA82XX(ha)) { 3565 3566 iounmap((device_reg_t *)ha->nx_pcibase); 3567 if (!ql2xdbwr) 3568 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3569 } else { 3570 if (ha->iobase) 3571 iounmap(ha->iobase); 3572 3573 if (ha->cregbase) 3574 iounmap(ha->cregbase); 3575 3576 if (ha->mqiobase) 3577 iounmap(ha->mqiobase); 3578 3579 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3580 iounmap(ha->msixbase); 3581 } 3582 } 3583 3584 static void 3585 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3586 { 3587 if (IS_QLA8044(ha)) { 3588 qla8044_idc_lock(ha); 3589 qla8044_clear_drv_active(ha); 3590 qla8044_idc_unlock(ha); 3591 } else if (IS_QLA82XX(ha)) { 3592 qla82xx_idc_lock(ha); 3593 qla82xx_clear_drv_active(ha); 3594 qla82xx_idc_unlock(ha); 3595 } 3596 } 3597 3598 static void 3599 qla2x00_remove_one(struct pci_dev *pdev) 3600 { 3601 scsi_qla_host_t *base_vha; 3602 struct qla_hw_data *ha; 3603 3604 base_vha = pci_get_drvdata(pdev); 3605 ha = base_vha->hw; 3606 3607 /* Indicate device removal to prevent future board_disable and wait 3608 * until any pending board_disable has completed. */ 3609 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3610 cancel_work_sync(&ha->board_disable); 3611 3612 /* 3613 * If the PCI device is disabled then there was a PCI-disconnect and 3614 * qla2x00_disable_board_on_pci_error has taken care of most of the 3615 * resources. 3616 */ 3617 if (!atomic_read(&pdev->enable_cnt)) { 3618 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3619 base_vha->gnl.l, base_vha->gnl.ldma); 3620 3621 scsi_host_put(base_vha->host); 3622 kfree(ha); 3623 pci_set_drvdata(pdev, NULL); 3624 return; 3625 } 3626 qla2x00_wait_for_hba_ready(base_vha); 3627 3628 qla2x00_wait_for_sess_deletion(base_vha); 3629 3630 /* 3631 * if UNLOAD flag is already set, then continue unload, 3632 * where it was set first. 3633 */ 3634 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3635 return; 3636 3637 set_bit(UNLOADING, &base_vha->dpc_flags); 3638 3639 qla_nvme_delete(base_vha); 3640 3641 dma_free_coherent(&ha->pdev->dev, 3642 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3643 3644 vfree(base_vha->scan.l); 3645 3646 if (IS_QLAFX00(ha)) 3647 qlafx00_driver_shutdown(base_vha, 20); 3648 3649 qla2x00_delete_all_vps(ha, base_vha); 3650 3651 if (IS_QLA8031(ha)) { 3652 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3653 "Clearing fcoe driver presence.\n"); 3654 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3655 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3656 "Error while clearing DRV-Presence.\n"); 3657 } 3658 3659 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3660 3661 qla2x00_dfs_remove(base_vha); 3662 3663 qla84xx_put_chip(base_vha); 3664 3665 /* Disable timer */ 3666 if (base_vha->timer_active) 3667 qla2x00_stop_timer(base_vha); 3668 3669 base_vha->flags.online = 0; 3670 3671 /* free DMA memory */ 3672 if (ha->exlogin_buf) 3673 qla2x00_free_exlogin_buffer(ha); 3674 3675 /* free DMA memory */ 3676 if (ha->exchoffld_buf) 3677 qla2x00_free_exchoffld_buffer(ha); 3678 3679 qla2x00_destroy_deferred_work(ha); 3680 3681 qlt_remove_target(ha, base_vha); 3682 3683 qla2x00_free_sysfs_attr(base_vha, true); 3684 3685 fc_remove_host(base_vha->host); 3686 qlt_remove_target_resources(ha); 3687 3688 scsi_remove_host(base_vha->host); 3689 3690 qla2x00_free_device(base_vha); 3691 3692 qla2x00_clear_drv_active(ha); 3693 3694 scsi_host_put(base_vha->host); 3695 3696 qla2x00_unmap_iobases(ha); 3697 3698 pci_release_selected_regions(ha->pdev, ha->bars); 3699 kfree(ha); 3700 3701 pci_disable_pcie_error_reporting(pdev); 3702 3703 pci_disable_device(pdev); 3704 } 3705 3706 static void 3707 qla2x00_free_device(scsi_qla_host_t *vha) 3708 { 3709 struct qla_hw_data *ha = vha->hw; 3710 3711 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3712 3713 /* Disable timer */ 3714 if (vha->timer_active) 3715 qla2x00_stop_timer(vha); 3716 3717 qla25xx_delete_queues(vha); 3718 3719 if (ha->flags.fce_enabled) 3720 qla2x00_disable_fce_trace(vha, NULL, NULL); 3721 3722 if (ha->eft) 3723 qla2x00_disable_eft_trace(vha); 3724 3725 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3726 if (ha->flags.fw_started) 3727 qla2x00_abort_isp_cleanup(vha); 3728 } else { 3729 if (ha->flags.fw_started) { 3730 /* Stop currently executing firmware. */ 3731 qla2x00_try_to_stop_firmware(vha); 3732 ha->flags.fw_started = 0; 3733 } 3734 } 3735 3736 vha->flags.online = 0; 3737 3738 /* turn-off interrupts on the card */ 3739 if (ha->interrupts_on) { 3740 vha->flags.init_done = 0; 3741 ha->isp_ops->disable_intrs(ha); 3742 } 3743 3744 qla2x00_free_fcports(vha); 3745 3746 qla2x00_free_irqs(vha); 3747 3748 /* Flush the work queue and remove it */ 3749 if (ha->wq) { 3750 flush_workqueue(ha->wq); 3751 destroy_workqueue(ha->wq); 3752 ha->wq = NULL; 3753 } 3754 3755 3756 qla2x00_mem_free(ha); 3757 3758 qla82xx_md_free(vha); 3759 3760 qla2x00_free_queues(ha); 3761 } 3762 3763 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3764 { 3765 fc_port_t *fcport, *tfcport; 3766 3767 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3768 list_del(&fcport->list); 3769 qla2x00_clear_loop_id(fcport); 3770 kfree(fcport); 3771 } 3772 } 3773 3774 static inline void 3775 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3776 int defer) 3777 { 3778 struct fc_rport *rport; 3779 scsi_qla_host_t *base_vha; 3780 unsigned long flags; 3781 3782 if (!fcport->rport) 3783 return; 3784 3785 rport = fcport->rport; 3786 if (defer) { 3787 base_vha = pci_get_drvdata(vha->hw->pdev); 3788 spin_lock_irqsave(vha->host->host_lock, flags); 3789 fcport->drport = rport; 3790 spin_unlock_irqrestore(vha->host->host_lock, flags); 3791 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3792 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3793 qla2xxx_wake_dpc(base_vha); 3794 } else { 3795 int now; 3796 if (rport) { 3797 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3798 "%s %8phN. rport %p roles %x\n", 3799 __func__, fcport->port_name, rport, 3800 rport->roles); 3801 fc_remote_port_delete(rport); 3802 } 3803 qlt_do_generation_tick(vha, &now); 3804 } 3805 } 3806 3807 /* 3808 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3809 * 3810 * Input: ha = adapter block pointer. fcport = port structure pointer. 3811 * 3812 * Return: None. 3813 * 3814 * Context: 3815 */ 3816 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3817 int do_login, int defer) 3818 { 3819 if (IS_QLAFX00(vha->hw)) { 3820 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3821 qla2x00_schedule_rport_del(vha, fcport, defer); 3822 return; 3823 } 3824 3825 if (atomic_read(&fcport->state) == FCS_ONLINE && 3826 vha->vp_idx == fcport->vha->vp_idx) { 3827 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3828 qla2x00_schedule_rport_del(vha, fcport, defer); 3829 } 3830 /* 3831 * We may need to retry the login, so don't change the state of the 3832 * port but do the retries. 3833 */ 3834 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3835 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3836 3837 if (!do_login) 3838 return; 3839 3840 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3841 3842 if (fcport->login_retry == 0) { 3843 fcport->login_retry = vha->hw->login_retry_count; 3844 3845 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3846 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3847 fcport->port_name, fcport->loop_id, fcport->login_retry); 3848 } 3849 } 3850 3851 /* 3852 * qla2x00_mark_all_devices_lost 3853 * Updates fcport state when device goes offline. 3854 * 3855 * Input: 3856 * ha = adapter block pointer. 3857 * fcport = port structure pointer. 3858 * 3859 * Return: 3860 * None. 3861 * 3862 * Context: 3863 */ 3864 void 3865 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3866 { 3867 fc_port_t *fcport; 3868 3869 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3870 "Mark all dev lost\n"); 3871 3872 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3873 fcport->scan_state = 0; 3874 qlt_schedule_sess_for_deletion(fcport); 3875 3876 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3877 continue; 3878 3879 /* 3880 * No point in marking the device as lost, if the device is 3881 * already DEAD. 3882 */ 3883 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3884 continue; 3885 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3886 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3887 if (defer) 3888 qla2x00_schedule_rport_del(vha, fcport, defer); 3889 else if (vha->vp_idx == fcport->vha->vp_idx) 3890 qla2x00_schedule_rport_del(vha, fcport, defer); 3891 } 3892 } 3893 } 3894 3895 /* 3896 * qla2x00_mem_alloc 3897 * Allocates adapter memory. 3898 * 3899 * Returns: 3900 * 0 = success. 3901 * !0 = failure. 3902 */ 3903 static int 3904 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3905 struct req_que **req, struct rsp_que **rsp) 3906 { 3907 char name[16]; 3908 3909 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3910 &ha->init_cb_dma, GFP_KERNEL); 3911 if (!ha->init_cb) 3912 goto fail; 3913 3914 if (qlt_mem_alloc(ha) < 0) 3915 goto fail_free_init_cb; 3916 3917 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3918 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3919 if (!ha->gid_list) 3920 goto fail_free_tgt_mem; 3921 3922 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3923 if (!ha->srb_mempool) 3924 goto fail_free_gid_list; 3925 3926 if (IS_P3P_TYPE(ha)) { 3927 /* Allocate cache for CT6 Ctx. */ 3928 if (!ctx_cachep) { 3929 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3930 sizeof(struct ct6_dsd), 0, 3931 SLAB_HWCACHE_ALIGN, NULL); 3932 if (!ctx_cachep) 3933 goto fail_free_srb_mempool; 3934 } 3935 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3936 ctx_cachep); 3937 if (!ha->ctx_mempool) 3938 goto fail_free_srb_mempool; 3939 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3940 "ctx_cachep=%p ctx_mempool=%p.\n", 3941 ctx_cachep, ha->ctx_mempool); 3942 } 3943 3944 /* Get memory for cached NVRAM */ 3945 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3946 if (!ha->nvram) 3947 goto fail_free_ctx_mempool; 3948 3949 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3950 ha->pdev->device); 3951 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3952 DMA_POOL_SIZE, 8, 0); 3953 if (!ha->s_dma_pool) 3954 goto fail_free_nvram; 3955 3956 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3957 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3958 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3959 3960 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3961 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3962 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3963 if (!ha->dl_dma_pool) { 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3965 "Failed to allocate memory for dl_dma_pool.\n"); 3966 goto fail_s_dma_pool; 3967 } 3968 3969 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3970 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3971 if (!ha->fcp_cmnd_dma_pool) { 3972 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3973 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3974 goto fail_dl_dma_pool; 3975 } 3976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3977 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3978 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3979 } 3980 3981 /* Allocate memory for SNS commands */ 3982 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3983 /* Get consistent memory allocated for SNS commands */ 3984 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3985 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3986 if (!ha->sns_cmd) 3987 goto fail_dma_pool; 3988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3989 "sns_cmd: %p.\n", ha->sns_cmd); 3990 } else { 3991 /* Get consistent memory allocated for MS IOCB */ 3992 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3993 &ha->ms_iocb_dma); 3994 if (!ha->ms_iocb) 3995 goto fail_dma_pool; 3996 /* Get consistent memory allocated for CT SNS commands */ 3997 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3998 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3999 if (!ha->ct_sns) 4000 goto fail_free_ms_iocb; 4001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4002 "ms_iocb=%p ct_sns=%p.\n", 4003 ha->ms_iocb, ha->ct_sns); 4004 } 4005 4006 /* Allocate memory for request ring */ 4007 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4008 if (!*req) { 4009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4010 "Failed to allocate memory for req.\n"); 4011 goto fail_req; 4012 } 4013 (*req)->length = req_len; 4014 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4015 ((*req)->length + 1) * sizeof(request_t), 4016 &(*req)->dma, GFP_KERNEL); 4017 if (!(*req)->ring) { 4018 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4019 "Failed to allocate memory for req_ring.\n"); 4020 goto fail_req_ring; 4021 } 4022 /* Allocate memory for response ring */ 4023 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4024 if (!*rsp) { 4025 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4026 "Failed to allocate memory for rsp.\n"); 4027 goto fail_rsp; 4028 } 4029 (*rsp)->hw = ha; 4030 (*rsp)->length = rsp_len; 4031 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4032 ((*rsp)->length + 1) * sizeof(response_t), 4033 &(*rsp)->dma, GFP_KERNEL); 4034 if (!(*rsp)->ring) { 4035 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4036 "Failed to allocate memory for rsp_ring.\n"); 4037 goto fail_rsp_ring; 4038 } 4039 (*req)->rsp = *rsp; 4040 (*rsp)->req = *req; 4041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4042 "req=%p req->length=%d req->ring=%p rsp=%p " 4043 "rsp->length=%d rsp->ring=%p.\n", 4044 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4045 (*rsp)->ring); 4046 /* Allocate memory for NVRAM data for vports */ 4047 if (ha->nvram_npiv_size) { 4048 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 4049 ha->nvram_npiv_size, GFP_KERNEL); 4050 if (!ha->npiv_info) { 4051 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4052 "Failed to allocate memory for npiv_info.\n"); 4053 goto fail_npiv_info; 4054 } 4055 } else 4056 ha->npiv_info = NULL; 4057 4058 /* Get consistent memory allocated for EX-INIT-CB. */ 4059 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4060 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4061 &ha->ex_init_cb_dma); 4062 if (!ha->ex_init_cb) 4063 goto fail_ex_init_cb; 4064 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4065 "ex_init_cb=%p.\n", ha->ex_init_cb); 4066 } 4067 4068 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4069 4070 /* Get consistent memory allocated for Async Port-Database. */ 4071 if (!IS_FWI2_CAPABLE(ha)) { 4072 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4073 &ha->async_pd_dma); 4074 if (!ha->async_pd) 4075 goto fail_async_pd; 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4077 "async_pd=%p.\n", ha->async_pd); 4078 } 4079 4080 INIT_LIST_HEAD(&ha->vp_list); 4081 4082 /* Allocate memory for our loop_id bitmap */ 4083 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 4084 GFP_KERNEL); 4085 if (!ha->loop_id_map) 4086 goto fail_loop_id_map; 4087 else { 4088 qla2x00_set_reserved_loop_ids(ha); 4089 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4090 "loop_id_map=%p.\n", ha->loop_id_map); 4091 } 4092 4093 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4094 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4095 if (!ha->sfp_data) { 4096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4097 "Unable to allocate memory for SFP read-data.\n"); 4098 goto fail_sfp_data; 4099 } 4100 4101 return 0; 4102 4103 fail_sfp_data: 4104 kfree(ha->loop_id_map); 4105 fail_loop_id_map: 4106 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4107 fail_async_pd: 4108 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4109 fail_ex_init_cb: 4110 kfree(ha->npiv_info); 4111 fail_npiv_info: 4112 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4113 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4114 (*rsp)->ring = NULL; 4115 (*rsp)->dma = 0; 4116 fail_rsp_ring: 4117 kfree(*rsp); 4118 fail_rsp: 4119 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4120 sizeof(request_t), (*req)->ring, (*req)->dma); 4121 (*req)->ring = NULL; 4122 (*req)->dma = 0; 4123 fail_req_ring: 4124 kfree(*req); 4125 fail_req: 4126 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4127 ha->ct_sns, ha->ct_sns_dma); 4128 ha->ct_sns = NULL; 4129 ha->ct_sns_dma = 0; 4130 fail_free_ms_iocb: 4131 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4132 ha->ms_iocb = NULL; 4133 ha->ms_iocb_dma = 0; 4134 4135 if (ha->sns_cmd) 4136 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4137 ha->sns_cmd, ha->sns_cmd_dma); 4138 fail_dma_pool: 4139 if (IS_QLA82XX(ha) || ql2xenabledif) { 4140 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4141 ha->fcp_cmnd_dma_pool = NULL; 4142 } 4143 fail_dl_dma_pool: 4144 if (IS_QLA82XX(ha) || ql2xenabledif) { 4145 dma_pool_destroy(ha->dl_dma_pool); 4146 ha->dl_dma_pool = NULL; 4147 } 4148 fail_s_dma_pool: 4149 dma_pool_destroy(ha->s_dma_pool); 4150 ha->s_dma_pool = NULL; 4151 fail_free_nvram: 4152 kfree(ha->nvram); 4153 ha->nvram = NULL; 4154 fail_free_ctx_mempool: 4155 if (ha->ctx_mempool) 4156 mempool_destroy(ha->ctx_mempool); 4157 ha->ctx_mempool = NULL; 4158 fail_free_srb_mempool: 4159 if (ha->srb_mempool) 4160 mempool_destroy(ha->srb_mempool); 4161 ha->srb_mempool = NULL; 4162 fail_free_gid_list: 4163 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4164 ha->gid_list, 4165 ha->gid_list_dma); 4166 ha->gid_list = NULL; 4167 ha->gid_list_dma = 0; 4168 fail_free_tgt_mem: 4169 qlt_mem_free(ha); 4170 fail_free_init_cb: 4171 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4172 ha->init_cb_dma); 4173 ha->init_cb = NULL; 4174 ha->init_cb_dma = 0; 4175 fail: 4176 ql_log(ql_log_fatal, NULL, 0x0030, 4177 "Memory allocation failure.\n"); 4178 return -ENOMEM; 4179 } 4180 4181 int 4182 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4183 { 4184 int rval; 4185 uint16_t size, max_cnt, temp; 4186 struct qla_hw_data *ha = vha->hw; 4187 4188 /* Return if we don't need to alloacate any extended logins */ 4189 if (!ql2xexlogins) 4190 return QLA_SUCCESS; 4191 4192 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4193 return QLA_SUCCESS; 4194 4195 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4196 max_cnt = 0; 4197 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4198 if (rval != QLA_SUCCESS) { 4199 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4200 "Failed to get exlogin status.\n"); 4201 return rval; 4202 } 4203 4204 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4205 temp *= size; 4206 4207 if (temp != ha->exlogin_size) { 4208 qla2x00_free_exlogin_buffer(ha); 4209 ha->exlogin_size = temp; 4210 4211 ql_log(ql_log_info, vha, 0xd024, 4212 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4213 max_cnt, size, temp); 4214 4215 ql_log(ql_log_info, vha, 0xd025, 4216 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4217 4218 /* Get consistent memory for extended logins */ 4219 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4220 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4221 if (!ha->exlogin_buf) { 4222 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4223 "Failed to allocate memory for exlogin_buf_dma.\n"); 4224 return -ENOMEM; 4225 } 4226 } 4227 4228 /* Now configure the dma buffer */ 4229 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4230 if (rval) { 4231 ql_log(ql_log_fatal, vha, 0xd033, 4232 "Setup extended login buffer ****FAILED****.\n"); 4233 qla2x00_free_exlogin_buffer(ha); 4234 } 4235 4236 return rval; 4237 } 4238 4239 /* 4240 * qla2x00_free_exlogin_buffer 4241 * 4242 * Input: 4243 * ha = adapter block pointer 4244 */ 4245 void 4246 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4247 { 4248 if (ha->exlogin_buf) { 4249 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4250 ha->exlogin_buf, ha->exlogin_buf_dma); 4251 ha->exlogin_buf = NULL; 4252 ha->exlogin_size = 0; 4253 } 4254 } 4255 4256 static void 4257 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4258 { 4259 u32 temp; 4260 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4261 4262 if (max_cnt > vha->hw->max_exchg) 4263 max_cnt = vha->hw->max_exchg; 4264 4265 if (qla_ini_mode_enabled(vha)) { 4266 if (ql2xiniexchg > max_cnt) 4267 ql2xiniexchg = max_cnt; 4268 4269 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4270 *ret_cnt = ql2xiniexchg; 4271 } else if (qla_tgt_mode_enabled(vha)) { 4272 if (ql2xexchoffld > max_cnt) 4273 ql2xexchoffld = max_cnt; 4274 4275 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4276 *ret_cnt = ql2xexchoffld; 4277 } else if (qla_dual_mode_enabled(vha)) { 4278 temp = ql2xiniexchg + ql2xexchoffld; 4279 if (temp > max_cnt) { 4280 ql2xiniexchg -= (temp - max_cnt)/2; 4281 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4282 temp = max_cnt; 4283 } 4284 4285 if (temp > FW_DEF_EXCHANGES_CNT) 4286 *ret_cnt = temp; 4287 } 4288 } 4289 4290 int 4291 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4292 { 4293 int rval; 4294 u16 size, max_cnt; 4295 u32 actual_cnt, totsz; 4296 struct qla_hw_data *ha = vha->hw; 4297 4298 if (!ha->flags.exchoffld_enabled) 4299 return QLA_SUCCESS; 4300 4301 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4302 return QLA_SUCCESS; 4303 4304 max_cnt = 0; 4305 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4306 if (rval != QLA_SUCCESS) { 4307 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4308 "Failed to get exlogin status.\n"); 4309 return rval; 4310 } 4311 4312 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4313 ql_log(ql_log_info, vha, 0xd014, 4314 "Actual exchange offload count: %d.\n", actual_cnt); 4315 4316 totsz = actual_cnt * size; 4317 4318 if (totsz != ha->exchoffld_size) { 4319 qla2x00_free_exchoffld_buffer(ha); 4320 ha->exchoffld_size = totsz; 4321 4322 ql_log(ql_log_info, vha, 0xd016, 4323 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4324 max_cnt, actual_cnt, size, totsz); 4325 4326 ql_log(ql_log_info, vha, 0xd017, 4327 "Exchange Buffers requested size = 0x%x\n", 4328 ha->exchoffld_size); 4329 4330 /* Get consistent memory for extended logins */ 4331 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4332 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4333 if (!ha->exchoffld_buf) { 4334 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4335 "Failed to allocate memory for Exchange Offload.\n"); 4336 4337 if (ha->max_exchg > 4338 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4339 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4340 } else if (ha->max_exchg > 4341 (FW_DEF_EXCHANGES_CNT + 512)) { 4342 ha->max_exchg -= 512; 4343 } else { 4344 ha->flags.exchoffld_enabled = 0; 4345 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4346 "Disabling Exchange offload due to lack of memory\n"); 4347 } 4348 ha->exchoffld_size = 0; 4349 4350 return -ENOMEM; 4351 } 4352 } 4353 4354 /* Now configure the dma buffer */ 4355 rval = qla_set_exchoffld_mem_cfg(vha); 4356 if (rval) { 4357 ql_log(ql_log_fatal, vha, 0xd02e, 4358 "Setup exchange offload buffer ****FAILED****.\n"); 4359 qla2x00_free_exchoffld_buffer(ha); 4360 } else { 4361 /* re-adjust number of target exchange */ 4362 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4363 4364 if (qla_ini_mode_enabled(vha)) 4365 icb->exchange_count = 0; 4366 else 4367 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4368 } 4369 4370 return rval; 4371 } 4372 4373 /* 4374 * qla2x00_free_exchoffld_buffer 4375 * 4376 * Input: 4377 * ha = adapter block pointer 4378 */ 4379 void 4380 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4381 { 4382 if (ha->exchoffld_buf) { 4383 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4384 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4385 ha->exchoffld_buf = NULL; 4386 ha->exchoffld_size = 0; 4387 } 4388 } 4389 4390 /* 4391 * qla2x00_free_fw_dump 4392 * Frees fw dump stuff. 4393 * 4394 * Input: 4395 * ha = adapter block pointer 4396 */ 4397 static void 4398 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4399 { 4400 if (ha->fce) 4401 dma_free_coherent(&ha->pdev->dev, 4402 FCE_SIZE, ha->fce, ha->fce_dma); 4403 4404 if (ha->eft) 4405 dma_free_coherent(&ha->pdev->dev, 4406 EFT_SIZE, ha->eft, ha->eft_dma); 4407 4408 if (ha->fw_dump) 4409 vfree(ha->fw_dump); 4410 if (ha->fw_dump_template) 4411 vfree(ha->fw_dump_template); 4412 4413 ha->fce = NULL; 4414 ha->fce_dma = 0; 4415 ha->eft = NULL; 4416 ha->eft_dma = 0; 4417 ha->fw_dumped = 0; 4418 ha->fw_dump_cap_flags = 0; 4419 ha->fw_dump_reading = 0; 4420 ha->fw_dump = NULL; 4421 ha->fw_dump_len = 0; 4422 ha->fw_dump_template = NULL; 4423 ha->fw_dump_template_len = 0; 4424 } 4425 4426 /* 4427 * qla2x00_mem_free 4428 * Frees all adapter allocated memory. 4429 * 4430 * Input: 4431 * ha = adapter block pointer. 4432 */ 4433 static void 4434 qla2x00_mem_free(struct qla_hw_data *ha) 4435 { 4436 qla2x00_free_fw_dump(ha); 4437 4438 if (ha->mctp_dump) 4439 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4440 ha->mctp_dump_dma); 4441 4442 if (ha->srb_mempool) 4443 mempool_destroy(ha->srb_mempool); 4444 4445 if (ha->dcbx_tlv) 4446 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4447 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4448 4449 if (ha->xgmac_data) 4450 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4451 ha->xgmac_data, ha->xgmac_data_dma); 4452 4453 if (ha->sns_cmd) 4454 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4455 ha->sns_cmd, ha->sns_cmd_dma); 4456 4457 if (ha->ct_sns) 4458 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4459 ha->ct_sns, ha->ct_sns_dma); 4460 4461 if (ha->sfp_data) 4462 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4463 ha->sfp_data_dma); 4464 4465 if (ha->ms_iocb) 4466 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4467 4468 if (ha->ex_init_cb) 4469 dma_pool_free(ha->s_dma_pool, 4470 ha->ex_init_cb, ha->ex_init_cb_dma); 4471 4472 if (ha->async_pd) 4473 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4474 4475 if (ha->s_dma_pool) 4476 dma_pool_destroy(ha->s_dma_pool); 4477 4478 if (ha->gid_list) 4479 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4480 ha->gid_list, ha->gid_list_dma); 4481 4482 if (IS_QLA82XX(ha)) { 4483 if (!list_empty(&ha->gbl_dsd_list)) { 4484 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4485 4486 /* clean up allocated prev pool */ 4487 list_for_each_entry_safe(dsd_ptr, 4488 tdsd_ptr, &ha->gbl_dsd_list, list) { 4489 dma_pool_free(ha->dl_dma_pool, 4490 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4491 list_del(&dsd_ptr->list); 4492 kfree(dsd_ptr); 4493 } 4494 } 4495 } 4496 4497 if (ha->dl_dma_pool) 4498 dma_pool_destroy(ha->dl_dma_pool); 4499 4500 if (ha->fcp_cmnd_dma_pool) 4501 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4502 4503 if (ha->ctx_mempool) 4504 mempool_destroy(ha->ctx_mempool); 4505 4506 qlt_mem_free(ha); 4507 4508 if (ha->init_cb) 4509 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4510 ha->init_cb, ha->init_cb_dma); 4511 vfree(ha->optrom_buffer); 4512 kfree(ha->nvram); 4513 kfree(ha->npiv_info); 4514 kfree(ha->swl); 4515 kfree(ha->loop_id_map); 4516 4517 ha->srb_mempool = NULL; 4518 ha->ctx_mempool = NULL; 4519 ha->sns_cmd = NULL; 4520 ha->sns_cmd_dma = 0; 4521 ha->ct_sns = NULL; 4522 ha->ct_sns_dma = 0; 4523 ha->ms_iocb = NULL; 4524 ha->ms_iocb_dma = 0; 4525 ha->init_cb = NULL; 4526 ha->init_cb_dma = 0; 4527 ha->ex_init_cb = NULL; 4528 ha->ex_init_cb_dma = 0; 4529 ha->async_pd = NULL; 4530 ha->async_pd_dma = 0; 4531 4532 ha->s_dma_pool = NULL; 4533 ha->dl_dma_pool = NULL; 4534 ha->fcp_cmnd_dma_pool = NULL; 4535 4536 ha->gid_list = NULL; 4537 ha->gid_list_dma = 0; 4538 4539 ha->tgt.atio_ring = NULL; 4540 ha->tgt.atio_dma = 0; 4541 ha->tgt.tgt_vp_map = NULL; 4542 } 4543 4544 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4545 struct qla_hw_data *ha) 4546 { 4547 struct Scsi_Host *host; 4548 struct scsi_qla_host *vha = NULL; 4549 4550 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4551 if (!host) { 4552 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4553 "Failed to allocate host from the scsi layer, aborting.\n"); 4554 return NULL; 4555 } 4556 4557 /* Clear our data area */ 4558 vha = shost_priv(host); 4559 memset(vha, 0, sizeof(scsi_qla_host_t)); 4560 4561 vha->host = host; 4562 vha->host_no = host->host_no; 4563 vha->hw = ha; 4564 4565 INIT_LIST_HEAD(&vha->vp_fcports); 4566 INIT_LIST_HEAD(&vha->work_list); 4567 INIT_LIST_HEAD(&vha->list); 4568 INIT_LIST_HEAD(&vha->qla_cmd_list); 4569 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4570 INIT_LIST_HEAD(&vha->logo_list); 4571 INIT_LIST_HEAD(&vha->plogi_ack_list); 4572 INIT_LIST_HEAD(&vha->qp_list); 4573 INIT_LIST_HEAD(&vha->gnl.fcports); 4574 INIT_LIST_HEAD(&vha->nvme_rport_list); 4575 INIT_LIST_HEAD(&vha->gpnid_list); 4576 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4577 4578 spin_lock_init(&vha->work_lock); 4579 spin_lock_init(&vha->cmd_list_lock); 4580 init_waitqueue_head(&vha->fcport_waitQ); 4581 init_waitqueue_head(&vha->vref_waitq); 4582 4583 vha->gnl.size = sizeof(struct get_name_list_extended) * 4584 (ha->max_loop_id + 1); 4585 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4586 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4587 if (!vha->gnl.l) { 4588 ql_log(ql_log_fatal, vha, 0xd04a, 4589 "Alloc failed for name list.\n"); 4590 scsi_remove_host(vha->host); 4591 return NULL; 4592 } 4593 4594 /* todo: what about ext login? */ 4595 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4596 vha->scan.l = vmalloc(vha->scan.size); 4597 if (!vha->scan.l) { 4598 ql_log(ql_log_fatal, vha, 0xd04a, 4599 "Alloc failed for scan database.\n"); 4600 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4601 vha->gnl.l, vha->gnl.ldma); 4602 scsi_remove_host(vha->host); 4603 return NULL; 4604 } 4605 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4606 4607 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4608 ql_dbg(ql_dbg_init, vha, 0x0041, 4609 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4610 vha->host, vha->hw, vha, 4611 dev_name(&(ha->pdev->dev))); 4612 4613 return vha; 4614 } 4615 4616 struct qla_work_evt * 4617 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4618 { 4619 struct qla_work_evt *e; 4620 uint8_t bail; 4621 4622 QLA_VHA_MARK_BUSY(vha, bail); 4623 if (bail) 4624 return NULL; 4625 4626 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4627 if (!e) { 4628 QLA_VHA_MARK_NOT_BUSY(vha); 4629 return NULL; 4630 } 4631 4632 INIT_LIST_HEAD(&e->list); 4633 e->type = type; 4634 e->flags = QLA_EVT_FLAG_FREE; 4635 return e; 4636 } 4637 4638 int 4639 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4640 { 4641 unsigned long flags; 4642 bool q = false; 4643 4644 spin_lock_irqsave(&vha->work_lock, flags); 4645 list_add_tail(&e->list, &vha->work_list); 4646 4647 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4648 q = true; 4649 4650 spin_unlock_irqrestore(&vha->work_lock, flags); 4651 4652 if (q) 4653 queue_work(vha->hw->wq, &vha->iocb_work); 4654 4655 return QLA_SUCCESS; 4656 } 4657 4658 int 4659 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4660 u32 data) 4661 { 4662 struct qla_work_evt *e; 4663 4664 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4665 if (!e) 4666 return QLA_FUNCTION_FAILED; 4667 4668 e->u.aen.code = code; 4669 e->u.aen.data = data; 4670 return qla2x00_post_work(vha, e); 4671 } 4672 4673 int 4674 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4675 { 4676 struct qla_work_evt *e; 4677 4678 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4679 if (!e) 4680 return QLA_FUNCTION_FAILED; 4681 4682 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4683 return qla2x00_post_work(vha, e); 4684 } 4685 4686 #define qla2x00_post_async_work(name, type) \ 4687 int qla2x00_post_async_##name##_work( \ 4688 struct scsi_qla_host *vha, \ 4689 fc_port_t *fcport, uint16_t *data) \ 4690 { \ 4691 struct qla_work_evt *e; \ 4692 \ 4693 e = qla2x00_alloc_work(vha, type); \ 4694 if (!e) \ 4695 return QLA_FUNCTION_FAILED; \ 4696 \ 4697 e->u.logio.fcport = fcport; \ 4698 if (data) { \ 4699 e->u.logio.data[0] = data[0]; \ 4700 e->u.logio.data[1] = data[1]; \ 4701 } \ 4702 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4703 return qla2x00_post_work(vha, e); \ 4704 } 4705 4706 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4707 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4708 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4709 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4710 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4711 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4712 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4713 4714 int 4715 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4716 { 4717 struct qla_work_evt *e; 4718 4719 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4720 if (!e) 4721 return QLA_FUNCTION_FAILED; 4722 4723 e->u.uevent.code = code; 4724 return qla2x00_post_work(vha, e); 4725 } 4726 4727 static void 4728 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4729 { 4730 char event_string[40]; 4731 char *envp[] = { event_string, NULL }; 4732 4733 switch (code) { 4734 case QLA_UEVENT_CODE_FW_DUMP: 4735 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4736 vha->host_no); 4737 break; 4738 default: 4739 /* do nothing */ 4740 break; 4741 } 4742 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4743 } 4744 4745 int 4746 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4747 uint32_t *data, int cnt) 4748 { 4749 struct qla_work_evt *e; 4750 4751 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4752 if (!e) 4753 return QLA_FUNCTION_FAILED; 4754 4755 e->u.aenfx.evtcode = evtcode; 4756 e->u.aenfx.count = cnt; 4757 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4758 return qla2x00_post_work(vha, e); 4759 } 4760 4761 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4762 { 4763 struct qla_work_evt *e; 4764 4765 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4766 if (!e) 4767 return QLA_FUNCTION_FAILED; 4768 4769 e->u.fcport.fcport = fcport; 4770 return qla2x00_post_work(vha, e); 4771 } 4772 4773 static 4774 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4775 { 4776 unsigned long flags; 4777 fc_port_t *fcport = NULL, *tfcp; 4778 struct qlt_plogi_ack_t *pla = 4779 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4780 uint8_t free_fcport = 0; 4781 u64 wwn; 4782 4783 ql_dbg(ql_dbg_disc, vha, 0xffff, 4784 "%s %d %8phC enter\n", 4785 __func__, __LINE__, e->u.new_sess.port_name); 4786 4787 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4788 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4789 if (fcport) { 4790 fcport->d_id = e->u.new_sess.id; 4791 if (pla) { 4792 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4793 memcpy(fcport->node_name, 4794 pla->iocb.u.isp24.u.plogi.node_name, 4795 WWN_SIZE); 4796 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4797 /* we took an extra ref_count to prevent PLOGI ACK when 4798 * fcport/sess has not been created. 4799 */ 4800 pla->ref_count--; 4801 } 4802 } else { 4803 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4804 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4805 if (fcport) { 4806 fcport->d_id = e->u.new_sess.id; 4807 fcport->flags |= FCF_FABRIC_DEVICE; 4808 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4809 if (e->u.new_sess.fc4_type == FC4_TYPE_FCP_SCSI) 4810 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4811 4812 memcpy(fcport->port_name, e->u.new_sess.port_name, 4813 WWN_SIZE); 4814 } else { 4815 ql_dbg(ql_dbg_disc, vha, 0xffff, 4816 "%s %8phC mem alloc fail.\n", 4817 __func__, e->u.new_sess.port_name); 4818 4819 if (pla) 4820 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4821 return; 4822 } 4823 4824 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4825 /* search again to make sure no one else got ahead */ 4826 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4827 e->u.new_sess.port_name, 1); 4828 if (tfcp) { 4829 /* should rarily happen */ 4830 ql_dbg(ql_dbg_disc, vha, 0xffff, 4831 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4832 __func__, tfcp->port_name, tfcp->disc_state, 4833 tfcp->fw_login_state); 4834 4835 free_fcport = 1; 4836 } else { 4837 list_add_tail(&fcport->list, &vha->vp_fcports); 4838 4839 } 4840 if (pla) { 4841 qlt_plogi_ack_link(vha, pla, fcport, 4842 QLT_PLOGI_LINK_SAME_WWN); 4843 pla->ref_count--; 4844 } 4845 } 4846 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4847 4848 if (fcport) { 4849 if (N2N_TOPO(vha->hw)) 4850 fcport->flags &= ~FCF_FABRIC_DEVICE; 4851 4852 fcport->id_changed = 1; 4853 fcport->scan_state = QLA_FCPORT_FOUND; 4854 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4855 4856 if (pla) { 4857 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4858 u16 wd3_lo; 4859 4860 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4861 fcport->local = 0; 4862 fcport->loop_id = 4863 le16_to_cpu( 4864 pla->iocb.u.isp24.nport_handle); 4865 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4866 wd3_lo = 4867 le16_to_cpu( 4868 pla->iocb.u.isp24.u.prli.wd3_lo); 4869 4870 if (wd3_lo & BIT_7) 4871 fcport->conf_compl_supported = 1; 4872 4873 if ((wd3_lo & BIT_4) == 0) 4874 fcport->port_type = FCT_INITIATOR; 4875 else 4876 fcport->port_type = FCT_TARGET; 4877 } 4878 qlt_plogi_ack_unref(vha, pla); 4879 } else { 4880 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4881 tfcp = qla2x00_find_fcport_by_nportid(vha, 4882 &e->u.new_sess.id, 1); 4883 if (tfcp && (tfcp != fcport)) { 4884 /* 4885 * We have a conflict fcport with same NportID. 4886 */ 4887 ql_dbg(ql_dbg_disc, vha, 0xffff, 4888 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4889 __func__, tfcp->port_name, tfcp->disc_state, 4890 tfcp->fw_login_state); 4891 4892 switch (tfcp->disc_state) { 4893 case DSC_DELETED: 4894 break; 4895 case DSC_DELETE_PEND: 4896 fcport->login_pause = 1; 4897 tfcp->conflict = fcport; 4898 break; 4899 default: 4900 fcport->login_pause = 1; 4901 tfcp->conflict = fcport; 4902 qlt_schedule_sess_for_deletion(tfcp); 4903 break; 4904 } 4905 } 4906 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4907 4908 wwn = wwn_to_u64(fcport->node_name); 4909 4910 if (!wwn) 4911 qla24xx_async_gnnid(vha, fcport); 4912 else 4913 qla24xx_async_gnl(vha, fcport); 4914 } 4915 } 4916 4917 if (free_fcport) { 4918 qla2x00_free_fcport(fcport); 4919 if (pla) 4920 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4921 } 4922 } 4923 4924 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4925 { 4926 struct srb *sp = e->u.iosb.sp; 4927 int rval; 4928 4929 rval = qla2x00_start_sp(sp); 4930 if (rval != QLA_SUCCESS) { 4931 ql_dbg(ql_dbg_disc, vha, 0x2043, 4932 "%s: %s: Re-issue IOCB failed (%d).\n", 4933 __func__, sp->name, rval); 4934 qla24xx_sp_unmap(vha, sp); 4935 } 4936 } 4937 4938 void 4939 qla2x00_do_work(struct scsi_qla_host *vha) 4940 { 4941 struct qla_work_evt *e, *tmp; 4942 unsigned long flags; 4943 LIST_HEAD(work); 4944 4945 spin_lock_irqsave(&vha->work_lock, flags); 4946 list_splice_init(&vha->work_list, &work); 4947 spin_unlock_irqrestore(&vha->work_lock, flags); 4948 4949 list_for_each_entry_safe(e, tmp, &work, list) { 4950 list_del_init(&e->list); 4951 4952 switch (e->type) { 4953 case QLA_EVT_AEN: 4954 fc_host_post_event(vha->host, fc_get_event_number(), 4955 e->u.aen.code, e->u.aen.data); 4956 break; 4957 case QLA_EVT_IDC_ACK: 4958 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4959 break; 4960 case QLA_EVT_ASYNC_LOGIN: 4961 qla2x00_async_login(vha, e->u.logio.fcport, 4962 e->u.logio.data); 4963 break; 4964 case QLA_EVT_ASYNC_LOGOUT: 4965 qla2x00_async_logout(vha, e->u.logio.fcport); 4966 break; 4967 case QLA_EVT_ASYNC_LOGOUT_DONE: 4968 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4969 e->u.logio.data); 4970 break; 4971 case QLA_EVT_ASYNC_ADISC: 4972 qla2x00_async_adisc(vha, e->u.logio.fcport, 4973 e->u.logio.data); 4974 break; 4975 case QLA_EVT_ASYNC_ADISC_DONE: 4976 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4977 e->u.logio.data); 4978 break; 4979 case QLA_EVT_UEVENT: 4980 qla2x00_uevent_emit(vha, e->u.uevent.code); 4981 break; 4982 case QLA_EVT_AENFX: 4983 qlafx00_process_aen(vha, e); 4984 break; 4985 case QLA_EVT_GIDPN: 4986 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 4987 break; 4988 case QLA_EVT_GPNID: 4989 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 4990 break; 4991 case QLA_EVT_UNMAP: 4992 qla24xx_sp_unmap(vha, e->u.iosb.sp); 4993 break; 4994 case QLA_EVT_RELOGIN: 4995 qla2x00_relogin(vha); 4996 break; 4997 case QLA_EVT_NEW_SESS: 4998 qla24xx_create_new_sess(vha, e); 4999 break; 5000 case QLA_EVT_GPDB: 5001 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5002 e->u.fcport.opt); 5003 break; 5004 case QLA_EVT_PRLI: 5005 qla24xx_async_prli(vha, e->u.fcport.fcport); 5006 break; 5007 case QLA_EVT_GPSC: 5008 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5009 break; 5010 case QLA_EVT_UPD_FCPORT: 5011 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5012 break; 5013 case QLA_EVT_GNL: 5014 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5015 break; 5016 case QLA_EVT_NACK: 5017 qla24xx_do_nack_work(vha, e); 5018 break; 5019 case QLA_EVT_ASYNC_PRLO: 5020 qla2x00_async_prlo(vha, e->u.logio.fcport); 5021 break; 5022 case QLA_EVT_ASYNC_PRLO_DONE: 5023 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5024 e->u.logio.data); 5025 break; 5026 case QLA_EVT_GPNFT: 5027 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type); 5028 break; 5029 case QLA_EVT_GPNFT_DONE: 5030 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5031 break; 5032 case QLA_EVT_GNNFT_DONE: 5033 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5034 break; 5035 case QLA_EVT_GNNID: 5036 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5037 break; 5038 case QLA_EVT_GFPNID: 5039 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5040 break; 5041 case QLA_EVT_SP_RETRY: 5042 qla_sp_retry(vha, e); 5043 } 5044 if (e->flags & QLA_EVT_FLAG_FREE) 5045 kfree(e); 5046 5047 /* For each work completed decrement vha ref count */ 5048 QLA_VHA_MARK_NOT_BUSY(vha); 5049 } 5050 } 5051 5052 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5053 { 5054 struct qla_work_evt *e; 5055 5056 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5057 5058 if (!e) { 5059 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5060 return QLA_FUNCTION_FAILED; 5061 } 5062 5063 return qla2x00_post_work(vha, e); 5064 } 5065 5066 /* Relogins all the fcports of a vport 5067 * Context: dpc thread 5068 */ 5069 void qla2x00_relogin(struct scsi_qla_host *vha) 5070 { 5071 fc_port_t *fcport; 5072 int status; 5073 struct event_arg ea; 5074 5075 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5076 /* 5077 * If the port is not ONLINE then try to login 5078 * to it if we haven't run out of retries. 5079 */ 5080 if (atomic_read(&fcport->state) != FCS_ONLINE && 5081 fcport->login_retry && 5082 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) { 5083 if (vha->hw->current_topology != ISP_CFG_NL) { 5084 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 5085 "%s %8phC DS %d LS %d\n", __func__, 5086 fcport->port_name, fcport->disc_state, 5087 fcport->fw_login_state); 5088 memset(&ea, 0, sizeof(ea)); 5089 ea.event = FCME_RELOGIN; 5090 ea.fcport = fcport; 5091 qla2x00_fcport_event_handler(vha, &ea); 5092 } else if (vha->hw->current_topology == ISP_CFG_NL) { 5093 fcport->login_retry--; 5094 status = qla2x00_local_device_login(vha, 5095 fcport); 5096 if (status == QLA_SUCCESS) { 5097 fcport->old_loop_id = fcport->loop_id; 5098 ql_dbg(ql_dbg_disc, vha, 0x2003, 5099 "Port login OK: logged in ID 0x%x.\n", 5100 fcport->loop_id); 5101 qla2x00_update_fcport(vha, fcport); 5102 } else if (status == 1) { 5103 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5104 /* retry the login again */ 5105 ql_dbg(ql_dbg_disc, vha, 0x2007, 5106 "Retrying %d login again loop_id 0x%x.\n", 5107 fcport->login_retry, 5108 fcport->loop_id); 5109 } else { 5110 fcport->login_retry = 0; 5111 } 5112 5113 if (fcport->login_retry == 0 && 5114 status != QLA_SUCCESS) 5115 qla2x00_clear_loop_id(fcport); 5116 } 5117 } 5118 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5119 break; 5120 } 5121 5122 ql_dbg(ql_dbg_disc, vha, 0x400e, 5123 "Relogin end.\n"); 5124 } 5125 5126 /* Schedule work on any of the dpc-workqueues */ 5127 void 5128 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5129 { 5130 struct qla_hw_data *ha = base_vha->hw; 5131 5132 switch (work_code) { 5133 case MBA_IDC_AEN: /* 0x8200 */ 5134 if (ha->dpc_lp_wq) 5135 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5136 break; 5137 5138 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5139 if (!ha->flags.nic_core_reset_hdlr_active) { 5140 if (ha->dpc_hp_wq) 5141 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5142 } else 5143 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5144 "NIC Core reset is already active. Skip " 5145 "scheduling it again.\n"); 5146 break; 5147 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5148 if (ha->dpc_hp_wq) 5149 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5150 break; 5151 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5152 if (ha->dpc_hp_wq) 5153 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5154 break; 5155 default: 5156 ql_log(ql_log_warn, base_vha, 0xb05f, 5157 "Unknown work-code=0x%x.\n", work_code); 5158 } 5159 5160 return; 5161 } 5162 5163 /* Work: Perform NIC Core Unrecoverable state handling */ 5164 void 5165 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5166 { 5167 struct qla_hw_data *ha = 5168 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5169 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5170 uint32_t dev_state = 0; 5171 5172 qla83xx_idc_lock(base_vha, 0); 5173 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5174 qla83xx_reset_ownership(base_vha); 5175 if (ha->flags.nic_core_reset_owner) { 5176 ha->flags.nic_core_reset_owner = 0; 5177 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5178 QLA8XXX_DEV_FAILED); 5179 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5180 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5181 } 5182 qla83xx_idc_unlock(base_vha, 0); 5183 } 5184 5185 /* Work: Execute IDC state handler */ 5186 void 5187 qla83xx_idc_state_handler_work(struct work_struct *work) 5188 { 5189 struct qla_hw_data *ha = 5190 container_of(work, struct qla_hw_data, idc_state_handler); 5191 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5192 uint32_t dev_state = 0; 5193 5194 qla83xx_idc_lock(base_vha, 0); 5195 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5196 if (dev_state == QLA8XXX_DEV_FAILED || 5197 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5198 qla83xx_idc_state_handler(base_vha); 5199 qla83xx_idc_unlock(base_vha, 0); 5200 } 5201 5202 static int 5203 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5204 { 5205 int rval = QLA_SUCCESS; 5206 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5207 uint32_t heart_beat_counter1, heart_beat_counter2; 5208 5209 do { 5210 if (time_after(jiffies, heart_beat_wait)) { 5211 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5212 "Nic Core f/w is not alive.\n"); 5213 rval = QLA_FUNCTION_FAILED; 5214 break; 5215 } 5216 5217 qla83xx_idc_lock(base_vha, 0); 5218 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5219 &heart_beat_counter1); 5220 qla83xx_idc_unlock(base_vha, 0); 5221 msleep(100); 5222 qla83xx_idc_lock(base_vha, 0); 5223 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5224 &heart_beat_counter2); 5225 qla83xx_idc_unlock(base_vha, 0); 5226 } while (heart_beat_counter1 == heart_beat_counter2); 5227 5228 return rval; 5229 } 5230 5231 /* Work: Perform NIC Core Reset handling */ 5232 void 5233 qla83xx_nic_core_reset_work(struct work_struct *work) 5234 { 5235 struct qla_hw_data *ha = 5236 container_of(work, struct qla_hw_data, nic_core_reset); 5237 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5238 uint32_t dev_state = 0; 5239 5240 if (IS_QLA2031(ha)) { 5241 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5242 ql_log(ql_log_warn, base_vha, 0xb081, 5243 "Failed to dump mctp\n"); 5244 return; 5245 } 5246 5247 if (!ha->flags.nic_core_reset_hdlr_active) { 5248 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5249 qla83xx_idc_lock(base_vha, 0); 5250 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5251 &dev_state); 5252 qla83xx_idc_unlock(base_vha, 0); 5253 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5254 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5255 "Nic Core f/w is alive.\n"); 5256 return; 5257 } 5258 } 5259 5260 ha->flags.nic_core_reset_hdlr_active = 1; 5261 if (qla83xx_nic_core_reset(base_vha)) { 5262 /* NIC Core reset failed. */ 5263 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5264 "NIC Core reset failed.\n"); 5265 } 5266 ha->flags.nic_core_reset_hdlr_active = 0; 5267 } 5268 } 5269 5270 /* Work: Handle 8200 IDC aens */ 5271 void 5272 qla83xx_service_idc_aen(struct work_struct *work) 5273 { 5274 struct qla_hw_data *ha = 5275 container_of(work, struct qla_hw_data, idc_aen); 5276 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5277 uint32_t dev_state, idc_control; 5278 5279 qla83xx_idc_lock(base_vha, 0); 5280 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5281 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5282 qla83xx_idc_unlock(base_vha, 0); 5283 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5284 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5285 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5286 "Application requested NIC Core Reset.\n"); 5287 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5288 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5289 QLA_SUCCESS) { 5290 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5291 "Other protocol driver requested NIC Core Reset.\n"); 5292 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5293 } 5294 } else if (dev_state == QLA8XXX_DEV_FAILED || 5295 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5296 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5297 } 5298 } 5299 5300 static void 5301 qla83xx_wait_logic(void) 5302 { 5303 int i; 5304 5305 /* Yield CPU */ 5306 if (!in_interrupt()) { 5307 /* 5308 * Wait about 200ms before retrying again. 5309 * This controls the number of retries for single 5310 * lock operation. 5311 */ 5312 msleep(100); 5313 schedule(); 5314 } else { 5315 for (i = 0; i < 20; i++) 5316 cpu_relax(); /* This a nop instr on i386 */ 5317 } 5318 } 5319 5320 static int 5321 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5322 { 5323 int rval; 5324 uint32_t data; 5325 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5326 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5327 struct qla_hw_data *ha = base_vha->hw; 5328 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5329 "Trying force recovery of the IDC lock.\n"); 5330 5331 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5332 if (rval) 5333 return rval; 5334 5335 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5336 return QLA_SUCCESS; 5337 } else { 5338 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5339 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5340 data); 5341 if (rval) 5342 return rval; 5343 5344 msleep(200); 5345 5346 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5347 &data); 5348 if (rval) 5349 return rval; 5350 5351 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5352 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5353 ~(idc_lck_rcvry_stage_mask)); 5354 rval = qla83xx_wr_reg(base_vha, 5355 QLA83XX_IDC_LOCK_RECOVERY, data); 5356 if (rval) 5357 return rval; 5358 5359 /* Forcefully perform IDC UnLock */ 5360 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5361 &data); 5362 if (rval) 5363 return rval; 5364 /* Clear lock-id by setting 0xff */ 5365 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5366 0xff); 5367 if (rval) 5368 return rval; 5369 /* Clear lock-recovery by setting 0x0 */ 5370 rval = qla83xx_wr_reg(base_vha, 5371 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5372 if (rval) 5373 return rval; 5374 } else 5375 return QLA_SUCCESS; 5376 } 5377 5378 return rval; 5379 } 5380 5381 static int 5382 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5383 { 5384 int rval = QLA_SUCCESS; 5385 uint32_t o_drv_lockid, n_drv_lockid; 5386 unsigned long lock_recovery_timeout; 5387 5388 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5389 retry_lockid: 5390 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5391 if (rval) 5392 goto exit; 5393 5394 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5395 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5396 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5397 return QLA_SUCCESS; 5398 else 5399 return QLA_FUNCTION_FAILED; 5400 } 5401 5402 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5403 if (rval) 5404 goto exit; 5405 5406 if (o_drv_lockid == n_drv_lockid) { 5407 qla83xx_wait_logic(); 5408 goto retry_lockid; 5409 } else 5410 return QLA_SUCCESS; 5411 5412 exit: 5413 return rval; 5414 } 5415 5416 void 5417 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5418 { 5419 uint16_t options = (requester_id << 15) | BIT_6; 5420 uint32_t data; 5421 uint32_t lock_owner; 5422 struct qla_hw_data *ha = base_vha->hw; 5423 5424 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5425 retry_lock: 5426 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5427 == QLA_SUCCESS) { 5428 if (data) { 5429 /* Setting lock-id to our function-number */ 5430 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5431 ha->portnum); 5432 } else { 5433 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5434 &lock_owner); 5435 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5436 "Failed to acquire IDC lock, acquired by %d, " 5437 "retrying...\n", lock_owner); 5438 5439 /* Retry/Perform IDC-Lock recovery */ 5440 if (qla83xx_idc_lock_recovery(base_vha) 5441 == QLA_SUCCESS) { 5442 qla83xx_wait_logic(); 5443 goto retry_lock; 5444 } else 5445 ql_log(ql_log_warn, base_vha, 0xb075, 5446 "IDC Lock recovery FAILED.\n"); 5447 } 5448 5449 } 5450 5451 return; 5452 5453 /* XXX: IDC-lock implementation using access-control mbx */ 5454 retry_lock2: 5455 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5456 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5457 "Failed to acquire IDC lock. retrying...\n"); 5458 /* Retry/Perform IDC-Lock recovery */ 5459 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5460 qla83xx_wait_logic(); 5461 goto retry_lock2; 5462 } else 5463 ql_log(ql_log_warn, base_vha, 0xb076, 5464 "IDC Lock recovery FAILED.\n"); 5465 } 5466 5467 return; 5468 } 5469 5470 void 5471 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5472 { 5473 #if 0 5474 uint16_t options = (requester_id << 15) | BIT_7; 5475 #endif 5476 uint16_t retry; 5477 uint32_t data; 5478 struct qla_hw_data *ha = base_vha->hw; 5479 5480 /* IDC-unlock implementation using driver-unlock/lock-id 5481 * remote registers 5482 */ 5483 retry = 0; 5484 retry_unlock: 5485 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5486 == QLA_SUCCESS) { 5487 if (data == ha->portnum) { 5488 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5489 /* Clearing lock-id by setting 0xff */ 5490 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5491 } else if (retry < 10) { 5492 /* SV: XXX: IDC unlock retrying needed here? */ 5493 5494 /* Retry for IDC-unlock */ 5495 qla83xx_wait_logic(); 5496 retry++; 5497 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5498 "Failed to release IDC lock, retrying=%d\n", retry); 5499 goto retry_unlock; 5500 } 5501 } else if (retry < 10) { 5502 /* Retry for IDC-unlock */ 5503 qla83xx_wait_logic(); 5504 retry++; 5505 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5506 "Failed to read drv-lockid, retrying=%d\n", retry); 5507 goto retry_unlock; 5508 } 5509 5510 return; 5511 5512 #if 0 5513 /* XXX: IDC-unlock implementation using access-control mbx */ 5514 retry = 0; 5515 retry_unlock2: 5516 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5517 if (retry < 10) { 5518 /* Retry for IDC-unlock */ 5519 qla83xx_wait_logic(); 5520 retry++; 5521 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5522 "Failed to release IDC lock, retrying=%d\n", retry); 5523 goto retry_unlock2; 5524 } 5525 } 5526 5527 return; 5528 #endif 5529 } 5530 5531 int 5532 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5533 { 5534 int rval = QLA_SUCCESS; 5535 struct qla_hw_data *ha = vha->hw; 5536 uint32_t drv_presence; 5537 5538 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5539 if (rval == QLA_SUCCESS) { 5540 drv_presence |= (1 << ha->portnum); 5541 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5542 drv_presence); 5543 } 5544 5545 return rval; 5546 } 5547 5548 int 5549 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5550 { 5551 int rval = QLA_SUCCESS; 5552 5553 qla83xx_idc_lock(vha, 0); 5554 rval = __qla83xx_set_drv_presence(vha); 5555 qla83xx_idc_unlock(vha, 0); 5556 5557 return rval; 5558 } 5559 5560 int 5561 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5562 { 5563 int rval = QLA_SUCCESS; 5564 struct qla_hw_data *ha = vha->hw; 5565 uint32_t drv_presence; 5566 5567 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5568 if (rval == QLA_SUCCESS) { 5569 drv_presence &= ~(1 << ha->portnum); 5570 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5571 drv_presence); 5572 } 5573 5574 return rval; 5575 } 5576 5577 int 5578 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5579 { 5580 int rval = QLA_SUCCESS; 5581 5582 qla83xx_idc_lock(vha, 0); 5583 rval = __qla83xx_clear_drv_presence(vha); 5584 qla83xx_idc_unlock(vha, 0); 5585 5586 return rval; 5587 } 5588 5589 static void 5590 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5591 { 5592 struct qla_hw_data *ha = vha->hw; 5593 uint32_t drv_ack, drv_presence; 5594 unsigned long ack_timeout; 5595 5596 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5597 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5598 while (1) { 5599 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5600 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5601 if ((drv_ack & drv_presence) == drv_presence) 5602 break; 5603 5604 if (time_after_eq(jiffies, ack_timeout)) { 5605 ql_log(ql_log_warn, vha, 0xb067, 5606 "RESET ACK TIMEOUT! drv_presence=0x%x " 5607 "drv_ack=0x%x\n", drv_presence, drv_ack); 5608 /* 5609 * The function(s) which did not ack in time are forced 5610 * to withdraw any further participation in the IDC 5611 * reset. 5612 */ 5613 if (drv_ack != drv_presence) 5614 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5615 drv_ack); 5616 break; 5617 } 5618 5619 qla83xx_idc_unlock(vha, 0); 5620 msleep(1000); 5621 qla83xx_idc_lock(vha, 0); 5622 } 5623 5624 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5625 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5626 } 5627 5628 static int 5629 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5630 { 5631 int rval = QLA_SUCCESS; 5632 uint32_t idc_control; 5633 5634 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5635 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5636 5637 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5638 __qla83xx_get_idc_control(vha, &idc_control); 5639 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5640 __qla83xx_set_idc_control(vha, 0); 5641 5642 qla83xx_idc_unlock(vha, 0); 5643 rval = qla83xx_restart_nic_firmware(vha); 5644 qla83xx_idc_lock(vha, 0); 5645 5646 if (rval != QLA_SUCCESS) { 5647 ql_log(ql_log_fatal, vha, 0xb06a, 5648 "Failed to restart NIC f/w.\n"); 5649 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5650 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5651 } else { 5652 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5653 "Success in restarting nic f/w.\n"); 5654 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5655 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5656 } 5657 5658 return rval; 5659 } 5660 5661 /* Assumes idc_lock always held on entry */ 5662 int 5663 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5664 { 5665 struct qla_hw_data *ha = base_vha->hw; 5666 int rval = QLA_SUCCESS; 5667 unsigned long dev_init_timeout; 5668 uint32_t dev_state; 5669 5670 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5671 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5672 5673 while (1) { 5674 5675 if (time_after_eq(jiffies, dev_init_timeout)) { 5676 ql_log(ql_log_warn, base_vha, 0xb06e, 5677 "Initialization TIMEOUT!\n"); 5678 /* Init timeout. Disable further NIC Core 5679 * communication. 5680 */ 5681 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5682 QLA8XXX_DEV_FAILED); 5683 ql_log(ql_log_info, base_vha, 0xb06f, 5684 "HW State: FAILED.\n"); 5685 } 5686 5687 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5688 switch (dev_state) { 5689 case QLA8XXX_DEV_READY: 5690 if (ha->flags.nic_core_reset_owner) 5691 qla83xx_idc_audit(base_vha, 5692 IDC_AUDIT_COMPLETION); 5693 ha->flags.nic_core_reset_owner = 0; 5694 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5695 "Reset_owner reset by 0x%x.\n", 5696 ha->portnum); 5697 goto exit; 5698 case QLA8XXX_DEV_COLD: 5699 if (ha->flags.nic_core_reset_owner) 5700 rval = qla83xx_device_bootstrap(base_vha); 5701 else { 5702 /* Wait for AEN to change device-state */ 5703 qla83xx_idc_unlock(base_vha, 0); 5704 msleep(1000); 5705 qla83xx_idc_lock(base_vha, 0); 5706 } 5707 break; 5708 case QLA8XXX_DEV_INITIALIZING: 5709 /* Wait for AEN to change device-state */ 5710 qla83xx_idc_unlock(base_vha, 0); 5711 msleep(1000); 5712 qla83xx_idc_lock(base_vha, 0); 5713 break; 5714 case QLA8XXX_DEV_NEED_RESET: 5715 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5716 qla83xx_need_reset_handler(base_vha); 5717 else { 5718 /* Wait for AEN to change device-state */ 5719 qla83xx_idc_unlock(base_vha, 0); 5720 msleep(1000); 5721 qla83xx_idc_lock(base_vha, 0); 5722 } 5723 /* reset timeout value after need reset handler */ 5724 dev_init_timeout = jiffies + 5725 (ha->fcoe_dev_init_timeout * HZ); 5726 break; 5727 case QLA8XXX_DEV_NEED_QUIESCENT: 5728 /* XXX: DEBUG for now */ 5729 qla83xx_idc_unlock(base_vha, 0); 5730 msleep(1000); 5731 qla83xx_idc_lock(base_vha, 0); 5732 break; 5733 case QLA8XXX_DEV_QUIESCENT: 5734 /* XXX: DEBUG for now */ 5735 if (ha->flags.quiesce_owner) 5736 goto exit; 5737 5738 qla83xx_idc_unlock(base_vha, 0); 5739 msleep(1000); 5740 qla83xx_idc_lock(base_vha, 0); 5741 dev_init_timeout = jiffies + 5742 (ha->fcoe_dev_init_timeout * HZ); 5743 break; 5744 case QLA8XXX_DEV_FAILED: 5745 if (ha->flags.nic_core_reset_owner) 5746 qla83xx_idc_audit(base_vha, 5747 IDC_AUDIT_COMPLETION); 5748 ha->flags.nic_core_reset_owner = 0; 5749 __qla83xx_clear_drv_presence(base_vha); 5750 qla83xx_idc_unlock(base_vha, 0); 5751 qla8xxx_dev_failed_handler(base_vha); 5752 rval = QLA_FUNCTION_FAILED; 5753 qla83xx_idc_lock(base_vha, 0); 5754 goto exit; 5755 case QLA8XXX_BAD_VALUE: 5756 qla83xx_idc_unlock(base_vha, 0); 5757 msleep(1000); 5758 qla83xx_idc_lock(base_vha, 0); 5759 break; 5760 default: 5761 ql_log(ql_log_warn, base_vha, 0xb071, 5762 "Unknown Device State: %x.\n", dev_state); 5763 qla83xx_idc_unlock(base_vha, 0); 5764 qla8xxx_dev_failed_handler(base_vha); 5765 rval = QLA_FUNCTION_FAILED; 5766 qla83xx_idc_lock(base_vha, 0); 5767 goto exit; 5768 } 5769 } 5770 5771 exit: 5772 return rval; 5773 } 5774 5775 void 5776 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5777 { 5778 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5779 board_disable); 5780 struct pci_dev *pdev = ha->pdev; 5781 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5782 5783 /* 5784 * if UNLOAD flag is already set, then continue unload, 5785 * where it was set first. 5786 */ 5787 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5788 return; 5789 5790 ql_log(ql_log_warn, base_vha, 0x015b, 5791 "Disabling adapter.\n"); 5792 5793 if (!atomic_read(&pdev->enable_cnt)) { 5794 ql_log(ql_log_info, base_vha, 0xfffc, 5795 "PCI device disabled, no action req for PCI error=%lx\n", 5796 base_vha->pci_flags); 5797 return; 5798 } 5799 5800 qla2x00_wait_for_sess_deletion(base_vha); 5801 5802 set_bit(UNLOADING, &base_vha->dpc_flags); 5803 5804 qla2x00_delete_all_vps(ha, base_vha); 5805 5806 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5807 5808 qla2x00_dfs_remove(base_vha); 5809 5810 qla84xx_put_chip(base_vha); 5811 5812 if (base_vha->timer_active) 5813 qla2x00_stop_timer(base_vha); 5814 5815 base_vha->flags.online = 0; 5816 5817 qla2x00_destroy_deferred_work(ha); 5818 5819 /* 5820 * Do not try to stop beacon blink as it will issue a mailbox 5821 * command. 5822 */ 5823 qla2x00_free_sysfs_attr(base_vha, false); 5824 5825 fc_remove_host(base_vha->host); 5826 5827 scsi_remove_host(base_vha->host); 5828 5829 base_vha->flags.init_done = 0; 5830 qla25xx_delete_queues(base_vha); 5831 qla2x00_free_fcports(base_vha); 5832 qla2x00_free_irqs(base_vha); 5833 qla2x00_mem_free(ha); 5834 qla82xx_md_free(base_vha); 5835 qla2x00_free_queues(ha); 5836 5837 qla2x00_unmap_iobases(ha); 5838 5839 pci_release_selected_regions(ha->pdev, ha->bars); 5840 pci_disable_pcie_error_reporting(pdev); 5841 pci_disable_device(pdev); 5842 5843 /* 5844 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5845 */ 5846 } 5847 5848 /************************************************************************** 5849 * qla2x00_do_dpc 5850 * This kernel thread is a task that is schedule by the interrupt handler 5851 * to perform the background processing for interrupts. 5852 * 5853 * Notes: 5854 * This task always run in the context of a kernel thread. It 5855 * is kick-off by the driver's detect code and starts up 5856 * up one per adapter. It immediately goes to sleep and waits for 5857 * some fibre event. When either the interrupt handler or 5858 * the timer routine detects a event it will one of the task 5859 * bits then wake us up. 5860 **************************************************************************/ 5861 static int 5862 qla2x00_do_dpc(void *data) 5863 { 5864 scsi_qla_host_t *base_vha; 5865 struct qla_hw_data *ha; 5866 uint32_t online; 5867 struct qla_qpair *qpair; 5868 5869 ha = (struct qla_hw_data *)data; 5870 base_vha = pci_get_drvdata(ha->pdev); 5871 5872 set_user_nice(current, MIN_NICE); 5873 5874 set_current_state(TASK_INTERRUPTIBLE); 5875 while (!kthread_should_stop()) { 5876 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5877 "DPC handler sleeping.\n"); 5878 5879 schedule(); 5880 5881 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5882 goto end_loop; 5883 5884 if (ha->flags.eeh_busy) { 5885 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5886 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5887 goto end_loop; 5888 } 5889 5890 ha->dpc_active = 1; 5891 5892 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5893 "DPC handler waking up, dpc_flags=0x%lx.\n", 5894 base_vha->dpc_flags); 5895 5896 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5897 break; 5898 5899 if (IS_P3P_TYPE(ha)) { 5900 if (IS_QLA8044(ha)) { 5901 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5902 &base_vha->dpc_flags)) { 5903 qla8044_idc_lock(ha); 5904 qla8044_wr_direct(base_vha, 5905 QLA8044_CRB_DEV_STATE_INDEX, 5906 QLA8XXX_DEV_FAILED); 5907 qla8044_idc_unlock(ha); 5908 ql_log(ql_log_info, base_vha, 0x4004, 5909 "HW State: FAILED.\n"); 5910 qla8044_device_state_handler(base_vha); 5911 continue; 5912 } 5913 5914 } else { 5915 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5916 &base_vha->dpc_flags)) { 5917 qla82xx_idc_lock(ha); 5918 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5919 QLA8XXX_DEV_FAILED); 5920 qla82xx_idc_unlock(ha); 5921 ql_log(ql_log_info, base_vha, 0x0151, 5922 "HW State: FAILED.\n"); 5923 qla82xx_device_state_handler(base_vha); 5924 continue; 5925 } 5926 } 5927 5928 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5929 &base_vha->dpc_flags)) { 5930 5931 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5932 "FCoE context reset scheduled.\n"); 5933 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5934 &base_vha->dpc_flags))) { 5935 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5936 /* FCoE-ctx reset failed. 5937 * Escalate to chip-reset 5938 */ 5939 set_bit(ISP_ABORT_NEEDED, 5940 &base_vha->dpc_flags); 5941 } 5942 clear_bit(ABORT_ISP_ACTIVE, 5943 &base_vha->dpc_flags); 5944 } 5945 5946 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5947 "FCoE context reset end.\n"); 5948 } 5949 } else if (IS_QLAFX00(ha)) { 5950 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5951 &base_vha->dpc_flags)) { 5952 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5953 "Firmware Reset Recovery\n"); 5954 if (qlafx00_reset_initialize(base_vha)) { 5955 /* Failed. Abort isp later. */ 5956 if (!test_bit(UNLOADING, 5957 &base_vha->dpc_flags)) { 5958 set_bit(ISP_UNRECOVERABLE, 5959 &base_vha->dpc_flags); 5960 ql_dbg(ql_dbg_dpc, base_vha, 5961 0x4021, 5962 "Reset Recovery Failed\n"); 5963 } 5964 } 5965 } 5966 5967 if (test_and_clear_bit(FX00_TARGET_SCAN, 5968 &base_vha->dpc_flags)) { 5969 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5970 "ISPFx00 Target Scan scheduled\n"); 5971 if (qlafx00_rescan_isp(base_vha)) { 5972 if (!test_bit(UNLOADING, 5973 &base_vha->dpc_flags)) 5974 set_bit(ISP_UNRECOVERABLE, 5975 &base_vha->dpc_flags); 5976 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5977 "ISPFx00 Target Scan Failed\n"); 5978 } 5979 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5980 "ISPFx00 Target Scan End\n"); 5981 } 5982 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5983 &base_vha->dpc_flags)) { 5984 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5985 "ISPFx00 Host Info resend scheduled\n"); 5986 qlafx00_fx_disc(base_vha, 5987 &base_vha->hw->mr.fcport, 5988 FXDISC_REG_HOST_INFO); 5989 } 5990 } 5991 5992 if (test_and_clear_bit(DETECT_SFP_CHANGE, 5993 &base_vha->dpc_flags) && 5994 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 5995 qla24xx_detect_sfp(base_vha); 5996 5997 if (ha->flags.detected_lr_sfp != 5998 ha->flags.using_lr_setting) 5999 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6000 } 6001 6002 if (test_and_clear_bit(ISP_ABORT_NEEDED, 6003 &base_vha->dpc_flags)) { 6004 6005 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6006 "ISP abort scheduled.\n"); 6007 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6008 &base_vha->dpc_flags))) { 6009 6010 if (ha->isp_ops->abort_isp(base_vha)) { 6011 /* failed. retry later */ 6012 set_bit(ISP_ABORT_NEEDED, 6013 &base_vha->dpc_flags); 6014 } 6015 clear_bit(ABORT_ISP_ACTIVE, 6016 &base_vha->dpc_flags); 6017 } 6018 6019 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6020 "ISP abort end.\n"); 6021 } 6022 6023 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6024 &base_vha->dpc_flags)) { 6025 qla2x00_update_fcports(base_vha); 6026 } 6027 6028 if (IS_QLAFX00(ha)) 6029 goto loop_resync_check; 6030 6031 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6032 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6033 "Quiescence mode scheduled.\n"); 6034 if (IS_P3P_TYPE(ha)) { 6035 if (IS_QLA82XX(ha)) 6036 qla82xx_device_state_handler(base_vha); 6037 if (IS_QLA8044(ha)) 6038 qla8044_device_state_handler(base_vha); 6039 clear_bit(ISP_QUIESCE_NEEDED, 6040 &base_vha->dpc_flags); 6041 if (!ha->flags.quiesce_owner) { 6042 qla2x00_perform_loop_resync(base_vha); 6043 if (IS_QLA82XX(ha)) { 6044 qla82xx_idc_lock(ha); 6045 qla82xx_clear_qsnt_ready( 6046 base_vha); 6047 qla82xx_idc_unlock(ha); 6048 } else if (IS_QLA8044(ha)) { 6049 qla8044_idc_lock(ha); 6050 qla8044_clear_qsnt_ready( 6051 base_vha); 6052 qla8044_idc_unlock(ha); 6053 } 6054 } 6055 } else { 6056 clear_bit(ISP_QUIESCE_NEEDED, 6057 &base_vha->dpc_flags); 6058 qla2x00_quiesce_io(base_vha); 6059 } 6060 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6061 "Quiescence mode end.\n"); 6062 } 6063 6064 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6065 &base_vha->dpc_flags) && 6066 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6067 6068 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6069 "Reset marker scheduled.\n"); 6070 qla2x00_rst_aen(base_vha); 6071 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6072 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6073 "Reset marker end.\n"); 6074 } 6075 6076 /* Retry each device up to login retry count */ 6077 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6078 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6079 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6080 6081 if (!base_vha->relogin_jif || 6082 time_after_eq(jiffies, base_vha->relogin_jif)) { 6083 base_vha->relogin_jif = jiffies + HZ; 6084 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6085 6086 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6087 "Relogin scheduled.\n"); 6088 qla24xx_post_relogin_work(base_vha); 6089 } 6090 } 6091 loop_resync_check: 6092 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6093 &base_vha->dpc_flags)) { 6094 6095 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6096 "Loop resync scheduled.\n"); 6097 6098 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6099 &base_vha->dpc_flags))) { 6100 6101 qla2x00_loop_resync(base_vha); 6102 6103 clear_bit(LOOP_RESYNC_ACTIVE, 6104 &base_vha->dpc_flags); 6105 } 6106 6107 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6108 "Loop resync end.\n"); 6109 } 6110 6111 if (IS_QLAFX00(ha)) 6112 goto intr_on_check; 6113 6114 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6115 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6116 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6117 qla2xxx_flash_npiv_conf(base_vha); 6118 } 6119 6120 intr_on_check: 6121 if (!ha->interrupts_on) 6122 ha->isp_ops->enable_intrs(ha); 6123 6124 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6125 &base_vha->dpc_flags)) { 6126 if (ha->beacon_blink_led == 1) 6127 ha->isp_ops->beacon_blink(base_vha); 6128 } 6129 6130 /* qpair online check */ 6131 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6132 &base_vha->dpc_flags)) { 6133 if (ha->flags.eeh_busy || 6134 ha->flags.pci_channel_io_perm_failure) 6135 online = 0; 6136 else 6137 online = 1; 6138 6139 mutex_lock(&ha->mq_lock); 6140 list_for_each_entry(qpair, &base_vha->qp_list, 6141 qp_list_elem) 6142 qpair->online = online; 6143 mutex_unlock(&ha->mq_lock); 6144 } 6145 6146 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6147 ql_log(ql_log_info, base_vha, 0xffffff, 6148 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6149 ha->nvme_last_rptd_aen); 6150 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6151 ql_log(ql_log_info, base_vha, 0xffffff, 6152 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6153 ha->nvme_last_rptd_aen); 6154 } 6155 } 6156 6157 if (!IS_QLAFX00(ha)) 6158 qla2x00_do_dpc_all_vps(base_vha); 6159 6160 ha->dpc_active = 0; 6161 end_loop: 6162 set_current_state(TASK_INTERRUPTIBLE); 6163 } /* End of while(1) */ 6164 __set_current_state(TASK_RUNNING); 6165 6166 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6167 "DPC handler exiting.\n"); 6168 6169 /* 6170 * Make sure that nobody tries to wake us up again. 6171 */ 6172 ha->dpc_active = 0; 6173 6174 /* Cleanup any residual CTX SRBs. */ 6175 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6176 6177 return 0; 6178 } 6179 6180 void 6181 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6182 { 6183 struct qla_hw_data *ha = vha->hw; 6184 struct task_struct *t = ha->dpc_thread; 6185 6186 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6187 wake_up_process(t); 6188 } 6189 6190 /* 6191 * qla2x00_rst_aen 6192 * Processes asynchronous reset. 6193 * 6194 * Input: 6195 * ha = adapter block pointer. 6196 */ 6197 static void 6198 qla2x00_rst_aen(scsi_qla_host_t *vha) 6199 { 6200 if (vha->flags.online && !vha->flags.reset_active && 6201 !atomic_read(&vha->loop_down_timer) && 6202 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6203 do { 6204 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6205 6206 /* 6207 * Issue marker command only when we are going to start 6208 * the I/O. 6209 */ 6210 vha->marker_needed = 1; 6211 } while (!atomic_read(&vha->loop_down_timer) && 6212 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6213 } 6214 } 6215 6216 /************************************************************************** 6217 * qla2x00_timer 6218 * 6219 * Description: 6220 * One second timer 6221 * 6222 * Context: Interrupt 6223 ***************************************************************************/ 6224 void 6225 qla2x00_timer(struct timer_list *t) 6226 { 6227 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6228 unsigned long cpu_flags = 0; 6229 int start_dpc = 0; 6230 int index; 6231 srb_t *sp; 6232 uint16_t w; 6233 struct qla_hw_data *ha = vha->hw; 6234 struct req_que *req; 6235 6236 if (ha->flags.eeh_busy) { 6237 ql_dbg(ql_dbg_timer, vha, 0x6000, 6238 "EEH = %d, restarting timer.\n", 6239 ha->flags.eeh_busy); 6240 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6241 return; 6242 } 6243 6244 /* 6245 * Hardware read to raise pending EEH errors during mailbox waits. If 6246 * the read returns -1 then disable the board. 6247 */ 6248 if (!pci_channel_offline(ha->pdev)) { 6249 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6250 qla2x00_check_reg16_for_disconnect(vha, w); 6251 } 6252 6253 /* Make sure qla82xx_watchdog is run only for physical port */ 6254 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6255 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6256 start_dpc++; 6257 if (IS_QLA82XX(ha)) 6258 qla82xx_watchdog(vha); 6259 else if (IS_QLA8044(ha)) 6260 qla8044_watchdog(vha); 6261 } 6262 6263 if (!vha->vp_idx && IS_QLAFX00(ha)) 6264 qlafx00_timer_routine(vha); 6265 6266 /* Loop down handler. */ 6267 if (atomic_read(&vha->loop_down_timer) > 0 && 6268 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6269 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6270 && vha->flags.online) { 6271 6272 if (atomic_read(&vha->loop_down_timer) == 6273 vha->loop_down_abort_time) { 6274 6275 ql_log(ql_log_info, vha, 0x6008, 6276 "Loop down - aborting the queues before time expires.\n"); 6277 6278 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6279 atomic_set(&vha->loop_state, LOOP_DEAD); 6280 6281 /* 6282 * Schedule an ISP abort to return any FCP2-device 6283 * commands. 6284 */ 6285 /* NPIV - scan physical port only */ 6286 if (!vha->vp_idx) { 6287 spin_lock_irqsave(&ha->hardware_lock, 6288 cpu_flags); 6289 req = ha->req_q_map[0]; 6290 for (index = 1; 6291 index < req->num_outstanding_cmds; 6292 index++) { 6293 fc_port_t *sfcp; 6294 6295 sp = req->outstanding_cmds[index]; 6296 if (!sp) 6297 continue; 6298 if (sp->cmd_type != TYPE_SRB) 6299 continue; 6300 if (sp->type != SRB_SCSI_CMD) 6301 continue; 6302 sfcp = sp->fcport; 6303 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6304 continue; 6305 6306 if (IS_QLA82XX(ha)) 6307 set_bit(FCOE_CTX_RESET_NEEDED, 6308 &vha->dpc_flags); 6309 else 6310 set_bit(ISP_ABORT_NEEDED, 6311 &vha->dpc_flags); 6312 break; 6313 } 6314 spin_unlock_irqrestore(&ha->hardware_lock, 6315 cpu_flags); 6316 } 6317 start_dpc++; 6318 } 6319 6320 /* if the loop has been down for 4 minutes, reinit adapter */ 6321 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6322 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6323 ql_log(ql_log_warn, vha, 0x6009, 6324 "Loop down - aborting ISP.\n"); 6325 6326 if (IS_QLA82XX(ha)) 6327 set_bit(FCOE_CTX_RESET_NEEDED, 6328 &vha->dpc_flags); 6329 else 6330 set_bit(ISP_ABORT_NEEDED, 6331 &vha->dpc_flags); 6332 } 6333 } 6334 ql_dbg(ql_dbg_timer, vha, 0x600a, 6335 "Loop down - seconds remaining %d.\n", 6336 atomic_read(&vha->loop_down_timer)); 6337 } 6338 /* Check if beacon LED needs to be blinked for physical host only */ 6339 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6340 /* There is no beacon_blink function for ISP82xx */ 6341 if (!IS_P3P_TYPE(ha)) { 6342 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6343 start_dpc++; 6344 } 6345 } 6346 6347 /* Process any deferred work. */ 6348 if (!list_empty(&vha->work_list)) { 6349 unsigned long flags; 6350 bool q = false; 6351 6352 spin_lock_irqsave(&vha->work_lock, flags); 6353 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6354 q = true; 6355 spin_unlock_irqrestore(&vha->work_lock, flags); 6356 if (q) 6357 queue_work(vha->hw->wq, &vha->iocb_work); 6358 } 6359 6360 /* 6361 * FC-NVME 6362 * see if the active AEN count has changed from what was last reported. 6363 */ 6364 if (!vha->vp_idx && 6365 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6366 ha->zio_mode == QLA_ZIO_MODE_6) { 6367 ql_log(ql_log_info, vha, 0x3002, 6368 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6369 ha->nvme_last_rptd_aen); 6370 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6371 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6372 start_dpc++; 6373 } 6374 6375 /* Schedule the DPC routine if needed */ 6376 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6377 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6378 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6379 start_dpc || 6380 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6381 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6382 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6383 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6384 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6385 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6386 ql_dbg(ql_dbg_timer, vha, 0x600b, 6387 "isp_abort_needed=%d loop_resync_needed=%d " 6388 "fcport_update_needed=%d start_dpc=%d " 6389 "reset_marker_needed=%d", 6390 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6391 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6392 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6393 start_dpc, 6394 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6395 ql_dbg(ql_dbg_timer, vha, 0x600c, 6396 "beacon_blink_needed=%d isp_unrecoverable=%d " 6397 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6398 "relogin_needed=%d.\n", 6399 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6400 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6401 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6402 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6403 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6404 qla2xxx_wake_dpc(vha); 6405 } 6406 6407 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6408 } 6409 6410 /* Firmware interface routines. */ 6411 6412 #define FW_BLOBS 11 6413 #define FW_ISP21XX 0 6414 #define FW_ISP22XX 1 6415 #define FW_ISP2300 2 6416 #define FW_ISP2322 3 6417 #define FW_ISP24XX 4 6418 #define FW_ISP25XX 5 6419 #define FW_ISP81XX 6 6420 #define FW_ISP82XX 7 6421 #define FW_ISP2031 8 6422 #define FW_ISP8031 9 6423 #define FW_ISP27XX 10 6424 6425 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6426 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6427 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6428 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6429 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6430 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6431 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6432 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6433 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6434 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6435 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6436 6437 6438 static DEFINE_MUTEX(qla_fw_lock); 6439 6440 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6441 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6442 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6443 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6444 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6445 { .name = FW_FILE_ISP24XX, }, 6446 { .name = FW_FILE_ISP25XX, }, 6447 { .name = FW_FILE_ISP81XX, }, 6448 { .name = FW_FILE_ISP82XX, }, 6449 { .name = FW_FILE_ISP2031, }, 6450 { .name = FW_FILE_ISP8031, }, 6451 { .name = FW_FILE_ISP27XX, }, 6452 }; 6453 6454 struct fw_blob * 6455 qla2x00_request_firmware(scsi_qla_host_t *vha) 6456 { 6457 struct qla_hw_data *ha = vha->hw; 6458 struct fw_blob *blob; 6459 6460 if (IS_QLA2100(ha)) { 6461 blob = &qla_fw_blobs[FW_ISP21XX]; 6462 } else if (IS_QLA2200(ha)) { 6463 blob = &qla_fw_blobs[FW_ISP22XX]; 6464 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6465 blob = &qla_fw_blobs[FW_ISP2300]; 6466 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6467 blob = &qla_fw_blobs[FW_ISP2322]; 6468 } else if (IS_QLA24XX_TYPE(ha)) { 6469 blob = &qla_fw_blobs[FW_ISP24XX]; 6470 } else if (IS_QLA25XX(ha)) { 6471 blob = &qla_fw_blobs[FW_ISP25XX]; 6472 } else if (IS_QLA81XX(ha)) { 6473 blob = &qla_fw_blobs[FW_ISP81XX]; 6474 } else if (IS_QLA82XX(ha)) { 6475 blob = &qla_fw_blobs[FW_ISP82XX]; 6476 } else if (IS_QLA2031(ha)) { 6477 blob = &qla_fw_blobs[FW_ISP2031]; 6478 } else if (IS_QLA8031(ha)) { 6479 blob = &qla_fw_blobs[FW_ISP8031]; 6480 } else if (IS_QLA27XX(ha)) { 6481 blob = &qla_fw_blobs[FW_ISP27XX]; 6482 } else { 6483 return NULL; 6484 } 6485 6486 mutex_lock(&qla_fw_lock); 6487 if (blob->fw) 6488 goto out; 6489 6490 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6491 ql_log(ql_log_warn, vha, 0x0063, 6492 "Failed to load firmware image (%s).\n", blob->name); 6493 blob->fw = NULL; 6494 blob = NULL; 6495 goto out; 6496 } 6497 6498 out: 6499 mutex_unlock(&qla_fw_lock); 6500 return blob; 6501 } 6502 6503 static void 6504 qla2x00_release_firmware(void) 6505 { 6506 int idx; 6507 6508 mutex_lock(&qla_fw_lock); 6509 for (idx = 0; idx < FW_BLOBS; idx++) 6510 release_firmware(qla_fw_blobs[idx].fw); 6511 mutex_unlock(&qla_fw_lock); 6512 } 6513 6514 static pci_ers_result_t 6515 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6516 { 6517 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6518 struct qla_hw_data *ha = vha->hw; 6519 6520 ql_dbg(ql_dbg_aer, vha, 0x9000, 6521 "PCI error detected, state %x.\n", state); 6522 6523 if (!atomic_read(&pdev->enable_cnt)) { 6524 ql_log(ql_log_info, vha, 0xffff, 6525 "PCI device is disabled,state %x\n", state); 6526 return PCI_ERS_RESULT_NEED_RESET; 6527 } 6528 6529 switch (state) { 6530 case pci_channel_io_normal: 6531 ha->flags.eeh_busy = 0; 6532 if (ql2xmqsupport || ql2xnvmeenable) { 6533 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6534 qla2xxx_wake_dpc(vha); 6535 } 6536 return PCI_ERS_RESULT_CAN_RECOVER; 6537 case pci_channel_io_frozen: 6538 ha->flags.eeh_busy = 1; 6539 /* For ISP82XX complete any pending mailbox cmd */ 6540 if (IS_QLA82XX(ha)) { 6541 ha->flags.isp82xx_fw_hung = 1; 6542 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6543 qla82xx_clear_pending_mbx(vha); 6544 } 6545 qla2x00_free_irqs(vha); 6546 pci_disable_device(pdev); 6547 /* Return back all IOs */ 6548 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6549 if (ql2xmqsupport || ql2xnvmeenable) { 6550 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6551 qla2xxx_wake_dpc(vha); 6552 } 6553 return PCI_ERS_RESULT_NEED_RESET; 6554 case pci_channel_io_perm_failure: 6555 ha->flags.pci_channel_io_perm_failure = 1; 6556 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6557 if (ql2xmqsupport || ql2xnvmeenable) { 6558 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6559 qla2xxx_wake_dpc(vha); 6560 } 6561 return PCI_ERS_RESULT_DISCONNECT; 6562 } 6563 return PCI_ERS_RESULT_NEED_RESET; 6564 } 6565 6566 static pci_ers_result_t 6567 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6568 { 6569 int risc_paused = 0; 6570 uint32_t stat; 6571 unsigned long flags; 6572 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6573 struct qla_hw_data *ha = base_vha->hw; 6574 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6575 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6576 6577 if (IS_QLA82XX(ha)) 6578 return PCI_ERS_RESULT_RECOVERED; 6579 6580 spin_lock_irqsave(&ha->hardware_lock, flags); 6581 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6582 stat = RD_REG_DWORD(®->hccr); 6583 if (stat & HCCR_RISC_PAUSE) 6584 risc_paused = 1; 6585 } else if (IS_QLA23XX(ha)) { 6586 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6587 if (stat & HSR_RISC_PAUSED) 6588 risc_paused = 1; 6589 } else if (IS_FWI2_CAPABLE(ha)) { 6590 stat = RD_REG_DWORD(®24->host_status); 6591 if (stat & HSRX_RISC_PAUSED) 6592 risc_paused = 1; 6593 } 6594 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6595 6596 if (risc_paused) { 6597 ql_log(ql_log_info, base_vha, 0x9003, 6598 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6599 ha->isp_ops->fw_dump(base_vha, 0); 6600 6601 return PCI_ERS_RESULT_NEED_RESET; 6602 } else 6603 return PCI_ERS_RESULT_RECOVERED; 6604 } 6605 6606 static uint32_t 6607 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6608 { 6609 uint32_t rval = QLA_FUNCTION_FAILED; 6610 uint32_t drv_active = 0; 6611 struct qla_hw_data *ha = base_vha->hw; 6612 int fn; 6613 struct pci_dev *other_pdev = NULL; 6614 6615 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6616 "Entered %s.\n", __func__); 6617 6618 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6619 6620 if (base_vha->flags.online) { 6621 /* Abort all outstanding commands, 6622 * so as to be requeued later */ 6623 qla2x00_abort_isp_cleanup(base_vha); 6624 } 6625 6626 6627 fn = PCI_FUNC(ha->pdev->devfn); 6628 while (fn > 0) { 6629 fn--; 6630 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6631 "Finding pci device at function = 0x%x.\n", fn); 6632 other_pdev = 6633 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6634 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6635 fn)); 6636 6637 if (!other_pdev) 6638 continue; 6639 if (atomic_read(&other_pdev->enable_cnt)) { 6640 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6641 "Found PCI func available and enable at 0x%x.\n", 6642 fn); 6643 pci_dev_put(other_pdev); 6644 break; 6645 } 6646 pci_dev_put(other_pdev); 6647 } 6648 6649 if (!fn) { 6650 /* Reset owner */ 6651 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6652 "This devfn is reset owner = 0x%x.\n", 6653 ha->pdev->devfn); 6654 qla82xx_idc_lock(ha); 6655 6656 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6657 QLA8XXX_DEV_INITIALIZING); 6658 6659 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6660 QLA82XX_IDC_VERSION); 6661 6662 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6663 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6664 "drv_active = 0x%x.\n", drv_active); 6665 6666 qla82xx_idc_unlock(ha); 6667 /* Reset if device is not already reset 6668 * drv_active would be 0 if a reset has already been done 6669 */ 6670 if (drv_active) 6671 rval = qla82xx_start_firmware(base_vha); 6672 else 6673 rval = QLA_SUCCESS; 6674 qla82xx_idc_lock(ha); 6675 6676 if (rval != QLA_SUCCESS) { 6677 ql_log(ql_log_info, base_vha, 0x900b, 6678 "HW State: FAILED.\n"); 6679 qla82xx_clear_drv_active(ha); 6680 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6681 QLA8XXX_DEV_FAILED); 6682 } else { 6683 ql_log(ql_log_info, base_vha, 0x900c, 6684 "HW State: READY.\n"); 6685 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6686 QLA8XXX_DEV_READY); 6687 qla82xx_idc_unlock(ha); 6688 ha->flags.isp82xx_fw_hung = 0; 6689 rval = qla82xx_restart_isp(base_vha); 6690 qla82xx_idc_lock(ha); 6691 /* Clear driver state register */ 6692 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6693 qla82xx_set_drv_active(base_vha); 6694 } 6695 qla82xx_idc_unlock(ha); 6696 } else { 6697 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6698 "This devfn is not reset owner = 0x%x.\n", 6699 ha->pdev->devfn); 6700 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6701 QLA8XXX_DEV_READY)) { 6702 ha->flags.isp82xx_fw_hung = 0; 6703 rval = qla82xx_restart_isp(base_vha); 6704 qla82xx_idc_lock(ha); 6705 qla82xx_set_drv_active(base_vha); 6706 qla82xx_idc_unlock(ha); 6707 } 6708 } 6709 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6710 6711 return rval; 6712 } 6713 6714 static pci_ers_result_t 6715 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6716 { 6717 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6718 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6719 struct qla_hw_data *ha = base_vha->hw; 6720 struct rsp_que *rsp; 6721 int rc, retries = 10; 6722 6723 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6724 "Slot Reset.\n"); 6725 6726 /* Workaround: qla2xxx driver which access hardware earlier 6727 * needs error state to be pci_channel_io_online. 6728 * Otherwise mailbox command timesout. 6729 */ 6730 pdev->error_state = pci_channel_io_normal; 6731 6732 pci_restore_state(pdev); 6733 6734 /* pci_restore_state() clears the saved_state flag of the device 6735 * save restored state which resets saved_state flag 6736 */ 6737 pci_save_state(pdev); 6738 6739 if (ha->mem_only) 6740 rc = pci_enable_device_mem(pdev); 6741 else 6742 rc = pci_enable_device(pdev); 6743 6744 if (rc) { 6745 ql_log(ql_log_warn, base_vha, 0x9005, 6746 "Can't re-enable PCI device after reset.\n"); 6747 goto exit_slot_reset; 6748 } 6749 6750 rsp = ha->rsp_q_map[0]; 6751 if (qla2x00_request_irqs(ha, rsp)) 6752 goto exit_slot_reset; 6753 6754 if (ha->isp_ops->pci_config(base_vha)) 6755 goto exit_slot_reset; 6756 6757 if (IS_QLA82XX(ha)) { 6758 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6759 ret = PCI_ERS_RESULT_RECOVERED; 6760 goto exit_slot_reset; 6761 } else 6762 goto exit_slot_reset; 6763 } 6764 6765 while (ha->flags.mbox_busy && retries--) 6766 msleep(1000); 6767 6768 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6769 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6770 ret = PCI_ERS_RESULT_RECOVERED; 6771 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6772 6773 6774 exit_slot_reset: 6775 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6776 "slot_reset return %x.\n", ret); 6777 6778 return ret; 6779 } 6780 6781 static void 6782 qla2xxx_pci_resume(struct pci_dev *pdev) 6783 { 6784 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6785 struct qla_hw_data *ha = base_vha->hw; 6786 int ret; 6787 6788 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6789 "pci_resume.\n"); 6790 6791 ret = qla2x00_wait_for_hba_online(base_vha); 6792 if (ret != QLA_SUCCESS) { 6793 ql_log(ql_log_fatal, base_vha, 0x9002, 6794 "The device failed to resume I/O from slot/link_reset.\n"); 6795 } 6796 6797 pci_cleanup_aer_uncorrect_error_status(pdev); 6798 6799 ha->flags.eeh_busy = 0; 6800 } 6801 6802 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6803 { 6804 int rc; 6805 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6806 6807 if (USER_CTRL_IRQ(vha->hw)) 6808 rc = blk_mq_map_queues(&shost->tag_set); 6809 else 6810 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6811 return rc; 6812 } 6813 6814 static const struct pci_error_handlers qla2xxx_err_handler = { 6815 .error_detected = qla2xxx_pci_error_detected, 6816 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6817 .slot_reset = qla2xxx_pci_slot_reset, 6818 .resume = qla2xxx_pci_resume, 6819 }; 6820 6821 static struct pci_device_id qla2xxx_pci_tbl[] = { 6822 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6823 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6824 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6825 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6826 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6827 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6828 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6829 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6830 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6831 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6832 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6833 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6834 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6835 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6836 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6837 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6838 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6839 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6840 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6841 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6842 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6843 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6844 { 0 }, 6845 }; 6846 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6847 6848 static struct pci_driver qla2xxx_pci_driver = { 6849 .name = QLA2XXX_DRIVER_NAME, 6850 .driver = { 6851 .owner = THIS_MODULE, 6852 }, 6853 .id_table = qla2xxx_pci_tbl, 6854 .probe = qla2x00_probe_one, 6855 .remove = qla2x00_remove_one, 6856 .shutdown = qla2x00_shutdown, 6857 .err_handler = &qla2xxx_err_handler, 6858 }; 6859 6860 static const struct file_operations apidev_fops = { 6861 .owner = THIS_MODULE, 6862 .llseek = noop_llseek, 6863 }; 6864 6865 /** 6866 * qla2x00_module_init - Module initialization. 6867 **/ 6868 static int __init 6869 qla2x00_module_init(void) 6870 { 6871 int ret = 0; 6872 6873 /* Allocate cache for SRBs. */ 6874 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6875 SLAB_HWCACHE_ALIGN, NULL); 6876 if (srb_cachep == NULL) { 6877 ql_log(ql_log_fatal, NULL, 0x0001, 6878 "Unable to allocate SRB cache...Failing load!.\n"); 6879 return -ENOMEM; 6880 } 6881 6882 /* Initialize target kmem_cache and mem_pools */ 6883 ret = qlt_init(); 6884 if (ret < 0) { 6885 kmem_cache_destroy(srb_cachep); 6886 return ret; 6887 } else if (ret > 0) { 6888 /* 6889 * If initiator mode is explictly disabled by qlt_init(), 6890 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6891 * performing scsi_scan_target() during LOOP UP event. 6892 */ 6893 qla2xxx_transport_functions.disable_target_scan = 1; 6894 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6895 } 6896 6897 /* Derive version string. */ 6898 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6899 if (ql2xextended_error_logging) 6900 strcat(qla2x00_version_str, "-debug"); 6901 if (ql2xextended_error_logging == 1) 6902 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6903 6904 qla2xxx_transport_template = 6905 fc_attach_transport(&qla2xxx_transport_functions); 6906 if (!qla2xxx_transport_template) { 6907 kmem_cache_destroy(srb_cachep); 6908 ql_log(ql_log_fatal, NULL, 0x0002, 6909 "fc_attach_transport failed...Failing load!.\n"); 6910 qlt_exit(); 6911 return -ENODEV; 6912 } 6913 6914 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6915 if (apidev_major < 0) { 6916 ql_log(ql_log_fatal, NULL, 0x0003, 6917 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6918 } 6919 6920 qla2xxx_transport_vport_template = 6921 fc_attach_transport(&qla2xxx_transport_vport_functions); 6922 if (!qla2xxx_transport_vport_template) { 6923 kmem_cache_destroy(srb_cachep); 6924 qlt_exit(); 6925 fc_release_transport(qla2xxx_transport_template); 6926 ql_log(ql_log_fatal, NULL, 0x0004, 6927 "fc_attach_transport vport failed...Failing load!.\n"); 6928 return -ENODEV; 6929 } 6930 ql_log(ql_log_info, NULL, 0x0005, 6931 "QLogic Fibre Channel HBA Driver: %s.\n", 6932 qla2x00_version_str); 6933 ret = pci_register_driver(&qla2xxx_pci_driver); 6934 if (ret) { 6935 kmem_cache_destroy(srb_cachep); 6936 qlt_exit(); 6937 fc_release_transport(qla2xxx_transport_template); 6938 fc_release_transport(qla2xxx_transport_vport_template); 6939 ql_log(ql_log_fatal, NULL, 0x0006, 6940 "pci_register_driver failed...ret=%d Failing load!.\n", 6941 ret); 6942 } 6943 return ret; 6944 } 6945 6946 /** 6947 * qla2x00_module_exit - Module cleanup. 6948 **/ 6949 static void __exit 6950 qla2x00_module_exit(void) 6951 { 6952 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6953 pci_unregister_driver(&qla2xxx_pci_driver); 6954 qla2x00_release_firmware(); 6955 kmem_cache_destroy(srb_cachep); 6956 qlt_exit(); 6957 if (ctx_cachep) 6958 kmem_cache_destroy(ctx_cachep); 6959 fc_release_transport(qla2xxx_transport_template); 6960 fc_release_transport(qla2xxx_transport_vport_template); 6961 } 6962 6963 module_init(qla2x00_module_init); 6964 module_exit(qla2x00_module_exit); 6965 6966 MODULE_AUTHOR("QLogic Corporation"); 6967 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6968 MODULE_LICENSE("GPL"); 6969 MODULE_VERSION(QLA2XXX_VERSION); 6970 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6971 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6972 MODULE_FIRMWARE(FW_FILE_ISP2300); 6973 MODULE_FIRMWARE(FW_FILE_ISP2322); 6974 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6975 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6976