1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 32 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 32."); 122 123 int ql2xenabledif = 2; 124 module_param(ql2xenabledif, int, S_IRUGO); 125 MODULE_PARM_DESC(ql2xenabledif, 126 " Enable T10-CRC-DIF:\n" 127 " Default is 2.\n" 128 " 0 -- No DIF Support\n" 129 " 1 -- Enable DIF for all types\n" 130 " 2 -- Enable DIF for all types, except Type 0.\n"); 131 132 int ql2xenablehba_err_chk = 2; 133 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 134 MODULE_PARM_DESC(ql2xenablehba_err_chk, 135 " Enable T10-CRC-DIF Error isolation by HBA:\n" 136 " Default is 2.\n" 137 " 0 -- Error isolation disabled\n" 138 " 1 -- Error isolation enabled only for DIX Type 0\n" 139 " 2 -- Error isolation enabled for all Types\n"); 140 141 int ql2xiidmaenable=1; 142 module_param(ql2xiidmaenable, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xiidmaenable, 144 "Enables iIDMA settings " 145 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 146 147 int ql2xmqsupport = 1; 148 module_param(ql2xmqsupport, int, S_IRUGO); 149 MODULE_PARM_DESC(ql2xmqsupport, 150 "Enable on demand multiple queue pairs support " 151 "Default is 1 for supported. " 152 "Set it to 0 to turn off mq qpair support."); 153 154 int ql2xfwloadbin; 155 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 156 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 157 MODULE_PARM_DESC(ql2xfwloadbin, 158 "Option to specify location from which to load ISP firmware:.\n" 159 " 2 -- load firmware via the request_firmware() (hotplug).\n" 160 " interface.\n" 161 " 1 -- load firmware from flash.\n" 162 " 0 -- use default semantics.\n"); 163 164 int ql2xetsenable; 165 module_param(ql2xetsenable, int, S_IRUGO); 166 MODULE_PARM_DESC(ql2xetsenable, 167 "Enables firmware ETS burst." 168 "Default is 0 - skip ETS enablement."); 169 170 int ql2xdbwr = 1; 171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xdbwr, 173 "Option to specify scheme for request queue posting.\n" 174 " 0 -- Regular doorbell.\n" 175 " 1 -- CAMRAM doorbell (faster).\n"); 176 177 int ql2xtargetreset = 1; 178 module_param(ql2xtargetreset, int, S_IRUGO); 179 MODULE_PARM_DESC(ql2xtargetreset, 180 "Enable target reset." 181 "Default is 1 - use hw defaults."); 182 183 int ql2xgffidenable; 184 module_param(ql2xgffidenable, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xgffidenable, 186 "Enables GFF_ID checks of port type. " 187 "Default is 0 - Do not use GFF_ID information."); 188 189 int ql2xasynctmfenable; 190 module_param(ql2xasynctmfenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xasynctmfenable, 192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 193 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 194 195 int ql2xdontresethba; 196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 197 MODULE_PARM_DESC(ql2xdontresethba, 198 "Option to specify reset behaviour.\n" 199 " 0 (Default) -- Reset on failure.\n" 200 " 1 -- Do not reset on failure.\n"); 201 202 uint64_t ql2xmaxlun = MAX_LUNS; 203 module_param(ql2xmaxlun, ullong, S_IRUGO); 204 MODULE_PARM_DESC(ql2xmaxlun, 205 "Defines the maximum LU number to register with the SCSI " 206 "midlayer. Default is 65535."); 207 208 int ql2xmdcapmask = 0x1F; 209 module_param(ql2xmdcapmask, int, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmdcapmask, 211 "Set the Minidump driver capture mask level. " 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 213 214 int ql2xmdenable = 1; 215 module_param(ql2xmdenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdenable, 217 "Enable/disable MiniDump. " 218 "0 - MiniDump disabled. " 219 "1 (Default) - MiniDump enabled."); 220 221 int ql2xexlogins = 0; 222 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 223 MODULE_PARM_DESC(ql2xexlogins, 224 "Number of extended Logins. " 225 "0 (Default)- Disabled."); 226 227 int ql2xexchoffld = 0; 228 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xexchoffld, 230 "Number of exchanges to offload. " 231 "0 (Default)- Disabled."); 232 233 int ql2xfwholdabts = 0; 234 module_param(ql2xfwholdabts, int, S_IRUGO); 235 MODULE_PARM_DESC(ql2xfwholdabts, 236 "Allow FW to hold status IOCB until ABTS rsp received. " 237 "0 (Default) Do not set fw option. " 238 "1 - Set fw option to hold ABTS."); 239 240 /* 241 * SCSI host template entry points 242 */ 243 static int qla2xxx_slave_configure(struct scsi_device * device); 244 static int qla2xxx_slave_alloc(struct scsi_device *); 245 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 246 static void qla2xxx_scan_start(struct Scsi_Host *); 247 static void qla2xxx_slave_destroy(struct scsi_device *); 248 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 249 static int qla2xxx_eh_abort(struct scsi_cmnd *); 250 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 251 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 252 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 253 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 254 255 static void qla2x00_clear_drv_active(struct qla_hw_data *); 256 static void qla2x00_free_device(scsi_qla_host_t *); 257 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 258 static int qla2xxx_map_queues(struct Scsi_Host *shost); 259 260 struct scsi_host_template qla2xxx_driver_template = { 261 .module = THIS_MODULE, 262 .name = QLA2XXX_DRIVER_NAME, 263 .queuecommand = qla2xxx_queuecommand, 264 265 .eh_timed_out = fc_eh_timed_out, 266 .eh_abort_handler = qla2xxx_eh_abort, 267 .eh_device_reset_handler = qla2xxx_eh_device_reset, 268 .eh_target_reset_handler = qla2xxx_eh_target_reset, 269 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 270 .eh_host_reset_handler = qla2xxx_eh_host_reset, 271 272 .slave_configure = qla2xxx_slave_configure, 273 274 .slave_alloc = qla2xxx_slave_alloc, 275 .slave_destroy = qla2xxx_slave_destroy, 276 .scan_finished = qla2xxx_scan_finished, 277 .scan_start = qla2xxx_scan_start, 278 .change_queue_depth = scsi_change_queue_depth, 279 .map_queues = qla2xxx_map_queues, 280 .this_id = -1, 281 .cmd_per_lun = 3, 282 .use_clustering = ENABLE_CLUSTERING, 283 .sg_tablesize = SG_ALL, 284 285 .max_sectors = 0xFFFF, 286 .shost_attrs = qla2x00_host_attrs, 287 288 .supported_mode = MODE_INITIATOR, 289 .track_queue_depth = 1, 290 }; 291 292 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 293 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 294 295 /* TODO Convert to inlines 296 * 297 * Timer routines 298 */ 299 300 __inline__ void 301 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 302 { 303 init_timer(&vha->timer); 304 vha->timer.expires = jiffies + interval * HZ; 305 vha->timer.data = (unsigned long)vha; 306 vha->timer.function = (void (*)(unsigned long))func; 307 add_timer(&vha->timer); 308 vha->timer_active = 1; 309 } 310 311 static inline void 312 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 313 { 314 /* Currently used for 82XX only. */ 315 if (vha->device_flags & DFLG_DEV_FAILED) { 316 ql_dbg(ql_dbg_timer, vha, 0x600d, 317 "Device in a failed state, returning.\n"); 318 return; 319 } 320 321 mod_timer(&vha->timer, jiffies + interval * HZ); 322 } 323 324 static __inline__ void 325 qla2x00_stop_timer(scsi_qla_host_t *vha) 326 { 327 del_timer_sync(&vha->timer); 328 vha->timer_active = 0; 329 } 330 331 static int qla2x00_do_dpc(void *data); 332 333 static void qla2x00_rst_aen(scsi_qla_host_t *); 334 335 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 336 struct req_que **, struct rsp_que **); 337 static void qla2x00_free_fw_dump(struct qla_hw_data *); 338 static void qla2x00_mem_free(struct qla_hw_data *); 339 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 340 struct qla_qpair *qpair); 341 342 /* -------------------------------------------------------------------------- */ 343 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 344 struct rsp_que *rsp) 345 { 346 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 347 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 348 GFP_KERNEL); 349 if (!ha->req_q_map) { 350 ql_log(ql_log_fatal, vha, 0x003b, 351 "Unable to allocate memory for request queue ptrs.\n"); 352 goto fail_req_map; 353 } 354 355 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 356 GFP_KERNEL); 357 if (!ha->rsp_q_map) { 358 ql_log(ql_log_fatal, vha, 0x003c, 359 "Unable to allocate memory for response queue ptrs.\n"); 360 goto fail_rsp_map; 361 } 362 363 if (ql2xmqsupport && ha->max_qpairs) { 364 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 365 GFP_KERNEL); 366 if (!ha->queue_pair_map) { 367 ql_log(ql_log_fatal, vha, 0x0180, 368 "Unable to allocate memory for queue pair ptrs.\n"); 369 goto fail_qpair_map; 370 } 371 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 372 if (ha->base_qpair == NULL) { 373 ql_log(ql_log_warn, vha, 0x0182, 374 "Failed to allocate base queue pair memory.\n"); 375 goto fail_base_qpair; 376 } 377 ha->base_qpair->req = req; 378 ha->base_qpair->rsp = rsp; 379 } 380 381 /* 382 * Make sure we record at least the request and response queue zero in 383 * case we need to free them if part of the probe fails. 384 */ 385 ha->rsp_q_map[0] = rsp; 386 ha->req_q_map[0] = req; 387 set_bit(0, ha->rsp_qid_map); 388 set_bit(0, ha->req_qid_map); 389 return 1; 390 391 fail_base_qpair: 392 kfree(ha->queue_pair_map); 393 fail_qpair_map: 394 kfree(ha->rsp_q_map); 395 ha->rsp_q_map = NULL; 396 fail_rsp_map: 397 kfree(ha->req_q_map); 398 ha->req_q_map = NULL; 399 fail_req_map: 400 return -ENOMEM; 401 } 402 403 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 404 { 405 if (IS_QLAFX00(ha)) { 406 if (req && req->ring_fx00) 407 dma_free_coherent(&ha->pdev->dev, 408 (req->length_fx00 + 1) * sizeof(request_t), 409 req->ring_fx00, req->dma_fx00); 410 } else if (req && req->ring) 411 dma_free_coherent(&ha->pdev->dev, 412 (req->length + 1) * sizeof(request_t), 413 req->ring, req->dma); 414 415 if (req) 416 kfree(req->outstanding_cmds); 417 418 kfree(req); 419 req = NULL; 420 } 421 422 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 423 { 424 if (IS_QLAFX00(ha)) { 425 if (rsp && rsp->ring) 426 dma_free_coherent(&ha->pdev->dev, 427 (rsp->length_fx00 + 1) * sizeof(request_t), 428 rsp->ring_fx00, rsp->dma_fx00); 429 } else if (rsp && rsp->ring) { 430 dma_free_coherent(&ha->pdev->dev, 431 (rsp->length + 1) * sizeof(response_t), 432 rsp->ring, rsp->dma); 433 } 434 kfree(rsp); 435 rsp = NULL; 436 } 437 438 static void qla2x00_free_queues(struct qla_hw_data *ha) 439 { 440 struct req_que *req; 441 struct rsp_que *rsp; 442 int cnt; 443 unsigned long flags; 444 445 spin_lock_irqsave(&ha->hardware_lock, flags); 446 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 447 if (!test_bit(cnt, ha->req_qid_map)) 448 continue; 449 450 req = ha->req_q_map[cnt]; 451 clear_bit(cnt, ha->req_qid_map); 452 ha->req_q_map[cnt] = NULL; 453 454 spin_unlock_irqrestore(&ha->hardware_lock, flags); 455 qla2x00_free_req_que(ha, req); 456 spin_lock_irqsave(&ha->hardware_lock, flags); 457 } 458 spin_unlock_irqrestore(&ha->hardware_lock, flags); 459 460 kfree(ha->req_q_map); 461 ha->req_q_map = NULL; 462 463 464 spin_lock_irqsave(&ha->hardware_lock, flags); 465 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 466 if (!test_bit(cnt, ha->rsp_qid_map)) 467 continue; 468 469 rsp = ha->rsp_q_map[cnt]; 470 clear_bit(cnt, ha->rsp_qid_map); 471 ha->rsp_q_map[cnt] = NULL; 472 spin_unlock_irqrestore(&ha->hardware_lock, flags); 473 qla2x00_free_rsp_que(ha, rsp); 474 spin_lock_irqsave(&ha->hardware_lock, flags); 475 } 476 spin_unlock_irqrestore(&ha->hardware_lock, flags); 477 478 kfree(ha->rsp_q_map); 479 ha->rsp_q_map = NULL; 480 } 481 482 static char * 483 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 484 { 485 struct qla_hw_data *ha = vha->hw; 486 static char *pci_bus_modes[] = { 487 "33", "66", "100", "133", 488 }; 489 uint16_t pci_bus; 490 491 strcpy(str, "PCI"); 492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 493 if (pci_bus) { 494 strcat(str, "-X ("); 495 strcat(str, pci_bus_modes[pci_bus]); 496 } else { 497 pci_bus = (ha->pci_attr & BIT_8) >> 8; 498 strcat(str, " ("); 499 strcat(str, pci_bus_modes[pci_bus]); 500 } 501 strcat(str, " MHz)"); 502 503 return (str); 504 } 505 506 static char * 507 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 508 { 509 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 510 struct qla_hw_data *ha = vha->hw; 511 uint32_t pci_bus; 512 513 if (pci_is_pcie(ha->pdev)) { 514 char lwstr[6]; 515 uint32_t lstat, lspeed, lwidth; 516 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 518 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 520 521 strcpy(str, "PCIe ("); 522 switch (lspeed) { 523 case 1: 524 strcat(str, "2.5GT/s "); 525 break; 526 case 2: 527 strcat(str, "5.0GT/s "); 528 break; 529 case 3: 530 strcat(str, "8.0GT/s "); 531 break; 532 default: 533 strcat(str, "<unknown> "); 534 break; 535 } 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 537 strcat(str, lwstr); 538 539 return str; 540 } 541 542 strcpy(str, "PCI"); 543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 544 if (pci_bus == 0 || pci_bus == 8) { 545 strcat(str, " ("); 546 strcat(str, pci_bus_modes[pci_bus >> 3]); 547 } else { 548 strcat(str, "-X "); 549 if (pci_bus & BIT_2) 550 strcat(str, "Mode 2"); 551 else 552 strcat(str, "Mode 1"); 553 strcat(str, " ("); 554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 555 } 556 strcat(str, " MHz)"); 557 558 return str; 559 } 560 561 static char * 562 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 563 { 564 char un_str[10]; 565 struct qla_hw_data *ha = vha->hw; 566 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 568 ha->fw_minor_version, ha->fw_subminor_version); 569 570 if (ha->fw_attributes & BIT_9) { 571 strcat(str, "FLX"); 572 return (str); 573 } 574 575 switch (ha->fw_attributes & 0xFF) { 576 case 0x7: 577 strcat(str, "EF"); 578 break; 579 case 0x17: 580 strcat(str, "TP"); 581 break; 582 case 0x37: 583 strcat(str, "IP"); 584 break; 585 case 0x77: 586 strcat(str, "VI"); 587 break; 588 default: 589 sprintf(un_str, "(%x)", ha->fw_attributes); 590 strcat(str, un_str); 591 break; 592 } 593 if (ha->fw_attributes & 0x100) 594 strcat(str, "X"); 595 596 return (str); 597 } 598 599 static char * 600 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 606 return str; 607 } 608 609 void 610 qla2x00_sp_free_dma(void *vha, void *ptr) 611 { 612 srb_t *sp = (srb_t *)ptr; 613 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 614 struct qla_hw_data *ha = sp->fcport->vha->hw; 615 void *ctx = GET_CMD_CTX_SP(sp); 616 617 if (sp->flags & SRB_DMA_VALID) { 618 scsi_dma_unmap(cmd); 619 sp->flags &= ~SRB_DMA_VALID; 620 } 621 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 624 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 626 } 627 628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 629 /* List assured to be having elements */ 630 qla2x00_clean_dsd_pool(ha, sp, NULL); 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 632 } 633 634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 635 dma_pool_free(ha->dl_dma_pool, ctx, 636 ((struct crc_context *)ctx)->crc_ctx_dma); 637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 638 } 639 640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 642 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 644 ctx1->fcp_cmnd_dma); 645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 648 mempool_free(ctx1, ha->ctx_mempool); 649 ctx1 = NULL; 650 } 651 652 CMD_SP(cmd) = NULL; 653 qla2x00_rel_sp(sp->fcport->vha, sp); 654 } 655 656 void 657 qla2x00_sp_compl(void *data, void *ptr, int res) 658 { 659 struct qla_hw_data *ha = (struct qla_hw_data *)data; 660 srb_t *sp = (srb_t *)ptr; 661 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 662 663 cmd->result = res; 664 665 if (atomic_read(&sp->ref_count) == 0) { 666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 668 sp, GET_CMD_SP(sp)); 669 if (ql2xextended_error_logging & ql_dbg_io) 670 WARN_ON(atomic_read(&sp->ref_count) == 0); 671 return; 672 } 673 if (!atomic_dec_and_test(&sp->ref_count)) 674 return; 675 676 qla2x00_sp_free_dma(ha, sp); 677 cmd->scsi_done(cmd); 678 } 679 680 void 681 qla2xxx_qpair_sp_free_dma(void *vha, void *ptr) 682 { 683 srb_t *sp = (srb_t *)ptr; 684 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 685 struct qla_hw_data *ha = sp->fcport->vha->hw; 686 void *ctx = GET_CMD_CTX_SP(sp); 687 688 if (sp->flags & SRB_DMA_VALID) { 689 scsi_dma_unmap(cmd); 690 sp->flags &= ~SRB_DMA_VALID; 691 } 692 693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 695 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 697 } 698 699 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 700 /* List assured to be having elements */ 701 qla2x00_clean_dsd_pool(ha, sp, NULL); 702 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 703 } 704 705 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 706 dma_pool_free(ha->dl_dma_pool, ctx, 707 ((struct crc_context *)ctx)->crc_ctx_dma); 708 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 709 } 710 711 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 712 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 713 714 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 715 ctx1->fcp_cmnd_dma); 716 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 717 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 718 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 719 mempool_free(ctx1, ha->ctx_mempool); 720 } 721 722 CMD_SP(cmd) = NULL; 723 qla2xxx_rel_qpair_sp(sp->qpair, sp); 724 } 725 726 void 727 qla2xxx_qpair_sp_compl(void *data, void *ptr, int res) 728 { 729 srb_t *sp = (srb_t *)ptr; 730 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 731 732 cmd->result = res; 733 734 if (atomic_read(&sp->ref_count) == 0) { 735 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 737 sp, GET_CMD_SP(sp)); 738 if (ql2xextended_error_logging & ql_dbg_io) 739 WARN_ON(atomic_read(&sp->ref_count) == 0); 740 return; 741 } 742 if (!atomic_dec_and_test(&sp->ref_count)) 743 return; 744 745 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp); 746 cmd->scsi_done(cmd); 747 } 748 749 /* If we are SP1 here, we need to still take and release the host_lock as SP1 750 * does not have the changes necessary to avoid taking host->host_lock. 751 */ 752 static int 753 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 754 { 755 scsi_qla_host_t *vha = shost_priv(host); 756 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 757 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 758 struct qla_hw_data *ha = vha->hw; 759 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 760 srb_t *sp; 761 int rval; 762 struct qla_qpair *qpair = NULL; 763 uint32_t tag; 764 uint16_t hwq; 765 766 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 767 cmd->result = DID_NO_CONNECT << 16; 768 goto qc24_fail_command; 769 } 770 771 if (ha->mqenable) { 772 if (shost_use_blk_mq(vha->host)) { 773 tag = blk_mq_unique_tag(cmd->request); 774 hwq = blk_mq_unique_tag_to_hwq(tag); 775 qpair = ha->queue_pair_map[hwq]; 776 } else if (vha->vp_idx && vha->qpair) { 777 qpair = vha->qpair; 778 } 779 780 if (qpair) 781 return qla2xxx_mqueuecommand(host, cmd, qpair); 782 } 783 784 if (ha->flags.eeh_busy) { 785 if (ha->flags.pci_channel_io_perm_failure) { 786 ql_dbg(ql_dbg_aer, vha, 0x9010, 787 "PCI Channel IO permanent failure, exiting " 788 "cmd=%p.\n", cmd); 789 cmd->result = DID_NO_CONNECT << 16; 790 } else { 791 ql_dbg(ql_dbg_aer, vha, 0x9011, 792 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 793 cmd->result = DID_REQUEUE << 16; 794 } 795 goto qc24_fail_command; 796 } 797 798 rval = fc_remote_port_chkready(rport); 799 if (rval) { 800 cmd->result = rval; 801 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 802 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 803 cmd, rval); 804 goto qc24_fail_command; 805 } 806 807 if (!vha->flags.difdix_supported && 808 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 809 ql_dbg(ql_dbg_io, vha, 0x3004, 810 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 811 cmd); 812 cmd->result = DID_NO_CONNECT << 16; 813 goto qc24_fail_command; 814 } 815 816 if (!fcport) { 817 cmd->result = DID_NO_CONNECT << 16; 818 goto qc24_fail_command; 819 } 820 821 if (atomic_read(&fcport->state) != FCS_ONLINE) { 822 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 823 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 824 ql_dbg(ql_dbg_io, vha, 0x3005, 825 "Returning DNC, fcport_state=%d loop_state=%d.\n", 826 atomic_read(&fcport->state), 827 atomic_read(&base_vha->loop_state)); 828 cmd->result = DID_NO_CONNECT << 16; 829 goto qc24_fail_command; 830 } 831 goto qc24_target_busy; 832 } 833 834 /* 835 * Return target busy if we've received a non-zero retry_delay_timer 836 * in a FCP_RSP. 837 */ 838 if (fcport->retry_delay_timestamp == 0) { 839 /* retry delay not set */ 840 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 841 fcport->retry_delay_timestamp = 0; 842 else 843 goto qc24_target_busy; 844 845 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 846 if (!sp) 847 goto qc24_host_busy; 848 849 sp->u.scmd.cmd = cmd; 850 sp->type = SRB_SCSI_CMD; 851 atomic_set(&sp->ref_count, 1); 852 CMD_SP(cmd) = (void *)sp; 853 sp->free = qla2x00_sp_free_dma; 854 sp->done = qla2x00_sp_compl; 855 856 rval = ha->isp_ops->start_scsi(sp); 857 if (rval != QLA_SUCCESS) { 858 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 859 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 860 goto qc24_host_busy_free_sp; 861 } 862 863 return 0; 864 865 qc24_host_busy_free_sp: 866 qla2x00_sp_free_dma(ha, sp); 867 868 qc24_host_busy: 869 return SCSI_MLQUEUE_HOST_BUSY; 870 871 qc24_target_busy: 872 return SCSI_MLQUEUE_TARGET_BUSY; 873 874 qc24_fail_command: 875 cmd->scsi_done(cmd); 876 877 return 0; 878 } 879 880 /* For MQ supported I/O */ 881 int 882 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 883 struct qla_qpair *qpair) 884 { 885 scsi_qla_host_t *vha = shost_priv(host); 886 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 887 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 888 struct qla_hw_data *ha = vha->hw; 889 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 890 srb_t *sp; 891 int rval; 892 893 rval = fc_remote_port_chkready(rport); 894 if (rval) { 895 cmd->result = rval; 896 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 897 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 898 cmd, rval); 899 goto qc24_fail_command; 900 } 901 902 if (!fcport) { 903 cmd->result = DID_NO_CONNECT << 16; 904 goto qc24_fail_command; 905 } 906 907 if (atomic_read(&fcport->state) != FCS_ONLINE) { 908 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 909 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 910 ql_dbg(ql_dbg_io, vha, 0x3077, 911 "Returning DNC, fcport_state=%d loop_state=%d.\n", 912 atomic_read(&fcport->state), 913 atomic_read(&base_vha->loop_state)); 914 cmd->result = DID_NO_CONNECT << 16; 915 goto qc24_fail_command; 916 } 917 goto qc24_target_busy; 918 } 919 920 /* 921 * Return target busy if we've received a non-zero retry_delay_timer 922 * in a FCP_RSP. 923 */ 924 if (fcport->retry_delay_timestamp == 0) { 925 /* retry delay not set */ 926 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 927 fcport->retry_delay_timestamp = 0; 928 else 929 goto qc24_target_busy; 930 931 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 932 if (!sp) 933 goto qc24_host_busy; 934 935 sp->u.scmd.cmd = cmd; 936 sp->type = SRB_SCSI_CMD; 937 atomic_set(&sp->ref_count, 1); 938 CMD_SP(cmd) = (void *)sp; 939 sp->free = qla2xxx_qpair_sp_free_dma; 940 sp->done = qla2xxx_qpair_sp_compl; 941 sp->qpair = qpair; 942 943 rval = ha->isp_ops->start_scsi_mq(sp); 944 if (rval != QLA_SUCCESS) { 945 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 946 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 947 if (rval == QLA_INTERFACE_ERROR) 948 goto qc24_fail_command; 949 goto qc24_host_busy_free_sp; 950 } 951 952 return 0; 953 954 qc24_host_busy_free_sp: 955 qla2xxx_qpair_sp_free_dma(vha, sp); 956 957 qc24_host_busy: 958 return SCSI_MLQUEUE_HOST_BUSY; 959 960 qc24_target_busy: 961 return SCSI_MLQUEUE_TARGET_BUSY; 962 963 qc24_fail_command: 964 cmd->scsi_done(cmd); 965 966 return 0; 967 } 968 969 /* 970 * qla2x00_eh_wait_on_command 971 * Waits for the command to be returned by the Firmware for some 972 * max time. 973 * 974 * Input: 975 * cmd = Scsi Command to wait on. 976 * 977 * Return: 978 * Not Found : 0 979 * Found : 1 980 */ 981 static int 982 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 983 { 984 #define ABORT_POLLING_PERIOD 1000 985 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 986 unsigned long wait_iter = ABORT_WAIT_ITER; 987 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 988 struct qla_hw_data *ha = vha->hw; 989 int ret = QLA_SUCCESS; 990 991 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 992 ql_dbg(ql_dbg_taskm, vha, 0x8005, 993 "Return:eh_wait.\n"); 994 return ret; 995 } 996 997 while (CMD_SP(cmd) && wait_iter--) { 998 msleep(ABORT_POLLING_PERIOD); 999 } 1000 if (CMD_SP(cmd)) 1001 ret = QLA_FUNCTION_FAILED; 1002 1003 return ret; 1004 } 1005 1006 /* 1007 * qla2x00_wait_for_hba_online 1008 * Wait till the HBA is online after going through 1009 * <= MAX_RETRIES_OF_ISP_ABORT or 1010 * finally HBA is disabled ie marked offline 1011 * 1012 * Input: 1013 * ha - pointer to host adapter structure 1014 * 1015 * Note: 1016 * Does context switching-Release SPIN_LOCK 1017 * (if any) before calling this routine. 1018 * 1019 * Return: 1020 * Success (Adapter is online) : 0 1021 * Failed (Adapter is offline/disabled) : 1 1022 */ 1023 int 1024 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1025 { 1026 int return_status; 1027 unsigned long wait_online; 1028 struct qla_hw_data *ha = vha->hw; 1029 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1030 1031 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1032 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1033 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1034 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1035 ha->dpc_active) && time_before(jiffies, wait_online)) { 1036 1037 msleep(1000); 1038 } 1039 if (base_vha->flags.online) 1040 return_status = QLA_SUCCESS; 1041 else 1042 return_status = QLA_FUNCTION_FAILED; 1043 1044 return (return_status); 1045 } 1046 1047 /* 1048 * qla2x00_wait_for_hba_ready 1049 * Wait till the HBA is ready before doing driver unload 1050 * 1051 * Input: 1052 * ha - pointer to host adapter structure 1053 * 1054 * Note: 1055 * Does context switching-Release SPIN_LOCK 1056 * (if any) before calling this routine. 1057 * 1058 */ 1059 static void 1060 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1061 { 1062 struct qla_hw_data *ha = vha->hw; 1063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1064 1065 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1066 ha->flags.mbox_busy) || 1067 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1068 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1069 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1070 break; 1071 msleep(1000); 1072 } 1073 } 1074 1075 int 1076 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1077 { 1078 int return_status; 1079 unsigned long wait_reset; 1080 struct qla_hw_data *ha = vha->hw; 1081 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1082 1083 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1084 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1085 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1086 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1087 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1088 1089 msleep(1000); 1090 1091 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1092 ha->flags.chip_reset_done) 1093 break; 1094 } 1095 if (ha->flags.chip_reset_done) 1096 return_status = QLA_SUCCESS; 1097 else 1098 return_status = QLA_FUNCTION_FAILED; 1099 1100 return return_status; 1101 } 1102 1103 static void 1104 sp_get(struct srb *sp) 1105 { 1106 atomic_inc(&sp->ref_count); 1107 } 1108 1109 #define ISP_REG_DISCONNECT 0xffffffffU 1110 /************************************************************************** 1111 * qla2x00_isp_reg_stat 1112 * 1113 * Description: 1114 * Read the host status register of ISP before aborting the command. 1115 * 1116 * Input: 1117 * ha = pointer to host adapter structure. 1118 * 1119 * 1120 * Returns: 1121 * Either true or false. 1122 * 1123 * Note: Return true if there is register disconnect. 1124 **************************************************************************/ 1125 static inline 1126 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1127 { 1128 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1129 1130 return ((RD_REG_DWORD(®->host_status)) == ISP_REG_DISCONNECT); 1131 } 1132 1133 /************************************************************************** 1134 * qla2xxx_eh_abort 1135 * 1136 * Description: 1137 * The abort function will abort the specified command. 1138 * 1139 * Input: 1140 * cmd = Linux SCSI command packet to be aborted. 1141 * 1142 * Returns: 1143 * Either SUCCESS or FAILED. 1144 * 1145 * Note: 1146 * Only return FAILED if command not returned by firmware. 1147 **************************************************************************/ 1148 static int 1149 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1150 { 1151 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1152 srb_t *sp; 1153 int ret; 1154 unsigned int id; 1155 uint64_t lun; 1156 unsigned long flags; 1157 int rval, wait = 0; 1158 struct qla_hw_data *ha = vha->hw; 1159 1160 if (qla2x00_isp_reg_stat(ha)) { 1161 ql_log(ql_log_info, vha, 0x8042, 1162 "PCI/Register disconnect, exiting.\n"); 1163 return FAILED; 1164 } 1165 if (!CMD_SP(cmd)) 1166 return SUCCESS; 1167 1168 ret = fc_block_scsi_eh(cmd); 1169 if (ret != 0) 1170 return ret; 1171 ret = SUCCESS; 1172 1173 id = cmd->device->id; 1174 lun = cmd->device->lun; 1175 1176 spin_lock_irqsave(&ha->hardware_lock, flags); 1177 sp = (srb_t *) CMD_SP(cmd); 1178 if (!sp) { 1179 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1180 return SUCCESS; 1181 } 1182 1183 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1184 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1185 vha->host_no, id, lun, sp, cmd, sp->handle); 1186 1187 /* Get a reference to the sp and drop the lock.*/ 1188 sp_get(sp); 1189 1190 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1191 rval = ha->isp_ops->abort_command(sp); 1192 if (rval) { 1193 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1194 ret = SUCCESS; 1195 else 1196 ret = FAILED; 1197 1198 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1199 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1200 } else { 1201 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1202 "Abort command mbx success cmd=%p.\n", cmd); 1203 wait = 1; 1204 } 1205 1206 spin_lock_irqsave(&ha->hardware_lock, flags); 1207 sp->done(ha, sp, 0); 1208 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1209 1210 /* Did the command return during mailbox execution? */ 1211 if (ret == FAILED && !CMD_SP(cmd)) 1212 ret = SUCCESS; 1213 1214 /* Wait for the command to be returned. */ 1215 if (wait) { 1216 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1217 ql_log(ql_log_warn, vha, 0x8006, 1218 "Abort handler timed out cmd=%p.\n", cmd); 1219 ret = FAILED; 1220 } 1221 } 1222 1223 ql_log(ql_log_info, vha, 0x801c, 1224 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1225 vha->host_no, id, lun, wait, ret); 1226 1227 return ret; 1228 } 1229 1230 int 1231 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1232 uint64_t l, enum nexus_wait_type type) 1233 { 1234 int cnt, match, status; 1235 unsigned long flags; 1236 struct qla_hw_data *ha = vha->hw; 1237 struct req_que *req; 1238 srb_t *sp; 1239 struct scsi_cmnd *cmd; 1240 1241 status = QLA_SUCCESS; 1242 1243 spin_lock_irqsave(&ha->hardware_lock, flags); 1244 req = vha->req; 1245 for (cnt = 1; status == QLA_SUCCESS && 1246 cnt < req->num_outstanding_cmds; cnt++) { 1247 sp = req->outstanding_cmds[cnt]; 1248 if (!sp) 1249 continue; 1250 if (sp->type != SRB_SCSI_CMD) 1251 continue; 1252 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1253 continue; 1254 match = 0; 1255 cmd = GET_CMD_SP(sp); 1256 switch (type) { 1257 case WAIT_HOST: 1258 match = 1; 1259 break; 1260 case WAIT_TARGET: 1261 match = cmd->device->id == t; 1262 break; 1263 case WAIT_LUN: 1264 match = (cmd->device->id == t && 1265 cmd->device->lun == l); 1266 break; 1267 } 1268 if (!match) 1269 continue; 1270 1271 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1272 status = qla2x00_eh_wait_on_command(cmd); 1273 spin_lock_irqsave(&ha->hardware_lock, flags); 1274 } 1275 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1276 1277 return status; 1278 } 1279 1280 static char *reset_errors[] = { 1281 "HBA not online", 1282 "HBA not ready", 1283 "Task management failed", 1284 "Waiting for command completions", 1285 }; 1286 1287 static int 1288 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1289 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1290 { 1291 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1292 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1293 int err; 1294 1295 if (!fcport) { 1296 return FAILED; 1297 } 1298 1299 err = fc_block_scsi_eh(cmd); 1300 if (err != 0) 1301 return err; 1302 1303 ql_log(ql_log_info, vha, 0x8009, 1304 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1305 cmd->device->id, cmd->device->lun, cmd); 1306 1307 err = 0; 1308 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1309 ql_log(ql_log_warn, vha, 0x800a, 1310 "Wait for hba online failed for cmd=%p.\n", cmd); 1311 goto eh_reset_failed; 1312 } 1313 err = 2; 1314 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1315 != QLA_SUCCESS) { 1316 ql_log(ql_log_warn, vha, 0x800c, 1317 "do_reset failed for cmd=%p.\n", cmd); 1318 goto eh_reset_failed; 1319 } 1320 err = 3; 1321 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1322 cmd->device->lun, type) != QLA_SUCCESS) { 1323 ql_log(ql_log_warn, vha, 0x800d, 1324 "wait for pending cmds failed for cmd=%p.\n", cmd); 1325 goto eh_reset_failed; 1326 } 1327 1328 ql_log(ql_log_info, vha, 0x800e, 1329 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1330 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1331 1332 return SUCCESS; 1333 1334 eh_reset_failed: 1335 ql_log(ql_log_info, vha, 0x800f, 1336 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1337 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1338 cmd); 1339 return FAILED; 1340 } 1341 1342 static int 1343 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1344 { 1345 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1346 struct qla_hw_data *ha = vha->hw; 1347 1348 if (qla2x00_isp_reg_stat(ha)) { 1349 ql_log(ql_log_info, vha, 0x803e, 1350 "PCI/Register disconnect, exiting.\n"); 1351 return FAILED; 1352 } 1353 1354 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1355 ha->isp_ops->lun_reset); 1356 } 1357 1358 static int 1359 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1360 { 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1362 struct qla_hw_data *ha = vha->hw; 1363 1364 if (qla2x00_isp_reg_stat(ha)) { 1365 ql_log(ql_log_info, vha, 0x803f, 1366 "PCI/Register disconnect, exiting.\n"); 1367 return FAILED; 1368 } 1369 1370 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1371 ha->isp_ops->target_reset); 1372 } 1373 1374 /************************************************************************** 1375 * qla2xxx_eh_bus_reset 1376 * 1377 * Description: 1378 * The bus reset function will reset the bus and abort any executing 1379 * commands. 1380 * 1381 * Input: 1382 * cmd = Linux SCSI command packet of the command that cause the 1383 * bus reset. 1384 * 1385 * Returns: 1386 * SUCCESS/FAILURE (defined as macro in scsi.h). 1387 * 1388 **************************************************************************/ 1389 static int 1390 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1391 { 1392 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1393 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1394 int ret = FAILED; 1395 unsigned int id; 1396 uint64_t lun; 1397 struct qla_hw_data *ha = vha->hw; 1398 1399 if (qla2x00_isp_reg_stat(ha)) { 1400 ql_log(ql_log_info, vha, 0x8040, 1401 "PCI/Register disconnect, exiting.\n"); 1402 return FAILED; 1403 } 1404 1405 id = cmd->device->id; 1406 lun = cmd->device->lun; 1407 1408 if (!fcport) { 1409 return ret; 1410 } 1411 1412 ret = fc_block_scsi_eh(cmd); 1413 if (ret != 0) 1414 return ret; 1415 ret = FAILED; 1416 1417 ql_log(ql_log_info, vha, 0x8012, 1418 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1419 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1421 ql_log(ql_log_fatal, vha, 0x8013, 1422 "Wait for hba online failed board disabled.\n"); 1423 goto eh_bus_reset_done; 1424 } 1425 1426 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1427 ret = SUCCESS; 1428 1429 if (ret == FAILED) 1430 goto eh_bus_reset_done; 1431 1432 /* Flush outstanding commands. */ 1433 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1434 QLA_SUCCESS) { 1435 ql_log(ql_log_warn, vha, 0x8014, 1436 "Wait for pending commands failed.\n"); 1437 ret = FAILED; 1438 } 1439 1440 eh_bus_reset_done: 1441 ql_log(ql_log_warn, vha, 0x802b, 1442 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1443 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1444 1445 return ret; 1446 } 1447 1448 /************************************************************************** 1449 * qla2xxx_eh_host_reset 1450 * 1451 * Description: 1452 * The reset function will reset the Adapter. 1453 * 1454 * Input: 1455 * cmd = Linux SCSI command packet of the command that cause the 1456 * adapter reset. 1457 * 1458 * Returns: 1459 * Either SUCCESS or FAILED. 1460 * 1461 * Note: 1462 **************************************************************************/ 1463 static int 1464 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1465 { 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1467 struct qla_hw_data *ha = vha->hw; 1468 int ret = FAILED; 1469 unsigned int id; 1470 uint64_t lun; 1471 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1472 1473 if (qla2x00_isp_reg_stat(ha)) { 1474 ql_log(ql_log_info, vha, 0x8041, 1475 "PCI/Register disconnect, exiting.\n"); 1476 schedule_work(&ha->board_disable); 1477 return SUCCESS; 1478 } 1479 1480 id = cmd->device->id; 1481 lun = cmd->device->lun; 1482 1483 ql_log(ql_log_info, vha, 0x8018, 1484 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1485 1486 /* 1487 * No point in issuing another reset if one is active. Also do not 1488 * attempt a reset if we are updating flash. 1489 */ 1490 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1491 goto eh_host_reset_lock; 1492 1493 if (vha != base_vha) { 1494 if (qla2x00_vp_abort_isp(vha)) 1495 goto eh_host_reset_lock; 1496 } else { 1497 if (IS_P3P_TYPE(vha->hw)) { 1498 if (!qla82xx_fcoe_ctx_reset(vha)) { 1499 /* Ctx reset success */ 1500 ret = SUCCESS; 1501 goto eh_host_reset_lock; 1502 } 1503 /* fall thru if ctx reset failed */ 1504 } 1505 if (ha->wq) 1506 flush_workqueue(ha->wq); 1507 1508 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1509 if (ha->isp_ops->abort_isp(base_vha)) { 1510 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1511 /* failed. schedule dpc to try */ 1512 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1513 1514 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1515 ql_log(ql_log_warn, vha, 0x802a, 1516 "wait for hba online failed.\n"); 1517 goto eh_host_reset_lock; 1518 } 1519 } 1520 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1521 } 1522 1523 /* Waiting for command to be returned to OS.*/ 1524 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1525 QLA_SUCCESS) 1526 ret = SUCCESS; 1527 1528 eh_host_reset_lock: 1529 ql_log(ql_log_info, vha, 0x8017, 1530 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1531 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1532 1533 return ret; 1534 } 1535 1536 /* 1537 * qla2x00_loop_reset 1538 * Issue loop reset. 1539 * 1540 * Input: 1541 * ha = adapter block pointer. 1542 * 1543 * Returns: 1544 * 0 = success 1545 */ 1546 int 1547 qla2x00_loop_reset(scsi_qla_host_t *vha) 1548 { 1549 int ret; 1550 struct fc_port *fcport; 1551 struct qla_hw_data *ha = vha->hw; 1552 1553 if (IS_QLAFX00(ha)) { 1554 return qlafx00_loop_reset(vha); 1555 } 1556 1557 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1558 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1559 if (fcport->port_type != FCT_TARGET) 1560 continue; 1561 1562 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1563 if (ret != QLA_SUCCESS) { 1564 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1565 "Bus Reset failed: Reset=%d " 1566 "d_id=%x.\n", ret, fcport->d_id.b24); 1567 } 1568 } 1569 } 1570 1571 1572 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1573 atomic_set(&vha->loop_state, LOOP_DOWN); 1574 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1575 qla2x00_mark_all_devices_lost(vha, 0); 1576 ret = qla2x00_full_login_lip(vha); 1577 if (ret != QLA_SUCCESS) { 1578 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1579 "full_login_lip=%d.\n", ret); 1580 } 1581 } 1582 1583 if (ha->flags.enable_lip_reset) { 1584 ret = qla2x00_lip_reset(vha); 1585 if (ret != QLA_SUCCESS) 1586 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1587 "lip_reset failed (%d).\n", ret); 1588 } 1589 1590 /* Issue marker command only when we are going to start the I/O */ 1591 vha->marker_needed = 1; 1592 1593 return QLA_SUCCESS; 1594 } 1595 1596 void 1597 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1598 { 1599 int que, cnt; 1600 unsigned long flags; 1601 srb_t *sp; 1602 struct qla_hw_data *ha = vha->hw; 1603 struct req_que *req; 1604 1605 qlt_host_reset_handler(ha); 1606 1607 spin_lock_irqsave(&ha->hardware_lock, flags); 1608 for (que = 0; que < ha->max_req_queues; que++) { 1609 req = ha->req_q_map[que]; 1610 if (!req) 1611 continue; 1612 if (!req->outstanding_cmds) 1613 continue; 1614 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1615 sp = req->outstanding_cmds[cnt]; 1616 if (sp) { 1617 /* Don't abort commands in adapter during EEH 1618 * recovery as it's not accessible/responding. 1619 */ 1620 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy) { 1621 /* Get a reference to the sp and drop the lock. 1622 * The reference ensures this sp->done() call 1623 * - and not the call in qla2xxx_eh_abort() - 1624 * ends the SCSI command (with result 'res'). 1625 */ 1626 sp_get(sp); 1627 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1628 qla2xxx_eh_abort(GET_CMD_SP(sp)); 1629 spin_lock_irqsave(&ha->hardware_lock, flags); 1630 } 1631 req->outstanding_cmds[cnt] = NULL; 1632 sp->done(vha, sp, res); 1633 } 1634 } 1635 } 1636 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1637 } 1638 1639 static int 1640 qla2xxx_slave_alloc(struct scsi_device *sdev) 1641 { 1642 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1643 1644 if (!rport || fc_remote_port_chkready(rport)) 1645 return -ENXIO; 1646 1647 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1648 1649 return 0; 1650 } 1651 1652 static int 1653 qla2xxx_slave_configure(struct scsi_device *sdev) 1654 { 1655 scsi_qla_host_t *vha = shost_priv(sdev->host); 1656 struct req_que *req = vha->req; 1657 1658 if (IS_T10_PI_CAPABLE(vha->hw)) 1659 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1660 1661 scsi_change_queue_depth(sdev, req->max_q_depth); 1662 return 0; 1663 } 1664 1665 static void 1666 qla2xxx_slave_destroy(struct scsi_device *sdev) 1667 { 1668 sdev->hostdata = NULL; 1669 } 1670 1671 /** 1672 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1673 * @ha: HA context 1674 * 1675 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1676 * supported addressing method. 1677 */ 1678 static void 1679 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1680 { 1681 /* Assume a 32bit DMA mask. */ 1682 ha->flags.enable_64bit_addressing = 0; 1683 1684 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1685 /* Any upper-dword bits set? */ 1686 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1687 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1688 /* Ok, a 64bit DMA mask is applicable. */ 1689 ha->flags.enable_64bit_addressing = 1; 1690 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1691 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1692 return; 1693 } 1694 } 1695 1696 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1697 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1698 } 1699 1700 static void 1701 qla2x00_enable_intrs(struct qla_hw_data *ha) 1702 { 1703 unsigned long flags = 0; 1704 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1705 1706 spin_lock_irqsave(&ha->hardware_lock, flags); 1707 ha->interrupts_on = 1; 1708 /* enable risc and host interrupts */ 1709 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1710 RD_REG_WORD(®->ictrl); 1711 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1712 1713 } 1714 1715 static void 1716 qla2x00_disable_intrs(struct qla_hw_data *ha) 1717 { 1718 unsigned long flags = 0; 1719 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1720 1721 spin_lock_irqsave(&ha->hardware_lock, flags); 1722 ha->interrupts_on = 0; 1723 /* disable risc and host interrupts */ 1724 WRT_REG_WORD(®->ictrl, 0); 1725 RD_REG_WORD(®->ictrl); 1726 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1727 } 1728 1729 static void 1730 qla24xx_enable_intrs(struct qla_hw_data *ha) 1731 { 1732 unsigned long flags = 0; 1733 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1734 1735 spin_lock_irqsave(&ha->hardware_lock, flags); 1736 ha->interrupts_on = 1; 1737 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1738 RD_REG_DWORD(®->ictrl); 1739 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1740 } 1741 1742 static void 1743 qla24xx_disable_intrs(struct qla_hw_data *ha) 1744 { 1745 unsigned long flags = 0; 1746 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1747 1748 if (IS_NOPOLLING_TYPE(ha)) 1749 return; 1750 spin_lock_irqsave(&ha->hardware_lock, flags); 1751 ha->interrupts_on = 0; 1752 WRT_REG_DWORD(®->ictrl, 0); 1753 RD_REG_DWORD(®->ictrl); 1754 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1755 } 1756 1757 static int 1758 qla2x00_iospace_config(struct qla_hw_data *ha) 1759 { 1760 resource_size_t pio; 1761 uint16_t msix; 1762 1763 if (pci_request_selected_regions(ha->pdev, ha->bars, 1764 QLA2XXX_DRIVER_NAME)) { 1765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1766 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1767 pci_name(ha->pdev)); 1768 goto iospace_error_exit; 1769 } 1770 if (!(ha->bars & 1)) 1771 goto skip_pio; 1772 1773 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1774 pio = pci_resource_start(ha->pdev, 0); 1775 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1776 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1777 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1778 "Invalid pci I/O region size (%s).\n", 1779 pci_name(ha->pdev)); 1780 pio = 0; 1781 } 1782 } else { 1783 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1784 "Region #0 no a PIO resource (%s).\n", 1785 pci_name(ha->pdev)); 1786 pio = 0; 1787 } 1788 ha->pio_address = pio; 1789 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1790 "PIO address=%llu.\n", 1791 (unsigned long long)ha->pio_address); 1792 1793 skip_pio: 1794 /* Use MMIO operations for all accesses. */ 1795 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1796 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1797 "Region #1 not an MMIO resource (%s), aborting.\n", 1798 pci_name(ha->pdev)); 1799 goto iospace_error_exit; 1800 } 1801 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1802 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1803 "Invalid PCI mem region size (%s), aborting.\n", 1804 pci_name(ha->pdev)); 1805 goto iospace_error_exit; 1806 } 1807 1808 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1809 if (!ha->iobase) { 1810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1811 "Cannot remap MMIO (%s), aborting.\n", 1812 pci_name(ha->pdev)); 1813 goto iospace_error_exit; 1814 } 1815 1816 /* Determine queue resources */ 1817 ha->max_req_queues = ha->max_rsp_queues = 1; 1818 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1819 goto mqiobase_exit; 1820 1821 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1822 pci_resource_len(ha->pdev, 3)); 1823 if (ha->mqiobase) { 1824 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1825 "MQIO Base=%p.\n", ha->mqiobase); 1826 /* Read MSIX vector size of the board */ 1827 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1828 ha->msix_count = msix + 1; 1829 /* Max queues are bounded by available msix vectors */ 1830 /* MB interrupt uses 1 vector */ 1831 ha->max_req_queues = ha->msix_count - 1; 1832 ha->max_rsp_queues = ha->max_req_queues; 1833 /* Queue pairs is the max value minus the base queue pair */ 1834 ha->max_qpairs = ha->max_rsp_queues - 1; 1835 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 1836 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1837 1838 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1839 "MSI-X vector count: %d.\n", ha->msix_count); 1840 } else 1841 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1842 "BAR 3 not enabled.\n"); 1843 1844 mqiobase_exit: 1845 ha->msix_count = ha->max_rsp_queues + 1; 1846 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1847 "MSIX Count:%d.\n", ha->msix_count); 1848 return (0); 1849 1850 iospace_error_exit: 1851 return (-ENOMEM); 1852 } 1853 1854 1855 static int 1856 qla83xx_iospace_config(struct qla_hw_data *ha) 1857 { 1858 uint16_t msix; 1859 1860 if (pci_request_selected_regions(ha->pdev, ha->bars, 1861 QLA2XXX_DRIVER_NAME)) { 1862 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1863 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1864 pci_name(ha->pdev)); 1865 1866 goto iospace_error_exit; 1867 } 1868 1869 /* Use MMIO operations for all accesses. */ 1870 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1871 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1872 "Invalid pci I/O region size (%s).\n", 1873 pci_name(ha->pdev)); 1874 goto iospace_error_exit; 1875 } 1876 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1877 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1878 "Invalid PCI mem region size (%s), aborting\n", 1879 pci_name(ha->pdev)); 1880 goto iospace_error_exit; 1881 } 1882 1883 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1884 if (!ha->iobase) { 1885 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1886 "Cannot remap MMIO (%s), aborting.\n", 1887 pci_name(ha->pdev)); 1888 goto iospace_error_exit; 1889 } 1890 1891 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1892 /* 83XX 26XX always use MQ type access for queues 1893 * - mbar 2, a.k.a region 4 */ 1894 ha->max_req_queues = ha->max_rsp_queues = 1; 1895 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1896 pci_resource_len(ha->pdev, 4)); 1897 1898 if (!ha->mqiobase) { 1899 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1900 "BAR2/region4 not enabled\n"); 1901 goto mqiobase_exit; 1902 } 1903 1904 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1905 pci_resource_len(ha->pdev, 2)); 1906 if (ha->msixbase) { 1907 /* Read MSIX vector size of the board */ 1908 pci_read_config_word(ha->pdev, 1909 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1910 ha->msix_count = msix + 1; 1911 /* 1912 * By default, driver uses at least two msix vectors 1913 * (default & rspq) 1914 */ 1915 if (ql2xmqsupport) { 1916 /* MB interrupt uses 1 vector */ 1917 ha->max_req_queues = ha->msix_count - 1; 1918 ha->max_rsp_queues = ha->max_req_queues; 1919 1920 /* ATIOQ needs 1 vector. That's 1 less QPair */ 1921 if (QLA_TGT_MODE_ENABLED()) 1922 ha->max_req_queues--; 1923 1924 /* Queue pairs is the max value minus 1925 * the base queue pair */ 1926 ha->max_qpairs = ha->max_req_queues - 1; 1927 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190, 1928 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1929 } 1930 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1931 "MSI-X vector count: %d.\n", ha->msix_count); 1932 } else 1933 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1934 "BAR 1 not enabled.\n"); 1935 1936 mqiobase_exit: 1937 ha->msix_count = ha->max_rsp_queues + 1; 1938 if (QLA_TGT_MODE_ENABLED()) 1939 ha->msix_count++; 1940 1941 qlt_83xx_iospace_config(ha); 1942 1943 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1944 "MSIX Count:%d.\n", ha->msix_count); 1945 return 0; 1946 1947 iospace_error_exit: 1948 return -ENOMEM; 1949 } 1950 1951 static struct isp_operations qla2100_isp_ops = { 1952 .pci_config = qla2100_pci_config, 1953 .reset_chip = qla2x00_reset_chip, 1954 .chip_diag = qla2x00_chip_diag, 1955 .config_rings = qla2x00_config_rings, 1956 .reset_adapter = qla2x00_reset_adapter, 1957 .nvram_config = qla2x00_nvram_config, 1958 .update_fw_options = qla2x00_update_fw_options, 1959 .load_risc = qla2x00_load_risc, 1960 .pci_info_str = qla2x00_pci_info_str, 1961 .fw_version_str = qla2x00_fw_version_str, 1962 .intr_handler = qla2100_intr_handler, 1963 .enable_intrs = qla2x00_enable_intrs, 1964 .disable_intrs = qla2x00_disable_intrs, 1965 .abort_command = qla2x00_abort_command, 1966 .target_reset = qla2x00_abort_target, 1967 .lun_reset = qla2x00_lun_reset, 1968 .fabric_login = qla2x00_login_fabric, 1969 .fabric_logout = qla2x00_fabric_logout, 1970 .calc_req_entries = qla2x00_calc_iocbs_32, 1971 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1972 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1973 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1974 .read_nvram = qla2x00_read_nvram_data, 1975 .write_nvram = qla2x00_write_nvram_data, 1976 .fw_dump = qla2100_fw_dump, 1977 .beacon_on = NULL, 1978 .beacon_off = NULL, 1979 .beacon_blink = NULL, 1980 .read_optrom = qla2x00_read_optrom_data, 1981 .write_optrom = qla2x00_write_optrom_data, 1982 .get_flash_version = qla2x00_get_flash_version, 1983 .start_scsi = qla2x00_start_scsi, 1984 .start_scsi_mq = NULL, 1985 .abort_isp = qla2x00_abort_isp, 1986 .iospace_config = qla2x00_iospace_config, 1987 .initialize_adapter = qla2x00_initialize_adapter, 1988 }; 1989 1990 static struct isp_operations qla2300_isp_ops = { 1991 .pci_config = qla2300_pci_config, 1992 .reset_chip = qla2x00_reset_chip, 1993 .chip_diag = qla2x00_chip_diag, 1994 .config_rings = qla2x00_config_rings, 1995 .reset_adapter = qla2x00_reset_adapter, 1996 .nvram_config = qla2x00_nvram_config, 1997 .update_fw_options = qla2x00_update_fw_options, 1998 .load_risc = qla2x00_load_risc, 1999 .pci_info_str = qla2x00_pci_info_str, 2000 .fw_version_str = qla2x00_fw_version_str, 2001 .intr_handler = qla2300_intr_handler, 2002 .enable_intrs = qla2x00_enable_intrs, 2003 .disable_intrs = qla2x00_disable_intrs, 2004 .abort_command = qla2x00_abort_command, 2005 .target_reset = qla2x00_abort_target, 2006 .lun_reset = qla2x00_lun_reset, 2007 .fabric_login = qla2x00_login_fabric, 2008 .fabric_logout = qla2x00_fabric_logout, 2009 .calc_req_entries = qla2x00_calc_iocbs_32, 2010 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2011 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2012 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2013 .read_nvram = qla2x00_read_nvram_data, 2014 .write_nvram = qla2x00_write_nvram_data, 2015 .fw_dump = qla2300_fw_dump, 2016 .beacon_on = qla2x00_beacon_on, 2017 .beacon_off = qla2x00_beacon_off, 2018 .beacon_blink = qla2x00_beacon_blink, 2019 .read_optrom = qla2x00_read_optrom_data, 2020 .write_optrom = qla2x00_write_optrom_data, 2021 .get_flash_version = qla2x00_get_flash_version, 2022 .start_scsi = qla2x00_start_scsi, 2023 .start_scsi_mq = NULL, 2024 .abort_isp = qla2x00_abort_isp, 2025 .iospace_config = qla2x00_iospace_config, 2026 .initialize_adapter = qla2x00_initialize_adapter, 2027 }; 2028 2029 static struct isp_operations qla24xx_isp_ops = { 2030 .pci_config = qla24xx_pci_config, 2031 .reset_chip = qla24xx_reset_chip, 2032 .chip_diag = qla24xx_chip_diag, 2033 .config_rings = qla24xx_config_rings, 2034 .reset_adapter = qla24xx_reset_adapter, 2035 .nvram_config = qla24xx_nvram_config, 2036 .update_fw_options = qla24xx_update_fw_options, 2037 .load_risc = qla24xx_load_risc, 2038 .pci_info_str = qla24xx_pci_info_str, 2039 .fw_version_str = qla24xx_fw_version_str, 2040 .intr_handler = qla24xx_intr_handler, 2041 .enable_intrs = qla24xx_enable_intrs, 2042 .disable_intrs = qla24xx_disable_intrs, 2043 .abort_command = qla24xx_abort_command, 2044 .target_reset = qla24xx_abort_target, 2045 .lun_reset = qla24xx_lun_reset, 2046 .fabric_login = qla24xx_login_fabric, 2047 .fabric_logout = qla24xx_fabric_logout, 2048 .calc_req_entries = NULL, 2049 .build_iocbs = NULL, 2050 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2052 .read_nvram = qla24xx_read_nvram_data, 2053 .write_nvram = qla24xx_write_nvram_data, 2054 .fw_dump = qla24xx_fw_dump, 2055 .beacon_on = qla24xx_beacon_on, 2056 .beacon_off = qla24xx_beacon_off, 2057 .beacon_blink = qla24xx_beacon_blink, 2058 .read_optrom = qla24xx_read_optrom_data, 2059 .write_optrom = qla24xx_write_optrom_data, 2060 .get_flash_version = qla24xx_get_flash_version, 2061 .start_scsi = qla24xx_start_scsi, 2062 .start_scsi_mq = NULL, 2063 .abort_isp = qla2x00_abort_isp, 2064 .iospace_config = qla2x00_iospace_config, 2065 .initialize_adapter = qla2x00_initialize_adapter, 2066 }; 2067 2068 static struct isp_operations qla25xx_isp_ops = { 2069 .pci_config = qla25xx_pci_config, 2070 .reset_chip = qla24xx_reset_chip, 2071 .chip_diag = qla24xx_chip_diag, 2072 .config_rings = qla24xx_config_rings, 2073 .reset_adapter = qla24xx_reset_adapter, 2074 .nvram_config = qla24xx_nvram_config, 2075 .update_fw_options = qla24xx_update_fw_options, 2076 .load_risc = qla24xx_load_risc, 2077 .pci_info_str = qla24xx_pci_info_str, 2078 .fw_version_str = qla24xx_fw_version_str, 2079 .intr_handler = qla24xx_intr_handler, 2080 .enable_intrs = qla24xx_enable_intrs, 2081 .disable_intrs = qla24xx_disable_intrs, 2082 .abort_command = qla24xx_abort_command, 2083 .target_reset = qla24xx_abort_target, 2084 .lun_reset = qla24xx_lun_reset, 2085 .fabric_login = qla24xx_login_fabric, 2086 .fabric_logout = qla24xx_fabric_logout, 2087 .calc_req_entries = NULL, 2088 .build_iocbs = NULL, 2089 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2090 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2091 .read_nvram = qla25xx_read_nvram_data, 2092 .write_nvram = qla25xx_write_nvram_data, 2093 .fw_dump = qla25xx_fw_dump, 2094 .beacon_on = qla24xx_beacon_on, 2095 .beacon_off = qla24xx_beacon_off, 2096 .beacon_blink = qla24xx_beacon_blink, 2097 .read_optrom = qla25xx_read_optrom_data, 2098 .write_optrom = qla24xx_write_optrom_data, 2099 .get_flash_version = qla24xx_get_flash_version, 2100 .start_scsi = qla24xx_dif_start_scsi, 2101 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2102 .abort_isp = qla2x00_abort_isp, 2103 .iospace_config = qla2x00_iospace_config, 2104 .initialize_adapter = qla2x00_initialize_adapter, 2105 }; 2106 2107 static struct isp_operations qla81xx_isp_ops = { 2108 .pci_config = qla25xx_pci_config, 2109 .reset_chip = qla24xx_reset_chip, 2110 .chip_diag = qla24xx_chip_diag, 2111 .config_rings = qla24xx_config_rings, 2112 .reset_adapter = qla24xx_reset_adapter, 2113 .nvram_config = qla81xx_nvram_config, 2114 .update_fw_options = qla81xx_update_fw_options, 2115 .load_risc = qla81xx_load_risc, 2116 .pci_info_str = qla24xx_pci_info_str, 2117 .fw_version_str = qla24xx_fw_version_str, 2118 .intr_handler = qla24xx_intr_handler, 2119 .enable_intrs = qla24xx_enable_intrs, 2120 .disable_intrs = qla24xx_disable_intrs, 2121 .abort_command = qla24xx_abort_command, 2122 .target_reset = qla24xx_abort_target, 2123 .lun_reset = qla24xx_lun_reset, 2124 .fabric_login = qla24xx_login_fabric, 2125 .fabric_logout = qla24xx_fabric_logout, 2126 .calc_req_entries = NULL, 2127 .build_iocbs = NULL, 2128 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2129 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2130 .read_nvram = NULL, 2131 .write_nvram = NULL, 2132 .fw_dump = qla81xx_fw_dump, 2133 .beacon_on = qla24xx_beacon_on, 2134 .beacon_off = qla24xx_beacon_off, 2135 .beacon_blink = qla83xx_beacon_blink, 2136 .read_optrom = qla25xx_read_optrom_data, 2137 .write_optrom = qla24xx_write_optrom_data, 2138 .get_flash_version = qla24xx_get_flash_version, 2139 .start_scsi = qla24xx_dif_start_scsi, 2140 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2141 .abort_isp = qla2x00_abort_isp, 2142 .iospace_config = qla2x00_iospace_config, 2143 .initialize_adapter = qla2x00_initialize_adapter, 2144 }; 2145 2146 static struct isp_operations qla82xx_isp_ops = { 2147 .pci_config = qla82xx_pci_config, 2148 .reset_chip = qla82xx_reset_chip, 2149 .chip_diag = qla24xx_chip_diag, 2150 .config_rings = qla82xx_config_rings, 2151 .reset_adapter = qla24xx_reset_adapter, 2152 .nvram_config = qla81xx_nvram_config, 2153 .update_fw_options = qla24xx_update_fw_options, 2154 .load_risc = qla82xx_load_risc, 2155 .pci_info_str = qla24xx_pci_info_str, 2156 .fw_version_str = qla24xx_fw_version_str, 2157 .intr_handler = qla82xx_intr_handler, 2158 .enable_intrs = qla82xx_enable_intrs, 2159 .disable_intrs = qla82xx_disable_intrs, 2160 .abort_command = qla24xx_abort_command, 2161 .target_reset = qla24xx_abort_target, 2162 .lun_reset = qla24xx_lun_reset, 2163 .fabric_login = qla24xx_login_fabric, 2164 .fabric_logout = qla24xx_fabric_logout, 2165 .calc_req_entries = NULL, 2166 .build_iocbs = NULL, 2167 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2168 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2169 .read_nvram = qla24xx_read_nvram_data, 2170 .write_nvram = qla24xx_write_nvram_data, 2171 .fw_dump = qla82xx_fw_dump, 2172 .beacon_on = qla82xx_beacon_on, 2173 .beacon_off = qla82xx_beacon_off, 2174 .beacon_blink = NULL, 2175 .read_optrom = qla82xx_read_optrom_data, 2176 .write_optrom = qla82xx_write_optrom_data, 2177 .get_flash_version = qla82xx_get_flash_version, 2178 .start_scsi = qla82xx_start_scsi, 2179 .start_scsi_mq = NULL, 2180 .abort_isp = qla82xx_abort_isp, 2181 .iospace_config = qla82xx_iospace_config, 2182 .initialize_adapter = qla2x00_initialize_adapter, 2183 }; 2184 2185 static struct isp_operations qla8044_isp_ops = { 2186 .pci_config = qla82xx_pci_config, 2187 .reset_chip = qla82xx_reset_chip, 2188 .chip_diag = qla24xx_chip_diag, 2189 .config_rings = qla82xx_config_rings, 2190 .reset_adapter = qla24xx_reset_adapter, 2191 .nvram_config = qla81xx_nvram_config, 2192 .update_fw_options = qla24xx_update_fw_options, 2193 .load_risc = qla82xx_load_risc, 2194 .pci_info_str = qla24xx_pci_info_str, 2195 .fw_version_str = qla24xx_fw_version_str, 2196 .intr_handler = qla8044_intr_handler, 2197 .enable_intrs = qla82xx_enable_intrs, 2198 .disable_intrs = qla82xx_disable_intrs, 2199 .abort_command = qla24xx_abort_command, 2200 .target_reset = qla24xx_abort_target, 2201 .lun_reset = qla24xx_lun_reset, 2202 .fabric_login = qla24xx_login_fabric, 2203 .fabric_logout = qla24xx_fabric_logout, 2204 .calc_req_entries = NULL, 2205 .build_iocbs = NULL, 2206 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2207 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2208 .read_nvram = NULL, 2209 .write_nvram = NULL, 2210 .fw_dump = qla8044_fw_dump, 2211 .beacon_on = qla82xx_beacon_on, 2212 .beacon_off = qla82xx_beacon_off, 2213 .beacon_blink = NULL, 2214 .read_optrom = qla8044_read_optrom_data, 2215 .write_optrom = qla8044_write_optrom_data, 2216 .get_flash_version = qla82xx_get_flash_version, 2217 .start_scsi = qla82xx_start_scsi, 2218 .start_scsi_mq = NULL, 2219 .abort_isp = qla8044_abort_isp, 2220 .iospace_config = qla82xx_iospace_config, 2221 .initialize_adapter = qla2x00_initialize_adapter, 2222 }; 2223 2224 static struct isp_operations qla83xx_isp_ops = { 2225 .pci_config = qla25xx_pci_config, 2226 .reset_chip = qla24xx_reset_chip, 2227 .chip_diag = qla24xx_chip_diag, 2228 .config_rings = qla24xx_config_rings, 2229 .reset_adapter = qla24xx_reset_adapter, 2230 .nvram_config = qla81xx_nvram_config, 2231 .update_fw_options = qla81xx_update_fw_options, 2232 .load_risc = qla81xx_load_risc, 2233 .pci_info_str = qla24xx_pci_info_str, 2234 .fw_version_str = qla24xx_fw_version_str, 2235 .intr_handler = qla24xx_intr_handler, 2236 .enable_intrs = qla24xx_enable_intrs, 2237 .disable_intrs = qla24xx_disable_intrs, 2238 .abort_command = qla24xx_abort_command, 2239 .target_reset = qla24xx_abort_target, 2240 .lun_reset = qla24xx_lun_reset, 2241 .fabric_login = qla24xx_login_fabric, 2242 .fabric_logout = qla24xx_fabric_logout, 2243 .calc_req_entries = NULL, 2244 .build_iocbs = NULL, 2245 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2246 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2247 .read_nvram = NULL, 2248 .write_nvram = NULL, 2249 .fw_dump = qla83xx_fw_dump, 2250 .beacon_on = qla24xx_beacon_on, 2251 .beacon_off = qla24xx_beacon_off, 2252 .beacon_blink = qla83xx_beacon_blink, 2253 .read_optrom = qla25xx_read_optrom_data, 2254 .write_optrom = qla24xx_write_optrom_data, 2255 .get_flash_version = qla24xx_get_flash_version, 2256 .start_scsi = qla24xx_dif_start_scsi, 2257 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2258 .abort_isp = qla2x00_abort_isp, 2259 .iospace_config = qla83xx_iospace_config, 2260 .initialize_adapter = qla2x00_initialize_adapter, 2261 }; 2262 2263 static struct isp_operations qlafx00_isp_ops = { 2264 .pci_config = qlafx00_pci_config, 2265 .reset_chip = qlafx00_soft_reset, 2266 .chip_diag = qlafx00_chip_diag, 2267 .config_rings = qlafx00_config_rings, 2268 .reset_adapter = qlafx00_soft_reset, 2269 .nvram_config = NULL, 2270 .update_fw_options = NULL, 2271 .load_risc = NULL, 2272 .pci_info_str = qlafx00_pci_info_str, 2273 .fw_version_str = qlafx00_fw_version_str, 2274 .intr_handler = qlafx00_intr_handler, 2275 .enable_intrs = qlafx00_enable_intrs, 2276 .disable_intrs = qlafx00_disable_intrs, 2277 .abort_command = qla24xx_async_abort_command, 2278 .target_reset = qlafx00_abort_target, 2279 .lun_reset = qlafx00_lun_reset, 2280 .fabric_login = NULL, 2281 .fabric_logout = NULL, 2282 .calc_req_entries = NULL, 2283 .build_iocbs = NULL, 2284 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2285 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2286 .read_nvram = qla24xx_read_nvram_data, 2287 .write_nvram = qla24xx_write_nvram_data, 2288 .fw_dump = NULL, 2289 .beacon_on = qla24xx_beacon_on, 2290 .beacon_off = qla24xx_beacon_off, 2291 .beacon_blink = NULL, 2292 .read_optrom = qla24xx_read_optrom_data, 2293 .write_optrom = qla24xx_write_optrom_data, 2294 .get_flash_version = qla24xx_get_flash_version, 2295 .start_scsi = qlafx00_start_scsi, 2296 .start_scsi_mq = NULL, 2297 .abort_isp = qlafx00_abort_isp, 2298 .iospace_config = qlafx00_iospace_config, 2299 .initialize_adapter = qlafx00_initialize_adapter, 2300 }; 2301 2302 static struct isp_operations qla27xx_isp_ops = { 2303 .pci_config = qla25xx_pci_config, 2304 .reset_chip = qla24xx_reset_chip, 2305 .chip_diag = qla24xx_chip_diag, 2306 .config_rings = qla24xx_config_rings, 2307 .reset_adapter = qla24xx_reset_adapter, 2308 .nvram_config = qla81xx_nvram_config, 2309 .update_fw_options = qla81xx_update_fw_options, 2310 .load_risc = qla81xx_load_risc, 2311 .pci_info_str = qla24xx_pci_info_str, 2312 .fw_version_str = qla24xx_fw_version_str, 2313 .intr_handler = qla24xx_intr_handler, 2314 .enable_intrs = qla24xx_enable_intrs, 2315 .disable_intrs = qla24xx_disable_intrs, 2316 .abort_command = qla24xx_abort_command, 2317 .target_reset = qla24xx_abort_target, 2318 .lun_reset = qla24xx_lun_reset, 2319 .fabric_login = qla24xx_login_fabric, 2320 .fabric_logout = qla24xx_fabric_logout, 2321 .calc_req_entries = NULL, 2322 .build_iocbs = NULL, 2323 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2324 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2325 .read_nvram = NULL, 2326 .write_nvram = NULL, 2327 .fw_dump = qla27xx_fwdump, 2328 .beacon_on = qla24xx_beacon_on, 2329 .beacon_off = qla24xx_beacon_off, 2330 .beacon_blink = qla83xx_beacon_blink, 2331 .read_optrom = qla25xx_read_optrom_data, 2332 .write_optrom = qla24xx_write_optrom_data, 2333 .get_flash_version = qla24xx_get_flash_version, 2334 .start_scsi = qla24xx_dif_start_scsi, 2335 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2336 .abort_isp = qla2x00_abort_isp, 2337 .iospace_config = qla83xx_iospace_config, 2338 .initialize_adapter = qla2x00_initialize_adapter, 2339 }; 2340 2341 static inline void 2342 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2343 { 2344 ha->device_type = DT_EXTENDED_IDS; 2345 switch (ha->pdev->device) { 2346 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2347 ha->isp_type |= DT_ISP2100; 2348 ha->device_type &= ~DT_EXTENDED_IDS; 2349 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2350 break; 2351 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2352 ha->isp_type |= DT_ISP2200; 2353 ha->device_type &= ~DT_EXTENDED_IDS; 2354 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2355 break; 2356 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2357 ha->isp_type |= DT_ISP2300; 2358 ha->device_type |= DT_ZIO_SUPPORTED; 2359 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2360 break; 2361 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2362 ha->isp_type |= DT_ISP2312; 2363 ha->device_type |= DT_ZIO_SUPPORTED; 2364 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2365 break; 2366 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2367 ha->isp_type |= DT_ISP2322; 2368 ha->device_type |= DT_ZIO_SUPPORTED; 2369 if (ha->pdev->subsystem_vendor == 0x1028 && 2370 ha->pdev->subsystem_device == 0x0170) 2371 ha->device_type |= DT_OEM_001; 2372 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2373 break; 2374 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2375 ha->isp_type |= DT_ISP6312; 2376 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2377 break; 2378 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2379 ha->isp_type |= DT_ISP6322; 2380 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2381 break; 2382 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2383 ha->isp_type |= DT_ISP2422; 2384 ha->device_type |= DT_ZIO_SUPPORTED; 2385 ha->device_type |= DT_FWI2; 2386 ha->device_type |= DT_IIDMA; 2387 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2388 break; 2389 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2390 ha->isp_type |= DT_ISP2432; 2391 ha->device_type |= DT_ZIO_SUPPORTED; 2392 ha->device_type |= DT_FWI2; 2393 ha->device_type |= DT_IIDMA; 2394 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2395 break; 2396 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2397 ha->isp_type |= DT_ISP8432; 2398 ha->device_type |= DT_ZIO_SUPPORTED; 2399 ha->device_type |= DT_FWI2; 2400 ha->device_type |= DT_IIDMA; 2401 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2402 break; 2403 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2404 ha->isp_type |= DT_ISP5422; 2405 ha->device_type |= DT_FWI2; 2406 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2407 break; 2408 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2409 ha->isp_type |= DT_ISP5432; 2410 ha->device_type |= DT_FWI2; 2411 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2412 break; 2413 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2414 ha->isp_type |= DT_ISP2532; 2415 ha->device_type |= DT_ZIO_SUPPORTED; 2416 ha->device_type |= DT_FWI2; 2417 ha->device_type |= DT_IIDMA; 2418 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2419 break; 2420 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2421 ha->isp_type |= DT_ISP8001; 2422 ha->device_type |= DT_ZIO_SUPPORTED; 2423 ha->device_type |= DT_FWI2; 2424 ha->device_type |= DT_IIDMA; 2425 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2426 break; 2427 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2428 ha->isp_type |= DT_ISP8021; 2429 ha->device_type |= DT_ZIO_SUPPORTED; 2430 ha->device_type |= DT_FWI2; 2431 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2432 /* Initialize 82XX ISP flags */ 2433 qla82xx_init_flags(ha); 2434 break; 2435 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2436 ha->isp_type |= DT_ISP8044; 2437 ha->device_type |= DT_ZIO_SUPPORTED; 2438 ha->device_type |= DT_FWI2; 2439 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2440 /* Initialize 82XX ISP flags */ 2441 qla82xx_init_flags(ha); 2442 break; 2443 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2444 ha->isp_type |= DT_ISP2031; 2445 ha->device_type |= DT_ZIO_SUPPORTED; 2446 ha->device_type |= DT_FWI2; 2447 ha->device_type |= DT_IIDMA; 2448 ha->device_type |= DT_T10_PI; 2449 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2450 break; 2451 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2452 ha->isp_type |= DT_ISP8031; 2453 ha->device_type |= DT_ZIO_SUPPORTED; 2454 ha->device_type |= DT_FWI2; 2455 ha->device_type |= DT_IIDMA; 2456 ha->device_type |= DT_T10_PI; 2457 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2458 break; 2459 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2460 ha->isp_type |= DT_ISPFX00; 2461 break; 2462 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2463 ha->isp_type |= DT_ISP2071; 2464 ha->device_type |= DT_ZIO_SUPPORTED; 2465 ha->device_type |= DT_FWI2; 2466 ha->device_type |= DT_IIDMA; 2467 ha->device_type |= DT_T10_PI; 2468 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2469 break; 2470 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2471 ha->isp_type |= DT_ISP2271; 2472 ha->device_type |= DT_ZIO_SUPPORTED; 2473 ha->device_type |= DT_FWI2; 2474 ha->device_type |= DT_IIDMA; 2475 ha->device_type |= DT_T10_PI; 2476 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2477 break; 2478 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2479 ha->isp_type |= DT_ISP2261; 2480 ha->device_type |= DT_ZIO_SUPPORTED; 2481 ha->device_type |= DT_FWI2; 2482 ha->device_type |= DT_IIDMA; 2483 ha->device_type |= DT_T10_PI; 2484 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2485 break; 2486 } 2487 2488 if (IS_QLA82XX(ha)) 2489 ha->port_no = ha->portnum & 1; 2490 else { 2491 /* Get adapter physical port no from interrupt pin register. */ 2492 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2493 if (IS_QLA27XX(ha)) 2494 ha->port_no--; 2495 else 2496 ha->port_no = !(ha->port_no & 1); 2497 } 2498 2499 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2500 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2501 ha->device_type, ha->port_no, ha->fw_srisc_address); 2502 } 2503 2504 static void 2505 qla2xxx_scan_start(struct Scsi_Host *shost) 2506 { 2507 scsi_qla_host_t *vha = shost_priv(shost); 2508 2509 if (vha->hw->flags.running_gold_fw) 2510 return; 2511 2512 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2513 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2514 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2515 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2516 } 2517 2518 static int 2519 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2520 { 2521 scsi_qla_host_t *vha = shost_priv(shost); 2522 2523 if (test_bit(UNLOADING, &vha->dpc_flags)) 2524 return 1; 2525 if (!vha->host) 2526 return 1; 2527 if (time > vha->hw->loop_reset_delay * HZ) 2528 return 1; 2529 2530 return atomic_read(&vha->loop_state) == LOOP_READY; 2531 } 2532 2533 /* 2534 * PCI driver interface 2535 */ 2536 static int 2537 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2538 { 2539 int ret = -ENODEV; 2540 struct Scsi_Host *host; 2541 scsi_qla_host_t *base_vha = NULL; 2542 struct qla_hw_data *ha; 2543 char pci_info[30]; 2544 char fw_str[30], wq_name[30]; 2545 struct scsi_host_template *sht; 2546 int bars, mem_only = 0; 2547 uint16_t req_length = 0, rsp_length = 0; 2548 struct req_que *req = NULL; 2549 struct rsp_que *rsp = NULL; 2550 int i; 2551 2552 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2553 sht = &qla2xxx_driver_template; 2554 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2555 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2556 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2557 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2558 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2559 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2560 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2561 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2562 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2563 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2564 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2565 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2566 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2567 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2568 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2569 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2570 mem_only = 1; 2571 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2572 "Mem only adapter.\n"); 2573 } 2574 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2575 "Bars=%d.\n", bars); 2576 2577 if (mem_only) { 2578 if (pci_enable_device_mem(pdev)) 2579 goto probe_out; 2580 } else { 2581 if (pci_enable_device(pdev)) 2582 goto probe_out; 2583 } 2584 2585 /* This may fail but that's ok */ 2586 pci_enable_pcie_error_reporting(pdev); 2587 2588 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2589 if (!ha) { 2590 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2591 "Unable to allocate memory for ha.\n"); 2592 goto probe_out; 2593 } 2594 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2595 "Memory allocated for ha=%p.\n", ha); 2596 ha->pdev = pdev; 2597 ha->tgt.enable_class_2 = ql2xenableclass2; 2598 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2599 spin_lock_init(&ha->tgt.q_full_lock); 2600 spin_lock_init(&ha->tgt.sess_lock); 2601 spin_lock_init(&ha->tgt.atio_lock); 2602 2603 2604 /* Clear our data area */ 2605 ha->bars = bars; 2606 ha->mem_only = mem_only; 2607 spin_lock_init(&ha->hardware_lock); 2608 spin_lock_init(&ha->vport_slock); 2609 mutex_init(&ha->selflogin_lock); 2610 mutex_init(&ha->optrom_mutex); 2611 2612 /* Set ISP-type information. */ 2613 qla2x00_set_isp_flags(ha); 2614 2615 /* Set EEH reset type to fundamental if required by hba */ 2616 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2617 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2618 pdev->needs_freset = 1; 2619 2620 ha->prev_topology = 0; 2621 ha->init_cb_size = sizeof(init_cb_t); 2622 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2623 ha->optrom_size = OPTROM_SIZE_2300; 2624 2625 /* Assign ISP specific operations. */ 2626 if (IS_QLA2100(ha)) { 2627 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2628 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2629 req_length = REQUEST_ENTRY_CNT_2100; 2630 rsp_length = RESPONSE_ENTRY_CNT_2100; 2631 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2632 ha->gid_list_info_size = 4; 2633 ha->flash_conf_off = ~0; 2634 ha->flash_data_off = ~0; 2635 ha->nvram_conf_off = ~0; 2636 ha->nvram_data_off = ~0; 2637 ha->isp_ops = &qla2100_isp_ops; 2638 } else if (IS_QLA2200(ha)) { 2639 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2640 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2641 req_length = REQUEST_ENTRY_CNT_2200; 2642 rsp_length = RESPONSE_ENTRY_CNT_2100; 2643 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2644 ha->gid_list_info_size = 4; 2645 ha->flash_conf_off = ~0; 2646 ha->flash_data_off = ~0; 2647 ha->nvram_conf_off = ~0; 2648 ha->nvram_data_off = ~0; 2649 ha->isp_ops = &qla2100_isp_ops; 2650 } else if (IS_QLA23XX(ha)) { 2651 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2652 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2653 req_length = REQUEST_ENTRY_CNT_2200; 2654 rsp_length = RESPONSE_ENTRY_CNT_2300; 2655 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2656 ha->gid_list_info_size = 6; 2657 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2658 ha->optrom_size = OPTROM_SIZE_2322; 2659 ha->flash_conf_off = ~0; 2660 ha->flash_data_off = ~0; 2661 ha->nvram_conf_off = ~0; 2662 ha->nvram_data_off = ~0; 2663 ha->isp_ops = &qla2300_isp_ops; 2664 } else if (IS_QLA24XX_TYPE(ha)) { 2665 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2666 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2667 req_length = REQUEST_ENTRY_CNT_24XX; 2668 rsp_length = RESPONSE_ENTRY_CNT_2300; 2669 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2670 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2671 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2672 ha->gid_list_info_size = 8; 2673 ha->optrom_size = OPTROM_SIZE_24XX; 2674 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2675 ha->isp_ops = &qla24xx_isp_ops; 2676 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2677 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2678 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2679 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2680 } else if (IS_QLA25XX(ha)) { 2681 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2682 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2683 req_length = REQUEST_ENTRY_CNT_24XX; 2684 rsp_length = RESPONSE_ENTRY_CNT_2300; 2685 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2686 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2687 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2688 ha->gid_list_info_size = 8; 2689 ha->optrom_size = OPTROM_SIZE_25XX; 2690 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2691 ha->isp_ops = &qla25xx_isp_ops; 2692 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2693 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2694 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2695 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2696 } else if (IS_QLA81XX(ha)) { 2697 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2698 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2699 req_length = REQUEST_ENTRY_CNT_24XX; 2700 rsp_length = RESPONSE_ENTRY_CNT_2300; 2701 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2702 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2703 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2704 ha->gid_list_info_size = 8; 2705 ha->optrom_size = OPTROM_SIZE_81XX; 2706 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2707 ha->isp_ops = &qla81xx_isp_ops; 2708 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2709 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2710 ha->nvram_conf_off = ~0; 2711 ha->nvram_data_off = ~0; 2712 } else if (IS_QLA82XX(ha)) { 2713 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2714 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2715 req_length = REQUEST_ENTRY_CNT_82XX; 2716 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2717 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2718 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2719 ha->gid_list_info_size = 8; 2720 ha->optrom_size = OPTROM_SIZE_82XX; 2721 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2722 ha->isp_ops = &qla82xx_isp_ops; 2723 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2724 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2725 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2726 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2727 } else if (IS_QLA8044(ha)) { 2728 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2729 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2730 req_length = REQUEST_ENTRY_CNT_82XX; 2731 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2732 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2733 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2734 ha->gid_list_info_size = 8; 2735 ha->optrom_size = OPTROM_SIZE_83XX; 2736 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2737 ha->isp_ops = &qla8044_isp_ops; 2738 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2739 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2740 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2741 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2742 } else if (IS_QLA83XX(ha)) { 2743 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2744 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2745 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2746 req_length = REQUEST_ENTRY_CNT_83XX; 2747 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2748 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2749 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2750 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2751 ha->gid_list_info_size = 8; 2752 ha->optrom_size = OPTROM_SIZE_83XX; 2753 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2754 ha->isp_ops = &qla83xx_isp_ops; 2755 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2756 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2757 ha->nvram_conf_off = ~0; 2758 ha->nvram_data_off = ~0; 2759 } else if (IS_QLAFX00(ha)) { 2760 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2761 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2762 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2763 req_length = REQUEST_ENTRY_CNT_FX00; 2764 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2765 ha->isp_ops = &qlafx00_isp_ops; 2766 ha->port_down_retry_count = 30; /* default value */ 2767 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2768 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2769 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2770 ha->mr.fw_hbt_en = 1; 2771 ha->mr.host_info_resend = false; 2772 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2773 } else if (IS_QLA27XX(ha)) { 2774 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2775 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2776 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2777 req_length = REQUEST_ENTRY_CNT_83XX; 2778 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2779 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2780 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2781 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2782 ha->gid_list_info_size = 8; 2783 ha->optrom_size = OPTROM_SIZE_83XX; 2784 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2785 ha->isp_ops = &qla27xx_isp_ops; 2786 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2787 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2788 ha->nvram_conf_off = ~0; 2789 ha->nvram_data_off = ~0; 2790 } 2791 2792 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2793 "mbx_count=%d, req_length=%d, " 2794 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2795 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2796 "max_fibre_devices=%d.\n", 2797 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2798 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2799 ha->nvram_npiv_size, ha->max_fibre_devices); 2800 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2801 "isp_ops=%p, flash_conf_off=%d, " 2802 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2803 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2804 ha->nvram_conf_off, ha->nvram_data_off); 2805 2806 /* Configure PCI I/O space */ 2807 ret = ha->isp_ops->iospace_config(ha); 2808 if (ret) 2809 goto iospace_config_failed; 2810 2811 ql_log_pci(ql_log_info, pdev, 0x001d, 2812 "Found an ISP%04X irq %d iobase 0x%p.\n", 2813 pdev->device, pdev->irq, ha->iobase); 2814 mutex_init(&ha->vport_lock); 2815 mutex_init(&ha->mq_lock); 2816 init_completion(&ha->mbx_cmd_comp); 2817 complete(&ha->mbx_cmd_comp); 2818 init_completion(&ha->mbx_intr_comp); 2819 init_completion(&ha->dcbx_comp); 2820 init_completion(&ha->lb_portup_comp); 2821 2822 set_bit(0, (unsigned long *) ha->vp_idx_map); 2823 2824 qla2x00_config_dma_addressing(ha); 2825 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2826 "64 Bit addressing is %s.\n", 2827 ha->flags.enable_64bit_addressing ? "enable" : 2828 "disable"); 2829 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2830 if (ret) { 2831 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2832 "Failed to allocate memory for adapter, aborting.\n"); 2833 2834 goto probe_hw_failed; 2835 } 2836 2837 req->max_q_depth = MAX_Q_DEPTH; 2838 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2839 req->max_q_depth = ql2xmaxqdepth; 2840 2841 2842 base_vha = qla2x00_create_host(sht, ha); 2843 if (!base_vha) { 2844 ret = -ENOMEM; 2845 qla2x00_mem_free(ha); 2846 qla2x00_free_req_que(ha, req); 2847 qla2x00_free_rsp_que(ha, rsp); 2848 goto probe_hw_failed; 2849 } 2850 2851 pci_set_drvdata(pdev, base_vha); 2852 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2853 2854 host = base_vha->host; 2855 base_vha->req = req; 2856 if (IS_QLA2XXX_MIDTYPE(ha)) 2857 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2858 else 2859 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2860 base_vha->vp_idx; 2861 2862 /* Setup fcport template structure. */ 2863 ha->mr.fcport.vha = base_vha; 2864 ha->mr.fcport.port_type = FCT_UNKNOWN; 2865 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2866 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2867 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2868 ha->mr.fcport.scan_state = 1; 2869 2870 /* Set the SG table size based on ISP type */ 2871 if (!IS_FWI2_CAPABLE(ha)) { 2872 if (IS_QLA2100(ha)) 2873 host->sg_tablesize = 32; 2874 } else { 2875 if (!IS_QLA82XX(ha)) 2876 host->sg_tablesize = QLA_SG_ALL; 2877 } 2878 host->max_id = ha->max_fibre_devices; 2879 host->cmd_per_lun = 3; 2880 host->unique_id = host->host_no; 2881 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2882 host->max_cmd_len = 32; 2883 else 2884 host->max_cmd_len = MAX_CMDSZ; 2885 host->max_channel = MAX_BUSES - 1; 2886 /* Older HBAs support only 16-bit LUNs */ 2887 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2888 ql2xmaxlun > 0xffff) 2889 host->max_lun = 0xffff; 2890 else 2891 host->max_lun = ql2xmaxlun; 2892 host->transportt = qla2xxx_transport_template; 2893 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2894 2895 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2896 "max_id=%d this_id=%d " 2897 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2898 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2899 host->this_id, host->cmd_per_lun, host->unique_id, 2900 host->max_cmd_len, host->max_channel, host->max_lun, 2901 host->transportt, sht->vendor_id); 2902 2903 /* Set up the irqs */ 2904 ret = qla2x00_request_irqs(ha, rsp); 2905 if (ret) 2906 goto probe_init_failed; 2907 2908 /* Alloc arrays of request and response ring ptrs */ 2909 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2910 ql_log(ql_log_fatal, base_vha, 0x003d, 2911 "Failed to allocate memory for queue pointers..." 2912 "aborting.\n"); 2913 goto probe_init_failed; 2914 } 2915 2916 if (ha->mqenable && shost_use_blk_mq(host)) { 2917 /* number of hardware queues supported by blk/scsi-mq*/ 2918 host->nr_hw_queues = ha->max_qpairs; 2919 2920 ql_dbg(ql_dbg_init, base_vha, 0x0192, 2921 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 2922 } else 2923 ql_dbg(ql_dbg_init, base_vha, 0x0193, 2924 "blk/scsi-mq disabled.\n"); 2925 2926 qlt_probe_one_stage1(base_vha, ha); 2927 2928 pci_save_state(pdev); 2929 2930 /* Assign back pointers */ 2931 rsp->req = req; 2932 req->rsp = rsp; 2933 2934 if (IS_QLAFX00(ha)) { 2935 ha->rsp_q_map[0] = rsp; 2936 ha->req_q_map[0] = req; 2937 set_bit(0, ha->req_qid_map); 2938 set_bit(0, ha->rsp_qid_map); 2939 } 2940 2941 /* FWI2-capable only. */ 2942 req->req_q_in = &ha->iobase->isp24.req_q_in; 2943 req->req_q_out = &ha->iobase->isp24.req_q_out; 2944 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2945 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2946 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2947 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2948 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2949 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2950 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2951 } 2952 2953 if (IS_QLAFX00(ha)) { 2954 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2955 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2956 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2957 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2958 } 2959 2960 if (IS_P3P_TYPE(ha)) { 2961 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2962 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2963 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2964 } 2965 2966 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2967 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2968 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2969 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2970 "req->req_q_in=%p req->req_q_out=%p " 2971 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2972 req->req_q_in, req->req_q_out, 2973 rsp->rsp_q_in, rsp->rsp_q_out); 2974 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2975 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2976 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2977 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2978 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2979 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2980 2981 if (ha->isp_ops->initialize_adapter(base_vha)) { 2982 ql_log(ql_log_fatal, base_vha, 0x00d6, 2983 "Failed to initialize adapter - Adapter flags %x.\n", 2984 base_vha->device_flags); 2985 2986 if (IS_QLA82XX(ha)) { 2987 qla82xx_idc_lock(ha); 2988 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2989 QLA8XXX_DEV_FAILED); 2990 qla82xx_idc_unlock(ha); 2991 ql_log(ql_log_fatal, base_vha, 0x00d7, 2992 "HW State: FAILED.\n"); 2993 } else if (IS_QLA8044(ha)) { 2994 qla8044_idc_lock(ha); 2995 qla8044_wr_direct(base_vha, 2996 QLA8044_CRB_DEV_STATE_INDEX, 2997 QLA8XXX_DEV_FAILED); 2998 qla8044_idc_unlock(ha); 2999 ql_log(ql_log_fatal, base_vha, 0x0150, 3000 "HW State: FAILED.\n"); 3001 } 3002 3003 ret = -ENODEV; 3004 goto probe_failed; 3005 } 3006 3007 if (IS_QLAFX00(ha)) 3008 host->can_queue = QLAFX00_MAX_CANQUEUE; 3009 else 3010 host->can_queue = req->num_outstanding_cmds - 10; 3011 3012 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3013 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3014 host->can_queue, base_vha->req, 3015 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3016 3017 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) { 3018 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 3019 /* Create start of day qpairs for Block MQ */ 3020 if (shost_use_blk_mq(host)) { 3021 for (i = 0; i < ha->max_qpairs; i++) 3022 qla2xxx_create_qpair(base_vha, 5, 0); 3023 } 3024 } 3025 3026 if (ha->flags.running_gold_fw) 3027 goto skip_dpc; 3028 3029 /* 3030 * Startup the kernel thread for this host adapter 3031 */ 3032 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3033 "%s_dpc", base_vha->host_str); 3034 if (IS_ERR(ha->dpc_thread)) { 3035 ql_log(ql_log_fatal, base_vha, 0x00ed, 3036 "Failed to start DPC thread.\n"); 3037 ret = PTR_ERR(ha->dpc_thread); 3038 goto probe_failed; 3039 } 3040 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3041 "DPC thread started successfully.\n"); 3042 3043 /* 3044 * If we're not coming up in initiator mode, we might sit for 3045 * a while without waking up the dpc thread, which leads to a 3046 * stuck process warning. So just kick the dpc once here and 3047 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3048 */ 3049 qla2xxx_wake_dpc(base_vha); 3050 3051 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3052 3053 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3054 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3055 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3056 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3057 3058 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3059 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3060 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3061 INIT_WORK(&ha->idc_state_handler, 3062 qla83xx_idc_state_handler_work); 3063 INIT_WORK(&ha->nic_core_unrecoverable, 3064 qla83xx_nic_core_unrecoverable_work); 3065 } 3066 3067 skip_dpc: 3068 list_add_tail(&base_vha->list, &ha->vp_list); 3069 base_vha->host->irq = ha->pdev->irq; 3070 3071 /* Initialized the timer */ 3072 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 3073 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3074 "Started qla2x00_timer with " 3075 "interval=%d.\n", WATCH_INTERVAL); 3076 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3077 "Detected hba at address=%p.\n", 3078 ha); 3079 3080 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3081 if (ha->fw_attributes & BIT_4) { 3082 int prot = 0, guard; 3083 base_vha->flags.difdix_supported = 1; 3084 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3085 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3086 if (ql2xenabledif == 1) 3087 prot = SHOST_DIX_TYPE0_PROTECTION; 3088 scsi_host_set_prot(host, 3089 prot | SHOST_DIF_TYPE1_PROTECTION 3090 | SHOST_DIF_TYPE2_PROTECTION 3091 | SHOST_DIF_TYPE3_PROTECTION 3092 | SHOST_DIX_TYPE1_PROTECTION 3093 | SHOST_DIX_TYPE2_PROTECTION 3094 | SHOST_DIX_TYPE3_PROTECTION); 3095 3096 guard = SHOST_DIX_GUARD_CRC; 3097 3098 if (IS_PI_IPGUARD_CAPABLE(ha) && 3099 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3100 guard |= SHOST_DIX_GUARD_IP; 3101 3102 scsi_host_set_guard(host, guard); 3103 } else 3104 base_vha->flags.difdix_supported = 0; 3105 } 3106 3107 ha->isp_ops->enable_intrs(ha); 3108 3109 if (IS_QLAFX00(ha)) { 3110 ret = qlafx00_fx_disc(base_vha, 3111 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3112 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3113 QLA_SG_ALL : 128; 3114 } 3115 3116 ret = scsi_add_host(host, &pdev->dev); 3117 if (ret) 3118 goto probe_failed; 3119 3120 base_vha->flags.init_done = 1; 3121 base_vha->flags.online = 1; 3122 ha->prev_minidump_failed = 0; 3123 3124 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3125 "Init done and hba is online.\n"); 3126 3127 if (qla_ini_mode_enabled(base_vha)) 3128 scsi_scan_host(host); 3129 else 3130 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3131 "skipping scsi_scan_host() for non-initiator port\n"); 3132 3133 qla2x00_alloc_sysfs_attr(base_vha); 3134 3135 if (IS_QLAFX00(ha)) { 3136 ret = qlafx00_fx_disc(base_vha, 3137 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3138 3139 /* Register system information */ 3140 ret = qlafx00_fx_disc(base_vha, 3141 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3142 } 3143 3144 qla2x00_init_host_attr(base_vha); 3145 3146 qla2x00_dfs_setup(base_vha); 3147 3148 ql_log(ql_log_info, base_vha, 0x00fb, 3149 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3150 ql_log(ql_log_info, base_vha, 0x00fc, 3151 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3152 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3153 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3154 base_vha->host_no, 3155 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3156 3157 qlt_add_target(ha, base_vha); 3158 3159 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3160 3161 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3162 return -ENODEV; 3163 3164 return 0; 3165 3166 probe_init_failed: 3167 qla2x00_free_req_que(ha, req); 3168 ha->req_q_map[0] = NULL; 3169 clear_bit(0, ha->req_qid_map); 3170 qla2x00_free_rsp_que(ha, rsp); 3171 ha->rsp_q_map[0] = NULL; 3172 clear_bit(0, ha->rsp_qid_map); 3173 ha->max_req_queues = ha->max_rsp_queues = 0; 3174 3175 probe_failed: 3176 if (base_vha->timer_active) 3177 qla2x00_stop_timer(base_vha); 3178 base_vha->flags.online = 0; 3179 if (ha->dpc_thread) { 3180 struct task_struct *t = ha->dpc_thread; 3181 3182 ha->dpc_thread = NULL; 3183 kthread_stop(t); 3184 } 3185 3186 qla2x00_free_device(base_vha); 3187 3188 scsi_host_put(base_vha->host); 3189 3190 probe_hw_failed: 3191 qla2x00_clear_drv_active(ha); 3192 3193 iospace_config_failed: 3194 if (IS_P3P_TYPE(ha)) { 3195 if (!ha->nx_pcibase) 3196 iounmap((device_reg_t *)ha->nx_pcibase); 3197 if (!ql2xdbwr) 3198 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3199 } else { 3200 if (ha->iobase) 3201 iounmap(ha->iobase); 3202 if (ha->cregbase) 3203 iounmap(ha->cregbase); 3204 } 3205 pci_release_selected_regions(ha->pdev, ha->bars); 3206 kfree(ha); 3207 ha = NULL; 3208 3209 probe_out: 3210 pci_disable_device(pdev); 3211 return ret; 3212 } 3213 3214 static void 3215 qla2x00_shutdown(struct pci_dev *pdev) 3216 { 3217 scsi_qla_host_t *vha; 3218 struct qla_hw_data *ha; 3219 3220 if (!atomic_read(&pdev->enable_cnt)) 3221 return; 3222 3223 vha = pci_get_drvdata(pdev); 3224 ha = vha->hw; 3225 3226 /* Notify ISPFX00 firmware */ 3227 if (IS_QLAFX00(ha)) 3228 qlafx00_driver_shutdown(vha, 20); 3229 3230 /* Turn-off FCE trace */ 3231 if (ha->flags.fce_enabled) { 3232 qla2x00_disable_fce_trace(vha, NULL, NULL); 3233 ha->flags.fce_enabled = 0; 3234 } 3235 3236 /* Turn-off EFT trace */ 3237 if (ha->eft) 3238 qla2x00_disable_eft_trace(vha); 3239 3240 /* Stop currently executing firmware. */ 3241 qla2x00_try_to_stop_firmware(vha); 3242 3243 /* Turn adapter off line */ 3244 vha->flags.online = 0; 3245 3246 /* turn-off interrupts on the card */ 3247 if (ha->interrupts_on) { 3248 vha->flags.init_done = 0; 3249 ha->isp_ops->disable_intrs(ha); 3250 } 3251 3252 qla2x00_free_irqs(vha); 3253 3254 qla2x00_free_fw_dump(ha); 3255 3256 pci_disable_pcie_error_reporting(pdev); 3257 pci_disable_device(pdev); 3258 } 3259 3260 /* Deletes all the virtual ports for a given ha */ 3261 static void 3262 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3263 { 3264 scsi_qla_host_t *vha; 3265 unsigned long flags; 3266 3267 mutex_lock(&ha->vport_lock); 3268 while (ha->cur_vport_count) { 3269 spin_lock_irqsave(&ha->vport_slock, flags); 3270 3271 BUG_ON(base_vha->list.next == &ha->vp_list); 3272 /* This assumes first entry in ha->vp_list is always base vha */ 3273 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3274 scsi_host_get(vha->host); 3275 3276 spin_unlock_irqrestore(&ha->vport_slock, flags); 3277 mutex_unlock(&ha->vport_lock); 3278 3279 fc_vport_terminate(vha->fc_vport); 3280 scsi_host_put(vha->host); 3281 3282 mutex_lock(&ha->vport_lock); 3283 } 3284 mutex_unlock(&ha->vport_lock); 3285 } 3286 3287 /* Stops all deferred work threads */ 3288 static void 3289 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3290 { 3291 /* Cancel all work and destroy DPC workqueues */ 3292 if (ha->dpc_lp_wq) { 3293 cancel_work_sync(&ha->idc_aen); 3294 destroy_workqueue(ha->dpc_lp_wq); 3295 ha->dpc_lp_wq = NULL; 3296 } 3297 3298 if (ha->dpc_hp_wq) { 3299 cancel_work_sync(&ha->nic_core_reset); 3300 cancel_work_sync(&ha->idc_state_handler); 3301 cancel_work_sync(&ha->nic_core_unrecoverable); 3302 destroy_workqueue(ha->dpc_hp_wq); 3303 ha->dpc_hp_wq = NULL; 3304 } 3305 3306 /* Kill the kernel thread for this host */ 3307 if (ha->dpc_thread) { 3308 struct task_struct *t = ha->dpc_thread; 3309 3310 /* 3311 * qla2xxx_wake_dpc checks for ->dpc_thread 3312 * so we need to zero it out. 3313 */ 3314 ha->dpc_thread = NULL; 3315 kthread_stop(t); 3316 } 3317 } 3318 3319 static void 3320 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3321 { 3322 if (IS_QLA82XX(ha)) { 3323 3324 iounmap((device_reg_t *)ha->nx_pcibase); 3325 if (!ql2xdbwr) 3326 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3327 } else { 3328 if (ha->iobase) 3329 iounmap(ha->iobase); 3330 3331 if (ha->cregbase) 3332 iounmap(ha->cregbase); 3333 3334 if (ha->mqiobase) 3335 iounmap(ha->mqiobase); 3336 3337 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3338 iounmap(ha->msixbase); 3339 } 3340 } 3341 3342 static void 3343 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3344 { 3345 if (IS_QLA8044(ha)) { 3346 qla8044_idc_lock(ha); 3347 qla8044_clear_drv_active(ha); 3348 qla8044_idc_unlock(ha); 3349 } else if (IS_QLA82XX(ha)) { 3350 qla82xx_idc_lock(ha); 3351 qla82xx_clear_drv_active(ha); 3352 qla82xx_idc_unlock(ha); 3353 } 3354 } 3355 3356 static void 3357 qla2x00_remove_one(struct pci_dev *pdev) 3358 { 3359 scsi_qla_host_t *base_vha; 3360 struct qla_hw_data *ha; 3361 3362 base_vha = pci_get_drvdata(pdev); 3363 ha = base_vha->hw; 3364 3365 /* Indicate device removal to prevent future board_disable and wait 3366 * until any pending board_disable has completed. */ 3367 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3368 cancel_work_sync(&ha->board_disable); 3369 3370 /* 3371 * If the PCI device is disabled then there was a PCI-disconnect and 3372 * qla2x00_disable_board_on_pci_error has taken care of most of the 3373 * resources. 3374 */ 3375 if (!atomic_read(&pdev->enable_cnt)) { 3376 scsi_host_put(base_vha->host); 3377 kfree(ha); 3378 pci_set_drvdata(pdev, NULL); 3379 return; 3380 } 3381 3382 qla2x00_wait_for_hba_ready(base_vha); 3383 3384 /* if UNLOAD flag is already set, then continue unload, 3385 * where it was set first. 3386 */ 3387 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3388 return; 3389 3390 set_bit(UNLOADING, &base_vha->dpc_flags); 3391 3392 if (IS_QLAFX00(ha)) 3393 qlafx00_driver_shutdown(base_vha, 20); 3394 3395 qla2x00_delete_all_vps(ha, base_vha); 3396 3397 if (IS_QLA8031(ha)) { 3398 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3399 "Clearing fcoe driver presence.\n"); 3400 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3401 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3402 "Error while clearing DRV-Presence.\n"); 3403 } 3404 3405 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3406 3407 qla2x00_dfs_remove(base_vha); 3408 3409 qla84xx_put_chip(base_vha); 3410 3411 /* Laser should be disabled only for ISP2031 */ 3412 if (IS_QLA2031(ha)) 3413 qla83xx_disable_laser(base_vha); 3414 3415 /* Disable timer */ 3416 if (base_vha->timer_active) 3417 qla2x00_stop_timer(base_vha); 3418 3419 base_vha->flags.online = 0; 3420 3421 /* free DMA memory */ 3422 if (ha->exlogin_buf) 3423 qla2x00_free_exlogin_buffer(ha); 3424 3425 /* free DMA memory */ 3426 if (ha->exchoffld_buf) 3427 qla2x00_free_exchoffld_buffer(ha); 3428 3429 qla2x00_destroy_deferred_work(ha); 3430 3431 qlt_remove_target(ha, base_vha); 3432 3433 qla2x00_free_sysfs_attr(base_vha, true); 3434 3435 fc_remove_host(base_vha->host); 3436 3437 scsi_remove_host(base_vha->host); 3438 3439 qla2x00_free_device(base_vha); 3440 3441 qla2x00_clear_drv_active(ha); 3442 3443 scsi_host_put(base_vha->host); 3444 3445 qla2x00_unmap_iobases(ha); 3446 3447 pci_release_selected_regions(ha->pdev, ha->bars); 3448 kfree(ha); 3449 ha = NULL; 3450 3451 pci_disable_pcie_error_reporting(pdev); 3452 3453 pci_disable_device(pdev); 3454 } 3455 3456 static void 3457 qla2x00_free_device(scsi_qla_host_t *vha) 3458 { 3459 struct qla_hw_data *ha = vha->hw; 3460 3461 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3462 3463 /* Disable timer */ 3464 if (vha->timer_active) 3465 qla2x00_stop_timer(vha); 3466 3467 qla25xx_delete_queues(vha); 3468 3469 if (ha->flags.fce_enabled) 3470 qla2x00_disable_fce_trace(vha, NULL, NULL); 3471 3472 if (ha->eft) 3473 qla2x00_disable_eft_trace(vha); 3474 3475 /* Stop currently executing firmware. */ 3476 qla2x00_try_to_stop_firmware(vha); 3477 3478 vha->flags.online = 0; 3479 3480 /* turn-off interrupts on the card */ 3481 if (ha->interrupts_on) { 3482 vha->flags.init_done = 0; 3483 ha->isp_ops->disable_intrs(ha); 3484 } 3485 3486 qla2x00_free_fcports(vha); 3487 3488 qla2x00_free_irqs(vha); 3489 3490 /* Flush the work queue and remove it */ 3491 if (ha->wq) { 3492 flush_workqueue(ha->wq); 3493 destroy_workqueue(ha->wq); 3494 ha->wq = NULL; 3495 } 3496 3497 3498 qla2x00_mem_free(ha); 3499 3500 qla82xx_md_free(vha); 3501 3502 qla2x00_free_queues(ha); 3503 } 3504 3505 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3506 { 3507 fc_port_t *fcport, *tfcport; 3508 3509 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3510 list_del(&fcport->list); 3511 qla2x00_clear_loop_id(fcport); 3512 kfree(fcport); 3513 fcport = NULL; 3514 } 3515 } 3516 3517 static inline void 3518 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3519 int defer) 3520 { 3521 struct fc_rport *rport; 3522 scsi_qla_host_t *base_vha; 3523 unsigned long flags; 3524 3525 if (!fcport->rport) 3526 return; 3527 3528 rport = fcport->rport; 3529 if (defer) { 3530 base_vha = pci_get_drvdata(vha->hw->pdev); 3531 spin_lock_irqsave(vha->host->host_lock, flags); 3532 fcport->drport = rport; 3533 spin_unlock_irqrestore(vha->host->host_lock, flags); 3534 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3535 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3536 qla2xxx_wake_dpc(base_vha); 3537 } else { 3538 int now; 3539 if (rport) 3540 fc_remote_port_delete(rport); 3541 qlt_do_generation_tick(vha, &now); 3542 qlt_fc_port_deleted(vha, fcport, now); 3543 } 3544 } 3545 3546 /* 3547 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3548 * 3549 * Input: ha = adapter block pointer. fcport = port structure pointer. 3550 * 3551 * Return: None. 3552 * 3553 * Context: 3554 */ 3555 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3556 int do_login, int defer) 3557 { 3558 if (IS_QLAFX00(vha->hw)) { 3559 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3560 qla2x00_schedule_rport_del(vha, fcport, defer); 3561 return; 3562 } 3563 3564 if (atomic_read(&fcport->state) == FCS_ONLINE && 3565 vha->vp_idx == fcport->vha->vp_idx) { 3566 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3567 qla2x00_schedule_rport_del(vha, fcport, defer); 3568 } 3569 /* 3570 * We may need to retry the login, so don't change the state of the 3571 * port but do the retries. 3572 */ 3573 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3574 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3575 3576 if (!do_login) 3577 return; 3578 3579 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3580 3581 if (fcport->login_retry == 0) { 3582 fcport->login_retry = vha->hw->login_retry_count; 3583 3584 ql_dbg(ql_dbg_disc, vha, 0x2067, 3585 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3586 fcport->port_name, fcport->loop_id, fcport->login_retry); 3587 } 3588 } 3589 3590 /* 3591 * qla2x00_mark_all_devices_lost 3592 * Updates fcport state when device goes offline. 3593 * 3594 * Input: 3595 * ha = adapter block pointer. 3596 * fcport = port structure pointer. 3597 * 3598 * Return: 3599 * None. 3600 * 3601 * Context: 3602 */ 3603 void 3604 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3605 { 3606 fc_port_t *fcport; 3607 3608 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3609 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3610 continue; 3611 3612 /* 3613 * No point in marking the device as lost, if the device is 3614 * already DEAD. 3615 */ 3616 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3617 continue; 3618 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3619 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3620 if (defer) 3621 qla2x00_schedule_rport_del(vha, fcport, defer); 3622 else if (vha->vp_idx == fcport->vha->vp_idx) 3623 qla2x00_schedule_rport_del(vha, fcport, defer); 3624 } 3625 } 3626 } 3627 3628 /* 3629 * qla2x00_mem_alloc 3630 * Allocates adapter memory. 3631 * 3632 * Returns: 3633 * 0 = success. 3634 * !0 = failure. 3635 */ 3636 static int 3637 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3638 struct req_que **req, struct rsp_que **rsp) 3639 { 3640 char name[16]; 3641 3642 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3643 &ha->init_cb_dma, GFP_KERNEL); 3644 if (!ha->init_cb) 3645 goto fail; 3646 3647 if (qlt_mem_alloc(ha) < 0) 3648 goto fail_free_init_cb; 3649 3650 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3651 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3652 if (!ha->gid_list) 3653 goto fail_free_tgt_mem; 3654 3655 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3656 if (!ha->srb_mempool) 3657 goto fail_free_gid_list; 3658 3659 if (IS_P3P_TYPE(ha)) { 3660 /* Allocate cache for CT6 Ctx. */ 3661 if (!ctx_cachep) { 3662 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3663 sizeof(struct ct6_dsd), 0, 3664 SLAB_HWCACHE_ALIGN, NULL); 3665 if (!ctx_cachep) 3666 goto fail_free_srb_mempool; 3667 } 3668 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3669 ctx_cachep); 3670 if (!ha->ctx_mempool) 3671 goto fail_free_srb_mempool; 3672 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3673 "ctx_cachep=%p ctx_mempool=%p.\n", 3674 ctx_cachep, ha->ctx_mempool); 3675 } 3676 3677 /* Get memory for cached NVRAM */ 3678 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3679 if (!ha->nvram) 3680 goto fail_free_ctx_mempool; 3681 3682 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3683 ha->pdev->device); 3684 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3685 DMA_POOL_SIZE, 8, 0); 3686 if (!ha->s_dma_pool) 3687 goto fail_free_nvram; 3688 3689 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3690 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3691 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3692 3693 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3694 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3695 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3696 if (!ha->dl_dma_pool) { 3697 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3698 "Failed to allocate memory for dl_dma_pool.\n"); 3699 goto fail_s_dma_pool; 3700 } 3701 3702 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3703 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3704 if (!ha->fcp_cmnd_dma_pool) { 3705 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3706 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3707 goto fail_dl_dma_pool; 3708 } 3709 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3710 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3711 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3712 } 3713 3714 /* Allocate memory for SNS commands */ 3715 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3716 /* Get consistent memory allocated for SNS commands */ 3717 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3718 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3719 if (!ha->sns_cmd) 3720 goto fail_dma_pool; 3721 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3722 "sns_cmd: %p.\n", ha->sns_cmd); 3723 } else { 3724 /* Get consistent memory allocated for MS IOCB */ 3725 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3726 &ha->ms_iocb_dma); 3727 if (!ha->ms_iocb) 3728 goto fail_dma_pool; 3729 /* Get consistent memory allocated for CT SNS commands */ 3730 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3731 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3732 if (!ha->ct_sns) 3733 goto fail_free_ms_iocb; 3734 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3735 "ms_iocb=%p ct_sns=%p.\n", 3736 ha->ms_iocb, ha->ct_sns); 3737 } 3738 3739 /* Allocate memory for request ring */ 3740 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3741 if (!*req) { 3742 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3743 "Failed to allocate memory for req.\n"); 3744 goto fail_req; 3745 } 3746 (*req)->length = req_len; 3747 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3748 ((*req)->length + 1) * sizeof(request_t), 3749 &(*req)->dma, GFP_KERNEL); 3750 if (!(*req)->ring) { 3751 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3752 "Failed to allocate memory for req_ring.\n"); 3753 goto fail_req_ring; 3754 } 3755 /* Allocate memory for response ring */ 3756 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3757 if (!*rsp) { 3758 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3759 "Failed to allocate memory for rsp.\n"); 3760 goto fail_rsp; 3761 } 3762 (*rsp)->hw = ha; 3763 (*rsp)->length = rsp_len; 3764 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3765 ((*rsp)->length + 1) * sizeof(response_t), 3766 &(*rsp)->dma, GFP_KERNEL); 3767 if (!(*rsp)->ring) { 3768 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3769 "Failed to allocate memory for rsp_ring.\n"); 3770 goto fail_rsp_ring; 3771 } 3772 (*req)->rsp = *rsp; 3773 (*rsp)->req = *req; 3774 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3775 "req=%p req->length=%d req->ring=%p rsp=%p " 3776 "rsp->length=%d rsp->ring=%p.\n", 3777 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3778 (*rsp)->ring); 3779 /* Allocate memory for NVRAM data for vports */ 3780 if (ha->nvram_npiv_size) { 3781 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3782 ha->nvram_npiv_size, GFP_KERNEL); 3783 if (!ha->npiv_info) { 3784 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3785 "Failed to allocate memory for npiv_info.\n"); 3786 goto fail_npiv_info; 3787 } 3788 } else 3789 ha->npiv_info = NULL; 3790 3791 /* Get consistent memory allocated for EX-INIT-CB. */ 3792 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3793 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3794 &ha->ex_init_cb_dma); 3795 if (!ha->ex_init_cb) 3796 goto fail_ex_init_cb; 3797 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3798 "ex_init_cb=%p.\n", ha->ex_init_cb); 3799 } 3800 3801 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3802 3803 /* Get consistent memory allocated for Async Port-Database. */ 3804 if (!IS_FWI2_CAPABLE(ha)) { 3805 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3806 &ha->async_pd_dma); 3807 if (!ha->async_pd) 3808 goto fail_async_pd; 3809 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3810 "async_pd=%p.\n", ha->async_pd); 3811 } 3812 3813 INIT_LIST_HEAD(&ha->vp_list); 3814 3815 /* Allocate memory for our loop_id bitmap */ 3816 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3817 GFP_KERNEL); 3818 if (!ha->loop_id_map) 3819 goto fail_loop_id_map; 3820 else { 3821 qla2x00_set_reserved_loop_ids(ha); 3822 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3823 "loop_id_map=%p.\n", ha->loop_id_map); 3824 } 3825 3826 return 0; 3827 3828 fail_loop_id_map: 3829 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3830 fail_async_pd: 3831 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3832 fail_ex_init_cb: 3833 kfree(ha->npiv_info); 3834 fail_npiv_info: 3835 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3836 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3837 (*rsp)->ring = NULL; 3838 (*rsp)->dma = 0; 3839 fail_rsp_ring: 3840 kfree(*rsp); 3841 fail_rsp: 3842 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3843 sizeof(request_t), (*req)->ring, (*req)->dma); 3844 (*req)->ring = NULL; 3845 (*req)->dma = 0; 3846 fail_req_ring: 3847 kfree(*req); 3848 fail_req: 3849 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3850 ha->ct_sns, ha->ct_sns_dma); 3851 ha->ct_sns = NULL; 3852 ha->ct_sns_dma = 0; 3853 fail_free_ms_iocb: 3854 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3855 ha->ms_iocb = NULL; 3856 ha->ms_iocb_dma = 0; 3857 3858 if (ha->sns_cmd) 3859 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3860 ha->sns_cmd, ha->sns_cmd_dma); 3861 fail_dma_pool: 3862 if (IS_QLA82XX(ha) || ql2xenabledif) { 3863 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3864 ha->fcp_cmnd_dma_pool = NULL; 3865 } 3866 fail_dl_dma_pool: 3867 if (IS_QLA82XX(ha) || ql2xenabledif) { 3868 dma_pool_destroy(ha->dl_dma_pool); 3869 ha->dl_dma_pool = NULL; 3870 } 3871 fail_s_dma_pool: 3872 dma_pool_destroy(ha->s_dma_pool); 3873 ha->s_dma_pool = NULL; 3874 fail_free_nvram: 3875 kfree(ha->nvram); 3876 ha->nvram = NULL; 3877 fail_free_ctx_mempool: 3878 if (ha->ctx_mempool) 3879 mempool_destroy(ha->ctx_mempool); 3880 ha->ctx_mempool = NULL; 3881 fail_free_srb_mempool: 3882 if (ha->srb_mempool) 3883 mempool_destroy(ha->srb_mempool); 3884 ha->srb_mempool = NULL; 3885 fail_free_gid_list: 3886 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3887 ha->gid_list, 3888 ha->gid_list_dma); 3889 ha->gid_list = NULL; 3890 ha->gid_list_dma = 0; 3891 fail_free_tgt_mem: 3892 qlt_mem_free(ha); 3893 fail_free_init_cb: 3894 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3895 ha->init_cb_dma); 3896 ha->init_cb = NULL; 3897 ha->init_cb_dma = 0; 3898 fail: 3899 ql_log(ql_log_fatal, NULL, 0x0030, 3900 "Memory allocation failure.\n"); 3901 return -ENOMEM; 3902 } 3903 3904 int 3905 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3906 { 3907 int rval; 3908 uint16_t size, max_cnt, temp; 3909 struct qla_hw_data *ha = vha->hw; 3910 3911 /* Return if we don't need to alloacate any extended logins */ 3912 if (!ql2xexlogins) 3913 return QLA_SUCCESS; 3914 3915 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3916 max_cnt = 0; 3917 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3918 if (rval != QLA_SUCCESS) { 3919 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3920 "Failed to get exlogin status.\n"); 3921 return rval; 3922 } 3923 3924 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3925 ha->exlogin_size = (size * temp); 3926 ql_log(ql_log_info, vha, 0xd024, 3927 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3928 max_cnt, size, temp); 3929 3930 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3931 ha->exlogin_size); 3932 3933 /* Get consistent memory for extended logins */ 3934 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 3935 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 3936 if (!ha->exlogin_buf) { 3937 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 3938 "Failed to allocate memory for exlogin_buf_dma.\n"); 3939 return -ENOMEM; 3940 } 3941 3942 /* Now configure the dma buffer */ 3943 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 3944 if (rval) { 3945 ql_log(ql_log_fatal, vha, 0x00cf, 3946 "Setup extended login buffer ****FAILED****.\n"); 3947 qla2x00_free_exlogin_buffer(ha); 3948 } 3949 3950 return rval; 3951 } 3952 3953 /* 3954 * qla2x00_free_exlogin_buffer 3955 * 3956 * Input: 3957 * ha = adapter block pointer 3958 */ 3959 void 3960 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 3961 { 3962 if (ha->exlogin_buf) { 3963 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 3964 ha->exlogin_buf, ha->exlogin_buf_dma); 3965 ha->exlogin_buf = NULL; 3966 ha->exlogin_size = 0; 3967 } 3968 } 3969 3970 int 3971 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 3972 { 3973 int rval; 3974 uint16_t size, max_cnt, temp; 3975 struct qla_hw_data *ha = vha->hw; 3976 3977 /* Return if we don't need to alloacate any extended logins */ 3978 if (!ql2xexchoffld) 3979 return QLA_SUCCESS; 3980 3981 ql_log(ql_log_info, vha, 0xd014, 3982 "Exchange offload count: %d.\n", ql2xexlogins); 3983 3984 max_cnt = 0; 3985 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 3986 if (rval != QLA_SUCCESS) { 3987 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 3988 "Failed to get exlogin status.\n"); 3989 return rval; 3990 } 3991 3992 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 3993 ha->exchoffld_size = (size * temp); 3994 ql_log(ql_log_info, vha, 0xd016, 3995 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 3996 max_cnt, size, temp); 3997 3998 ql_log(ql_log_info, vha, 0xd017, 3999 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 4000 4001 /* Get consistent memory for extended logins */ 4002 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4003 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4004 if (!ha->exchoffld_buf) { 4005 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4006 "Failed to allocate memory for exchoffld_buf_dma.\n"); 4007 return -ENOMEM; 4008 } 4009 4010 /* Now configure the dma buffer */ 4011 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 4012 if (rval) { 4013 ql_log(ql_log_fatal, vha, 0xd02e, 4014 "Setup exchange offload buffer ****FAILED****.\n"); 4015 qla2x00_free_exchoffld_buffer(ha); 4016 } 4017 4018 return rval; 4019 } 4020 4021 /* 4022 * qla2x00_free_exchoffld_buffer 4023 * 4024 * Input: 4025 * ha = adapter block pointer 4026 */ 4027 void 4028 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4029 { 4030 if (ha->exchoffld_buf) { 4031 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4032 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4033 ha->exchoffld_buf = NULL; 4034 ha->exchoffld_size = 0; 4035 } 4036 } 4037 4038 /* 4039 * qla2x00_free_fw_dump 4040 * Frees fw dump stuff. 4041 * 4042 * Input: 4043 * ha = adapter block pointer 4044 */ 4045 static void 4046 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4047 { 4048 if (ha->fce) 4049 dma_free_coherent(&ha->pdev->dev, 4050 FCE_SIZE, ha->fce, ha->fce_dma); 4051 4052 if (ha->eft) 4053 dma_free_coherent(&ha->pdev->dev, 4054 EFT_SIZE, ha->eft, ha->eft_dma); 4055 4056 if (ha->fw_dump) 4057 vfree(ha->fw_dump); 4058 if (ha->fw_dump_template) 4059 vfree(ha->fw_dump_template); 4060 4061 ha->fce = NULL; 4062 ha->fce_dma = 0; 4063 ha->eft = NULL; 4064 ha->eft_dma = 0; 4065 ha->fw_dumped = 0; 4066 ha->fw_dump_cap_flags = 0; 4067 ha->fw_dump_reading = 0; 4068 ha->fw_dump = NULL; 4069 ha->fw_dump_len = 0; 4070 ha->fw_dump_template = NULL; 4071 ha->fw_dump_template_len = 0; 4072 } 4073 4074 /* 4075 * qla2x00_mem_free 4076 * Frees all adapter allocated memory. 4077 * 4078 * Input: 4079 * ha = adapter block pointer. 4080 */ 4081 static void 4082 qla2x00_mem_free(struct qla_hw_data *ha) 4083 { 4084 qla2x00_free_fw_dump(ha); 4085 4086 if (ha->mctp_dump) 4087 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4088 ha->mctp_dump_dma); 4089 4090 if (ha->srb_mempool) 4091 mempool_destroy(ha->srb_mempool); 4092 4093 if (ha->dcbx_tlv) 4094 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4095 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4096 4097 if (ha->xgmac_data) 4098 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4099 ha->xgmac_data, ha->xgmac_data_dma); 4100 4101 if (ha->sns_cmd) 4102 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4103 ha->sns_cmd, ha->sns_cmd_dma); 4104 4105 if (ha->ct_sns) 4106 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4107 ha->ct_sns, ha->ct_sns_dma); 4108 4109 if (ha->sfp_data) 4110 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 4111 4112 if (ha->ms_iocb) 4113 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4114 4115 if (ha->ex_init_cb) 4116 dma_pool_free(ha->s_dma_pool, 4117 ha->ex_init_cb, ha->ex_init_cb_dma); 4118 4119 if (ha->async_pd) 4120 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4121 4122 if (ha->s_dma_pool) 4123 dma_pool_destroy(ha->s_dma_pool); 4124 4125 if (ha->gid_list) 4126 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4127 ha->gid_list, ha->gid_list_dma); 4128 4129 if (IS_QLA82XX(ha)) { 4130 if (!list_empty(&ha->gbl_dsd_list)) { 4131 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4132 4133 /* clean up allocated prev pool */ 4134 list_for_each_entry_safe(dsd_ptr, 4135 tdsd_ptr, &ha->gbl_dsd_list, list) { 4136 dma_pool_free(ha->dl_dma_pool, 4137 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4138 list_del(&dsd_ptr->list); 4139 kfree(dsd_ptr); 4140 } 4141 } 4142 } 4143 4144 if (ha->dl_dma_pool) 4145 dma_pool_destroy(ha->dl_dma_pool); 4146 4147 if (ha->fcp_cmnd_dma_pool) 4148 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4149 4150 if (ha->ctx_mempool) 4151 mempool_destroy(ha->ctx_mempool); 4152 4153 qlt_mem_free(ha); 4154 4155 if (ha->init_cb) 4156 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4157 ha->init_cb, ha->init_cb_dma); 4158 vfree(ha->optrom_buffer); 4159 kfree(ha->nvram); 4160 kfree(ha->npiv_info); 4161 kfree(ha->swl); 4162 kfree(ha->loop_id_map); 4163 4164 ha->srb_mempool = NULL; 4165 ha->ctx_mempool = NULL; 4166 ha->sns_cmd = NULL; 4167 ha->sns_cmd_dma = 0; 4168 ha->ct_sns = NULL; 4169 ha->ct_sns_dma = 0; 4170 ha->ms_iocb = NULL; 4171 ha->ms_iocb_dma = 0; 4172 ha->init_cb = NULL; 4173 ha->init_cb_dma = 0; 4174 ha->ex_init_cb = NULL; 4175 ha->ex_init_cb_dma = 0; 4176 ha->async_pd = NULL; 4177 ha->async_pd_dma = 0; 4178 4179 ha->s_dma_pool = NULL; 4180 ha->dl_dma_pool = NULL; 4181 ha->fcp_cmnd_dma_pool = NULL; 4182 4183 ha->gid_list = NULL; 4184 ha->gid_list_dma = 0; 4185 4186 ha->tgt.atio_ring = NULL; 4187 ha->tgt.atio_dma = 0; 4188 ha->tgt.tgt_vp_map = NULL; 4189 } 4190 4191 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4192 struct qla_hw_data *ha) 4193 { 4194 struct Scsi_Host *host; 4195 struct scsi_qla_host *vha = NULL; 4196 4197 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4198 if (host == NULL) { 4199 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4200 "Failed to allocate host from the scsi layer, aborting.\n"); 4201 goto fail; 4202 } 4203 4204 /* Clear our data area */ 4205 vha = shost_priv(host); 4206 memset(vha, 0, sizeof(scsi_qla_host_t)); 4207 4208 vha->host = host; 4209 vha->host_no = host->host_no; 4210 vha->hw = ha; 4211 4212 INIT_LIST_HEAD(&vha->vp_fcports); 4213 INIT_LIST_HEAD(&vha->work_list); 4214 INIT_LIST_HEAD(&vha->list); 4215 INIT_LIST_HEAD(&vha->qla_cmd_list); 4216 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4217 INIT_LIST_HEAD(&vha->logo_list); 4218 INIT_LIST_HEAD(&vha->plogi_ack_list); 4219 INIT_LIST_HEAD(&vha->qp_list); 4220 4221 spin_lock_init(&vha->work_lock); 4222 spin_lock_init(&vha->cmd_list_lock); 4223 4224 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4225 ql_dbg(ql_dbg_init, vha, 0x0041, 4226 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4227 vha->host, vha->hw, vha, 4228 dev_name(&(ha->pdev->dev))); 4229 4230 return vha; 4231 4232 fail: 4233 return vha; 4234 } 4235 4236 static struct qla_work_evt * 4237 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4238 { 4239 struct qla_work_evt *e; 4240 uint8_t bail; 4241 4242 QLA_VHA_MARK_BUSY(vha, bail); 4243 if (bail) 4244 return NULL; 4245 4246 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4247 if (!e) { 4248 QLA_VHA_MARK_NOT_BUSY(vha); 4249 return NULL; 4250 } 4251 4252 INIT_LIST_HEAD(&e->list); 4253 e->type = type; 4254 e->flags = QLA_EVT_FLAG_FREE; 4255 return e; 4256 } 4257 4258 static int 4259 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4260 { 4261 unsigned long flags; 4262 4263 spin_lock_irqsave(&vha->work_lock, flags); 4264 list_add_tail(&e->list, &vha->work_list); 4265 spin_unlock_irqrestore(&vha->work_lock, flags); 4266 qla2xxx_wake_dpc(vha); 4267 4268 return QLA_SUCCESS; 4269 } 4270 4271 int 4272 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4273 u32 data) 4274 { 4275 struct qla_work_evt *e; 4276 4277 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4278 if (!e) 4279 return QLA_FUNCTION_FAILED; 4280 4281 e->u.aen.code = code; 4282 e->u.aen.data = data; 4283 return qla2x00_post_work(vha, e); 4284 } 4285 4286 int 4287 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4288 { 4289 struct qla_work_evt *e; 4290 4291 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4292 if (!e) 4293 return QLA_FUNCTION_FAILED; 4294 4295 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4296 return qla2x00_post_work(vha, e); 4297 } 4298 4299 #define qla2x00_post_async_work(name, type) \ 4300 int qla2x00_post_async_##name##_work( \ 4301 struct scsi_qla_host *vha, \ 4302 fc_port_t *fcport, uint16_t *data) \ 4303 { \ 4304 struct qla_work_evt *e; \ 4305 \ 4306 e = qla2x00_alloc_work(vha, type); \ 4307 if (!e) \ 4308 return QLA_FUNCTION_FAILED; \ 4309 \ 4310 e->u.logio.fcport = fcport; \ 4311 if (data) { \ 4312 e->u.logio.data[0] = data[0]; \ 4313 e->u.logio.data[1] = data[1]; \ 4314 } \ 4315 return qla2x00_post_work(vha, e); \ 4316 } 4317 4318 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4319 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 4320 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4321 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4322 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4323 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4324 4325 int 4326 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4327 { 4328 struct qla_work_evt *e; 4329 4330 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4331 if (!e) 4332 return QLA_FUNCTION_FAILED; 4333 4334 e->u.uevent.code = code; 4335 return qla2x00_post_work(vha, e); 4336 } 4337 4338 static void 4339 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4340 { 4341 char event_string[40]; 4342 char *envp[] = { event_string, NULL }; 4343 4344 switch (code) { 4345 case QLA_UEVENT_CODE_FW_DUMP: 4346 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4347 vha->host_no); 4348 break; 4349 default: 4350 /* do nothing */ 4351 break; 4352 } 4353 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4354 } 4355 4356 int 4357 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4358 uint32_t *data, int cnt) 4359 { 4360 struct qla_work_evt *e; 4361 4362 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4363 if (!e) 4364 return QLA_FUNCTION_FAILED; 4365 4366 e->u.aenfx.evtcode = evtcode; 4367 e->u.aenfx.count = cnt; 4368 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4369 return qla2x00_post_work(vha, e); 4370 } 4371 4372 void 4373 qla2x00_do_work(struct scsi_qla_host *vha) 4374 { 4375 struct qla_work_evt *e, *tmp; 4376 unsigned long flags; 4377 LIST_HEAD(work); 4378 4379 spin_lock_irqsave(&vha->work_lock, flags); 4380 list_splice_init(&vha->work_list, &work); 4381 spin_unlock_irqrestore(&vha->work_lock, flags); 4382 4383 list_for_each_entry_safe(e, tmp, &work, list) { 4384 list_del_init(&e->list); 4385 4386 switch (e->type) { 4387 case QLA_EVT_AEN: 4388 fc_host_post_event(vha->host, fc_get_event_number(), 4389 e->u.aen.code, e->u.aen.data); 4390 break; 4391 case QLA_EVT_IDC_ACK: 4392 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4393 break; 4394 case QLA_EVT_ASYNC_LOGIN: 4395 qla2x00_async_login(vha, e->u.logio.fcport, 4396 e->u.logio.data); 4397 break; 4398 case QLA_EVT_ASYNC_LOGIN_DONE: 4399 qla2x00_async_login_done(vha, e->u.logio.fcport, 4400 e->u.logio.data); 4401 break; 4402 case QLA_EVT_ASYNC_LOGOUT: 4403 qla2x00_async_logout(vha, e->u.logio.fcport); 4404 break; 4405 case QLA_EVT_ASYNC_LOGOUT_DONE: 4406 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4407 e->u.logio.data); 4408 break; 4409 case QLA_EVT_ASYNC_ADISC: 4410 qla2x00_async_adisc(vha, e->u.logio.fcport, 4411 e->u.logio.data); 4412 break; 4413 case QLA_EVT_ASYNC_ADISC_DONE: 4414 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4415 e->u.logio.data); 4416 break; 4417 case QLA_EVT_UEVENT: 4418 qla2x00_uevent_emit(vha, e->u.uevent.code); 4419 break; 4420 case QLA_EVT_AENFX: 4421 qlafx00_process_aen(vha, e); 4422 break; 4423 } 4424 if (e->flags & QLA_EVT_FLAG_FREE) 4425 kfree(e); 4426 4427 /* For each work completed decrement vha ref count */ 4428 QLA_VHA_MARK_NOT_BUSY(vha); 4429 } 4430 } 4431 4432 /* Relogins all the fcports of a vport 4433 * Context: dpc thread 4434 */ 4435 void qla2x00_relogin(struct scsi_qla_host *vha) 4436 { 4437 fc_port_t *fcport; 4438 int status; 4439 uint16_t next_loopid = 0; 4440 struct qla_hw_data *ha = vha->hw; 4441 uint16_t data[2]; 4442 4443 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4444 /* 4445 * If the port is not ONLINE then try to login 4446 * to it if we haven't run out of retries. 4447 */ 4448 if (atomic_read(&fcport->state) != FCS_ONLINE && 4449 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4450 fcport->login_retry--; 4451 if (fcport->flags & FCF_FABRIC_DEVICE) { 4452 if (fcport->flags & FCF_FCP2_DEVICE) 4453 ha->isp_ops->fabric_logout(vha, 4454 fcport->loop_id, 4455 fcport->d_id.b.domain, 4456 fcport->d_id.b.area, 4457 fcport->d_id.b.al_pa); 4458 4459 if (fcport->loop_id == FC_NO_LOOP_ID) { 4460 fcport->loop_id = next_loopid = 4461 ha->min_external_loopid; 4462 status = qla2x00_find_new_loop_id( 4463 vha, fcport); 4464 if (status != QLA_SUCCESS) { 4465 /* Ran out of IDs to use */ 4466 break; 4467 } 4468 } 4469 4470 if (IS_ALOGIO_CAPABLE(ha)) { 4471 fcport->flags |= FCF_ASYNC_SENT; 4472 data[0] = 0; 4473 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4474 status = qla2x00_post_async_login_work( 4475 vha, fcport, data); 4476 if (status == QLA_SUCCESS) 4477 continue; 4478 /* Attempt a retry. */ 4479 status = 1; 4480 } else { 4481 status = qla2x00_fabric_login(vha, 4482 fcport, &next_loopid); 4483 if (status == QLA_SUCCESS) { 4484 int status2; 4485 uint8_t opts; 4486 4487 opts = 0; 4488 if (fcport->flags & 4489 FCF_FCP2_DEVICE) 4490 opts |= BIT_1; 4491 status2 = 4492 qla2x00_get_port_database( 4493 vha, fcport, opts); 4494 if (status2 != QLA_SUCCESS) 4495 status = 1; 4496 } 4497 } 4498 } else 4499 status = qla2x00_local_device_login(vha, 4500 fcport); 4501 4502 if (status == QLA_SUCCESS) { 4503 fcport->old_loop_id = fcport->loop_id; 4504 4505 ql_dbg(ql_dbg_disc, vha, 0x2003, 4506 "Port login OK: logged in ID 0x%x.\n", 4507 fcport->loop_id); 4508 4509 qla2x00_update_fcport(vha, fcport); 4510 4511 } else if (status == 1) { 4512 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4513 /* retry the login again */ 4514 ql_dbg(ql_dbg_disc, vha, 0x2007, 4515 "Retrying %d login again loop_id 0x%x.\n", 4516 fcport->login_retry, fcport->loop_id); 4517 } else { 4518 fcport->login_retry = 0; 4519 } 4520 4521 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4522 qla2x00_clear_loop_id(fcport); 4523 } 4524 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4525 break; 4526 } 4527 } 4528 4529 /* Schedule work on any of the dpc-workqueues */ 4530 void 4531 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4532 { 4533 struct qla_hw_data *ha = base_vha->hw; 4534 4535 switch (work_code) { 4536 case MBA_IDC_AEN: /* 0x8200 */ 4537 if (ha->dpc_lp_wq) 4538 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4539 break; 4540 4541 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4542 if (!ha->flags.nic_core_reset_hdlr_active) { 4543 if (ha->dpc_hp_wq) 4544 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4545 } else 4546 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4547 "NIC Core reset is already active. Skip " 4548 "scheduling it again.\n"); 4549 break; 4550 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4551 if (ha->dpc_hp_wq) 4552 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4553 break; 4554 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4555 if (ha->dpc_hp_wq) 4556 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4557 break; 4558 default: 4559 ql_log(ql_log_warn, base_vha, 0xb05f, 4560 "Unknown work-code=0x%x.\n", work_code); 4561 } 4562 4563 return; 4564 } 4565 4566 /* Work: Perform NIC Core Unrecoverable state handling */ 4567 void 4568 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4569 { 4570 struct qla_hw_data *ha = 4571 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4572 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4573 uint32_t dev_state = 0; 4574 4575 qla83xx_idc_lock(base_vha, 0); 4576 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4577 qla83xx_reset_ownership(base_vha); 4578 if (ha->flags.nic_core_reset_owner) { 4579 ha->flags.nic_core_reset_owner = 0; 4580 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4581 QLA8XXX_DEV_FAILED); 4582 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4583 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4584 } 4585 qla83xx_idc_unlock(base_vha, 0); 4586 } 4587 4588 /* Work: Execute IDC state handler */ 4589 void 4590 qla83xx_idc_state_handler_work(struct work_struct *work) 4591 { 4592 struct qla_hw_data *ha = 4593 container_of(work, struct qla_hw_data, idc_state_handler); 4594 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4595 uint32_t dev_state = 0; 4596 4597 qla83xx_idc_lock(base_vha, 0); 4598 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4599 if (dev_state == QLA8XXX_DEV_FAILED || 4600 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4601 qla83xx_idc_state_handler(base_vha); 4602 qla83xx_idc_unlock(base_vha, 0); 4603 } 4604 4605 static int 4606 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4607 { 4608 int rval = QLA_SUCCESS; 4609 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4610 uint32_t heart_beat_counter1, heart_beat_counter2; 4611 4612 do { 4613 if (time_after(jiffies, heart_beat_wait)) { 4614 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4615 "Nic Core f/w is not alive.\n"); 4616 rval = QLA_FUNCTION_FAILED; 4617 break; 4618 } 4619 4620 qla83xx_idc_lock(base_vha, 0); 4621 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4622 &heart_beat_counter1); 4623 qla83xx_idc_unlock(base_vha, 0); 4624 msleep(100); 4625 qla83xx_idc_lock(base_vha, 0); 4626 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4627 &heart_beat_counter2); 4628 qla83xx_idc_unlock(base_vha, 0); 4629 } while (heart_beat_counter1 == heart_beat_counter2); 4630 4631 return rval; 4632 } 4633 4634 /* Work: Perform NIC Core Reset handling */ 4635 void 4636 qla83xx_nic_core_reset_work(struct work_struct *work) 4637 { 4638 struct qla_hw_data *ha = 4639 container_of(work, struct qla_hw_data, nic_core_reset); 4640 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4641 uint32_t dev_state = 0; 4642 4643 if (IS_QLA2031(ha)) { 4644 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4645 ql_log(ql_log_warn, base_vha, 0xb081, 4646 "Failed to dump mctp\n"); 4647 return; 4648 } 4649 4650 if (!ha->flags.nic_core_reset_hdlr_active) { 4651 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4652 qla83xx_idc_lock(base_vha, 0); 4653 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4654 &dev_state); 4655 qla83xx_idc_unlock(base_vha, 0); 4656 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4657 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4658 "Nic Core f/w is alive.\n"); 4659 return; 4660 } 4661 } 4662 4663 ha->flags.nic_core_reset_hdlr_active = 1; 4664 if (qla83xx_nic_core_reset(base_vha)) { 4665 /* NIC Core reset failed. */ 4666 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4667 "NIC Core reset failed.\n"); 4668 } 4669 ha->flags.nic_core_reset_hdlr_active = 0; 4670 } 4671 } 4672 4673 /* Work: Handle 8200 IDC aens */ 4674 void 4675 qla83xx_service_idc_aen(struct work_struct *work) 4676 { 4677 struct qla_hw_data *ha = 4678 container_of(work, struct qla_hw_data, idc_aen); 4679 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4680 uint32_t dev_state, idc_control; 4681 4682 qla83xx_idc_lock(base_vha, 0); 4683 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4684 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4685 qla83xx_idc_unlock(base_vha, 0); 4686 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4687 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4688 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4689 "Application requested NIC Core Reset.\n"); 4690 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4691 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4692 QLA_SUCCESS) { 4693 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4694 "Other protocol driver requested NIC Core Reset.\n"); 4695 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4696 } 4697 } else if (dev_state == QLA8XXX_DEV_FAILED || 4698 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4699 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4700 } 4701 } 4702 4703 static void 4704 qla83xx_wait_logic(void) 4705 { 4706 int i; 4707 4708 /* Yield CPU */ 4709 if (!in_interrupt()) { 4710 /* 4711 * Wait about 200ms before retrying again. 4712 * This controls the number of retries for single 4713 * lock operation. 4714 */ 4715 msleep(100); 4716 schedule(); 4717 } else { 4718 for (i = 0; i < 20; i++) 4719 cpu_relax(); /* This a nop instr on i386 */ 4720 } 4721 } 4722 4723 static int 4724 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4725 { 4726 int rval; 4727 uint32_t data; 4728 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4729 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4730 struct qla_hw_data *ha = base_vha->hw; 4731 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4732 "Trying force recovery of the IDC lock.\n"); 4733 4734 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4735 if (rval) 4736 return rval; 4737 4738 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4739 return QLA_SUCCESS; 4740 } else { 4741 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4742 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4743 data); 4744 if (rval) 4745 return rval; 4746 4747 msleep(200); 4748 4749 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4750 &data); 4751 if (rval) 4752 return rval; 4753 4754 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4755 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4756 ~(idc_lck_rcvry_stage_mask)); 4757 rval = qla83xx_wr_reg(base_vha, 4758 QLA83XX_IDC_LOCK_RECOVERY, data); 4759 if (rval) 4760 return rval; 4761 4762 /* Forcefully perform IDC UnLock */ 4763 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4764 &data); 4765 if (rval) 4766 return rval; 4767 /* Clear lock-id by setting 0xff */ 4768 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4769 0xff); 4770 if (rval) 4771 return rval; 4772 /* Clear lock-recovery by setting 0x0 */ 4773 rval = qla83xx_wr_reg(base_vha, 4774 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4775 if (rval) 4776 return rval; 4777 } else 4778 return QLA_SUCCESS; 4779 } 4780 4781 return rval; 4782 } 4783 4784 static int 4785 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4786 { 4787 int rval = QLA_SUCCESS; 4788 uint32_t o_drv_lockid, n_drv_lockid; 4789 unsigned long lock_recovery_timeout; 4790 4791 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4792 retry_lockid: 4793 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4794 if (rval) 4795 goto exit; 4796 4797 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4798 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4799 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4800 return QLA_SUCCESS; 4801 else 4802 return QLA_FUNCTION_FAILED; 4803 } 4804 4805 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4806 if (rval) 4807 goto exit; 4808 4809 if (o_drv_lockid == n_drv_lockid) { 4810 qla83xx_wait_logic(); 4811 goto retry_lockid; 4812 } else 4813 return QLA_SUCCESS; 4814 4815 exit: 4816 return rval; 4817 } 4818 4819 void 4820 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4821 { 4822 uint16_t options = (requester_id << 15) | BIT_6; 4823 uint32_t data; 4824 uint32_t lock_owner; 4825 struct qla_hw_data *ha = base_vha->hw; 4826 4827 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4828 retry_lock: 4829 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4830 == QLA_SUCCESS) { 4831 if (data) { 4832 /* Setting lock-id to our function-number */ 4833 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4834 ha->portnum); 4835 } else { 4836 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4837 &lock_owner); 4838 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4839 "Failed to acquire IDC lock, acquired by %d, " 4840 "retrying...\n", lock_owner); 4841 4842 /* Retry/Perform IDC-Lock recovery */ 4843 if (qla83xx_idc_lock_recovery(base_vha) 4844 == QLA_SUCCESS) { 4845 qla83xx_wait_logic(); 4846 goto retry_lock; 4847 } else 4848 ql_log(ql_log_warn, base_vha, 0xb075, 4849 "IDC Lock recovery FAILED.\n"); 4850 } 4851 4852 } 4853 4854 return; 4855 4856 /* XXX: IDC-lock implementation using access-control mbx */ 4857 retry_lock2: 4858 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4859 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4860 "Failed to acquire IDC lock. retrying...\n"); 4861 /* Retry/Perform IDC-Lock recovery */ 4862 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4863 qla83xx_wait_logic(); 4864 goto retry_lock2; 4865 } else 4866 ql_log(ql_log_warn, base_vha, 0xb076, 4867 "IDC Lock recovery FAILED.\n"); 4868 } 4869 4870 return; 4871 } 4872 4873 void 4874 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4875 { 4876 #if 0 4877 uint16_t options = (requester_id << 15) | BIT_7; 4878 #endif 4879 uint16_t retry; 4880 uint32_t data; 4881 struct qla_hw_data *ha = base_vha->hw; 4882 4883 /* IDC-unlock implementation using driver-unlock/lock-id 4884 * remote registers 4885 */ 4886 retry = 0; 4887 retry_unlock: 4888 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4889 == QLA_SUCCESS) { 4890 if (data == ha->portnum) { 4891 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4892 /* Clearing lock-id by setting 0xff */ 4893 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4894 } else if (retry < 10) { 4895 /* SV: XXX: IDC unlock retrying needed here? */ 4896 4897 /* Retry for IDC-unlock */ 4898 qla83xx_wait_logic(); 4899 retry++; 4900 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4901 "Failed to release IDC lock, retrying=%d\n", retry); 4902 goto retry_unlock; 4903 } 4904 } else if (retry < 10) { 4905 /* Retry for IDC-unlock */ 4906 qla83xx_wait_logic(); 4907 retry++; 4908 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4909 "Failed to read drv-lockid, retrying=%d\n", retry); 4910 goto retry_unlock; 4911 } 4912 4913 return; 4914 4915 #if 0 4916 /* XXX: IDC-unlock implementation using access-control mbx */ 4917 retry = 0; 4918 retry_unlock2: 4919 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4920 if (retry < 10) { 4921 /* Retry for IDC-unlock */ 4922 qla83xx_wait_logic(); 4923 retry++; 4924 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4925 "Failed to release IDC lock, retrying=%d\n", retry); 4926 goto retry_unlock2; 4927 } 4928 } 4929 4930 return; 4931 #endif 4932 } 4933 4934 int 4935 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4936 { 4937 int rval = QLA_SUCCESS; 4938 struct qla_hw_data *ha = vha->hw; 4939 uint32_t drv_presence; 4940 4941 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4942 if (rval == QLA_SUCCESS) { 4943 drv_presence |= (1 << ha->portnum); 4944 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4945 drv_presence); 4946 } 4947 4948 return rval; 4949 } 4950 4951 int 4952 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4953 { 4954 int rval = QLA_SUCCESS; 4955 4956 qla83xx_idc_lock(vha, 0); 4957 rval = __qla83xx_set_drv_presence(vha); 4958 qla83xx_idc_unlock(vha, 0); 4959 4960 return rval; 4961 } 4962 4963 int 4964 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4965 { 4966 int rval = QLA_SUCCESS; 4967 struct qla_hw_data *ha = vha->hw; 4968 uint32_t drv_presence; 4969 4970 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4971 if (rval == QLA_SUCCESS) { 4972 drv_presence &= ~(1 << ha->portnum); 4973 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4974 drv_presence); 4975 } 4976 4977 return rval; 4978 } 4979 4980 int 4981 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4982 { 4983 int rval = QLA_SUCCESS; 4984 4985 qla83xx_idc_lock(vha, 0); 4986 rval = __qla83xx_clear_drv_presence(vha); 4987 qla83xx_idc_unlock(vha, 0); 4988 4989 return rval; 4990 } 4991 4992 static void 4993 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4994 { 4995 struct qla_hw_data *ha = vha->hw; 4996 uint32_t drv_ack, drv_presence; 4997 unsigned long ack_timeout; 4998 4999 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5000 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5001 while (1) { 5002 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5003 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5004 if ((drv_ack & drv_presence) == drv_presence) 5005 break; 5006 5007 if (time_after_eq(jiffies, ack_timeout)) { 5008 ql_log(ql_log_warn, vha, 0xb067, 5009 "RESET ACK TIMEOUT! drv_presence=0x%x " 5010 "drv_ack=0x%x\n", drv_presence, drv_ack); 5011 /* 5012 * The function(s) which did not ack in time are forced 5013 * to withdraw any further participation in the IDC 5014 * reset. 5015 */ 5016 if (drv_ack != drv_presence) 5017 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5018 drv_ack); 5019 break; 5020 } 5021 5022 qla83xx_idc_unlock(vha, 0); 5023 msleep(1000); 5024 qla83xx_idc_lock(vha, 0); 5025 } 5026 5027 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5028 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5029 } 5030 5031 static int 5032 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5033 { 5034 int rval = QLA_SUCCESS; 5035 uint32_t idc_control; 5036 5037 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5038 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5039 5040 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5041 __qla83xx_get_idc_control(vha, &idc_control); 5042 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5043 __qla83xx_set_idc_control(vha, 0); 5044 5045 qla83xx_idc_unlock(vha, 0); 5046 rval = qla83xx_restart_nic_firmware(vha); 5047 qla83xx_idc_lock(vha, 0); 5048 5049 if (rval != QLA_SUCCESS) { 5050 ql_log(ql_log_fatal, vha, 0xb06a, 5051 "Failed to restart NIC f/w.\n"); 5052 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5053 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5054 } else { 5055 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5056 "Success in restarting nic f/w.\n"); 5057 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5058 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5059 } 5060 5061 return rval; 5062 } 5063 5064 /* Assumes idc_lock always held on entry */ 5065 int 5066 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5067 { 5068 struct qla_hw_data *ha = base_vha->hw; 5069 int rval = QLA_SUCCESS; 5070 unsigned long dev_init_timeout; 5071 uint32_t dev_state; 5072 5073 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5074 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5075 5076 while (1) { 5077 5078 if (time_after_eq(jiffies, dev_init_timeout)) { 5079 ql_log(ql_log_warn, base_vha, 0xb06e, 5080 "Initialization TIMEOUT!\n"); 5081 /* Init timeout. Disable further NIC Core 5082 * communication. 5083 */ 5084 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5085 QLA8XXX_DEV_FAILED); 5086 ql_log(ql_log_info, base_vha, 0xb06f, 5087 "HW State: FAILED.\n"); 5088 } 5089 5090 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5091 switch (dev_state) { 5092 case QLA8XXX_DEV_READY: 5093 if (ha->flags.nic_core_reset_owner) 5094 qla83xx_idc_audit(base_vha, 5095 IDC_AUDIT_COMPLETION); 5096 ha->flags.nic_core_reset_owner = 0; 5097 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5098 "Reset_owner reset by 0x%x.\n", 5099 ha->portnum); 5100 goto exit; 5101 case QLA8XXX_DEV_COLD: 5102 if (ha->flags.nic_core_reset_owner) 5103 rval = qla83xx_device_bootstrap(base_vha); 5104 else { 5105 /* Wait for AEN to change device-state */ 5106 qla83xx_idc_unlock(base_vha, 0); 5107 msleep(1000); 5108 qla83xx_idc_lock(base_vha, 0); 5109 } 5110 break; 5111 case QLA8XXX_DEV_INITIALIZING: 5112 /* Wait for AEN to change device-state */ 5113 qla83xx_idc_unlock(base_vha, 0); 5114 msleep(1000); 5115 qla83xx_idc_lock(base_vha, 0); 5116 break; 5117 case QLA8XXX_DEV_NEED_RESET: 5118 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5119 qla83xx_need_reset_handler(base_vha); 5120 else { 5121 /* Wait for AEN to change device-state */ 5122 qla83xx_idc_unlock(base_vha, 0); 5123 msleep(1000); 5124 qla83xx_idc_lock(base_vha, 0); 5125 } 5126 /* reset timeout value after need reset handler */ 5127 dev_init_timeout = jiffies + 5128 (ha->fcoe_dev_init_timeout * HZ); 5129 break; 5130 case QLA8XXX_DEV_NEED_QUIESCENT: 5131 /* XXX: DEBUG for now */ 5132 qla83xx_idc_unlock(base_vha, 0); 5133 msleep(1000); 5134 qla83xx_idc_lock(base_vha, 0); 5135 break; 5136 case QLA8XXX_DEV_QUIESCENT: 5137 /* XXX: DEBUG for now */ 5138 if (ha->flags.quiesce_owner) 5139 goto exit; 5140 5141 qla83xx_idc_unlock(base_vha, 0); 5142 msleep(1000); 5143 qla83xx_idc_lock(base_vha, 0); 5144 dev_init_timeout = jiffies + 5145 (ha->fcoe_dev_init_timeout * HZ); 5146 break; 5147 case QLA8XXX_DEV_FAILED: 5148 if (ha->flags.nic_core_reset_owner) 5149 qla83xx_idc_audit(base_vha, 5150 IDC_AUDIT_COMPLETION); 5151 ha->flags.nic_core_reset_owner = 0; 5152 __qla83xx_clear_drv_presence(base_vha); 5153 qla83xx_idc_unlock(base_vha, 0); 5154 qla8xxx_dev_failed_handler(base_vha); 5155 rval = QLA_FUNCTION_FAILED; 5156 qla83xx_idc_lock(base_vha, 0); 5157 goto exit; 5158 case QLA8XXX_BAD_VALUE: 5159 qla83xx_idc_unlock(base_vha, 0); 5160 msleep(1000); 5161 qla83xx_idc_lock(base_vha, 0); 5162 break; 5163 default: 5164 ql_log(ql_log_warn, base_vha, 0xb071, 5165 "Unknown Device State: %x.\n", dev_state); 5166 qla83xx_idc_unlock(base_vha, 0); 5167 qla8xxx_dev_failed_handler(base_vha); 5168 rval = QLA_FUNCTION_FAILED; 5169 qla83xx_idc_lock(base_vha, 0); 5170 goto exit; 5171 } 5172 } 5173 5174 exit: 5175 return rval; 5176 } 5177 5178 void 5179 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5180 { 5181 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5182 board_disable); 5183 struct pci_dev *pdev = ha->pdev; 5184 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5185 5186 /* if UNLOAD flag is already set, then continue unload, 5187 * where it was set first. 5188 */ 5189 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5190 return; 5191 5192 ql_log(ql_log_warn, base_vha, 0x015b, 5193 "Disabling adapter.\n"); 5194 5195 set_bit(UNLOADING, &base_vha->dpc_flags); 5196 5197 qla2x00_delete_all_vps(ha, base_vha); 5198 5199 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5200 5201 qla2x00_dfs_remove(base_vha); 5202 5203 qla84xx_put_chip(base_vha); 5204 5205 if (base_vha->timer_active) 5206 qla2x00_stop_timer(base_vha); 5207 5208 base_vha->flags.online = 0; 5209 5210 qla2x00_destroy_deferred_work(ha); 5211 5212 /* 5213 * Do not try to stop beacon blink as it will issue a mailbox 5214 * command. 5215 */ 5216 qla2x00_free_sysfs_attr(base_vha, false); 5217 5218 fc_remove_host(base_vha->host); 5219 5220 scsi_remove_host(base_vha->host); 5221 5222 base_vha->flags.init_done = 0; 5223 qla25xx_delete_queues(base_vha); 5224 qla2x00_free_fcports(base_vha); 5225 qla2x00_free_irqs(base_vha); 5226 qla2x00_mem_free(ha); 5227 qla82xx_md_free(base_vha); 5228 qla2x00_free_queues(ha); 5229 5230 qla2x00_unmap_iobases(ha); 5231 5232 pci_release_selected_regions(ha->pdev, ha->bars); 5233 pci_disable_pcie_error_reporting(pdev); 5234 pci_disable_device(pdev); 5235 5236 /* 5237 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5238 */ 5239 } 5240 5241 /************************************************************************** 5242 * qla2x00_do_dpc 5243 * This kernel thread is a task that is schedule by the interrupt handler 5244 * to perform the background processing for interrupts. 5245 * 5246 * Notes: 5247 * This task always run in the context of a kernel thread. It 5248 * is kick-off by the driver's detect code and starts up 5249 * up one per adapter. It immediately goes to sleep and waits for 5250 * some fibre event. When either the interrupt handler or 5251 * the timer routine detects a event it will one of the task 5252 * bits then wake us up. 5253 **************************************************************************/ 5254 static int 5255 qla2x00_do_dpc(void *data) 5256 { 5257 scsi_qla_host_t *base_vha; 5258 struct qla_hw_data *ha; 5259 uint32_t online; 5260 struct qla_qpair *qpair; 5261 5262 ha = (struct qla_hw_data *)data; 5263 base_vha = pci_get_drvdata(ha->pdev); 5264 5265 set_user_nice(current, MIN_NICE); 5266 5267 set_current_state(TASK_INTERRUPTIBLE); 5268 while (!kthread_should_stop()) { 5269 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5270 "DPC handler sleeping.\n"); 5271 5272 schedule(); 5273 5274 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5275 goto end_loop; 5276 5277 if (ha->flags.eeh_busy) { 5278 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5279 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5280 goto end_loop; 5281 } 5282 5283 ha->dpc_active = 1; 5284 5285 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5286 "DPC handler waking up, dpc_flags=0x%lx.\n", 5287 base_vha->dpc_flags); 5288 5289 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5290 break; 5291 5292 qla2x00_do_work(base_vha); 5293 5294 if (IS_P3P_TYPE(ha)) { 5295 if (IS_QLA8044(ha)) { 5296 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5297 &base_vha->dpc_flags)) { 5298 qla8044_idc_lock(ha); 5299 qla8044_wr_direct(base_vha, 5300 QLA8044_CRB_DEV_STATE_INDEX, 5301 QLA8XXX_DEV_FAILED); 5302 qla8044_idc_unlock(ha); 5303 ql_log(ql_log_info, base_vha, 0x4004, 5304 "HW State: FAILED.\n"); 5305 qla8044_device_state_handler(base_vha); 5306 continue; 5307 } 5308 5309 } else { 5310 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5311 &base_vha->dpc_flags)) { 5312 qla82xx_idc_lock(ha); 5313 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5314 QLA8XXX_DEV_FAILED); 5315 qla82xx_idc_unlock(ha); 5316 ql_log(ql_log_info, base_vha, 0x0151, 5317 "HW State: FAILED.\n"); 5318 qla82xx_device_state_handler(base_vha); 5319 continue; 5320 } 5321 } 5322 5323 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5324 &base_vha->dpc_flags)) { 5325 5326 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5327 "FCoE context reset scheduled.\n"); 5328 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5329 &base_vha->dpc_flags))) { 5330 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5331 /* FCoE-ctx reset failed. 5332 * Escalate to chip-reset 5333 */ 5334 set_bit(ISP_ABORT_NEEDED, 5335 &base_vha->dpc_flags); 5336 } 5337 clear_bit(ABORT_ISP_ACTIVE, 5338 &base_vha->dpc_flags); 5339 } 5340 5341 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5342 "FCoE context reset end.\n"); 5343 } 5344 } else if (IS_QLAFX00(ha)) { 5345 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5346 &base_vha->dpc_flags)) { 5347 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5348 "Firmware Reset Recovery\n"); 5349 if (qlafx00_reset_initialize(base_vha)) { 5350 /* Failed. Abort isp later. */ 5351 if (!test_bit(UNLOADING, 5352 &base_vha->dpc_flags)) { 5353 set_bit(ISP_UNRECOVERABLE, 5354 &base_vha->dpc_flags); 5355 ql_dbg(ql_dbg_dpc, base_vha, 5356 0x4021, 5357 "Reset Recovery Failed\n"); 5358 } 5359 } 5360 } 5361 5362 if (test_and_clear_bit(FX00_TARGET_SCAN, 5363 &base_vha->dpc_flags)) { 5364 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5365 "ISPFx00 Target Scan scheduled\n"); 5366 if (qlafx00_rescan_isp(base_vha)) { 5367 if (!test_bit(UNLOADING, 5368 &base_vha->dpc_flags)) 5369 set_bit(ISP_UNRECOVERABLE, 5370 &base_vha->dpc_flags); 5371 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5372 "ISPFx00 Target Scan Failed\n"); 5373 } 5374 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5375 "ISPFx00 Target Scan End\n"); 5376 } 5377 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5378 &base_vha->dpc_flags)) { 5379 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5380 "ISPFx00 Host Info resend scheduled\n"); 5381 qlafx00_fx_disc(base_vha, 5382 &base_vha->hw->mr.fcport, 5383 FXDISC_REG_HOST_INFO); 5384 } 5385 } 5386 5387 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5388 &base_vha->dpc_flags)) { 5389 5390 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5391 "ISP abort scheduled.\n"); 5392 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5393 &base_vha->dpc_flags))) { 5394 5395 if (ha->isp_ops->abort_isp(base_vha)) { 5396 /* failed. retry later */ 5397 set_bit(ISP_ABORT_NEEDED, 5398 &base_vha->dpc_flags); 5399 } 5400 clear_bit(ABORT_ISP_ACTIVE, 5401 &base_vha->dpc_flags); 5402 } 5403 5404 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5405 "ISP abort end.\n"); 5406 } 5407 5408 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5409 &base_vha->dpc_flags)) { 5410 qla2x00_update_fcports(base_vha); 5411 } 5412 5413 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 5414 int ret; 5415 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 5416 if (ret != QLA_SUCCESS) 5417 ql_log(ql_log_warn, base_vha, 0x121, 5418 "Failed to enable receiving of RSCN " 5419 "requests: 0x%x.\n", ret); 5420 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 5421 } 5422 5423 if (IS_QLAFX00(ha)) 5424 goto loop_resync_check; 5425 5426 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5427 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5428 "Quiescence mode scheduled.\n"); 5429 if (IS_P3P_TYPE(ha)) { 5430 if (IS_QLA82XX(ha)) 5431 qla82xx_device_state_handler(base_vha); 5432 if (IS_QLA8044(ha)) 5433 qla8044_device_state_handler(base_vha); 5434 clear_bit(ISP_QUIESCE_NEEDED, 5435 &base_vha->dpc_flags); 5436 if (!ha->flags.quiesce_owner) { 5437 qla2x00_perform_loop_resync(base_vha); 5438 if (IS_QLA82XX(ha)) { 5439 qla82xx_idc_lock(ha); 5440 qla82xx_clear_qsnt_ready( 5441 base_vha); 5442 qla82xx_idc_unlock(ha); 5443 } else if (IS_QLA8044(ha)) { 5444 qla8044_idc_lock(ha); 5445 qla8044_clear_qsnt_ready( 5446 base_vha); 5447 qla8044_idc_unlock(ha); 5448 } 5449 } 5450 } else { 5451 clear_bit(ISP_QUIESCE_NEEDED, 5452 &base_vha->dpc_flags); 5453 qla2x00_quiesce_io(base_vha); 5454 } 5455 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5456 "Quiescence mode end.\n"); 5457 } 5458 5459 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5460 &base_vha->dpc_flags) && 5461 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5462 5463 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5464 "Reset marker scheduled.\n"); 5465 qla2x00_rst_aen(base_vha); 5466 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5467 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5468 "Reset marker end.\n"); 5469 } 5470 5471 /* Retry each device up to login retry count */ 5472 if ((test_and_clear_bit(RELOGIN_NEEDED, 5473 &base_vha->dpc_flags)) && 5474 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5475 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5476 5477 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5478 "Relogin scheduled.\n"); 5479 qla2x00_relogin(base_vha); 5480 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5481 "Relogin end.\n"); 5482 } 5483 loop_resync_check: 5484 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5485 &base_vha->dpc_flags)) { 5486 5487 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5488 "Loop resync scheduled.\n"); 5489 5490 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5491 &base_vha->dpc_flags))) { 5492 5493 qla2x00_loop_resync(base_vha); 5494 5495 clear_bit(LOOP_RESYNC_ACTIVE, 5496 &base_vha->dpc_flags); 5497 } 5498 5499 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5500 "Loop resync end.\n"); 5501 } 5502 5503 if (IS_QLAFX00(ha)) 5504 goto intr_on_check; 5505 5506 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5507 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5508 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5509 qla2xxx_flash_npiv_conf(base_vha); 5510 } 5511 5512 intr_on_check: 5513 if (!ha->interrupts_on) 5514 ha->isp_ops->enable_intrs(ha); 5515 5516 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5517 &base_vha->dpc_flags)) { 5518 if (ha->beacon_blink_led == 1) 5519 ha->isp_ops->beacon_blink(base_vha); 5520 } 5521 5522 /* qpair online check */ 5523 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 5524 &base_vha->dpc_flags)) { 5525 if (ha->flags.eeh_busy || 5526 ha->flags.pci_channel_io_perm_failure) 5527 online = 0; 5528 else 5529 online = 1; 5530 5531 mutex_lock(&ha->mq_lock); 5532 list_for_each_entry(qpair, &base_vha->qp_list, 5533 qp_list_elem) 5534 qpair->online = online; 5535 mutex_unlock(&ha->mq_lock); 5536 } 5537 5538 if (!IS_QLAFX00(ha)) 5539 qla2x00_do_dpc_all_vps(base_vha); 5540 5541 ha->dpc_active = 0; 5542 end_loop: 5543 set_current_state(TASK_INTERRUPTIBLE); 5544 } /* End of while(1) */ 5545 __set_current_state(TASK_RUNNING); 5546 5547 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5548 "DPC handler exiting.\n"); 5549 5550 /* 5551 * Make sure that nobody tries to wake us up again. 5552 */ 5553 ha->dpc_active = 0; 5554 5555 /* Cleanup any residual CTX SRBs. */ 5556 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5557 5558 return 0; 5559 } 5560 5561 void 5562 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5563 { 5564 struct qla_hw_data *ha = vha->hw; 5565 struct task_struct *t = ha->dpc_thread; 5566 5567 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5568 wake_up_process(t); 5569 } 5570 5571 /* 5572 * qla2x00_rst_aen 5573 * Processes asynchronous reset. 5574 * 5575 * Input: 5576 * ha = adapter block pointer. 5577 */ 5578 static void 5579 qla2x00_rst_aen(scsi_qla_host_t *vha) 5580 { 5581 if (vha->flags.online && !vha->flags.reset_active && 5582 !atomic_read(&vha->loop_down_timer) && 5583 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5584 do { 5585 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5586 5587 /* 5588 * Issue marker command only when we are going to start 5589 * the I/O. 5590 */ 5591 vha->marker_needed = 1; 5592 } while (!atomic_read(&vha->loop_down_timer) && 5593 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5594 } 5595 } 5596 5597 /************************************************************************** 5598 * qla2x00_timer 5599 * 5600 * Description: 5601 * One second timer 5602 * 5603 * Context: Interrupt 5604 ***************************************************************************/ 5605 void 5606 qla2x00_timer(scsi_qla_host_t *vha) 5607 { 5608 unsigned long cpu_flags = 0; 5609 int start_dpc = 0; 5610 int index; 5611 srb_t *sp; 5612 uint16_t w; 5613 struct qla_hw_data *ha = vha->hw; 5614 struct req_que *req; 5615 5616 if (ha->flags.eeh_busy) { 5617 ql_dbg(ql_dbg_timer, vha, 0x6000, 5618 "EEH = %d, restarting timer.\n", 5619 ha->flags.eeh_busy); 5620 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5621 return; 5622 } 5623 5624 /* 5625 * Hardware read to raise pending EEH errors during mailbox waits. If 5626 * the read returns -1 then disable the board. 5627 */ 5628 if (!pci_channel_offline(ha->pdev)) { 5629 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5630 qla2x00_check_reg16_for_disconnect(vha, w); 5631 } 5632 5633 /* Make sure qla82xx_watchdog is run only for physical port */ 5634 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5635 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5636 start_dpc++; 5637 if (IS_QLA82XX(ha)) 5638 qla82xx_watchdog(vha); 5639 else if (IS_QLA8044(ha)) 5640 qla8044_watchdog(vha); 5641 } 5642 5643 if (!vha->vp_idx && IS_QLAFX00(ha)) 5644 qlafx00_timer_routine(vha); 5645 5646 /* Loop down handler. */ 5647 if (atomic_read(&vha->loop_down_timer) > 0 && 5648 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5649 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5650 && vha->flags.online) { 5651 5652 if (atomic_read(&vha->loop_down_timer) == 5653 vha->loop_down_abort_time) { 5654 5655 ql_log(ql_log_info, vha, 0x6008, 5656 "Loop down - aborting the queues before time expires.\n"); 5657 5658 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5659 atomic_set(&vha->loop_state, LOOP_DEAD); 5660 5661 /* 5662 * Schedule an ISP abort to return any FCP2-device 5663 * commands. 5664 */ 5665 /* NPIV - scan physical port only */ 5666 if (!vha->vp_idx) { 5667 spin_lock_irqsave(&ha->hardware_lock, 5668 cpu_flags); 5669 req = ha->req_q_map[0]; 5670 for (index = 1; 5671 index < req->num_outstanding_cmds; 5672 index++) { 5673 fc_port_t *sfcp; 5674 5675 sp = req->outstanding_cmds[index]; 5676 if (!sp) 5677 continue; 5678 if (sp->type != SRB_SCSI_CMD) 5679 continue; 5680 sfcp = sp->fcport; 5681 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5682 continue; 5683 5684 if (IS_QLA82XX(ha)) 5685 set_bit(FCOE_CTX_RESET_NEEDED, 5686 &vha->dpc_flags); 5687 else 5688 set_bit(ISP_ABORT_NEEDED, 5689 &vha->dpc_flags); 5690 break; 5691 } 5692 spin_unlock_irqrestore(&ha->hardware_lock, 5693 cpu_flags); 5694 } 5695 start_dpc++; 5696 } 5697 5698 /* if the loop has been down for 4 minutes, reinit adapter */ 5699 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5700 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5701 ql_log(ql_log_warn, vha, 0x6009, 5702 "Loop down - aborting ISP.\n"); 5703 5704 if (IS_QLA82XX(ha)) 5705 set_bit(FCOE_CTX_RESET_NEEDED, 5706 &vha->dpc_flags); 5707 else 5708 set_bit(ISP_ABORT_NEEDED, 5709 &vha->dpc_flags); 5710 } 5711 } 5712 ql_dbg(ql_dbg_timer, vha, 0x600a, 5713 "Loop down - seconds remaining %d.\n", 5714 atomic_read(&vha->loop_down_timer)); 5715 } 5716 /* Check if beacon LED needs to be blinked for physical host only */ 5717 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5718 /* There is no beacon_blink function for ISP82xx */ 5719 if (!IS_P3P_TYPE(ha)) { 5720 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5721 start_dpc++; 5722 } 5723 } 5724 5725 /* Process any deferred work. */ 5726 if (!list_empty(&vha->work_list)) 5727 start_dpc++; 5728 5729 /* Schedule the DPC routine if needed */ 5730 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5731 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5732 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5733 start_dpc || 5734 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5735 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5736 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5737 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5738 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5739 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5740 ql_dbg(ql_dbg_timer, vha, 0x600b, 5741 "isp_abort_needed=%d loop_resync_needed=%d " 5742 "fcport_update_needed=%d start_dpc=%d " 5743 "reset_marker_needed=%d", 5744 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5745 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5746 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5747 start_dpc, 5748 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5749 ql_dbg(ql_dbg_timer, vha, 0x600c, 5750 "beacon_blink_needed=%d isp_unrecoverable=%d " 5751 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5752 "relogin_needed=%d.\n", 5753 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5754 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5755 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5756 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5757 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5758 qla2xxx_wake_dpc(vha); 5759 } 5760 5761 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5762 } 5763 5764 /* Firmware interface routines. */ 5765 5766 #define FW_BLOBS 11 5767 #define FW_ISP21XX 0 5768 #define FW_ISP22XX 1 5769 #define FW_ISP2300 2 5770 #define FW_ISP2322 3 5771 #define FW_ISP24XX 4 5772 #define FW_ISP25XX 5 5773 #define FW_ISP81XX 6 5774 #define FW_ISP82XX 7 5775 #define FW_ISP2031 8 5776 #define FW_ISP8031 9 5777 #define FW_ISP27XX 10 5778 5779 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5780 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5781 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5782 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5783 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5784 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5785 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5786 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5787 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5788 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5789 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5790 5791 5792 static DEFINE_MUTEX(qla_fw_lock); 5793 5794 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5795 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5796 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5797 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5798 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5799 { .name = FW_FILE_ISP24XX, }, 5800 { .name = FW_FILE_ISP25XX, }, 5801 { .name = FW_FILE_ISP81XX, }, 5802 { .name = FW_FILE_ISP82XX, }, 5803 { .name = FW_FILE_ISP2031, }, 5804 { .name = FW_FILE_ISP8031, }, 5805 { .name = FW_FILE_ISP27XX, }, 5806 }; 5807 5808 struct fw_blob * 5809 qla2x00_request_firmware(scsi_qla_host_t *vha) 5810 { 5811 struct qla_hw_data *ha = vha->hw; 5812 struct fw_blob *blob; 5813 5814 if (IS_QLA2100(ha)) { 5815 blob = &qla_fw_blobs[FW_ISP21XX]; 5816 } else if (IS_QLA2200(ha)) { 5817 blob = &qla_fw_blobs[FW_ISP22XX]; 5818 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5819 blob = &qla_fw_blobs[FW_ISP2300]; 5820 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5821 blob = &qla_fw_blobs[FW_ISP2322]; 5822 } else if (IS_QLA24XX_TYPE(ha)) { 5823 blob = &qla_fw_blobs[FW_ISP24XX]; 5824 } else if (IS_QLA25XX(ha)) { 5825 blob = &qla_fw_blobs[FW_ISP25XX]; 5826 } else if (IS_QLA81XX(ha)) { 5827 blob = &qla_fw_blobs[FW_ISP81XX]; 5828 } else if (IS_QLA82XX(ha)) { 5829 blob = &qla_fw_blobs[FW_ISP82XX]; 5830 } else if (IS_QLA2031(ha)) { 5831 blob = &qla_fw_blobs[FW_ISP2031]; 5832 } else if (IS_QLA8031(ha)) { 5833 blob = &qla_fw_blobs[FW_ISP8031]; 5834 } else if (IS_QLA27XX(ha)) { 5835 blob = &qla_fw_blobs[FW_ISP27XX]; 5836 } else { 5837 return NULL; 5838 } 5839 5840 mutex_lock(&qla_fw_lock); 5841 if (blob->fw) 5842 goto out; 5843 5844 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5845 ql_log(ql_log_warn, vha, 0x0063, 5846 "Failed to load firmware image (%s).\n", blob->name); 5847 blob->fw = NULL; 5848 blob = NULL; 5849 goto out; 5850 } 5851 5852 out: 5853 mutex_unlock(&qla_fw_lock); 5854 return blob; 5855 } 5856 5857 static void 5858 qla2x00_release_firmware(void) 5859 { 5860 int idx; 5861 5862 mutex_lock(&qla_fw_lock); 5863 for (idx = 0; idx < FW_BLOBS; idx++) 5864 release_firmware(qla_fw_blobs[idx].fw); 5865 mutex_unlock(&qla_fw_lock); 5866 } 5867 5868 static pci_ers_result_t 5869 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5870 { 5871 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5872 struct qla_hw_data *ha = vha->hw; 5873 5874 ql_dbg(ql_dbg_aer, vha, 0x9000, 5875 "PCI error detected, state %x.\n", state); 5876 5877 switch (state) { 5878 case pci_channel_io_normal: 5879 ha->flags.eeh_busy = 0; 5880 if (ql2xmqsupport) { 5881 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5882 qla2xxx_wake_dpc(vha); 5883 } 5884 return PCI_ERS_RESULT_CAN_RECOVER; 5885 case pci_channel_io_frozen: 5886 ha->flags.eeh_busy = 1; 5887 /* For ISP82XX complete any pending mailbox cmd */ 5888 if (IS_QLA82XX(ha)) { 5889 ha->flags.isp82xx_fw_hung = 1; 5890 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5891 qla82xx_clear_pending_mbx(vha); 5892 } 5893 qla2x00_free_irqs(vha); 5894 pci_disable_device(pdev); 5895 /* Return back all IOs */ 5896 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5897 if (ql2xmqsupport) { 5898 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5899 qla2xxx_wake_dpc(vha); 5900 } 5901 return PCI_ERS_RESULT_NEED_RESET; 5902 case pci_channel_io_perm_failure: 5903 ha->flags.pci_channel_io_perm_failure = 1; 5904 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5905 if (ql2xmqsupport) { 5906 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 5907 qla2xxx_wake_dpc(vha); 5908 } 5909 return PCI_ERS_RESULT_DISCONNECT; 5910 } 5911 return PCI_ERS_RESULT_NEED_RESET; 5912 } 5913 5914 static pci_ers_result_t 5915 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5916 { 5917 int risc_paused = 0; 5918 uint32_t stat; 5919 unsigned long flags; 5920 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5921 struct qla_hw_data *ha = base_vha->hw; 5922 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5923 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5924 5925 if (IS_QLA82XX(ha)) 5926 return PCI_ERS_RESULT_RECOVERED; 5927 5928 spin_lock_irqsave(&ha->hardware_lock, flags); 5929 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5930 stat = RD_REG_DWORD(®->hccr); 5931 if (stat & HCCR_RISC_PAUSE) 5932 risc_paused = 1; 5933 } else if (IS_QLA23XX(ha)) { 5934 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5935 if (stat & HSR_RISC_PAUSED) 5936 risc_paused = 1; 5937 } else if (IS_FWI2_CAPABLE(ha)) { 5938 stat = RD_REG_DWORD(®24->host_status); 5939 if (stat & HSRX_RISC_PAUSED) 5940 risc_paused = 1; 5941 } 5942 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5943 5944 if (risc_paused) { 5945 ql_log(ql_log_info, base_vha, 0x9003, 5946 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5947 ha->isp_ops->fw_dump(base_vha, 0); 5948 5949 return PCI_ERS_RESULT_NEED_RESET; 5950 } else 5951 return PCI_ERS_RESULT_RECOVERED; 5952 } 5953 5954 static uint32_t 5955 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5956 { 5957 uint32_t rval = QLA_FUNCTION_FAILED; 5958 uint32_t drv_active = 0; 5959 struct qla_hw_data *ha = base_vha->hw; 5960 int fn; 5961 struct pci_dev *other_pdev = NULL; 5962 5963 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5964 "Entered %s.\n", __func__); 5965 5966 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5967 5968 if (base_vha->flags.online) { 5969 /* Abort all outstanding commands, 5970 * so as to be requeued later */ 5971 qla2x00_abort_isp_cleanup(base_vha); 5972 } 5973 5974 5975 fn = PCI_FUNC(ha->pdev->devfn); 5976 while (fn > 0) { 5977 fn--; 5978 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5979 "Finding pci device at function = 0x%x.\n", fn); 5980 other_pdev = 5981 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5982 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5983 fn)); 5984 5985 if (!other_pdev) 5986 continue; 5987 if (atomic_read(&other_pdev->enable_cnt)) { 5988 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5989 "Found PCI func available and enable at 0x%x.\n", 5990 fn); 5991 pci_dev_put(other_pdev); 5992 break; 5993 } 5994 pci_dev_put(other_pdev); 5995 } 5996 5997 if (!fn) { 5998 /* Reset owner */ 5999 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6000 "This devfn is reset owner = 0x%x.\n", 6001 ha->pdev->devfn); 6002 qla82xx_idc_lock(ha); 6003 6004 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6005 QLA8XXX_DEV_INITIALIZING); 6006 6007 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6008 QLA82XX_IDC_VERSION); 6009 6010 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6011 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6012 "drv_active = 0x%x.\n", drv_active); 6013 6014 qla82xx_idc_unlock(ha); 6015 /* Reset if device is not already reset 6016 * drv_active would be 0 if a reset has already been done 6017 */ 6018 if (drv_active) 6019 rval = qla82xx_start_firmware(base_vha); 6020 else 6021 rval = QLA_SUCCESS; 6022 qla82xx_idc_lock(ha); 6023 6024 if (rval != QLA_SUCCESS) { 6025 ql_log(ql_log_info, base_vha, 0x900b, 6026 "HW State: FAILED.\n"); 6027 qla82xx_clear_drv_active(ha); 6028 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6029 QLA8XXX_DEV_FAILED); 6030 } else { 6031 ql_log(ql_log_info, base_vha, 0x900c, 6032 "HW State: READY.\n"); 6033 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6034 QLA8XXX_DEV_READY); 6035 qla82xx_idc_unlock(ha); 6036 ha->flags.isp82xx_fw_hung = 0; 6037 rval = qla82xx_restart_isp(base_vha); 6038 qla82xx_idc_lock(ha); 6039 /* Clear driver state register */ 6040 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6041 qla82xx_set_drv_active(base_vha); 6042 } 6043 qla82xx_idc_unlock(ha); 6044 } else { 6045 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6046 "This devfn is not reset owner = 0x%x.\n", 6047 ha->pdev->devfn); 6048 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6049 QLA8XXX_DEV_READY)) { 6050 ha->flags.isp82xx_fw_hung = 0; 6051 rval = qla82xx_restart_isp(base_vha); 6052 qla82xx_idc_lock(ha); 6053 qla82xx_set_drv_active(base_vha); 6054 qla82xx_idc_unlock(ha); 6055 } 6056 } 6057 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6058 6059 return rval; 6060 } 6061 6062 static pci_ers_result_t 6063 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6064 { 6065 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6066 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6067 struct qla_hw_data *ha = base_vha->hw; 6068 struct rsp_que *rsp; 6069 int rc, retries = 10; 6070 6071 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6072 "Slot Reset.\n"); 6073 6074 /* Workaround: qla2xxx driver which access hardware earlier 6075 * needs error state to be pci_channel_io_online. 6076 * Otherwise mailbox command timesout. 6077 */ 6078 pdev->error_state = pci_channel_io_normal; 6079 6080 pci_restore_state(pdev); 6081 6082 /* pci_restore_state() clears the saved_state flag of the device 6083 * save restored state which resets saved_state flag 6084 */ 6085 pci_save_state(pdev); 6086 6087 if (ha->mem_only) 6088 rc = pci_enable_device_mem(pdev); 6089 else 6090 rc = pci_enable_device(pdev); 6091 6092 if (rc) { 6093 ql_log(ql_log_warn, base_vha, 0x9005, 6094 "Can't re-enable PCI device after reset.\n"); 6095 goto exit_slot_reset; 6096 } 6097 6098 rsp = ha->rsp_q_map[0]; 6099 if (qla2x00_request_irqs(ha, rsp)) 6100 goto exit_slot_reset; 6101 6102 if (ha->isp_ops->pci_config(base_vha)) 6103 goto exit_slot_reset; 6104 6105 if (IS_QLA82XX(ha)) { 6106 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6107 ret = PCI_ERS_RESULT_RECOVERED; 6108 goto exit_slot_reset; 6109 } else 6110 goto exit_slot_reset; 6111 } 6112 6113 while (ha->flags.mbox_busy && retries--) 6114 msleep(1000); 6115 6116 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6117 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6118 ret = PCI_ERS_RESULT_RECOVERED; 6119 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6120 6121 6122 exit_slot_reset: 6123 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6124 "slot_reset return %x.\n", ret); 6125 6126 return ret; 6127 } 6128 6129 static void 6130 qla2xxx_pci_resume(struct pci_dev *pdev) 6131 { 6132 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6133 struct qla_hw_data *ha = base_vha->hw; 6134 int ret; 6135 6136 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6137 "pci_resume.\n"); 6138 6139 ret = qla2x00_wait_for_hba_online(base_vha); 6140 if (ret != QLA_SUCCESS) { 6141 ql_log(ql_log_fatal, base_vha, 0x9002, 6142 "The device failed to resume I/O from slot/link_reset.\n"); 6143 } 6144 6145 pci_cleanup_aer_uncorrect_error_status(pdev); 6146 6147 ha->flags.eeh_busy = 0; 6148 } 6149 6150 static void 6151 qla83xx_disable_laser(scsi_qla_host_t *vha) 6152 { 6153 uint32_t reg, data, fn; 6154 struct qla_hw_data *ha = vha->hw; 6155 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 6156 6157 /* pci func #/port # */ 6158 ql_dbg(ql_dbg_init, vha, 0x004b, 6159 "Disabling Laser for hba: %p\n", vha); 6160 6161 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 6162 (BIT_15|BIT_14|BIT_13|BIT_12)); 6163 6164 fn = (fn >> 12); 6165 6166 if (fn & 1) 6167 reg = PORT_1_2031; 6168 else 6169 reg = PORT_0_2031; 6170 6171 data = LASER_OFF_2031; 6172 6173 qla83xx_wr_reg(vha, reg, data); 6174 } 6175 6176 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6177 { 6178 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6179 6180 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6181 } 6182 6183 static const struct pci_error_handlers qla2xxx_err_handler = { 6184 .error_detected = qla2xxx_pci_error_detected, 6185 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6186 .slot_reset = qla2xxx_pci_slot_reset, 6187 .resume = qla2xxx_pci_resume, 6188 }; 6189 6190 static struct pci_device_id qla2xxx_pci_tbl[] = { 6191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6213 { 0 }, 6214 }; 6215 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6216 6217 static struct pci_driver qla2xxx_pci_driver = { 6218 .name = QLA2XXX_DRIVER_NAME, 6219 .driver = { 6220 .owner = THIS_MODULE, 6221 }, 6222 .id_table = qla2xxx_pci_tbl, 6223 .probe = qla2x00_probe_one, 6224 .remove = qla2x00_remove_one, 6225 .shutdown = qla2x00_shutdown, 6226 .err_handler = &qla2xxx_err_handler, 6227 }; 6228 6229 static const struct file_operations apidev_fops = { 6230 .owner = THIS_MODULE, 6231 .llseek = noop_llseek, 6232 }; 6233 6234 /** 6235 * qla2x00_module_init - Module initialization. 6236 **/ 6237 static int __init 6238 qla2x00_module_init(void) 6239 { 6240 int ret = 0; 6241 6242 /* Allocate cache for SRBs. */ 6243 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6244 SLAB_HWCACHE_ALIGN, NULL); 6245 if (srb_cachep == NULL) { 6246 ql_log(ql_log_fatal, NULL, 0x0001, 6247 "Unable to allocate SRB cache...Failing load!.\n"); 6248 return -ENOMEM; 6249 } 6250 6251 /* Initialize target kmem_cache and mem_pools */ 6252 ret = qlt_init(); 6253 if (ret < 0) { 6254 kmem_cache_destroy(srb_cachep); 6255 return ret; 6256 } else if (ret > 0) { 6257 /* 6258 * If initiator mode is explictly disabled by qlt_init(), 6259 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6260 * performing scsi_scan_target() during LOOP UP event. 6261 */ 6262 qla2xxx_transport_functions.disable_target_scan = 1; 6263 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6264 } 6265 6266 /* Derive version string. */ 6267 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6268 if (ql2xextended_error_logging) 6269 strcat(qla2x00_version_str, "-debug"); 6270 6271 qla2xxx_transport_template = 6272 fc_attach_transport(&qla2xxx_transport_functions); 6273 if (!qla2xxx_transport_template) { 6274 kmem_cache_destroy(srb_cachep); 6275 ql_log(ql_log_fatal, NULL, 0x0002, 6276 "fc_attach_transport failed...Failing load!.\n"); 6277 qlt_exit(); 6278 return -ENODEV; 6279 } 6280 6281 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6282 if (apidev_major < 0) { 6283 ql_log(ql_log_fatal, NULL, 0x0003, 6284 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6285 } 6286 6287 qla2xxx_transport_vport_template = 6288 fc_attach_transport(&qla2xxx_transport_vport_functions); 6289 if (!qla2xxx_transport_vport_template) { 6290 kmem_cache_destroy(srb_cachep); 6291 qlt_exit(); 6292 fc_release_transport(qla2xxx_transport_template); 6293 ql_log(ql_log_fatal, NULL, 0x0004, 6294 "fc_attach_transport vport failed...Failing load!.\n"); 6295 return -ENODEV; 6296 } 6297 ql_log(ql_log_info, NULL, 0x0005, 6298 "QLogic Fibre Channel HBA Driver: %s.\n", 6299 qla2x00_version_str); 6300 ret = pci_register_driver(&qla2xxx_pci_driver); 6301 if (ret) { 6302 kmem_cache_destroy(srb_cachep); 6303 qlt_exit(); 6304 fc_release_transport(qla2xxx_transport_template); 6305 fc_release_transport(qla2xxx_transport_vport_template); 6306 ql_log(ql_log_fatal, NULL, 0x0006, 6307 "pci_register_driver failed...ret=%d Failing load!.\n", 6308 ret); 6309 } 6310 return ret; 6311 } 6312 6313 /** 6314 * qla2x00_module_exit - Module cleanup. 6315 **/ 6316 static void __exit 6317 qla2x00_module_exit(void) 6318 { 6319 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6320 pci_unregister_driver(&qla2xxx_pci_driver); 6321 qla2x00_release_firmware(); 6322 kmem_cache_destroy(srb_cachep); 6323 qlt_exit(); 6324 if (ctx_cachep) 6325 kmem_cache_destroy(ctx_cachep); 6326 fc_release_transport(qla2xxx_transport_template); 6327 fc_release_transport(qla2xxx_transport_vport_template); 6328 } 6329 6330 module_init(qla2x00_module_init); 6331 module_exit(qla2x00_module_exit); 6332 6333 MODULE_AUTHOR("QLogic Corporation"); 6334 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6335 MODULE_LICENSE("GPL"); 6336 MODULE_VERSION(QLA2XXX_VERSION); 6337 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6338 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6339 MODULE_FIRMWARE(FW_FILE_ISP2300); 6340 MODULE_FIRMWARE(FW_FILE_ISP2322); 6341 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6342 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6343