1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 18 #include <scsi/scsi_tcq.h> 19 #include <scsi/scsicam.h> 20 #include <scsi/scsi_transport.h> 21 #include <scsi/scsi_transport_fc.h> 22 23 #include "qla_target.h" 24 25 /* 26 * Driver version 27 */ 28 char qla2x00_version_str[40]; 29 30 static int apidev_major; 31 32 /* 33 * SRB allocation cache 34 */ 35 struct kmem_cache *srb_cachep; 36 37 int ql2xfulldump_on_mpifail; 38 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 39 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 40 "Set this to take full dump on MPI hang."); 41 42 int ql2xenforce_iocb_limit = 1; 43 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 45 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 46 47 /* 48 * CT6 CTX allocation cache 49 */ 50 static struct kmem_cache *ctx_cachep; 51 /* 52 * error level for logging 53 */ 54 uint ql_errlev = 0x8001; 55 56 static int ql2xenableclass2; 57 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 58 MODULE_PARM_DESC(ql2xenableclass2, 59 "Specify if Class 2 operations are supported from the very " 60 "beginning. Default is 0 - class 2 not supported."); 61 62 63 int ql2xlogintimeout = 20; 64 module_param(ql2xlogintimeout, int, S_IRUGO); 65 MODULE_PARM_DESC(ql2xlogintimeout, 66 "Login timeout value in seconds."); 67 68 int qlport_down_retry; 69 module_param(qlport_down_retry, int, S_IRUGO); 70 MODULE_PARM_DESC(qlport_down_retry, 71 "Maximum number of command retries to a port that returns " 72 "a PORT-DOWN status."); 73 74 int ql2xplogiabsentdevice; 75 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 76 MODULE_PARM_DESC(ql2xplogiabsentdevice, 77 "Option to enable PLOGI to devices that are not present after " 78 "a Fabric scan. This is needed for several broken switches. " 79 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 80 81 int ql2xloginretrycount; 82 module_param(ql2xloginretrycount, int, S_IRUGO); 83 MODULE_PARM_DESC(ql2xloginretrycount, 84 "Specify an alternate value for the NVRAM login retry count."); 85 86 int ql2xallocfwdump = 1; 87 module_param(ql2xallocfwdump, int, S_IRUGO); 88 MODULE_PARM_DESC(ql2xallocfwdump, 89 "Option to enable allocation of memory for a firmware dump " 90 "during HBA initialization. Memory allocation requirements " 91 "vary by ISP type. Default is 1 - allocate memory."); 92 93 int ql2xextended_error_logging; 94 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 95 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 96 MODULE_PARM_DESC(ql2xextended_error_logging, 97 "Option to enable extended error logging,\n" 98 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 99 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 100 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 101 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 102 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 103 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 104 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 105 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 106 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 107 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 108 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 109 "\t\t0x1e400000 - Preferred value for capturing essential " 110 "debug information (equivalent to old " 111 "ql2xextended_error_logging=1).\n" 112 "\t\tDo LOGICAL OR of the value to enable more than one level"); 113 114 int ql2xshiftctondsd = 6; 115 module_param(ql2xshiftctondsd, int, S_IRUGO); 116 MODULE_PARM_DESC(ql2xshiftctondsd, 117 "Set to control shifting of command type processing " 118 "based on total number of SG elements."); 119 120 int ql2xfdmienable = 1; 121 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 122 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 123 MODULE_PARM_DESC(ql2xfdmienable, 124 "Enables FDMI registrations. " 125 "0 - no FDMI registrations. " 126 "1 - provide FDMI registrations (default)."); 127 128 #define MAX_Q_DEPTH 64 129 static int ql2xmaxqdepth = MAX_Q_DEPTH; 130 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xmaxqdepth, 132 "Maximum queue depth to set for each LUN. " 133 "Default is 64."); 134 135 int ql2xenabledif = 2; 136 module_param(ql2xenabledif, int, S_IRUGO); 137 MODULE_PARM_DESC(ql2xenabledif, 138 " Enable T10-CRC-DIF:\n" 139 " Default is 2.\n" 140 " 0 -- No DIF Support\n" 141 " 1 -- Enable DIF for all types\n" 142 " 2 -- Enable DIF for all types, except Type 0.\n"); 143 144 #if (IS_ENABLED(CONFIG_NVME_FC)) 145 int ql2xnvmeenable = 1; 146 #else 147 int ql2xnvmeenable; 148 #endif 149 module_param(ql2xnvmeenable, int, 0644); 150 MODULE_PARM_DESC(ql2xnvmeenable, 151 "Enables NVME support. " 152 "0 - no NVMe. Default is Y"); 153 154 int ql2xenablehba_err_chk = 2; 155 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 156 MODULE_PARM_DESC(ql2xenablehba_err_chk, 157 " Enable T10-CRC-DIF Error isolation by HBA:\n" 158 " Default is 2.\n" 159 " 0 -- Error isolation disabled\n" 160 " 1 -- Error isolation enabled only for DIX Type 0\n" 161 " 2 -- Error isolation enabled for all Types\n"); 162 163 int ql2xiidmaenable = 1; 164 module_param(ql2xiidmaenable, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xiidmaenable, 166 "Enables iIDMA settings " 167 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 168 169 int ql2xmqsupport = 1; 170 module_param(ql2xmqsupport, int, S_IRUGO); 171 MODULE_PARM_DESC(ql2xmqsupport, 172 "Enable on demand multiple queue pairs support " 173 "Default is 1 for supported. " 174 "Set it to 0 to turn off mq qpair support."); 175 176 int ql2xfwloadbin; 177 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 178 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 179 MODULE_PARM_DESC(ql2xfwloadbin, 180 "Option to specify location from which to load ISP firmware:.\n" 181 " 2 -- load firmware via the request_firmware() (hotplug).\n" 182 " interface.\n" 183 " 1 -- load firmware from flash.\n" 184 " 0 -- use default semantics.\n"); 185 186 int ql2xetsenable; 187 module_param(ql2xetsenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xetsenable, 189 "Enables firmware ETS burst." 190 "Default is 0 - skip ETS enablement."); 191 192 int ql2xdbwr = 1; 193 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xdbwr, 195 "Option to specify scheme for request queue posting.\n" 196 " 0 -- Regular doorbell.\n" 197 " 1 -- CAMRAM doorbell (faster).\n"); 198 199 int ql2xtargetreset = 1; 200 module_param(ql2xtargetreset, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xtargetreset, 202 "Enable target reset." 203 "Default is 1 - use hw defaults."); 204 205 int ql2xgffidenable; 206 module_param(ql2xgffidenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xgffidenable, 208 "Enables GFF_ID checks of port type. " 209 "Default is 0 - Do not use GFF_ID information."); 210 211 int ql2xasynctmfenable = 1; 212 module_param(ql2xasynctmfenable, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xasynctmfenable, 214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 215 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 216 217 int ql2xdontresethba; 218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 219 MODULE_PARM_DESC(ql2xdontresethba, 220 "Option to specify reset behaviour.\n" 221 " 0 (Default) -- Reset on failure.\n" 222 " 1 -- Do not reset on failure.\n"); 223 224 uint64_t ql2xmaxlun = MAX_LUNS; 225 module_param(ql2xmaxlun, ullong, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmaxlun, 227 "Defines the maximum LU number to register with the SCSI " 228 "midlayer. Default is 65535."); 229 230 int ql2xmdcapmask = 0x1F; 231 module_param(ql2xmdcapmask, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdcapmask, 233 "Set the Minidump driver capture mask level. " 234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 235 236 int ql2xmdenable = 1; 237 module_param(ql2xmdenable, int, S_IRUGO); 238 MODULE_PARM_DESC(ql2xmdenable, 239 "Enable/disable MiniDump. " 240 "0 - MiniDump disabled. " 241 "1 (Default) - MiniDump enabled."); 242 243 int ql2xexlogins; 244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 245 MODULE_PARM_DESC(ql2xexlogins, 246 "Number of extended Logins. " 247 "0 (Default)- Disabled."); 248 249 int ql2xexchoffld = 1024; 250 module_param(ql2xexchoffld, uint, 0644); 251 MODULE_PARM_DESC(ql2xexchoffld, 252 "Number of target exchanges."); 253 254 int ql2xiniexchg = 1024; 255 module_param(ql2xiniexchg, uint, 0644); 256 MODULE_PARM_DESC(ql2xiniexchg, 257 "Number of initiator exchanges."); 258 259 int ql2xfwholdabts; 260 module_param(ql2xfwholdabts, int, S_IRUGO); 261 MODULE_PARM_DESC(ql2xfwholdabts, 262 "Allow FW to hold status IOCB until ABTS rsp received. " 263 "0 (Default) Do not set fw option. " 264 "1 - Set fw option to hold ABTS."); 265 266 int ql2xmvasynctoatio = 1; 267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 268 MODULE_PARM_DESC(ql2xmvasynctoatio, 269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 270 "0 (Default). Do not move IOCBs" 271 "1 - Move IOCBs."); 272 273 int ql2xautodetectsfp = 1; 274 module_param(ql2xautodetectsfp, int, 0444); 275 MODULE_PARM_DESC(ql2xautodetectsfp, 276 "Detect SFP range and set appropriate distance.\n" 277 "1 (Default): Enable\n"); 278 279 int ql2xenablemsix = 1; 280 module_param(ql2xenablemsix, int, 0444); 281 MODULE_PARM_DESC(ql2xenablemsix, 282 "Set to enable MSI or MSI-X interrupt mechanism.\n" 283 " Default is 1, enable MSI-X interrupt mechanism.\n" 284 " 0 -- enable traditional pin-based mechanism.\n" 285 " 1 -- enable MSI-X interrupt mechanism.\n" 286 " 2 -- enable MSI interrupt mechanism.\n"); 287 288 int qla2xuseresexchforels; 289 module_param(qla2xuseresexchforels, int, 0444); 290 MODULE_PARM_DESC(qla2xuseresexchforels, 291 "Reserve 1/2 of emergency exchanges for ELS.\n" 292 " 0 (default): disabled"); 293 294 static int ql2xprotmask; 295 module_param(ql2xprotmask, int, 0644); 296 MODULE_PARM_DESC(ql2xprotmask, 297 "Override DIF/DIX protection capabilities mask\n" 298 "Default is 0 which sets protection mask based on " 299 "capabilities reported by HBA firmware.\n"); 300 301 static int ql2xprotguard; 302 module_param(ql2xprotguard, int, 0644); 303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 304 " 0 -- Let HBA firmware decide\n" 305 " 1 -- Force T10 CRC\n" 306 " 2 -- Force IP checksum\n"); 307 308 int ql2xdifbundlinginternalbuffers; 309 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 311 "Force using internal buffers for DIF information\n" 312 "0 (Default). Based on check.\n" 313 "1 Force using internal buffers\n"); 314 315 int ql2xsmartsan; 316 module_param(ql2xsmartsan, int, 0444); 317 module_param_named(smartsan, ql2xsmartsan, int, 0444); 318 MODULE_PARM_DESC(ql2xsmartsan, 319 "Send SmartSAN Management Attributes for FDMI Registration." 320 " Default is 0 - No SmartSAN registration," 321 " 1 - Register SmartSAN Management Attributes."); 322 323 int ql2xrdpenable; 324 module_param(ql2xrdpenable, int, 0444); 325 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 326 MODULE_PARM_DESC(ql2xrdpenable, 327 "Enables RDP responses. " 328 "0 - no RDP responses (default). " 329 "1 - provide RDP responses."); 330 int ql2xabts_wait_nvme = 1; 331 module_param(ql2xabts_wait_nvme, int, 0444); 332 MODULE_PARM_DESC(ql2xabts_wait_nvme, 333 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 334 335 336 static void qla2x00_clear_drv_active(struct qla_hw_data *); 337 static void qla2x00_free_device(scsi_qla_host_t *); 338 static int qla2xxx_map_queues(struct Scsi_Host *shost); 339 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 340 341 342 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 343 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 344 345 /* TODO Convert to inlines 346 * 347 * Timer routines 348 */ 349 350 __inline__ void 351 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 352 { 353 timer_setup(&vha->timer, qla2x00_timer, 0); 354 vha->timer.expires = jiffies + interval * HZ; 355 add_timer(&vha->timer); 356 vha->timer_active = 1; 357 } 358 359 static inline void 360 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 361 { 362 /* Currently used for 82XX only. */ 363 if (vha->device_flags & DFLG_DEV_FAILED) { 364 ql_dbg(ql_dbg_timer, vha, 0x600d, 365 "Device in a failed state, returning.\n"); 366 return; 367 } 368 369 mod_timer(&vha->timer, jiffies + interval * HZ); 370 } 371 372 static __inline__ void 373 qla2x00_stop_timer(scsi_qla_host_t *vha) 374 { 375 del_timer_sync(&vha->timer); 376 vha->timer_active = 0; 377 } 378 379 static int qla2x00_do_dpc(void *data); 380 381 static void qla2x00_rst_aen(scsi_qla_host_t *); 382 383 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 384 struct req_que **, struct rsp_que **); 385 static void qla2x00_free_fw_dump(struct qla_hw_data *); 386 static void qla2x00_mem_free(struct qla_hw_data *); 387 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 388 struct qla_qpair *qpair); 389 390 /* -------------------------------------------------------------------------- */ 391 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 392 struct rsp_que *rsp) 393 { 394 struct qla_hw_data *ha = vha->hw; 395 396 rsp->qpair = ha->base_qpair; 397 rsp->req = req; 398 ha->base_qpair->hw = ha; 399 ha->base_qpair->req = req; 400 ha->base_qpair->rsp = rsp; 401 ha->base_qpair->vha = vha; 402 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 403 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 404 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 405 ha->base_qpair->srb_mempool = ha->srb_mempool; 406 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 407 ha->base_qpair->enable_class_2 = ql2xenableclass2; 408 /* init qpair to this cpu. Will adjust at run time. */ 409 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 410 ha->base_qpair->pdev = ha->pdev; 411 412 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 413 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 414 } 415 416 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 417 struct rsp_que *rsp) 418 { 419 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 420 421 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 422 GFP_KERNEL); 423 if (!ha->req_q_map) { 424 ql_log(ql_log_fatal, vha, 0x003b, 425 "Unable to allocate memory for request queue ptrs.\n"); 426 goto fail_req_map; 427 } 428 429 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 430 GFP_KERNEL); 431 if (!ha->rsp_q_map) { 432 ql_log(ql_log_fatal, vha, 0x003c, 433 "Unable to allocate memory for response queue ptrs.\n"); 434 goto fail_rsp_map; 435 } 436 437 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 438 if (ha->base_qpair == NULL) { 439 ql_log(ql_log_warn, vha, 0x00e0, 440 "Failed to allocate base queue pair memory.\n"); 441 goto fail_base_qpair; 442 } 443 444 qla_init_base_qpair(vha, req, rsp); 445 446 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 447 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 448 GFP_KERNEL); 449 if (!ha->queue_pair_map) { 450 ql_log(ql_log_fatal, vha, 0x0180, 451 "Unable to allocate memory for queue pair ptrs.\n"); 452 goto fail_qpair_map; 453 } 454 } 455 456 /* 457 * Make sure we record at least the request and response queue zero in 458 * case we need to free them if part of the probe fails. 459 */ 460 ha->rsp_q_map[0] = rsp; 461 ha->req_q_map[0] = req; 462 set_bit(0, ha->rsp_qid_map); 463 set_bit(0, ha->req_qid_map); 464 return 0; 465 466 fail_qpair_map: 467 kfree(ha->base_qpair); 468 ha->base_qpair = NULL; 469 fail_base_qpair: 470 kfree(ha->rsp_q_map); 471 ha->rsp_q_map = NULL; 472 fail_rsp_map: 473 kfree(ha->req_q_map); 474 ha->req_q_map = NULL; 475 fail_req_map: 476 return -ENOMEM; 477 } 478 479 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 480 { 481 if (IS_QLAFX00(ha)) { 482 if (req && req->ring_fx00) 483 dma_free_coherent(&ha->pdev->dev, 484 (req->length_fx00 + 1) * sizeof(request_t), 485 req->ring_fx00, req->dma_fx00); 486 } else if (req && req->ring) 487 dma_free_coherent(&ha->pdev->dev, 488 (req->length + 1) * sizeof(request_t), 489 req->ring, req->dma); 490 491 if (req) 492 kfree(req->outstanding_cmds); 493 494 kfree(req); 495 } 496 497 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 498 { 499 if (IS_QLAFX00(ha)) { 500 if (rsp && rsp->ring_fx00) 501 dma_free_coherent(&ha->pdev->dev, 502 (rsp->length_fx00 + 1) * sizeof(request_t), 503 rsp->ring_fx00, rsp->dma_fx00); 504 } else if (rsp && rsp->ring) { 505 dma_free_coherent(&ha->pdev->dev, 506 (rsp->length + 1) * sizeof(response_t), 507 rsp->ring, rsp->dma); 508 } 509 kfree(rsp); 510 } 511 512 static void qla2x00_free_queues(struct qla_hw_data *ha) 513 { 514 struct req_que *req; 515 struct rsp_que *rsp; 516 int cnt; 517 unsigned long flags; 518 519 if (ha->queue_pair_map) { 520 kfree(ha->queue_pair_map); 521 ha->queue_pair_map = NULL; 522 } 523 if (ha->base_qpair) { 524 kfree(ha->base_qpair); 525 ha->base_qpair = NULL; 526 } 527 528 spin_lock_irqsave(&ha->hardware_lock, flags); 529 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 530 if (!test_bit(cnt, ha->req_qid_map)) 531 continue; 532 533 req = ha->req_q_map[cnt]; 534 clear_bit(cnt, ha->req_qid_map); 535 ha->req_q_map[cnt] = NULL; 536 537 spin_unlock_irqrestore(&ha->hardware_lock, flags); 538 qla2x00_free_req_que(ha, req); 539 spin_lock_irqsave(&ha->hardware_lock, flags); 540 } 541 spin_unlock_irqrestore(&ha->hardware_lock, flags); 542 543 kfree(ha->req_q_map); 544 ha->req_q_map = NULL; 545 546 547 spin_lock_irqsave(&ha->hardware_lock, flags); 548 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 549 if (!test_bit(cnt, ha->rsp_qid_map)) 550 continue; 551 552 rsp = ha->rsp_q_map[cnt]; 553 clear_bit(cnt, ha->rsp_qid_map); 554 ha->rsp_q_map[cnt] = NULL; 555 spin_unlock_irqrestore(&ha->hardware_lock, flags); 556 qla2x00_free_rsp_que(ha, rsp); 557 spin_lock_irqsave(&ha->hardware_lock, flags); 558 } 559 spin_unlock_irqrestore(&ha->hardware_lock, flags); 560 561 kfree(ha->rsp_q_map); 562 ha->rsp_q_map = NULL; 563 } 564 565 static char * 566 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 567 { 568 struct qla_hw_data *ha = vha->hw; 569 static const char *const pci_bus_modes[] = { 570 "33", "66", "100", "133", 571 }; 572 uint16_t pci_bus; 573 574 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 575 if (pci_bus) { 576 snprintf(str, str_len, "PCI-X (%s MHz)", 577 pci_bus_modes[pci_bus]); 578 } else { 579 pci_bus = (ha->pci_attr & BIT_8) >> 8; 580 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 581 } 582 583 return str; 584 } 585 586 static char * 587 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 588 { 589 static const char *const pci_bus_modes[] = { 590 "33", "66", "100", "133", 591 }; 592 struct qla_hw_data *ha = vha->hw; 593 uint32_t pci_bus; 594 595 if (pci_is_pcie(ha->pdev)) { 596 uint32_t lstat, lspeed, lwidth; 597 const char *speed_str; 598 599 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 600 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 601 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 602 603 switch (lspeed) { 604 case 1: 605 speed_str = "2.5GT/s"; 606 break; 607 case 2: 608 speed_str = "5.0GT/s"; 609 break; 610 case 3: 611 speed_str = "8.0GT/s"; 612 break; 613 case 4: 614 speed_str = "16.0GT/s"; 615 break; 616 default: 617 speed_str = "<unknown>"; 618 break; 619 } 620 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 621 622 return str; 623 } 624 625 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 626 if (pci_bus == 0 || pci_bus == 8) 627 snprintf(str, str_len, "PCI (%s MHz)", 628 pci_bus_modes[pci_bus >> 3]); 629 else 630 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 631 pci_bus & 4 ? 2 : 1, 632 pci_bus_modes[pci_bus & 3]); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void qla2x00_sp_free_dma(srb_t *sp) 686 { 687 struct qla_hw_data *ha = sp->vha->hw; 688 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 689 690 if (sp->flags & SRB_DMA_VALID) { 691 scsi_dma_unmap(cmd); 692 sp->flags &= ~SRB_DMA_VALID; 693 } 694 695 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 696 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 697 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 698 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 699 } 700 701 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 702 /* List assured to be having elements */ 703 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 704 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 705 } 706 707 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 708 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 709 710 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 711 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 712 } 713 714 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 715 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 716 717 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 718 ctx1->fcp_cmnd_dma); 719 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 720 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 721 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 722 mempool_free(ctx1, ha->ctx_mempool); 723 } 724 } 725 726 void qla2x00_sp_compl(srb_t *sp, int res) 727 { 728 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 729 struct completion *comp = sp->comp; 730 731 sp->free(sp); 732 cmd->result = res; 733 CMD_SP(cmd) = NULL; 734 cmd->scsi_done(cmd); 735 if (comp) 736 complete(comp); 737 } 738 739 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 740 { 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 742 struct qla_hw_data *ha = sp->fcport->vha->hw; 743 744 if (sp->flags & SRB_DMA_VALID) { 745 scsi_dma_unmap(cmd); 746 sp->flags &= ~SRB_DMA_VALID; 747 } 748 749 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 750 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 751 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 752 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 753 } 754 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 756 /* List assured to be having elements */ 757 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 759 } 760 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 762 struct crc_context *difctx = sp->u.scmd.crc_ctx; 763 struct dsd_dma *dif_dsd, *nxt_dsd; 764 765 list_for_each_entry_safe(dif_dsd, nxt_dsd, 766 &difctx->ldif_dma_hndl_list, list) { 767 list_del(&dif_dsd->list); 768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 769 dif_dsd->dsd_list_dma); 770 kfree(dif_dsd); 771 difctx->no_dif_bundl--; 772 } 773 774 list_for_each_entry_safe(dif_dsd, nxt_dsd, 775 &difctx->ldif_dsd_list, list) { 776 list_del(&dif_dsd->list); 777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 778 dif_dsd->dsd_list_dma); 779 kfree(dif_dsd); 780 difctx->no_ldif_dsd--; 781 } 782 783 if (difctx->no_ldif_dsd) { 784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 785 "%s: difctx->no_ldif_dsd=%x\n", 786 __func__, difctx->no_ldif_dsd); 787 } 788 789 if (difctx->no_dif_bundl) { 790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 791 "%s: difctx->no_dif_bundl=%x\n", 792 __func__, difctx->no_dif_bundl); 793 } 794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 795 } 796 797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 798 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 799 800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 801 ctx1->fcp_cmnd_dma); 802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 805 mempool_free(ctx1, ha->ctx_mempool); 806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 807 } 808 809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 810 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 811 812 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 814 } 815 } 816 817 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 818 { 819 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 820 struct completion *comp = sp->comp; 821 822 sp->free(sp); 823 cmd->result = res; 824 CMD_SP(cmd) = NULL; 825 cmd->scsi_done(cmd); 826 if (comp) 827 complete(comp); 828 } 829 830 static int 831 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 832 { 833 scsi_qla_host_t *vha = shost_priv(host); 834 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 835 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 836 struct qla_hw_data *ha = vha->hw; 837 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 838 srb_t *sp; 839 int rval; 840 841 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 842 WARN_ON_ONCE(!rport)) { 843 cmd->result = DID_NO_CONNECT << 16; 844 goto qc24_fail_command; 845 } 846 847 if (ha->mqenable) { 848 uint32_t tag; 849 uint16_t hwq; 850 struct qla_qpair *qpair = NULL; 851 852 tag = blk_mq_unique_tag(cmd->request); 853 hwq = blk_mq_unique_tag_to_hwq(tag); 854 qpair = ha->queue_pair_map[hwq]; 855 856 if (qpair) 857 return qla2xxx_mqueuecommand(host, cmd, qpair); 858 } 859 860 if (ha->flags.eeh_busy) { 861 if (ha->flags.pci_channel_io_perm_failure) { 862 ql_dbg(ql_dbg_aer, vha, 0x9010, 863 "PCI Channel IO permanent failure, exiting " 864 "cmd=%p.\n", cmd); 865 cmd->result = DID_NO_CONNECT << 16; 866 } else { 867 ql_dbg(ql_dbg_aer, vha, 0x9011, 868 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 869 cmd->result = DID_REQUEUE << 16; 870 } 871 goto qc24_fail_command; 872 } 873 874 rval = fc_remote_port_chkready(rport); 875 if (rval) { 876 cmd->result = rval; 877 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 878 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 879 cmd, rval); 880 goto qc24_fail_command; 881 } 882 883 if (!vha->flags.difdix_supported && 884 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 885 ql_dbg(ql_dbg_io, vha, 0x3004, 886 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 887 cmd); 888 cmd->result = DID_NO_CONNECT << 16; 889 goto qc24_fail_command; 890 } 891 892 if (!fcport || fcport->deleted) { 893 cmd->result = DID_IMM_RETRY << 16; 894 goto qc24_fail_command; 895 } 896 897 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 898 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 899 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 900 ql_dbg(ql_dbg_io, vha, 0x3005, 901 "Returning DNC, fcport_state=%d loop_state=%d.\n", 902 atomic_read(&fcport->state), 903 atomic_read(&base_vha->loop_state)); 904 cmd->result = DID_NO_CONNECT << 16; 905 goto qc24_fail_command; 906 } 907 goto qc24_target_busy; 908 } 909 910 /* 911 * Return target busy if we've received a non-zero retry_delay_timer 912 * in a FCP_RSP. 913 */ 914 if (fcport->retry_delay_timestamp == 0) { 915 /* retry delay not set */ 916 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 917 fcport->retry_delay_timestamp = 0; 918 else 919 goto qc24_target_busy; 920 921 sp = scsi_cmd_priv(cmd); 922 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 923 924 sp->u.scmd.cmd = cmd; 925 sp->type = SRB_SCSI_CMD; 926 927 CMD_SP(cmd) = (void *)sp; 928 sp->free = qla2x00_sp_free_dma; 929 sp->done = qla2x00_sp_compl; 930 931 rval = ha->isp_ops->start_scsi(sp); 932 if (rval != QLA_SUCCESS) { 933 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 934 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 935 goto qc24_host_busy_free_sp; 936 } 937 938 return 0; 939 940 qc24_host_busy_free_sp: 941 sp->free(sp); 942 943 qc24_target_busy: 944 return SCSI_MLQUEUE_TARGET_BUSY; 945 946 qc24_fail_command: 947 cmd->scsi_done(cmd); 948 949 return 0; 950 } 951 952 /* For MQ supported I/O */ 953 int 954 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 955 struct qla_qpair *qpair) 956 { 957 scsi_qla_host_t *vha = shost_priv(host); 958 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 959 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 960 struct qla_hw_data *ha = vha->hw; 961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 962 srb_t *sp; 963 int rval; 964 965 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 966 if (rval) { 967 cmd->result = rval; 968 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 969 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 970 cmd, rval); 971 goto qc24_fail_command; 972 } 973 974 if (!fcport || fcport->deleted) { 975 cmd->result = DID_IMM_RETRY << 16; 976 goto qc24_fail_command; 977 } 978 979 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 980 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 981 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 982 ql_dbg(ql_dbg_io, vha, 0x3077, 983 "Returning DNC, fcport_state=%d loop_state=%d.\n", 984 atomic_read(&fcport->state), 985 atomic_read(&base_vha->loop_state)); 986 cmd->result = DID_NO_CONNECT << 16; 987 goto qc24_fail_command; 988 } 989 goto qc24_target_busy; 990 } 991 992 /* 993 * Return target busy if we've received a non-zero retry_delay_timer 994 * in a FCP_RSP. 995 */ 996 if (fcport->retry_delay_timestamp == 0) { 997 /* retry delay not set */ 998 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 999 fcport->retry_delay_timestamp = 0; 1000 else 1001 goto qc24_target_busy; 1002 1003 sp = scsi_cmd_priv(cmd); 1004 qla2xxx_init_sp(sp, vha, qpair, fcport); 1005 1006 sp->u.scmd.cmd = cmd; 1007 sp->type = SRB_SCSI_CMD; 1008 CMD_SP(cmd) = (void *)sp; 1009 sp->free = qla2xxx_qpair_sp_free_dma; 1010 sp->done = qla2xxx_qpair_sp_compl; 1011 1012 rval = ha->isp_ops->start_scsi_mq(sp); 1013 if (rval != QLA_SUCCESS) { 1014 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1015 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1016 if (rval == QLA_INTERFACE_ERROR) 1017 goto qc24_free_sp_fail_command; 1018 goto qc24_host_busy_free_sp; 1019 } 1020 1021 return 0; 1022 1023 qc24_host_busy_free_sp: 1024 sp->free(sp); 1025 1026 qc24_target_busy: 1027 return SCSI_MLQUEUE_TARGET_BUSY; 1028 1029 qc24_free_sp_fail_command: 1030 sp->free(sp); 1031 CMD_SP(cmd) = NULL; 1032 qla2xxx_rel_qpair_sp(sp->qpair, sp); 1033 1034 qc24_fail_command: 1035 cmd->scsi_done(cmd); 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * qla2x00_eh_wait_on_command 1042 * Waits for the command to be returned by the Firmware for some 1043 * max time. 1044 * 1045 * Input: 1046 * cmd = Scsi Command to wait on. 1047 * 1048 * Return: 1049 * Completed in time : QLA_SUCCESS 1050 * Did not complete in time : QLA_FUNCTION_FAILED 1051 */ 1052 static int 1053 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1054 { 1055 #define ABORT_POLLING_PERIOD 1000 1056 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1057 unsigned long wait_iter = ABORT_WAIT_ITER; 1058 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1059 struct qla_hw_data *ha = vha->hw; 1060 int ret = QLA_SUCCESS; 1061 1062 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1063 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1064 "Return:eh_wait.\n"); 1065 return ret; 1066 } 1067 1068 while (CMD_SP(cmd) && wait_iter--) { 1069 msleep(ABORT_POLLING_PERIOD); 1070 } 1071 if (CMD_SP(cmd)) 1072 ret = QLA_FUNCTION_FAILED; 1073 1074 return ret; 1075 } 1076 1077 /* 1078 * qla2x00_wait_for_hba_online 1079 * Wait till the HBA is online after going through 1080 * <= MAX_RETRIES_OF_ISP_ABORT or 1081 * finally HBA is disabled ie marked offline 1082 * 1083 * Input: 1084 * ha - pointer to host adapter structure 1085 * 1086 * Note: 1087 * Does context switching-Release SPIN_LOCK 1088 * (if any) before calling this routine. 1089 * 1090 * Return: 1091 * Success (Adapter is online) : 0 1092 * Failed (Adapter is offline/disabled) : 1 1093 */ 1094 int 1095 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1096 { 1097 int return_status; 1098 unsigned long wait_online; 1099 struct qla_hw_data *ha = vha->hw; 1100 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1101 1102 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1103 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1104 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1105 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1106 ha->dpc_active) && time_before(jiffies, wait_online)) { 1107 1108 msleep(1000); 1109 } 1110 if (base_vha->flags.online) 1111 return_status = QLA_SUCCESS; 1112 else 1113 return_status = QLA_FUNCTION_FAILED; 1114 1115 return (return_status); 1116 } 1117 1118 static inline int test_fcport_count(scsi_qla_host_t *vha) 1119 { 1120 struct qla_hw_data *ha = vha->hw; 1121 unsigned long flags; 1122 int res; 1123 1124 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1125 ql_dbg(ql_dbg_init, vha, 0x00ec, 1126 "tgt %p, fcport_count=%d\n", 1127 vha, vha->fcport_count); 1128 res = (vha->fcport_count == 0); 1129 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1130 1131 return res; 1132 } 1133 1134 /* 1135 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1136 * it has dependency on UNLOADING flag to stop device discovery 1137 */ 1138 void 1139 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1140 { 1141 u8 i; 1142 1143 qla2x00_mark_all_devices_lost(vha); 1144 1145 for (i = 0; i < 10; i++) { 1146 if (wait_event_timeout(vha->fcport_waitQ, 1147 test_fcport_count(vha), HZ) > 0) 1148 break; 1149 } 1150 1151 flush_workqueue(vha->hw->wq); 1152 } 1153 1154 /* 1155 * qla2x00_wait_for_hba_ready 1156 * Wait till the HBA is ready before doing driver unload 1157 * 1158 * Input: 1159 * ha - pointer to host adapter structure 1160 * 1161 * Note: 1162 * Does context switching-Release SPIN_LOCK 1163 * (if any) before calling this routine. 1164 * 1165 */ 1166 static void 1167 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1168 { 1169 struct qla_hw_data *ha = vha->hw; 1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1171 1172 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1173 ha->flags.mbox_busy) || 1174 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1175 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1176 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1177 break; 1178 msleep(1000); 1179 } 1180 } 1181 1182 int 1183 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1184 { 1185 int return_status; 1186 unsigned long wait_reset; 1187 struct qla_hw_data *ha = vha->hw; 1188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1189 1190 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1191 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1192 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1193 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1194 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1195 1196 msleep(1000); 1197 1198 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1199 ha->flags.chip_reset_done) 1200 break; 1201 } 1202 if (ha->flags.chip_reset_done) 1203 return_status = QLA_SUCCESS; 1204 else 1205 return_status = QLA_FUNCTION_FAILED; 1206 1207 return return_status; 1208 } 1209 1210 #define ISP_REG_DISCONNECT 0xffffffffU 1211 /************************************************************************** 1212 * qla2x00_isp_reg_stat 1213 * 1214 * Description: 1215 * Read the host status register of ISP before aborting the command. 1216 * 1217 * Input: 1218 * ha = pointer to host adapter structure. 1219 * 1220 * 1221 * Returns: 1222 * Either true or false. 1223 * 1224 * Note: Return true if there is register disconnect. 1225 **************************************************************************/ 1226 static inline 1227 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1228 { 1229 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1230 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1231 1232 if (IS_P3P_TYPE(ha)) 1233 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT); 1234 else 1235 return ((rd_reg_dword(®->host_status)) == 1236 ISP_REG_DISCONNECT); 1237 } 1238 1239 /************************************************************************** 1240 * qla2xxx_eh_abort 1241 * 1242 * Description: 1243 * The abort function will abort the specified command. 1244 * 1245 * Input: 1246 * cmd = Linux SCSI command packet to be aborted. 1247 * 1248 * Returns: 1249 * Either SUCCESS or FAILED. 1250 * 1251 * Note: 1252 * Only return FAILED if command not returned by firmware. 1253 **************************************************************************/ 1254 static int 1255 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1256 { 1257 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1258 DECLARE_COMPLETION_ONSTACK(comp); 1259 srb_t *sp; 1260 int ret; 1261 unsigned int id; 1262 uint64_t lun; 1263 int rval; 1264 struct qla_hw_data *ha = vha->hw; 1265 uint32_t ratov_j; 1266 struct qla_qpair *qpair; 1267 unsigned long flags; 1268 1269 if (qla2x00_isp_reg_stat(ha)) { 1270 ql_log(ql_log_info, vha, 0x8042, 1271 "PCI/Register disconnect, exiting.\n"); 1272 return FAILED; 1273 } 1274 1275 ret = fc_block_scsi_eh(cmd); 1276 if (ret != 0) 1277 return ret; 1278 1279 sp = scsi_cmd_priv(cmd); 1280 qpair = sp->qpair; 1281 1282 vha->cmd_timeout_cnt++; 1283 1284 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1285 return SUCCESS; 1286 1287 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1288 sp->comp = ∁ 1289 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1290 1291 1292 id = cmd->device->id; 1293 lun = cmd->device->lun; 1294 1295 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1296 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1297 vha->host_no, id, lun, sp, cmd, sp->handle); 1298 1299 /* 1300 * Abort will release the original Command/sp from FW. Let the 1301 * original command call scsi_done. In return, he will wakeup 1302 * this sleeping thread. 1303 */ 1304 rval = ha->isp_ops->abort_command(sp); 1305 1306 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1307 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1308 1309 /* Wait for the command completion. */ 1310 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1311 ratov_j = msecs_to_jiffies(ratov_j); 1312 switch (rval) { 1313 case QLA_SUCCESS: 1314 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1315 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1316 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1317 __func__, ha->r_a_tov/10); 1318 ret = FAILED; 1319 } else { 1320 ret = SUCCESS; 1321 } 1322 break; 1323 default: 1324 ret = FAILED; 1325 break; 1326 } 1327 1328 sp->comp = NULL; 1329 1330 ql_log(ql_log_info, vha, 0x801c, 1331 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1332 vha->host_no, id, lun, ret); 1333 1334 return ret; 1335 } 1336 1337 /* 1338 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1339 */ 1340 int 1341 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1342 uint64_t l, enum nexus_wait_type type) 1343 { 1344 int cnt, match, status; 1345 unsigned long flags; 1346 struct qla_hw_data *ha = vha->hw; 1347 struct req_que *req; 1348 srb_t *sp; 1349 struct scsi_cmnd *cmd; 1350 1351 status = QLA_SUCCESS; 1352 1353 spin_lock_irqsave(&ha->hardware_lock, flags); 1354 req = vha->req; 1355 for (cnt = 1; status == QLA_SUCCESS && 1356 cnt < req->num_outstanding_cmds; cnt++) { 1357 sp = req->outstanding_cmds[cnt]; 1358 if (!sp) 1359 continue; 1360 if (sp->type != SRB_SCSI_CMD) 1361 continue; 1362 if (vha->vp_idx != sp->vha->vp_idx) 1363 continue; 1364 match = 0; 1365 cmd = GET_CMD_SP(sp); 1366 switch (type) { 1367 case WAIT_HOST: 1368 match = 1; 1369 break; 1370 case WAIT_TARGET: 1371 match = cmd->device->id == t; 1372 break; 1373 case WAIT_LUN: 1374 match = (cmd->device->id == t && 1375 cmd->device->lun == l); 1376 break; 1377 } 1378 if (!match) 1379 continue; 1380 1381 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1382 status = qla2x00_eh_wait_on_command(cmd); 1383 spin_lock_irqsave(&ha->hardware_lock, flags); 1384 } 1385 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1386 1387 return status; 1388 } 1389 1390 static char *reset_errors[] = { 1391 "HBA not online", 1392 "HBA not ready", 1393 "Task management failed", 1394 "Waiting for command completions", 1395 }; 1396 1397 static int 1398 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1399 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1400 { 1401 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1402 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1403 int err; 1404 1405 if (!fcport) { 1406 return FAILED; 1407 } 1408 1409 err = fc_block_scsi_eh(cmd); 1410 if (err != 0) 1411 return err; 1412 1413 if (fcport->deleted) 1414 return SUCCESS; 1415 1416 ql_log(ql_log_info, vha, 0x8009, 1417 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1418 cmd->device->id, cmd->device->lun, cmd); 1419 1420 err = 0; 1421 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1422 ql_log(ql_log_warn, vha, 0x800a, 1423 "Wait for hba online failed for cmd=%p.\n", cmd); 1424 goto eh_reset_failed; 1425 } 1426 err = 2; 1427 if (do_reset(fcport, cmd->device->lun, 1) 1428 != QLA_SUCCESS) { 1429 ql_log(ql_log_warn, vha, 0x800c, 1430 "do_reset failed for cmd=%p.\n", cmd); 1431 goto eh_reset_failed; 1432 } 1433 err = 3; 1434 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1435 cmd->device->lun, type) != QLA_SUCCESS) { 1436 ql_log(ql_log_warn, vha, 0x800d, 1437 "wait for pending cmds failed for cmd=%p.\n", cmd); 1438 goto eh_reset_failed; 1439 } 1440 1441 ql_log(ql_log_info, vha, 0x800e, 1442 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1443 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1444 1445 return SUCCESS; 1446 1447 eh_reset_failed: 1448 ql_log(ql_log_info, vha, 0x800f, 1449 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1450 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1451 cmd); 1452 vha->reset_cmd_err_cnt++; 1453 return FAILED; 1454 } 1455 1456 static int 1457 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1458 { 1459 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1460 struct qla_hw_data *ha = vha->hw; 1461 1462 if (qla2x00_isp_reg_stat(ha)) { 1463 ql_log(ql_log_info, vha, 0x803e, 1464 "PCI/Register disconnect, exiting.\n"); 1465 return FAILED; 1466 } 1467 1468 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1469 ha->isp_ops->lun_reset); 1470 } 1471 1472 static int 1473 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1474 { 1475 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1476 struct qla_hw_data *ha = vha->hw; 1477 1478 if (qla2x00_isp_reg_stat(ha)) { 1479 ql_log(ql_log_info, vha, 0x803f, 1480 "PCI/Register disconnect, exiting.\n"); 1481 return FAILED; 1482 } 1483 1484 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1485 ha->isp_ops->target_reset); 1486 } 1487 1488 /************************************************************************** 1489 * qla2xxx_eh_bus_reset 1490 * 1491 * Description: 1492 * The bus reset function will reset the bus and abort any executing 1493 * commands. 1494 * 1495 * Input: 1496 * cmd = Linux SCSI command packet of the command that cause the 1497 * bus reset. 1498 * 1499 * Returns: 1500 * SUCCESS/FAILURE (defined as macro in scsi.h). 1501 * 1502 **************************************************************************/ 1503 static int 1504 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1505 { 1506 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1507 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1508 int ret = FAILED; 1509 unsigned int id; 1510 uint64_t lun; 1511 struct qla_hw_data *ha = vha->hw; 1512 1513 if (qla2x00_isp_reg_stat(ha)) { 1514 ql_log(ql_log_info, vha, 0x8040, 1515 "PCI/Register disconnect, exiting.\n"); 1516 return FAILED; 1517 } 1518 1519 id = cmd->device->id; 1520 lun = cmd->device->lun; 1521 1522 if (!fcport) { 1523 return ret; 1524 } 1525 1526 ret = fc_block_scsi_eh(cmd); 1527 if (ret != 0) 1528 return ret; 1529 ret = FAILED; 1530 1531 if (qla2x00_chip_is_down(vha)) 1532 return ret; 1533 1534 ql_log(ql_log_info, vha, 0x8012, 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1536 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1538 ql_log(ql_log_fatal, vha, 0x8013, 1539 "Wait for hba online failed board disabled.\n"); 1540 goto eh_bus_reset_done; 1541 } 1542 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1544 ret = SUCCESS; 1545 1546 if (ret == FAILED) 1547 goto eh_bus_reset_done; 1548 1549 /* Flush outstanding commands. */ 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1551 QLA_SUCCESS) { 1552 ql_log(ql_log_warn, vha, 0x8014, 1553 "Wait for pending commands failed.\n"); 1554 ret = FAILED; 1555 } 1556 1557 eh_bus_reset_done: 1558 ql_log(ql_log_warn, vha, 0x802b, 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1561 1562 return ret; 1563 } 1564 1565 /************************************************************************** 1566 * qla2xxx_eh_host_reset 1567 * 1568 * Description: 1569 * The reset function will reset the Adapter. 1570 * 1571 * Input: 1572 * cmd = Linux SCSI command packet of the command that cause the 1573 * adapter reset. 1574 * 1575 * Returns: 1576 * Either SUCCESS or FAILED. 1577 * 1578 * Note: 1579 **************************************************************************/ 1580 static int 1581 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1582 { 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1584 struct qla_hw_data *ha = vha->hw; 1585 int ret = FAILED; 1586 unsigned int id; 1587 uint64_t lun; 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1589 1590 if (qla2x00_isp_reg_stat(ha)) { 1591 ql_log(ql_log_info, vha, 0x8041, 1592 "PCI/Register disconnect, exiting.\n"); 1593 schedule_work(&ha->board_disable); 1594 return SUCCESS; 1595 } 1596 1597 id = cmd->device->id; 1598 lun = cmd->device->lun; 1599 1600 ql_log(ql_log_info, vha, 0x8018, 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1602 1603 /* 1604 * No point in issuing another reset if one is active. Also do not 1605 * attempt a reset if we are updating flash. 1606 */ 1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1608 goto eh_host_reset_lock; 1609 1610 if (vha != base_vha) { 1611 if (qla2x00_vp_abort_isp(vha)) 1612 goto eh_host_reset_lock; 1613 } else { 1614 if (IS_P3P_TYPE(vha->hw)) { 1615 if (!qla82xx_fcoe_ctx_reset(vha)) { 1616 /* Ctx reset success */ 1617 ret = SUCCESS; 1618 goto eh_host_reset_lock; 1619 } 1620 /* fall thru if ctx reset failed */ 1621 } 1622 if (ha->wq) 1623 flush_workqueue(ha->wq); 1624 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 if (ha->isp_ops->abort_isp(base_vha)) { 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1628 /* failed. schedule dpc to try */ 1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1630 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1632 ql_log(ql_log_warn, vha, 0x802a, 1633 "wait for hba online failed.\n"); 1634 goto eh_host_reset_lock; 1635 } 1636 } 1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1638 } 1639 1640 /* Waiting for command to be returned to OS.*/ 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1642 QLA_SUCCESS) 1643 ret = SUCCESS; 1644 1645 eh_host_reset_lock: 1646 ql_log(ql_log_info, vha, 0x8017, 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1649 1650 return ret; 1651 } 1652 1653 /* 1654 * qla2x00_loop_reset 1655 * Issue loop reset. 1656 * 1657 * Input: 1658 * ha = adapter block pointer. 1659 * 1660 * Returns: 1661 * 0 = success 1662 */ 1663 int 1664 qla2x00_loop_reset(scsi_qla_host_t *vha) 1665 { 1666 int ret; 1667 struct fc_port *fcport; 1668 struct qla_hw_data *ha = vha->hw; 1669 1670 if (IS_QLAFX00(ha)) { 1671 return qlafx00_loop_reset(vha); 1672 } 1673 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1676 if (fcport->port_type != FCT_TARGET) 1677 continue; 1678 1679 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1680 if (ret != QLA_SUCCESS) { 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1682 "Bus Reset failed: Reset=%d " 1683 "d_id=%x.\n", ret, fcport->d_id.b24); 1684 } 1685 } 1686 } 1687 1688 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1690 atomic_set(&vha->loop_state, LOOP_DOWN); 1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1692 qla2x00_mark_all_devices_lost(vha); 1693 ret = qla2x00_full_login_lip(vha); 1694 if (ret != QLA_SUCCESS) { 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1696 "full_login_lip=%d.\n", ret); 1697 } 1698 } 1699 1700 if (ha->flags.enable_lip_reset) { 1701 ret = qla2x00_lip_reset(vha); 1702 if (ret != QLA_SUCCESS) 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1704 "lip_reset failed (%d).\n", ret); 1705 } 1706 1707 /* Issue marker command only when we are going to start the I/O */ 1708 vha->marker_needed = 1; 1709 1710 return QLA_SUCCESS; 1711 } 1712 1713 /* 1714 * The caller must ensure that no completion interrupts will happen 1715 * while this function is in progress. 1716 */ 1717 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1718 unsigned long *flags) 1719 __releases(qp->qp_lock_ptr) 1720 __acquires(qp->qp_lock_ptr) 1721 { 1722 DECLARE_COMPLETION_ONSTACK(comp); 1723 scsi_qla_host_t *vha = qp->vha; 1724 struct qla_hw_data *ha = vha->hw; 1725 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1726 int rval; 1727 bool ret_cmd; 1728 uint32_t ratov_j; 1729 1730 lockdep_assert_held(qp->qp_lock_ptr); 1731 1732 if (qla2x00_chip_is_down(vha)) { 1733 sp->done(sp, res); 1734 return; 1735 } 1736 1737 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1738 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1739 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1740 !qla2x00_isp_reg_stat(ha))) { 1741 if (sp->comp) { 1742 sp->done(sp, res); 1743 return; 1744 } 1745 1746 sp->comp = ∁ 1747 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1748 1749 rval = ha->isp_ops->abort_command(sp); 1750 /* Wait for command completion. */ 1751 ret_cmd = false; 1752 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1753 ratov_j = msecs_to_jiffies(ratov_j); 1754 switch (rval) { 1755 case QLA_SUCCESS: 1756 if (wait_for_completion_timeout(&comp, ratov_j)) { 1757 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1758 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1759 __func__, ha->r_a_tov/10); 1760 ret_cmd = true; 1761 } 1762 /* else FW return SP to driver */ 1763 break; 1764 default: 1765 ret_cmd = true; 1766 break; 1767 } 1768 1769 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1770 if (ret_cmd && blk_mq_request_started(cmd->request)) 1771 sp->done(sp, res); 1772 } else { 1773 sp->done(sp, res); 1774 } 1775 } 1776 1777 /* 1778 * The caller must ensure that no completion interrupts will happen 1779 * while this function is in progress. 1780 */ 1781 static void 1782 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1783 { 1784 int cnt; 1785 unsigned long flags; 1786 srb_t *sp; 1787 scsi_qla_host_t *vha = qp->vha; 1788 struct qla_hw_data *ha = vha->hw; 1789 struct req_que *req; 1790 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1791 struct qla_tgt_cmd *cmd; 1792 1793 if (!ha->req_q_map) 1794 return; 1795 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1796 req = qp->req; 1797 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1798 sp = req->outstanding_cmds[cnt]; 1799 if (sp) { 1800 switch (sp->cmd_type) { 1801 case TYPE_SRB: 1802 qla2x00_abort_srb(qp, sp, res, &flags); 1803 break; 1804 case TYPE_TGT_CMD: 1805 if (!vha->hw->tgt.tgt_ops || !tgt || 1806 qla_ini_mode_enabled(vha)) { 1807 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1808 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1809 vha->dpc_flags); 1810 continue; 1811 } 1812 cmd = (struct qla_tgt_cmd *)sp; 1813 cmd->aborted = 1; 1814 break; 1815 case TYPE_TGT_TMCMD: 1816 /* Skip task management functions. */ 1817 break; 1818 default: 1819 break; 1820 } 1821 req->outstanding_cmds[cnt] = NULL; 1822 } 1823 } 1824 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1825 } 1826 1827 /* 1828 * The caller must ensure that no completion interrupts will happen 1829 * while this function is in progress. 1830 */ 1831 void 1832 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1833 { 1834 int que; 1835 struct qla_hw_data *ha = vha->hw; 1836 1837 /* Continue only if initialization complete. */ 1838 if (!ha->base_qpair) 1839 return; 1840 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1841 1842 if (!ha->queue_pair_map) 1843 return; 1844 for (que = 0; que < ha->max_qpairs; que++) { 1845 if (!ha->queue_pair_map[que]) 1846 continue; 1847 1848 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1849 } 1850 } 1851 1852 static int 1853 qla2xxx_slave_alloc(struct scsi_device *sdev) 1854 { 1855 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1856 1857 if (!rport || fc_remote_port_chkready(rport)) 1858 return -ENXIO; 1859 1860 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1861 1862 return 0; 1863 } 1864 1865 static int 1866 qla2xxx_slave_configure(struct scsi_device *sdev) 1867 { 1868 scsi_qla_host_t *vha = shost_priv(sdev->host); 1869 struct req_que *req = vha->req; 1870 1871 if (IS_T10_PI_CAPABLE(vha->hw)) 1872 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1873 1874 scsi_change_queue_depth(sdev, req->max_q_depth); 1875 return 0; 1876 } 1877 1878 static void 1879 qla2xxx_slave_destroy(struct scsi_device *sdev) 1880 { 1881 sdev->hostdata = NULL; 1882 } 1883 1884 /** 1885 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1886 * @ha: HA context 1887 * 1888 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1889 * supported addressing method. 1890 */ 1891 static void 1892 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1893 { 1894 /* Assume a 32bit DMA mask. */ 1895 ha->flags.enable_64bit_addressing = 0; 1896 1897 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1898 /* Any upper-dword bits set? */ 1899 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1900 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1901 /* Ok, a 64bit DMA mask is applicable. */ 1902 ha->flags.enable_64bit_addressing = 1; 1903 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1904 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1905 return; 1906 } 1907 } 1908 1909 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1910 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1911 } 1912 1913 static void 1914 qla2x00_enable_intrs(struct qla_hw_data *ha) 1915 { 1916 unsigned long flags = 0; 1917 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1918 1919 spin_lock_irqsave(&ha->hardware_lock, flags); 1920 ha->interrupts_on = 1; 1921 /* enable risc and host interrupts */ 1922 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1923 rd_reg_word(®->ictrl); 1924 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1925 1926 } 1927 1928 static void 1929 qla2x00_disable_intrs(struct qla_hw_data *ha) 1930 { 1931 unsigned long flags = 0; 1932 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1933 1934 spin_lock_irqsave(&ha->hardware_lock, flags); 1935 ha->interrupts_on = 0; 1936 /* disable risc and host interrupts */ 1937 wrt_reg_word(®->ictrl, 0); 1938 rd_reg_word(®->ictrl); 1939 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1940 } 1941 1942 static void 1943 qla24xx_enable_intrs(struct qla_hw_data *ha) 1944 { 1945 unsigned long flags = 0; 1946 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1947 1948 spin_lock_irqsave(&ha->hardware_lock, flags); 1949 ha->interrupts_on = 1; 1950 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1951 rd_reg_dword(®->ictrl); 1952 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1953 } 1954 1955 static void 1956 qla24xx_disable_intrs(struct qla_hw_data *ha) 1957 { 1958 unsigned long flags = 0; 1959 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1960 1961 if (IS_NOPOLLING_TYPE(ha)) 1962 return; 1963 spin_lock_irqsave(&ha->hardware_lock, flags); 1964 ha->interrupts_on = 0; 1965 wrt_reg_dword(®->ictrl, 0); 1966 rd_reg_dword(®->ictrl); 1967 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1968 } 1969 1970 static int 1971 qla2x00_iospace_config(struct qla_hw_data *ha) 1972 { 1973 resource_size_t pio; 1974 uint16_t msix; 1975 1976 if (pci_request_selected_regions(ha->pdev, ha->bars, 1977 QLA2XXX_DRIVER_NAME)) { 1978 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1979 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1980 pci_name(ha->pdev)); 1981 goto iospace_error_exit; 1982 } 1983 if (!(ha->bars & 1)) 1984 goto skip_pio; 1985 1986 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1987 pio = pci_resource_start(ha->pdev, 0); 1988 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1989 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1990 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1991 "Invalid pci I/O region size (%s).\n", 1992 pci_name(ha->pdev)); 1993 pio = 0; 1994 } 1995 } else { 1996 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1997 "Region #0 no a PIO resource (%s).\n", 1998 pci_name(ha->pdev)); 1999 pio = 0; 2000 } 2001 ha->pio_address = pio; 2002 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2003 "PIO address=%llu.\n", 2004 (unsigned long long)ha->pio_address); 2005 2006 skip_pio: 2007 /* Use MMIO operations for all accesses. */ 2008 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2010 "Region #1 not an MMIO resource (%s), aborting.\n", 2011 pci_name(ha->pdev)); 2012 goto iospace_error_exit; 2013 } 2014 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2015 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2016 "Invalid PCI mem region size (%s), aborting.\n", 2017 pci_name(ha->pdev)); 2018 goto iospace_error_exit; 2019 } 2020 2021 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2022 if (!ha->iobase) { 2023 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2024 "Cannot remap MMIO (%s), aborting.\n", 2025 pci_name(ha->pdev)); 2026 goto iospace_error_exit; 2027 } 2028 2029 /* Determine queue resources */ 2030 ha->max_req_queues = ha->max_rsp_queues = 1; 2031 ha->msix_count = QLA_BASE_VECTORS; 2032 2033 /* Check if FW supports MQ or not */ 2034 if (!(ha->fw_attributes & BIT_6)) 2035 goto mqiobase_exit; 2036 2037 if (!ql2xmqsupport || !ql2xnvmeenable || 2038 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2039 goto mqiobase_exit; 2040 2041 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2042 pci_resource_len(ha->pdev, 3)); 2043 if (ha->mqiobase) { 2044 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2045 "MQIO Base=%p.\n", ha->mqiobase); 2046 /* Read MSIX vector size of the board */ 2047 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2048 ha->msix_count = msix + 1; 2049 /* Max queues are bounded by available msix vectors */ 2050 /* MB interrupt uses 1 vector */ 2051 ha->max_req_queues = ha->msix_count - 1; 2052 ha->max_rsp_queues = ha->max_req_queues; 2053 /* Queue pairs is the max value minus the base queue pair */ 2054 ha->max_qpairs = ha->max_rsp_queues - 1; 2055 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2056 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2057 2058 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2059 "MSI-X vector count: %d.\n", ha->msix_count); 2060 } else 2061 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2062 "BAR 3 not enabled.\n"); 2063 2064 mqiobase_exit: 2065 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2066 "MSIX Count: %d.\n", ha->msix_count); 2067 return (0); 2068 2069 iospace_error_exit: 2070 return (-ENOMEM); 2071 } 2072 2073 2074 static int 2075 qla83xx_iospace_config(struct qla_hw_data *ha) 2076 { 2077 uint16_t msix; 2078 2079 if (pci_request_selected_regions(ha->pdev, ha->bars, 2080 QLA2XXX_DRIVER_NAME)) { 2081 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2082 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2083 pci_name(ha->pdev)); 2084 2085 goto iospace_error_exit; 2086 } 2087 2088 /* Use MMIO operations for all accesses. */ 2089 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2090 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2091 "Invalid pci I/O region size (%s).\n", 2092 pci_name(ha->pdev)); 2093 goto iospace_error_exit; 2094 } 2095 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2096 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2097 "Invalid PCI mem region size (%s), aborting\n", 2098 pci_name(ha->pdev)); 2099 goto iospace_error_exit; 2100 } 2101 2102 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2103 if (!ha->iobase) { 2104 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2105 "Cannot remap MMIO (%s), aborting.\n", 2106 pci_name(ha->pdev)); 2107 goto iospace_error_exit; 2108 } 2109 2110 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2111 /* 83XX 26XX always use MQ type access for queues 2112 * - mbar 2, a.k.a region 4 */ 2113 ha->max_req_queues = ha->max_rsp_queues = 1; 2114 ha->msix_count = QLA_BASE_VECTORS; 2115 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2116 pci_resource_len(ha->pdev, 4)); 2117 2118 if (!ha->mqiobase) { 2119 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2120 "BAR2/region4 not enabled\n"); 2121 goto mqiobase_exit; 2122 } 2123 2124 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2125 pci_resource_len(ha->pdev, 2)); 2126 if (ha->msixbase) { 2127 /* Read MSIX vector size of the board */ 2128 pci_read_config_word(ha->pdev, 2129 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2130 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2131 /* 2132 * By default, driver uses at least two msix vectors 2133 * (default & rspq) 2134 */ 2135 if (ql2xmqsupport || ql2xnvmeenable) { 2136 /* MB interrupt uses 1 vector */ 2137 ha->max_req_queues = ha->msix_count - 1; 2138 2139 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2140 if (QLA_TGT_MODE_ENABLED()) 2141 ha->max_req_queues--; 2142 2143 ha->max_rsp_queues = ha->max_req_queues; 2144 2145 /* Queue pairs is the max value minus 2146 * the base queue pair */ 2147 ha->max_qpairs = ha->max_req_queues - 1; 2148 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2149 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2150 } 2151 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2152 "MSI-X vector count: %d.\n", ha->msix_count); 2153 } else 2154 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2155 "BAR 1 not enabled.\n"); 2156 2157 mqiobase_exit: 2158 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2159 "MSIX Count: %d.\n", ha->msix_count); 2160 return 0; 2161 2162 iospace_error_exit: 2163 return -ENOMEM; 2164 } 2165 2166 static struct isp_operations qla2100_isp_ops = { 2167 .pci_config = qla2100_pci_config, 2168 .reset_chip = qla2x00_reset_chip, 2169 .chip_diag = qla2x00_chip_diag, 2170 .config_rings = qla2x00_config_rings, 2171 .reset_adapter = qla2x00_reset_adapter, 2172 .nvram_config = qla2x00_nvram_config, 2173 .update_fw_options = qla2x00_update_fw_options, 2174 .load_risc = qla2x00_load_risc, 2175 .pci_info_str = qla2x00_pci_info_str, 2176 .fw_version_str = qla2x00_fw_version_str, 2177 .intr_handler = qla2100_intr_handler, 2178 .enable_intrs = qla2x00_enable_intrs, 2179 .disable_intrs = qla2x00_disable_intrs, 2180 .abort_command = qla2x00_abort_command, 2181 .target_reset = qla2x00_abort_target, 2182 .lun_reset = qla2x00_lun_reset, 2183 .fabric_login = qla2x00_login_fabric, 2184 .fabric_logout = qla2x00_fabric_logout, 2185 .calc_req_entries = qla2x00_calc_iocbs_32, 2186 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2187 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2188 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2189 .read_nvram = qla2x00_read_nvram_data, 2190 .write_nvram = qla2x00_write_nvram_data, 2191 .fw_dump = qla2100_fw_dump, 2192 .beacon_on = NULL, 2193 .beacon_off = NULL, 2194 .beacon_blink = NULL, 2195 .read_optrom = qla2x00_read_optrom_data, 2196 .write_optrom = qla2x00_write_optrom_data, 2197 .get_flash_version = qla2x00_get_flash_version, 2198 .start_scsi = qla2x00_start_scsi, 2199 .start_scsi_mq = NULL, 2200 .abort_isp = qla2x00_abort_isp, 2201 .iospace_config = qla2x00_iospace_config, 2202 .initialize_adapter = qla2x00_initialize_adapter, 2203 }; 2204 2205 static struct isp_operations qla2300_isp_ops = { 2206 .pci_config = qla2300_pci_config, 2207 .reset_chip = qla2x00_reset_chip, 2208 .chip_diag = qla2x00_chip_diag, 2209 .config_rings = qla2x00_config_rings, 2210 .reset_adapter = qla2x00_reset_adapter, 2211 .nvram_config = qla2x00_nvram_config, 2212 .update_fw_options = qla2x00_update_fw_options, 2213 .load_risc = qla2x00_load_risc, 2214 .pci_info_str = qla2x00_pci_info_str, 2215 .fw_version_str = qla2x00_fw_version_str, 2216 .intr_handler = qla2300_intr_handler, 2217 .enable_intrs = qla2x00_enable_intrs, 2218 .disable_intrs = qla2x00_disable_intrs, 2219 .abort_command = qla2x00_abort_command, 2220 .target_reset = qla2x00_abort_target, 2221 .lun_reset = qla2x00_lun_reset, 2222 .fabric_login = qla2x00_login_fabric, 2223 .fabric_logout = qla2x00_fabric_logout, 2224 .calc_req_entries = qla2x00_calc_iocbs_32, 2225 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2226 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2227 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2228 .read_nvram = qla2x00_read_nvram_data, 2229 .write_nvram = qla2x00_write_nvram_data, 2230 .fw_dump = qla2300_fw_dump, 2231 .beacon_on = qla2x00_beacon_on, 2232 .beacon_off = qla2x00_beacon_off, 2233 .beacon_blink = qla2x00_beacon_blink, 2234 .read_optrom = qla2x00_read_optrom_data, 2235 .write_optrom = qla2x00_write_optrom_data, 2236 .get_flash_version = qla2x00_get_flash_version, 2237 .start_scsi = qla2x00_start_scsi, 2238 .start_scsi_mq = NULL, 2239 .abort_isp = qla2x00_abort_isp, 2240 .iospace_config = qla2x00_iospace_config, 2241 .initialize_adapter = qla2x00_initialize_adapter, 2242 }; 2243 2244 static struct isp_operations qla24xx_isp_ops = { 2245 .pci_config = qla24xx_pci_config, 2246 .reset_chip = qla24xx_reset_chip, 2247 .chip_diag = qla24xx_chip_diag, 2248 .config_rings = qla24xx_config_rings, 2249 .reset_adapter = qla24xx_reset_adapter, 2250 .nvram_config = qla24xx_nvram_config, 2251 .update_fw_options = qla24xx_update_fw_options, 2252 .load_risc = qla24xx_load_risc, 2253 .pci_info_str = qla24xx_pci_info_str, 2254 .fw_version_str = qla24xx_fw_version_str, 2255 .intr_handler = qla24xx_intr_handler, 2256 .enable_intrs = qla24xx_enable_intrs, 2257 .disable_intrs = qla24xx_disable_intrs, 2258 .abort_command = qla24xx_abort_command, 2259 .target_reset = qla24xx_abort_target, 2260 .lun_reset = qla24xx_lun_reset, 2261 .fabric_login = qla24xx_login_fabric, 2262 .fabric_logout = qla24xx_fabric_logout, 2263 .calc_req_entries = NULL, 2264 .build_iocbs = NULL, 2265 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2266 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2267 .read_nvram = qla24xx_read_nvram_data, 2268 .write_nvram = qla24xx_write_nvram_data, 2269 .fw_dump = qla24xx_fw_dump, 2270 .beacon_on = qla24xx_beacon_on, 2271 .beacon_off = qla24xx_beacon_off, 2272 .beacon_blink = qla24xx_beacon_blink, 2273 .read_optrom = qla24xx_read_optrom_data, 2274 .write_optrom = qla24xx_write_optrom_data, 2275 .get_flash_version = qla24xx_get_flash_version, 2276 .start_scsi = qla24xx_start_scsi, 2277 .start_scsi_mq = NULL, 2278 .abort_isp = qla2x00_abort_isp, 2279 .iospace_config = qla2x00_iospace_config, 2280 .initialize_adapter = qla2x00_initialize_adapter, 2281 }; 2282 2283 static struct isp_operations qla25xx_isp_ops = { 2284 .pci_config = qla25xx_pci_config, 2285 .reset_chip = qla24xx_reset_chip, 2286 .chip_diag = qla24xx_chip_diag, 2287 .config_rings = qla24xx_config_rings, 2288 .reset_adapter = qla24xx_reset_adapter, 2289 .nvram_config = qla24xx_nvram_config, 2290 .update_fw_options = qla24xx_update_fw_options, 2291 .load_risc = qla24xx_load_risc, 2292 .pci_info_str = qla24xx_pci_info_str, 2293 .fw_version_str = qla24xx_fw_version_str, 2294 .intr_handler = qla24xx_intr_handler, 2295 .enable_intrs = qla24xx_enable_intrs, 2296 .disable_intrs = qla24xx_disable_intrs, 2297 .abort_command = qla24xx_abort_command, 2298 .target_reset = qla24xx_abort_target, 2299 .lun_reset = qla24xx_lun_reset, 2300 .fabric_login = qla24xx_login_fabric, 2301 .fabric_logout = qla24xx_fabric_logout, 2302 .calc_req_entries = NULL, 2303 .build_iocbs = NULL, 2304 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2305 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2306 .read_nvram = qla25xx_read_nvram_data, 2307 .write_nvram = qla25xx_write_nvram_data, 2308 .fw_dump = qla25xx_fw_dump, 2309 .beacon_on = qla24xx_beacon_on, 2310 .beacon_off = qla24xx_beacon_off, 2311 .beacon_blink = qla24xx_beacon_blink, 2312 .read_optrom = qla25xx_read_optrom_data, 2313 .write_optrom = qla24xx_write_optrom_data, 2314 .get_flash_version = qla24xx_get_flash_version, 2315 .start_scsi = qla24xx_dif_start_scsi, 2316 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2317 .abort_isp = qla2x00_abort_isp, 2318 .iospace_config = qla2x00_iospace_config, 2319 .initialize_adapter = qla2x00_initialize_adapter, 2320 }; 2321 2322 static struct isp_operations qla81xx_isp_ops = { 2323 .pci_config = qla25xx_pci_config, 2324 .reset_chip = qla24xx_reset_chip, 2325 .chip_diag = qla24xx_chip_diag, 2326 .config_rings = qla24xx_config_rings, 2327 .reset_adapter = qla24xx_reset_adapter, 2328 .nvram_config = qla81xx_nvram_config, 2329 .update_fw_options = qla24xx_update_fw_options, 2330 .load_risc = qla81xx_load_risc, 2331 .pci_info_str = qla24xx_pci_info_str, 2332 .fw_version_str = qla24xx_fw_version_str, 2333 .intr_handler = qla24xx_intr_handler, 2334 .enable_intrs = qla24xx_enable_intrs, 2335 .disable_intrs = qla24xx_disable_intrs, 2336 .abort_command = qla24xx_abort_command, 2337 .target_reset = qla24xx_abort_target, 2338 .lun_reset = qla24xx_lun_reset, 2339 .fabric_login = qla24xx_login_fabric, 2340 .fabric_logout = qla24xx_fabric_logout, 2341 .calc_req_entries = NULL, 2342 .build_iocbs = NULL, 2343 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2344 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2345 .read_nvram = NULL, 2346 .write_nvram = NULL, 2347 .fw_dump = qla81xx_fw_dump, 2348 .beacon_on = qla24xx_beacon_on, 2349 .beacon_off = qla24xx_beacon_off, 2350 .beacon_blink = qla83xx_beacon_blink, 2351 .read_optrom = qla25xx_read_optrom_data, 2352 .write_optrom = qla24xx_write_optrom_data, 2353 .get_flash_version = qla24xx_get_flash_version, 2354 .start_scsi = qla24xx_dif_start_scsi, 2355 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2356 .abort_isp = qla2x00_abort_isp, 2357 .iospace_config = qla2x00_iospace_config, 2358 .initialize_adapter = qla2x00_initialize_adapter, 2359 }; 2360 2361 static struct isp_operations qla82xx_isp_ops = { 2362 .pci_config = qla82xx_pci_config, 2363 .reset_chip = qla82xx_reset_chip, 2364 .chip_diag = qla24xx_chip_diag, 2365 .config_rings = qla82xx_config_rings, 2366 .reset_adapter = qla24xx_reset_adapter, 2367 .nvram_config = qla81xx_nvram_config, 2368 .update_fw_options = qla24xx_update_fw_options, 2369 .load_risc = qla82xx_load_risc, 2370 .pci_info_str = qla24xx_pci_info_str, 2371 .fw_version_str = qla24xx_fw_version_str, 2372 .intr_handler = qla82xx_intr_handler, 2373 .enable_intrs = qla82xx_enable_intrs, 2374 .disable_intrs = qla82xx_disable_intrs, 2375 .abort_command = qla24xx_abort_command, 2376 .target_reset = qla24xx_abort_target, 2377 .lun_reset = qla24xx_lun_reset, 2378 .fabric_login = qla24xx_login_fabric, 2379 .fabric_logout = qla24xx_fabric_logout, 2380 .calc_req_entries = NULL, 2381 .build_iocbs = NULL, 2382 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2383 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2384 .read_nvram = qla24xx_read_nvram_data, 2385 .write_nvram = qla24xx_write_nvram_data, 2386 .fw_dump = qla82xx_fw_dump, 2387 .beacon_on = qla82xx_beacon_on, 2388 .beacon_off = qla82xx_beacon_off, 2389 .beacon_blink = NULL, 2390 .read_optrom = qla82xx_read_optrom_data, 2391 .write_optrom = qla82xx_write_optrom_data, 2392 .get_flash_version = qla82xx_get_flash_version, 2393 .start_scsi = qla82xx_start_scsi, 2394 .start_scsi_mq = NULL, 2395 .abort_isp = qla82xx_abort_isp, 2396 .iospace_config = qla82xx_iospace_config, 2397 .initialize_adapter = qla2x00_initialize_adapter, 2398 }; 2399 2400 static struct isp_operations qla8044_isp_ops = { 2401 .pci_config = qla82xx_pci_config, 2402 .reset_chip = qla82xx_reset_chip, 2403 .chip_diag = qla24xx_chip_diag, 2404 .config_rings = qla82xx_config_rings, 2405 .reset_adapter = qla24xx_reset_adapter, 2406 .nvram_config = qla81xx_nvram_config, 2407 .update_fw_options = qla24xx_update_fw_options, 2408 .load_risc = qla82xx_load_risc, 2409 .pci_info_str = qla24xx_pci_info_str, 2410 .fw_version_str = qla24xx_fw_version_str, 2411 .intr_handler = qla8044_intr_handler, 2412 .enable_intrs = qla82xx_enable_intrs, 2413 .disable_intrs = qla82xx_disable_intrs, 2414 .abort_command = qla24xx_abort_command, 2415 .target_reset = qla24xx_abort_target, 2416 .lun_reset = qla24xx_lun_reset, 2417 .fabric_login = qla24xx_login_fabric, 2418 .fabric_logout = qla24xx_fabric_logout, 2419 .calc_req_entries = NULL, 2420 .build_iocbs = NULL, 2421 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2422 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2423 .read_nvram = NULL, 2424 .write_nvram = NULL, 2425 .fw_dump = qla8044_fw_dump, 2426 .beacon_on = qla82xx_beacon_on, 2427 .beacon_off = qla82xx_beacon_off, 2428 .beacon_blink = NULL, 2429 .read_optrom = qla8044_read_optrom_data, 2430 .write_optrom = qla8044_write_optrom_data, 2431 .get_flash_version = qla82xx_get_flash_version, 2432 .start_scsi = qla82xx_start_scsi, 2433 .start_scsi_mq = NULL, 2434 .abort_isp = qla8044_abort_isp, 2435 .iospace_config = qla82xx_iospace_config, 2436 .initialize_adapter = qla2x00_initialize_adapter, 2437 }; 2438 2439 static struct isp_operations qla83xx_isp_ops = { 2440 .pci_config = qla25xx_pci_config, 2441 .reset_chip = qla24xx_reset_chip, 2442 .chip_diag = qla24xx_chip_diag, 2443 .config_rings = qla24xx_config_rings, 2444 .reset_adapter = qla24xx_reset_adapter, 2445 .nvram_config = qla81xx_nvram_config, 2446 .update_fw_options = qla24xx_update_fw_options, 2447 .load_risc = qla81xx_load_risc, 2448 .pci_info_str = qla24xx_pci_info_str, 2449 .fw_version_str = qla24xx_fw_version_str, 2450 .intr_handler = qla24xx_intr_handler, 2451 .enable_intrs = qla24xx_enable_intrs, 2452 .disable_intrs = qla24xx_disable_intrs, 2453 .abort_command = qla24xx_abort_command, 2454 .target_reset = qla24xx_abort_target, 2455 .lun_reset = qla24xx_lun_reset, 2456 .fabric_login = qla24xx_login_fabric, 2457 .fabric_logout = qla24xx_fabric_logout, 2458 .calc_req_entries = NULL, 2459 .build_iocbs = NULL, 2460 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2461 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2462 .read_nvram = NULL, 2463 .write_nvram = NULL, 2464 .fw_dump = qla83xx_fw_dump, 2465 .beacon_on = qla24xx_beacon_on, 2466 .beacon_off = qla24xx_beacon_off, 2467 .beacon_blink = qla83xx_beacon_blink, 2468 .read_optrom = qla25xx_read_optrom_data, 2469 .write_optrom = qla24xx_write_optrom_data, 2470 .get_flash_version = qla24xx_get_flash_version, 2471 .start_scsi = qla24xx_dif_start_scsi, 2472 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2473 .abort_isp = qla2x00_abort_isp, 2474 .iospace_config = qla83xx_iospace_config, 2475 .initialize_adapter = qla2x00_initialize_adapter, 2476 }; 2477 2478 static struct isp_operations qlafx00_isp_ops = { 2479 .pci_config = qlafx00_pci_config, 2480 .reset_chip = qlafx00_soft_reset, 2481 .chip_diag = qlafx00_chip_diag, 2482 .config_rings = qlafx00_config_rings, 2483 .reset_adapter = qlafx00_soft_reset, 2484 .nvram_config = NULL, 2485 .update_fw_options = NULL, 2486 .load_risc = NULL, 2487 .pci_info_str = qlafx00_pci_info_str, 2488 .fw_version_str = qlafx00_fw_version_str, 2489 .intr_handler = qlafx00_intr_handler, 2490 .enable_intrs = qlafx00_enable_intrs, 2491 .disable_intrs = qlafx00_disable_intrs, 2492 .abort_command = qla24xx_async_abort_command, 2493 .target_reset = qlafx00_abort_target, 2494 .lun_reset = qlafx00_lun_reset, 2495 .fabric_login = NULL, 2496 .fabric_logout = NULL, 2497 .calc_req_entries = NULL, 2498 .build_iocbs = NULL, 2499 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2500 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2501 .read_nvram = qla24xx_read_nvram_data, 2502 .write_nvram = qla24xx_write_nvram_data, 2503 .fw_dump = NULL, 2504 .beacon_on = qla24xx_beacon_on, 2505 .beacon_off = qla24xx_beacon_off, 2506 .beacon_blink = NULL, 2507 .read_optrom = qla24xx_read_optrom_data, 2508 .write_optrom = qla24xx_write_optrom_data, 2509 .get_flash_version = qla24xx_get_flash_version, 2510 .start_scsi = qlafx00_start_scsi, 2511 .start_scsi_mq = NULL, 2512 .abort_isp = qlafx00_abort_isp, 2513 .iospace_config = qlafx00_iospace_config, 2514 .initialize_adapter = qlafx00_initialize_adapter, 2515 }; 2516 2517 static struct isp_operations qla27xx_isp_ops = { 2518 .pci_config = qla25xx_pci_config, 2519 .reset_chip = qla24xx_reset_chip, 2520 .chip_diag = qla24xx_chip_diag, 2521 .config_rings = qla24xx_config_rings, 2522 .reset_adapter = qla24xx_reset_adapter, 2523 .nvram_config = qla81xx_nvram_config, 2524 .update_fw_options = qla24xx_update_fw_options, 2525 .load_risc = qla81xx_load_risc, 2526 .pci_info_str = qla24xx_pci_info_str, 2527 .fw_version_str = qla24xx_fw_version_str, 2528 .intr_handler = qla24xx_intr_handler, 2529 .enable_intrs = qla24xx_enable_intrs, 2530 .disable_intrs = qla24xx_disable_intrs, 2531 .abort_command = qla24xx_abort_command, 2532 .target_reset = qla24xx_abort_target, 2533 .lun_reset = qla24xx_lun_reset, 2534 .fabric_login = qla24xx_login_fabric, 2535 .fabric_logout = qla24xx_fabric_logout, 2536 .calc_req_entries = NULL, 2537 .build_iocbs = NULL, 2538 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2539 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2540 .read_nvram = NULL, 2541 .write_nvram = NULL, 2542 .fw_dump = qla27xx_fwdump, 2543 .mpi_fw_dump = qla27xx_mpi_fwdump, 2544 .beacon_on = qla24xx_beacon_on, 2545 .beacon_off = qla24xx_beacon_off, 2546 .beacon_blink = qla83xx_beacon_blink, 2547 .read_optrom = qla25xx_read_optrom_data, 2548 .write_optrom = qla24xx_write_optrom_data, 2549 .get_flash_version = qla24xx_get_flash_version, 2550 .start_scsi = qla24xx_dif_start_scsi, 2551 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2552 .abort_isp = qla2x00_abort_isp, 2553 .iospace_config = qla83xx_iospace_config, 2554 .initialize_adapter = qla2x00_initialize_adapter, 2555 }; 2556 2557 static inline void 2558 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2559 { 2560 ha->device_type = DT_EXTENDED_IDS; 2561 switch (ha->pdev->device) { 2562 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2563 ha->isp_type |= DT_ISP2100; 2564 ha->device_type &= ~DT_EXTENDED_IDS; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2568 ha->isp_type |= DT_ISP2200; 2569 ha->device_type &= ~DT_EXTENDED_IDS; 2570 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2571 break; 2572 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2573 ha->isp_type |= DT_ISP2300; 2574 ha->device_type |= DT_ZIO_SUPPORTED; 2575 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2576 break; 2577 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2578 ha->isp_type |= DT_ISP2312; 2579 ha->device_type |= DT_ZIO_SUPPORTED; 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2581 break; 2582 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2583 ha->isp_type |= DT_ISP2322; 2584 ha->device_type |= DT_ZIO_SUPPORTED; 2585 if (ha->pdev->subsystem_vendor == 0x1028 && 2586 ha->pdev->subsystem_device == 0x0170) 2587 ha->device_type |= DT_OEM_001; 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2591 ha->isp_type |= DT_ISP6312; 2592 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2593 break; 2594 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2595 ha->isp_type |= DT_ISP6322; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2599 ha->isp_type |= DT_ISP2422; 2600 ha->device_type |= DT_ZIO_SUPPORTED; 2601 ha->device_type |= DT_FWI2; 2602 ha->device_type |= DT_IIDMA; 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2604 break; 2605 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2606 ha->isp_type |= DT_ISP2432; 2607 ha->device_type |= DT_ZIO_SUPPORTED; 2608 ha->device_type |= DT_FWI2; 2609 ha->device_type |= DT_IIDMA; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2611 break; 2612 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2613 ha->isp_type |= DT_ISP8432; 2614 ha->device_type |= DT_ZIO_SUPPORTED; 2615 ha->device_type |= DT_FWI2; 2616 ha->device_type |= DT_IIDMA; 2617 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2618 break; 2619 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2620 ha->isp_type |= DT_ISP5422; 2621 ha->device_type |= DT_FWI2; 2622 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2623 break; 2624 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2625 ha->isp_type |= DT_ISP5432; 2626 ha->device_type |= DT_FWI2; 2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2628 break; 2629 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2630 ha->isp_type |= DT_ISP2532; 2631 ha->device_type |= DT_ZIO_SUPPORTED; 2632 ha->device_type |= DT_FWI2; 2633 ha->device_type |= DT_IIDMA; 2634 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2635 break; 2636 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2637 ha->isp_type |= DT_ISP8001; 2638 ha->device_type |= DT_ZIO_SUPPORTED; 2639 ha->device_type |= DT_FWI2; 2640 ha->device_type |= DT_IIDMA; 2641 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2642 break; 2643 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2644 ha->isp_type |= DT_ISP8021; 2645 ha->device_type |= DT_ZIO_SUPPORTED; 2646 ha->device_type |= DT_FWI2; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2648 /* Initialize 82XX ISP flags */ 2649 qla82xx_init_flags(ha); 2650 break; 2651 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2652 ha->isp_type |= DT_ISP8044; 2653 ha->device_type |= DT_ZIO_SUPPORTED; 2654 ha->device_type |= DT_FWI2; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 /* Initialize 82XX ISP flags */ 2657 qla82xx_init_flags(ha); 2658 break; 2659 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2660 ha->isp_type |= DT_ISP2031; 2661 ha->device_type |= DT_ZIO_SUPPORTED; 2662 ha->device_type |= DT_FWI2; 2663 ha->device_type |= DT_IIDMA; 2664 ha->device_type |= DT_T10_PI; 2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2666 break; 2667 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2668 ha->isp_type |= DT_ISP8031; 2669 ha->device_type |= DT_ZIO_SUPPORTED; 2670 ha->device_type |= DT_FWI2; 2671 ha->device_type |= DT_IIDMA; 2672 ha->device_type |= DT_T10_PI; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2674 break; 2675 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2676 ha->isp_type |= DT_ISPFX00; 2677 break; 2678 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2679 ha->isp_type |= DT_ISP2071; 2680 ha->device_type |= DT_ZIO_SUPPORTED; 2681 ha->device_type |= DT_FWI2; 2682 ha->device_type |= DT_IIDMA; 2683 ha->device_type |= DT_T10_PI; 2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2685 break; 2686 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2687 ha->isp_type |= DT_ISP2271; 2688 ha->device_type |= DT_ZIO_SUPPORTED; 2689 ha->device_type |= DT_FWI2; 2690 ha->device_type |= DT_IIDMA; 2691 ha->device_type |= DT_T10_PI; 2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2693 break; 2694 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2695 ha->isp_type |= DT_ISP2261; 2696 ha->device_type |= DT_ZIO_SUPPORTED; 2697 ha->device_type |= DT_FWI2; 2698 ha->device_type |= DT_IIDMA; 2699 ha->device_type |= DT_T10_PI; 2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2701 break; 2702 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2703 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2704 ha->isp_type |= DT_ISP2081; 2705 ha->device_type |= DT_ZIO_SUPPORTED; 2706 ha->device_type |= DT_FWI2; 2707 ha->device_type |= DT_IIDMA; 2708 ha->device_type |= DT_T10_PI; 2709 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2710 break; 2711 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2712 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2713 ha->isp_type |= DT_ISP2281; 2714 ha->device_type |= DT_ZIO_SUPPORTED; 2715 ha->device_type |= DT_FWI2; 2716 ha->device_type |= DT_IIDMA; 2717 ha->device_type |= DT_T10_PI; 2718 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2719 break; 2720 } 2721 2722 if (IS_QLA82XX(ha)) 2723 ha->port_no = ha->portnum & 1; 2724 else { 2725 /* Get adapter physical port no from interrupt pin register. */ 2726 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2727 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2728 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2729 ha->port_no--; 2730 else 2731 ha->port_no = !(ha->port_no & 1); 2732 } 2733 2734 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2735 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2736 ha->device_type, ha->port_no, ha->fw_srisc_address); 2737 } 2738 2739 static void 2740 qla2xxx_scan_start(struct Scsi_Host *shost) 2741 { 2742 scsi_qla_host_t *vha = shost_priv(shost); 2743 2744 if (vha->hw->flags.running_gold_fw) 2745 return; 2746 2747 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2748 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2749 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2750 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2751 } 2752 2753 static int 2754 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2755 { 2756 scsi_qla_host_t *vha = shost_priv(shost); 2757 2758 if (test_bit(UNLOADING, &vha->dpc_flags)) 2759 return 1; 2760 if (!vha->host) 2761 return 1; 2762 if (time > vha->hw->loop_reset_delay * HZ) 2763 return 1; 2764 2765 return atomic_read(&vha->loop_state) == LOOP_READY; 2766 } 2767 2768 static void qla2x00_iocb_work_fn(struct work_struct *work) 2769 { 2770 struct scsi_qla_host *vha = container_of(work, 2771 struct scsi_qla_host, iocb_work); 2772 struct qla_hw_data *ha = vha->hw; 2773 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2774 int i = 2; 2775 unsigned long flags; 2776 2777 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2778 return; 2779 2780 while (!list_empty(&vha->work_list) && i > 0) { 2781 qla2x00_do_work(vha); 2782 i--; 2783 } 2784 2785 spin_lock_irqsave(&vha->work_lock, flags); 2786 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2787 spin_unlock_irqrestore(&vha->work_lock, flags); 2788 } 2789 2790 /* 2791 * PCI driver interface 2792 */ 2793 static int 2794 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2795 { 2796 int ret = -ENODEV; 2797 struct Scsi_Host *host; 2798 scsi_qla_host_t *base_vha = NULL; 2799 struct qla_hw_data *ha; 2800 char pci_info[30]; 2801 char fw_str[30], wq_name[30]; 2802 struct scsi_host_template *sht; 2803 int bars, mem_only = 0; 2804 uint16_t req_length = 0, rsp_length = 0; 2805 struct req_que *req = NULL; 2806 struct rsp_que *rsp = NULL; 2807 int i; 2808 2809 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2810 sht = &qla2xxx_driver_template; 2811 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2817 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2818 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2819 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2820 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2821 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2822 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2823 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2824 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2825 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2826 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2827 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2828 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2829 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2830 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2831 mem_only = 1; 2832 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2833 "Mem only adapter.\n"); 2834 } 2835 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2836 "Bars=%d.\n", bars); 2837 2838 if (mem_only) { 2839 if (pci_enable_device_mem(pdev)) 2840 return ret; 2841 } else { 2842 if (pci_enable_device(pdev)) 2843 return ret; 2844 } 2845 2846 /* This may fail but that's ok */ 2847 pci_enable_pcie_error_reporting(pdev); 2848 2849 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2850 if (!ha) { 2851 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2852 "Unable to allocate memory for ha.\n"); 2853 goto disable_device; 2854 } 2855 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2856 "Memory allocated for ha=%p.\n", ha); 2857 ha->pdev = pdev; 2858 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2859 spin_lock_init(&ha->tgt.q_full_lock); 2860 spin_lock_init(&ha->tgt.sess_lock); 2861 spin_lock_init(&ha->tgt.atio_lock); 2862 2863 atomic_set(&ha->nvme_active_aen_cnt, 0); 2864 2865 /* Clear our data area */ 2866 ha->bars = bars; 2867 ha->mem_only = mem_only; 2868 spin_lock_init(&ha->hardware_lock); 2869 spin_lock_init(&ha->vport_slock); 2870 mutex_init(&ha->selflogin_lock); 2871 mutex_init(&ha->optrom_mutex); 2872 2873 /* Set ISP-type information. */ 2874 qla2x00_set_isp_flags(ha); 2875 2876 /* Set EEH reset type to fundamental if required by hba */ 2877 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2878 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2879 pdev->needs_freset = 1; 2880 2881 ha->prev_topology = 0; 2882 ha->init_cb_size = sizeof(init_cb_t); 2883 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2884 ha->optrom_size = OPTROM_SIZE_2300; 2885 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2886 atomic_set(&ha->num_pend_mbx_stage1, 0); 2887 atomic_set(&ha->num_pend_mbx_stage2, 0); 2888 atomic_set(&ha->num_pend_mbx_stage3, 0); 2889 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2890 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2891 2892 /* Assign ISP specific operations. */ 2893 if (IS_QLA2100(ha)) { 2894 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2895 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2896 req_length = REQUEST_ENTRY_CNT_2100; 2897 rsp_length = RESPONSE_ENTRY_CNT_2100; 2898 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2899 ha->gid_list_info_size = 4; 2900 ha->flash_conf_off = ~0; 2901 ha->flash_data_off = ~0; 2902 ha->nvram_conf_off = ~0; 2903 ha->nvram_data_off = ~0; 2904 ha->isp_ops = &qla2100_isp_ops; 2905 } else if (IS_QLA2200(ha)) { 2906 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2907 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2908 req_length = REQUEST_ENTRY_CNT_2200; 2909 rsp_length = RESPONSE_ENTRY_CNT_2100; 2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2911 ha->gid_list_info_size = 4; 2912 ha->flash_conf_off = ~0; 2913 ha->flash_data_off = ~0; 2914 ha->nvram_conf_off = ~0; 2915 ha->nvram_data_off = ~0; 2916 ha->isp_ops = &qla2100_isp_ops; 2917 } else if (IS_QLA23XX(ha)) { 2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2919 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2920 req_length = REQUEST_ENTRY_CNT_2200; 2921 rsp_length = RESPONSE_ENTRY_CNT_2300; 2922 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2923 ha->gid_list_info_size = 6; 2924 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2925 ha->optrom_size = OPTROM_SIZE_2322; 2926 ha->flash_conf_off = ~0; 2927 ha->flash_data_off = ~0; 2928 ha->nvram_conf_off = ~0; 2929 ha->nvram_data_off = ~0; 2930 ha->isp_ops = &qla2300_isp_ops; 2931 } else if (IS_QLA24XX_TYPE(ha)) { 2932 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2933 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2934 req_length = REQUEST_ENTRY_CNT_24XX; 2935 rsp_length = RESPONSE_ENTRY_CNT_2300; 2936 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2937 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2938 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2939 ha->gid_list_info_size = 8; 2940 ha->optrom_size = OPTROM_SIZE_24XX; 2941 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2942 ha->isp_ops = &qla24xx_isp_ops; 2943 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2944 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2945 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2946 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2947 } else if (IS_QLA25XX(ha)) { 2948 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2949 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2950 req_length = REQUEST_ENTRY_CNT_24XX; 2951 rsp_length = RESPONSE_ENTRY_CNT_2300; 2952 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2953 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2954 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2955 ha->gid_list_info_size = 8; 2956 ha->optrom_size = OPTROM_SIZE_25XX; 2957 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2958 ha->isp_ops = &qla25xx_isp_ops; 2959 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2960 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2961 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2962 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2963 } else if (IS_QLA81XX(ha)) { 2964 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2965 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2966 req_length = REQUEST_ENTRY_CNT_24XX; 2967 rsp_length = RESPONSE_ENTRY_CNT_2300; 2968 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2969 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2970 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2971 ha->gid_list_info_size = 8; 2972 ha->optrom_size = OPTROM_SIZE_81XX; 2973 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2974 ha->isp_ops = &qla81xx_isp_ops; 2975 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2976 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2977 ha->nvram_conf_off = ~0; 2978 ha->nvram_data_off = ~0; 2979 } else if (IS_QLA82XX(ha)) { 2980 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2981 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2982 req_length = REQUEST_ENTRY_CNT_82XX; 2983 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2984 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2985 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2986 ha->gid_list_info_size = 8; 2987 ha->optrom_size = OPTROM_SIZE_82XX; 2988 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2989 ha->isp_ops = &qla82xx_isp_ops; 2990 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2991 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2992 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2993 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2994 } else if (IS_QLA8044(ha)) { 2995 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2996 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2997 req_length = REQUEST_ENTRY_CNT_82XX; 2998 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2999 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3000 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3001 ha->gid_list_info_size = 8; 3002 ha->optrom_size = OPTROM_SIZE_83XX; 3003 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3004 ha->isp_ops = &qla8044_isp_ops; 3005 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3006 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3007 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3008 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3009 } else if (IS_QLA83XX(ha)) { 3010 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3011 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3012 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3013 req_length = REQUEST_ENTRY_CNT_83XX; 3014 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3015 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3016 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3017 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3018 ha->gid_list_info_size = 8; 3019 ha->optrom_size = OPTROM_SIZE_83XX; 3020 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3021 ha->isp_ops = &qla83xx_isp_ops; 3022 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3023 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3024 ha->nvram_conf_off = ~0; 3025 ha->nvram_data_off = ~0; 3026 } else if (IS_QLAFX00(ha)) { 3027 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3028 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3029 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3030 req_length = REQUEST_ENTRY_CNT_FX00; 3031 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3032 ha->isp_ops = &qlafx00_isp_ops; 3033 ha->port_down_retry_count = 30; /* default value */ 3034 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3035 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3036 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3037 ha->mr.fw_hbt_en = 1; 3038 ha->mr.host_info_resend = false; 3039 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3040 } else if (IS_QLA27XX(ha)) { 3041 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3043 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3044 req_length = REQUEST_ENTRY_CNT_83XX; 3045 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3046 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3047 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3048 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3049 ha->gid_list_info_size = 8; 3050 ha->optrom_size = OPTROM_SIZE_83XX; 3051 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3052 ha->isp_ops = &qla27xx_isp_ops; 3053 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3054 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3055 ha->nvram_conf_off = ~0; 3056 ha->nvram_data_off = ~0; 3057 } else if (IS_QLA28XX(ha)) { 3058 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3059 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3060 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3061 req_length = REQUEST_ENTRY_CNT_24XX; 3062 rsp_length = RESPONSE_ENTRY_CNT_2300; 3063 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3064 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3065 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3066 ha->gid_list_info_size = 8; 3067 ha->optrom_size = OPTROM_SIZE_28XX; 3068 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3069 ha->isp_ops = &qla27xx_isp_ops; 3070 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3071 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3072 ha->nvram_conf_off = ~0; 3073 ha->nvram_data_off = ~0; 3074 } 3075 3076 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3077 "mbx_count=%d, req_length=%d, " 3078 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3079 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3080 "max_fibre_devices=%d.\n", 3081 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3082 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3083 ha->nvram_npiv_size, ha->max_fibre_devices); 3084 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3085 "isp_ops=%p, flash_conf_off=%d, " 3086 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3087 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3088 ha->nvram_conf_off, ha->nvram_data_off); 3089 3090 /* Configure PCI I/O space */ 3091 ret = ha->isp_ops->iospace_config(ha); 3092 if (ret) 3093 goto iospace_config_failed; 3094 3095 ql_log_pci(ql_log_info, pdev, 0x001d, 3096 "Found an ISP%04X irq %d iobase 0x%p.\n", 3097 pdev->device, pdev->irq, ha->iobase); 3098 mutex_init(&ha->vport_lock); 3099 mutex_init(&ha->mq_lock); 3100 init_completion(&ha->mbx_cmd_comp); 3101 complete(&ha->mbx_cmd_comp); 3102 init_completion(&ha->mbx_intr_comp); 3103 init_completion(&ha->dcbx_comp); 3104 init_completion(&ha->lb_portup_comp); 3105 3106 set_bit(0, (unsigned long *) ha->vp_idx_map); 3107 3108 qla2x00_config_dma_addressing(ha); 3109 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3110 "64 Bit addressing is %s.\n", 3111 ha->flags.enable_64bit_addressing ? "enable" : 3112 "disable"); 3113 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3114 if (ret) { 3115 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3116 "Failed to allocate memory for adapter, aborting.\n"); 3117 3118 goto probe_hw_failed; 3119 } 3120 3121 req->max_q_depth = MAX_Q_DEPTH; 3122 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3123 req->max_q_depth = ql2xmaxqdepth; 3124 3125 3126 base_vha = qla2x00_create_host(sht, ha); 3127 if (!base_vha) { 3128 ret = -ENOMEM; 3129 goto probe_hw_failed; 3130 } 3131 3132 pci_set_drvdata(pdev, base_vha); 3133 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3134 3135 host = base_vha->host; 3136 base_vha->req = req; 3137 if (IS_QLA2XXX_MIDTYPE(ha)) 3138 base_vha->mgmt_svr_loop_id = 3139 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3140 else 3141 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3142 base_vha->vp_idx; 3143 3144 /* Setup fcport template structure. */ 3145 ha->mr.fcport.vha = base_vha; 3146 ha->mr.fcport.port_type = FCT_UNKNOWN; 3147 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3148 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3149 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3150 ha->mr.fcport.scan_state = 1; 3151 3152 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3153 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3154 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3155 3156 /* Set the SG table size based on ISP type */ 3157 if (!IS_FWI2_CAPABLE(ha)) { 3158 if (IS_QLA2100(ha)) 3159 host->sg_tablesize = 32; 3160 } else { 3161 if (!IS_QLA82XX(ha)) 3162 host->sg_tablesize = QLA_SG_ALL; 3163 } 3164 host->max_id = ha->max_fibre_devices; 3165 host->cmd_per_lun = 3; 3166 host->unique_id = host->host_no; 3167 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3168 host->max_cmd_len = 32; 3169 else 3170 host->max_cmd_len = MAX_CMDSZ; 3171 host->max_channel = MAX_BUSES - 1; 3172 /* Older HBAs support only 16-bit LUNs */ 3173 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3174 ql2xmaxlun > 0xffff) 3175 host->max_lun = 0xffff; 3176 else 3177 host->max_lun = ql2xmaxlun; 3178 host->transportt = qla2xxx_transport_template; 3179 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3180 3181 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3182 "max_id=%d this_id=%d " 3183 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3184 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3185 host->this_id, host->cmd_per_lun, host->unique_id, 3186 host->max_cmd_len, host->max_channel, host->max_lun, 3187 host->transportt, sht->vendor_id); 3188 3189 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3190 3191 /* Set up the irqs */ 3192 ret = qla2x00_request_irqs(ha, rsp); 3193 if (ret) 3194 goto probe_failed; 3195 3196 /* Alloc arrays of request and response ring ptrs */ 3197 ret = qla2x00_alloc_queues(ha, req, rsp); 3198 if (ret) { 3199 ql_log(ql_log_fatal, base_vha, 0x003d, 3200 "Failed to allocate memory for queue pointers..." 3201 "aborting.\n"); 3202 ret = -ENODEV; 3203 goto probe_failed; 3204 } 3205 3206 if (ha->mqenable) { 3207 /* number of hardware queues supported by blk/scsi-mq*/ 3208 host->nr_hw_queues = ha->max_qpairs; 3209 3210 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3211 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3212 } else { 3213 if (ql2xnvmeenable) { 3214 host->nr_hw_queues = ha->max_qpairs; 3215 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3216 "FC-NVMe support is enabled, HW queues=%d\n", 3217 host->nr_hw_queues); 3218 } else { 3219 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3220 "blk/scsi-mq disabled.\n"); 3221 } 3222 } 3223 3224 qlt_probe_one_stage1(base_vha, ha); 3225 3226 pci_save_state(pdev); 3227 3228 /* Assign back pointers */ 3229 rsp->req = req; 3230 req->rsp = rsp; 3231 3232 if (IS_QLAFX00(ha)) { 3233 ha->rsp_q_map[0] = rsp; 3234 ha->req_q_map[0] = req; 3235 set_bit(0, ha->req_qid_map); 3236 set_bit(0, ha->rsp_qid_map); 3237 } 3238 3239 /* FWI2-capable only. */ 3240 req->req_q_in = &ha->iobase->isp24.req_q_in; 3241 req->req_q_out = &ha->iobase->isp24.req_q_out; 3242 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3243 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3244 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3245 IS_QLA28XX(ha)) { 3246 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3247 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3248 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3249 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3250 } 3251 3252 if (IS_QLAFX00(ha)) { 3253 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3254 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3255 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3256 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3257 } 3258 3259 if (IS_P3P_TYPE(ha)) { 3260 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3261 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3262 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3263 } 3264 3265 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3266 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3267 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3268 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3269 "req->req_q_in=%p req->req_q_out=%p " 3270 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3271 req->req_q_in, req->req_q_out, 3272 rsp->rsp_q_in, rsp->rsp_q_out); 3273 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3274 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3275 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3276 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3277 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3278 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3279 3280 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3281 if (unlikely(!ha->wq)) { 3282 ret = -ENOMEM; 3283 goto probe_failed; 3284 } 3285 3286 if (ha->isp_ops->initialize_adapter(base_vha)) { 3287 ql_log(ql_log_fatal, base_vha, 0x00d6, 3288 "Failed to initialize adapter - Adapter flags %x.\n", 3289 base_vha->device_flags); 3290 3291 if (IS_QLA82XX(ha)) { 3292 qla82xx_idc_lock(ha); 3293 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3294 QLA8XXX_DEV_FAILED); 3295 qla82xx_idc_unlock(ha); 3296 ql_log(ql_log_fatal, base_vha, 0x00d7, 3297 "HW State: FAILED.\n"); 3298 } else if (IS_QLA8044(ha)) { 3299 qla8044_idc_lock(ha); 3300 qla8044_wr_direct(base_vha, 3301 QLA8044_CRB_DEV_STATE_INDEX, 3302 QLA8XXX_DEV_FAILED); 3303 qla8044_idc_unlock(ha); 3304 ql_log(ql_log_fatal, base_vha, 0x0150, 3305 "HW State: FAILED.\n"); 3306 } 3307 3308 ret = -ENODEV; 3309 goto probe_failed; 3310 } 3311 3312 if (IS_QLAFX00(ha)) 3313 host->can_queue = QLAFX00_MAX_CANQUEUE; 3314 else 3315 host->can_queue = req->num_outstanding_cmds - 10; 3316 3317 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3318 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3319 host->can_queue, base_vha->req, 3320 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3321 3322 if (ha->mqenable) { 3323 bool startit = false; 3324 3325 if (QLA_TGT_MODE_ENABLED()) 3326 startit = false; 3327 3328 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3329 startit = true; 3330 3331 /* Create start of day qpairs for Block MQ */ 3332 for (i = 0; i < ha->max_qpairs; i++) 3333 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3334 } 3335 qla_init_iocb_limit(base_vha); 3336 3337 if (ha->flags.running_gold_fw) 3338 goto skip_dpc; 3339 3340 /* 3341 * Startup the kernel thread for this host adapter 3342 */ 3343 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3344 "%s_dpc", base_vha->host_str); 3345 if (IS_ERR(ha->dpc_thread)) { 3346 ql_log(ql_log_fatal, base_vha, 0x00ed, 3347 "Failed to start DPC thread.\n"); 3348 ret = PTR_ERR(ha->dpc_thread); 3349 ha->dpc_thread = NULL; 3350 goto probe_failed; 3351 } 3352 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3353 "DPC thread started successfully.\n"); 3354 3355 /* 3356 * If we're not coming up in initiator mode, we might sit for 3357 * a while without waking up the dpc thread, which leads to a 3358 * stuck process warning. So just kick the dpc once here and 3359 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3360 */ 3361 qla2xxx_wake_dpc(base_vha); 3362 3363 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3364 3365 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3366 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3367 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3368 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3369 3370 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3371 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3372 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3373 INIT_WORK(&ha->idc_state_handler, 3374 qla83xx_idc_state_handler_work); 3375 INIT_WORK(&ha->nic_core_unrecoverable, 3376 qla83xx_nic_core_unrecoverable_work); 3377 } 3378 3379 skip_dpc: 3380 list_add_tail(&base_vha->list, &ha->vp_list); 3381 base_vha->host->irq = ha->pdev->irq; 3382 3383 /* Initialized the timer */ 3384 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3385 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3386 "Started qla2x00_timer with " 3387 "interval=%d.\n", WATCH_INTERVAL); 3388 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3389 "Detected hba at address=%p.\n", 3390 ha); 3391 3392 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3393 if (ha->fw_attributes & BIT_4) { 3394 int prot = 0, guard; 3395 3396 base_vha->flags.difdix_supported = 1; 3397 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3398 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3399 if (ql2xenabledif == 1) 3400 prot = SHOST_DIX_TYPE0_PROTECTION; 3401 if (ql2xprotmask) 3402 scsi_host_set_prot(host, ql2xprotmask); 3403 else 3404 scsi_host_set_prot(host, 3405 prot | SHOST_DIF_TYPE1_PROTECTION 3406 | SHOST_DIF_TYPE2_PROTECTION 3407 | SHOST_DIF_TYPE3_PROTECTION 3408 | SHOST_DIX_TYPE1_PROTECTION 3409 | SHOST_DIX_TYPE2_PROTECTION 3410 | SHOST_DIX_TYPE3_PROTECTION); 3411 3412 guard = SHOST_DIX_GUARD_CRC; 3413 3414 if (IS_PI_IPGUARD_CAPABLE(ha) && 3415 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3416 guard |= SHOST_DIX_GUARD_IP; 3417 3418 if (ql2xprotguard) 3419 scsi_host_set_guard(host, ql2xprotguard); 3420 else 3421 scsi_host_set_guard(host, guard); 3422 } else 3423 base_vha->flags.difdix_supported = 0; 3424 } 3425 3426 ha->isp_ops->enable_intrs(ha); 3427 3428 if (IS_QLAFX00(ha)) { 3429 ret = qlafx00_fx_disc(base_vha, 3430 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3431 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3432 QLA_SG_ALL : 128; 3433 } 3434 3435 ret = scsi_add_host(host, &pdev->dev); 3436 if (ret) 3437 goto probe_failed; 3438 3439 base_vha->flags.init_done = 1; 3440 base_vha->flags.online = 1; 3441 ha->prev_minidump_failed = 0; 3442 3443 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3444 "Init done and hba is online.\n"); 3445 3446 if (qla_ini_mode_enabled(base_vha) || 3447 qla_dual_mode_enabled(base_vha)) 3448 scsi_scan_host(host); 3449 else 3450 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3451 "skipping scsi_scan_host() for non-initiator port\n"); 3452 3453 qla2x00_alloc_sysfs_attr(base_vha); 3454 3455 if (IS_QLAFX00(ha)) { 3456 ret = qlafx00_fx_disc(base_vha, 3457 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3458 3459 /* Register system information */ 3460 ret = qlafx00_fx_disc(base_vha, 3461 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3462 } 3463 3464 qla2x00_init_host_attr(base_vha); 3465 3466 qla2x00_dfs_setup(base_vha); 3467 3468 ql_log(ql_log_info, base_vha, 0x00fb, 3469 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3470 ql_log(ql_log_info, base_vha, 0x00fc, 3471 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3472 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3473 sizeof(pci_info)), 3474 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3475 base_vha->host_no, 3476 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3477 3478 qlt_add_target(ha, base_vha); 3479 3480 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3481 3482 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3483 return -ENODEV; 3484 3485 return 0; 3486 3487 probe_failed: 3488 if (base_vha->gnl.l) { 3489 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3490 base_vha->gnl.l, base_vha->gnl.ldma); 3491 base_vha->gnl.l = NULL; 3492 } 3493 3494 if (base_vha->timer_active) 3495 qla2x00_stop_timer(base_vha); 3496 base_vha->flags.online = 0; 3497 if (ha->dpc_thread) { 3498 struct task_struct *t = ha->dpc_thread; 3499 3500 ha->dpc_thread = NULL; 3501 kthread_stop(t); 3502 } 3503 3504 qla2x00_free_device(base_vha); 3505 scsi_host_put(base_vha->host); 3506 /* 3507 * Need to NULL out local req/rsp after 3508 * qla2x00_free_device => qla2x00_free_queues frees 3509 * what these are pointing to. Or else we'll 3510 * fall over below in qla2x00_free_req/rsp_que. 3511 */ 3512 req = NULL; 3513 rsp = NULL; 3514 3515 probe_hw_failed: 3516 qla2x00_mem_free(ha); 3517 qla2x00_free_req_que(ha, req); 3518 qla2x00_free_rsp_que(ha, rsp); 3519 qla2x00_clear_drv_active(ha); 3520 3521 iospace_config_failed: 3522 if (IS_P3P_TYPE(ha)) { 3523 if (!ha->nx_pcibase) 3524 iounmap((device_reg_t *)ha->nx_pcibase); 3525 if (!ql2xdbwr) 3526 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3527 } else { 3528 if (ha->iobase) 3529 iounmap(ha->iobase); 3530 if (ha->cregbase) 3531 iounmap(ha->cregbase); 3532 } 3533 pci_release_selected_regions(ha->pdev, ha->bars); 3534 kfree(ha); 3535 3536 disable_device: 3537 pci_disable_device(pdev); 3538 return ret; 3539 } 3540 3541 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3542 { 3543 scsi_qla_host_t *vp; 3544 unsigned long flags; 3545 struct qla_hw_data *ha; 3546 3547 if (!base_vha) 3548 return; 3549 3550 ha = base_vha->hw; 3551 3552 spin_lock_irqsave(&ha->vport_slock, flags); 3553 list_for_each_entry(vp, &ha->vp_list, list) 3554 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3555 3556 /* 3557 * Indicate device removal to prevent future board_disable 3558 * and wait until any pending board_disable has completed. 3559 */ 3560 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3561 spin_unlock_irqrestore(&ha->vport_slock, flags); 3562 } 3563 3564 static void 3565 qla2x00_shutdown(struct pci_dev *pdev) 3566 { 3567 scsi_qla_host_t *vha; 3568 struct qla_hw_data *ha; 3569 3570 vha = pci_get_drvdata(pdev); 3571 ha = vha->hw; 3572 3573 ql_log(ql_log_info, vha, 0xfffa, 3574 "Adapter shutdown\n"); 3575 3576 /* 3577 * Prevent future board_disable and wait 3578 * until any pending board_disable has completed. 3579 */ 3580 __qla_set_remove_flag(vha); 3581 cancel_work_sync(&ha->board_disable); 3582 3583 if (!atomic_read(&pdev->enable_cnt)) 3584 return; 3585 3586 /* Notify ISPFX00 firmware */ 3587 if (IS_QLAFX00(ha)) 3588 qlafx00_driver_shutdown(vha, 20); 3589 3590 /* Turn-off FCE trace */ 3591 if (ha->flags.fce_enabled) { 3592 qla2x00_disable_fce_trace(vha, NULL, NULL); 3593 ha->flags.fce_enabled = 0; 3594 } 3595 3596 /* Turn-off EFT trace */ 3597 if (ha->eft) 3598 qla2x00_disable_eft_trace(vha); 3599 3600 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3601 IS_QLA28XX(ha)) { 3602 if (ha->flags.fw_started) 3603 qla2x00_abort_isp_cleanup(vha); 3604 } else { 3605 /* Stop currently executing firmware. */ 3606 qla2x00_try_to_stop_firmware(vha); 3607 } 3608 3609 /* Disable timer */ 3610 if (vha->timer_active) 3611 qla2x00_stop_timer(vha); 3612 3613 /* Turn adapter off line */ 3614 vha->flags.online = 0; 3615 3616 /* turn-off interrupts on the card */ 3617 if (ha->interrupts_on) { 3618 vha->flags.init_done = 0; 3619 ha->isp_ops->disable_intrs(ha); 3620 } 3621 3622 qla2x00_free_irqs(vha); 3623 3624 qla2x00_free_fw_dump(ha); 3625 3626 pci_disable_device(pdev); 3627 ql_log(ql_log_info, vha, 0xfffe, 3628 "Adapter shutdown successfully.\n"); 3629 } 3630 3631 /* Deletes all the virtual ports for a given ha */ 3632 static void 3633 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3634 { 3635 scsi_qla_host_t *vha; 3636 unsigned long flags; 3637 3638 mutex_lock(&ha->vport_lock); 3639 while (ha->cur_vport_count) { 3640 spin_lock_irqsave(&ha->vport_slock, flags); 3641 3642 BUG_ON(base_vha->list.next == &ha->vp_list); 3643 /* This assumes first entry in ha->vp_list is always base vha */ 3644 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3645 scsi_host_get(vha->host); 3646 3647 spin_unlock_irqrestore(&ha->vport_slock, flags); 3648 mutex_unlock(&ha->vport_lock); 3649 3650 qla_nvme_delete(vha); 3651 3652 fc_vport_terminate(vha->fc_vport); 3653 scsi_host_put(vha->host); 3654 3655 mutex_lock(&ha->vport_lock); 3656 } 3657 mutex_unlock(&ha->vport_lock); 3658 } 3659 3660 /* Stops all deferred work threads */ 3661 static void 3662 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3663 { 3664 /* Cancel all work and destroy DPC workqueues */ 3665 if (ha->dpc_lp_wq) { 3666 cancel_work_sync(&ha->idc_aen); 3667 destroy_workqueue(ha->dpc_lp_wq); 3668 ha->dpc_lp_wq = NULL; 3669 } 3670 3671 if (ha->dpc_hp_wq) { 3672 cancel_work_sync(&ha->nic_core_reset); 3673 cancel_work_sync(&ha->idc_state_handler); 3674 cancel_work_sync(&ha->nic_core_unrecoverable); 3675 destroy_workqueue(ha->dpc_hp_wq); 3676 ha->dpc_hp_wq = NULL; 3677 } 3678 3679 /* Kill the kernel thread for this host */ 3680 if (ha->dpc_thread) { 3681 struct task_struct *t = ha->dpc_thread; 3682 3683 /* 3684 * qla2xxx_wake_dpc checks for ->dpc_thread 3685 * so we need to zero it out. 3686 */ 3687 ha->dpc_thread = NULL; 3688 kthread_stop(t); 3689 } 3690 } 3691 3692 static void 3693 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3694 { 3695 if (IS_QLA82XX(ha)) { 3696 3697 iounmap((device_reg_t *)ha->nx_pcibase); 3698 if (!ql2xdbwr) 3699 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3700 } else { 3701 if (ha->iobase) 3702 iounmap(ha->iobase); 3703 3704 if (ha->cregbase) 3705 iounmap(ha->cregbase); 3706 3707 if (ha->mqiobase) 3708 iounmap(ha->mqiobase); 3709 3710 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3711 ha->msixbase) 3712 iounmap(ha->msixbase); 3713 } 3714 } 3715 3716 static void 3717 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3718 { 3719 if (IS_QLA8044(ha)) { 3720 qla8044_idc_lock(ha); 3721 qla8044_clear_drv_active(ha); 3722 qla8044_idc_unlock(ha); 3723 } else if (IS_QLA82XX(ha)) { 3724 qla82xx_idc_lock(ha); 3725 qla82xx_clear_drv_active(ha); 3726 qla82xx_idc_unlock(ha); 3727 } 3728 } 3729 3730 static void 3731 qla2x00_remove_one(struct pci_dev *pdev) 3732 { 3733 scsi_qla_host_t *base_vha; 3734 struct qla_hw_data *ha; 3735 3736 base_vha = pci_get_drvdata(pdev); 3737 ha = base_vha->hw; 3738 ql_log(ql_log_info, base_vha, 0xb079, 3739 "Removing driver\n"); 3740 __qla_set_remove_flag(base_vha); 3741 cancel_work_sync(&ha->board_disable); 3742 3743 /* 3744 * If the PCI device is disabled then there was a PCI-disconnect and 3745 * qla2x00_disable_board_on_pci_error has taken care of most of the 3746 * resources. 3747 */ 3748 if (!atomic_read(&pdev->enable_cnt)) { 3749 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3750 base_vha->gnl.l, base_vha->gnl.ldma); 3751 base_vha->gnl.l = NULL; 3752 scsi_host_put(base_vha->host); 3753 kfree(ha); 3754 pci_set_drvdata(pdev, NULL); 3755 return; 3756 } 3757 qla2x00_wait_for_hba_ready(base_vha); 3758 3759 /* 3760 * if UNLOADING flag is already set, then continue unload, 3761 * where it was set first. 3762 */ 3763 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3764 return; 3765 3766 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3767 IS_QLA28XX(ha)) { 3768 if (ha->flags.fw_started) 3769 qla2x00_abort_isp_cleanup(base_vha); 3770 } else if (!IS_QLAFX00(ha)) { 3771 if (IS_QLA8031(ha)) { 3772 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3773 "Clearing fcoe driver presence.\n"); 3774 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3775 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3776 "Error while clearing DRV-Presence.\n"); 3777 } 3778 3779 qla2x00_try_to_stop_firmware(base_vha); 3780 } 3781 3782 qla2x00_wait_for_sess_deletion(base_vha); 3783 3784 qla_nvme_delete(base_vha); 3785 3786 dma_free_coherent(&ha->pdev->dev, 3787 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3788 3789 base_vha->gnl.l = NULL; 3790 3791 vfree(base_vha->scan.l); 3792 3793 if (IS_QLAFX00(ha)) 3794 qlafx00_driver_shutdown(base_vha, 20); 3795 3796 qla2x00_delete_all_vps(ha, base_vha); 3797 3798 qla2x00_dfs_remove(base_vha); 3799 3800 qla84xx_put_chip(base_vha); 3801 3802 /* Disable timer */ 3803 if (base_vha->timer_active) 3804 qla2x00_stop_timer(base_vha); 3805 3806 base_vha->flags.online = 0; 3807 3808 /* free DMA memory */ 3809 if (ha->exlogin_buf) 3810 qla2x00_free_exlogin_buffer(ha); 3811 3812 /* free DMA memory */ 3813 if (ha->exchoffld_buf) 3814 qla2x00_free_exchoffld_buffer(ha); 3815 3816 qla2x00_destroy_deferred_work(ha); 3817 3818 qlt_remove_target(ha, base_vha); 3819 3820 qla2x00_free_sysfs_attr(base_vha, true); 3821 3822 fc_remove_host(base_vha->host); 3823 qlt_remove_target_resources(ha); 3824 3825 scsi_remove_host(base_vha->host); 3826 3827 qla2x00_free_device(base_vha); 3828 3829 qla2x00_clear_drv_active(ha); 3830 3831 scsi_host_put(base_vha->host); 3832 3833 qla2x00_unmap_iobases(ha); 3834 3835 pci_release_selected_regions(ha->pdev, ha->bars); 3836 kfree(ha); 3837 3838 pci_disable_pcie_error_reporting(pdev); 3839 3840 pci_disable_device(pdev); 3841 } 3842 3843 static inline void 3844 qla24xx_free_purex_list(struct purex_list *list) 3845 { 3846 struct list_head *item, *next; 3847 ulong flags; 3848 3849 spin_lock_irqsave(&list->lock, flags); 3850 list_for_each_safe(item, next, &list->head) { 3851 list_del(item); 3852 kfree(list_entry(item, struct purex_item, list)); 3853 } 3854 spin_unlock_irqrestore(&list->lock, flags); 3855 } 3856 3857 static void 3858 qla2x00_free_device(scsi_qla_host_t *vha) 3859 { 3860 struct qla_hw_data *ha = vha->hw; 3861 3862 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3863 3864 /* Disable timer */ 3865 if (vha->timer_active) 3866 qla2x00_stop_timer(vha); 3867 3868 qla25xx_delete_queues(vha); 3869 vha->flags.online = 0; 3870 3871 /* turn-off interrupts on the card */ 3872 if (ha->interrupts_on) { 3873 vha->flags.init_done = 0; 3874 ha->isp_ops->disable_intrs(ha); 3875 } 3876 3877 qla2x00_free_fcports(vha); 3878 3879 qla2x00_free_irqs(vha); 3880 3881 /* Flush the work queue and remove it */ 3882 if (ha->wq) { 3883 flush_workqueue(ha->wq); 3884 destroy_workqueue(ha->wq); 3885 ha->wq = NULL; 3886 } 3887 3888 3889 qla24xx_free_purex_list(&vha->purex_list); 3890 3891 qla2x00_mem_free(ha); 3892 3893 qla82xx_md_free(vha); 3894 3895 qla2x00_free_queues(ha); 3896 } 3897 3898 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3899 { 3900 fc_port_t *fcport, *tfcport; 3901 3902 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3903 qla2x00_free_fcport(fcport); 3904 } 3905 3906 static inline void 3907 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3908 { 3909 int now; 3910 3911 if (!fcport->rport) 3912 return; 3913 3914 if (fcport->rport) { 3915 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3916 "%s %8phN. rport %p roles %x\n", 3917 __func__, fcport->port_name, fcport->rport, 3918 fcport->rport->roles); 3919 fc_remote_port_delete(fcport->rport); 3920 } 3921 qlt_do_generation_tick(vha, &now); 3922 } 3923 3924 /* 3925 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3926 * 3927 * Input: ha = adapter block pointer. fcport = port structure pointer. 3928 * 3929 * Return: None. 3930 * 3931 * Context: 3932 */ 3933 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3934 int do_login) 3935 { 3936 if (IS_QLAFX00(vha->hw)) { 3937 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3938 qla2x00_schedule_rport_del(vha, fcport); 3939 return; 3940 } 3941 3942 if (atomic_read(&fcport->state) == FCS_ONLINE && 3943 vha->vp_idx == fcport->vha->vp_idx) { 3944 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3945 qla2x00_schedule_rport_del(vha, fcport); 3946 } 3947 /* 3948 * We may need to retry the login, so don't change the state of the 3949 * port but do the retries. 3950 */ 3951 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3952 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3953 3954 if (!do_login) 3955 return; 3956 3957 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3958 } 3959 3960 void 3961 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 3962 { 3963 fc_port_t *fcport; 3964 3965 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3966 "Mark all dev lost\n"); 3967 3968 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3969 fcport->scan_state = 0; 3970 qlt_schedule_sess_for_deletion(fcport); 3971 } 3972 } 3973 3974 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3975 { 3976 int i; 3977 3978 if (IS_FWI2_CAPABLE(ha)) 3979 return; 3980 3981 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3982 set_bit(i, ha->loop_id_map); 3983 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3984 set_bit(BROADCAST, ha->loop_id_map); 3985 } 3986 3987 /* 3988 * qla2x00_mem_alloc 3989 * Allocates adapter memory. 3990 * 3991 * Returns: 3992 * 0 = success. 3993 * !0 = failure. 3994 */ 3995 static int 3996 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3997 struct req_que **req, struct rsp_que **rsp) 3998 { 3999 char name[16]; 4000 4001 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4002 &ha->init_cb_dma, GFP_KERNEL); 4003 if (!ha->init_cb) 4004 goto fail; 4005 4006 if (qlt_mem_alloc(ha) < 0) 4007 goto fail_free_init_cb; 4008 4009 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4010 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4011 if (!ha->gid_list) 4012 goto fail_free_tgt_mem; 4013 4014 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4015 if (!ha->srb_mempool) 4016 goto fail_free_gid_list; 4017 4018 if (IS_P3P_TYPE(ha)) { 4019 /* Allocate cache for CT6 Ctx. */ 4020 if (!ctx_cachep) { 4021 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4022 sizeof(struct ct6_dsd), 0, 4023 SLAB_HWCACHE_ALIGN, NULL); 4024 if (!ctx_cachep) 4025 goto fail_free_srb_mempool; 4026 } 4027 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4028 ctx_cachep); 4029 if (!ha->ctx_mempool) 4030 goto fail_free_srb_mempool; 4031 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4032 "ctx_cachep=%p ctx_mempool=%p.\n", 4033 ctx_cachep, ha->ctx_mempool); 4034 } 4035 4036 /* Get memory for cached NVRAM */ 4037 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4038 if (!ha->nvram) 4039 goto fail_free_ctx_mempool; 4040 4041 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4042 ha->pdev->device); 4043 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4044 DMA_POOL_SIZE, 8, 0); 4045 if (!ha->s_dma_pool) 4046 goto fail_free_nvram; 4047 4048 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4049 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4050 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4051 4052 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4053 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4054 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4055 if (!ha->dl_dma_pool) { 4056 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4057 "Failed to allocate memory for dl_dma_pool.\n"); 4058 goto fail_s_dma_pool; 4059 } 4060 4061 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4062 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4063 if (!ha->fcp_cmnd_dma_pool) { 4064 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4065 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4066 goto fail_dl_dma_pool; 4067 } 4068 4069 if (ql2xenabledif) { 4070 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4071 struct dsd_dma *dsd, *nxt; 4072 uint i; 4073 /* Creata a DMA pool of buffers for DIF bundling */ 4074 ha->dif_bundl_pool = dma_pool_create(name, 4075 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4076 if (!ha->dif_bundl_pool) { 4077 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4078 "%s: failed create dif_bundl_pool\n", 4079 __func__); 4080 goto fail_dif_bundl_dma_pool; 4081 } 4082 4083 INIT_LIST_HEAD(&ha->pool.good.head); 4084 INIT_LIST_HEAD(&ha->pool.unusable.head); 4085 ha->pool.good.count = 0; 4086 ha->pool.unusable.count = 0; 4087 for (i = 0; i < 128; i++) { 4088 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4089 if (!dsd) { 4090 ql_dbg_pci(ql_dbg_init, ha->pdev, 4091 0xe0ee, "%s: failed alloc dsd\n", 4092 __func__); 4093 return 1; 4094 } 4095 ha->dif_bundle_kallocs++; 4096 4097 dsd->dsd_addr = dma_pool_alloc( 4098 ha->dif_bundl_pool, GFP_ATOMIC, 4099 &dsd->dsd_list_dma); 4100 if (!dsd->dsd_addr) { 4101 ql_dbg_pci(ql_dbg_init, ha->pdev, 4102 0xe0ee, 4103 "%s: failed alloc ->dsd_addr\n", 4104 __func__); 4105 kfree(dsd); 4106 ha->dif_bundle_kallocs--; 4107 continue; 4108 } 4109 ha->dif_bundle_dma_allocs++; 4110 4111 /* 4112 * if DMA buffer crosses 4G boundary, 4113 * put it on bad list 4114 */ 4115 if (MSD(dsd->dsd_list_dma) ^ 4116 MSD(dsd->dsd_list_dma + bufsize)) { 4117 list_add_tail(&dsd->list, 4118 &ha->pool.unusable.head); 4119 ha->pool.unusable.count++; 4120 } else { 4121 list_add_tail(&dsd->list, 4122 &ha->pool.good.head); 4123 ha->pool.good.count++; 4124 } 4125 } 4126 4127 /* return the good ones back to the pool */ 4128 list_for_each_entry_safe(dsd, nxt, 4129 &ha->pool.good.head, list) { 4130 list_del(&dsd->list); 4131 dma_pool_free(ha->dif_bundl_pool, 4132 dsd->dsd_addr, dsd->dsd_list_dma); 4133 ha->dif_bundle_dma_allocs--; 4134 kfree(dsd); 4135 ha->dif_bundle_kallocs--; 4136 } 4137 4138 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4139 "%s: dif dma pool (good=%u unusable=%u)\n", 4140 __func__, ha->pool.good.count, 4141 ha->pool.unusable.count); 4142 } 4143 4144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4145 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4146 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4147 ha->dif_bundl_pool); 4148 } 4149 4150 /* Allocate memory for SNS commands */ 4151 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4152 /* Get consistent memory allocated for SNS commands */ 4153 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4154 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4155 if (!ha->sns_cmd) 4156 goto fail_dma_pool; 4157 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4158 "sns_cmd: %p.\n", ha->sns_cmd); 4159 } else { 4160 /* Get consistent memory allocated for MS IOCB */ 4161 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4162 &ha->ms_iocb_dma); 4163 if (!ha->ms_iocb) 4164 goto fail_dma_pool; 4165 /* Get consistent memory allocated for CT SNS commands */ 4166 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4167 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4168 if (!ha->ct_sns) 4169 goto fail_free_ms_iocb; 4170 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4171 "ms_iocb=%p ct_sns=%p.\n", 4172 ha->ms_iocb, ha->ct_sns); 4173 } 4174 4175 /* Allocate memory for request ring */ 4176 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4177 if (!*req) { 4178 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4179 "Failed to allocate memory for req.\n"); 4180 goto fail_req; 4181 } 4182 (*req)->length = req_len; 4183 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4184 ((*req)->length + 1) * sizeof(request_t), 4185 &(*req)->dma, GFP_KERNEL); 4186 if (!(*req)->ring) { 4187 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4188 "Failed to allocate memory for req_ring.\n"); 4189 goto fail_req_ring; 4190 } 4191 /* Allocate memory for response ring */ 4192 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4193 if (!*rsp) { 4194 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4195 "Failed to allocate memory for rsp.\n"); 4196 goto fail_rsp; 4197 } 4198 (*rsp)->hw = ha; 4199 (*rsp)->length = rsp_len; 4200 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4201 ((*rsp)->length + 1) * sizeof(response_t), 4202 &(*rsp)->dma, GFP_KERNEL); 4203 if (!(*rsp)->ring) { 4204 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4205 "Failed to allocate memory for rsp_ring.\n"); 4206 goto fail_rsp_ring; 4207 } 4208 (*req)->rsp = *rsp; 4209 (*rsp)->req = *req; 4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4211 "req=%p req->length=%d req->ring=%p rsp=%p " 4212 "rsp->length=%d rsp->ring=%p.\n", 4213 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4214 (*rsp)->ring); 4215 /* Allocate memory for NVRAM data for vports */ 4216 if (ha->nvram_npiv_size) { 4217 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4218 sizeof(struct qla_npiv_entry), 4219 GFP_KERNEL); 4220 if (!ha->npiv_info) { 4221 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4222 "Failed to allocate memory for npiv_info.\n"); 4223 goto fail_npiv_info; 4224 } 4225 } else 4226 ha->npiv_info = NULL; 4227 4228 /* Get consistent memory allocated for EX-INIT-CB. */ 4229 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4230 IS_QLA28XX(ha)) { 4231 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4232 &ha->ex_init_cb_dma); 4233 if (!ha->ex_init_cb) 4234 goto fail_ex_init_cb; 4235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4236 "ex_init_cb=%p.\n", ha->ex_init_cb); 4237 } 4238 4239 /* Get consistent memory allocated for Special Features-CB. */ 4240 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4241 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4242 &ha->sf_init_cb_dma); 4243 if (!ha->sf_init_cb) 4244 goto fail_sf_init_cb; 4245 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb)); 4246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4247 "sf_init_cb=%p.\n", ha->sf_init_cb); 4248 } 4249 4250 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4251 4252 /* Get consistent memory allocated for Async Port-Database. */ 4253 if (!IS_FWI2_CAPABLE(ha)) { 4254 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4255 &ha->async_pd_dma); 4256 if (!ha->async_pd) 4257 goto fail_async_pd; 4258 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4259 "async_pd=%p.\n", ha->async_pd); 4260 } 4261 4262 INIT_LIST_HEAD(&ha->vp_list); 4263 4264 /* Allocate memory for our loop_id bitmap */ 4265 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4266 sizeof(long), 4267 GFP_KERNEL); 4268 if (!ha->loop_id_map) 4269 goto fail_loop_id_map; 4270 else { 4271 qla2x00_set_reserved_loop_ids(ha); 4272 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4273 "loop_id_map=%p.\n", ha->loop_id_map); 4274 } 4275 4276 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4277 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4278 if (!ha->sfp_data) { 4279 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4280 "Unable to allocate memory for SFP read-data.\n"); 4281 goto fail_sfp_data; 4282 } 4283 4284 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4285 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4286 GFP_KERNEL); 4287 if (!ha->flt) { 4288 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4289 "Unable to allocate memory for FLT.\n"); 4290 goto fail_flt_buffer; 4291 } 4292 4293 return 0; 4294 4295 fail_flt_buffer: 4296 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4297 ha->sfp_data, ha->sfp_data_dma); 4298 fail_sfp_data: 4299 kfree(ha->loop_id_map); 4300 fail_loop_id_map: 4301 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4302 fail_async_pd: 4303 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4304 fail_sf_init_cb: 4305 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4306 fail_ex_init_cb: 4307 kfree(ha->npiv_info); 4308 fail_npiv_info: 4309 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4310 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4311 (*rsp)->ring = NULL; 4312 (*rsp)->dma = 0; 4313 fail_rsp_ring: 4314 kfree(*rsp); 4315 *rsp = NULL; 4316 fail_rsp: 4317 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4318 sizeof(request_t), (*req)->ring, (*req)->dma); 4319 (*req)->ring = NULL; 4320 (*req)->dma = 0; 4321 fail_req_ring: 4322 kfree(*req); 4323 *req = NULL; 4324 fail_req: 4325 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4326 ha->ct_sns, ha->ct_sns_dma); 4327 ha->ct_sns = NULL; 4328 ha->ct_sns_dma = 0; 4329 fail_free_ms_iocb: 4330 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4331 ha->ms_iocb = NULL; 4332 ha->ms_iocb_dma = 0; 4333 4334 if (ha->sns_cmd) 4335 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4336 ha->sns_cmd, ha->sns_cmd_dma); 4337 fail_dma_pool: 4338 if (ql2xenabledif) { 4339 struct dsd_dma *dsd, *nxt; 4340 4341 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4342 list) { 4343 list_del(&dsd->list); 4344 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4345 dsd->dsd_list_dma); 4346 ha->dif_bundle_dma_allocs--; 4347 kfree(dsd); 4348 ha->dif_bundle_kallocs--; 4349 ha->pool.unusable.count--; 4350 } 4351 dma_pool_destroy(ha->dif_bundl_pool); 4352 ha->dif_bundl_pool = NULL; 4353 } 4354 4355 fail_dif_bundl_dma_pool: 4356 if (IS_QLA82XX(ha) || ql2xenabledif) { 4357 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4358 ha->fcp_cmnd_dma_pool = NULL; 4359 } 4360 fail_dl_dma_pool: 4361 if (IS_QLA82XX(ha) || ql2xenabledif) { 4362 dma_pool_destroy(ha->dl_dma_pool); 4363 ha->dl_dma_pool = NULL; 4364 } 4365 fail_s_dma_pool: 4366 dma_pool_destroy(ha->s_dma_pool); 4367 ha->s_dma_pool = NULL; 4368 fail_free_nvram: 4369 kfree(ha->nvram); 4370 ha->nvram = NULL; 4371 fail_free_ctx_mempool: 4372 mempool_destroy(ha->ctx_mempool); 4373 ha->ctx_mempool = NULL; 4374 fail_free_srb_mempool: 4375 mempool_destroy(ha->srb_mempool); 4376 ha->srb_mempool = NULL; 4377 fail_free_gid_list: 4378 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4379 ha->gid_list, 4380 ha->gid_list_dma); 4381 ha->gid_list = NULL; 4382 ha->gid_list_dma = 0; 4383 fail_free_tgt_mem: 4384 qlt_mem_free(ha); 4385 fail_free_init_cb: 4386 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4387 ha->init_cb_dma); 4388 ha->init_cb = NULL; 4389 ha->init_cb_dma = 0; 4390 fail: 4391 ql_log(ql_log_fatal, NULL, 0x0030, 4392 "Memory allocation failure.\n"); 4393 return -ENOMEM; 4394 } 4395 4396 int 4397 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4398 { 4399 int rval; 4400 uint16_t size, max_cnt; 4401 uint32_t temp; 4402 struct qla_hw_data *ha = vha->hw; 4403 4404 /* Return if we don't need to alloacate any extended logins */ 4405 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4406 return QLA_SUCCESS; 4407 4408 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4409 return QLA_SUCCESS; 4410 4411 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4412 max_cnt = 0; 4413 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4414 if (rval != QLA_SUCCESS) { 4415 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4416 "Failed to get exlogin status.\n"); 4417 return rval; 4418 } 4419 4420 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4421 temp *= size; 4422 4423 if (temp != ha->exlogin_size) { 4424 qla2x00_free_exlogin_buffer(ha); 4425 ha->exlogin_size = temp; 4426 4427 ql_log(ql_log_info, vha, 0xd024, 4428 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4429 max_cnt, size, temp); 4430 4431 ql_log(ql_log_info, vha, 0xd025, 4432 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4433 4434 /* Get consistent memory for extended logins */ 4435 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4436 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4437 if (!ha->exlogin_buf) { 4438 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4439 "Failed to allocate memory for exlogin_buf_dma.\n"); 4440 return -ENOMEM; 4441 } 4442 } 4443 4444 /* Now configure the dma buffer */ 4445 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4446 if (rval) { 4447 ql_log(ql_log_fatal, vha, 0xd033, 4448 "Setup extended login buffer ****FAILED****.\n"); 4449 qla2x00_free_exlogin_buffer(ha); 4450 } 4451 4452 return rval; 4453 } 4454 4455 /* 4456 * qla2x00_free_exlogin_buffer 4457 * 4458 * Input: 4459 * ha = adapter block pointer 4460 */ 4461 void 4462 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4463 { 4464 if (ha->exlogin_buf) { 4465 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4466 ha->exlogin_buf, ha->exlogin_buf_dma); 4467 ha->exlogin_buf = NULL; 4468 ha->exlogin_size = 0; 4469 } 4470 } 4471 4472 static void 4473 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4474 { 4475 u32 temp; 4476 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4477 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4478 4479 if (max_cnt > vha->hw->max_exchg) 4480 max_cnt = vha->hw->max_exchg; 4481 4482 if (qla_ini_mode_enabled(vha)) { 4483 if (vha->ql2xiniexchg > max_cnt) 4484 vha->ql2xiniexchg = max_cnt; 4485 4486 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4487 *ret_cnt = vha->ql2xiniexchg; 4488 4489 } else if (qla_tgt_mode_enabled(vha)) { 4490 if (vha->ql2xexchoffld > max_cnt) { 4491 vha->ql2xexchoffld = max_cnt; 4492 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4493 } 4494 4495 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4496 *ret_cnt = vha->ql2xexchoffld; 4497 } else if (qla_dual_mode_enabled(vha)) { 4498 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4499 if (temp > max_cnt) { 4500 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4501 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4502 temp = max_cnt; 4503 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4504 } 4505 4506 if (temp > FW_DEF_EXCHANGES_CNT) 4507 *ret_cnt = temp; 4508 } 4509 } 4510 4511 int 4512 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4513 { 4514 int rval; 4515 u16 size, max_cnt; 4516 u32 actual_cnt, totsz; 4517 struct qla_hw_data *ha = vha->hw; 4518 4519 if (!ha->flags.exchoffld_enabled) 4520 return QLA_SUCCESS; 4521 4522 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4523 return QLA_SUCCESS; 4524 4525 max_cnt = 0; 4526 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4527 if (rval != QLA_SUCCESS) { 4528 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4529 "Failed to get exlogin status.\n"); 4530 return rval; 4531 } 4532 4533 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4534 ql_log(ql_log_info, vha, 0xd014, 4535 "Actual exchange offload count: %d.\n", actual_cnt); 4536 4537 totsz = actual_cnt * size; 4538 4539 if (totsz != ha->exchoffld_size) { 4540 qla2x00_free_exchoffld_buffer(ha); 4541 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4542 ha->exchoffld_size = 0; 4543 ha->flags.exchoffld_enabled = 0; 4544 return QLA_SUCCESS; 4545 } 4546 4547 ha->exchoffld_size = totsz; 4548 4549 ql_log(ql_log_info, vha, 0xd016, 4550 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4551 max_cnt, actual_cnt, size, totsz); 4552 4553 ql_log(ql_log_info, vha, 0xd017, 4554 "Exchange Buffers requested size = 0x%x\n", 4555 ha->exchoffld_size); 4556 4557 /* Get consistent memory for extended logins */ 4558 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4559 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4560 if (!ha->exchoffld_buf) { 4561 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4562 "Failed to allocate memory for Exchange Offload.\n"); 4563 4564 if (ha->max_exchg > 4565 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4566 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4567 } else if (ha->max_exchg > 4568 (FW_DEF_EXCHANGES_CNT + 512)) { 4569 ha->max_exchg -= 512; 4570 } else { 4571 ha->flags.exchoffld_enabled = 0; 4572 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4573 "Disabling Exchange offload due to lack of memory\n"); 4574 } 4575 ha->exchoffld_size = 0; 4576 4577 return -ENOMEM; 4578 } 4579 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4580 /* pathological case */ 4581 qla2x00_free_exchoffld_buffer(ha); 4582 ha->exchoffld_size = 0; 4583 ha->flags.exchoffld_enabled = 0; 4584 ql_log(ql_log_info, vha, 0xd016, 4585 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4586 ha->exchoffld_size, actual_cnt, size, totsz); 4587 return 0; 4588 } 4589 4590 /* Now configure the dma buffer */ 4591 rval = qla_set_exchoffld_mem_cfg(vha); 4592 if (rval) { 4593 ql_log(ql_log_fatal, vha, 0xd02e, 4594 "Setup exchange offload buffer ****FAILED****.\n"); 4595 qla2x00_free_exchoffld_buffer(ha); 4596 } else { 4597 /* re-adjust number of target exchange */ 4598 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4599 4600 if (qla_ini_mode_enabled(vha)) 4601 icb->exchange_count = 0; 4602 else 4603 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4604 } 4605 4606 return rval; 4607 } 4608 4609 /* 4610 * qla2x00_free_exchoffld_buffer 4611 * 4612 * Input: 4613 * ha = adapter block pointer 4614 */ 4615 void 4616 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4617 { 4618 if (ha->exchoffld_buf) { 4619 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4620 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4621 ha->exchoffld_buf = NULL; 4622 ha->exchoffld_size = 0; 4623 } 4624 } 4625 4626 /* 4627 * qla2x00_free_fw_dump 4628 * Frees fw dump stuff. 4629 * 4630 * Input: 4631 * ha = adapter block pointer 4632 */ 4633 static void 4634 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4635 { 4636 struct fwdt *fwdt = ha->fwdt; 4637 uint j; 4638 4639 if (ha->fce) 4640 dma_free_coherent(&ha->pdev->dev, 4641 FCE_SIZE, ha->fce, ha->fce_dma); 4642 4643 if (ha->eft) 4644 dma_free_coherent(&ha->pdev->dev, 4645 EFT_SIZE, ha->eft, ha->eft_dma); 4646 4647 if (ha->fw_dump) 4648 vfree(ha->fw_dump); 4649 4650 ha->fce = NULL; 4651 ha->fce_dma = 0; 4652 ha->flags.fce_enabled = 0; 4653 ha->eft = NULL; 4654 ha->eft_dma = 0; 4655 ha->fw_dumped = false; 4656 ha->fw_dump_cap_flags = 0; 4657 ha->fw_dump_reading = 0; 4658 ha->fw_dump = NULL; 4659 ha->fw_dump_len = 0; 4660 4661 for (j = 0; j < 2; j++, fwdt++) { 4662 if (fwdt->template) 4663 vfree(fwdt->template); 4664 fwdt->template = NULL; 4665 fwdt->length = 0; 4666 } 4667 } 4668 4669 /* 4670 * qla2x00_mem_free 4671 * Frees all adapter allocated memory. 4672 * 4673 * Input: 4674 * ha = adapter block pointer. 4675 */ 4676 static void 4677 qla2x00_mem_free(struct qla_hw_data *ha) 4678 { 4679 qla2x00_free_fw_dump(ha); 4680 4681 if (ha->mctp_dump) 4682 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4683 ha->mctp_dump_dma); 4684 ha->mctp_dump = NULL; 4685 4686 mempool_destroy(ha->srb_mempool); 4687 ha->srb_mempool = NULL; 4688 4689 if (ha->dcbx_tlv) 4690 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4691 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4692 ha->dcbx_tlv = NULL; 4693 4694 if (ha->xgmac_data) 4695 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4696 ha->xgmac_data, ha->xgmac_data_dma); 4697 ha->xgmac_data = NULL; 4698 4699 if (ha->sns_cmd) 4700 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4701 ha->sns_cmd, ha->sns_cmd_dma); 4702 ha->sns_cmd = NULL; 4703 ha->sns_cmd_dma = 0; 4704 4705 if (ha->ct_sns) 4706 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4707 ha->ct_sns, ha->ct_sns_dma); 4708 ha->ct_sns = NULL; 4709 ha->ct_sns_dma = 0; 4710 4711 if (ha->sfp_data) 4712 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4713 ha->sfp_data_dma); 4714 ha->sfp_data = NULL; 4715 4716 if (ha->flt) 4717 dma_free_coherent(&ha->pdev->dev, 4718 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4719 ha->flt, ha->flt_dma); 4720 ha->flt = NULL; 4721 ha->flt_dma = 0; 4722 4723 if (ha->ms_iocb) 4724 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4725 ha->ms_iocb = NULL; 4726 ha->ms_iocb_dma = 0; 4727 4728 if (ha->sf_init_cb) 4729 dma_pool_free(ha->s_dma_pool, 4730 ha->sf_init_cb, ha->sf_init_cb_dma); 4731 4732 if (ha->ex_init_cb) 4733 dma_pool_free(ha->s_dma_pool, 4734 ha->ex_init_cb, ha->ex_init_cb_dma); 4735 ha->ex_init_cb = NULL; 4736 ha->ex_init_cb_dma = 0; 4737 4738 if (ha->async_pd) 4739 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4740 ha->async_pd = NULL; 4741 ha->async_pd_dma = 0; 4742 4743 dma_pool_destroy(ha->s_dma_pool); 4744 ha->s_dma_pool = NULL; 4745 4746 if (ha->gid_list) 4747 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4748 ha->gid_list, ha->gid_list_dma); 4749 ha->gid_list = NULL; 4750 ha->gid_list_dma = 0; 4751 4752 if (IS_QLA82XX(ha)) { 4753 if (!list_empty(&ha->gbl_dsd_list)) { 4754 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4755 4756 /* clean up allocated prev pool */ 4757 list_for_each_entry_safe(dsd_ptr, 4758 tdsd_ptr, &ha->gbl_dsd_list, list) { 4759 dma_pool_free(ha->dl_dma_pool, 4760 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4761 list_del(&dsd_ptr->list); 4762 kfree(dsd_ptr); 4763 } 4764 } 4765 } 4766 4767 dma_pool_destroy(ha->dl_dma_pool); 4768 ha->dl_dma_pool = NULL; 4769 4770 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4771 ha->fcp_cmnd_dma_pool = NULL; 4772 4773 mempool_destroy(ha->ctx_mempool); 4774 ha->ctx_mempool = NULL; 4775 4776 if (ql2xenabledif && ha->dif_bundl_pool) { 4777 struct dsd_dma *dsd, *nxt; 4778 4779 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4780 list) { 4781 list_del(&dsd->list); 4782 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4783 dsd->dsd_list_dma); 4784 ha->dif_bundle_dma_allocs--; 4785 kfree(dsd); 4786 ha->dif_bundle_kallocs--; 4787 ha->pool.unusable.count--; 4788 } 4789 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4790 list_del(&dsd->list); 4791 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4792 dsd->dsd_list_dma); 4793 ha->dif_bundle_dma_allocs--; 4794 kfree(dsd); 4795 ha->dif_bundle_kallocs--; 4796 } 4797 } 4798 4799 dma_pool_destroy(ha->dif_bundl_pool); 4800 ha->dif_bundl_pool = NULL; 4801 4802 qlt_mem_free(ha); 4803 4804 if (ha->init_cb) 4805 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4806 ha->init_cb, ha->init_cb_dma); 4807 ha->init_cb = NULL; 4808 ha->init_cb_dma = 0; 4809 4810 vfree(ha->optrom_buffer); 4811 ha->optrom_buffer = NULL; 4812 kfree(ha->nvram); 4813 ha->nvram = NULL; 4814 kfree(ha->npiv_info); 4815 ha->npiv_info = NULL; 4816 kfree(ha->swl); 4817 ha->swl = NULL; 4818 kfree(ha->loop_id_map); 4819 ha->sf_init_cb = NULL; 4820 ha->sf_init_cb_dma = 0; 4821 ha->loop_id_map = NULL; 4822 } 4823 4824 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4825 struct qla_hw_data *ha) 4826 { 4827 struct Scsi_Host *host; 4828 struct scsi_qla_host *vha = NULL; 4829 4830 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4831 if (!host) { 4832 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4833 "Failed to allocate host from the scsi layer, aborting.\n"); 4834 return NULL; 4835 } 4836 4837 /* Clear our data area */ 4838 vha = shost_priv(host); 4839 memset(vha, 0, sizeof(scsi_qla_host_t)); 4840 4841 vha->host = host; 4842 vha->host_no = host->host_no; 4843 vha->hw = ha; 4844 4845 vha->qlini_mode = ql2x_ini_mode; 4846 vha->ql2xexchoffld = ql2xexchoffld; 4847 vha->ql2xiniexchg = ql2xiniexchg; 4848 4849 INIT_LIST_HEAD(&vha->vp_fcports); 4850 INIT_LIST_HEAD(&vha->work_list); 4851 INIT_LIST_HEAD(&vha->list); 4852 INIT_LIST_HEAD(&vha->qla_cmd_list); 4853 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4854 INIT_LIST_HEAD(&vha->logo_list); 4855 INIT_LIST_HEAD(&vha->plogi_ack_list); 4856 INIT_LIST_HEAD(&vha->qp_list); 4857 INIT_LIST_HEAD(&vha->gnl.fcports); 4858 INIT_LIST_HEAD(&vha->gpnid_list); 4859 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4860 4861 INIT_LIST_HEAD(&vha->purex_list.head); 4862 spin_lock_init(&vha->purex_list.lock); 4863 4864 spin_lock_init(&vha->work_lock); 4865 spin_lock_init(&vha->cmd_list_lock); 4866 init_waitqueue_head(&vha->fcport_waitQ); 4867 init_waitqueue_head(&vha->vref_waitq); 4868 4869 vha->gnl.size = sizeof(struct get_name_list_extended) * 4870 (ha->max_loop_id + 1); 4871 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4872 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4873 if (!vha->gnl.l) { 4874 ql_log(ql_log_fatal, vha, 0xd04a, 4875 "Alloc failed for name list.\n"); 4876 scsi_host_put(vha->host); 4877 return NULL; 4878 } 4879 4880 /* todo: what about ext login? */ 4881 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4882 vha->scan.l = vmalloc(vha->scan.size); 4883 if (!vha->scan.l) { 4884 ql_log(ql_log_fatal, vha, 0xd04a, 4885 "Alloc failed for scan database.\n"); 4886 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4887 vha->gnl.l, vha->gnl.ldma); 4888 vha->gnl.l = NULL; 4889 scsi_host_put(vha->host); 4890 return NULL; 4891 } 4892 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4893 4894 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 4895 ql_dbg(ql_dbg_init, vha, 0x0041, 4896 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4897 vha->host, vha->hw, vha, 4898 dev_name(&(ha->pdev->dev))); 4899 4900 return vha; 4901 } 4902 4903 struct qla_work_evt * 4904 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4905 { 4906 struct qla_work_evt *e; 4907 uint8_t bail; 4908 4909 if (test_bit(UNLOADING, &vha->dpc_flags)) 4910 return NULL; 4911 4912 QLA_VHA_MARK_BUSY(vha, bail); 4913 if (bail) 4914 return NULL; 4915 4916 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4917 if (!e) { 4918 QLA_VHA_MARK_NOT_BUSY(vha); 4919 return NULL; 4920 } 4921 4922 INIT_LIST_HEAD(&e->list); 4923 e->type = type; 4924 e->flags = QLA_EVT_FLAG_FREE; 4925 return e; 4926 } 4927 4928 int 4929 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4930 { 4931 unsigned long flags; 4932 bool q = false; 4933 4934 spin_lock_irqsave(&vha->work_lock, flags); 4935 list_add_tail(&e->list, &vha->work_list); 4936 4937 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4938 q = true; 4939 4940 spin_unlock_irqrestore(&vha->work_lock, flags); 4941 4942 if (q) 4943 queue_work(vha->hw->wq, &vha->iocb_work); 4944 4945 return QLA_SUCCESS; 4946 } 4947 4948 int 4949 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4950 u32 data) 4951 { 4952 struct qla_work_evt *e; 4953 4954 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4955 if (!e) 4956 return QLA_FUNCTION_FAILED; 4957 4958 e->u.aen.code = code; 4959 e->u.aen.data = data; 4960 return qla2x00_post_work(vha, e); 4961 } 4962 4963 int 4964 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4965 { 4966 struct qla_work_evt *e; 4967 4968 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4969 if (!e) 4970 return QLA_FUNCTION_FAILED; 4971 4972 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4973 return qla2x00_post_work(vha, e); 4974 } 4975 4976 #define qla2x00_post_async_work(name, type) \ 4977 int qla2x00_post_async_##name##_work( \ 4978 struct scsi_qla_host *vha, \ 4979 fc_port_t *fcport, uint16_t *data) \ 4980 { \ 4981 struct qla_work_evt *e; \ 4982 \ 4983 e = qla2x00_alloc_work(vha, type); \ 4984 if (!e) \ 4985 return QLA_FUNCTION_FAILED; \ 4986 \ 4987 e->u.logio.fcport = fcport; \ 4988 if (data) { \ 4989 e->u.logio.data[0] = data[0]; \ 4990 e->u.logio.data[1] = data[1]; \ 4991 } \ 4992 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4993 return qla2x00_post_work(vha, e); \ 4994 } 4995 4996 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4997 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4998 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4999 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5000 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5001 5002 int 5003 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5004 { 5005 struct qla_work_evt *e; 5006 5007 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5008 if (!e) 5009 return QLA_FUNCTION_FAILED; 5010 5011 e->u.uevent.code = code; 5012 return qla2x00_post_work(vha, e); 5013 } 5014 5015 static void 5016 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5017 { 5018 char event_string[40]; 5019 char *envp[] = { event_string, NULL }; 5020 5021 switch (code) { 5022 case QLA_UEVENT_CODE_FW_DUMP: 5023 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5024 vha->host_no); 5025 break; 5026 default: 5027 /* do nothing */ 5028 break; 5029 } 5030 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5031 } 5032 5033 int 5034 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5035 uint32_t *data, int cnt) 5036 { 5037 struct qla_work_evt *e; 5038 5039 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5040 if (!e) 5041 return QLA_FUNCTION_FAILED; 5042 5043 e->u.aenfx.evtcode = evtcode; 5044 e->u.aenfx.count = cnt; 5045 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5046 return qla2x00_post_work(vha, e); 5047 } 5048 5049 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5050 { 5051 unsigned long flags; 5052 5053 if (IS_SW_RESV_ADDR(fcport->d_id)) 5054 return; 5055 5056 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5057 if (fcport->disc_state == DSC_UPD_FCPORT) { 5058 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5059 return; 5060 } 5061 fcport->jiffies_at_registration = jiffies; 5062 fcport->sec_since_registration = 0; 5063 fcport->next_disc_state = DSC_DELETED; 5064 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5065 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5066 5067 queue_work(system_unbound_wq, &fcport->reg_work); 5068 } 5069 5070 static 5071 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5072 { 5073 unsigned long flags; 5074 fc_port_t *fcport = NULL, *tfcp; 5075 struct qlt_plogi_ack_t *pla = 5076 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5077 uint8_t free_fcport = 0; 5078 5079 ql_dbg(ql_dbg_disc, vha, 0xffff, 5080 "%s %d %8phC enter\n", 5081 __func__, __LINE__, e->u.new_sess.port_name); 5082 5083 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5084 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5085 if (fcport) { 5086 fcport->d_id = e->u.new_sess.id; 5087 if (pla) { 5088 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5089 memcpy(fcport->node_name, 5090 pla->iocb.u.isp24.u.plogi.node_name, 5091 WWN_SIZE); 5092 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5093 /* we took an extra ref_count to prevent PLOGI ACK when 5094 * fcport/sess has not been created. 5095 */ 5096 pla->ref_count--; 5097 } 5098 } else { 5099 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5100 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5101 if (fcport) { 5102 fcport->d_id = e->u.new_sess.id; 5103 fcport->flags |= FCF_FABRIC_DEVICE; 5104 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5105 fcport->tgt_short_link_down_cnt = 0; 5106 5107 memcpy(fcport->port_name, e->u.new_sess.port_name, 5108 WWN_SIZE); 5109 5110 fcport->fc4_type = e->u.new_sess.fc4_type; 5111 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5112 fcport->dm_login_expire = jiffies + 5113 QLA_N2N_WAIT_TIME * HZ; 5114 fcport->fc4_type = FS_FC4TYPE_FCP; 5115 fcport->n2n_flag = 1; 5116 if (vha->flags.nvme_enabled) 5117 fcport->fc4_type |= FS_FC4TYPE_NVME; 5118 } 5119 5120 } else { 5121 ql_dbg(ql_dbg_disc, vha, 0xffff, 5122 "%s %8phC mem alloc fail.\n", 5123 __func__, e->u.new_sess.port_name); 5124 5125 if (pla) { 5126 list_del(&pla->list); 5127 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5128 } 5129 return; 5130 } 5131 5132 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5133 /* search again to make sure no one else got ahead */ 5134 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5135 e->u.new_sess.port_name, 1); 5136 if (tfcp) { 5137 /* should rarily happen */ 5138 ql_dbg(ql_dbg_disc, vha, 0xffff, 5139 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5140 __func__, tfcp->port_name, tfcp->disc_state, 5141 tfcp->fw_login_state); 5142 5143 free_fcport = 1; 5144 } else { 5145 list_add_tail(&fcport->list, &vha->vp_fcports); 5146 5147 } 5148 if (pla) { 5149 qlt_plogi_ack_link(vha, pla, fcport, 5150 QLT_PLOGI_LINK_SAME_WWN); 5151 pla->ref_count--; 5152 } 5153 } 5154 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5155 5156 if (fcport) { 5157 fcport->id_changed = 1; 5158 fcport->scan_state = QLA_FCPORT_FOUND; 5159 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5160 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5161 5162 if (pla) { 5163 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5164 u16 wd3_lo; 5165 5166 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5167 fcport->local = 0; 5168 fcport->loop_id = 5169 le16_to_cpu( 5170 pla->iocb.u.isp24.nport_handle); 5171 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5172 wd3_lo = 5173 le16_to_cpu( 5174 pla->iocb.u.isp24.u.prli.wd3_lo); 5175 5176 if (wd3_lo & BIT_7) 5177 fcport->conf_compl_supported = 1; 5178 5179 if ((wd3_lo & BIT_4) == 0) 5180 fcport->port_type = FCT_INITIATOR; 5181 else 5182 fcport->port_type = FCT_TARGET; 5183 } 5184 qlt_plogi_ack_unref(vha, pla); 5185 } else { 5186 fc_port_t *dfcp = NULL; 5187 5188 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5189 tfcp = qla2x00_find_fcport_by_nportid(vha, 5190 &e->u.new_sess.id, 1); 5191 if (tfcp && (tfcp != fcport)) { 5192 /* 5193 * We have a conflict fcport with same NportID. 5194 */ 5195 ql_dbg(ql_dbg_disc, vha, 0xffff, 5196 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5197 __func__, tfcp->port_name, tfcp->disc_state, 5198 tfcp->fw_login_state); 5199 5200 switch (tfcp->disc_state) { 5201 case DSC_DELETED: 5202 break; 5203 case DSC_DELETE_PEND: 5204 fcport->login_pause = 1; 5205 tfcp->conflict = fcport; 5206 break; 5207 default: 5208 fcport->login_pause = 1; 5209 tfcp->conflict = fcport; 5210 dfcp = tfcp; 5211 break; 5212 } 5213 } 5214 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5215 if (dfcp) 5216 qlt_schedule_sess_for_deletion(tfcp); 5217 5218 if (N2N_TOPO(vha->hw)) { 5219 fcport->flags &= ~FCF_FABRIC_DEVICE; 5220 fcport->keep_nport_handle = 1; 5221 if (vha->flags.nvme_enabled) { 5222 fcport->fc4_type = 5223 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5224 fcport->n2n_flag = 1; 5225 } 5226 fcport->fw_login_state = 0; 5227 5228 schedule_delayed_work(&vha->scan.scan_work, 5); 5229 } else { 5230 qla24xx_fcport_handle_login(vha, fcport); 5231 } 5232 } 5233 } 5234 5235 if (free_fcport) { 5236 qla2x00_free_fcport(fcport); 5237 if (pla) { 5238 list_del(&pla->list); 5239 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5240 } 5241 } 5242 } 5243 5244 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5245 { 5246 struct srb *sp = e->u.iosb.sp; 5247 int rval; 5248 5249 rval = qla2x00_start_sp(sp); 5250 if (rval != QLA_SUCCESS) { 5251 ql_dbg(ql_dbg_disc, vha, 0x2043, 5252 "%s: %s: Re-issue IOCB failed (%d).\n", 5253 __func__, sp->name, rval); 5254 qla24xx_sp_unmap(vha, sp); 5255 } 5256 } 5257 5258 void 5259 qla2x00_do_work(struct scsi_qla_host *vha) 5260 { 5261 struct qla_work_evt *e, *tmp; 5262 unsigned long flags; 5263 LIST_HEAD(work); 5264 int rc; 5265 5266 spin_lock_irqsave(&vha->work_lock, flags); 5267 list_splice_init(&vha->work_list, &work); 5268 spin_unlock_irqrestore(&vha->work_lock, flags); 5269 5270 list_for_each_entry_safe(e, tmp, &work, list) { 5271 rc = QLA_SUCCESS; 5272 switch (e->type) { 5273 case QLA_EVT_AEN: 5274 fc_host_post_event(vha->host, fc_get_event_number(), 5275 e->u.aen.code, e->u.aen.data); 5276 break; 5277 case QLA_EVT_IDC_ACK: 5278 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5279 break; 5280 case QLA_EVT_ASYNC_LOGIN: 5281 qla2x00_async_login(vha, e->u.logio.fcport, 5282 e->u.logio.data); 5283 break; 5284 case QLA_EVT_ASYNC_LOGOUT: 5285 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5286 break; 5287 case QLA_EVT_ASYNC_ADISC: 5288 qla2x00_async_adisc(vha, e->u.logio.fcport, 5289 e->u.logio.data); 5290 break; 5291 case QLA_EVT_UEVENT: 5292 qla2x00_uevent_emit(vha, e->u.uevent.code); 5293 break; 5294 case QLA_EVT_AENFX: 5295 qlafx00_process_aen(vha, e); 5296 break; 5297 case QLA_EVT_GPNID: 5298 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5299 break; 5300 case QLA_EVT_UNMAP: 5301 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5302 break; 5303 case QLA_EVT_RELOGIN: 5304 qla2x00_relogin(vha); 5305 break; 5306 case QLA_EVT_NEW_SESS: 5307 qla24xx_create_new_sess(vha, e); 5308 break; 5309 case QLA_EVT_GPDB: 5310 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5311 e->u.fcport.opt); 5312 break; 5313 case QLA_EVT_PRLI: 5314 qla24xx_async_prli(vha, e->u.fcport.fcport); 5315 break; 5316 case QLA_EVT_GPSC: 5317 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5318 break; 5319 case QLA_EVT_GNL: 5320 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5321 break; 5322 case QLA_EVT_NACK: 5323 qla24xx_do_nack_work(vha, e); 5324 break; 5325 case QLA_EVT_ASYNC_PRLO: 5326 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5327 break; 5328 case QLA_EVT_ASYNC_PRLO_DONE: 5329 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5330 e->u.logio.data); 5331 break; 5332 case QLA_EVT_GPNFT: 5333 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5334 e->u.gpnft.sp); 5335 break; 5336 case QLA_EVT_GPNFT_DONE: 5337 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5338 break; 5339 case QLA_EVT_GNNFT_DONE: 5340 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5341 break; 5342 case QLA_EVT_GNNID: 5343 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5344 break; 5345 case QLA_EVT_GFPNID: 5346 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5347 break; 5348 case QLA_EVT_SP_RETRY: 5349 qla_sp_retry(vha, e); 5350 break; 5351 case QLA_EVT_IIDMA: 5352 qla_do_iidma_work(vha, e->u.fcport.fcport); 5353 break; 5354 case QLA_EVT_ELS_PLOGI: 5355 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5356 e->u.fcport.fcport, false); 5357 break; 5358 } 5359 5360 if (rc == EAGAIN) { 5361 /* put 'work' at head of 'vha->work_list' */ 5362 spin_lock_irqsave(&vha->work_lock, flags); 5363 list_splice(&work, &vha->work_list); 5364 spin_unlock_irqrestore(&vha->work_lock, flags); 5365 break; 5366 } 5367 list_del_init(&e->list); 5368 if (e->flags & QLA_EVT_FLAG_FREE) 5369 kfree(e); 5370 5371 /* For each work completed decrement vha ref count */ 5372 QLA_VHA_MARK_NOT_BUSY(vha); 5373 } 5374 } 5375 5376 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5377 { 5378 struct qla_work_evt *e; 5379 5380 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5381 5382 if (!e) { 5383 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5384 return QLA_FUNCTION_FAILED; 5385 } 5386 5387 return qla2x00_post_work(vha, e); 5388 } 5389 5390 /* Relogins all the fcports of a vport 5391 * Context: dpc thread 5392 */ 5393 void qla2x00_relogin(struct scsi_qla_host *vha) 5394 { 5395 fc_port_t *fcport; 5396 int status, relogin_needed = 0; 5397 struct event_arg ea; 5398 5399 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5400 /* 5401 * If the port is not ONLINE then try to login 5402 * to it if we haven't run out of retries. 5403 */ 5404 if (atomic_read(&fcport->state) != FCS_ONLINE && 5405 fcport->login_retry) { 5406 if (fcport->scan_state != QLA_FCPORT_FOUND || 5407 fcport->disc_state == DSC_LOGIN_COMPLETE) 5408 continue; 5409 5410 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5411 fcport->disc_state == DSC_DELETE_PEND) { 5412 relogin_needed = 1; 5413 } else { 5414 if (vha->hw->current_topology != ISP_CFG_NL) { 5415 memset(&ea, 0, sizeof(ea)); 5416 ea.fcport = fcport; 5417 qla24xx_handle_relogin_event(vha, &ea); 5418 } else if (vha->hw->current_topology == 5419 ISP_CFG_NL) { 5420 fcport->login_retry--; 5421 status = 5422 qla2x00_local_device_login(vha, 5423 fcport); 5424 if (status == QLA_SUCCESS) { 5425 fcport->old_loop_id = 5426 fcport->loop_id; 5427 ql_dbg(ql_dbg_disc, vha, 0x2003, 5428 "Port login OK: logged in ID 0x%x.\n", 5429 fcport->loop_id); 5430 qla2x00_update_fcport 5431 (vha, fcport); 5432 } else if (status == 1) { 5433 set_bit(RELOGIN_NEEDED, 5434 &vha->dpc_flags); 5435 /* retry the login again */ 5436 ql_dbg(ql_dbg_disc, vha, 0x2007, 5437 "Retrying %d login again loop_id 0x%x.\n", 5438 fcport->login_retry, 5439 fcport->loop_id); 5440 } else { 5441 fcport->login_retry = 0; 5442 } 5443 5444 if (fcport->login_retry == 0 && 5445 status != QLA_SUCCESS) 5446 qla2x00_clear_loop_id(fcport); 5447 } 5448 } 5449 } 5450 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5451 break; 5452 } 5453 5454 if (relogin_needed) 5455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5456 5457 ql_dbg(ql_dbg_disc, vha, 0x400e, 5458 "Relogin end.\n"); 5459 } 5460 5461 /* Schedule work on any of the dpc-workqueues */ 5462 void 5463 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5464 { 5465 struct qla_hw_data *ha = base_vha->hw; 5466 5467 switch (work_code) { 5468 case MBA_IDC_AEN: /* 0x8200 */ 5469 if (ha->dpc_lp_wq) 5470 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5471 break; 5472 5473 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5474 if (!ha->flags.nic_core_reset_hdlr_active) { 5475 if (ha->dpc_hp_wq) 5476 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5477 } else 5478 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5479 "NIC Core reset is already active. Skip " 5480 "scheduling it again.\n"); 5481 break; 5482 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5483 if (ha->dpc_hp_wq) 5484 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5485 break; 5486 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5487 if (ha->dpc_hp_wq) 5488 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5489 break; 5490 default: 5491 ql_log(ql_log_warn, base_vha, 0xb05f, 5492 "Unknown work-code=0x%x.\n", work_code); 5493 } 5494 5495 return; 5496 } 5497 5498 /* Work: Perform NIC Core Unrecoverable state handling */ 5499 void 5500 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5501 { 5502 struct qla_hw_data *ha = 5503 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5504 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5505 uint32_t dev_state = 0; 5506 5507 qla83xx_idc_lock(base_vha, 0); 5508 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5509 qla83xx_reset_ownership(base_vha); 5510 if (ha->flags.nic_core_reset_owner) { 5511 ha->flags.nic_core_reset_owner = 0; 5512 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5513 QLA8XXX_DEV_FAILED); 5514 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5515 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5516 } 5517 qla83xx_idc_unlock(base_vha, 0); 5518 } 5519 5520 /* Work: Execute IDC state handler */ 5521 void 5522 qla83xx_idc_state_handler_work(struct work_struct *work) 5523 { 5524 struct qla_hw_data *ha = 5525 container_of(work, struct qla_hw_data, idc_state_handler); 5526 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5527 uint32_t dev_state = 0; 5528 5529 qla83xx_idc_lock(base_vha, 0); 5530 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5531 if (dev_state == QLA8XXX_DEV_FAILED || 5532 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5533 qla83xx_idc_state_handler(base_vha); 5534 qla83xx_idc_unlock(base_vha, 0); 5535 } 5536 5537 static int 5538 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5539 { 5540 int rval = QLA_SUCCESS; 5541 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5542 uint32_t heart_beat_counter1, heart_beat_counter2; 5543 5544 do { 5545 if (time_after(jiffies, heart_beat_wait)) { 5546 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5547 "Nic Core f/w is not alive.\n"); 5548 rval = QLA_FUNCTION_FAILED; 5549 break; 5550 } 5551 5552 qla83xx_idc_lock(base_vha, 0); 5553 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5554 &heart_beat_counter1); 5555 qla83xx_idc_unlock(base_vha, 0); 5556 msleep(100); 5557 qla83xx_idc_lock(base_vha, 0); 5558 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5559 &heart_beat_counter2); 5560 qla83xx_idc_unlock(base_vha, 0); 5561 } while (heart_beat_counter1 == heart_beat_counter2); 5562 5563 return rval; 5564 } 5565 5566 /* Work: Perform NIC Core Reset handling */ 5567 void 5568 qla83xx_nic_core_reset_work(struct work_struct *work) 5569 { 5570 struct qla_hw_data *ha = 5571 container_of(work, struct qla_hw_data, nic_core_reset); 5572 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5573 uint32_t dev_state = 0; 5574 5575 if (IS_QLA2031(ha)) { 5576 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5577 ql_log(ql_log_warn, base_vha, 0xb081, 5578 "Failed to dump mctp\n"); 5579 return; 5580 } 5581 5582 if (!ha->flags.nic_core_reset_hdlr_active) { 5583 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5584 qla83xx_idc_lock(base_vha, 0); 5585 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5586 &dev_state); 5587 qla83xx_idc_unlock(base_vha, 0); 5588 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5589 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5590 "Nic Core f/w is alive.\n"); 5591 return; 5592 } 5593 } 5594 5595 ha->flags.nic_core_reset_hdlr_active = 1; 5596 if (qla83xx_nic_core_reset(base_vha)) { 5597 /* NIC Core reset failed. */ 5598 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5599 "NIC Core reset failed.\n"); 5600 } 5601 ha->flags.nic_core_reset_hdlr_active = 0; 5602 } 5603 } 5604 5605 /* Work: Handle 8200 IDC aens */ 5606 void 5607 qla83xx_service_idc_aen(struct work_struct *work) 5608 { 5609 struct qla_hw_data *ha = 5610 container_of(work, struct qla_hw_data, idc_aen); 5611 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5612 uint32_t dev_state, idc_control; 5613 5614 qla83xx_idc_lock(base_vha, 0); 5615 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5616 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5617 qla83xx_idc_unlock(base_vha, 0); 5618 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5619 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5620 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5621 "Application requested NIC Core Reset.\n"); 5622 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5623 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5624 QLA_SUCCESS) { 5625 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5626 "Other protocol driver requested NIC Core Reset.\n"); 5627 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5628 } 5629 } else if (dev_state == QLA8XXX_DEV_FAILED || 5630 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5631 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5632 } 5633 } 5634 5635 /* 5636 * Control the frequency of IDC lock retries 5637 */ 5638 #define QLA83XX_WAIT_LOGIC_MS 100 5639 5640 static int 5641 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5642 { 5643 int rval; 5644 uint32_t data; 5645 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5646 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5647 struct qla_hw_data *ha = base_vha->hw; 5648 5649 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5650 "Trying force recovery of the IDC lock.\n"); 5651 5652 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5653 if (rval) 5654 return rval; 5655 5656 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5657 return QLA_SUCCESS; 5658 } else { 5659 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5660 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5661 data); 5662 if (rval) 5663 return rval; 5664 5665 msleep(200); 5666 5667 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5668 &data); 5669 if (rval) 5670 return rval; 5671 5672 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5673 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5674 ~(idc_lck_rcvry_stage_mask)); 5675 rval = qla83xx_wr_reg(base_vha, 5676 QLA83XX_IDC_LOCK_RECOVERY, data); 5677 if (rval) 5678 return rval; 5679 5680 /* Forcefully perform IDC UnLock */ 5681 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5682 &data); 5683 if (rval) 5684 return rval; 5685 /* Clear lock-id by setting 0xff */ 5686 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5687 0xff); 5688 if (rval) 5689 return rval; 5690 /* Clear lock-recovery by setting 0x0 */ 5691 rval = qla83xx_wr_reg(base_vha, 5692 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5693 if (rval) 5694 return rval; 5695 } else 5696 return QLA_SUCCESS; 5697 } 5698 5699 return rval; 5700 } 5701 5702 static int 5703 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5704 { 5705 int rval = QLA_SUCCESS; 5706 uint32_t o_drv_lockid, n_drv_lockid; 5707 unsigned long lock_recovery_timeout; 5708 5709 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5710 retry_lockid: 5711 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5712 if (rval) 5713 goto exit; 5714 5715 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5716 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5717 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5718 return QLA_SUCCESS; 5719 else 5720 return QLA_FUNCTION_FAILED; 5721 } 5722 5723 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5724 if (rval) 5725 goto exit; 5726 5727 if (o_drv_lockid == n_drv_lockid) { 5728 msleep(QLA83XX_WAIT_LOGIC_MS); 5729 goto retry_lockid; 5730 } else 5731 return QLA_SUCCESS; 5732 5733 exit: 5734 return rval; 5735 } 5736 5737 /* 5738 * Context: task, can sleep 5739 */ 5740 void 5741 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5742 { 5743 uint32_t data; 5744 uint32_t lock_owner; 5745 struct qla_hw_data *ha = base_vha->hw; 5746 5747 might_sleep(); 5748 5749 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5750 retry_lock: 5751 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5752 == QLA_SUCCESS) { 5753 if (data) { 5754 /* Setting lock-id to our function-number */ 5755 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5756 ha->portnum); 5757 } else { 5758 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5759 &lock_owner); 5760 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5761 "Failed to acquire IDC lock, acquired by %d, " 5762 "retrying...\n", lock_owner); 5763 5764 /* Retry/Perform IDC-Lock recovery */ 5765 if (qla83xx_idc_lock_recovery(base_vha) 5766 == QLA_SUCCESS) { 5767 msleep(QLA83XX_WAIT_LOGIC_MS); 5768 goto retry_lock; 5769 } else 5770 ql_log(ql_log_warn, base_vha, 0xb075, 5771 "IDC Lock recovery FAILED.\n"); 5772 } 5773 5774 } 5775 5776 return; 5777 } 5778 5779 static bool 5780 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5781 struct purex_entry_24xx *purex) 5782 { 5783 char fwstr[16]; 5784 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5785 struct port_database_24xx *pdb; 5786 5787 /* Domain Controller is always logged-out. */ 5788 /* if RDP request is not from Domain Controller: */ 5789 if (sid != 0xfffc01) 5790 return false; 5791 5792 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5793 5794 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5795 if (!pdb) { 5796 ql_dbg(ql_dbg_init, vha, 0x0181, 5797 "%s: Failed allocate pdb\n", __func__); 5798 } else if (qla24xx_get_port_database(vha, 5799 le16_to_cpu(purex->nport_handle), pdb)) { 5800 ql_dbg(ql_dbg_init, vha, 0x0181, 5801 "%s: Failed get pdb sid=%x\n", __func__, sid); 5802 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5803 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5804 ql_dbg(ql_dbg_init, vha, 0x0181, 5805 "%s: Port not logged in sid=%#x\n", __func__, sid); 5806 } else { 5807 /* RDP request is from logged in port */ 5808 kfree(pdb); 5809 return false; 5810 } 5811 kfree(pdb); 5812 5813 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5814 fwstr[strcspn(fwstr, " ")] = 0; 5815 /* if FW version allows RDP response length upto 2048 bytes: */ 5816 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5817 return false; 5818 5819 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5820 5821 /* RDP response length is to be reduced to maximum 256 bytes */ 5822 return true; 5823 } 5824 5825 /* 5826 * Function Name: qla24xx_process_purex_iocb 5827 * 5828 * Description: 5829 * Prepare a RDP response and send to Fabric switch 5830 * 5831 * PARAMETERS: 5832 * vha: SCSI qla host 5833 * purex: RDP request received by HBA 5834 */ 5835 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5836 struct purex_item *item) 5837 { 5838 struct qla_hw_data *ha = vha->hw; 5839 struct purex_entry_24xx *purex = 5840 (struct purex_entry_24xx *)&item->iocb; 5841 dma_addr_t rsp_els_dma; 5842 dma_addr_t rsp_payload_dma; 5843 dma_addr_t stat_dma; 5844 dma_addr_t sfp_dma; 5845 struct els_entry_24xx *rsp_els = NULL; 5846 struct rdp_rsp_payload *rsp_payload = NULL; 5847 struct link_statistics *stat = NULL; 5848 uint8_t *sfp = NULL; 5849 uint16_t sfp_flags = 0; 5850 uint rsp_payload_length = sizeof(*rsp_payload); 5851 int rval; 5852 5853 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5854 "%s: Enter\n", __func__); 5855 5856 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5857 "-------- ELS REQ -------\n"); 5858 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5859 purex, sizeof(*purex)); 5860 5861 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5862 rsp_payload_length = 5863 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5864 ql_dbg(ql_dbg_init, vha, 0x0181, 5865 "Reducing RSP payload length to %u bytes...\n", 5866 rsp_payload_length); 5867 } 5868 5869 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5870 &rsp_els_dma, GFP_KERNEL); 5871 if (!rsp_els) { 5872 ql_log(ql_log_warn, vha, 0x0183, 5873 "Failed allocate dma buffer ELS RSP.\n"); 5874 goto dealloc; 5875 } 5876 5877 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5878 &rsp_payload_dma, GFP_KERNEL); 5879 if (!rsp_payload) { 5880 ql_log(ql_log_warn, vha, 0x0184, 5881 "Failed allocate dma buffer ELS RSP payload.\n"); 5882 goto dealloc; 5883 } 5884 5885 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5886 &sfp_dma, GFP_KERNEL); 5887 5888 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 5889 &stat_dma, GFP_KERNEL); 5890 5891 /* Prepare Response IOCB */ 5892 rsp_els->entry_type = ELS_IOCB_TYPE; 5893 rsp_els->entry_count = 1; 5894 rsp_els->sys_define = 0; 5895 rsp_els->entry_status = 0; 5896 rsp_els->handle = 0; 5897 rsp_els->nport_handle = purex->nport_handle; 5898 rsp_els->tx_dsd_count = cpu_to_le16(1); 5899 rsp_els->vp_index = purex->vp_idx; 5900 rsp_els->sof_type = EST_SOFI3; 5901 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 5902 rsp_els->rx_dsd_count = 0; 5903 rsp_els->opcode = purex->els_frame_payload[0]; 5904 5905 rsp_els->d_id[0] = purex->s_id[0]; 5906 rsp_els->d_id[1] = purex->s_id[1]; 5907 rsp_els->d_id[2] = purex->s_id[2]; 5908 5909 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 5910 rsp_els->rx_byte_count = 0; 5911 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 5912 5913 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 5914 rsp_els->tx_len = rsp_els->tx_byte_count; 5915 5916 rsp_els->rx_address = 0; 5917 rsp_els->rx_len = 0; 5918 5919 /* Prepare Response Payload */ 5920 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 5921 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 5922 sizeof(rsp_payload->hdr)); 5923 5924 /* Link service Request Info Descriptor */ 5925 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 5926 rsp_payload->ls_req_info_desc.desc_len = 5927 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 5928 rsp_payload->ls_req_info_desc.req_payload_word_0 = 5929 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5930 5931 /* Link service Request Info Descriptor 2 */ 5932 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 5933 rsp_payload->ls_req_info_desc2.desc_len = 5934 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 5935 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 5936 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5937 5938 5939 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 5940 rsp_payload->sfp_diag_desc.desc_len = 5941 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 5942 5943 if (sfp) { 5944 /* SFP Flags */ 5945 memset(sfp, 0, SFP_RTDI_LEN); 5946 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 5947 if (!rval) { 5948 /* SFP Flags bits 3-0: Port Tx Laser Type */ 5949 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 5950 sfp_flags |= BIT_0; /* short wave */ 5951 else if (sfp[0] & BIT_1) 5952 sfp_flags |= BIT_1; /* long wave 1310nm */ 5953 else if (sfp[1] & BIT_4) 5954 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 5955 } 5956 5957 /* SFP Type */ 5958 memset(sfp, 0, SFP_RTDI_LEN); 5959 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 5960 if (!rval) { 5961 sfp_flags |= BIT_4; /* optical */ 5962 if (sfp[0] == 0x3) 5963 sfp_flags |= BIT_6; /* sfp+ */ 5964 } 5965 5966 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 5967 5968 /* SFP Diagnostics */ 5969 memset(sfp, 0, SFP_RTDI_LEN); 5970 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 5971 if (!rval) { 5972 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 5973 rsp_payload->sfp_diag_desc.temperature = trx[0]; 5974 rsp_payload->sfp_diag_desc.vcc = trx[1]; 5975 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 5976 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 5977 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 5978 } 5979 } 5980 5981 /* Port Speed Descriptor */ 5982 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 5983 rsp_payload->port_speed_desc.desc_len = 5984 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 5985 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 5986 qla25xx_fdmi_port_speed_capability(ha)); 5987 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 5988 qla25xx_fdmi_port_speed_currently(ha)); 5989 5990 /* Link Error Status Descriptor */ 5991 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 5992 rsp_payload->ls_err_desc.desc_len = 5993 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 5994 5995 if (stat) { 5996 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 5997 if (!rval) { 5998 rsp_payload->ls_err_desc.link_fail_cnt = 5999 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6000 rsp_payload->ls_err_desc.loss_sync_cnt = 6001 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6002 rsp_payload->ls_err_desc.loss_sig_cnt = 6003 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6004 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6005 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6006 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6007 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6008 rsp_payload->ls_err_desc.inval_crc_cnt = 6009 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6010 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6011 } 6012 } 6013 6014 /* Portname Descriptor */ 6015 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6016 rsp_payload->port_name_diag_desc.desc_len = 6017 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6018 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6019 vha->node_name, 6020 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6021 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6022 vha->port_name, 6023 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6024 6025 /* F-Port Portname Descriptor */ 6026 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6027 rsp_payload->port_name_direct_desc.desc_len = 6028 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6029 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6030 vha->fabric_node_name, 6031 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6032 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6033 vha->fabric_port_name, 6034 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6035 6036 /* Bufer Credit Descriptor */ 6037 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6038 rsp_payload->buffer_credit_desc.desc_len = 6039 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6040 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6041 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6042 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6043 6044 if (ha->flags.plogi_template_valid) { 6045 uint32_t tmp = 6046 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6047 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6048 } 6049 6050 if (rsp_payload_length < sizeof(*rsp_payload)) 6051 goto send; 6052 6053 /* Optical Element Descriptor, Temperature */ 6054 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6055 rsp_payload->optical_elmt_desc[0].desc_len = 6056 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6057 /* Optical Element Descriptor, Voltage */ 6058 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6059 rsp_payload->optical_elmt_desc[1].desc_len = 6060 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6061 /* Optical Element Descriptor, Tx Bias Current */ 6062 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6063 rsp_payload->optical_elmt_desc[2].desc_len = 6064 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6065 /* Optical Element Descriptor, Tx Power */ 6066 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6067 rsp_payload->optical_elmt_desc[3].desc_len = 6068 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6069 /* Optical Element Descriptor, Rx Power */ 6070 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6071 rsp_payload->optical_elmt_desc[4].desc_len = 6072 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6073 6074 if (sfp) { 6075 memset(sfp, 0, SFP_RTDI_LEN); 6076 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6077 if (!rval) { 6078 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6079 6080 /* Optical Element Descriptor, Temperature */ 6081 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6082 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6083 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6084 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6085 rsp_payload->optical_elmt_desc[0].element_flags = 6086 cpu_to_be32(1 << 28); 6087 6088 /* Optical Element Descriptor, Voltage */ 6089 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6090 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6091 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6092 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6093 rsp_payload->optical_elmt_desc[1].element_flags = 6094 cpu_to_be32(2 << 28); 6095 6096 /* Optical Element Descriptor, Tx Bias Current */ 6097 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6098 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6099 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6100 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6101 rsp_payload->optical_elmt_desc[2].element_flags = 6102 cpu_to_be32(3 << 28); 6103 6104 /* Optical Element Descriptor, Tx Power */ 6105 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6106 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6107 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6108 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6109 rsp_payload->optical_elmt_desc[3].element_flags = 6110 cpu_to_be32(4 << 28); 6111 6112 /* Optical Element Descriptor, Rx Power */ 6113 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6114 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6115 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6116 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6117 rsp_payload->optical_elmt_desc[4].element_flags = 6118 cpu_to_be32(5 << 28); 6119 } 6120 6121 memset(sfp, 0, SFP_RTDI_LEN); 6122 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6123 if (!rval) { 6124 /* Temperature high/low alarm/warning */ 6125 rsp_payload->optical_elmt_desc[0].element_flags |= 6126 cpu_to_be32( 6127 (sfp[0] >> 7 & 1) << 3 | 6128 (sfp[0] >> 6 & 1) << 2 | 6129 (sfp[4] >> 7 & 1) << 1 | 6130 (sfp[4] >> 6 & 1) << 0); 6131 6132 /* Voltage high/low alarm/warning */ 6133 rsp_payload->optical_elmt_desc[1].element_flags |= 6134 cpu_to_be32( 6135 (sfp[0] >> 5 & 1) << 3 | 6136 (sfp[0] >> 4 & 1) << 2 | 6137 (sfp[4] >> 5 & 1) << 1 | 6138 (sfp[4] >> 4 & 1) << 0); 6139 6140 /* Tx Bias Current high/low alarm/warning */ 6141 rsp_payload->optical_elmt_desc[2].element_flags |= 6142 cpu_to_be32( 6143 (sfp[0] >> 3 & 1) << 3 | 6144 (sfp[0] >> 2 & 1) << 2 | 6145 (sfp[4] >> 3 & 1) << 1 | 6146 (sfp[4] >> 2 & 1) << 0); 6147 6148 /* Tx Power high/low alarm/warning */ 6149 rsp_payload->optical_elmt_desc[3].element_flags |= 6150 cpu_to_be32( 6151 (sfp[0] >> 1 & 1) << 3 | 6152 (sfp[0] >> 0 & 1) << 2 | 6153 (sfp[4] >> 1 & 1) << 1 | 6154 (sfp[4] >> 0 & 1) << 0); 6155 6156 /* Rx Power high/low alarm/warning */ 6157 rsp_payload->optical_elmt_desc[4].element_flags |= 6158 cpu_to_be32( 6159 (sfp[1] >> 7 & 1) << 3 | 6160 (sfp[1] >> 6 & 1) << 2 | 6161 (sfp[5] >> 7 & 1) << 1 | 6162 (sfp[5] >> 6 & 1) << 0); 6163 } 6164 } 6165 6166 /* Optical Product Data Descriptor */ 6167 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6168 rsp_payload->optical_prod_desc.desc_len = 6169 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6170 6171 if (sfp) { 6172 memset(sfp, 0, SFP_RTDI_LEN); 6173 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6174 if (!rval) { 6175 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6176 sfp + 0, 6177 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6178 memcpy(rsp_payload->optical_prod_desc.part_number, 6179 sfp + 20, 6180 sizeof(rsp_payload->optical_prod_desc.part_number)); 6181 memcpy(rsp_payload->optical_prod_desc.revision, 6182 sfp + 36, 6183 sizeof(rsp_payload->optical_prod_desc.revision)); 6184 memcpy(rsp_payload->optical_prod_desc.serial_number, 6185 sfp + 48, 6186 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6187 } 6188 6189 memset(sfp, 0, SFP_RTDI_LEN); 6190 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6191 if (!rval) { 6192 memcpy(rsp_payload->optical_prod_desc.date, 6193 sfp + 0, 6194 sizeof(rsp_payload->optical_prod_desc.date)); 6195 } 6196 } 6197 6198 send: 6199 ql_dbg(ql_dbg_init, vha, 0x0183, 6200 "Sending ELS Response to RDP Request...\n"); 6201 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6202 "-------- ELS RSP -------\n"); 6203 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6204 rsp_els, sizeof(*rsp_els)); 6205 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6206 "-------- ELS RSP PAYLOAD -------\n"); 6207 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6208 rsp_payload, rsp_payload_length); 6209 6210 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6211 6212 if (rval) { 6213 ql_log(ql_log_warn, vha, 0x0188, 6214 "%s: iocb failed to execute -> %x\n", __func__, rval); 6215 } else if (rsp_els->comp_status) { 6216 ql_log(ql_log_warn, vha, 0x0189, 6217 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6218 __func__, rsp_els->comp_status, 6219 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6220 } else { 6221 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6222 } 6223 6224 dealloc: 6225 if (stat) 6226 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6227 stat, stat_dma); 6228 if (sfp) 6229 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6230 sfp, sfp_dma); 6231 if (rsp_payload) 6232 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6233 rsp_payload, rsp_payload_dma); 6234 if (rsp_els) 6235 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6236 rsp_els, rsp_els_dma); 6237 } 6238 6239 void 6240 qla24xx_free_purex_item(struct purex_item *item) 6241 { 6242 if (item == &item->vha->default_item) 6243 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6244 else 6245 kfree(item); 6246 } 6247 6248 void qla24xx_process_purex_list(struct purex_list *list) 6249 { 6250 struct list_head head = LIST_HEAD_INIT(head); 6251 struct purex_item *item, *next; 6252 ulong flags; 6253 6254 spin_lock_irqsave(&list->lock, flags); 6255 list_splice_init(&list->head, &head); 6256 spin_unlock_irqrestore(&list->lock, flags); 6257 6258 list_for_each_entry_safe(item, next, &head, list) { 6259 list_del(&item->list); 6260 item->process_item(item->vha, item); 6261 qla24xx_free_purex_item(item); 6262 } 6263 } 6264 6265 /* 6266 * Context: task, can sleep 6267 */ 6268 void 6269 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6270 { 6271 #if 0 6272 uint16_t options = (requester_id << 15) | BIT_7; 6273 #endif 6274 uint16_t retry; 6275 uint32_t data; 6276 struct qla_hw_data *ha = base_vha->hw; 6277 6278 might_sleep(); 6279 6280 /* IDC-unlock implementation using driver-unlock/lock-id 6281 * remote registers 6282 */ 6283 retry = 0; 6284 retry_unlock: 6285 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6286 == QLA_SUCCESS) { 6287 if (data == ha->portnum) { 6288 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6289 /* Clearing lock-id by setting 0xff */ 6290 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6291 } else if (retry < 10) { 6292 /* SV: XXX: IDC unlock retrying needed here? */ 6293 6294 /* Retry for IDC-unlock */ 6295 msleep(QLA83XX_WAIT_LOGIC_MS); 6296 retry++; 6297 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6298 "Failed to release IDC lock, retrying=%d\n", retry); 6299 goto retry_unlock; 6300 } 6301 } else if (retry < 10) { 6302 /* Retry for IDC-unlock */ 6303 msleep(QLA83XX_WAIT_LOGIC_MS); 6304 retry++; 6305 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6306 "Failed to read drv-lockid, retrying=%d\n", retry); 6307 goto retry_unlock; 6308 } 6309 6310 return; 6311 6312 #if 0 6313 /* XXX: IDC-unlock implementation using access-control mbx */ 6314 retry = 0; 6315 retry_unlock2: 6316 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6317 if (retry < 10) { 6318 /* Retry for IDC-unlock */ 6319 msleep(QLA83XX_WAIT_LOGIC_MS); 6320 retry++; 6321 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6322 "Failed to release IDC lock, retrying=%d\n", retry); 6323 goto retry_unlock2; 6324 } 6325 } 6326 6327 return; 6328 #endif 6329 } 6330 6331 int 6332 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6333 { 6334 int rval = QLA_SUCCESS; 6335 struct qla_hw_data *ha = vha->hw; 6336 uint32_t drv_presence; 6337 6338 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6339 if (rval == QLA_SUCCESS) { 6340 drv_presence |= (1 << ha->portnum); 6341 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6342 drv_presence); 6343 } 6344 6345 return rval; 6346 } 6347 6348 int 6349 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6350 { 6351 int rval = QLA_SUCCESS; 6352 6353 qla83xx_idc_lock(vha, 0); 6354 rval = __qla83xx_set_drv_presence(vha); 6355 qla83xx_idc_unlock(vha, 0); 6356 6357 return rval; 6358 } 6359 6360 int 6361 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6362 { 6363 int rval = QLA_SUCCESS; 6364 struct qla_hw_data *ha = vha->hw; 6365 uint32_t drv_presence; 6366 6367 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6368 if (rval == QLA_SUCCESS) { 6369 drv_presence &= ~(1 << ha->portnum); 6370 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6371 drv_presence); 6372 } 6373 6374 return rval; 6375 } 6376 6377 int 6378 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6379 { 6380 int rval = QLA_SUCCESS; 6381 6382 qla83xx_idc_lock(vha, 0); 6383 rval = __qla83xx_clear_drv_presence(vha); 6384 qla83xx_idc_unlock(vha, 0); 6385 6386 return rval; 6387 } 6388 6389 static void 6390 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6391 { 6392 struct qla_hw_data *ha = vha->hw; 6393 uint32_t drv_ack, drv_presence; 6394 unsigned long ack_timeout; 6395 6396 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6397 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6398 while (1) { 6399 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6400 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6401 if ((drv_ack & drv_presence) == drv_presence) 6402 break; 6403 6404 if (time_after_eq(jiffies, ack_timeout)) { 6405 ql_log(ql_log_warn, vha, 0xb067, 6406 "RESET ACK TIMEOUT! drv_presence=0x%x " 6407 "drv_ack=0x%x\n", drv_presence, drv_ack); 6408 /* 6409 * The function(s) which did not ack in time are forced 6410 * to withdraw any further participation in the IDC 6411 * reset. 6412 */ 6413 if (drv_ack != drv_presence) 6414 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6415 drv_ack); 6416 break; 6417 } 6418 6419 qla83xx_idc_unlock(vha, 0); 6420 msleep(1000); 6421 qla83xx_idc_lock(vha, 0); 6422 } 6423 6424 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6425 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6426 } 6427 6428 static int 6429 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6430 { 6431 int rval = QLA_SUCCESS; 6432 uint32_t idc_control; 6433 6434 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6435 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6436 6437 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6438 __qla83xx_get_idc_control(vha, &idc_control); 6439 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6440 __qla83xx_set_idc_control(vha, 0); 6441 6442 qla83xx_idc_unlock(vha, 0); 6443 rval = qla83xx_restart_nic_firmware(vha); 6444 qla83xx_idc_lock(vha, 0); 6445 6446 if (rval != QLA_SUCCESS) { 6447 ql_log(ql_log_fatal, vha, 0xb06a, 6448 "Failed to restart NIC f/w.\n"); 6449 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6450 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6451 } else { 6452 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6453 "Success in restarting nic f/w.\n"); 6454 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6455 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6456 } 6457 6458 return rval; 6459 } 6460 6461 /* Assumes idc_lock always held on entry */ 6462 int 6463 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6464 { 6465 struct qla_hw_data *ha = base_vha->hw; 6466 int rval = QLA_SUCCESS; 6467 unsigned long dev_init_timeout; 6468 uint32_t dev_state; 6469 6470 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6471 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6472 6473 while (1) { 6474 6475 if (time_after_eq(jiffies, dev_init_timeout)) { 6476 ql_log(ql_log_warn, base_vha, 0xb06e, 6477 "Initialization TIMEOUT!\n"); 6478 /* Init timeout. Disable further NIC Core 6479 * communication. 6480 */ 6481 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6482 QLA8XXX_DEV_FAILED); 6483 ql_log(ql_log_info, base_vha, 0xb06f, 6484 "HW State: FAILED.\n"); 6485 } 6486 6487 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6488 switch (dev_state) { 6489 case QLA8XXX_DEV_READY: 6490 if (ha->flags.nic_core_reset_owner) 6491 qla83xx_idc_audit(base_vha, 6492 IDC_AUDIT_COMPLETION); 6493 ha->flags.nic_core_reset_owner = 0; 6494 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6495 "Reset_owner reset by 0x%x.\n", 6496 ha->portnum); 6497 goto exit; 6498 case QLA8XXX_DEV_COLD: 6499 if (ha->flags.nic_core_reset_owner) 6500 rval = qla83xx_device_bootstrap(base_vha); 6501 else { 6502 /* Wait for AEN to change device-state */ 6503 qla83xx_idc_unlock(base_vha, 0); 6504 msleep(1000); 6505 qla83xx_idc_lock(base_vha, 0); 6506 } 6507 break; 6508 case QLA8XXX_DEV_INITIALIZING: 6509 /* Wait for AEN to change device-state */ 6510 qla83xx_idc_unlock(base_vha, 0); 6511 msleep(1000); 6512 qla83xx_idc_lock(base_vha, 0); 6513 break; 6514 case QLA8XXX_DEV_NEED_RESET: 6515 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6516 qla83xx_need_reset_handler(base_vha); 6517 else { 6518 /* Wait for AEN to change device-state */ 6519 qla83xx_idc_unlock(base_vha, 0); 6520 msleep(1000); 6521 qla83xx_idc_lock(base_vha, 0); 6522 } 6523 /* reset timeout value after need reset handler */ 6524 dev_init_timeout = jiffies + 6525 (ha->fcoe_dev_init_timeout * HZ); 6526 break; 6527 case QLA8XXX_DEV_NEED_QUIESCENT: 6528 /* XXX: DEBUG for now */ 6529 qla83xx_idc_unlock(base_vha, 0); 6530 msleep(1000); 6531 qla83xx_idc_lock(base_vha, 0); 6532 break; 6533 case QLA8XXX_DEV_QUIESCENT: 6534 /* XXX: DEBUG for now */ 6535 if (ha->flags.quiesce_owner) 6536 goto exit; 6537 6538 qla83xx_idc_unlock(base_vha, 0); 6539 msleep(1000); 6540 qla83xx_idc_lock(base_vha, 0); 6541 dev_init_timeout = jiffies + 6542 (ha->fcoe_dev_init_timeout * HZ); 6543 break; 6544 case QLA8XXX_DEV_FAILED: 6545 if (ha->flags.nic_core_reset_owner) 6546 qla83xx_idc_audit(base_vha, 6547 IDC_AUDIT_COMPLETION); 6548 ha->flags.nic_core_reset_owner = 0; 6549 __qla83xx_clear_drv_presence(base_vha); 6550 qla83xx_idc_unlock(base_vha, 0); 6551 qla8xxx_dev_failed_handler(base_vha); 6552 rval = QLA_FUNCTION_FAILED; 6553 qla83xx_idc_lock(base_vha, 0); 6554 goto exit; 6555 case QLA8XXX_BAD_VALUE: 6556 qla83xx_idc_unlock(base_vha, 0); 6557 msleep(1000); 6558 qla83xx_idc_lock(base_vha, 0); 6559 break; 6560 default: 6561 ql_log(ql_log_warn, base_vha, 0xb071, 6562 "Unknown Device State: %x.\n", dev_state); 6563 qla83xx_idc_unlock(base_vha, 0); 6564 qla8xxx_dev_failed_handler(base_vha); 6565 rval = QLA_FUNCTION_FAILED; 6566 qla83xx_idc_lock(base_vha, 0); 6567 goto exit; 6568 } 6569 } 6570 6571 exit: 6572 return rval; 6573 } 6574 6575 void 6576 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6577 { 6578 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6579 board_disable); 6580 struct pci_dev *pdev = ha->pdev; 6581 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6582 6583 ql_log(ql_log_warn, base_vha, 0x015b, 6584 "Disabling adapter.\n"); 6585 6586 if (!atomic_read(&pdev->enable_cnt)) { 6587 ql_log(ql_log_info, base_vha, 0xfffc, 6588 "PCI device disabled, no action req for PCI error=%lx\n", 6589 base_vha->pci_flags); 6590 return; 6591 } 6592 6593 /* 6594 * if UNLOADING flag is already set, then continue unload, 6595 * where it was set first. 6596 */ 6597 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6598 return; 6599 6600 qla2x00_wait_for_sess_deletion(base_vha); 6601 6602 qla2x00_delete_all_vps(ha, base_vha); 6603 6604 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6605 6606 qla2x00_dfs_remove(base_vha); 6607 6608 qla84xx_put_chip(base_vha); 6609 6610 if (base_vha->timer_active) 6611 qla2x00_stop_timer(base_vha); 6612 6613 base_vha->flags.online = 0; 6614 6615 qla2x00_destroy_deferred_work(ha); 6616 6617 /* 6618 * Do not try to stop beacon blink as it will issue a mailbox 6619 * command. 6620 */ 6621 qla2x00_free_sysfs_attr(base_vha, false); 6622 6623 fc_remove_host(base_vha->host); 6624 6625 scsi_remove_host(base_vha->host); 6626 6627 base_vha->flags.init_done = 0; 6628 qla25xx_delete_queues(base_vha); 6629 qla2x00_free_fcports(base_vha); 6630 qla2x00_free_irqs(base_vha); 6631 qla2x00_mem_free(ha); 6632 qla82xx_md_free(base_vha); 6633 qla2x00_free_queues(ha); 6634 6635 qla2x00_unmap_iobases(ha); 6636 6637 pci_release_selected_regions(ha->pdev, ha->bars); 6638 pci_disable_pcie_error_reporting(pdev); 6639 pci_disable_device(pdev); 6640 6641 /* 6642 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6643 */ 6644 } 6645 6646 /************************************************************************** 6647 * qla2x00_do_dpc 6648 * This kernel thread is a task that is schedule by the interrupt handler 6649 * to perform the background processing for interrupts. 6650 * 6651 * Notes: 6652 * This task always run in the context of a kernel thread. It 6653 * is kick-off by the driver's detect code and starts up 6654 * up one per adapter. It immediately goes to sleep and waits for 6655 * some fibre event. When either the interrupt handler or 6656 * the timer routine detects a event it will one of the task 6657 * bits then wake us up. 6658 **************************************************************************/ 6659 static int 6660 qla2x00_do_dpc(void *data) 6661 { 6662 scsi_qla_host_t *base_vha; 6663 struct qla_hw_data *ha; 6664 uint32_t online; 6665 struct qla_qpair *qpair; 6666 6667 ha = (struct qla_hw_data *)data; 6668 base_vha = pci_get_drvdata(ha->pdev); 6669 6670 set_user_nice(current, MIN_NICE); 6671 6672 set_current_state(TASK_INTERRUPTIBLE); 6673 while (!kthread_should_stop()) { 6674 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6675 "DPC handler sleeping.\n"); 6676 6677 schedule(); 6678 6679 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6680 goto end_loop; 6681 6682 if (ha->flags.eeh_busy) { 6683 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6684 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6685 goto end_loop; 6686 } 6687 6688 ha->dpc_active = 1; 6689 6690 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6691 "DPC handler waking up, dpc_flags=0x%lx.\n", 6692 base_vha->dpc_flags); 6693 6694 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6695 break; 6696 6697 if (IS_P3P_TYPE(ha)) { 6698 if (IS_QLA8044(ha)) { 6699 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6700 &base_vha->dpc_flags)) { 6701 qla8044_idc_lock(ha); 6702 qla8044_wr_direct(base_vha, 6703 QLA8044_CRB_DEV_STATE_INDEX, 6704 QLA8XXX_DEV_FAILED); 6705 qla8044_idc_unlock(ha); 6706 ql_log(ql_log_info, base_vha, 0x4004, 6707 "HW State: FAILED.\n"); 6708 qla8044_device_state_handler(base_vha); 6709 continue; 6710 } 6711 6712 } else { 6713 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6714 &base_vha->dpc_flags)) { 6715 qla82xx_idc_lock(ha); 6716 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6717 QLA8XXX_DEV_FAILED); 6718 qla82xx_idc_unlock(ha); 6719 ql_log(ql_log_info, base_vha, 0x0151, 6720 "HW State: FAILED.\n"); 6721 qla82xx_device_state_handler(base_vha); 6722 continue; 6723 } 6724 } 6725 6726 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6727 &base_vha->dpc_flags)) { 6728 6729 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6730 "FCoE context reset scheduled.\n"); 6731 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6732 &base_vha->dpc_flags))) { 6733 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6734 /* FCoE-ctx reset failed. 6735 * Escalate to chip-reset 6736 */ 6737 set_bit(ISP_ABORT_NEEDED, 6738 &base_vha->dpc_flags); 6739 } 6740 clear_bit(ABORT_ISP_ACTIVE, 6741 &base_vha->dpc_flags); 6742 } 6743 6744 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6745 "FCoE context reset end.\n"); 6746 } 6747 } else if (IS_QLAFX00(ha)) { 6748 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6749 &base_vha->dpc_flags)) { 6750 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6751 "Firmware Reset Recovery\n"); 6752 if (qlafx00_reset_initialize(base_vha)) { 6753 /* Failed. Abort isp later. */ 6754 if (!test_bit(UNLOADING, 6755 &base_vha->dpc_flags)) { 6756 set_bit(ISP_UNRECOVERABLE, 6757 &base_vha->dpc_flags); 6758 ql_dbg(ql_dbg_dpc, base_vha, 6759 0x4021, 6760 "Reset Recovery Failed\n"); 6761 } 6762 } 6763 } 6764 6765 if (test_and_clear_bit(FX00_TARGET_SCAN, 6766 &base_vha->dpc_flags)) { 6767 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6768 "ISPFx00 Target Scan scheduled\n"); 6769 if (qlafx00_rescan_isp(base_vha)) { 6770 if (!test_bit(UNLOADING, 6771 &base_vha->dpc_flags)) 6772 set_bit(ISP_UNRECOVERABLE, 6773 &base_vha->dpc_flags); 6774 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6775 "ISPFx00 Target Scan Failed\n"); 6776 } 6777 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6778 "ISPFx00 Target Scan End\n"); 6779 } 6780 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6781 &base_vha->dpc_flags)) { 6782 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6783 "ISPFx00 Host Info resend scheduled\n"); 6784 qlafx00_fx_disc(base_vha, 6785 &base_vha->hw->mr.fcport, 6786 FXDISC_REG_HOST_INFO); 6787 } 6788 } 6789 6790 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6791 &base_vha->dpc_flags)) { 6792 /* Semantic: 6793 * - NO-OP -- await next ISP-ABORT. Preferred method 6794 * to minimize disruptions that will occur 6795 * when a forced chip-reset occurs. 6796 * - Force -- ISP-ABORT scheduled. 6797 */ 6798 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6799 } 6800 6801 if (test_and_clear_bit 6802 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6803 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6804 bool do_reset = true; 6805 6806 switch (base_vha->qlini_mode) { 6807 case QLA2XXX_INI_MODE_ENABLED: 6808 break; 6809 case QLA2XXX_INI_MODE_DISABLED: 6810 if (!qla_tgt_mode_enabled(base_vha) && 6811 !ha->flags.fw_started) 6812 do_reset = false; 6813 break; 6814 case QLA2XXX_INI_MODE_DUAL: 6815 if (!qla_dual_mode_enabled(base_vha) && 6816 !ha->flags.fw_started) 6817 do_reset = false; 6818 break; 6819 default: 6820 break; 6821 } 6822 6823 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6824 &base_vha->dpc_flags))) { 6825 base_vha->flags.online = 1; 6826 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6827 "ISP abort scheduled.\n"); 6828 if (ha->isp_ops->abort_isp(base_vha)) { 6829 /* failed. retry later */ 6830 set_bit(ISP_ABORT_NEEDED, 6831 &base_vha->dpc_flags); 6832 } 6833 clear_bit(ABORT_ISP_ACTIVE, 6834 &base_vha->dpc_flags); 6835 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6836 "ISP abort end.\n"); 6837 } 6838 } 6839 6840 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6841 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6842 qla24xx_process_purex_list 6843 (&base_vha->purex_list); 6844 clear_bit(PROCESS_PUREX_IOCB, 6845 &base_vha->dpc_flags); 6846 } 6847 } 6848 6849 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6850 &base_vha->dpc_flags)) { 6851 qla2x00_update_fcports(base_vha); 6852 } 6853 6854 if (IS_QLAFX00(ha)) 6855 goto loop_resync_check; 6856 6857 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6858 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6859 "Quiescence mode scheduled.\n"); 6860 if (IS_P3P_TYPE(ha)) { 6861 if (IS_QLA82XX(ha)) 6862 qla82xx_device_state_handler(base_vha); 6863 if (IS_QLA8044(ha)) 6864 qla8044_device_state_handler(base_vha); 6865 clear_bit(ISP_QUIESCE_NEEDED, 6866 &base_vha->dpc_flags); 6867 if (!ha->flags.quiesce_owner) { 6868 qla2x00_perform_loop_resync(base_vha); 6869 if (IS_QLA82XX(ha)) { 6870 qla82xx_idc_lock(ha); 6871 qla82xx_clear_qsnt_ready( 6872 base_vha); 6873 qla82xx_idc_unlock(ha); 6874 } else if (IS_QLA8044(ha)) { 6875 qla8044_idc_lock(ha); 6876 qla8044_clear_qsnt_ready( 6877 base_vha); 6878 qla8044_idc_unlock(ha); 6879 } 6880 } 6881 } else { 6882 clear_bit(ISP_QUIESCE_NEEDED, 6883 &base_vha->dpc_flags); 6884 qla2x00_quiesce_io(base_vha); 6885 } 6886 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6887 "Quiescence mode end.\n"); 6888 } 6889 6890 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6891 &base_vha->dpc_flags) && 6892 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6893 6894 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6895 "Reset marker scheduled.\n"); 6896 qla2x00_rst_aen(base_vha); 6897 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6898 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6899 "Reset marker end.\n"); 6900 } 6901 6902 /* Retry each device up to login retry count */ 6903 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6904 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6905 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6906 6907 if (!base_vha->relogin_jif || 6908 time_after_eq(jiffies, base_vha->relogin_jif)) { 6909 base_vha->relogin_jif = jiffies + HZ; 6910 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6911 6912 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6913 "Relogin scheduled.\n"); 6914 qla24xx_post_relogin_work(base_vha); 6915 } 6916 } 6917 loop_resync_check: 6918 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6919 &base_vha->dpc_flags)) { 6920 6921 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6922 "Loop resync scheduled.\n"); 6923 6924 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6925 &base_vha->dpc_flags))) { 6926 6927 qla2x00_loop_resync(base_vha); 6928 6929 clear_bit(LOOP_RESYNC_ACTIVE, 6930 &base_vha->dpc_flags); 6931 } 6932 6933 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6934 "Loop resync end.\n"); 6935 } 6936 6937 if (IS_QLAFX00(ha)) 6938 goto intr_on_check; 6939 6940 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6941 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6942 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6943 qla2xxx_flash_npiv_conf(base_vha); 6944 } 6945 6946 intr_on_check: 6947 if (!ha->interrupts_on) 6948 ha->isp_ops->enable_intrs(ha); 6949 6950 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6951 &base_vha->dpc_flags)) { 6952 if (ha->beacon_blink_led == 1) 6953 ha->isp_ops->beacon_blink(base_vha); 6954 } 6955 6956 /* qpair online check */ 6957 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6958 &base_vha->dpc_flags)) { 6959 if (ha->flags.eeh_busy || 6960 ha->flags.pci_channel_io_perm_failure) 6961 online = 0; 6962 else 6963 online = 1; 6964 6965 mutex_lock(&ha->mq_lock); 6966 list_for_each_entry(qpair, &base_vha->qp_list, 6967 qp_list_elem) 6968 qpair->online = online; 6969 mutex_unlock(&ha->mq_lock); 6970 } 6971 6972 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6973 &base_vha->dpc_flags)) { 6974 ql_log(ql_log_info, base_vha, 0xffffff, 6975 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6976 ha->nvme_last_rptd_aen); 6977 if (qla27xx_set_zio_threshold(base_vha, 6978 ha->nvme_last_rptd_aen)) { 6979 ql_log(ql_log_info, base_vha, 0xffffff, 6980 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6981 ha->nvme_last_rptd_aen); 6982 } 6983 } 6984 6985 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6986 &base_vha->dpc_flags)) { 6987 ql_log(ql_log_info, base_vha, 0xffffff, 6988 "SET ZIO Activity exchange threshold to %d.\n", 6989 ha->last_zio_threshold); 6990 qla27xx_set_zio_threshold(base_vha, 6991 ha->last_zio_threshold); 6992 } 6993 6994 if (!IS_QLAFX00(ha)) 6995 qla2x00_do_dpc_all_vps(base_vha); 6996 6997 if (test_and_clear_bit(N2N_LINK_RESET, 6998 &base_vha->dpc_flags)) { 6999 qla2x00_lip_reset(base_vha); 7000 } 7001 7002 ha->dpc_active = 0; 7003 end_loop: 7004 set_current_state(TASK_INTERRUPTIBLE); 7005 } /* End of while(1) */ 7006 __set_current_state(TASK_RUNNING); 7007 7008 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7009 "DPC handler exiting.\n"); 7010 7011 /* 7012 * Make sure that nobody tries to wake us up again. 7013 */ 7014 ha->dpc_active = 0; 7015 7016 /* Cleanup any residual CTX SRBs. */ 7017 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7018 7019 return 0; 7020 } 7021 7022 void 7023 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7024 { 7025 struct qla_hw_data *ha = vha->hw; 7026 struct task_struct *t = ha->dpc_thread; 7027 7028 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7029 wake_up_process(t); 7030 } 7031 7032 /* 7033 * qla2x00_rst_aen 7034 * Processes asynchronous reset. 7035 * 7036 * Input: 7037 * ha = adapter block pointer. 7038 */ 7039 static void 7040 qla2x00_rst_aen(scsi_qla_host_t *vha) 7041 { 7042 if (vha->flags.online && !vha->flags.reset_active && 7043 !atomic_read(&vha->loop_down_timer) && 7044 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7045 do { 7046 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7047 7048 /* 7049 * Issue marker command only when we are going to start 7050 * the I/O. 7051 */ 7052 vha->marker_needed = 1; 7053 } while (!atomic_read(&vha->loop_down_timer) && 7054 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7055 } 7056 } 7057 7058 /************************************************************************** 7059 * qla2x00_timer 7060 * 7061 * Description: 7062 * One second timer 7063 * 7064 * Context: Interrupt 7065 ***************************************************************************/ 7066 void 7067 qla2x00_timer(struct timer_list *t) 7068 { 7069 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7070 unsigned long cpu_flags = 0; 7071 int start_dpc = 0; 7072 int index; 7073 srb_t *sp; 7074 uint16_t w; 7075 struct qla_hw_data *ha = vha->hw; 7076 struct req_que *req; 7077 unsigned long flags; 7078 fc_port_t *fcport = NULL; 7079 7080 if (ha->flags.eeh_busy) { 7081 ql_dbg(ql_dbg_timer, vha, 0x6000, 7082 "EEH = %d, restarting timer.\n", 7083 ha->flags.eeh_busy); 7084 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7085 return; 7086 } 7087 7088 /* 7089 * Hardware read to raise pending EEH errors during mailbox waits. If 7090 * the read returns -1 then disable the board. 7091 */ 7092 if (!pci_channel_offline(ha->pdev)) { 7093 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7094 qla2x00_check_reg16_for_disconnect(vha, w); 7095 } 7096 7097 /* Make sure qla82xx_watchdog is run only for physical port */ 7098 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7099 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7100 start_dpc++; 7101 if (IS_QLA82XX(ha)) 7102 qla82xx_watchdog(vha); 7103 else if (IS_QLA8044(ha)) 7104 qla8044_watchdog(vha); 7105 } 7106 7107 if (!vha->vp_idx && IS_QLAFX00(ha)) 7108 qlafx00_timer_routine(vha); 7109 7110 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7111 vha->link_down_time++; 7112 7113 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7114 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7115 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7116 fcport->tgt_link_down_time++; 7117 } 7118 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7119 7120 /* Loop down handler. */ 7121 if (atomic_read(&vha->loop_down_timer) > 0 && 7122 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7123 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7124 && vha->flags.online) { 7125 7126 if (atomic_read(&vha->loop_down_timer) == 7127 vha->loop_down_abort_time) { 7128 7129 ql_log(ql_log_info, vha, 0x6008, 7130 "Loop down - aborting the queues before time expires.\n"); 7131 7132 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7133 atomic_set(&vha->loop_state, LOOP_DEAD); 7134 7135 /* 7136 * Schedule an ISP abort to return any FCP2-device 7137 * commands. 7138 */ 7139 /* NPIV - scan physical port only */ 7140 if (!vha->vp_idx) { 7141 spin_lock_irqsave(&ha->hardware_lock, 7142 cpu_flags); 7143 req = ha->req_q_map[0]; 7144 for (index = 1; 7145 index < req->num_outstanding_cmds; 7146 index++) { 7147 fc_port_t *sfcp; 7148 7149 sp = req->outstanding_cmds[index]; 7150 if (!sp) 7151 continue; 7152 if (sp->cmd_type != TYPE_SRB) 7153 continue; 7154 if (sp->type != SRB_SCSI_CMD) 7155 continue; 7156 sfcp = sp->fcport; 7157 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7158 continue; 7159 7160 if (IS_QLA82XX(ha)) 7161 set_bit(FCOE_CTX_RESET_NEEDED, 7162 &vha->dpc_flags); 7163 else 7164 set_bit(ISP_ABORT_NEEDED, 7165 &vha->dpc_flags); 7166 break; 7167 } 7168 spin_unlock_irqrestore(&ha->hardware_lock, 7169 cpu_flags); 7170 } 7171 start_dpc++; 7172 } 7173 7174 /* if the loop has been down for 4 minutes, reinit adapter */ 7175 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7176 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7177 ql_log(ql_log_warn, vha, 0x6009, 7178 "Loop down - aborting ISP.\n"); 7179 7180 if (IS_QLA82XX(ha)) 7181 set_bit(FCOE_CTX_RESET_NEEDED, 7182 &vha->dpc_flags); 7183 else 7184 set_bit(ISP_ABORT_NEEDED, 7185 &vha->dpc_flags); 7186 } 7187 } 7188 ql_dbg(ql_dbg_timer, vha, 0x600a, 7189 "Loop down - seconds remaining %d.\n", 7190 atomic_read(&vha->loop_down_timer)); 7191 } 7192 /* Check if beacon LED needs to be blinked for physical host only */ 7193 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7194 /* There is no beacon_blink function for ISP82xx */ 7195 if (!IS_P3P_TYPE(ha)) { 7196 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7197 start_dpc++; 7198 } 7199 } 7200 7201 /* Process any deferred work. */ 7202 if (!list_empty(&vha->work_list)) { 7203 unsigned long flags; 7204 bool q = false; 7205 7206 spin_lock_irqsave(&vha->work_lock, flags); 7207 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7208 q = true; 7209 spin_unlock_irqrestore(&vha->work_lock, flags); 7210 if (q) 7211 queue_work(vha->hw->wq, &vha->iocb_work); 7212 } 7213 7214 /* 7215 * FC-NVME 7216 * see if the active AEN count has changed from what was last reported. 7217 */ 7218 index = atomic_read(&ha->nvme_active_aen_cnt); 7219 if (!vha->vp_idx && 7220 (index != ha->nvme_last_rptd_aen) && 7221 (index >= DEFAULT_ZIO_THRESHOLD) && 7222 ha->zio_mode == QLA_ZIO_MODE_6 && 7223 !ha->flags.host_shutting_down) { 7224 ql_log(ql_log_info, vha, 0x3002, 7225 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7226 ha->nvme_last_rptd_aen); 7227 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7228 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7229 start_dpc++; 7230 } 7231 7232 if (!vha->vp_idx && 7233 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7234 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7235 ql_log(ql_log_info, vha, 0x3002, 7236 "Sched: Set ZIO exchange threshold to %d.\n", 7237 ha->last_zio_threshold); 7238 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7239 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7240 start_dpc++; 7241 } 7242 7243 /* Schedule the DPC routine if needed */ 7244 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7245 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7246 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7247 start_dpc || 7248 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7249 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7250 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7251 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7252 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7253 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7254 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7255 ql_dbg(ql_dbg_timer, vha, 0x600b, 7256 "isp_abort_needed=%d loop_resync_needed=%d " 7257 "fcport_update_needed=%d start_dpc=%d " 7258 "reset_marker_needed=%d", 7259 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7260 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7261 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7262 start_dpc, 7263 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7264 ql_dbg(ql_dbg_timer, vha, 0x600c, 7265 "beacon_blink_needed=%d isp_unrecoverable=%d " 7266 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7267 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7268 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7269 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7270 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7271 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7272 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7273 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7274 qla2xxx_wake_dpc(vha); 7275 } 7276 7277 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7278 } 7279 7280 /* Firmware interface routines. */ 7281 7282 #define FW_ISP21XX 0 7283 #define FW_ISP22XX 1 7284 #define FW_ISP2300 2 7285 #define FW_ISP2322 3 7286 #define FW_ISP24XX 4 7287 #define FW_ISP25XX 5 7288 #define FW_ISP81XX 6 7289 #define FW_ISP82XX 7 7290 #define FW_ISP2031 8 7291 #define FW_ISP8031 9 7292 #define FW_ISP27XX 10 7293 #define FW_ISP28XX 11 7294 7295 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7296 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7297 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7298 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7299 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7300 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7301 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7302 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7303 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7304 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7305 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7306 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7307 7308 7309 static DEFINE_MUTEX(qla_fw_lock); 7310 7311 static struct fw_blob qla_fw_blobs[] = { 7312 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7313 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7314 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7315 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7316 { .name = FW_FILE_ISP24XX, }, 7317 { .name = FW_FILE_ISP25XX, }, 7318 { .name = FW_FILE_ISP81XX, }, 7319 { .name = FW_FILE_ISP82XX, }, 7320 { .name = FW_FILE_ISP2031, }, 7321 { .name = FW_FILE_ISP8031, }, 7322 { .name = FW_FILE_ISP27XX, }, 7323 { .name = FW_FILE_ISP28XX, }, 7324 { .name = NULL, }, 7325 }; 7326 7327 struct fw_blob * 7328 qla2x00_request_firmware(scsi_qla_host_t *vha) 7329 { 7330 struct qla_hw_data *ha = vha->hw; 7331 struct fw_blob *blob; 7332 7333 if (IS_QLA2100(ha)) { 7334 blob = &qla_fw_blobs[FW_ISP21XX]; 7335 } else if (IS_QLA2200(ha)) { 7336 blob = &qla_fw_blobs[FW_ISP22XX]; 7337 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7338 blob = &qla_fw_blobs[FW_ISP2300]; 7339 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7340 blob = &qla_fw_blobs[FW_ISP2322]; 7341 } else if (IS_QLA24XX_TYPE(ha)) { 7342 blob = &qla_fw_blobs[FW_ISP24XX]; 7343 } else if (IS_QLA25XX(ha)) { 7344 blob = &qla_fw_blobs[FW_ISP25XX]; 7345 } else if (IS_QLA81XX(ha)) { 7346 blob = &qla_fw_blobs[FW_ISP81XX]; 7347 } else if (IS_QLA82XX(ha)) { 7348 blob = &qla_fw_blobs[FW_ISP82XX]; 7349 } else if (IS_QLA2031(ha)) { 7350 blob = &qla_fw_blobs[FW_ISP2031]; 7351 } else if (IS_QLA8031(ha)) { 7352 blob = &qla_fw_blobs[FW_ISP8031]; 7353 } else if (IS_QLA27XX(ha)) { 7354 blob = &qla_fw_blobs[FW_ISP27XX]; 7355 } else if (IS_QLA28XX(ha)) { 7356 blob = &qla_fw_blobs[FW_ISP28XX]; 7357 } else { 7358 return NULL; 7359 } 7360 7361 if (!blob->name) 7362 return NULL; 7363 7364 mutex_lock(&qla_fw_lock); 7365 if (blob->fw) 7366 goto out; 7367 7368 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7369 ql_log(ql_log_warn, vha, 0x0063, 7370 "Failed to load firmware image (%s).\n", blob->name); 7371 blob->fw = NULL; 7372 blob = NULL; 7373 } 7374 7375 out: 7376 mutex_unlock(&qla_fw_lock); 7377 return blob; 7378 } 7379 7380 static void 7381 qla2x00_release_firmware(void) 7382 { 7383 struct fw_blob *blob; 7384 7385 mutex_lock(&qla_fw_lock); 7386 for (blob = qla_fw_blobs; blob->name; blob++) 7387 release_firmware(blob->fw); 7388 mutex_unlock(&qla_fw_lock); 7389 } 7390 7391 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7392 { 7393 struct qla_hw_data *ha = vha->hw; 7394 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7395 struct qla_qpair *qpair = NULL; 7396 struct scsi_qla_host *vp; 7397 fc_port_t *fcport; 7398 int i; 7399 unsigned long flags; 7400 7401 ha->chip_reset++; 7402 7403 ha->base_qpair->chip_reset = ha->chip_reset; 7404 for (i = 0; i < ha->max_qpairs; i++) { 7405 if (ha->queue_pair_map[i]) 7406 ha->queue_pair_map[i]->chip_reset = 7407 ha->base_qpair->chip_reset; 7408 } 7409 7410 /* purge MBox commands */ 7411 if (atomic_read(&ha->num_pend_mbx_stage3)) { 7412 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 7413 complete(&ha->mbx_intr_comp); 7414 } 7415 7416 i = 0; 7417 7418 while (atomic_read(&ha->num_pend_mbx_stage3) || 7419 atomic_read(&ha->num_pend_mbx_stage2) || 7420 atomic_read(&ha->num_pend_mbx_stage1)) { 7421 msleep(20); 7422 i++; 7423 if (i > 50) 7424 break; 7425 } 7426 7427 ha->flags.purge_mbox = 0; 7428 7429 mutex_lock(&ha->mq_lock); 7430 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7431 qpair->online = 0; 7432 mutex_unlock(&ha->mq_lock); 7433 7434 qla2x00_mark_all_devices_lost(vha); 7435 7436 spin_lock_irqsave(&ha->vport_slock, flags); 7437 list_for_each_entry(vp, &ha->vp_list, list) { 7438 atomic_inc(&vp->vref_count); 7439 spin_unlock_irqrestore(&ha->vport_slock, flags); 7440 qla2x00_mark_all_devices_lost(vp); 7441 spin_lock_irqsave(&ha->vport_slock, flags); 7442 atomic_dec(&vp->vref_count); 7443 } 7444 spin_unlock_irqrestore(&ha->vport_slock, flags); 7445 7446 /* Clear all async request states across all VPs. */ 7447 list_for_each_entry(fcport, &vha->vp_fcports, list) 7448 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7449 7450 spin_lock_irqsave(&ha->vport_slock, flags); 7451 list_for_each_entry(vp, &ha->vp_list, list) { 7452 atomic_inc(&vp->vref_count); 7453 spin_unlock_irqrestore(&ha->vport_slock, flags); 7454 list_for_each_entry(fcport, &vp->vp_fcports, list) 7455 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7456 spin_lock_irqsave(&ha->vport_slock, flags); 7457 atomic_dec(&vp->vref_count); 7458 } 7459 spin_unlock_irqrestore(&ha->vport_slock, flags); 7460 } 7461 7462 7463 static pci_ers_result_t 7464 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7465 { 7466 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7467 struct qla_hw_data *ha = vha->hw; 7468 7469 ql_dbg(ql_dbg_aer, vha, 0x9000, 7470 "PCI error detected, state %x.\n", state); 7471 7472 if (!atomic_read(&pdev->enable_cnt)) { 7473 ql_log(ql_log_info, vha, 0xffff, 7474 "PCI device is disabled,state %x\n", state); 7475 return PCI_ERS_RESULT_NEED_RESET; 7476 } 7477 7478 switch (state) { 7479 case pci_channel_io_normal: 7480 ha->flags.eeh_busy = 0; 7481 if (ql2xmqsupport || ql2xnvmeenable) { 7482 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7483 qla2xxx_wake_dpc(vha); 7484 } 7485 return PCI_ERS_RESULT_CAN_RECOVER; 7486 case pci_channel_io_frozen: 7487 ha->flags.eeh_busy = 1; 7488 qla_pci_error_cleanup(vha); 7489 return PCI_ERS_RESULT_NEED_RESET; 7490 case pci_channel_io_perm_failure: 7491 ha->flags.pci_channel_io_perm_failure = 1; 7492 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7493 if (ql2xmqsupport || ql2xnvmeenable) { 7494 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7495 qla2xxx_wake_dpc(vha); 7496 } 7497 return PCI_ERS_RESULT_DISCONNECT; 7498 } 7499 return PCI_ERS_RESULT_NEED_RESET; 7500 } 7501 7502 static pci_ers_result_t 7503 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7504 { 7505 int risc_paused = 0; 7506 uint32_t stat; 7507 unsigned long flags; 7508 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7509 struct qla_hw_data *ha = base_vha->hw; 7510 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7511 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7512 7513 if (IS_QLA82XX(ha)) 7514 return PCI_ERS_RESULT_RECOVERED; 7515 7516 spin_lock_irqsave(&ha->hardware_lock, flags); 7517 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7518 stat = rd_reg_word(®->hccr); 7519 if (stat & HCCR_RISC_PAUSE) 7520 risc_paused = 1; 7521 } else if (IS_QLA23XX(ha)) { 7522 stat = rd_reg_dword(®->u.isp2300.host_status); 7523 if (stat & HSR_RISC_PAUSED) 7524 risc_paused = 1; 7525 } else if (IS_FWI2_CAPABLE(ha)) { 7526 stat = rd_reg_dword(®24->host_status); 7527 if (stat & HSRX_RISC_PAUSED) 7528 risc_paused = 1; 7529 } 7530 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7531 7532 if (risc_paused) { 7533 ql_log(ql_log_info, base_vha, 0x9003, 7534 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7535 qla2xxx_dump_fw(base_vha); 7536 7537 return PCI_ERS_RESULT_NEED_RESET; 7538 } else 7539 return PCI_ERS_RESULT_RECOVERED; 7540 } 7541 7542 static pci_ers_result_t 7543 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7544 { 7545 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7546 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7547 struct qla_hw_data *ha = base_vha->hw; 7548 int rc; 7549 struct qla_qpair *qpair = NULL; 7550 7551 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 7552 "Slot Reset.\n"); 7553 7554 /* Workaround: qla2xxx driver which access hardware earlier 7555 * needs error state to be pci_channel_io_online. 7556 * Otherwise mailbox command timesout. 7557 */ 7558 pdev->error_state = pci_channel_io_normal; 7559 7560 pci_restore_state(pdev); 7561 7562 /* pci_restore_state() clears the saved_state flag of the device 7563 * save restored state which resets saved_state flag 7564 */ 7565 pci_save_state(pdev); 7566 7567 if (ha->mem_only) 7568 rc = pci_enable_device_mem(pdev); 7569 else 7570 rc = pci_enable_device(pdev); 7571 7572 if (rc) { 7573 ql_log(ql_log_warn, base_vha, 0x9005, 7574 "Can't re-enable PCI device after reset.\n"); 7575 goto exit_slot_reset; 7576 } 7577 7578 7579 if (ha->isp_ops->pci_config(base_vha)) 7580 goto exit_slot_reset; 7581 7582 mutex_lock(&ha->mq_lock); 7583 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7584 qpair->online = 1; 7585 mutex_unlock(&ha->mq_lock); 7586 7587 base_vha->flags.online = 1; 7588 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7589 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7590 ret = PCI_ERS_RESULT_RECOVERED; 7591 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7592 7593 7594 exit_slot_reset: 7595 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7596 "slot_reset return %x.\n", ret); 7597 7598 return ret; 7599 } 7600 7601 static void 7602 qla2xxx_pci_resume(struct pci_dev *pdev) 7603 { 7604 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7605 struct qla_hw_data *ha = base_vha->hw; 7606 int ret; 7607 7608 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7609 "pci_resume.\n"); 7610 7611 ha->flags.eeh_busy = 0; 7612 7613 ret = qla2x00_wait_for_hba_online(base_vha); 7614 if (ret != QLA_SUCCESS) { 7615 ql_log(ql_log_fatal, base_vha, 0x9002, 7616 "The device failed to resume I/O from slot/link_reset.\n"); 7617 } 7618 } 7619 7620 static void 7621 qla_pci_reset_prepare(struct pci_dev *pdev) 7622 { 7623 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7624 struct qla_hw_data *ha = base_vha->hw; 7625 struct qla_qpair *qpair; 7626 7627 ql_log(ql_log_warn, base_vha, 0xffff, 7628 "%s.\n", __func__); 7629 7630 /* 7631 * PCI FLR/function reset is about to reset the 7632 * slot. Stop the chip to stop all DMA access. 7633 * It is assumed that pci_reset_done will be called 7634 * after FLR to resume Chip operation. 7635 */ 7636 ha->flags.eeh_busy = 1; 7637 mutex_lock(&ha->mq_lock); 7638 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7639 qpair->online = 0; 7640 mutex_unlock(&ha->mq_lock); 7641 7642 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7643 qla2x00_abort_isp_cleanup(base_vha); 7644 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7645 } 7646 7647 static void 7648 qla_pci_reset_done(struct pci_dev *pdev) 7649 { 7650 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7651 struct qla_hw_data *ha = base_vha->hw; 7652 struct qla_qpair *qpair; 7653 7654 ql_log(ql_log_warn, base_vha, 0xffff, 7655 "%s.\n", __func__); 7656 7657 /* 7658 * FLR just completed by PCI layer. Resume adapter 7659 */ 7660 ha->flags.eeh_busy = 0; 7661 mutex_lock(&ha->mq_lock); 7662 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7663 qpair->online = 1; 7664 mutex_unlock(&ha->mq_lock); 7665 7666 base_vha->flags.online = 1; 7667 ha->isp_ops->abort_isp(base_vha); 7668 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7669 } 7670 7671 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7672 { 7673 int rc; 7674 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7675 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7676 7677 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7678 rc = blk_mq_map_queues(qmap); 7679 else 7680 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7681 return rc; 7682 } 7683 7684 struct scsi_host_template qla2xxx_driver_template = { 7685 .module = THIS_MODULE, 7686 .name = QLA2XXX_DRIVER_NAME, 7687 .queuecommand = qla2xxx_queuecommand, 7688 7689 .eh_timed_out = fc_eh_timed_out, 7690 .eh_abort_handler = qla2xxx_eh_abort, 7691 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7692 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7693 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7694 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7695 7696 .slave_configure = qla2xxx_slave_configure, 7697 7698 .slave_alloc = qla2xxx_slave_alloc, 7699 .slave_destroy = qla2xxx_slave_destroy, 7700 .scan_finished = qla2xxx_scan_finished, 7701 .scan_start = qla2xxx_scan_start, 7702 .change_queue_depth = scsi_change_queue_depth, 7703 .map_queues = qla2xxx_map_queues, 7704 .this_id = -1, 7705 .cmd_per_lun = 3, 7706 .sg_tablesize = SG_ALL, 7707 7708 .max_sectors = 0xFFFF, 7709 .shost_attrs = qla2x00_host_attrs, 7710 7711 .supported_mode = MODE_INITIATOR, 7712 .track_queue_depth = 1, 7713 .cmd_size = sizeof(srb_t), 7714 }; 7715 7716 static const struct pci_error_handlers qla2xxx_err_handler = { 7717 .error_detected = qla2xxx_pci_error_detected, 7718 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7719 .slot_reset = qla2xxx_pci_slot_reset, 7720 .resume = qla2xxx_pci_resume, 7721 .reset_prepare = qla_pci_reset_prepare, 7722 .reset_done = qla_pci_reset_done, 7723 }; 7724 7725 static struct pci_device_id qla2xxx_pci_tbl[] = { 7726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7731 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7732 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7733 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7734 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7735 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7736 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7737 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7738 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7739 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7740 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7741 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7742 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7743 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7744 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7745 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7746 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7747 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7748 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7749 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7750 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7751 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7752 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7753 { 0 }, 7754 }; 7755 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7756 7757 static struct pci_driver qla2xxx_pci_driver = { 7758 .name = QLA2XXX_DRIVER_NAME, 7759 .driver = { 7760 .owner = THIS_MODULE, 7761 }, 7762 .id_table = qla2xxx_pci_tbl, 7763 .probe = qla2x00_probe_one, 7764 .remove = qla2x00_remove_one, 7765 .shutdown = qla2x00_shutdown, 7766 .err_handler = &qla2xxx_err_handler, 7767 }; 7768 7769 static const struct file_operations apidev_fops = { 7770 .owner = THIS_MODULE, 7771 .llseek = noop_llseek, 7772 }; 7773 7774 /** 7775 * qla2x00_module_init - Module initialization. 7776 **/ 7777 static int __init 7778 qla2x00_module_init(void) 7779 { 7780 int ret = 0; 7781 7782 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 7783 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7784 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7785 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7786 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7787 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 7788 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7789 BUILD_BUG_ON(sizeof(request_t) != 64); 7790 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 7791 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 7792 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 7793 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7794 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 7795 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7796 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7797 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7798 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7799 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7800 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7801 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7802 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344); 7803 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 7804 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 7805 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 7806 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 7807 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 7808 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7809 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 7810 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 7811 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 7812 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 7813 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 7814 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7815 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 7816 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7817 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 7818 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7819 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7820 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 7821 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 7822 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 7823 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 7824 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 7825 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 7826 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7827 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 7828 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 7829 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 7830 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 7831 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 7832 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 7833 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 7834 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 7835 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 7836 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 7837 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 7838 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 7839 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 7840 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 7841 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 7842 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 7843 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 7844 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 7845 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 7846 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 7847 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 7848 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 7849 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 7850 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7851 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 7852 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 7853 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 7854 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7855 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 7856 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7857 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 7858 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 7859 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 7860 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 7861 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 7862 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 7863 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 7864 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 7865 BUILD_BUG_ON(sizeof(target_id_t) != 2); 7866 7867 /* Allocate cache for SRBs. */ 7868 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7869 SLAB_HWCACHE_ALIGN, NULL); 7870 if (srb_cachep == NULL) { 7871 ql_log(ql_log_fatal, NULL, 0x0001, 7872 "Unable to allocate SRB cache...Failing load!.\n"); 7873 return -ENOMEM; 7874 } 7875 7876 /* Initialize target kmem_cache and mem_pools */ 7877 ret = qlt_init(); 7878 if (ret < 0) { 7879 goto destroy_cache; 7880 } else if (ret > 0) { 7881 /* 7882 * If initiator mode is explictly disabled by qlt_init(), 7883 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7884 * performing scsi_scan_target() during LOOP UP event. 7885 */ 7886 qla2xxx_transport_functions.disable_target_scan = 1; 7887 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7888 } 7889 7890 /* Derive version string. */ 7891 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7892 if (ql2xextended_error_logging) 7893 strcat(qla2x00_version_str, "-debug"); 7894 if (ql2xextended_error_logging == 1) 7895 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7896 7897 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7898 qla_insert_tgt_attrs(); 7899 7900 qla2xxx_transport_template = 7901 fc_attach_transport(&qla2xxx_transport_functions); 7902 if (!qla2xxx_transport_template) { 7903 ql_log(ql_log_fatal, NULL, 0x0002, 7904 "fc_attach_transport failed...Failing load!.\n"); 7905 ret = -ENODEV; 7906 goto qlt_exit; 7907 } 7908 7909 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7910 if (apidev_major < 0) { 7911 ql_log(ql_log_fatal, NULL, 0x0003, 7912 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7913 } 7914 7915 qla2xxx_transport_vport_template = 7916 fc_attach_transport(&qla2xxx_transport_vport_functions); 7917 if (!qla2xxx_transport_vport_template) { 7918 ql_log(ql_log_fatal, NULL, 0x0004, 7919 "fc_attach_transport vport failed...Failing load!.\n"); 7920 ret = -ENODEV; 7921 goto unreg_chrdev; 7922 } 7923 ql_log(ql_log_info, NULL, 0x0005, 7924 "QLogic Fibre Channel HBA Driver: %s.\n", 7925 qla2x00_version_str); 7926 ret = pci_register_driver(&qla2xxx_pci_driver); 7927 if (ret) { 7928 ql_log(ql_log_fatal, NULL, 0x0006, 7929 "pci_register_driver failed...ret=%d Failing load!.\n", 7930 ret); 7931 goto release_vport_transport; 7932 } 7933 return ret; 7934 7935 release_vport_transport: 7936 fc_release_transport(qla2xxx_transport_vport_template); 7937 7938 unreg_chrdev: 7939 if (apidev_major >= 0) 7940 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7941 fc_release_transport(qla2xxx_transport_template); 7942 7943 qlt_exit: 7944 qlt_exit(); 7945 7946 destroy_cache: 7947 kmem_cache_destroy(srb_cachep); 7948 return ret; 7949 } 7950 7951 /** 7952 * qla2x00_module_exit - Module cleanup. 7953 **/ 7954 static void __exit 7955 qla2x00_module_exit(void) 7956 { 7957 pci_unregister_driver(&qla2xxx_pci_driver); 7958 qla2x00_release_firmware(); 7959 kmem_cache_destroy(ctx_cachep); 7960 fc_release_transport(qla2xxx_transport_vport_template); 7961 if (apidev_major >= 0) 7962 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7963 fc_release_transport(qla2xxx_transport_template); 7964 qlt_exit(); 7965 kmem_cache_destroy(srb_cachep); 7966 } 7967 7968 module_init(qla2x00_module_init); 7969 module_exit(qla2x00_module_exit); 7970 7971 MODULE_AUTHOR("QLogic Corporation"); 7972 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7973 MODULE_LICENSE("GPL"); 7974 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7975 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7976 MODULE_FIRMWARE(FW_FILE_ISP2300); 7977 MODULE_FIRMWARE(FW_FILE_ISP2322); 7978 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7979 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7980