1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 /* 23 * Driver version 24 */ 25 char qla2x00_version_str[40]; 26 27 static int apidev_major; 28 29 /* 30 * SRB allocation cache 31 */ 32 static struct kmem_cache *srb_cachep; 33 34 /* 35 * CT6 CTX allocation cache 36 */ 37 static struct kmem_cache *ctx_cachep; 38 /* 39 * error level for logging 40 */ 41 int ql_errlev = ql_log_all; 42 43 int ql2xlogintimeout = 20; 44 module_param(ql2xlogintimeout, int, S_IRUGO); 45 MODULE_PARM_DESC(ql2xlogintimeout, 46 "Login timeout value in seconds."); 47 48 int qlport_down_retry; 49 module_param(qlport_down_retry, int, S_IRUGO); 50 MODULE_PARM_DESC(qlport_down_retry, 51 "Maximum number of command retries to a port that returns " 52 "a PORT-DOWN status."); 53 54 int ql2xplogiabsentdevice; 55 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 56 MODULE_PARM_DESC(ql2xplogiabsentdevice, 57 "Option to enable PLOGI to devices that are not present after " 58 "a Fabric scan. This is needed for several broken switches. " 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 60 61 int ql2xloginretrycount = 0; 62 module_param(ql2xloginretrycount, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xloginretrycount, 64 "Specify an alternate value for the NVRAM login retry count."); 65 66 int ql2xallocfwdump = 1; 67 module_param(ql2xallocfwdump, int, S_IRUGO); 68 MODULE_PARM_DESC(ql2xallocfwdump, 69 "Option to enable allocation of memory for a firmware dump " 70 "during HBA initialization. Memory allocation requirements " 71 "vary by ISP type. Default is 1 - allocate memory."); 72 73 int ql2xextended_error_logging; 74 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 75 MODULE_PARM_DESC(ql2xextended_error_logging, 76 "Option to enable extended error logging,\n" 77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 86 "\t\t0x1e400000 - Preferred value for capturing essential " 87 "debug information (equivalent to old " 88 "ql2xextended_error_logging=1).\n" 89 "\t\tDo LOGICAL OR of the value to enable more than one level"); 90 91 int ql2xshiftctondsd = 6; 92 module_param(ql2xshiftctondsd, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xshiftctondsd, 94 "Set to control shifting of command type processing " 95 "based on total number of SG elements."); 96 97 static void qla2x00_free_device(scsi_qla_host_t *); 98 99 int ql2xfdmienable=1; 100 module_param(ql2xfdmienable, int, S_IRUGO); 101 MODULE_PARM_DESC(ql2xfdmienable, 102 "Enables FDMI registrations. " 103 "0 - no FDMI. Default is 1 - perform FDMI."); 104 105 #define MAX_Q_DEPTH 32 106 static int ql2xmaxqdepth = MAX_Q_DEPTH; 107 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 108 MODULE_PARM_DESC(ql2xmaxqdepth, 109 "Maximum queue depth to report for target devices."); 110 111 /* Do not change the value of this after module load */ 112 int ql2xenabledif = 0; 113 module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xenabledif, 115 " Enable T10-CRC-DIF " 116 " Default is 0 - No DIF Support. 1 - Enable it" 117 ", 2 - Enable DIF for all types, except Type 0."); 118 119 int ql2xenablehba_err_chk = 2; 120 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xenablehba_err_chk, 122 " Enable T10-CRC-DIF Error isolation by HBA:\n" 123 " Default is 1.\n" 124 " 0 -- Error isolation disabled\n" 125 " 1 -- Error isolation enabled only for DIX Type 0\n" 126 " 2 -- Error isolation enabled for all Types\n"); 127 128 int ql2xiidmaenable=1; 129 module_param(ql2xiidmaenable, int, S_IRUGO); 130 MODULE_PARM_DESC(ql2xiidmaenable, 131 "Enables iIDMA settings " 132 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 133 134 int ql2xmaxqueues = 1; 135 module_param(ql2xmaxqueues, int, S_IRUGO); 136 MODULE_PARM_DESC(ql2xmaxqueues, 137 "Enables MQ settings " 138 "Default is 1 for single queue. Set it to number " 139 "of queues in MQ mode."); 140 141 int ql2xmultique_tag; 142 module_param(ql2xmultique_tag, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xmultique_tag, 144 "Enables CPU affinity settings for the driver " 145 "Default is 0 for no affinity of request and response IO. " 146 "Set it to 1 to turn on the cpu affinity."); 147 148 int ql2xfwloadbin; 149 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xfwloadbin, 151 "Option to specify location from which to load ISP firmware:.\n" 152 " 2 -- load firmware via the request_firmware() (hotplug).\n" 153 " interface.\n" 154 " 1 -- load firmware from flash.\n" 155 " 0 -- use default semantics.\n"); 156 157 int ql2xetsenable; 158 module_param(ql2xetsenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xetsenable, 160 "Enables firmware ETS burst." 161 "Default is 0 - skip ETS enablement."); 162 163 int ql2xdbwr = 1; 164 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 165 MODULE_PARM_DESC(ql2xdbwr, 166 "Option to specify scheme for request queue posting.\n" 167 " 0 -- Regular doorbell.\n" 168 " 1 -- CAMRAM doorbell (faster).\n"); 169 170 int ql2xtargetreset = 1; 171 module_param(ql2xtargetreset, int, S_IRUGO); 172 MODULE_PARM_DESC(ql2xtargetreset, 173 "Enable target reset." 174 "Default is 1 - use hw defaults."); 175 176 int ql2xgffidenable; 177 module_param(ql2xgffidenable, int, S_IRUGO); 178 MODULE_PARM_DESC(ql2xgffidenable, 179 "Enables GFF_ID checks of port type. " 180 "Default is 0 - Do not use GFF_ID information."); 181 182 int ql2xasynctmfenable; 183 module_param(ql2xasynctmfenable, int, S_IRUGO); 184 MODULE_PARM_DESC(ql2xasynctmfenable, 185 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 186 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 187 188 int ql2xdontresethba; 189 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 190 MODULE_PARM_DESC(ql2xdontresethba, 191 "Option to specify reset behaviour.\n" 192 " 0 (Default) -- Reset on failure.\n" 193 " 1 -- Do not reset on failure.\n"); 194 195 uint ql2xmaxlun = MAX_LUNS; 196 module_param(ql2xmaxlun, uint, S_IRUGO); 197 MODULE_PARM_DESC(ql2xmaxlun, 198 "Defines the maximum LU number to register with the SCSI " 199 "midlayer. Default is 65535."); 200 201 int ql2xmdcapmask = 0x1F; 202 module_param(ql2xmdcapmask, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xmdcapmask, 204 "Set the Minidump driver capture mask level. " 205 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 206 207 int ql2xmdenable = 1; 208 module_param(ql2xmdenable, int, S_IRUGO); 209 MODULE_PARM_DESC(ql2xmdenable, 210 "Enable/disable MiniDump. " 211 "0 - MiniDump disabled. " 212 "1 (Default) - MiniDump enabled."); 213 214 /* 215 * SCSI host template entry points 216 */ 217 static int qla2xxx_slave_configure(struct scsi_device * device); 218 static int qla2xxx_slave_alloc(struct scsi_device *); 219 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 220 static void qla2xxx_scan_start(struct Scsi_Host *); 221 static void qla2xxx_slave_destroy(struct scsi_device *); 222 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 223 static int qla2xxx_eh_abort(struct scsi_cmnd *); 224 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 225 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 226 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 227 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 228 229 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 230 static int qla2x00_change_queue_type(struct scsi_device *, int); 231 232 struct scsi_host_template qla2xxx_driver_template = { 233 .module = THIS_MODULE, 234 .name = QLA2XXX_DRIVER_NAME, 235 .queuecommand = qla2xxx_queuecommand, 236 237 .eh_abort_handler = qla2xxx_eh_abort, 238 .eh_device_reset_handler = qla2xxx_eh_device_reset, 239 .eh_target_reset_handler = qla2xxx_eh_target_reset, 240 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 241 .eh_host_reset_handler = qla2xxx_eh_host_reset, 242 243 .slave_configure = qla2xxx_slave_configure, 244 245 .slave_alloc = qla2xxx_slave_alloc, 246 .slave_destroy = qla2xxx_slave_destroy, 247 .scan_finished = qla2xxx_scan_finished, 248 .scan_start = qla2xxx_scan_start, 249 .change_queue_depth = qla2x00_change_queue_depth, 250 .change_queue_type = qla2x00_change_queue_type, 251 .this_id = -1, 252 .cmd_per_lun = 3, 253 .use_clustering = ENABLE_CLUSTERING, 254 .sg_tablesize = SG_ALL, 255 256 .max_sectors = 0xFFFF, 257 .shost_attrs = qla2x00_host_attrs, 258 }; 259 260 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 261 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 262 263 /* TODO Convert to inlines 264 * 265 * Timer routines 266 */ 267 268 __inline__ void 269 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 270 { 271 init_timer(&vha->timer); 272 vha->timer.expires = jiffies + interval * HZ; 273 vha->timer.data = (unsigned long)vha; 274 vha->timer.function = (void (*)(unsigned long))func; 275 add_timer(&vha->timer); 276 vha->timer_active = 1; 277 } 278 279 static inline void 280 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 281 { 282 /* Currently used for 82XX only. */ 283 if (vha->device_flags & DFLG_DEV_FAILED) { 284 ql_dbg(ql_dbg_timer, vha, 0x600d, 285 "Device in a failed state, returning.\n"); 286 return; 287 } 288 289 mod_timer(&vha->timer, jiffies + interval * HZ); 290 } 291 292 static __inline__ void 293 qla2x00_stop_timer(scsi_qla_host_t *vha) 294 { 295 del_timer_sync(&vha->timer); 296 vha->timer_active = 0; 297 } 298 299 static int qla2x00_do_dpc(void *data); 300 301 static void qla2x00_rst_aen(scsi_qla_host_t *); 302 303 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 304 struct req_que **, struct rsp_que **); 305 static void qla2x00_free_fw_dump(struct qla_hw_data *); 306 static void qla2x00_mem_free(struct qla_hw_data *); 307 308 /* -------------------------------------------------------------------------- */ 309 static int qla2x00_alloc_queues(struct qla_hw_data *ha) 310 { 311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 312 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 313 GFP_KERNEL); 314 if (!ha->req_q_map) { 315 ql_log(ql_log_fatal, vha, 0x003b, 316 "Unable to allocate memory for request queue ptrs.\n"); 317 goto fail_req_map; 318 } 319 320 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 321 GFP_KERNEL); 322 if (!ha->rsp_q_map) { 323 ql_log(ql_log_fatal, vha, 0x003c, 324 "Unable to allocate memory for response queue ptrs.\n"); 325 goto fail_rsp_map; 326 } 327 set_bit(0, ha->rsp_qid_map); 328 set_bit(0, ha->req_qid_map); 329 return 1; 330 331 fail_rsp_map: 332 kfree(ha->req_q_map); 333 ha->req_q_map = NULL; 334 fail_req_map: 335 return -ENOMEM; 336 } 337 338 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 339 { 340 if (req && req->ring) 341 dma_free_coherent(&ha->pdev->dev, 342 (req->length + 1) * sizeof(request_t), 343 req->ring, req->dma); 344 345 kfree(req); 346 req = NULL; 347 } 348 349 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 350 { 351 if (rsp && rsp->ring) 352 dma_free_coherent(&ha->pdev->dev, 353 (rsp->length + 1) * sizeof(response_t), 354 rsp->ring, rsp->dma); 355 356 kfree(rsp); 357 rsp = NULL; 358 } 359 360 static void qla2x00_free_queues(struct qla_hw_data *ha) 361 { 362 struct req_que *req; 363 struct rsp_que *rsp; 364 int cnt; 365 366 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 367 req = ha->req_q_map[cnt]; 368 qla2x00_free_req_que(ha, req); 369 } 370 kfree(ha->req_q_map); 371 ha->req_q_map = NULL; 372 373 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 374 rsp = ha->rsp_q_map[cnt]; 375 qla2x00_free_rsp_que(ha, rsp); 376 } 377 kfree(ha->rsp_q_map); 378 ha->rsp_q_map = NULL; 379 } 380 381 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 382 { 383 uint16_t options = 0; 384 int ques, req, ret; 385 struct qla_hw_data *ha = vha->hw; 386 387 if (!(ha->fw_attributes & BIT_6)) { 388 ql_log(ql_log_warn, vha, 0x00d8, 389 "Firmware is not multi-queue capable.\n"); 390 goto fail; 391 } 392 if (ql2xmultique_tag) { 393 /* create a request queue for IO */ 394 options |= BIT_7; 395 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 396 QLA_DEFAULT_QUE_QOS); 397 if (!req) { 398 ql_log(ql_log_warn, vha, 0x00e0, 399 "Failed to create request queue.\n"); 400 goto fail; 401 } 402 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 403 vha->req = ha->req_q_map[req]; 404 options |= BIT_1; 405 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 406 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 407 if (!ret) { 408 ql_log(ql_log_warn, vha, 0x00e8, 409 "Failed to create response queue.\n"); 410 goto fail2; 411 } 412 } 413 ha->flags.cpu_affinity_enabled = 1; 414 ql_dbg(ql_dbg_multiq, vha, 0xc007, 415 "CPU affinity mode enalbed, " 416 "no. of response queues:%d no. of request queues:%d.\n", 417 ha->max_rsp_queues, ha->max_req_queues); 418 ql_dbg(ql_dbg_init, vha, 0x00e9, 419 "CPU affinity mode enalbed, " 420 "no. of response queues:%d no. of request queues:%d.\n", 421 ha->max_rsp_queues, ha->max_req_queues); 422 } 423 return 0; 424 fail2: 425 qla25xx_delete_queues(vha); 426 destroy_workqueue(ha->wq); 427 ha->wq = NULL; 428 vha->req = ha->req_q_map[0]; 429 fail: 430 ha->mqenable = 0; 431 kfree(ha->req_q_map); 432 kfree(ha->rsp_q_map); 433 ha->max_req_queues = ha->max_rsp_queues = 1; 434 return 1; 435 } 436 437 static char * 438 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 439 { 440 struct qla_hw_data *ha = vha->hw; 441 static char *pci_bus_modes[] = { 442 "33", "66", "100", "133", 443 }; 444 uint16_t pci_bus; 445 446 strcpy(str, "PCI"); 447 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 448 if (pci_bus) { 449 strcat(str, "-X ("); 450 strcat(str, pci_bus_modes[pci_bus]); 451 } else { 452 pci_bus = (ha->pci_attr & BIT_8) >> 8; 453 strcat(str, " ("); 454 strcat(str, pci_bus_modes[pci_bus]); 455 } 456 strcat(str, " MHz)"); 457 458 return (str); 459 } 460 461 static char * 462 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 463 { 464 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 465 struct qla_hw_data *ha = vha->hw; 466 uint32_t pci_bus; 467 int pcie_reg; 468 469 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 470 if (pcie_reg) { 471 char lwstr[6]; 472 uint16_t pcie_lstat, lspeed, lwidth; 473 474 pcie_reg += 0x12; 475 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); 476 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); 477 lwidth = (pcie_lstat & 478 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; 479 480 strcpy(str, "PCIe ("); 481 if (lspeed == 1) 482 strcat(str, "2.5GT/s "); 483 else if (lspeed == 2) 484 strcat(str, "5.0GT/s "); 485 else 486 strcat(str, "<unknown> "); 487 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 488 strcat(str, lwstr); 489 490 return str; 491 } 492 493 strcpy(str, "PCI"); 494 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 495 if (pci_bus == 0 || pci_bus == 8) { 496 strcat(str, " ("); 497 strcat(str, pci_bus_modes[pci_bus >> 3]); 498 } else { 499 strcat(str, "-X "); 500 if (pci_bus & BIT_2) 501 strcat(str, "Mode 2"); 502 else 503 strcat(str, "Mode 1"); 504 strcat(str, " ("); 505 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 506 } 507 strcat(str, " MHz)"); 508 509 return str; 510 } 511 512 static char * 513 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 514 { 515 char un_str[10]; 516 struct qla_hw_data *ha = vha->hw; 517 518 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 519 ha->fw_minor_version, 520 ha->fw_subminor_version); 521 522 if (ha->fw_attributes & BIT_9) { 523 strcat(str, "FLX"); 524 return (str); 525 } 526 527 switch (ha->fw_attributes & 0xFF) { 528 case 0x7: 529 strcat(str, "EF"); 530 break; 531 case 0x17: 532 strcat(str, "TP"); 533 break; 534 case 0x37: 535 strcat(str, "IP"); 536 break; 537 case 0x77: 538 strcat(str, "VI"); 539 break; 540 default: 541 sprintf(un_str, "(%x)", ha->fw_attributes); 542 strcat(str, un_str); 543 break; 544 } 545 if (ha->fw_attributes & 0x100) 546 strcat(str, "X"); 547 548 return (str); 549 } 550 551 static char * 552 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 553 { 554 struct qla_hw_data *ha = vha->hw; 555 556 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 557 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 558 return str; 559 } 560 561 void 562 qla2x00_sp_free_dma(void *vha, void *ptr) 563 { 564 srb_t *sp = (srb_t *)ptr; 565 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 566 struct qla_hw_data *ha = sp->fcport->vha->hw; 567 void *ctx = GET_CMD_CTX_SP(sp); 568 569 if (sp->flags & SRB_DMA_VALID) { 570 scsi_dma_unmap(cmd); 571 sp->flags &= ~SRB_DMA_VALID; 572 } 573 574 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 575 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 576 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 577 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 578 } 579 580 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 581 /* List assured to be having elements */ 582 qla2x00_clean_dsd_pool(ha, sp); 583 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 584 } 585 586 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 587 dma_pool_free(ha->dl_dma_pool, ctx, 588 ((struct crc_context *)ctx)->crc_ctx_dma); 589 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 590 } 591 592 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 593 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 594 595 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 596 ctx1->fcp_cmnd_dma); 597 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 598 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 599 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 600 mempool_free(ctx1, ha->ctx_mempool); 601 ctx1 = NULL; 602 } 603 604 CMD_SP(cmd) = NULL; 605 mempool_free(sp, ha->srb_mempool); 606 } 607 608 static void 609 qla2x00_sp_compl(void *data, void *ptr, int res) 610 { 611 struct qla_hw_data *ha = (struct qla_hw_data *)data; 612 srb_t *sp = (srb_t *)ptr; 613 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 614 615 cmd->result = res; 616 617 if (atomic_read(&sp->ref_count) == 0) { 618 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 619 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 620 sp, GET_CMD_SP(sp)); 621 if (ql2xextended_error_logging & ql_dbg_io) 622 BUG(); 623 return; 624 } 625 if (!atomic_dec_and_test(&sp->ref_count)) 626 return; 627 628 qla2x00_sp_free_dma(ha, sp); 629 cmd->scsi_done(cmd); 630 } 631 632 static int 633 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 634 { 635 scsi_qla_host_t *vha = shost_priv(host); 636 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 637 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 638 struct qla_hw_data *ha = vha->hw; 639 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 640 srb_t *sp; 641 int rval; 642 643 if (ha->flags.eeh_busy) { 644 if (ha->flags.pci_channel_io_perm_failure) { 645 ql_dbg(ql_dbg_io, vha, 0x3001, 646 "PCI Channel IO permanent failure, exiting " 647 "cmd=%p.\n", cmd); 648 cmd->result = DID_NO_CONNECT << 16; 649 } else { 650 ql_dbg(ql_dbg_io, vha, 0x3002, 651 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 652 cmd->result = DID_REQUEUE << 16; 653 } 654 goto qc24_fail_command; 655 } 656 657 rval = fc_remote_port_chkready(rport); 658 if (rval) { 659 cmd->result = rval; 660 ql_dbg(ql_dbg_io, vha, 0x3003, 661 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 662 cmd, rval); 663 goto qc24_fail_command; 664 } 665 666 if (!vha->flags.difdix_supported && 667 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 668 ql_dbg(ql_dbg_io, vha, 0x3004, 669 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 670 cmd); 671 cmd->result = DID_NO_CONNECT << 16; 672 goto qc24_fail_command; 673 } 674 675 if (!fcport) { 676 cmd->result = DID_NO_CONNECT << 16; 677 goto qc24_fail_command; 678 } 679 680 if (atomic_read(&fcport->state) != FCS_ONLINE) { 681 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 682 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 683 ql_dbg(ql_dbg_io, vha, 0x3005, 684 "Returning DNC, fcport_state=%d loop_state=%d.\n", 685 atomic_read(&fcport->state), 686 atomic_read(&base_vha->loop_state)); 687 cmd->result = DID_NO_CONNECT << 16; 688 goto qc24_fail_command; 689 } 690 goto qc24_target_busy; 691 } 692 693 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC); 694 if (!sp) 695 goto qc24_host_busy; 696 697 sp->u.scmd.cmd = cmd; 698 sp->type = SRB_SCSI_CMD; 699 atomic_set(&sp->ref_count, 1); 700 CMD_SP(cmd) = (void *)sp; 701 sp->free = qla2x00_sp_free_dma; 702 sp->done = qla2x00_sp_compl; 703 704 rval = ha->isp_ops->start_scsi(sp); 705 if (rval != QLA_SUCCESS) { 706 ql_dbg(ql_dbg_io, vha, 0x3013, 707 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 708 goto qc24_host_busy_free_sp; 709 } 710 711 return 0; 712 713 qc24_host_busy_free_sp: 714 qla2x00_sp_free_dma(ha, sp); 715 716 qc24_host_busy: 717 return SCSI_MLQUEUE_HOST_BUSY; 718 719 qc24_target_busy: 720 return SCSI_MLQUEUE_TARGET_BUSY; 721 722 qc24_fail_command: 723 cmd->scsi_done(cmd); 724 725 return 0; 726 } 727 728 /* 729 * qla2x00_eh_wait_on_command 730 * Waits for the command to be returned by the Firmware for some 731 * max time. 732 * 733 * Input: 734 * cmd = Scsi Command to wait on. 735 * 736 * Return: 737 * Not Found : 0 738 * Found : 1 739 */ 740 static int 741 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 742 { 743 #define ABORT_POLLING_PERIOD 1000 744 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 745 unsigned long wait_iter = ABORT_WAIT_ITER; 746 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 747 struct qla_hw_data *ha = vha->hw; 748 int ret = QLA_SUCCESS; 749 750 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 751 ql_dbg(ql_dbg_taskm, vha, 0x8005, 752 "Return:eh_wait.\n"); 753 return ret; 754 } 755 756 while (CMD_SP(cmd) && wait_iter--) { 757 msleep(ABORT_POLLING_PERIOD); 758 } 759 if (CMD_SP(cmd)) 760 ret = QLA_FUNCTION_FAILED; 761 762 return ret; 763 } 764 765 /* 766 * qla2x00_wait_for_hba_online 767 * Wait till the HBA is online after going through 768 * <= MAX_RETRIES_OF_ISP_ABORT or 769 * finally HBA is disabled ie marked offline 770 * 771 * Input: 772 * ha - pointer to host adapter structure 773 * 774 * Note: 775 * Does context switching-Release SPIN_LOCK 776 * (if any) before calling this routine. 777 * 778 * Return: 779 * Success (Adapter is online) : 0 780 * Failed (Adapter is offline/disabled) : 1 781 */ 782 int 783 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 784 { 785 int return_status; 786 unsigned long wait_online; 787 struct qla_hw_data *ha = vha->hw; 788 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 789 790 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 791 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 792 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 793 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 794 ha->dpc_active) && time_before(jiffies, wait_online)) { 795 796 msleep(1000); 797 } 798 if (base_vha->flags.online) 799 return_status = QLA_SUCCESS; 800 else 801 return_status = QLA_FUNCTION_FAILED; 802 803 return (return_status); 804 } 805 806 /* 807 * qla2x00_wait_for_reset_ready 808 * Wait till the HBA is online after going through 809 * <= MAX_RETRIES_OF_ISP_ABORT or 810 * finally HBA is disabled ie marked offline or flash 811 * operations are in progress. 812 * 813 * Input: 814 * ha - pointer to host adapter structure 815 * 816 * Note: 817 * Does context switching-Release SPIN_LOCK 818 * (if any) before calling this routine. 819 * 820 * Return: 821 * Success (Adapter is online/no flash ops) : 0 822 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 823 */ 824 static int 825 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 826 { 827 int return_status; 828 unsigned long wait_online; 829 struct qla_hw_data *ha = vha->hw; 830 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 831 832 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 833 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 834 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 835 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 836 ha->optrom_state != QLA_SWAITING || 837 ha->dpc_active) && time_before(jiffies, wait_online)) 838 msleep(1000); 839 840 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 841 return_status = QLA_SUCCESS; 842 else 843 return_status = QLA_FUNCTION_FAILED; 844 845 ql_dbg(ql_dbg_taskm, vha, 0x8019, 846 "%s return status=%d.\n", __func__, return_status); 847 848 return return_status; 849 } 850 851 int 852 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 853 { 854 int return_status; 855 unsigned long wait_reset; 856 struct qla_hw_data *ha = vha->hw; 857 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 858 859 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 860 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 861 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 862 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 863 ha->dpc_active) && time_before(jiffies, wait_reset)) { 864 865 msleep(1000); 866 867 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 868 ha->flags.chip_reset_done) 869 break; 870 } 871 if (ha->flags.chip_reset_done) 872 return_status = QLA_SUCCESS; 873 else 874 return_status = QLA_FUNCTION_FAILED; 875 876 return return_status; 877 } 878 879 static void 880 sp_get(struct srb *sp) 881 { 882 atomic_inc(&sp->ref_count); 883 } 884 885 /************************************************************************** 886 * qla2xxx_eh_abort 887 * 888 * Description: 889 * The abort function will abort the specified command. 890 * 891 * Input: 892 * cmd = Linux SCSI command packet to be aborted. 893 * 894 * Returns: 895 * Either SUCCESS or FAILED. 896 * 897 * Note: 898 * Only return FAILED if command not returned by firmware. 899 **************************************************************************/ 900 static int 901 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 902 { 903 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 904 srb_t *sp; 905 int ret; 906 unsigned int id, lun; 907 unsigned long flags; 908 int wait = 0; 909 struct qla_hw_data *ha = vha->hw; 910 911 if (!CMD_SP(cmd)) 912 return SUCCESS; 913 914 ret = fc_block_scsi_eh(cmd); 915 if (ret != 0) 916 return ret; 917 ret = SUCCESS; 918 919 id = cmd->device->id; 920 lun = cmd->device->lun; 921 922 spin_lock_irqsave(&ha->hardware_lock, flags); 923 sp = (srb_t *) CMD_SP(cmd); 924 if (!sp) { 925 spin_unlock_irqrestore(&ha->hardware_lock, flags); 926 return SUCCESS; 927 } 928 929 ql_dbg(ql_dbg_taskm, vha, 0x8002, 930 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", 931 vha->host_no, id, lun, sp, cmd); 932 933 /* Get a reference to the sp and drop the lock.*/ 934 sp_get(sp); 935 936 spin_unlock_irqrestore(&ha->hardware_lock, flags); 937 if (ha->isp_ops->abort_command(sp)) { 938 ret = FAILED; 939 ql_dbg(ql_dbg_taskm, vha, 0x8003, 940 "Abort command mbx failed cmd=%p.\n", cmd); 941 } else { 942 ql_dbg(ql_dbg_taskm, vha, 0x8004, 943 "Abort command mbx success cmd=%p.\n", cmd); 944 wait = 1; 945 } 946 947 spin_lock_irqsave(&ha->hardware_lock, flags); 948 sp->done(ha, sp, 0); 949 spin_unlock_irqrestore(&ha->hardware_lock, flags); 950 951 /* Did the command return during mailbox execution? */ 952 if (ret == FAILED && !CMD_SP(cmd)) 953 ret = SUCCESS; 954 955 /* Wait for the command to be returned. */ 956 if (wait) { 957 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 958 ql_log(ql_log_warn, vha, 0x8006, 959 "Abort handler timed out cmd=%p.\n", cmd); 960 ret = FAILED; 961 } 962 } 963 964 ql_log(ql_log_info, vha, 0x801c, 965 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", 966 vha->host_no, id, lun, wait, ret); 967 968 return ret; 969 } 970 971 int 972 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 973 unsigned int l, enum nexus_wait_type type) 974 { 975 int cnt, match, status; 976 unsigned long flags; 977 struct qla_hw_data *ha = vha->hw; 978 struct req_que *req; 979 srb_t *sp; 980 struct scsi_cmnd *cmd; 981 982 status = QLA_SUCCESS; 983 984 spin_lock_irqsave(&ha->hardware_lock, flags); 985 req = vha->req; 986 for (cnt = 1; status == QLA_SUCCESS && 987 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 988 sp = req->outstanding_cmds[cnt]; 989 if (!sp) 990 continue; 991 if (sp->type != SRB_SCSI_CMD) 992 continue; 993 if (vha->vp_idx != sp->fcport->vha->vp_idx) 994 continue; 995 match = 0; 996 cmd = GET_CMD_SP(sp); 997 switch (type) { 998 case WAIT_HOST: 999 match = 1; 1000 break; 1001 case WAIT_TARGET: 1002 match = cmd->device->id == t; 1003 break; 1004 case WAIT_LUN: 1005 match = (cmd->device->id == t && 1006 cmd->device->lun == l); 1007 break; 1008 } 1009 if (!match) 1010 continue; 1011 1012 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1013 status = qla2x00_eh_wait_on_command(cmd); 1014 spin_lock_irqsave(&ha->hardware_lock, flags); 1015 } 1016 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1017 1018 return status; 1019 } 1020 1021 static char *reset_errors[] = { 1022 "HBA not online", 1023 "HBA not ready", 1024 "Task management failed", 1025 "Waiting for command completions", 1026 }; 1027 1028 static int 1029 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1030 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 1031 { 1032 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1033 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1034 int err; 1035 1036 if (!fcport) { 1037 return FAILED; 1038 } 1039 1040 err = fc_block_scsi_eh(cmd); 1041 if (err != 0) 1042 return err; 1043 1044 ql_log(ql_log_info, vha, 0x8009, 1045 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, 1046 cmd->device->id, cmd->device->lun, cmd); 1047 1048 err = 0; 1049 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1050 ql_log(ql_log_warn, vha, 0x800a, 1051 "Wait for hba online failed for cmd=%p.\n", cmd); 1052 goto eh_reset_failed; 1053 } 1054 err = 2; 1055 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1056 != QLA_SUCCESS) { 1057 ql_log(ql_log_warn, vha, 0x800c, 1058 "do_reset failed for cmd=%p.\n", cmd); 1059 goto eh_reset_failed; 1060 } 1061 err = 3; 1062 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1063 cmd->device->lun, type) != QLA_SUCCESS) { 1064 ql_log(ql_log_warn, vha, 0x800d, 1065 "wait for peding cmds failed for cmd=%p.\n", cmd); 1066 goto eh_reset_failed; 1067 } 1068 1069 ql_log(ql_log_info, vha, 0x800e, 1070 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, 1071 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1072 1073 return SUCCESS; 1074 1075 eh_reset_failed: 1076 ql_log(ql_log_info, vha, 0x800f, 1077 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, 1078 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1079 cmd); 1080 return FAILED; 1081 } 1082 1083 static int 1084 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1085 { 1086 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1087 struct qla_hw_data *ha = vha->hw; 1088 1089 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1090 ha->isp_ops->lun_reset); 1091 } 1092 1093 static int 1094 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1095 { 1096 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1097 struct qla_hw_data *ha = vha->hw; 1098 1099 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1100 ha->isp_ops->target_reset); 1101 } 1102 1103 /************************************************************************** 1104 * qla2xxx_eh_bus_reset 1105 * 1106 * Description: 1107 * The bus reset function will reset the bus and abort any executing 1108 * commands. 1109 * 1110 * Input: 1111 * cmd = Linux SCSI command packet of the command that cause the 1112 * bus reset. 1113 * 1114 * Returns: 1115 * SUCCESS/FAILURE (defined as macro in scsi.h). 1116 * 1117 **************************************************************************/ 1118 static int 1119 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1120 { 1121 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1122 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1123 int ret = FAILED; 1124 unsigned int id, lun; 1125 1126 id = cmd->device->id; 1127 lun = cmd->device->lun; 1128 1129 if (!fcport) { 1130 return ret; 1131 } 1132 1133 ret = fc_block_scsi_eh(cmd); 1134 if (ret != 0) 1135 return ret; 1136 ret = FAILED; 1137 1138 ql_log(ql_log_info, vha, 0x8012, 1139 "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun); 1140 1141 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1142 ql_log(ql_log_fatal, vha, 0x8013, 1143 "Wait for hba online failed board disabled.\n"); 1144 goto eh_bus_reset_done; 1145 } 1146 1147 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1148 ret = SUCCESS; 1149 1150 if (ret == FAILED) 1151 goto eh_bus_reset_done; 1152 1153 /* Flush outstanding commands. */ 1154 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1155 QLA_SUCCESS) { 1156 ql_log(ql_log_warn, vha, 0x8014, 1157 "Wait for pending commands failed.\n"); 1158 ret = FAILED; 1159 } 1160 1161 eh_bus_reset_done: 1162 ql_log(ql_log_warn, vha, 0x802b, 1163 "BUS RESET %s nexus=%ld:%d:%d.\n", 1164 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun); 1165 1166 return ret; 1167 } 1168 1169 /************************************************************************** 1170 * qla2xxx_eh_host_reset 1171 * 1172 * Description: 1173 * The reset function will reset the Adapter. 1174 * 1175 * Input: 1176 * cmd = Linux SCSI command packet of the command that cause the 1177 * adapter reset. 1178 * 1179 * Returns: 1180 * Either SUCCESS or FAILED. 1181 * 1182 * Note: 1183 **************************************************************************/ 1184 static int 1185 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1186 { 1187 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1188 struct qla_hw_data *ha = vha->hw; 1189 int ret = FAILED; 1190 unsigned int id, lun; 1191 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1192 1193 id = cmd->device->id; 1194 lun = cmd->device->lun; 1195 1196 ql_log(ql_log_info, vha, 0x8018, 1197 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1198 1199 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1200 goto eh_host_reset_lock; 1201 1202 if (vha != base_vha) { 1203 if (qla2x00_vp_abort_isp(vha)) 1204 goto eh_host_reset_lock; 1205 } else { 1206 if (IS_QLA82XX(vha->hw)) { 1207 if (!qla82xx_fcoe_ctx_reset(vha)) { 1208 /* Ctx reset success */ 1209 ret = SUCCESS; 1210 goto eh_host_reset_lock; 1211 } 1212 /* fall thru if ctx reset failed */ 1213 } 1214 if (ha->wq) 1215 flush_workqueue(ha->wq); 1216 1217 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1218 if (ha->isp_ops->abort_isp(base_vha)) { 1219 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1220 /* failed. schedule dpc to try */ 1221 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1222 1223 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1224 ql_log(ql_log_warn, vha, 0x802a, 1225 "wait for hba online failed.\n"); 1226 goto eh_host_reset_lock; 1227 } 1228 } 1229 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1230 } 1231 1232 /* Waiting for command to be returned to OS.*/ 1233 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1234 QLA_SUCCESS) 1235 ret = SUCCESS; 1236 1237 eh_host_reset_lock: 1238 ql_log(ql_log_info, vha, 0x8017, 1239 "ADAPTER RESET %s nexus=%ld:%d:%d.\n", 1240 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1241 1242 return ret; 1243 } 1244 1245 /* 1246 * qla2x00_loop_reset 1247 * Issue loop reset. 1248 * 1249 * Input: 1250 * ha = adapter block pointer. 1251 * 1252 * Returns: 1253 * 0 = success 1254 */ 1255 int 1256 qla2x00_loop_reset(scsi_qla_host_t *vha) 1257 { 1258 int ret; 1259 struct fc_port *fcport; 1260 struct qla_hw_data *ha = vha->hw; 1261 1262 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1263 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1264 if (fcport->port_type != FCT_TARGET) 1265 continue; 1266 1267 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1268 if (ret != QLA_SUCCESS) { 1269 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1270 "Bus Reset failed: Target Reset=%d " 1271 "d_id=%x.\n", ret, fcport->d_id.b24); 1272 } 1273 } 1274 } 1275 1276 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1277 ret = qla2x00_full_login_lip(vha); 1278 if (ret != QLA_SUCCESS) { 1279 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1280 "full_login_lip=%d.\n", ret); 1281 } 1282 atomic_set(&vha->loop_state, LOOP_DOWN); 1283 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1284 qla2x00_mark_all_devices_lost(vha, 0); 1285 } 1286 1287 if (ha->flags.enable_lip_reset) { 1288 ret = qla2x00_lip_reset(vha); 1289 if (ret != QLA_SUCCESS) 1290 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1291 "lip_reset failed (%d).\n", ret); 1292 } 1293 1294 /* Issue marker command only when we are going to start the I/O */ 1295 vha->marker_needed = 1; 1296 1297 return QLA_SUCCESS; 1298 } 1299 1300 void 1301 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1302 { 1303 int que, cnt; 1304 unsigned long flags; 1305 srb_t *sp; 1306 struct qla_hw_data *ha = vha->hw; 1307 struct req_que *req; 1308 1309 spin_lock_irqsave(&ha->hardware_lock, flags); 1310 for (que = 0; que < ha->max_req_queues; que++) { 1311 req = ha->req_q_map[que]; 1312 if (!req) 1313 continue; 1314 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 1315 sp = req->outstanding_cmds[cnt]; 1316 if (sp) { 1317 req->outstanding_cmds[cnt] = NULL; 1318 sp->done(vha, sp, res); 1319 } 1320 } 1321 } 1322 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1323 } 1324 1325 static int 1326 qla2xxx_slave_alloc(struct scsi_device *sdev) 1327 { 1328 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1329 1330 if (!rport || fc_remote_port_chkready(rport)) 1331 return -ENXIO; 1332 1333 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1334 1335 return 0; 1336 } 1337 1338 static int 1339 qla2xxx_slave_configure(struct scsi_device *sdev) 1340 { 1341 scsi_qla_host_t *vha = shost_priv(sdev->host); 1342 struct req_que *req = vha->req; 1343 1344 if (sdev->tagged_supported) 1345 scsi_activate_tcq(sdev, req->max_q_depth); 1346 else 1347 scsi_deactivate_tcq(sdev, req->max_q_depth); 1348 return 0; 1349 } 1350 1351 static void 1352 qla2xxx_slave_destroy(struct scsi_device *sdev) 1353 { 1354 sdev->hostdata = NULL; 1355 } 1356 1357 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1358 { 1359 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1360 1361 if (!scsi_track_queue_full(sdev, qdepth)) 1362 return; 1363 1364 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1365 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", 1366 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1367 } 1368 1369 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1370 { 1371 fc_port_t *fcport = sdev->hostdata; 1372 struct scsi_qla_host *vha = fcport->vha; 1373 struct req_que *req = NULL; 1374 1375 req = vha->req; 1376 if (!req) 1377 return; 1378 1379 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1380 return; 1381 1382 if (sdev->ordered_tags) 1383 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1384 else 1385 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1386 1387 ql_dbg(ql_dbg_io, vha, 0x302a, 1388 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", 1389 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1390 } 1391 1392 static int 1393 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1394 { 1395 switch (reason) { 1396 case SCSI_QDEPTH_DEFAULT: 1397 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1398 break; 1399 case SCSI_QDEPTH_QFULL: 1400 qla2x00_handle_queue_full(sdev, qdepth); 1401 break; 1402 case SCSI_QDEPTH_RAMP_UP: 1403 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1404 break; 1405 default: 1406 return -EOPNOTSUPP; 1407 } 1408 1409 return sdev->queue_depth; 1410 } 1411 1412 static int 1413 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1414 { 1415 if (sdev->tagged_supported) { 1416 scsi_set_tag_type(sdev, tag_type); 1417 if (tag_type) 1418 scsi_activate_tcq(sdev, sdev->queue_depth); 1419 else 1420 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1421 } else 1422 tag_type = 0; 1423 1424 return tag_type; 1425 } 1426 1427 /** 1428 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1429 * @ha: HA context 1430 * 1431 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1432 * supported addressing method. 1433 */ 1434 static void 1435 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1436 { 1437 /* Assume a 32bit DMA mask. */ 1438 ha->flags.enable_64bit_addressing = 0; 1439 1440 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1441 /* Any upper-dword bits set? */ 1442 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1443 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1444 /* Ok, a 64bit DMA mask is applicable. */ 1445 ha->flags.enable_64bit_addressing = 1; 1446 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1447 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1448 return; 1449 } 1450 } 1451 1452 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1453 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1454 } 1455 1456 static void 1457 qla2x00_enable_intrs(struct qla_hw_data *ha) 1458 { 1459 unsigned long flags = 0; 1460 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1461 1462 spin_lock_irqsave(&ha->hardware_lock, flags); 1463 ha->interrupts_on = 1; 1464 /* enable risc and host interrupts */ 1465 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1466 RD_REG_WORD(®->ictrl); 1467 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1468 1469 } 1470 1471 static void 1472 qla2x00_disable_intrs(struct qla_hw_data *ha) 1473 { 1474 unsigned long flags = 0; 1475 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1476 1477 spin_lock_irqsave(&ha->hardware_lock, flags); 1478 ha->interrupts_on = 0; 1479 /* disable risc and host interrupts */ 1480 WRT_REG_WORD(®->ictrl, 0); 1481 RD_REG_WORD(®->ictrl); 1482 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1483 } 1484 1485 static void 1486 qla24xx_enable_intrs(struct qla_hw_data *ha) 1487 { 1488 unsigned long flags = 0; 1489 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1490 1491 spin_lock_irqsave(&ha->hardware_lock, flags); 1492 ha->interrupts_on = 1; 1493 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1494 RD_REG_DWORD(®->ictrl); 1495 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1496 } 1497 1498 static void 1499 qla24xx_disable_intrs(struct qla_hw_data *ha) 1500 { 1501 unsigned long flags = 0; 1502 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1503 1504 if (IS_NOPOLLING_TYPE(ha)) 1505 return; 1506 spin_lock_irqsave(&ha->hardware_lock, flags); 1507 ha->interrupts_on = 0; 1508 WRT_REG_DWORD(®->ictrl, 0); 1509 RD_REG_DWORD(®->ictrl); 1510 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1511 } 1512 1513 static int 1514 qla2x00_iospace_config(struct qla_hw_data *ha) 1515 { 1516 resource_size_t pio; 1517 uint16_t msix; 1518 int cpus; 1519 1520 if (pci_request_selected_regions(ha->pdev, ha->bars, 1521 QLA2XXX_DRIVER_NAME)) { 1522 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1523 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1524 pci_name(ha->pdev)); 1525 goto iospace_error_exit; 1526 } 1527 if (!(ha->bars & 1)) 1528 goto skip_pio; 1529 1530 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1531 pio = pci_resource_start(ha->pdev, 0); 1532 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1533 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1534 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1535 "Invalid pci I/O region size (%s).\n", 1536 pci_name(ha->pdev)); 1537 pio = 0; 1538 } 1539 } else { 1540 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1541 "Region #0 no a PIO resource (%s).\n", 1542 pci_name(ha->pdev)); 1543 pio = 0; 1544 } 1545 ha->pio_address = pio; 1546 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1547 "PIO address=%llu.\n", 1548 (unsigned long long)ha->pio_address); 1549 1550 skip_pio: 1551 /* Use MMIO operations for all accesses. */ 1552 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1553 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1554 "Region #1 not an MMIO resource (%s), aborting.\n", 1555 pci_name(ha->pdev)); 1556 goto iospace_error_exit; 1557 } 1558 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1560 "Invalid PCI mem region size (%s), aborting.\n", 1561 pci_name(ha->pdev)); 1562 goto iospace_error_exit; 1563 } 1564 1565 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1566 if (!ha->iobase) { 1567 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1568 "Cannot remap MMIO (%s), aborting.\n", 1569 pci_name(ha->pdev)); 1570 goto iospace_error_exit; 1571 } 1572 1573 /* Determine queue resources */ 1574 ha->max_req_queues = ha->max_rsp_queues = 1; 1575 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1576 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1577 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1578 goto mqiobase_exit; 1579 1580 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1581 pci_resource_len(ha->pdev, 3)); 1582 if (ha->mqiobase) { 1583 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1584 "MQIO Base=%p.\n", ha->mqiobase); 1585 /* Read MSIX vector size of the board */ 1586 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1587 ha->msix_count = msix; 1588 /* Max queues are bounded by available msix vectors */ 1589 /* queue 0 uses two msix vectors */ 1590 if (ql2xmultique_tag) { 1591 cpus = num_online_cpus(); 1592 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1593 (cpus + 1) : (ha->msix_count - 1); 1594 ha->max_req_queues = 2; 1595 } else if (ql2xmaxqueues > 1) { 1596 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1597 QLA_MQ_SIZE : ql2xmaxqueues; 1598 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1599 "QoS mode set, max no of request queues:%d.\n", 1600 ha->max_req_queues); 1601 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1602 "QoS mode set, max no of request queues:%d.\n", 1603 ha->max_req_queues); 1604 } 1605 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1606 "MSI-X vector count: %d.\n", msix); 1607 } else 1608 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1609 "BAR 3 not enabled.\n"); 1610 1611 mqiobase_exit: 1612 ha->msix_count = ha->max_rsp_queues + 1; 1613 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1614 "MSIX Count:%d.\n", ha->msix_count); 1615 return (0); 1616 1617 iospace_error_exit: 1618 return (-ENOMEM); 1619 } 1620 1621 1622 static int 1623 qla83xx_iospace_config(struct qla_hw_data *ha) 1624 { 1625 uint16_t msix; 1626 int cpus; 1627 1628 if (pci_request_selected_regions(ha->pdev, ha->bars, 1629 QLA2XXX_DRIVER_NAME)) { 1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1631 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1632 pci_name(ha->pdev)); 1633 1634 goto iospace_error_exit; 1635 } 1636 1637 /* Use MMIO operations for all accesses. */ 1638 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1639 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1640 "Invalid pci I/O region size (%s).\n", 1641 pci_name(ha->pdev)); 1642 goto iospace_error_exit; 1643 } 1644 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1645 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1646 "Invalid PCI mem region size (%s), aborting\n", 1647 pci_name(ha->pdev)); 1648 goto iospace_error_exit; 1649 } 1650 1651 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1652 if (!ha->iobase) { 1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1654 "Cannot remap MMIO (%s), aborting.\n", 1655 pci_name(ha->pdev)); 1656 goto iospace_error_exit; 1657 } 1658 1659 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1660 /* 83XX 26XX always use MQ type access for queues 1661 * - mbar 2, a.k.a region 4 */ 1662 ha->max_req_queues = ha->max_rsp_queues = 1; 1663 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1664 pci_resource_len(ha->pdev, 4)); 1665 1666 if (!ha->mqiobase) { 1667 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1668 "BAR2/region4 not enabled\n"); 1669 goto mqiobase_exit; 1670 } 1671 1672 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1673 pci_resource_len(ha->pdev, 2)); 1674 if (ha->msixbase) { 1675 /* Read MSIX vector size of the board */ 1676 pci_read_config_word(ha->pdev, 1677 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1678 ha->msix_count = msix; 1679 /* Max queues are bounded by available msix vectors */ 1680 /* queue 0 uses two msix vectors */ 1681 if (ql2xmultique_tag) { 1682 cpus = num_online_cpus(); 1683 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1684 (cpus + 1) : (ha->msix_count - 1); 1685 ha->max_req_queues = 2; 1686 } else if (ql2xmaxqueues > 1) { 1687 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1688 QLA_MQ_SIZE : ql2xmaxqueues; 1689 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1690 "QoS mode set, max no of request queues:%d.\n", 1691 ha->max_req_queues); 1692 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1693 "QoS mode set, max no of request queues:%d.\n", 1694 ha->max_req_queues); 1695 } 1696 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1697 "MSI-X vector count: %d.\n", msix); 1698 } else 1699 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1700 "BAR 1 not enabled.\n"); 1701 1702 mqiobase_exit: 1703 ha->msix_count = ha->max_rsp_queues + 1; 1704 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1705 "MSIX Count:%d.\n", ha->msix_count); 1706 return 0; 1707 1708 iospace_error_exit: 1709 return -ENOMEM; 1710 } 1711 1712 static struct isp_operations qla2100_isp_ops = { 1713 .pci_config = qla2100_pci_config, 1714 .reset_chip = qla2x00_reset_chip, 1715 .chip_diag = qla2x00_chip_diag, 1716 .config_rings = qla2x00_config_rings, 1717 .reset_adapter = qla2x00_reset_adapter, 1718 .nvram_config = qla2x00_nvram_config, 1719 .update_fw_options = qla2x00_update_fw_options, 1720 .load_risc = qla2x00_load_risc, 1721 .pci_info_str = qla2x00_pci_info_str, 1722 .fw_version_str = qla2x00_fw_version_str, 1723 .intr_handler = qla2100_intr_handler, 1724 .enable_intrs = qla2x00_enable_intrs, 1725 .disable_intrs = qla2x00_disable_intrs, 1726 .abort_command = qla2x00_abort_command, 1727 .target_reset = qla2x00_abort_target, 1728 .lun_reset = qla2x00_lun_reset, 1729 .fabric_login = qla2x00_login_fabric, 1730 .fabric_logout = qla2x00_fabric_logout, 1731 .calc_req_entries = qla2x00_calc_iocbs_32, 1732 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1733 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1734 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1735 .read_nvram = qla2x00_read_nvram_data, 1736 .write_nvram = qla2x00_write_nvram_data, 1737 .fw_dump = qla2100_fw_dump, 1738 .beacon_on = NULL, 1739 .beacon_off = NULL, 1740 .beacon_blink = NULL, 1741 .read_optrom = qla2x00_read_optrom_data, 1742 .write_optrom = qla2x00_write_optrom_data, 1743 .get_flash_version = qla2x00_get_flash_version, 1744 .start_scsi = qla2x00_start_scsi, 1745 .abort_isp = qla2x00_abort_isp, 1746 .iospace_config = qla2x00_iospace_config, 1747 }; 1748 1749 static struct isp_operations qla2300_isp_ops = { 1750 .pci_config = qla2300_pci_config, 1751 .reset_chip = qla2x00_reset_chip, 1752 .chip_diag = qla2x00_chip_diag, 1753 .config_rings = qla2x00_config_rings, 1754 .reset_adapter = qla2x00_reset_adapter, 1755 .nvram_config = qla2x00_nvram_config, 1756 .update_fw_options = qla2x00_update_fw_options, 1757 .load_risc = qla2x00_load_risc, 1758 .pci_info_str = qla2x00_pci_info_str, 1759 .fw_version_str = qla2x00_fw_version_str, 1760 .intr_handler = qla2300_intr_handler, 1761 .enable_intrs = qla2x00_enable_intrs, 1762 .disable_intrs = qla2x00_disable_intrs, 1763 .abort_command = qla2x00_abort_command, 1764 .target_reset = qla2x00_abort_target, 1765 .lun_reset = qla2x00_lun_reset, 1766 .fabric_login = qla2x00_login_fabric, 1767 .fabric_logout = qla2x00_fabric_logout, 1768 .calc_req_entries = qla2x00_calc_iocbs_32, 1769 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1770 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1771 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1772 .read_nvram = qla2x00_read_nvram_data, 1773 .write_nvram = qla2x00_write_nvram_data, 1774 .fw_dump = qla2300_fw_dump, 1775 .beacon_on = qla2x00_beacon_on, 1776 .beacon_off = qla2x00_beacon_off, 1777 .beacon_blink = qla2x00_beacon_blink, 1778 .read_optrom = qla2x00_read_optrom_data, 1779 .write_optrom = qla2x00_write_optrom_data, 1780 .get_flash_version = qla2x00_get_flash_version, 1781 .start_scsi = qla2x00_start_scsi, 1782 .abort_isp = qla2x00_abort_isp, 1783 .iospace_config = qla2x00_iospace_config, 1784 }; 1785 1786 static struct isp_operations qla24xx_isp_ops = { 1787 .pci_config = qla24xx_pci_config, 1788 .reset_chip = qla24xx_reset_chip, 1789 .chip_diag = qla24xx_chip_diag, 1790 .config_rings = qla24xx_config_rings, 1791 .reset_adapter = qla24xx_reset_adapter, 1792 .nvram_config = qla24xx_nvram_config, 1793 .update_fw_options = qla24xx_update_fw_options, 1794 .load_risc = qla24xx_load_risc, 1795 .pci_info_str = qla24xx_pci_info_str, 1796 .fw_version_str = qla24xx_fw_version_str, 1797 .intr_handler = qla24xx_intr_handler, 1798 .enable_intrs = qla24xx_enable_intrs, 1799 .disable_intrs = qla24xx_disable_intrs, 1800 .abort_command = qla24xx_abort_command, 1801 .target_reset = qla24xx_abort_target, 1802 .lun_reset = qla24xx_lun_reset, 1803 .fabric_login = qla24xx_login_fabric, 1804 .fabric_logout = qla24xx_fabric_logout, 1805 .calc_req_entries = NULL, 1806 .build_iocbs = NULL, 1807 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1808 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1809 .read_nvram = qla24xx_read_nvram_data, 1810 .write_nvram = qla24xx_write_nvram_data, 1811 .fw_dump = qla24xx_fw_dump, 1812 .beacon_on = qla24xx_beacon_on, 1813 .beacon_off = qla24xx_beacon_off, 1814 .beacon_blink = qla24xx_beacon_blink, 1815 .read_optrom = qla24xx_read_optrom_data, 1816 .write_optrom = qla24xx_write_optrom_data, 1817 .get_flash_version = qla24xx_get_flash_version, 1818 .start_scsi = qla24xx_start_scsi, 1819 .abort_isp = qla2x00_abort_isp, 1820 .iospace_config = qla2x00_iospace_config, 1821 }; 1822 1823 static struct isp_operations qla25xx_isp_ops = { 1824 .pci_config = qla25xx_pci_config, 1825 .reset_chip = qla24xx_reset_chip, 1826 .chip_diag = qla24xx_chip_diag, 1827 .config_rings = qla24xx_config_rings, 1828 .reset_adapter = qla24xx_reset_adapter, 1829 .nvram_config = qla24xx_nvram_config, 1830 .update_fw_options = qla24xx_update_fw_options, 1831 .load_risc = qla24xx_load_risc, 1832 .pci_info_str = qla24xx_pci_info_str, 1833 .fw_version_str = qla24xx_fw_version_str, 1834 .intr_handler = qla24xx_intr_handler, 1835 .enable_intrs = qla24xx_enable_intrs, 1836 .disable_intrs = qla24xx_disable_intrs, 1837 .abort_command = qla24xx_abort_command, 1838 .target_reset = qla24xx_abort_target, 1839 .lun_reset = qla24xx_lun_reset, 1840 .fabric_login = qla24xx_login_fabric, 1841 .fabric_logout = qla24xx_fabric_logout, 1842 .calc_req_entries = NULL, 1843 .build_iocbs = NULL, 1844 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1845 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1846 .read_nvram = qla25xx_read_nvram_data, 1847 .write_nvram = qla25xx_write_nvram_data, 1848 .fw_dump = qla25xx_fw_dump, 1849 .beacon_on = qla24xx_beacon_on, 1850 .beacon_off = qla24xx_beacon_off, 1851 .beacon_blink = qla24xx_beacon_blink, 1852 .read_optrom = qla25xx_read_optrom_data, 1853 .write_optrom = qla24xx_write_optrom_data, 1854 .get_flash_version = qla24xx_get_flash_version, 1855 .start_scsi = qla24xx_dif_start_scsi, 1856 .abort_isp = qla2x00_abort_isp, 1857 .iospace_config = qla2x00_iospace_config, 1858 }; 1859 1860 static struct isp_operations qla81xx_isp_ops = { 1861 .pci_config = qla25xx_pci_config, 1862 .reset_chip = qla24xx_reset_chip, 1863 .chip_diag = qla24xx_chip_diag, 1864 .config_rings = qla24xx_config_rings, 1865 .reset_adapter = qla24xx_reset_adapter, 1866 .nvram_config = qla81xx_nvram_config, 1867 .update_fw_options = qla81xx_update_fw_options, 1868 .load_risc = qla81xx_load_risc, 1869 .pci_info_str = qla24xx_pci_info_str, 1870 .fw_version_str = qla24xx_fw_version_str, 1871 .intr_handler = qla24xx_intr_handler, 1872 .enable_intrs = qla24xx_enable_intrs, 1873 .disable_intrs = qla24xx_disable_intrs, 1874 .abort_command = qla24xx_abort_command, 1875 .target_reset = qla24xx_abort_target, 1876 .lun_reset = qla24xx_lun_reset, 1877 .fabric_login = qla24xx_login_fabric, 1878 .fabric_logout = qla24xx_fabric_logout, 1879 .calc_req_entries = NULL, 1880 .build_iocbs = NULL, 1881 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1882 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1883 .read_nvram = NULL, 1884 .write_nvram = NULL, 1885 .fw_dump = qla81xx_fw_dump, 1886 .beacon_on = qla24xx_beacon_on, 1887 .beacon_off = qla24xx_beacon_off, 1888 .beacon_blink = qla83xx_beacon_blink, 1889 .read_optrom = qla25xx_read_optrom_data, 1890 .write_optrom = qla24xx_write_optrom_data, 1891 .get_flash_version = qla24xx_get_flash_version, 1892 .start_scsi = qla24xx_dif_start_scsi, 1893 .abort_isp = qla2x00_abort_isp, 1894 .iospace_config = qla2x00_iospace_config, 1895 }; 1896 1897 static struct isp_operations qla82xx_isp_ops = { 1898 .pci_config = qla82xx_pci_config, 1899 .reset_chip = qla82xx_reset_chip, 1900 .chip_diag = qla24xx_chip_diag, 1901 .config_rings = qla82xx_config_rings, 1902 .reset_adapter = qla24xx_reset_adapter, 1903 .nvram_config = qla81xx_nvram_config, 1904 .update_fw_options = qla24xx_update_fw_options, 1905 .load_risc = qla82xx_load_risc, 1906 .pci_info_str = qla82xx_pci_info_str, 1907 .fw_version_str = qla24xx_fw_version_str, 1908 .intr_handler = qla82xx_intr_handler, 1909 .enable_intrs = qla82xx_enable_intrs, 1910 .disable_intrs = qla82xx_disable_intrs, 1911 .abort_command = qla24xx_abort_command, 1912 .target_reset = qla24xx_abort_target, 1913 .lun_reset = qla24xx_lun_reset, 1914 .fabric_login = qla24xx_login_fabric, 1915 .fabric_logout = qla24xx_fabric_logout, 1916 .calc_req_entries = NULL, 1917 .build_iocbs = NULL, 1918 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1920 .read_nvram = qla24xx_read_nvram_data, 1921 .write_nvram = qla24xx_write_nvram_data, 1922 .fw_dump = qla24xx_fw_dump, 1923 .beacon_on = qla82xx_beacon_on, 1924 .beacon_off = qla82xx_beacon_off, 1925 .beacon_blink = NULL, 1926 .read_optrom = qla82xx_read_optrom_data, 1927 .write_optrom = qla82xx_write_optrom_data, 1928 .get_flash_version = qla24xx_get_flash_version, 1929 .start_scsi = qla82xx_start_scsi, 1930 .abort_isp = qla82xx_abort_isp, 1931 .iospace_config = qla82xx_iospace_config, 1932 }; 1933 1934 static struct isp_operations qla83xx_isp_ops = { 1935 .pci_config = qla25xx_pci_config, 1936 .reset_chip = qla24xx_reset_chip, 1937 .chip_diag = qla24xx_chip_diag, 1938 .config_rings = qla24xx_config_rings, 1939 .reset_adapter = qla24xx_reset_adapter, 1940 .nvram_config = qla81xx_nvram_config, 1941 .update_fw_options = qla81xx_update_fw_options, 1942 .load_risc = qla81xx_load_risc, 1943 .pci_info_str = qla24xx_pci_info_str, 1944 .fw_version_str = qla24xx_fw_version_str, 1945 .intr_handler = qla24xx_intr_handler, 1946 .enable_intrs = qla24xx_enable_intrs, 1947 .disable_intrs = qla24xx_disable_intrs, 1948 .abort_command = qla24xx_abort_command, 1949 .target_reset = qla24xx_abort_target, 1950 .lun_reset = qla24xx_lun_reset, 1951 .fabric_login = qla24xx_login_fabric, 1952 .fabric_logout = qla24xx_fabric_logout, 1953 .calc_req_entries = NULL, 1954 .build_iocbs = NULL, 1955 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1956 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1957 .read_nvram = NULL, 1958 .write_nvram = NULL, 1959 .fw_dump = qla83xx_fw_dump, 1960 .beacon_on = qla24xx_beacon_on, 1961 .beacon_off = qla24xx_beacon_off, 1962 .beacon_blink = qla83xx_beacon_blink, 1963 .read_optrom = qla25xx_read_optrom_data, 1964 .write_optrom = qla24xx_write_optrom_data, 1965 .get_flash_version = qla24xx_get_flash_version, 1966 .start_scsi = qla24xx_dif_start_scsi, 1967 .abort_isp = qla2x00_abort_isp, 1968 .iospace_config = qla83xx_iospace_config, 1969 }; 1970 1971 static inline void 1972 qla2x00_set_isp_flags(struct qla_hw_data *ha) 1973 { 1974 ha->device_type = DT_EXTENDED_IDS; 1975 switch (ha->pdev->device) { 1976 case PCI_DEVICE_ID_QLOGIC_ISP2100: 1977 ha->device_type |= DT_ISP2100; 1978 ha->device_type &= ~DT_EXTENDED_IDS; 1979 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1980 break; 1981 case PCI_DEVICE_ID_QLOGIC_ISP2200: 1982 ha->device_type |= DT_ISP2200; 1983 ha->device_type &= ~DT_EXTENDED_IDS; 1984 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 1985 break; 1986 case PCI_DEVICE_ID_QLOGIC_ISP2300: 1987 ha->device_type |= DT_ISP2300; 1988 ha->device_type |= DT_ZIO_SUPPORTED; 1989 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1990 break; 1991 case PCI_DEVICE_ID_QLOGIC_ISP2312: 1992 ha->device_type |= DT_ISP2312; 1993 ha->device_type |= DT_ZIO_SUPPORTED; 1994 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 1995 break; 1996 case PCI_DEVICE_ID_QLOGIC_ISP2322: 1997 ha->device_type |= DT_ISP2322; 1998 ha->device_type |= DT_ZIO_SUPPORTED; 1999 if (ha->pdev->subsystem_vendor == 0x1028 && 2000 ha->pdev->subsystem_device == 0x0170) 2001 ha->device_type |= DT_OEM_001; 2002 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2003 break; 2004 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2005 ha->device_type |= DT_ISP6312; 2006 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2007 break; 2008 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2009 ha->device_type |= DT_ISP6322; 2010 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2011 break; 2012 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2013 ha->device_type |= DT_ISP2422; 2014 ha->device_type |= DT_ZIO_SUPPORTED; 2015 ha->device_type |= DT_FWI2; 2016 ha->device_type |= DT_IIDMA; 2017 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2018 break; 2019 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2020 ha->device_type |= DT_ISP2432; 2021 ha->device_type |= DT_ZIO_SUPPORTED; 2022 ha->device_type |= DT_FWI2; 2023 ha->device_type |= DT_IIDMA; 2024 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2025 break; 2026 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2027 ha->device_type |= DT_ISP8432; 2028 ha->device_type |= DT_ZIO_SUPPORTED; 2029 ha->device_type |= DT_FWI2; 2030 ha->device_type |= DT_IIDMA; 2031 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2032 break; 2033 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2034 ha->device_type |= DT_ISP5422; 2035 ha->device_type |= DT_FWI2; 2036 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2037 break; 2038 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2039 ha->device_type |= DT_ISP5432; 2040 ha->device_type |= DT_FWI2; 2041 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2042 break; 2043 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2044 ha->device_type |= DT_ISP2532; 2045 ha->device_type |= DT_ZIO_SUPPORTED; 2046 ha->device_type |= DT_FWI2; 2047 ha->device_type |= DT_IIDMA; 2048 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2049 break; 2050 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2051 ha->device_type |= DT_ISP8001; 2052 ha->device_type |= DT_ZIO_SUPPORTED; 2053 ha->device_type |= DT_FWI2; 2054 ha->device_type |= DT_IIDMA; 2055 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2056 break; 2057 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2058 ha->device_type |= DT_ISP8021; 2059 ha->device_type |= DT_ZIO_SUPPORTED; 2060 ha->device_type |= DT_FWI2; 2061 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2062 /* Initialize 82XX ISP flags */ 2063 qla82xx_init_flags(ha); 2064 break; 2065 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2066 ha->device_type |= DT_ISP2031; 2067 ha->device_type |= DT_ZIO_SUPPORTED; 2068 ha->device_type |= DT_FWI2; 2069 ha->device_type |= DT_IIDMA; 2070 ha->device_type |= DT_T10_PI; 2071 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2072 break; 2073 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2074 ha->device_type |= DT_ISP8031; 2075 ha->device_type |= DT_ZIO_SUPPORTED; 2076 ha->device_type |= DT_FWI2; 2077 ha->device_type |= DT_IIDMA; 2078 ha->device_type |= DT_T10_PI; 2079 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2080 break; 2081 } 2082 2083 if (IS_QLA82XX(ha)) 2084 ha->port_no = !(ha->portnum & 1); 2085 else 2086 /* Get adapter physical port no from interrupt pin register. */ 2087 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2088 2089 if (ha->port_no & 1) 2090 ha->flags.port0 = 1; 2091 else 2092 ha->flags.port0 = 0; 2093 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2094 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2095 ha->device_type, ha->flags.port0, ha->fw_srisc_address); 2096 } 2097 2098 static void 2099 qla2xxx_scan_start(struct Scsi_Host *shost) 2100 { 2101 scsi_qla_host_t *vha = shost_priv(shost); 2102 2103 if (vha->hw->flags.running_gold_fw) 2104 return; 2105 2106 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2107 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2108 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2109 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2110 } 2111 2112 static int 2113 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2114 { 2115 scsi_qla_host_t *vha = shost_priv(shost); 2116 2117 if (!vha->host) 2118 return 1; 2119 if (time > vha->hw->loop_reset_delay * HZ) 2120 return 1; 2121 2122 return atomic_read(&vha->loop_state) == LOOP_READY; 2123 } 2124 2125 /* 2126 * PCI driver interface 2127 */ 2128 static int __devinit 2129 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2130 { 2131 int ret = -ENODEV; 2132 struct Scsi_Host *host; 2133 scsi_qla_host_t *base_vha = NULL; 2134 struct qla_hw_data *ha; 2135 char pci_info[30]; 2136 char fw_str[30]; 2137 struct scsi_host_template *sht; 2138 int bars, mem_only = 0; 2139 uint16_t req_length = 0, rsp_length = 0; 2140 struct req_que *req = NULL; 2141 struct rsp_que *rsp = NULL; 2142 2143 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2144 sht = &qla2xxx_driver_template; 2145 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2146 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2147 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2148 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2149 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2150 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2151 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2152 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2153 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2154 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) { 2155 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2156 mem_only = 1; 2157 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2158 "Mem only adapter.\n"); 2159 } 2160 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2161 "Bars=%d.\n", bars); 2162 2163 if (mem_only) { 2164 if (pci_enable_device_mem(pdev)) 2165 goto probe_out; 2166 } else { 2167 if (pci_enable_device(pdev)) 2168 goto probe_out; 2169 } 2170 2171 /* This may fail but that's ok */ 2172 pci_enable_pcie_error_reporting(pdev); 2173 2174 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2175 if (!ha) { 2176 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2177 "Unable to allocate memory for ha.\n"); 2178 goto probe_out; 2179 } 2180 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2181 "Memory allocated for ha=%p.\n", ha); 2182 ha->pdev = pdev; 2183 2184 /* Clear our data area */ 2185 ha->bars = bars; 2186 ha->mem_only = mem_only; 2187 spin_lock_init(&ha->hardware_lock); 2188 spin_lock_init(&ha->vport_slock); 2189 2190 /* Set ISP-type information. */ 2191 qla2x00_set_isp_flags(ha); 2192 2193 /* Set EEH reset type to fundamental if required by hba */ 2194 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) 2195 pdev->needs_freset = 1; 2196 2197 ha->prev_topology = 0; 2198 ha->init_cb_size = sizeof(init_cb_t); 2199 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2200 ha->optrom_size = OPTROM_SIZE_2300; 2201 2202 /* Assign ISP specific operations. */ 2203 if (IS_QLA2100(ha)) { 2204 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2205 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2206 req_length = REQUEST_ENTRY_CNT_2100; 2207 rsp_length = RESPONSE_ENTRY_CNT_2100; 2208 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2209 ha->gid_list_info_size = 4; 2210 ha->flash_conf_off = ~0; 2211 ha->flash_data_off = ~0; 2212 ha->nvram_conf_off = ~0; 2213 ha->nvram_data_off = ~0; 2214 ha->isp_ops = &qla2100_isp_ops; 2215 } else if (IS_QLA2200(ha)) { 2216 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2217 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2218 req_length = REQUEST_ENTRY_CNT_2200; 2219 rsp_length = RESPONSE_ENTRY_CNT_2100; 2220 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2221 ha->gid_list_info_size = 4; 2222 ha->flash_conf_off = ~0; 2223 ha->flash_data_off = ~0; 2224 ha->nvram_conf_off = ~0; 2225 ha->nvram_data_off = ~0; 2226 ha->isp_ops = &qla2100_isp_ops; 2227 } else if (IS_QLA23XX(ha)) { 2228 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2229 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2230 req_length = REQUEST_ENTRY_CNT_2200; 2231 rsp_length = RESPONSE_ENTRY_CNT_2300; 2232 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2233 ha->gid_list_info_size = 6; 2234 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2235 ha->optrom_size = OPTROM_SIZE_2322; 2236 ha->flash_conf_off = ~0; 2237 ha->flash_data_off = ~0; 2238 ha->nvram_conf_off = ~0; 2239 ha->nvram_data_off = ~0; 2240 ha->isp_ops = &qla2300_isp_ops; 2241 } else if (IS_QLA24XX_TYPE(ha)) { 2242 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2243 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2244 req_length = REQUEST_ENTRY_CNT_24XX; 2245 rsp_length = RESPONSE_ENTRY_CNT_2300; 2246 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2247 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2248 ha->gid_list_info_size = 8; 2249 ha->optrom_size = OPTROM_SIZE_24XX; 2250 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2251 ha->isp_ops = &qla24xx_isp_ops; 2252 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2253 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2254 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2255 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2256 } else if (IS_QLA25XX(ha)) { 2257 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2258 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2259 req_length = REQUEST_ENTRY_CNT_24XX; 2260 rsp_length = RESPONSE_ENTRY_CNT_2300; 2261 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2262 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2263 ha->gid_list_info_size = 8; 2264 ha->optrom_size = OPTROM_SIZE_25XX; 2265 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2266 ha->isp_ops = &qla25xx_isp_ops; 2267 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2268 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2269 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2270 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2271 } else if (IS_QLA81XX(ha)) { 2272 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2273 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2274 req_length = REQUEST_ENTRY_CNT_24XX; 2275 rsp_length = RESPONSE_ENTRY_CNT_2300; 2276 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2277 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2278 ha->gid_list_info_size = 8; 2279 ha->optrom_size = OPTROM_SIZE_81XX; 2280 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2281 ha->isp_ops = &qla81xx_isp_ops; 2282 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2283 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2284 ha->nvram_conf_off = ~0; 2285 ha->nvram_data_off = ~0; 2286 } else if (IS_QLA82XX(ha)) { 2287 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2288 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2289 req_length = REQUEST_ENTRY_CNT_82XX; 2290 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2291 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2292 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2293 ha->gid_list_info_size = 8; 2294 ha->optrom_size = OPTROM_SIZE_82XX; 2295 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2296 ha->isp_ops = &qla82xx_isp_ops; 2297 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2298 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2299 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2300 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2301 } else if (IS_QLA83XX(ha)) { 2302 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2303 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2304 req_length = REQUEST_ENTRY_CNT_24XX; 2305 rsp_length = RESPONSE_ENTRY_CNT_2300; 2306 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2307 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2308 ha->gid_list_info_size = 8; 2309 ha->optrom_size = OPTROM_SIZE_83XX; 2310 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2311 ha->isp_ops = &qla83xx_isp_ops; 2312 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2313 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2314 ha->nvram_conf_off = ~0; 2315 ha->nvram_data_off = ~0; 2316 } 2317 2318 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2319 "mbx_count=%d, req_length=%d, " 2320 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2321 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2322 "max_fibre_devices=%d.\n", 2323 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2324 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2325 ha->nvram_npiv_size, ha->max_fibre_devices); 2326 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2327 "isp_ops=%p, flash_conf_off=%d, " 2328 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2329 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2330 ha->nvram_conf_off, ha->nvram_data_off); 2331 2332 /* Configure PCI I/O space */ 2333 ret = ha->isp_ops->iospace_config(ha); 2334 if (ret) 2335 goto probe_hw_failed; 2336 2337 ql_log_pci(ql_log_info, pdev, 0x001d, 2338 "Found an ISP%04X irq %d iobase 0x%p.\n", 2339 pdev->device, pdev->irq, ha->iobase); 2340 mutex_init(&ha->vport_lock); 2341 init_completion(&ha->mbx_cmd_comp); 2342 complete(&ha->mbx_cmd_comp); 2343 init_completion(&ha->mbx_intr_comp); 2344 init_completion(&ha->dcbx_comp); 2345 2346 set_bit(0, (unsigned long *) ha->vp_idx_map); 2347 2348 qla2x00_config_dma_addressing(ha); 2349 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2350 "64 Bit addressing is %s.\n", 2351 ha->flags.enable_64bit_addressing ? "enable" : 2352 "disable"); 2353 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2354 if (!ret) { 2355 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2356 "Failed to allocate memory for adapter, aborting.\n"); 2357 2358 goto probe_hw_failed; 2359 } 2360 2361 req->max_q_depth = MAX_Q_DEPTH; 2362 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2363 req->max_q_depth = ql2xmaxqdepth; 2364 2365 2366 base_vha = qla2x00_create_host(sht, ha); 2367 if (!base_vha) { 2368 ret = -ENOMEM; 2369 qla2x00_mem_free(ha); 2370 qla2x00_free_req_que(ha, req); 2371 qla2x00_free_rsp_que(ha, rsp); 2372 goto probe_hw_failed; 2373 } 2374 2375 pci_set_drvdata(pdev, base_vha); 2376 2377 host = base_vha->host; 2378 base_vha->req = req; 2379 host->can_queue = req->length + 128; 2380 if (IS_QLA2XXX_MIDTYPE(ha)) 2381 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2382 else 2383 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2384 base_vha->vp_idx; 2385 2386 /* Set the SG table size based on ISP type */ 2387 if (!IS_FWI2_CAPABLE(ha)) { 2388 if (IS_QLA2100(ha)) 2389 host->sg_tablesize = 32; 2390 } else { 2391 if (!IS_QLA82XX(ha)) 2392 host->sg_tablesize = QLA_SG_ALL; 2393 } 2394 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2395 "can_queue=%d, req=%p, " 2396 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2397 host->can_queue, base_vha->req, 2398 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2399 host->max_id = ha->max_fibre_devices; 2400 host->this_id = 255; 2401 host->cmd_per_lun = 3; 2402 host->unique_id = host->host_no; 2403 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2404 host->max_cmd_len = 32; 2405 else 2406 host->max_cmd_len = MAX_CMDSZ; 2407 host->max_channel = MAX_BUSES - 1; 2408 host->max_lun = ql2xmaxlun; 2409 host->transportt = qla2xxx_transport_template; 2410 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2411 2412 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2413 "max_id=%d this_id=%d " 2414 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2415 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, 2416 host->this_id, host->cmd_per_lun, host->unique_id, 2417 host->max_cmd_len, host->max_channel, host->max_lun, 2418 host->transportt, sht->vendor_id); 2419 2420 /* Set up the irqs */ 2421 ret = qla2x00_request_irqs(ha, rsp); 2422 if (ret) 2423 goto probe_init_failed; 2424 2425 pci_save_state(pdev); 2426 2427 /* Alloc arrays of request and response ring ptrs */ 2428 que_init: 2429 if (!qla2x00_alloc_queues(ha)) { 2430 ql_log(ql_log_fatal, base_vha, 0x003d, 2431 "Failed to allocate memory for queue pointers.. aborting.\n"); 2432 goto probe_init_failed; 2433 } 2434 2435 ha->rsp_q_map[0] = rsp; 2436 ha->req_q_map[0] = req; 2437 rsp->req = req; 2438 req->rsp = rsp; 2439 set_bit(0, ha->req_qid_map); 2440 set_bit(0, ha->rsp_qid_map); 2441 /* FWI2-capable only. */ 2442 req->req_q_in = &ha->iobase->isp24.req_q_in; 2443 req->req_q_out = &ha->iobase->isp24.req_q_out; 2444 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2445 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2446 if (ha->mqenable || IS_QLA83XX(ha)) { 2447 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2448 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2449 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2450 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2451 } 2452 2453 if (IS_QLA82XX(ha)) { 2454 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2455 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2456 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2457 } 2458 2459 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2460 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2461 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2462 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2463 "req->req_q_in=%p req->req_q_out=%p " 2464 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2465 req->req_q_in, req->req_q_out, 2466 rsp->rsp_q_in, rsp->rsp_q_out); 2467 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2468 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2469 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2470 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2471 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2472 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2473 2474 if (qla2x00_initialize_adapter(base_vha)) { 2475 ql_log(ql_log_fatal, base_vha, 0x00d6, 2476 "Failed to initialize adapter - Adapter flags %x.\n", 2477 base_vha->device_flags); 2478 2479 if (IS_QLA82XX(ha)) { 2480 qla82xx_idc_lock(ha); 2481 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2482 QLA82XX_DEV_FAILED); 2483 qla82xx_idc_unlock(ha); 2484 ql_log(ql_log_fatal, base_vha, 0x00d7, 2485 "HW State: FAILED.\n"); 2486 } 2487 2488 ret = -ENODEV; 2489 goto probe_failed; 2490 } 2491 2492 if (ha->mqenable) { 2493 if (qla25xx_setup_mode(base_vha)) { 2494 ql_log(ql_log_warn, base_vha, 0x00ec, 2495 "Failed to create queues, falling back to single queue mode.\n"); 2496 goto que_init; 2497 } 2498 } 2499 2500 if (ha->flags.running_gold_fw) 2501 goto skip_dpc; 2502 2503 /* 2504 * Startup the kernel thread for this host adapter 2505 */ 2506 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2507 "%s_dpc", base_vha->host_str); 2508 if (IS_ERR(ha->dpc_thread)) { 2509 ql_log(ql_log_fatal, base_vha, 0x00ed, 2510 "Failed to start DPC thread.\n"); 2511 ret = PTR_ERR(ha->dpc_thread); 2512 goto probe_failed; 2513 } 2514 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2515 "DPC thread started successfully.\n"); 2516 2517 skip_dpc: 2518 list_add_tail(&base_vha->list, &ha->vp_list); 2519 base_vha->host->irq = ha->pdev->irq; 2520 2521 /* Initialized the timer */ 2522 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2523 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2524 "Started qla2x00_timer with " 2525 "interval=%d.\n", WATCH_INTERVAL); 2526 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2527 "Detected hba at address=%p.\n", 2528 ha); 2529 2530 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2531 if (ha->fw_attributes & BIT_4) { 2532 int prot = 0; 2533 base_vha->flags.difdix_supported = 1; 2534 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2535 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2536 if (ql2xenabledif == 1) 2537 prot = SHOST_DIX_TYPE0_PROTECTION; 2538 scsi_host_set_prot(host, 2539 prot | SHOST_DIF_TYPE1_PROTECTION 2540 | SHOST_DIF_TYPE2_PROTECTION 2541 | SHOST_DIF_TYPE3_PROTECTION 2542 | SHOST_DIX_TYPE1_PROTECTION 2543 | SHOST_DIX_TYPE2_PROTECTION 2544 | SHOST_DIX_TYPE3_PROTECTION); 2545 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); 2546 } else 2547 base_vha->flags.difdix_supported = 0; 2548 } 2549 2550 ha->isp_ops->enable_intrs(ha); 2551 2552 ret = scsi_add_host(host, &pdev->dev); 2553 if (ret) 2554 goto probe_failed; 2555 2556 base_vha->flags.init_done = 1; 2557 base_vha->flags.online = 1; 2558 2559 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2560 "Init done and hba is online.\n"); 2561 2562 scsi_scan_host(host); 2563 2564 qla2x00_alloc_sysfs_attr(base_vha); 2565 2566 qla2x00_init_host_attr(base_vha); 2567 2568 qla2x00_dfs_setup(base_vha); 2569 2570 ql_log(ql_log_info, base_vha, 0x00fb, 2571 "QLogic %s - %s.\n", 2572 ha->model_number, ha->model_desc ? ha->model_desc : ""); 2573 ql_log(ql_log_info, base_vha, 0x00fc, 2574 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2575 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2576 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2577 base_vha->host_no, 2578 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2579 2580 return 0; 2581 2582 probe_init_failed: 2583 qla2x00_free_req_que(ha, req); 2584 qla2x00_free_rsp_que(ha, rsp); 2585 ha->max_req_queues = ha->max_rsp_queues = 0; 2586 2587 probe_failed: 2588 if (base_vha->timer_active) 2589 qla2x00_stop_timer(base_vha); 2590 base_vha->flags.online = 0; 2591 if (ha->dpc_thread) { 2592 struct task_struct *t = ha->dpc_thread; 2593 2594 ha->dpc_thread = NULL; 2595 kthread_stop(t); 2596 } 2597 2598 qla2x00_free_device(base_vha); 2599 2600 scsi_host_put(base_vha->host); 2601 2602 probe_hw_failed: 2603 if (IS_QLA82XX(ha)) { 2604 qla82xx_idc_lock(ha); 2605 qla82xx_clear_drv_active(ha); 2606 qla82xx_idc_unlock(ha); 2607 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2608 if (!ql2xdbwr) 2609 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2610 } else { 2611 if (ha->iobase) 2612 iounmap(ha->iobase); 2613 } 2614 pci_release_selected_regions(ha->pdev, ha->bars); 2615 kfree(ha); 2616 ha = NULL; 2617 2618 probe_out: 2619 pci_disable_device(pdev); 2620 return ret; 2621 } 2622 2623 static void 2624 qla2x00_shutdown(struct pci_dev *pdev) 2625 { 2626 scsi_qla_host_t *vha; 2627 struct qla_hw_data *ha; 2628 2629 vha = pci_get_drvdata(pdev); 2630 ha = vha->hw; 2631 2632 /* Turn-off FCE trace */ 2633 if (ha->flags.fce_enabled) { 2634 qla2x00_disable_fce_trace(vha, NULL, NULL); 2635 ha->flags.fce_enabled = 0; 2636 } 2637 2638 /* Turn-off EFT trace */ 2639 if (ha->eft) 2640 qla2x00_disable_eft_trace(vha); 2641 2642 /* Stop currently executing firmware. */ 2643 qla2x00_try_to_stop_firmware(vha); 2644 2645 /* Turn adapter off line */ 2646 vha->flags.online = 0; 2647 2648 /* turn-off interrupts on the card */ 2649 if (ha->interrupts_on) { 2650 vha->flags.init_done = 0; 2651 ha->isp_ops->disable_intrs(ha); 2652 } 2653 2654 qla2x00_free_irqs(vha); 2655 2656 qla2x00_free_fw_dump(ha); 2657 } 2658 2659 static void 2660 qla2x00_remove_one(struct pci_dev *pdev) 2661 { 2662 scsi_qla_host_t *base_vha, *vha; 2663 struct qla_hw_data *ha; 2664 unsigned long flags; 2665 2666 base_vha = pci_get_drvdata(pdev); 2667 ha = base_vha->hw; 2668 2669 mutex_lock(&ha->vport_lock); 2670 while (ha->cur_vport_count) { 2671 struct Scsi_Host *scsi_host; 2672 2673 spin_lock_irqsave(&ha->vport_slock, flags); 2674 2675 BUG_ON(base_vha->list.next == &ha->vp_list); 2676 /* This assumes first entry in ha->vp_list is always base vha */ 2677 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2678 scsi_host = scsi_host_get(vha->host); 2679 2680 spin_unlock_irqrestore(&ha->vport_slock, flags); 2681 mutex_unlock(&ha->vport_lock); 2682 2683 fc_vport_terminate(vha->fc_vport); 2684 scsi_host_put(vha->host); 2685 2686 mutex_lock(&ha->vport_lock); 2687 } 2688 mutex_unlock(&ha->vport_lock); 2689 2690 set_bit(UNLOADING, &base_vha->dpc_flags); 2691 2692 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 2693 2694 qla2x00_dfs_remove(base_vha); 2695 2696 qla84xx_put_chip(base_vha); 2697 2698 /* Disable timer */ 2699 if (base_vha->timer_active) 2700 qla2x00_stop_timer(base_vha); 2701 2702 base_vha->flags.online = 0; 2703 2704 /* Flush the work queue and remove it */ 2705 if (ha->wq) { 2706 flush_workqueue(ha->wq); 2707 destroy_workqueue(ha->wq); 2708 ha->wq = NULL; 2709 } 2710 2711 /* Kill the kernel thread for this host */ 2712 if (ha->dpc_thread) { 2713 struct task_struct *t = ha->dpc_thread; 2714 2715 /* 2716 * qla2xxx_wake_dpc checks for ->dpc_thread 2717 * so we need to zero it out. 2718 */ 2719 ha->dpc_thread = NULL; 2720 kthread_stop(t); 2721 } 2722 2723 qla2x00_free_sysfs_attr(base_vha); 2724 2725 fc_remove_host(base_vha->host); 2726 2727 scsi_remove_host(base_vha->host); 2728 2729 qla2x00_free_device(base_vha); 2730 2731 scsi_host_put(base_vha->host); 2732 2733 if (IS_QLA82XX(ha)) { 2734 qla82xx_idc_lock(ha); 2735 qla82xx_clear_drv_active(ha); 2736 qla82xx_idc_unlock(ha); 2737 2738 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2739 if (!ql2xdbwr) 2740 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2741 } else { 2742 if (ha->iobase) 2743 iounmap(ha->iobase); 2744 2745 if (ha->mqiobase) 2746 iounmap(ha->mqiobase); 2747 2748 if (IS_QLA83XX(ha) && ha->msixbase) 2749 iounmap(ha->msixbase); 2750 } 2751 2752 pci_release_selected_regions(ha->pdev, ha->bars); 2753 kfree(ha); 2754 ha = NULL; 2755 2756 pci_disable_pcie_error_reporting(pdev); 2757 2758 pci_disable_device(pdev); 2759 pci_set_drvdata(pdev, NULL); 2760 } 2761 2762 static void 2763 qla2x00_free_device(scsi_qla_host_t *vha) 2764 { 2765 struct qla_hw_data *ha = vha->hw; 2766 2767 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2768 2769 /* Disable timer */ 2770 if (vha->timer_active) 2771 qla2x00_stop_timer(vha); 2772 2773 /* Kill the kernel thread for this host */ 2774 if (ha->dpc_thread) { 2775 struct task_struct *t = ha->dpc_thread; 2776 2777 /* 2778 * qla2xxx_wake_dpc checks for ->dpc_thread 2779 * so we need to zero it out. 2780 */ 2781 ha->dpc_thread = NULL; 2782 kthread_stop(t); 2783 } 2784 2785 qla25xx_delete_queues(vha); 2786 2787 if (ha->flags.fce_enabled) 2788 qla2x00_disable_fce_trace(vha, NULL, NULL); 2789 2790 if (ha->eft) 2791 qla2x00_disable_eft_trace(vha); 2792 2793 /* Stop currently executing firmware. */ 2794 qla2x00_try_to_stop_firmware(vha); 2795 2796 vha->flags.online = 0; 2797 2798 /* turn-off interrupts on the card */ 2799 if (ha->interrupts_on) { 2800 vha->flags.init_done = 0; 2801 ha->isp_ops->disable_intrs(ha); 2802 } 2803 2804 qla2x00_free_irqs(vha); 2805 2806 qla2x00_free_fcports(vha); 2807 2808 qla2x00_mem_free(ha); 2809 2810 qla82xx_md_free(vha); 2811 2812 qla2x00_free_queues(ha); 2813 } 2814 2815 void qla2x00_free_fcports(struct scsi_qla_host *vha) 2816 { 2817 fc_port_t *fcport, *tfcport; 2818 2819 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 2820 list_del(&fcport->list); 2821 kfree(fcport); 2822 fcport = NULL; 2823 } 2824 } 2825 2826 static inline void 2827 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 2828 int defer) 2829 { 2830 struct fc_rport *rport; 2831 scsi_qla_host_t *base_vha; 2832 unsigned long flags; 2833 2834 if (!fcport->rport) 2835 return; 2836 2837 rport = fcport->rport; 2838 if (defer) { 2839 base_vha = pci_get_drvdata(vha->hw->pdev); 2840 spin_lock_irqsave(vha->host->host_lock, flags); 2841 fcport->drport = rport; 2842 spin_unlock_irqrestore(vha->host->host_lock, flags); 2843 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 2844 qla2xxx_wake_dpc(base_vha); 2845 } else 2846 fc_remote_port_delete(rport); 2847 } 2848 2849 /* 2850 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 2851 * 2852 * Input: ha = adapter block pointer. fcport = port structure pointer. 2853 * 2854 * Return: None. 2855 * 2856 * Context: 2857 */ 2858 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 2859 int do_login, int defer) 2860 { 2861 if (atomic_read(&fcport->state) == FCS_ONLINE && 2862 vha->vp_idx == fcport->vp_idx) { 2863 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2864 qla2x00_schedule_rport_del(vha, fcport, defer); 2865 } 2866 /* 2867 * We may need to retry the login, so don't change the state of the 2868 * port but do the retries. 2869 */ 2870 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 2871 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2872 2873 if (!do_login) 2874 return; 2875 2876 if (fcport->login_retry == 0) { 2877 fcport->login_retry = vha->hw->login_retry_count; 2878 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2879 2880 ql_dbg(ql_dbg_disc, vha, 0x2067, 2881 "Port login retry " 2882 "%02x%02x%02x%02x%02x%02x%02x%02x, " 2883 "id = 0x%04x retry cnt=%d.\n", 2884 fcport->port_name[0], fcport->port_name[1], 2885 fcport->port_name[2], fcport->port_name[3], 2886 fcport->port_name[4], fcport->port_name[5], 2887 fcport->port_name[6], fcport->port_name[7], 2888 fcport->loop_id, fcport->login_retry); 2889 } 2890 } 2891 2892 /* 2893 * qla2x00_mark_all_devices_lost 2894 * Updates fcport state when device goes offline. 2895 * 2896 * Input: 2897 * ha = adapter block pointer. 2898 * fcport = port structure pointer. 2899 * 2900 * Return: 2901 * None. 2902 * 2903 * Context: 2904 */ 2905 void 2906 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 2907 { 2908 fc_port_t *fcport; 2909 2910 list_for_each_entry(fcport, &vha->vp_fcports, list) { 2911 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx) 2912 continue; 2913 2914 /* 2915 * No point in marking the device as lost, if the device is 2916 * already DEAD. 2917 */ 2918 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 2919 continue; 2920 if (atomic_read(&fcport->state) == FCS_ONLINE) { 2921 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2922 if (defer) 2923 qla2x00_schedule_rport_del(vha, fcport, defer); 2924 else if (vha->vp_idx == fcport->vp_idx) 2925 qla2x00_schedule_rport_del(vha, fcport, defer); 2926 } 2927 } 2928 } 2929 2930 /* 2931 * qla2x00_mem_alloc 2932 * Allocates adapter memory. 2933 * 2934 * Returns: 2935 * 0 = success. 2936 * !0 = failure. 2937 */ 2938 static int 2939 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 2940 struct req_que **req, struct rsp_que **rsp) 2941 { 2942 char name[16]; 2943 2944 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 2945 &ha->init_cb_dma, GFP_KERNEL); 2946 if (!ha->init_cb) 2947 goto fail; 2948 2949 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 2950 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 2951 if (!ha->gid_list) 2952 goto fail_free_init_cb; 2953 2954 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 2955 if (!ha->srb_mempool) 2956 goto fail_free_gid_list; 2957 2958 if (IS_QLA82XX(ha)) { 2959 /* Allocate cache for CT6 Ctx. */ 2960 if (!ctx_cachep) { 2961 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 2962 sizeof(struct ct6_dsd), 0, 2963 SLAB_HWCACHE_ALIGN, NULL); 2964 if (!ctx_cachep) 2965 goto fail_free_gid_list; 2966 } 2967 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 2968 ctx_cachep); 2969 if (!ha->ctx_mempool) 2970 goto fail_free_srb_mempool; 2971 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 2972 "ctx_cachep=%p ctx_mempool=%p.\n", 2973 ctx_cachep, ha->ctx_mempool); 2974 } 2975 2976 /* Get memory for cached NVRAM */ 2977 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 2978 if (!ha->nvram) 2979 goto fail_free_ctx_mempool; 2980 2981 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 2982 ha->pdev->device); 2983 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2984 DMA_POOL_SIZE, 8, 0); 2985 if (!ha->s_dma_pool) 2986 goto fail_free_nvram; 2987 2988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 2989 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 2990 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 2991 2992 if (IS_QLA82XX(ha) || ql2xenabledif) { 2993 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 2994 DSD_LIST_DMA_POOL_SIZE, 8, 0); 2995 if (!ha->dl_dma_pool) { 2996 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 2997 "Failed to allocate memory for dl_dma_pool.\n"); 2998 goto fail_s_dma_pool; 2999 } 3000 3001 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3002 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3003 if (!ha->fcp_cmnd_dma_pool) { 3004 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3005 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3006 goto fail_dl_dma_pool; 3007 } 3008 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3009 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3010 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3011 } 3012 3013 /* Allocate memory for SNS commands */ 3014 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3015 /* Get consistent memory allocated for SNS commands */ 3016 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3017 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3018 if (!ha->sns_cmd) 3019 goto fail_dma_pool; 3020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3021 "sns_cmd: %p.\n", ha->sns_cmd); 3022 } else { 3023 /* Get consistent memory allocated for MS IOCB */ 3024 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3025 &ha->ms_iocb_dma); 3026 if (!ha->ms_iocb) 3027 goto fail_dma_pool; 3028 /* Get consistent memory allocated for CT SNS commands */ 3029 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3030 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3031 if (!ha->ct_sns) 3032 goto fail_free_ms_iocb; 3033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3034 "ms_iocb=%p ct_sns=%p.\n", 3035 ha->ms_iocb, ha->ct_sns); 3036 } 3037 3038 /* Allocate memory for request ring */ 3039 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3040 if (!*req) { 3041 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3042 "Failed to allocate memory for req.\n"); 3043 goto fail_req; 3044 } 3045 (*req)->length = req_len; 3046 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3047 ((*req)->length + 1) * sizeof(request_t), 3048 &(*req)->dma, GFP_KERNEL); 3049 if (!(*req)->ring) { 3050 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3051 "Failed to allocate memory for req_ring.\n"); 3052 goto fail_req_ring; 3053 } 3054 /* Allocate memory for response ring */ 3055 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3056 if (!*rsp) { 3057 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3058 "Failed to allocate memory for rsp.\n"); 3059 goto fail_rsp; 3060 } 3061 (*rsp)->hw = ha; 3062 (*rsp)->length = rsp_len; 3063 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3064 ((*rsp)->length + 1) * sizeof(response_t), 3065 &(*rsp)->dma, GFP_KERNEL); 3066 if (!(*rsp)->ring) { 3067 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3068 "Failed to allocate memory for rsp_ring.\n"); 3069 goto fail_rsp_ring; 3070 } 3071 (*req)->rsp = *rsp; 3072 (*rsp)->req = *req; 3073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3074 "req=%p req->length=%d req->ring=%p rsp=%p " 3075 "rsp->length=%d rsp->ring=%p.\n", 3076 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3077 (*rsp)->ring); 3078 /* Allocate memory for NVRAM data for vports */ 3079 if (ha->nvram_npiv_size) { 3080 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3081 ha->nvram_npiv_size, GFP_KERNEL); 3082 if (!ha->npiv_info) { 3083 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3084 "Failed to allocate memory for npiv_info.\n"); 3085 goto fail_npiv_info; 3086 } 3087 } else 3088 ha->npiv_info = NULL; 3089 3090 /* Get consistent memory allocated for EX-INIT-CB. */ 3091 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) { 3092 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3093 &ha->ex_init_cb_dma); 3094 if (!ha->ex_init_cb) 3095 goto fail_ex_init_cb; 3096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3097 "ex_init_cb=%p.\n", ha->ex_init_cb); 3098 } 3099 3100 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3101 3102 /* Get consistent memory allocated for Async Port-Database. */ 3103 if (!IS_FWI2_CAPABLE(ha)) { 3104 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3105 &ha->async_pd_dma); 3106 if (!ha->async_pd) 3107 goto fail_async_pd; 3108 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3109 "async_pd=%p.\n", ha->async_pd); 3110 } 3111 3112 INIT_LIST_HEAD(&ha->vp_list); 3113 return 1; 3114 3115 fail_async_pd: 3116 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3117 fail_ex_init_cb: 3118 kfree(ha->npiv_info); 3119 fail_npiv_info: 3120 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3121 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3122 (*rsp)->ring = NULL; 3123 (*rsp)->dma = 0; 3124 fail_rsp_ring: 3125 kfree(*rsp); 3126 fail_rsp: 3127 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3128 sizeof(request_t), (*req)->ring, (*req)->dma); 3129 (*req)->ring = NULL; 3130 (*req)->dma = 0; 3131 fail_req_ring: 3132 kfree(*req); 3133 fail_req: 3134 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3135 ha->ct_sns, ha->ct_sns_dma); 3136 ha->ct_sns = NULL; 3137 ha->ct_sns_dma = 0; 3138 fail_free_ms_iocb: 3139 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3140 ha->ms_iocb = NULL; 3141 ha->ms_iocb_dma = 0; 3142 fail_dma_pool: 3143 if (IS_QLA82XX(ha) || ql2xenabledif) { 3144 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3145 ha->fcp_cmnd_dma_pool = NULL; 3146 } 3147 fail_dl_dma_pool: 3148 if (IS_QLA82XX(ha) || ql2xenabledif) { 3149 dma_pool_destroy(ha->dl_dma_pool); 3150 ha->dl_dma_pool = NULL; 3151 } 3152 fail_s_dma_pool: 3153 dma_pool_destroy(ha->s_dma_pool); 3154 ha->s_dma_pool = NULL; 3155 fail_free_nvram: 3156 kfree(ha->nvram); 3157 ha->nvram = NULL; 3158 fail_free_ctx_mempool: 3159 mempool_destroy(ha->ctx_mempool); 3160 ha->ctx_mempool = NULL; 3161 fail_free_srb_mempool: 3162 mempool_destroy(ha->srb_mempool); 3163 ha->srb_mempool = NULL; 3164 fail_free_gid_list: 3165 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3166 ha->gid_list, 3167 ha->gid_list_dma); 3168 ha->gid_list = NULL; 3169 ha->gid_list_dma = 0; 3170 fail_free_init_cb: 3171 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3172 ha->init_cb_dma); 3173 ha->init_cb = NULL; 3174 ha->init_cb_dma = 0; 3175 fail: 3176 ql_log(ql_log_fatal, NULL, 0x0030, 3177 "Memory allocation failure.\n"); 3178 return -ENOMEM; 3179 } 3180 3181 /* 3182 * qla2x00_free_fw_dump 3183 * Frees fw dump stuff. 3184 * 3185 * Input: 3186 * ha = adapter block pointer. 3187 */ 3188 static void 3189 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3190 { 3191 if (ha->fce) 3192 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 3193 ha->fce_dma); 3194 3195 if (ha->fw_dump) { 3196 if (ha->eft) 3197 dma_free_coherent(&ha->pdev->dev, 3198 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); 3199 vfree(ha->fw_dump); 3200 } 3201 ha->fce = NULL; 3202 ha->fce_dma = 0; 3203 ha->eft = NULL; 3204 ha->eft_dma = 0; 3205 ha->fw_dump = NULL; 3206 ha->fw_dumped = 0; 3207 ha->fw_dump_reading = 0; 3208 } 3209 3210 /* 3211 * qla2x00_mem_free 3212 * Frees all adapter allocated memory. 3213 * 3214 * Input: 3215 * ha = adapter block pointer. 3216 */ 3217 static void 3218 qla2x00_mem_free(struct qla_hw_data *ha) 3219 { 3220 qla2x00_free_fw_dump(ha); 3221 3222 if (ha->srb_mempool) 3223 mempool_destroy(ha->srb_mempool); 3224 3225 if (ha->dcbx_tlv) 3226 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3227 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3228 3229 if (ha->xgmac_data) 3230 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3231 ha->xgmac_data, ha->xgmac_data_dma); 3232 3233 if (ha->sns_cmd) 3234 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3235 ha->sns_cmd, ha->sns_cmd_dma); 3236 3237 if (ha->ct_sns) 3238 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3239 ha->ct_sns, ha->ct_sns_dma); 3240 3241 if (ha->sfp_data) 3242 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3243 3244 if (ha->ms_iocb) 3245 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3246 3247 if (ha->ex_init_cb) 3248 dma_pool_free(ha->s_dma_pool, 3249 ha->ex_init_cb, ha->ex_init_cb_dma); 3250 3251 if (ha->async_pd) 3252 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3253 3254 if (ha->s_dma_pool) 3255 dma_pool_destroy(ha->s_dma_pool); 3256 3257 if (ha->gid_list) 3258 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3259 ha->gid_list, ha->gid_list_dma); 3260 3261 if (IS_QLA82XX(ha)) { 3262 if (!list_empty(&ha->gbl_dsd_list)) { 3263 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3264 3265 /* clean up allocated prev pool */ 3266 list_for_each_entry_safe(dsd_ptr, 3267 tdsd_ptr, &ha->gbl_dsd_list, list) { 3268 dma_pool_free(ha->dl_dma_pool, 3269 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3270 list_del(&dsd_ptr->list); 3271 kfree(dsd_ptr); 3272 } 3273 } 3274 } 3275 3276 if (ha->dl_dma_pool) 3277 dma_pool_destroy(ha->dl_dma_pool); 3278 3279 if (ha->fcp_cmnd_dma_pool) 3280 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3281 3282 if (ha->ctx_mempool) 3283 mempool_destroy(ha->ctx_mempool); 3284 3285 if (ha->init_cb) 3286 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3287 ha->init_cb, ha->init_cb_dma); 3288 vfree(ha->optrom_buffer); 3289 kfree(ha->nvram); 3290 kfree(ha->npiv_info); 3291 kfree(ha->swl); 3292 3293 ha->srb_mempool = NULL; 3294 ha->ctx_mempool = NULL; 3295 ha->sns_cmd = NULL; 3296 ha->sns_cmd_dma = 0; 3297 ha->ct_sns = NULL; 3298 ha->ct_sns_dma = 0; 3299 ha->ms_iocb = NULL; 3300 ha->ms_iocb_dma = 0; 3301 ha->init_cb = NULL; 3302 ha->init_cb_dma = 0; 3303 ha->ex_init_cb = NULL; 3304 ha->ex_init_cb_dma = 0; 3305 ha->async_pd = NULL; 3306 ha->async_pd_dma = 0; 3307 3308 ha->s_dma_pool = NULL; 3309 ha->dl_dma_pool = NULL; 3310 ha->fcp_cmnd_dma_pool = NULL; 3311 3312 ha->gid_list = NULL; 3313 ha->gid_list_dma = 0; 3314 } 3315 3316 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3317 struct qla_hw_data *ha) 3318 { 3319 struct Scsi_Host *host; 3320 struct scsi_qla_host *vha = NULL; 3321 3322 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3323 if (host == NULL) { 3324 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3325 "Failed to allocate host from the scsi layer, aborting.\n"); 3326 goto fail; 3327 } 3328 3329 /* Clear our data area */ 3330 vha = shost_priv(host); 3331 memset(vha, 0, sizeof(scsi_qla_host_t)); 3332 3333 vha->host = host; 3334 vha->host_no = host->host_no; 3335 vha->hw = ha; 3336 3337 INIT_LIST_HEAD(&vha->vp_fcports); 3338 INIT_LIST_HEAD(&vha->work_list); 3339 INIT_LIST_HEAD(&vha->list); 3340 3341 spin_lock_init(&vha->work_lock); 3342 3343 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3344 ql_dbg(ql_dbg_init, vha, 0x0041, 3345 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3346 vha->host, vha->hw, vha, 3347 dev_name(&(ha->pdev->dev))); 3348 3349 return vha; 3350 3351 fail: 3352 return vha; 3353 } 3354 3355 static struct qla_work_evt * 3356 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3357 { 3358 struct qla_work_evt *e; 3359 uint8_t bail; 3360 3361 QLA_VHA_MARK_BUSY(vha, bail); 3362 if (bail) 3363 return NULL; 3364 3365 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3366 if (!e) { 3367 QLA_VHA_MARK_NOT_BUSY(vha); 3368 return NULL; 3369 } 3370 3371 INIT_LIST_HEAD(&e->list); 3372 e->type = type; 3373 e->flags = QLA_EVT_FLAG_FREE; 3374 return e; 3375 } 3376 3377 static int 3378 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3379 { 3380 unsigned long flags; 3381 3382 spin_lock_irqsave(&vha->work_lock, flags); 3383 list_add_tail(&e->list, &vha->work_list); 3384 spin_unlock_irqrestore(&vha->work_lock, flags); 3385 qla2xxx_wake_dpc(vha); 3386 3387 return QLA_SUCCESS; 3388 } 3389 3390 int 3391 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3392 u32 data) 3393 { 3394 struct qla_work_evt *e; 3395 3396 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3397 if (!e) 3398 return QLA_FUNCTION_FAILED; 3399 3400 e->u.aen.code = code; 3401 e->u.aen.data = data; 3402 return qla2x00_post_work(vha, e); 3403 } 3404 3405 int 3406 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3407 { 3408 struct qla_work_evt *e; 3409 3410 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3411 if (!e) 3412 return QLA_FUNCTION_FAILED; 3413 3414 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3415 return qla2x00_post_work(vha, e); 3416 } 3417 3418 #define qla2x00_post_async_work(name, type) \ 3419 int qla2x00_post_async_##name##_work( \ 3420 struct scsi_qla_host *vha, \ 3421 fc_port_t *fcport, uint16_t *data) \ 3422 { \ 3423 struct qla_work_evt *e; \ 3424 \ 3425 e = qla2x00_alloc_work(vha, type); \ 3426 if (!e) \ 3427 return QLA_FUNCTION_FAILED; \ 3428 \ 3429 e->u.logio.fcport = fcport; \ 3430 if (data) { \ 3431 e->u.logio.data[0] = data[0]; \ 3432 e->u.logio.data[1] = data[1]; \ 3433 } \ 3434 return qla2x00_post_work(vha, e); \ 3435 } 3436 3437 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3438 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3439 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3440 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3441 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3442 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3443 3444 int 3445 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3446 { 3447 struct qla_work_evt *e; 3448 3449 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3450 if (!e) 3451 return QLA_FUNCTION_FAILED; 3452 3453 e->u.uevent.code = code; 3454 return qla2x00_post_work(vha, e); 3455 } 3456 3457 static void 3458 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3459 { 3460 char event_string[40]; 3461 char *envp[] = { event_string, NULL }; 3462 3463 switch (code) { 3464 case QLA_UEVENT_CODE_FW_DUMP: 3465 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3466 vha->host_no); 3467 break; 3468 default: 3469 /* do nothing */ 3470 break; 3471 } 3472 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3473 } 3474 3475 void 3476 qla2x00_do_work(struct scsi_qla_host *vha) 3477 { 3478 struct qla_work_evt *e, *tmp; 3479 unsigned long flags; 3480 LIST_HEAD(work); 3481 3482 spin_lock_irqsave(&vha->work_lock, flags); 3483 list_splice_init(&vha->work_list, &work); 3484 spin_unlock_irqrestore(&vha->work_lock, flags); 3485 3486 list_for_each_entry_safe(e, tmp, &work, list) { 3487 list_del_init(&e->list); 3488 3489 switch (e->type) { 3490 case QLA_EVT_AEN: 3491 fc_host_post_event(vha->host, fc_get_event_number(), 3492 e->u.aen.code, e->u.aen.data); 3493 break; 3494 case QLA_EVT_IDC_ACK: 3495 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3496 break; 3497 case QLA_EVT_ASYNC_LOGIN: 3498 qla2x00_async_login(vha, e->u.logio.fcport, 3499 e->u.logio.data); 3500 break; 3501 case QLA_EVT_ASYNC_LOGIN_DONE: 3502 qla2x00_async_login_done(vha, e->u.logio.fcport, 3503 e->u.logio.data); 3504 break; 3505 case QLA_EVT_ASYNC_LOGOUT: 3506 qla2x00_async_logout(vha, e->u.logio.fcport); 3507 break; 3508 case QLA_EVT_ASYNC_LOGOUT_DONE: 3509 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3510 e->u.logio.data); 3511 break; 3512 case QLA_EVT_ASYNC_ADISC: 3513 qla2x00_async_adisc(vha, e->u.logio.fcport, 3514 e->u.logio.data); 3515 break; 3516 case QLA_EVT_ASYNC_ADISC_DONE: 3517 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3518 e->u.logio.data); 3519 break; 3520 case QLA_EVT_UEVENT: 3521 qla2x00_uevent_emit(vha, e->u.uevent.code); 3522 break; 3523 } 3524 if (e->flags & QLA_EVT_FLAG_FREE) 3525 kfree(e); 3526 3527 /* For each work completed decrement vha ref count */ 3528 QLA_VHA_MARK_NOT_BUSY(vha); 3529 } 3530 } 3531 3532 /* Relogins all the fcports of a vport 3533 * Context: dpc thread 3534 */ 3535 void qla2x00_relogin(struct scsi_qla_host *vha) 3536 { 3537 fc_port_t *fcport; 3538 int status; 3539 uint16_t next_loopid = 0; 3540 struct qla_hw_data *ha = vha->hw; 3541 uint16_t data[2]; 3542 3543 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3544 /* 3545 * If the port is not ONLINE then try to login 3546 * to it if we haven't run out of retries. 3547 */ 3548 if (atomic_read(&fcport->state) != FCS_ONLINE && 3549 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3550 fcport->login_retry--; 3551 if (fcport->flags & FCF_FABRIC_DEVICE) { 3552 if (fcport->flags & FCF_FCP2_DEVICE) 3553 ha->isp_ops->fabric_logout(vha, 3554 fcport->loop_id, 3555 fcport->d_id.b.domain, 3556 fcport->d_id.b.area, 3557 fcport->d_id.b.al_pa); 3558 3559 if (fcport->loop_id == FC_NO_LOOP_ID) { 3560 fcport->loop_id = next_loopid = 3561 ha->min_external_loopid; 3562 status = qla2x00_find_new_loop_id( 3563 vha, fcport); 3564 if (status != QLA_SUCCESS) { 3565 /* Ran out of IDs to use */ 3566 break; 3567 } 3568 } 3569 3570 if (IS_ALOGIO_CAPABLE(ha)) { 3571 fcport->flags |= FCF_ASYNC_SENT; 3572 data[0] = 0; 3573 data[1] = QLA_LOGIO_LOGIN_RETRIED; 3574 status = qla2x00_post_async_login_work( 3575 vha, fcport, data); 3576 if (status == QLA_SUCCESS) 3577 continue; 3578 /* Attempt a retry. */ 3579 status = 1; 3580 } else { 3581 status = qla2x00_fabric_login(vha, 3582 fcport, &next_loopid); 3583 if (status == QLA_SUCCESS) { 3584 int status2; 3585 uint8_t opts; 3586 3587 opts = 0; 3588 if (fcport->flags & 3589 FCF_FCP2_DEVICE) 3590 opts |= BIT_1; 3591 status2 = 3592 qla2x00_get_port_database( 3593 vha, fcport, 3594 opts); 3595 if (status2 != QLA_SUCCESS) 3596 status = 1; 3597 } 3598 } 3599 } else 3600 status = qla2x00_local_device_login(vha, 3601 fcport); 3602 3603 if (status == QLA_SUCCESS) { 3604 fcport->old_loop_id = fcport->loop_id; 3605 3606 ql_dbg(ql_dbg_disc, vha, 0x2003, 3607 "Port login OK: logged in ID 0x%x.\n", 3608 fcport->loop_id); 3609 3610 qla2x00_update_fcport(vha, fcport); 3611 3612 } else if (status == 1) { 3613 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3614 /* retry the login again */ 3615 ql_dbg(ql_dbg_disc, vha, 0x2007, 3616 "Retrying %d login again loop_id 0x%x.\n", 3617 fcport->login_retry, fcport->loop_id); 3618 } else { 3619 fcport->login_retry = 0; 3620 } 3621 3622 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 3623 fcport->loop_id = FC_NO_LOOP_ID; 3624 } 3625 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3626 break; 3627 } 3628 } 3629 3630 /************************************************************************** 3631 * qla2x00_do_dpc 3632 * This kernel thread is a task that is schedule by the interrupt handler 3633 * to perform the background processing for interrupts. 3634 * 3635 * Notes: 3636 * This task always run in the context of a kernel thread. It 3637 * is kick-off by the driver's detect code and starts up 3638 * up one per adapter. It immediately goes to sleep and waits for 3639 * some fibre event. When either the interrupt handler or 3640 * the timer routine detects a event it will one of the task 3641 * bits then wake us up. 3642 **************************************************************************/ 3643 static int 3644 qla2x00_do_dpc(void *data) 3645 { 3646 int rval; 3647 scsi_qla_host_t *base_vha; 3648 struct qla_hw_data *ha; 3649 3650 ha = (struct qla_hw_data *)data; 3651 base_vha = pci_get_drvdata(ha->pdev); 3652 3653 set_user_nice(current, -20); 3654 3655 set_current_state(TASK_INTERRUPTIBLE); 3656 while (!kthread_should_stop()) { 3657 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 3658 "DPC handler sleeping.\n"); 3659 3660 schedule(); 3661 __set_current_state(TASK_RUNNING); 3662 3663 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 3664 goto end_loop; 3665 3666 if (ha->flags.eeh_busy) { 3667 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 3668 "eeh_busy=%d.\n", ha->flags.eeh_busy); 3669 goto end_loop; 3670 } 3671 3672 ha->dpc_active = 1; 3673 3674 ql_dbg(ql_dbg_dpc, base_vha, 0x4001, 3675 "DPC handler waking up.\n"); 3676 ql_dbg(ql_dbg_dpc, base_vha, 0x4002, 3677 "dpc_flags=0x%lx.\n", base_vha->dpc_flags); 3678 3679 qla2x00_do_work(base_vha); 3680 3681 if (IS_QLA82XX(ha)) { 3682 if (test_and_clear_bit(ISP_UNRECOVERABLE, 3683 &base_vha->dpc_flags)) { 3684 qla82xx_idc_lock(ha); 3685 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3686 QLA82XX_DEV_FAILED); 3687 qla82xx_idc_unlock(ha); 3688 ql_log(ql_log_info, base_vha, 0x4004, 3689 "HW State: FAILED.\n"); 3690 qla82xx_device_state_handler(base_vha); 3691 continue; 3692 } 3693 3694 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 3695 &base_vha->dpc_flags)) { 3696 3697 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 3698 "FCoE context reset scheduled.\n"); 3699 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3700 &base_vha->dpc_flags))) { 3701 if (qla82xx_fcoe_ctx_reset(base_vha)) { 3702 /* FCoE-ctx reset failed. 3703 * Escalate to chip-reset 3704 */ 3705 set_bit(ISP_ABORT_NEEDED, 3706 &base_vha->dpc_flags); 3707 } 3708 clear_bit(ABORT_ISP_ACTIVE, 3709 &base_vha->dpc_flags); 3710 } 3711 3712 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 3713 "FCoE context reset end.\n"); 3714 } 3715 } 3716 3717 if (test_and_clear_bit(ISP_ABORT_NEEDED, 3718 &base_vha->dpc_flags)) { 3719 3720 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 3721 "ISP abort scheduled.\n"); 3722 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 3723 &base_vha->dpc_flags))) { 3724 3725 if (ha->isp_ops->abort_isp(base_vha)) { 3726 /* failed. retry later */ 3727 set_bit(ISP_ABORT_NEEDED, 3728 &base_vha->dpc_flags); 3729 } 3730 clear_bit(ABORT_ISP_ACTIVE, 3731 &base_vha->dpc_flags); 3732 } 3733 3734 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 3735 "ISP abort end.\n"); 3736 } 3737 3738 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { 3739 qla2x00_update_fcports(base_vha); 3740 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3741 } 3742 3743 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 3744 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 3745 "Quiescence mode scheduled.\n"); 3746 qla82xx_device_state_handler(base_vha); 3747 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); 3748 if (!ha->flags.quiesce_owner) { 3749 qla2x00_perform_loop_resync(base_vha); 3750 3751 qla82xx_idc_lock(ha); 3752 qla82xx_clear_qsnt_ready(base_vha); 3753 qla82xx_idc_unlock(ha); 3754 } 3755 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 3756 "Quiescence mode end.\n"); 3757 } 3758 3759 if (test_and_clear_bit(RESET_MARKER_NEEDED, 3760 &base_vha->dpc_flags) && 3761 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 3762 3763 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 3764 "Reset marker scheduled.\n"); 3765 qla2x00_rst_aen(base_vha); 3766 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 3767 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 3768 "Reset marker end.\n"); 3769 } 3770 3771 /* Retry each device up to login retry count */ 3772 if ((test_and_clear_bit(RELOGIN_NEEDED, 3773 &base_vha->dpc_flags)) && 3774 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 3775 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 3776 3777 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 3778 "Relogin scheduled.\n"); 3779 qla2x00_relogin(base_vha); 3780 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 3781 "Relogin end.\n"); 3782 } 3783 3784 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 3785 &base_vha->dpc_flags)) { 3786 3787 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 3788 "Loop resync scheduled.\n"); 3789 3790 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 3791 &base_vha->dpc_flags))) { 3792 3793 rval = qla2x00_loop_resync(base_vha); 3794 3795 clear_bit(LOOP_RESYNC_ACTIVE, 3796 &base_vha->dpc_flags); 3797 } 3798 3799 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 3800 "Loop resync end.\n"); 3801 } 3802 3803 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 3804 atomic_read(&base_vha->loop_state) == LOOP_READY) { 3805 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 3806 qla2xxx_flash_npiv_conf(base_vha); 3807 } 3808 3809 if (!ha->interrupts_on) 3810 ha->isp_ops->enable_intrs(ha); 3811 3812 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 3813 &base_vha->dpc_flags)) 3814 ha->isp_ops->beacon_blink(base_vha); 3815 3816 qla2x00_do_dpc_all_vps(base_vha); 3817 3818 ha->dpc_active = 0; 3819 end_loop: 3820 set_current_state(TASK_INTERRUPTIBLE); 3821 } /* End of while(1) */ 3822 __set_current_state(TASK_RUNNING); 3823 3824 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 3825 "DPC handler exiting.\n"); 3826 3827 /* 3828 * Make sure that nobody tries to wake us up again. 3829 */ 3830 ha->dpc_active = 0; 3831 3832 /* Cleanup any residual CTX SRBs. */ 3833 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3834 3835 return 0; 3836 } 3837 3838 void 3839 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 3840 { 3841 struct qla_hw_data *ha = vha->hw; 3842 struct task_struct *t = ha->dpc_thread; 3843 3844 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 3845 wake_up_process(t); 3846 } 3847 3848 /* 3849 * qla2x00_rst_aen 3850 * Processes asynchronous reset. 3851 * 3852 * Input: 3853 * ha = adapter block pointer. 3854 */ 3855 static void 3856 qla2x00_rst_aen(scsi_qla_host_t *vha) 3857 { 3858 if (vha->flags.online && !vha->flags.reset_active && 3859 !atomic_read(&vha->loop_down_timer) && 3860 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 3861 do { 3862 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 3863 3864 /* 3865 * Issue marker command only when we are going to start 3866 * the I/O. 3867 */ 3868 vha->marker_needed = 1; 3869 } while (!atomic_read(&vha->loop_down_timer) && 3870 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 3871 } 3872 } 3873 3874 /************************************************************************** 3875 * qla2x00_timer 3876 * 3877 * Description: 3878 * One second timer 3879 * 3880 * Context: Interrupt 3881 ***************************************************************************/ 3882 void 3883 qla2x00_timer(scsi_qla_host_t *vha) 3884 { 3885 unsigned long cpu_flags = 0; 3886 int start_dpc = 0; 3887 int index; 3888 srb_t *sp; 3889 uint16_t w; 3890 struct qla_hw_data *ha = vha->hw; 3891 struct req_que *req; 3892 3893 if (ha->flags.eeh_busy) { 3894 ql_dbg(ql_dbg_timer, vha, 0x6000, 3895 "EEH = %d, restarting timer.\n", 3896 ha->flags.eeh_busy); 3897 qla2x00_restart_timer(vha, WATCH_INTERVAL); 3898 return; 3899 } 3900 3901 /* Hardware read to raise pending EEH errors during mailbox waits. */ 3902 if (!pci_channel_offline(ha->pdev)) 3903 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 3904 3905 /* Make sure qla82xx_watchdog is run only for physical port */ 3906 if (!vha->vp_idx && IS_QLA82XX(ha)) { 3907 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 3908 start_dpc++; 3909 qla82xx_watchdog(vha); 3910 } 3911 3912 /* Loop down handler. */ 3913 if (atomic_read(&vha->loop_down_timer) > 0 && 3914 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 3915 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 3916 && vha->flags.online) { 3917 3918 if (atomic_read(&vha->loop_down_timer) == 3919 vha->loop_down_abort_time) { 3920 3921 ql_log(ql_log_info, vha, 0x6008, 3922 "Loop down - aborting the queues before time expires.\n"); 3923 3924 if (!IS_QLA2100(ha) && vha->link_down_timeout) 3925 atomic_set(&vha->loop_state, LOOP_DEAD); 3926 3927 /* 3928 * Schedule an ISP abort to return any FCP2-device 3929 * commands. 3930 */ 3931 /* NPIV - scan physical port only */ 3932 if (!vha->vp_idx) { 3933 spin_lock_irqsave(&ha->hardware_lock, 3934 cpu_flags); 3935 req = ha->req_q_map[0]; 3936 for (index = 1; 3937 index < MAX_OUTSTANDING_COMMANDS; 3938 index++) { 3939 fc_port_t *sfcp; 3940 3941 sp = req->outstanding_cmds[index]; 3942 if (!sp) 3943 continue; 3944 if (sp->type != SRB_SCSI_CMD) 3945 continue; 3946 sfcp = sp->fcport; 3947 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 3948 continue; 3949 3950 if (IS_QLA82XX(ha)) 3951 set_bit(FCOE_CTX_RESET_NEEDED, 3952 &vha->dpc_flags); 3953 else 3954 set_bit(ISP_ABORT_NEEDED, 3955 &vha->dpc_flags); 3956 break; 3957 } 3958 spin_unlock_irqrestore(&ha->hardware_lock, 3959 cpu_flags); 3960 } 3961 start_dpc++; 3962 } 3963 3964 /* if the loop has been down for 4 minutes, reinit adapter */ 3965 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 3966 if (!(vha->device_flags & DFLG_NO_CABLE)) { 3967 ql_log(ql_log_warn, vha, 0x6009, 3968 "Loop down - aborting ISP.\n"); 3969 3970 if (IS_QLA82XX(ha)) 3971 set_bit(FCOE_CTX_RESET_NEEDED, 3972 &vha->dpc_flags); 3973 else 3974 set_bit(ISP_ABORT_NEEDED, 3975 &vha->dpc_flags); 3976 } 3977 } 3978 ql_dbg(ql_dbg_timer, vha, 0x600a, 3979 "Loop down - seconds remaining %d.\n", 3980 atomic_read(&vha->loop_down_timer)); 3981 } 3982 3983 /* Check if beacon LED needs to be blinked for physical host only */ 3984 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 3985 /* There is no beacon_blink function for ISP82xx */ 3986 if (!IS_QLA82XX(ha)) { 3987 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 3988 start_dpc++; 3989 } 3990 } 3991 3992 /* Process any deferred work. */ 3993 if (!list_empty(&vha->work_list)) 3994 start_dpc++; 3995 3996 /* Schedule the DPC routine if needed */ 3997 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 3998 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 3999 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 4000 start_dpc || 4001 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 4002 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 4003 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 4004 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 4005 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 4006 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 4007 ql_dbg(ql_dbg_timer, vha, 0x600b, 4008 "isp_abort_needed=%d loop_resync_needed=%d " 4009 "fcport_update_needed=%d start_dpc=%d " 4010 "reset_marker_needed=%d", 4011 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 4012 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 4013 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 4014 start_dpc, 4015 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 4016 ql_dbg(ql_dbg_timer, vha, 0x600c, 4017 "beacon_blink_needed=%d isp_unrecoverable=%d " 4018 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 4019 "relogin_needed=%d.\n", 4020 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 4021 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 4022 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 4023 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 4024 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 4025 qla2xxx_wake_dpc(vha); 4026 } 4027 4028 qla2x00_restart_timer(vha, WATCH_INTERVAL); 4029 } 4030 4031 /* Firmware interface routines. */ 4032 4033 #define FW_BLOBS 10 4034 #define FW_ISP21XX 0 4035 #define FW_ISP22XX 1 4036 #define FW_ISP2300 2 4037 #define FW_ISP2322 3 4038 #define FW_ISP24XX 4 4039 #define FW_ISP25XX 5 4040 #define FW_ISP81XX 6 4041 #define FW_ISP82XX 7 4042 #define FW_ISP2031 8 4043 #define FW_ISP8031 9 4044 4045 #define FW_FILE_ISP21XX "ql2100_fw.bin" 4046 #define FW_FILE_ISP22XX "ql2200_fw.bin" 4047 #define FW_FILE_ISP2300 "ql2300_fw.bin" 4048 #define FW_FILE_ISP2322 "ql2322_fw.bin" 4049 #define FW_FILE_ISP24XX "ql2400_fw.bin" 4050 #define FW_FILE_ISP25XX "ql2500_fw.bin" 4051 #define FW_FILE_ISP81XX "ql8100_fw.bin" 4052 #define FW_FILE_ISP82XX "ql8200_fw.bin" 4053 #define FW_FILE_ISP2031 "ql2600_fw.bin" 4054 #define FW_FILE_ISP8031 "ql8300_fw.bin" 4055 4056 static DEFINE_MUTEX(qla_fw_lock); 4057 4058 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 4059 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 4060 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 4061 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 4062 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 4063 { .name = FW_FILE_ISP24XX, }, 4064 { .name = FW_FILE_ISP25XX, }, 4065 { .name = FW_FILE_ISP81XX, }, 4066 { .name = FW_FILE_ISP82XX, }, 4067 { .name = FW_FILE_ISP2031, }, 4068 { .name = FW_FILE_ISP8031, }, 4069 }; 4070 4071 struct fw_blob * 4072 qla2x00_request_firmware(scsi_qla_host_t *vha) 4073 { 4074 struct qla_hw_data *ha = vha->hw; 4075 struct fw_blob *blob; 4076 4077 if (IS_QLA2100(ha)) { 4078 blob = &qla_fw_blobs[FW_ISP21XX]; 4079 } else if (IS_QLA2200(ha)) { 4080 blob = &qla_fw_blobs[FW_ISP22XX]; 4081 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4082 blob = &qla_fw_blobs[FW_ISP2300]; 4083 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 4084 blob = &qla_fw_blobs[FW_ISP2322]; 4085 } else if (IS_QLA24XX_TYPE(ha)) { 4086 blob = &qla_fw_blobs[FW_ISP24XX]; 4087 } else if (IS_QLA25XX(ha)) { 4088 blob = &qla_fw_blobs[FW_ISP25XX]; 4089 } else if (IS_QLA81XX(ha)) { 4090 blob = &qla_fw_blobs[FW_ISP81XX]; 4091 } else if (IS_QLA82XX(ha)) { 4092 blob = &qla_fw_blobs[FW_ISP82XX]; 4093 } else if (IS_QLA2031(ha)) { 4094 blob = &qla_fw_blobs[FW_ISP2031]; 4095 } else if (IS_QLA8031(ha)) { 4096 blob = &qla_fw_blobs[FW_ISP8031]; 4097 } else { 4098 return NULL; 4099 } 4100 4101 mutex_lock(&qla_fw_lock); 4102 if (blob->fw) 4103 goto out; 4104 4105 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 4106 ql_log(ql_log_warn, vha, 0x0063, 4107 "Failed to load firmware image (%s).\n", blob->name); 4108 blob->fw = NULL; 4109 blob = NULL; 4110 goto out; 4111 } 4112 4113 out: 4114 mutex_unlock(&qla_fw_lock); 4115 return blob; 4116 } 4117 4118 static void 4119 qla2x00_release_firmware(void) 4120 { 4121 int idx; 4122 4123 mutex_lock(&qla_fw_lock); 4124 for (idx = 0; idx < FW_BLOBS; idx++) 4125 if (qla_fw_blobs[idx].fw) 4126 release_firmware(qla_fw_blobs[idx].fw); 4127 mutex_unlock(&qla_fw_lock); 4128 } 4129 4130 static pci_ers_result_t 4131 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 4132 { 4133 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 4134 struct qla_hw_data *ha = vha->hw; 4135 4136 ql_dbg(ql_dbg_aer, vha, 0x9000, 4137 "PCI error detected, state %x.\n", state); 4138 4139 switch (state) { 4140 case pci_channel_io_normal: 4141 ha->flags.eeh_busy = 0; 4142 return PCI_ERS_RESULT_CAN_RECOVER; 4143 case pci_channel_io_frozen: 4144 ha->flags.eeh_busy = 1; 4145 /* For ISP82XX complete any pending mailbox cmd */ 4146 if (IS_QLA82XX(ha)) { 4147 ha->flags.isp82xx_fw_hung = 1; 4148 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 4149 qla82xx_clear_pending_mbx(vha); 4150 } 4151 qla2x00_free_irqs(vha); 4152 pci_disable_device(pdev); 4153 /* Return back all IOs */ 4154 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4155 return PCI_ERS_RESULT_NEED_RESET; 4156 case pci_channel_io_perm_failure: 4157 ha->flags.pci_channel_io_perm_failure = 1; 4158 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4159 return PCI_ERS_RESULT_DISCONNECT; 4160 } 4161 return PCI_ERS_RESULT_NEED_RESET; 4162 } 4163 4164 static pci_ers_result_t 4165 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 4166 { 4167 int risc_paused = 0; 4168 uint32_t stat; 4169 unsigned long flags; 4170 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4171 struct qla_hw_data *ha = base_vha->hw; 4172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4173 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 4174 4175 if (IS_QLA82XX(ha)) 4176 return PCI_ERS_RESULT_RECOVERED; 4177 4178 spin_lock_irqsave(&ha->hardware_lock, flags); 4179 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 4180 stat = RD_REG_DWORD(®->hccr); 4181 if (stat & HCCR_RISC_PAUSE) 4182 risc_paused = 1; 4183 } else if (IS_QLA23XX(ha)) { 4184 stat = RD_REG_DWORD(®->u.isp2300.host_status); 4185 if (stat & HSR_RISC_PAUSED) 4186 risc_paused = 1; 4187 } else if (IS_FWI2_CAPABLE(ha)) { 4188 stat = RD_REG_DWORD(®24->host_status); 4189 if (stat & HSRX_RISC_PAUSED) 4190 risc_paused = 1; 4191 } 4192 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4193 4194 if (risc_paused) { 4195 ql_log(ql_log_info, base_vha, 0x9003, 4196 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 4197 ha->isp_ops->fw_dump(base_vha, 0); 4198 4199 return PCI_ERS_RESULT_NEED_RESET; 4200 } else 4201 return PCI_ERS_RESULT_RECOVERED; 4202 } 4203 4204 uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) 4205 { 4206 uint32_t rval = QLA_FUNCTION_FAILED; 4207 uint32_t drv_active = 0; 4208 struct qla_hw_data *ha = base_vha->hw; 4209 int fn; 4210 struct pci_dev *other_pdev = NULL; 4211 4212 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 4213 "Entered %s.\n", __func__); 4214 4215 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4216 4217 if (base_vha->flags.online) { 4218 /* Abort all outstanding commands, 4219 * so as to be requeued later */ 4220 qla2x00_abort_isp_cleanup(base_vha); 4221 } 4222 4223 4224 fn = PCI_FUNC(ha->pdev->devfn); 4225 while (fn > 0) { 4226 fn--; 4227 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 4228 "Finding pci device at function = 0x%x.\n", fn); 4229 other_pdev = 4230 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 4231 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 4232 fn)); 4233 4234 if (!other_pdev) 4235 continue; 4236 if (atomic_read(&other_pdev->enable_cnt)) { 4237 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 4238 "Found PCI func available and enable at 0x%x.\n", 4239 fn); 4240 pci_dev_put(other_pdev); 4241 break; 4242 } 4243 pci_dev_put(other_pdev); 4244 } 4245 4246 if (!fn) { 4247 /* Reset owner */ 4248 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 4249 "This devfn is reset owner = 0x%x.\n", 4250 ha->pdev->devfn); 4251 qla82xx_idc_lock(ha); 4252 4253 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4254 QLA82XX_DEV_INITIALIZING); 4255 4256 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 4257 QLA82XX_IDC_VERSION); 4258 4259 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 4260 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 4261 "drv_active = 0x%x.\n", drv_active); 4262 4263 qla82xx_idc_unlock(ha); 4264 /* Reset if device is not already reset 4265 * drv_active would be 0 if a reset has already been done 4266 */ 4267 if (drv_active) 4268 rval = qla82xx_start_firmware(base_vha); 4269 else 4270 rval = QLA_SUCCESS; 4271 qla82xx_idc_lock(ha); 4272 4273 if (rval != QLA_SUCCESS) { 4274 ql_log(ql_log_info, base_vha, 0x900b, 4275 "HW State: FAILED.\n"); 4276 qla82xx_clear_drv_active(ha); 4277 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4278 QLA82XX_DEV_FAILED); 4279 } else { 4280 ql_log(ql_log_info, base_vha, 0x900c, 4281 "HW State: READY.\n"); 4282 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4283 QLA82XX_DEV_READY); 4284 qla82xx_idc_unlock(ha); 4285 ha->flags.isp82xx_fw_hung = 0; 4286 rval = qla82xx_restart_isp(base_vha); 4287 qla82xx_idc_lock(ha); 4288 /* Clear driver state register */ 4289 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 4290 qla82xx_set_drv_active(base_vha); 4291 } 4292 qla82xx_idc_unlock(ha); 4293 } else { 4294 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 4295 "This devfn is not reset owner = 0x%x.\n", 4296 ha->pdev->devfn); 4297 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 4298 QLA82XX_DEV_READY)) { 4299 ha->flags.isp82xx_fw_hung = 0; 4300 rval = qla82xx_restart_isp(base_vha); 4301 qla82xx_idc_lock(ha); 4302 qla82xx_set_drv_active(base_vha); 4303 qla82xx_idc_unlock(ha); 4304 } 4305 } 4306 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4307 4308 return rval; 4309 } 4310 4311 static pci_ers_result_t 4312 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 4313 { 4314 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 4315 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4316 struct qla_hw_data *ha = base_vha->hw; 4317 struct rsp_que *rsp; 4318 int rc, retries = 10; 4319 4320 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 4321 "Slot Reset.\n"); 4322 4323 /* Workaround: qla2xxx driver which access hardware earlier 4324 * needs error state to be pci_channel_io_online. 4325 * Otherwise mailbox command timesout. 4326 */ 4327 pdev->error_state = pci_channel_io_normal; 4328 4329 pci_restore_state(pdev); 4330 4331 /* pci_restore_state() clears the saved_state flag of the device 4332 * save restored state which resets saved_state flag 4333 */ 4334 pci_save_state(pdev); 4335 4336 if (ha->mem_only) 4337 rc = pci_enable_device_mem(pdev); 4338 else 4339 rc = pci_enable_device(pdev); 4340 4341 if (rc) { 4342 ql_log(ql_log_warn, base_vha, 0x9005, 4343 "Can't re-enable PCI device after reset.\n"); 4344 goto exit_slot_reset; 4345 } 4346 4347 rsp = ha->rsp_q_map[0]; 4348 if (qla2x00_request_irqs(ha, rsp)) 4349 goto exit_slot_reset; 4350 4351 if (ha->isp_ops->pci_config(base_vha)) 4352 goto exit_slot_reset; 4353 4354 if (IS_QLA82XX(ha)) { 4355 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 4356 ret = PCI_ERS_RESULT_RECOVERED; 4357 goto exit_slot_reset; 4358 } else 4359 goto exit_slot_reset; 4360 } 4361 4362 while (ha->flags.mbox_busy && retries--) 4363 msleep(1000); 4364 4365 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4366 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 4367 ret = PCI_ERS_RESULT_RECOVERED; 4368 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 4369 4370 4371 exit_slot_reset: 4372 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 4373 "slot_reset return %x.\n", ret); 4374 4375 return ret; 4376 } 4377 4378 static void 4379 qla2xxx_pci_resume(struct pci_dev *pdev) 4380 { 4381 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 4382 struct qla_hw_data *ha = base_vha->hw; 4383 int ret; 4384 4385 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 4386 "pci_resume.\n"); 4387 4388 ret = qla2x00_wait_for_hba_online(base_vha); 4389 if (ret != QLA_SUCCESS) { 4390 ql_log(ql_log_fatal, base_vha, 0x9002, 4391 "The device failed to resume I/O from slot/link_reset.\n"); 4392 } 4393 4394 pci_cleanup_aer_uncorrect_error_status(pdev); 4395 4396 ha->flags.eeh_busy = 0; 4397 } 4398 4399 static struct pci_error_handlers qla2xxx_err_handler = { 4400 .error_detected = qla2xxx_pci_error_detected, 4401 .mmio_enabled = qla2xxx_pci_mmio_enabled, 4402 .slot_reset = qla2xxx_pci_slot_reset, 4403 .resume = qla2xxx_pci_resume, 4404 }; 4405 4406 static struct pci_device_id qla2xxx_pci_tbl[] = { 4407 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 4408 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 4409 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 4410 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 4411 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 4412 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 4413 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 4414 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 4415 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 4416 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 4417 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 4418 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 4419 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 4420 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 4421 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 4422 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 4423 { 0 }, 4424 }; 4425 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 4426 4427 static struct pci_driver qla2xxx_pci_driver = { 4428 .name = QLA2XXX_DRIVER_NAME, 4429 .driver = { 4430 .owner = THIS_MODULE, 4431 }, 4432 .id_table = qla2xxx_pci_tbl, 4433 .probe = qla2x00_probe_one, 4434 .remove = qla2x00_remove_one, 4435 .shutdown = qla2x00_shutdown, 4436 .err_handler = &qla2xxx_err_handler, 4437 }; 4438 4439 static struct file_operations apidev_fops = { 4440 .owner = THIS_MODULE, 4441 .llseek = noop_llseek, 4442 }; 4443 4444 /** 4445 * qla2x00_module_init - Module initialization. 4446 **/ 4447 static int __init 4448 qla2x00_module_init(void) 4449 { 4450 int ret = 0; 4451 4452 /* Allocate cache for SRBs. */ 4453 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 4454 SLAB_HWCACHE_ALIGN, NULL); 4455 if (srb_cachep == NULL) { 4456 ql_log(ql_log_fatal, NULL, 0x0001, 4457 "Unable to allocate SRB cache...Failing load!.\n"); 4458 return -ENOMEM; 4459 } 4460 4461 /* Derive version string. */ 4462 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 4463 if (ql2xextended_error_logging) 4464 strcat(qla2x00_version_str, "-debug"); 4465 4466 qla2xxx_transport_template = 4467 fc_attach_transport(&qla2xxx_transport_functions); 4468 if (!qla2xxx_transport_template) { 4469 kmem_cache_destroy(srb_cachep); 4470 ql_log(ql_log_fatal, NULL, 0x0002, 4471 "fc_attach_transport failed...Failing load!.\n"); 4472 return -ENODEV; 4473 } 4474 4475 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 4476 if (apidev_major < 0) { 4477 ql_log(ql_log_fatal, NULL, 0x0003, 4478 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 4479 } 4480 4481 qla2xxx_transport_vport_template = 4482 fc_attach_transport(&qla2xxx_transport_vport_functions); 4483 if (!qla2xxx_transport_vport_template) { 4484 kmem_cache_destroy(srb_cachep); 4485 fc_release_transport(qla2xxx_transport_template); 4486 ql_log(ql_log_fatal, NULL, 0x0004, 4487 "fc_attach_transport vport failed...Failing load!.\n"); 4488 return -ENODEV; 4489 } 4490 ql_log(ql_log_info, NULL, 0x0005, 4491 "QLogic Fibre Channel HBA Driver: %s.\n", 4492 qla2x00_version_str); 4493 ret = pci_register_driver(&qla2xxx_pci_driver); 4494 if (ret) { 4495 kmem_cache_destroy(srb_cachep); 4496 fc_release_transport(qla2xxx_transport_template); 4497 fc_release_transport(qla2xxx_transport_vport_template); 4498 ql_log(ql_log_fatal, NULL, 0x0006, 4499 "pci_register_driver failed...ret=%d Failing load!.\n", 4500 ret); 4501 } 4502 return ret; 4503 } 4504 4505 /** 4506 * qla2x00_module_exit - Module cleanup. 4507 **/ 4508 static void __exit 4509 qla2x00_module_exit(void) 4510 { 4511 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 4512 pci_unregister_driver(&qla2xxx_pci_driver); 4513 qla2x00_release_firmware(); 4514 kmem_cache_destroy(srb_cachep); 4515 if (ctx_cachep) 4516 kmem_cache_destroy(ctx_cachep); 4517 fc_release_transport(qla2xxx_transport_template); 4518 fc_release_transport(qla2xxx_transport_vport_template); 4519 } 4520 4521 module_init(qla2x00_module_init); 4522 module_exit(qla2x00_module_exit); 4523 4524 MODULE_AUTHOR("QLogic Corporation"); 4525 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 4526 MODULE_LICENSE("GPL"); 4527 MODULE_VERSION(QLA2XXX_VERSION); 4528 MODULE_FIRMWARE(FW_FILE_ISP21XX); 4529 MODULE_FIRMWARE(FW_FILE_ISP22XX); 4530 MODULE_FIRMWARE(FW_FILE_ISP2300); 4531 MODULE_FIRMWARE(FW_FILE_ISP2322); 4532 MODULE_FIRMWARE(FW_FILE_ISP24XX); 4533 MODULE_FIRMWARE(FW_FILE_ISP25XX); 4534