1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101 int ql2xshiftctondsd = 6; 102 module_param(ql2xshiftctondsd, int, S_IRUGO); 103 MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107 int ql2xfdmienable=1; 108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 109 MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113 #define MAX_Q_DEPTH 32 114 static int ql2xmaxqdepth = MAX_Q_DEPTH; 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116 MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120 int ql2xenabledif = 2; 121 module_param(ql2xenabledif, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF:\n" 124 " Default is 2.\n" 125 " 0 -- No DIF Support\n" 126 " 1 -- Enable DIF for all types\n" 127 " 2 -- Enable DIF for all types, except Type 0.\n"); 128 129 int ql2xenablehba_err_chk = 2; 130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xenablehba_err_chk, 132 " Enable T10-CRC-DIF Error isolation by HBA:\n" 133 " Default is 2.\n" 134 " 0 -- Error isolation disabled\n" 135 " 1 -- Error isolation enabled only for DIX Type 0\n" 136 " 2 -- Error isolation enabled for all Types\n"); 137 138 int ql2xiidmaenable=1; 139 module_param(ql2xiidmaenable, int, S_IRUGO); 140 MODULE_PARM_DESC(ql2xiidmaenable, 141 "Enables iIDMA settings " 142 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 143 144 int ql2xmaxqueues = 1; 145 module_param(ql2xmaxqueues, int, S_IRUGO); 146 MODULE_PARM_DESC(ql2xmaxqueues, 147 "Enables MQ settings " 148 "Default is 1 for single queue. Set it to number " 149 "of queues in MQ mode."); 150 151 int ql2xmultique_tag; 152 module_param(ql2xmultique_tag, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xmultique_tag, 154 "Enables CPU affinity settings for the driver " 155 "Default is 0 for no affinity of request and response IO. " 156 "Set it to 1 to turn on the cpu affinity."); 157 158 int ql2xfwloadbin; 159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 160 MODULE_PARM_DESC(ql2xfwloadbin, 161 "Option to specify location from which to load ISP firmware:.\n" 162 " 2 -- load firmware via the request_firmware() (hotplug).\n" 163 " interface.\n" 164 " 1 -- load firmware from flash.\n" 165 " 0 -- use default semantics.\n"); 166 167 int ql2xetsenable; 168 module_param(ql2xetsenable, int, S_IRUGO); 169 MODULE_PARM_DESC(ql2xetsenable, 170 "Enables firmware ETS burst." 171 "Default is 0 - skip ETS enablement."); 172 173 int ql2xdbwr = 1; 174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 175 MODULE_PARM_DESC(ql2xdbwr, 176 "Option to specify scheme for request queue posting.\n" 177 " 0 -- Regular doorbell.\n" 178 " 1 -- CAMRAM doorbell (faster).\n"); 179 180 int ql2xtargetreset = 1; 181 module_param(ql2xtargetreset, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xtargetreset, 183 "Enable target reset." 184 "Default is 1 - use hw defaults."); 185 186 int ql2xgffidenable; 187 module_param(ql2xgffidenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xgffidenable, 189 "Enables GFF_ID checks of port type. " 190 "Default is 0 - Do not use GFF_ID information."); 191 192 int ql2xasynctmfenable; 193 module_param(ql2xasynctmfenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xasynctmfenable, 195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 196 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 197 198 int ql2xdontresethba; 199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdontresethba, 201 "Option to specify reset behaviour.\n" 202 " 0 (Default) -- Reset on failure.\n" 203 " 1 -- Do not reset on failure.\n"); 204 205 uint64_t ql2xmaxlun = MAX_LUNS; 206 module_param(ql2xmaxlun, ullong, S_IRUGO); 207 MODULE_PARM_DESC(ql2xmaxlun, 208 "Defines the maximum LU number to register with the SCSI " 209 "midlayer. Default is 65535."); 210 211 int ql2xmdcapmask = 0x1F; 212 module_param(ql2xmdcapmask, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xmdcapmask, 214 "Set the Minidump driver capture mask level. " 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 216 217 int ql2xmdenable = 1; 218 module_param(ql2xmdenable, int, S_IRUGO); 219 MODULE_PARM_DESC(ql2xmdenable, 220 "Enable/disable MiniDump. " 221 "0 - MiniDump disabled. " 222 "1 (Default) - MiniDump enabled."); 223 224 int ql2xexlogins = 0; 225 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 226 MODULE_PARM_DESC(ql2xexlogins, 227 "Number of extended Logins. " 228 "0 (Default)- Disabled."); 229 230 int ql2xexchoffld = 0; 231 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 232 MODULE_PARM_DESC(ql2xexchoffld, 233 "Number of exchanges to offload. " 234 "0 (Default)- Disabled."); 235 236 /* 237 * SCSI host template entry points 238 */ 239 static int qla2xxx_slave_configure(struct scsi_device * device); 240 static int qla2xxx_slave_alloc(struct scsi_device *); 241 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 242 static void qla2xxx_scan_start(struct Scsi_Host *); 243 static void qla2xxx_slave_destroy(struct scsi_device *); 244 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 245 static int qla2xxx_eh_abort(struct scsi_cmnd *); 246 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 247 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 248 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 249 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 250 251 static void qla2x00_clear_drv_active(struct qla_hw_data *); 252 static void qla2x00_free_device(scsi_qla_host_t *); 253 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 254 255 struct scsi_host_template qla2xxx_driver_template = { 256 .module = THIS_MODULE, 257 .name = QLA2XXX_DRIVER_NAME, 258 .queuecommand = qla2xxx_queuecommand, 259 260 .eh_abort_handler = qla2xxx_eh_abort, 261 .eh_device_reset_handler = qla2xxx_eh_device_reset, 262 .eh_target_reset_handler = qla2xxx_eh_target_reset, 263 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 264 .eh_host_reset_handler = qla2xxx_eh_host_reset, 265 266 .slave_configure = qla2xxx_slave_configure, 267 268 .slave_alloc = qla2xxx_slave_alloc, 269 .slave_destroy = qla2xxx_slave_destroy, 270 .scan_finished = qla2xxx_scan_finished, 271 .scan_start = qla2xxx_scan_start, 272 .change_queue_depth = scsi_change_queue_depth, 273 .this_id = -1, 274 .cmd_per_lun = 3, 275 .use_clustering = ENABLE_CLUSTERING, 276 .sg_tablesize = SG_ALL, 277 278 .max_sectors = 0xFFFF, 279 .shost_attrs = qla2x00_host_attrs, 280 281 .supported_mode = MODE_INITIATOR, 282 .track_queue_depth = 1, 283 }; 284 285 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 286 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 287 288 /* TODO Convert to inlines 289 * 290 * Timer routines 291 */ 292 293 __inline__ void 294 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 295 { 296 init_timer(&vha->timer); 297 vha->timer.expires = jiffies + interval * HZ; 298 vha->timer.data = (unsigned long)vha; 299 vha->timer.function = (void (*)(unsigned long))func; 300 add_timer(&vha->timer); 301 vha->timer_active = 1; 302 } 303 304 static inline void 305 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 306 { 307 /* Currently used for 82XX only. */ 308 if (vha->device_flags & DFLG_DEV_FAILED) { 309 ql_dbg(ql_dbg_timer, vha, 0x600d, 310 "Device in a failed state, returning.\n"); 311 return; 312 } 313 314 mod_timer(&vha->timer, jiffies + interval * HZ); 315 } 316 317 static __inline__ void 318 qla2x00_stop_timer(scsi_qla_host_t *vha) 319 { 320 del_timer_sync(&vha->timer); 321 vha->timer_active = 0; 322 } 323 324 static int qla2x00_do_dpc(void *data); 325 326 static void qla2x00_rst_aen(scsi_qla_host_t *); 327 328 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 329 struct req_que **, struct rsp_que **); 330 static void qla2x00_free_fw_dump(struct qla_hw_data *); 331 static void qla2x00_mem_free(struct qla_hw_data *); 332 333 /* -------------------------------------------------------------------------- */ 334 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 335 struct rsp_que *rsp) 336 { 337 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 338 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 339 GFP_KERNEL); 340 if (!ha->req_q_map) { 341 ql_log(ql_log_fatal, vha, 0x003b, 342 "Unable to allocate memory for request queue ptrs.\n"); 343 goto fail_req_map; 344 } 345 346 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 347 GFP_KERNEL); 348 if (!ha->rsp_q_map) { 349 ql_log(ql_log_fatal, vha, 0x003c, 350 "Unable to allocate memory for response queue ptrs.\n"); 351 goto fail_rsp_map; 352 } 353 /* 354 * Make sure we record at least the request and response queue zero in 355 * case we need to free them if part of the probe fails. 356 */ 357 ha->rsp_q_map[0] = rsp; 358 ha->req_q_map[0] = req; 359 set_bit(0, ha->rsp_qid_map); 360 set_bit(0, ha->req_qid_map); 361 return 1; 362 363 fail_rsp_map: 364 kfree(ha->req_q_map); 365 ha->req_q_map = NULL; 366 fail_req_map: 367 return -ENOMEM; 368 } 369 370 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 371 { 372 if (IS_QLAFX00(ha)) { 373 if (req && req->ring_fx00) 374 dma_free_coherent(&ha->pdev->dev, 375 (req->length_fx00 + 1) * sizeof(request_t), 376 req->ring_fx00, req->dma_fx00); 377 } else if (req && req->ring) 378 dma_free_coherent(&ha->pdev->dev, 379 (req->length + 1) * sizeof(request_t), 380 req->ring, req->dma); 381 382 if (req) 383 kfree(req->outstanding_cmds); 384 385 kfree(req); 386 req = NULL; 387 } 388 389 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 390 { 391 if (IS_QLAFX00(ha)) { 392 if (rsp && rsp->ring) 393 dma_free_coherent(&ha->pdev->dev, 394 (rsp->length_fx00 + 1) * sizeof(request_t), 395 rsp->ring_fx00, rsp->dma_fx00); 396 } else if (rsp && rsp->ring) { 397 dma_free_coherent(&ha->pdev->dev, 398 (rsp->length + 1) * sizeof(response_t), 399 rsp->ring, rsp->dma); 400 } 401 kfree(rsp); 402 rsp = NULL; 403 } 404 405 static void qla2x00_free_queues(struct qla_hw_data *ha) 406 { 407 struct req_que *req; 408 struct rsp_que *rsp; 409 int cnt; 410 411 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 412 req = ha->req_q_map[cnt]; 413 qla2x00_free_req_que(ha, req); 414 } 415 kfree(ha->req_q_map); 416 ha->req_q_map = NULL; 417 418 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 419 rsp = ha->rsp_q_map[cnt]; 420 qla2x00_free_rsp_que(ha, rsp); 421 } 422 kfree(ha->rsp_q_map); 423 ha->rsp_q_map = NULL; 424 } 425 426 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 427 { 428 uint16_t options = 0; 429 int ques, req, ret; 430 struct qla_hw_data *ha = vha->hw; 431 432 if (!(ha->fw_attributes & BIT_6)) { 433 ql_log(ql_log_warn, vha, 0x00d8, 434 "Firmware is not multi-queue capable.\n"); 435 goto fail; 436 } 437 if (ql2xmultique_tag) { 438 /* create a request queue for IO */ 439 options |= BIT_7; 440 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 441 QLA_DEFAULT_QUE_QOS); 442 if (!req) { 443 ql_log(ql_log_warn, vha, 0x00e0, 444 "Failed to create request queue.\n"); 445 goto fail; 446 } 447 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 448 vha->req = ha->req_q_map[req]; 449 options |= BIT_1; 450 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 451 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 452 if (!ret) { 453 ql_log(ql_log_warn, vha, 0x00e8, 454 "Failed to create response queue.\n"); 455 goto fail2; 456 } 457 } 458 ha->flags.cpu_affinity_enabled = 1; 459 ql_dbg(ql_dbg_multiq, vha, 0xc007, 460 "CPU affinity mode enabled, " 461 "no. of response queues:%d no. of request queues:%d.\n", 462 ha->max_rsp_queues, ha->max_req_queues); 463 ql_dbg(ql_dbg_init, vha, 0x00e9, 464 "CPU affinity mode enabled, " 465 "no. of response queues:%d no. of request queues:%d.\n", 466 ha->max_rsp_queues, ha->max_req_queues); 467 } 468 return 0; 469 fail2: 470 qla25xx_delete_queues(vha); 471 destroy_workqueue(ha->wq); 472 ha->wq = NULL; 473 vha->req = ha->req_q_map[0]; 474 fail: 475 ha->mqenable = 0; 476 kfree(ha->req_q_map); 477 kfree(ha->rsp_q_map); 478 ha->max_req_queues = ha->max_rsp_queues = 1; 479 return 1; 480 } 481 482 static char * 483 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 484 { 485 struct qla_hw_data *ha = vha->hw; 486 static char *pci_bus_modes[] = { 487 "33", "66", "100", "133", 488 }; 489 uint16_t pci_bus; 490 491 strcpy(str, "PCI"); 492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 493 if (pci_bus) { 494 strcat(str, "-X ("); 495 strcat(str, pci_bus_modes[pci_bus]); 496 } else { 497 pci_bus = (ha->pci_attr & BIT_8) >> 8; 498 strcat(str, " ("); 499 strcat(str, pci_bus_modes[pci_bus]); 500 } 501 strcat(str, " MHz)"); 502 503 return (str); 504 } 505 506 static char * 507 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 508 { 509 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 510 struct qla_hw_data *ha = vha->hw; 511 uint32_t pci_bus; 512 513 if (pci_is_pcie(ha->pdev)) { 514 char lwstr[6]; 515 uint32_t lstat, lspeed, lwidth; 516 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 518 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 520 521 strcpy(str, "PCIe ("); 522 switch (lspeed) { 523 case 1: 524 strcat(str, "2.5GT/s "); 525 break; 526 case 2: 527 strcat(str, "5.0GT/s "); 528 break; 529 case 3: 530 strcat(str, "8.0GT/s "); 531 break; 532 default: 533 strcat(str, "<unknown> "); 534 break; 535 } 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 537 strcat(str, lwstr); 538 539 return str; 540 } 541 542 strcpy(str, "PCI"); 543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 544 if (pci_bus == 0 || pci_bus == 8) { 545 strcat(str, " ("); 546 strcat(str, pci_bus_modes[pci_bus >> 3]); 547 } else { 548 strcat(str, "-X "); 549 if (pci_bus & BIT_2) 550 strcat(str, "Mode 2"); 551 else 552 strcat(str, "Mode 1"); 553 strcat(str, " ("); 554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 555 } 556 strcat(str, " MHz)"); 557 558 return str; 559 } 560 561 static char * 562 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 563 { 564 char un_str[10]; 565 struct qla_hw_data *ha = vha->hw; 566 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 568 ha->fw_minor_version, ha->fw_subminor_version); 569 570 if (ha->fw_attributes & BIT_9) { 571 strcat(str, "FLX"); 572 return (str); 573 } 574 575 switch (ha->fw_attributes & 0xFF) { 576 case 0x7: 577 strcat(str, "EF"); 578 break; 579 case 0x17: 580 strcat(str, "TP"); 581 break; 582 case 0x37: 583 strcat(str, "IP"); 584 break; 585 case 0x77: 586 strcat(str, "VI"); 587 break; 588 default: 589 sprintf(un_str, "(%x)", ha->fw_attributes); 590 strcat(str, un_str); 591 break; 592 } 593 if (ha->fw_attributes & 0x100) 594 strcat(str, "X"); 595 596 return (str); 597 } 598 599 static char * 600 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 606 return str; 607 } 608 609 void 610 qla2x00_sp_free_dma(void *vha, void *ptr) 611 { 612 srb_t *sp = (srb_t *)ptr; 613 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 614 struct qla_hw_data *ha = sp->fcport->vha->hw; 615 void *ctx = GET_CMD_CTX_SP(sp); 616 617 if (sp->flags & SRB_DMA_VALID) { 618 scsi_dma_unmap(cmd); 619 sp->flags &= ~SRB_DMA_VALID; 620 } 621 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 624 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 626 } 627 628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 629 /* List assured to be having elements */ 630 qla2x00_clean_dsd_pool(ha, sp, NULL); 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 632 } 633 634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 635 dma_pool_free(ha->dl_dma_pool, ctx, 636 ((struct crc_context *)ctx)->crc_ctx_dma); 637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 638 } 639 640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 642 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 644 ctx1->fcp_cmnd_dma); 645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 648 mempool_free(ctx1, ha->ctx_mempool); 649 ctx1 = NULL; 650 } 651 652 CMD_SP(cmd) = NULL; 653 qla2x00_rel_sp(sp->fcport->vha, sp); 654 } 655 656 static void 657 qla2x00_sp_compl(void *data, void *ptr, int res) 658 { 659 struct qla_hw_data *ha = (struct qla_hw_data *)data; 660 srb_t *sp = (srb_t *)ptr; 661 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 662 663 cmd->result = res; 664 665 if (atomic_read(&sp->ref_count) == 0) { 666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 668 sp, GET_CMD_SP(sp)); 669 if (ql2xextended_error_logging & ql_dbg_io) 670 WARN_ON(atomic_read(&sp->ref_count) == 0); 671 return; 672 } 673 if (!atomic_dec_and_test(&sp->ref_count)) 674 return; 675 676 qla2x00_sp_free_dma(ha, sp); 677 cmd->scsi_done(cmd); 678 } 679 680 /* If we are SP1 here, we need to still take and release the host_lock as SP1 681 * does not have the changes necessary to avoid taking host->host_lock. 682 */ 683 static int 684 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 685 { 686 scsi_qla_host_t *vha = shost_priv(host); 687 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 688 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 689 struct qla_hw_data *ha = vha->hw; 690 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 691 srb_t *sp; 692 int rval; 693 694 if (ha->flags.eeh_busy) { 695 if (ha->flags.pci_channel_io_perm_failure) { 696 ql_dbg(ql_dbg_aer, vha, 0x9010, 697 "PCI Channel IO permanent failure, exiting " 698 "cmd=%p.\n", cmd); 699 cmd->result = DID_NO_CONNECT << 16; 700 } else { 701 ql_dbg(ql_dbg_aer, vha, 0x9011, 702 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 703 cmd->result = DID_REQUEUE << 16; 704 } 705 goto qc24_fail_command; 706 } 707 708 rval = fc_remote_port_chkready(rport); 709 if (rval) { 710 cmd->result = rval; 711 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 712 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 713 cmd, rval); 714 goto qc24_fail_command; 715 } 716 717 if (!vha->flags.difdix_supported && 718 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 719 ql_dbg(ql_dbg_io, vha, 0x3004, 720 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 721 cmd); 722 cmd->result = DID_NO_CONNECT << 16; 723 goto qc24_fail_command; 724 } 725 726 if (!fcport) { 727 cmd->result = DID_NO_CONNECT << 16; 728 goto qc24_fail_command; 729 } 730 731 if (atomic_read(&fcport->state) != FCS_ONLINE) { 732 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 733 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 734 ql_dbg(ql_dbg_io, vha, 0x3005, 735 "Returning DNC, fcport_state=%d loop_state=%d.\n", 736 atomic_read(&fcport->state), 737 atomic_read(&base_vha->loop_state)); 738 cmd->result = DID_NO_CONNECT << 16; 739 goto qc24_fail_command; 740 } 741 goto qc24_target_busy; 742 } 743 744 /* 745 * Return target busy if we've received a non-zero retry_delay_timer 746 * in a FCP_RSP. 747 */ 748 if (fcport->retry_delay_timestamp == 0) { 749 /* retry delay not set */ 750 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 751 fcport->retry_delay_timestamp = 0; 752 else 753 goto qc24_target_busy; 754 755 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 756 if (!sp) 757 goto qc24_host_busy; 758 759 sp->u.scmd.cmd = cmd; 760 sp->type = SRB_SCSI_CMD; 761 atomic_set(&sp->ref_count, 1); 762 CMD_SP(cmd) = (void *)sp; 763 sp->free = qla2x00_sp_free_dma; 764 sp->done = qla2x00_sp_compl; 765 766 rval = ha->isp_ops->start_scsi(sp); 767 if (rval != QLA_SUCCESS) { 768 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 769 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 770 goto qc24_host_busy_free_sp; 771 } 772 773 return 0; 774 775 qc24_host_busy_free_sp: 776 qla2x00_sp_free_dma(ha, sp); 777 778 qc24_host_busy: 779 return SCSI_MLQUEUE_HOST_BUSY; 780 781 qc24_target_busy: 782 return SCSI_MLQUEUE_TARGET_BUSY; 783 784 qc24_fail_command: 785 cmd->scsi_done(cmd); 786 787 return 0; 788 } 789 790 /* 791 * qla2x00_eh_wait_on_command 792 * Waits for the command to be returned by the Firmware for some 793 * max time. 794 * 795 * Input: 796 * cmd = Scsi Command to wait on. 797 * 798 * Return: 799 * Not Found : 0 800 * Found : 1 801 */ 802 static int 803 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 804 { 805 #define ABORT_POLLING_PERIOD 1000 806 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 807 unsigned long wait_iter = ABORT_WAIT_ITER; 808 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 809 struct qla_hw_data *ha = vha->hw; 810 int ret = QLA_SUCCESS; 811 812 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 813 ql_dbg(ql_dbg_taskm, vha, 0x8005, 814 "Return:eh_wait.\n"); 815 return ret; 816 } 817 818 while (CMD_SP(cmd) && wait_iter--) { 819 msleep(ABORT_POLLING_PERIOD); 820 } 821 if (CMD_SP(cmd)) 822 ret = QLA_FUNCTION_FAILED; 823 824 return ret; 825 } 826 827 /* 828 * qla2x00_wait_for_hba_online 829 * Wait till the HBA is online after going through 830 * <= MAX_RETRIES_OF_ISP_ABORT or 831 * finally HBA is disabled ie marked offline 832 * 833 * Input: 834 * ha - pointer to host adapter structure 835 * 836 * Note: 837 * Does context switching-Release SPIN_LOCK 838 * (if any) before calling this routine. 839 * 840 * Return: 841 * Success (Adapter is online) : 0 842 * Failed (Adapter is offline/disabled) : 1 843 */ 844 int 845 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 846 { 847 int return_status; 848 unsigned long wait_online; 849 struct qla_hw_data *ha = vha->hw; 850 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 851 852 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 853 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 854 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 855 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 856 ha->dpc_active) && time_before(jiffies, wait_online)) { 857 858 msleep(1000); 859 } 860 if (base_vha->flags.online) 861 return_status = QLA_SUCCESS; 862 else 863 return_status = QLA_FUNCTION_FAILED; 864 865 return (return_status); 866 } 867 868 /* 869 * qla2x00_wait_for_hba_ready 870 * Wait till the HBA is ready before doing driver unload 871 * 872 * Input: 873 * ha - pointer to host adapter structure 874 * 875 * Note: 876 * Does context switching-Release SPIN_LOCK 877 * (if any) before calling this routine. 878 * 879 */ 880 static void 881 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 882 { 883 struct qla_hw_data *ha = vha->hw; 884 885 while (((qla2x00_reset_active(vha)) || ha->dpc_active || 886 ha->flags.mbox_busy) || 887 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 888 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) 889 msleep(1000); 890 } 891 892 int 893 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 894 { 895 int return_status; 896 unsigned long wait_reset; 897 struct qla_hw_data *ha = vha->hw; 898 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 899 900 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 901 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 902 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 903 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 904 ha->dpc_active) && time_before(jiffies, wait_reset)) { 905 906 msleep(1000); 907 908 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 909 ha->flags.chip_reset_done) 910 break; 911 } 912 if (ha->flags.chip_reset_done) 913 return_status = QLA_SUCCESS; 914 else 915 return_status = QLA_FUNCTION_FAILED; 916 917 return return_status; 918 } 919 920 static void 921 sp_get(struct srb *sp) 922 { 923 atomic_inc(&sp->ref_count); 924 } 925 926 /************************************************************************** 927 * qla2xxx_eh_abort 928 * 929 * Description: 930 * The abort function will abort the specified command. 931 * 932 * Input: 933 * cmd = Linux SCSI command packet to be aborted. 934 * 935 * Returns: 936 * Either SUCCESS or FAILED. 937 * 938 * Note: 939 * Only return FAILED if command not returned by firmware. 940 **************************************************************************/ 941 static int 942 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 943 { 944 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 945 srb_t *sp; 946 int ret; 947 unsigned int id; 948 uint64_t lun; 949 unsigned long flags; 950 int rval, wait = 0; 951 struct qla_hw_data *ha = vha->hw; 952 953 if (!CMD_SP(cmd)) 954 return SUCCESS; 955 956 ret = fc_block_scsi_eh(cmd); 957 if (ret != 0) 958 return ret; 959 ret = SUCCESS; 960 961 id = cmd->device->id; 962 lun = cmd->device->lun; 963 964 spin_lock_irqsave(&ha->hardware_lock, flags); 965 sp = (srb_t *) CMD_SP(cmd); 966 if (!sp) { 967 spin_unlock_irqrestore(&ha->hardware_lock, flags); 968 return SUCCESS; 969 } 970 971 ql_dbg(ql_dbg_taskm, vha, 0x8002, 972 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 973 vha->host_no, id, lun, sp, cmd, sp->handle); 974 975 /* Get a reference to the sp and drop the lock.*/ 976 sp_get(sp); 977 978 spin_unlock_irqrestore(&ha->hardware_lock, flags); 979 rval = ha->isp_ops->abort_command(sp); 980 if (rval) { 981 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 982 ret = SUCCESS; 983 else 984 ret = FAILED; 985 986 ql_dbg(ql_dbg_taskm, vha, 0x8003, 987 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 988 } else { 989 ql_dbg(ql_dbg_taskm, vha, 0x8004, 990 "Abort command mbx success cmd=%p.\n", cmd); 991 wait = 1; 992 } 993 994 spin_lock_irqsave(&ha->hardware_lock, flags); 995 sp->done(ha, sp, 0); 996 spin_unlock_irqrestore(&ha->hardware_lock, flags); 997 998 /* Did the command return during mailbox execution? */ 999 if (ret == FAILED && !CMD_SP(cmd)) 1000 ret = SUCCESS; 1001 1002 /* Wait for the command to be returned. */ 1003 if (wait) { 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1005 ql_log(ql_log_warn, vha, 0x8006, 1006 "Abort handler timed out cmd=%p.\n", cmd); 1007 ret = FAILED; 1008 } 1009 } 1010 1011 ql_log(ql_log_info, vha, 0x801c, 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1013 vha->host_no, id, lun, wait, ret); 1014 1015 return ret; 1016 } 1017 1018 int 1019 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1020 uint64_t l, enum nexus_wait_type type) 1021 { 1022 int cnt, match, status; 1023 unsigned long flags; 1024 struct qla_hw_data *ha = vha->hw; 1025 struct req_que *req; 1026 srb_t *sp; 1027 struct scsi_cmnd *cmd; 1028 1029 status = QLA_SUCCESS; 1030 1031 spin_lock_irqsave(&ha->hardware_lock, flags); 1032 req = vha->req; 1033 for (cnt = 1; status == QLA_SUCCESS && 1034 cnt < req->num_outstanding_cmds; cnt++) { 1035 sp = req->outstanding_cmds[cnt]; 1036 if (!sp) 1037 continue; 1038 if (sp->type != SRB_SCSI_CMD) 1039 continue; 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1041 continue; 1042 match = 0; 1043 cmd = GET_CMD_SP(sp); 1044 switch (type) { 1045 case WAIT_HOST: 1046 match = 1; 1047 break; 1048 case WAIT_TARGET: 1049 match = cmd->device->id == t; 1050 break; 1051 case WAIT_LUN: 1052 match = (cmd->device->id == t && 1053 cmd->device->lun == l); 1054 break; 1055 } 1056 if (!match) 1057 continue; 1058 1059 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1060 status = qla2x00_eh_wait_on_command(cmd); 1061 spin_lock_irqsave(&ha->hardware_lock, flags); 1062 } 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1064 1065 return status; 1066 } 1067 1068 static char *reset_errors[] = { 1069 "HBA not online", 1070 "HBA not ready", 1071 "Task management failed", 1072 "Waiting for command completions", 1073 }; 1074 1075 static int 1076 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1078 { 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1081 int err; 1082 1083 if (!fcport) { 1084 return FAILED; 1085 } 1086 1087 err = fc_block_scsi_eh(cmd); 1088 if (err != 0) 1089 return err; 1090 1091 ql_log(ql_log_info, vha, 0x8009, 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1093 cmd->device->id, cmd->device->lun, cmd); 1094 1095 err = 0; 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1097 ql_log(ql_log_warn, vha, 0x800a, 1098 "Wait for hba online failed for cmd=%p.\n", cmd); 1099 goto eh_reset_failed; 1100 } 1101 err = 2; 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1103 != QLA_SUCCESS) { 1104 ql_log(ql_log_warn, vha, 0x800c, 1105 "do_reset failed for cmd=%p.\n", cmd); 1106 goto eh_reset_failed; 1107 } 1108 err = 3; 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1110 cmd->device->lun, type) != QLA_SUCCESS) { 1111 ql_log(ql_log_warn, vha, 0x800d, 1112 "wait for pending cmds failed for cmd=%p.\n", cmd); 1113 goto eh_reset_failed; 1114 } 1115 1116 ql_log(ql_log_info, vha, 0x800e, 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1119 1120 return SUCCESS; 1121 1122 eh_reset_failed: 1123 ql_log(ql_log_info, vha, 0x800f, 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1126 cmd); 1127 return FAILED; 1128 } 1129 1130 static int 1131 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1132 { 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1134 struct qla_hw_data *ha = vha->hw; 1135 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1137 ha->isp_ops->lun_reset); 1138 } 1139 1140 static int 1141 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1142 { 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1144 struct qla_hw_data *ha = vha->hw; 1145 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1147 ha->isp_ops->target_reset); 1148 } 1149 1150 /************************************************************************** 1151 * qla2xxx_eh_bus_reset 1152 * 1153 * Description: 1154 * The bus reset function will reset the bus and abort any executing 1155 * commands. 1156 * 1157 * Input: 1158 * cmd = Linux SCSI command packet of the command that cause the 1159 * bus reset. 1160 * 1161 * Returns: 1162 * SUCCESS/FAILURE (defined as macro in scsi.h). 1163 * 1164 **************************************************************************/ 1165 static int 1166 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1167 { 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1170 int ret = FAILED; 1171 unsigned int id; 1172 uint64_t lun; 1173 1174 id = cmd->device->id; 1175 lun = cmd->device->lun; 1176 1177 if (!fcport) { 1178 return ret; 1179 } 1180 1181 ret = fc_block_scsi_eh(cmd); 1182 if (ret != 0) 1183 return ret; 1184 ret = FAILED; 1185 1186 ql_log(ql_log_info, vha, 0x8012, 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1188 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1190 ql_log(ql_log_fatal, vha, 0x8013, 1191 "Wait for hba online failed board disabled.\n"); 1192 goto eh_bus_reset_done; 1193 } 1194 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1196 ret = SUCCESS; 1197 1198 if (ret == FAILED) 1199 goto eh_bus_reset_done; 1200 1201 /* Flush outstanding commands. */ 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1203 QLA_SUCCESS) { 1204 ql_log(ql_log_warn, vha, 0x8014, 1205 "Wait for pending commands failed.\n"); 1206 ret = FAILED; 1207 } 1208 1209 eh_bus_reset_done: 1210 ql_log(ql_log_warn, vha, 0x802b, 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1213 1214 return ret; 1215 } 1216 1217 /************************************************************************** 1218 * qla2xxx_eh_host_reset 1219 * 1220 * Description: 1221 * The reset function will reset the Adapter. 1222 * 1223 * Input: 1224 * cmd = Linux SCSI command packet of the command that cause the 1225 * adapter reset. 1226 * 1227 * Returns: 1228 * Either SUCCESS or FAILED. 1229 * 1230 * Note: 1231 **************************************************************************/ 1232 static int 1233 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1234 { 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1236 struct qla_hw_data *ha = vha->hw; 1237 int ret = FAILED; 1238 unsigned int id; 1239 uint64_t lun; 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1241 1242 id = cmd->device->id; 1243 lun = cmd->device->lun; 1244 1245 ql_log(ql_log_info, vha, 0x8018, 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1247 1248 /* 1249 * No point in issuing another reset if one is active. Also do not 1250 * attempt a reset if we are updating flash. 1251 */ 1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1253 goto eh_host_reset_lock; 1254 1255 if (vha != base_vha) { 1256 if (qla2x00_vp_abort_isp(vha)) 1257 goto eh_host_reset_lock; 1258 } else { 1259 if (IS_P3P_TYPE(vha->hw)) { 1260 if (!qla82xx_fcoe_ctx_reset(vha)) { 1261 /* Ctx reset success */ 1262 ret = SUCCESS; 1263 goto eh_host_reset_lock; 1264 } 1265 /* fall thru if ctx reset failed */ 1266 } 1267 if (ha->wq) 1268 flush_workqueue(ha->wq); 1269 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1271 if (ha->isp_ops->abort_isp(base_vha)) { 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1273 /* failed. schedule dpc to try */ 1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1275 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1277 ql_log(ql_log_warn, vha, 0x802a, 1278 "wait for hba online failed.\n"); 1279 goto eh_host_reset_lock; 1280 } 1281 } 1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1283 } 1284 1285 /* Waiting for command to be returned to OS.*/ 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1287 QLA_SUCCESS) 1288 ret = SUCCESS; 1289 1290 eh_host_reset_lock: 1291 ql_log(ql_log_info, vha, 0x8017, 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1294 1295 return ret; 1296 } 1297 1298 /* 1299 * qla2x00_loop_reset 1300 * Issue loop reset. 1301 * 1302 * Input: 1303 * ha = adapter block pointer. 1304 * 1305 * Returns: 1306 * 0 = success 1307 */ 1308 int 1309 qla2x00_loop_reset(scsi_qla_host_t *vha) 1310 { 1311 int ret; 1312 struct fc_port *fcport; 1313 struct qla_hw_data *ha = vha->hw; 1314 1315 if (IS_QLAFX00(ha)) { 1316 return qlafx00_loop_reset(vha); 1317 } 1318 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1321 if (fcport->port_type != FCT_TARGET) 1322 continue; 1323 1324 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1325 if (ret != QLA_SUCCESS) { 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1327 "Bus Reset failed: Reset=%d " 1328 "d_id=%x.\n", ret, fcport->d_id.b24); 1329 } 1330 } 1331 } 1332 1333 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1335 atomic_set(&vha->loop_state, LOOP_DOWN); 1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1337 qla2x00_mark_all_devices_lost(vha, 0); 1338 ret = qla2x00_full_login_lip(vha); 1339 if (ret != QLA_SUCCESS) { 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1341 "full_login_lip=%d.\n", ret); 1342 } 1343 } 1344 1345 if (ha->flags.enable_lip_reset) { 1346 ret = qla2x00_lip_reset(vha); 1347 if (ret != QLA_SUCCESS) 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1349 "lip_reset failed (%d).\n", ret); 1350 } 1351 1352 /* Issue marker command only when we are going to start the I/O */ 1353 vha->marker_needed = 1; 1354 1355 return QLA_SUCCESS; 1356 } 1357 1358 void 1359 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1360 { 1361 int que, cnt; 1362 unsigned long flags; 1363 srb_t *sp; 1364 struct qla_hw_data *ha = vha->hw; 1365 struct req_que *req; 1366 1367 qlt_host_reset_handler(ha); 1368 1369 spin_lock_irqsave(&ha->hardware_lock, flags); 1370 for (que = 0; que < ha->max_req_queues; que++) { 1371 req = ha->req_q_map[que]; 1372 if (!req) 1373 continue; 1374 if (!req->outstanding_cmds) 1375 continue; 1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1377 sp = req->outstanding_cmds[cnt]; 1378 if (sp) { 1379 req->outstanding_cmds[cnt] = NULL; 1380 sp->done(vha, sp, res); 1381 } 1382 } 1383 } 1384 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1385 } 1386 1387 static int 1388 qla2xxx_slave_alloc(struct scsi_device *sdev) 1389 { 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1391 1392 if (!rport || fc_remote_port_chkready(rport)) 1393 return -ENXIO; 1394 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1396 1397 return 0; 1398 } 1399 1400 static int 1401 qla2xxx_slave_configure(struct scsi_device *sdev) 1402 { 1403 scsi_qla_host_t *vha = shost_priv(sdev->host); 1404 struct req_que *req = vha->req; 1405 1406 if (IS_T10_PI_CAPABLE(vha->hw)) 1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1408 1409 scsi_change_queue_depth(sdev, req->max_q_depth); 1410 return 0; 1411 } 1412 1413 static void 1414 qla2xxx_slave_destroy(struct scsi_device *sdev) 1415 { 1416 sdev->hostdata = NULL; 1417 } 1418 1419 /** 1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1421 * @ha: HA context 1422 * 1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1424 * supported addressing method. 1425 */ 1426 static void 1427 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1428 { 1429 /* Assume a 32bit DMA mask. */ 1430 ha->flags.enable_64bit_addressing = 0; 1431 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1433 /* Any upper-dword bits set? */ 1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1436 /* Ok, a 64bit DMA mask is applicable. */ 1437 ha->flags.enable_64bit_addressing = 1; 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1440 return; 1441 } 1442 } 1443 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1446 } 1447 1448 static void 1449 qla2x00_enable_intrs(struct qla_hw_data *ha) 1450 { 1451 unsigned long flags = 0; 1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1453 1454 spin_lock_irqsave(&ha->hardware_lock, flags); 1455 ha->interrupts_on = 1; 1456 /* enable risc and host interrupts */ 1457 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1458 RD_REG_WORD(®->ictrl); 1459 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1460 1461 } 1462 1463 static void 1464 qla2x00_disable_intrs(struct qla_hw_data *ha) 1465 { 1466 unsigned long flags = 0; 1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1468 1469 spin_lock_irqsave(&ha->hardware_lock, flags); 1470 ha->interrupts_on = 0; 1471 /* disable risc and host interrupts */ 1472 WRT_REG_WORD(®->ictrl, 0); 1473 RD_REG_WORD(®->ictrl); 1474 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1475 } 1476 1477 static void 1478 qla24xx_enable_intrs(struct qla_hw_data *ha) 1479 { 1480 unsigned long flags = 0; 1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1482 1483 spin_lock_irqsave(&ha->hardware_lock, flags); 1484 ha->interrupts_on = 1; 1485 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1486 RD_REG_DWORD(®->ictrl); 1487 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1488 } 1489 1490 static void 1491 qla24xx_disable_intrs(struct qla_hw_data *ha) 1492 { 1493 unsigned long flags = 0; 1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1495 1496 if (IS_NOPOLLING_TYPE(ha)) 1497 return; 1498 spin_lock_irqsave(&ha->hardware_lock, flags); 1499 ha->interrupts_on = 0; 1500 WRT_REG_DWORD(®->ictrl, 0); 1501 RD_REG_DWORD(®->ictrl); 1502 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1503 } 1504 1505 static int 1506 qla2x00_iospace_config(struct qla_hw_data *ha) 1507 { 1508 resource_size_t pio; 1509 uint16_t msix; 1510 int cpus; 1511 1512 if (pci_request_selected_regions(ha->pdev, ha->bars, 1513 QLA2XXX_DRIVER_NAME)) { 1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1516 pci_name(ha->pdev)); 1517 goto iospace_error_exit; 1518 } 1519 if (!(ha->bars & 1)) 1520 goto skip_pio; 1521 1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1523 pio = pci_resource_start(ha->pdev, 0); 1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1527 "Invalid pci I/O region size (%s).\n", 1528 pci_name(ha->pdev)); 1529 pio = 0; 1530 } 1531 } else { 1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1533 "Region #0 no a PIO resource (%s).\n", 1534 pci_name(ha->pdev)); 1535 pio = 0; 1536 } 1537 ha->pio_address = pio; 1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1539 "PIO address=%llu.\n", 1540 (unsigned long long)ha->pio_address); 1541 1542 skip_pio: 1543 /* Use MMIO operations for all accesses. */ 1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1546 "Region #1 not an MMIO resource (%s), aborting.\n", 1547 pci_name(ha->pdev)); 1548 goto iospace_error_exit; 1549 } 1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1552 "Invalid PCI mem region size (%s), aborting.\n", 1553 pci_name(ha->pdev)); 1554 goto iospace_error_exit; 1555 } 1556 1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1558 if (!ha->iobase) { 1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1560 "Cannot remap MMIO (%s), aborting.\n", 1561 pci_name(ha->pdev)); 1562 goto iospace_error_exit; 1563 } 1564 1565 /* Determine queue resources */ 1566 ha->max_req_queues = ha->max_rsp_queues = 1; 1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1570 goto mqiobase_exit; 1571 1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1573 pci_resource_len(ha->pdev, 3)); 1574 if (ha->mqiobase) { 1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1576 "MQIO Base=%p.\n", ha->mqiobase); 1577 /* Read MSIX vector size of the board */ 1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1579 ha->msix_count = msix; 1580 /* Max queues are bounded by available msix vectors */ 1581 /* queue 0 uses two msix vectors */ 1582 if (ql2xmultique_tag) { 1583 cpus = num_online_cpus(); 1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1585 (cpus + 1) : (ha->msix_count - 1); 1586 ha->max_req_queues = 2; 1587 } else if (ql2xmaxqueues > 1) { 1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1589 QLA_MQ_SIZE : ql2xmaxqueues; 1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1591 "QoS mode set, max no of request queues:%d.\n", 1592 ha->max_req_queues); 1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1594 "QoS mode set, max no of request queues:%d.\n", 1595 ha->max_req_queues); 1596 } 1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1598 "MSI-X vector count: %d.\n", msix); 1599 } else 1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1601 "BAR 3 not enabled.\n"); 1602 1603 mqiobase_exit: 1604 ha->msix_count = ha->max_rsp_queues + 1; 1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1606 "MSIX Count:%d.\n", ha->msix_count); 1607 return (0); 1608 1609 iospace_error_exit: 1610 return (-ENOMEM); 1611 } 1612 1613 1614 static int 1615 qla83xx_iospace_config(struct qla_hw_data *ha) 1616 { 1617 uint16_t msix; 1618 int cpus; 1619 1620 if (pci_request_selected_regions(ha->pdev, ha->bars, 1621 QLA2XXX_DRIVER_NAME)) { 1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1624 pci_name(ha->pdev)); 1625 1626 goto iospace_error_exit; 1627 } 1628 1629 /* Use MMIO operations for all accesses. */ 1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1632 "Invalid pci I/O region size (%s).\n", 1633 pci_name(ha->pdev)); 1634 goto iospace_error_exit; 1635 } 1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1638 "Invalid PCI mem region size (%s), aborting\n", 1639 pci_name(ha->pdev)); 1640 goto iospace_error_exit; 1641 } 1642 1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1644 if (!ha->iobase) { 1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1646 "Cannot remap MMIO (%s), aborting.\n", 1647 pci_name(ha->pdev)); 1648 goto iospace_error_exit; 1649 } 1650 1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1652 /* 83XX 26XX always use MQ type access for queues 1653 * - mbar 2, a.k.a region 4 */ 1654 ha->max_req_queues = ha->max_rsp_queues = 1; 1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1656 pci_resource_len(ha->pdev, 4)); 1657 1658 if (!ha->mqiobase) { 1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1660 "BAR2/region4 not enabled\n"); 1661 goto mqiobase_exit; 1662 } 1663 1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1665 pci_resource_len(ha->pdev, 2)); 1666 if (ha->msixbase) { 1667 /* Read MSIX vector size of the board */ 1668 pci_read_config_word(ha->pdev, 1669 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1670 ha->msix_count = msix; 1671 /* Max queues are bounded by available msix vectors */ 1672 /* queue 0 uses two msix vectors */ 1673 if (ql2xmultique_tag) { 1674 cpus = num_online_cpus(); 1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1676 (cpus + 1) : (ha->msix_count - 1); 1677 ha->max_req_queues = 2; 1678 } else if (ql2xmaxqueues > 1) { 1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1680 QLA_MQ_SIZE : ql2xmaxqueues; 1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1682 "QoS mode set, max no of request queues:%d.\n", 1683 ha->max_req_queues); 1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1685 "QoS mode set, max no of request queues:%d.\n", 1686 ha->max_req_queues); 1687 } 1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1689 "MSI-X vector count: %d.\n", msix); 1690 } else 1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1692 "BAR 1 not enabled.\n"); 1693 1694 mqiobase_exit: 1695 ha->msix_count = ha->max_rsp_queues + 1; 1696 1697 qlt_83xx_iospace_config(ha); 1698 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1700 "MSIX Count:%d.\n", ha->msix_count); 1701 return 0; 1702 1703 iospace_error_exit: 1704 return -ENOMEM; 1705 } 1706 1707 static struct isp_operations qla2100_isp_ops = { 1708 .pci_config = qla2100_pci_config, 1709 .reset_chip = qla2x00_reset_chip, 1710 .chip_diag = qla2x00_chip_diag, 1711 .config_rings = qla2x00_config_rings, 1712 .reset_adapter = qla2x00_reset_adapter, 1713 .nvram_config = qla2x00_nvram_config, 1714 .update_fw_options = qla2x00_update_fw_options, 1715 .load_risc = qla2x00_load_risc, 1716 .pci_info_str = qla2x00_pci_info_str, 1717 .fw_version_str = qla2x00_fw_version_str, 1718 .intr_handler = qla2100_intr_handler, 1719 .enable_intrs = qla2x00_enable_intrs, 1720 .disable_intrs = qla2x00_disable_intrs, 1721 .abort_command = qla2x00_abort_command, 1722 .target_reset = qla2x00_abort_target, 1723 .lun_reset = qla2x00_lun_reset, 1724 .fabric_login = qla2x00_login_fabric, 1725 .fabric_logout = qla2x00_fabric_logout, 1726 .calc_req_entries = qla2x00_calc_iocbs_32, 1727 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1728 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1730 .read_nvram = qla2x00_read_nvram_data, 1731 .write_nvram = qla2x00_write_nvram_data, 1732 .fw_dump = qla2100_fw_dump, 1733 .beacon_on = NULL, 1734 .beacon_off = NULL, 1735 .beacon_blink = NULL, 1736 .read_optrom = qla2x00_read_optrom_data, 1737 .write_optrom = qla2x00_write_optrom_data, 1738 .get_flash_version = qla2x00_get_flash_version, 1739 .start_scsi = qla2x00_start_scsi, 1740 .abort_isp = qla2x00_abort_isp, 1741 .iospace_config = qla2x00_iospace_config, 1742 .initialize_adapter = qla2x00_initialize_adapter, 1743 }; 1744 1745 static struct isp_operations qla2300_isp_ops = { 1746 .pci_config = qla2300_pci_config, 1747 .reset_chip = qla2x00_reset_chip, 1748 .chip_diag = qla2x00_chip_diag, 1749 .config_rings = qla2x00_config_rings, 1750 .reset_adapter = qla2x00_reset_adapter, 1751 .nvram_config = qla2x00_nvram_config, 1752 .update_fw_options = qla2x00_update_fw_options, 1753 .load_risc = qla2x00_load_risc, 1754 .pci_info_str = qla2x00_pci_info_str, 1755 .fw_version_str = qla2x00_fw_version_str, 1756 .intr_handler = qla2300_intr_handler, 1757 .enable_intrs = qla2x00_enable_intrs, 1758 .disable_intrs = qla2x00_disable_intrs, 1759 .abort_command = qla2x00_abort_command, 1760 .target_reset = qla2x00_abort_target, 1761 .lun_reset = qla2x00_lun_reset, 1762 .fabric_login = qla2x00_login_fabric, 1763 .fabric_logout = qla2x00_fabric_logout, 1764 .calc_req_entries = qla2x00_calc_iocbs_32, 1765 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1766 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1768 .read_nvram = qla2x00_read_nvram_data, 1769 .write_nvram = qla2x00_write_nvram_data, 1770 .fw_dump = qla2300_fw_dump, 1771 .beacon_on = qla2x00_beacon_on, 1772 .beacon_off = qla2x00_beacon_off, 1773 .beacon_blink = qla2x00_beacon_blink, 1774 .read_optrom = qla2x00_read_optrom_data, 1775 .write_optrom = qla2x00_write_optrom_data, 1776 .get_flash_version = qla2x00_get_flash_version, 1777 .start_scsi = qla2x00_start_scsi, 1778 .abort_isp = qla2x00_abort_isp, 1779 .iospace_config = qla2x00_iospace_config, 1780 .initialize_adapter = qla2x00_initialize_adapter, 1781 }; 1782 1783 static struct isp_operations qla24xx_isp_ops = { 1784 .pci_config = qla24xx_pci_config, 1785 .reset_chip = qla24xx_reset_chip, 1786 .chip_diag = qla24xx_chip_diag, 1787 .config_rings = qla24xx_config_rings, 1788 .reset_adapter = qla24xx_reset_adapter, 1789 .nvram_config = qla24xx_nvram_config, 1790 .update_fw_options = qla24xx_update_fw_options, 1791 .load_risc = qla24xx_load_risc, 1792 .pci_info_str = qla24xx_pci_info_str, 1793 .fw_version_str = qla24xx_fw_version_str, 1794 .intr_handler = qla24xx_intr_handler, 1795 .enable_intrs = qla24xx_enable_intrs, 1796 .disable_intrs = qla24xx_disable_intrs, 1797 .abort_command = qla24xx_abort_command, 1798 .target_reset = qla24xx_abort_target, 1799 .lun_reset = qla24xx_lun_reset, 1800 .fabric_login = qla24xx_login_fabric, 1801 .fabric_logout = qla24xx_fabric_logout, 1802 .calc_req_entries = NULL, 1803 .build_iocbs = NULL, 1804 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1806 .read_nvram = qla24xx_read_nvram_data, 1807 .write_nvram = qla24xx_write_nvram_data, 1808 .fw_dump = qla24xx_fw_dump, 1809 .beacon_on = qla24xx_beacon_on, 1810 .beacon_off = qla24xx_beacon_off, 1811 .beacon_blink = qla24xx_beacon_blink, 1812 .read_optrom = qla24xx_read_optrom_data, 1813 .write_optrom = qla24xx_write_optrom_data, 1814 .get_flash_version = qla24xx_get_flash_version, 1815 .start_scsi = qla24xx_start_scsi, 1816 .abort_isp = qla2x00_abort_isp, 1817 .iospace_config = qla2x00_iospace_config, 1818 .initialize_adapter = qla2x00_initialize_adapter, 1819 }; 1820 1821 static struct isp_operations qla25xx_isp_ops = { 1822 .pci_config = qla25xx_pci_config, 1823 .reset_chip = qla24xx_reset_chip, 1824 .chip_diag = qla24xx_chip_diag, 1825 .config_rings = qla24xx_config_rings, 1826 .reset_adapter = qla24xx_reset_adapter, 1827 .nvram_config = qla24xx_nvram_config, 1828 .update_fw_options = qla24xx_update_fw_options, 1829 .load_risc = qla24xx_load_risc, 1830 .pci_info_str = qla24xx_pci_info_str, 1831 .fw_version_str = qla24xx_fw_version_str, 1832 .intr_handler = qla24xx_intr_handler, 1833 .enable_intrs = qla24xx_enable_intrs, 1834 .disable_intrs = qla24xx_disable_intrs, 1835 .abort_command = qla24xx_abort_command, 1836 .target_reset = qla24xx_abort_target, 1837 .lun_reset = qla24xx_lun_reset, 1838 .fabric_login = qla24xx_login_fabric, 1839 .fabric_logout = qla24xx_fabric_logout, 1840 .calc_req_entries = NULL, 1841 .build_iocbs = NULL, 1842 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1844 .read_nvram = qla25xx_read_nvram_data, 1845 .write_nvram = qla25xx_write_nvram_data, 1846 .fw_dump = qla25xx_fw_dump, 1847 .beacon_on = qla24xx_beacon_on, 1848 .beacon_off = qla24xx_beacon_off, 1849 .beacon_blink = qla24xx_beacon_blink, 1850 .read_optrom = qla25xx_read_optrom_data, 1851 .write_optrom = qla24xx_write_optrom_data, 1852 .get_flash_version = qla24xx_get_flash_version, 1853 .start_scsi = qla24xx_dif_start_scsi, 1854 .abort_isp = qla2x00_abort_isp, 1855 .iospace_config = qla2x00_iospace_config, 1856 .initialize_adapter = qla2x00_initialize_adapter, 1857 }; 1858 1859 static struct isp_operations qla81xx_isp_ops = { 1860 .pci_config = qla25xx_pci_config, 1861 .reset_chip = qla24xx_reset_chip, 1862 .chip_diag = qla24xx_chip_diag, 1863 .config_rings = qla24xx_config_rings, 1864 .reset_adapter = qla24xx_reset_adapter, 1865 .nvram_config = qla81xx_nvram_config, 1866 .update_fw_options = qla81xx_update_fw_options, 1867 .load_risc = qla81xx_load_risc, 1868 .pci_info_str = qla24xx_pci_info_str, 1869 .fw_version_str = qla24xx_fw_version_str, 1870 .intr_handler = qla24xx_intr_handler, 1871 .enable_intrs = qla24xx_enable_intrs, 1872 .disable_intrs = qla24xx_disable_intrs, 1873 .abort_command = qla24xx_abort_command, 1874 .target_reset = qla24xx_abort_target, 1875 .lun_reset = qla24xx_lun_reset, 1876 .fabric_login = qla24xx_login_fabric, 1877 .fabric_logout = qla24xx_fabric_logout, 1878 .calc_req_entries = NULL, 1879 .build_iocbs = NULL, 1880 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1882 .read_nvram = NULL, 1883 .write_nvram = NULL, 1884 .fw_dump = qla81xx_fw_dump, 1885 .beacon_on = qla24xx_beacon_on, 1886 .beacon_off = qla24xx_beacon_off, 1887 .beacon_blink = qla83xx_beacon_blink, 1888 .read_optrom = qla25xx_read_optrom_data, 1889 .write_optrom = qla24xx_write_optrom_data, 1890 .get_flash_version = qla24xx_get_flash_version, 1891 .start_scsi = qla24xx_dif_start_scsi, 1892 .abort_isp = qla2x00_abort_isp, 1893 .iospace_config = qla2x00_iospace_config, 1894 .initialize_adapter = qla2x00_initialize_adapter, 1895 }; 1896 1897 static struct isp_operations qla82xx_isp_ops = { 1898 .pci_config = qla82xx_pci_config, 1899 .reset_chip = qla82xx_reset_chip, 1900 .chip_diag = qla24xx_chip_diag, 1901 .config_rings = qla82xx_config_rings, 1902 .reset_adapter = qla24xx_reset_adapter, 1903 .nvram_config = qla81xx_nvram_config, 1904 .update_fw_options = qla24xx_update_fw_options, 1905 .load_risc = qla82xx_load_risc, 1906 .pci_info_str = qla24xx_pci_info_str, 1907 .fw_version_str = qla24xx_fw_version_str, 1908 .intr_handler = qla82xx_intr_handler, 1909 .enable_intrs = qla82xx_enable_intrs, 1910 .disable_intrs = qla82xx_disable_intrs, 1911 .abort_command = qla24xx_abort_command, 1912 .target_reset = qla24xx_abort_target, 1913 .lun_reset = qla24xx_lun_reset, 1914 .fabric_login = qla24xx_login_fabric, 1915 .fabric_logout = qla24xx_fabric_logout, 1916 .calc_req_entries = NULL, 1917 .build_iocbs = NULL, 1918 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1920 .read_nvram = qla24xx_read_nvram_data, 1921 .write_nvram = qla24xx_write_nvram_data, 1922 .fw_dump = qla82xx_fw_dump, 1923 .beacon_on = qla82xx_beacon_on, 1924 .beacon_off = qla82xx_beacon_off, 1925 .beacon_blink = NULL, 1926 .read_optrom = qla82xx_read_optrom_data, 1927 .write_optrom = qla82xx_write_optrom_data, 1928 .get_flash_version = qla82xx_get_flash_version, 1929 .start_scsi = qla82xx_start_scsi, 1930 .abort_isp = qla82xx_abort_isp, 1931 .iospace_config = qla82xx_iospace_config, 1932 .initialize_adapter = qla2x00_initialize_adapter, 1933 }; 1934 1935 static struct isp_operations qla8044_isp_ops = { 1936 .pci_config = qla82xx_pci_config, 1937 .reset_chip = qla82xx_reset_chip, 1938 .chip_diag = qla24xx_chip_diag, 1939 .config_rings = qla82xx_config_rings, 1940 .reset_adapter = qla24xx_reset_adapter, 1941 .nvram_config = qla81xx_nvram_config, 1942 .update_fw_options = qla24xx_update_fw_options, 1943 .load_risc = qla82xx_load_risc, 1944 .pci_info_str = qla24xx_pci_info_str, 1945 .fw_version_str = qla24xx_fw_version_str, 1946 .intr_handler = qla8044_intr_handler, 1947 .enable_intrs = qla82xx_enable_intrs, 1948 .disable_intrs = qla82xx_disable_intrs, 1949 .abort_command = qla24xx_abort_command, 1950 .target_reset = qla24xx_abort_target, 1951 .lun_reset = qla24xx_lun_reset, 1952 .fabric_login = qla24xx_login_fabric, 1953 .fabric_logout = qla24xx_fabric_logout, 1954 .calc_req_entries = NULL, 1955 .build_iocbs = NULL, 1956 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1958 .read_nvram = NULL, 1959 .write_nvram = NULL, 1960 .fw_dump = qla8044_fw_dump, 1961 .beacon_on = qla82xx_beacon_on, 1962 .beacon_off = qla82xx_beacon_off, 1963 .beacon_blink = NULL, 1964 .read_optrom = qla8044_read_optrom_data, 1965 .write_optrom = qla8044_write_optrom_data, 1966 .get_flash_version = qla82xx_get_flash_version, 1967 .start_scsi = qla82xx_start_scsi, 1968 .abort_isp = qla8044_abort_isp, 1969 .iospace_config = qla82xx_iospace_config, 1970 .initialize_adapter = qla2x00_initialize_adapter, 1971 }; 1972 1973 static struct isp_operations qla83xx_isp_ops = { 1974 .pci_config = qla25xx_pci_config, 1975 .reset_chip = qla24xx_reset_chip, 1976 .chip_diag = qla24xx_chip_diag, 1977 .config_rings = qla24xx_config_rings, 1978 .reset_adapter = qla24xx_reset_adapter, 1979 .nvram_config = qla81xx_nvram_config, 1980 .update_fw_options = qla81xx_update_fw_options, 1981 .load_risc = qla81xx_load_risc, 1982 .pci_info_str = qla24xx_pci_info_str, 1983 .fw_version_str = qla24xx_fw_version_str, 1984 .intr_handler = qla24xx_intr_handler, 1985 .enable_intrs = qla24xx_enable_intrs, 1986 .disable_intrs = qla24xx_disable_intrs, 1987 .abort_command = qla24xx_abort_command, 1988 .target_reset = qla24xx_abort_target, 1989 .lun_reset = qla24xx_lun_reset, 1990 .fabric_login = qla24xx_login_fabric, 1991 .fabric_logout = qla24xx_fabric_logout, 1992 .calc_req_entries = NULL, 1993 .build_iocbs = NULL, 1994 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1996 .read_nvram = NULL, 1997 .write_nvram = NULL, 1998 .fw_dump = qla83xx_fw_dump, 1999 .beacon_on = qla24xx_beacon_on, 2000 .beacon_off = qla24xx_beacon_off, 2001 .beacon_blink = qla83xx_beacon_blink, 2002 .read_optrom = qla25xx_read_optrom_data, 2003 .write_optrom = qla24xx_write_optrom_data, 2004 .get_flash_version = qla24xx_get_flash_version, 2005 .start_scsi = qla24xx_dif_start_scsi, 2006 .abort_isp = qla2x00_abort_isp, 2007 .iospace_config = qla83xx_iospace_config, 2008 .initialize_adapter = qla2x00_initialize_adapter, 2009 }; 2010 2011 static struct isp_operations qlafx00_isp_ops = { 2012 .pci_config = qlafx00_pci_config, 2013 .reset_chip = qlafx00_soft_reset, 2014 .chip_diag = qlafx00_chip_diag, 2015 .config_rings = qlafx00_config_rings, 2016 .reset_adapter = qlafx00_soft_reset, 2017 .nvram_config = NULL, 2018 .update_fw_options = NULL, 2019 .load_risc = NULL, 2020 .pci_info_str = qlafx00_pci_info_str, 2021 .fw_version_str = qlafx00_fw_version_str, 2022 .intr_handler = qlafx00_intr_handler, 2023 .enable_intrs = qlafx00_enable_intrs, 2024 .disable_intrs = qlafx00_disable_intrs, 2025 .abort_command = qla24xx_async_abort_command, 2026 .target_reset = qlafx00_abort_target, 2027 .lun_reset = qlafx00_lun_reset, 2028 .fabric_login = NULL, 2029 .fabric_logout = NULL, 2030 .calc_req_entries = NULL, 2031 .build_iocbs = NULL, 2032 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2034 .read_nvram = qla24xx_read_nvram_data, 2035 .write_nvram = qla24xx_write_nvram_data, 2036 .fw_dump = NULL, 2037 .beacon_on = qla24xx_beacon_on, 2038 .beacon_off = qla24xx_beacon_off, 2039 .beacon_blink = NULL, 2040 .read_optrom = qla24xx_read_optrom_data, 2041 .write_optrom = qla24xx_write_optrom_data, 2042 .get_flash_version = qla24xx_get_flash_version, 2043 .start_scsi = qlafx00_start_scsi, 2044 .abort_isp = qlafx00_abort_isp, 2045 .iospace_config = qlafx00_iospace_config, 2046 .initialize_adapter = qlafx00_initialize_adapter, 2047 }; 2048 2049 static struct isp_operations qla27xx_isp_ops = { 2050 .pci_config = qla25xx_pci_config, 2051 .reset_chip = qla24xx_reset_chip, 2052 .chip_diag = qla24xx_chip_diag, 2053 .config_rings = qla24xx_config_rings, 2054 .reset_adapter = qla24xx_reset_adapter, 2055 .nvram_config = qla81xx_nvram_config, 2056 .update_fw_options = qla81xx_update_fw_options, 2057 .load_risc = qla81xx_load_risc, 2058 .pci_info_str = qla24xx_pci_info_str, 2059 .fw_version_str = qla24xx_fw_version_str, 2060 .intr_handler = qla24xx_intr_handler, 2061 .enable_intrs = qla24xx_enable_intrs, 2062 .disable_intrs = qla24xx_disable_intrs, 2063 .abort_command = qla24xx_abort_command, 2064 .target_reset = qla24xx_abort_target, 2065 .lun_reset = qla24xx_lun_reset, 2066 .fabric_login = qla24xx_login_fabric, 2067 .fabric_logout = qla24xx_fabric_logout, 2068 .calc_req_entries = NULL, 2069 .build_iocbs = NULL, 2070 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2072 .read_nvram = NULL, 2073 .write_nvram = NULL, 2074 .fw_dump = qla27xx_fwdump, 2075 .beacon_on = qla24xx_beacon_on, 2076 .beacon_off = qla24xx_beacon_off, 2077 .beacon_blink = qla83xx_beacon_blink, 2078 .read_optrom = qla25xx_read_optrom_data, 2079 .write_optrom = qla24xx_write_optrom_data, 2080 .get_flash_version = qla24xx_get_flash_version, 2081 .start_scsi = qla24xx_dif_start_scsi, 2082 .abort_isp = qla2x00_abort_isp, 2083 .iospace_config = qla83xx_iospace_config, 2084 .initialize_adapter = qla2x00_initialize_adapter, 2085 }; 2086 2087 static inline void 2088 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2089 { 2090 ha->device_type = DT_EXTENDED_IDS; 2091 switch (ha->pdev->device) { 2092 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2093 ha->device_type |= DT_ISP2100; 2094 ha->device_type &= ~DT_EXTENDED_IDS; 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2096 break; 2097 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2098 ha->device_type |= DT_ISP2200; 2099 ha->device_type &= ~DT_EXTENDED_IDS; 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2101 break; 2102 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2103 ha->device_type |= DT_ISP2300; 2104 ha->device_type |= DT_ZIO_SUPPORTED; 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2106 break; 2107 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2108 ha->device_type |= DT_ISP2312; 2109 ha->device_type |= DT_ZIO_SUPPORTED; 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2111 break; 2112 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2113 ha->device_type |= DT_ISP2322; 2114 ha->device_type |= DT_ZIO_SUPPORTED; 2115 if (ha->pdev->subsystem_vendor == 0x1028 && 2116 ha->pdev->subsystem_device == 0x0170) 2117 ha->device_type |= DT_OEM_001; 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2119 break; 2120 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2121 ha->device_type |= DT_ISP6312; 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2123 break; 2124 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2125 ha->device_type |= DT_ISP6322; 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2127 break; 2128 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2129 ha->device_type |= DT_ISP2422; 2130 ha->device_type |= DT_ZIO_SUPPORTED; 2131 ha->device_type |= DT_FWI2; 2132 ha->device_type |= DT_IIDMA; 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2134 break; 2135 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2136 ha->device_type |= DT_ISP2432; 2137 ha->device_type |= DT_ZIO_SUPPORTED; 2138 ha->device_type |= DT_FWI2; 2139 ha->device_type |= DT_IIDMA; 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2141 break; 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2143 ha->device_type |= DT_ISP8432; 2144 ha->device_type |= DT_ZIO_SUPPORTED; 2145 ha->device_type |= DT_FWI2; 2146 ha->device_type |= DT_IIDMA; 2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2148 break; 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2150 ha->device_type |= DT_ISP5422; 2151 ha->device_type |= DT_FWI2; 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2153 break; 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2155 ha->device_type |= DT_ISP5432; 2156 ha->device_type |= DT_FWI2; 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2158 break; 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2160 ha->device_type |= DT_ISP2532; 2161 ha->device_type |= DT_ZIO_SUPPORTED; 2162 ha->device_type |= DT_FWI2; 2163 ha->device_type |= DT_IIDMA; 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2165 break; 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2167 ha->device_type |= DT_ISP8001; 2168 ha->device_type |= DT_ZIO_SUPPORTED; 2169 ha->device_type |= DT_FWI2; 2170 ha->device_type |= DT_IIDMA; 2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2172 break; 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2174 ha->device_type |= DT_ISP8021; 2175 ha->device_type |= DT_ZIO_SUPPORTED; 2176 ha->device_type |= DT_FWI2; 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2178 /* Initialize 82XX ISP flags */ 2179 qla82xx_init_flags(ha); 2180 break; 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2182 ha->device_type |= DT_ISP8044; 2183 ha->device_type |= DT_ZIO_SUPPORTED; 2184 ha->device_type |= DT_FWI2; 2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2186 /* Initialize 82XX ISP flags */ 2187 qla82xx_init_flags(ha); 2188 break; 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2190 ha->device_type |= DT_ISP2031; 2191 ha->device_type |= DT_ZIO_SUPPORTED; 2192 ha->device_type |= DT_FWI2; 2193 ha->device_type |= DT_IIDMA; 2194 ha->device_type |= DT_T10_PI; 2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2196 break; 2197 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2198 ha->device_type |= DT_ISP8031; 2199 ha->device_type |= DT_ZIO_SUPPORTED; 2200 ha->device_type |= DT_FWI2; 2201 ha->device_type |= DT_IIDMA; 2202 ha->device_type |= DT_T10_PI; 2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2204 break; 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2206 ha->device_type |= DT_ISPFX00; 2207 break; 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2209 ha->device_type |= DT_ISP2071; 2210 ha->device_type |= DT_ZIO_SUPPORTED; 2211 ha->device_type |= DT_FWI2; 2212 ha->device_type |= DT_IIDMA; 2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2214 break; 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2216 ha->device_type |= DT_ISP2271; 2217 ha->device_type |= DT_ZIO_SUPPORTED; 2218 ha->device_type |= DT_FWI2; 2219 ha->device_type |= DT_IIDMA; 2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2221 break; 2222 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2223 ha->device_type |= DT_ISP2261; 2224 ha->device_type |= DT_ZIO_SUPPORTED; 2225 ha->device_type |= DT_FWI2; 2226 ha->device_type |= DT_IIDMA; 2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2228 break; 2229 } 2230 2231 if (IS_QLA82XX(ha)) 2232 ha->port_no = ha->portnum & 1; 2233 else { 2234 /* Get adapter physical port no from interrupt pin register. */ 2235 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2236 if (IS_QLA27XX(ha)) 2237 ha->port_no--; 2238 else 2239 ha->port_no = !(ha->port_no & 1); 2240 } 2241 2242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2243 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2244 ha->device_type, ha->port_no, ha->fw_srisc_address); 2245 } 2246 2247 static void 2248 qla2xxx_scan_start(struct Scsi_Host *shost) 2249 { 2250 scsi_qla_host_t *vha = shost_priv(shost); 2251 2252 if (vha->hw->flags.running_gold_fw) 2253 return; 2254 2255 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2256 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2257 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2258 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2259 } 2260 2261 static int 2262 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2263 { 2264 scsi_qla_host_t *vha = shost_priv(shost); 2265 2266 if (!vha->host) 2267 return 1; 2268 if (time > vha->hw->loop_reset_delay * HZ) 2269 return 1; 2270 2271 return atomic_read(&vha->loop_state) == LOOP_READY; 2272 } 2273 2274 /* 2275 * PCI driver interface 2276 */ 2277 static int 2278 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2279 { 2280 int ret = -ENODEV; 2281 struct Scsi_Host *host; 2282 scsi_qla_host_t *base_vha = NULL; 2283 struct qla_hw_data *ha; 2284 char pci_info[30]; 2285 char fw_str[30], wq_name[30]; 2286 struct scsi_host_template *sht; 2287 int bars, mem_only = 0; 2288 uint16_t req_length = 0, rsp_length = 0; 2289 struct req_que *req = NULL; 2290 struct rsp_que *rsp = NULL; 2291 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2292 sht = &qla2xxx_driver_template; 2293 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2301 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2302 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2303 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2304 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2305 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2306 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2307 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2308 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2309 mem_only = 1; 2310 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2311 "Mem only adapter.\n"); 2312 } 2313 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2314 "Bars=%d.\n", bars); 2315 2316 if (mem_only) { 2317 if (pci_enable_device_mem(pdev)) 2318 goto probe_out; 2319 } else { 2320 if (pci_enable_device(pdev)) 2321 goto probe_out; 2322 } 2323 2324 /* This may fail but that's ok */ 2325 pci_enable_pcie_error_reporting(pdev); 2326 2327 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2328 if (!ha) { 2329 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2330 "Unable to allocate memory for ha.\n"); 2331 goto probe_out; 2332 } 2333 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2334 "Memory allocated for ha=%p.\n", ha); 2335 ha->pdev = pdev; 2336 ha->tgt.enable_class_2 = ql2xenableclass2; 2337 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2338 spin_lock_init(&ha->tgt.q_full_lock); 2339 spin_lock_init(&ha->tgt.sess_lock); 2340 spin_lock_init(&ha->tgt.atio_lock); 2341 2342 2343 /* Clear our data area */ 2344 ha->bars = bars; 2345 ha->mem_only = mem_only; 2346 spin_lock_init(&ha->hardware_lock); 2347 spin_lock_init(&ha->vport_slock); 2348 mutex_init(&ha->selflogin_lock); 2349 mutex_init(&ha->optrom_mutex); 2350 2351 /* Set ISP-type information. */ 2352 qla2x00_set_isp_flags(ha); 2353 2354 /* Set EEH reset type to fundamental if required by hba */ 2355 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2356 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2357 pdev->needs_freset = 1; 2358 2359 ha->prev_topology = 0; 2360 ha->init_cb_size = sizeof(init_cb_t); 2361 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2362 ha->optrom_size = OPTROM_SIZE_2300; 2363 2364 /* Assign ISP specific operations. */ 2365 if (IS_QLA2100(ha)) { 2366 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2367 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2368 req_length = REQUEST_ENTRY_CNT_2100; 2369 rsp_length = RESPONSE_ENTRY_CNT_2100; 2370 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2371 ha->gid_list_info_size = 4; 2372 ha->flash_conf_off = ~0; 2373 ha->flash_data_off = ~0; 2374 ha->nvram_conf_off = ~0; 2375 ha->nvram_data_off = ~0; 2376 ha->isp_ops = &qla2100_isp_ops; 2377 } else if (IS_QLA2200(ha)) { 2378 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2379 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2380 req_length = REQUEST_ENTRY_CNT_2200; 2381 rsp_length = RESPONSE_ENTRY_CNT_2100; 2382 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2383 ha->gid_list_info_size = 4; 2384 ha->flash_conf_off = ~0; 2385 ha->flash_data_off = ~0; 2386 ha->nvram_conf_off = ~0; 2387 ha->nvram_data_off = ~0; 2388 ha->isp_ops = &qla2100_isp_ops; 2389 } else if (IS_QLA23XX(ha)) { 2390 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2391 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2392 req_length = REQUEST_ENTRY_CNT_2200; 2393 rsp_length = RESPONSE_ENTRY_CNT_2300; 2394 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2395 ha->gid_list_info_size = 6; 2396 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2397 ha->optrom_size = OPTROM_SIZE_2322; 2398 ha->flash_conf_off = ~0; 2399 ha->flash_data_off = ~0; 2400 ha->nvram_conf_off = ~0; 2401 ha->nvram_data_off = ~0; 2402 ha->isp_ops = &qla2300_isp_ops; 2403 } else if (IS_QLA24XX_TYPE(ha)) { 2404 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2405 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2406 req_length = REQUEST_ENTRY_CNT_24XX; 2407 rsp_length = RESPONSE_ENTRY_CNT_2300; 2408 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2409 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2410 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2411 ha->gid_list_info_size = 8; 2412 ha->optrom_size = OPTROM_SIZE_24XX; 2413 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2414 ha->isp_ops = &qla24xx_isp_ops; 2415 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2416 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2417 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2418 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2419 } else if (IS_QLA25XX(ha)) { 2420 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2421 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2422 req_length = REQUEST_ENTRY_CNT_24XX; 2423 rsp_length = RESPONSE_ENTRY_CNT_2300; 2424 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2425 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2426 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2427 ha->gid_list_info_size = 8; 2428 ha->optrom_size = OPTROM_SIZE_25XX; 2429 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2430 ha->isp_ops = &qla25xx_isp_ops; 2431 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2432 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2433 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2434 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2435 } else if (IS_QLA81XX(ha)) { 2436 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2437 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2438 req_length = REQUEST_ENTRY_CNT_24XX; 2439 rsp_length = RESPONSE_ENTRY_CNT_2300; 2440 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2441 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2442 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2443 ha->gid_list_info_size = 8; 2444 ha->optrom_size = OPTROM_SIZE_81XX; 2445 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2446 ha->isp_ops = &qla81xx_isp_ops; 2447 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2448 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2449 ha->nvram_conf_off = ~0; 2450 ha->nvram_data_off = ~0; 2451 } else if (IS_QLA82XX(ha)) { 2452 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2453 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2454 req_length = REQUEST_ENTRY_CNT_82XX; 2455 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2456 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2457 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2458 ha->gid_list_info_size = 8; 2459 ha->optrom_size = OPTROM_SIZE_82XX; 2460 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2461 ha->isp_ops = &qla82xx_isp_ops; 2462 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2463 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2464 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2465 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2466 } else if (IS_QLA8044(ha)) { 2467 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2468 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2469 req_length = REQUEST_ENTRY_CNT_82XX; 2470 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2471 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2472 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2473 ha->gid_list_info_size = 8; 2474 ha->optrom_size = OPTROM_SIZE_83XX; 2475 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2476 ha->isp_ops = &qla8044_isp_ops; 2477 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2478 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2479 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2480 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2481 } else if (IS_QLA83XX(ha)) { 2482 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2483 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2484 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2485 req_length = REQUEST_ENTRY_CNT_83XX; 2486 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2487 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2488 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2489 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2490 ha->gid_list_info_size = 8; 2491 ha->optrom_size = OPTROM_SIZE_83XX; 2492 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2493 ha->isp_ops = &qla83xx_isp_ops; 2494 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2495 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2496 ha->nvram_conf_off = ~0; 2497 ha->nvram_data_off = ~0; 2498 } else if (IS_QLAFX00(ha)) { 2499 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2500 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2501 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2502 req_length = REQUEST_ENTRY_CNT_FX00; 2503 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2504 ha->isp_ops = &qlafx00_isp_ops; 2505 ha->port_down_retry_count = 30; /* default value */ 2506 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2507 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2508 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2509 ha->mr.fw_hbt_en = 1; 2510 ha->mr.host_info_resend = false; 2511 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2512 } else if (IS_QLA27XX(ha)) { 2513 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2514 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2515 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2516 req_length = REQUEST_ENTRY_CNT_83XX; 2517 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2518 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2519 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2520 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2521 ha->gid_list_info_size = 8; 2522 ha->optrom_size = OPTROM_SIZE_83XX; 2523 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2524 ha->isp_ops = &qla27xx_isp_ops; 2525 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2526 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2527 ha->nvram_conf_off = ~0; 2528 ha->nvram_data_off = ~0; 2529 } 2530 2531 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2532 "mbx_count=%d, req_length=%d, " 2533 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2534 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2535 "max_fibre_devices=%d.\n", 2536 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2537 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2538 ha->nvram_npiv_size, ha->max_fibre_devices); 2539 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2540 "isp_ops=%p, flash_conf_off=%d, " 2541 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2542 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2543 ha->nvram_conf_off, ha->nvram_data_off); 2544 2545 /* Configure PCI I/O space */ 2546 ret = ha->isp_ops->iospace_config(ha); 2547 if (ret) 2548 goto iospace_config_failed; 2549 2550 ql_log_pci(ql_log_info, pdev, 0x001d, 2551 "Found an ISP%04X irq %d iobase 0x%p.\n", 2552 pdev->device, pdev->irq, ha->iobase); 2553 mutex_init(&ha->vport_lock); 2554 init_completion(&ha->mbx_cmd_comp); 2555 complete(&ha->mbx_cmd_comp); 2556 init_completion(&ha->mbx_intr_comp); 2557 init_completion(&ha->dcbx_comp); 2558 init_completion(&ha->lb_portup_comp); 2559 2560 set_bit(0, (unsigned long *) ha->vp_idx_map); 2561 2562 qla2x00_config_dma_addressing(ha); 2563 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2564 "64 Bit addressing is %s.\n", 2565 ha->flags.enable_64bit_addressing ? "enable" : 2566 "disable"); 2567 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2568 if (ret) { 2569 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2570 "Failed to allocate memory for adapter, aborting.\n"); 2571 2572 goto probe_hw_failed; 2573 } 2574 2575 req->max_q_depth = MAX_Q_DEPTH; 2576 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2577 req->max_q_depth = ql2xmaxqdepth; 2578 2579 2580 base_vha = qla2x00_create_host(sht, ha); 2581 if (!base_vha) { 2582 ret = -ENOMEM; 2583 qla2x00_mem_free(ha); 2584 qla2x00_free_req_que(ha, req); 2585 qla2x00_free_rsp_que(ha, rsp); 2586 goto probe_hw_failed; 2587 } 2588 2589 pci_set_drvdata(pdev, base_vha); 2590 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2591 2592 host = base_vha->host; 2593 base_vha->req = req; 2594 if (IS_QLA2XXX_MIDTYPE(ha)) 2595 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2596 else 2597 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2598 base_vha->vp_idx; 2599 2600 /* Setup fcport template structure. */ 2601 ha->mr.fcport.vha = base_vha; 2602 ha->mr.fcport.port_type = FCT_UNKNOWN; 2603 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2604 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2605 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2606 ha->mr.fcport.scan_state = 1; 2607 2608 /* Set the SG table size based on ISP type */ 2609 if (!IS_FWI2_CAPABLE(ha)) { 2610 if (IS_QLA2100(ha)) 2611 host->sg_tablesize = 32; 2612 } else { 2613 if (!IS_QLA82XX(ha)) 2614 host->sg_tablesize = QLA_SG_ALL; 2615 } 2616 host->max_id = ha->max_fibre_devices; 2617 host->cmd_per_lun = 3; 2618 host->unique_id = host->host_no; 2619 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2620 host->max_cmd_len = 32; 2621 else 2622 host->max_cmd_len = MAX_CMDSZ; 2623 host->max_channel = MAX_BUSES - 1; 2624 /* Older HBAs support only 16-bit LUNs */ 2625 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2626 ql2xmaxlun > 0xffff) 2627 host->max_lun = 0xffff; 2628 else 2629 host->max_lun = ql2xmaxlun; 2630 host->transportt = qla2xxx_transport_template; 2631 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2632 2633 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2634 "max_id=%d this_id=%d " 2635 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2636 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2637 host->this_id, host->cmd_per_lun, host->unique_id, 2638 host->max_cmd_len, host->max_channel, host->max_lun, 2639 host->transportt, sht->vendor_id); 2640 2641 que_init: 2642 /* Alloc arrays of request and response ring ptrs */ 2643 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2644 ql_log(ql_log_fatal, base_vha, 0x003d, 2645 "Failed to allocate memory for queue pointers..." 2646 "aborting.\n"); 2647 goto probe_init_failed; 2648 } 2649 2650 qlt_probe_one_stage1(base_vha, ha); 2651 2652 /* Set up the irqs */ 2653 ret = qla2x00_request_irqs(ha, rsp); 2654 if (ret) 2655 goto probe_init_failed; 2656 2657 pci_save_state(pdev); 2658 2659 /* Assign back pointers */ 2660 rsp->req = req; 2661 req->rsp = rsp; 2662 2663 if (IS_QLAFX00(ha)) { 2664 ha->rsp_q_map[0] = rsp; 2665 ha->req_q_map[0] = req; 2666 set_bit(0, ha->req_qid_map); 2667 set_bit(0, ha->rsp_qid_map); 2668 } 2669 2670 /* FWI2-capable only. */ 2671 req->req_q_in = &ha->iobase->isp24.req_q_in; 2672 req->req_q_out = &ha->iobase->isp24.req_q_out; 2673 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2674 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2675 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2676 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2677 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2678 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2679 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2680 } 2681 2682 if (IS_QLAFX00(ha)) { 2683 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2684 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2685 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2686 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2687 } 2688 2689 if (IS_P3P_TYPE(ha)) { 2690 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2691 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2692 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2693 } 2694 2695 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2696 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2697 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2698 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2699 "req->req_q_in=%p req->req_q_out=%p " 2700 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2701 req->req_q_in, req->req_q_out, 2702 rsp->rsp_q_in, rsp->rsp_q_out); 2703 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2704 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2705 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2706 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2707 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2708 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2709 2710 if (ha->isp_ops->initialize_adapter(base_vha)) { 2711 ql_log(ql_log_fatal, base_vha, 0x00d6, 2712 "Failed to initialize adapter - Adapter flags %x.\n", 2713 base_vha->device_flags); 2714 2715 if (IS_QLA82XX(ha)) { 2716 qla82xx_idc_lock(ha); 2717 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2718 QLA8XXX_DEV_FAILED); 2719 qla82xx_idc_unlock(ha); 2720 ql_log(ql_log_fatal, base_vha, 0x00d7, 2721 "HW State: FAILED.\n"); 2722 } else if (IS_QLA8044(ha)) { 2723 qla8044_idc_lock(ha); 2724 qla8044_wr_direct(base_vha, 2725 QLA8044_CRB_DEV_STATE_INDEX, 2726 QLA8XXX_DEV_FAILED); 2727 qla8044_idc_unlock(ha); 2728 ql_log(ql_log_fatal, base_vha, 0x0150, 2729 "HW State: FAILED.\n"); 2730 } 2731 2732 ret = -ENODEV; 2733 goto probe_failed; 2734 } 2735 2736 if (IS_QLAFX00(ha)) 2737 host->can_queue = QLAFX00_MAX_CANQUEUE; 2738 else 2739 host->can_queue = req->num_outstanding_cmds - 10; 2740 2741 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2742 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2743 host->can_queue, base_vha->req, 2744 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2745 2746 if (ha->mqenable) { 2747 if (qla25xx_setup_mode(base_vha)) { 2748 ql_log(ql_log_warn, base_vha, 0x00ec, 2749 "Failed to create queues, falling back to single queue mode.\n"); 2750 goto que_init; 2751 } 2752 } 2753 2754 if (ha->flags.running_gold_fw) 2755 goto skip_dpc; 2756 2757 /* 2758 * Startup the kernel thread for this host adapter 2759 */ 2760 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2761 "%s_dpc", base_vha->host_str); 2762 if (IS_ERR(ha->dpc_thread)) { 2763 ql_log(ql_log_fatal, base_vha, 0x00ed, 2764 "Failed to start DPC thread.\n"); 2765 ret = PTR_ERR(ha->dpc_thread); 2766 goto probe_failed; 2767 } 2768 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2769 "DPC thread started successfully.\n"); 2770 2771 /* 2772 * If we're not coming up in initiator mode, we might sit for 2773 * a while without waking up the dpc thread, which leads to a 2774 * stuck process warning. So just kick the dpc once here and 2775 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2776 */ 2777 qla2xxx_wake_dpc(base_vha); 2778 2779 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2780 2781 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2782 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2783 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2784 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2785 2786 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2787 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2788 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2789 INIT_WORK(&ha->idc_state_handler, 2790 qla83xx_idc_state_handler_work); 2791 INIT_WORK(&ha->nic_core_unrecoverable, 2792 qla83xx_nic_core_unrecoverable_work); 2793 } 2794 2795 skip_dpc: 2796 list_add_tail(&base_vha->list, &ha->vp_list); 2797 base_vha->host->irq = ha->pdev->irq; 2798 2799 /* Initialized the timer */ 2800 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2801 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2802 "Started qla2x00_timer with " 2803 "interval=%d.\n", WATCH_INTERVAL); 2804 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2805 "Detected hba at address=%p.\n", 2806 ha); 2807 2808 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2809 if (ha->fw_attributes & BIT_4) { 2810 int prot = 0, guard; 2811 base_vha->flags.difdix_supported = 1; 2812 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2813 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2814 if (ql2xenabledif == 1) 2815 prot = SHOST_DIX_TYPE0_PROTECTION; 2816 scsi_host_set_prot(host, 2817 prot | SHOST_DIF_TYPE1_PROTECTION 2818 | SHOST_DIF_TYPE2_PROTECTION 2819 | SHOST_DIF_TYPE3_PROTECTION 2820 | SHOST_DIX_TYPE1_PROTECTION 2821 | SHOST_DIX_TYPE2_PROTECTION 2822 | SHOST_DIX_TYPE3_PROTECTION); 2823 2824 guard = SHOST_DIX_GUARD_CRC; 2825 2826 if (IS_PI_IPGUARD_CAPABLE(ha) && 2827 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2828 guard |= SHOST_DIX_GUARD_IP; 2829 2830 scsi_host_set_guard(host, guard); 2831 } else 2832 base_vha->flags.difdix_supported = 0; 2833 } 2834 2835 ha->isp_ops->enable_intrs(ha); 2836 2837 if (IS_QLAFX00(ha)) { 2838 ret = qlafx00_fx_disc(base_vha, 2839 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2840 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2841 QLA_SG_ALL : 128; 2842 } 2843 2844 ret = scsi_add_host(host, &pdev->dev); 2845 if (ret) 2846 goto probe_failed; 2847 2848 base_vha->flags.init_done = 1; 2849 base_vha->flags.online = 1; 2850 ha->prev_minidump_failed = 0; 2851 2852 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2853 "Init done and hba is online.\n"); 2854 2855 if (qla_ini_mode_enabled(base_vha)) 2856 scsi_scan_host(host); 2857 else 2858 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2859 "skipping scsi_scan_host() for non-initiator port\n"); 2860 2861 qla2x00_alloc_sysfs_attr(base_vha); 2862 2863 if (IS_QLAFX00(ha)) { 2864 ret = qlafx00_fx_disc(base_vha, 2865 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2866 2867 /* Register system information */ 2868 ret = qlafx00_fx_disc(base_vha, 2869 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2870 } 2871 2872 qla2x00_init_host_attr(base_vha); 2873 2874 qla2x00_dfs_setup(base_vha); 2875 2876 ql_log(ql_log_info, base_vha, 0x00fb, 2877 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2878 ql_log(ql_log_info, base_vha, 0x00fc, 2879 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2880 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2881 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2882 base_vha->host_no, 2883 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 2884 2885 qlt_add_target(ha, base_vha); 2886 2887 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2888 return 0; 2889 2890 probe_init_failed: 2891 qla2x00_free_req_que(ha, req); 2892 ha->req_q_map[0] = NULL; 2893 clear_bit(0, ha->req_qid_map); 2894 qla2x00_free_rsp_que(ha, rsp); 2895 ha->rsp_q_map[0] = NULL; 2896 clear_bit(0, ha->rsp_qid_map); 2897 ha->max_req_queues = ha->max_rsp_queues = 0; 2898 2899 probe_failed: 2900 if (base_vha->timer_active) 2901 qla2x00_stop_timer(base_vha); 2902 base_vha->flags.online = 0; 2903 if (ha->dpc_thread) { 2904 struct task_struct *t = ha->dpc_thread; 2905 2906 ha->dpc_thread = NULL; 2907 kthread_stop(t); 2908 } 2909 2910 qla2x00_free_device(base_vha); 2911 2912 scsi_host_put(base_vha->host); 2913 2914 probe_hw_failed: 2915 qla2x00_clear_drv_active(ha); 2916 2917 iospace_config_failed: 2918 if (IS_P3P_TYPE(ha)) { 2919 if (!ha->nx_pcibase) 2920 iounmap((device_reg_t *)ha->nx_pcibase); 2921 if (!ql2xdbwr) 2922 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 2923 } else { 2924 if (ha->iobase) 2925 iounmap(ha->iobase); 2926 if (ha->cregbase) 2927 iounmap(ha->cregbase); 2928 } 2929 pci_release_selected_regions(ha->pdev, ha->bars); 2930 kfree(ha); 2931 ha = NULL; 2932 2933 probe_out: 2934 pci_disable_device(pdev); 2935 return ret; 2936 } 2937 2938 static void 2939 qla2x00_shutdown(struct pci_dev *pdev) 2940 { 2941 scsi_qla_host_t *vha; 2942 struct qla_hw_data *ha; 2943 2944 if (!atomic_read(&pdev->enable_cnt)) 2945 return; 2946 2947 vha = pci_get_drvdata(pdev); 2948 ha = vha->hw; 2949 2950 /* Notify ISPFX00 firmware */ 2951 if (IS_QLAFX00(ha)) 2952 qlafx00_driver_shutdown(vha, 20); 2953 2954 /* Turn-off FCE trace */ 2955 if (ha->flags.fce_enabled) { 2956 qla2x00_disable_fce_trace(vha, NULL, NULL); 2957 ha->flags.fce_enabled = 0; 2958 } 2959 2960 /* Turn-off EFT trace */ 2961 if (ha->eft) 2962 qla2x00_disable_eft_trace(vha); 2963 2964 /* Stop currently executing firmware. */ 2965 qla2x00_try_to_stop_firmware(vha); 2966 2967 /* Turn adapter off line */ 2968 vha->flags.online = 0; 2969 2970 /* turn-off interrupts on the card */ 2971 if (ha->interrupts_on) { 2972 vha->flags.init_done = 0; 2973 ha->isp_ops->disable_intrs(ha); 2974 } 2975 2976 qla2x00_free_irqs(vha); 2977 2978 qla2x00_free_fw_dump(ha); 2979 2980 pci_disable_pcie_error_reporting(pdev); 2981 pci_disable_device(pdev); 2982 } 2983 2984 /* Deletes all the virtual ports for a given ha */ 2985 static void 2986 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 2987 { 2988 scsi_qla_host_t *vha; 2989 unsigned long flags; 2990 2991 mutex_lock(&ha->vport_lock); 2992 while (ha->cur_vport_count) { 2993 spin_lock_irqsave(&ha->vport_slock, flags); 2994 2995 BUG_ON(base_vha->list.next == &ha->vp_list); 2996 /* This assumes first entry in ha->vp_list is always base vha */ 2997 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2998 scsi_host_get(vha->host); 2999 3000 spin_unlock_irqrestore(&ha->vport_slock, flags); 3001 mutex_unlock(&ha->vport_lock); 3002 3003 fc_vport_terminate(vha->fc_vport); 3004 scsi_host_put(vha->host); 3005 3006 mutex_lock(&ha->vport_lock); 3007 } 3008 mutex_unlock(&ha->vport_lock); 3009 } 3010 3011 /* Stops all deferred work threads */ 3012 static void 3013 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3014 { 3015 /* Flush the work queue and remove it */ 3016 if (ha->wq) { 3017 flush_workqueue(ha->wq); 3018 destroy_workqueue(ha->wq); 3019 ha->wq = NULL; 3020 } 3021 3022 /* Cancel all work and destroy DPC workqueues */ 3023 if (ha->dpc_lp_wq) { 3024 cancel_work_sync(&ha->idc_aen); 3025 destroy_workqueue(ha->dpc_lp_wq); 3026 ha->dpc_lp_wq = NULL; 3027 } 3028 3029 if (ha->dpc_hp_wq) { 3030 cancel_work_sync(&ha->nic_core_reset); 3031 cancel_work_sync(&ha->idc_state_handler); 3032 cancel_work_sync(&ha->nic_core_unrecoverable); 3033 destroy_workqueue(ha->dpc_hp_wq); 3034 ha->dpc_hp_wq = NULL; 3035 } 3036 3037 /* Kill the kernel thread for this host */ 3038 if (ha->dpc_thread) { 3039 struct task_struct *t = ha->dpc_thread; 3040 3041 /* 3042 * qla2xxx_wake_dpc checks for ->dpc_thread 3043 * so we need to zero it out. 3044 */ 3045 ha->dpc_thread = NULL; 3046 kthread_stop(t); 3047 } 3048 } 3049 3050 static void 3051 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3052 { 3053 if (IS_QLA82XX(ha)) { 3054 3055 iounmap((device_reg_t *)ha->nx_pcibase); 3056 if (!ql2xdbwr) 3057 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3058 } else { 3059 if (ha->iobase) 3060 iounmap(ha->iobase); 3061 3062 if (ha->cregbase) 3063 iounmap(ha->cregbase); 3064 3065 if (ha->mqiobase) 3066 iounmap(ha->mqiobase); 3067 3068 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3069 iounmap(ha->msixbase); 3070 } 3071 } 3072 3073 static void 3074 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3075 { 3076 if (IS_QLA8044(ha)) { 3077 qla8044_idc_lock(ha); 3078 qla8044_clear_drv_active(ha); 3079 qla8044_idc_unlock(ha); 3080 } else if (IS_QLA82XX(ha)) { 3081 qla82xx_idc_lock(ha); 3082 qla82xx_clear_drv_active(ha); 3083 qla82xx_idc_unlock(ha); 3084 } 3085 } 3086 3087 static void 3088 qla2x00_remove_one(struct pci_dev *pdev) 3089 { 3090 scsi_qla_host_t *base_vha; 3091 struct qla_hw_data *ha; 3092 3093 base_vha = pci_get_drvdata(pdev); 3094 ha = base_vha->hw; 3095 3096 /* Indicate device removal to prevent future board_disable and wait 3097 * until any pending board_disable has completed. */ 3098 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3099 cancel_work_sync(&ha->board_disable); 3100 3101 /* 3102 * If the PCI device is disabled then there was a PCI-disconnect and 3103 * qla2x00_disable_board_on_pci_error has taken care of most of the 3104 * resources. 3105 */ 3106 if (!atomic_read(&pdev->enable_cnt)) { 3107 scsi_host_put(base_vha->host); 3108 kfree(ha); 3109 pci_set_drvdata(pdev, NULL); 3110 return; 3111 } 3112 3113 qla2x00_wait_for_hba_ready(base_vha); 3114 3115 set_bit(UNLOADING, &base_vha->dpc_flags); 3116 3117 if (IS_QLAFX00(ha)) 3118 qlafx00_driver_shutdown(base_vha, 20); 3119 3120 qla2x00_delete_all_vps(ha, base_vha); 3121 3122 if (IS_QLA8031(ha)) { 3123 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3124 "Clearing fcoe driver presence.\n"); 3125 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3126 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3127 "Error while clearing DRV-Presence.\n"); 3128 } 3129 3130 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3131 3132 qla2x00_dfs_remove(base_vha); 3133 3134 qla84xx_put_chip(base_vha); 3135 3136 /* Laser should be disabled only for ISP2031 */ 3137 if (IS_QLA2031(ha)) 3138 qla83xx_disable_laser(base_vha); 3139 3140 /* Disable timer */ 3141 if (base_vha->timer_active) 3142 qla2x00_stop_timer(base_vha); 3143 3144 base_vha->flags.online = 0; 3145 3146 /* free DMA memory */ 3147 if (ha->exlogin_buf) 3148 qla2x00_free_exlogin_buffer(ha); 3149 3150 /* free DMA memory */ 3151 if (ha->exchoffld_buf) 3152 qla2x00_free_exchoffld_buffer(ha); 3153 3154 qla2x00_destroy_deferred_work(ha); 3155 3156 qlt_remove_target(ha, base_vha); 3157 3158 qla2x00_free_sysfs_attr(base_vha, true); 3159 3160 fc_remove_host(base_vha->host); 3161 3162 scsi_remove_host(base_vha->host); 3163 3164 qla2x00_free_device(base_vha); 3165 3166 qla2x00_clear_drv_active(ha); 3167 3168 scsi_host_put(base_vha->host); 3169 3170 qla2x00_unmap_iobases(ha); 3171 3172 pci_release_selected_regions(ha->pdev, ha->bars); 3173 kfree(ha); 3174 ha = NULL; 3175 3176 pci_disable_pcie_error_reporting(pdev); 3177 3178 pci_disable_device(pdev); 3179 } 3180 3181 static void 3182 qla2x00_free_device(scsi_qla_host_t *vha) 3183 { 3184 struct qla_hw_data *ha = vha->hw; 3185 3186 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3187 3188 /* Disable timer */ 3189 if (vha->timer_active) 3190 qla2x00_stop_timer(vha); 3191 3192 qla25xx_delete_queues(vha); 3193 3194 if (ha->flags.fce_enabled) 3195 qla2x00_disable_fce_trace(vha, NULL, NULL); 3196 3197 if (ha->eft) 3198 qla2x00_disable_eft_trace(vha); 3199 3200 /* Stop currently executing firmware. */ 3201 qla2x00_try_to_stop_firmware(vha); 3202 3203 vha->flags.online = 0; 3204 3205 /* turn-off interrupts on the card */ 3206 if (ha->interrupts_on) { 3207 vha->flags.init_done = 0; 3208 ha->isp_ops->disable_intrs(ha); 3209 } 3210 3211 qla2x00_free_irqs(vha); 3212 3213 qla2x00_free_fcports(vha); 3214 3215 qla2x00_mem_free(ha); 3216 3217 qla82xx_md_free(vha); 3218 3219 qla2x00_free_queues(ha); 3220 } 3221 3222 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3223 { 3224 fc_port_t *fcport, *tfcport; 3225 3226 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3227 list_del(&fcport->list); 3228 qla2x00_clear_loop_id(fcport); 3229 kfree(fcport); 3230 fcport = NULL; 3231 } 3232 } 3233 3234 static inline void 3235 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3236 int defer) 3237 { 3238 struct fc_rport *rport; 3239 scsi_qla_host_t *base_vha; 3240 unsigned long flags; 3241 3242 if (!fcport->rport) 3243 return; 3244 3245 rport = fcport->rport; 3246 if (defer) { 3247 base_vha = pci_get_drvdata(vha->hw->pdev); 3248 spin_lock_irqsave(vha->host->host_lock, flags); 3249 fcport->drport = rport; 3250 spin_unlock_irqrestore(vha->host->host_lock, flags); 3251 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3252 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3253 qla2xxx_wake_dpc(base_vha); 3254 } else { 3255 int now; 3256 if (rport) 3257 fc_remote_port_delete(rport); 3258 qlt_do_generation_tick(vha, &now); 3259 qlt_fc_port_deleted(vha, fcport, now); 3260 } 3261 } 3262 3263 /* 3264 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3265 * 3266 * Input: ha = adapter block pointer. fcport = port structure pointer. 3267 * 3268 * Return: None. 3269 * 3270 * Context: 3271 */ 3272 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3273 int do_login, int defer) 3274 { 3275 if (IS_QLAFX00(vha->hw)) { 3276 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3277 qla2x00_schedule_rport_del(vha, fcport, defer); 3278 return; 3279 } 3280 3281 if (atomic_read(&fcport->state) == FCS_ONLINE && 3282 vha->vp_idx == fcport->vha->vp_idx) { 3283 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3284 qla2x00_schedule_rport_del(vha, fcport, defer); 3285 } 3286 /* 3287 * We may need to retry the login, so don't change the state of the 3288 * port but do the retries. 3289 */ 3290 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3291 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3292 3293 if (!do_login) 3294 return; 3295 3296 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3297 3298 if (fcport->login_retry == 0) { 3299 fcport->login_retry = vha->hw->login_retry_count; 3300 3301 ql_dbg(ql_dbg_disc, vha, 0x2067, 3302 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3303 fcport->port_name, fcport->loop_id, fcport->login_retry); 3304 } 3305 } 3306 3307 /* 3308 * qla2x00_mark_all_devices_lost 3309 * Updates fcport state when device goes offline. 3310 * 3311 * Input: 3312 * ha = adapter block pointer. 3313 * fcport = port structure pointer. 3314 * 3315 * Return: 3316 * None. 3317 * 3318 * Context: 3319 */ 3320 void 3321 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3322 { 3323 fc_port_t *fcport; 3324 3325 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3326 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3327 continue; 3328 3329 /* 3330 * No point in marking the device as lost, if the device is 3331 * already DEAD. 3332 */ 3333 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3334 continue; 3335 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3336 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3337 if (defer) 3338 qla2x00_schedule_rport_del(vha, fcport, defer); 3339 else if (vha->vp_idx == fcport->vha->vp_idx) 3340 qla2x00_schedule_rport_del(vha, fcport, defer); 3341 } 3342 } 3343 } 3344 3345 /* 3346 * qla2x00_mem_alloc 3347 * Allocates adapter memory. 3348 * 3349 * Returns: 3350 * 0 = success. 3351 * !0 = failure. 3352 */ 3353 static int 3354 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3355 struct req_que **req, struct rsp_que **rsp) 3356 { 3357 char name[16]; 3358 3359 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3360 &ha->init_cb_dma, GFP_KERNEL); 3361 if (!ha->init_cb) 3362 goto fail; 3363 3364 if (qlt_mem_alloc(ha) < 0) 3365 goto fail_free_init_cb; 3366 3367 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3368 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3369 if (!ha->gid_list) 3370 goto fail_free_tgt_mem; 3371 3372 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3373 if (!ha->srb_mempool) 3374 goto fail_free_gid_list; 3375 3376 if (IS_P3P_TYPE(ha)) { 3377 /* Allocate cache for CT6 Ctx. */ 3378 if (!ctx_cachep) { 3379 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3380 sizeof(struct ct6_dsd), 0, 3381 SLAB_HWCACHE_ALIGN, NULL); 3382 if (!ctx_cachep) 3383 goto fail_free_gid_list; 3384 } 3385 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3386 ctx_cachep); 3387 if (!ha->ctx_mempool) 3388 goto fail_free_srb_mempool; 3389 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3390 "ctx_cachep=%p ctx_mempool=%p.\n", 3391 ctx_cachep, ha->ctx_mempool); 3392 } 3393 3394 /* Get memory for cached NVRAM */ 3395 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3396 if (!ha->nvram) 3397 goto fail_free_ctx_mempool; 3398 3399 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3400 ha->pdev->device); 3401 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3402 DMA_POOL_SIZE, 8, 0); 3403 if (!ha->s_dma_pool) 3404 goto fail_free_nvram; 3405 3406 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3407 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3408 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3409 3410 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3411 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3412 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3413 if (!ha->dl_dma_pool) { 3414 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3415 "Failed to allocate memory for dl_dma_pool.\n"); 3416 goto fail_s_dma_pool; 3417 } 3418 3419 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3420 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3421 if (!ha->fcp_cmnd_dma_pool) { 3422 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3423 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3424 goto fail_dl_dma_pool; 3425 } 3426 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3427 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3428 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3429 } 3430 3431 /* Allocate memory for SNS commands */ 3432 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3433 /* Get consistent memory allocated for SNS commands */ 3434 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3435 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3436 if (!ha->sns_cmd) 3437 goto fail_dma_pool; 3438 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3439 "sns_cmd: %p.\n", ha->sns_cmd); 3440 } else { 3441 /* Get consistent memory allocated for MS IOCB */ 3442 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3443 &ha->ms_iocb_dma); 3444 if (!ha->ms_iocb) 3445 goto fail_dma_pool; 3446 /* Get consistent memory allocated for CT SNS commands */ 3447 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3448 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3449 if (!ha->ct_sns) 3450 goto fail_free_ms_iocb; 3451 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3452 "ms_iocb=%p ct_sns=%p.\n", 3453 ha->ms_iocb, ha->ct_sns); 3454 } 3455 3456 /* Allocate memory for request ring */ 3457 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3458 if (!*req) { 3459 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3460 "Failed to allocate memory for req.\n"); 3461 goto fail_req; 3462 } 3463 (*req)->length = req_len; 3464 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3465 ((*req)->length + 1) * sizeof(request_t), 3466 &(*req)->dma, GFP_KERNEL); 3467 if (!(*req)->ring) { 3468 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3469 "Failed to allocate memory for req_ring.\n"); 3470 goto fail_req_ring; 3471 } 3472 /* Allocate memory for response ring */ 3473 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3474 if (!*rsp) { 3475 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3476 "Failed to allocate memory for rsp.\n"); 3477 goto fail_rsp; 3478 } 3479 (*rsp)->hw = ha; 3480 (*rsp)->length = rsp_len; 3481 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3482 ((*rsp)->length + 1) * sizeof(response_t), 3483 &(*rsp)->dma, GFP_KERNEL); 3484 if (!(*rsp)->ring) { 3485 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3486 "Failed to allocate memory for rsp_ring.\n"); 3487 goto fail_rsp_ring; 3488 } 3489 (*req)->rsp = *rsp; 3490 (*rsp)->req = *req; 3491 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3492 "req=%p req->length=%d req->ring=%p rsp=%p " 3493 "rsp->length=%d rsp->ring=%p.\n", 3494 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3495 (*rsp)->ring); 3496 /* Allocate memory for NVRAM data for vports */ 3497 if (ha->nvram_npiv_size) { 3498 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3499 ha->nvram_npiv_size, GFP_KERNEL); 3500 if (!ha->npiv_info) { 3501 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3502 "Failed to allocate memory for npiv_info.\n"); 3503 goto fail_npiv_info; 3504 } 3505 } else 3506 ha->npiv_info = NULL; 3507 3508 /* Get consistent memory allocated for EX-INIT-CB. */ 3509 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3510 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3511 &ha->ex_init_cb_dma); 3512 if (!ha->ex_init_cb) 3513 goto fail_ex_init_cb; 3514 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3515 "ex_init_cb=%p.\n", ha->ex_init_cb); 3516 } 3517 3518 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3519 3520 /* Get consistent memory allocated for Async Port-Database. */ 3521 if (!IS_FWI2_CAPABLE(ha)) { 3522 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3523 &ha->async_pd_dma); 3524 if (!ha->async_pd) 3525 goto fail_async_pd; 3526 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3527 "async_pd=%p.\n", ha->async_pd); 3528 } 3529 3530 INIT_LIST_HEAD(&ha->vp_list); 3531 3532 /* Allocate memory for our loop_id bitmap */ 3533 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3534 GFP_KERNEL); 3535 if (!ha->loop_id_map) 3536 goto fail_async_pd; 3537 else { 3538 qla2x00_set_reserved_loop_ids(ha); 3539 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3540 "loop_id_map=%p.\n", ha->loop_id_map); 3541 } 3542 3543 return 0; 3544 3545 fail_async_pd: 3546 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3547 fail_ex_init_cb: 3548 kfree(ha->npiv_info); 3549 fail_npiv_info: 3550 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3551 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3552 (*rsp)->ring = NULL; 3553 (*rsp)->dma = 0; 3554 fail_rsp_ring: 3555 kfree(*rsp); 3556 fail_rsp: 3557 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3558 sizeof(request_t), (*req)->ring, (*req)->dma); 3559 (*req)->ring = NULL; 3560 (*req)->dma = 0; 3561 fail_req_ring: 3562 kfree(*req); 3563 fail_req: 3564 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3565 ha->ct_sns, ha->ct_sns_dma); 3566 ha->ct_sns = NULL; 3567 ha->ct_sns_dma = 0; 3568 fail_free_ms_iocb: 3569 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3570 ha->ms_iocb = NULL; 3571 ha->ms_iocb_dma = 0; 3572 fail_dma_pool: 3573 if (IS_QLA82XX(ha) || ql2xenabledif) { 3574 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3575 ha->fcp_cmnd_dma_pool = NULL; 3576 } 3577 fail_dl_dma_pool: 3578 if (IS_QLA82XX(ha) || ql2xenabledif) { 3579 dma_pool_destroy(ha->dl_dma_pool); 3580 ha->dl_dma_pool = NULL; 3581 } 3582 fail_s_dma_pool: 3583 dma_pool_destroy(ha->s_dma_pool); 3584 ha->s_dma_pool = NULL; 3585 fail_free_nvram: 3586 kfree(ha->nvram); 3587 ha->nvram = NULL; 3588 fail_free_ctx_mempool: 3589 mempool_destroy(ha->ctx_mempool); 3590 ha->ctx_mempool = NULL; 3591 fail_free_srb_mempool: 3592 mempool_destroy(ha->srb_mempool); 3593 ha->srb_mempool = NULL; 3594 fail_free_gid_list: 3595 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3596 ha->gid_list, 3597 ha->gid_list_dma); 3598 ha->gid_list = NULL; 3599 ha->gid_list_dma = 0; 3600 fail_free_tgt_mem: 3601 qlt_mem_free(ha); 3602 fail_free_init_cb: 3603 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3604 ha->init_cb_dma); 3605 ha->init_cb = NULL; 3606 ha->init_cb_dma = 0; 3607 fail: 3608 ql_log(ql_log_fatal, NULL, 0x0030, 3609 "Memory allocation failure.\n"); 3610 return -ENOMEM; 3611 } 3612 3613 int 3614 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3615 { 3616 int rval; 3617 uint16_t size, max_cnt, temp; 3618 struct qla_hw_data *ha = vha->hw; 3619 3620 /* Return if we don't need to alloacate any extended logins */ 3621 if (!ql2xexlogins) 3622 return QLA_SUCCESS; 3623 3624 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3625 max_cnt = 0; 3626 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3627 if (rval != QLA_SUCCESS) { 3628 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3629 "Failed to get exlogin status.\n"); 3630 return rval; 3631 } 3632 3633 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3634 ha->exlogin_size = (size * temp); 3635 ql_log(ql_log_info, vha, 0xd024, 3636 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3637 max_cnt, size, temp); 3638 3639 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3640 ha->exlogin_size); 3641 3642 /* Get consistent memory for extended logins */ 3643 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 3644 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 3645 if (!ha->exlogin_buf) { 3646 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 3647 "Failed to allocate memory for exlogin_buf_dma.\n"); 3648 return -ENOMEM; 3649 } 3650 3651 /* Now configure the dma buffer */ 3652 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 3653 if (rval) { 3654 ql_log(ql_log_fatal, vha, 0x00cf, 3655 "Setup extended login buffer ****FAILED****.\n"); 3656 qla2x00_free_exlogin_buffer(ha); 3657 } 3658 3659 return rval; 3660 } 3661 3662 /* 3663 * qla2x00_free_exlogin_buffer 3664 * 3665 * Input: 3666 * ha = adapter block pointer 3667 */ 3668 void 3669 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 3670 { 3671 if (ha->exlogin_buf) { 3672 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 3673 ha->exlogin_buf, ha->exlogin_buf_dma); 3674 ha->exlogin_buf = NULL; 3675 ha->exlogin_size = 0; 3676 } 3677 } 3678 3679 int 3680 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 3681 { 3682 int rval; 3683 uint16_t size, max_cnt, temp; 3684 struct qla_hw_data *ha = vha->hw; 3685 3686 /* Return if we don't need to alloacate any extended logins */ 3687 if (!ql2xexchoffld) 3688 return QLA_SUCCESS; 3689 3690 ql_log(ql_log_info, vha, 0xd014, 3691 "Exchange offload count: %d.\n", ql2xexlogins); 3692 3693 max_cnt = 0; 3694 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 3695 if (rval != QLA_SUCCESS) { 3696 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 3697 "Failed to get exlogin status.\n"); 3698 return rval; 3699 } 3700 3701 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 3702 ha->exchoffld_size = (size * temp); 3703 ql_log(ql_log_info, vha, 0xd016, 3704 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 3705 max_cnt, size, temp); 3706 3707 ql_log(ql_log_info, vha, 0xd017, 3708 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 3709 3710 /* Get consistent memory for extended logins */ 3711 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 3712 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 3713 if (!ha->exchoffld_buf) { 3714 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 3715 "Failed to allocate memory for exchoffld_buf_dma.\n"); 3716 return -ENOMEM; 3717 } 3718 3719 /* Now configure the dma buffer */ 3720 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 3721 if (rval) { 3722 ql_log(ql_log_fatal, vha, 0xd02e, 3723 "Setup exchange offload buffer ****FAILED****.\n"); 3724 qla2x00_free_exchoffld_buffer(ha); 3725 } 3726 3727 return rval; 3728 } 3729 3730 /* 3731 * qla2x00_free_exchoffld_buffer 3732 * 3733 * Input: 3734 * ha = adapter block pointer 3735 */ 3736 void 3737 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 3738 { 3739 if (ha->exchoffld_buf) { 3740 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 3741 ha->exchoffld_buf, ha->exchoffld_buf_dma); 3742 ha->exchoffld_buf = NULL; 3743 ha->exchoffld_size = 0; 3744 } 3745 } 3746 3747 /* 3748 * qla2x00_free_fw_dump 3749 * Frees fw dump stuff. 3750 * 3751 * Input: 3752 * ha = adapter block pointer 3753 */ 3754 static void 3755 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3756 { 3757 if (ha->fce) 3758 dma_free_coherent(&ha->pdev->dev, 3759 FCE_SIZE, ha->fce, ha->fce_dma); 3760 3761 if (ha->eft) 3762 dma_free_coherent(&ha->pdev->dev, 3763 EFT_SIZE, ha->eft, ha->eft_dma); 3764 3765 if (ha->fw_dump) 3766 vfree(ha->fw_dump); 3767 if (ha->fw_dump_template) 3768 vfree(ha->fw_dump_template); 3769 3770 ha->fce = NULL; 3771 ha->fce_dma = 0; 3772 ha->eft = NULL; 3773 ha->eft_dma = 0; 3774 ha->fw_dumped = 0; 3775 ha->fw_dump_cap_flags = 0; 3776 ha->fw_dump_reading = 0; 3777 ha->fw_dump = NULL; 3778 ha->fw_dump_len = 0; 3779 ha->fw_dump_template = NULL; 3780 ha->fw_dump_template_len = 0; 3781 } 3782 3783 /* 3784 * qla2x00_mem_free 3785 * Frees all adapter allocated memory. 3786 * 3787 * Input: 3788 * ha = adapter block pointer. 3789 */ 3790 static void 3791 qla2x00_mem_free(struct qla_hw_data *ha) 3792 { 3793 qla2x00_free_fw_dump(ha); 3794 3795 if (ha->mctp_dump) 3796 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3797 ha->mctp_dump_dma); 3798 3799 if (ha->srb_mempool) 3800 mempool_destroy(ha->srb_mempool); 3801 3802 if (ha->dcbx_tlv) 3803 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3804 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3805 3806 if (ha->xgmac_data) 3807 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3808 ha->xgmac_data, ha->xgmac_data_dma); 3809 3810 if (ha->sns_cmd) 3811 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3812 ha->sns_cmd, ha->sns_cmd_dma); 3813 3814 if (ha->ct_sns) 3815 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3816 ha->ct_sns, ha->ct_sns_dma); 3817 3818 if (ha->sfp_data) 3819 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3820 3821 if (ha->ms_iocb) 3822 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3823 3824 if (ha->ex_init_cb) 3825 dma_pool_free(ha->s_dma_pool, 3826 ha->ex_init_cb, ha->ex_init_cb_dma); 3827 3828 if (ha->async_pd) 3829 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3830 3831 if (ha->s_dma_pool) 3832 dma_pool_destroy(ha->s_dma_pool); 3833 3834 if (ha->gid_list) 3835 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3836 ha->gid_list, ha->gid_list_dma); 3837 3838 if (IS_QLA82XX(ha)) { 3839 if (!list_empty(&ha->gbl_dsd_list)) { 3840 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3841 3842 /* clean up allocated prev pool */ 3843 list_for_each_entry_safe(dsd_ptr, 3844 tdsd_ptr, &ha->gbl_dsd_list, list) { 3845 dma_pool_free(ha->dl_dma_pool, 3846 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3847 list_del(&dsd_ptr->list); 3848 kfree(dsd_ptr); 3849 } 3850 } 3851 } 3852 3853 if (ha->dl_dma_pool) 3854 dma_pool_destroy(ha->dl_dma_pool); 3855 3856 if (ha->fcp_cmnd_dma_pool) 3857 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3858 3859 if (ha->ctx_mempool) 3860 mempool_destroy(ha->ctx_mempool); 3861 3862 qlt_mem_free(ha); 3863 3864 if (ha->init_cb) 3865 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3866 ha->init_cb, ha->init_cb_dma); 3867 vfree(ha->optrom_buffer); 3868 kfree(ha->nvram); 3869 kfree(ha->npiv_info); 3870 kfree(ha->swl); 3871 kfree(ha->loop_id_map); 3872 3873 ha->srb_mempool = NULL; 3874 ha->ctx_mempool = NULL; 3875 ha->sns_cmd = NULL; 3876 ha->sns_cmd_dma = 0; 3877 ha->ct_sns = NULL; 3878 ha->ct_sns_dma = 0; 3879 ha->ms_iocb = NULL; 3880 ha->ms_iocb_dma = 0; 3881 ha->init_cb = NULL; 3882 ha->init_cb_dma = 0; 3883 ha->ex_init_cb = NULL; 3884 ha->ex_init_cb_dma = 0; 3885 ha->async_pd = NULL; 3886 ha->async_pd_dma = 0; 3887 3888 ha->s_dma_pool = NULL; 3889 ha->dl_dma_pool = NULL; 3890 ha->fcp_cmnd_dma_pool = NULL; 3891 3892 ha->gid_list = NULL; 3893 ha->gid_list_dma = 0; 3894 3895 ha->tgt.atio_ring = NULL; 3896 ha->tgt.atio_dma = 0; 3897 ha->tgt.tgt_vp_map = NULL; 3898 } 3899 3900 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3901 struct qla_hw_data *ha) 3902 { 3903 struct Scsi_Host *host; 3904 struct scsi_qla_host *vha = NULL; 3905 3906 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3907 if (host == NULL) { 3908 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3909 "Failed to allocate host from the scsi layer, aborting.\n"); 3910 goto fail; 3911 } 3912 3913 /* Clear our data area */ 3914 vha = shost_priv(host); 3915 memset(vha, 0, sizeof(scsi_qla_host_t)); 3916 3917 vha->host = host; 3918 vha->host_no = host->host_no; 3919 vha->hw = ha; 3920 3921 INIT_LIST_HEAD(&vha->vp_fcports); 3922 INIT_LIST_HEAD(&vha->work_list); 3923 INIT_LIST_HEAD(&vha->list); 3924 INIT_LIST_HEAD(&vha->qla_cmd_list); 3925 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 3926 INIT_LIST_HEAD(&vha->logo_list); 3927 INIT_LIST_HEAD(&vha->plogi_ack_list); 3928 3929 spin_lock_init(&vha->work_lock); 3930 spin_lock_init(&vha->cmd_list_lock); 3931 3932 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3933 ql_dbg(ql_dbg_init, vha, 0x0041, 3934 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3935 vha->host, vha->hw, vha, 3936 dev_name(&(ha->pdev->dev))); 3937 3938 return vha; 3939 3940 fail: 3941 return vha; 3942 } 3943 3944 static struct qla_work_evt * 3945 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3946 { 3947 struct qla_work_evt *e; 3948 uint8_t bail; 3949 3950 QLA_VHA_MARK_BUSY(vha, bail); 3951 if (bail) 3952 return NULL; 3953 3954 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3955 if (!e) { 3956 QLA_VHA_MARK_NOT_BUSY(vha); 3957 return NULL; 3958 } 3959 3960 INIT_LIST_HEAD(&e->list); 3961 e->type = type; 3962 e->flags = QLA_EVT_FLAG_FREE; 3963 return e; 3964 } 3965 3966 static int 3967 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3968 { 3969 unsigned long flags; 3970 3971 spin_lock_irqsave(&vha->work_lock, flags); 3972 list_add_tail(&e->list, &vha->work_list); 3973 spin_unlock_irqrestore(&vha->work_lock, flags); 3974 qla2xxx_wake_dpc(vha); 3975 3976 return QLA_SUCCESS; 3977 } 3978 3979 int 3980 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3981 u32 data) 3982 { 3983 struct qla_work_evt *e; 3984 3985 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3986 if (!e) 3987 return QLA_FUNCTION_FAILED; 3988 3989 e->u.aen.code = code; 3990 e->u.aen.data = data; 3991 return qla2x00_post_work(vha, e); 3992 } 3993 3994 int 3995 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3996 { 3997 struct qla_work_evt *e; 3998 3999 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4000 if (!e) 4001 return QLA_FUNCTION_FAILED; 4002 4003 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4004 return qla2x00_post_work(vha, e); 4005 } 4006 4007 #define qla2x00_post_async_work(name, type) \ 4008 int qla2x00_post_async_##name##_work( \ 4009 struct scsi_qla_host *vha, \ 4010 fc_port_t *fcport, uint16_t *data) \ 4011 { \ 4012 struct qla_work_evt *e; \ 4013 \ 4014 e = qla2x00_alloc_work(vha, type); \ 4015 if (!e) \ 4016 return QLA_FUNCTION_FAILED; \ 4017 \ 4018 e->u.logio.fcport = fcport; \ 4019 if (data) { \ 4020 e->u.logio.data[0] = data[0]; \ 4021 e->u.logio.data[1] = data[1]; \ 4022 } \ 4023 return qla2x00_post_work(vha, e); \ 4024 } 4025 4026 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4027 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 4028 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4029 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4030 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4031 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4032 4033 int 4034 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4035 { 4036 struct qla_work_evt *e; 4037 4038 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4039 if (!e) 4040 return QLA_FUNCTION_FAILED; 4041 4042 e->u.uevent.code = code; 4043 return qla2x00_post_work(vha, e); 4044 } 4045 4046 static void 4047 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4048 { 4049 char event_string[40]; 4050 char *envp[] = { event_string, NULL }; 4051 4052 switch (code) { 4053 case QLA_UEVENT_CODE_FW_DUMP: 4054 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4055 vha->host_no); 4056 break; 4057 default: 4058 /* do nothing */ 4059 break; 4060 } 4061 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4062 } 4063 4064 int 4065 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4066 uint32_t *data, int cnt) 4067 { 4068 struct qla_work_evt *e; 4069 4070 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4071 if (!e) 4072 return QLA_FUNCTION_FAILED; 4073 4074 e->u.aenfx.evtcode = evtcode; 4075 e->u.aenfx.count = cnt; 4076 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4077 return qla2x00_post_work(vha, e); 4078 } 4079 4080 void 4081 qla2x00_do_work(struct scsi_qla_host *vha) 4082 { 4083 struct qla_work_evt *e, *tmp; 4084 unsigned long flags; 4085 LIST_HEAD(work); 4086 4087 spin_lock_irqsave(&vha->work_lock, flags); 4088 list_splice_init(&vha->work_list, &work); 4089 spin_unlock_irqrestore(&vha->work_lock, flags); 4090 4091 list_for_each_entry_safe(e, tmp, &work, list) { 4092 list_del_init(&e->list); 4093 4094 switch (e->type) { 4095 case QLA_EVT_AEN: 4096 fc_host_post_event(vha->host, fc_get_event_number(), 4097 e->u.aen.code, e->u.aen.data); 4098 break; 4099 case QLA_EVT_IDC_ACK: 4100 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4101 break; 4102 case QLA_EVT_ASYNC_LOGIN: 4103 qla2x00_async_login(vha, e->u.logio.fcport, 4104 e->u.logio.data); 4105 break; 4106 case QLA_EVT_ASYNC_LOGIN_DONE: 4107 qla2x00_async_login_done(vha, e->u.logio.fcport, 4108 e->u.logio.data); 4109 break; 4110 case QLA_EVT_ASYNC_LOGOUT: 4111 qla2x00_async_logout(vha, e->u.logio.fcport); 4112 break; 4113 case QLA_EVT_ASYNC_LOGOUT_DONE: 4114 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4115 e->u.logio.data); 4116 break; 4117 case QLA_EVT_ASYNC_ADISC: 4118 qla2x00_async_adisc(vha, e->u.logio.fcport, 4119 e->u.logio.data); 4120 break; 4121 case QLA_EVT_ASYNC_ADISC_DONE: 4122 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4123 e->u.logio.data); 4124 break; 4125 case QLA_EVT_UEVENT: 4126 qla2x00_uevent_emit(vha, e->u.uevent.code); 4127 break; 4128 case QLA_EVT_AENFX: 4129 qlafx00_process_aen(vha, e); 4130 break; 4131 } 4132 if (e->flags & QLA_EVT_FLAG_FREE) 4133 kfree(e); 4134 4135 /* For each work completed decrement vha ref count */ 4136 QLA_VHA_MARK_NOT_BUSY(vha); 4137 } 4138 } 4139 4140 /* Relogins all the fcports of a vport 4141 * Context: dpc thread 4142 */ 4143 void qla2x00_relogin(struct scsi_qla_host *vha) 4144 { 4145 fc_port_t *fcport; 4146 int status; 4147 uint16_t next_loopid = 0; 4148 struct qla_hw_data *ha = vha->hw; 4149 uint16_t data[2]; 4150 4151 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4152 /* 4153 * If the port is not ONLINE then try to login 4154 * to it if we haven't run out of retries. 4155 */ 4156 if (atomic_read(&fcport->state) != FCS_ONLINE && 4157 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4158 fcport->login_retry--; 4159 if (fcport->flags & FCF_FABRIC_DEVICE) { 4160 if (fcport->flags & FCF_FCP2_DEVICE) 4161 ha->isp_ops->fabric_logout(vha, 4162 fcport->loop_id, 4163 fcport->d_id.b.domain, 4164 fcport->d_id.b.area, 4165 fcport->d_id.b.al_pa); 4166 4167 if (fcport->loop_id == FC_NO_LOOP_ID) { 4168 fcport->loop_id = next_loopid = 4169 ha->min_external_loopid; 4170 status = qla2x00_find_new_loop_id( 4171 vha, fcport); 4172 if (status != QLA_SUCCESS) { 4173 /* Ran out of IDs to use */ 4174 break; 4175 } 4176 } 4177 4178 if (IS_ALOGIO_CAPABLE(ha)) { 4179 fcport->flags |= FCF_ASYNC_SENT; 4180 data[0] = 0; 4181 data[1] = QLA_LOGIO_LOGIN_RETRIED; 4182 status = qla2x00_post_async_login_work( 4183 vha, fcport, data); 4184 if (status == QLA_SUCCESS) 4185 continue; 4186 /* Attempt a retry. */ 4187 status = 1; 4188 } else { 4189 status = qla2x00_fabric_login(vha, 4190 fcport, &next_loopid); 4191 if (status == QLA_SUCCESS) { 4192 int status2; 4193 uint8_t opts; 4194 4195 opts = 0; 4196 if (fcport->flags & 4197 FCF_FCP2_DEVICE) 4198 opts |= BIT_1; 4199 status2 = 4200 qla2x00_get_port_database( 4201 vha, fcport, opts); 4202 if (status2 != QLA_SUCCESS) 4203 status = 1; 4204 } 4205 } 4206 } else 4207 status = qla2x00_local_device_login(vha, 4208 fcport); 4209 4210 if (status == QLA_SUCCESS) { 4211 fcport->old_loop_id = fcport->loop_id; 4212 4213 ql_dbg(ql_dbg_disc, vha, 0x2003, 4214 "Port login OK: logged in ID 0x%x.\n", 4215 fcport->loop_id); 4216 4217 qla2x00_update_fcport(vha, fcport); 4218 4219 } else if (status == 1) { 4220 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4221 /* retry the login again */ 4222 ql_dbg(ql_dbg_disc, vha, 0x2007, 4223 "Retrying %d login again loop_id 0x%x.\n", 4224 fcport->login_retry, fcport->loop_id); 4225 } else { 4226 fcport->login_retry = 0; 4227 } 4228 4229 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4230 qla2x00_clear_loop_id(fcport); 4231 } 4232 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4233 break; 4234 } 4235 } 4236 4237 /* Schedule work on any of the dpc-workqueues */ 4238 void 4239 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4240 { 4241 struct qla_hw_data *ha = base_vha->hw; 4242 4243 switch (work_code) { 4244 case MBA_IDC_AEN: /* 0x8200 */ 4245 if (ha->dpc_lp_wq) 4246 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4247 break; 4248 4249 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4250 if (!ha->flags.nic_core_reset_hdlr_active) { 4251 if (ha->dpc_hp_wq) 4252 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4253 } else 4254 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4255 "NIC Core reset is already active. Skip " 4256 "scheduling it again.\n"); 4257 break; 4258 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4259 if (ha->dpc_hp_wq) 4260 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4261 break; 4262 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4263 if (ha->dpc_hp_wq) 4264 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4265 break; 4266 default: 4267 ql_log(ql_log_warn, base_vha, 0xb05f, 4268 "Unknown work-code=0x%x.\n", work_code); 4269 } 4270 4271 return; 4272 } 4273 4274 /* Work: Perform NIC Core Unrecoverable state handling */ 4275 void 4276 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4277 { 4278 struct qla_hw_data *ha = 4279 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4280 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4281 uint32_t dev_state = 0; 4282 4283 qla83xx_idc_lock(base_vha, 0); 4284 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4285 qla83xx_reset_ownership(base_vha); 4286 if (ha->flags.nic_core_reset_owner) { 4287 ha->flags.nic_core_reset_owner = 0; 4288 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4289 QLA8XXX_DEV_FAILED); 4290 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4291 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4292 } 4293 qla83xx_idc_unlock(base_vha, 0); 4294 } 4295 4296 /* Work: Execute IDC state handler */ 4297 void 4298 qla83xx_idc_state_handler_work(struct work_struct *work) 4299 { 4300 struct qla_hw_data *ha = 4301 container_of(work, struct qla_hw_data, idc_state_handler); 4302 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4303 uint32_t dev_state = 0; 4304 4305 qla83xx_idc_lock(base_vha, 0); 4306 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4307 if (dev_state == QLA8XXX_DEV_FAILED || 4308 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4309 qla83xx_idc_state_handler(base_vha); 4310 qla83xx_idc_unlock(base_vha, 0); 4311 } 4312 4313 static int 4314 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4315 { 4316 int rval = QLA_SUCCESS; 4317 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4318 uint32_t heart_beat_counter1, heart_beat_counter2; 4319 4320 do { 4321 if (time_after(jiffies, heart_beat_wait)) { 4322 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4323 "Nic Core f/w is not alive.\n"); 4324 rval = QLA_FUNCTION_FAILED; 4325 break; 4326 } 4327 4328 qla83xx_idc_lock(base_vha, 0); 4329 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4330 &heart_beat_counter1); 4331 qla83xx_idc_unlock(base_vha, 0); 4332 msleep(100); 4333 qla83xx_idc_lock(base_vha, 0); 4334 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4335 &heart_beat_counter2); 4336 qla83xx_idc_unlock(base_vha, 0); 4337 } while (heart_beat_counter1 == heart_beat_counter2); 4338 4339 return rval; 4340 } 4341 4342 /* Work: Perform NIC Core Reset handling */ 4343 void 4344 qla83xx_nic_core_reset_work(struct work_struct *work) 4345 { 4346 struct qla_hw_data *ha = 4347 container_of(work, struct qla_hw_data, nic_core_reset); 4348 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4349 uint32_t dev_state = 0; 4350 4351 if (IS_QLA2031(ha)) { 4352 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4353 ql_log(ql_log_warn, base_vha, 0xb081, 4354 "Failed to dump mctp\n"); 4355 return; 4356 } 4357 4358 if (!ha->flags.nic_core_reset_hdlr_active) { 4359 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4360 qla83xx_idc_lock(base_vha, 0); 4361 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4362 &dev_state); 4363 qla83xx_idc_unlock(base_vha, 0); 4364 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4365 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4366 "Nic Core f/w is alive.\n"); 4367 return; 4368 } 4369 } 4370 4371 ha->flags.nic_core_reset_hdlr_active = 1; 4372 if (qla83xx_nic_core_reset(base_vha)) { 4373 /* NIC Core reset failed. */ 4374 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4375 "NIC Core reset failed.\n"); 4376 } 4377 ha->flags.nic_core_reset_hdlr_active = 0; 4378 } 4379 } 4380 4381 /* Work: Handle 8200 IDC aens */ 4382 void 4383 qla83xx_service_idc_aen(struct work_struct *work) 4384 { 4385 struct qla_hw_data *ha = 4386 container_of(work, struct qla_hw_data, idc_aen); 4387 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4388 uint32_t dev_state, idc_control; 4389 4390 qla83xx_idc_lock(base_vha, 0); 4391 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4392 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4393 qla83xx_idc_unlock(base_vha, 0); 4394 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4395 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4396 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4397 "Application requested NIC Core Reset.\n"); 4398 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4399 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4400 QLA_SUCCESS) { 4401 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4402 "Other protocol driver requested NIC Core Reset.\n"); 4403 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4404 } 4405 } else if (dev_state == QLA8XXX_DEV_FAILED || 4406 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4407 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4408 } 4409 } 4410 4411 static void 4412 qla83xx_wait_logic(void) 4413 { 4414 int i; 4415 4416 /* Yield CPU */ 4417 if (!in_interrupt()) { 4418 /* 4419 * Wait about 200ms before retrying again. 4420 * This controls the number of retries for single 4421 * lock operation. 4422 */ 4423 msleep(100); 4424 schedule(); 4425 } else { 4426 for (i = 0; i < 20; i++) 4427 cpu_relax(); /* This a nop instr on i386 */ 4428 } 4429 } 4430 4431 static int 4432 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4433 { 4434 int rval; 4435 uint32_t data; 4436 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4437 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4438 struct qla_hw_data *ha = base_vha->hw; 4439 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4440 "Trying force recovery of the IDC lock.\n"); 4441 4442 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4443 if (rval) 4444 return rval; 4445 4446 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4447 return QLA_SUCCESS; 4448 } else { 4449 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4450 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4451 data); 4452 if (rval) 4453 return rval; 4454 4455 msleep(200); 4456 4457 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4458 &data); 4459 if (rval) 4460 return rval; 4461 4462 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4463 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4464 ~(idc_lck_rcvry_stage_mask)); 4465 rval = qla83xx_wr_reg(base_vha, 4466 QLA83XX_IDC_LOCK_RECOVERY, data); 4467 if (rval) 4468 return rval; 4469 4470 /* Forcefully perform IDC UnLock */ 4471 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4472 &data); 4473 if (rval) 4474 return rval; 4475 /* Clear lock-id by setting 0xff */ 4476 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4477 0xff); 4478 if (rval) 4479 return rval; 4480 /* Clear lock-recovery by setting 0x0 */ 4481 rval = qla83xx_wr_reg(base_vha, 4482 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4483 if (rval) 4484 return rval; 4485 } else 4486 return QLA_SUCCESS; 4487 } 4488 4489 return rval; 4490 } 4491 4492 static int 4493 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4494 { 4495 int rval = QLA_SUCCESS; 4496 uint32_t o_drv_lockid, n_drv_lockid; 4497 unsigned long lock_recovery_timeout; 4498 4499 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4500 retry_lockid: 4501 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4502 if (rval) 4503 goto exit; 4504 4505 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4506 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4507 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4508 return QLA_SUCCESS; 4509 else 4510 return QLA_FUNCTION_FAILED; 4511 } 4512 4513 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4514 if (rval) 4515 goto exit; 4516 4517 if (o_drv_lockid == n_drv_lockid) { 4518 qla83xx_wait_logic(); 4519 goto retry_lockid; 4520 } else 4521 return QLA_SUCCESS; 4522 4523 exit: 4524 return rval; 4525 } 4526 4527 void 4528 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4529 { 4530 uint16_t options = (requester_id << 15) | BIT_6; 4531 uint32_t data; 4532 uint32_t lock_owner; 4533 struct qla_hw_data *ha = base_vha->hw; 4534 4535 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4536 retry_lock: 4537 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4538 == QLA_SUCCESS) { 4539 if (data) { 4540 /* Setting lock-id to our function-number */ 4541 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4542 ha->portnum); 4543 } else { 4544 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4545 &lock_owner); 4546 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4547 "Failed to acquire IDC lock, acquired by %d, " 4548 "retrying...\n", lock_owner); 4549 4550 /* Retry/Perform IDC-Lock recovery */ 4551 if (qla83xx_idc_lock_recovery(base_vha) 4552 == QLA_SUCCESS) { 4553 qla83xx_wait_logic(); 4554 goto retry_lock; 4555 } else 4556 ql_log(ql_log_warn, base_vha, 0xb075, 4557 "IDC Lock recovery FAILED.\n"); 4558 } 4559 4560 } 4561 4562 return; 4563 4564 /* XXX: IDC-lock implementation using access-control mbx */ 4565 retry_lock2: 4566 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4567 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4568 "Failed to acquire IDC lock. retrying...\n"); 4569 /* Retry/Perform IDC-Lock recovery */ 4570 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4571 qla83xx_wait_logic(); 4572 goto retry_lock2; 4573 } else 4574 ql_log(ql_log_warn, base_vha, 0xb076, 4575 "IDC Lock recovery FAILED.\n"); 4576 } 4577 4578 return; 4579 } 4580 4581 void 4582 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4583 { 4584 #if 0 4585 uint16_t options = (requester_id << 15) | BIT_7; 4586 #endif 4587 uint16_t retry; 4588 uint32_t data; 4589 struct qla_hw_data *ha = base_vha->hw; 4590 4591 /* IDC-unlock implementation using driver-unlock/lock-id 4592 * remote registers 4593 */ 4594 retry = 0; 4595 retry_unlock: 4596 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4597 == QLA_SUCCESS) { 4598 if (data == ha->portnum) { 4599 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4600 /* Clearing lock-id by setting 0xff */ 4601 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4602 } else if (retry < 10) { 4603 /* SV: XXX: IDC unlock retrying needed here? */ 4604 4605 /* Retry for IDC-unlock */ 4606 qla83xx_wait_logic(); 4607 retry++; 4608 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4609 "Failed to release IDC lock, retyring=%d\n", retry); 4610 goto retry_unlock; 4611 } 4612 } else if (retry < 10) { 4613 /* Retry for IDC-unlock */ 4614 qla83xx_wait_logic(); 4615 retry++; 4616 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4617 "Failed to read drv-lockid, retyring=%d\n", retry); 4618 goto retry_unlock; 4619 } 4620 4621 return; 4622 4623 #if 0 4624 /* XXX: IDC-unlock implementation using access-control mbx */ 4625 retry = 0; 4626 retry_unlock2: 4627 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4628 if (retry < 10) { 4629 /* Retry for IDC-unlock */ 4630 qla83xx_wait_logic(); 4631 retry++; 4632 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4633 "Failed to release IDC lock, retyring=%d\n", retry); 4634 goto retry_unlock2; 4635 } 4636 } 4637 4638 return; 4639 #endif 4640 } 4641 4642 int 4643 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4644 { 4645 int rval = QLA_SUCCESS; 4646 struct qla_hw_data *ha = vha->hw; 4647 uint32_t drv_presence; 4648 4649 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4650 if (rval == QLA_SUCCESS) { 4651 drv_presence |= (1 << ha->portnum); 4652 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4653 drv_presence); 4654 } 4655 4656 return rval; 4657 } 4658 4659 int 4660 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4661 { 4662 int rval = QLA_SUCCESS; 4663 4664 qla83xx_idc_lock(vha, 0); 4665 rval = __qla83xx_set_drv_presence(vha); 4666 qla83xx_idc_unlock(vha, 0); 4667 4668 return rval; 4669 } 4670 4671 int 4672 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4673 { 4674 int rval = QLA_SUCCESS; 4675 struct qla_hw_data *ha = vha->hw; 4676 uint32_t drv_presence; 4677 4678 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4679 if (rval == QLA_SUCCESS) { 4680 drv_presence &= ~(1 << ha->portnum); 4681 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4682 drv_presence); 4683 } 4684 4685 return rval; 4686 } 4687 4688 int 4689 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4690 { 4691 int rval = QLA_SUCCESS; 4692 4693 qla83xx_idc_lock(vha, 0); 4694 rval = __qla83xx_clear_drv_presence(vha); 4695 qla83xx_idc_unlock(vha, 0); 4696 4697 return rval; 4698 } 4699 4700 static void 4701 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4702 { 4703 struct qla_hw_data *ha = vha->hw; 4704 uint32_t drv_ack, drv_presence; 4705 unsigned long ack_timeout; 4706 4707 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4708 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4709 while (1) { 4710 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4711 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4712 if ((drv_ack & drv_presence) == drv_presence) 4713 break; 4714 4715 if (time_after_eq(jiffies, ack_timeout)) { 4716 ql_log(ql_log_warn, vha, 0xb067, 4717 "RESET ACK TIMEOUT! drv_presence=0x%x " 4718 "drv_ack=0x%x\n", drv_presence, drv_ack); 4719 /* 4720 * The function(s) which did not ack in time are forced 4721 * to withdraw any further participation in the IDC 4722 * reset. 4723 */ 4724 if (drv_ack != drv_presence) 4725 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4726 drv_ack); 4727 break; 4728 } 4729 4730 qla83xx_idc_unlock(vha, 0); 4731 msleep(1000); 4732 qla83xx_idc_lock(vha, 0); 4733 } 4734 4735 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4736 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4737 } 4738 4739 static int 4740 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4741 { 4742 int rval = QLA_SUCCESS; 4743 uint32_t idc_control; 4744 4745 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4746 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4747 4748 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4749 __qla83xx_get_idc_control(vha, &idc_control); 4750 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4751 __qla83xx_set_idc_control(vha, 0); 4752 4753 qla83xx_idc_unlock(vha, 0); 4754 rval = qla83xx_restart_nic_firmware(vha); 4755 qla83xx_idc_lock(vha, 0); 4756 4757 if (rval != QLA_SUCCESS) { 4758 ql_log(ql_log_fatal, vha, 0xb06a, 4759 "Failed to restart NIC f/w.\n"); 4760 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4761 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4762 } else { 4763 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4764 "Success in restarting nic f/w.\n"); 4765 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4766 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4767 } 4768 4769 return rval; 4770 } 4771 4772 /* Assumes idc_lock always held on entry */ 4773 int 4774 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4775 { 4776 struct qla_hw_data *ha = base_vha->hw; 4777 int rval = QLA_SUCCESS; 4778 unsigned long dev_init_timeout; 4779 uint32_t dev_state; 4780 4781 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4782 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4783 4784 while (1) { 4785 4786 if (time_after_eq(jiffies, dev_init_timeout)) { 4787 ql_log(ql_log_warn, base_vha, 0xb06e, 4788 "Initialization TIMEOUT!\n"); 4789 /* Init timeout. Disable further NIC Core 4790 * communication. 4791 */ 4792 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4793 QLA8XXX_DEV_FAILED); 4794 ql_log(ql_log_info, base_vha, 0xb06f, 4795 "HW State: FAILED.\n"); 4796 } 4797 4798 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4799 switch (dev_state) { 4800 case QLA8XXX_DEV_READY: 4801 if (ha->flags.nic_core_reset_owner) 4802 qla83xx_idc_audit(base_vha, 4803 IDC_AUDIT_COMPLETION); 4804 ha->flags.nic_core_reset_owner = 0; 4805 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4806 "Reset_owner reset by 0x%x.\n", 4807 ha->portnum); 4808 goto exit; 4809 case QLA8XXX_DEV_COLD: 4810 if (ha->flags.nic_core_reset_owner) 4811 rval = qla83xx_device_bootstrap(base_vha); 4812 else { 4813 /* Wait for AEN to change device-state */ 4814 qla83xx_idc_unlock(base_vha, 0); 4815 msleep(1000); 4816 qla83xx_idc_lock(base_vha, 0); 4817 } 4818 break; 4819 case QLA8XXX_DEV_INITIALIZING: 4820 /* Wait for AEN to change device-state */ 4821 qla83xx_idc_unlock(base_vha, 0); 4822 msleep(1000); 4823 qla83xx_idc_lock(base_vha, 0); 4824 break; 4825 case QLA8XXX_DEV_NEED_RESET: 4826 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4827 qla83xx_need_reset_handler(base_vha); 4828 else { 4829 /* Wait for AEN to change device-state */ 4830 qla83xx_idc_unlock(base_vha, 0); 4831 msleep(1000); 4832 qla83xx_idc_lock(base_vha, 0); 4833 } 4834 /* reset timeout value after need reset handler */ 4835 dev_init_timeout = jiffies + 4836 (ha->fcoe_dev_init_timeout * HZ); 4837 break; 4838 case QLA8XXX_DEV_NEED_QUIESCENT: 4839 /* XXX: DEBUG for now */ 4840 qla83xx_idc_unlock(base_vha, 0); 4841 msleep(1000); 4842 qla83xx_idc_lock(base_vha, 0); 4843 break; 4844 case QLA8XXX_DEV_QUIESCENT: 4845 /* XXX: DEBUG for now */ 4846 if (ha->flags.quiesce_owner) 4847 goto exit; 4848 4849 qla83xx_idc_unlock(base_vha, 0); 4850 msleep(1000); 4851 qla83xx_idc_lock(base_vha, 0); 4852 dev_init_timeout = jiffies + 4853 (ha->fcoe_dev_init_timeout * HZ); 4854 break; 4855 case QLA8XXX_DEV_FAILED: 4856 if (ha->flags.nic_core_reset_owner) 4857 qla83xx_idc_audit(base_vha, 4858 IDC_AUDIT_COMPLETION); 4859 ha->flags.nic_core_reset_owner = 0; 4860 __qla83xx_clear_drv_presence(base_vha); 4861 qla83xx_idc_unlock(base_vha, 0); 4862 qla8xxx_dev_failed_handler(base_vha); 4863 rval = QLA_FUNCTION_FAILED; 4864 qla83xx_idc_lock(base_vha, 0); 4865 goto exit; 4866 case QLA8XXX_BAD_VALUE: 4867 qla83xx_idc_unlock(base_vha, 0); 4868 msleep(1000); 4869 qla83xx_idc_lock(base_vha, 0); 4870 break; 4871 default: 4872 ql_log(ql_log_warn, base_vha, 0xb071, 4873 "Unknown Device State: %x.\n", dev_state); 4874 qla83xx_idc_unlock(base_vha, 0); 4875 qla8xxx_dev_failed_handler(base_vha); 4876 rval = QLA_FUNCTION_FAILED; 4877 qla83xx_idc_lock(base_vha, 0); 4878 goto exit; 4879 } 4880 } 4881 4882 exit: 4883 return rval; 4884 } 4885 4886 void 4887 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4888 { 4889 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4890 board_disable); 4891 struct pci_dev *pdev = ha->pdev; 4892 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4893 4894 ql_log(ql_log_warn, base_vha, 0x015b, 4895 "Disabling adapter.\n"); 4896 4897 set_bit(UNLOADING, &base_vha->dpc_flags); 4898 4899 qla2x00_delete_all_vps(ha, base_vha); 4900 4901 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4902 4903 qla2x00_dfs_remove(base_vha); 4904 4905 qla84xx_put_chip(base_vha); 4906 4907 if (base_vha->timer_active) 4908 qla2x00_stop_timer(base_vha); 4909 4910 base_vha->flags.online = 0; 4911 4912 qla2x00_destroy_deferred_work(ha); 4913 4914 /* 4915 * Do not try to stop beacon blink as it will issue a mailbox 4916 * command. 4917 */ 4918 qla2x00_free_sysfs_attr(base_vha, false); 4919 4920 fc_remove_host(base_vha->host); 4921 4922 scsi_remove_host(base_vha->host); 4923 4924 base_vha->flags.init_done = 0; 4925 qla25xx_delete_queues(base_vha); 4926 qla2x00_free_irqs(base_vha); 4927 qla2x00_free_fcports(base_vha); 4928 qla2x00_mem_free(ha); 4929 qla82xx_md_free(base_vha); 4930 qla2x00_free_queues(ha); 4931 4932 qla2x00_unmap_iobases(ha); 4933 4934 pci_release_selected_regions(ha->pdev, ha->bars); 4935 pci_disable_pcie_error_reporting(pdev); 4936 pci_disable_device(pdev); 4937 4938 /* 4939 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 4940 */ 4941 } 4942 4943 /************************************************************************** 4944 * qla2x00_do_dpc 4945 * This kernel thread is a task that is schedule by the interrupt handler 4946 * to perform the background processing for interrupts. 4947 * 4948 * Notes: 4949 * This task always run in the context of a kernel thread. It 4950 * is kick-off by the driver's detect code and starts up 4951 * up one per adapter. It immediately goes to sleep and waits for 4952 * some fibre event. When either the interrupt handler or 4953 * the timer routine detects a event it will one of the task 4954 * bits then wake us up. 4955 **************************************************************************/ 4956 static int 4957 qla2x00_do_dpc(void *data) 4958 { 4959 scsi_qla_host_t *base_vha; 4960 struct qla_hw_data *ha; 4961 4962 ha = (struct qla_hw_data *)data; 4963 base_vha = pci_get_drvdata(ha->pdev); 4964 4965 set_user_nice(current, MIN_NICE); 4966 4967 set_current_state(TASK_INTERRUPTIBLE); 4968 while (!kthread_should_stop()) { 4969 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4970 "DPC handler sleeping.\n"); 4971 4972 schedule(); 4973 4974 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4975 goto end_loop; 4976 4977 if (ha->flags.eeh_busy) { 4978 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4979 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4980 goto end_loop; 4981 } 4982 4983 ha->dpc_active = 1; 4984 4985 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4986 "DPC handler waking up, dpc_flags=0x%lx.\n", 4987 base_vha->dpc_flags); 4988 4989 qla2x00_do_work(base_vha); 4990 4991 if (IS_P3P_TYPE(ha)) { 4992 if (IS_QLA8044(ha)) { 4993 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4994 &base_vha->dpc_flags)) { 4995 qla8044_idc_lock(ha); 4996 qla8044_wr_direct(base_vha, 4997 QLA8044_CRB_DEV_STATE_INDEX, 4998 QLA8XXX_DEV_FAILED); 4999 qla8044_idc_unlock(ha); 5000 ql_log(ql_log_info, base_vha, 0x4004, 5001 "HW State: FAILED.\n"); 5002 qla8044_device_state_handler(base_vha); 5003 continue; 5004 } 5005 5006 } else { 5007 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5008 &base_vha->dpc_flags)) { 5009 qla82xx_idc_lock(ha); 5010 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5011 QLA8XXX_DEV_FAILED); 5012 qla82xx_idc_unlock(ha); 5013 ql_log(ql_log_info, base_vha, 0x0151, 5014 "HW State: FAILED.\n"); 5015 qla82xx_device_state_handler(base_vha); 5016 continue; 5017 } 5018 } 5019 5020 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5021 &base_vha->dpc_flags)) { 5022 5023 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5024 "FCoE context reset scheduled.\n"); 5025 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5026 &base_vha->dpc_flags))) { 5027 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5028 /* FCoE-ctx reset failed. 5029 * Escalate to chip-reset 5030 */ 5031 set_bit(ISP_ABORT_NEEDED, 5032 &base_vha->dpc_flags); 5033 } 5034 clear_bit(ABORT_ISP_ACTIVE, 5035 &base_vha->dpc_flags); 5036 } 5037 5038 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5039 "FCoE context reset end.\n"); 5040 } 5041 } else if (IS_QLAFX00(ha)) { 5042 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5043 &base_vha->dpc_flags)) { 5044 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5045 "Firmware Reset Recovery\n"); 5046 if (qlafx00_reset_initialize(base_vha)) { 5047 /* Failed. Abort isp later. */ 5048 if (!test_bit(UNLOADING, 5049 &base_vha->dpc_flags)) { 5050 set_bit(ISP_UNRECOVERABLE, 5051 &base_vha->dpc_flags); 5052 ql_dbg(ql_dbg_dpc, base_vha, 5053 0x4021, 5054 "Reset Recovery Failed\n"); 5055 } 5056 } 5057 } 5058 5059 if (test_and_clear_bit(FX00_TARGET_SCAN, 5060 &base_vha->dpc_flags)) { 5061 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5062 "ISPFx00 Target Scan scheduled\n"); 5063 if (qlafx00_rescan_isp(base_vha)) { 5064 if (!test_bit(UNLOADING, 5065 &base_vha->dpc_flags)) 5066 set_bit(ISP_UNRECOVERABLE, 5067 &base_vha->dpc_flags); 5068 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5069 "ISPFx00 Target Scan Failed\n"); 5070 } 5071 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5072 "ISPFx00 Target Scan End\n"); 5073 } 5074 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5075 &base_vha->dpc_flags)) { 5076 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5077 "ISPFx00 Host Info resend scheduled\n"); 5078 qlafx00_fx_disc(base_vha, 5079 &base_vha->hw->mr.fcport, 5080 FXDISC_REG_HOST_INFO); 5081 } 5082 } 5083 5084 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5085 &base_vha->dpc_flags)) { 5086 5087 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5088 "ISP abort scheduled.\n"); 5089 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5090 &base_vha->dpc_flags))) { 5091 5092 if (ha->isp_ops->abort_isp(base_vha)) { 5093 /* failed. retry later */ 5094 set_bit(ISP_ABORT_NEEDED, 5095 &base_vha->dpc_flags); 5096 } 5097 clear_bit(ABORT_ISP_ACTIVE, 5098 &base_vha->dpc_flags); 5099 } 5100 5101 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5102 "ISP abort end.\n"); 5103 } 5104 5105 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5106 &base_vha->dpc_flags)) { 5107 qla2x00_update_fcports(base_vha); 5108 } 5109 5110 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 5111 int ret; 5112 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 5113 if (ret != QLA_SUCCESS) 5114 ql_log(ql_log_warn, base_vha, 0x121, 5115 "Failed to enable receiving of RSCN " 5116 "requests: 0x%x.\n", ret); 5117 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 5118 } 5119 5120 if (IS_QLAFX00(ha)) 5121 goto loop_resync_check; 5122 5123 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5124 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5125 "Quiescence mode scheduled.\n"); 5126 if (IS_P3P_TYPE(ha)) { 5127 if (IS_QLA82XX(ha)) 5128 qla82xx_device_state_handler(base_vha); 5129 if (IS_QLA8044(ha)) 5130 qla8044_device_state_handler(base_vha); 5131 clear_bit(ISP_QUIESCE_NEEDED, 5132 &base_vha->dpc_flags); 5133 if (!ha->flags.quiesce_owner) { 5134 qla2x00_perform_loop_resync(base_vha); 5135 if (IS_QLA82XX(ha)) { 5136 qla82xx_idc_lock(ha); 5137 qla82xx_clear_qsnt_ready( 5138 base_vha); 5139 qla82xx_idc_unlock(ha); 5140 } else if (IS_QLA8044(ha)) { 5141 qla8044_idc_lock(ha); 5142 qla8044_clear_qsnt_ready( 5143 base_vha); 5144 qla8044_idc_unlock(ha); 5145 } 5146 } 5147 } else { 5148 clear_bit(ISP_QUIESCE_NEEDED, 5149 &base_vha->dpc_flags); 5150 qla2x00_quiesce_io(base_vha); 5151 } 5152 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5153 "Quiescence mode end.\n"); 5154 } 5155 5156 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5157 &base_vha->dpc_flags) && 5158 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5159 5160 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5161 "Reset marker scheduled.\n"); 5162 qla2x00_rst_aen(base_vha); 5163 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5164 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5165 "Reset marker end.\n"); 5166 } 5167 5168 /* Retry each device up to login retry count */ 5169 if ((test_and_clear_bit(RELOGIN_NEEDED, 5170 &base_vha->dpc_flags)) && 5171 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5172 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5173 5174 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5175 "Relogin scheduled.\n"); 5176 qla2x00_relogin(base_vha); 5177 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5178 "Relogin end.\n"); 5179 } 5180 loop_resync_check: 5181 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5182 &base_vha->dpc_flags)) { 5183 5184 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5185 "Loop resync scheduled.\n"); 5186 5187 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5188 &base_vha->dpc_flags))) { 5189 5190 qla2x00_loop_resync(base_vha); 5191 5192 clear_bit(LOOP_RESYNC_ACTIVE, 5193 &base_vha->dpc_flags); 5194 } 5195 5196 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5197 "Loop resync end.\n"); 5198 } 5199 5200 if (IS_QLAFX00(ha)) 5201 goto intr_on_check; 5202 5203 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5204 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5205 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5206 qla2xxx_flash_npiv_conf(base_vha); 5207 } 5208 5209 intr_on_check: 5210 if (!ha->interrupts_on) 5211 ha->isp_ops->enable_intrs(ha); 5212 5213 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5214 &base_vha->dpc_flags)) { 5215 if (ha->beacon_blink_led == 1) 5216 ha->isp_ops->beacon_blink(base_vha); 5217 } 5218 5219 if (!IS_QLAFX00(ha)) 5220 qla2x00_do_dpc_all_vps(base_vha); 5221 5222 ha->dpc_active = 0; 5223 end_loop: 5224 set_current_state(TASK_INTERRUPTIBLE); 5225 } /* End of while(1) */ 5226 __set_current_state(TASK_RUNNING); 5227 5228 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5229 "DPC handler exiting.\n"); 5230 5231 /* 5232 * Make sure that nobody tries to wake us up again. 5233 */ 5234 ha->dpc_active = 0; 5235 5236 /* Cleanup any residual CTX SRBs. */ 5237 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5238 5239 return 0; 5240 } 5241 5242 void 5243 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5244 { 5245 struct qla_hw_data *ha = vha->hw; 5246 struct task_struct *t = ha->dpc_thread; 5247 5248 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5249 wake_up_process(t); 5250 } 5251 5252 /* 5253 * qla2x00_rst_aen 5254 * Processes asynchronous reset. 5255 * 5256 * Input: 5257 * ha = adapter block pointer. 5258 */ 5259 static void 5260 qla2x00_rst_aen(scsi_qla_host_t *vha) 5261 { 5262 if (vha->flags.online && !vha->flags.reset_active && 5263 !atomic_read(&vha->loop_down_timer) && 5264 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5265 do { 5266 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5267 5268 /* 5269 * Issue marker command only when we are going to start 5270 * the I/O. 5271 */ 5272 vha->marker_needed = 1; 5273 } while (!atomic_read(&vha->loop_down_timer) && 5274 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5275 } 5276 } 5277 5278 /************************************************************************** 5279 * qla2x00_timer 5280 * 5281 * Description: 5282 * One second timer 5283 * 5284 * Context: Interrupt 5285 ***************************************************************************/ 5286 void 5287 qla2x00_timer(scsi_qla_host_t *vha) 5288 { 5289 unsigned long cpu_flags = 0; 5290 int start_dpc = 0; 5291 int index; 5292 srb_t *sp; 5293 uint16_t w; 5294 struct qla_hw_data *ha = vha->hw; 5295 struct req_que *req; 5296 5297 if (ha->flags.eeh_busy) { 5298 ql_dbg(ql_dbg_timer, vha, 0x6000, 5299 "EEH = %d, restarting timer.\n", 5300 ha->flags.eeh_busy); 5301 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5302 return; 5303 } 5304 5305 /* 5306 * Hardware read to raise pending EEH errors during mailbox waits. If 5307 * the read returns -1 then disable the board. 5308 */ 5309 if (!pci_channel_offline(ha->pdev)) { 5310 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5311 qla2x00_check_reg16_for_disconnect(vha, w); 5312 } 5313 5314 /* Make sure qla82xx_watchdog is run only for physical port */ 5315 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5316 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5317 start_dpc++; 5318 if (IS_QLA82XX(ha)) 5319 qla82xx_watchdog(vha); 5320 else if (IS_QLA8044(ha)) 5321 qla8044_watchdog(vha); 5322 } 5323 5324 if (!vha->vp_idx && IS_QLAFX00(ha)) 5325 qlafx00_timer_routine(vha); 5326 5327 /* Loop down handler. */ 5328 if (atomic_read(&vha->loop_down_timer) > 0 && 5329 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5330 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5331 && vha->flags.online) { 5332 5333 if (atomic_read(&vha->loop_down_timer) == 5334 vha->loop_down_abort_time) { 5335 5336 ql_log(ql_log_info, vha, 0x6008, 5337 "Loop down - aborting the queues before time expires.\n"); 5338 5339 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5340 atomic_set(&vha->loop_state, LOOP_DEAD); 5341 5342 /* 5343 * Schedule an ISP abort to return any FCP2-device 5344 * commands. 5345 */ 5346 /* NPIV - scan physical port only */ 5347 if (!vha->vp_idx) { 5348 spin_lock_irqsave(&ha->hardware_lock, 5349 cpu_flags); 5350 req = ha->req_q_map[0]; 5351 for (index = 1; 5352 index < req->num_outstanding_cmds; 5353 index++) { 5354 fc_port_t *sfcp; 5355 5356 sp = req->outstanding_cmds[index]; 5357 if (!sp) 5358 continue; 5359 if (sp->type != SRB_SCSI_CMD) 5360 continue; 5361 sfcp = sp->fcport; 5362 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5363 continue; 5364 5365 if (IS_QLA82XX(ha)) 5366 set_bit(FCOE_CTX_RESET_NEEDED, 5367 &vha->dpc_flags); 5368 else 5369 set_bit(ISP_ABORT_NEEDED, 5370 &vha->dpc_flags); 5371 break; 5372 } 5373 spin_unlock_irqrestore(&ha->hardware_lock, 5374 cpu_flags); 5375 } 5376 start_dpc++; 5377 } 5378 5379 /* if the loop has been down for 4 minutes, reinit adapter */ 5380 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5381 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5382 ql_log(ql_log_warn, vha, 0x6009, 5383 "Loop down - aborting ISP.\n"); 5384 5385 if (IS_QLA82XX(ha)) 5386 set_bit(FCOE_CTX_RESET_NEEDED, 5387 &vha->dpc_flags); 5388 else 5389 set_bit(ISP_ABORT_NEEDED, 5390 &vha->dpc_flags); 5391 } 5392 } 5393 ql_dbg(ql_dbg_timer, vha, 0x600a, 5394 "Loop down - seconds remaining %d.\n", 5395 atomic_read(&vha->loop_down_timer)); 5396 } 5397 /* Check if beacon LED needs to be blinked for physical host only */ 5398 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5399 /* There is no beacon_blink function for ISP82xx */ 5400 if (!IS_P3P_TYPE(ha)) { 5401 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5402 start_dpc++; 5403 } 5404 } 5405 5406 /* Process any deferred work. */ 5407 if (!list_empty(&vha->work_list)) 5408 start_dpc++; 5409 5410 /* Schedule the DPC routine if needed */ 5411 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5412 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5413 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5414 start_dpc || 5415 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5416 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5417 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5418 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5419 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5420 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5421 ql_dbg(ql_dbg_timer, vha, 0x600b, 5422 "isp_abort_needed=%d loop_resync_needed=%d " 5423 "fcport_update_needed=%d start_dpc=%d " 5424 "reset_marker_needed=%d", 5425 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5426 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5427 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5428 start_dpc, 5429 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5430 ql_dbg(ql_dbg_timer, vha, 0x600c, 5431 "beacon_blink_needed=%d isp_unrecoverable=%d " 5432 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5433 "relogin_needed=%d.\n", 5434 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5435 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5436 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5437 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5438 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5439 qla2xxx_wake_dpc(vha); 5440 } 5441 5442 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5443 } 5444 5445 /* Firmware interface routines. */ 5446 5447 #define FW_BLOBS 11 5448 #define FW_ISP21XX 0 5449 #define FW_ISP22XX 1 5450 #define FW_ISP2300 2 5451 #define FW_ISP2322 3 5452 #define FW_ISP24XX 4 5453 #define FW_ISP25XX 5 5454 #define FW_ISP81XX 6 5455 #define FW_ISP82XX 7 5456 #define FW_ISP2031 8 5457 #define FW_ISP8031 9 5458 #define FW_ISP27XX 10 5459 5460 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5461 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5462 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5463 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5464 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5465 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5466 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5467 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5468 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5469 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5470 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5471 5472 5473 static DEFINE_MUTEX(qla_fw_lock); 5474 5475 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5476 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5477 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5478 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5479 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5480 { .name = FW_FILE_ISP24XX, }, 5481 { .name = FW_FILE_ISP25XX, }, 5482 { .name = FW_FILE_ISP81XX, }, 5483 { .name = FW_FILE_ISP82XX, }, 5484 { .name = FW_FILE_ISP2031, }, 5485 { .name = FW_FILE_ISP8031, }, 5486 { .name = FW_FILE_ISP27XX, }, 5487 }; 5488 5489 struct fw_blob * 5490 qla2x00_request_firmware(scsi_qla_host_t *vha) 5491 { 5492 struct qla_hw_data *ha = vha->hw; 5493 struct fw_blob *blob; 5494 5495 if (IS_QLA2100(ha)) { 5496 blob = &qla_fw_blobs[FW_ISP21XX]; 5497 } else if (IS_QLA2200(ha)) { 5498 blob = &qla_fw_blobs[FW_ISP22XX]; 5499 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5500 blob = &qla_fw_blobs[FW_ISP2300]; 5501 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5502 blob = &qla_fw_blobs[FW_ISP2322]; 5503 } else if (IS_QLA24XX_TYPE(ha)) { 5504 blob = &qla_fw_blobs[FW_ISP24XX]; 5505 } else if (IS_QLA25XX(ha)) { 5506 blob = &qla_fw_blobs[FW_ISP25XX]; 5507 } else if (IS_QLA81XX(ha)) { 5508 blob = &qla_fw_blobs[FW_ISP81XX]; 5509 } else if (IS_QLA82XX(ha)) { 5510 blob = &qla_fw_blobs[FW_ISP82XX]; 5511 } else if (IS_QLA2031(ha)) { 5512 blob = &qla_fw_blobs[FW_ISP2031]; 5513 } else if (IS_QLA8031(ha)) { 5514 blob = &qla_fw_blobs[FW_ISP8031]; 5515 } else if (IS_QLA27XX(ha)) { 5516 blob = &qla_fw_blobs[FW_ISP27XX]; 5517 } else { 5518 return NULL; 5519 } 5520 5521 mutex_lock(&qla_fw_lock); 5522 if (blob->fw) 5523 goto out; 5524 5525 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5526 ql_log(ql_log_warn, vha, 0x0063, 5527 "Failed to load firmware image (%s).\n", blob->name); 5528 blob->fw = NULL; 5529 blob = NULL; 5530 goto out; 5531 } 5532 5533 out: 5534 mutex_unlock(&qla_fw_lock); 5535 return blob; 5536 } 5537 5538 static void 5539 qla2x00_release_firmware(void) 5540 { 5541 int idx; 5542 5543 mutex_lock(&qla_fw_lock); 5544 for (idx = 0; idx < FW_BLOBS; idx++) 5545 release_firmware(qla_fw_blobs[idx].fw); 5546 mutex_unlock(&qla_fw_lock); 5547 } 5548 5549 static pci_ers_result_t 5550 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5551 { 5552 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5553 struct qla_hw_data *ha = vha->hw; 5554 5555 ql_dbg(ql_dbg_aer, vha, 0x9000, 5556 "PCI error detected, state %x.\n", state); 5557 5558 switch (state) { 5559 case pci_channel_io_normal: 5560 ha->flags.eeh_busy = 0; 5561 return PCI_ERS_RESULT_CAN_RECOVER; 5562 case pci_channel_io_frozen: 5563 ha->flags.eeh_busy = 1; 5564 /* For ISP82XX complete any pending mailbox cmd */ 5565 if (IS_QLA82XX(ha)) { 5566 ha->flags.isp82xx_fw_hung = 1; 5567 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5568 qla82xx_clear_pending_mbx(vha); 5569 } 5570 qla2x00_free_irqs(vha); 5571 pci_disable_device(pdev); 5572 /* Return back all IOs */ 5573 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5574 return PCI_ERS_RESULT_NEED_RESET; 5575 case pci_channel_io_perm_failure: 5576 ha->flags.pci_channel_io_perm_failure = 1; 5577 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5578 return PCI_ERS_RESULT_DISCONNECT; 5579 } 5580 return PCI_ERS_RESULT_NEED_RESET; 5581 } 5582 5583 static pci_ers_result_t 5584 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5585 { 5586 int risc_paused = 0; 5587 uint32_t stat; 5588 unsigned long flags; 5589 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5590 struct qla_hw_data *ha = base_vha->hw; 5591 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5592 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5593 5594 if (IS_QLA82XX(ha)) 5595 return PCI_ERS_RESULT_RECOVERED; 5596 5597 spin_lock_irqsave(&ha->hardware_lock, flags); 5598 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5599 stat = RD_REG_DWORD(®->hccr); 5600 if (stat & HCCR_RISC_PAUSE) 5601 risc_paused = 1; 5602 } else if (IS_QLA23XX(ha)) { 5603 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5604 if (stat & HSR_RISC_PAUSED) 5605 risc_paused = 1; 5606 } else if (IS_FWI2_CAPABLE(ha)) { 5607 stat = RD_REG_DWORD(®24->host_status); 5608 if (stat & HSRX_RISC_PAUSED) 5609 risc_paused = 1; 5610 } 5611 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5612 5613 if (risc_paused) { 5614 ql_log(ql_log_info, base_vha, 0x9003, 5615 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5616 ha->isp_ops->fw_dump(base_vha, 0); 5617 5618 return PCI_ERS_RESULT_NEED_RESET; 5619 } else 5620 return PCI_ERS_RESULT_RECOVERED; 5621 } 5622 5623 static uint32_t 5624 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5625 { 5626 uint32_t rval = QLA_FUNCTION_FAILED; 5627 uint32_t drv_active = 0; 5628 struct qla_hw_data *ha = base_vha->hw; 5629 int fn; 5630 struct pci_dev *other_pdev = NULL; 5631 5632 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5633 "Entered %s.\n", __func__); 5634 5635 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5636 5637 if (base_vha->flags.online) { 5638 /* Abort all outstanding commands, 5639 * so as to be requeued later */ 5640 qla2x00_abort_isp_cleanup(base_vha); 5641 } 5642 5643 5644 fn = PCI_FUNC(ha->pdev->devfn); 5645 while (fn > 0) { 5646 fn--; 5647 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5648 "Finding pci device at function = 0x%x.\n", fn); 5649 other_pdev = 5650 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5651 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5652 fn)); 5653 5654 if (!other_pdev) 5655 continue; 5656 if (atomic_read(&other_pdev->enable_cnt)) { 5657 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5658 "Found PCI func available and enable at 0x%x.\n", 5659 fn); 5660 pci_dev_put(other_pdev); 5661 break; 5662 } 5663 pci_dev_put(other_pdev); 5664 } 5665 5666 if (!fn) { 5667 /* Reset owner */ 5668 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5669 "This devfn is reset owner = 0x%x.\n", 5670 ha->pdev->devfn); 5671 qla82xx_idc_lock(ha); 5672 5673 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5674 QLA8XXX_DEV_INITIALIZING); 5675 5676 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5677 QLA82XX_IDC_VERSION); 5678 5679 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5680 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5681 "drv_active = 0x%x.\n", drv_active); 5682 5683 qla82xx_idc_unlock(ha); 5684 /* Reset if device is not already reset 5685 * drv_active would be 0 if a reset has already been done 5686 */ 5687 if (drv_active) 5688 rval = qla82xx_start_firmware(base_vha); 5689 else 5690 rval = QLA_SUCCESS; 5691 qla82xx_idc_lock(ha); 5692 5693 if (rval != QLA_SUCCESS) { 5694 ql_log(ql_log_info, base_vha, 0x900b, 5695 "HW State: FAILED.\n"); 5696 qla82xx_clear_drv_active(ha); 5697 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5698 QLA8XXX_DEV_FAILED); 5699 } else { 5700 ql_log(ql_log_info, base_vha, 0x900c, 5701 "HW State: READY.\n"); 5702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5703 QLA8XXX_DEV_READY); 5704 qla82xx_idc_unlock(ha); 5705 ha->flags.isp82xx_fw_hung = 0; 5706 rval = qla82xx_restart_isp(base_vha); 5707 qla82xx_idc_lock(ha); 5708 /* Clear driver state register */ 5709 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5710 qla82xx_set_drv_active(base_vha); 5711 } 5712 qla82xx_idc_unlock(ha); 5713 } else { 5714 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5715 "This devfn is not reset owner = 0x%x.\n", 5716 ha->pdev->devfn); 5717 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5718 QLA8XXX_DEV_READY)) { 5719 ha->flags.isp82xx_fw_hung = 0; 5720 rval = qla82xx_restart_isp(base_vha); 5721 qla82xx_idc_lock(ha); 5722 qla82xx_set_drv_active(base_vha); 5723 qla82xx_idc_unlock(ha); 5724 } 5725 } 5726 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5727 5728 return rval; 5729 } 5730 5731 static pci_ers_result_t 5732 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5733 { 5734 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5735 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5736 struct qla_hw_data *ha = base_vha->hw; 5737 struct rsp_que *rsp; 5738 int rc, retries = 10; 5739 5740 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5741 "Slot Reset.\n"); 5742 5743 /* Workaround: qla2xxx driver which access hardware earlier 5744 * needs error state to be pci_channel_io_online. 5745 * Otherwise mailbox command timesout. 5746 */ 5747 pdev->error_state = pci_channel_io_normal; 5748 5749 pci_restore_state(pdev); 5750 5751 /* pci_restore_state() clears the saved_state flag of the device 5752 * save restored state which resets saved_state flag 5753 */ 5754 pci_save_state(pdev); 5755 5756 if (ha->mem_only) 5757 rc = pci_enable_device_mem(pdev); 5758 else 5759 rc = pci_enable_device(pdev); 5760 5761 if (rc) { 5762 ql_log(ql_log_warn, base_vha, 0x9005, 5763 "Can't re-enable PCI device after reset.\n"); 5764 goto exit_slot_reset; 5765 } 5766 5767 rsp = ha->rsp_q_map[0]; 5768 if (qla2x00_request_irqs(ha, rsp)) 5769 goto exit_slot_reset; 5770 5771 if (ha->isp_ops->pci_config(base_vha)) 5772 goto exit_slot_reset; 5773 5774 if (IS_QLA82XX(ha)) { 5775 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5776 ret = PCI_ERS_RESULT_RECOVERED; 5777 goto exit_slot_reset; 5778 } else 5779 goto exit_slot_reset; 5780 } 5781 5782 while (ha->flags.mbox_busy && retries--) 5783 msleep(1000); 5784 5785 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5786 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5787 ret = PCI_ERS_RESULT_RECOVERED; 5788 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5789 5790 5791 exit_slot_reset: 5792 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5793 "slot_reset return %x.\n", ret); 5794 5795 return ret; 5796 } 5797 5798 static void 5799 qla2xxx_pci_resume(struct pci_dev *pdev) 5800 { 5801 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5802 struct qla_hw_data *ha = base_vha->hw; 5803 int ret; 5804 5805 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5806 "pci_resume.\n"); 5807 5808 ret = qla2x00_wait_for_hba_online(base_vha); 5809 if (ret != QLA_SUCCESS) { 5810 ql_log(ql_log_fatal, base_vha, 0x9002, 5811 "The device failed to resume I/O from slot/link_reset.\n"); 5812 } 5813 5814 pci_cleanup_aer_uncorrect_error_status(pdev); 5815 5816 ha->flags.eeh_busy = 0; 5817 } 5818 5819 static void 5820 qla83xx_disable_laser(scsi_qla_host_t *vha) 5821 { 5822 uint32_t reg, data, fn; 5823 struct qla_hw_data *ha = vha->hw; 5824 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 5825 5826 /* pci func #/port # */ 5827 ql_dbg(ql_dbg_init, vha, 0x004b, 5828 "Disabling Laser for hba: %p\n", vha); 5829 5830 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 5831 (BIT_15|BIT_14|BIT_13|BIT_12)); 5832 5833 fn = (fn >> 12); 5834 5835 if (fn & 1) 5836 reg = PORT_1_2031; 5837 else 5838 reg = PORT_0_2031; 5839 5840 data = LASER_OFF_2031; 5841 5842 qla83xx_wr_reg(vha, reg, data); 5843 } 5844 5845 static const struct pci_error_handlers qla2xxx_err_handler = { 5846 .error_detected = qla2xxx_pci_error_detected, 5847 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5848 .slot_reset = qla2xxx_pci_slot_reset, 5849 .resume = qla2xxx_pci_resume, 5850 }; 5851 5852 static struct pci_device_id qla2xxx_pci_tbl[] = { 5853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5872 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 5873 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 5874 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 5875 { 0 }, 5876 }; 5877 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5878 5879 static struct pci_driver qla2xxx_pci_driver = { 5880 .name = QLA2XXX_DRIVER_NAME, 5881 .driver = { 5882 .owner = THIS_MODULE, 5883 }, 5884 .id_table = qla2xxx_pci_tbl, 5885 .probe = qla2x00_probe_one, 5886 .remove = qla2x00_remove_one, 5887 .shutdown = qla2x00_shutdown, 5888 .err_handler = &qla2xxx_err_handler, 5889 }; 5890 5891 static const struct file_operations apidev_fops = { 5892 .owner = THIS_MODULE, 5893 .llseek = noop_llseek, 5894 }; 5895 5896 /** 5897 * qla2x00_module_init - Module initialization. 5898 **/ 5899 static int __init 5900 qla2x00_module_init(void) 5901 { 5902 int ret = 0; 5903 5904 /* Allocate cache for SRBs. */ 5905 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5906 SLAB_HWCACHE_ALIGN, NULL); 5907 if (srb_cachep == NULL) { 5908 ql_log(ql_log_fatal, NULL, 0x0001, 5909 "Unable to allocate SRB cache...Failing load!.\n"); 5910 return -ENOMEM; 5911 } 5912 5913 /* Initialize target kmem_cache and mem_pools */ 5914 ret = qlt_init(); 5915 if (ret < 0) { 5916 kmem_cache_destroy(srb_cachep); 5917 return ret; 5918 } else if (ret > 0) { 5919 /* 5920 * If initiator mode is explictly disabled by qlt_init(), 5921 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5922 * performing scsi_scan_target() during LOOP UP event. 5923 */ 5924 qla2xxx_transport_functions.disable_target_scan = 1; 5925 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5926 } 5927 5928 /* Derive version string. */ 5929 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5930 if (ql2xextended_error_logging) 5931 strcat(qla2x00_version_str, "-debug"); 5932 5933 qla2xxx_transport_template = 5934 fc_attach_transport(&qla2xxx_transport_functions); 5935 if (!qla2xxx_transport_template) { 5936 kmem_cache_destroy(srb_cachep); 5937 ql_log(ql_log_fatal, NULL, 0x0002, 5938 "fc_attach_transport failed...Failing load!.\n"); 5939 qlt_exit(); 5940 return -ENODEV; 5941 } 5942 5943 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5944 if (apidev_major < 0) { 5945 ql_log(ql_log_fatal, NULL, 0x0003, 5946 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5947 } 5948 5949 qla2xxx_transport_vport_template = 5950 fc_attach_transport(&qla2xxx_transport_vport_functions); 5951 if (!qla2xxx_transport_vport_template) { 5952 kmem_cache_destroy(srb_cachep); 5953 qlt_exit(); 5954 fc_release_transport(qla2xxx_transport_template); 5955 ql_log(ql_log_fatal, NULL, 0x0004, 5956 "fc_attach_transport vport failed...Failing load!.\n"); 5957 return -ENODEV; 5958 } 5959 ql_log(ql_log_info, NULL, 0x0005, 5960 "QLogic Fibre Channel HBA Driver: %s.\n", 5961 qla2x00_version_str); 5962 ret = pci_register_driver(&qla2xxx_pci_driver); 5963 if (ret) { 5964 kmem_cache_destroy(srb_cachep); 5965 qlt_exit(); 5966 fc_release_transport(qla2xxx_transport_template); 5967 fc_release_transport(qla2xxx_transport_vport_template); 5968 ql_log(ql_log_fatal, NULL, 0x0006, 5969 "pci_register_driver failed...ret=%d Failing load!.\n", 5970 ret); 5971 } 5972 return ret; 5973 } 5974 5975 /** 5976 * qla2x00_module_exit - Module cleanup. 5977 **/ 5978 static void __exit 5979 qla2x00_module_exit(void) 5980 { 5981 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5982 pci_unregister_driver(&qla2xxx_pci_driver); 5983 qla2x00_release_firmware(); 5984 kmem_cache_destroy(srb_cachep); 5985 qlt_exit(); 5986 if (ctx_cachep) 5987 kmem_cache_destroy(ctx_cachep); 5988 fc_release_transport(qla2xxx_transport_template); 5989 fc_release_transport(qla2xxx_transport_vport_template); 5990 } 5991 5992 module_init(qla2x00_module_init); 5993 module_exit(qla2x00_module_exit); 5994 5995 MODULE_AUTHOR("QLogic Corporation"); 5996 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5997 MODULE_LICENSE("GPL"); 5998 MODULE_VERSION(QLA2XXX_VERSION); 5999 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6000 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6001 MODULE_FIRMWARE(FW_FILE_ISP2300); 6002 MODULE_FIRMWARE(FW_FILE_ISP2322); 6003 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6004 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6005