1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 int ql2xfulldump_on_mpifail; 39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 41 "Set this to take full dump on MPI hang."); 42 43 /* 44 * CT6 CTX allocation cache 45 */ 46 static struct kmem_cache *ctx_cachep; 47 /* 48 * error level for logging 49 */ 50 uint ql_errlev = 0x8001; 51 52 static int ql2xenableclass2; 53 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 54 MODULE_PARM_DESC(ql2xenableclass2, 55 "Specify if Class 2 operations are supported from the very " 56 "beginning. Default is 0 - class 2 not supported."); 57 58 59 int ql2xlogintimeout = 20; 60 module_param(ql2xlogintimeout, int, S_IRUGO); 61 MODULE_PARM_DESC(ql2xlogintimeout, 62 "Login timeout value in seconds."); 63 64 int qlport_down_retry; 65 module_param(qlport_down_retry, int, S_IRUGO); 66 MODULE_PARM_DESC(qlport_down_retry, 67 "Maximum number of command retries to a port that returns " 68 "a PORT-DOWN status."); 69 70 int ql2xplogiabsentdevice; 71 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 72 MODULE_PARM_DESC(ql2xplogiabsentdevice, 73 "Option to enable PLOGI to devices that are not present after " 74 "a Fabric scan. This is needed for several broken switches. " 75 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 76 77 int ql2xloginretrycount; 78 module_param(ql2xloginretrycount, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xloginretrycount, 80 "Specify an alternate value for the NVRAM login retry count."); 81 82 int ql2xallocfwdump = 1; 83 module_param(ql2xallocfwdump, int, S_IRUGO); 84 MODULE_PARM_DESC(ql2xallocfwdump, 85 "Option to enable allocation of memory for a firmware dump " 86 "during HBA initialization. Memory allocation requirements " 87 "vary by ISP type. Default is 1 - allocate memory."); 88 89 int ql2xextended_error_logging; 90 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 91 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 92 MODULE_PARM_DESC(ql2xextended_error_logging, 93 "Option to enable extended error logging,\n" 94 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 95 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 96 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 97 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 98 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 99 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 100 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 101 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 102 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 103 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 104 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 105 "\t\t0x1e400000 - Preferred value for capturing essential " 106 "debug information (equivalent to old " 107 "ql2xextended_error_logging=1).\n" 108 "\t\tDo LOGICAL OR of the value to enable more than one level"); 109 110 int ql2xshiftctondsd = 6; 111 module_param(ql2xshiftctondsd, int, S_IRUGO); 112 MODULE_PARM_DESC(ql2xshiftctondsd, 113 "Set to control shifting of command type processing " 114 "based on total number of SG elements."); 115 116 int ql2xfdmienable = 1; 117 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 118 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xfdmienable, 120 "Enables FDMI registrations. " 121 "0 - no FDMI registrations. " 122 "1 - provide FDMI registrations (default)."); 123 124 #define MAX_Q_DEPTH 64 125 static int ql2xmaxqdepth = MAX_Q_DEPTH; 126 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 127 MODULE_PARM_DESC(ql2xmaxqdepth, 128 "Maximum queue depth to set for each LUN. " 129 "Default is 64."); 130 131 int ql2xenabledif = 2; 132 module_param(ql2xenabledif, int, S_IRUGO); 133 MODULE_PARM_DESC(ql2xenabledif, 134 " Enable T10-CRC-DIF:\n" 135 " Default is 2.\n" 136 " 0 -- No DIF Support\n" 137 " 1 -- Enable DIF for all types\n" 138 " 2 -- Enable DIF for all types, except Type 0.\n"); 139 140 #if (IS_ENABLED(CONFIG_NVME_FC)) 141 int ql2xnvmeenable = 1; 142 #else 143 int ql2xnvmeenable; 144 #endif 145 module_param(ql2xnvmeenable, int, 0644); 146 MODULE_PARM_DESC(ql2xnvmeenable, 147 "Enables NVME support. " 148 "0 - no NVMe. Default is Y"); 149 150 int ql2xenablehba_err_chk = 2; 151 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 152 MODULE_PARM_DESC(ql2xenablehba_err_chk, 153 " Enable T10-CRC-DIF Error isolation by HBA:\n" 154 " Default is 2.\n" 155 " 0 -- Error isolation disabled\n" 156 " 1 -- Error isolation enabled only for DIX Type 0\n" 157 " 2 -- Error isolation enabled for all Types\n"); 158 159 int ql2xiidmaenable = 1; 160 module_param(ql2xiidmaenable, int, S_IRUGO); 161 MODULE_PARM_DESC(ql2xiidmaenable, 162 "Enables iIDMA settings " 163 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 164 165 int ql2xmqsupport = 1; 166 module_param(ql2xmqsupport, int, S_IRUGO); 167 MODULE_PARM_DESC(ql2xmqsupport, 168 "Enable on demand multiple queue pairs support " 169 "Default is 1 for supported. " 170 "Set it to 0 to turn off mq qpair support."); 171 172 int ql2xfwloadbin; 173 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 174 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 175 MODULE_PARM_DESC(ql2xfwloadbin, 176 "Option to specify location from which to load ISP firmware:.\n" 177 " 2 -- load firmware via the request_firmware() (hotplug).\n" 178 " interface.\n" 179 " 1 -- load firmware from flash.\n" 180 " 0 -- use default semantics.\n"); 181 182 int ql2xetsenable; 183 module_param(ql2xetsenable, int, S_IRUGO); 184 MODULE_PARM_DESC(ql2xetsenable, 185 "Enables firmware ETS burst." 186 "Default is 0 - skip ETS enablement."); 187 188 int ql2xdbwr = 1; 189 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 190 MODULE_PARM_DESC(ql2xdbwr, 191 "Option to specify scheme for request queue posting.\n" 192 " 0 -- Regular doorbell.\n" 193 " 1 -- CAMRAM doorbell (faster).\n"); 194 195 int ql2xtargetreset = 1; 196 module_param(ql2xtargetreset, int, S_IRUGO); 197 MODULE_PARM_DESC(ql2xtargetreset, 198 "Enable target reset." 199 "Default is 1 - use hw defaults."); 200 201 int ql2xgffidenable; 202 module_param(ql2xgffidenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xgffidenable, 204 "Enables GFF_ID checks of port type. " 205 "Default is 0 - Do not use GFF_ID information."); 206 207 int ql2xasynctmfenable = 1; 208 module_param(ql2xasynctmfenable, int, S_IRUGO); 209 MODULE_PARM_DESC(ql2xasynctmfenable, 210 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 211 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 212 213 int ql2xdontresethba; 214 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 215 MODULE_PARM_DESC(ql2xdontresethba, 216 "Option to specify reset behaviour.\n" 217 " 0 (Default) -- Reset on failure.\n" 218 " 1 -- Do not reset on failure.\n"); 219 220 uint64_t ql2xmaxlun = MAX_LUNS; 221 module_param(ql2xmaxlun, ullong, S_IRUGO); 222 MODULE_PARM_DESC(ql2xmaxlun, 223 "Defines the maximum LU number to register with the SCSI " 224 "midlayer. Default is 65535."); 225 226 int ql2xmdcapmask = 0x1F; 227 module_param(ql2xmdcapmask, int, S_IRUGO); 228 MODULE_PARM_DESC(ql2xmdcapmask, 229 "Set the Minidump driver capture mask level. " 230 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 231 232 int ql2xmdenable = 1; 233 module_param(ql2xmdenable, int, S_IRUGO); 234 MODULE_PARM_DESC(ql2xmdenable, 235 "Enable/disable MiniDump. " 236 "0 - MiniDump disabled. " 237 "1 (Default) - MiniDump enabled."); 238 239 int ql2xexlogins; 240 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 241 MODULE_PARM_DESC(ql2xexlogins, 242 "Number of extended Logins. " 243 "0 (Default)- Disabled."); 244 245 int ql2xexchoffld = 1024; 246 module_param(ql2xexchoffld, uint, 0644); 247 MODULE_PARM_DESC(ql2xexchoffld, 248 "Number of target exchanges."); 249 250 int ql2xiniexchg = 1024; 251 module_param(ql2xiniexchg, uint, 0644); 252 MODULE_PARM_DESC(ql2xiniexchg, 253 "Number of initiator exchanges."); 254 255 int ql2xfwholdabts; 256 module_param(ql2xfwholdabts, int, S_IRUGO); 257 MODULE_PARM_DESC(ql2xfwholdabts, 258 "Allow FW to hold status IOCB until ABTS rsp received. " 259 "0 (Default) Do not set fw option. " 260 "1 - Set fw option to hold ABTS."); 261 262 int ql2xmvasynctoatio = 1; 263 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 264 MODULE_PARM_DESC(ql2xmvasynctoatio, 265 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 266 "0 (Default). Do not move IOCBs" 267 "1 - Move IOCBs."); 268 269 int ql2xautodetectsfp = 1; 270 module_param(ql2xautodetectsfp, int, 0444); 271 MODULE_PARM_DESC(ql2xautodetectsfp, 272 "Detect SFP range and set appropriate distance.\n" 273 "1 (Default): Enable\n"); 274 275 int ql2xenablemsix = 1; 276 module_param(ql2xenablemsix, int, 0444); 277 MODULE_PARM_DESC(ql2xenablemsix, 278 "Set to enable MSI or MSI-X interrupt mechanism.\n" 279 " Default is 1, enable MSI-X interrupt mechanism.\n" 280 " 0 -- enable traditional pin-based mechanism.\n" 281 " 1 -- enable MSI-X interrupt mechanism.\n" 282 " 2 -- enable MSI interrupt mechanism.\n"); 283 284 int qla2xuseresexchforels; 285 module_param(qla2xuseresexchforels, int, 0444); 286 MODULE_PARM_DESC(qla2xuseresexchforels, 287 "Reserve 1/2 of emergency exchanges for ELS.\n" 288 " 0 (default): disabled"); 289 290 static int ql2xprotmask; 291 module_param(ql2xprotmask, int, 0644); 292 MODULE_PARM_DESC(ql2xprotmask, 293 "Override DIF/DIX protection capabilities mask\n" 294 "Default is 0 which sets protection mask based on " 295 "capabilities reported by HBA firmware.\n"); 296 297 static int ql2xprotguard; 298 module_param(ql2xprotguard, int, 0644); 299 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 300 " 0 -- Let HBA firmware decide\n" 301 " 1 -- Force T10 CRC\n" 302 " 2 -- Force IP checksum\n"); 303 304 int ql2xdifbundlinginternalbuffers; 305 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 306 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 307 "Force using internal buffers for DIF information\n" 308 "0 (Default). Based on check.\n" 309 "1 Force using internal buffers\n"); 310 311 int ql2xsmartsan; 312 module_param(ql2xsmartsan, int, 0444); 313 module_param_named(smartsan, ql2xsmartsan, int, 0444); 314 MODULE_PARM_DESC(ql2xsmartsan, 315 "Send SmartSAN Management Attributes for FDMI Registration." 316 " Default is 0 - No SmartSAN registration," 317 " 1 - Register SmartSAN Management Attributes."); 318 319 int ql2xrdpenable; 320 module_param(ql2xrdpenable, int, 0444); 321 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 322 MODULE_PARM_DESC(ql2xrdpenable, 323 "Enables RDP responses. " 324 "0 - no RDP responses (default). " 325 "1 - provide RDP responses."); 326 327 static void qla2x00_clear_drv_active(struct qla_hw_data *); 328 static void qla2x00_free_device(scsi_qla_host_t *); 329 static int qla2xxx_map_queues(struct Scsi_Host *shost); 330 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 331 332 333 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 334 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 335 336 /* TODO Convert to inlines 337 * 338 * Timer routines 339 */ 340 341 __inline__ void 342 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 343 { 344 timer_setup(&vha->timer, qla2x00_timer, 0); 345 vha->timer.expires = jiffies + interval * HZ; 346 add_timer(&vha->timer); 347 vha->timer_active = 1; 348 } 349 350 static inline void 351 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 352 { 353 /* Currently used for 82XX only. */ 354 if (vha->device_flags & DFLG_DEV_FAILED) { 355 ql_dbg(ql_dbg_timer, vha, 0x600d, 356 "Device in a failed state, returning.\n"); 357 return; 358 } 359 360 mod_timer(&vha->timer, jiffies + interval * HZ); 361 } 362 363 static __inline__ void 364 qla2x00_stop_timer(scsi_qla_host_t *vha) 365 { 366 del_timer_sync(&vha->timer); 367 vha->timer_active = 0; 368 } 369 370 static int qla2x00_do_dpc(void *data); 371 372 static void qla2x00_rst_aen(scsi_qla_host_t *); 373 374 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 375 struct req_que **, struct rsp_que **); 376 static void qla2x00_free_fw_dump(struct qla_hw_data *); 377 static void qla2x00_mem_free(struct qla_hw_data *); 378 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 379 struct qla_qpair *qpair); 380 381 /* -------------------------------------------------------------------------- */ 382 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 383 struct rsp_que *rsp) 384 { 385 struct qla_hw_data *ha = vha->hw; 386 387 rsp->qpair = ha->base_qpair; 388 rsp->req = req; 389 ha->base_qpair->hw = ha; 390 ha->base_qpair->req = req; 391 ha->base_qpair->rsp = rsp; 392 ha->base_qpair->vha = vha; 393 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 394 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 395 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 396 ha->base_qpair->srb_mempool = ha->srb_mempool; 397 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 398 ha->base_qpair->enable_class_2 = ql2xenableclass2; 399 /* init qpair to this cpu. Will adjust at run time. */ 400 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 401 ha->base_qpair->pdev = ha->pdev; 402 403 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 404 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 405 } 406 407 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 408 struct rsp_que *rsp) 409 { 410 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 411 412 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 413 GFP_KERNEL); 414 if (!ha->req_q_map) { 415 ql_log(ql_log_fatal, vha, 0x003b, 416 "Unable to allocate memory for request queue ptrs.\n"); 417 goto fail_req_map; 418 } 419 420 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 421 GFP_KERNEL); 422 if (!ha->rsp_q_map) { 423 ql_log(ql_log_fatal, vha, 0x003c, 424 "Unable to allocate memory for response queue ptrs.\n"); 425 goto fail_rsp_map; 426 } 427 428 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 429 if (ha->base_qpair == NULL) { 430 ql_log(ql_log_warn, vha, 0x00e0, 431 "Failed to allocate base queue pair memory.\n"); 432 goto fail_base_qpair; 433 } 434 435 qla_init_base_qpair(vha, req, rsp); 436 437 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 438 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 439 GFP_KERNEL); 440 if (!ha->queue_pair_map) { 441 ql_log(ql_log_fatal, vha, 0x0180, 442 "Unable to allocate memory for queue pair ptrs.\n"); 443 goto fail_qpair_map; 444 } 445 } 446 447 /* 448 * Make sure we record at least the request and response queue zero in 449 * case we need to free them if part of the probe fails. 450 */ 451 ha->rsp_q_map[0] = rsp; 452 ha->req_q_map[0] = req; 453 set_bit(0, ha->rsp_qid_map); 454 set_bit(0, ha->req_qid_map); 455 return 0; 456 457 fail_qpair_map: 458 kfree(ha->base_qpair); 459 ha->base_qpair = NULL; 460 fail_base_qpair: 461 kfree(ha->rsp_q_map); 462 ha->rsp_q_map = NULL; 463 fail_rsp_map: 464 kfree(ha->req_q_map); 465 ha->req_q_map = NULL; 466 fail_req_map: 467 return -ENOMEM; 468 } 469 470 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 471 { 472 if (IS_QLAFX00(ha)) { 473 if (req && req->ring_fx00) 474 dma_free_coherent(&ha->pdev->dev, 475 (req->length_fx00 + 1) * sizeof(request_t), 476 req->ring_fx00, req->dma_fx00); 477 } else if (req && req->ring) 478 dma_free_coherent(&ha->pdev->dev, 479 (req->length + 1) * sizeof(request_t), 480 req->ring, req->dma); 481 482 if (req) 483 kfree(req->outstanding_cmds); 484 485 kfree(req); 486 } 487 488 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 489 { 490 if (IS_QLAFX00(ha)) { 491 if (rsp && rsp->ring_fx00) 492 dma_free_coherent(&ha->pdev->dev, 493 (rsp->length_fx00 + 1) * sizeof(request_t), 494 rsp->ring_fx00, rsp->dma_fx00); 495 } else if (rsp && rsp->ring) { 496 dma_free_coherent(&ha->pdev->dev, 497 (rsp->length + 1) * sizeof(response_t), 498 rsp->ring, rsp->dma); 499 } 500 kfree(rsp); 501 } 502 503 static void qla2x00_free_queues(struct qla_hw_data *ha) 504 { 505 struct req_que *req; 506 struct rsp_que *rsp; 507 int cnt; 508 unsigned long flags; 509 510 if (ha->queue_pair_map) { 511 kfree(ha->queue_pair_map); 512 ha->queue_pair_map = NULL; 513 } 514 if (ha->base_qpair) { 515 kfree(ha->base_qpair); 516 ha->base_qpair = NULL; 517 } 518 519 spin_lock_irqsave(&ha->hardware_lock, flags); 520 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 521 if (!test_bit(cnt, ha->req_qid_map)) 522 continue; 523 524 req = ha->req_q_map[cnt]; 525 clear_bit(cnt, ha->req_qid_map); 526 ha->req_q_map[cnt] = NULL; 527 528 spin_unlock_irqrestore(&ha->hardware_lock, flags); 529 qla2x00_free_req_que(ha, req); 530 spin_lock_irqsave(&ha->hardware_lock, flags); 531 } 532 spin_unlock_irqrestore(&ha->hardware_lock, flags); 533 534 kfree(ha->req_q_map); 535 ha->req_q_map = NULL; 536 537 538 spin_lock_irqsave(&ha->hardware_lock, flags); 539 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 540 if (!test_bit(cnt, ha->rsp_qid_map)) 541 continue; 542 543 rsp = ha->rsp_q_map[cnt]; 544 clear_bit(cnt, ha->rsp_qid_map); 545 ha->rsp_q_map[cnt] = NULL; 546 spin_unlock_irqrestore(&ha->hardware_lock, flags); 547 qla2x00_free_rsp_que(ha, rsp); 548 spin_lock_irqsave(&ha->hardware_lock, flags); 549 } 550 spin_unlock_irqrestore(&ha->hardware_lock, flags); 551 552 kfree(ha->rsp_q_map); 553 ha->rsp_q_map = NULL; 554 } 555 556 static char * 557 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 558 { 559 struct qla_hw_data *ha = vha->hw; 560 static const char *const pci_bus_modes[] = { 561 "33", "66", "100", "133", 562 }; 563 uint16_t pci_bus; 564 565 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 566 if (pci_bus) { 567 snprintf(str, str_len, "PCI-X (%s MHz)", 568 pci_bus_modes[pci_bus]); 569 } else { 570 pci_bus = (ha->pci_attr & BIT_8) >> 8; 571 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 572 } 573 574 return str; 575 } 576 577 static char * 578 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 579 { 580 static const char *const pci_bus_modes[] = { 581 "33", "66", "100", "133", 582 }; 583 struct qla_hw_data *ha = vha->hw; 584 uint32_t pci_bus; 585 586 if (pci_is_pcie(ha->pdev)) { 587 uint32_t lstat, lspeed, lwidth; 588 const char *speed_str; 589 590 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 591 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 592 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 593 594 switch (lspeed) { 595 case 1: 596 speed_str = "2.5GT/s"; 597 break; 598 case 2: 599 speed_str = "5.0GT/s"; 600 break; 601 case 3: 602 speed_str = "8.0GT/s"; 603 break; 604 case 4: 605 speed_str = "16.0GT/s"; 606 break; 607 default: 608 speed_str = "<unknown>"; 609 break; 610 } 611 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 612 613 return str; 614 } 615 616 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 617 if (pci_bus == 0 || pci_bus == 8) 618 snprintf(str, str_len, "PCI (%s MHz)", 619 pci_bus_modes[pci_bus >> 3]); 620 else 621 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 622 pci_bus & 4 ? 2 : 1, 623 pci_bus_modes[pci_bus & 3]); 624 625 return str; 626 } 627 628 static char * 629 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 630 { 631 char un_str[10]; 632 struct qla_hw_data *ha = vha->hw; 633 634 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 635 ha->fw_minor_version, ha->fw_subminor_version); 636 637 if (ha->fw_attributes & BIT_9) { 638 strcat(str, "FLX"); 639 return (str); 640 } 641 642 switch (ha->fw_attributes & 0xFF) { 643 case 0x7: 644 strcat(str, "EF"); 645 break; 646 case 0x17: 647 strcat(str, "TP"); 648 break; 649 case 0x37: 650 strcat(str, "IP"); 651 break; 652 case 0x77: 653 strcat(str, "VI"); 654 break; 655 default: 656 sprintf(un_str, "(%x)", ha->fw_attributes); 657 strcat(str, un_str); 658 break; 659 } 660 if (ha->fw_attributes & 0x100) 661 strcat(str, "X"); 662 663 return (str); 664 } 665 666 static char * 667 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 668 { 669 struct qla_hw_data *ha = vha->hw; 670 671 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 672 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 673 return str; 674 } 675 676 void qla2x00_sp_free_dma(srb_t *sp) 677 { 678 struct qla_hw_data *ha = sp->vha->hw; 679 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 680 681 if (sp->flags & SRB_DMA_VALID) { 682 scsi_dma_unmap(cmd); 683 sp->flags &= ~SRB_DMA_VALID; 684 } 685 686 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 687 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 688 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 689 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 690 } 691 692 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 693 /* List assured to be having elements */ 694 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 695 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 696 } 697 698 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 699 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 700 701 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 702 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 703 } 704 705 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 706 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 707 708 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 709 ctx1->fcp_cmnd_dma); 710 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 711 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 712 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 713 mempool_free(ctx1, ha->ctx_mempool); 714 } 715 } 716 717 void qla2x00_sp_compl(srb_t *sp, int res) 718 { 719 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 720 struct completion *comp = sp->comp; 721 722 sp->free(sp); 723 cmd->result = res; 724 CMD_SP(cmd) = NULL; 725 cmd->scsi_done(cmd); 726 if (comp) 727 complete(comp); 728 } 729 730 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 731 { 732 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 733 struct qla_hw_data *ha = sp->fcport->vha->hw; 734 735 if (sp->flags & SRB_DMA_VALID) { 736 scsi_dma_unmap(cmd); 737 sp->flags &= ~SRB_DMA_VALID; 738 } 739 740 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 741 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 742 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 743 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 744 } 745 746 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 747 /* List assured to be having elements */ 748 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 749 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 750 } 751 752 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 753 struct crc_context *difctx = sp->u.scmd.crc_ctx; 754 struct dsd_dma *dif_dsd, *nxt_dsd; 755 756 list_for_each_entry_safe(dif_dsd, nxt_dsd, 757 &difctx->ldif_dma_hndl_list, list) { 758 list_del(&dif_dsd->list); 759 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 760 dif_dsd->dsd_list_dma); 761 kfree(dif_dsd); 762 difctx->no_dif_bundl--; 763 } 764 765 list_for_each_entry_safe(dif_dsd, nxt_dsd, 766 &difctx->ldif_dsd_list, list) { 767 list_del(&dif_dsd->list); 768 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 769 dif_dsd->dsd_list_dma); 770 kfree(dif_dsd); 771 difctx->no_ldif_dsd--; 772 } 773 774 if (difctx->no_ldif_dsd) { 775 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 776 "%s: difctx->no_ldif_dsd=%x\n", 777 __func__, difctx->no_ldif_dsd); 778 } 779 780 if (difctx->no_dif_bundl) { 781 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 782 "%s: difctx->no_dif_bundl=%x\n", 783 __func__, difctx->no_dif_bundl); 784 } 785 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 786 } 787 788 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 789 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 790 791 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 792 ctx1->fcp_cmnd_dma); 793 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 794 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 795 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 796 mempool_free(ctx1, ha->ctx_mempool); 797 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 798 } 799 800 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 801 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 802 803 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 804 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 805 } 806 } 807 808 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 809 { 810 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 811 struct completion *comp = sp->comp; 812 813 sp->free(sp); 814 cmd->result = res; 815 CMD_SP(cmd) = NULL; 816 cmd->scsi_done(cmd); 817 if (comp) 818 complete(comp); 819 } 820 821 static int 822 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 823 { 824 scsi_qla_host_t *vha = shost_priv(host); 825 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 826 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 827 struct qla_hw_data *ha = vha->hw; 828 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 829 srb_t *sp; 830 int rval; 831 832 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 833 WARN_ON_ONCE(!rport)) { 834 cmd->result = DID_NO_CONNECT << 16; 835 goto qc24_fail_command; 836 } 837 838 if (ha->mqenable) { 839 uint32_t tag; 840 uint16_t hwq; 841 struct qla_qpair *qpair = NULL; 842 843 tag = blk_mq_unique_tag(cmd->request); 844 hwq = blk_mq_unique_tag_to_hwq(tag); 845 qpair = ha->queue_pair_map[hwq]; 846 847 if (qpair) 848 return qla2xxx_mqueuecommand(host, cmd, qpair); 849 } 850 851 if (ha->flags.eeh_busy) { 852 if (ha->flags.pci_channel_io_perm_failure) { 853 ql_dbg(ql_dbg_aer, vha, 0x9010, 854 "PCI Channel IO permanent failure, exiting " 855 "cmd=%p.\n", cmd); 856 cmd->result = DID_NO_CONNECT << 16; 857 } else { 858 ql_dbg(ql_dbg_aer, vha, 0x9011, 859 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 860 cmd->result = DID_REQUEUE << 16; 861 } 862 goto qc24_fail_command; 863 } 864 865 rval = fc_remote_port_chkready(rport); 866 if (rval) { 867 cmd->result = rval; 868 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 869 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 870 cmd, rval); 871 goto qc24_fail_command; 872 } 873 874 if (!vha->flags.difdix_supported && 875 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 876 ql_dbg(ql_dbg_io, vha, 0x3004, 877 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 878 cmd); 879 cmd->result = DID_NO_CONNECT << 16; 880 goto qc24_fail_command; 881 } 882 883 if (!fcport) { 884 cmd->result = DID_NO_CONNECT << 16; 885 goto qc24_fail_command; 886 } 887 888 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 889 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 890 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 891 ql_dbg(ql_dbg_io, vha, 0x3005, 892 "Returning DNC, fcport_state=%d loop_state=%d.\n", 893 atomic_read(&fcport->state), 894 atomic_read(&base_vha->loop_state)); 895 cmd->result = DID_NO_CONNECT << 16; 896 goto qc24_fail_command; 897 } 898 goto qc24_target_busy; 899 } 900 901 /* 902 * Return target busy if we've received a non-zero retry_delay_timer 903 * in a FCP_RSP. 904 */ 905 if (fcport->retry_delay_timestamp == 0) { 906 /* retry delay not set */ 907 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 908 fcport->retry_delay_timestamp = 0; 909 else 910 goto qc24_target_busy; 911 912 sp = scsi_cmd_priv(cmd); 913 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 914 915 sp->u.scmd.cmd = cmd; 916 sp->type = SRB_SCSI_CMD; 917 918 CMD_SP(cmd) = (void *)sp; 919 sp->free = qla2x00_sp_free_dma; 920 sp->done = qla2x00_sp_compl; 921 922 rval = ha->isp_ops->start_scsi(sp); 923 if (rval != QLA_SUCCESS) { 924 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 925 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 926 goto qc24_host_busy_free_sp; 927 } 928 929 return 0; 930 931 qc24_host_busy_free_sp: 932 sp->free(sp); 933 934 qc24_target_busy: 935 return SCSI_MLQUEUE_TARGET_BUSY; 936 937 qc24_fail_command: 938 cmd->scsi_done(cmd); 939 940 return 0; 941 } 942 943 /* For MQ supported I/O */ 944 int 945 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 946 struct qla_qpair *qpair) 947 { 948 scsi_qla_host_t *vha = shost_priv(host); 949 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 950 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 951 struct qla_hw_data *ha = vha->hw; 952 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 953 srb_t *sp; 954 int rval; 955 956 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 957 if (rval) { 958 cmd->result = rval; 959 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 960 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 961 cmd, rval); 962 goto qc24_fail_command; 963 } 964 965 if (!fcport) { 966 cmd->result = DID_NO_CONNECT << 16; 967 goto qc24_fail_command; 968 } 969 970 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 971 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 972 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 973 ql_dbg(ql_dbg_io, vha, 0x3077, 974 "Returning DNC, fcport_state=%d loop_state=%d.\n", 975 atomic_read(&fcport->state), 976 atomic_read(&base_vha->loop_state)); 977 cmd->result = DID_NO_CONNECT << 16; 978 goto qc24_fail_command; 979 } 980 goto qc24_target_busy; 981 } 982 983 /* 984 * Return target busy if we've received a non-zero retry_delay_timer 985 * in a FCP_RSP. 986 */ 987 if (fcport->retry_delay_timestamp == 0) { 988 /* retry delay not set */ 989 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 990 fcport->retry_delay_timestamp = 0; 991 else 992 goto qc24_target_busy; 993 994 sp = scsi_cmd_priv(cmd); 995 qla2xxx_init_sp(sp, vha, qpair, fcport); 996 997 sp->u.scmd.cmd = cmd; 998 sp->type = SRB_SCSI_CMD; 999 CMD_SP(cmd) = (void *)sp; 1000 sp->free = qla2xxx_qpair_sp_free_dma; 1001 sp->done = qla2xxx_qpair_sp_compl; 1002 1003 rval = ha->isp_ops->start_scsi_mq(sp); 1004 if (rval != QLA_SUCCESS) { 1005 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1006 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1007 if (rval == QLA_INTERFACE_ERROR) 1008 goto qc24_free_sp_fail_command; 1009 goto qc24_host_busy_free_sp; 1010 } 1011 1012 return 0; 1013 1014 qc24_host_busy_free_sp: 1015 sp->free(sp); 1016 1017 qc24_target_busy: 1018 return SCSI_MLQUEUE_TARGET_BUSY; 1019 1020 qc24_free_sp_fail_command: 1021 sp->free(sp); 1022 CMD_SP(cmd) = NULL; 1023 qla2xxx_rel_qpair_sp(sp->qpair, sp); 1024 1025 qc24_fail_command: 1026 cmd->scsi_done(cmd); 1027 1028 return 0; 1029 } 1030 1031 /* 1032 * qla2x00_eh_wait_on_command 1033 * Waits for the command to be returned by the Firmware for some 1034 * max time. 1035 * 1036 * Input: 1037 * cmd = Scsi Command to wait on. 1038 * 1039 * Return: 1040 * Completed in time : QLA_SUCCESS 1041 * Did not complete in time : QLA_FUNCTION_FAILED 1042 */ 1043 static int 1044 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1045 { 1046 #define ABORT_POLLING_PERIOD 1000 1047 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1048 unsigned long wait_iter = ABORT_WAIT_ITER; 1049 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1050 struct qla_hw_data *ha = vha->hw; 1051 int ret = QLA_SUCCESS; 1052 1053 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1054 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1055 "Return:eh_wait.\n"); 1056 return ret; 1057 } 1058 1059 while (CMD_SP(cmd) && wait_iter--) { 1060 msleep(ABORT_POLLING_PERIOD); 1061 } 1062 if (CMD_SP(cmd)) 1063 ret = QLA_FUNCTION_FAILED; 1064 1065 return ret; 1066 } 1067 1068 /* 1069 * qla2x00_wait_for_hba_online 1070 * Wait till the HBA is online after going through 1071 * <= MAX_RETRIES_OF_ISP_ABORT or 1072 * finally HBA is disabled ie marked offline 1073 * 1074 * Input: 1075 * ha - pointer to host adapter structure 1076 * 1077 * Note: 1078 * Does context switching-Release SPIN_LOCK 1079 * (if any) before calling this routine. 1080 * 1081 * Return: 1082 * Success (Adapter is online) : 0 1083 * Failed (Adapter is offline/disabled) : 1 1084 */ 1085 int 1086 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1087 { 1088 int return_status; 1089 unsigned long wait_online; 1090 struct qla_hw_data *ha = vha->hw; 1091 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1092 1093 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1094 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1095 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1096 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1097 ha->dpc_active) && time_before(jiffies, wait_online)) { 1098 1099 msleep(1000); 1100 } 1101 if (base_vha->flags.online) 1102 return_status = QLA_SUCCESS; 1103 else 1104 return_status = QLA_FUNCTION_FAILED; 1105 1106 return (return_status); 1107 } 1108 1109 static inline int test_fcport_count(scsi_qla_host_t *vha) 1110 { 1111 struct qla_hw_data *ha = vha->hw; 1112 unsigned long flags; 1113 int res; 1114 1115 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1116 ql_dbg(ql_dbg_init, vha, 0x00ec, 1117 "tgt %p, fcport_count=%d\n", 1118 vha, vha->fcport_count); 1119 res = (vha->fcport_count == 0); 1120 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1121 1122 return res; 1123 } 1124 1125 /* 1126 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1127 * it has dependency on UNLOADING flag to stop device discovery 1128 */ 1129 void 1130 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1131 { 1132 u8 i; 1133 1134 qla2x00_mark_all_devices_lost(vha); 1135 1136 for (i = 0; i < 10; i++) { 1137 if (wait_event_timeout(vha->fcport_waitQ, 1138 test_fcport_count(vha), HZ) > 0) 1139 break; 1140 } 1141 1142 flush_workqueue(vha->hw->wq); 1143 } 1144 1145 /* 1146 * qla2x00_wait_for_hba_ready 1147 * Wait till the HBA is ready before doing driver unload 1148 * 1149 * Input: 1150 * ha - pointer to host adapter structure 1151 * 1152 * Note: 1153 * Does context switching-Release SPIN_LOCK 1154 * (if any) before calling this routine. 1155 * 1156 */ 1157 static void 1158 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1159 { 1160 struct qla_hw_data *ha = vha->hw; 1161 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1162 1163 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1164 ha->flags.mbox_busy) || 1165 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1166 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1167 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1168 break; 1169 msleep(1000); 1170 } 1171 } 1172 1173 int 1174 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1175 { 1176 int return_status; 1177 unsigned long wait_reset; 1178 struct qla_hw_data *ha = vha->hw; 1179 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1180 1181 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1182 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1183 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1184 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1185 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1186 1187 msleep(1000); 1188 1189 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1190 ha->flags.chip_reset_done) 1191 break; 1192 } 1193 if (ha->flags.chip_reset_done) 1194 return_status = QLA_SUCCESS; 1195 else 1196 return_status = QLA_FUNCTION_FAILED; 1197 1198 return return_status; 1199 } 1200 1201 #define ISP_REG_DISCONNECT 0xffffffffU 1202 /************************************************************************** 1203 * qla2x00_isp_reg_stat 1204 * 1205 * Description: 1206 * Read the host status register of ISP before aborting the command. 1207 * 1208 * Input: 1209 * ha = pointer to host adapter structure. 1210 * 1211 * 1212 * Returns: 1213 * Either true or false. 1214 * 1215 * Note: Return true if there is register disconnect. 1216 **************************************************************************/ 1217 static inline 1218 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1219 { 1220 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1221 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1222 1223 if (IS_P3P_TYPE(ha)) 1224 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT); 1225 else 1226 return ((rd_reg_dword(®->host_status)) == 1227 ISP_REG_DISCONNECT); 1228 } 1229 1230 /************************************************************************** 1231 * qla2xxx_eh_abort 1232 * 1233 * Description: 1234 * The abort function will abort the specified command. 1235 * 1236 * Input: 1237 * cmd = Linux SCSI command packet to be aborted. 1238 * 1239 * Returns: 1240 * Either SUCCESS or FAILED. 1241 * 1242 * Note: 1243 * Only return FAILED if command not returned by firmware. 1244 **************************************************************************/ 1245 static int 1246 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1247 { 1248 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1249 DECLARE_COMPLETION_ONSTACK(comp); 1250 srb_t *sp; 1251 int ret; 1252 unsigned int id; 1253 uint64_t lun; 1254 int rval; 1255 struct qla_hw_data *ha = vha->hw; 1256 uint32_t ratov_j; 1257 struct qla_qpair *qpair; 1258 unsigned long flags; 1259 1260 if (qla2x00_isp_reg_stat(ha)) { 1261 ql_log(ql_log_info, vha, 0x8042, 1262 "PCI/Register disconnect, exiting.\n"); 1263 return FAILED; 1264 } 1265 1266 ret = fc_block_scsi_eh(cmd); 1267 if (ret != 0) 1268 return ret; 1269 1270 sp = scsi_cmd_priv(cmd); 1271 qpair = sp->qpair; 1272 1273 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1274 return SUCCESS; 1275 1276 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1277 sp->comp = ∁ 1278 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1279 1280 1281 id = cmd->device->id; 1282 lun = cmd->device->lun; 1283 1284 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1285 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1286 vha->host_no, id, lun, sp, cmd, sp->handle); 1287 1288 /* 1289 * Abort will release the original Command/sp from FW. Let the 1290 * original command call scsi_done. In return, he will wakeup 1291 * this sleeping thread. 1292 */ 1293 rval = ha->isp_ops->abort_command(sp); 1294 1295 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1296 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1297 1298 /* Wait for the command completion. */ 1299 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1300 ratov_j = msecs_to_jiffies(ratov_j); 1301 switch (rval) { 1302 case QLA_SUCCESS: 1303 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1304 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1305 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1306 __func__, ha->r_a_tov/10); 1307 ret = FAILED; 1308 } else { 1309 ret = SUCCESS; 1310 } 1311 break; 1312 default: 1313 ret = FAILED; 1314 break; 1315 } 1316 1317 sp->comp = NULL; 1318 1319 ql_log(ql_log_info, vha, 0x801c, 1320 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1321 vha->host_no, id, lun, ret); 1322 1323 return ret; 1324 } 1325 1326 /* 1327 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1328 */ 1329 int 1330 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1331 uint64_t l, enum nexus_wait_type type) 1332 { 1333 int cnt, match, status; 1334 unsigned long flags; 1335 struct qla_hw_data *ha = vha->hw; 1336 struct req_que *req; 1337 srb_t *sp; 1338 struct scsi_cmnd *cmd; 1339 1340 status = QLA_SUCCESS; 1341 1342 spin_lock_irqsave(&ha->hardware_lock, flags); 1343 req = vha->req; 1344 for (cnt = 1; status == QLA_SUCCESS && 1345 cnt < req->num_outstanding_cmds; cnt++) { 1346 sp = req->outstanding_cmds[cnt]; 1347 if (!sp) 1348 continue; 1349 if (sp->type != SRB_SCSI_CMD) 1350 continue; 1351 if (vha->vp_idx != sp->vha->vp_idx) 1352 continue; 1353 match = 0; 1354 cmd = GET_CMD_SP(sp); 1355 switch (type) { 1356 case WAIT_HOST: 1357 match = 1; 1358 break; 1359 case WAIT_TARGET: 1360 match = cmd->device->id == t; 1361 break; 1362 case WAIT_LUN: 1363 match = (cmd->device->id == t && 1364 cmd->device->lun == l); 1365 break; 1366 } 1367 if (!match) 1368 continue; 1369 1370 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1371 status = qla2x00_eh_wait_on_command(cmd); 1372 spin_lock_irqsave(&ha->hardware_lock, flags); 1373 } 1374 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1375 1376 return status; 1377 } 1378 1379 static char *reset_errors[] = { 1380 "HBA not online", 1381 "HBA not ready", 1382 "Task management failed", 1383 "Waiting for command completions", 1384 }; 1385 1386 static int 1387 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1388 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1389 { 1390 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1391 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1392 int err; 1393 1394 if (!fcport) { 1395 return FAILED; 1396 } 1397 1398 err = fc_block_scsi_eh(cmd); 1399 if (err != 0) 1400 return err; 1401 1402 if (fcport->deleted) 1403 return SUCCESS; 1404 1405 ql_log(ql_log_info, vha, 0x8009, 1406 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1407 cmd->device->id, cmd->device->lun, cmd); 1408 1409 err = 0; 1410 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1411 ql_log(ql_log_warn, vha, 0x800a, 1412 "Wait for hba online failed for cmd=%p.\n", cmd); 1413 goto eh_reset_failed; 1414 } 1415 err = 2; 1416 if (do_reset(fcport, cmd->device->lun, 1) 1417 != QLA_SUCCESS) { 1418 ql_log(ql_log_warn, vha, 0x800c, 1419 "do_reset failed for cmd=%p.\n", cmd); 1420 goto eh_reset_failed; 1421 } 1422 err = 3; 1423 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1424 cmd->device->lun, type) != QLA_SUCCESS) { 1425 ql_log(ql_log_warn, vha, 0x800d, 1426 "wait for pending cmds failed for cmd=%p.\n", cmd); 1427 goto eh_reset_failed; 1428 } 1429 1430 ql_log(ql_log_info, vha, 0x800e, 1431 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1432 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1433 1434 return SUCCESS; 1435 1436 eh_reset_failed: 1437 ql_log(ql_log_info, vha, 0x800f, 1438 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1439 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1440 cmd); 1441 return FAILED; 1442 } 1443 1444 static int 1445 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1446 { 1447 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1448 struct qla_hw_data *ha = vha->hw; 1449 1450 if (qla2x00_isp_reg_stat(ha)) { 1451 ql_log(ql_log_info, vha, 0x803e, 1452 "PCI/Register disconnect, exiting.\n"); 1453 return FAILED; 1454 } 1455 1456 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1457 ha->isp_ops->lun_reset); 1458 } 1459 1460 static int 1461 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1462 { 1463 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1464 struct qla_hw_data *ha = vha->hw; 1465 1466 if (qla2x00_isp_reg_stat(ha)) { 1467 ql_log(ql_log_info, vha, 0x803f, 1468 "PCI/Register disconnect, exiting.\n"); 1469 return FAILED; 1470 } 1471 1472 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1473 ha->isp_ops->target_reset); 1474 } 1475 1476 /************************************************************************** 1477 * qla2xxx_eh_bus_reset 1478 * 1479 * Description: 1480 * The bus reset function will reset the bus and abort any executing 1481 * commands. 1482 * 1483 * Input: 1484 * cmd = Linux SCSI command packet of the command that cause the 1485 * bus reset. 1486 * 1487 * Returns: 1488 * SUCCESS/FAILURE (defined as macro in scsi.h). 1489 * 1490 **************************************************************************/ 1491 static int 1492 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1493 { 1494 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1495 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1496 int ret = FAILED; 1497 unsigned int id; 1498 uint64_t lun; 1499 struct qla_hw_data *ha = vha->hw; 1500 1501 if (qla2x00_isp_reg_stat(ha)) { 1502 ql_log(ql_log_info, vha, 0x8040, 1503 "PCI/Register disconnect, exiting.\n"); 1504 return FAILED; 1505 } 1506 1507 id = cmd->device->id; 1508 lun = cmd->device->lun; 1509 1510 if (!fcport) { 1511 return ret; 1512 } 1513 1514 ret = fc_block_scsi_eh(cmd); 1515 if (ret != 0) 1516 return ret; 1517 ret = FAILED; 1518 1519 if (qla2x00_chip_is_down(vha)) 1520 return ret; 1521 1522 ql_log(ql_log_info, vha, 0x8012, 1523 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1524 1525 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1526 ql_log(ql_log_fatal, vha, 0x8013, 1527 "Wait for hba online failed board disabled.\n"); 1528 goto eh_bus_reset_done; 1529 } 1530 1531 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1532 ret = SUCCESS; 1533 1534 if (ret == FAILED) 1535 goto eh_bus_reset_done; 1536 1537 /* Flush outstanding commands. */ 1538 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1539 QLA_SUCCESS) { 1540 ql_log(ql_log_warn, vha, 0x8014, 1541 "Wait for pending commands failed.\n"); 1542 ret = FAILED; 1543 } 1544 1545 eh_bus_reset_done: 1546 ql_log(ql_log_warn, vha, 0x802b, 1547 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1548 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1549 1550 return ret; 1551 } 1552 1553 /************************************************************************** 1554 * qla2xxx_eh_host_reset 1555 * 1556 * Description: 1557 * The reset function will reset the Adapter. 1558 * 1559 * Input: 1560 * cmd = Linux SCSI command packet of the command that cause the 1561 * adapter reset. 1562 * 1563 * Returns: 1564 * Either SUCCESS or FAILED. 1565 * 1566 * Note: 1567 **************************************************************************/ 1568 static int 1569 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1570 { 1571 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1572 struct qla_hw_data *ha = vha->hw; 1573 int ret = FAILED; 1574 unsigned int id; 1575 uint64_t lun; 1576 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1577 1578 if (qla2x00_isp_reg_stat(ha)) { 1579 ql_log(ql_log_info, vha, 0x8041, 1580 "PCI/Register disconnect, exiting.\n"); 1581 schedule_work(&ha->board_disable); 1582 return SUCCESS; 1583 } 1584 1585 id = cmd->device->id; 1586 lun = cmd->device->lun; 1587 1588 ql_log(ql_log_info, vha, 0x8018, 1589 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1590 1591 /* 1592 * No point in issuing another reset if one is active. Also do not 1593 * attempt a reset if we are updating flash. 1594 */ 1595 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1596 goto eh_host_reset_lock; 1597 1598 if (vha != base_vha) { 1599 if (qla2x00_vp_abort_isp(vha)) 1600 goto eh_host_reset_lock; 1601 } else { 1602 if (IS_P3P_TYPE(vha->hw)) { 1603 if (!qla82xx_fcoe_ctx_reset(vha)) { 1604 /* Ctx reset success */ 1605 ret = SUCCESS; 1606 goto eh_host_reset_lock; 1607 } 1608 /* fall thru if ctx reset failed */ 1609 } 1610 if (ha->wq) 1611 flush_workqueue(ha->wq); 1612 1613 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1614 if (ha->isp_ops->abort_isp(base_vha)) { 1615 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1616 /* failed. schedule dpc to try */ 1617 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1618 1619 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1620 ql_log(ql_log_warn, vha, 0x802a, 1621 "wait for hba online failed.\n"); 1622 goto eh_host_reset_lock; 1623 } 1624 } 1625 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 } 1627 1628 /* Waiting for command to be returned to OS.*/ 1629 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1630 QLA_SUCCESS) 1631 ret = SUCCESS; 1632 1633 eh_host_reset_lock: 1634 ql_log(ql_log_info, vha, 0x8017, 1635 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1636 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1637 1638 return ret; 1639 } 1640 1641 /* 1642 * qla2x00_loop_reset 1643 * Issue loop reset. 1644 * 1645 * Input: 1646 * ha = adapter block pointer. 1647 * 1648 * Returns: 1649 * 0 = success 1650 */ 1651 int 1652 qla2x00_loop_reset(scsi_qla_host_t *vha) 1653 { 1654 int ret; 1655 struct fc_port *fcport; 1656 struct qla_hw_data *ha = vha->hw; 1657 1658 if (IS_QLAFX00(ha)) { 1659 return qlafx00_loop_reset(vha); 1660 } 1661 1662 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1663 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1664 if (fcport->port_type != FCT_TARGET) 1665 continue; 1666 1667 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1668 if (ret != QLA_SUCCESS) { 1669 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1670 "Bus Reset failed: Reset=%d " 1671 "d_id=%x.\n", ret, fcport->d_id.b24); 1672 } 1673 } 1674 } 1675 1676 1677 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1678 atomic_set(&vha->loop_state, LOOP_DOWN); 1679 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1680 qla2x00_mark_all_devices_lost(vha); 1681 ret = qla2x00_full_login_lip(vha); 1682 if (ret != QLA_SUCCESS) { 1683 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1684 "full_login_lip=%d.\n", ret); 1685 } 1686 } 1687 1688 if (ha->flags.enable_lip_reset) { 1689 ret = qla2x00_lip_reset(vha); 1690 if (ret != QLA_SUCCESS) 1691 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1692 "lip_reset failed (%d).\n", ret); 1693 } 1694 1695 /* Issue marker command only when we are going to start the I/O */ 1696 vha->marker_needed = 1; 1697 1698 return QLA_SUCCESS; 1699 } 1700 1701 /* 1702 * The caller must ensure that no completion interrupts will happen 1703 * while this function is in progress. 1704 */ 1705 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1706 unsigned long *flags) 1707 __releases(qp->qp_lock_ptr) 1708 __acquires(qp->qp_lock_ptr) 1709 { 1710 DECLARE_COMPLETION_ONSTACK(comp); 1711 scsi_qla_host_t *vha = qp->vha; 1712 struct qla_hw_data *ha = vha->hw; 1713 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1714 int rval; 1715 bool ret_cmd; 1716 uint32_t ratov_j; 1717 1718 lockdep_assert_held(qp->qp_lock_ptr); 1719 1720 if (qla2x00_chip_is_down(vha)) { 1721 sp->done(sp, res); 1722 return; 1723 } 1724 1725 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1726 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1727 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1728 !qla2x00_isp_reg_stat(ha))) { 1729 if (sp->comp) { 1730 sp->done(sp, res); 1731 return; 1732 } 1733 1734 sp->comp = ∁ 1735 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1736 1737 rval = ha->isp_ops->abort_command(sp); 1738 /* Wait for command completion. */ 1739 ret_cmd = false; 1740 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1741 ratov_j = msecs_to_jiffies(ratov_j); 1742 switch (rval) { 1743 case QLA_SUCCESS: 1744 if (wait_for_completion_timeout(&comp, ratov_j)) { 1745 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1746 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1747 __func__, ha->r_a_tov/10); 1748 ret_cmd = true; 1749 } 1750 /* else FW return SP to driver */ 1751 break; 1752 default: 1753 ret_cmd = true; 1754 break; 1755 } 1756 1757 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1758 if (ret_cmd && blk_mq_request_started(cmd->request)) 1759 sp->done(sp, res); 1760 } else { 1761 sp->done(sp, res); 1762 } 1763 } 1764 1765 /* 1766 * The caller must ensure that no completion interrupts will happen 1767 * while this function is in progress. 1768 */ 1769 static void 1770 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1771 { 1772 int cnt; 1773 unsigned long flags; 1774 srb_t *sp; 1775 scsi_qla_host_t *vha = qp->vha; 1776 struct qla_hw_data *ha = vha->hw; 1777 struct req_que *req; 1778 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1779 struct qla_tgt_cmd *cmd; 1780 1781 if (!ha->req_q_map) 1782 return; 1783 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1784 req = qp->req; 1785 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1786 sp = req->outstanding_cmds[cnt]; 1787 if (sp) { 1788 switch (sp->cmd_type) { 1789 case TYPE_SRB: 1790 qla2x00_abort_srb(qp, sp, res, &flags); 1791 break; 1792 case TYPE_TGT_CMD: 1793 if (!vha->hw->tgt.tgt_ops || !tgt || 1794 qla_ini_mode_enabled(vha)) { 1795 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1796 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1797 vha->dpc_flags); 1798 continue; 1799 } 1800 cmd = (struct qla_tgt_cmd *)sp; 1801 cmd->aborted = 1; 1802 break; 1803 case TYPE_TGT_TMCMD: 1804 /* Skip task management functions. */ 1805 break; 1806 default: 1807 break; 1808 } 1809 req->outstanding_cmds[cnt] = NULL; 1810 } 1811 } 1812 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1813 } 1814 1815 /* 1816 * The caller must ensure that no completion interrupts will happen 1817 * while this function is in progress. 1818 */ 1819 void 1820 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1821 { 1822 int que; 1823 struct qla_hw_data *ha = vha->hw; 1824 1825 /* Continue only if initialization complete. */ 1826 if (!ha->base_qpair) 1827 return; 1828 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1829 1830 if (!ha->queue_pair_map) 1831 return; 1832 for (que = 0; que < ha->max_qpairs; que++) { 1833 if (!ha->queue_pair_map[que]) 1834 continue; 1835 1836 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1837 } 1838 } 1839 1840 static int 1841 qla2xxx_slave_alloc(struct scsi_device *sdev) 1842 { 1843 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1844 1845 if (!rport || fc_remote_port_chkready(rport)) 1846 return -ENXIO; 1847 1848 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1849 1850 return 0; 1851 } 1852 1853 static int 1854 qla2xxx_slave_configure(struct scsi_device *sdev) 1855 { 1856 scsi_qla_host_t *vha = shost_priv(sdev->host); 1857 struct req_que *req = vha->req; 1858 1859 if (IS_T10_PI_CAPABLE(vha->hw)) 1860 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1861 1862 scsi_change_queue_depth(sdev, req->max_q_depth); 1863 return 0; 1864 } 1865 1866 static void 1867 qla2xxx_slave_destroy(struct scsi_device *sdev) 1868 { 1869 sdev->hostdata = NULL; 1870 } 1871 1872 /** 1873 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1874 * @ha: HA context 1875 * 1876 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1877 * supported addressing method. 1878 */ 1879 static void 1880 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1881 { 1882 /* Assume a 32bit DMA mask. */ 1883 ha->flags.enable_64bit_addressing = 0; 1884 1885 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1886 /* Any upper-dword bits set? */ 1887 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1888 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1889 /* Ok, a 64bit DMA mask is applicable. */ 1890 ha->flags.enable_64bit_addressing = 1; 1891 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1892 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1893 return; 1894 } 1895 } 1896 1897 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1898 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1899 } 1900 1901 static void 1902 qla2x00_enable_intrs(struct qla_hw_data *ha) 1903 { 1904 unsigned long flags = 0; 1905 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1906 1907 spin_lock_irqsave(&ha->hardware_lock, flags); 1908 ha->interrupts_on = 1; 1909 /* enable risc and host interrupts */ 1910 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1911 rd_reg_word(®->ictrl); 1912 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1913 1914 } 1915 1916 static void 1917 qla2x00_disable_intrs(struct qla_hw_data *ha) 1918 { 1919 unsigned long flags = 0; 1920 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1921 1922 spin_lock_irqsave(&ha->hardware_lock, flags); 1923 ha->interrupts_on = 0; 1924 /* disable risc and host interrupts */ 1925 wrt_reg_word(®->ictrl, 0); 1926 rd_reg_word(®->ictrl); 1927 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1928 } 1929 1930 static void 1931 qla24xx_enable_intrs(struct qla_hw_data *ha) 1932 { 1933 unsigned long flags = 0; 1934 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1935 1936 spin_lock_irqsave(&ha->hardware_lock, flags); 1937 ha->interrupts_on = 1; 1938 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1939 rd_reg_dword(®->ictrl); 1940 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1941 } 1942 1943 static void 1944 qla24xx_disable_intrs(struct qla_hw_data *ha) 1945 { 1946 unsigned long flags = 0; 1947 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1948 1949 if (IS_NOPOLLING_TYPE(ha)) 1950 return; 1951 spin_lock_irqsave(&ha->hardware_lock, flags); 1952 ha->interrupts_on = 0; 1953 wrt_reg_dword(®->ictrl, 0); 1954 rd_reg_dword(®->ictrl); 1955 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1956 } 1957 1958 static int 1959 qla2x00_iospace_config(struct qla_hw_data *ha) 1960 { 1961 resource_size_t pio; 1962 uint16_t msix; 1963 1964 if (pci_request_selected_regions(ha->pdev, ha->bars, 1965 QLA2XXX_DRIVER_NAME)) { 1966 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1967 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1968 pci_name(ha->pdev)); 1969 goto iospace_error_exit; 1970 } 1971 if (!(ha->bars & 1)) 1972 goto skip_pio; 1973 1974 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1975 pio = pci_resource_start(ha->pdev, 0); 1976 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1977 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1978 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1979 "Invalid pci I/O region size (%s).\n", 1980 pci_name(ha->pdev)); 1981 pio = 0; 1982 } 1983 } else { 1984 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1985 "Region #0 no a PIO resource (%s).\n", 1986 pci_name(ha->pdev)); 1987 pio = 0; 1988 } 1989 ha->pio_address = pio; 1990 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1991 "PIO address=%llu.\n", 1992 (unsigned long long)ha->pio_address); 1993 1994 skip_pio: 1995 /* Use MMIO operations for all accesses. */ 1996 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1997 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1998 "Region #1 not an MMIO resource (%s), aborting.\n", 1999 pci_name(ha->pdev)); 2000 goto iospace_error_exit; 2001 } 2002 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2003 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2004 "Invalid PCI mem region size (%s), aborting.\n", 2005 pci_name(ha->pdev)); 2006 goto iospace_error_exit; 2007 } 2008 2009 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2010 if (!ha->iobase) { 2011 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2012 "Cannot remap MMIO (%s), aborting.\n", 2013 pci_name(ha->pdev)); 2014 goto iospace_error_exit; 2015 } 2016 2017 /* Determine queue resources */ 2018 ha->max_req_queues = ha->max_rsp_queues = 1; 2019 ha->msix_count = QLA_BASE_VECTORS; 2020 if (!ql2xmqsupport || !ql2xnvmeenable || 2021 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2022 goto mqiobase_exit; 2023 2024 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2025 pci_resource_len(ha->pdev, 3)); 2026 if (ha->mqiobase) { 2027 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2028 "MQIO Base=%p.\n", ha->mqiobase); 2029 /* Read MSIX vector size of the board */ 2030 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2031 ha->msix_count = msix + 1; 2032 /* Max queues are bounded by available msix vectors */ 2033 /* MB interrupt uses 1 vector */ 2034 ha->max_req_queues = ha->msix_count - 1; 2035 ha->max_rsp_queues = ha->max_req_queues; 2036 /* Queue pairs is the max value minus the base queue pair */ 2037 ha->max_qpairs = ha->max_rsp_queues - 1; 2038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2039 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2040 2041 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2042 "MSI-X vector count: %d.\n", ha->msix_count); 2043 } else 2044 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2045 "BAR 3 not enabled.\n"); 2046 2047 mqiobase_exit: 2048 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2049 "MSIX Count: %d.\n", ha->msix_count); 2050 return (0); 2051 2052 iospace_error_exit: 2053 return (-ENOMEM); 2054 } 2055 2056 2057 static int 2058 qla83xx_iospace_config(struct qla_hw_data *ha) 2059 { 2060 uint16_t msix; 2061 2062 if (pci_request_selected_regions(ha->pdev, ha->bars, 2063 QLA2XXX_DRIVER_NAME)) { 2064 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2065 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2066 pci_name(ha->pdev)); 2067 2068 goto iospace_error_exit; 2069 } 2070 2071 /* Use MMIO operations for all accesses. */ 2072 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2073 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2074 "Invalid pci I/O region size (%s).\n", 2075 pci_name(ha->pdev)); 2076 goto iospace_error_exit; 2077 } 2078 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2079 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2080 "Invalid PCI mem region size (%s), aborting\n", 2081 pci_name(ha->pdev)); 2082 goto iospace_error_exit; 2083 } 2084 2085 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2086 if (!ha->iobase) { 2087 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2088 "Cannot remap MMIO (%s), aborting.\n", 2089 pci_name(ha->pdev)); 2090 goto iospace_error_exit; 2091 } 2092 2093 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2094 /* 83XX 26XX always use MQ type access for queues 2095 * - mbar 2, a.k.a region 4 */ 2096 ha->max_req_queues = ha->max_rsp_queues = 1; 2097 ha->msix_count = QLA_BASE_VECTORS; 2098 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2099 pci_resource_len(ha->pdev, 4)); 2100 2101 if (!ha->mqiobase) { 2102 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2103 "BAR2/region4 not enabled\n"); 2104 goto mqiobase_exit; 2105 } 2106 2107 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2108 pci_resource_len(ha->pdev, 2)); 2109 if (ha->msixbase) { 2110 /* Read MSIX vector size of the board */ 2111 pci_read_config_word(ha->pdev, 2112 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2113 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2114 /* 2115 * By default, driver uses at least two msix vectors 2116 * (default & rspq) 2117 */ 2118 if (ql2xmqsupport || ql2xnvmeenable) { 2119 /* MB interrupt uses 1 vector */ 2120 ha->max_req_queues = ha->msix_count - 1; 2121 2122 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2123 if (QLA_TGT_MODE_ENABLED()) 2124 ha->max_req_queues--; 2125 2126 ha->max_rsp_queues = ha->max_req_queues; 2127 2128 /* Queue pairs is the max value minus 2129 * the base queue pair */ 2130 ha->max_qpairs = ha->max_req_queues - 1; 2131 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2132 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2133 } 2134 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2135 "MSI-X vector count: %d.\n", ha->msix_count); 2136 } else 2137 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2138 "BAR 1 not enabled.\n"); 2139 2140 mqiobase_exit: 2141 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2142 "MSIX Count: %d.\n", ha->msix_count); 2143 return 0; 2144 2145 iospace_error_exit: 2146 return -ENOMEM; 2147 } 2148 2149 static struct isp_operations qla2100_isp_ops = { 2150 .pci_config = qla2100_pci_config, 2151 .reset_chip = qla2x00_reset_chip, 2152 .chip_diag = qla2x00_chip_diag, 2153 .config_rings = qla2x00_config_rings, 2154 .reset_adapter = qla2x00_reset_adapter, 2155 .nvram_config = qla2x00_nvram_config, 2156 .update_fw_options = qla2x00_update_fw_options, 2157 .load_risc = qla2x00_load_risc, 2158 .pci_info_str = qla2x00_pci_info_str, 2159 .fw_version_str = qla2x00_fw_version_str, 2160 .intr_handler = qla2100_intr_handler, 2161 .enable_intrs = qla2x00_enable_intrs, 2162 .disable_intrs = qla2x00_disable_intrs, 2163 .abort_command = qla2x00_abort_command, 2164 .target_reset = qla2x00_abort_target, 2165 .lun_reset = qla2x00_lun_reset, 2166 .fabric_login = qla2x00_login_fabric, 2167 .fabric_logout = qla2x00_fabric_logout, 2168 .calc_req_entries = qla2x00_calc_iocbs_32, 2169 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2170 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2171 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2172 .read_nvram = qla2x00_read_nvram_data, 2173 .write_nvram = qla2x00_write_nvram_data, 2174 .fw_dump = qla2100_fw_dump, 2175 .beacon_on = NULL, 2176 .beacon_off = NULL, 2177 .beacon_blink = NULL, 2178 .read_optrom = qla2x00_read_optrom_data, 2179 .write_optrom = qla2x00_write_optrom_data, 2180 .get_flash_version = qla2x00_get_flash_version, 2181 .start_scsi = qla2x00_start_scsi, 2182 .start_scsi_mq = NULL, 2183 .abort_isp = qla2x00_abort_isp, 2184 .iospace_config = qla2x00_iospace_config, 2185 .initialize_adapter = qla2x00_initialize_adapter, 2186 }; 2187 2188 static struct isp_operations qla2300_isp_ops = { 2189 .pci_config = qla2300_pci_config, 2190 .reset_chip = qla2x00_reset_chip, 2191 .chip_diag = qla2x00_chip_diag, 2192 .config_rings = qla2x00_config_rings, 2193 .reset_adapter = qla2x00_reset_adapter, 2194 .nvram_config = qla2x00_nvram_config, 2195 .update_fw_options = qla2x00_update_fw_options, 2196 .load_risc = qla2x00_load_risc, 2197 .pci_info_str = qla2x00_pci_info_str, 2198 .fw_version_str = qla2x00_fw_version_str, 2199 .intr_handler = qla2300_intr_handler, 2200 .enable_intrs = qla2x00_enable_intrs, 2201 .disable_intrs = qla2x00_disable_intrs, 2202 .abort_command = qla2x00_abort_command, 2203 .target_reset = qla2x00_abort_target, 2204 .lun_reset = qla2x00_lun_reset, 2205 .fabric_login = qla2x00_login_fabric, 2206 .fabric_logout = qla2x00_fabric_logout, 2207 .calc_req_entries = qla2x00_calc_iocbs_32, 2208 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2209 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2210 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2211 .read_nvram = qla2x00_read_nvram_data, 2212 .write_nvram = qla2x00_write_nvram_data, 2213 .fw_dump = qla2300_fw_dump, 2214 .beacon_on = qla2x00_beacon_on, 2215 .beacon_off = qla2x00_beacon_off, 2216 .beacon_blink = qla2x00_beacon_blink, 2217 .read_optrom = qla2x00_read_optrom_data, 2218 .write_optrom = qla2x00_write_optrom_data, 2219 .get_flash_version = qla2x00_get_flash_version, 2220 .start_scsi = qla2x00_start_scsi, 2221 .start_scsi_mq = NULL, 2222 .abort_isp = qla2x00_abort_isp, 2223 .iospace_config = qla2x00_iospace_config, 2224 .initialize_adapter = qla2x00_initialize_adapter, 2225 }; 2226 2227 static struct isp_operations qla24xx_isp_ops = { 2228 .pci_config = qla24xx_pci_config, 2229 .reset_chip = qla24xx_reset_chip, 2230 .chip_diag = qla24xx_chip_diag, 2231 .config_rings = qla24xx_config_rings, 2232 .reset_adapter = qla24xx_reset_adapter, 2233 .nvram_config = qla24xx_nvram_config, 2234 .update_fw_options = qla24xx_update_fw_options, 2235 .load_risc = qla24xx_load_risc, 2236 .pci_info_str = qla24xx_pci_info_str, 2237 .fw_version_str = qla24xx_fw_version_str, 2238 .intr_handler = qla24xx_intr_handler, 2239 .enable_intrs = qla24xx_enable_intrs, 2240 .disable_intrs = qla24xx_disable_intrs, 2241 .abort_command = qla24xx_abort_command, 2242 .target_reset = qla24xx_abort_target, 2243 .lun_reset = qla24xx_lun_reset, 2244 .fabric_login = qla24xx_login_fabric, 2245 .fabric_logout = qla24xx_fabric_logout, 2246 .calc_req_entries = NULL, 2247 .build_iocbs = NULL, 2248 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2249 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2250 .read_nvram = qla24xx_read_nvram_data, 2251 .write_nvram = qla24xx_write_nvram_data, 2252 .fw_dump = qla24xx_fw_dump, 2253 .beacon_on = qla24xx_beacon_on, 2254 .beacon_off = qla24xx_beacon_off, 2255 .beacon_blink = qla24xx_beacon_blink, 2256 .read_optrom = qla24xx_read_optrom_data, 2257 .write_optrom = qla24xx_write_optrom_data, 2258 .get_flash_version = qla24xx_get_flash_version, 2259 .start_scsi = qla24xx_start_scsi, 2260 .start_scsi_mq = NULL, 2261 .abort_isp = qla2x00_abort_isp, 2262 .iospace_config = qla2x00_iospace_config, 2263 .initialize_adapter = qla2x00_initialize_adapter, 2264 }; 2265 2266 static struct isp_operations qla25xx_isp_ops = { 2267 .pci_config = qla25xx_pci_config, 2268 .reset_chip = qla24xx_reset_chip, 2269 .chip_diag = qla24xx_chip_diag, 2270 .config_rings = qla24xx_config_rings, 2271 .reset_adapter = qla24xx_reset_adapter, 2272 .nvram_config = qla24xx_nvram_config, 2273 .update_fw_options = qla24xx_update_fw_options, 2274 .load_risc = qla24xx_load_risc, 2275 .pci_info_str = qla24xx_pci_info_str, 2276 .fw_version_str = qla24xx_fw_version_str, 2277 .intr_handler = qla24xx_intr_handler, 2278 .enable_intrs = qla24xx_enable_intrs, 2279 .disable_intrs = qla24xx_disable_intrs, 2280 .abort_command = qla24xx_abort_command, 2281 .target_reset = qla24xx_abort_target, 2282 .lun_reset = qla24xx_lun_reset, 2283 .fabric_login = qla24xx_login_fabric, 2284 .fabric_logout = qla24xx_fabric_logout, 2285 .calc_req_entries = NULL, 2286 .build_iocbs = NULL, 2287 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2288 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2289 .read_nvram = qla25xx_read_nvram_data, 2290 .write_nvram = qla25xx_write_nvram_data, 2291 .fw_dump = qla25xx_fw_dump, 2292 .beacon_on = qla24xx_beacon_on, 2293 .beacon_off = qla24xx_beacon_off, 2294 .beacon_blink = qla24xx_beacon_blink, 2295 .read_optrom = qla25xx_read_optrom_data, 2296 .write_optrom = qla24xx_write_optrom_data, 2297 .get_flash_version = qla24xx_get_flash_version, 2298 .start_scsi = qla24xx_dif_start_scsi, 2299 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2300 .abort_isp = qla2x00_abort_isp, 2301 .iospace_config = qla2x00_iospace_config, 2302 .initialize_adapter = qla2x00_initialize_adapter, 2303 }; 2304 2305 static struct isp_operations qla81xx_isp_ops = { 2306 .pci_config = qla25xx_pci_config, 2307 .reset_chip = qla24xx_reset_chip, 2308 .chip_diag = qla24xx_chip_diag, 2309 .config_rings = qla24xx_config_rings, 2310 .reset_adapter = qla24xx_reset_adapter, 2311 .nvram_config = qla81xx_nvram_config, 2312 .update_fw_options = qla24xx_update_fw_options, 2313 .load_risc = qla81xx_load_risc, 2314 .pci_info_str = qla24xx_pci_info_str, 2315 .fw_version_str = qla24xx_fw_version_str, 2316 .intr_handler = qla24xx_intr_handler, 2317 .enable_intrs = qla24xx_enable_intrs, 2318 .disable_intrs = qla24xx_disable_intrs, 2319 .abort_command = qla24xx_abort_command, 2320 .target_reset = qla24xx_abort_target, 2321 .lun_reset = qla24xx_lun_reset, 2322 .fabric_login = qla24xx_login_fabric, 2323 .fabric_logout = qla24xx_fabric_logout, 2324 .calc_req_entries = NULL, 2325 .build_iocbs = NULL, 2326 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2327 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2328 .read_nvram = NULL, 2329 .write_nvram = NULL, 2330 .fw_dump = qla81xx_fw_dump, 2331 .beacon_on = qla24xx_beacon_on, 2332 .beacon_off = qla24xx_beacon_off, 2333 .beacon_blink = qla83xx_beacon_blink, 2334 .read_optrom = qla25xx_read_optrom_data, 2335 .write_optrom = qla24xx_write_optrom_data, 2336 .get_flash_version = qla24xx_get_flash_version, 2337 .start_scsi = qla24xx_dif_start_scsi, 2338 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2339 .abort_isp = qla2x00_abort_isp, 2340 .iospace_config = qla2x00_iospace_config, 2341 .initialize_adapter = qla2x00_initialize_adapter, 2342 }; 2343 2344 static struct isp_operations qla82xx_isp_ops = { 2345 .pci_config = qla82xx_pci_config, 2346 .reset_chip = qla82xx_reset_chip, 2347 .chip_diag = qla24xx_chip_diag, 2348 .config_rings = qla82xx_config_rings, 2349 .reset_adapter = qla24xx_reset_adapter, 2350 .nvram_config = qla81xx_nvram_config, 2351 .update_fw_options = qla24xx_update_fw_options, 2352 .load_risc = qla82xx_load_risc, 2353 .pci_info_str = qla24xx_pci_info_str, 2354 .fw_version_str = qla24xx_fw_version_str, 2355 .intr_handler = qla82xx_intr_handler, 2356 .enable_intrs = qla82xx_enable_intrs, 2357 .disable_intrs = qla82xx_disable_intrs, 2358 .abort_command = qla24xx_abort_command, 2359 .target_reset = qla24xx_abort_target, 2360 .lun_reset = qla24xx_lun_reset, 2361 .fabric_login = qla24xx_login_fabric, 2362 .fabric_logout = qla24xx_fabric_logout, 2363 .calc_req_entries = NULL, 2364 .build_iocbs = NULL, 2365 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2366 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2367 .read_nvram = qla24xx_read_nvram_data, 2368 .write_nvram = qla24xx_write_nvram_data, 2369 .fw_dump = qla82xx_fw_dump, 2370 .beacon_on = qla82xx_beacon_on, 2371 .beacon_off = qla82xx_beacon_off, 2372 .beacon_blink = NULL, 2373 .read_optrom = qla82xx_read_optrom_data, 2374 .write_optrom = qla82xx_write_optrom_data, 2375 .get_flash_version = qla82xx_get_flash_version, 2376 .start_scsi = qla82xx_start_scsi, 2377 .start_scsi_mq = NULL, 2378 .abort_isp = qla82xx_abort_isp, 2379 .iospace_config = qla82xx_iospace_config, 2380 .initialize_adapter = qla2x00_initialize_adapter, 2381 }; 2382 2383 static struct isp_operations qla8044_isp_ops = { 2384 .pci_config = qla82xx_pci_config, 2385 .reset_chip = qla82xx_reset_chip, 2386 .chip_diag = qla24xx_chip_diag, 2387 .config_rings = qla82xx_config_rings, 2388 .reset_adapter = qla24xx_reset_adapter, 2389 .nvram_config = qla81xx_nvram_config, 2390 .update_fw_options = qla24xx_update_fw_options, 2391 .load_risc = qla82xx_load_risc, 2392 .pci_info_str = qla24xx_pci_info_str, 2393 .fw_version_str = qla24xx_fw_version_str, 2394 .intr_handler = qla8044_intr_handler, 2395 .enable_intrs = qla82xx_enable_intrs, 2396 .disable_intrs = qla82xx_disable_intrs, 2397 .abort_command = qla24xx_abort_command, 2398 .target_reset = qla24xx_abort_target, 2399 .lun_reset = qla24xx_lun_reset, 2400 .fabric_login = qla24xx_login_fabric, 2401 .fabric_logout = qla24xx_fabric_logout, 2402 .calc_req_entries = NULL, 2403 .build_iocbs = NULL, 2404 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2405 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2406 .read_nvram = NULL, 2407 .write_nvram = NULL, 2408 .fw_dump = qla8044_fw_dump, 2409 .beacon_on = qla82xx_beacon_on, 2410 .beacon_off = qla82xx_beacon_off, 2411 .beacon_blink = NULL, 2412 .read_optrom = qla8044_read_optrom_data, 2413 .write_optrom = qla8044_write_optrom_data, 2414 .get_flash_version = qla82xx_get_flash_version, 2415 .start_scsi = qla82xx_start_scsi, 2416 .start_scsi_mq = NULL, 2417 .abort_isp = qla8044_abort_isp, 2418 .iospace_config = qla82xx_iospace_config, 2419 .initialize_adapter = qla2x00_initialize_adapter, 2420 }; 2421 2422 static struct isp_operations qla83xx_isp_ops = { 2423 .pci_config = qla25xx_pci_config, 2424 .reset_chip = qla24xx_reset_chip, 2425 .chip_diag = qla24xx_chip_diag, 2426 .config_rings = qla24xx_config_rings, 2427 .reset_adapter = qla24xx_reset_adapter, 2428 .nvram_config = qla81xx_nvram_config, 2429 .update_fw_options = qla24xx_update_fw_options, 2430 .load_risc = qla81xx_load_risc, 2431 .pci_info_str = qla24xx_pci_info_str, 2432 .fw_version_str = qla24xx_fw_version_str, 2433 .intr_handler = qla24xx_intr_handler, 2434 .enable_intrs = qla24xx_enable_intrs, 2435 .disable_intrs = qla24xx_disable_intrs, 2436 .abort_command = qla24xx_abort_command, 2437 .target_reset = qla24xx_abort_target, 2438 .lun_reset = qla24xx_lun_reset, 2439 .fabric_login = qla24xx_login_fabric, 2440 .fabric_logout = qla24xx_fabric_logout, 2441 .calc_req_entries = NULL, 2442 .build_iocbs = NULL, 2443 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2444 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2445 .read_nvram = NULL, 2446 .write_nvram = NULL, 2447 .fw_dump = qla83xx_fw_dump, 2448 .beacon_on = qla24xx_beacon_on, 2449 .beacon_off = qla24xx_beacon_off, 2450 .beacon_blink = qla83xx_beacon_blink, 2451 .read_optrom = qla25xx_read_optrom_data, 2452 .write_optrom = qla24xx_write_optrom_data, 2453 .get_flash_version = qla24xx_get_flash_version, 2454 .start_scsi = qla24xx_dif_start_scsi, 2455 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2456 .abort_isp = qla2x00_abort_isp, 2457 .iospace_config = qla83xx_iospace_config, 2458 .initialize_adapter = qla2x00_initialize_adapter, 2459 }; 2460 2461 static struct isp_operations qlafx00_isp_ops = { 2462 .pci_config = qlafx00_pci_config, 2463 .reset_chip = qlafx00_soft_reset, 2464 .chip_diag = qlafx00_chip_diag, 2465 .config_rings = qlafx00_config_rings, 2466 .reset_adapter = qlafx00_soft_reset, 2467 .nvram_config = NULL, 2468 .update_fw_options = NULL, 2469 .load_risc = NULL, 2470 .pci_info_str = qlafx00_pci_info_str, 2471 .fw_version_str = qlafx00_fw_version_str, 2472 .intr_handler = qlafx00_intr_handler, 2473 .enable_intrs = qlafx00_enable_intrs, 2474 .disable_intrs = qlafx00_disable_intrs, 2475 .abort_command = qla24xx_async_abort_command, 2476 .target_reset = qlafx00_abort_target, 2477 .lun_reset = qlafx00_lun_reset, 2478 .fabric_login = NULL, 2479 .fabric_logout = NULL, 2480 .calc_req_entries = NULL, 2481 .build_iocbs = NULL, 2482 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2483 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2484 .read_nvram = qla24xx_read_nvram_data, 2485 .write_nvram = qla24xx_write_nvram_data, 2486 .fw_dump = NULL, 2487 .beacon_on = qla24xx_beacon_on, 2488 .beacon_off = qla24xx_beacon_off, 2489 .beacon_blink = NULL, 2490 .read_optrom = qla24xx_read_optrom_data, 2491 .write_optrom = qla24xx_write_optrom_data, 2492 .get_flash_version = qla24xx_get_flash_version, 2493 .start_scsi = qlafx00_start_scsi, 2494 .start_scsi_mq = NULL, 2495 .abort_isp = qlafx00_abort_isp, 2496 .iospace_config = qlafx00_iospace_config, 2497 .initialize_adapter = qlafx00_initialize_adapter, 2498 }; 2499 2500 static struct isp_operations qla27xx_isp_ops = { 2501 .pci_config = qla25xx_pci_config, 2502 .reset_chip = qla24xx_reset_chip, 2503 .chip_diag = qla24xx_chip_diag, 2504 .config_rings = qla24xx_config_rings, 2505 .reset_adapter = qla24xx_reset_adapter, 2506 .nvram_config = qla81xx_nvram_config, 2507 .update_fw_options = qla24xx_update_fw_options, 2508 .load_risc = qla81xx_load_risc, 2509 .pci_info_str = qla24xx_pci_info_str, 2510 .fw_version_str = qla24xx_fw_version_str, 2511 .intr_handler = qla24xx_intr_handler, 2512 .enable_intrs = qla24xx_enable_intrs, 2513 .disable_intrs = qla24xx_disable_intrs, 2514 .abort_command = qla24xx_abort_command, 2515 .target_reset = qla24xx_abort_target, 2516 .lun_reset = qla24xx_lun_reset, 2517 .fabric_login = qla24xx_login_fabric, 2518 .fabric_logout = qla24xx_fabric_logout, 2519 .calc_req_entries = NULL, 2520 .build_iocbs = NULL, 2521 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2522 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2523 .read_nvram = NULL, 2524 .write_nvram = NULL, 2525 .fw_dump = qla27xx_fwdump, 2526 .mpi_fw_dump = qla27xx_mpi_fwdump, 2527 .beacon_on = qla24xx_beacon_on, 2528 .beacon_off = qla24xx_beacon_off, 2529 .beacon_blink = qla83xx_beacon_blink, 2530 .read_optrom = qla25xx_read_optrom_data, 2531 .write_optrom = qla24xx_write_optrom_data, 2532 .get_flash_version = qla24xx_get_flash_version, 2533 .start_scsi = qla24xx_dif_start_scsi, 2534 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2535 .abort_isp = qla2x00_abort_isp, 2536 .iospace_config = qla83xx_iospace_config, 2537 .initialize_adapter = qla2x00_initialize_adapter, 2538 }; 2539 2540 static inline void 2541 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2542 { 2543 ha->device_type = DT_EXTENDED_IDS; 2544 switch (ha->pdev->device) { 2545 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2546 ha->isp_type |= DT_ISP2100; 2547 ha->device_type &= ~DT_EXTENDED_IDS; 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2549 break; 2550 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2551 ha->isp_type |= DT_ISP2200; 2552 ha->device_type &= ~DT_EXTENDED_IDS; 2553 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2554 break; 2555 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2556 ha->isp_type |= DT_ISP2300; 2557 ha->device_type |= DT_ZIO_SUPPORTED; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2561 ha->isp_type |= DT_ISP2312; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2564 break; 2565 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2566 ha->isp_type |= DT_ISP2322; 2567 ha->device_type |= DT_ZIO_SUPPORTED; 2568 if (ha->pdev->subsystem_vendor == 0x1028 && 2569 ha->pdev->subsystem_device == 0x0170) 2570 ha->device_type |= DT_OEM_001; 2571 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2572 break; 2573 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2574 ha->isp_type |= DT_ISP6312; 2575 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2576 break; 2577 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2578 ha->isp_type |= DT_ISP6322; 2579 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2580 break; 2581 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2582 ha->isp_type |= DT_ISP2422; 2583 ha->device_type |= DT_ZIO_SUPPORTED; 2584 ha->device_type |= DT_FWI2; 2585 ha->device_type |= DT_IIDMA; 2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2587 break; 2588 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2589 ha->isp_type |= DT_ISP2432; 2590 ha->device_type |= DT_ZIO_SUPPORTED; 2591 ha->device_type |= DT_FWI2; 2592 ha->device_type |= DT_IIDMA; 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2594 break; 2595 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2596 ha->isp_type |= DT_ISP8432; 2597 ha->device_type |= DT_ZIO_SUPPORTED; 2598 ha->device_type |= DT_FWI2; 2599 ha->device_type |= DT_IIDMA; 2600 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2601 break; 2602 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2603 ha->isp_type |= DT_ISP5422; 2604 ha->device_type |= DT_FWI2; 2605 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2606 break; 2607 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2608 ha->isp_type |= DT_ISP5432; 2609 ha->device_type |= DT_FWI2; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2611 break; 2612 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2613 ha->isp_type |= DT_ISP2532; 2614 ha->device_type |= DT_ZIO_SUPPORTED; 2615 ha->device_type |= DT_FWI2; 2616 ha->device_type |= DT_IIDMA; 2617 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2618 break; 2619 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2620 ha->isp_type |= DT_ISP8001; 2621 ha->device_type |= DT_ZIO_SUPPORTED; 2622 ha->device_type |= DT_FWI2; 2623 ha->device_type |= DT_IIDMA; 2624 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2625 break; 2626 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2627 ha->isp_type |= DT_ISP8021; 2628 ha->device_type |= DT_ZIO_SUPPORTED; 2629 ha->device_type |= DT_FWI2; 2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2631 /* Initialize 82XX ISP flags */ 2632 qla82xx_init_flags(ha); 2633 break; 2634 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2635 ha->isp_type |= DT_ISP8044; 2636 ha->device_type |= DT_ZIO_SUPPORTED; 2637 ha->device_type |= DT_FWI2; 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2639 /* Initialize 82XX ISP flags */ 2640 qla82xx_init_flags(ha); 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2643 ha->isp_type |= DT_ISP2031; 2644 ha->device_type |= DT_ZIO_SUPPORTED; 2645 ha->device_type |= DT_FWI2; 2646 ha->device_type |= DT_IIDMA; 2647 ha->device_type |= DT_T10_PI; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2651 ha->isp_type |= DT_ISP8031; 2652 ha->device_type |= DT_ZIO_SUPPORTED; 2653 ha->device_type |= DT_FWI2; 2654 ha->device_type |= DT_IIDMA; 2655 ha->device_type |= DT_T10_PI; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2657 break; 2658 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2659 ha->isp_type |= DT_ISPFX00; 2660 break; 2661 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2662 ha->isp_type |= DT_ISP2071; 2663 ha->device_type |= DT_ZIO_SUPPORTED; 2664 ha->device_type |= DT_FWI2; 2665 ha->device_type |= DT_IIDMA; 2666 ha->device_type |= DT_T10_PI; 2667 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2668 break; 2669 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2670 ha->isp_type |= DT_ISP2271; 2671 ha->device_type |= DT_ZIO_SUPPORTED; 2672 ha->device_type |= DT_FWI2; 2673 ha->device_type |= DT_IIDMA; 2674 ha->device_type |= DT_T10_PI; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2678 ha->isp_type |= DT_ISP2261; 2679 ha->device_type |= DT_ZIO_SUPPORTED; 2680 ha->device_type |= DT_FWI2; 2681 ha->device_type |= DT_IIDMA; 2682 ha->device_type |= DT_T10_PI; 2683 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2684 break; 2685 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2686 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2687 ha->isp_type |= DT_ISP2081; 2688 ha->device_type |= DT_ZIO_SUPPORTED; 2689 ha->device_type |= DT_FWI2; 2690 ha->device_type |= DT_IIDMA; 2691 ha->device_type |= DT_T10_PI; 2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2693 break; 2694 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2695 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2696 ha->isp_type |= DT_ISP2281; 2697 ha->device_type |= DT_ZIO_SUPPORTED; 2698 ha->device_type |= DT_FWI2; 2699 ha->device_type |= DT_IIDMA; 2700 ha->device_type |= DT_T10_PI; 2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2702 break; 2703 } 2704 2705 if (IS_QLA82XX(ha)) 2706 ha->port_no = ha->portnum & 1; 2707 else { 2708 /* Get adapter physical port no from interrupt pin register. */ 2709 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2710 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2711 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2712 ha->port_no--; 2713 else 2714 ha->port_no = !(ha->port_no & 1); 2715 } 2716 2717 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2718 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2719 ha->device_type, ha->port_no, ha->fw_srisc_address); 2720 } 2721 2722 static void 2723 qla2xxx_scan_start(struct Scsi_Host *shost) 2724 { 2725 scsi_qla_host_t *vha = shost_priv(shost); 2726 2727 if (vha->hw->flags.running_gold_fw) 2728 return; 2729 2730 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2731 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2732 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2733 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2734 } 2735 2736 static int 2737 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2738 { 2739 scsi_qla_host_t *vha = shost_priv(shost); 2740 2741 if (test_bit(UNLOADING, &vha->dpc_flags)) 2742 return 1; 2743 if (!vha->host) 2744 return 1; 2745 if (time > vha->hw->loop_reset_delay * HZ) 2746 return 1; 2747 2748 return atomic_read(&vha->loop_state) == LOOP_READY; 2749 } 2750 2751 static void qla2x00_iocb_work_fn(struct work_struct *work) 2752 { 2753 struct scsi_qla_host *vha = container_of(work, 2754 struct scsi_qla_host, iocb_work); 2755 struct qla_hw_data *ha = vha->hw; 2756 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2757 int i = 2; 2758 unsigned long flags; 2759 2760 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2761 return; 2762 2763 while (!list_empty(&vha->work_list) && i > 0) { 2764 qla2x00_do_work(vha); 2765 i--; 2766 } 2767 2768 spin_lock_irqsave(&vha->work_lock, flags); 2769 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2770 spin_unlock_irqrestore(&vha->work_lock, flags); 2771 } 2772 2773 /* 2774 * PCI driver interface 2775 */ 2776 static int 2777 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2778 { 2779 int ret = -ENODEV; 2780 struct Scsi_Host *host; 2781 scsi_qla_host_t *base_vha = NULL; 2782 struct qla_hw_data *ha; 2783 char pci_info[30]; 2784 char fw_str[30], wq_name[30]; 2785 struct scsi_host_template *sht; 2786 int bars, mem_only = 0; 2787 uint16_t req_length = 0, rsp_length = 0; 2788 struct req_que *req = NULL; 2789 struct rsp_que *rsp = NULL; 2790 int i; 2791 2792 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2793 sht = &qla2xxx_driver_template; 2794 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2813 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2814 mem_only = 1; 2815 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2816 "Mem only adapter.\n"); 2817 } 2818 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2819 "Bars=%d.\n", bars); 2820 2821 if (mem_only) { 2822 if (pci_enable_device_mem(pdev)) 2823 return ret; 2824 } else { 2825 if (pci_enable_device(pdev)) 2826 return ret; 2827 } 2828 2829 /* This may fail but that's ok */ 2830 pci_enable_pcie_error_reporting(pdev); 2831 2832 /* Turn off T10-DIF when FC-NVMe is enabled */ 2833 if (ql2xnvmeenable) 2834 ql2xenabledif = 0; 2835 2836 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2837 if (!ha) { 2838 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2839 "Unable to allocate memory for ha.\n"); 2840 goto disable_device; 2841 } 2842 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2843 "Memory allocated for ha=%p.\n", ha); 2844 ha->pdev = pdev; 2845 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2846 spin_lock_init(&ha->tgt.q_full_lock); 2847 spin_lock_init(&ha->tgt.sess_lock); 2848 spin_lock_init(&ha->tgt.atio_lock); 2849 2850 atomic_set(&ha->nvme_active_aen_cnt, 0); 2851 2852 /* Clear our data area */ 2853 ha->bars = bars; 2854 ha->mem_only = mem_only; 2855 spin_lock_init(&ha->hardware_lock); 2856 spin_lock_init(&ha->vport_slock); 2857 mutex_init(&ha->selflogin_lock); 2858 mutex_init(&ha->optrom_mutex); 2859 2860 /* Set ISP-type information. */ 2861 qla2x00_set_isp_flags(ha); 2862 2863 /* Set EEH reset type to fundamental if required by hba */ 2864 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2865 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2866 pdev->needs_freset = 1; 2867 2868 ha->prev_topology = 0; 2869 ha->init_cb_size = sizeof(init_cb_t); 2870 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2871 ha->optrom_size = OPTROM_SIZE_2300; 2872 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2873 atomic_set(&ha->num_pend_mbx_stage1, 0); 2874 atomic_set(&ha->num_pend_mbx_stage2, 0); 2875 atomic_set(&ha->num_pend_mbx_stage3, 0); 2876 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2877 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2878 2879 /* Assign ISP specific operations. */ 2880 if (IS_QLA2100(ha)) { 2881 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2882 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2883 req_length = REQUEST_ENTRY_CNT_2100; 2884 rsp_length = RESPONSE_ENTRY_CNT_2100; 2885 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2886 ha->gid_list_info_size = 4; 2887 ha->flash_conf_off = ~0; 2888 ha->flash_data_off = ~0; 2889 ha->nvram_conf_off = ~0; 2890 ha->nvram_data_off = ~0; 2891 ha->isp_ops = &qla2100_isp_ops; 2892 } else if (IS_QLA2200(ha)) { 2893 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2894 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2895 req_length = REQUEST_ENTRY_CNT_2200; 2896 rsp_length = RESPONSE_ENTRY_CNT_2100; 2897 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2898 ha->gid_list_info_size = 4; 2899 ha->flash_conf_off = ~0; 2900 ha->flash_data_off = ~0; 2901 ha->nvram_conf_off = ~0; 2902 ha->nvram_data_off = ~0; 2903 ha->isp_ops = &qla2100_isp_ops; 2904 } else if (IS_QLA23XX(ha)) { 2905 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2906 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2907 req_length = REQUEST_ENTRY_CNT_2200; 2908 rsp_length = RESPONSE_ENTRY_CNT_2300; 2909 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2910 ha->gid_list_info_size = 6; 2911 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2912 ha->optrom_size = OPTROM_SIZE_2322; 2913 ha->flash_conf_off = ~0; 2914 ha->flash_data_off = ~0; 2915 ha->nvram_conf_off = ~0; 2916 ha->nvram_data_off = ~0; 2917 ha->isp_ops = &qla2300_isp_ops; 2918 } else if (IS_QLA24XX_TYPE(ha)) { 2919 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2920 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2921 req_length = REQUEST_ENTRY_CNT_24XX; 2922 rsp_length = RESPONSE_ENTRY_CNT_2300; 2923 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2924 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2925 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2926 ha->gid_list_info_size = 8; 2927 ha->optrom_size = OPTROM_SIZE_24XX; 2928 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2929 ha->isp_ops = &qla24xx_isp_ops; 2930 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2931 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2932 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2933 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2934 } else if (IS_QLA25XX(ha)) { 2935 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2936 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2937 req_length = REQUEST_ENTRY_CNT_24XX; 2938 rsp_length = RESPONSE_ENTRY_CNT_2300; 2939 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2940 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2941 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2942 ha->gid_list_info_size = 8; 2943 ha->optrom_size = OPTROM_SIZE_25XX; 2944 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2945 ha->isp_ops = &qla25xx_isp_ops; 2946 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2947 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2948 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2949 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2950 } else if (IS_QLA81XX(ha)) { 2951 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2952 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2953 req_length = REQUEST_ENTRY_CNT_24XX; 2954 rsp_length = RESPONSE_ENTRY_CNT_2300; 2955 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2956 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2957 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2958 ha->gid_list_info_size = 8; 2959 ha->optrom_size = OPTROM_SIZE_81XX; 2960 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2961 ha->isp_ops = &qla81xx_isp_ops; 2962 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2963 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2964 ha->nvram_conf_off = ~0; 2965 ha->nvram_data_off = ~0; 2966 } else if (IS_QLA82XX(ha)) { 2967 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2968 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2969 req_length = REQUEST_ENTRY_CNT_82XX; 2970 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2971 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2972 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2973 ha->gid_list_info_size = 8; 2974 ha->optrom_size = OPTROM_SIZE_82XX; 2975 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2976 ha->isp_ops = &qla82xx_isp_ops; 2977 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2978 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2979 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2980 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2981 } else if (IS_QLA8044(ha)) { 2982 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2983 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2984 req_length = REQUEST_ENTRY_CNT_82XX; 2985 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2988 ha->gid_list_info_size = 8; 2989 ha->optrom_size = OPTROM_SIZE_83XX; 2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2991 ha->isp_ops = &qla8044_isp_ops; 2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2994 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2995 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2996 } else if (IS_QLA83XX(ha)) { 2997 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2998 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2999 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3000 req_length = REQUEST_ENTRY_CNT_83XX; 3001 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3002 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3003 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3004 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3005 ha->gid_list_info_size = 8; 3006 ha->optrom_size = OPTROM_SIZE_83XX; 3007 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3008 ha->isp_ops = &qla83xx_isp_ops; 3009 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3010 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3011 ha->nvram_conf_off = ~0; 3012 ha->nvram_data_off = ~0; 3013 } else if (IS_QLAFX00(ha)) { 3014 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3015 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3016 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3017 req_length = REQUEST_ENTRY_CNT_FX00; 3018 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3019 ha->isp_ops = &qlafx00_isp_ops; 3020 ha->port_down_retry_count = 30; /* default value */ 3021 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3022 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3023 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3024 ha->mr.fw_hbt_en = 1; 3025 ha->mr.host_info_resend = false; 3026 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3027 } else if (IS_QLA27XX(ha)) { 3028 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3030 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3031 req_length = REQUEST_ENTRY_CNT_83XX; 3032 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3033 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3035 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3036 ha->gid_list_info_size = 8; 3037 ha->optrom_size = OPTROM_SIZE_83XX; 3038 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3039 ha->isp_ops = &qla27xx_isp_ops; 3040 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3041 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3042 ha->nvram_conf_off = ~0; 3043 ha->nvram_data_off = ~0; 3044 } else if (IS_QLA28XX(ha)) { 3045 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3046 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3047 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3048 req_length = REQUEST_ENTRY_CNT_24XX; 3049 rsp_length = RESPONSE_ENTRY_CNT_2300; 3050 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3051 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3052 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3053 ha->gid_list_info_size = 8; 3054 ha->optrom_size = OPTROM_SIZE_28XX; 3055 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3056 ha->isp_ops = &qla27xx_isp_ops; 3057 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3058 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3059 ha->nvram_conf_off = ~0; 3060 ha->nvram_data_off = ~0; 3061 } 3062 3063 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3064 "mbx_count=%d, req_length=%d, " 3065 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3066 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3067 "max_fibre_devices=%d.\n", 3068 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3069 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3070 ha->nvram_npiv_size, ha->max_fibre_devices); 3071 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3072 "isp_ops=%p, flash_conf_off=%d, " 3073 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3074 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3075 ha->nvram_conf_off, ha->nvram_data_off); 3076 3077 /* Configure PCI I/O space */ 3078 ret = ha->isp_ops->iospace_config(ha); 3079 if (ret) 3080 goto iospace_config_failed; 3081 3082 ql_log_pci(ql_log_info, pdev, 0x001d, 3083 "Found an ISP%04X irq %d iobase 0x%p.\n", 3084 pdev->device, pdev->irq, ha->iobase); 3085 mutex_init(&ha->vport_lock); 3086 mutex_init(&ha->mq_lock); 3087 init_completion(&ha->mbx_cmd_comp); 3088 complete(&ha->mbx_cmd_comp); 3089 init_completion(&ha->mbx_intr_comp); 3090 init_completion(&ha->dcbx_comp); 3091 init_completion(&ha->lb_portup_comp); 3092 3093 set_bit(0, (unsigned long *) ha->vp_idx_map); 3094 3095 qla2x00_config_dma_addressing(ha); 3096 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3097 "64 Bit addressing is %s.\n", 3098 ha->flags.enable_64bit_addressing ? "enable" : 3099 "disable"); 3100 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3101 if (ret) { 3102 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3103 "Failed to allocate memory for adapter, aborting.\n"); 3104 3105 goto probe_hw_failed; 3106 } 3107 3108 req->max_q_depth = MAX_Q_DEPTH; 3109 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3110 req->max_q_depth = ql2xmaxqdepth; 3111 3112 3113 base_vha = qla2x00_create_host(sht, ha); 3114 if (!base_vha) { 3115 ret = -ENOMEM; 3116 goto probe_hw_failed; 3117 } 3118 3119 pci_set_drvdata(pdev, base_vha); 3120 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3121 3122 host = base_vha->host; 3123 base_vha->req = req; 3124 if (IS_QLA2XXX_MIDTYPE(ha)) 3125 base_vha->mgmt_svr_loop_id = 3126 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3127 else 3128 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3129 base_vha->vp_idx; 3130 3131 /* Setup fcport template structure. */ 3132 ha->mr.fcport.vha = base_vha; 3133 ha->mr.fcport.port_type = FCT_UNKNOWN; 3134 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3135 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3136 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3137 ha->mr.fcport.scan_state = 1; 3138 3139 /* Set the SG table size based on ISP type */ 3140 if (!IS_FWI2_CAPABLE(ha)) { 3141 if (IS_QLA2100(ha)) 3142 host->sg_tablesize = 32; 3143 } else { 3144 if (!IS_QLA82XX(ha)) 3145 host->sg_tablesize = QLA_SG_ALL; 3146 } 3147 host->max_id = ha->max_fibre_devices; 3148 host->cmd_per_lun = 3; 3149 host->unique_id = host->host_no; 3150 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3151 host->max_cmd_len = 32; 3152 else 3153 host->max_cmd_len = MAX_CMDSZ; 3154 host->max_channel = MAX_BUSES - 1; 3155 /* Older HBAs support only 16-bit LUNs */ 3156 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3157 ql2xmaxlun > 0xffff) 3158 host->max_lun = 0xffff; 3159 else 3160 host->max_lun = ql2xmaxlun; 3161 host->transportt = qla2xxx_transport_template; 3162 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3163 3164 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3165 "max_id=%d this_id=%d " 3166 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3167 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3168 host->this_id, host->cmd_per_lun, host->unique_id, 3169 host->max_cmd_len, host->max_channel, host->max_lun, 3170 host->transportt, sht->vendor_id); 3171 3172 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3173 3174 /* Set up the irqs */ 3175 ret = qla2x00_request_irqs(ha, rsp); 3176 if (ret) 3177 goto probe_failed; 3178 3179 /* Alloc arrays of request and response ring ptrs */ 3180 ret = qla2x00_alloc_queues(ha, req, rsp); 3181 if (ret) { 3182 ql_log(ql_log_fatal, base_vha, 0x003d, 3183 "Failed to allocate memory for queue pointers..." 3184 "aborting.\n"); 3185 ret = -ENODEV; 3186 goto probe_failed; 3187 } 3188 3189 if (ha->mqenable) { 3190 /* number of hardware queues supported by blk/scsi-mq*/ 3191 host->nr_hw_queues = ha->max_qpairs; 3192 3193 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3194 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3195 } else { 3196 if (ql2xnvmeenable) { 3197 host->nr_hw_queues = ha->max_qpairs; 3198 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3199 "FC-NVMe support is enabled, HW queues=%d\n", 3200 host->nr_hw_queues); 3201 } else { 3202 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3203 "blk/scsi-mq disabled.\n"); 3204 } 3205 } 3206 3207 qlt_probe_one_stage1(base_vha, ha); 3208 3209 pci_save_state(pdev); 3210 3211 /* Assign back pointers */ 3212 rsp->req = req; 3213 req->rsp = rsp; 3214 3215 if (IS_QLAFX00(ha)) { 3216 ha->rsp_q_map[0] = rsp; 3217 ha->req_q_map[0] = req; 3218 set_bit(0, ha->req_qid_map); 3219 set_bit(0, ha->rsp_qid_map); 3220 } 3221 3222 /* FWI2-capable only. */ 3223 req->req_q_in = &ha->iobase->isp24.req_q_in; 3224 req->req_q_out = &ha->iobase->isp24.req_q_out; 3225 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3226 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3227 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3228 IS_QLA28XX(ha)) { 3229 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3230 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3231 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3232 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3233 } 3234 3235 if (IS_QLAFX00(ha)) { 3236 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3237 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3238 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3239 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3240 } 3241 3242 if (IS_P3P_TYPE(ha)) { 3243 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3244 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3245 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3246 } 3247 3248 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3249 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3250 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3251 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3252 "req->req_q_in=%p req->req_q_out=%p " 3253 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3254 req->req_q_in, req->req_q_out, 3255 rsp->rsp_q_in, rsp->rsp_q_out); 3256 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3257 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3258 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3259 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3260 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3261 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3262 3263 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3264 if (unlikely(!ha->wq)) { 3265 ret = -ENOMEM; 3266 goto probe_failed; 3267 } 3268 3269 if (ha->isp_ops->initialize_adapter(base_vha)) { 3270 ql_log(ql_log_fatal, base_vha, 0x00d6, 3271 "Failed to initialize adapter - Adapter flags %x.\n", 3272 base_vha->device_flags); 3273 3274 if (IS_QLA82XX(ha)) { 3275 qla82xx_idc_lock(ha); 3276 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3277 QLA8XXX_DEV_FAILED); 3278 qla82xx_idc_unlock(ha); 3279 ql_log(ql_log_fatal, base_vha, 0x00d7, 3280 "HW State: FAILED.\n"); 3281 } else if (IS_QLA8044(ha)) { 3282 qla8044_idc_lock(ha); 3283 qla8044_wr_direct(base_vha, 3284 QLA8044_CRB_DEV_STATE_INDEX, 3285 QLA8XXX_DEV_FAILED); 3286 qla8044_idc_unlock(ha); 3287 ql_log(ql_log_fatal, base_vha, 0x0150, 3288 "HW State: FAILED.\n"); 3289 } 3290 3291 ret = -ENODEV; 3292 goto probe_failed; 3293 } 3294 3295 if (IS_QLAFX00(ha)) 3296 host->can_queue = QLAFX00_MAX_CANQUEUE; 3297 else 3298 host->can_queue = req->num_outstanding_cmds - 10; 3299 3300 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3301 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3302 host->can_queue, base_vha->req, 3303 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3304 3305 if (ha->mqenable) { 3306 bool startit = false; 3307 3308 if (QLA_TGT_MODE_ENABLED()) 3309 startit = false; 3310 3311 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3312 startit = true; 3313 3314 /* Create start of day qpairs for Block MQ */ 3315 for (i = 0; i < ha->max_qpairs; i++) 3316 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3317 } 3318 3319 if (ha->flags.running_gold_fw) 3320 goto skip_dpc; 3321 3322 /* 3323 * Startup the kernel thread for this host adapter 3324 */ 3325 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3326 "%s_dpc", base_vha->host_str); 3327 if (IS_ERR(ha->dpc_thread)) { 3328 ql_log(ql_log_fatal, base_vha, 0x00ed, 3329 "Failed to start DPC thread.\n"); 3330 ret = PTR_ERR(ha->dpc_thread); 3331 ha->dpc_thread = NULL; 3332 goto probe_failed; 3333 } 3334 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3335 "DPC thread started successfully.\n"); 3336 3337 /* 3338 * If we're not coming up in initiator mode, we might sit for 3339 * a while without waking up the dpc thread, which leads to a 3340 * stuck process warning. So just kick the dpc once here and 3341 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3342 */ 3343 qla2xxx_wake_dpc(base_vha); 3344 3345 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3346 3347 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3348 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3349 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3350 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3351 3352 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3353 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3354 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3355 INIT_WORK(&ha->idc_state_handler, 3356 qla83xx_idc_state_handler_work); 3357 INIT_WORK(&ha->nic_core_unrecoverable, 3358 qla83xx_nic_core_unrecoverable_work); 3359 } 3360 3361 skip_dpc: 3362 list_add_tail(&base_vha->list, &ha->vp_list); 3363 base_vha->host->irq = ha->pdev->irq; 3364 3365 /* Initialized the timer */ 3366 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3367 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3368 "Started qla2x00_timer with " 3369 "interval=%d.\n", WATCH_INTERVAL); 3370 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3371 "Detected hba at address=%p.\n", 3372 ha); 3373 3374 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3375 if (ha->fw_attributes & BIT_4) { 3376 int prot = 0, guard; 3377 3378 base_vha->flags.difdix_supported = 1; 3379 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3380 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3381 if (ql2xenabledif == 1) 3382 prot = SHOST_DIX_TYPE0_PROTECTION; 3383 if (ql2xprotmask) 3384 scsi_host_set_prot(host, ql2xprotmask); 3385 else 3386 scsi_host_set_prot(host, 3387 prot | SHOST_DIF_TYPE1_PROTECTION 3388 | SHOST_DIF_TYPE2_PROTECTION 3389 | SHOST_DIF_TYPE3_PROTECTION 3390 | SHOST_DIX_TYPE1_PROTECTION 3391 | SHOST_DIX_TYPE2_PROTECTION 3392 | SHOST_DIX_TYPE3_PROTECTION); 3393 3394 guard = SHOST_DIX_GUARD_CRC; 3395 3396 if (IS_PI_IPGUARD_CAPABLE(ha) && 3397 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3398 guard |= SHOST_DIX_GUARD_IP; 3399 3400 if (ql2xprotguard) 3401 scsi_host_set_guard(host, ql2xprotguard); 3402 else 3403 scsi_host_set_guard(host, guard); 3404 } else 3405 base_vha->flags.difdix_supported = 0; 3406 } 3407 3408 ha->isp_ops->enable_intrs(ha); 3409 3410 if (IS_QLAFX00(ha)) { 3411 ret = qlafx00_fx_disc(base_vha, 3412 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3413 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3414 QLA_SG_ALL : 128; 3415 } 3416 3417 ret = scsi_add_host(host, &pdev->dev); 3418 if (ret) 3419 goto probe_failed; 3420 3421 base_vha->flags.init_done = 1; 3422 base_vha->flags.online = 1; 3423 ha->prev_minidump_failed = 0; 3424 3425 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3426 "Init done and hba is online.\n"); 3427 3428 if (qla_ini_mode_enabled(base_vha) || 3429 qla_dual_mode_enabled(base_vha)) 3430 scsi_scan_host(host); 3431 else 3432 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3433 "skipping scsi_scan_host() for non-initiator port\n"); 3434 3435 qla2x00_alloc_sysfs_attr(base_vha); 3436 3437 if (IS_QLAFX00(ha)) { 3438 ret = qlafx00_fx_disc(base_vha, 3439 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3440 3441 /* Register system information */ 3442 ret = qlafx00_fx_disc(base_vha, 3443 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3444 } 3445 3446 qla2x00_init_host_attr(base_vha); 3447 3448 qla2x00_dfs_setup(base_vha); 3449 3450 ql_log(ql_log_info, base_vha, 0x00fb, 3451 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3452 ql_log(ql_log_info, base_vha, 0x00fc, 3453 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3454 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3455 sizeof(pci_info)), 3456 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3457 base_vha->host_no, 3458 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3459 3460 qlt_add_target(ha, base_vha); 3461 3462 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3463 3464 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3465 return -ENODEV; 3466 3467 return 0; 3468 3469 probe_failed: 3470 if (base_vha->gnl.l) { 3471 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3472 base_vha->gnl.l, base_vha->gnl.ldma); 3473 base_vha->gnl.l = NULL; 3474 } 3475 3476 if (base_vha->timer_active) 3477 qla2x00_stop_timer(base_vha); 3478 base_vha->flags.online = 0; 3479 if (ha->dpc_thread) { 3480 struct task_struct *t = ha->dpc_thread; 3481 3482 ha->dpc_thread = NULL; 3483 kthread_stop(t); 3484 } 3485 3486 qla2x00_free_device(base_vha); 3487 scsi_host_put(base_vha->host); 3488 /* 3489 * Need to NULL out local req/rsp after 3490 * qla2x00_free_device => qla2x00_free_queues frees 3491 * what these are pointing to. Or else we'll 3492 * fall over below in qla2x00_free_req/rsp_que. 3493 */ 3494 req = NULL; 3495 rsp = NULL; 3496 3497 probe_hw_failed: 3498 qla2x00_mem_free(ha); 3499 qla2x00_free_req_que(ha, req); 3500 qla2x00_free_rsp_que(ha, rsp); 3501 qla2x00_clear_drv_active(ha); 3502 3503 iospace_config_failed: 3504 if (IS_P3P_TYPE(ha)) { 3505 if (!ha->nx_pcibase) 3506 iounmap((device_reg_t *)ha->nx_pcibase); 3507 if (!ql2xdbwr) 3508 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3509 } else { 3510 if (ha->iobase) 3511 iounmap(ha->iobase); 3512 if (ha->cregbase) 3513 iounmap(ha->cregbase); 3514 } 3515 pci_release_selected_regions(ha->pdev, ha->bars); 3516 kfree(ha); 3517 3518 disable_device: 3519 pci_disable_device(pdev); 3520 return ret; 3521 } 3522 3523 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3524 { 3525 scsi_qla_host_t *vp; 3526 unsigned long flags; 3527 struct qla_hw_data *ha; 3528 3529 if (!base_vha) 3530 return; 3531 3532 ha = base_vha->hw; 3533 3534 spin_lock_irqsave(&ha->vport_slock, flags); 3535 list_for_each_entry(vp, &ha->vp_list, list) 3536 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3537 3538 /* 3539 * Indicate device removal to prevent future board_disable 3540 * and wait until any pending board_disable has completed. 3541 */ 3542 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3543 spin_unlock_irqrestore(&ha->vport_slock, flags); 3544 } 3545 3546 static void 3547 qla2x00_shutdown(struct pci_dev *pdev) 3548 { 3549 scsi_qla_host_t *vha; 3550 struct qla_hw_data *ha; 3551 3552 vha = pci_get_drvdata(pdev); 3553 ha = vha->hw; 3554 3555 ql_log(ql_log_info, vha, 0xfffa, 3556 "Adapter shutdown\n"); 3557 3558 /* 3559 * Prevent future board_disable and wait 3560 * until any pending board_disable has completed. 3561 */ 3562 __qla_set_remove_flag(vha); 3563 cancel_work_sync(&ha->board_disable); 3564 3565 if (!atomic_read(&pdev->enable_cnt)) 3566 return; 3567 3568 /* Notify ISPFX00 firmware */ 3569 if (IS_QLAFX00(ha)) 3570 qlafx00_driver_shutdown(vha, 20); 3571 3572 /* Turn-off FCE trace */ 3573 if (ha->flags.fce_enabled) { 3574 qla2x00_disable_fce_trace(vha, NULL, NULL); 3575 ha->flags.fce_enabled = 0; 3576 } 3577 3578 /* Turn-off EFT trace */ 3579 if (ha->eft) 3580 qla2x00_disable_eft_trace(vha); 3581 3582 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3583 IS_QLA28XX(ha)) { 3584 if (ha->flags.fw_started) 3585 qla2x00_abort_isp_cleanup(vha); 3586 } else { 3587 /* Stop currently executing firmware. */ 3588 qla2x00_try_to_stop_firmware(vha); 3589 } 3590 3591 /* Disable timer */ 3592 if (vha->timer_active) 3593 qla2x00_stop_timer(vha); 3594 3595 /* Turn adapter off line */ 3596 vha->flags.online = 0; 3597 3598 /* turn-off interrupts on the card */ 3599 if (ha->interrupts_on) { 3600 vha->flags.init_done = 0; 3601 ha->isp_ops->disable_intrs(ha); 3602 } 3603 3604 qla2x00_free_irqs(vha); 3605 3606 qla2x00_free_fw_dump(ha); 3607 3608 pci_disable_device(pdev); 3609 ql_log(ql_log_info, vha, 0xfffe, 3610 "Adapter shutdown successfully.\n"); 3611 } 3612 3613 /* Deletes all the virtual ports for a given ha */ 3614 static void 3615 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3616 { 3617 scsi_qla_host_t *vha; 3618 unsigned long flags; 3619 3620 mutex_lock(&ha->vport_lock); 3621 while (ha->cur_vport_count) { 3622 spin_lock_irqsave(&ha->vport_slock, flags); 3623 3624 BUG_ON(base_vha->list.next == &ha->vp_list); 3625 /* This assumes first entry in ha->vp_list is always base vha */ 3626 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3627 scsi_host_get(vha->host); 3628 3629 spin_unlock_irqrestore(&ha->vport_slock, flags); 3630 mutex_unlock(&ha->vport_lock); 3631 3632 qla_nvme_delete(vha); 3633 3634 fc_vport_terminate(vha->fc_vport); 3635 scsi_host_put(vha->host); 3636 3637 mutex_lock(&ha->vport_lock); 3638 } 3639 mutex_unlock(&ha->vport_lock); 3640 } 3641 3642 /* Stops all deferred work threads */ 3643 static void 3644 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3645 { 3646 /* Cancel all work and destroy DPC workqueues */ 3647 if (ha->dpc_lp_wq) { 3648 cancel_work_sync(&ha->idc_aen); 3649 destroy_workqueue(ha->dpc_lp_wq); 3650 ha->dpc_lp_wq = NULL; 3651 } 3652 3653 if (ha->dpc_hp_wq) { 3654 cancel_work_sync(&ha->nic_core_reset); 3655 cancel_work_sync(&ha->idc_state_handler); 3656 cancel_work_sync(&ha->nic_core_unrecoverable); 3657 destroy_workqueue(ha->dpc_hp_wq); 3658 ha->dpc_hp_wq = NULL; 3659 } 3660 3661 /* Kill the kernel thread for this host */ 3662 if (ha->dpc_thread) { 3663 struct task_struct *t = ha->dpc_thread; 3664 3665 /* 3666 * qla2xxx_wake_dpc checks for ->dpc_thread 3667 * so we need to zero it out. 3668 */ 3669 ha->dpc_thread = NULL; 3670 kthread_stop(t); 3671 } 3672 } 3673 3674 static void 3675 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3676 { 3677 if (IS_QLA82XX(ha)) { 3678 3679 iounmap((device_reg_t *)ha->nx_pcibase); 3680 if (!ql2xdbwr) 3681 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3682 } else { 3683 if (ha->iobase) 3684 iounmap(ha->iobase); 3685 3686 if (ha->cregbase) 3687 iounmap(ha->cregbase); 3688 3689 if (ha->mqiobase) 3690 iounmap(ha->mqiobase); 3691 3692 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3693 ha->msixbase) 3694 iounmap(ha->msixbase); 3695 } 3696 } 3697 3698 static void 3699 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3700 { 3701 if (IS_QLA8044(ha)) { 3702 qla8044_idc_lock(ha); 3703 qla8044_clear_drv_active(ha); 3704 qla8044_idc_unlock(ha); 3705 } else if (IS_QLA82XX(ha)) { 3706 qla82xx_idc_lock(ha); 3707 qla82xx_clear_drv_active(ha); 3708 qla82xx_idc_unlock(ha); 3709 } 3710 } 3711 3712 static void 3713 qla2x00_remove_one(struct pci_dev *pdev) 3714 { 3715 scsi_qla_host_t *base_vha; 3716 struct qla_hw_data *ha; 3717 3718 base_vha = pci_get_drvdata(pdev); 3719 ha = base_vha->hw; 3720 ql_log(ql_log_info, base_vha, 0xb079, 3721 "Removing driver\n"); 3722 __qla_set_remove_flag(base_vha); 3723 cancel_work_sync(&ha->board_disable); 3724 3725 /* 3726 * If the PCI device is disabled then there was a PCI-disconnect and 3727 * qla2x00_disable_board_on_pci_error has taken care of most of the 3728 * resources. 3729 */ 3730 if (!atomic_read(&pdev->enable_cnt)) { 3731 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3732 base_vha->gnl.l, base_vha->gnl.ldma); 3733 base_vha->gnl.l = NULL; 3734 scsi_host_put(base_vha->host); 3735 kfree(ha); 3736 pci_set_drvdata(pdev, NULL); 3737 return; 3738 } 3739 qla2x00_wait_for_hba_ready(base_vha); 3740 3741 /* 3742 * if UNLOADING flag is already set, then continue unload, 3743 * where it was set first. 3744 */ 3745 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3746 return; 3747 3748 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3749 IS_QLA28XX(ha)) { 3750 if (ha->flags.fw_started) 3751 qla2x00_abort_isp_cleanup(base_vha); 3752 } else if (!IS_QLAFX00(ha)) { 3753 if (IS_QLA8031(ha)) { 3754 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3755 "Clearing fcoe driver presence.\n"); 3756 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3757 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3758 "Error while clearing DRV-Presence.\n"); 3759 } 3760 3761 qla2x00_try_to_stop_firmware(base_vha); 3762 } 3763 3764 qla2x00_wait_for_sess_deletion(base_vha); 3765 3766 qla_nvme_delete(base_vha); 3767 3768 dma_free_coherent(&ha->pdev->dev, 3769 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3770 3771 base_vha->gnl.l = NULL; 3772 3773 vfree(base_vha->scan.l); 3774 3775 if (IS_QLAFX00(ha)) 3776 qlafx00_driver_shutdown(base_vha, 20); 3777 3778 qla2x00_delete_all_vps(ha, base_vha); 3779 3780 qla2x00_dfs_remove(base_vha); 3781 3782 qla84xx_put_chip(base_vha); 3783 3784 /* Disable timer */ 3785 if (base_vha->timer_active) 3786 qla2x00_stop_timer(base_vha); 3787 3788 base_vha->flags.online = 0; 3789 3790 /* free DMA memory */ 3791 if (ha->exlogin_buf) 3792 qla2x00_free_exlogin_buffer(ha); 3793 3794 /* free DMA memory */ 3795 if (ha->exchoffld_buf) 3796 qla2x00_free_exchoffld_buffer(ha); 3797 3798 qla2x00_destroy_deferred_work(ha); 3799 3800 qlt_remove_target(ha, base_vha); 3801 3802 qla2x00_free_sysfs_attr(base_vha, true); 3803 3804 fc_remove_host(base_vha->host); 3805 qlt_remove_target_resources(ha); 3806 3807 scsi_remove_host(base_vha->host); 3808 3809 qla2x00_free_device(base_vha); 3810 3811 qla2x00_clear_drv_active(ha); 3812 3813 scsi_host_put(base_vha->host); 3814 3815 qla2x00_unmap_iobases(ha); 3816 3817 pci_release_selected_regions(ha->pdev, ha->bars); 3818 kfree(ha); 3819 3820 pci_disable_pcie_error_reporting(pdev); 3821 3822 pci_disable_device(pdev); 3823 } 3824 3825 static inline void 3826 qla24xx_free_purex_list(struct purex_list *list) 3827 { 3828 struct list_head *item, *next; 3829 ulong flags; 3830 3831 spin_lock_irqsave(&list->lock, flags); 3832 list_for_each_safe(item, next, &list->head) { 3833 list_del(item); 3834 kfree(list_entry(item, struct purex_item, list)); 3835 } 3836 spin_unlock_irqrestore(&list->lock, flags); 3837 } 3838 3839 static void 3840 qla2x00_free_device(scsi_qla_host_t *vha) 3841 { 3842 struct qla_hw_data *ha = vha->hw; 3843 3844 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3845 3846 /* Disable timer */ 3847 if (vha->timer_active) 3848 qla2x00_stop_timer(vha); 3849 3850 qla25xx_delete_queues(vha); 3851 vha->flags.online = 0; 3852 3853 /* turn-off interrupts on the card */ 3854 if (ha->interrupts_on) { 3855 vha->flags.init_done = 0; 3856 ha->isp_ops->disable_intrs(ha); 3857 } 3858 3859 qla2x00_free_fcports(vha); 3860 3861 qla2x00_free_irqs(vha); 3862 3863 /* Flush the work queue and remove it */ 3864 if (ha->wq) { 3865 flush_workqueue(ha->wq); 3866 destroy_workqueue(ha->wq); 3867 ha->wq = NULL; 3868 } 3869 3870 3871 qla24xx_free_purex_list(&vha->purex_list); 3872 3873 qla2x00_mem_free(ha); 3874 3875 qla82xx_md_free(vha); 3876 3877 qla2x00_free_queues(ha); 3878 } 3879 3880 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3881 { 3882 fc_port_t *fcport, *tfcport; 3883 3884 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3885 qla2x00_free_fcport(fcport); 3886 } 3887 3888 static inline void 3889 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3890 { 3891 int now; 3892 3893 if (!fcport->rport) 3894 return; 3895 3896 if (fcport->rport) { 3897 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3898 "%s %8phN. rport %p roles %x\n", 3899 __func__, fcport->port_name, fcport->rport, 3900 fcport->rport->roles); 3901 fc_remote_port_delete(fcport->rport); 3902 } 3903 qlt_do_generation_tick(vha, &now); 3904 } 3905 3906 /* 3907 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3908 * 3909 * Input: ha = adapter block pointer. fcport = port structure pointer. 3910 * 3911 * Return: None. 3912 * 3913 * Context: 3914 */ 3915 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3916 int do_login) 3917 { 3918 if (IS_QLAFX00(vha->hw)) { 3919 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3920 qla2x00_schedule_rport_del(vha, fcport); 3921 return; 3922 } 3923 3924 if (atomic_read(&fcport->state) == FCS_ONLINE && 3925 vha->vp_idx == fcport->vha->vp_idx) { 3926 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3927 qla2x00_schedule_rport_del(vha, fcport); 3928 } 3929 /* 3930 * We may need to retry the login, so don't change the state of the 3931 * port but do the retries. 3932 */ 3933 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3934 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3935 3936 if (!do_login) 3937 return; 3938 3939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3940 } 3941 3942 void 3943 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 3944 { 3945 fc_port_t *fcport; 3946 3947 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3948 "Mark all dev lost\n"); 3949 3950 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3951 fcport->scan_state = 0; 3952 qlt_schedule_sess_for_deletion(fcport); 3953 } 3954 } 3955 3956 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3957 { 3958 int i; 3959 3960 if (IS_FWI2_CAPABLE(ha)) 3961 return; 3962 3963 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3964 set_bit(i, ha->loop_id_map); 3965 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3966 set_bit(BROADCAST, ha->loop_id_map); 3967 } 3968 3969 /* 3970 * qla2x00_mem_alloc 3971 * Allocates adapter memory. 3972 * 3973 * Returns: 3974 * 0 = success. 3975 * !0 = failure. 3976 */ 3977 static int 3978 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3979 struct req_que **req, struct rsp_que **rsp) 3980 { 3981 char name[16]; 3982 3983 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3984 &ha->init_cb_dma, GFP_KERNEL); 3985 if (!ha->init_cb) 3986 goto fail; 3987 3988 if (qlt_mem_alloc(ha) < 0) 3989 goto fail_free_init_cb; 3990 3991 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3992 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3993 if (!ha->gid_list) 3994 goto fail_free_tgt_mem; 3995 3996 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3997 if (!ha->srb_mempool) 3998 goto fail_free_gid_list; 3999 4000 if (IS_P3P_TYPE(ha)) { 4001 /* Allocate cache for CT6 Ctx. */ 4002 if (!ctx_cachep) { 4003 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4004 sizeof(struct ct6_dsd), 0, 4005 SLAB_HWCACHE_ALIGN, NULL); 4006 if (!ctx_cachep) 4007 goto fail_free_srb_mempool; 4008 } 4009 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4010 ctx_cachep); 4011 if (!ha->ctx_mempool) 4012 goto fail_free_srb_mempool; 4013 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4014 "ctx_cachep=%p ctx_mempool=%p.\n", 4015 ctx_cachep, ha->ctx_mempool); 4016 } 4017 4018 /* Get memory for cached NVRAM */ 4019 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4020 if (!ha->nvram) 4021 goto fail_free_ctx_mempool; 4022 4023 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4024 ha->pdev->device); 4025 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4026 DMA_POOL_SIZE, 8, 0); 4027 if (!ha->s_dma_pool) 4028 goto fail_free_nvram; 4029 4030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4031 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4032 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4033 4034 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4035 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4036 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4037 if (!ha->dl_dma_pool) { 4038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4039 "Failed to allocate memory for dl_dma_pool.\n"); 4040 goto fail_s_dma_pool; 4041 } 4042 4043 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4044 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4045 if (!ha->fcp_cmnd_dma_pool) { 4046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4047 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4048 goto fail_dl_dma_pool; 4049 } 4050 4051 if (ql2xenabledif) { 4052 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4053 struct dsd_dma *dsd, *nxt; 4054 uint i; 4055 /* Creata a DMA pool of buffers for DIF bundling */ 4056 ha->dif_bundl_pool = dma_pool_create(name, 4057 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4058 if (!ha->dif_bundl_pool) { 4059 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4060 "%s: failed create dif_bundl_pool\n", 4061 __func__); 4062 goto fail_dif_bundl_dma_pool; 4063 } 4064 4065 INIT_LIST_HEAD(&ha->pool.good.head); 4066 INIT_LIST_HEAD(&ha->pool.unusable.head); 4067 ha->pool.good.count = 0; 4068 ha->pool.unusable.count = 0; 4069 for (i = 0; i < 128; i++) { 4070 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4071 if (!dsd) { 4072 ql_dbg_pci(ql_dbg_init, ha->pdev, 4073 0xe0ee, "%s: failed alloc dsd\n", 4074 __func__); 4075 return 1; 4076 } 4077 ha->dif_bundle_kallocs++; 4078 4079 dsd->dsd_addr = dma_pool_alloc( 4080 ha->dif_bundl_pool, GFP_ATOMIC, 4081 &dsd->dsd_list_dma); 4082 if (!dsd->dsd_addr) { 4083 ql_dbg_pci(ql_dbg_init, ha->pdev, 4084 0xe0ee, 4085 "%s: failed alloc ->dsd_addr\n", 4086 __func__); 4087 kfree(dsd); 4088 ha->dif_bundle_kallocs--; 4089 continue; 4090 } 4091 ha->dif_bundle_dma_allocs++; 4092 4093 /* 4094 * if DMA buffer crosses 4G boundary, 4095 * put it on bad list 4096 */ 4097 if (MSD(dsd->dsd_list_dma) ^ 4098 MSD(dsd->dsd_list_dma + bufsize)) { 4099 list_add_tail(&dsd->list, 4100 &ha->pool.unusable.head); 4101 ha->pool.unusable.count++; 4102 } else { 4103 list_add_tail(&dsd->list, 4104 &ha->pool.good.head); 4105 ha->pool.good.count++; 4106 } 4107 } 4108 4109 /* return the good ones back to the pool */ 4110 list_for_each_entry_safe(dsd, nxt, 4111 &ha->pool.good.head, list) { 4112 list_del(&dsd->list); 4113 dma_pool_free(ha->dif_bundl_pool, 4114 dsd->dsd_addr, dsd->dsd_list_dma); 4115 ha->dif_bundle_dma_allocs--; 4116 kfree(dsd); 4117 ha->dif_bundle_kallocs--; 4118 } 4119 4120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4121 "%s: dif dma pool (good=%u unusable=%u)\n", 4122 __func__, ha->pool.good.count, 4123 ha->pool.unusable.count); 4124 } 4125 4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4127 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4128 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4129 ha->dif_bundl_pool); 4130 } 4131 4132 /* Allocate memory for SNS commands */ 4133 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4134 /* Get consistent memory allocated for SNS commands */ 4135 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4136 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4137 if (!ha->sns_cmd) 4138 goto fail_dma_pool; 4139 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4140 "sns_cmd: %p.\n", ha->sns_cmd); 4141 } else { 4142 /* Get consistent memory allocated for MS IOCB */ 4143 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4144 &ha->ms_iocb_dma); 4145 if (!ha->ms_iocb) 4146 goto fail_dma_pool; 4147 /* Get consistent memory allocated for CT SNS commands */ 4148 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4149 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4150 if (!ha->ct_sns) 4151 goto fail_free_ms_iocb; 4152 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4153 "ms_iocb=%p ct_sns=%p.\n", 4154 ha->ms_iocb, ha->ct_sns); 4155 } 4156 4157 /* Allocate memory for request ring */ 4158 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4159 if (!*req) { 4160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4161 "Failed to allocate memory for req.\n"); 4162 goto fail_req; 4163 } 4164 (*req)->length = req_len; 4165 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4166 ((*req)->length + 1) * sizeof(request_t), 4167 &(*req)->dma, GFP_KERNEL); 4168 if (!(*req)->ring) { 4169 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4170 "Failed to allocate memory for req_ring.\n"); 4171 goto fail_req_ring; 4172 } 4173 /* Allocate memory for response ring */ 4174 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4175 if (!*rsp) { 4176 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4177 "Failed to allocate memory for rsp.\n"); 4178 goto fail_rsp; 4179 } 4180 (*rsp)->hw = ha; 4181 (*rsp)->length = rsp_len; 4182 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4183 ((*rsp)->length + 1) * sizeof(response_t), 4184 &(*rsp)->dma, GFP_KERNEL); 4185 if (!(*rsp)->ring) { 4186 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4187 "Failed to allocate memory for rsp_ring.\n"); 4188 goto fail_rsp_ring; 4189 } 4190 (*req)->rsp = *rsp; 4191 (*rsp)->req = *req; 4192 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4193 "req=%p req->length=%d req->ring=%p rsp=%p " 4194 "rsp->length=%d rsp->ring=%p.\n", 4195 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4196 (*rsp)->ring); 4197 /* Allocate memory for NVRAM data for vports */ 4198 if (ha->nvram_npiv_size) { 4199 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4200 sizeof(struct qla_npiv_entry), 4201 GFP_KERNEL); 4202 if (!ha->npiv_info) { 4203 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4204 "Failed to allocate memory for npiv_info.\n"); 4205 goto fail_npiv_info; 4206 } 4207 } else 4208 ha->npiv_info = NULL; 4209 4210 /* Get consistent memory allocated for EX-INIT-CB. */ 4211 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4212 IS_QLA28XX(ha)) { 4213 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4214 &ha->ex_init_cb_dma); 4215 if (!ha->ex_init_cb) 4216 goto fail_ex_init_cb; 4217 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4218 "ex_init_cb=%p.\n", ha->ex_init_cb); 4219 } 4220 4221 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4222 4223 /* Get consistent memory allocated for Async Port-Database. */ 4224 if (!IS_FWI2_CAPABLE(ha)) { 4225 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4226 &ha->async_pd_dma); 4227 if (!ha->async_pd) 4228 goto fail_async_pd; 4229 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4230 "async_pd=%p.\n", ha->async_pd); 4231 } 4232 4233 INIT_LIST_HEAD(&ha->vp_list); 4234 4235 /* Allocate memory for our loop_id bitmap */ 4236 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4237 sizeof(long), 4238 GFP_KERNEL); 4239 if (!ha->loop_id_map) 4240 goto fail_loop_id_map; 4241 else { 4242 qla2x00_set_reserved_loop_ids(ha); 4243 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4244 "loop_id_map=%p.\n", ha->loop_id_map); 4245 } 4246 4247 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4248 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4249 if (!ha->sfp_data) { 4250 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4251 "Unable to allocate memory for SFP read-data.\n"); 4252 goto fail_sfp_data; 4253 } 4254 4255 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4256 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4257 GFP_KERNEL); 4258 if (!ha->flt) { 4259 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4260 "Unable to allocate memory for FLT.\n"); 4261 goto fail_flt_buffer; 4262 } 4263 4264 return 0; 4265 4266 fail_flt_buffer: 4267 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4268 ha->sfp_data, ha->sfp_data_dma); 4269 fail_sfp_data: 4270 kfree(ha->loop_id_map); 4271 fail_loop_id_map: 4272 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4273 fail_async_pd: 4274 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4275 fail_ex_init_cb: 4276 kfree(ha->npiv_info); 4277 fail_npiv_info: 4278 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4279 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4280 (*rsp)->ring = NULL; 4281 (*rsp)->dma = 0; 4282 fail_rsp_ring: 4283 kfree(*rsp); 4284 *rsp = NULL; 4285 fail_rsp: 4286 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4287 sizeof(request_t), (*req)->ring, (*req)->dma); 4288 (*req)->ring = NULL; 4289 (*req)->dma = 0; 4290 fail_req_ring: 4291 kfree(*req); 4292 *req = NULL; 4293 fail_req: 4294 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4295 ha->ct_sns, ha->ct_sns_dma); 4296 ha->ct_sns = NULL; 4297 ha->ct_sns_dma = 0; 4298 fail_free_ms_iocb: 4299 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4300 ha->ms_iocb = NULL; 4301 ha->ms_iocb_dma = 0; 4302 4303 if (ha->sns_cmd) 4304 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4305 ha->sns_cmd, ha->sns_cmd_dma); 4306 fail_dma_pool: 4307 if (ql2xenabledif) { 4308 struct dsd_dma *dsd, *nxt; 4309 4310 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4311 list) { 4312 list_del(&dsd->list); 4313 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4314 dsd->dsd_list_dma); 4315 ha->dif_bundle_dma_allocs--; 4316 kfree(dsd); 4317 ha->dif_bundle_kallocs--; 4318 ha->pool.unusable.count--; 4319 } 4320 dma_pool_destroy(ha->dif_bundl_pool); 4321 ha->dif_bundl_pool = NULL; 4322 } 4323 4324 fail_dif_bundl_dma_pool: 4325 if (IS_QLA82XX(ha) || ql2xenabledif) { 4326 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4327 ha->fcp_cmnd_dma_pool = NULL; 4328 } 4329 fail_dl_dma_pool: 4330 if (IS_QLA82XX(ha) || ql2xenabledif) { 4331 dma_pool_destroy(ha->dl_dma_pool); 4332 ha->dl_dma_pool = NULL; 4333 } 4334 fail_s_dma_pool: 4335 dma_pool_destroy(ha->s_dma_pool); 4336 ha->s_dma_pool = NULL; 4337 fail_free_nvram: 4338 kfree(ha->nvram); 4339 ha->nvram = NULL; 4340 fail_free_ctx_mempool: 4341 mempool_destroy(ha->ctx_mempool); 4342 ha->ctx_mempool = NULL; 4343 fail_free_srb_mempool: 4344 mempool_destroy(ha->srb_mempool); 4345 ha->srb_mempool = NULL; 4346 fail_free_gid_list: 4347 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4348 ha->gid_list, 4349 ha->gid_list_dma); 4350 ha->gid_list = NULL; 4351 ha->gid_list_dma = 0; 4352 fail_free_tgt_mem: 4353 qlt_mem_free(ha); 4354 fail_free_init_cb: 4355 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4356 ha->init_cb_dma); 4357 ha->init_cb = NULL; 4358 ha->init_cb_dma = 0; 4359 fail: 4360 ql_log(ql_log_fatal, NULL, 0x0030, 4361 "Memory allocation failure.\n"); 4362 return -ENOMEM; 4363 } 4364 4365 int 4366 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4367 { 4368 int rval; 4369 uint16_t size, max_cnt, temp; 4370 struct qla_hw_data *ha = vha->hw; 4371 4372 /* Return if we don't need to alloacate any extended logins */ 4373 if (!ql2xexlogins) 4374 return QLA_SUCCESS; 4375 4376 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4377 return QLA_SUCCESS; 4378 4379 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4380 max_cnt = 0; 4381 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4382 if (rval != QLA_SUCCESS) { 4383 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4384 "Failed to get exlogin status.\n"); 4385 return rval; 4386 } 4387 4388 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4389 temp *= size; 4390 4391 if (temp != ha->exlogin_size) { 4392 qla2x00_free_exlogin_buffer(ha); 4393 ha->exlogin_size = temp; 4394 4395 ql_log(ql_log_info, vha, 0xd024, 4396 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4397 max_cnt, size, temp); 4398 4399 ql_log(ql_log_info, vha, 0xd025, 4400 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4401 4402 /* Get consistent memory for extended logins */ 4403 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4404 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4405 if (!ha->exlogin_buf) { 4406 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4407 "Failed to allocate memory for exlogin_buf_dma.\n"); 4408 return -ENOMEM; 4409 } 4410 } 4411 4412 /* Now configure the dma buffer */ 4413 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4414 if (rval) { 4415 ql_log(ql_log_fatal, vha, 0xd033, 4416 "Setup extended login buffer ****FAILED****.\n"); 4417 qla2x00_free_exlogin_buffer(ha); 4418 } 4419 4420 return rval; 4421 } 4422 4423 /* 4424 * qla2x00_free_exlogin_buffer 4425 * 4426 * Input: 4427 * ha = adapter block pointer 4428 */ 4429 void 4430 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4431 { 4432 if (ha->exlogin_buf) { 4433 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4434 ha->exlogin_buf, ha->exlogin_buf_dma); 4435 ha->exlogin_buf = NULL; 4436 ha->exlogin_size = 0; 4437 } 4438 } 4439 4440 static void 4441 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4442 { 4443 u32 temp; 4444 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4445 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4446 4447 if (max_cnt > vha->hw->max_exchg) 4448 max_cnt = vha->hw->max_exchg; 4449 4450 if (qla_ini_mode_enabled(vha)) { 4451 if (vha->ql2xiniexchg > max_cnt) 4452 vha->ql2xiniexchg = max_cnt; 4453 4454 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4455 *ret_cnt = vha->ql2xiniexchg; 4456 4457 } else if (qla_tgt_mode_enabled(vha)) { 4458 if (vha->ql2xexchoffld > max_cnt) { 4459 vha->ql2xexchoffld = max_cnt; 4460 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4461 } 4462 4463 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4464 *ret_cnt = vha->ql2xexchoffld; 4465 } else if (qla_dual_mode_enabled(vha)) { 4466 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4467 if (temp > max_cnt) { 4468 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4469 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4470 temp = max_cnt; 4471 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4472 } 4473 4474 if (temp > FW_DEF_EXCHANGES_CNT) 4475 *ret_cnt = temp; 4476 } 4477 } 4478 4479 int 4480 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4481 { 4482 int rval; 4483 u16 size, max_cnt; 4484 u32 actual_cnt, totsz; 4485 struct qla_hw_data *ha = vha->hw; 4486 4487 if (!ha->flags.exchoffld_enabled) 4488 return QLA_SUCCESS; 4489 4490 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4491 return QLA_SUCCESS; 4492 4493 max_cnt = 0; 4494 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4495 if (rval != QLA_SUCCESS) { 4496 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4497 "Failed to get exlogin status.\n"); 4498 return rval; 4499 } 4500 4501 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4502 ql_log(ql_log_info, vha, 0xd014, 4503 "Actual exchange offload count: %d.\n", actual_cnt); 4504 4505 totsz = actual_cnt * size; 4506 4507 if (totsz != ha->exchoffld_size) { 4508 qla2x00_free_exchoffld_buffer(ha); 4509 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4510 ha->exchoffld_size = 0; 4511 ha->flags.exchoffld_enabled = 0; 4512 return QLA_SUCCESS; 4513 } 4514 4515 ha->exchoffld_size = totsz; 4516 4517 ql_log(ql_log_info, vha, 0xd016, 4518 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4519 max_cnt, actual_cnt, size, totsz); 4520 4521 ql_log(ql_log_info, vha, 0xd017, 4522 "Exchange Buffers requested size = 0x%x\n", 4523 ha->exchoffld_size); 4524 4525 /* Get consistent memory for extended logins */ 4526 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4527 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4528 if (!ha->exchoffld_buf) { 4529 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4530 "Failed to allocate memory for Exchange Offload.\n"); 4531 4532 if (ha->max_exchg > 4533 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4534 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4535 } else if (ha->max_exchg > 4536 (FW_DEF_EXCHANGES_CNT + 512)) { 4537 ha->max_exchg -= 512; 4538 } else { 4539 ha->flags.exchoffld_enabled = 0; 4540 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4541 "Disabling Exchange offload due to lack of memory\n"); 4542 } 4543 ha->exchoffld_size = 0; 4544 4545 return -ENOMEM; 4546 } 4547 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4548 /* pathological case */ 4549 qla2x00_free_exchoffld_buffer(ha); 4550 ha->exchoffld_size = 0; 4551 ha->flags.exchoffld_enabled = 0; 4552 ql_log(ql_log_info, vha, 0xd016, 4553 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4554 ha->exchoffld_size, actual_cnt, size, totsz); 4555 return 0; 4556 } 4557 4558 /* Now configure the dma buffer */ 4559 rval = qla_set_exchoffld_mem_cfg(vha); 4560 if (rval) { 4561 ql_log(ql_log_fatal, vha, 0xd02e, 4562 "Setup exchange offload buffer ****FAILED****.\n"); 4563 qla2x00_free_exchoffld_buffer(ha); 4564 } else { 4565 /* re-adjust number of target exchange */ 4566 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4567 4568 if (qla_ini_mode_enabled(vha)) 4569 icb->exchange_count = 0; 4570 else 4571 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4572 } 4573 4574 return rval; 4575 } 4576 4577 /* 4578 * qla2x00_free_exchoffld_buffer 4579 * 4580 * Input: 4581 * ha = adapter block pointer 4582 */ 4583 void 4584 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4585 { 4586 if (ha->exchoffld_buf) { 4587 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4588 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4589 ha->exchoffld_buf = NULL; 4590 ha->exchoffld_size = 0; 4591 } 4592 } 4593 4594 /* 4595 * qla2x00_free_fw_dump 4596 * Frees fw dump stuff. 4597 * 4598 * Input: 4599 * ha = adapter block pointer 4600 */ 4601 static void 4602 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4603 { 4604 struct fwdt *fwdt = ha->fwdt; 4605 uint j; 4606 4607 if (ha->fce) 4608 dma_free_coherent(&ha->pdev->dev, 4609 FCE_SIZE, ha->fce, ha->fce_dma); 4610 4611 if (ha->eft) 4612 dma_free_coherent(&ha->pdev->dev, 4613 EFT_SIZE, ha->eft, ha->eft_dma); 4614 4615 if (ha->fw_dump) 4616 vfree(ha->fw_dump); 4617 4618 ha->fce = NULL; 4619 ha->fce_dma = 0; 4620 ha->flags.fce_enabled = 0; 4621 ha->eft = NULL; 4622 ha->eft_dma = 0; 4623 ha->fw_dumped = false; 4624 ha->fw_dump_cap_flags = 0; 4625 ha->fw_dump_reading = 0; 4626 ha->fw_dump = NULL; 4627 ha->fw_dump_len = 0; 4628 4629 for (j = 0; j < 2; j++, fwdt++) { 4630 if (fwdt->template) 4631 vfree(fwdt->template); 4632 fwdt->template = NULL; 4633 fwdt->length = 0; 4634 } 4635 } 4636 4637 /* 4638 * qla2x00_mem_free 4639 * Frees all adapter allocated memory. 4640 * 4641 * Input: 4642 * ha = adapter block pointer. 4643 */ 4644 static void 4645 qla2x00_mem_free(struct qla_hw_data *ha) 4646 { 4647 qla2x00_free_fw_dump(ha); 4648 4649 if (ha->mctp_dump) 4650 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4651 ha->mctp_dump_dma); 4652 ha->mctp_dump = NULL; 4653 4654 mempool_destroy(ha->srb_mempool); 4655 ha->srb_mempool = NULL; 4656 4657 if (ha->dcbx_tlv) 4658 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4659 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4660 ha->dcbx_tlv = NULL; 4661 4662 if (ha->xgmac_data) 4663 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4664 ha->xgmac_data, ha->xgmac_data_dma); 4665 ha->xgmac_data = NULL; 4666 4667 if (ha->sns_cmd) 4668 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4669 ha->sns_cmd, ha->sns_cmd_dma); 4670 ha->sns_cmd = NULL; 4671 ha->sns_cmd_dma = 0; 4672 4673 if (ha->ct_sns) 4674 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4675 ha->ct_sns, ha->ct_sns_dma); 4676 ha->ct_sns = NULL; 4677 ha->ct_sns_dma = 0; 4678 4679 if (ha->sfp_data) 4680 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4681 ha->sfp_data_dma); 4682 ha->sfp_data = NULL; 4683 4684 if (ha->flt) 4685 dma_free_coherent(&ha->pdev->dev, 4686 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4687 ha->flt, ha->flt_dma); 4688 ha->flt = NULL; 4689 ha->flt_dma = 0; 4690 4691 if (ha->ms_iocb) 4692 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4693 ha->ms_iocb = NULL; 4694 ha->ms_iocb_dma = 0; 4695 4696 if (ha->ex_init_cb) 4697 dma_pool_free(ha->s_dma_pool, 4698 ha->ex_init_cb, ha->ex_init_cb_dma); 4699 ha->ex_init_cb = NULL; 4700 ha->ex_init_cb_dma = 0; 4701 4702 if (ha->async_pd) 4703 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4704 ha->async_pd = NULL; 4705 ha->async_pd_dma = 0; 4706 4707 dma_pool_destroy(ha->s_dma_pool); 4708 ha->s_dma_pool = NULL; 4709 4710 if (ha->gid_list) 4711 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4712 ha->gid_list, ha->gid_list_dma); 4713 ha->gid_list = NULL; 4714 ha->gid_list_dma = 0; 4715 4716 if (IS_QLA82XX(ha)) { 4717 if (!list_empty(&ha->gbl_dsd_list)) { 4718 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4719 4720 /* clean up allocated prev pool */ 4721 list_for_each_entry_safe(dsd_ptr, 4722 tdsd_ptr, &ha->gbl_dsd_list, list) { 4723 dma_pool_free(ha->dl_dma_pool, 4724 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4725 list_del(&dsd_ptr->list); 4726 kfree(dsd_ptr); 4727 } 4728 } 4729 } 4730 4731 dma_pool_destroy(ha->dl_dma_pool); 4732 ha->dl_dma_pool = NULL; 4733 4734 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4735 ha->fcp_cmnd_dma_pool = NULL; 4736 4737 mempool_destroy(ha->ctx_mempool); 4738 ha->ctx_mempool = NULL; 4739 4740 if (ql2xenabledif && ha->dif_bundl_pool) { 4741 struct dsd_dma *dsd, *nxt; 4742 4743 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4744 list) { 4745 list_del(&dsd->list); 4746 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4747 dsd->dsd_list_dma); 4748 ha->dif_bundle_dma_allocs--; 4749 kfree(dsd); 4750 ha->dif_bundle_kallocs--; 4751 ha->pool.unusable.count--; 4752 } 4753 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4754 list_del(&dsd->list); 4755 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4756 dsd->dsd_list_dma); 4757 ha->dif_bundle_dma_allocs--; 4758 kfree(dsd); 4759 ha->dif_bundle_kallocs--; 4760 } 4761 } 4762 4763 dma_pool_destroy(ha->dif_bundl_pool); 4764 ha->dif_bundl_pool = NULL; 4765 4766 qlt_mem_free(ha); 4767 4768 if (ha->init_cb) 4769 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4770 ha->init_cb, ha->init_cb_dma); 4771 ha->init_cb = NULL; 4772 ha->init_cb_dma = 0; 4773 4774 vfree(ha->optrom_buffer); 4775 ha->optrom_buffer = NULL; 4776 kfree(ha->nvram); 4777 ha->nvram = NULL; 4778 kfree(ha->npiv_info); 4779 ha->npiv_info = NULL; 4780 kfree(ha->swl); 4781 ha->swl = NULL; 4782 kfree(ha->loop_id_map); 4783 ha->loop_id_map = NULL; 4784 } 4785 4786 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4787 struct qla_hw_data *ha) 4788 { 4789 struct Scsi_Host *host; 4790 struct scsi_qla_host *vha = NULL; 4791 4792 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4793 if (!host) { 4794 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4795 "Failed to allocate host from the scsi layer, aborting.\n"); 4796 return NULL; 4797 } 4798 4799 /* Clear our data area */ 4800 vha = shost_priv(host); 4801 memset(vha, 0, sizeof(scsi_qla_host_t)); 4802 4803 vha->host = host; 4804 vha->host_no = host->host_no; 4805 vha->hw = ha; 4806 4807 vha->qlini_mode = ql2x_ini_mode; 4808 vha->ql2xexchoffld = ql2xexchoffld; 4809 vha->ql2xiniexchg = ql2xiniexchg; 4810 4811 INIT_LIST_HEAD(&vha->vp_fcports); 4812 INIT_LIST_HEAD(&vha->work_list); 4813 INIT_LIST_HEAD(&vha->list); 4814 INIT_LIST_HEAD(&vha->qla_cmd_list); 4815 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4816 INIT_LIST_HEAD(&vha->logo_list); 4817 INIT_LIST_HEAD(&vha->plogi_ack_list); 4818 INIT_LIST_HEAD(&vha->qp_list); 4819 INIT_LIST_HEAD(&vha->gnl.fcports); 4820 INIT_LIST_HEAD(&vha->gpnid_list); 4821 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4822 4823 INIT_LIST_HEAD(&vha->purex_list.head); 4824 spin_lock_init(&vha->purex_list.lock); 4825 4826 spin_lock_init(&vha->work_lock); 4827 spin_lock_init(&vha->cmd_list_lock); 4828 init_waitqueue_head(&vha->fcport_waitQ); 4829 init_waitqueue_head(&vha->vref_waitq); 4830 4831 vha->gnl.size = sizeof(struct get_name_list_extended) * 4832 (ha->max_loop_id + 1); 4833 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4834 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4835 if (!vha->gnl.l) { 4836 ql_log(ql_log_fatal, vha, 0xd04a, 4837 "Alloc failed for name list.\n"); 4838 scsi_host_put(vha->host); 4839 return NULL; 4840 } 4841 4842 /* todo: what about ext login? */ 4843 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4844 vha->scan.l = vmalloc(vha->scan.size); 4845 if (!vha->scan.l) { 4846 ql_log(ql_log_fatal, vha, 0xd04a, 4847 "Alloc failed for scan database.\n"); 4848 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4849 vha->gnl.l, vha->gnl.ldma); 4850 vha->gnl.l = NULL; 4851 scsi_host_put(vha->host); 4852 return NULL; 4853 } 4854 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4855 4856 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4857 ql_dbg(ql_dbg_init, vha, 0x0041, 4858 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4859 vha->host, vha->hw, vha, 4860 dev_name(&(ha->pdev->dev))); 4861 4862 return vha; 4863 } 4864 4865 struct qla_work_evt * 4866 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4867 { 4868 struct qla_work_evt *e; 4869 uint8_t bail; 4870 4871 if (test_bit(UNLOADING, &vha->dpc_flags)) 4872 return NULL; 4873 4874 QLA_VHA_MARK_BUSY(vha, bail); 4875 if (bail) 4876 return NULL; 4877 4878 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4879 if (!e) { 4880 QLA_VHA_MARK_NOT_BUSY(vha); 4881 return NULL; 4882 } 4883 4884 INIT_LIST_HEAD(&e->list); 4885 e->type = type; 4886 e->flags = QLA_EVT_FLAG_FREE; 4887 return e; 4888 } 4889 4890 int 4891 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4892 { 4893 unsigned long flags; 4894 bool q = false; 4895 4896 spin_lock_irqsave(&vha->work_lock, flags); 4897 list_add_tail(&e->list, &vha->work_list); 4898 4899 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4900 q = true; 4901 4902 spin_unlock_irqrestore(&vha->work_lock, flags); 4903 4904 if (q) 4905 queue_work(vha->hw->wq, &vha->iocb_work); 4906 4907 return QLA_SUCCESS; 4908 } 4909 4910 int 4911 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4912 u32 data) 4913 { 4914 struct qla_work_evt *e; 4915 4916 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4917 if (!e) 4918 return QLA_FUNCTION_FAILED; 4919 4920 e->u.aen.code = code; 4921 e->u.aen.data = data; 4922 return qla2x00_post_work(vha, e); 4923 } 4924 4925 int 4926 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4927 { 4928 struct qla_work_evt *e; 4929 4930 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4931 if (!e) 4932 return QLA_FUNCTION_FAILED; 4933 4934 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4935 return qla2x00_post_work(vha, e); 4936 } 4937 4938 #define qla2x00_post_async_work(name, type) \ 4939 int qla2x00_post_async_##name##_work( \ 4940 struct scsi_qla_host *vha, \ 4941 fc_port_t *fcport, uint16_t *data) \ 4942 { \ 4943 struct qla_work_evt *e; \ 4944 \ 4945 e = qla2x00_alloc_work(vha, type); \ 4946 if (!e) \ 4947 return QLA_FUNCTION_FAILED; \ 4948 \ 4949 e->u.logio.fcport = fcport; \ 4950 if (data) { \ 4951 e->u.logio.data[0] = data[0]; \ 4952 e->u.logio.data[1] = data[1]; \ 4953 } \ 4954 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4955 return qla2x00_post_work(vha, e); \ 4956 } 4957 4958 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4959 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4960 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4961 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4962 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4963 4964 int 4965 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4966 { 4967 struct qla_work_evt *e; 4968 4969 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4970 if (!e) 4971 return QLA_FUNCTION_FAILED; 4972 4973 e->u.uevent.code = code; 4974 return qla2x00_post_work(vha, e); 4975 } 4976 4977 static void 4978 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4979 { 4980 char event_string[40]; 4981 char *envp[] = { event_string, NULL }; 4982 4983 switch (code) { 4984 case QLA_UEVENT_CODE_FW_DUMP: 4985 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4986 vha->host_no); 4987 break; 4988 default: 4989 /* do nothing */ 4990 break; 4991 } 4992 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4993 } 4994 4995 int 4996 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4997 uint32_t *data, int cnt) 4998 { 4999 struct qla_work_evt *e; 5000 5001 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5002 if (!e) 5003 return QLA_FUNCTION_FAILED; 5004 5005 e->u.aenfx.evtcode = evtcode; 5006 e->u.aenfx.count = cnt; 5007 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5008 return qla2x00_post_work(vha, e); 5009 } 5010 5011 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5012 { 5013 unsigned long flags; 5014 5015 if (IS_SW_RESV_ADDR(fcport->d_id)) 5016 return; 5017 5018 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5019 if (fcport->disc_state == DSC_UPD_FCPORT) { 5020 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5021 return; 5022 } 5023 fcport->jiffies_at_registration = jiffies; 5024 fcport->sec_since_registration = 0; 5025 fcport->next_disc_state = DSC_DELETED; 5026 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5027 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5028 5029 queue_work(system_unbound_wq, &fcport->reg_work); 5030 } 5031 5032 static 5033 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5034 { 5035 unsigned long flags; 5036 fc_port_t *fcport = NULL, *tfcp; 5037 struct qlt_plogi_ack_t *pla = 5038 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5039 uint8_t free_fcport = 0; 5040 5041 ql_dbg(ql_dbg_disc, vha, 0xffff, 5042 "%s %d %8phC enter\n", 5043 __func__, __LINE__, e->u.new_sess.port_name); 5044 5045 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5046 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5047 if (fcport) { 5048 fcport->d_id = e->u.new_sess.id; 5049 if (pla) { 5050 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5051 memcpy(fcport->node_name, 5052 pla->iocb.u.isp24.u.plogi.node_name, 5053 WWN_SIZE); 5054 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5055 /* we took an extra ref_count to prevent PLOGI ACK when 5056 * fcport/sess has not been created. 5057 */ 5058 pla->ref_count--; 5059 } 5060 } else { 5061 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5062 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5063 if (fcport) { 5064 fcport->d_id = e->u.new_sess.id; 5065 fcport->flags |= FCF_FABRIC_DEVICE; 5066 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5067 5068 memcpy(fcport->port_name, e->u.new_sess.port_name, 5069 WWN_SIZE); 5070 5071 fcport->fc4_type = e->u.new_sess.fc4_type; 5072 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5073 fcport->fc4_type = FS_FC4TYPE_FCP; 5074 fcport->n2n_flag = 1; 5075 if (vha->flags.nvme_enabled) 5076 fcport->fc4_type |= FS_FC4TYPE_NVME; 5077 } 5078 5079 } else { 5080 ql_dbg(ql_dbg_disc, vha, 0xffff, 5081 "%s %8phC mem alloc fail.\n", 5082 __func__, e->u.new_sess.port_name); 5083 5084 if (pla) { 5085 list_del(&pla->list); 5086 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5087 } 5088 return; 5089 } 5090 5091 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5092 /* search again to make sure no one else got ahead */ 5093 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5094 e->u.new_sess.port_name, 1); 5095 if (tfcp) { 5096 /* should rarily happen */ 5097 ql_dbg(ql_dbg_disc, vha, 0xffff, 5098 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5099 __func__, tfcp->port_name, tfcp->disc_state, 5100 tfcp->fw_login_state); 5101 5102 free_fcport = 1; 5103 } else { 5104 list_add_tail(&fcport->list, &vha->vp_fcports); 5105 5106 } 5107 if (pla) { 5108 qlt_plogi_ack_link(vha, pla, fcport, 5109 QLT_PLOGI_LINK_SAME_WWN); 5110 pla->ref_count--; 5111 } 5112 } 5113 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5114 5115 if (fcport) { 5116 fcport->id_changed = 1; 5117 fcport->scan_state = QLA_FCPORT_FOUND; 5118 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5119 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5120 5121 if (pla) { 5122 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5123 u16 wd3_lo; 5124 5125 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5126 fcport->local = 0; 5127 fcport->loop_id = 5128 le16_to_cpu( 5129 pla->iocb.u.isp24.nport_handle); 5130 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5131 wd3_lo = 5132 le16_to_cpu( 5133 pla->iocb.u.isp24.u.prli.wd3_lo); 5134 5135 if (wd3_lo & BIT_7) 5136 fcport->conf_compl_supported = 1; 5137 5138 if ((wd3_lo & BIT_4) == 0) 5139 fcport->port_type = FCT_INITIATOR; 5140 else 5141 fcport->port_type = FCT_TARGET; 5142 } 5143 qlt_plogi_ack_unref(vha, pla); 5144 } else { 5145 fc_port_t *dfcp = NULL; 5146 5147 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5148 tfcp = qla2x00_find_fcport_by_nportid(vha, 5149 &e->u.new_sess.id, 1); 5150 if (tfcp && (tfcp != fcport)) { 5151 /* 5152 * We have a conflict fcport with same NportID. 5153 */ 5154 ql_dbg(ql_dbg_disc, vha, 0xffff, 5155 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5156 __func__, tfcp->port_name, tfcp->disc_state, 5157 tfcp->fw_login_state); 5158 5159 switch (tfcp->disc_state) { 5160 case DSC_DELETED: 5161 break; 5162 case DSC_DELETE_PEND: 5163 fcport->login_pause = 1; 5164 tfcp->conflict = fcport; 5165 break; 5166 default: 5167 fcport->login_pause = 1; 5168 tfcp->conflict = fcport; 5169 dfcp = tfcp; 5170 break; 5171 } 5172 } 5173 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5174 if (dfcp) 5175 qlt_schedule_sess_for_deletion(tfcp); 5176 5177 if (N2N_TOPO(vha->hw)) { 5178 fcport->flags &= ~FCF_FABRIC_DEVICE; 5179 fcport->keep_nport_handle = 1; 5180 if (vha->flags.nvme_enabled) { 5181 fcport->fc4_type = 5182 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5183 fcport->n2n_flag = 1; 5184 } 5185 fcport->fw_login_state = 0; 5186 5187 schedule_delayed_work(&vha->scan.scan_work, 5); 5188 } else { 5189 qla24xx_fcport_handle_login(vha, fcport); 5190 } 5191 } 5192 } 5193 5194 if (free_fcport) { 5195 qla2x00_free_fcport(fcport); 5196 if (pla) { 5197 list_del(&pla->list); 5198 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5199 } 5200 } 5201 } 5202 5203 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5204 { 5205 struct srb *sp = e->u.iosb.sp; 5206 int rval; 5207 5208 rval = qla2x00_start_sp(sp); 5209 if (rval != QLA_SUCCESS) { 5210 ql_dbg(ql_dbg_disc, vha, 0x2043, 5211 "%s: %s: Re-issue IOCB failed (%d).\n", 5212 __func__, sp->name, rval); 5213 qla24xx_sp_unmap(vha, sp); 5214 } 5215 } 5216 5217 void 5218 qla2x00_do_work(struct scsi_qla_host *vha) 5219 { 5220 struct qla_work_evt *e, *tmp; 5221 unsigned long flags; 5222 LIST_HEAD(work); 5223 int rc; 5224 5225 spin_lock_irqsave(&vha->work_lock, flags); 5226 list_splice_init(&vha->work_list, &work); 5227 spin_unlock_irqrestore(&vha->work_lock, flags); 5228 5229 list_for_each_entry_safe(e, tmp, &work, list) { 5230 rc = QLA_SUCCESS; 5231 switch (e->type) { 5232 case QLA_EVT_AEN: 5233 fc_host_post_event(vha->host, fc_get_event_number(), 5234 e->u.aen.code, e->u.aen.data); 5235 break; 5236 case QLA_EVT_IDC_ACK: 5237 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5238 break; 5239 case QLA_EVT_ASYNC_LOGIN: 5240 qla2x00_async_login(vha, e->u.logio.fcport, 5241 e->u.logio.data); 5242 break; 5243 case QLA_EVT_ASYNC_LOGOUT: 5244 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5245 break; 5246 case QLA_EVT_ASYNC_ADISC: 5247 qla2x00_async_adisc(vha, e->u.logio.fcport, 5248 e->u.logio.data); 5249 break; 5250 case QLA_EVT_UEVENT: 5251 qla2x00_uevent_emit(vha, e->u.uevent.code); 5252 break; 5253 case QLA_EVT_AENFX: 5254 qlafx00_process_aen(vha, e); 5255 break; 5256 case QLA_EVT_GPNID: 5257 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5258 break; 5259 case QLA_EVT_UNMAP: 5260 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5261 break; 5262 case QLA_EVT_RELOGIN: 5263 qla2x00_relogin(vha); 5264 break; 5265 case QLA_EVT_NEW_SESS: 5266 qla24xx_create_new_sess(vha, e); 5267 break; 5268 case QLA_EVT_GPDB: 5269 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5270 e->u.fcport.opt); 5271 break; 5272 case QLA_EVT_PRLI: 5273 qla24xx_async_prli(vha, e->u.fcport.fcport); 5274 break; 5275 case QLA_EVT_GPSC: 5276 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5277 break; 5278 case QLA_EVT_GNL: 5279 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5280 break; 5281 case QLA_EVT_NACK: 5282 qla24xx_do_nack_work(vha, e); 5283 break; 5284 case QLA_EVT_ASYNC_PRLO: 5285 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5286 break; 5287 case QLA_EVT_ASYNC_PRLO_DONE: 5288 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5289 e->u.logio.data); 5290 break; 5291 case QLA_EVT_GPNFT: 5292 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5293 e->u.gpnft.sp); 5294 break; 5295 case QLA_EVT_GPNFT_DONE: 5296 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5297 break; 5298 case QLA_EVT_GNNFT_DONE: 5299 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5300 break; 5301 case QLA_EVT_GNNID: 5302 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5303 break; 5304 case QLA_EVT_GFPNID: 5305 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5306 break; 5307 case QLA_EVT_SP_RETRY: 5308 qla_sp_retry(vha, e); 5309 break; 5310 case QLA_EVT_IIDMA: 5311 qla_do_iidma_work(vha, e->u.fcport.fcport); 5312 break; 5313 case QLA_EVT_ELS_PLOGI: 5314 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5315 e->u.fcport.fcport, false); 5316 break; 5317 } 5318 5319 if (rc == EAGAIN) { 5320 /* put 'work' at head of 'vha->work_list' */ 5321 spin_lock_irqsave(&vha->work_lock, flags); 5322 list_splice(&work, &vha->work_list); 5323 spin_unlock_irqrestore(&vha->work_lock, flags); 5324 break; 5325 } 5326 list_del_init(&e->list); 5327 if (e->flags & QLA_EVT_FLAG_FREE) 5328 kfree(e); 5329 5330 /* For each work completed decrement vha ref count */ 5331 QLA_VHA_MARK_NOT_BUSY(vha); 5332 } 5333 } 5334 5335 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5336 { 5337 struct qla_work_evt *e; 5338 5339 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5340 5341 if (!e) { 5342 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5343 return QLA_FUNCTION_FAILED; 5344 } 5345 5346 return qla2x00_post_work(vha, e); 5347 } 5348 5349 /* Relogins all the fcports of a vport 5350 * Context: dpc thread 5351 */ 5352 void qla2x00_relogin(struct scsi_qla_host *vha) 5353 { 5354 fc_port_t *fcport; 5355 int status, relogin_needed = 0; 5356 struct event_arg ea; 5357 5358 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5359 /* 5360 * If the port is not ONLINE then try to login 5361 * to it if we haven't run out of retries. 5362 */ 5363 if (atomic_read(&fcport->state) != FCS_ONLINE && 5364 fcport->login_retry) { 5365 if (fcport->scan_state != QLA_FCPORT_FOUND || 5366 fcport->disc_state == DSC_LOGIN_COMPLETE) 5367 continue; 5368 5369 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5370 fcport->disc_state == DSC_DELETE_PEND) { 5371 relogin_needed = 1; 5372 } else { 5373 if (vha->hw->current_topology != ISP_CFG_NL) { 5374 memset(&ea, 0, sizeof(ea)); 5375 ea.fcport = fcport; 5376 qla24xx_handle_relogin_event(vha, &ea); 5377 } else if (vha->hw->current_topology == 5378 ISP_CFG_NL) { 5379 fcport->login_retry--; 5380 status = 5381 qla2x00_local_device_login(vha, 5382 fcport); 5383 if (status == QLA_SUCCESS) { 5384 fcport->old_loop_id = 5385 fcport->loop_id; 5386 ql_dbg(ql_dbg_disc, vha, 0x2003, 5387 "Port login OK: logged in ID 0x%x.\n", 5388 fcport->loop_id); 5389 qla2x00_update_fcport 5390 (vha, fcport); 5391 } else if (status == 1) { 5392 set_bit(RELOGIN_NEEDED, 5393 &vha->dpc_flags); 5394 /* retry the login again */ 5395 ql_dbg(ql_dbg_disc, vha, 0x2007, 5396 "Retrying %d login again loop_id 0x%x.\n", 5397 fcport->login_retry, 5398 fcport->loop_id); 5399 } else { 5400 fcport->login_retry = 0; 5401 } 5402 5403 if (fcport->login_retry == 0 && 5404 status != QLA_SUCCESS) 5405 qla2x00_clear_loop_id(fcport); 5406 } 5407 } 5408 } 5409 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5410 break; 5411 } 5412 5413 if (relogin_needed) 5414 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5415 5416 ql_dbg(ql_dbg_disc, vha, 0x400e, 5417 "Relogin end.\n"); 5418 } 5419 5420 /* Schedule work on any of the dpc-workqueues */ 5421 void 5422 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5423 { 5424 struct qla_hw_data *ha = base_vha->hw; 5425 5426 switch (work_code) { 5427 case MBA_IDC_AEN: /* 0x8200 */ 5428 if (ha->dpc_lp_wq) 5429 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5430 break; 5431 5432 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5433 if (!ha->flags.nic_core_reset_hdlr_active) { 5434 if (ha->dpc_hp_wq) 5435 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5436 } else 5437 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5438 "NIC Core reset is already active. Skip " 5439 "scheduling it again.\n"); 5440 break; 5441 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5442 if (ha->dpc_hp_wq) 5443 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5444 break; 5445 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5446 if (ha->dpc_hp_wq) 5447 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5448 break; 5449 default: 5450 ql_log(ql_log_warn, base_vha, 0xb05f, 5451 "Unknown work-code=0x%x.\n", work_code); 5452 } 5453 5454 return; 5455 } 5456 5457 /* Work: Perform NIC Core Unrecoverable state handling */ 5458 void 5459 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5460 { 5461 struct qla_hw_data *ha = 5462 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5463 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5464 uint32_t dev_state = 0; 5465 5466 qla83xx_idc_lock(base_vha, 0); 5467 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5468 qla83xx_reset_ownership(base_vha); 5469 if (ha->flags.nic_core_reset_owner) { 5470 ha->flags.nic_core_reset_owner = 0; 5471 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5472 QLA8XXX_DEV_FAILED); 5473 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5474 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5475 } 5476 qla83xx_idc_unlock(base_vha, 0); 5477 } 5478 5479 /* Work: Execute IDC state handler */ 5480 void 5481 qla83xx_idc_state_handler_work(struct work_struct *work) 5482 { 5483 struct qla_hw_data *ha = 5484 container_of(work, struct qla_hw_data, idc_state_handler); 5485 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5486 uint32_t dev_state = 0; 5487 5488 qla83xx_idc_lock(base_vha, 0); 5489 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5490 if (dev_state == QLA8XXX_DEV_FAILED || 5491 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5492 qla83xx_idc_state_handler(base_vha); 5493 qla83xx_idc_unlock(base_vha, 0); 5494 } 5495 5496 static int 5497 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5498 { 5499 int rval = QLA_SUCCESS; 5500 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5501 uint32_t heart_beat_counter1, heart_beat_counter2; 5502 5503 do { 5504 if (time_after(jiffies, heart_beat_wait)) { 5505 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5506 "Nic Core f/w is not alive.\n"); 5507 rval = QLA_FUNCTION_FAILED; 5508 break; 5509 } 5510 5511 qla83xx_idc_lock(base_vha, 0); 5512 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5513 &heart_beat_counter1); 5514 qla83xx_idc_unlock(base_vha, 0); 5515 msleep(100); 5516 qla83xx_idc_lock(base_vha, 0); 5517 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5518 &heart_beat_counter2); 5519 qla83xx_idc_unlock(base_vha, 0); 5520 } while (heart_beat_counter1 == heart_beat_counter2); 5521 5522 return rval; 5523 } 5524 5525 /* Work: Perform NIC Core Reset handling */ 5526 void 5527 qla83xx_nic_core_reset_work(struct work_struct *work) 5528 { 5529 struct qla_hw_data *ha = 5530 container_of(work, struct qla_hw_data, nic_core_reset); 5531 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5532 uint32_t dev_state = 0; 5533 5534 if (IS_QLA2031(ha)) { 5535 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5536 ql_log(ql_log_warn, base_vha, 0xb081, 5537 "Failed to dump mctp\n"); 5538 return; 5539 } 5540 5541 if (!ha->flags.nic_core_reset_hdlr_active) { 5542 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5543 qla83xx_idc_lock(base_vha, 0); 5544 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5545 &dev_state); 5546 qla83xx_idc_unlock(base_vha, 0); 5547 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5548 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5549 "Nic Core f/w is alive.\n"); 5550 return; 5551 } 5552 } 5553 5554 ha->flags.nic_core_reset_hdlr_active = 1; 5555 if (qla83xx_nic_core_reset(base_vha)) { 5556 /* NIC Core reset failed. */ 5557 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5558 "NIC Core reset failed.\n"); 5559 } 5560 ha->flags.nic_core_reset_hdlr_active = 0; 5561 } 5562 } 5563 5564 /* Work: Handle 8200 IDC aens */ 5565 void 5566 qla83xx_service_idc_aen(struct work_struct *work) 5567 { 5568 struct qla_hw_data *ha = 5569 container_of(work, struct qla_hw_data, idc_aen); 5570 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5571 uint32_t dev_state, idc_control; 5572 5573 qla83xx_idc_lock(base_vha, 0); 5574 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5575 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5576 qla83xx_idc_unlock(base_vha, 0); 5577 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5578 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5579 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5580 "Application requested NIC Core Reset.\n"); 5581 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5582 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5583 QLA_SUCCESS) { 5584 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5585 "Other protocol driver requested NIC Core Reset.\n"); 5586 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5587 } 5588 } else if (dev_state == QLA8XXX_DEV_FAILED || 5589 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5590 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5591 } 5592 } 5593 5594 static void 5595 qla83xx_wait_logic(void) 5596 { 5597 int i; 5598 5599 /* Yield CPU */ 5600 if (!in_interrupt()) { 5601 /* 5602 * Wait about 200ms before retrying again. 5603 * This controls the number of retries for single 5604 * lock operation. 5605 */ 5606 msleep(100); 5607 schedule(); 5608 } else { 5609 for (i = 0; i < 20; i++) 5610 cpu_relax(); /* This a nop instr on i386 */ 5611 } 5612 } 5613 5614 static int 5615 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5616 { 5617 int rval; 5618 uint32_t data; 5619 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5620 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5621 struct qla_hw_data *ha = base_vha->hw; 5622 5623 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5624 "Trying force recovery of the IDC lock.\n"); 5625 5626 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5627 if (rval) 5628 return rval; 5629 5630 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5631 return QLA_SUCCESS; 5632 } else { 5633 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5634 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5635 data); 5636 if (rval) 5637 return rval; 5638 5639 msleep(200); 5640 5641 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5642 &data); 5643 if (rval) 5644 return rval; 5645 5646 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5647 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5648 ~(idc_lck_rcvry_stage_mask)); 5649 rval = qla83xx_wr_reg(base_vha, 5650 QLA83XX_IDC_LOCK_RECOVERY, data); 5651 if (rval) 5652 return rval; 5653 5654 /* Forcefully perform IDC UnLock */ 5655 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5656 &data); 5657 if (rval) 5658 return rval; 5659 /* Clear lock-id by setting 0xff */ 5660 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5661 0xff); 5662 if (rval) 5663 return rval; 5664 /* Clear lock-recovery by setting 0x0 */ 5665 rval = qla83xx_wr_reg(base_vha, 5666 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5667 if (rval) 5668 return rval; 5669 } else 5670 return QLA_SUCCESS; 5671 } 5672 5673 return rval; 5674 } 5675 5676 static int 5677 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5678 { 5679 int rval = QLA_SUCCESS; 5680 uint32_t o_drv_lockid, n_drv_lockid; 5681 unsigned long lock_recovery_timeout; 5682 5683 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5684 retry_lockid: 5685 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5686 if (rval) 5687 goto exit; 5688 5689 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5690 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5691 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5692 return QLA_SUCCESS; 5693 else 5694 return QLA_FUNCTION_FAILED; 5695 } 5696 5697 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5698 if (rval) 5699 goto exit; 5700 5701 if (o_drv_lockid == n_drv_lockid) { 5702 qla83xx_wait_logic(); 5703 goto retry_lockid; 5704 } else 5705 return QLA_SUCCESS; 5706 5707 exit: 5708 return rval; 5709 } 5710 5711 void 5712 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5713 { 5714 uint32_t data; 5715 uint32_t lock_owner; 5716 struct qla_hw_data *ha = base_vha->hw; 5717 5718 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5719 retry_lock: 5720 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5721 == QLA_SUCCESS) { 5722 if (data) { 5723 /* Setting lock-id to our function-number */ 5724 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5725 ha->portnum); 5726 } else { 5727 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5728 &lock_owner); 5729 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5730 "Failed to acquire IDC lock, acquired by %d, " 5731 "retrying...\n", lock_owner); 5732 5733 /* Retry/Perform IDC-Lock recovery */ 5734 if (qla83xx_idc_lock_recovery(base_vha) 5735 == QLA_SUCCESS) { 5736 qla83xx_wait_logic(); 5737 goto retry_lock; 5738 } else 5739 ql_log(ql_log_warn, base_vha, 0xb075, 5740 "IDC Lock recovery FAILED.\n"); 5741 } 5742 5743 } 5744 5745 return; 5746 } 5747 5748 static bool 5749 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5750 struct purex_entry_24xx *purex) 5751 { 5752 char fwstr[16]; 5753 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5754 struct port_database_24xx *pdb; 5755 5756 /* Domain Controller is always logged-out. */ 5757 /* if RDP request is not from Domain Controller: */ 5758 if (sid != 0xfffc01) 5759 return false; 5760 5761 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5762 5763 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5764 if (!pdb) { 5765 ql_dbg(ql_dbg_init, vha, 0x0181, 5766 "%s: Failed allocate pdb\n", __func__); 5767 } else if (qla24xx_get_port_database(vha, 5768 le16_to_cpu(purex->nport_handle), pdb)) { 5769 ql_dbg(ql_dbg_init, vha, 0x0181, 5770 "%s: Failed get pdb sid=%x\n", __func__, sid); 5771 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5772 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5773 ql_dbg(ql_dbg_init, vha, 0x0181, 5774 "%s: Port not logged in sid=%#x\n", __func__, sid); 5775 } else { 5776 /* RDP request is from logged in port */ 5777 kfree(pdb); 5778 return false; 5779 } 5780 kfree(pdb); 5781 5782 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5783 fwstr[strcspn(fwstr, " ")] = 0; 5784 /* if FW version allows RDP response length upto 2048 bytes: */ 5785 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5786 return false; 5787 5788 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5789 5790 /* RDP response length is to be reduced to maximum 256 bytes */ 5791 return true; 5792 } 5793 5794 static uint 5795 qla25xx_rdp_port_speed_capability(struct qla_hw_data *ha) 5796 { 5797 if (IS_CNA_CAPABLE(ha)) 5798 return RDP_PORT_SPEED_10GB; 5799 5800 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 5801 unsigned int speeds = 0; 5802 5803 if (ha->max_supported_speed == 2) { 5804 if (ha->min_supported_speed <= 6) 5805 speeds |= RDP_PORT_SPEED_64GB; 5806 } 5807 5808 if (ha->max_supported_speed == 2 || 5809 ha->max_supported_speed == 1) { 5810 if (ha->min_supported_speed <= 5) 5811 speeds |= RDP_PORT_SPEED_32GB; 5812 } 5813 5814 if (ha->max_supported_speed == 2 || 5815 ha->max_supported_speed == 1 || 5816 ha->max_supported_speed == 0) { 5817 if (ha->min_supported_speed <= 4) 5818 speeds |= RDP_PORT_SPEED_16GB; 5819 } 5820 5821 if (ha->max_supported_speed == 1 || 5822 ha->max_supported_speed == 0) { 5823 if (ha->min_supported_speed <= 3) 5824 speeds |= RDP_PORT_SPEED_8GB; 5825 } 5826 5827 if (ha->max_supported_speed == 0) { 5828 if (ha->min_supported_speed <= 2) 5829 speeds |= RDP_PORT_SPEED_4GB; 5830 } 5831 5832 return speeds; 5833 } 5834 5835 if (IS_QLA2031(ha)) 5836 return RDP_PORT_SPEED_16GB|RDP_PORT_SPEED_8GB| 5837 RDP_PORT_SPEED_4GB; 5838 5839 if (IS_QLA25XX(ha)) 5840 return RDP_PORT_SPEED_8GB|RDP_PORT_SPEED_4GB| 5841 RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB; 5842 5843 if (IS_QLA24XX_TYPE(ha)) 5844 return RDP_PORT_SPEED_4GB|RDP_PORT_SPEED_2GB| 5845 RDP_PORT_SPEED_1GB; 5846 5847 if (IS_QLA23XX(ha)) 5848 return RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB; 5849 5850 return RDP_PORT_SPEED_1GB; 5851 } 5852 5853 static uint 5854 qla25xx_rdp_port_speed_currently(struct qla_hw_data *ha) 5855 { 5856 switch (ha->link_data_rate) { 5857 case PORT_SPEED_1GB: 5858 return RDP_PORT_SPEED_1GB; 5859 5860 case PORT_SPEED_2GB: 5861 return RDP_PORT_SPEED_2GB; 5862 5863 case PORT_SPEED_4GB: 5864 return RDP_PORT_SPEED_4GB; 5865 5866 case PORT_SPEED_8GB: 5867 return RDP_PORT_SPEED_8GB; 5868 5869 case PORT_SPEED_10GB: 5870 return RDP_PORT_SPEED_10GB; 5871 5872 case PORT_SPEED_16GB: 5873 return RDP_PORT_SPEED_16GB; 5874 5875 case PORT_SPEED_32GB: 5876 return RDP_PORT_SPEED_32GB; 5877 5878 case PORT_SPEED_64GB: 5879 return RDP_PORT_SPEED_64GB; 5880 5881 default: 5882 return RDP_PORT_SPEED_UNKNOWN; 5883 } 5884 } 5885 5886 /* 5887 * Function Name: qla24xx_process_purex_iocb 5888 * 5889 * Description: 5890 * Prepare a RDP response and send to Fabric switch 5891 * 5892 * PARAMETERS: 5893 * vha: SCSI qla host 5894 * purex: RDP request received by HBA 5895 */ 5896 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, void *pkt) 5897 { 5898 struct qla_hw_data *ha = vha->hw; 5899 struct purex_entry_24xx *purex = pkt; 5900 dma_addr_t rsp_els_dma; 5901 dma_addr_t rsp_payload_dma; 5902 dma_addr_t stat_dma; 5903 dma_addr_t bbc_dma; 5904 dma_addr_t sfp_dma; 5905 struct els_entry_24xx *rsp_els = NULL; 5906 struct rdp_rsp_payload *rsp_payload = NULL; 5907 struct link_statistics *stat = NULL; 5908 struct buffer_credit_24xx *bbc = NULL; 5909 uint8_t *sfp = NULL; 5910 uint16_t sfp_flags = 0; 5911 uint rsp_payload_length = sizeof(*rsp_payload); 5912 int rval; 5913 5914 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5915 "%s: Enter\n", __func__); 5916 5917 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5918 "-------- ELS REQ -------\n"); 5919 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5920 purex, sizeof(*purex)); 5921 5922 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5923 rsp_payload_length = 5924 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5925 ql_dbg(ql_dbg_init, vha, 0x0181, 5926 "Reducing RSP payload length to %u bytes...\n", 5927 rsp_payload_length); 5928 } 5929 5930 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5931 &rsp_els_dma, GFP_KERNEL); 5932 if (!rsp_els) { 5933 ql_log(ql_log_warn, vha, 0x0183, 5934 "Failed allocate dma buffer ELS RSP.\n"); 5935 goto dealloc; 5936 } 5937 5938 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5939 &rsp_payload_dma, GFP_KERNEL); 5940 if (!rsp_payload) { 5941 ql_log(ql_log_warn, vha, 0x0184, 5942 "Failed allocate dma buffer ELS RSP payload.\n"); 5943 goto dealloc; 5944 } 5945 5946 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5947 &sfp_dma, GFP_KERNEL); 5948 5949 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 5950 &stat_dma, GFP_KERNEL); 5951 5952 bbc = dma_alloc_coherent(&ha->pdev->dev, sizeof(*bbc), 5953 &bbc_dma, GFP_KERNEL); 5954 5955 /* Prepare Response IOCB */ 5956 rsp_els->entry_type = ELS_IOCB_TYPE; 5957 rsp_els->entry_count = 1; 5958 rsp_els->sys_define = 0; 5959 rsp_els->entry_status = 0; 5960 rsp_els->handle = 0; 5961 rsp_els->nport_handle = purex->nport_handle; 5962 rsp_els->tx_dsd_count = cpu_to_le16(1); 5963 rsp_els->vp_index = purex->vp_idx; 5964 rsp_els->sof_type = EST_SOFI3; 5965 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 5966 rsp_els->rx_dsd_count = 0; 5967 rsp_els->opcode = purex->els_frame_payload[0]; 5968 5969 rsp_els->d_id[0] = purex->s_id[0]; 5970 rsp_els->d_id[1] = purex->s_id[1]; 5971 rsp_els->d_id[2] = purex->s_id[2]; 5972 5973 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 5974 rsp_els->rx_byte_count = 0; 5975 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 5976 5977 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 5978 rsp_els->tx_len = rsp_els->tx_byte_count; 5979 5980 rsp_els->rx_address = 0; 5981 rsp_els->rx_len = 0; 5982 5983 /* Prepare Response Payload */ 5984 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 5985 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 5986 sizeof(rsp_payload->hdr)); 5987 5988 /* Link service Request Info Descriptor */ 5989 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 5990 rsp_payload->ls_req_info_desc.desc_len = 5991 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 5992 rsp_payload->ls_req_info_desc.req_payload_word_0 = 5993 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5994 5995 /* Link service Request Info Descriptor 2 */ 5996 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 5997 rsp_payload->ls_req_info_desc2.desc_len = 5998 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 5999 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6000 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6001 6002 6003 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6004 rsp_payload->sfp_diag_desc.desc_len = 6005 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6006 6007 if (sfp) { 6008 /* SFP Flags */ 6009 memset(sfp, 0, SFP_RTDI_LEN); 6010 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6011 if (!rval) { 6012 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6013 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6014 sfp_flags |= BIT_0; /* short wave */ 6015 else if (sfp[0] & BIT_1) 6016 sfp_flags |= BIT_1; /* long wave 1310nm */ 6017 else if (sfp[1] & BIT_4) 6018 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6019 } 6020 6021 /* SFP Type */ 6022 memset(sfp, 0, SFP_RTDI_LEN); 6023 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6024 if (!rval) { 6025 sfp_flags |= BIT_4; /* optical */ 6026 if (sfp[0] == 0x3) 6027 sfp_flags |= BIT_6; /* sfp+ */ 6028 } 6029 6030 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6031 6032 /* SFP Diagnostics */ 6033 memset(sfp, 0, SFP_RTDI_LEN); 6034 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6035 if (!rval) { 6036 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6037 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6038 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6039 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6040 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6041 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6042 } 6043 } 6044 6045 /* Port Speed Descriptor */ 6046 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6047 rsp_payload->port_speed_desc.desc_len = 6048 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6049 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6050 qla25xx_rdp_port_speed_capability(ha)); 6051 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6052 qla25xx_rdp_port_speed_currently(ha)); 6053 6054 /* Link Error Status Descriptor */ 6055 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6056 rsp_payload->ls_err_desc.desc_len = 6057 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6058 6059 if (stat) { 6060 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6061 if (!rval) { 6062 rsp_payload->ls_err_desc.link_fail_cnt = 6063 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6064 rsp_payload->ls_err_desc.loss_sync_cnt = 6065 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6066 rsp_payload->ls_err_desc.loss_sig_cnt = 6067 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6068 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6069 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6070 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6071 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6072 rsp_payload->ls_err_desc.inval_crc_cnt = 6073 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6074 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6075 } 6076 } 6077 6078 /* Portname Descriptor */ 6079 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6080 rsp_payload->port_name_diag_desc.desc_len = 6081 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6082 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6083 vha->node_name, 6084 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6085 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6086 vha->port_name, 6087 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6088 6089 /* F-Port Portname Descriptor */ 6090 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6091 rsp_payload->port_name_direct_desc.desc_len = 6092 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6093 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6094 vha->fabric_node_name, 6095 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6096 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6097 vha->fabric_port_name, 6098 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6099 6100 /* Bufer Credit Descriptor */ 6101 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6102 rsp_payload->buffer_credit_desc.desc_len = 6103 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6104 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6105 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6106 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6107 6108 if (bbc) { 6109 memset(bbc, 0, sizeof(*bbc)); 6110 rval = qla24xx_get_buffer_credits(vha, bbc, bbc_dma); 6111 if (!rval) { 6112 rsp_payload->buffer_credit_desc.fcport_b2b = 6113 cpu_to_be32(LSW(bbc->parameter[0])); 6114 } 6115 } 6116 6117 if (rsp_payload_length < sizeof(*rsp_payload)) 6118 goto send; 6119 6120 /* Optical Element Descriptor, Temperature */ 6121 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6122 rsp_payload->optical_elmt_desc[0].desc_len = 6123 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6124 /* Optical Element Descriptor, Voltage */ 6125 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6126 rsp_payload->optical_elmt_desc[1].desc_len = 6127 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6128 /* Optical Element Descriptor, Tx Bias Current */ 6129 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6130 rsp_payload->optical_elmt_desc[2].desc_len = 6131 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6132 /* Optical Element Descriptor, Tx Power */ 6133 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6134 rsp_payload->optical_elmt_desc[3].desc_len = 6135 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6136 /* Optical Element Descriptor, Rx Power */ 6137 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6138 rsp_payload->optical_elmt_desc[4].desc_len = 6139 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6140 6141 if (sfp) { 6142 memset(sfp, 0, SFP_RTDI_LEN); 6143 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6144 if (!rval) { 6145 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6146 6147 /* Optical Element Descriptor, Temperature */ 6148 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6149 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6150 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6151 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6152 rsp_payload->optical_elmt_desc[0].element_flags = 6153 cpu_to_be32(1 << 28); 6154 6155 /* Optical Element Descriptor, Voltage */ 6156 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6157 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6158 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6159 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6160 rsp_payload->optical_elmt_desc[1].element_flags = 6161 cpu_to_be32(2 << 28); 6162 6163 /* Optical Element Descriptor, Tx Bias Current */ 6164 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6165 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6166 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6167 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6168 rsp_payload->optical_elmt_desc[2].element_flags = 6169 cpu_to_be32(3 << 28); 6170 6171 /* Optical Element Descriptor, Tx Power */ 6172 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6173 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6174 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6175 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6176 rsp_payload->optical_elmt_desc[3].element_flags = 6177 cpu_to_be32(4 << 28); 6178 6179 /* Optical Element Descriptor, Rx Power */ 6180 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6181 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6182 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6183 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6184 rsp_payload->optical_elmt_desc[4].element_flags = 6185 cpu_to_be32(5 << 28); 6186 } 6187 6188 memset(sfp, 0, SFP_RTDI_LEN); 6189 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6190 if (!rval) { 6191 /* Temperature high/low alarm/warning */ 6192 rsp_payload->optical_elmt_desc[0].element_flags |= 6193 cpu_to_be32( 6194 (sfp[0] >> 7 & 1) << 3 | 6195 (sfp[0] >> 6 & 1) << 2 | 6196 (sfp[4] >> 7 & 1) << 1 | 6197 (sfp[4] >> 6 & 1) << 0); 6198 6199 /* Voltage high/low alarm/warning */ 6200 rsp_payload->optical_elmt_desc[1].element_flags |= 6201 cpu_to_be32( 6202 (sfp[0] >> 5 & 1) << 3 | 6203 (sfp[0] >> 4 & 1) << 2 | 6204 (sfp[4] >> 5 & 1) << 1 | 6205 (sfp[4] >> 4 & 1) << 0); 6206 6207 /* Tx Bias Current high/low alarm/warning */ 6208 rsp_payload->optical_elmt_desc[2].element_flags |= 6209 cpu_to_be32( 6210 (sfp[0] >> 3 & 1) << 3 | 6211 (sfp[0] >> 2 & 1) << 2 | 6212 (sfp[4] >> 3 & 1) << 1 | 6213 (sfp[4] >> 2 & 1) << 0); 6214 6215 /* Tx Power high/low alarm/warning */ 6216 rsp_payload->optical_elmt_desc[3].element_flags |= 6217 cpu_to_be32( 6218 (sfp[0] >> 1 & 1) << 3 | 6219 (sfp[0] >> 0 & 1) << 2 | 6220 (sfp[4] >> 1 & 1) << 1 | 6221 (sfp[4] >> 0 & 1) << 0); 6222 6223 /* Rx Power high/low alarm/warning */ 6224 rsp_payload->optical_elmt_desc[4].element_flags |= 6225 cpu_to_be32( 6226 (sfp[1] >> 7 & 1) << 3 | 6227 (sfp[1] >> 6 & 1) << 2 | 6228 (sfp[5] >> 7 & 1) << 1 | 6229 (sfp[5] >> 6 & 1) << 0); 6230 } 6231 } 6232 6233 /* Optical Product Data Descriptor */ 6234 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6235 rsp_payload->optical_prod_desc.desc_len = 6236 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6237 6238 if (sfp) { 6239 memset(sfp, 0, SFP_RTDI_LEN); 6240 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6241 if (!rval) { 6242 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6243 sfp + 0, 6244 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6245 memcpy(rsp_payload->optical_prod_desc.part_number, 6246 sfp + 20, 6247 sizeof(rsp_payload->optical_prod_desc.part_number)); 6248 memcpy(rsp_payload->optical_prod_desc.revision, 6249 sfp + 36, 6250 sizeof(rsp_payload->optical_prod_desc.revision)); 6251 memcpy(rsp_payload->optical_prod_desc.serial_number, 6252 sfp + 48, 6253 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6254 } 6255 6256 memset(sfp, 0, SFP_RTDI_LEN); 6257 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6258 if (!rval) { 6259 memcpy(rsp_payload->optical_prod_desc.date, 6260 sfp + 0, 6261 sizeof(rsp_payload->optical_prod_desc.date)); 6262 } 6263 } 6264 6265 send: 6266 ql_dbg(ql_dbg_init, vha, 0x0183, 6267 "Sending ELS Response to RDP Request...\n"); 6268 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6269 "-------- ELS RSP -------\n"); 6270 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6271 rsp_els, sizeof(*rsp_els)); 6272 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6273 "-------- ELS RSP PAYLOAD -------\n"); 6274 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6275 rsp_payload, rsp_payload_length); 6276 6277 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6278 6279 if (rval) { 6280 ql_log(ql_log_warn, vha, 0x0188, 6281 "%s: iocb failed to execute -> %x\n", __func__, rval); 6282 } else if (rsp_els->comp_status) { 6283 ql_log(ql_log_warn, vha, 0x0189, 6284 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6285 __func__, rsp_els->comp_status, 6286 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6287 } else { 6288 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6289 } 6290 6291 dealloc: 6292 if (bbc) 6293 dma_free_coherent(&ha->pdev->dev, sizeof(*bbc), 6294 bbc, bbc_dma); 6295 if (stat) 6296 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6297 stat, stat_dma); 6298 if (sfp) 6299 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6300 sfp, sfp_dma); 6301 if (rsp_payload) 6302 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6303 rsp_payload, rsp_payload_dma); 6304 if (rsp_els) 6305 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6306 rsp_els, rsp_els_dma); 6307 } 6308 6309 void qla24xx_process_purex_list(struct purex_list *list) 6310 { 6311 struct list_head head = LIST_HEAD_INIT(head); 6312 struct purex_item *item, *next; 6313 ulong flags; 6314 6315 spin_lock_irqsave(&list->lock, flags); 6316 list_splice_init(&list->head, &head); 6317 spin_unlock_irqrestore(&list->lock, flags); 6318 6319 list_for_each_entry_safe(item, next, &head, list) { 6320 list_del(&item->list); 6321 item->process_item(item->vha, &item->iocb); 6322 kfree(item); 6323 } 6324 } 6325 6326 void 6327 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6328 { 6329 #if 0 6330 uint16_t options = (requester_id << 15) | BIT_7; 6331 #endif 6332 uint16_t retry; 6333 uint32_t data; 6334 struct qla_hw_data *ha = base_vha->hw; 6335 6336 /* IDC-unlock implementation using driver-unlock/lock-id 6337 * remote registers 6338 */ 6339 retry = 0; 6340 retry_unlock: 6341 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6342 == QLA_SUCCESS) { 6343 if (data == ha->portnum) { 6344 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6345 /* Clearing lock-id by setting 0xff */ 6346 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6347 } else if (retry < 10) { 6348 /* SV: XXX: IDC unlock retrying needed here? */ 6349 6350 /* Retry for IDC-unlock */ 6351 qla83xx_wait_logic(); 6352 retry++; 6353 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6354 "Failed to release IDC lock, retrying=%d\n", retry); 6355 goto retry_unlock; 6356 } 6357 } else if (retry < 10) { 6358 /* Retry for IDC-unlock */ 6359 qla83xx_wait_logic(); 6360 retry++; 6361 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6362 "Failed to read drv-lockid, retrying=%d\n", retry); 6363 goto retry_unlock; 6364 } 6365 6366 return; 6367 6368 #if 0 6369 /* XXX: IDC-unlock implementation using access-control mbx */ 6370 retry = 0; 6371 retry_unlock2: 6372 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6373 if (retry < 10) { 6374 /* Retry for IDC-unlock */ 6375 qla83xx_wait_logic(); 6376 retry++; 6377 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6378 "Failed to release IDC lock, retrying=%d\n", retry); 6379 goto retry_unlock2; 6380 } 6381 } 6382 6383 return; 6384 #endif 6385 } 6386 6387 int 6388 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6389 { 6390 int rval = QLA_SUCCESS; 6391 struct qla_hw_data *ha = vha->hw; 6392 uint32_t drv_presence; 6393 6394 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6395 if (rval == QLA_SUCCESS) { 6396 drv_presence |= (1 << ha->portnum); 6397 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6398 drv_presence); 6399 } 6400 6401 return rval; 6402 } 6403 6404 int 6405 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6406 { 6407 int rval = QLA_SUCCESS; 6408 6409 qla83xx_idc_lock(vha, 0); 6410 rval = __qla83xx_set_drv_presence(vha); 6411 qla83xx_idc_unlock(vha, 0); 6412 6413 return rval; 6414 } 6415 6416 int 6417 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6418 { 6419 int rval = QLA_SUCCESS; 6420 struct qla_hw_data *ha = vha->hw; 6421 uint32_t drv_presence; 6422 6423 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6424 if (rval == QLA_SUCCESS) { 6425 drv_presence &= ~(1 << ha->portnum); 6426 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6427 drv_presence); 6428 } 6429 6430 return rval; 6431 } 6432 6433 int 6434 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6435 { 6436 int rval = QLA_SUCCESS; 6437 6438 qla83xx_idc_lock(vha, 0); 6439 rval = __qla83xx_clear_drv_presence(vha); 6440 qla83xx_idc_unlock(vha, 0); 6441 6442 return rval; 6443 } 6444 6445 static void 6446 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6447 { 6448 struct qla_hw_data *ha = vha->hw; 6449 uint32_t drv_ack, drv_presence; 6450 unsigned long ack_timeout; 6451 6452 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6453 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6454 while (1) { 6455 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6456 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6457 if ((drv_ack & drv_presence) == drv_presence) 6458 break; 6459 6460 if (time_after_eq(jiffies, ack_timeout)) { 6461 ql_log(ql_log_warn, vha, 0xb067, 6462 "RESET ACK TIMEOUT! drv_presence=0x%x " 6463 "drv_ack=0x%x\n", drv_presence, drv_ack); 6464 /* 6465 * The function(s) which did not ack in time are forced 6466 * to withdraw any further participation in the IDC 6467 * reset. 6468 */ 6469 if (drv_ack != drv_presence) 6470 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6471 drv_ack); 6472 break; 6473 } 6474 6475 qla83xx_idc_unlock(vha, 0); 6476 msleep(1000); 6477 qla83xx_idc_lock(vha, 0); 6478 } 6479 6480 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6481 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6482 } 6483 6484 static int 6485 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6486 { 6487 int rval = QLA_SUCCESS; 6488 uint32_t idc_control; 6489 6490 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6491 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6492 6493 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6494 __qla83xx_get_idc_control(vha, &idc_control); 6495 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6496 __qla83xx_set_idc_control(vha, 0); 6497 6498 qla83xx_idc_unlock(vha, 0); 6499 rval = qla83xx_restart_nic_firmware(vha); 6500 qla83xx_idc_lock(vha, 0); 6501 6502 if (rval != QLA_SUCCESS) { 6503 ql_log(ql_log_fatal, vha, 0xb06a, 6504 "Failed to restart NIC f/w.\n"); 6505 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6506 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6507 } else { 6508 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6509 "Success in restarting nic f/w.\n"); 6510 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6511 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6512 } 6513 6514 return rval; 6515 } 6516 6517 /* Assumes idc_lock always held on entry */ 6518 int 6519 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6520 { 6521 struct qla_hw_data *ha = base_vha->hw; 6522 int rval = QLA_SUCCESS; 6523 unsigned long dev_init_timeout; 6524 uint32_t dev_state; 6525 6526 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6527 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6528 6529 while (1) { 6530 6531 if (time_after_eq(jiffies, dev_init_timeout)) { 6532 ql_log(ql_log_warn, base_vha, 0xb06e, 6533 "Initialization TIMEOUT!\n"); 6534 /* Init timeout. Disable further NIC Core 6535 * communication. 6536 */ 6537 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6538 QLA8XXX_DEV_FAILED); 6539 ql_log(ql_log_info, base_vha, 0xb06f, 6540 "HW State: FAILED.\n"); 6541 } 6542 6543 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6544 switch (dev_state) { 6545 case QLA8XXX_DEV_READY: 6546 if (ha->flags.nic_core_reset_owner) 6547 qla83xx_idc_audit(base_vha, 6548 IDC_AUDIT_COMPLETION); 6549 ha->flags.nic_core_reset_owner = 0; 6550 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6551 "Reset_owner reset by 0x%x.\n", 6552 ha->portnum); 6553 goto exit; 6554 case QLA8XXX_DEV_COLD: 6555 if (ha->flags.nic_core_reset_owner) 6556 rval = qla83xx_device_bootstrap(base_vha); 6557 else { 6558 /* Wait for AEN to change device-state */ 6559 qla83xx_idc_unlock(base_vha, 0); 6560 msleep(1000); 6561 qla83xx_idc_lock(base_vha, 0); 6562 } 6563 break; 6564 case QLA8XXX_DEV_INITIALIZING: 6565 /* Wait for AEN to change device-state */ 6566 qla83xx_idc_unlock(base_vha, 0); 6567 msleep(1000); 6568 qla83xx_idc_lock(base_vha, 0); 6569 break; 6570 case QLA8XXX_DEV_NEED_RESET: 6571 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6572 qla83xx_need_reset_handler(base_vha); 6573 else { 6574 /* Wait for AEN to change device-state */ 6575 qla83xx_idc_unlock(base_vha, 0); 6576 msleep(1000); 6577 qla83xx_idc_lock(base_vha, 0); 6578 } 6579 /* reset timeout value after need reset handler */ 6580 dev_init_timeout = jiffies + 6581 (ha->fcoe_dev_init_timeout * HZ); 6582 break; 6583 case QLA8XXX_DEV_NEED_QUIESCENT: 6584 /* XXX: DEBUG for now */ 6585 qla83xx_idc_unlock(base_vha, 0); 6586 msleep(1000); 6587 qla83xx_idc_lock(base_vha, 0); 6588 break; 6589 case QLA8XXX_DEV_QUIESCENT: 6590 /* XXX: DEBUG for now */ 6591 if (ha->flags.quiesce_owner) 6592 goto exit; 6593 6594 qla83xx_idc_unlock(base_vha, 0); 6595 msleep(1000); 6596 qla83xx_idc_lock(base_vha, 0); 6597 dev_init_timeout = jiffies + 6598 (ha->fcoe_dev_init_timeout * HZ); 6599 break; 6600 case QLA8XXX_DEV_FAILED: 6601 if (ha->flags.nic_core_reset_owner) 6602 qla83xx_idc_audit(base_vha, 6603 IDC_AUDIT_COMPLETION); 6604 ha->flags.nic_core_reset_owner = 0; 6605 __qla83xx_clear_drv_presence(base_vha); 6606 qla83xx_idc_unlock(base_vha, 0); 6607 qla8xxx_dev_failed_handler(base_vha); 6608 rval = QLA_FUNCTION_FAILED; 6609 qla83xx_idc_lock(base_vha, 0); 6610 goto exit; 6611 case QLA8XXX_BAD_VALUE: 6612 qla83xx_idc_unlock(base_vha, 0); 6613 msleep(1000); 6614 qla83xx_idc_lock(base_vha, 0); 6615 break; 6616 default: 6617 ql_log(ql_log_warn, base_vha, 0xb071, 6618 "Unknown Device State: %x.\n", dev_state); 6619 qla83xx_idc_unlock(base_vha, 0); 6620 qla8xxx_dev_failed_handler(base_vha); 6621 rval = QLA_FUNCTION_FAILED; 6622 qla83xx_idc_lock(base_vha, 0); 6623 goto exit; 6624 } 6625 } 6626 6627 exit: 6628 return rval; 6629 } 6630 6631 void 6632 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6633 { 6634 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6635 board_disable); 6636 struct pci_dev *pdev = ha->pdev; 6637 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6638 6639 ql_log(ql_log_warn, base_vha, 0x015b, 6640 "Disabling adapter.\n"); 6641 6642 if (!atomic_read(&pdev->enable_cnt)) { 6643 ql_log(ql_log_info, base_vha, 0xfffc, 6644 "PCI device disabled, no action req for PCI error=%lx\n", 6645 base_vha->pci_flags); 6646 return; 6647 } 6648 6649 /* 6650 * if UNLOADING flag is already set, then continue unload, 6651 * where it was set first. 6652 */ 6653 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6654 return; 6655 6656 qla2x00_wait_for_sess_deletion(base_vha); 6657 6658 qla2x00_delete_all_vps(ha, base_vha); 6659 6660 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6661 6662 qla2x00_dfs_remove(base_vha); 6663 6664 qla84xx_put_chip(base_vha); 6665 6666 if (base_vha->timer_active) 6667 qla2x00_stop_timer(base_vha); 6668 6669 base_vha->flags.online = 0; 6670 6671 qla2x00_destroy_deferred_work(ha); 6672 6673 /* 6674 * Do not try to stop beacon blink as it will issue a mailbox 6675 * command. 6676 */ 6677 qla2x00_free_sysfs_attr(base_vha, false); 6678 6679 fc_remove_host(base_vha->host); 6680 6681 scsi_remove_host(base_vha->host); 6682 6683 base_vha->flags.init_done = 0; 6684 qla25xx_delete_queues(base_vha); 6685 qla2x00_free_fcports(base_vha); 6686 qla2x00_free_irqs(base_vha); 6687 qla2x00_mem_free(ha); 6688 qla82xx_md_free(base_vha); 6689 qla2x00_free_queues(ha); 6690 6691 qla2x00_unmap_iobases(ha); 6692 6693 pci_release_selected_regions(ha->pdev, ha->bars); 6694 pci_disable_pcie_error_reporting(pdev); 6695 pci_disable_device(pdev); 6696 6697 /* 6698 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6699 */ 6700 } 6701 6702 /************************************************************************** 6703 * qla2x00_do_dpc 6704 * This kernel thread is a task that is schedule by the interrupt handler 6705 * to perform the background processing for interrupts. 6706 * 6707 * Notes: 6708 * This task always run in the context of a kernel thread. It 6709 * is kick-off by the driver's detect code and starts up 6710 * up one per adapter. It immediately goes to sleep and waits for 6711 * some fibre event. When either the interrupt handler or 6712 * the timer routine detects a event it will one of the task 6713 * bits then wake us up. 6714 **************************************************************************/ 6715 static int 6716 qla2x00_do_dpc(void *data) 6717 { 6718 scsi_qla_host_t *base_vha; 6719 struct qla_hw_data *ha; 6720 uint32_t online; 6721 struct qla_qpair *qpair; 6722 6723 ha = (struct qla_hw_data *)data; 6724 base_vha = pci_get_drvdata(ha->pdev); 6725 6726 set_user_nice(current, MIN_NICE); 6727 6728 set_current_state(TASK_INTERRUPTIBLE); 6729 while (!kthread_should_stop()) { 6730 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6731 "DPC handler sleeping.\n"); 6732 6733 schedule(); 6734 6735 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6736 goto end_loop; 6737 6738 if (ha->flags.eeh_busy) { 6739 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6740 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6741 goto end_loop; 6742 } 6743 6744 ha->dpc_active = 1; 6745 6746 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6747 "DPC handler waking up, dpc_flags=0x%lx.\n", 6748 base_vha->dpc_flags); 6749 6750 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6751 break; 6752 6753 if (IS_P3P_TYPE(ha)) { 6754 if (IS_QLA8044(ha)) { 6755 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6756 &base_vha->dpc_flags)) { 6757 qla8044_idc_lock(ha); 6758 qla8044_wr_direct(base_vha, 6759 QLA8044_CRB_DEV_STATE_INDEX, 6760 QLA8XXX_DEV_FAILED); 6761 qla8044_idc_unlock(ha); 6762 ql_log(ql_log_info, base_vha, 0x4004, 6763 "HW State: FAILED.\n"); 6764 qla8044_device_state_handler(base_vha); 6765 continue; 6766 } 6767 6768 } else { 6769 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6770 &base_vha->dpc_flags)) { 6771 qla82xx_idc_lock(ha); 6772 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6773 QLA8XXX_DEV_FAILED); 6774 qla82xx_idc_unlock(ha); 6775 ql_log(ql_log_info, base_vha, 0x0151, 6776 "HW State: FAILED.\n"); 6777 qla82xx_device_state_handler(base_vha); 6778 continue; 6779 } 6780 } 6781 6782 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6783 &base_vha->dpc_flags)) { 6784 6785 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6786 "FCoE context reset scheduled.\n"); 6787 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6788 &base_vha->dpc_flags))) { 6789 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6790 /* FCoE-ctx reset failed. 6791 * Escalate to chip-reset 6792 */ 6793 set_bit(ISP_ABORT_NEEDED, 6794 &base_vha->dpc_flags); 6795 } 6796 clear_bit(ABORT_ISP_ACTIVE, 6797 &base_vha->dpc_flags); 6798 } 6799 6800 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6801 "FCoE context reset end.\n"); 6802 } 6803 } else if (IS_QLAFX00(ha)) { 6804 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6805 &base_vha->dpc_flags)) { 6806 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6807 "Firmware Reset Recovery\n"); 6808 if (qlafx00_reset_initialize(base_vha)) { 6809 /* Failed. Abort isp later. */ 6810 if (!test_bit(UNLOADING, 6811 &base_vha->dpc_flags)) { 6812 set_bit(ISP_UNRECOVERABLE, 6813 &base_vha->dpc_flags); 6814 ql_dbg(ql_dbg_dpc, base_vha, 6815 0x4021, 6816 "Reset Recovery Failed\n"); 6817 } 6818 } 6819 } 6820 6821 if (test_and_clear_bit(FX00_TARGET_SCAN, 6822 &base_vha->dpc_flags)) { 6823 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6824 "ISPFx00 Target Scan scheduled\n"); 6825 if (qlafx00_rescan_isp(base_vha)) { 6826 if (!test_bit(UNLOADING, 6827 &base_vha->dpc_flags)) 6828 set_bit(ISP_UNRECOVERABLE, 6829 &base_vha->dpc_flags); 6830 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6831 "ISPFx00 Target Scan Failed\n"); 6832 } 6833 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6834 "ISPFx00 Target Scan End\n"); 6835 } 6836 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6837 &base_vha->dpc_flags)) { 6838 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6839 "ISPFx00 Host Info resend scheduled\n"); 6840 qlafx00_fx_disc(base_vha, 6841 &base_vha->hw->mr.fcport, 6842 FXDISC_REG_HOST_INFO); 6843 } 6844 } 6845 6846 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6847 &base_vha->dpc_flags)) { 6848 /* Semantic: 6849 * - NO-OP -- await next ISP-ABORT. Preferred method 6850 * to minimize disruptions that will occur 6851 * when a forced chip-reset occurs. 6852 * - Force -- ISP-ABORT scheduled. 6853 */ 6854 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6855 } 6856 6857 if (test_and_clear_bit 6858 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6859 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6860 bool do_reset = true; 6861 6862 switch (base_vha->qlini_mode) { 6863 case QLA2XXX_INI_MODE_ENABLED: 6864 break; 6865 case QLA2XXX_INI_MODE_DISABLED: 6866 if (!qla_tgt_mode_enabled(base_vha) && 6867 !ha->flags.fw_started) 6868 do_reset = false; 6869 break; 6870 case QLA2XXX_INI_MODE_DUAL: 6871 if (!qla_dual_mode_enabled(base_vha) && 6872 !ha->flags.fw_started) 6873 do_reset = false; 6874 break; 6875 default: 6876 break; 6877 } 6878 6879 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6880 &base_vha->dpc_flags))) { 6881 base_vha->flags.online = 1; 6882 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6883 "ISP abort scheduled.\n"); 6884 if (ha->isp_ops->abort_isp(base_vha)) { 6885 /* failed. retry later */ 6886 set_bit(ISP_ABORT_NEEDED, 6887 &base_vha->dpc_flags); 6888 } 6889 clear_bit(ABORT_ISP_ACTIVE, 6890 &base_vha->dpc_flags); 6891 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6892 "ISP abort end.\n"); 6893 } 6894 } 6895 6896 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6897 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6898 qla24xx_process_purex_list 6899 (&base_vha->purex_list); 6900 clear_bit(PROCESS_PUREX_IOCB, 6901 &base_vha->dpc_flags); 6902 } 6903 } 6904 6905 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6906 &base_vha->dpc_flags)) { 6907 qla2x00_update_fcports(base_vha); 6908 } 6909 6910 if (IS_QLAFX00(ha)) 6911 goto loop_resync_check; 6912 6913 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6914 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6915 "Quiescence mode scheduled.\n"); 6916 if (IS_P3P_TYPE(ha)) { 6917 if (IS_QLA82XX(ha)) 6918 qla82xx_device_state_handler(base_vha); 6919 if (IS_QLA8044(ha)) 6920 qla8044_device_state_handler(base_vha); 6921 clear_bit(ISP_QUIESCE_NEEDED, 6922 &base_vha->dpc_flags); 6923 if (!ha->flags.quiesce_owner) { 6924 qla2x00_perform_loop_resync(base_vha); 6925 if (IS_QLA82XX(ha)) { 6926 qla82xx_idc_lock(ha); 6927 qla82xx_clear_qsnt_ready( 6928 base_vha); 6929 qla82xx_idc_unlock(ha); 6930 } else if (IS_QLA8044(ha)) { 6931 qla8044_idc_lock(ha); 6932 qla8044_clear_qsnt_ready( 6933 base_vha); 6934 qla8044_idc_unlock(ha); 6935 } 6936 } 6937 } else { 6938 clear_bit(ISP_QUIESCE_NEEDED, 6939 &base_vha->dpc_flags); 6940 qla2x00_quiesce_io(base_vha); 6941 } 6942 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6943 "Quiescence mode end.\n"); 6944 } 6945 6946 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6947 &base_vha->dpc_flags) && 6948 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6949 6950 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6951 "Reset marker scheduled.\n"); 6952 qla2x00_rst_aen(base_vha); 6953 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6954 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6955 "Reset marker end.\n"); 6956 } 6957 6958 /* Retry each device up to login retry count */ 6959 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6960 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6961 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6962 6963 if (!base_vha->relogin_jif || 6964 time_after_eq(jiffies, base_vha->relogin_jif)) { 6965 base_vha->relogin_jif = jiffies + HZ; 6966 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6967 6968 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6969 "Relogin scheduled.\n"); 6970 qla24xx_post_relogin_work(base_vha); 6971 } 6972 } 6973 loop_resync_check: 6974 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6975 &base_vha->dpc_flags)) { 6976 6977 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6978 "Loop resync scheduled.\n"); 6979 6980 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6981 &base_vha->dpc_flags))) { 6982 6983 qla2x00_loop_resync(base_vha); 6984 6985 clear_bit(LOOP_RESYNC_ACTIVE, 6986 &base_vha->dpc_flags); 6987 } 6988 6989 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6990 "Loop resync end.\n"); 6991 } 6992 6993 if (IS_QLAFX00(ha)) 6994 goto intr_on_check; 6995 6996 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6997 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6998 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6999 qla2xxx_flash_npiv_conf(base_vha); 7000 } 7001 7002 intr_on_check: 7003 if (!ha->interrupts_on) 7004 ha->isp_ops->enable_intrs(ha); 7005 7006 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7007 &base_vha->dpc_flags)) { 7008 if (ha->beacon_blink_led == 1) 7009 ha->isp_ops->beacon_blink(base_vha); 7010 } 7011 7012 /* qpair online check */ 7013 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7014 &base_vha->dpc_flags)) { 7015 if (ha->flags.eeh_busy || 7016 ha->flags.pci_channel_io_perm_failure) 7017 online = 0; 7018 else 7019 online = 1; 7020 7021 mutex_lock(&ha->mq_lock); 7022 list_for_each_entry(qpair, &base_vha->qp_list, 7023 qp_list_elem) 7024 qpair->online = online; 7025 mutex_unlock(&ha->mq_lock); 7026 } 7027 7028 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 7029 &base_vha->dpc_flags)) { 7030 ql_log(ql_log_info, base_vha, 0xffffff, 7031 "nvme: SET ZIO Activity exchange threshold to %d.\n", 7032 ha->nvme_last_rptd_aen); 7033 if (qla27xx_set_zio_threshold(base_vha, 7034 ha->nvme_last_rptd_aen)) { 7035 ql_log(ql_log_info, base_vha, 0xffffff, 7036 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 7037 ha->nvme_last_rptd_aen); 7038 } 7039 } 7040 7041 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7042 &base_vha->dpc_flags)) { 7043 ql_log(ql_log_info, base_vha, 0xffffff, 7044 "SET ZIO Activity exchange threshold to %d.\n", 7045 ha->last_zio_threshold); 7046 qla27xx_set_zio_threshold(base_vha, 7047 ha->last_zio_threshold); 7048 } 7049 7050 if (!IS_QLAFX00(ha)) 7051 qla2x00_do_dpc_all_vps(base_vha); 7052 7053 if (test_and_clear_bit(N2N_LINK_RESET, 7054 &base_vha->dpc_flags)) { 7055 qla2x00_lip_reset(base_vha); 7056 } 7057 7058 ha->dpc_active = 0; 7059 end_loop: 7060 set_current_state(TASK_INTERRUPTIBLE); 7061 } /* End of while(1) */ 7062 __set_current_state(TASK_RUNNING); 7063 7064 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7065 "DPC handler exiting.\n"); 7066 7067 /* 7068 * Make sure that nobody tries to wake us up again. 7069 */ 7070 ha->dpc_active = 0; 7071 7072 /* Cleanup any residual CTX SRBs. */ 7073 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7074 7075 return 0; 7076 } 7077 7078 void 7079 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7080 { 7081 struct qla_hw_data *ha = vha->hw; 7082 struct task_struct *t = ha->dpc_thread; 7083 7084 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7085 wake_up_process(t); 7086 } 7087 7088 /* 7089 * qla2x00_rst_aen 7090 * Processes asynchronous reset. 7091 * 7092 * Input: 7093 * ha = adapter block pointer. 7094 */ 7095 static void 7096 qla2x00_rst_aen(scsi_qla_host_t *vha) 7097 { 7098 if (vha->flags.online && !vha->flags.reset_active && 7099 !atomic_read(&vha->loop_down_timer) && 7100 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7101 do { 7102 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7103 7104 /* 7105 * Issue marker command only when we are going to start 7106 * the I/O. 7107 */ 7108 vha->marker_needed = 1; 7109 } while (!atomic_read(&vha->loop_down_timer) && 7110 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7111 } 7112 } 7113 7114 /************************************************************************** 7115 * qla2x00_timer 7116 * 7117 * Description: 7118 * One second timer 7119 * 7120 * Context: Interrupt 7121 ***************************************************************************/ 7122 void 7123 qla2x00_timer(struct timer_list *t) 7124 { 7125 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7126 unsigned long cpu_flags = 0; 7127 int start_dpc = 0; 7128 int index; 7129 srb_t *sp; 7130 uint16_t w; 7131 struct qla_hw_data *ha = vha->hw; 7132 struct req_que *req; 7133 7134 if (ha->flags.eeh_busy) { 7135 ql_dbg(ql_dbg_timer, vha, 0x6000, 7136 "EEH = %d, restarting timer.\n", 7137 ha->flags.eeh_busy); 7138 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7139 return; 7140 } 7141 7142 /* 7143 * Hardware read to raise pending EEH errors during mailbox waits. If 7144 * the read returns -1 then disable the board. 7145 */ 7146 if (!pci_channel_offline(ha->pdev)) { 7147 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7148 qla2x00_check_reg16_for_disconnect(vha, w); 7149 } 7150 7151 /* Make sure qla82xx_watchdog is run only for physical port */ 7152 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7153 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7154 start_dpc++; 7155 if (IS_QLA82XX(ha)) 7156 qla82xx_watchdog(vha); 7157 else if (IS_QLA8044(ha)) 7158 qla8044_watchdog(vha); 7159 } 7160 7161 if (!vha->vp_idx && IS_QLAFX00(ha)) 7162 qlafx00_timer_routine(vha); 7163 7164 /* Loop down handler. */ 7165 if (atomic_read(&vha->loop_down_timer) > 0 && 7166 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7167 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7168 && vha->flags.online) { 7169 7170 if (atomic_read(&vha->loop_down_timer) == 7171 vha->loop_down_abort_time) { 7172 7173 ql_log(ql_log_info, vha, 0x6008, 7174 "Loop down - aborting the queues before time expires.\n"); 7175 7176 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7177 atomic_set(&vha->loop_state, LOOP_DEAD); 7178 7179 /* 7180 * Schedule an ISP abort to return any FCP2-device 7181 * commands. 7182 */ 7183 /* NPIV - scan physical port only */ 7184 if (!vha->vp_idx) { 7185 spin_lock_irqsave(&ha->hardware_lock, 7186 cpu_flags); 7187 req = ha->req_q_map[0]; 7188 for (index = 1; 7189 index < req->num_outstanding_cmds; 7190 index++) { 7191 fc_port_t *sfcp; 7192 7193 sp = req->outstanding_cmds[index]; 7194 if (!sp) 7195 continue; 7196 if (sp->cmd_type != TYPE_SRB) 7197 continue; 7198 if (sp->type != SRB_SCSI_CMD) 7199 continue; 7200 sfcp = sp->fcport; 7201 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7202 continue; 7203 7204 if (IS_QLA82XX(ha)) 7205 set_bit(FCOE_CTX_RESET_NEEDED, 7206 &vha->dpc_flags); 7207 else 7208 set_bit(ISP_ABORT_NEEDED, 7209 &vha->dpc_flags); 7210 break; 7211 } 7212 spin_unlock_irqrestore(&ha->hardware_lock, 7213 cpu_flags); 7214 } 7215 start_dpc++; 7216 } 7217 7218 /* if the loop has been down for 4 minutes, reinit adapter */ 7219 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7220 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7221 ql_log(ql_log_warn, vha, 0x6009, 7222 "Loop down - aborting ISP.\n"); 7223 7224 if (IS_QLA82XX(ha)) 7225 set_bit(FCOE_CTX_RESET_NEEDED, 7226 &vha->dpc_flags); 7227 else 7228 set_bit(ISP_ABORT_NEEDED, 7229 &vha->dpc_flags); 7230 } 7231 } 7232 ql_dbg(ql_dbg_timer, vha, 0x600a, 7233 "Loop down - seconds remaining %d.\n", 7234 atomic_read(&vha->loop_down_timer)); 7235 } 7236 /* Check if beacon LED needs to be blinked for physical host only */ 7237 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7238 /* There is no beacon_blink function for ISP82xx */ 7239 if (!IS_P3P_TYPE(ha)) { 7240 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7241 start_dpc++; 7242 } 7243 } 7244 7245 /* Process any deferred work. */ 7246 if (!list_empty(&vha->work_list)) { 7247 unsigned long flags; 7248 bool q = false; 7249 7250 spin_lock_irqsave(&vha->work_lock, flags); 7251 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7252 q = true; 7253 spin_unlock_irqrestore(&vha->work_lock, flags); 7254 if (q) 7255 queue_work(vha->hw->wq, &vha->iocb_work); 7256 } 7257 7258 /* 7259 * FC-NVME 7260 * see if the active AEN count has changed from what was last reported. 7261 */ 7262 if (!vha->vp_idx && 7263 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) && 7264 ha->zio_mode == QLA_ZIO_MODE_6 && 7265 !ha->flags.host_shutting_down) { 7266 ql_log(ql_log_info, vha, 0x3002, 7267 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7268 ha->nvme_last_rptd_aen); 7269 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7270 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7271 start_dpc++; 7272 } 7273 7274 if (!vha->vp_idx && 7275 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 7276 (ha->zio_mode == QLA_ZIO_MODE_6) && 7277 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 7278 ql_log(ql_log_info, vha, 0x3002, 7279 "Sched: Set ZIO exchange threshold to %d.\n", 7280 ha->last_zio_threshold); 7281 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7282 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7283 start_dpc++; 7284 } 7285 7286 /* Schedule the DPC routine if needed */ 7287 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7288 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7289 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7290 start_dpc || 7291 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7292 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7293 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7294 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7295 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7296 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7297 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7298 ql_dbg(ql_dbg_timer, vha, 0x600b, 7299 "isp_abort_needed=%d loop_resync_needed=%d " 7300 "fcport_update_needed=%d start_dpc=%d " 7301 "reset_marker_needed=%d", 7302 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7303 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7304 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7305 start_dpc, 7306 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7307 ql_dbg(ql_dbg_timer, vha, 0x600c, 7308 "beacon_blink_needed=%d isp_unrecoverable=%d " 7309 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7310 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7311 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7312 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7313 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7314 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7315 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7316 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7317 qla2xxx_wake_dpc(vha); 7318 } 7319 7320 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7321 } 7322 7323 /* Firmware interface routines. */ 7324 7325 #define FW_ISP21XX 0 7326 #define FW_ISP22XX 1 7327 #define FW_ISP2300 2 7328 #define FW_ISP2322 3 7329 #define FW_ISP24XX 4 7330 #define FW_ISP25XX 5 7331 #define FW_ISP81XX 6 7332 #define FW_ISP82XX 7 7333 #define FW_ISP2031 8 7334 #define FW_ISP8031 9 7335 #define FW_ISP27XX 10 7336 #define FW_ISP28XX 11 7337 7338 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7339 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7340 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7341 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7342 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7343 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7344 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7345 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7346 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7347 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7348 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7349 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7350 7351 7352 static DEFINE_MUTEX(qla_fw_lock); 7353 7354 static struct fw_blob qla_fw_blobs[] = { 7355 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7356 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7357 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7358 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7359 { .name = FW_FILE_ISP24XX, }, 7360 { .name = FW_FILE_ISP25XX, }, 7361 { .name = FW_FILE_ISP81XX, }, 7362 { .name = FW_FILE_ISP82XX, }, 7363 { .name = FW_FILE_ISP2031, }, 7364 { .name = FW_FILE_ISP8031, }, 7365 { .name = FW_FILE_ISP27XX, }, 7366 { .name = FW_FILE_ISP28XX, }, 7367 { .name = NULL, }, 7368 }; 7369 7370 struct fw_blob * 7371 qla2x00_request_firmware(scsi_qla_host_t *vha) 7372 { 7373 struct qla_hw_data *ha = vha->hw; 7374 struct fw_blob *blob; 7375 7376 if (IS_QLA2100(ha)) { 7377 blob = &qla_fw_blobs[FW_ISP21XX]; 7378 } else if (IS_QLA2200(ha)) { 7379 blob = &qla_fw_blobs[FW_ISP22XX]; 7380 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7381 blob = &qla_fw_blobs[FW_ISP2300]; 7382 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7383 blob = &qla_fw_blobs[FW_ISP2322]; 7384 } else if (IS_QLA24XX_TYPE(ha)) { 7385 blob = &qla_fw_blobs[FW_ISP24XX]; 7386 } else if (IS_QLA25XX(ha)) { 7387 blob = &qla_fw_blobs[FW_ISP25XX]; 7388 } else if (IS_QLA81XX(ha)) { 7389 blob = &qla_fw_blobs[FW_ISP81XX]; 7390 } else if (IS_QLA82XX(ha)) { 7391 blob = &qla_fw_blobs[FW_ISP82XX]; 7392 } else if (IS_QLA2031(ha)) { 7393 blob = &qla_fw_blobs[FW_ISP2031]; 7394 } else if (IS_QLA8031(ha)) { 7395 blob = &qla_fw_blobs[FW_ISP8031]; 7396 } else if (IS_QLA27XX(ha)) { 7397 blob = &qla_fw_blobs[FW_ISP27XX]; 7398 } else if (IS_QLA28XX(ha)) { 7399 blob = &qla_fw_blobs[FW_ISP28XX]; 7400 } else { 7401 return NULL; 7402 } 7403 7404 if (!blob->name) 7405 return NULL; 7406 7407 mutex_lock(&qla_fw_lock); 7408 if (blob->fw) 7409 goto out; 7410 7411 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7412 ql_log(ql_log_warn, vha, 0x0063, 7413 "Failed to load firmware image (%s).\n", blob->name); 7414 blob->fw = NULL; 7415 blob = NULL; 7416 } 7417 7418 out: 7419 mutex_unlock(&qla_fw_lock); 7420 return blob; 7421 } 7422 7423 static void 7424 qla2x00_release_firmware(void) 7425 { 7426 struct fw_blob *blob; 7427 7428 mutex_lock(&qla_fw_lock); 7429 for (blob = qla_fw_blobs; blob->name; blob++) 7430 release_firmware(blob->fw); 7431 mutex_unlock(&qla_fw_lock); 7432 } 7433 7434 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7435 { 7436 struct qla_hw_data *ha = vha->hw; 7437 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7438 struct qla_qpair *qpair = NULL; 7439 struct scsi_qla_host *vp; 7440 fc_port_t *fcport; 7441 int i; 7442 unsigned long flags; 7443 7444 ha->chip_reset++; 7445 7446 ha->base_qpair->chip_reset = ha->chip_reset; 7447 for (i = 0; i < ha->max_qpairs; i++) { 7448 if (ha->queue_pair_map[i]) 7449 ha->queue_pair_map[i]->chip_reset = 7450 ha->base_qpair->chip_reset; 7451 } 7452 7453 /* purge MBox commands */ 7454 if (atomic_read(&ha->num_pend_mbx_stage3)) { 7455 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 7456 complete(&ha->mbx_intr_comp); 7457 } 7458 7459 i = 0; 7460 7461 while (atomic_read(&ha->num_pend_mbx_stage3) || 7462 atomic_read(&ha->num_pend_mbx_stage2) || 7463 atomic_read(&ha->num_pend_mbx_stage1)) { 7464 msleep(20); 7465 i++; 7466 if (i > 50) 7467 break; 7468 } 7469 7470 ha->flags.purge_mbox = 0; 7471 7472 mutex_lock(&ha->mq_lock); 7473 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7474 qpair->online = 0; 7475 mutex_unlock(&ha->mq_lock); 7476 7477 qla2x00_mark_all_devices_lost(vha); 7478 7479 spin_lock_irqsave(&ha->vport_slock, flags); 7480 list_for_each_entry(vp, &ha->vp_list, list) { 7481 atomic_inc(&vp->vref_count); 7482 spin_unlock_irqrestore(&ha->vport_slock, flags); 7483 qla2x00_mark_all_devices_lost(vp); 7484 spin_lock_irqsave(&ha->vport_slock, flags); 7485 atomic_dec(&vp->vref_count); 7486 } 7487 spin_unlock_irqrestore(&ha->vport_slock, flags); 7488 7489 /* Clear all async request states across all VPs. */ 7490 list_for_each_entry(fcport, &vha->vp_fcports, list) 7491 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7492 7493 spin_lock_irqsave(&ha->vport_slock, flags); 7494 list_for_each_entry(vp, &ha->vp_list, list) { 7495 atomic_inc(&vp->vref_count); 7496 spin_unlock_irqrestore(&ha->vport_slock, flags); 7497 list_for_each_entry(fcport, &vp->vp_fcports, list) 7498 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7499 spin_lock_irqsave(&ha->vport_slock, flags); 7500 atomic_dec(&vp->vref_count); 7501 } 7502 spin_unlock_irqrestore(&ha->vport_slock, flags); 7503 } 7504 7505 7506 static pci_ers_result_t 7507 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7508 { 7509 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7510 struct qla_hw_data *ha = vha->hw; 7511 7512 ql_dbg(ql_dbg_aer, vha, 0x9000, 7513 "PCI error detected, state %x.\n", state); 7514 7515 if (!atomic_read(&pdev->enable_cnt)) { 7516 ql_log(ql_log_info, vha, 0xffff, 7517 "PCI device is disabled,state %x\n", state); 7518 return PCI_ERS_RESULT_NEED_RESET; 7519 } 7520 7521 switch (state) { 7522 case pci_channel_io_normal: 7523 ha->flags.eeh_busy = 0; 7524 if (ql2xmqsupport || ql2xnvmeenable) { 7525 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7526 qla2xxx_wake_dpc(vha); 7527 } 7528 return PCI_ERS_RESULT_CAN_RECOVER; 7529 case pci_channel_io_frozen: 7530 ha->flags.eeh_busy = 1; 7531 qla_pci_error_cleanup(vha); 7532 return PCI_ERS_RESULT_NEED_RESET; 7533 case pci_channel_io_perm_failure: 7534 ha->flags.pci_channel_io_perm_failure = 1; 7535 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7536 if (ql2xmqsupport || ql2xnvmeenable) { 7537 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7538 qla2xxx_wake_dpc(vha); 7539 } 7540 return PCI_ERS_RESULT_DISCONNECT; 7541 } 7542 return PCI_ERS_RESULT_NEED_RESET; 7543 } 7544 7545 static pci_ers_result_t 7546 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7547 { 7548 int risc_paused = 0; 7549 uint32_t stat; 7550 unsigned long flags; 7551 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7552 struct qla_hw_data *ha = base_vha->hw; 7553 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7554 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7555 7556 if (IS_QLA82XX(ha)) 7557 return PCI_ERS_RESULT_RECOVERED; 7558 7559 spin_lock_irqsave(&ha->hardware_lock, flags); 7560 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7561 stat = rd_reg_word(®->hccr); 7562 if (stat & HCCR_RISC_PAUSE) 7563 risc_paused = 1; 7564 } else if (IS_QLA23XX(ha)) { 7565 stat = rd_reg_dword(®->u.isp2300.host_status); 7566 if (stat & HSR_RISC_PAUSED) 7567 risc_paused = 1; 7568 } else if (IS_FWI2_CAPABLE(ha)) { 7569 stat = rd_reg_dword(®24->host_status); 7570 if (stat & HSRX_RISC_PAUSED) 7571 risc_paused = 1; 7572 } 7573 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7574 7575 if (risc_paused) { 7576 ql_log(ql_log_info, base_vha, 0x9003, 7577 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7578 qla2xxx_dump_fw(base_vha); 7579 7580 return PCI_ERS_RESULT_NEED_RESET; 7581 } else 7582 return PCI_ERS_RESULT_RECOVERED; 7583 } 7584 7585 static pci_ers_result_t 7586 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7587 { 7588 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7589 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7590 struct qla_hw_data *ha = base_vha->hw; 7591 int rc; 7592 struct qla_qpair *qpair = NULL; 7593 7594 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 7595 "Slot Reset.\n"); 7596 7597 /* Workaround: qla2xxx driver which access hardware earlier 7598 * needs error state to be pci_channel_io_online. 7599 * Otherwise mailbox command timesout. 7600 */ 7601 pdev->error_state = pci_channel_io_normal; 7602 7603 pci_restore_state(pdev); 7604 7605 /* pci_restore_state() clears the saved_state flag of the device 7606 * save restored state which resets saved_state flag 7607 */ 7608 pci_save_state(pdev); 7609 7610 if (ha->mem_only) 7611 rc = pci_enable_device_mem(pdev); 7612 else 7613 rc = pci_enable_device(pdev); 7614 7615 if (rc) { 7616 ql_log(ql_log_warn, base_vha, 0x9005, 7617 "Can't re-enable PCI device after reset.\n"); 7618 goto exit_slot_reset; 7619 } 7620 7621 7622 if (ha->isp_ops->pci_config(base_vha)) 7623 goto exit_slot_reset; 7624 7625 mutex_lock(&ha->mq_lock); 7626 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7627 qpair->online = 1; 7628 mutex_unlock(&ha->mq_lock); 7629 7630 base_vha->flags.online = 1; 7631 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7632 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7633 ret = PCI_ERS_RESULT_RECOVERED; 7634 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7635 7636 7637 exit_slot_reset: 7638 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7639 "slot_reset return %x.\n", ret); 7640 7641 return ret; 7642 } 7643 7644 static void 7645 qla2xxx_pci_resume(struct pci_dev *pdev) 7646 { 7647 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7648 struct qla_hw_data *ha = base_vha->hw; 7649 int ret; 7650 7651 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7652 "pci_resume.\n"); 7653 7654 ha->flags.eeh_busy = 0; 7655 7656 ret = qla2x00_wait_for_hba_online(base_vha); 7657 if (ret != QLA_SUCCESS) { 7658 ql_log(ql_log_fatal, base_vha, 0x9002, 7659 "The device failed to resume I/O from slot/link_reset.\n"); 7660 } 7661 } 7662 7663 static void 7664 qla_pci_reset_prepare(struct pci_dev *pdev) 7665 { 7666 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7667 struct qla_hw_data *ha = base_vha->hw; 7668 struct qla_qpair *qpair; 7669 7670 ql_log(ql_log_warn, base_vha, 0xffff, 7671 "%s.\n", __func__); 7672 7673 /* 7674 * PCI FLR/function reset is about to reset the 7675 * slot. Stop the chip to stop all DMA access. 7676 * It is assumed that pci_reset_done will be called 7677 * after FLR to resume Chip operation. 7678 */ 7679 ha->flags.eeh_busy = 1; 7680 mutex_lock(&ha->mq_lock); 7681 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7682 qpair->online = 0; 7683 mutex_unlock(&ha->mq_lock); 7684 7685 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7686 qla2x00_abort_isp_cleanup(base_vha); 7687 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7688 } 7689 7690 static void 7691 qla_pci_reset_done(struct pci_dev *pdev) 7692 { 7693 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7694 struct qla_hw_data *ha = base_vha->hw; 7695 struct qla_qpair *qpair; 7696 7697 ql_log(ql_log_warn, base_vha, 0xffff, 7698 "%s.\n", __func__); 7699 7700 /* 7701 * FLR just completed by PCI layer. Resume adapter 7702 */ 7703 ha->flags.eeh_busy = 0; 7704 mutex_lock(&ha->mq_lock); 7705 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7706 qpair->online = 1; 7707 mutex_unlock(&ha->mq_lock); 7708 7709 base_vha->flags.online = 1; 7710 ha->isp_ops->abort_isp(base_vha); 7711 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7712 } 7713 7714 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7715 { 7716 int rc; 7717 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7718 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7719 7720 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7721 rc = blk_mq_map_queues(qmap); 7722 else 7723 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7724 return rc; 7725 } 7726 7727 struct scsi_host_template qla2xxx_driver_template = { 7728 .module = THIS_MODULE, 7729 .name = QLA2XXX_DRIVER_NAME, 7730 .queuecommand = qla2xxx_queuecommand, 7731 7732 .eh_timed_out = fc_eh_timed_out, 7733 .eh_abort_handler = qla2xxx_eh_abort, 7734 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7735 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7736 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7737 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7738 7739 .slave_configure = qla2xxx_slave_configure, 7740 7741 .slave_alloc = qla2xxx_slave_alloc, 7742 .slave_destroy = qla2xxx_slave_destroy, 7743 .scan_finished = qla2xxx_scan_finished, 7744 .scan_start = qla2xxx_scan_start, 7745 .change_queue_depth = scsi_change_queue_depth, 7746 .map_queues = qla2xxx_map_queues, 7747 .this_id = -1, 7748 .cmd_per_lun = 3, 7749 .sg_tablesize = SG_ALL, 7750 7751 .max_sectors = 0xFFFF, 7752 .shost_attrs = qla2x00_host_attrs, 7753 7754 .supported_mode = MODE_INITIATOR, 7755 .track_queue_depth = 1, 7756 .cmd_size = sizeof(srb_t), 7757 }; 7758 7759 static const struct pci_error_handlers qla2xxx_err_handler = { 7760 .error_detected = qla2xxx_pci_error_detected, 7761 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7762 .slot_reset = qla2xxx_pci_slot_reset, 7763 .resume = qla2xxx_pci_resume, 7764 .reset_prepare = qla_pci_reset_prepare, 7765 .reset_done = qla_pci_reset_done, 7766 }; 7767 7768 static struct pci_device_id qla2xxx_pci_tbl[] = { 7769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7776 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7777 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7778 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7779 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7780 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7781 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7782 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7783 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7784 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7785 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7786 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7787 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7788 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7789 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7790 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7791 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7792 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7793 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7794 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7795 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7796 { 0 }, 7797 }; 7798 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7799 7800 static struct pci_driver qla2xxx_pci_driver = { 7801 .name = QLA2XXX_DRIVER_NAME, 7802 .driver = { 7803 .owner = THIS_MODULE, 7804 }, 7805 .id_table = qla2xxx_pci_tbl, 7806 .probe = qla2x00_probe_one, 7807 .remove = qla2x00_remove_one, 7808 .shutdown = qla2x00_shutdown, 7809 .err_handler = &qla2xxx_err_handler, 7810 }; 7811 7812 static const struct file_operations apidev_fops = { 7813 .owner = THIS_MODULE, 7814 .llseek = noop_llseek, 7815 }; 7816 7817 /** 7818 * qla2x00_module_init - Module initialization. 7819 **/ 7820 static int __init 7821 qla2x00_module_init(void) 7822 { 7823 int ret = 0; 7824 7825 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 7826 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7827 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7828 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7829 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7830 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 7831 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7832 BUILD_BUG_ON(sizeof(request_t) != 64); 7833 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 7834 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 7835 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 7836 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7837 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 7838 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7839 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7840 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7841 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7842 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7843 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7844 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7845 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344); 7846 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 7847 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 7848 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 7849 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 7850 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 7851 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7852 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 7853 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 7854 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 7855 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 7856 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 7857 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7858 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 7859 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7860 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 7861 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7862 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7863 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 7864 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 7865 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 7866 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 7867 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 7868 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 7869 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7870 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 7871 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 7872 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 7873 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 7874 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 7875 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 7876 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 7877 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 7878 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 7879 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 7880 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 7881 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 7882 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 7883 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 7884 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 7885 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 7886 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 7887 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 7888 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 7889 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 7890 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 7891 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 7892 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 7893 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7894 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 7895 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 7896 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 7897 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7898 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 7899 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7900 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 7901 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 7902 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 7903 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 7904 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 7905 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 7906 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 7907 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 7908 BUILD_BUG_ON(sizeof(target_id_t) != 2); 7909 7910 /* Allocate cache for SRBs. */ 7911 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7912 SLAB_HWCACHE_ALIGN, NULL); 7913 if (srb_cachep == NULL) { 7914 ql_log(ql_log_fatal, NULL, 0x0001, 7915 "Unable to allocate SRB cache...Failing load!.\n"); 7916 return -ENOMEM; 7917 } 7918 7919 /* Initialize target kmem_cache and mem_pools */ 7920 ret = qlt_init(); 7921 if (ret < 0) { 7922 goto destroy_cache; 7923 } else if (ret > 0) { 7924 /* 7925 * If initiator mode is explictly disabled by qlt_init(), 7926 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7927 * performing scsi_scan_target() during LOOP UP event. 7928 */ 7929 qla2xxx_transport_functions.disable_target_scan = 1; 7930 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7931 } 7932 7933 /* Derive version string. */ 7934 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7935 if (ql2xextended_error_logging) 7936 strcat(qla2x00_version_str, "-debug"); 7937 if (ql2xextended_error_logging == 1) 7938 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7939 7940 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7941 qla_insert_tgt_attrs(); 7942 7943 qla2xxx_transport_template = 7944 fc_attach_transport(&qla2xxx_transport_functions); 7945 if (!qla2xxx_transport_template) { 7946 ql_log(ql_log_fatal, NULL, 0x0002, 7947 "fc_attach_transport failed...Failing load!.\n"); 7948 ret = -ENODEV; 7949 goto qlt_exit; 7950 } 7951 7952 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7953 if (apidev_major < 0) { 7954 ql_log(ql_log_fatal, NULL, 0x0003, 7955 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7956 } 7957 7958 qla2xxx_transport_vport_template = 7959 fc_attach_transport(&qla2xxx_transport_vport_functions); 7960 if (!qla2xxx_transport_vport_template) { 7961 ql_log(ql_log_fatal, NULL, 0x0004, 7962 "fc_attach_transport vport failed...Failing load!.\n"); 7963 ret = -ENODEV; 7964 goto unreg_chrdev; 7965 } 7966 ql_log(ql_log_info, NULL, 0x0005, 7967 "QLogic Fibre Channel HBA Driver: %s.\n", 7968 qla2x00_version_str); 7969 ret = pci_register_driver(&qla2xxx_pci_driver); 7970 if (ret) { 7971 ql_log(ql_log_fatal, NULL, 0x0006, 7972 "pci_register_driver failed...ret=%d Failing load!.\n", 7973 ret); 7974 goto release_vport_transport; 7975 } 7976 return ret; 7977 7978 release_vport_transport: 7979 fc_release_transport(qla2xxx_transport_vport_template); 7980 7981 unreg_chrdev: 7982 if (apidev_major >= 0) 7983 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7984 fc_release_transport(qla2xxx_transport_template); 7985 7986 qlt_exit: 7987 qlt_exit(); 7988 7989 destroy_cache: 7990 kmem_cache_destroy(srb_cachep); 7991 return ret; 7992 } 7993 7994 /** 7995 * qla2x00_module_exit - Module cleanup. 7996 **/ 7997 static void __exit 7998 qla2x00_module_exit(void) 7999 { 8000 pci_unregister_driver(&qla2xxx_pci_driver); 8001 qla2x00_release_firmware(); 8002 kmem_cache_destroy(ctx_cachep); 8003 fc_release_transport(qla2xxx_transport_vport_template); 8004 if (apidev_major >= 0) 8005 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8006 fc_release_transport(qla2xxx_transport_template); 8007 qlt_exit(); 8008 kmem_cache_destroy(srb_cachep); 8009 } 8010 8011 module_init(qla2x00_module_init); 8012 module_exit(qla2x00_module_exit); 8013 8014 MODULE_AUTHOR("QLogic Corporation"); 8015 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8016 MODULE_LICENSE("GPL"); 8017 MODULE_VERSION(QLA2XXX_VERSION); 8018 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8019 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8020 MODULE_FIRMWARE(FW_FILE_ISP2300); 8021 MODULE_FIRMWARE(FW_FILE_ISP2322); 8022 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8023 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8024