1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <scsi/scsi_tcq.h> 17 #include <scsi/scsicam.h> 18 #include <scsi/scsi_transport.h> 19 #include <scsi/scsi_transport_fc.h> 20 21 #include "qla_target.h" 22 23 /* 24 * Driver version 25 */ 26 char qla2x00_version_str[40]; 27 28 static int apidev_major; 29 30 /* 31 * SRB allocation cache 32 */ 33 static struct kmem_cache *srb_cachep; 34 35 /* 36 * CT6 CTX allocation cache 37 */ 38 static struct kmem_cache *ctx_cachep; 39 /* 40 * error level for logging 41 */ 42 int ql_errlev = ql_log_all; 43 44 static int ql2xenableclass2; 45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 46 MODULE_PARM_DESC(ql2xenableclass2, 47 "Specify if Class 2 operations are supported from the very " 48 "beginning. Default is 0 - class 2 not supported."); 49 50 51 int ql2xlogintimeout = 20; 52 module_param(ql2xlogintimeout, int, S_IRUGO); 53 MODULE_PARM_DESC(ql2xlogintimeout, 54 "Login timeout value in seconds."); 55 56 int qlport_down_retry; 57 module_param(qlport_down_retry, int, S_IRUGO); 58 MODULE_PARM_DESC(qlport_down_retry, 59 "Maximum number of command retries to a port that returns " 60 "a PORT-DOWN status."); 61 62 int ql2xplogiabsentdevice; 63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 64 MODULE_PARM_DESC(ql2xplogiabsentdevice, 65 "Option to enable PLOGI to devices that are not present after " 66 "a Fabric scan. This is needed for several broken switches. " 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 68 69 int ql2xloginretrycount = 0; 70 module_param(ql2xloginretrycount, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xloginretrycount, 72 "Specify an alternate value for the NVRAM login retry count."); 73 74 int ql2xallocfwdump = 1; 75 module_param(ql2xallocfwdump, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xallocfwdump, 77 "Option to enable allocation of memory for a firmware dump " 78 "during HBA initialization. Memory allocation requirements " 79 "vary by ISP type. Default is 1 - allocate memory."); 80 81 int ql2xextended_error_logging; 82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 83 MODULE_PARM_DESC(ql2xextended_error_logging, 84 "Option to enable extended error logging,\n" 85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 96 "\t\t0x1e400000 - Preferred value for capturing essential " 97 "debug information (equivalent to old " 98 "ql2xextended_error_logging=1).\n" 99 "\t\tDo LOGICAL OR of the value to enable more than one level"); 100 101 int ql2xshiftctondsd = 6; 102 module_param(ql2xshiftctondsd, int, S_IRUGO); 103 MODULE_PARM_DESC(ql2xshiftctondsd, 104 "Set to control shifting of command type processing " 105 "based on total number of SG elements."); 106 107 int ql2xfdmienable=1; 108 module_param(ql2xfdmienable, int, S_IRUGO); 109 MODULE_PARM_DESC(ql2xfdmienable, 110 "Enables FDMI registrations. " 111 "0 - no FDMI. Default is 1 - perform FDMI."); 112 113 #define MAX_Q_DEPTH 32 114 static int ql2xmaxqdepth = MAX_Q_DEPTH; 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 116 MODULE_PARM_DESC(ql2xmaxqdepth, 117 "Maximum queue depth to set for each LUN. " 118 "Default is 32."); 119 120 int ql2xenabledif = 2; 121 module_param(ql2xenabledif, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xenabledif, 123 " Enable T10-CRC-DIF " 124 " Default is 0 - No DIF Support. 1 - Enable it" 125 ", 2 - Enable DIF for all types, except Type 0."); 126 127 int ql2xenablehba_err_chk = 2; 128 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 129 MODULE_PARM_DESC(ql2xenablehba_err_chk, 130 " Enable T10-CRC-DIF Error isolation by HBA:\n" 131 " Default is 1.\n" 132 " 0 -- Error isolation disabled\n" 133 " 1 -- Error isolation enabled only for DIX Type 0\n" 134 " 2 -- Error isolation enabled for all Types\n"); 135 136 int ql2xiidmaenable=1; 137 module_param(ql2xiidmaenable, int, S_IRUGO); 138 MODULE_PARM_DESC(ql2xiidmaenable, 139 "Enables iIDMA settings " 140 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 141 142 int ql2xmaxqueues = 1; 143 module_param(ql2xmaxqueues, int, S_IRUGO); 144 MODULE_PARM_DESC(ql2xmaxqueues, 145 "Enables MQ settings " 146 "Default is 1 for single queue. Set it to number " 147 "of queues in MQ mode."); 148 149 int ql2xmultique_tag; 150 module_param(ql2xmultique_tag, int, S_IRUGO); 151 MODULE_PARM_DESC(ql2xmultique_tag, 152 "Enables CPU affinity settings for the driver " 153 "Default is 0 for no affinity of request and response IO. " 154 "Set it to 1 to turn on the cpu affinity."); 155 156 int ql2xfwloadbin; 157 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 158 MODULE_PARM_DESC(ql2xfwloadbin, 159 "Option to specify location from which to load ISP firmware:.\n" 160 " 2 -- load firmware via the request_firmware() (hotplug).\n" 161 " interface.\n" 162 " 1 -- load firmware from flash.\n" 163 " 0 -- use default semantics.\n"); 164 165 int ql2xetsenable; 166 module_param(ql2xetsenable, int, S_IRUGO); 167 MODULE_PARM_DESC(ql2xetsenable, 168 "Enables firmware ETS burst." 169 "Default is 0 - skip ETS enablement."); 170 171 int ql2xdbwr = 1; 172 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xdbwr, 174 "Option to specify scheme for request queue posting.\n" 175 " 0 -- Regular doorbell.\n" 176 " 1 -- CAMRAM doorbell (faster).\n"); 177 178 int ql2xtargetreset = 1; 179 module_param(ql2xtargetreset, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xtargetreset, 181 "Enable target reset." 182 "Default is 1 - use hw defaults."); 183 184 int ql2xgffidenable; 185 module_param(ql2xgffidenable, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xgffidenable, 187 "Enables GFF_ID checks of port type. " 188 "Default is 0 - Do not use GFF_ID information."); 189 190 int ql2xasynctmfenable; 191 module_param(ql2xasynctmfenable, int, S_IRUGO); 192 MODULE_PARM_DESC(ql2xasynctmfenable, 193 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 194 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 195 196 int ql2xdontresethba; 197 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 198 MODULE_PARM_DESC(ql2xdontresethba, 199 "Option to specify reset behaviour.\n" 200 " 0 (Default) -- Reset on failure.\n" 201 " 1 -- Do not reset on failure.\n"); 202 203 uint ql2xmaxlun = MAX_LUNS; 204 module_param(ql2xmaxlun, uint, S_IRUGO); 205 MODULE_PARM_DESC(ql2xmaxlun, 206 "Defines the maximum LU number to register with the SCSI " 207 "midlayer. Default is 65535."); 208 209 int ql2xmdcapmask = 0x1F; 210 module_param(ql2xmdcapmask, int, S_IRUGO); 211 MODULE_PARM_DESC(ql2xmdcapmask, 212 "Set the Minidump driver capture mask level. " 213 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 214 215 int ql2xmdenable = 1; 216 module_param(ql2xmdenable, int, S_IRUGO); 217 MODULE_PARM_DESC(ql2xmdenable, 218 "Enable/disable MiniDump. " 219 "0 - MiniDump disabled. " 220 "1 (Default) - MiniDump enabled."); 221 222 /* 223 * SCSI host template entry points 224 */ 225 static int qla2xxx_slave_configure(struct scsi_device * device); 226 static int qla2xxx_slave_alloc(struct scsi_device *); 227 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 228 static void qla2xxx_scan_start(struct Scsi_Host *); 229 static void qla2xxx_slave_destroy(struct scsi_device *); 230 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 231 static int qla2xxx_eh_abort(struct scsi_cmnd *); 232 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 233 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 234 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 235 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 236 237 static int qla2x00_change_queue_depth(struct scsi_device *, int, int); 238 static int qla2x00_change_queue_type(struct scsi_device *, int); 239 static void qla2x00_free_device(scsi_qla_host_t *); 240 241 struct scsi_host_template qla2xxx_driver_template = { 242 .module = THIS_MODULE, 243 .name = QLA2XXX_DRIVER_NAME, 244 .queuecommand = qla2xxx_queuecommand, 245 246 .eh_abort_handler = qla2xxx_eh_abort, 247 .eh_device_reset_handler = qla2xxx_eh_device_reset, 248 .eh_target_reset_handler = qla2xxx_eh_target_reset, 249 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 250 .eh_host_reset_handler = qla2xxx_eh_host_reset, 251 252 .slave_configure = qla2xxx_slave_configure, 253 254 .slave_alloc = qla2xxx_slave_alloc, 255 .slave_destroy = qla2xxx_slave_destroy, 256 .scan_finished = qla2xxx_scan_finished, 257 .scan_start = qla2xxx_scan_start, 258 .change_queue_depth = qla2x00_change_queue_depth, 259 .change_queue_type = qla2x00_change_queue_type, 260 .this_id = -1, 261 .cmd_per_lun = 3, 262 .use_clustering = ENABLE_CLUSTERING, 263 .sg_tablesize = SG_ALL, 264 265 .max_sectors = 0xFFFF, 266 .shost_attrs = qla2x00_host_attrs, 267 268 .supported_mode = MODE_INITIATOR, 269 }; 270 271 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 272 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 273 274 /* TODO Convert to inlines 275 * 276 * Timer routines 277 */ 278 279 __inline__ void 280 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 281 { 282 init_timer(&vha->timer); 283 vha->timer.expires = jiffies + interval * HZ; 284 vha->timer.data = (unsigned long)vha; 285 vha->timer.function = (void (*)(unsigned long))func; 286 add_timer(&vha->timer); 287 vha->timer_active = 1; 288 } 289 290 static inline void 291 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 292 { 293 /* Currently used for 82XX only. */ 294 if (vha->device_flags & DFLG_DEV_FAILED) { 295 ql_dbg(ql_dbg_timer, vha, 0x600d, 296 "Device in a failed state, returning.\n"); 297 return; 298 } 299 300 mod_timer(&vha->timer, jiffies + interval * HZ); 301 } 302 303 static __inline__ void 304 qla2x00_stop_timer(scsi_qla_host_t *vha) 305 { 306 del_timer_sync(&vha->timer); 307 vha->timer_active = 0; 308 } 309 310 static int qla2x00_do_dpc(void *data); 311 312 static void qla2x00_rst_aen(scsi_qla_host_t *); 313 314 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 315 struct req_que **, struct rsp_que **); 316 static void qla2x00_free_fw_dump(struct qla_hw_data *); 317 static void qla2x00_mem_free(struct qla_hw_data *); 318 319 /* -------------------------------------------------------------------------- */ 320 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 321 struct rsp_que *rsp) 322 { 323 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 324 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 325 GFP_KERNEL); 326 if (!ha->req_q_map) { 327 ql_log(ql_log_fatal, vha, 0x003b, 328 "Unable to allocate memory for request queue ptrs.\n"); 329 goto fail_req_map; 330 } 331 332 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 333 GFP_KERNEL); 334 if (!ha->rsp_q_map) { 335 ql_log(ql_log_fatal, vha, 0x003c, 336 "Unable to allocate memory for response queue ptrs.\n"); 337 goto fail_rsp_map; 338 } 339 /* 340 * Make sure we record at least the request and response queue zero in 341 * case we need to free them if part of the probe fails. 342 */ 343 ha->rsp_q_map[0] = rsp; 344 ha->req_q_map[0] = req; 345 set_bit(0, ha->rsp_qid_map); 346 set_bit(0, ha->req_qid_map); 347 return 1; 348 349 fail_rsp_map: 350 kfree(ha->req_q_map); 351 ha->req_q_map = NULL; 352 fail_req_map: 353 return -ENOMEM; 354 } 355 356 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 357 { 358 if (IS_QLAFX00(ha)) { 359 if (req && req->ring_fx00) 360 dma_free_coherent(&ha->pdev->dev, 361 (req->length_fx00 + 1) * sizeof(request_t), 362 req->ring_fx00, req->dma_fx00); 363 } else if (req && req->ring) 364 dma_free_coherent(&ha->pdev->dev, 365 (req->length + 1) * sizeof(request_t), 366 req->ring, req->dma); 367 368 if (req) 369 kfree(req->outstanding_cmds); 370 371 kfree(req); 372 req = NULL; 373 } 374 375 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 376 { 377 if (IS_QLAFX00(ha)) { 378 if (rsp && rsp->ring) 379 dma_free_coherent(&ha->pdev->dev, 380 (rsp->length_fx00 + 1) * sizeof(request_t), 381 rsp->ring_fx00, rsp->dma_fx00); 382 } else if (rsp && rsp->ring) { 383 dma_free_coherent(&ha->pdev->dev, 384 (rsp->length + 1) * sizeof(response_t), 385 rsp->ring, rsp->dma); 386 } 387 kfree(rsp); 388 rsp = NULL; 389 } 390 391 static void qla2x00_free_queues(struct qla_hw_data *ha) 392 { 393 struct req_que *req; 394 struct rsp_que *rsp; 395 int cnt; 396 397 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 398 req = ha->req_q_map[cnt]; 399 qla2x00_free_req_que(ha, req); 400 } 401 kfree(ha->req_q_map); 402 ha->req_q_map = NULL; 403 404 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 405 rsp = ha->rsp_q_map[cnt]; 406 qla2x00_free_rsp_que(ha, rsp); 407 } 408 kfree(ha->rsp_q_map); 409 ha->rsp_q_map = NULL; 410 } 411 412 static int qla25xx_setup_mode(struct scsi_qla_host *vha) 413 { 414 uint16_t options = 0; 415 int ques, req, ret; 416 struct qla_hw_data *ha = vha->hw; 417 418 if (!(ha->fw_attributes & BIT_6)) { 419 ql_log(ql_log_warn, vha, 0x00d8, 420 "Firmware is not multi-queue capable.\n"); 421 goto fail; 422 } 423 if (ql2xmultique_tag) { 424 /* create a request queue for IO */ 425 options |= BIT_7; 426 req = qla25xx_create_req_que(ha, options, 0, 0, -1, 427 QLA_DEFAULT_QUE_QOS); 428 if (!req) { 429 ql_log(ql_log_warn, vha, 0x00e0, 430 "Failed to create request queue.\n"); 431 goto fail; 432 } 433 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 434 vha->req = ha->req_q_map[req]; 435 options |= BIT_1; 436 for (ques = 1; ques < ha->max_rsp_queues; ques++) { 437 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); 438 if (!ret) { 439 ql_log(ql_log_warn, vha, 0x00e8, 440 "Failed to create response queue.\n"); 441 goto fail2; 442 } 443 } 444 ha->flags.cpu_affinity_enabled = 1; 445 ql_dbg(ql_dbg_multiq, vha, 0xc007, 446 "CPU affinity mode enalbed, " 447 "no. of response queues:%d no. of request queues:%d.\n", 448 ha->max_rsp_queues, ha->max_req_queues); 449 ql_dbg(ql_dbg_init, vha, 0x00e9, 450 "CPU affinity mode enalbed, " 451 "no. of response queues:%d no. of request queues:%d.\n", 452 ha->max_rsp_queues, ha->max_req_queues); 453 } 454 return 0; 455 fail2: 456 qla25xx_delete_queues(vha); 457 destroy_workqueue(ha->wq); 458 ha->wq = NULL; 459 vha->req = ha->req_q_map[0]; 460 fail: 461 ha->mqenable = 0; 462 kfree(ha->req_q_map); 463 kfree(ha->rsp_q_map); 464 ha->max_req_queues = ha->max_rsp_queues = 1; 465 return 1; 466 } 467 468 static char * 469 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 470 { 471 struct qla_hw_data *ha = vha->hw; 472 static char *pci_bus_modes[] = { 473 "33", "66", "100", "133", 474 }; 475 uint16_t pci_bus; 476 477 strcpy(str, "PCI"); 478 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 479 if (pci_bus) { 480 strcat(str, "-X ("); 481 strcat(str, pci_bus_modes[pci_bus]); 482 } else { 483 pci_bus = (ha->pci_attr & BIT_8) >> 8; 484 strcat(str, " ("); 485 strcat(str, pci_bus_modes[pci_bus]); 486 } 487 strcat(str, " MHz)"); 488 489 return (str); 490 } 491 492 static char * 493 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 494 { 495 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 496 struct qla_hw_data *ha = vha->hw; 497 uint32_t pci_bus; 498 499 if (pci_is_pcie(ha->pdev)) { 500 char lwstr[6]; 501 uint32_t lstat, lspeed, lwidth; 502 503 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 504 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 505 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 506 507 strcpy(str, "PCIe ("); 508 switch (lspeed) { 509 case 1: 510 strcat(str, "2.5GT/s "); 511 break; 512 case 2: 513 strcat(str, "5.0GT/s "); 514 break; 515 case 3: 516 strcat(str, "8.0GT/s "); 517 break; 518 default: 519 strcat(str, "<unknown> "); 520 break; 521 } 522 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 523 strcat(str, lwstr); 524 525 return str; 526 } 527 528 strcpy(str, "PCI"); 529 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 530 if (pci_bus == 0 || pci_bus == 8) { 531 strcat(str, " ("); 532 strcat(str, pci_bus_modes[pci_bus >> 3]); 533 } else { 534 strcat(str, "-X "); 535 if (pci_bus & BIT_2) 536 strcat(str, "Mode 2"); 537 else 538 strcat(str, "Mode 1"); 539 strcat(str, " ("); 540 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 541 } 542 strcat(str, " MHz)"); 543 544 return str; 545 } 546 547 static char * 548 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) 549 { 550 char un_str[10]; 551 struct qla_hw_data *ha = vha->hw; 552 553 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, 554 ha->fw_minor_version, 555 ha->fw_subminor_version); 556 557 if (ha->fw_attributes & BIT_9) { 558 strcat(str, "FLX"); 559 return (str); 560 } 561 562 switch (ha->fw_attributes & 0xFF) { 563 case 0x7: 564 strcat(str, "EF"); 565 break; 566 case 0x17: 567 strcat(str, "TP"); 568 break; 569 case 0x37: 570 strcat(str, "IP"); 571 break; 572 case 0x77: 573 strcat(str, "VI"); 574 break; 575 default: 576 sprintf(un_str, "(%x)", ha->fw_attributes); 577 strcat(str, un_str); 578 break; 579 } 580 if (ha->fw_attributes & 0x100) 581 strcat(str, "X"); 582 583 return (str); 584 } 585 586 static char * 587 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) 588 { 589 struct qla_hw_data *ha = vha->hw; 590 591 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, 592 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 593 return str; 594 } 595 596 void 597 qla2x00_sp_free_dma(void *vha, void *ptr) 598 { 599 srb_t *sp = (srb_t *)ptr; 600 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 601 struct qla_hw_data *ha = sp->fcport->vha->hw; 602 void *ctx = GET_CMD_CTX_SP(sp); 603 604 if (sp->flags & SRB_DMA_VALID) { 605 scsi_dma_unmap(cmd); 606 sp->flags &= ~SRB_DMA_VALID; 607 } 608 609 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 610 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 611 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 612 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 613 } 614 615 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 616 /* List assured to be having elements */ 617 qla2x00_clean_dsd_pool(ha, sp); 618 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 619 } 620 621 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 622 dma_pool_free(ha->dl_dma_pool, ctx, 623 ((struct crc_context *)ctx)->crc_ctx_dma); 624 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 625 } 626 627 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 628 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 629 630 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 631 ctx1->fcp_cmnd_dma); 632 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 633 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 634 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 635 mempool_free(ctx1, ha->ctx_mempool); 636 ctx1 = NULL; 637 } 638 639 CMD_SP(cmd) = NULL; 640 qla2x00_rel_sp(sp->fcport->vha, sp); 641 } 642 643 static void 644 qla2x00_sp_compl(void *data, void *ptr, int res) 645 { 646 struct qla_hw_data *ha = (struct qla_hw_data *)data; 647 srb_t *sp = (srb_t *)ptr; 648 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 649 650 cmd->result = res; 651 652 if (atomic_read(&sp->ref_count) == 0) { 653 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, 654 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 655 sp, GET_CMD_SP(sp)); 656 if (ql2xextended_error_logging & ql_dbg_io) 657 BUG(); 658 return; 659 } 660 if (!atomic_dec_and_test(&sp->ref_count)) 661 return; 662 663 qla2x00_sp_free_dma(ha, sp); 664 cmd->scsi_done(cmd); 665 } 666 667 /* If we are SP1 here, we need to still take and release the host_lock as SP1 668 * does not have the changes necessary to avoid taking host->host_lock. 669 */ 670 static int 671 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 672 { 673 scsi_qla_host_t *vha = shost_priv(host); 674 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 675 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 676 struct qla_hw_data *ha = vha->hw; 677 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 678 srb_t *sp; 679 int rval; 680 681 if (ha->flags.eeh_busy) { 682 if (ha->flags.pci_channel_io_perm_failure) { 683 ql_dbg(ql_dbg_aer, vha, 0x9010, 684 "PCI Channel IO permanent failure, exiting " 685 "cmd=%p.\n", cmd); 686 cmd->result = DID_NO_CONNECT << 16; 687 } else { 688 ql_dbg(ql_dbg_aer, vha, 0x9011, 689 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 690 cmd->result = DID_REQUEUE << 16; 691 } 692 goto qc24_fail_command; 693 } 694 695 rval = fc_remote_port_chkready(rport); 696 if (rval) { 697 cmd->result = rval; 698 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 699 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 700 cmd, rval); 701 goto qc24_fail_command; 702 } 703 704 if (!vha->flags.difdix_supported && 705 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 706 ql_dbg(ql_dbg_io, vha, 0x3004, 707 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 708 cmd); 709 cmd->result = DID_NO_CONNECT << 16; 710 goto qc24_fail_command; 711 } 712 713 if (!fcport) { 714 cmd->result = DID_NO_CONNECT << 16; 715 goto qc24_fail_command; 716 } 717 718 if (atomic_read(&fcport->state) != FCS_ONLINE) { 719 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 720 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 721 ql_dbg(ql_dbg_io, vha, 0x3005, 722 "Returning DNC, fcport_state=%d loop_state=%d.\n", 723 atomic_read(&fcport->state), 724 atomic_read(&base_vha->loop_state)); 725 cmd->result = DID_NO_CONNECT << 16; 726 goto qc24_fail_command; 727 } 728 goto qc24_target_busy; 729 } 730 731 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 732 if (!sp) 733 goto qc24_host_busy; 734 735 sp->u.scmd.cmd = cmd; 736 sp->type = SRB_SCSI_CMD; 737 atomic_set(&sp->ref_count, 1); 738 CMD_SP(cmd) = (void *)sp; 739 sp->free = qla2x00_sp_free_dma; 740 sp->done = qla2x00_sp_compl; 741 742 rval = ha->isp_ops->start_scsi(sp); 743 if (rval != QLA_SUCCESS) { 744 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 745 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 746 goto qc24_host_busy_free_sp; 747 } 748 749 return 0; 750 751 qc24_host_busy_free_sp: 752 qla2x00_sp_free_dma(ha, sp); 753 754 qc24_host_busy: 755 return SCSI_MLQUEUE_HOST_BUSY; 756 757 qc24_target_busy: 758 return SCSI_MLQUEUE_TARGET_BUSY; 759 760 qc24_fail_command: 761 cmd->scsi_done(cmd); 762 763 return 0; 764 } 765 766 /* 767 * qla2x00_eh_wait_on_command 768 * Waits for the command to be returned by the Firmware for some 769 * max time. 770 * 771 * Input: 772 * cmd = Scsi Command to wait on. 773 * 774 * Return: 775 * Not Found : 0 776 * Found : 1 777 */ 778 static int 779 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 780 { 781 #define ABORT_POLLING_PERIOD 1000 782 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) 783 unsigned long wait_iter = ABORT_WAIT_ITER; 784 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 785 struct qla_hw_data *ha = vha->hw; 786 int ret = QLA_SUCCESS; 787 788 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 789 ql_dbg(ql_dbg_taskm, vha, 0x8005, 790 "Return:eh_wait.\n"); 791 return ret; 792 } 793 794 while (CMD_SP(cmd) && wait_iter--) { 795 msleep(ABORT_POLLING_PERIOD); 796 } 797 if (CMD_SP(cmd)) 798 ret = QLA_FUNCTION_FAILED; 799 800 return ret; 801 } 802 803 /* 804 * qla2x00_wait_for_hba_online 805 * Wait till the HBA is online after going through 806 * <= MAX_RETRIES_OF_ISP_ABORT or 807 * finally HBA is disabled ie marked offline 808 * 809 * Input: 810 * ha - pointer to host adapter structure 811 * 812 * Note: 813 * Does context switching-Release SPIN_LOCK 814 * (if any) before calling this routine. 815 * 816 * Return: 817 * Success (Adapter is online) : 0 818 * Failed (Adapter is offline/disabled) : 1 819 */ 820 int 821 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 822 { 823 int return_status; 824 unsigned long wait_online; 825 struct qla_hw_data *ha = vha->hw; 826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 827 828 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 829 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 830 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 831 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 832 ha->dpc_active) && time_before(jiffies, wait_online)) { 833 834 msleep(1000); 835 } 836 if (base_vha->flags.online) 837 return_status = QLA_SUCCESS; 838 else 839 return_status = QLA_FUNCTION_FAILED; 840 841 return (return_status); 842 } 843 844 /* 845 * qla2x00_wait_for_reset_ready 846 * Wait till the HBA is online after going through 847 * <= MAX_RETRIES_OF_ISP_ABORT or 848 * finally HBA is disabled ie marked offline or flash 849 * operations are in progress. 850 * 851 * Input: 852 * ha - pointer to host adapter structure 853 * 854 * Note: 855 * Does context switching-Release SPIN_LOCK 856 * (if any) before calling this routine. 857 * 858 * Return: 859 * Success (Adapter is online/no flash ops) : 0 860 * Failed (Adapter is offline/disabled/flash ops in progress) : 1 861 */ 862 static int 863 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) 864 { 865 int return_status; 866 unsigned long wait_online; 867 struct qla_hw_data *ha = vha->hw; 868 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 869 870 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 871 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 872 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 873 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 874 ha->optrom_state != QLA_SWAITING || 875 ha->dpc_active) && time_before(jiffies, wait_online)) 876 msleep(1000); 877 878 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) 879 return_status = QLA_SUCCESS; 880 else 881 return_status = QLA_FUNCTION_FAILED; 882 883 ql_dbg(ql_dbg_taskm, vha, 0x8019, 884 "%s return status=%d.\n", __func__, return_status); 885 886 return return_status; 887 } 888 889 int 890 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 891 { 892 int return_status; 893 unsigned long wait_reset; 894 struct qla_hw_data *ha = vha->hw; 895 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 896 897 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 898 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 899 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 900 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 901 ha->dpc_active) && time_before(jiffies, wait_reset)) { 902 903 msleep(1000); 904 905 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 906 ha->flags.chip_reset_done) 907 break; 908 } 909 if (ha->flags.chip_reset_done) 910 return_status = QLA_SUCCESS; 911 else 912 return_status = QLA_FUNCTION_FAILED; 913 914 return return_status; 915 } 916 917 static void 918 sp_get(struct srb *sp) 919 { 920 atomic_inc(&sp->ref_count); 921 } 922 923 /************************************************************************** 924 * qla2xxx_eh_abort 925 * 926 * Description: 927 * The abort function will abort the specified command. 928 * 929 * Input: 930 * cmd = Linux SCSI command packet to be aborted. 931 * 932 * Returns: 933 * Either SUCCESS or FAILED. 934 * 935 * Note: 936 * Only return FAILED if command not returned by firmware. 937 **************************************************************************/ 938 static int 939 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 940 { 941 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 942 srb_t *sp; 943 int ret; 944 unsigned int id, lun; 945 unsigned long flags; 946 int wait = 0; 947 struct qla_hw_data *ha = vha->hw; 948 949 if (!CMD_SP(cmd)) 950 return SUCCESS; 951 952 ret = fc_block_scsi_eh(cmd); 953 if (ret != 0) 954 return ret; 955 ret = SUCCESS; 956 957 id = cmd->device->id; 958 lun = cmd->device->lun; 959 960 spin_lock_irqsave(&ha->hardware_lock, flags); 961 sp = (srb_t *) CMD_SP(cmd); 962 if (!sp) { 963 spin_unlock_irqrestore(&ha->hardware_lock, flags); 964 return SUCCESS; 965 } 966 967 ql_dbg(ql_dbg_taskm, vha, 0x8002, 968 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", 969 vha->host_no, id, lun, sp, cmd); 970 971 /* Get a reference to the sp and drop the lock.*/ 972 sp_get(sp); 973 974 spin_unlock_irqrestore(&ha->hardware_lock, flags); 975 if (ha->isp_ops->abort_command(sp)) { 976 ret = FAILED; 977 ql_dbg(ql_dbg_taskm, vha, 0x8003, 978 "Abort command mbx failed cmd=%p.\n", cmd); 979 } else { 980 ql_dbg(ql_dbg_taskm, vha, 0x8004, 981 "Abort command mbx success cmd=%p.\n", cmd); 982 wait = 1; 983 } 984 985 spin_lock_irqsave(&ha->hardware_lock, flags); 986 sp->done(ha, sp, 0); 987 spin_unlock_irqrestore(&ha->hardware_lock, flags); 988 989 /* Did the command return during mailbox execution? */ 990 if (ret == FAILED && !CMD_SP(cmd)) 991 ret = SUCCESS; 992 993 /* Wait for the command to be returned. */ 994 if (wait) { 995 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 996 ql_log(ql_log_warn, vha, 0x8006, 997 "Abort handler timed out cmd=%p.\n", cmd); 998 ret = FAILED; 999 } 1000 } 1001 1002 ql_log(ql_log_info, vha, 0x801c, 1003 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", 1004 vha->host_no, id, lun, wait, ret); 1005 1006 return ret; 1007 } 1008 1009 int 1010 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1011 unsigned int l, enum nexus_wait_type type) 1012 { 1013 int cnt, match, status; 1014 unsigned long flags; 1015 struct qla_hw_data *ha = vha->hw; 1016 struct req_que *req; 1017 srb_t *sp; 1018 struct scsi_cmnd *cmd; 1019 1020 status = QLA_SUCCESS; 1021 1022 spin_lock_irqsave(&ha->hardware_lock, flags); 1023 req = vha->req; 1024 for (cnt = 1; status == QLA_SUCCESS && 1025 cnt < req->num_outstanding_cmds; cnt++) { 1026 sp = req->outstanding_cmds[cnt]; 1027 if (!sp) 1028 continue; 1029 if (sp->type != SRB_SCSI_CMD) 1030 continue; 1031 if (vha->vp_idx != sp->fcport->vha->vp_idx) 1032 continue; 1033 match = 0; 1034 cmd = GET_CMD_SP(sp); 1035 switch (type) { 1036 case WAIT_HOST: 1037 match = 1; 1038 break; 1039 case WAIT_TARGET: 1040 match = cmd->device->id == t; 1041 break; 1042 case WAIT_LUN: 1043 match = (cmd->device->id == t && 1044 cmd->device->lun == l); 1045 break; 1046 } 1047 if (!match) 1048 continue; 1049 1050 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1051 status = qla2x00_eh_wait_on_command(cmd); 1052 spin_lock_irqsave(&ha->hardware_lock, flags); 1053 } 1054 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1055 1056 return status; 1057 } 1058 1059 static char *reset_errors[] = { 1060 "HBA not online", 1061 "HBA not ready", 1062 "Task management failed", 1063 "Waiting for command completions", 1064 }; 1065 1066 static int 1067 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1068 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) 1069 { 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1071 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1072 int err; 1073 1074 if (!fcport) { 1075 return FAILED; 1076 } 1077 1078 err = fc_block_scsi_eh(cmd); 1079 if (err != 0) 1080 return err; 1081 1082 ql_log(ql_log_info, vha, 0x8009, 1083 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, 1084 cmd->device->id, cmd->device->lun, cmd); 1085 1086 err = 0; 1087 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1088 ql_log(ql_log_warn, vha, 0x800a, 1089 "Wait for hba online failed for cmd=%p.\n", cmd); 1090 goto eh_reset_failed; 1091 } 1092 err = 2; 1093 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1094 != QLA_SUCCESS) { 1095 ql_log(ql_log_warn, vha, 0x800c, 1096 "do_reset failed for cmd=%p.\n", cmd); 1097 goto eh_reset_failed; 1098 } 1099 err = 3; 1100 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1101 cmd->device->lun, type) != QLA_SUCCESS) { 1102 ql_log(ql_log_warn, vha, 0x800d, 1103 "wait for pending cmds failed for cmd=%p.\n", cmd); 1104 goto eh_reset_failed; 1105 } 1106 1107 ql_log(ql_log_info, vha, 0x800e, 1108 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, 1109 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1110 1111 return SUCCESS; 1112 1113 eh_reset_failed: 1114 ql_log(ql_log_info, vha, 0x800f, 1115 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, 1116 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1117 cmd); 1118 return FAILED; 1119 } 1120 1121 static int 1122 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1123 { 1124 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1125 struct qla_hw_data *ha = vha->hw; 1126 1127 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1128 ha->isp_ops->lun_reset); 1129 } 1130 1131 static int 1132 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1133 { 1134 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1135 struct qla_hw_data *ha = vha->hw; 1136 1137 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1138 ha->isp_ops->target_reset); 1139 } 1140 1141 /************************************************************************** 1142 * qla2xxx_eh_bus_reset 1143 * 1144 * Description: 1145 * The bus reset function will reset the bus and abort any executing 1146 * commands. 1147 * 1148 * Input: 1149 * cmd = Linux SCSI command packet of the command that cause the 1150 * bus reset. 1151 * 1152 * Returns: 1153 * SUCCESS/FAILURE (defined as macro in scsi.h). 1154 * 1155 **************************************************************************/ 1156 static int 1157 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1158 { 1159 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1160 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1161 int ret = FAILED; 1162 unsigned int id, lun; 1163 1164 id = cmd->device->id; 1165 lun = cmd->device->lun; 1166 1167 if (!fcport) { 1168 return ret; 1169 } 1170 1171 ret = fc_block_scsi_eh(cmd); 1172 if (ret != 0) 1173 return ret; 1174 ret = FAILED; 1175 1176 ql_log(ql_log_info, vha, 0x8012, 1177 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1178 1179 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1180 ql_log(ql_log_fatal, vha, 0x8013, 1181 "Wait for hba online failed board disabled.\n"); 1182 goto eh_bus_reset_done; 1183 } 1184 1185 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1186 ret = SUCCESS; 1187 1188 if (ret == FAILED) 1189 goto eh_bus_reset_done; 1190 1191 /* Flush outstanding commands. */ 1192 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1193 QLA_SUCCESS) { 1194 ql_log(ql_log_warn, vha, 0x8014, 1195 "Wait for pending commands failed.\n"); 1196 ret = FAILED; 1197 } 1198 1199 eh_bus_reset_done: 1200 ql_log(ql_log_warn, vha, 0x802b, 1201 "BUS RESET %s nexus=%ld:%d:%d.\n", 1202 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1203 1204 return ret; 1205 } 1206 1207 /************************************************************************** 1208 * qla2xxx_eh_host_reset 1209 * 1210 * Description: 1211 * The reset function will reset the Adapter. 1212 * 1213 * Input: 1214 * cmd = Linux SCSI command packet of the command that cause the 1215 * adapter reset. 1216 * 1217 * Returns: 1218 * Either SUCCESS or FAILED. 1219 * 1220 * Note: 1221 **************************************************************************/ 1222 static int 1223 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1224 { 1225 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1226 struct qla_hw_data *ha = vha->hw; 1227 int ret = FAILED; 1228 unsigned int id, lun; 1229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1230 1231 id = cmd->device->id; 1232 lun = cmd->device->lun; 1233 1234 ql_log(ql_log_info, vha, 0x8018, 1235 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); 1236 1237 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) 1238 goto eh_host_reset_lock; 1239 1240 if (vha != base_vha) { 1241 if (qla2x00_vp_abort_isp(vha)) 1242 goto eh_host_reset_lock; 1243 } else { 1244 if (IS_P3P_TYPE(vha->hw)) { 1245 if (!qla82xx_fcoe_ctx_reset(vha)) { 1246 /* Ctx reset success */ 1247 ret = SUCCESS; 1248 goto eh_host_reset_lock; 1249 } 1250 /* fall thru if ctx reset failed */ 1251 } 1252 if (ha->wq) 1253 flush_workqueue(ha->wq); 1254 1255 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1256 if (ha->isp_ops->abort_isp(base_vha)) { 1257 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1258 /* failed. schedule dpc to try */ 1259 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1260 1261 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1262 ql_log(ql_log_warn, vha, 0x802a, 1263 "wait for hba online failed.\n"); 1264 goto eh_host_reset_lock; 1265 } 1266 } 1267 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1268 } 1269 1270 /* Waiting for command to be returned to OS.*/ 1271 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1272 QLA_SUCCESS) 1273 ret = SUCCESS; 1274 1275 eh_host_reset_lock: 1276 ql_log(ql_log_info, vha, 0x8017, 1277 "ADAPTER RESET %s nexus=%ld:%d:%d.\n", 1278 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1279 1280 return ret; 1281 } 1282 1283 /* 1284 * qla2x00_loop_reset 1285 * Issue loop reset. 1286 * 1287 * Input: 1288 * ha = adapter block pointer. 1289 * 1290 * Returns: 1291 * 0 = success 1292 */ 1293 int 1294 qla2x00_loop_reset(scsi_qla_host_t *vha) 1295 { 1296 int ret; 1297 struct fc_port *fcport; 1298 struct qla_hw_data *ha = vha->hw; 1299 1300 if (IS_QLAFX00(ha)) { 1301 return qlafx00_loop_reset(vha); 1302 } 1303 1304 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1305 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1306 if (fcport->port_type != FCT_TARGET) 1307 continue; 1308 1309 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1310 if (ret != QLA_SUCCESS) { 1311 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1312 "Bus Reset failed: Reset=%d " 1313 "d_id=%x.\n", ret, fcport->d_id.b24); 1314 } 1315 } 1316 } 1317 1318 1319 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1320 atomic_set(&vha->loop_state, LOOP_DOWN); 1321 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1322 qla2x00_mark_all_devices_lost(vha, 0); 1323 ret = qla2x00_full_login_lip(vha); 1324 if (ret != QLA_SUCCESS) { 1325 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1326 "full_login_lip=%d.\n", ret); 1327 } 1328 } 1329 1330 if (ha->flags.enable_lip_reset) { 1331 ret = qla2x00_lip_reset(vha); 1332 if (ret != QLA_SUCCESS) 1333 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1334 "lip_reset failed (%d).\n", ret); 1335 } 1336 1337 /* Issue marker command only when we are going to start the I/O */ 1338 vha->marker_needed = 1; 1339 1340 return QLA_SUCCESS; 1341 } 1342 1343 void 1344 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1345 { 1346 int que, cnt; 1347 unsigned long flags; 1348 srb_t *sp; 1349 struct qla_hw_data *ha = vha->hw; 1350 struct req_que *req; 1351 1352 spin_lock_irqsave(&ha->hardware_lock, flags); 1353 for (que = 0; que < ha->max_req_queues; que++) { 1354 req = ha->req_q_map[que]; 1355 if (!req) 1356 continue; 1357 if (!req->outstanding_cmds) 1358 continue; 1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1360 sp = req->outstanding_cmds[cnt]; 1361 if (sp) { 1362 req->outstanding_cmds[cnt] = NULL; 1363 sp->done(vha, sp, res); 1364 } 1365 } 1366 } 1367 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1368 } 1369 1370 static int 1371 qla2xxx_slave_alloc(struct scsi_device *sdev) 1372 { 1373 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1374 1375 if (!rport || fc_remote_port_chkready(rport)) 1376 return -ENXIO; 1377 1378 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1379 1380 return 0; 1381 } 1382 1383 static int 1384 qla2xxx_slave_configure(struct scsi_device *sdev) 1385 { 1386 scsi_qla_host_t *vha = shost_priv(sdev->host); 1387 struct req_que *req = vha->req; 1388 1389 if (IS_T10_PI_CAPABLE(vha->hw)) 1390 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1391 1392 if (sdev->tagged_supported) 1393 scsi_activate_tcq(sdev, req->max_q_depth); 1394 else 1395 scsi_deactivate_tcq(sdev, req->max_q_depth); 1396 return 0; 1397 } 1398 1399 static void 1400 qla2xxx_slave_destroy(struct scsi_device *sdev) 1401 { 1402 sdev->hostdata = NULL; 1403 } 1404 1405 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) 1406 { 1407 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1408 1409 if (!scsi_track_queue_full(sdev, qdepth)) 1410 return; 1411 1412 ql_dbg(ql_dbg_io, fcport->vha, 0x3029, 1413 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", 1414 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1415 } 1416 1417 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) 1418 { 1419 fc_port_t *fcport = sdev->hostdata; 1420 struct scsi_qla_host *vha = fcport->vha; 1421 struct req_que *req = NULL; 1422 1423 req = vha->req; 1424 if (!req) 1425 return; 1426 1427 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) 1428 return; 1429 1430 if (sdev->ordered_tags) 1431 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); 1432 else 1433 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); 1434 1435 ql_dbg(ql_dbg_io, vha, 0x302a, 1436 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", 1437 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); 1438 } 1439 1440 static int 1441 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) 1442 { 1443 switch (reason) { 1444 case SCSI_QDEPTH_DEFAULT: 1445 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); 1446 break; 1447 case SCSI_QDEPTH_QFULL: 1448 qla2x00_handle_queue_full(sdev, qdepth); 1449 break; 1450 case SCSI_QDEPTH_RAMP_UP: 1451 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); 1452 break; 1453 default: 1454 return -EOPNOTSUPP; 1455 } 1456 1457 return sdev->queue_depth; 1458 } 1459 1460 static int 1461 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) 1462 { 1463 if (sdev->tagged_supported) { 1464 scsi_set_tag_type(sdev, tag_type); 1465 if (tag_type) 1466 scsi_activate_tcq(sdev, sdev->queue_depth); 1467 else 1468 scsi_deactivate_tcq(sdev, sdev->queue_depth); 1469 } else 1470 tag_type = 0; 1471 1472 return tag_type; 1473 } 1474 1475 /** 1476 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1477 * @ha: HA context 1478 * 1479 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1480 * supported addressing method. 1481 */ 1482 static void 1483 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1484 { 1485 /* Assume a 32bit DMA mask. */ 1486 ha->flags.enable_64bit_addressing = 0; 1487 1488 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1489 /* Any upper-dword bits set? */ 1490 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1491 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1492 /* Ok, a 64bit DMA mask is applicable. */ 1493 ha->flags.enable_64bit_addressing = 1; 1494 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1495 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1496 return; 1497 } 1498 } 1499 1500 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1501 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1502 } 1503 1504 static void 1505 qla2x00_enable_intrs(struct qla_hw_data *ha) 1506 { 1507 unsigned long flags = 0; 1508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1509 1510 spin_lock_irqsave(&ha->hardware_lock, flags); 1511 ha->interrupts_on = 1; 1512 /* enable risc and host interrupts */ 1513 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1514 RD_REG_WORD(®->ictrl); 1515 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1516 1517 } 1518 1519 static void 1520 qla2x00_disable_intrs(struct qla_hw_data *ha) 1521 { 1522 unsigned long flags = 0; 1523 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1524 1525 spin_lock_irqsave(&ha->hardware_lock, flags); 1526 ha->interrupts_on = 0; 1527 /* disable risc and host interrupts */ 1528 WRT_REG_WORD(®->ictrl, 0); 1529 RD_REG_WORD(®->ictrl); 1530 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1531 } 1532 1533 static void 1534 qla24xx_enable_intrs(struct qla_hw_data *ha) 1535 { 1536 unsigned long flags = 0; 1537 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1538 1539 spin_lock_irqsave(&ha->hardware_lock, flags); 1540 ha->interrupts_on = 1; 1541 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1542 RD_REG_DWORD(®->ictrl); 1543 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1544 } 1545 1546 static void 1547 qla24xx_disable_intrs(struct qla_hw_data *ha) 1548 { 1549 unsigned long flags = 0; 1550 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1551 1552 if (IS_NOPOLLING_TYPE(ha)) 1553 return; 1554 spin_lock_irqsave(&ha->hardware_lock, flags); 1555 ha->interrupts_on = 0; 1556 WRT_REG_DWORD(®->ictrl, 0); 1557 RD_REG_DWORD(®->ictrl); 1558 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1559 } 1560 1561 static int 1562 qla2x00_iospace_config(struct qla_hw_data *ha) 1563 { 1564 resource_size_t pio; 1565 uint16_t msix; 1566 int cpus; 1567 1568 if (pci_request_selected_regions(ha->pdev, ha->bars, 1569 QLA2XXX_DRIVER_NAME)) { 1570 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1571 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1572 pci_name(ha->pdev)); 1573 goto iospace_error_exit; 1574 } 1575 if (!(ha->bars & 1)) 1576 goto skip_pio; 1577 1578 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1579 pio = pci_resource_start(ha->pdev, 0); 1580 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1581 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1582 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1583 "Invalid pci I/O region size (%s).\n", 1584 pci_name(ha->pdev)); 1585 pio = 0; 1586 } 1587 } else { 1588 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1589 "Region #0 no a PIO resource (%s).\n", 1590 pci_name(ha->pdev)); 1591 pio = 0; 1592 } 1593 ha->pio_address = pio; 1594 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1595 "PIO address=%llu.\n", 1596 (unsigned long long)ha->pio_address); 1597 1598 skip_pio: 1599 /* Use MMIO operations for all accesses. */ 1600 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1601 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1602 "Region #1 not an MMIO resource (%s), aborting.\n", 1603 pci_name(ha->pdev)); 1604 goto iospace_error_exit; 1605 } 1606 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1607 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1608 "Invalid PCI mem region size (%s), aborting.\n", 1609 pci_name(ha->pdev)); 1610 goto iospace_error_exit; 1611 } 1612 1613 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1614 if (!ha->iobase) { 1615 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1616 "Cannot remap MMIO (%s), aborting.\n", 1617 pci_name(ha->pdev)); 1618 goto iospace_error_exit; 1619 } 1620 1621 /* Determine queue resources */ 1622 ha->max_req_queues = ha->max_rsp_queues = 1; 1623 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || 1624 (ql2xmaxqueues > 1 && ql2xmultique_tag) || 1625 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1626 goto mqiobase_exit; 1627 1628 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1629 pci_resource_len(ha->pdev, 3)); 1630 if (ha->mqiobase) { 1631 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1632 "MQIO Base=%p.\n", ha->mqiobase); 1633 /* Read MSIX vector size of the board */ 1634 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1635 ha->msix_count = msix; 1636 /* Max queues are bounded by available msix vectors */ 1637 /* queue 0 uses two msix vectors */ 1638 if (ql2xmultique_tag) { 1639 cpus = num_online_cpus(); 1640 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1641 (cpus + 1) : (ha->msix_count - 1); 1642 ha->max_req_queues = 2; 1643 } else if (ql2xmaxqueues > 1) { 1644 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1645 QLA_MQ_SIZE : ql2xmaxqueues; 1646 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, 1647 "QoS mode set, max no of request queues:%d.\n", 1648 ha->max_req_queues); 1649 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, 1650 "QoS mode set, max no of request queues:%d.\n", 1651 ha->max_req_queues); 1652 } 1653 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1654 "MSI-X vector count: %d.\n", msix); 1655 } else 1656 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1657 "BAR 3 not enabled.\n"); 1658 1659 mqiobase_exit: 1660 ha->msix_count = ha->max_rsp_queues + 1; 1661 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1662 "MSIX Count:%d.\n", ha->msix_count); 1663 return (0); 1664 1665 iospace_error_exit: 1666 return (-ENOMEM); 1667 } 1668 1669 1670 static int 1671 qla83xx_iospace_config(struct qla_hw_data *ha) 1672 { 1673 uint16_t msix; 1674 int cpus; 1675 1676 if (pci_request_selected_regions(ha->pdev, ha->bars, 1677 QLA2XXX_DRIVER_NAME)) { 1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1679 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1680 pci_name(ha->pdev)); 1681 1682 goto iospace_error_exit; 1683 } 1684 1685 /* Use MMIO operations for all accesses. */ 1686 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1687 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1688 "Invalid pci I/O region size (%s).\n", 1689 pci_name(ha->pdev)); 1690 goto iospace_error_exit; 1691 } 1692 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1693 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1694 "Invalid PCI mem region size (%s), aborting\n", 1695 pci_name(ha->pdev)); 1696 goto iospace_error_exit; 1697 } 1698 1699 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1700 if (!ha->iobase) { 1701 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1702 "Cannot remap MMIO (%s), aborting.\n", 1703 pci_name(ha->pdev)); 1704 goto iospace_error_exit; 1705 } 1706 1707 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1708 /* 83XX 26XX always use MQ type access for queues 1709 * - mbar 2, a.k.a region 4 */ 1710 ha->max_req_queues = ha->max_rsp_queues = 1; 1711 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1712 pci_resource_len(ha->pdev, 4)); 1713 1714 if (!ha->mqiobase) { 1715 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1716 "BAR2/region4 not enabled\n"); 1717 goto mqiobase_exit; 1718 } 1719 1720 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1721 pci_resource_len(ha->pdev, 2)); 1722 if (ha->msixbase) { 1723 /* Read MSIX vector size of the board */ 1724 pci_read_config_word(ha->pdev, 1725 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1726 ha->msix_count = msix; 1727 /* Max queues are bounded by available msix vectors */ 1728 /* queue 0 uses two msix vectors */ 1729 if (ql2xmultique_tag) { 1730 cpus = num_online_cpus(); 1731 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? 1732 (cpus + 1) : (ha->msix_count - 1); 1733 ha->max_req_queues = 2; 1734 } else if (ql2xmaxqueues > 1) { 1735 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? 1736 QLA_MQ_SIZE : ql2xmaxqueues; 1737 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, 1738 "QoS mode set, max no of request queues:%d.\n", 1739 ha->max_req_queues); 1740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 1741 "QoS mode set, max no of request queues:%d.\n", 1742 ha->max_req_queues); 1743 } 1744 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1745 "MSI-X vector count: %d.\n", msix); 1746 } else 1747 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1748 "BAR 1 not enabled.\n"); 1749 1750 mqiobase_exit: 1751 ha->msix_count = ha->max_rsp_queues + 1; 1752 1753 qlt_83xx_iospace_config(ha); 1754 1755 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1756 "MSIX Count:%d.\n", ha->msix_count); 1757 return 0; 1758 1759 iospace_error_exit: 1760 return -ENOMEM; 1761 } 1762 1763 static struct isp_operations qla2100_isp_ops = { 1764 .pci_config = qla2100_pci_config, 1765 .reset_chip = qla2x00_reset_chip, 1766 .chip_diag = qla2x00_chip_diag, 1767 .config_rings = qla2x00_config_rings, 1768 .reset_adapter = qla2x00_reset_adapter, 1769 .nvram_config = qla2x00_nvram_config, 1770 .update_fw_options = qla2x00_update_fw_options, 1771 .load_risc = qla2x00_load_risc, 1772 .pci_info_str = qla2x00_pci_info_str, 1773 .fw_version_str = qla2x00_fw_version_str, 1774 .intr_handler = qla2100_intr_handler, 1775 .enable_intrs = qla2x00_enable_intrs, 1776 .disable_intrs = qla2x00_disable_intrs, 1777 .abort_command = qla2x00_abort_command, 1778 .target_reset = qla2x00_abort_target, 1779 .lun_reset = qla2x00_lun_reset, 1780 .fabric_login = qla2x00_login_fabric, 1781 .fabric_logout = qla2x00_fabric_logout, 1782 .calc_req_entries = qla2x00_calc_iocbs_32, 1783 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1784 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1785 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1786 .read_nvram = qla2x00_read_nvram_data, 1787 .write_nvram = qla2x00_write_nvram_data, 1788 .fw_dump = qla2100_fw_dump, 1789 .beacon_on = NULL, 1790 .beacon_off = NULL, 1791 .beacon_blink = NULL, 1792 .read_optrom = qla2x00_read_optrom_data, 1793 .write_optrom = qla2x00_write_optrom_data, 1794 .get_flash_version = qla2x00_get_flash_version, 1795 .start_scsi = qla2x00_start_scsi, 1796 .abort_isp = qla2x00_abort_isp, 1797 .iospace_config = qla2x00_iospace_config, 1798 .initialize_adapter = qla2x00_initialize_adapter, 1799 }; 1800 1801 static struct isp_operations qla2300_isp_ops = { 1802 .pci_config = qla2300_pci_config, 1803 .reset_chip = qla2x00_reset_chip, 1804 .chip_diag = qla2x00_chip_diag, 1805 .config_rings = qla2x00_config_rings, 1806 .reset_adapter = qla2x00_reset_adapter, 1807 .nvram_config = qla2x00_nvram_config, 1808 .update_fw_options = qla2x00_update_fw_options, 1809 .load_risc = qla2x00_load_risc, 1810 .pci_info_str = qla2x00_pci_info_str, 1811 .fw_version_str = qla2x00_fw_version_str, 1812 .intr_handler = qla2300_intr_handler, 1813 .enable_intrs = qla2x00_enable_intrs, 1814 .disable_intrs = qla2x00_disable_intrs, 1815 .abort_command = qla2x00_abort_command, 1816 .target_reset = qla2x00_abort_target, 1817 .lun_reset = qla2x00_lun_reset, 1818 .fabric_login = qla2x00_login_fabric, 1819 .fabric_logout = qla2x00_fabric_logout, 1820 .calc_req_entries = qla2x00_calc_iocbs_32, 1821 .build_iocbs = qla2x00_build_scsi_iocbs_32, 1822 .prep_ms_iocb = qla2x00_prep_ms_iocb, 1823 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1824 .read_nvram = qla2x00_read_nvram_data, 1825 .write_nvram = qla2x00_write_nvram_data, 1826 .fw_dump = qla2300_fw_dump, 1827 .beacon_on = qla2x00_beacon_on, 1828 .beacon_off = qla2x00_beacon_off, 1829 .beacon_blink = qla2x00_beacon_blink, 1830 .read_optrom = qla2x00_read_optrom_data, 1831 .write_optrom = qla2x00_write_optrom_data, 1832 .get_flash_version = qla2x00_get_flash_version, 1833 .start_scsi = qla2x00_start_scsi, 1834 .abort_isp = qla2x00_abort_isp, 1835 .iospace_config = qla2x00_iospace_config, 1836 .initialize_adapter = qla2x00_initialize_adapter, 1837 }; 1838 1839 static struct isp_operations qla24xx_isp_ops = { 1840 .pci_config = qla24xx_pci_config, 1841 .reset_chip = qla24xx_reset_chip, 1842 .chip_diag = qla24xx_chip_diag, 1843 .config_rings = qla24xx_config_rings, 1844 .reset_adapter = qla24xx_reset_adapter, 1845 .nvram_config = qla24xx_nvram_config, 1846 .update_fw_options = qla24xx_update_fw_options, 1847 .load_risc = qla24xx_load_risc, 1848 .pci_info_str = qla24xx_pci_info_str, 1849 .fw_version_str = qla24xx_fw_version_str, 1850 .intr_handler = qla24xx_intr_handler, 1851 .enable_intrs = qla24xx_enable_intrs, 1852 .disable_intrs = qla24xx_disable_intrs, 1853 .abort_command = qla24xx_abort_command, 1854 .target_reset = qla24xx_abort_target, 1855 .lun_reset = qla24xx_lun_reset, 1856 .fabric_login = qla24xx_login_fabric, 1857 .fabric_logout = qla24xx_fabric_logout, 1858 .calc_req_entries = NULL, 1859 .build_iocbs = NULL, 1860 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1861 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1862 .read_nvram = qla24xx_read_nvram_data, 1863 .write_nvram = qla24xx_write_nvram_data, 1864 .fw_dump = qla24xx_fw_dump, 1865 .beacon_on = qla24xx_beacon_on, 1866 .beacon_off = qla24xx_beacon_off, 1867 .beacon_blink = qla24xx_beacon_blink, 1868 .read_optrom = qla24xx_read_optrom_data, 1869 .write_optrom = qla24xx_write_optrom_data, 1870 .get_flash_version = qla24xx_get_flash_version, 1871 .start_scsi = qla24xx_start_scsi, 1872 .abort_isp = qla2x00_abort_isp, 1873 .iospace_config = qla2x00_iospace_config, 1874 .initialize_adapter = qla2x00_initialize_adapter, 1875 }; 1876 1877 static struct isp_operations qla25xx_isp_ops = { 1878 .pci_config = qla25xx_pci_config, 1879 .reset_chip = qla24xx_reset_chip, 1880 .chip_diag = qla24xx_chip_diag, 1881 .config_rings = qla24xx_config_rings, 1882 .reset_adapter = qla24xx_reset_adapter, 1883 .nvram_config = qla24xx_nvram_config, 1884 .update_fw_options = qla24xx_update_fw_options, 1885 .load_risc = qla24xx_load_risc, 1886 .pci_info_str = qla24xx_pci_info_str, 1887 .fw_version_str = qla24xx_fw_version_str, 1888 .intr_handler = qla24xx_intr_handler, 1889 .enable_intrs = qla24xx_enable_intrs, 1890 .disable_intrs = qla24xx_disable_intrs, 1891 .abort_command = qla24xx_abort_command, 1892 .target_reset = qla24xx_abort_target, 1893 .lun_reset = qla24xx_lun_reset, 1894 .fabric_login = qla24xx_login_fabric, 1895 .fabric_logout = qla24xx_fabric_logout, 1896 .calc_req_entries = NULL, 1897 .build_iocbs = NULL, 1898 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1899 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1900 .read_nvram = qla25xx_read_nvram_data, 1901 .write_nvram = qla25xx_write_nvram_data, 1902 .fw_dump = qla25xx_fw_dump, 1903 .beacon_on = qla24xx_beacon_on, 1904 .beacon_off = qla24xx_beacon_off, 1905 .beacon_blink = qla24xx_beacon_blink, 1906 .read_optrom = qla25xx_read_optrom_data, 1907 .write_optrom = qla24xx_write_optrom_data, 1908 .get_flash_version = qla24xx_get_flash_version, 1909 .start_scsi = qla24xx_dif_start_scsi, 1910 .abort_isp = qla2x00_abort_isp, 1911 .iospace_config = qla2x00_iospace_config, 1912 .initialize_adapter = qla2x00_initialize_adapter, 1913 }; 1914 1915 static struct isp_operations qla81xx_isp_ops = { 1916 .pci_config = qla25xx_pci_config, 1917 .reset_chip = qla24xx_reset_chip, 1918 .chip_diag = qla24xx_chip_diag, 1919 .config_rings = qla24xx_config_rings, 1920 .reset_adapter = qla24xx_reset_adapter, 1921 .nvram_config = qla81xx_nvram_config, 1922 .update_fw_options = qla81xx_update_fw_options, 1923 .load_risc = qla81xx_load_risc, 1924 .pci_info_str = qla24xx_pci_info_str, 1925 .fw_version_str = qla24xx_fw_version_str, 1926 .intr_handler = qla24xx_intr_handler, 1927 .enable_intrs = qla24xx_enable_intrs, 1928 .disable_intrs = qla24xx_disable_intrs, 1929 .abort_command = qla24xx_abort_command, 1930 .target_reset = qla24xx_abort_target, 1931 .lun_reset = qla24xx_lun_reset, 1932 .fabric_login = qla24xx_login_fabric, 1933 .fabric_logout = qla24xx_fabric_logout, 1934 .calc_req_entries = NULL, 1935 .build_iocbs = NULL, 1936 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1937 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1938 .read_nvram = NULL, 1939 .write_nvram = NULL, 1940 .fw_dump = qla81xx_fw_dump, 1941 .beacon_on = qla24xx_beacon_on, 1942 .beacon_off = qla24xx_beacon_off, 1943 .beacon_blink = qla83xx_beacon_blink, 1944 .read_optrom = qla25xx_read_optrom_data, 1945 .write_optrom = qla24xx_write_optrom_data, 1946 .get_flash_version = qla24xx_get_flash_version, 1947 .start_scsi = qla24xx_dif_start_scsi, 1948 .abort_isp = qla2x00_abort_isp, 1949 .iospace_config = qla2x00_iospace_config, 1950 .initialize_adapter = qla2x00_initialize_adapter, 1951 }; 1952 1953 static struct isp_operations qla82xx_isp_ops = { 1954 .pci_config = qla82xx_pci_config, 1955 .reset_chip = qla82xx_reset_chip, 1956 .chip_diag = qla24xx_chip_diag, 1957 .config_rings = qla82xx_config_rings, 1958 .reset_adapter = qla24xx_reset_adapter, 1959 .nvram_config = qla81xx_nvram_config, 1960 .update_fw_options = qla24xx_update_fw_options, 1961 .load_risc = qla82xx_load_risc, 1962 .pci_info_str = qla24xx_pci_info_str, 1963 .fw_version_str = qla24xx_fw_version_str, 1964 .intr_handler = qla82xx_intr_handler, 1965 .enable_intrs = qla82xx_enable_intrs, 1966 .disable_intrs = qla82xx_disable_intrs, 1967 .abort_command = qla24xx_abort_command, 1968 .target_reset = qla24xx_abort_target, 1969 .lun_reset = qla24xx_lun_reset, 1970 .fabric_login = qla24xx_login_fabric, 1971 .fabric_logout = qla24xx_fabric_logout, 1972 .calc_req_entries = NULL, 1973 .build_iocbs = NULL, 1974 .prep_ms_iocb = qla24xx_prep_ms_iocb, 1975 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1976 .read_nvram = qla24xx_read_nvram_data, 1977 .write_nvram = qla24xx_write_nvram_data, 1978 .fw_dump = qla24xx_fw_dump, 1979 .beacon_on = qla82xx_beacon_on, 1980 .beacon_off = qla82xx_beacon_off, 1981 .beacon_blink = NULL, 1982 .read_optrom = qla82xx_read_optrom_data, 1983 .write_optrom = qla82xx_write_optrom_data, 1984 .get_flash_version = qla82xx_get_flash_version, 1985 .start_scsi = qla82xx_start_scsi, 1986 .abort_isp = qla82xx_abort_isp, 1987 .iospace_config = qla82xx_iospace_config, 1988 .initialize_adapter = qla2x00_initialize_adapter, 1989 }; 1990 1991 static struct isp_operations qla8044_isp_ops = { 1992 .pci_config = qla82xx_pci_config, 1993 .reset_chip = qla82xx_reset_chip, 1994 .chip_diag = qla24xx_chip_diag, 1995 .config_rings = qla82xx_config_rings, 1996 .reset_adapter = qla24xx_reset_adapter, 1997 .nvram_config = qla81xx_nvram_config, 1998 .update_fw_options = qla24xx_update_fw_options, 1999 .load_risc = qla82xx_load_risc, 2000 .pci_info_str = qla24xx_pci_info_str, 2001 .fw_version_str = qla24xx_fw_version_str, 2002 .intr_handler = qla8044_intr_handler, 2003 .enable_intrs = qla82xx_enable_intrs, 2004 .disable_intrs = qla82xx_disable_intrs, 2005 .abort_command = qla24xx_abort_command, 2006 .target_reset = qla24xx_abort_target, 2007 .lun_reset = qla24xx_lun_reset, 2008 .fabric_login = qla24xx_login_fabric, 2009 .fabric_logout = qla24xx_fabric_logout, 2010 .calc_req_entries = NULL, 2011 .build_iocbs = NULL, 2012 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2013 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2014 .read_nvram = NULL, 2015 .write_nvram = NULL, 2016 .fw_dump = qla24xx_fw_dump, 2017 .beacon_on = qla82xx_beacon_on, 2018 .beacon_off = qla82xx_beacon_off, 2019 .beacon_blink = NULL, 2020 .read_optrom = qla82xx_read_optrom_data, 2021 .write_optrom = qla8044_write_optrom_data, 2022 .get_flash_version = qla82xx_get_flash_version, 2023 .start_scsi = qla82xx_start_scsi, 2024 .abort_isp = qla8044_abort_isp, 2025 .iospace_config = qla82xx_iospace_config, 2026 .initialize_adapter = qla2x00_initialize_adapter, 2027 }; 2028 2029 static struct isp_operations qla83xx_isp_ops = { 2030 .pci_config = qla25xx_pci_config, 2031 .reset_chip = qla24xx_reset_chip, 2032 .chip_diag = qla24xx_chip_diag, 2033 .config_rings = qla24xx_config_rings, 2034 .reset_adapter = qla24xx_reset_adapter, 2035 .nvram_config = qla81xx_nvram_config, 2036 .update_fw_options = qla81xx_update_fw_options, 2037 .load_risc = qla81xx_load_risc, 2038 .pci_info_str = qla24xx_pci_info_str, 2039 .fw_version_str = qla24xx_fw_version_str, 2040 .intr_handler = qla24xx_intr_handler, 2041 .enable_intrs = qla24xx_enable_intrs, 2042 .disable_intrs = qla24xx_disable_intrs, 2043 .abort_command = qla24xx_abort_command, 2044 .target_reset = qla24xx_abort_target, 2045 .lun_reset = qla24xx_lun_reset, 2046 .fabric_login = qla24xx_login_fabric, 2047 .fabric_logout = qla24xx_fabric_logout, 2048 .calc_req_entries = NULL, 2049 .build_iocbs = NULL, 2050 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2052 .read_nvram = NULL, 2053 .write_nvram = NULL, 2054 .fw_dump = qla83xx_fw_dump, 2055 .beacon_on = qla24xx_beacon_on, 2056 .beacon_off = qla24xx_beacon_off, 2057 .beacon_blink = qla83xx_beacon_blink, 2058 .read_optrom = qla25xx_read_optrom_data, 2059 .write_optrom = qla24xx_write_optrom_data, 2060 .get_flash_version = qla24xx_get_flash_version, 2061 .start_scsi = qla24xx_dif_start_scsi, 2062 .abort_isp = qla2x00_abort_isp, 2063 .iospace_config = qla83xx_iospace_config, 2064 .initialize_adapter = qla2x00_initialize_adapter, 2065 }; 2066 2067 static struct isp_operations qlafx00_isp_ops = { 2068 .pci_config = qlafx00_pci_config, 2069 .reset_chip = qlafx00_soft_reset, 2070 .chip_diag = qlafx00_chip_diag, 2071 .config_rings = qlafx00_config_rings, 2072 .reset_adapter = qlafx00_soft_reset, 2073 .nvram_config = NULL, 2074 .update_fw_options = NULL, 2075 .load_risc = NULL, 2076 .pci_info_str = qlafx00_pci_info_str, 2077 .fw_version_str = qlafx00_fw_version_str, 2078 .intr_handler = qlafx00_intr_handler, 2079 .enable_intrs = qlafx00_enable_intrs, 2080 .disable_intrs = qlafx00_disable_intrs, 2081 .abort_command = qlafx00_abort_command, 2082 .target_reset = qlafx00_abort_target, 2083 .lun_reset = qlafx00_lun_reset, 2084 .fabric_login = NULL, 2085 .fabric_logout = NULL, 2086 .calc_req_entries = NULL, 2087 .build_iocbs = NULL, 2088 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2089 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2090 .read_nvram = qla24xx_read_nvram_data, 2091 .write_nvram = qla24xx_write_nvram_data, 2092 .fw_dump = NULL, 2093 .beacon_on = qla24xx_beacon_on, 2094 .beacon_off = qla24xx_beacon_off, 2095 .beacon_blink = NULL, 2096 .read_optrom = qla24xx_read_optrom_data, 2097 .write_optrom = qla24xx_write_optrom_data, 2098 .get_flash_version = qla24xx_get_flash_version, 2099 .start_scsi = qlafx00_start_scsi, 2100 .abort_isp = qlafx00_abort_isp, 2101 .iospace_config = qlafx00_iospace_config, 2102 .initialize_adapter = qlafx00_initialize_adapter, 2103 }; 2104 2105 static inline void 2106 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2107 { 2108 ha->device_type = DT_EXTENDED_IDS; 2109 switch (ha->pdev->device) { 2110 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2111 ha->device_type |= DT_ISP2100; 2112 ha->device_type &= ~DT_EXTENDED_IDS; 2113 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2114 break; 2115 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2116 ha->device_type |= DT_ISP2200; 2117 ha->device_type &= ~DT_EXTENDED_IDS; 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2119 break; 2120 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2121 ha->device_type |= DT_ISP2300; 2122 ha->device_type |= DT_ZIO_SUPPORTED; 2123 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2124 break; 2125 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2126 ha->device_type |= DT_ISP2312; 2127 ha->device_type |= DT_ZIO_SUPPORTED; 2128 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2129 break; 2130 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2131 ha->device_type |= DT_ISP2322; 2132 ha->device_type |= DT_ZIO_SUPPORTED; 2133 if (ha->pdev->subsystem_vendor == 0x1028 && 2134 ha->pdev->subsystem_device == 0x0170) 2135 ha->device_type |= DT_OEM_001; 2136 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2137 break; 2138 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2139 ha->device_type |= DT_ISP6312; 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2141 break; 2142 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2143 ha->device_type |= DT_ISP6322; 2144 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2145 break; 2146 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2147 ha->device_type |= DT_ISP2422; 2148 ha->device_type |= DT_ZIO_SUPPORTED; 2149 ha->device_type |= DT_FWI2; 2150 ha->device_type |= DT_IIDMA; 2151 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2152 break; 2153 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2154 ha->device_type |= DT_ISP2432; 2155 ha->device_type |= DT_ZIO_SUPPORTED; 2156 ha->device_type |= DT_FWI2; 2157 ha->device_type |= DT_IIDMA; 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2159 break; 2160 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2161 ha->device_type |= DT_ISP8432; 2162 ha->device_type |= DT_ZIO_SUPPORTED; 2163 ha->device_type |= DT_FWI2; 2164 ha->device_type |= DT_IIDMA; 2165 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2166 break; 2167 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2168 ha->device_type |= DT_ISP5422; 2169 ha->device_type |= DT_FWI2; 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2171 break; 2172 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2173 ha->device_type |= DT_ISP5432; 2174 ha->device_type |= DT_FWI2; 2175 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2176 break; 2177 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2178 ha->device_type |= DT_ISP2532; 2179 ha->device_type |= DT_ZIO_SUPPORTED; 2180 ha->device_type |= DT_FWI2; 2181 ha->device_type |= DT_IIDMA; 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2183 break; 2184 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2185 ha->device_type |= DT_ISP8001; 2186 ha->device_type |= DT_ZIO_SUPPORTED; 2187 ha->device_type |= DT_FWI2; 2188 ha->device_type |= DT_IIDMA; 2189 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2190 break; 2191 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2192 ha->device_type |= DT_ISP8021; 2193 ha->device_type |= DT_ZIO_SUPPORTED; 2194 ha->device_type |= DT_FWI2; 2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2196 /* Initialize 82XX ISP flags */ 2197 qla82xx_init_flags(ha); 2198 break; 2199 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2200 ha->device_type |= DT_ISP8044; 2201 ha->device_type |= DT_ZIO_SUPPORTED; 2202 ha->device_type |= DT_FWI2; 2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2204 /* Initialize 82XX ISP flags */ 2205 qla82xx_init_flags(ha); 2206 break; 2207 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2208 ha->device_type |= DT_ISP2031; 2209 ha->device_type |= DT_ZIO_SUPPORTED; 2210 ha->device_type |= DT_FWI2; 2211 ha->device_type |= DT_IIDMA; 2212 ha->device_type |= DT_T10_PI; 2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2214 break; 2215 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2216 ha->device_type |= DT_ISP8031; 2217 ha->device_type |= DT_ZIO_SUPPORTED; 2218 ha->device_type |= DT_FWI2; 2219 ha->device_type |= DT_IIDMA; 2220 ha->device_type |= DT_T10_PI; 2221 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2222 break; 2223 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2224 ha->device_type |= DT_ISPFX00; 2225 break; 2226 } 2227 2228 if (IS_QLA82XX(ha)) 2229 ha->port_no = !(ha->portnum & 1); 2230 else 2231 /* Get adapter physical port no from interrupt pin register. */ 2232 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2233 2234 if (ha->port_no & 1) 2235 ha->flags.port0 = 1; 2236 else 2237 ha->flags.port0 = 0; 2238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2239 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2240 ha->device_type, ha->flags.port0, ha->fw_srisc_address); 2241 } 2242 2243 static void 2244 qla2xxx_scan_start(struct Scsi_Host *shost) 2245 { 2246 scsi_qla_host_t *vha = shost_priv(shost); 2247 2248 if (vha->hw->flags.running_gold_fw) 2249 return; 2250 2251 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2252 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2253 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2254 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2255 } 2256 2257 static int 2258 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2259 { 2260 scsi_qla_host_t *vha = shost_priv(shost); 2261 2262 if (!vha->host) 2263 return 1; 2264 if (time > vha->hw->loop_reset_delay * HZ) 2265 return 1; 2266 2267 return atomic_read(&vha->loop_state) == LOOP_READY; 2268 } 2269 2270 /* 2271 * PCI driver interface 2272 */ 2273 static int 2274 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2275 { 2276 int ret = -ENODEV; 2277 struct Scsi_Host *host; 2278 scsi_qla_host_t *base_vha = NULL; 2279 struct qla_hw_data *ha; 2280 char pci_info[30]; 2281 char fw_str[30], wq_name[30]; 2282 struct scsi_host_template *sht; 2283 int bars, mem_only = 0; 2284 uint16_t req_length = 0, rsp_length = 0; 2285 struct req_que *req = NULL; 2286 struct rsp_que *rsp = NULL; 2287 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2288 sht = &qla2xxx_driver_template; 2289 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) { 2301 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2302 mem_only = 1; 2303 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2304 "Mem only adapter.\n"); 2305 } 2306 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2307 "Bars=%d.\n", bars); 2308 2309 if (mem_only) { 2310 if (pci_enable_device_mem(pdev)) 2311 goto probe_out; 2312 } else { 2313 if (pci_enable_device(pdev)) 2314 goto probe_out; 2315 } 2316 2317 /* This may fail but that's ok */ 2318 pci_enable_pcie_error_reporting(pdev); 2319 2320 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2321 if (!ha) { 2322 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2323 "Unable to allocate memory for ha.\n"); 2324 goto probe_out; 2325 } 2326 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2327 "Memory allocated for ha=%p.\n", ha); 2328 ha->pdev = pdev; 2329 ha->tgt.enable_class_2 = ql2xenableclass2; 2330 2331 /* Clear our data area */ 2332 ha->bars = bars; 2333 ha->mem_only = mem_only; 2334 spin_lock_init(&ha->hardware_lock); 2335 spin_lock_init(&ha->vport_slock); 2336 mutex_init(&ha->selflogin_lock); 2337 2338 /* Set ISP-type information. */ 2339 qla2x00_set_isp_flags(ha); 2340 2341 /* Set EEH reset type to fundamental if required by hba */ 2342 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2343 IS_QLA83XX(ha)) 2344 pdev->needs_freset = 1; 2345 2346 ha->prev_topology = 0; 2347 ha->init_cb_size = sizeof(init_cb_t); 2348 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2349 ha->optrom_size = OPTROM_SIZE_2300; 2350 2351 /* Assign ISP specific operations. */ 2352 if (IS_QLA2100(ha)) { 2353 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2354 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2355 req_length = REQUEST_ENTRY_CNT_2100; 2356 rsp_length = RESPONSE_ENTRY_CNT_2100; 2357 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2358 ha->gid_list_info_size = 4; 2359 ha->flash_conf_off = ~0; 2360 ha->flash_data_off = ~0; 2361 ha->nvram_conf_off = ~0; 2362 ha->nvram_data_off = ~0; 2363 ha->isp_ops = &qla2100_isp_ops; 2364 } else if (IS_QLA2200(ha)) { 2365 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2366 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2367 req_length = REQUEST_ENTRY_CNT_2200; 2368 rsp_length = RESPONSE_ENTRY_CNT_2100; 2369 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2370 ha->gid_list_info_size = 4; 2371 ha->flash_conf_off = ~0; 2372 ha->flash_data_off = ~0; 2373 ha->nvram_conf_off = ~0; 2374 ha->nvram_data_off = ~0; 2375 ha->isp_ops = &qla2100_isp_ops; 2376 } else if (IS_QLA23XX(ha)) { 2377 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2378 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2379 req_length = REQUEST_ENTRY_CNT_2200; 2380 rsp_length = RESPONSE_ENTRY_CNT_2300; 2381 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2382 ha->gid_list_info_size = 6; 2383 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2384 ha->optrom_size = OPTROM_SIZE_2322; 2385 ha->flash_conf_off = ~0; 2386 ha->flash_data_off = ~0; 2387 ha->nvram_conf_off = ~0; 2388 ha->nvram_data_off = ~0; 2389 ha->isp_ops = &qla2300_isp_ops; 2390 } else if (IS_QLA24XX_TYPE(ha)) { 2391 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2392 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2393 req_length = REQUEST_ENTRY_CNT_24XX; 2394 rsp_length = RESPONSE_ENTRY_CNT_2300; 2395 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2396 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2397 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2398 ha->gid_list_info_size = 8; 2399 ha->optrom_size = OPTROM_SIZE_24XX; 2400 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2401 ha->isp_ops = &qla24xx_isp_ops; 2402 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2403 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2404 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2405 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2406 } else if (IS_QLA25XX(ha)) { 2407 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2408 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2409 req_length = REQUEST_ENTRY_CNT_24XX; 2410 rsp_length = RESPONSE_ENTRY_CNT_2300; 2411 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2413 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2414 ha->gid_list_info_size = 8; 2415 ha->optrom_size = OPTROM_SIZE_25XX; 2416 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2417 ha->isp_ops = &qla25xx_isp_ops; 2418 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2419 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2420 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2421 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2422 } else if (IS_QLA81XX(ha)) { 2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2424 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2425 req_length = REQUEST_ENTRY_CNT_24XX; 2426 rsp_length = RESPONSE_ENTRY_CNT_2300; 2427 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2428 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2429 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2430 ha->gid_list_info_size = 8; 2431 ha->optrom_size = OPTROM_SIZE_81XX; 2432 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2433 ha->isp_ops = &qla81xx_isp_ops; 2434 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2435 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2436 ha->nvram_conf_off = ~0; 2437 ha->nvram_data_off = ~0; 2438 } else if (IS_QLA82XX(ha)) { 2439 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2440 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2441 req_length = REQUEST_ENTRY_CNT_82XX; 2442 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2443 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2444 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2445 ha->gid_list_info_size = 8; 2446 ha->optrom_size = OPTROM_SIZE_82XX; 2447 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2448 ha->isp_ops = &qla82xx_isp_ops; 2449 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2450 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2451 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2452 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2453 } else if (IS_QLA8044(ha)) { 2454 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2455 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2456 req_length = REQUEST_ENTRY_CNT_82XX; 2457 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2458 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2459 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2460 ha->gid_list_info_size = 8; 2461 ha->optrom_size = OPTROM_SIZE_83XX; 2462 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2463 ha->isp_ops = &qla8044_isp_ops; 2464 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2465 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2466 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2467 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2468 } else if (IS_QLA83XX(ha)) { 2469 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2470 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2471 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2472 req_length = REQUEST_ENTRY_CNT_24XX; 2473 rsp_length = RESPONSE_ENTRY_CNT_2300; 2474 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2475 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2476 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2477 ha->gid_list_info_size = 8; 2478 ha->optrom_size = OPTROM_SIZE_83XX; 2479 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2480 ha->isp_ops = &qla83xx_isp_ops; 2481 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2482 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2483 ha->nvram_conf_off = ~0; 2484 ha->nvram_data_off = ~0; 2485 } else if (IS_QLAFX00(ha)) { 2486 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2487 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2488 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2489 req_length = REQUEST_ENTRY_CNT_FX00; 2490 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2491 ha->init_cb_size = sizeof(struct init_cb_fx); 2492 ha->isp_ops = &qlafx00_isp_ops; 2493 ha->port_down_retry_count = 30; /* default value */ 2494 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2495 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2496 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2497 ha->mr.fw_hbt_en = 1; 2498 ha->mr.host_info_resend = false; 2499 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2500 } 2501 2502 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2503 "mbx_count=%d, req_length=%d, " 2504 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2505 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2506 "max_fibre_devices=%d.\n", 2507 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2508 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2509 ha->nvram_npiv_size, ha->max_fibre_devices); 2510 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2511 "isp_ops=%p, flash_conf_off=%d, " 2512 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2513 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2514 ha->nvram_conf_off, ha->nvram_data_off); 2515 2516 /* Configure PCI I/O space */ 2517 ret = ha->isp_ops->iospace_config(ha); 2518 if (ret) 2519 goto iospace_config_failed; 2520 2521 ql_log_pci(ql_log_info, pdev, 0x001d, 2522 "Found an ISP%04X irq %d iobase 0x%p.\n", 2523 pdev->device, pdev->irq, ha->iobase); 2524 mutex_init(&ha->vport_lock); 2525 init_completion(&ha->mbx_cmd_comp); 2526 complete(&ha->mbx_cmd_comp); 2527 init_completion(&ha->mbx_intr_comp); 2528 init_completion(&ha->dcbx_comp); 2529 init_completion(&ha->lb_portup_comp); 2530 2531 set_bit(0, (unsigned long *) ha->vp_idx_map); 2532 2533 qla2x00_config_dma_addressing(ha); 2534 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2535 "64 Bit addressing is %s.\n", 2536 ha->flags.enable_64bit_addressing ? "enable" : 2537 "disable"); 2538 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2539 if (!ret) { 2540 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2541 "Failed to allocate memory for adapter, aborting.\n"); 2542 2543 goto probe_hw_failed; 2544 } 2545 2546 req->max_q_depth = MAX_Q_DEPTH; 2547 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2548 req->max_q_depth = ql2xmaxqdepth; 2549 2550 2551 base_vha = qla2x00_create_host(sht, ha); 2552 if (!base_vha) { 2553 ret = -ENOMEM; 2554 qla2x00_mem_free(ha); 2555 qla2x00_free_req_que(ha, req); 2556 qla2x00_free_rsp_que(ha, rsp); 2557 goto probe_hw_failed; 2558 } 2559 2560 pci_set_drvdata(pdev, base_vha); 2561 2562 host = base_vha->host; 2563 base_vha->req = req; 2564 if (IS_QLAFX00(ha)) 2565 host->can_queue = QLAFX00_MAX_CANQUEUE; 2566 else 2567 host->can_queue = req->length + 128; 2568 if (IS_QLA2XXX_MIDTYPE(ha)) 2569 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2570 else 2571 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2572 base_vha->vp_idx; 2573 2574 /* Setup fcport template structure. */ 2575 ha->mr.fcport.vha = base_vha; 2576 ha->mr.fcport.port_type = FCT_UNKNOWN; 2577 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2578 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2579 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2580 ha->mr.fcport.scan_state = 1; 2581 2582 /* Set the SG table size based on ISP type */ 2583 if (!IS_FWI2_CAPABLE(ha)) { 2584 if (IS_QLA2100(ha)) 2585 host->sg_tablesize = 32; 2586 } else { 2587 if (!IS_QLA82XX(ha)) 2588 host->sg_tablesize = QLA_SG_ALL; 2589 } 2590 ql_dbg(ql_dbg_init, base_vha, 0x0032, 2591 "can_queue=%d, req=%p, " 2592 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 2593 host->can_queue, base_vha->req, 2594 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 2595 host->max_id = ha->max_fibre_devices; 2596 host->cmd_per_lun = 3; 2597 host->unique_id = host->host_no; 2598 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2599 host->max_cmd_len = 32; 2600 else 2601 host->max_cmd_len = MAX_CMDSZ; 2602 host->max_channel = MAX_BUSES - 1; 2603 host->max_lun = ql2xmaxlun; 2604 host->transportt = qla2xxx_transport_template; 2605 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2606 2607 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2608 "max_id=%d this_id=%d " 2609 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2610 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, 2611 host->this_id, host->cmd_per_lun, host->unique_id, 2612 host->max_cmd_len, host->max_channel, host->max_lun, 2613 host->transportt, sht->vendor_id); 2614 2615 que_init: 2616 /* Alloc arrays of request and response ring ptrs */ 2617 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2618 ql_log(ql_log_fatal, base_vha, 0x003d, 2619 "Failed to allocate memory for queue pointers..." 2620 "aborting.\n"); 2621 goto probe_init_failed; 2622 } 2623 2624 qlt_probe_one_stage1(base_vha, ha); 2625 2626 /* Set up the irqs */ 2627 ret = qla2x00_request_irqs(ha, rsp); 2628 if (ret) 2629 goto probe_init_failed; 2630 2631 pci_save_state(pdev); 2632 2633 /* Assign back pointers */ 2634 rsp->req = req; 2635 req->rsp = rsp; 2636 2637 if (IS_QLAFX00(ha)) { 2638 ha->rsp_q_map[0] = rsp; 2639 ha->req_q_map[0] = req; 2640 set_bit(0, ha->req_qid_map); 2641 set_bit(0, ha->rsp_qid_map); 2642 } 2643 2644 /* FWI2-capable only. */ 2645 req->req_q_in = &ha->iobase->isp24.req_q_in; 2646 req->req_q_out = &ha->iobase->isp24.req_q_out; 2647 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2648 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2649 if (ha->mqenable || IS_QLA83XX(ha)) { 2650 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2651 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2652 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 2653 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 2654 } 2655 2656 if (IS_QLAFX00(ha)) { 2657 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 2658 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 2659 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 2660 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 2661 } 2662 2663 if (IS_P3P_TYPE(ha)) { 2664 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 2665 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 2666 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 2667 } 2668 2669 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 2670 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2671 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2672 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 2673 "req->req_q_in=%p req->req_q_out=%p " 2674 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2675 req->req_q_in, req->req_q_out, 2676 rsp->rsp_q_in, rsp->rsp_q_out); 2677 ql_dbg(ql_dbg_init, base_vha, 0x003e, 2678 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 2679 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 2680 ql_dbg(ql_dbg_init, base_vha, 0x003f, 2681 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 2682 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 2683 2684 if (ha->isp_ops->initialize_adapter(base_vha)) { 2685 ql_log(ql_log_fatal, base_vha, 0x00d6, 2686 "Failed to initialize adapter - Adapter flags %x.\n", 2687 base_vha->device_flags); 2688 2689 if (IS_QLA82XX(ha)) { 2690 qla82xx_idc_lock(ha); 2691 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2692 QLA8XXX_DEV_FAILED); 2693 qla82xx_idc_unlock(ha); 2694 ql_log(ql_log_fatal, base_vha, 0x00d7, 2695 "HW State: FAILED.\n"); 2696 } else if (IS_QLA8044(ha)) { 2697 qla8044_idc_lock(ha); 2698 qla8044_wr_direct(base_vha, 2699 QLA8044_CRB_DEV_STATE_INDEX, 2700 QLA8XXX_DEV_FAILED); 2701 qla8044_idc_unlock(ha); 2702 ql_log(ql_log_fatal, base_vha, 0x0150, 2703 "HW State: FAILED.\n"); 2704 } 2705 2706 ret = -ENODEV; 2707 goto probe_failed; 2708 } 2709 2710 if (ha->mqenable) { 2711 if (qla25xx_setup_mode(base_vha)) { 2712 ql_log(ql_log_warn, base_vha, 0x00ec, 2713 "Failed to create queues, falling back to single queue mode.\n"); 2714 goto que_init; 2715 } 2716 } 2717 2718 if (ha->flags.running_gold_fw) 2719 goto skip_dpc; 2720 2721 /* 2722 * Startup the kernel thread for this host adapter 2723 */ 2724 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 2725 "%s_dpc", base_vha->host_str); 2726 if (IS_ERR(ha->dpc_thread)) { 2727 ql_log(ql_log_fatal, base_vha, 0x00ed, 2728 "Failed to start DPC thread.\n"); 2729 ret = PTR_ERR(ha->dpc_thread); 2730 goto probe_failed; 2731 } 2732 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 2733 "DPC thread started successfully.\n"); 2734 2735 /* 2736 * If we're not coming up in initiator mode, we might sit for 2737 * a while without waking up the dpc thread, which leads to a 2738 * stuck process warning. So just kick the dpc once here and 2739 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 2740 */ 2741 qla2xxx_wake_dpc(base_vha); 2742 2743 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 2744 2745 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 2746 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 2747 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 2748 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 2749 2750 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 2751 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 2752 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 2753 INIT_WORK(&ha->idc_state_handler, 2754 qla83xx_idc_state_handler_work); 2755 INIT_WORK(&ha->nic_core_unrecoverable, 2756 qla83xx_nic_core_unrecoverable_work); 2757 } 2758 2759 skip_dpc: 2760 list_add_tail(&base_vha->list, &ha->vp_list); 2761 base_vha->host->irq = ha->pdev->irq; 2762 2763 /* Initialized the timer */ 2764 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 2765 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 2766 "Started qla2x00_timer with " 2767 "interval=%d.\n", WATCH_INTERVAL); 2768 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 2769 "Detected hba at address=%p.\n", 2770 ha); 2771 2772 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 2773 if (ha->fw_attributes & BIT_4) { 2774 int prot = 0, guard; 2775 base_vha->flags.difdix_supported = 1; 2776 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 2777 "Registering for DIF/DIX type 1 and 3 protection.\n"); 2778 if (ql2xenabledif == 1) 2779 prot = SHOST_DIX_TYPE0_PROTECTION; 2780 scsi_host_set_prot(host, 2781 prot | SHOST_DIF_TYPE1_PROTECTION 2782 | SHOST_DIF_TYPE2_PROTECTION 2783 | SHOST_DIF_TYPE3_PROTECTION 2784 | SHOST_DIX_TYPE1_PROTECTION 2785 | SHOST_DIX_TYPE2_PROTECTION 2786 | SHOST_DIX_TYPE3_PROTECTION); 2787 2788 guard = SHOST_DIX_GUARD_CRC; 2789 2790 if (IS_PI_IPGUARD_CAPABLE(ha) && 2791 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 2792 guard |= SHOST_DIX_GUARD_IP; 2793 2794 scsi_host_set_guard(host, guard); 2795 } else 2796 base_vha->flags.difdix_supported = 0; 2797 } 2798 2799 ha->isp_ops->enable_intrs(ha); 2800 2801 if (IS_QLAFX00(ha)) { 2802 ret = qlafx00_fx_disc(base_vha, 2803 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 2804 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 2805 QLA_SG_ALL : 128; 2806 } 2807 2808 ret = scsi_add_host(host, &pdev->dev); 2809 if (ret) 2810 goto probe_failed; 2811 2812 base_vha->flags.init_done = 1; 2813 base_vha->flags.online = 1; 2814 2815 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 2816 "Init done and hba is online.\n"); 2817 2818 if (qla_ini_mode_enabled(base_vha)) 2819 scsi_scan_host(host); 2820 else 2821 ql_dbg(ql_dbg_init, base_vha, 0x0122, 2822 "skipping scsi_scan_host() for non-initiator port\n"); 2823 2824 qla2x00_alloc_sysfs_attr(base_vha); 2825 2826 if (IS_QLAFX00(ha)) { 2827 ret = qlafx00_fx_disc(base_vha, 2828 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 2829 2830 /* Register system information */ 2831 ret = qlafx00_fx_disc(base_vha, 2832 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 2833 } 2834 2835 qla2x00_init_host_attr(base_vha); 2836 2837 qla2x00_dfs_setup(base_vha); 2838 2839 ql_log(ql_log_info, base_vha, 0x00fb, 2840 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 2841 ql_log(ql_log_info, base_vha, 0x00fc, 2842 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 2843 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 2844 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 2845 base_vha->host_no, 2846 ha->isp_ops->fw_version_str(base_vha, fw_str)); 2847 2848 qlt_add_target(ha, base_vha); 2849 2850 return 0; 2851 2852 probe_init_failed: 2853 qla2x00_free_req_que(ha, req); 2854 ha->req_q_map[0] = NULL; 2855 clear_bit(0, ha->req_qid_map); 2856 qla2x00_free_rsp_que(ha, rsp); 2857 ha->rsp_q_map[0] = NULL; 2858 clear_bit(0, ha->rsp_qid_map); 2859 ha->max_req_queues = ha->max_rsp_queues = 0; 2860 2861 probe_failed: 2862 if (base_vha->timer_active) 2863 qla2x00_stop_timer(base_vha); 2864 base_vha->flags.online = 0; 2865 if (ha->dpc_thread) { 2866 struct task_struct *t = ha->dpc_thread; 2867 2868 ha->dpc_thread = NULL; 2869 kthread_stop(t); 2870 } 2871 2872 qla2x00_free_device(base_vha); 2873 2874 scsi_host_put(base_vha->host); 2875 2876 probe_hw_failed: 2877 if (IS_QLA82XX(ha)) { 2878 qla82xx_idc_lock(ha); 2879 qla82xx_clear_drv_active(ha); 2880 qla82xx_idc_unlock(ha); 2881 } 2882 if (IS_QLA8044(ha)) { 2883 qla8044_idc_lock(ha); 2884 qla8044_clear_drv_active(ha); 2885 qla8044_idc_unlock(ha); 2886 } 2887 iospace_config_failed: 2888 if (IS_P3P_TYPE(ha)) { 2889 if (!ha->nx_pcibase) 2890 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 2891 if (!ql2xdbwr) 2892 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 2893 } else { 2894 if (ha->iobase) 2895 iounmap(ha->iobase); 2896 if (ha->cregbase) 2897 iounmap(ha->cregbase); 2898 } 2899 pci_release_selected_regions(ha->pdev, ha->bars); 2900 kfree(ha); 2901 ha = NULL; 2902 2903 probe_out: 2904 pci_disable_device(pdev); 2905 return ret; 2906 } 2907 2908 static void 2909 qla2x00_shutdown(struct pci_dev *pdev) 2910 { 2911 scsi_qla_host_t *vha; 2912 struct qla_hw_data *ha; 2913 2914 if (!atomic_read(&pdev->enable_cnt)) 2915 return; 2916 2917 vha = pci_get_drvdata(pdev); 2918 ha = vha->hw; 2919 2920 /* Notify ISPFX00 firmware */ 2921 if (IS_QLAFX00(ha)) 2922 qlafx00_driver_shutdown(vha, 20); 2923 2924 /* Turn-off FCE trace */ 2925 if (ha->flags.fce_enabled) { 2926 qla2x00_disable_fce_trace(vha, NULL, NULL); 2927 ha->flags.fce_enabled = 0; 2928 } 2929 2930 /* Turn-off EFT trace */ 2931 if (ha->eft) 2932 qla2x00_disable_eft_trace(vha); 2933 2934 /* Stop currently executing firmware. */ 2935 qla2x00_try_to_stop_firmware(vha); 2936 2937 /* Turn adapter off line */ 2938 vha->flags.online = 0; 2939 2940 /* turn-off interrupts on the card */ 2941 if (ha->interrupts_on) { 2942 vha->flags.init_done = 0; 2943 ha->isp_ops->disable_intrs(ha); 2944 } 2945 2946 qla2x00_free_irqs(vha); 2947 2948 qla2x00_free_fw_dump(ha); 2949 } 2950 2951 /* Deletes all the virtual ports for a given ha */ 2952 static void 2953 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 2954 { 2955 struct Scsi_Host *scsi_host; 2956 scsi_qla_host_t *vha; 2957 unsigned long flags; 2958 2959 mutex_lock(&ha->vport_lock); 2960 while (ha->cur_vport_count) { 2961 spin_lock_irqsave(&ha->vport_slock, flags); 2962 2963 BUG_ON(base_vha->list.next == &ha->vp_list); 2964 /* This assumes first entry in ha->vp_list is always base vha */ 2965 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 2966 scsi_host = scsi_host_get(vha->host); 2967 2968 spin_unlock_irqrestore(&ha->vport_slock, flags); 2969 mutex_unlock(&ha->vport_lock); 2970 2971 fc_vport_terminate(vha->fc_vport); 2972 scsi_host_put(vha->host); 2973 2974 mutex_lock(&ha->vport_lock); 2975 } 2976 mutex_unlock(&ha->vport_lock); 2977 } 2978 2979 /* Stops all deferred work threads */ 2980 static void 2981 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 2982 { 2983 /* Flush the work queue and remove it */ 2984 if (ha->wq) { 2985 flush_workqueue(ha->wq); 2986 destroy_workqueue(ha->wq); 2987 ha->wq = NULL; 2988 } 2989 2990 /* Cancel all work and destroy DPC workqueues */ 2991 if (ha->dpc_lp_wq) { 2992 cancel_work_sync(&ha->idc_aen); 2993 destroy_workqueue(ha->dpc_lp_wq); 2994 ha->dpc_lp_wq = NULL; 2995 } 2996 2997 if (ha->dpc_hp_wq) { 2998 cancel_work_sync(&ha->nic_core_reset); 2999 cancel_work_sync(&ha->idc_state_handler); 3000 cancel_work_sync(&ha->nic_core_unrecoverable); 3001 destroy_workqueue(ha->dpc_hp_wq); 3002 ha->dpc_hp_wq = NULL; 3003 } 3004 3005 /* Kill the kernel thread for this host */ 3006 if (ha->dpc_thread) { 3007 struct task_struct *t = ha->dpc_thread; 3008 3009 /* 3010 * qla2xxx_wake_dpc checks for ->dpc_thread 3011 * so we need to zero it out. 3012 */ 3013 ha->dpc_thread = NULL; 3014 kthread_stop(t); 3015 } 3016 } 3017 3018 static void 3019 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3020 { 3021 if (IS_QLA82XX(ha)) { 3022 3023 iounmap((device_reg_t __iomem *)ha->nx_pcibase); 3024 if (!ql2xdbwr) 3025 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); 3026 } else { 3027 if (ha->iobase) 3028 iounmap(ha->iobase); 3029 3030 if (ha->cregbase) 3031 iounmap(ha->cregbase); 3032 3033 if (ha->mqiobase) 3034 iounmap(ha->mqiobase); 3035 3036 if (IS_QLA83XX(ha) && ha->msixbase) 3037 iounmap(ha->msixbase); 3038 } 3039 } 3040 3041 static void 3042 qla2x00_clear_drv_active(scsi_qla_host_t *vha) 3043 { 3044 struct qla_hw_data *ha = vha->hw; 3045 3046 if (IS_QLA8044(ha)) { 3047 qla8044_idc_lock(ha); 3048 qla8044_clear_drv_active(ha); 3049 qla8044_idc_unlock(ha); 3050 } else if (IS_QLA82XX(ha)) { 3051 qla82xx_idc_lock(ha); 3052 qla82xx_clear_drv_active(ha); 3053 qla82xx_idc_unlock(ha); 3054 } 3055 } 3056 3057 static void 3058 qla2x00_remove_one(struct pci_dev *pdev) 3059 { 3060 scsi_qla_host_t *base_vha; 3061 struct qla_hw_data *ha; 3062 3063 /* 3064 * If the PCI device is disabled that means that probe failed and any 3065 * resources should be have cleaned up on probe exit. 3066 */ 3067 if (!atomic_read(&pdev->enable_cnt)) 3068 return; 3069 3070 base_vha = pci_get_drvdata(pdev); 3071 ha = base_vha->hw; 3072 3073 set_bit(UNLOADING, &base_vha->dpc_flags); 3074 3075 if (IS_QLAFX00(ha)) 3076 qlafx00_driver_shutdown(base_vha, 20); 3077 3078 qla2x00_delete_all_vps(ha, base_vha); 3079 3080 if (IS_QLA8031(ha)) { 3081 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3082 "Clearing fcoe driver presence.\n"); 3083 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3084 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3085 "Error while clearing DRV-Presence.\n"); 3086 } 3087 3088 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3089 3090 qla2x00_dfs_remove(base_vha); 3091 3092 qla84xx_put_chip(base_vha); 3093 3094 /* Disable timer */ 3095 if (base_vha->timer_active) 3096 qla2x00_stop_timer(base_vha); 3097 3098 base_vha->flags.online = 0; 3099 3100 qla2x00_destroy_deferred_work(ha); 3101 3102 qlt_remove_target(ha, base_vha); 3103 3104 qla2x00_free_sysfs_attr(base_vha, true); 3105 3106 fc_remove_host(base_vha->host); 3107 3108 scsi_remove_host(base_vha->host); 3109 3110 qla2x00_free_device(base_vha); 3111 3112 scsi_host_put(base_vha->host); 3113 3114 qla2x00_clear_drv_active(base_vha); 3115 3116 qla2x00_unmap_iobases(ha); 3117 3118 pci_release_selected_regions(ha->pdev, ha->bars); 3119 kfree(ha); 3120 ha = NULL; 3121 3122 pci_disable_pcie_error_reporting(pdev); 3123 3124 pci_disable_device(pdev); 3125 } 3126 3127 static void 3128 qla2x00_free_device(scsi_qla_host_t *vha) 3129 { 3130 struct qla_hw_data *ha = vha->hw; 3131 3132 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3133 3134 /* Disable timer */ 3135 if (vha->timer_active) 3136 qla2x00_stop_timer(vha); 3137 3138 qla25xx_delete_queues(vha); 3139 3140 if (ha->flags.fce_enabled) 3141 qla2x00_disable_fce_trace(vha, NULL, NULL); 3142 3143 if (ha->eft) 3144 qla2x00_disable_eft_trace(vha); 3145 3146 /* Stop currently executing firmware. */ 3147 qla2x00_try_to_stop_firmware(vha); 3148 3149 vha->flags.online = 0; 3150 3151 /* turn-off interrupts on the card */ 3152 if (ha->interrupts_on) { 3153 vha->flags.init_done = 0; 3154 ha->isp_ops->disable_intrs(ha); 3155 } 3156 3157 qla2x00_free_irqs(vha); 3158 3159 qla2x00_free_fcports(vha); 3160 3161 qla2x00_mem_free(ha); 3162 3163 qla82xx_md_free(vha); 3164 3165 qla2x00_free_queues(ha); 3166 } 3167 3168 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3169 { 3170 fc_port_t *fcport, *tfcport; 3171 3172 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3173 list_del(&fcport->list); 3174 qla2x00_clear_loop_id(fcport); 3175 kfree(fcport); 3176 fcport = NULL; 3177 } 3178 } 3179 3180 static inline void 3181 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3182 int defer) 3183 { 3184 struct fc_rport *rport; 3185 scsi_qla_host_t *base_vha; 3186 unsigned long flags; 3187 3188 if (!fcport->rport) 3189 return; 3190 3191 rport = fcport->rport; 3192 if (defer) { 3193 base_vha = pci_get_drvdata(vha->hw->pdev); 3194 spin_lock_irqsave(vha->host->host_lock, flags); 3195 fcport->drport = rport; 3196 spin_unlock_irqrestore(vha->host->host_lock, flags); 3197 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3198 qla2xxx_wake_dpc(base_vha); 3199 } else { 3200 fc_remote_port_delete(rport); 3201 qlt_fc_port_deleted(vha, fcport); 3202 } 3203 } 3204 3205 /* 3206 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3207 * 3208 * Input: ha = adapter block pointer. fcport = port structure pointer. 3209 * 3210 * Return: None. 3211 * 3212 * Context: 3213 */ 3214 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3215 int do_login, int defer) 3216 { 3217 if (IS_QLAFX00(vha->hw)) { 3218 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3219 qla2x00_schedule_rport_del(vha, fcport, defer); 3220 return; 3221 } 3222 3223 if (atomic_read(&fcport->state) == FCS_ONLINE && 3224 vha->vp_idx == fcport->vha->vp_idx) { 3225 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3226 qla2x00_schedule_rport_del(vha, fcport, defer); 3227 } 3228 /* 3229 * We may need to retry the login, so don't change the state of the 3230 * port but do the retries. 3231 */ 3232 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3233 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3234 3235 if (!do_login) 3236 return; 3237 3238 if (fcport->login_retry == 0) { 3239 fcport->login_retry = vha->hw->login_retry_count; 3240 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3241 3242 ql_dbg(ql_dbg_disc, vha, 0x2067, 3243 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", 3244 fcport->port_name, fcport->loop_id, fcport->login_retry); 3245 } 3246 } 3247 3248 /* 3249 * qla2x00_mark_all_devices_lost 3250 * Updates fcport state when device goes offline. 3251 * 3252 * Input: 3253 * ha = adapter block pointer. 3254 * fcport = port structure pointer. 3255 * 3256 * Return: 3257 * None. 3258 * 3259 * Context: 3260 */ 3261 void 3262 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3263 { 3264 fc_port_t *fcport; 3265 3266 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3267 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3268 continue; 3269 3270 /* 3271 * No point in marking the device as lost, if the device is 3272 * already DEAD. 3273 */ 3274 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3275 continue; 3276 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3277 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3278 if (defer) 3279 qla2x00_schedule_rport_del(vha, fcport, defer); 3280 else if (vha->vp_idx == fcport->vha->vp_idx) 3281 qla2x00_schedule_rport_del(vha, fcport, defer); 3282 } 3283 } 3284 } 3285 3286 /* 3287 * qla2x00_mem_alloc 3288 * Allocates adapter memory. 3289 * 3290 * Returns: 3291 * 0 = success. 3292 * !0 = failure. 3293 */ 3294 static int 3295 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3296 struct req_que **req, struct rsp_que **rsp) 3297 { 3298 char name[16]; 3299 3300 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3301 &ha->init_cb_dma, GFP_KERNEL); 3302 if (!ha->init_cb) 3303 goto fail; 3304 3305 if (qlt_mem_alloc(ha) < 0) 3306 goto fail_free_init_cb; 3307 3308 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3309 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3310 if (!ha->gid_list) 3311 goto fail_free_tgt_mem; 3312 3313 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3314 if (!ha->srb_mempool) 3315 goto fail_free_gid_list; 3316 3317 if (IS_P3P_TYPE(ha)) { 3318 /* Allocate cache for CT6 Ctx. */ 3319 if (!ctx_cachep) { 3320 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3321 sizeof(struct ct6_dsd), 0, 3322 SLAB_HWCACHE_ALIGN, NULL); 3323 if (!ctx_cachep) 3324 goto fail_free_gid_list; 3325 } 3326 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3327 ctx_cachep); 3328 if (!ha->ctx_mempool) 3329 goto fail_free_srb_mempool; 3330 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3331 "ctx_cachep=%p ctx_mempool=%p.\n", 3332 ctx_cachep, ha->ctx_mempool); 3333 } 3334 3335 /* Get memory for cached NVRAM */ 3336 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3337 if (!ha->nvram) 3338 goto fail_free_ctx_mempool; 3339 3340 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3341 ha->pdev->device); 3342 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3343 DMA_POOL_SIZE, 8, 0); 3344 if (!ha->s_dma_pool) 3345 goto fail_free_nvram; 3346 3347 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3348 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3349 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3350 3351 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3352 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3353 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3354 if (!ha->dl_dma_pool) { 3355 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3356 "Failed to allocate memory for dl_dma_pool.\n"); 3357 goto fail_s_dma_pool; 3358 } 3359 3360 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3361 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3362 if (!ha->fcp_cmnd_dma_pool) { 3363 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3364 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3365 goto fail_dl_dma_pool; 3366 } 3367 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3368 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3369 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3370 } 3371 3372 /* Allocate memory for SNS commands */ 3373 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3374 /* Get consistent memory allocated for SNS commands */ 3375 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3376 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3377 if (!ha->sns_cmd) 3378 goto fail_dma_pool; 3379 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3380 "sns_cmd: %p.\n", ha->sns_cmd); 3381 } else { 3382 /* Get consistent memory allocated for MS IOCB */ 3383 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3384 &ha->ms_iocb_dma); 3385 if (!ha->ms_iocb) 3386 goto fail_dma_pool; 3387 /* Get consistent memory allocated for CT SNS commands */ 3388 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3389 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3390 if (!ha->ct_sns) 3391 goto fail_free_ms_iocb; 3392 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3393 "ms_iocb=%p ct_sns=%p.\n", 3394 ha->ms_iocb, ha->ct_sns); 3395 } 3396 3397 /* Allocate memory for request ring */ 3398 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3399 if (!*req) { 3400 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3401 "Failed to allocate memory for req.\n"); 3402 goto fail_req; 3403 } 3404 (*req)->length = req_len; 3405 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3406 ((*req)->length + 1) * sizeof(request_t), 3407 &(*req)->dma, GFP_KERNEL); 3408 if (!(*req)->ring) { 3409 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3410 "Failed to allocate memory for req_ring.\n"); 3411 goto fail_req_ring; 3412 } 3413 /* Allocate memory for response ring */ 3414 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3415 if (!*rsp) { 3416 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3417 "Failed to allocate memory for rsp.\n"); 3418 goto fail_rsp; 3419 } 3420 (*rsp)->hw = ha; 3421 (*rsp)->length = rsp_len; 3422 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3423 ((*rsp)->length + 1) * sizeof(response_t), 3424 &(*rsp)->dma, GFP_KERNEL); 3425 if (!(*rsp)->ring) { 3426 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3427 "Failed to allocate memory for rsp_ring.\n"); 3428 goto fail_rsp_ring; 3429 } 3430 (*req)->rsp = *rsp; 3431 (*rsp)->req = *req; 3432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3433 "req=%p req->length=%d req->ring=%p rsp=%p " 3434 "rsp->length=%d rsp->ring=%p.\n", 3435 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3436 (*rsp)->ring); 3437 /* Allocate memory for NVRAM data for vports */ 3438 if (ha->nvram_npiv_size) { 3439 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3440 ha->nvram_npiv_size, GFP_KERNEL); 3441 if (!ha->npiv_info) { 3442 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3443 "Failed to allocate memory for npiv_info.\n"); 3444 goto fail_npiv_info; 3445 } 3446 } else 3447 ha->npiv_info = NULL; 3448 3449 /* Get consistent memory allocated for EX-INIT-CB. */ 3450 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) { 3451 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3452 &ha->ex_init_cb_dma); 3453 if (!ha->ex_init_cb) 3454 goto fail_ex_init_cb; 3455 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3456 "ex_init_cb=%p.\n", ha->ex_init_cb); 3457 } 3458 3459 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3460 3461 /* Get consistent memory allocated for Async Port-Database. */ 3462 if (!IS_FWI2_CAPABLE(ha)) { 3463 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3464 &ha->async_pd_dma); 3465 if (!ha->async_pd) 3466 goto fail_async_pd; 3467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3468 "async_pd=%p.\n", ha->async_pd); 3469 } 3470 3471 INIT_LIST_HEAD(&ha->vp_list); 3472 3473 /* Allocate memory for our loop_id bitmap */ 3474 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3475 GFP_KERNEL); 3476 if (!ha->loop_id_map) 3477 goto fail_async_pd; 3478 else { 3479 qla2x00_set_reserved_loop_ids(ha); 3480 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3481 "loop_id_map=%p. \n", ha->loop_id_map); 3482 } 3483 3484 return 1; 3485 3486 fail_async_pd: 3487 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3488 fail_ex_init_cb: 3489 kfree(ha->npiv_info); 3490 fail_npiv_info: 3491 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3492 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3493 (*rsp)->ring = NULL; 3494 (*rsp)->dma = 0; 3495 fail_rsp_ring: 3496 kfree(*rsp); 3497 fail_rsp: 3498 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3499 sizeof(request_t), (*req)->ring, (*req)->dma); 3500 (*req)->ring = NULL; 3501 (*req)->dma = 0; 3502 fail_req_ring: 3503 kfree(*req); 3504 fail_req: 3505 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3506 ha->ct_sns, ha->ct_sns_dma); 3507 ha->ct_sns = NULL; 3508 ha->ct_sns_dma = 0; 3509 fail_free_ms_iocb: 3510 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3511 ha->ms_iocb = NULL; 3512 ha->ms_iocb_dma = 0; 3513 fail_dma_pool: 3514 if (IS_QLA82XX(ha) || ql2xenabledif) { 3515 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3516 ha->fcp_cmnd_dma_pool = NULL; 3517 } 3518 fail_dl_dma_pool: 3519 if (IS_QLA82XX(ha) || ql2xenabledif) { 3520 dma_pool_destroy(ha->dl_dma_pool); 3521 ha->dl_dma_pool = NULL; 3522 } 3523 fail_s_dma_pool: 3524 dma_pool_destroy(ha->s_dma_pool); 3525 ha->s_dma_pool = NULL; 3526 fail_free_nvram: 3527 kfree(ha->nvram); 3528 ha->nvram = NULL; 3529 fail_free_ctx_mempool: 3530 mempool_destroy(ha->ctx_mempool); 3531 ha->ctx_mempool = NULL; 3532 fail_free_srb_mempool: 3533 mempool_destroy(ha->srb_mempool); 3534 ha->srb_mempool = NULL; 3535 fail_free_gid_list: 3536 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3537 ha->gid_list, 3538 ha->gid_list_dma); 3539 ha->gid_list = NULL; 3540 ha->gid_list_dma = 0; 3541 fail_free_tgt_mem: 3542 qlt_mem_free(ha); 3543 fail_free_init_cb: 3544 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3545 ha->init_cb_dma); 3546 ha->init_cb = NULL; 3547 ha->init_cb_dma = 0; 3548 fail: 3549 ql_log(ql_log_fatal, NULL, 0x0030, 3550 "Memory allocation failure.\n"); 3551 return -ENOMEM; 3552 } 3553 3554 /* 3555 * qla2x00_free_fw_dump 3556 * Frees fw dump stuff. 3557 * 3558 * Input: 3559 * ha = adapter block pointer 3560 */ 3561 static void 3562 qla2x00_free_fw_dump(struct qla_hw_data *ha) 3563 { 3564 if (ha->fce) 3565 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 3566 ha->fce_dma); 3567 3568 if (ha->fw_dump) { 3569 if (ha->eft) 3570 dma_free_coherent(&ha->pdev->dev, 3571 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); 3572 vfree(ha->fw_dump); 3573 } 3574 ha->fce = NULL; 3575 ha->fce_dma = 0; 3576 ha->eft = NULL; 3577 ha->eft_dma = 0; 3578 ha->fw_dump = NULL; 3579 ha->fw_dumped = 0; 3580 ha->fw_dump_reading = 0; 3581 } 3582 3583 /* 3584 * qla2x00_mem_free 3585 * Frees all adapter allocated memory. 3586 * 3587 * Input: 3588 * ha = adapter block pointer. 3589 */ 3590 static void 3591 qla2x00_mem_free(struct qla_hw_data *ha) 3592 { 3593 qla2x00_free_fw_dump(ha); 3594 3595 if (ha->mctp_dump) 3596 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 3597 ha->mctp_dump_dma); 3598 3599 if (ha->srb_mempool) 3600 mempool_destroy(ha->srb_mempool); 3601 3602 if (ha->dcbx_tlv) 3603 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 3604 ha->dcbx_tlv, ha->dcbx_tlv_dma); 3605 3606 if (ha->xgmac_data) 3607 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 3608 ha->xgmac_data, ha->xgmac_data_dma); 3609 3610 if (ha->sns_cmd) 3611 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3612 ha->sns_cmd, ha->sns_cmd_dma); 3613 3614 if (ha->ct_sns) 3615 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3616 ha->ct_sns, ha->ct_sns_dma); 3617 3618 if (ha->sfp_data) 3619 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 3620 3621 if (ha->ms_iocb) 3622 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3623 3624 if (ha->ex_init_cb) 3625 dma_pool_free(ha->s_dma_pool, 3626 ha->ex_init_cb, ha->ex_init_cb_dma); 3627 3628 if (ha->async_pd) 3629 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3630 3631 if (ha->s_dma_pool) 3632 dma_pool_destroy(ha->s_dma_pool); 3633 3634 if (ha->gid_list) 3635 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3636 ha->gid_list, ha->gid_list_dma); 3637 3638 if (IS_QLA82XX(ha)) { 3639 if (!list_empty(&ha->gbl_dsd_list)) { 3640 struct dsd_dma *dsd_ptr, *tdsd_ptr; 3641 3642 /* clean up allocated prev pool */ 3643 list_for_each_entry_safe(dsd_ptr, 3644 tdsd_ptr, &ha->gbl_dsd_list, list) { 3645 dma_pool_free(ha->dl_dma_pool, 3646 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 3647 list_del(&dsd_ptr->list); 3648 kfree(dsd_ptr); 3649 } 3650 } 3651 } 3652 3653 if (ha->dl_dma_pool) 3654 dma_pool_destroy(ha->dl_dma_pool); 3655 3656 if (ha->fcp_cmnd_dma_pool) 3657 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3658 3659 if (ha->ctx_mempool) 3660 mempool_destroy(ha->ctx_mempool); 3661 3662 qlt_mem_free(ha); 3663 3664 if (ha->init_cb) 3665 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 3666 ha->init_cb, ha->init_cb_dma); 3667 vfree(ha->optrom_buffer); 3668 kfree(ha->nvram); 3669 kfree(ha->npiv_info); 3670 kfree(ha->swl); 3671 kfree(ha->loop_id_map); 3672 3673 ha->srb_mempool = NULL; 3674 ha->ctx_mempool = NULL; 3675 ha->sns_cmd = NULL; 3676 ha->sns_cmd_dma = 0; 3677 ha->ct_sns = NULL; 3678 ha->ct_sns_dma = 0; 3679 ha->ms_iocb = NULL; 3680 ha->ms_iocb_dma = 0; 3681 ha->init_cb = NULL; 3682 ha->init_cb_dma = 0; 3683 ha->ex_init_cb = NULL; 3684 ha->ex_init_cb_dma = 0; 3685 ha->async_pd = NULL; 3686 ha->async_pd_dma = 0; 3687 3688 ha->s_dma_pool = NULL; 3689 ha->dl_dma_pool = NULL; 3690 ha->fcp_cmnd_dma_pool = NULL; 3691 3692 ha->gid_list = NULL; 3693 ha->gid_list_dma = 0; 3694 3695 ha->tgt.atio_ring = NULL; 3696 ha->tgt.atio_dma = 0; 3697 ha->tgt.tgt_vp_map = NULL; 3698 } 3699 3700 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 3701 struct qla_hw_data *ha) 3702 { 3703 struct Scsi_Host *host; 3704 struct scsi_qla_host *vha = NULL; 3705 3706 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 3707 if (host == NULL) { 3708 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 3709 "Failed to allocate host from the scsi layer, aborting.\n"); 3710 goto fail; 3711 } 3712 3713 /* Clear our data area */ 3714 vha = shost_priv(host); 3715 memset(vha, 0, sizeof(scsi_qla_host_t)); 3716 3717 vha->host = host; 3718 vha->host_no = host->host_no; 3719 vha->hw = ha; 3720 3721 INIT_LIST_HEAD(&vha->vp_fcports); 3722 INIT_LIST_HEAD(&vha->work_list); 3723 INIT_LIST_HEAD(&vha->list); 3724 3725 spin_lock_init(&vha->work_lock); 3726 3727 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 3728 ql_dbg(ql_dbg_init, vha, 0x0041, 3729 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 3730 vha->host, vha->hw, vha, 3731 dev_name(&(ha->pdev->dev))); 3732 3733 return vha; 3734 3735 fail: 3736 return vha; 3737 } 3738 3739 static struct qla_work_evt * 3740 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 3741 { 3742 struct qla_work_evt *e; 3743 uint8_t bail; 3744 3745 QLA_VHA_MARK_BUSY(vha, bail); 3746 if (bail) 3747 return NULL; 3748 3749 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 3750 if (!e) { 3751 QLA_VHA_MARK_NOT_BUSY(vha); 3752 return NULL; 3753 } 3754 3755 INIT_LIST_HEAD(&e->list); 3756 e->type = type; 3757 e->flags = QLA_EVT_FLAG_FREE; 3758 return e; 3759 } 3760 3761 static int 3762 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 3763 { 3764 unsigned long flags; 3765 3766 spin_lock_irqsave(&vha->work_lock, flags); 3767 list_add_tail(&e->list, &vha->work_list); 3768 spin_unlock_irqrestore(&vha->work_lock, flags); 3769 qla2xxx_wake_dpc(vha); 3770 3771 return QLA_SUCCESS; 3772 } 3773 3774 int 3775 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 3776 u32 data) 3777 { 3778 struct qla_work_evt *e; 3779 3780 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 3781 if (!e) 3782 return QLA_FUNCTION_FAILED; 3783 3784 e->u.aen.code = code; 3785 e->u.aen.data = data; 3786 return qla2x00_post_work(vha, e); 3787 } 3788 3789 int 3790 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 3791 { 3792 struct qla_work_evt *e; 3793 3794 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 3795 if (!e) 3796 return QLA_FUNCTION_FAILED; 3797 3798 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3799 return qla2x00_post_work(vha, e); 3800 } 3801 3802 #define qla2x00_post_async_work(name, type) \ 3803 int qla2x00_post_async_##name##_work( \ 3804 struct scsi_qla_host *vha, \ 3805 fc_port_t *fcport, uint16_t *data) \ 3806 { \ 3807 struct qla_work_evt *e; \ 3808 \ 3809 e = qla2x00_alloc_work(vha, type); \ 3810 if (!e) \ 3811 return QLA_FUNCTION_FAILED; \ 3812 \ 3813 e->u.logio.fcport = fcport; \ 3814 if (data) { \ 3815 e->u.logio.data[0] = data[0]; \ 3816 e->u.logio.data[1] = data[1]; \ 3817 } \ 3818 return qla2x00_post_work(vha, e); \ 3819 } 3820 3821 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 3822 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); 3823 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 3824 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 3825 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 3826 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 3827 3828 int 3829 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 3830 { 3831 struct qla_work_evt *e; 3832 3833 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 3834 if (!e) 3835 return QLA_FUNCTION_FAILED; 3836 3837 e->u.uevent.code = code; 3838 return qla2x00_post_work(vha, e); 3839 } 3840 3841 static void 3842 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 3843 { 3844 char event_string[40]; 3845 char *envp[] = { event_string, NULL }; 3846 3847 switch (code) { 3848 case QLA_UEVENT_CODE_FW_DUMP: 3849 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3850 vha->host_no); 3851 break; 3852 default: 3853 /* do nothing */ 3854 break; 3855 } 3856 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 3857 } 3858 3859 int 3860 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 3861 uint32_t *data, int cnt) 3862 { 3863 struct qla_work_evt *e; 3864 3865 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 3866 if (!e) 3867 return QLA_FUNCTION_FAILED; 3868 3869 e->u.aenfx.evtcode = evtcode; 3870 e->u.aenfx.count = cnt; 3871 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 3872 return qla2x00_post_work(vha, e); 3873 } 3874 3875 void 3876 qla2x00_do_work(struct scsi_qla_host *vha) 3877 { 3878 struct qla_work_evt *e, *tmp; 3879 unsigned long flags; 3880 LIST_HEAD(work); 3881 3882 spin_lock_irqsave(&vha->work_lock, flags); 3883 list_splice_init(&vha->work_list, &work); 3884 spin_unlock_irqrestore(&vha->work_lock, flags); 3885 3886 list_for_each_entry_safe(e, tmp, &work, list) { 3887 list_del_init(&e->list); 3888 3889 switch (e->type) { 3890 case QLA_EVT_AEN: 3891 fc_host_post_event(vha->host, fc_get_event_number(), 3892 e->u.aen.code, e->u.aen.data); 3893 break; 3894 case QLA_EVT_IDC_ACK: 3895 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 3896 break; 3897 case QLA_EVT_ASYNC_LOGIN: 3898 qla2x00_async_login(vha, e->u.logio.fcport, 3899 e->u.logio.data); 3900 break; 3901 case QLA_EVT_ASYNC_LOGIN_DONE: 3902 qla2x00_async_login_done(vha, e->u.logio.fcport, 3903 e->u.logio.data); 3904 break; 3905 case QLA_EVT_ASYNC_LOGOUT: 3906 qla2x00_async_logout(vha, e->u.logio.fcport); 3907 break; 3908 case QLA_EVT_ASYNC_LOGOUT_DONE: 3909 qla2x00_async_logout_done(vha, e->u.logio.fcport, 3910 e->u.logio.data); 3911 break; 3912 case QLA_EVT_ASYNC_ADISC: 3913 qla2x00_async_adisc(vha, e->u.logio.fcport, 3914 e->u.logio.data); 3915 break; 3916 case QLA_EVT_ASYNC_ADISC_DONE: 3917 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 3918 e->u.logio.data); 3919 break; 3920 case QLA_EVT_UEVENT: 3921 qla2x00_uevent_emit(vha, e->u.uevent.code); 3922 break; 3923 case QLA_EVT_AENFX: 3924 qlafx00_process_aen(vha, e); 3925 break; 3926 } 3927 if (e->flags & QLA_EVT_FLAG_FREE) 3928 kfree(e); 3929 3930 /* For each work completed decrement vha ref count */ 3931 QLA_VHA_MARK_NOT_BUSY(vha); 3932 } 3933 } 3934 3935 /* Relogins all the fcports of a vport 3936 * Context: dpc thread 3937 */ 3938 void qla2x00_relogin(struct scsi_qla_host *vha) 3939 { 3940 fc_port_t *fcport; 3941 int status; 3942 uint16_t next_loopid = 0; 3943 struct qla_hw_data *ha = vha->hw; 3944 uint16_t data[2]; 3945 3946 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3947 /* 3948 * If the port is not ONLINE then try to login 3949 * to it if we haven't run out of retries. 3950 */ 3951 if (atomic_read(&fcport->state) != FCS_ONLINE && 3952 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 3953 fcport->login_retry--; 3954 if (fcport->flags & FCF_FABRIC_DEVICE) { 3955 if (fcport->flags & FCF_FCP2_DEVICE) 3956 ha->isp_ops->fabric_logout(vha, 3957 fcport->loop_id, 3958 fcport->d_id.b.domain, 3959 fcport->d_id.b.area, 3960 fcport->d_id.b.al_pa); 3961 3962 if (fcport->loop_id == FC_NO_LOOP_ID) { 3963 fcport->loop_id = next_loopid = 3964 ha->min_external_loopid; 3965 status = qla2x00_find_new_loop_id( 3966 vha, fcport); 3967 if (status != QLA_SUCCESS) { 3968 /* Ran out of IDs to use */ 3969 break; 3970 } 3971 } 3972 3973 if (IS_ALOGIO_CAPABLE(ha)) { 3974 fcport->flags |= FCF_ASYNC_SENT; 3975 data[0] = 0; 3976 data[1] = QLA_LOGIO_LOGIN_RETRIED; 3977 status = qla2x00_post_async_login_work( 3978 vha, fcport, data); 3979 if (status == QLA_SUCCESS) 3980 continue; 3981 /* Attempt a retry. */ 3982 status = 1; 3983 } else { 3984 status = qla2x00_fabric_login(vha, 3985 fcport, &next_loopid); 3986 if (status == QLA_SUCCESS) { 3987 int status2; 3988 uint8_t opts; 3989 3990 opts = 0; 3991 if (fcport->flags & 3992 FCF_FCP2_DEVICE) 3993 opts |= BIT_1; 3994 status2 = 3995 qla2x00_get_port_database( 3996 vha, fcport, opts); 3997 if (status2 != QLA_SUCCESS) 3998 status = 1; 3999 } 4000 } 4001 } else 4002 status = qla2x00_local_device_login(vha, 4003 fcport); 4004 4005 if (status == QLA_SUCCESS) { 4006 fcport->old_loop_id = fcport->loop_id; 4007 4008 ql_dbg(ql_dbg_disc, vha, 0x2003, 4009 "Port login OK: logged in ID 0x%x.\n", 4010 fcport->loop_id); 4011 4012 qla2x00_update_fcport(vha, fcport); 4013 4014 } else if (status == 1) { 4015 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4016 /* retry the login again */ 4017 ql_dbg(ql_dbg_disc, vha, 0x2007, 4018 "Retrying %d login again loop_id 0x%x.\n", 4019 fcport->login_retry, fcport->loop_id); 4020 } else { 4021 fcport->login_retry = 0; 4022 } 4023 4024 if (fcport->login_retry == 0 && status != QLA_SUCCESS) 4025 qla2x00_clear_loop_id(fcport); 4026 } 4027 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4028 break; 4029 } 4030 } 4031 4032 /* Schedule work on any of the dpc-workqueues */ 4033 void 4034 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4035 { 4036 struct qla_hw_data *ha = base_vha->hw; 4037 4038 switch (work_code) { 4039 case MBA_IDC_AEN: /* 0x8200 */ 4040 if (ha->dpc_lp_wq) 4041 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4042 break; 4043 4044 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4045 if (!ha->flags.nic_core_reset_hdlr_active) { 4046 if (ha->dpc_hp_wq) 4047 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4048 } else 4049 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4050 "NIC Core reset is already active. Skip " 4051 "scheduling it again.\n"); 4052 break; 4053 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4054 if (ha->dpc_hp_wq) 4055 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4056 break; 4057 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4058 if (ha->dpc_hp_wq) 4059 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4060 break; 4061 default: 4062 ql_log(ql_log_warn, base_vha, 0xb05f, 4063 "Unknow work-code=0x%x.\n", work_code); 4064 } 4065 4066 return; 4067 } 4068 4069 /* Work: Perform NIC Core Unrecoverable state handling */ 4070 void 4071 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4072 { 4073 struct qla_hw_data *ha = 4074 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4075 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4076 uint32_t dev_state = 0; 4077 4078 qla83xx_idc_lock(base_vha, 0); 4079 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4080 qla83xx_reset_ownership(base_vha); 4081 if (ha->flags.nic_core_reset_owner) { 4082 ha->flags.nic_core_reset_owner = 0; 4083 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4084 QLA8XXX_DEV_FAILED); 4085 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4086 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4087 } 4088 qla83xx_idc_unlock(base_vha, 0); 4089 } 4090 4091 /* Work: Execute IDC state handler */ 4092 void 4093 qla83xx_idc_state_handler_work(struct work_struct *work) 4094 { 4095 struct qla_hw_data *ha = 4096 container_of(work, struct qla_hw_data, idc_state_handler); 4097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4098 uint32_t dev_state = 0; 4099 4100 qla83xx_idc_lock(base_vha, 0); 4101 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4102 if (dev_state == QLA8XXX_DEV_FAILED || 4103 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4104 qla83xx_idc_state_handler(base_vha); 4105 qla83xx_idc_unlock(base_vha, 0); 4106 } 4107 4108 static int 4109 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4110 { 4111 int rval = QLA_SUCCESS; 4112 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4113 uint32_t heart_beat_counter1, heart_beat_counter2; 4114 4115 do { 4116 if (time_after(jiffies, heart_beat_wait)) { 4117 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4118 "Nic Core f/w is not alive.\n"); 4119 rval = QLA_FUNCTION_FAILED; 4120 break; 4121 } 4122 4123 qla83xx_idc_lock(base_vha, 0); 4124 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4125 &heart_beat_counter1); 4126 qla83xx_idc_unlock(base_vha, 0); 4127 msleep(100); 4128 qla83xx_idc_lock(base_vha, 0); 4129 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4130 &heart_beat_counter2); 4131 qla83xx_idc_unlock(base_vha, 0); 4132 } while (heart_beat_counter1 == heart_beat_counter2); 4133 4134 return rval; 4135 } 4136 4137 /* Work: Perform NIC Core Reset handling */ 4138 void 4139 qla83xx_nic_core_reset_work(struct work_struct *work) 4140 { 4141 struct qla_hw_data *ha = 4142 container_of(work, struct qla_hw_data, nic_core_reset); 4143 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4144 uint32_t dev_state = 0; 4145 4146 if (IS_QLA2031(ha)) { 4147 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4148 ql_log(ql_log_warn, base_vha, 0xb081, 4149 "Failed to dump mctp\n"); 4150 return; 4151 } 4152 4153 if (!ha->flags.nic_core_reset_hdlr_active) { 4154 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4155 qla83xx_idc_lock(base_vha, 0); 4156 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4157 &dev_state); 4158 qla83xx_idc_unlock(base_vha, 0); 4159 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4160 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4161 "Nic Core f/w is alive.\n"); 4162 return; 4163 } 4164 } 4165 4166 ha->flags.nic_core_reset_hdlr_active = 1; 4167 if (qla83xx_nic_core_reset(base_vha)) { 4168 /* NIC Core reset failed. */ 4169 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4170 "NIC Core reset failed.\n"); 4171 } 4172 ha->flags.nic_core_reset_hdlr_active = 0; 4173 } 4174 } 4175 4176 /* Work: Handle 8200 IDC aens */ 4177 void 4178 qla83xx_service_idc_aen(struct work_struct *work) 4179 { 4180 struct qla_hw_data *ha = 4181 container_of(work, struct qla_hw_data, idc_aen); 4182 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4183 uint32_t dev_state, idc_control; 4184 4185 qla83xx_idc_lock(base_vha, 0); 4186 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4187 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4188 qla83xx_idc_unlock(base_vha, 0); 4189 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4190 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4191 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4192 "Application requested NIC Core Reset.\n"); 4193 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4194 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4195 QLA_SUCCESS) { 4196 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4197 "Other protocol driver requested NIC Core Reset.\n"); 4198 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4199 } 4200 } else if (dev_state == QLA8XXX_DEV_FAILED || 4201 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4202 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4203 } 4204 } 4205 4206 static void 4207 qla83xx_wait_logic(void) 4208 { 4209 int i; 4210 4211 /* Yield CPU */ 4212 if (!in_interrupt()) { 4213 /* 4214 * Wait about 200ms before retrying again. 4215 * This controls the number of retries for single 4216 * lock operation. 4217 */ 4218 msleep(100); 4219 schedule(); 4220 } else { 4221 for (i = 0; i < 20; i++) 4222 cpu_relax(); /* This a nop instr on i386 */ 4223 } 4224 } 4225 4226 static int 4227 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4228 { 4229 int rval; 4230 uint32_t data; 4231 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4232 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4233 struct qla_hw_data *ha = base_vha->hw; 4234 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4235 "Trying force recovery of the IDC lock.\n"); 4236 4237 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4238 if (rval) 4239 return rval; 4240 4241 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4242 return QLA_SUCCESS; 4243 } else { 4244 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4245 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4246 data); 4247 if (rval) 4248 return rval; 4249 4250 msleep(200); 4251 4252 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4253 &data); 4254 if (rval) 4255 return rval; 4256 4257 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4258 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4259 ~(idc_lck_rcvry_stage_mask)); 4260 rval = qla83xx_wr_reg(base_vha, 4261 QLA83XX_IDC_LOCK_RECOVERY, data); 4262 if (rval) 4263 return rval; 4264 4265 /* Forcefully perform IDC UnLock */ 4266 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4267 &data); 4268 if (rval) 4269 return rval; 4270 /* Clear lock-id by setting 0xff */ 4271 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4272 0xff); 4273 if (rval) 4274 return rval; 4275 /* Clear lock-recovery by setting 0x0 */ 4276 rval = qla83xx_wr_reg(base_vha, 4277 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4278 if (rval) 4279 return rval; 4280 } else 4281 return QLA_SUCCESS; 4282 } 4283 4284 return rval; 4285 } 4286 4287 static int 4288 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4289 { 4290 int rval = QLA_SUCCESS; 4291 uint32_t o_drv_lockid, n_drv_lockid; 4292 unsigned long lock_recovery_timeout; 4293 4294 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4295 retry_lockid: 4296 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4297 if (rval) 4298 goto exit; 4299 4300 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4301 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4302 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4303 return QLA_SUCCESS; 4304 else 4305 return QLA_FUNCTION_FAILED; 4306 } 4307 4308 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4309 if (rval) 4310 goto exit; 4311 4312 if (o_drv_lockid == n_drv_lockid) { 4313 qla83xx_wait_logic(); 4314 goto retry_lockid; 4315 } else 4316 return QLA_SUCCESS; 4317 4318 exit: 4319 return rval; 4320 } 4321 4322 void 4323 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4324 { 4325 uint16_t options = (requester_id << 15) | BIT_6; 4326 uint32_t data; 4327 uint32_t lock_owner; 4328 struct qla_hw_data *ha = base_vha->hw; 4329 4330 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4331 retry_lock: 4332 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4333 == QLA_SUCCESS) { 4334 if (data) { 4335 /* Setting lock-id to our function-number */ 4336 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4337 ha->portnum); 4338 } else { 4339 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4340 &lock_owner); 4341 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4342 "Failed to acquire IDC lock, acquired by %d, " 4343 "retrying...\n", lock_owner); 4344 4345 /* Retry/Perform IDC-Lock recovery */ 4346 if (qla83xx_idc_lock_recovery(base_vha) 4347 == QLA_SUCCESS) { 4348 qla83xx_wait_logic(); 4349 goto retry_lock; 4350 } else 4351 ql_log(ql_log_warn, base_vha, 0xb075, 4352 "IDC Lock recovery FAILED.\n"); 4353 } 4354 4355 } 4356 4357 return; 4358 4359 /* XXX: IDC-lock implementation using access-control mbx */ 4360 retry_lock2: 4361 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4362 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4363 "Failed to acquire IDC lock. retrying...\n"); 4364 /* Retry/Perform IDC-Lock recovery */ 4365 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4366 qla83xx_wait_logic(); 4367 goto retry_lock2; 4368 } else 4369 ql_log(ql_log_warn, base_vha, 0xb076, 4370 "IDC Lock recovery FAILED.\n"); 4371 } 4372 4373 return; 4374 } 4375 4376 void 4377 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4378 { 4379 uint16_t options = (requester_id << 15) | BIT_7, retry; 4380 uint32_t data; 4381 struct qla_hw_data *ha = base_vha->hw; 4382 4383 /* IDC-unlock implementation using driver-unlock/lock-id 4384 * remote registers 4385 */ 4386 retry = 0; 4387 retry_unlock: 4388 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 4389 == QLA_SUCCESS) { 4390 if (data == ha->portnum) { 4391 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 4392 /* Clearing lock-id by setting 0xff */ 4393 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 4394 } else if (retry < 10) { 4395 /* SV: XXX: IDC unlock retrying needed here? */ 4396 4397 /* Retry for IDC-unlock */ 4398 qla83xx_wait_logic(); 4399 retry++; 4400 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 4401 "Failed to release IDC lock, retyring=%d\n", retry); 4402 goto retry_unlock; 4403 } 4404 } else if (retry < 10) { 4405 /* Retry for IDC-unlock */ 4406 qla83xx_wait_logic(); 4407 retry++; 4408 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 4409 "Failed to read drv-lockid, retyring=%d\n", retry); 4410 goto retry_unlock; 4411 } 4412 4413 return; 4414 4415 /* XXX: IDC-unlock implementation using access-control mbx */ 4416 retry = 0; 4417 retry_unlock2: 4418 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4419 if (retry < 10) { 4420 /* Retry for IDC-unlock */ 4421 qla83xx_wait_logic(); 4422 retry++; 4423 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 4424 "Failed to release IDC lock, retyring=%d\n", retry); 4425 goto retry_unlock2; 4426 } 4427 } 4428 4429 return; 4430 } 4431 4432 int 4433 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4434 { 4435 int rval = QLA_SUCCESS; 4436 struct qla_hw_data *ha = vha->hw; 4437 uint32_t drv_presence; 4438 4439 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4440 if (rval == QLA_SUCCESS) { 4441 drv_presence |= (1 << ha->portnum); 4442 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4443 drv_presence); 4444 } 4445 4446 return rval; 4447 } 4448 4449 int 4450 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 4451 { 4452 int rval = QLA_SUCCESS; 4453 4454 qla83xx_idc_lock(vha, 0); 4455 rval = __qla83xx_set_drv_presence(vha); 4456 qla83xx_idc_unlock(vha, 0); 4457 4458 return rval; 4459 } 4460 4461 int 4462 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4463 { 4464 int rval = QLA_SUCCESS; 4465 struct qla_hw_data *ha = vha->hw; 4466 uint32_t drv_presence; 4467 4468 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4469 if (rval == QLA_SUCCESS) { 4470 drv_presence &= ~(1 << ha->portnum); 4471 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4472 drv_presence); 4473 } 4474 4475 return rval; 4476 } 4477 4478 int 4479 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 4480 { 4481 int rval = QLA_SUCCESS; 4482 4483 qla83xx_idc_lock(vha, 0); 4484 rval = __qla83xx_clear_drv_presence(vha); 4485 qla83xx_idc_unlock(vha, 0); 4486 4487 return rval; 4488 } 4489 4490 static void 4491 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 4492 { 4493 struct qla_hw_data *ha = vha->hw; 4494 uint32_t drv_ack, drv_presence; 4495 unsigned long ack_timeout; 4496 4497 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 4498 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 4499 while (1) { 4500 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4501 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4502 if ((drv_ack & drv_presence) == drv_presence) 4503 break; 4504 4505 if (time_after_eq(jiffies, ack_timeout)) { 4506 ql_log(ql_log_warn, vha, 0xb067, 4507 "RESET ACK TIMEOUT! drv_presence=0x%x " 4508 "drv_ack=0x%x\n", drv_presence, drv_ack); 4509 /* 4510 * The function(s) which did not ack in time are forced 4511 * to withdraw any further participation in the IDC 4512 * reset. 4513 */ 4514 if (drv_ack != drv_presence) 4515 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 4516 drv_ack); 4517 break; 4518 } 4519 4520 qla83xx_idc_unlock(vha, 0); 4521 msleep(1000); 4522 qla83xx_idc_lock(vha, 0); 4523 } 4524 4525 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 4526 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 4527 } 4528 4529 static int 4530 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 4531 { 4532 int rval = QLA_SUCCESS; 4533 uint32_t idc_control; 4534 4535 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 4536 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 4537 4538 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 4539 __qla83xx_get_idc_control(vha, &idc_control); 4540 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 4541 __qla83xx_set_idc_control(vha, 0); 4542 4543 qla83xx_idc_unlock(vha, 0); 4544 rval = qla83xx_restart_nic_firmware(vha); 4545 qla83xx_idc_lock(vha, 0); 4546 4547 if (rval != QLA_SUCCESS) { 4548 ql_log(ql_log_fatal, vha, 0xb06a, 4549 "Failed to restart NIC f/w.\n"); 4550 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 4551 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 4552 } else { 4553 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 4554 "Success in restarting nic f/w.\n"); 4555 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 4556 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 4557 } 4558 4559 return rval; 4560 } 4561 4562 /* Assumes idc_lock always held on entry */ 4563 int 4564 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 4565 { 4566 struct qla_hw_data *ha = base_vha->hw; 4567 int rval = QLA_SUCCESS; 4568 unsigned long dev_init_timeout; 4569 uint32_t dev_state; 4570 4571 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 4572 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 4573 4574 while (1) { 4575 4576 if (time_after_eq(jiffies, dev_init_timeout)) { 4577 ql_log(ql_log_warn, base_vha, 0xb06e, 4578 "Initialization TIMEOUT!\n"); 4579 /* Init timeout. Disable further NIC Core 4580 * communication. 4581 */ 4582 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4583 QLA8XXX_DEV_FAILED); 4584 ql_log(ql_log_info, base_vha, 0xb06f, 4585 "HW State: FAILED.\n"); 4586 } 4587 4588 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4589 switch (dev_state) { 4590 case QLA8XXX_DEV_READY: 4591 if (ha->flags.nic_core_reset_owner) 4592 qla83xx_idc_audit(base_vha, 4593 IDC_AUDIT_COMPLETION); 4594 ha->flags.nic_core_reset_owner = 0; 4595 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 4596 "Reset_owner reset by 0x%x.\n", 4597 ha->portnum); 4598 goto exit; 4599 case QLA8XXX_DEV_COLD: 4600 if (ha->flags.nic_core_reset_owner) 4601 rval = qla83xx_device_bootstrap(base_vha); 4602 else { 4603 /* Wait for AEN to change device-state */ 4604 qla83xx_idc_unlock(base_vha, 0); 4605 msleep(1000); 4606 qla83xx_idc_lock(base_vha, 0); 4607 } 4608 break; 4609 case QLA8XXX_DEV_INITIALIZING: 4610 /* Wait for AEN to change device-state */ 4611 qla83xx_idc_unlock(base_vha, 0); 4612 msleep(1000); 4613 qla83xx_idc_lock(base_vha, 0); 4614 break; 4615 case QLA8XXX_DEV_NEED_RESET: 4616 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 4617 qla83xx_need_reset_handler(base_vha); 4618 else { 4619 /* Wait for AEN to change device-state */ 4620 qla83xx_idc_unlock(base_vha, 0); 4621 msleep(1000); 4622 qla83xx_idc_lock(base_vha, 0); 4623 } 4624 /* reset timeout value after need reset handler */ 4625 dev_init_timeout = jiffies + 4626 (ha->fcoe_dev_init_timeout * HZ); 4627 break; 4628 case QLA8XXX_DEV_NEED_QUIESCENT: 4629 /* XXX: DEBUG for now */ 4630 qla83xx_idc_unlock(base_vha, 0); 4631 msleep(1000); 4632 qla83xx_idc_lock(base_vha, 0); 4633 break; 4634 case QLA8XXX_DEV_QUIESCENT: 4635 /* XXX: DEBUG for now */ 4636 if (ha->flags.quiesce_owner) 4637 goto exit; 4638 4639 qla83xx_idc_unlock(base_vha, 0); 4640 msleep(1000); 4641 qla83xx_idc_lock(base_vha, 0); 4642 dev_init_timeout = jiffies + 4643 (ha->fcoe_dev_init_timeout * HZ); 4644 break; 4645 case QLA8XXX_DEV_FAILED: 4646 if (ha->flags.nic_core_reset_owner) 4647 qla83xx_idc_audit(base_vha, 4648 IDC_AUDIT_COMPLETION); 4649 ha->flags.nic_core_reset_owner = 0; 4650 __qla83xx_clear_drv_presence(base_vha); 4651 qla83xx_idc_unlock(base_vha, 0); 4652 qla8xxx_dev_failed_handler(base_vha); 4653 rval = QLA_FUNCTION_FAILED; 4654 qla83xx_idc_lock(base_vha, 0); 4655 goto exit; 4656 case QLA8XXX_BAD_VALUE: 4657 qla83xx_idc_unlock(base_vha, 0); 4658 msleep(1000); 4659 qla83xx_idc_lock(base_vha, 0); 4660 break; 4661 default: 4662 ql_log(ql_log_warn, base_vha, 0xb071, 4663 "Unknow Device State: %x.\n", dev_state); 4664 qla83xx_idc_unlock(base_vha, 0); 4665 qla8xxx_dev_failed_handler(base_vha); 4666 rval = QLA_FUNCTION_FAILED; 4667 qla83xx_idc_lock(base_vha, 0); 4668 goto exit; 4669 } 4670 } 4671 4672 exit: 4673 return rval; 4674 } 4675 4676 void 4677 qla2x00_disable_board_on_pci_error(struct work_struct *work) 4678 { 4679 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 4680 board_disable); 4681 struct pci_dev *pdev = ha->pdev; 4682 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4683 4684 ql_log(ql_log_warn, base_vha, 0x015b, 4685 "Disabling adapter.\n"); 4686 4687 set_bit(UNLOADING, &base_vha->dpc_flags); 4688 4689 qla2x00_delete_all_vps(ha, base_vha); 4690 4691 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 4692 4693 qla2x00_dfs_remove(base_vha); 4694 4695 qla84xx_put_chip(base_vha); 4696 4697 if (base_vha->timer_active) 4698 qla2x00_stop_timer(base_vha); 4699 4700 base_vha->flags.online = 0; 4701 4702 qla2x00_destroy_deferred_work(ha); 4703 4704 /* 4705 * Do not try to stop beacon blink as it will issue a mailbox 4706 * command. 4707 */ 4708 qla2x00_free_sysfs_attr(base_vha, false); 4709 4710 fc_remove_host(base_vha->host); 4711 4712 scsi_remove_host(base_vha->host); 4713 4714 base_vha->flags.init_done = 0; 4715 qla25xx_delete_queues(base_vha); 4716 qla2x00_free_irqs(base_vha); 4717 qla2x00_free_fcports(base_vha); 4718 qla2x00_mem_free(ha); 4719 qla82xx_md_free(base_vha); 4720 qla2x00_free_queues(ha); 4721 4722 scsi_host_put(base_vha->host); 4723 4724 qla2x00_unmap_iobases(ha); 4725 4726 pci_release_selected_regions(ha->pdev, ha->bars); 4727 kfree(ha); 4728 ha = NULL; 4729 4730 pci_disable_pcie_error_reporting(pdev); 4731 pci_disable_device(pdev); 4732 pci_set_drvdata(pdev, NULL); 4733 4734 } 4735 4736 /************************************************************************** 4737 * qla2x00_do_dpc 4738 * This kernel thread is a task that is schedule by the interrupt handler 4739 * to perform the background processing for interrupts. 4740 * 4741 * Notes: 4742 * This task always run in the context of a kernel thread. It 4743 * is kick-off by the driver's detect code and starts up 4744 * up one per adapter. It immediately goes to sleep and waits for 4745 * some fibre event. When either the interrupt handler or 4746 * the timer routine detects a event it will one of the task 4747 * bits then wake us up. 4748 **************************************************************************/ 4749 static int 4750 qla2x00_do_dpc(void *data) 4751 { 4752 int rval; 4753 scsi_qla_host_t *base_vha; 4754 struct qla_hw_data *ha; 4755 4756 ha = (struct qla_hw_data *)data; 4757 base_vha = pci_get_drvdata(ha->pdev); 4758 4759 set_user_nice(current, -20); 4760 4761 set_current_state(TASK_INTERRUPTIBLE); 4762 while (!kthread_should_stop()) { 4763 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 4764 "DPC handler sleeping.\n"); 4765 4766 schedule(); 4767 __set_current_state(TASK_RUNNING); 4768 4769 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 4770 goto end_loop; 4771 4772 if (ha->flags.eeh_busy) { 4773 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 4774 "eeh_busy=%d.\n", ha->flags.eeh_busy); 4775 goto end_loop; 4776 } 4777 4778 ha->dpc_active = 1; 4779 4780 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 4781 "DPC handler waking up, dpc_flags=0x%lx.\n", 4782 base_vha->dpc_flags); 4783 4784 qla2x00_do_work(base_vha); 4785 4786 if (IS_P3P_TYPE(ha)) { 4787 if (IS_QLA8044(ha)) { 4788 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4789 &base_vha->dpc_flags)) { 4790 qla8044_idc_lock(ha); 4791 qla8044_wr_direct(base_vha, 4792 QLA8044_CRB_DEV_STATE_INDEX, 4793 QLA8XXX_DEV_FAILED); 4794 qla8044_idc_unlock(ha); 4795 ql_log(ql_log_info, base_vha, 0x4004, 4796 "HW State: FAILED.\n"); 4797 qla8044_device_state_handler(base_vha); 4798 continue; 4799 } 4800 4801 } else { 4802 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4803 &base_vha->dpc_flags)) { 4804 qla82xx_idc_lock(ha); 4805 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4806 QLA8XXX_DEV_FAILED); 4807 qla82xx_idc_unlock(ha); 4808 ql_log(ql_log_info, base_vha, 0x0151, 4809 "HW State: FAILED.\n"); 4810 qla82xx_device_state_handler(base_vha); 4811 continue; 4812 } 4813 } 4814 4815 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 4816 &base_vha->dpc_flags)) { 4817 4818 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 4819 "FCoE context reset scheduled.\n"); 4820 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4821 &base_vha->dpc_flags))) { 4822 if (qla82xx_fcoe_ctx_reset(base_vha)) { 4823 /* FCoE-ctx reset failed. 4824 * Escalate to chip-reset 4825 */ 4826 set_bit(ISP_ABORT_NEEDED, 4827 &base_vha->dpc_flags); 4828 } 4829 clear_bit(ABORT_ISP_ACTIVE, 4830 &base_vha->dpc_flags); 4831 } 4832 4833 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 4834 "FCoE context reset end.\n"); 4835 } 4836 } else if (IS_QLAFX00(ha)) { 4837 if (test_and_clear_bit(ISP_UNRECOVERABLE, 4838 &base_vha->dpc_flags)) { 4839 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 4840 "Firmware Reset Recovery\n"); 4841 if (qlafx00_reset_initialize(base_vha)) { 4842 /* Failed. Abort isp later. */ 4843 if (!test_bit(UNLOADING, 4844 &base_vha->dpc_flags)) 4845 set_bit(ISP_UNRECOVERABLE, 4846 &base_vha->dpc_flags); 4847 ql_dbg(ql_dbg_dpc, base_vha, 4848 0x4021, 4849 "Reset Recovery Failed\n"); 4850 } 4851 } 4852 4853 if (test_and_clear_bit(FX00_TARGET_SCAN, 4854 &base_vha->dpc_flags)) { 4855 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 4856 "ISPFx00 Target Scan scheduled\n"); 4857 if (qlafx00_rescan_isp(base_vha)) { 4858 if (!test_bit(UNLOADING, 4859 &base_vha->dpc_flags)) 4860 set_bit(ISP_UNRECOVERABLE, 4861 &base_vha->dpc_flags); 4862 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 4863 "ISPFx00 Target Scan Failed\n"); 4864 } 4865 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 4866 "ISPFx00 Target Scan End\n"); 4867 } 4868 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 4869 &base_vha->dpc_flags)) { 4870 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 4871 "ISPFx00 Host Info resend scheduled\n"); 4872 qlafx00_fx_disc(base_vha, 4873 &base_vha->hw->mr.fcport, 4874 FXDISC_REG_HOST_INFO); 4875 } 4876 } 4877 4878 if (test_and_clear_bit(ISP_ABORT_NEEDED, 4879 &base_vha->dpc_flags)) { 4880 4881 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 4882 "ISP abort scheduled.\n"); 4883 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 4884 &base_vha->dpc_flags))) { 4885 4886 if (ha->isp_ops->abort_isp(base_vha)) { 4887 /* failed. retry later */ 4888 set_bit(ISP_ABORT_NEEDED, 4889 &base_vha->dpc_flags); 4890 } 4891 clear_bit(ABORT_ISP_ACTIVE, 4892 &base_vha->dpc_flags); 4893 } 4894 4895 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 4896 "ISP abort end.\n"); 4897 } 4898 4899 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 4900 &base_vha->dpc_flags)) { 4901 qla2x00_update_fcports(base_vha); 4902 } 4903 4904 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { 4905 int ret; 4906 ret = qla2x00_send_change_request(base_vha, 0x3, 0); 4907 if (ret != QLA_SUCCESS) 4908 ql_log(ql_log_warn, base_vha, 0x121, 4909 "Failed to enable receiving of RSCN " 4910 "requests: 0x%x.\n", ret); 4911 clear_bit(SCR_PENDING, &base_vha->dpc_flags); 4912 } 4913 4914 if (IS_QLAFX00(ha)) 4915 goto loop_resync_check; 4916 4917 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 4918 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 4919 "Quiescence mode scheduled.\n"); 4920 if (IS_P3P_TYPE(ha)) { 4921 if (IS_QLA82XX(ha)) 4922 qla82xx_device_state_handler(base_vha); 4923 if (IS_QLA8044(ha)) 4924 qla8044_device_state_handler(base_vha); 4925 clear_bit(ISP_QUIESCE_NEEDED, 4926 &base_vha->dpc_flags); 4927 if (!ha->flags.quiesce_owner) { 4928 qla2x00_perform_loop_resync(base_vha); 4929 if (IS_QLA82XX(ha)) { 4930 qla82xx_idc_lock(ha); 4931 qla82xx_clear_qsnt_ready( 4932 base_vha); 4933 qla82xx_idc_unlock(ha); 4934 } else if (IS_QLA8044(ha)) { 4935 qla8044_idc_lock(ha); 4936 qla8044_clear_qsnt_ready( 4937 base_vha); 4938 qla8044_idc_unlock(ha); 4939 } 4940 } 4941 } else { 4942 clear_bit(ISP_QUIESCE_NEEDED, 4943 &base_vha->dpc_flags); 4944 qla2x00_quiesce_io(base_vha); 4945 } 4946 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 4947 "Quiescence mode end.\n"); 4948 } 4949 4950 if (test_and_clear_bit(RESET_MARKER_NEEDED, 4951 &base_vha->dpc_flags) && 4952 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 4953 4954 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 4955 "Reset marker scheduled.\n"); 4956 qla2x00_rst_aen(base_vha); 4957 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 4958 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 4959 "Reset marker end.\n"); 4960 } 4961 4962 /* Retry each device up to login retry count */ 4963 if ((test_and_clear_bit(RELOGIN_NEEDED, 4964 &base_vha->dpc_flags)) && 4965 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 4966 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 4967 4968 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 4969 "Relogin scheduled.\n"); 4970 qla2x00_relogin(base_vha); 4971 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 4972 "Relogin end.\n"); 4973 } 4974 loop_resync_check: 4975 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 4976 &base_vha->dpc_flags)) { 4977 4978 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 4979 "Loop resync scheduled.\n"); 4980 4981 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 4982 &base_vha->dpc_flags))) { 4983 4984 rval = qla2x00_loop_resync(base_vha); 4985 4986 clear_bit(LOOP_RESYNC_ACTIVE, 4987 &base_vha->dpc_flags); 4988 } 4989 4990 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 4991 "Loop resync end.\n"); 4992 } 4993 4994 if (IS_QLAFX00(ha)) 4995 goto intr_on_check; 4996 4997 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 4998 atomic_read(&base_vha->loop_state) == LOOP_READY) { 4999 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5000 qla2xxx_flash_npiv_conf(base_vha); 5001 } 5002 5003 intr_on_check: 5004 if (!ha->interrupts_on) 5005 ha->isp_ops->enable_intrs(ha); 5006 5007 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5008 &base_vha->dpc_flags)) 5009 ha->isp_ops->beacon_blink(base_vha); 5010 5011 if (!IS_QLAFX00(ha)) 5012 qla2x00_do_dpc_all_vps(base_vha); 5013 5014 ha->dpc_active = 0; 5015 end_loop: 5016 set_current_state(TASK_INTERRUPTIBLE); 5017 } /* End of while(1) */ 5018 __set_current_state(TASK_RUNNING); 5019 5020 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5021 "DPC handler exiting.\n"); 5022 5023 /* 5024 * Make sure that nobody tries to wake us up again. 5025 */ 5026 ha->dpc_active = 0; 5027 5028 /* Cleanup any residual CTX SRBs. */ 5029 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5030 5031 return 0; 5032 } 5033 5034 void 5035 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5036 { 5037 struct qla_hw_data *ha = vha->hw; 5038 struct task_struct *t = ha->dpc_thread; 5039 5040 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5041 wake_up_process(t); 5042 } 5043 5044 /* 5045 * qla2x00_rst_aen 5046 * Processes asynchronous reset. 5047 * 5048 * Input: 5049 * ha = adapter block pointer. 5050 */ 5051 static void 5052 qla2x00_rst_aen(scsi_qla_host_t *vha) 5053 { 5054 if (vha->flags.online && !vha->flags.reset_active && 5055 !atomic_read(&vha->loop_down_timer) && 5056 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5057 do { 5058 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5059 5060 /* 5061 * Issue marker command only when we are going to start 5062 * the I/O. 5063 */ 5064 vha->marker_needed = 1; 5065 } while (!atomic_read(&vha->loop_down_timer) && 5066 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5067 } 5068 } 5069 5070 /************************************************************************** 5071 * qla2x00_timer 5072 * 5073 * Description: 5074 * One second timer 5075 * 5076 * Context: Interrupt 5077 ***************************************************************************/ 5078 void 5079 qla2x00_timer(scsi_qla_host_t *vha) 5080 { 5081 unsigned long cpu_flags = 0; 5082 int start_dpc = 0; 5083 int index; 5084 srb_t *sp; 5085 uint16_t w; 5086 struct qla_hw_data *ha = vha->hw; 5087 struct req_que *req; 5088 5089 if (ha->flags.eeh_busy) { 5090 ql_dbg(ql_dbg_timer, vha, 0x6000, 5091 "EEH = %d, restarting timer.\n", 5092 ha->flags.eeh_busy); 5093 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5094 return; 5095 } 5096 5097 /* 5098 * Hardware read to raise pending EEH errors during mailbox waits. If 5099 * the read returns -1 then disable the board. 5100 */ 5101 if (!pci_channel_offline(ha->pdev)) { 5102 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5103 if (w == 0xffff) 5104 /* 5105 * Schedule this on the default system workqueue so that 5106 * all the adapter workqueues and the DPC thread can be 5107 * shutdown cleanly. 5108 */ 5109 schedule_work(&ha->board_disable); 5110 } 5111 5112 /* Make sure qla82xx_watchdog is run only for physical port */ 5113 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5114 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5115 start_dpc++; 5116 if (IS_QLA82XX(ha)) 5117 qla82xx_watchdog(vha); 5118 else if (IS_QLA8044(ha)) 5119 qla8044_watchdog(vha); 5120 } 5121 5122 if (!vha->vp_idx && IS_QLAFX00(ha)) 5123 qlafx00_timer_routine(vha); 5124 5125 /* Loop down handler. */ 5126 if (atomic_read(&vha->loop_down_timer) > 0 && 5127 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5128 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5129 && vha->flags.online) { 5130 5131 if (atomic_read(&vha->loop_down_timer) == 5132 vha->loop_down_abort_time) { 5133 5134 ql_log(ql_log_info, vha, 0x6008, 5135 "Loop down - aborting the queues before time expires.\n"); 5136 5137 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5138 atomic_set(&vha->loop_state, LOOP_DEAD); 5139 5140 /* 5141 * Schedule an ISP abort to return any FCP2-device 5142 * commands. 5143 */ 5144 /* NPIV - scan physical port only */ 5145 if (!vha->vp_idx) { 5146 spin_lock_irqsave(&ha->hardware_lock, 5147 cpu_flags); 5148 req = ha->req_q_map[0]; 5149 for (index = 1; 5150 index < req->num_outstanding_cmds; 5151 index++) { 5152 fc_port_t *sfcp; 5153 5154 sp = req->outstanding_cmds[index]; 5155 if (!sp) 5156 continue; 5157 if (sp->type != SRB_SCSI_CMD) 5158 continue; 5159 sfcp = sp->fcport; 5160 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5161 continue; 5162 5163 if (IS_QLA82XX(ha)) 5164 set_bit(FCOE_CTX_RESET_NEEDED, 5165 &vha->dpc_flags); 5166 else 5167 set_bit(ISP_ABORT_NEEDED, 5168 &vha->dpc_flags); 5169 break; 5170 } 5171 spin_unlock_irqrestore(&ha->hardware_lock, 5172 cpu_flags); 5173 } 5174 start_dpc++; 5175 } 5176 5177 /* if the loop has been down for 4 minutes, reinit adapter */ 5178 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5179 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5180 ql_log(ql_log_warn, vha, 0x6009, 5181 "Loop down - aborting ISP.\n"); 5182 5183 if (IS_QLA82XX(ha)) 5184 set_bit(FCOE_CTX_RESET_NEEDED, 5185 &vha->dpc_flags); 5186 else 5187 set_bit(ISP_ABORT_NEEDED, 5188 &vha->dpc_flags); 5189 } 5190 } 5191 ql_dbg(ql_dbg_timer, vha, 0x600a, 5192 "Loop down - seconds remaining %d.\n", 5193 atomic_read(&vha->loop_down_timer)); 5194 } 5195 /* Check if beacon LED needs to be blinked for physical host only */ 5196 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5197 /* There is no beacon_blink function for ISP82xx */ 5198 if (!IS_P3P_TYPE(ha)) { 5199 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5200 start_dpc++; 5201 } 5202 } 5203 5204 /* Process any deferred work. */ 5205 if (!list_empty(&vha->work_list)) 5206 start_dpc++; 5207 5208 /* Schedule the DPC routine if needed */ 5209 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5210 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5211 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5212 start_dpc || 5213 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5214 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5215 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5216 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5217 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5218 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5219 ql_dbg(ql_dbg_timer, vha, 0x600b, 5220 "isp_abort_needed=%d loop_resync_needed=%d " 5221 "fcport_update_needed=%d start_dpc=%d " 5222 "reset_marker_needed=%d", 5223 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5224 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5225 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5226 start_dpc, 5227 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5228 ql_dbg(ql_dbg_timer, vha, 0x600c, 5229 "beacon_blink_needed=%d isp_unrecoverable=%d " 5230 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5231 "relogin_needed=%d.\n", 5232 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5233 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5234 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5235 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5236 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5237 qla2xxx_wake_dpc(vha); 5238 } 5239 5240 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5241 } 5242 5243 /* Firmware interface routines. */ 5244 5245 #define FW_BLOBS 10 5246 #define FW_ISP21XX 0 5247 #define FW_ISP22XX 1 5248 #define FW_ISP2300 2 5249 #define FW_ISP2322 3 5250 #define FW_ISP24XX 4 5251 #define FW_ISP25XX 5 5252 #define FW_ISP81XX 6 5253 #define FW_ISP82XX 7 5254 #define FW_ISP2031 8 5255 #define FW_ISP8031 9 5256 5257 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5258 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5259 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5260 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5261 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5262 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5263 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5264 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5265 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5266 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5267 5268 static DEFINE_MUTEX(qla_fw_lock); 5269 5270 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5271 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5272 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5273 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5274 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5275 { .name = FW_FILE_ISP24XX, }, 5276 { .name = FW_FILE_ISP25XX, }, 5277 { .name = FW_FILE_ISP81XX, }, 5278 { .name = FW_FILE_ISP82XX, }, 5279 { .name = FW_FILE_ISP2031, }, 5280 { .name = FW_FILE_ISP8031, }, 5281 }; 5282 5283 struct fw_blob * 5284 qla2x00_request_firmware(scsi_qla_host_t *vha) 5285 { 5286 struct qla_hw_data *ha = vha->hw; 5287 struct fw_blob *blob; 5288 5289 if (IS_QLA2100(ha)) { 5290 blob = &qla_fw_blobs[FW_ISP21XX]; 5291 } else if (IS_QLA2200(ha)) { 5292 blob = &qla_fw_blobs[FW_ISP22XX]; 5293 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5294 blob = &qla_fw_blobs[FW_ISP2300]; 5295 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5296 blob = &qla_fw_blobs[FW_ISP2322]; 5297 } else if (IS_QLA24XX_TYPE(ha)) { 5298 blob = &qla_fw_blobs[FW_ISP24XX]; 5299 } else if (IS_QLA25XX(ha)) { 5300 blob = &qla_fw_blobs[FW_ISP25XX]; 5301 } else if (IS_QLA81XX(ha)) { 5302 blob = &qla_fw_blobs[FW_ISP81XX]; 5303 } else if (IS_QLA82XX(ha)) { 5304 blob = &qla_fw_blobs[FW_ISP82XX]; 5305 } else if (IS_QLA2031(ha)) { 5306 blob = &qla_fw_blobs[FW_ISP2031]; 5307 } else if (IS_QLA8031(ha)) { 5308 blob = &qla_fw_blobs[FW_ISP8031]; 5309 } else { 5310 return NULL; 5311 } 5312 5313 mutex_lock(&qla_fw_lock); 5314 if (blob->fw) 5315 goto out; 5316 5317 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5318 ql_log(ql_log_warn, vha, 0x0063, 5319 "Failed to load firmware image (%s).\n", blob->name); 5320 blob->fw = NULL; 5321 blob = NULL; 5322 goto out; 5323 } 5324 5325 out: 5326 mutex_unlock(&qla_fw_lock); 5327 return blob; 5328 } 5329 5330 static void 5331 qla2x00_release_firmware(void) 5332 { 5333 int idx; 5334 5335 mutex_lock(&qla_fw_lock); 5336 for (idx = 0; idx < FW_BLOBS; idx++) 5337 release_firmware(qla_fw_blobs[idx].fw); 5338 mutex_unlock(&qla_fw_lock); 5339 } 5340 5341 static pci_ers_result_t 5342 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5343 { 5344 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5345 struct qla_hw_data *ha = vha->hw; 5346 5347 ql_dbg(ql_dbg_aer, vha, 0x9000, 5348 "PCI error detected, state %x.\n", state); 5349 5350 switch (state) { 5351 case pci_channel_io_normal: 5352 ha->flags.eeh_busy = 0; 5353 return PCI_ERS_RESULT_CAN_RECOVER; 5354 case pci_channel_io_frozen: 5355 ha->flags.eeh_busy = 1; 5356 /* For ISP82XX complete any pending mailbox cmd */ 5357 if (IS_QLA82XX(ha)) { 5358 ha->flags.isp82xx_fw_hung = 1; 5359 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 5360 qla82xx_clear_pending_mbx(vha); 5361 } 5362 qla2x00_free_irqs(vha); 5363 pci_disable_device(pdev); 5364 /* Return back all IOs */ 5365 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5366 return PCI_ERS_RESULT_NEED_RESET; 5367 case pci_channel_io_perm_failure: 5368 ha->flags.pci_channel_io_perm_failure = 1; 5369 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 5370 return PCI_ERS_RESULT_DISCONNECT; 5371 } 5372 return PCI_ERS_RESULT_NEED_RESET; 5373 } 5374 5375 static pci_ers_result_t 5376 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 5377 { 5378 int risc_paused = 0; 5379 uint32_t stat; 5380 unsigned long flags; 5381 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5382 struct qla_hw_data *ha = base_vha->hw; 5383 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5384 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 5385 5386 if (IS_QLA82XX(ha)) 5387 return PCI_ERS_RESULT_RECOVERED; 5388 5389 spin_lock_irqsave(&ha->hardware_lock, flags); 5390 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 5391 stat = RD_REG_DWORD(®->hccr); 5392 if (stat & HCCR_RISC_PAUSE) 5393 risc_paused = 1; 5394 } else if (IS_QLA23XX(ha)) { 5395 stat = RD_REG_DWORD(®->u.isp2300.host_status); 5396 if (stat & HSR_RISC_PAUSED) 5397 risc_paused = 1; 5398 } else if (IS_FWI2_CAPABLE(ha)) { 5399 stat = RD_REG_DWORD(®24->host_status); 5400 if (stat & HSRX_RISC_PAUSED) 5401 risc_paused = 1; 5402 } 5403 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5404 5405 if (risc_paused) { 5406 ql_log(ql_log_info, base_vha, 0x9003, 5407 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 5408 ha->isp_ops->fw_dump(base_vha, 0); 5409 5410 return PCI_ERS_RESULT_NEED_RESET; 5411 } else 5412 return PCI_ERS_RESULT_RECOVERED; 5413 } 5414 5415 static uint32_t 5416 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 5417 { 5418 uint32_t rval = QLA_FUNCTION_FAILED; 5419 uint32_t drv_active = 0; 5420 struct qla_hw_data *ha = base_vha->hw; 5421 int fn; 5422 struct pci_dev *other_pdev = NULL; 5423 5424 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 5425 "Entered %s.\n", __func__); 5426 5427 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5428 5429 if (base_vha->flags.online) { 5430 /* Abort all outstanding commands, 5431 * so as to be requeued later */ 5432 qla2x00_abort_isp_cleanup(base_vha); 5433 } 5434 5435 5436 fn = PCI_FUNC(ha->pdev->devfn); 5437 while (fn > 0) { 5438 fn--; 5439 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 5440 "Finding pci device at function = 0x%x.\n", fn); 5441 other_pdev = 5442 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 5443 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 5444 fn)); 5445 5446 if (!other_pdev) 5447 continue; 5448 if (atomic_read(&other_pdev->enable_cnt)) { 5449 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 5450 "Found PCI func available and enable at 0x%x.\n", 5451 fn); 5452 pci_dev_put(other_pdev); 5453 break; 5454 } 5455 pci_dev_put(other_pdev); 5456 } 5457 5458 if (!fn) { 5459 /* Reset owner */ 5460 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 5461 "This devfn is reset owner = 0x%x.\n", 5462 ha->pdev->devfn); 5463 qla82xx_idc_lock(ha); 5464 5465 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5466 QLA8XXX_DEV_INITIALIZING); 5467 5468 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 5469 QLA82XX_IDC_VERSION); 5470 5471 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 5472 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 5473 "drv_active = 0x%x.\n", drv_active); 5474 5475 qla82xx_idc_unlock(ha); 5476 /* Reset if device is not already reset 5477 * drv_active would be 0 if a reset has already been done 5478 */ 5479 if (drv_active) 5480 rval = qla82xx_start_firmware(base_vha); 5481 else 5482 rval = QLA_SUCCESS; 5483 qla82xx_idc_lock(ha); 5484 5485 if (rval != QLA_SUCCESS) { 5486 ql_log(ql_log_info, base_vha, 0x900b, 5487 "HW State: FAILED.\n"); 5488 qla82xx_clear_drv_active(ha); 5489 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5490 QLA8XXX_DEV_FAILED); 5491 } else { 5492 ql_log(ql_log_info, base_vha, 0x900c, 5493 "HW State: READY.\n"); 5494 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5495 QLA8XXX_DEV_READY); 5496 qla82xx_idc_unlock(ha); 5497 ha->flags.isp82xx_fw_hung = 0; 5498 rval = qla82xx_restart_isp(base_vha); 5499 qla82xx_idc_lock(ha); 5500 /* Clear driver state register */ 5501 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 5502 qla82xx_set_drv_active(base_vha); 5503 } 5504 qla82xx_idc_unlock(ha); 5505 } else { 5506 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 5507 "This devfn is not reset owner = 0x%x.\n", 5508 ha->pdev->devfn); 5509 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 5510 QLA8XXX_DEV_READY)) { 5511 ha->flags.isp82xx_fw_hung = 0; 5512 rval = qla82xx_restart_isp(base_vha); 5513 qla82xx_idc_lock(ha); 5514 qla82xx_set_drv_active(base_vha); 5515 qla82xx_idc_unlock(ha); 5516 } 5517 } 5518 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5519 5520 return rval; 5521 } 5522 5523 static pci_ers_result_t 5524 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 5525 { 5526 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 5527 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5528 struct qla_hw_data *ha = base_vha->hw; 5529 struct rsp_que *rsp; 5530 int rc, retries = 10; 5531 5532 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 5533 "Slot Reset.\n"); 5534 5535 /* Workaround: qla2xxx driver which access hardware earlier 5536 * needs error state to be pci_channel_io_online. 5537 * Otherwise mailbox command timesout. 5538 */ 5539 pdev->error_state = pci_channel_io_normal; 5540 5541 pci_restore_state(pdev); 5542 5543 /* pci_restore_state() clears the saved_state flag of the device 5544 * save restored state which resets saved_state flag 5545 */ 5546 pci_save_state(pdev); 5547 5548 if (ha->mem_only) 5549 rc = pci_enable_device_mem(pdev); 5550 else 5551 rc = pci_enable_device(pdev); 5552 5553 if (rc) { 5554 ql_log(ql_log_warn, base_vha, 0x9005, 5555 "Can't re-enable PCI device after reset.\n"); 5556 goto exit_slot_reset; 5557 } 5558 5559 rsp = ha->rsp_q_map[0]; 5560 if (qla2x00_request_irqs(ha, rsp)) 5561 goto exit_slot_reset; 5562 5563 if (ha->isp_ops->pci_config(base_vha)) 5564 goto exit_slot_reset; 5565 5566 if (IS_QLA82XX(ha)) { 5567 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 5568 ret = PCI_ERS_RESULT_RECOVERED; 5569 goto exit_slot_reset; 5570 } else 5571 goto exit_slot_reset; 5572 } 5573 5574 while (ha->flags.mbox_busy && retries--) 5575 msleep(1000); 5576 5577 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5578 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 5579 ret = PCI_ERS_RESULT_RECOVERED; 5580 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 5581 5582 5583 exit_slot_reset: 5584 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 5585 "slot_reset return %x.\n", ret); 5586 5587 return ret; 5588 } 5589 5590 static void 5591 qla2xxx_pci_resume(struct pci_dev *pdev) 5592 { 5593 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 5594 struct qla_hw_data *ha = base_vha->hw; 5595 int ret; 5596 5597 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 5598 "pci_resume.\n"); 5599 5600 ret = qla2x00_wait_for_hba_online(base_vha); 5601 if (ret != QLA_SUCCESS) { 5602 ql_log(ql_log_fatal, base_vha, 0x9002, 5603 "The device failed to resume I/O from slot/link_reset.\n"); 5604 } 5605 5606 pci_cleanup_aer_uncorrect_error_status(pdev); 5607 5608 ha->flags.eeh_busy = 0; 5609 } 5610 5611 static const struct pci_error_handlers qla2xxx_err_handler = { 5612 .error_detected = qla2xxx_pci_error_detected, 5613 .mmio_enabled = qla2xxx_pci_mmio_enabled, 5614 .slot_reset = qla2xxx_pci_slot_reset, 5615 .resume = qla2xxx_pci_resume, 5616 }; 5617 5618 static struct pci_device_id qla2xxx_pci_tbl[] = { 5619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 5634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 5635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 5636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 5637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 5638 { 0 }, 5639 }; 5640 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 5641 5642 static struct pci_driver qla2xxx_pci_driver = { 5643 .name = QLA2XXX_DRIVER_NAME, 5644 .driver = { 5645 .owner = THIS_MODULE, 5646 }, 5647 .id_table = qla2xxx_pci_tbl, 5648 .probe = qla2x00_probe_one, 5649 .remove = qla2x00_remove_one, 5650 .shutdown = qla2x00_shutdown, 5651 .err_handler = &qla2xxx_err_handler, 5652 }; 5653 5654 static const struct file_operations apidev_fops = { 5655 .owner = THIS_MODULE, 5656 .llseek = noop_llseek, 5657 }; 5658 5659 /** 5660 * qla2x00_module_init - Module initialization. 5661 **/ 5662 static int __init 5663 qla2x00_module_init(void) 5664 { 5665 int ret = 0; 5666 5667 /* Allocate cache for SRBs. */ 5668 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 5669 SLAB_HWCACHE_ALIGN, NULL); 5670 if (srb_cachep == NULL) { 5671 ql_log(ql_log_fatal, NULL, 0x0001, 5672 "Unable to allocate SRB cache...Failing load!.\n"); 5673 return -ENOMEM; 5674 } 5675 5676 /* Initialize target kmem_cache and mem_pools */ 5677 ret = qlt_init(); 5678 if (ret < 0) { 5679 kmem_cache_destroy(srb_cachep); 5680 return ret; 5681 } else if (ret > 0) { 5682 /* 5683 * If initiator mode is explictly disabled by qlt_init(), 5684 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 5685 * performing scsi_scan_target() during LOOP UP event. 5686 */ 5687 qla2xxx_transport_functions.disable_target_scan = 1; 5688 qla2xxx_transport_vport_functions.disable_target_scan = 1; 5689 } 5690 5691 /* Derive version string. */ 5692 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 5693 if (ql2xextended_error_logging) 5694 strcat(qla2x00_version_str, "-debug"); 5695 5696 qla2xxx_transport_template = 5697 fc_attach_transport(&qla2xxx_transport_functions); 5698 if (!qla2xxx_transport_template) { 5699 kmem_cache_destroy(srb_cachep); 5700 ql_log(ql_log_fatal, NULL, 0x0002, 5701 "fc_attach_transport failed...Failing load!.\n"); 5702 qlt_exit(); 5703 return -ENODEV; 5704 } 5705 5706 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 5707 if (apidev_major < 0) { 5708 ql_log(ql_log_fatal, NULL, 0x0003, 5709 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 5710 } 5711 5712 qla2xxx_transport_vport_template = 5713 fc_attach_transport(&qla2xxx_transport_vport_functions); 5714 if (!qla2xxx_transport_vport_template) { 5715 kmem_cache_destroy(srb_cachep); 5716 qlt_exit(); 5717 fc_release_transport(qla2xxx_transport_template); 5718 ql_log(ql_log_fatal, NULL, 0x0004, 5719 "fc_attach_transport vport failed...Failing load!.\n"); 5720 return -ENODEV; 5721 } 5722 ql_log(ql_log_info, NULL, 0x0005, 5723 "QLogic Fibre Channel HBA Driver: %s.\n", 5724 qla2x00_version_str); 5725 ret = pci_register_driver(&qla2xxx_pci_driver); 5726 if (ret) { 5727 kmem_cache_destroy(srb_cachep); 5728 qlt_exit(); 5729 fc_release_transport(qla2xxx_transport_template); 5730 fc_release_transport(qla2xxx_transport_vport_template); 5731 ql_log(ql_log_fatal, NULL, 0x0006, 5732 "pci_register_driver failed...ret=%d Failing load!.\n", 5733 ret); 5734 } 5735 return ret; 5736 } 5737 5738 /** 5739 * qla2x00_module_exit - Module cleanup. 5740 **/ 5741 static void __exit 5742 qla2x00_module_exit(void) 5743 { 5744 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 5745 pci_unregister_driver(&qla2xxx_pci_driver); 5746 qla2x00_release_firmware(); 5747 kmem_cache_destroy(srb_cachep); 5748 qlt_exit(); 5749 if (ctx_cachep) 5750 kmem_cache_destroy(ctx_cachep); 5751 fc_release_transport(qla2xxx_transport_template); 5752 fc_release_transport(qla2xxx_transport_vport_template); 5753 } 5754 5755 module_init(qla2x00_module_init); 5756 module_exit(qla2x00_module_exit); 5757 5758 MODULE_AUTHOR("QLogic Corporation"); 5759 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 5760 MODULE_LICENSE("GPL"); 5761 MODULE_VERSION(QLA2XXX_VERSION); 5762 MODULE_FIRMWARE(FW_FILE_ISP21XX); 5763 MODULE_FIRMWARE(FW_FILE_ISP22XX); 5764 MODULE_FIRMWARE(FW_FILE_ISP2300); 5765 MODULE_FIRMWARE(FW_FILE_ISP2322); 5766 MODULE_FIRMWARE(FW_FILE_ISP24XX); 5767 MODULE_FIRMWARE(FW_FILE_ISP25XX); 5768