1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 int ql2xfulldump_on_mpifail; 39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 41 "Set this to take full dump on MPI hang."); 42 43 int ql2xenforce_iocb_limit = 1; 44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 47 48 /* 49 * CT6 CTX allocation cache 50 */ 51 static struct kmem_cache *ctx_cachep; 52 /* 53 * error level for logging 54 */ 55 uint ql_errlev = 0x8001; 56 57 int ql2xsecenable; 58 module_param(ql2xsecenable, int, S_IRUGO); 59 MODULE_PARM_DESC(ql2xsecenable, 60 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 61 62 static int ql2xenableclass2; 63 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 64 MODULE_PARM_DESC(ql2xenableclass2, 65 "Specify if Class 2 operations are supported from the very " 66 "beginning. Default is 0 - class 2 not supported."); 67 68 69 int ql2xlogintimeout = 20; 70 module_param(ql2xlogintimeout, int, S_IRUGO); 71 MODULE_PARM_DESC(ql2xlogintimeout, 72 "Login timeout value in seconds."); 73 74 int qlport_down_retry; 75 module_param(qlport_down_retry, int, S_IRUGO); 76 MODULE_PARM_DESC(qlport_down_retry, 77 "Maximum number of command retries to a port that returns " 78 "a PORT-DOWN status."); 79 80 int ql2xplogiabsentdevice; 81 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(ql2xplogiabsentdevice, 83 "Option to enable PLOGI to devices that are not present after " 84 "a Fabric scan. This is needed for several broken switches. " 85 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 86 87 int ql2xloginretrycount; 88 module_param(ql2xloginretrycount, int, S_IRUGO); 89 MODULE_PARM_DESC(ql2xloginretrycount, 90 "Specify an alternate value for the NVRAM login retry count."); 91 92 int ql2xallocfwdump = 1; 93 module_param(ql2xallocfwdump, int, S_IRUGO); 94 MODULE_PARM_DESC(ql2xallocfwdump, 95 "Option to enable allocation of memory for a firmware dump " 96 "during HBA initialization. Memory allocation requirements " 97 "vary by ISP type. Default is 1 - allocate memory."); 98 99 int ql2xextended_error_logging; 100 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 101 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 102 MODULE_PARM_DESC(ql2xextended_error_logging, 103 "Option to enable extended error logging,\n" 104 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 105 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 106 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 107 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 108 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 109 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 110 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 111 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 112 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 113 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 114 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 115 "\t\t0x1e400000 - Preferred value for capturing essential " 116 "debug information (equivalent to old " 117 "ql2xextended_error_logging=1).\n" 118 "\t\tDo LOGICAL OR of the value to enable more than one level"); 119 120 int ql2xshiftctondsd = 6; 121 module_param(ql2xshiftctondsd, int, S_IRUGO); 122 MODULE_PARM_DESC(ql2xshiftctondsd, 123 "Set to control shifting of command type processing " 124 "based on total number of SG elements."); 125 126 int ql2xfdmienable = 1; 127 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 128 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 129 MODULE_PARM_DESC(ql2xfdmienable, 130 "Enables FDMI registrations. " 131 "0 - no FDMI registrations. " 132 "1 - provide FDMI registrations (default)."); 133 134 #define MAX_Q_DEPTH 64 135 static int ql2xmaxqdepth = MAX_Q_DEPTH; 136 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 137 MODULE_PARM_DESC(ql2xmaxqdepth, 138 "Maximum queue depth to set for each LUN. " 139 "Default is 64."); 140 141 int ql2xenabledif = 2; 142 module_param(ql2xenabledif, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xenabledif, 144 " Enable T10-CRC-DIF:\n" 145 " Default is 2.\n" 146 " 0 -- No DIF Support\n" 147 " 1 -- Enable DIF for all types\n" 148 " 2 -- Enable DIF for all types, except Type 0.\n"); 149 150 #if (IS_ENABLED(CONFIG_NVME_FC)) 151 int ql2xnvmeenable = 1; 152 #else 153 int ql2xnvmeenable; 154 #endif 155 module_param(ql2xnvmeenable, int, 0644); 156 MODULE_PARM_DESC(ql2xnvmeenable, 157 "Enables NVME support. " 158 "0 - no NVMe. Default is Y"); 159 160 int ql2xenablehba_err_chk = 2; 161 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 162 MODULE_PARM_DESC(ql2xenablehba_err_chk, 163 " Enable T10-CRC-DIF Error isolation by HBA:\n" 164 " Default is 2.\n" 165 " 0 -- Error isolation disabled\n" 166 " 1 -- Error isolation enabled only for DIX Type 0\n" 167 " 2 -- Error isolation enabled for all Types\n"); 168 169 int ql2xiidmaenable = 1; 170 module_param(ql2xiidmaenable, int, S_IRUGO); 171 MODULE_PARM_DESC(ql2xiidmaenable, 172 "Enables iIDMA settings " 173 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 174 175 int ql2xmqsupport = 1; 176 module_param(ql2xmqsupport, int, S_IRUGO); 177 MODULE_PARM_DESC(ql2xmqsupport, 178 "Enable on demand multiple queue pairs support " 179 "Default is 1 for supported. " 180 "Set it to 0 to turn off mq qpair support."); 181 182 int ql2xfwloadbin; 183 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 184 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 185 MODULE_PARM_DESC(ql2xfwloadbin, 186 "Option to specify location from which to load ISP firmware:.\n" 187 " 2 -- load firmware via the request_firmware() (hotplug).\n" 188 " interface.\n" 189 " 1 -- load firmware from flash.\n" 190 " 0 -- use default semantics.\n"); 191 192 int ql2xetsenable; 193 module_param(ql2xetsenable, int, S_IRUGO); 194 MODULE_PARM_DESC(ql2xetsenable, 195 "Enables firmware ETS burst." 196 "Default is 0 - skip ETS enablement."); 197 198 int ql2xdbwr = 1; 199 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 200 MODULE_PARM_DESC(ql2xdbwr, 201 "Option to specify scheme for request queue posting.\n" 202 " 0 -- Regular doorbell.\n" 203 " 1 -- CAMRAM doorbell (faster).\n"); 204 205 int ql2xtargetreset = 1; 206 module_param(ql2xtargetreset, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xtargetreset, 208 "Enable target reset." 209 "Default is 1 - use hw defaults."); 210 211 int ql2xgffidenable; 212 module_param(ql2xgffidenable, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xgffidenable, 214 "Enables GFF_ID checks of port type. " 215 "Default is 0 - Do not use GFF_ID information."); 216 217 int ql2xasynctmfenable = 1; 218 module_param(ql2xasynctmfenable, int, S_IRUGO); 219 MODULE_PARM_DESC(ql2xasynctmfenable, 220 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 221 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 222 223 int ql2xdontresethba; 224 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 225 MODULE_PARM_DESC(ql2xdontresethba, 226 "Option to specify reset behaviour.\n" 227 " 0 (Default) -- Reset on failure.\n" 228 " 1 -- Do not reset on failure.\n"); 229 230 uint64_t ql2xmaxlun = MAX_LUNS; 231 module_param(ql2xmaxlun, ullong, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmaxlun, 233 "Defines the maximum LU number to register with the SCSI " 234 "midlayer. Default is 65535."); 235 236 int ql2xmdcapmask = 0x1F; 237 module_param(ql2xmdcapmask, int, S_IRUGO); 238 MODULE_PARM_DESC(ql2xmdcapmask, 239 "Set the Minidump driver capture mask level. " 240 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 241 242 int ql2xmdenable = 1; 243 module_param(ql2xmdenable, int, S_IRUGO); 244 MODULE_PARM_DESC(ql2xmdenable, 245 "Enable/disable MiniDump. " 246 "0 - MiniDump disabled. " 247 "1 (Default) - MiniDump enabled."); 248 249 int ql2xexlogins; 250 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 251 MODULE_PARM_DESC(ql2xexlogins, 252 "Number of extended Logins. " 253 "0 (Default)- Disabled."); 254 255 int ql2xexchoffld = 1024; 256 module_param(ql2xexchoffld, uint, 0644); 257 MODULE_PARM_DESC(ql2xexchoffld, 258 "Number of target exchanges."); 259 260 int ql2xiniexchg = 1024; 261 module_param(ql2xiniexchg, uint, 0644); 262 MODULE_PARM_DESC(ql2xiniexchg, 263 "Number of initiator exchanges."); 264 265 int ql2xfwholdabts; 266 module_param(ql2xfwholdabts, int, S_IRUGO); 267 MODULE_PARM_DESC(ql2xfwholdabts, 268 "Allow FW to hold status IOCB until ABTS rsp received. " 269 "0 (Default) Do not set fw option. " 270 "1 - Set fw option to hold ABTS."); 271 272 int ql2xmvasynctoatio = 1; 273 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 274 MODULE_PARM_DESC(ql2xmvasynctoatio, 275 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 276 "0 (Default). Do not move IOCBs" 277 "1 - Move IOCBs."); 278 279 int ql2xautodetectsfp = 1; 280 module_param(ql2xautodetectsfp, int, 0444); 281 MODULE_PARM_DESC(ql2xautodetectsfp, 282 "Detect SFP range and set appropriate distance.\n" 283 "1 (Default): Enable\n"); 284 285 int ql2xenablemsix = 1; 286 module_param(ql2xenablemsix, int, 0444); 287 MODULE_PARM_DESC(ql2xenablemsix, 288 "Set to enable MSI or MSI-X interrupt mechanism.\n" 289 " Default is 1, enable MSI-X interrupt mechanism.\n" 290 " 0 -- enable traditional pin-based mechanism.\n" 291 " 1 -- enable MSI-X interrupt mechanism.\n" 292 " 2 -- enable MSI interrupt mechanism.\n"); 293 294 int qla2xuseresexchforels; 295 module_param(qla2xuseresexchforels, int, 0444); 296 MODULE_PARM_DESC(qla2xuseresexchforels, 297 "Reserve 1/2 of emergency exchanges for ELS.\n" 298 " 0 (default): disabled"); 299 300 static int ql2xprotmask; 301 module_param(ql2xprotmask, int, 0644); 302 MODULE_PARM_DESC(ql2xprotmask, 303 "Override DIF/DIX protection capabilities mask\n" 304 "Default is 0 which sets protection mask based on " 305 "capabilities reported by HBA firmware.\n"); 306 307 static int ql2xprotguard; 308 module_param(ql2xprotguard, int, 0644); 309 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 310 " 0 -- Let HBA firmware decide\n" 311 " 1 -- Force T10 CRC\n" 312 " 2 -- Force IP checksum\n"); 313 314 int ql2xdifbundlinginternalbuffers; 315 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 316 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 317 "Force using internal buffers for DIF information\n" 318 "0 (Default). Based on check.\n" 319 "1 Force using internal buffers\n"); 320 321 int ql2xsmartsan; 322 module_param(ql2xsmartsan, int, 0444); 323 module_param_named(smartsan, ql2xsmartsan, int, 0444); 324 MODULE_PARM_DESC(ql2xsmartsan, 325 "Send SmartSAN Management Attributes for FDMI Registration." 326 " Default is 0 - No SmartSAN registration," 327 " 1 - Register SmartSAN Management Attributes."); 328 329 int ql2xrdpenable; 330 module_param(ql2xrdpenable, int, 0444); 331 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 332 MODULE_PARM_DESC(ql2xrdpenable, 333 "Enables RDP responses. " 334 "0 - no RDP responses (default). " 335 "1 - provide RDP responses."); 336 int ql2xabts_wait_nvme = 1; 337 module_param(ql2xabts_wait_nvme, int, 0444); 338 MODULE_PARM_DESC(ql2xabts_wait_nvme, 339 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 340 341 342 static void qla2x00_clear_drv_active(struct qla_hw_data *); 343 static void qla2x00_free_device(scsi_qla_host_t *); 344 static int qla2xxx_map_queues(struct Scsi_Host *shost); 345 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 346 347 348 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 349 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 350 351 /* TODO Convert to inlines 352 * 353 * Timer routines 354 */ 355 356 __inline__ void 357 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 358 { 359 timer_setup(&vha->timer, qla2x00_timer, 0); 360 vha->timer.expires = jiffies + interval * HZ; 361 add_timer(&vha->timer); 362 vha->timer_active = 1; 363 } 364 365 static inline void 366 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 367 { 368 /* Currently used for 82XX only. */ 369 if (vha->device_flags & DFLG_DEV_FAILED) { 370 ql_dbg(ql_dbg_timer, vha, 0x600d, 371 "Device in a failed state, returning.\n"); 372 return; 373 } 374 375 mod_timer(&vha->timer, jiffies + interval * HZ); 376 } 377 378 static __inline__ void 379 qla2x00_stop_timer(scsi_qla_host_t *vha) 380 { 381 del_timer_sync(&vha->timer); 382 vha->timer_active = 0; 383 } 384 385 static int qla2x00_do_dpc(void *data); 386 387 static void qla2x00_rst_aen(scsi_qla_host_t *); 388 389 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 390 struct req_que **, struct rsp_que **); 391 static void qla2x00_free_fw_dump(struct qla_hw_data *); 392 static void qla2x00_mem_free(struct qla_hw_data *); 393 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 394 struct qla_qpair *qpair); 395 396 /* -------------------------------------------------------------------------- */ 397 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 398 struct rsp_que *rsp) 399 { 400 struct qla_hw_data *ha = vha->hw; 401 402 rsp->qpair = ha->base_qpair; 403 rsp->req = req; 404 ha->base_qpair->hw = ha; 405 ha->base_qpair->req = req; 406 ha->base_qpair->rsp = rsp; 407 ha->base_qpair->vha = vha; 408 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 409 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 410 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 411 ha->base_qpair->srb_mempool = ha->srb_mempool; 412 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 413 ha->base_qpair->enable_class_2 = ql2xenableclass2; 414 /* init qpair to this cpu. Will adjust at run time. */ 415 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 416 ha->base_qpair->pdev = ha->pdev; 417 418 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 419 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 420 } 421 422 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 423 struct rsp_que *rsp) 424 { 425 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 426 427 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 428 GFP_KERNEL); 429 if (!ha->req_q_map) { 430 ql_log(ql_log_fatal, vha, 0x003b, 431 "Unable to allocate memory for request queue ptrs.\n"); 432 goto fail_req_map; 433 } 434 435 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 436 GFP_KERNEL); 437 if (!ha->rsp_q_map) { 438 ql_log(ql_log_fatal, vha, 0x003c, 439 "Unable to allocate memory for response queue ptrs.\n"); 440 goto fail_rsp_map; 441 } 442 443 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 444 if (ha->base_qpair == NULL) { 445 ql_log(ql_log_warn, vha, 0x00e0, 446 "Failed to allocate base queue pair memory.\n"); 447 goto fail_base_qpair; 448 } 449 450 qla_init_base_qpair(vha, req, rsp); 451 452 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 453 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 454 GFP_KERNEL); 455 if (!ha->queue_pair_map) { 456 ql_log(ql_log_fatal, vha, 0x0180, 457 "Unable to allocate memory for queue pair ptrs.\n"); 458 goto fail_qpair_map; 459 } 460 } 461 462 /* 463 * Make sure we record at least the request and response queue zero in 464 * case we need to free them if part of the probe fails. 465 */ 466 ha->rsp_q_map[0] = rsp; 467 ha->req_q_map[0] = req; 468 set_bit(0, ha->rsp_qid_map); 469 set_bit(0, ha->req_qid_map); 470 return 0; 471 472 fail_qpair_map: 473 kfree(ha->base_qpair); 474 ha->base_qpair = NULL; 475 fail_base_qpair: 476 kfree(ha->rsp_q_map); 477 ha->rsp_q_map = NULL; 478 fail_rsp_map: 479 kfree(ha->req_q_map); 480 ha->req_q_map = NULL; 481 fail_req_map: 482 return -ENOMEM; 483 } 484 485 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 486 { 487 if (IS_QLAFX00(ha)) { 488 if (req && req->ring_fx00) 489 dma_free_coherent(&ha->pdev->dev, 490 (req->length_fx00 + 1) * sizeof(request_t), 491 req->ring_fx00, req->dma_fx00); 492 } else if (req && req->ring) 493 dma_free_coherent(&ha->pdev->dev, 494 (req->length + 1) * sizeof(request_t), 495 req->ring, req->dma); 496 497 if (req) 498 kfree(req->outstanding_cmds); 499 500 kfree(req); 501 } 502 503 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 504 { 505 if (IS_QLAFX00(ha)) { 506 if (rsp && rsp->ring_fx00) 507 dma_free_coherent(&ha->pdev->dev, 508 (rsp->length_fx00 + 1) * sizeof(request_t), 509 rsp->ring_fx00, rsp->dma_fx00); 510 } else if (rsp && rsp->ring) { 511 dma_free_coherent(&ha->pdev->dev, 512 (rsp->length + 1) * sizeof(response_t), 513 rsp->ring, rsp->dma); 514 } 515 kfree(rsp); 516 } 517 518 static void qla2x00_free_queues(struct qla_hw_data *ha) 519 { 520 struct req_que *req; 521 struct rsp_que *rsp; 522 int cnt; 523 unsigned long flags; 524 525 if (ha->queue_pair_map) { 526 kfree(ha->queue_pair_map); 527 ha->queue_pair_map = NULL; 528 } 529 if (ha->base_qpair) { 530 kfree(ha->base_qpair); 531 ha->base_qpair = NULL; 532 } 533 534 spin_lock_irqsave(&ha->hardware_lock, flags); 535 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 536 if (!test_bit(cnt, ha->req_qid_map)) 537 continue; 538 539 req = ha->req_q_map[cnt]; 540 clear_bit(cnt, ha->req_qid_map); 541 ha->req_q_map[cnt] = NULL; 542 543 spin_unlock_irqrestore(&ha->hardware_lock, flags); 544 qla2x00_free_req_que(ha, req); 545 spin_lock_irqsave(&ha->hardware_lock, flags); 546 } 547 spin_unlock_irqrestore(&ha->hardware_lock, flags); 548 549 kfree(ha->req_q_map); 550 ha->req_q_map = NULL; 551 552 553 spin_lock_irqsave(&ha->hardware_lock, flags); 554 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 555 if (!test_bit(cnt, ha->rsp_qid_map)) 556 continue; 557 558 rsp = ha->rsp_q_map[cnt]; 559 clear_bit(cnt, ha->rsp_qid_map); 560 ha->rsp_q_map[cnt] = NULL; 561 spin_unlock_irqrestore(&ha->hardware_lock, flags); 562 qla2x00_free_rsp_que(ha, rsp); 563 spin_lock_irqsave(&ha->hardware_lock, flags); 564 } 565 spin_unlock_irqrestore(&ha->hardware_lock, flags); 566 567 kfree(ha->rsp_q_map); 568 ha->rsp_q_map = NULL; 569 } 570 571 static char * 572 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 573 { 574 struct qla_hw_data *ha = vha->hw; 575 static const char *const pci_bus_modes[] = { 576 "33", "66", "100", "133", 577 }; 578 uint16_t pci_bus; 579 580 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 581 if (pci_bus) { 582 snprintf(str, str_len, "PCI-X (%s MHz)", 583 pci_bus_modes[pci_bus]); 584 } else { 585 pci_bus = (ha->pci_attr & BIT_8) >> 8; 586 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 587 } 588 589 return str; 590 } 591 592 static char * 593 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 594 { 595 static const char *const pci_bus_modes[] = { 596 "33", "66", "100", "133", 597 }; 598 struct qla_hw_data *ha = vha->hw; 599 uint32_t pci_bus; 600 601 if (pci_is_pcie(ha->pdev)) { 602 uint32_t lstat, lspeed, lwidth; 603 const char *speed_str; 604 605 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 606 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 607 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 608 609 switch (lspeed) { 610 case 1: 611 speed_str = "2.5GT/s"; 612 break; 613 case 2: 614 speed_str = "5.0GT/s"; 615 break; 616 case 3: 617 speed_str = "8.0GT/s"; 618 break; 619 case 4: 620 speed_str = "16.0GT/s"; 621 break; 622 default: 623 speed_str = "<unknown>"; 624 break; 625 } 626 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 627 628 return str; 629 } 630 631 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 632 if (pci_bus == 0 || pci_bus == 8) 633 snprintf(str, str_len, "PCI (%s MHz)", 634 pci_bus_modes[pci_bus >> 3]); 635 else 636 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 637 pci_bus & 4 ? 2 : 1, 638 pci_bus_modes[pci_bus & 3]); 639 640 return str; 641 } 642 643 static char * 644 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 645 { 646 char un_str[10]; 647 struct qla_hw_data *ha = vha->hw; 648 649 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 650 ha->fw_minor_version, ha->fw_subminor_version); 651 652 if (ha->fw_attributes & BIT_9) { 653 strcat(str, "FLX"); 654 return (str); 655 } 656 657 switch (ha->fw_attributes & 0xFF) { 658 case 0x7: 659 strcat(str, "EF"); 660 break; 661 case 0x17: 662 strcat(str, "TP"); 663 break; 664 case 0x37: 665 strcat(str, "IP"); 666 break; 667 case 0x77: 668 strcat(str, "VI"); 669 break; 670 default: 671 sprintf(un_str, "(%x)", ha->fw_attributes); 672 strcat(str, un_str); 673 break; 674 } 675 if (ha->fw_attributes & 0x100) 676 strcat(str, "X"); 677 678 return (str); 679 } 680 681 static char * 682 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 683 { 684 struct qla_hw_data *ha = vha->hw; 685 686 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 687 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 688 return str; 689 } 690 691 void qla2x00_sp_free_dma(srb_t *sp) 692 { 693 struct qla_hw_data *ha = sp->vha->hw; 694 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 695 696 if (sp->flags & SRB_DMA_VALID) { 697 scsi_dma_unmap(cmd); 698 sp->flags &= ~SRB_DMA_VALID; 699 } 700 701 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 702 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 703 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 704 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 705 } 706 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 708 /* List assured to be having elements */ 709 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 711 } 712 713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 714 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 715 716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 718 } 719 720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 721 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 722 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 724 ctx1->fcp_cmnd_dma); 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 728 mempool_free(ctx1, ha->ctx_mempool); 729 } 730 } 731 732 void qla2x00_sp_compl(srb_t *sp, int res) 733 { 734 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 735 struct completion *comp = sp->comp; 736 737 sp->free(sp); 738 cmd->result = res; 739 CMD_SP(cmd) = NULL; 740 scsi_done(cmd); 741 if (comp) 742 complete(comp); 743 } 744 745 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 746 { 747 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 748 struct qla_hw_data *ha = sp->fcport->vha->hw; 749 750 if (sp->flags & SRB_DMA_VALID) { 751 scsi_dma_unmap(cmd); 752 sp->flags &= ~SRB_DMA_VALID; 753 } 754 755 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 756 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 757 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 758 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 759 } 760 761 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 762 /* List assured to be having elements */ 763 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 764 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 765 } 766 767 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 768 struct crc_context *difctx = sp->u.scmd.crc_ctx; 769 struct dsd_dma *dif_dsd, *nxt_dsd; 770 771 list_for_each_entry_safe(dif_dsd, nxt_dsd, 772 &difctx->ldif_dma_hndl_list, list) { 773 list_del(&dif_dsd->list); 774 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 775 dif_dsd->dsd_list_dma); 776 kfree(dif_dsd); 777 difctx->no_dif_bundl--; 778 } 779 780 list_for_each_entry_safe(dif_dsd, nxt_dsd, 781 &difctx->ldif_dsd_list, list) { 782 list_del(&dif_dsd->list); 783 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 784 dif_dsd->dsd_list_dma); 785 kfree(dif_dsd); 786 difctx->no_ldif_dsd--; 787 } 788 789 if (difctx->no_ldif_dsd) { 790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 791 "%s: difctx->no_ldif_dsd=%x\n", 792 __func__, difctx->no_ldif_dsd); 793 } 794 795 if (difctx->no_dif_bundl) { 796 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 797 "%s: difctx->no_dif_bundl=%x\n", 798 __func__, difctx->no_dif_bundl); 799 } 800 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 801 } 802 803 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 804 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 805 806 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 807 ctx1->fcp_cmnd_dma); 808 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 809 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 810 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 811 mempool_free(ctx1, ha->ctx_mempool); 812 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 813 } 814 815 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 816 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 817 818 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 819 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 820 } 821 } 822 823 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 824 { 825 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 826 struct completion *comp = sp->comp; 827 828 sp->free(sp); 829 cmd->result = res; 830 CMD_SP(cmd) = NULL; 831 scsi_done(cmd); 832 if (comp) 833 complete(comp); 834 } 835 836 static int 837 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 838 { 839 scsi_qla_host_t *vha = shost_priv(host); 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 842 struct qla_hw_data *ha = vha->hw; 843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 844 srb_t *sp; 845 int rval; 846 847 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 848 WARN_ON_ONCE(!rport)) { 849 cmd->result = DID_NO_CONNECT << 16; 850 goto qc24_fail_command; 851 } 852 853 if (ha->mqenable) { 854 uint32_t tag; 855 uint16_t hwq; 856 struct qla_qpair *qpair = NULL; 857 858 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 859 hwq = blk_mq_unique_tag_to_hwq(tag); 860 qpair = ha->queue_pair_map[hwq]; 861 862 if (qpair) 863 return qla2xxx_mqueuecommand(host, cmd, qpair); 864 } 865 866 if (ha->flags.eeh_busy) { 867 if (ha->flags.pci_channel_io_perm_failure) { 868 ql_dbg(ql_dbg_aer, vha, 0x9010, 869 "PCI Channel IO permanent failure, exiting " 870 "cmd=%p.\n", cmd); 871 cmd->result = DID_NO_CONNECT << 16; 872 } else { 873 ql_dbg(ql_dbg_aer, vha, 0x9011, 874 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 875 cmd->result = DID_REQUEUE << 16; 876 } 877 goto qc24_fail_command; 878 } 879 880 rval = fc_remote_port_chkready(rport); 881 if (rval) { 882 cmd->result = rval; 883 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 884 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 885 cmd, rval); 886 goto qc24_fail_command; 887 } 888 889 if (!vha->flags.difdix_supported && 890 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 891 ql_dbg(ql_dbg_io, vha, 0x3004, 892 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 893 cmd); 894 cmd->result = DID_NO_CONNECT << 16; 895 goto qc24_fail_command; 896 } 897 898 if (!fcport || fcport->deleted) { 899 cmd->result = DID_IMM_RETRY << 16; 900 goto qc24_fail_command; 901 } 902 903 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 904 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 905 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 906 ql_dbg(ql_dbg_io, vha, 0x3005, 907 "Returning DNC, fcport_state=%d loop_state=%d.\n", 908 atomic_read(&fcport->state), 909 atomic_read(&base_vha->loop_state)); 910 cmd->result = DID_NO_CONNECT << 16; 911 goto qc24_fail_command; 912 } 913 goto qc24_target_busy; 914 } 915 916 /* 917 * Return target busy if we've received a non-zero retry_delay_timer 918 * in a FCP_RSP. 919 */ 920 if (fcport->retry_delay_timestamp == 0) { 921 /* retry delay not set */ 922 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 923 fcport->retry_delay_timestamp = 0; 924 else 925 goto qc24_target_busy; 926 927 sp = scsi_cmd_priv(cmd); 928 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 929 930 sp->u.scmd.cmd = cmd; 931 sp->type = SRB_SCSI_CMD; 932 933 CMD_SP(cmd) = (void *)sp; 934 sp->free = qla2x00_sp_free_dma; 935 sp->done = qla2x00_sp_compl; 936 937 rval = ha->isp_ops->start_scsi(sp); 938 if (rval != QLA_SUCCESS) { 939 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 940 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 941 goto qc24_host_busy_free_sp; 942 } 943 944 return 0; 945 946 qc24_host_busy_free_sp: 947 sp->free(sp); 948 949 qc24_target_busy: 950 return SCSI_MLQUEUE_TARGET_BUSY; 951 952 qc24_fail_command: 953 scsi_done(cmd); 954 955 return 0; 956 } 957 958 /* For MQ supported I/O */ 959 int 960 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 961 struct qla_qpair *qpair) 962 { 963 scsi_qla_host_t *vha = shost_priv(host); 964 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 965 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 966 struct qla_hw_data *ha = vha->hw; 967 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 968 srb_t *sp; 969 int rval; 970 971 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 972 if (rval) { 973 cmd->result = rval; 974 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 975 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 976 cmd, rval); 977 goto qc24_fail_command; 978 } 979 980 if (!qpair->online) { 981 ql_dbg(ql_dbg_io, vha, 0x3077, 982 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 983 cmd->result = DID_NO_CONNECT << 16; 984 goto qc24_fail_command; 985 } 986 987 if (!fcport || fcport->deleted) { 988 cmd->result = DID_IMM_RETRY << 16; 989 goto qc24_fail_command; 990 } 991 992 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 993 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 994 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 995 ql_dbg(ql_dbg_io, vha, 0x3077, 996 "Returning DNC, fcport_state=%d loop_state=%d.\n", 997 atomic_read(&fcport->state), 998 atomic_read(&base_vha->loop_state)); 999 cmd->result = DID_NO_CONNECT << 16; 1000 goto qc24_fail_command; 1001 } 1002 goto qc24_target_busy; 1003 } 1004 1005 /* 1006 * Return target busy if we've received a non-zero retry_delay_timer 1007 * in a FCP_RSP. 1008 */ 1009 if (fcport->retry_delay_timestamp == 0) { 1010 /* retry delay not set */ 1011 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1012 fcport->retry_delay_timestamp = 0; 1013 else 1014 goto qc24_target_busy; 1015 1016 sp = scsi_cmd_priv(cmd); 1017 qla2xxx_init_sp(sp, vha, qpair, fcport); 1018 1019 sp->u.scmd.cmd = cmd; 1020 sp->type = SRB_SCSI_CMD; 1021 CMD_SP(cmd) = (void *)sp; 1022 sp->free = qla2xxx_qpair_sp_free_dma; 1023 sp->done = qla2xxx_qpair_sp_compl; 1024 1025 rval = ha->isp_ops->start_scsi_mq(sp); 1026 if (rval != QLA_SUCCESS) { 1027 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1028 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1029 goto qc24_host_busy_free_sp; 1030 } 1031 1032 return 0; 1033 1034 qc24_host_busy_free_sp: 1035 sp->free(sp); 1036 1037 qc24_target_busy: 1038 return SCSI_MLQUEUE_TARGET_BUSY; 1039 1040 qc24_fail_command: 1041 scsi_done(cmd); 1042 1043 return 0; 1044 } 1045 1046 /* 1047 * qla2x00_eh_wait_on_command 1048 * Waits for the command to be returned by the Firmware for some 1049 * max time. 1050 * 1051 * Input: 1052 * cmd = Scsi Command to wait on. 1053 * 1054 * Return: 1055 * Completed in time : QLA_SUCCESS 1056 * Did not complete in time : QLA_FUNCTION_FAILED 1057 */ 1058 static int 1059 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1060 { 1061 #define ABORT_POLLING_PERIOD 1000 1062 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1063 unsigned long wait_iter = ABORT_WAIT_ITER; 1064 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1065 struct qla_hw_data *ha = vha->hw; 1066 int ret = QLA_SUCCESS; 1067 1068 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1069 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1070 "Return:eh_wait.\n"); 1071 return ret; 1072 } 1073 1074 while (CMD_SP(cmd) && wait_iter--) { 1075 msleep(ABORT_POLLING_PERIOD); 1076 } 1077 if (CMD_SP(cmd)) 1078 ret = QLA_FUNCTION_FAILED; 1079 1080 return ret; 1081 } 1082 1083 /* 1084 * qla2x00_wait_for_hba_online 1085 * Wait till the HBA is online after going through 1086 * <= MAX_RETRIES_OF_ISP_ABORT or 1087 * finally HBA is disabled ie marked offline 1088 * 1089 * Input: 1090 * ha - pointer to host adapter structure 1091 * 1092 * Note: 1093 * Does context switching-Release SPIN_LOCK 1094 * (if any) before calling this routine. 1095 * 1096 * Return: 1097 * Success (Adapter is online) : 0 1098 * Failed (Adapter is offline/disabled) : 1 1099 */ 1100 int 1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1102 { 1103 int return_status; 1104 unsigned long wait_online; 1105 struct qla_hw_data *ha = vha->hw; 1106 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1107 1108 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1109 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1110 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1111 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1112 ha->dpc_active) && time_before(jiffies, wait_online)) { 1113 1114 msleep(1000); 1115 } 1116 if (base_vha->flags.online) 1117 return_status = QLA_SUCCESS; 1118 else 1119 return_status = QLA_FUNCTION_FAILED; 1120 1121 return (return_status); 1122 } 1123 1124 static inline int test_fcport_count(scsi_qla_host_t *vha) 1125 { 1126 struct qla_hw_data *ha = vha->hw; 1127 unsigned long flags; 1128 int res; 1129 /* Return 0 = sleep, x=wake */ 1130 1131 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1132 ql_dbg(ql_dbg_init, vha, 0x00ec, 1133 "tgt %p, fcport_count=%d\n", 1134 vha, vha->fcport_count); 1135 res = (vha->fcport_count == 0); 1136 if (res) { 1137 struct fc_port *fcport; 1138 1139 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1140 if (fcport->deleted != QLA_SESS_DELETED) { 1141 /* session(s) may not be fully logged in 1142 * (ie fcport_count=0), but session 1143 * deletion thread(s) may be inflight. 1144 */ 1145 1146 res = 0; 1147 break; 1148 } 1149 } 1150 } 1151 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1152 1153 return res; 1154 } 1155 1156 /* 1157 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1158 * it has dependency on UNLOADING flag to stop device discovery 1159 */ 1160 void 1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1162 { 1163 u8 i; 1164 1165 qla2x00_mark_all_devices_lost(vha); 1166 1167 for (i = 0; i < 10; i++) { 1168 if (wait_event_timeout(vha->fcport_waitQ, 1169 test_fcport_count(vha), HZ) > 0) 1170 break; 1171 } 1172 1173 flush_workqueue(vha->hw->wq); 1174 } 1175 1176 /* 1177 * qla2x00_wait_for_hba_ready 1178 * Wait till the HBA is ready before doing driver unload 1179 * 1180 * Input: 1181 * ha - pointer to host adapter structure 1182 * 1183 * Note: 1184 * Does context switching-Release SPIN_LOCK 1185 * (if any) before calling this routine. 1186 * 1187 */ 1188 static void 1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1190 { 1191 struct qla_hw_data *ha = vha->hw; 1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1195 ha->flags.mbox_busy) || 1196 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1197 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1198 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1199 break; 1200 msleep(1000); 1201 } 1202 } 1203 1204 int 1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1206 { 1207 int return_status; 1208 unsigned long wait_reset; 1209 struct qla_hw_data *ha = vha->hw; 1210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1211 1212 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1213 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1214 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1215 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1216 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1217 1218 msleep(1000); 1219 1220 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1221 ha->flags.chip_reset_done) 1222 break; 1223 } 1224 if (ha->flags.chip_reset_done) 1225 return_status = QLA_SUCCESS; 1226 else 1227 return_status = QLA_FUNCTION_FAILED; 1228 1229 return return_status; 1230 } 1231 1232 /************************************************************************** 1233 * qla2xxx_eh_abort 1234 * 1235 * Description: 1236 * The abort function will abort the specified command. 1237 * 1238 * Input: 1239 * cmd = Linux SCSI command packet to be aborted. 1240 * 1241 * Returns: 1242 * Either SUCCESS or FAILED. 1243 * 1244 * Note: 1245 * Only return FAILED if command not returned by firmware. 1246 **************************************************************************/ 1247 static int 1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1249 { 1250 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1251 DECLARE_COMPLETION_ONSTACK(comp); 1252 srb_t *sp; 1253 int ret; 1254 unsigned int id; 1255 uint64_t lun; 1256 int rval; 1257 struct qla_hw_data *ha = vha->hw; 1258 uint32_t ratov_j; 1259 struct qla_qpair *qpair; 1260 unsigned long flags; 1261 int fast_fail_status = SUCCESS; 1262 1263 if (qla2x00_isp_reg_stat(ha)) { 1264 ql_log(ql_log_info, vha, 0x8042, 1265 "PCI/Register disconnect, exiting.\n"); 1266 qla_pci_set_eeh_busy(vha); 1267 return FAILED; 1268 } 1269 1270 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1271 ret = fc_block_scsi_eh(cmd); 1272 if (ret != 0) 1273 fast_fail_status = ret; 1274 1275 sp = scsi_cmd_priv(cmd); 1276 qpair = sp->qpair; 1277 1278 vha->cmd_timeout_cnt++; 1279 1280 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1281 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1282 1283 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1284 sp->comp = ∁ 1285 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1286 1287 1288 id = cmd->device->id; 1289 lun = cmd->device->lun; 1290 1291 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1292 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1293 vha->host_no, id, lun, sp, cmd, sp->handle); 1294 1295 /* 1296 * Abort will release the original Command/sp from FW. Let the 1297 * original command call scsi_done. In return, he will wakeup 1298 * this sleeping thread. 1299 */ 1300 rval = ha->isp_ops->abort_command(sp); 1301 1302 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1303 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1304 1305 /* Wait for the command completion. */ 1306 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1307 ratov_j = msecs_to_jiffies(ratov_j); 1308 switch (rval) { 1309 case QLA_SUCCESS: 1310 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1311 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1312 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1313 __func__, ha->r_a_tov/10); 1314 ret = FAILED; 1315 } else { 1316 ret = fast_fail_status; 1317 } 1318 break; 1319 default: 1320 ret = FAILED; 1321 break; 1322 } 1323 1324 sp->comp = NULL; 1325 1326 ql_log(ql_log_info, vha, 0x801c, 1327 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1328 vha->host_no, id, lun, ret); 1329 1330 return ret; 1331 } 1332 1333 /* 1334 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1335 */ 1336 int 1337 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1338 uint64_t l, enum nexus_wait_type type) 1339 { 1340 int cnt, match, status; 1341 unsigned long flags; 1342 struct qla_hw_data *ha = vha->hw; 1343 struct req_que *req; 1344 srb_t *sp; 1345 struct scsi_cmnd *cmd; 1346 1347 status = QLA_SUCCESS; 1348 1349 spin_lock_irqsave(&ha->hardware_lock, flags); 1350 req = vha->req; 1351 for (cnt = 1; status == QLA_SUCCESS && 1352 cnt < req->num_outstanding_cmds; cnt++) { 1353 sp = req->outstanding_cmds[cnt]; 1354 if (!sp) 1355 continue; 1356 if (sp->type != SRB_SCSI_CMD) 1357 continue; 1358 if (vha->vp_idx != sp->vha->vp_idx) 1359 continue; 1360 match = 0; 1361 cmd = GET_CMD_SP(sp); 1362 switch (type) { 1363 case WAIT_HOST: 1364 match = 1; 1365 break; 1366 case WAIT_TARGET: 1367 match = cmd->device->id == t; 1368 break; 1369 case WAIT_LUN: 1370 match = (cmd->device->id == t && 1371 cmd->device->lun == l); 1372 break; 1373 } 1374 if (!match) 1375 continue; 1376 1377 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1378 status = qla2x00_eh_wait_on_command(cmd); 1379 spin_lock_irqsave(&ha->hardware_lock, flags); 1380 } 1381 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1382 1383 return status; 1384 } 1385 1386 static char *reset_errors[] = { 1387 "HBA not online", 1388 "HBA not ready", 1389 "Task management failed", 1390 "Waiting for command completions", 1391 }; 1392 1393 static int 1394 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1395 { 1396 struct scsi_device *sdev = cmd->device; 1397 scsi_qla_host_t *vha = shost_priv(sdev->host); 1398 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1399 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1400 struct qla_hw_data *ha = vha->hw; 1401 int err; 1402 1403 if (qla2x00_isp_reg_stat(ha)) { 1404 ql_log(ql_log_info, vha, 0x803e, 1405 "PCI/Register disconnect, exiting.\n"); 1406 qla_pci_set_eeh_busy(vha); 1407 return FAILED; 1408 } 1409 1410 if (!fcport) { 1411 return FAILED; 1412 } 1413 1414 err = fc_block_rport(rport); 1415 if (err != 0) 1416 return err; 1417 1418 if (fcport->deleted) 1419 return SUCCESS; 1420 1421 ql_log(ql_log_info, vha, 0x8009, 1422 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1423 sdev->id, sdev->lun, cmd); 1424 1425 err = 0; 1426 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1427 ql_log(ql_log_warn, vha, 0x800a, 1428 "Wait for hba online failed for cmd=%p.\n", cmd); 1429 goto eh_reset_failed; 1430 } 1431 err = 2; 1432 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1433 != QLA_SUCCESS) { 1434 ql_log(ql_log_warn, vha, 0x800c, 1435 "do_reset failed for cmd=%p.\n", cmd); 1436 goto eh_reset_failed; 1437 } 1438 err = 3; 1439 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1440 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1441 ql_log(ql_log_warn, vha, 0x800d, 1442 "wait for pending cmds failed for cmd=%p.\n", cmd); 1443 goto eh_reset_failed; 1444 } 1445 1446 ql_log(ql_log_info, vha, 0x800e, 1447 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1448 vha->host_no, sdev->id, sdev->lun, cmd); 1449 1450 return SUCCESS; 1451 1452 eh_reset_failed: 1453 ql_log(ql_log_info, vha, 0x800f, 1454 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1455 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1456 cmd); 1457 vha->reset_cmd_err_cnt++; 1458 return FAILED; 1459 } 1460 1461 static int 1462 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1463 { 1464 struct scsi_device *sdev = cmd->device; 1465 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1466 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1467 struct qla_hw_data *ha = vha->hw; 1468 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1469 int err; 1470 1471 if (qla2x00_isp_reg_stat(ha)) { 1472 ql_log(ql_log_info, vha, 0x803f, 1473 "PCI/Register disconnect, exiting.\n"); 1474 qla_pci_set_eeh_busy(vha); 1475 return FAILED; 1476 } 1477 1478 if (!fcport) { 1479 return FAILED; 1480 } 1481 1482 err = fc_block_rport(rport); 1483 if (err != 0) 1484 return err; 1485 1486 if (fcport->deleted) 1487 return SUCCESS; 1488 1489 ql_log(ql_log_info, vha, 0x8009, 1490 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1491 sdev->id, cmd); 1492 1493 err = 0; 1494 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1495 ql_log(ql_log_warn, vha, 0x800a, 1496 "Wait for hba online failed for cmd=%p.\n", cmd); 1497 goto eh_reset_failed; 1498 } 1499 err = 2; 1500 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1501 ql_log(ql_log_warn, vha, 0x800c, 1502 "target_reset failed for cmd=%p.\n", cmd); 1503 goto eh_reset_failed; 1504 } 1505 err = 3; 1506 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1507 0, WAIT_TARGET) != QLA_SUCCESS) { 1508 ql_log(ql_log_warn, vha, 0x800d, 1509 "wait for pending cmds failed for cmd=%p.\n", cmd); 1510 goto eh_reset_failed; 1511 } 1512 1513 ql_log(ql_log_info, vha, 0x800e, 1514 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1515 vha->host_no, sdev->id, cmd); 1516 1517 return SUCCESS; 1518 1519 eh_reset_failed: 1520 ql_log(ql_log_info, vha, 0x800f, 1521 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1522 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1523 cmd); 1524 vha->reset_cmd_err_cnt++; 1525 return FAILED; 1526 } 1527 1528 /************************************************************************** 1529 * qla2xxx_eh_bus_reset 1530 * 1531 * Description: 1532 * The bus reset function will reset the bus and abort any executing 1533 * commands. 1534 * 1535 * Input: 1536 * cmd = Linux SCSI command packet of the command that cause the 1537 * bus reset. 1538 * 1539 * Returns: 1540 * SUCCESS/FAILURE (defined as macro in scsi.h). 1541 * 1542 **************************************************************************/ 1543 static int 1544 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1545 { 1546 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1547 int ret = FAILED; 1548 unsigned int id; 1549 uint64_t lun; 1550 struct qla_hw_data *ha = vha->hw; 1551 1552 if (qla2x00_isp_reg_stat(ha)) { 1553 ql_log(ql_log_info, vha, 0x8040, 1554 "PCI/Register disconnect, exiting.\n"); 1555 qla_pci_set_eeh_busy(vha); 1556 return FAILED; 1557 } 1558 1559 id = cmd->device->id; 1560 lun = cmd->device->lun; 1561 1562 if (qla2x00_chip_is_down(vha)) 1563 return ret; 1564 1565 ql_log(ql_log_info, vha, 0x8012, 1566 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1567 1568 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1569 ql_log(ql_log_fatal, vha, 0x8013, 1570 "Wait for hba online failed board disabled.\n"); 1571 goto eh_bus_reset_done; 1572 } 1573 1574 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1575 ret = SUCCESS; 1576 1577 if (ret == FAILED) 1578 goto eh_bus_reset_done; 1579 1580 /* Flush outstanding commands. */ 1581 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1582 QLA_SUCCESS) { 1583 ql_log(ql_log_warn, vha, 0x8014, 1584 "Wait for pending commands failed.\n"); 1585 ret = FAILED; 1586 } 1587 1588 eh_bus_reset_done: 1589 ql_log(ql_log_warn, vha, 0x802b, 1590 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1591 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1592 1593 return ret; 1594 } 1595 1596 /************************************************************************** 1597 * qla2xxx_eh_host_reset 1598 * 1599 * Description: 1600 * The reset function will reset the Adapter. 1601 * 1602 * Input: 1603 * cmd = Linux SCSI command packet of the command that cause the 1604 * adapter reset. 1605 * 1606 * Returns: 1607 * Either SUCCESS or FAILED. 1608 * 1609 * Note: 1610 **************************************************************************/ 1611 static int 1612 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1613 { 1614 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1615 struct qla_hw_data *ha = vha->hw; 1616 int ret = FAILED; 1617 unsigned int id; 1618 uint64_t lun; 1619 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1620 1621 if (qla2x00_isp_reg_stat(ha)) { 1622 ql_log(ql_log_info, vha, 0x8041, 1623 "PCI/Register disconnect, exiting.\n"); 1624 qla_pci_set_eeh_busy(vha); 1625 return SUCCESS; 1626 } 1627 1628 id = cmd->device->id; 1629 lun = cmd->device->lun; 1630 1631 ql_log(ql_log_info, vha, 0x8018, 1632 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1633 1634 /* 1635 * No point in issuing another reset if one is active. Also do not 1636 * attempt a reset if we are updating flash. 1637 */ 1638 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1639 goto eh_host_reset_lock; 1640 1641 if (vha != base_vha) { 1642 if (qla2x00_vp_abort_isp(vha)) 1643 goto eh_host_reset_lock; 1644 } else { 1645 if (IS_P3P_TYPE(vha->hw)) { 1646 if (!qla82xx_fcoe_ctx_reset(vha)) { 1647 /* Ctx reset success */ 1648 ret = SUCCESS; 1649 goto eh_host_reset_lock; 1650 } 1651 /* fall thru if ctx reset failed */ 1652 } 1653 if (ha->wq) 1654 flush_workqueue(ha->wq); 1655 1656 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1657 if (ha->isp_ops->abort_isp(base_vha)) { 1658 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1659 /* failed. schedule dpc to try */ 1660 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1661 1662 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1663 ql_log(ql_log_warn, vha, 0x802a, 1664 "wait for hba online failed.\n"); 1665 goto eh_host_reset_lock; 1666 } 1667 } 1668 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1669 } 1670 1671 /* Waiting for command to be returned to OS.*/ 1672 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1673 QLA_SUCCESS) 1674 ret = SUCCESS; 1675 1676 eh_host_reset_lock: 1677 ql_log(ql_log_info, vha, 0x8017, 1678 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1679 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1680 1681 return ret; 1682 } 1683 1684 /* 1685 * qla2x00_loop_reset 1686 * Issue loop reset. 1687 * 1688 * Input: 1689 * ha = adapter block pointer. 1690 * 1691 * Returns: 1692 * 0 = success 1693 */ 1694 int 1695 qla2x00_loop_reset(scsi_qla_host_t *vha) 1696 { 1697 int ret; 1698 struct fc_port *fcport; 1699 struct qla_hw_data *ha = vha->hw; 1700 1701 if (IS_QLAFX00(ha)) { 1702 return qlafx00_loop_reset(vha); 1703 } 1704 1705 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1706 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1707 if (fcport->port_type != FCT_TARGET) 1708 continue; 1709 1710 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1711 if (ret != QLA_SUCCESS) { 1712 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1713 "Bus Reset failed: Reset=%d " 1714 "d_id=%x.\n", ret, fcport->d_id.b24); 1715 } 1716 } 1717 } 1718 1719 1720 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1721 atomic_set(&vha->loop_state, LOOP_DOWN); 1722 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1723 qla2x00_mark_all_devices_lost(vha); 1724 ret = qla2x00_full_login_lip(vha); 1725 if (ret != QLA_SUCCESS) { 1726 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1727 "full_login_lip=%d.\n", ret); 1728 } 1729 } 1730 1731 if (ha->flags.enable_lip_reset) { 1732 ret = qla2x00_lip_reset(vha); 1733 if (ret != QLA_SUCCESS) 1734 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1735 "lip_reset failed (%d).\n", ret); 1736 } 1737 1738 /* Issue marker command only when we are going to start the I/O */ 1739 vha->marker_needed = 1; 1740 1741 return QLA_SUCCESS; 1742 } 1743 1744 /* 1745 * The caller must ensure that no completion interrupts will happen 1746 * while this function is in progress. 1747 */ 1748 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1749 unsigned long *flags) 1750 __releases(qp->qp_lock_ptr) 1751 __acquires(qp->qp_lock_ptr) 1752 { 1753 DECLARE_COMPLETION_ONSTACK(comp); 1754 scsi_qla_host_t *vha = qp->vha; 1755 struct qla_hw_data *ha = vha->hw; 1756 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1757 int rval; 1758 bool ret_cmd; 1759 uint32_t ratov_j; 1760 1761 lockdep_assert_held(qp->qp_lock_ptr); 1762 1763 if (qla2x00_chip_is_down(vha)) { 1764 sp->done(sp, res); 1765 return; 1766 } 1767 1768 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1769 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1770 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1771 !qla2x00_isp_reg_stat(ha))) { 1772 if (sp->comp) { 1773 sp->done(sp, res); 1774 return; 1775 } 1776 1777 sp->comp = ∁ 1778 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1779 1780 rval = ha->isp_ops->abort_command(sp); 1781 /* Wait for command completion. */ 1782 ret_cmd = false; 1783 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1784 ratov_j = msecs_to_jiffies(ratov_j); 1785 switch (rval) { 1786 case QLA_SUCCESS: 1787 if (wait_for_completion_timeout(&comp, ratov_j)) { 1788 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1789 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1790 __func__, ha->r_a_tov/10); 1791 ret_cmd = true; 1792 } 1793 /* else FW return SP to driver */ 1794 break; 1795 default: 1796 ret_cmd = true; 1797 break; 1798 } 1799 1800 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1801 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1802 sp->done(sp, res); 1803 } else { 1804 sp->done(sp, res); 1805 } 1806 } 1807 1808 /* 1809 * The caller must ensure that no completion interrupts will happen 1810 * while this function is in progress. 1811 */ 1812 static void 1813 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1814 { 1815 int cnt; 1816 unsigned long flags; 1817 srb_t *sp; 1818 scsi_qla_host_t *vha = qp->vha; 1819 struct qla_hw_data *ha = vha->hw; 1820 struct req_que *req; 1821 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1822 struct qla_tgt_cmd *cmd; 1823 1824 if (!ha->req_q_map) 1825 return; 1826 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1827 req = qp->req; 1828 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1829 sp = req->outstanding_cmds[cnt]; 1830 if (sp) { 1831 switch (sp->cmd_type) { 1832 case TYPE_SRB: 1833 qla2x00_abort_srb(qp, sp, res, &flags); 1834 break; 1835 case TYPE_TGT_CMD: 1836 if (!vha->hw->tgt.tgt_ops || !tgt || 1837 qla_ini_mode_enabled(vha)) { 1838 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1839 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1840 vha->dpc_flags); 1841 continue; 1842 } 1843 cmd = (struct qla_tgt_cmd *)sp; 1844 cmd->aborted = 1; 1845 break; 1846 case TYPE_TGT_TMCMD: 1847 /* Skip task management functions. */ 1848 break; 1849 default: 1850 break; 1851 } 1852 req->outstanding_cmds[cnt] = NULL; 1853 } 1854 } 1855 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1856 } 1857 1858 /* 1859 * The caller must ensure that no completion interrupts will happen 1860 * while this function is in progress. 1861 */ 1862 void 1863 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1864 { 1865 int que; 1866 struct qla_hw_data *ha = vha->hw; 1867 1868 /* Continue only if initialization complete. */ 1869 if (!ha->base_qpair) 1870 return; 1871 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1872 1873 if (!ha->queue_pair_map) 1874 return; 1875 for (que = 0; que < ha->max_qpairs; que++) { 1876 if (!ha->queue_pair_map[que]) 1877 continue; 1878 1879 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1880 } 1881 } 1882 1883 static int 1884 qla2xxx_slave_alloc(struct scsi_device *sdev) 1885 { 1886 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1887 1888 if (!rport || fc_remote_port_chkready(rport)) 1889 return -ENXIO; 1890 1891 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1892 1893 return 0; 1894 } 1895 1896 static int 1897 qla2xxx_slave_configure(struct scsi_device *sdev) 1898 { 1899 scsi_qla_host_t *vha = shost_priv(sdev->host); 1900 struct req_que *req = vha->req; 1901 1902 if (IS_T10_PI_CAPABLE(vha->hw)) 1903 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1904 1905 scsi_change_queue_depth(sdev, req->max_q_depth); 1906 return 0; 1907 } 1908 1909 static void 1910 qla2xxx_slave_destroy(struct scsi_device *sdev) 1911 { 1912 sdev->hostdata = NULL; 1913 } 1914 1915 /** 1916 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1917 * @ha: HA context 1918 * 1919 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1920 * supported addressing method. 1921 */ 1922 static void 1923 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1924 { 1925 /* Assume a 32bit DMA mask. */ 1926 ha->flags.enable_64bit_addressing = 0; 1927 1928 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1929 /* Any upper-dword bits set? */ 1930 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1931 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1932 /* Ok, a 64bit DMA mask is applicable. */ 1933 ha->flags.enable_64bit_addressing = 1; 1934 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1935 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1936 return; 1937 } 1938 } 1939 1940 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1941 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1942 } 1943 1944 static void 1945 qla2x00_enable_intrs(struct qla_hw_data *ha) 1946 { 1947 unsigned long flags = 0; 1948 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1949 1950 spin_lock_irqsave(&ha->hardware_lock, flags); 1951 ha->interrupts_on = 1; 1952 /* enable risc and host interrupts */ 1953 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1954 rd_reg_word(®->ictrl); 1955 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1956 1957 } 1958 1959 static void 1960 qla2x00_disable_intrs(struct qla_hw_data *ha) 1961 { 1962 unsigned long flags = 0; 1963 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1964 1965 spin_lock_irqsave(&ha->hardware_lock, flags); 1966 ha->interrupts_on = 0; 1967 /* disable risc and host interrupts */ 1968 wrt_reg_word(®->ictrl, 0); 1969 rd_reg_word(®->ictrl); 1970 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1971 } 1972 1973 static void 1974 qla24xx_enable_intrs(struct qla_hw_data *ha) 1975 { 1976 unsigned long flags = 0; 1977 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1978 1979 spin_lock_irqsave(&ha->hardware_lock, flags); 1980 ha->interrupts_on = 1; 1981 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1982 rd_reg_dword(®->ictrl); 1983 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1984 } 1985 1986 static void 1987 qla24xx_disable_intrs(struct qla_hw_data *ha) 1988 { 1989 unsigned long flags = 0; 1990 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1991 1992 if (IS_NOPOLLING_TYPE(ha)) 1993 return; 1994 spin_lock_irqsave(&ha->hardware_lock, flags); 1995 ha->interrupts_on = 0; 1996 wrt_reg_dword(®->ictrl, 0); 1997 rd_reg_dword(®->ictrl); 1998 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1999 } 2000 2001 static int 2002 qla2x00_iospace_config(struct qla_hw_data *ha) 2003 { 2004 resource_size_t pio; 2005 uint16_t msix; 2006 2007 if (pci_request_selected_regions(ha->pdev, ha->bars, 2008 QLA2XXX_DRIVER_NAME)) { 2009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2010 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2011 pci_name(ha->pdev)); 2012 goto iospace_error_exit; 2013 } 2014 if (!(ha->bars & 1)) 2015 goto skip_pio; 2016 2017 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2018 pio = pci_resource_start(ha->pdev, 0); 2019 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2020 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2021 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2022 "Invalid pci I/O region size (%s).\n", 2023 pci_name(ha->pdev)); 2024 pio = 0; 2025 } 2026 } else { 2027 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2028 "Region #0 no a PIO resource (%s).\n", 2029 pci_name(ha->pdev)); 2030 pio = 0; 2031 } 2032 ha->pio_address = pio; 2033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2034 "PIO address=%llu.\n", 2035 (unsigned long long)ha->pio_address); 2036 2037 skip_pio: 2038 /* Use MMIO operations for all accesses. */ 2039 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2040 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2041 "Region #1 not an MMIO resource (%s), aborting.\n", 2042 pci_name(ha->pdev)); 2043 goto iospace_error_exit; 2044 } 2045 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2047 "Invalid PCI mem region size (%s), aborting.\n", 2048 pci_name(ha->pdev)); 2049 goto iospace_error_exit; 2050 } 2051 2052 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2053 if (!ha->iobase) { 2054 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2055 "Cannot remap MMIO (%s), aborting.\n", 2056 pci_name(ha->pdev)); 2057 goto iospace_error_exit; 2058 } 2059 2060 /* Determine queue resources */ 2061 ha->max_req_queues = ha->max_rsp_queues = 1; 2062 ha->msix_count = QLA_BASE_VECTORS; 2063 2064 /* Check if FW supports MQ or not */ 2065 if (!(ha->fw_attributes & BIT_6)) 2066 goto mqiobase_exit; 2067 2068 if (!ql2xmqsupport || !ql2xnvmeenable || 2069 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2070 goto mqiobase_exit; 2071 2072 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2073 pci_resource_len(ha->pdev, 3)); 2074 if (ha->mqiobase) { 2075 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2076 "MQIO Base=%p.\n", ha->mqiobase); 2077 /* Read MSIX vector size of the board */ 2078 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2079 ha->msix_count = msix + 1; 2080 /* Max queues are bounded by available msix vectors */ 2081 /* MB interrupt uses 1 vector */ 2082 ha->max_req_queues = ha->msix_count - 1; 2083 ha->max_rsp_queues = ha->max_req_queues; 2084 /* Queue pairs is the max value minus the base queue pair */ 2085 ha->max_qpairs = ha->max_rsp_queues - 1; 2086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2087 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2088 2089 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2090 "MSI-X vector count: %d.\n", ha->msix_count); 2091 } else 2092 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2093 "BAR 3 not enabled.\n"); 2094 2095 mqiobase_exit: 2096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2097 "MSIX Count: %d.\n", ha->msix_count); 2098 return (0); 2099 2100 iospace_error_exit: 2101 return (-ENOMEM); 2102 } 2103 2104 2105 static int 2106 qla83xx_iospace_config(struct qla_hw_data *ha) 2107 { 2108 uint16_t msix; 2109 2110 if (pci_request_selected_regions(ha->pdev, ha->bars, 2111 QLA2XXX_DRIVER_NAME)) { 2112 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2113 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2114 pci_name(ha->pdev)); 2115 2116 goto iospace_error_exit; 2117 } 2118 2119 /* Use MMIO operations for all accesses. */ 2120 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2121 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2122 "Invalid pci I/O region size (%s).\n", 2123 pci_name(ha->pdev)); 2124 goto iospace_error_exit; 2125 } 2126 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2127 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2128 "Invalid PCI mem region size (%s), aborting\n", 2129 pci_name(ha->pdev)); 2130 goto iospace_error_exit; 2131 } 2132 2133 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2134 if (!ha->iobase) { 2135 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2136 "Cannot remap MMIO (%s), aborting.\n", 2137 pci_name(ha->pdev)); 2138 goto iospace_error_exit; 2139 } 2140 2141 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2142 /* 83XX 26XX always use MQ type access for queues 2143 * - mbar 2, a.k.a region 4 */ 2144 ha->max_req_queues = ha->max_rsp_queues = 1; 2145 ha->msix_count = QLA_BASE_VECTORS; 2146 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2147 pci_resource_len(ha->pdev, 4)); 2148 2149 if (!ha->mqiobase) { 2150 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2151 "BAR2/region4 not enabled\n"); 2152 goto mqiobase_exit; 2153 } 2154 2155 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2156 pci_resource_len(ha->pdev, 2)); 2157 if (ha->msixbase) { 2158 /* Read MSIX vector size of the board */ 2159 pci_read_config_word(ha->pdev, 2160 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2161 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2162 /* 2163 * By default, driver uses at least two msix vectors 2164 * (default & rspq) 2165 */ 2166 if (ql2xmqsupport || ql2xnvmeenable) { 2167 /* MB interrupt uses 1 vector */ 2168 ha->max_req_queues = ha->msix_count - 1; 2169 2170 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2171 if (QLA_TGT_MODE_ENABLED()) 2172 ha->max_req_queues--; 2173 2174 ha->max_rsp_queues = ha->max_req_queues; 2175 2176 /* Queue pairs is the max value minus 2177 * the base queue pair */ 2178 ha->max_qpairs = ha->max_req_queues - 1; 2179 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2180 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2181 } 2182 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2183 "MSI-X vector count: %d.\n", ha->msix_count); 2184 } else 2185 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2186 "BAR 1 not enabled.\n"); 2187 2188 mqiobase_exit: 2189 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2190 "MSIX Count: %d.\n", ha->msix_count); 2191 return 0; 2192 2193 iospace_error_exit: 2194 return -ENOMEM; 2195 } 2196 2197 static struct isp_operations qla2100_isp_ops = { 2198 .pci_config = qla2100_pci_config, 2199 .reset_chip = qla2x00_reset_chip, 2200 .chip_diag = qla2x00_chip_diag, 2201 .config_rings = qla2x00_config_rings, 2202 .reset_adapter = qla2x00_reset_adapter, 2203 .nvram_config = qla2x00_nvram_config, 2204 .update_fw_options = qla2x00_update_fw_options, 2205 .load_risc = qla2x00_load_risc, 2206 .pci_info_str = qla2x00_pci_info_str, 2207 .fw_version_str = qla2x00_fw_version_str, 2208 .intr_handler = qla2100_intr_handler, 2209 .enable_intrs = qla2x00_enable_intrs, 2210 .disable_intrs = qla2x00_disable_intrs, 2211 .abort_command = qla2x00_abort_command, 2212 .target_reset = qla2x00_abort_target, 2213 .lun_reset = qla2x00_lun_reset, 2214 .fabric_login = qla2x00_login_fabric, 2215 .fabric_logout = qla2x00_fabric_logout, 2216 .calc_req_entries = qla2x00_calc_iocbs_32, 2217 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2218 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2219 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2220 .read_nvram = qla2x00_read_nvram_data, 2221 .write_nvram = qla2x00_write_nvram_data, 2222 .fw_dump = qla2100_fw_dump, 2223 .beacon_on = NULL, 2224 .beacon_off = NULL, 2225 .beacon_blink = NULL, 2226 .read_optrom = qla2x00_read_optrom_data, 2227 .write_optrom = qla2x00_write_optrom_data, 2228 .get_flash_version = qla2x00_get_flash_version, 2229 .start_scsi = qla2x00_start_scsi, 2230 .start_scsi_mq = NULL, 2231 .abort_isp = qla2x00_abort_isp, 2232 .iospace_config = qla2x00_iospace_config, 2233 .initialize_adapter = qla2x00_initialize_adapter, 2234 }; 2235 2236 static struct isp_operations qla2300_isp_ops = { 2237 .pci_config = qla2300_pci_config, 2238 .reset_chip = qla2x00_reset_chip, 2239 .chip_diag = qla2x00_chip_diag, 2240 .config_rings = qla2x00_config_rings, 2241 .reset_adapter = qla2x00_reset_adapter, 2242 .nvram_config = qla2x00_nvram_config, 2243 .update_fw_options = qla2x00_update_fw_options, 2244 .load_risc = qla2x00_load_risc, 2245 .pci_info_str = qla2x00_pci_info_str, 2246 .fw_version_str = qla2x00_fw_version_str, 2247 .intr_handler = qla2300_intr_handler, 2248 .enable_intrs = qla2x00_enable_intrs, 2249 .disable_intrs = qla2x00_disable_intrs, 2250 .abort_command = qla2x00_abort_command, 2251 .target_reset = qla2x00_abort_target, 2252 .lun_reset = qla2x00_lun_reset, 2253 .fabric_login = qla2x00_login_fabric, 2254 .fabric_logout = qla2x00_fabric_logout, 2255 .calc_req_entries = qla2x00_calc_iocbs_32, 2256 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2257 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2258 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2259 .read_nvram = qla2x00_read_nvram_data, 2260 .write_nvram = qla2x00_write_nvram_data, 2261 .fw_dump = qla2300_fw_dump, 2262 .beacon_on = qla2x00_beacon_on, 2263 .beacon_off = qla2x00_beacon_off, 2264 .beacon_blink = qla2x00_beacon_blink, 2265 .read_optrom = qla2x00_read_optrom_data, 2266 .write_optrom = qla2x00_write_optrom_data, 2267 .get_flash_version = qla2x00_get_flash_version, 2268 .start_scsi = qla2x00_start_scsi, 2269 .start_scsi_mq = NULL, 2270 .abort_isp = qla2x00_abort_isp, 2271 .iospace_config = qla2x00_iospace_config, 2272 .initialize_adapter = qla2x00_initialize_adapter, 2273 }; 2274 2275 static struct isp_operations qla24xx_isp_ops = { 2276 .pci_config = qla24xx_pci_config, 2277 .reset_chip = qla24xx_reset_chip, 2278 .chip_diag = qla24xx_chip_diag, 2279 .config_rings = qla24xx_config_rings, 2280 .reset_adapter = qla24xx_reset_adapter, 2281 .nvram_config = qla24xx_nvram_config, 2282 .update_fw_options = qla24xx_update_fw_options, 2283 .load_risc = qla24xx_load_risc, 2284 .pci_info_str = qla24xx_pci_info_str, 2285 .fw_version_str = qla24xx_fw_version_str, 2286 .intr_handler = qla24xx_intr_handler, 2287 .enable_intrs = qla24xx_enable_intrs, 2288 .disable_intrs = qla24xx_disable_intrs, 2289 .abort_command = qla24xx_abort_command, 2290 .target_reset = qla24xx_abort_target, 2291 .lun_reset = qla24xx_lun_reset, 2292 .fabric_login = qla24xx_login_fabric, 2293 .fabric_logout = qla24xx_fabric_logout, 2294 .calc_req_entries = NULL, 2295 .build_iocbs = NULL, 2296 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2297 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2298 .read_nvram = qla24xx_read_nvram_data, 2299 .write_nvram = qla24xx_write_nvram_data, 2300 .fw_dump = qla24xx_fw_dump, 2301 .beacon_on = qla24xx_beacon_on, 2302 .beacon_off = qla24xx_beacon_off, 2303 .beacon_blink = qla24xx_beacon_blink, 2304 .read_optrom = qla24xx_read_optrom_data, 2305 .write_optrom = qla24xx_write_optrom_data, 2306 .get_flash_version = qla24xx_get_flash_version, 2307 .start_scsi = qla24xx_start_scsi, 2308 .start_scsi_mq = NULL, 2309 .abort_isp = qla2x00_abort_isp, 2310 .iospace_config = qla2x00_iospace_config, 2311 .initialize_adapter = qla2x00_initialize_adapter, 2312 }; 2313 2314 static struct isp_operations qla25xx_isp_ops = { 2315 .pci_config = qla25xx_pci_config, 2316 .reset_chip = qla24xx_reset_chip, 2317 .chip_diag = qla24xx_chip_diag, 2318 .config_rings = qla24xx_config_rings, 2319 .reset_adapter = qla24xx_reset_adapter, 2320 .nvram_config = qla24xx_nvram_config, 2321 .update_fw_options = qla24xx_update_fw_options, 2322 .load_risc = qla24xx_load_risc, 2323 .pci_info_str = qla24xx_pci_info_str, 2324 .fw_version_str = qla24xx_fw_version_str, 2325 .intr_handler = qla24xx_intr_handler, 2326 .enable_intrs = qla24xx_enable_intrs, 2327 .disable_intrs = qla24xx_disable_intrs, 2328 .abort_command = qla24xx_abort_command, 2329 .target_reset = qla24xx_abort_target, 2330 .lun_reset = qla24xx_lun_reset, 2331 .fabric_login = qla24xx_login_fabric, 2332 .fabric_logout = qla24xx_fabric_logout, 2333 .calc_req_entries = NULL, 2334 .build_iocbs = NULL, 2335 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2336 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2337 .read_nvram = qla25xx_read_nvram_data, 2338 .write_nvram = qla25xx_write_nvram_data, 2339 .fw_dump = qla25xx_fw_dump, 2340 .beacon_on = qla24xx_beacon_on, 2341 .beacon_off = qla24xx_beacon_off, 2342 .beacon_blink = qla24xx_beacon_blink, 2343 .read_optrom = qla25xx_read_optrom_data, 2344 .write_optrom = qla24xx_write_optrom_data, 2345 .get_flash_version = qla24xx_get_flash_version, 2346 .start_scsi = qla24xx_dif_start_scsi, 2347 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2348 .abort_isp = qla2x00_abort_isp, 2349 .iospace_config = qla2x00_iospace_config, 2350 .initialize_adapter = qla2x00_initialize_adapter, 2351 }; 2352 2353 static struct isp_operations qla81xx_isp_ops = { 2354 .pci_config = qla25xx_pci_config, 2355 .reset_chip = qla24xx_reset_chip, 2356 .chip_diag = qla24xx_chip_diag, 2357 .config_rings = qla24xx_config_rings, 2358 .reset_adapter = qla24xx_reset_adapter, 2359 .nvram_config = qla81xx_nvram_config, 2360 .update_fw_options = qla24xx_update_fw_options, 2361 .load_risc = qla81xx_load_risc, 2362 .pci_info_str = qla24xx_pci_info_str, 2363 .fw_version_str = qla24xx_fw_version_str, 2364 .intr_handler = qla24xx_intr_handler, 2365 .enable_intrs = qla24xx_enable_intrs, 2366 .disable_intrs = qla24xx_disable_intrs, 2367 .abort_command = qla24xx_abort_command, 2368 .target_reset = qla24xx_abort_target, 2369 .lun_reset = qla24xx_lun_reset, 2370 .fabric_login = qla24xx_login_fabric, 2371 .fabric_logout = qla24xx_fabric_logout, 2372 .calc_req_entries = NULL, 2373 .build_iocbs = NULL, 2374 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2375 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2376 .read_nvram = NULL, 2377 .write_nvram = NULL, 2378 .fw_dump = qla81xx_fw_dump, 2379 .beacon_on = qla24xx_beacon_on, 2380 .beacon_off = qla24xx_beacon_off, 2381 .beacon_blink = qla83xx_beacon_blink, 2382 .read_optrom = qla25xx_read_optrom_data, 2383 .write_optrom = qla24xx_write_optrom_data, 2384 .get_flash_version = qla24xx_get_flash_version, 2385 .start_scsi = qla24xx_dif_start_scsi, 2386 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2387 .abort_isp = qla2x00_abort_isp, 2388 .iospace_config = qla2x00_iospace_config, 2389 .initialize_adapter = qla2x00_initialize_adapter, 2390 }; 2391 2392 static struct isp_operations qla82xx_isp_ops = { 2393 .pci_config = qla82xx_pci_config, 2394 .reset_chip = qla82xx_reset_chip, 2395 .chip_diag = qla24xx_chip_diag, 2396 .config_rings = qla82xx_config_rings, 2397 .reset_adapter = qla24xx_reset_adapter, 2398 .nvram_config = qla81xx_nvram_config, 2399 .update_fw_options = qla24xx_update_fw_options, 2400 .load_risc = qla82xx_load_risc, 2401 .pci_info_str = qla24xx_pci_info_str, 2402 .fw_version_str = qla24xx_fw_version_str, 2403 .intr_handler = qla82xx_intr_handler, 2404 .enable_intrs = qla82xx_enable_intrs, 2405 .disable_intrs = qla82xx_disable_intrs, 2406 .abort_command = qla24xx_abort_command, 2407 .target_reset = qla24xx_abort_target, 2408 .lun_reset = qla24xx_lun_reset, 2409 .fabric_login = qla24xx_login_fabric, 2410 .fabric_logout = qla24xx_fabric_logout, 2411 .calc_req_entries = NULL, 2412 .build_iocbs = NULL, 2413 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2414 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2415 .read_nvram = qla24xx_read_nvram_data, 2416 .write_nvram = qla24xx_write_nvram_data, 2417 .fw_dump = qla82xx_fw_dump, 2418 .beacon_on = qla82xx_beacon_on, 2419 .beacon_off = qla82xx_beacon_off, 2420 .beacon_blink = NULL, 2421 .read_optrom = qla82xx_read_optrom_data, 2422 .write_optrom = qla82xx_write_optrom_data, 2423 .get_flash_version = qla82xx_get_flash_version, 2424 .start_scsi = qla82xx_start_scsi, 2425 .start_scsi_mq = NULL, 2426 .abort_isp = qla82xx_abort_isp, 2427 .iospace_config = qla82xx_iospace_config, 2428 .initialize_adapter = qla2x00_initialize_adapter, 2429 }; 2430 2431 static struct isp_operations qla8044_isp_ops = { 2432 .pci_config = qla82xx_pci_config, 2433 .reset_chip = qla82xx_reset_chip, 2434 .chip_diag = qla24xx_chip_diag, 2435 .config_rings = qla82xx_config_rings, 2436 .reset_adapter = qla24xx_reset_adapter, 2437 .nvram_config = qla81xx_nvram_config, 2438 .update_fw_options = qla24xx_update_fw_options, 2439 .load_risc = qla82xx_load_risc, 2440 .pci_info_str = qla24xx_pci_info_str, 2441 .fw_version_str = qla24xx_fw_version_str, 2442 .intr_handler = qla8044_intr_handler, 2443 .enable_intrs = qla82xx_enable_intrs, 2444 .disable_intrs = qla82xx_disable_intrs, 2445 .abort_command = qla24xx_abort_command, 2446 .target_reset = qla24xx_abort_target, 2447 .lun_reset = qla24xx_lun_reset, 2448 .fabric_login = qla24xx_login_fabric, 2449 .fabric_logout = qla24xx_fabric_logout, 2450 .calc_req_entries = NULL, 2451 .build_iocbs = NULL, 2452 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2453 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2454 .read_nvram = NULL, 2455 .write_nvram = NULL, 2456 .fw_dump = qla8044_fw_dump, 2457 .beacon_on = qla82xx_beacon_on, 2458 .beacon_off = qla82xx_beacon_off, 2459 .beacon_blink = NULL, 2460 .read_optrom = qla8044_read_optrom_data, 2461 .write_optrom = qla8044_write_optrom_data, 2462 .get_flash_version = qla82xx_get_flash_version, 2463 .start_scsi = qla82xx_start_scsi, 2464 .start_scsi_mq = NULL, 2465 .abort_isp = qla8044_abort_isp, 2466 .iospace_config = qla82xx_iospace_config, 2467 .initialize_adapter = qla2x00_initialize_adapter, 2468 }; 2469 2470 static struct isp_operations qla83xx_isp_ops = { 2471 .pci_config = qla25xx_pci_config, 2472 .reset_chip = qla24xx_reset_chip, 2473 .chip_diag = qla24xx_chip_diag, 2474 .config_rings = qla24xx_config_rings, 2475 .reset_adapter = qla24xx_reset_adapter, 2476 .nvram_config = qla81xx_nvram_config, 2477 .update_fw_options = qla24xx_update_fw_options, 2478 .load_risc = qla81xx_load_risc, 2479 .pci_info_str = qla24xx_pci_info_str, 2480 .fw_version_str = qla24xx_fw_version_str, 2481 .intr_handler = qla24xx_intr_handler, 2482 .enable_intrs = qla24xx_enable_intrs, 2483 .disable_intrs = qla24xx_disable_intrs, 2484 .abort_command = qla24xx_abort_command, 2485 .target_reset = qla24xx_abort_target, 2486 .lun_reset = qla24xx_lun_reset, 2487 .fabric_login = qla24xx_login_fabric, 2488 .fabric_logout = qla24xx_fabric_logout, 2489 .calc_req_entries = NULL, 2490 .build_iocbs = NULL, 2491 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2492 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2493 .read_nvram = NULL, 2494 .write_nvram = NULL, 2495 .fw_dump = qla83xx_fw_dump, 2496 .beacon_on = qla24xx_beacon_on, 2497 .beacon_off = qla24xx_beacon_off, 2498 .beacon_blink = qla83xx_beacon_blink, 2499 .read_optrom = qla25xx_read_optrom_data, 2500 .write_optrom = qla24xx_write_optrom_data, 2501 .get_flash_version = qla24xx_get_flash_version, 2502 .start_scsi = qla24xx_dif_start_scsi, 2503 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2504 .abort_isp = qla2x00_abort_isp, 2505 .iospace_config = qla83xx_iospace_config, 2506 .initialize_adapter = qla2x00_initialize_adapter, 2507 }; 2508 2509 static struct isp_operations qlafx00_isp_ops = { 2510 .pci_config = qlafx00_pci_config, 2511 .reset_chip = qlafx00_soft_reset, 2512 .chip_diag = qlafx00_chip_diag, 2513 .config_rings = qlafx00_config_rings, 2514 .reset_adapter = qlafx00_soft_reset, 2515 .nvram_config = NULL, 2516 .update_fw_options = NULL, 2517 .load_risc = NULL, 2518 .pci_info_str = qlafx00_pci_info_str, 2519 .fw_version_str = qlafx00_fw_version_str, 2520 .intr_handler = qlafx00_intr_handler, 2521 .enable_intrs = qlafx00_enable_intrs, 2522 .disable_intrs = qlafx00_disable_intrs, 2523 .abort_command = qla24xx_async_abort_command, 2524 .target_reset = qlafx00_abort_target, 2525 .lun_reset = qlafx00_lun_reset, 2526 .fabric_login = NULL, 2527 .fabric_logout = NULL, 2528 .calc_req_entries = NULL, 2529 .build_iocbs = NULL, 2530 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2531 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2532 .read_nvram = qla24xx_read_nvram_data, 2533 .write_nvram = qla24xx_write_nvram_data, 2534 .fw_dump = NULL, 2535 .beacon_on = qla24xx_beacon_on, 2536 .beacon_off = qla24xx_beacon_off, 2537 .beacon_blink = NULL, 2538 .read_optrom = qla24xx_read_optrom_data, 2539 .write_optrom = qla24xx_write_optrom_data, 2540 .get_flash_version = qla24xx_get_flash_version, 2541 .start_scsi = qlafx00_start_scsi, 2542 .start_scsi_mq = NULL, 2543 .abort_isp = qlafx00_abort_isp, 2544 .iospace_config = qlafx00_iospace_config, 2545 .initialize_adapter = qlafx00_initialize_adapter, 2546 }; 2547 2548 static struct isp_operations qla27xx_isp_ops = { 2549 .pci_config = qla25xx_pci_config, 2550 .reset_chip = qla24xx_reset_chip, 2551 .chip_diag = qla24xx_chip_diag, 2552 .config_rings = qla24xx_config_rings, 2553 .reset_adapter = qla24xx_reset_adapter, 2554 .nvram_config = qla81xx_nvram_config, 2555 .update_fw_options = qla24xx_update_fw_options, 2556 .load_risc = qla81xx_load_risc, 2557 .pci_info_str = qla24xx_pci_info_str, 2558 .fw_version_str = qla24xx_fw_version_str, 2559 .intr_handler = qla24xx_intr_handler, 2560 .enable_intrs = qla24xx_enable_intrs, 2561 .disable_intrs = qla24xx_disable_intrs, 2562 .abort_command = qla24xx_abort_command, 2563 .target_reset = qla24xx_abort_target, 2564 .lun_reset = qla24xx_lun_reset, 2565 .fabric_login = qla24xx_login_fabric, 2566 .fabric_logout = qla24xx_fabric_logout, 2567 .calc_req_entries = NULL, 2568 .build_iocbs = NULL, 2569 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2570 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2571 .read_nvram = NULL, 2572 .write_nvram = NULL, 2573 .fw_dump = qla27xx_fwdump, 2574 .mpi_fw_dump = qla27xx_mpi_fwdump, 2575 .beacon_on = qla24xx_beacon_on, 2576 .beacon_off = qla24xx_beacon_off, 2577 .beacon_blink = qla83xx_beacon_blink, 2578 .read_optrom = qla25xx_read_optrom_data, 2579 .write_optrom = qla24xx_write_optrom_data, 2580 .get_flash_version = qla24xx_get_flash_version, 2581 .start_scsi = qla24xx_dif_start_scsi, 2582 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2583 .abort_isp = qla2x00_abort_isp, 2584 .iospace_config = qla83xx_iospace_config, 2585 .initialize_adapter = qla2x00_initialize_adapter, 2586 }; 2587 2588 static inline void 2589 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2590 { 2591 ha->device_type = DT_EXTENDED_IDS; 2592 switch (ha->pdev->device) { 2593 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2594 ha->isp_type |= DT_ISP2100; 2595 ha->device_type &= ~DT_EXTENDED_IDS; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2599 ha->isp_type |= DT_ISP2200; 2600 ha->device_type &= ~DT_EXTENDED_IDS; 2601 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2602 break; 2603 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2604 ha->isp_type |= DT_ISP2300; 2605 ha->device_type |= DT_ZIO_SUPPORTED; 2606 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2607 break; 2608 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2609 ha->isp_type |= DT_ISP2312; 2610 ha->device_type |= DT_ZIO_SUPPORTED; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2614 ha->isp_type |= DT_ISP2322; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 if (ha->pdev->subsystem_vendor == 0x1028 && 2617 ha->pdev->subsystem_device == 0x0170) 2618 ha->device_type |= DT_OEM_001; 2619 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2620 break; 2621 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2622 ha->isp_type |= DT_ISP6312; 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2624 break; 2625 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2626 ha->isp_type |= DT_ISP6322; 2627 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2628 break; 2629 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2630 ha->isp_type |= DT_ISP2422; 2631 ha->device_type |= DT_ZIO_SUPPORTED; 2632 ha->device_type |= DT_FWI2; 2633 ha->device_type |= DT_IIDMA; 2634 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2635 break; 2636 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2637 ha->isp_type |= DT_ISP2432; 2638 ha->device_type |= DT_ZIO_SUPPORTED; 2639 ha->device_type |= DT_FWI2; 2640 ha->device_type |= DT_IIDMA; 2641 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2642 break; 2643 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2644 ha->isp_type |= DT_ISP8432; 2645 ha->device_type |= DT_ZIO_SUPPORTED; 2646 ha->device_type |= DT_FWI2; 2647 ha->device_type |= DT_IIDMA; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2651 ha->isp_type |= DT_ISP5422; 2652 ha->device_type |= DT_FWI2; 2653 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2654 break; 2655 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2656 ha->isp_type |= DT_ISP5432; 2657 ha->device_type |= DT_FWI2; 2658 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2659 break; 2660 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2661 ha->isp_type |= DT_ISP2532; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 ha->device_type |= DT_FWI2; 2664 ha->device_type |= DT_IIDMA; 2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2666 break; 2667 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2668 ha->isp_type |= DT_ISP8001; 2669 ha->device_type |= DT_ZIO_SUPPORTED; 2670 ha->device_type |= DT_FWI2; 2671 ha->device_type |= DT_IIDMA; 2672 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2673 break; 2674 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2675 ha->isp_type |= DT_ISP8021; 2676 ha->device_type |= DT_ZIO_SUPPORTED; 2677 ha->device_type |= DT_FWI2; 2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2679 /* Initialize 82XX ISP flags */ 2680 qla82xx_init_flags(ha); 2681 break; 2682 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2683 ha->isp_type |= DT_ISP8044; 2684 ha->device_type |= DT_ZIO_SUPPORTED; 2685 ha->device_type |= DT_FWI2; 2686 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2687 /* Initialize 82XX ISP flags */ 2688 qla82xx_init_flags(ha); 2689 break; 2690 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2691 ha->isp_type |= DT_ISP2031; 2692 ha->device_type |= DT_ZIO_SUPPORTED; 2693 ha->device_type |= DT_FWI2; 2694 ha->device_type |= DT_IIDMA; 2695 ha->device_type |= DT_T10_PI; 2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2697 break; 2698 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2699 ha->isp_type |= DT_ISP8031; 2700 ha->device_type |= DT_ZIO_SUPPORTED; 2701 ha->device_type |= DT_FWI2; 2702 ha->device_type |= DT_IIDMA; 2703 ha->device_type |= DT_T10_PI; 2704 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2705 break; 2706 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2707 ha->isp_type |= DT_ISPFX00; 2708 break; 2709 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2710 ha->isp_type |= DT_ISP2071; 2711 ha->device_type |= DT_ZIO_SUPPORTED; 2712 ha->device_type |= DT_FWI2; 2713 ha->device_type |= DT_IIDMA; 2714 ha->device_type |= DT_T10_PI; 2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2716 break; 2717 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2718 ha->isp_type |= DT_ISP2271; 2719 ha->device_type |= DT_ZIO_SUPPORTED; 2720 ha->device_type |= DT_FWI2; 2721 ha->device_type |= DT_IIDMA; 2722 ha->device_type |= DT_T10_PI; 2723 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2724 break; 2725 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2726 ha->isp_type |= DT_ISP2261; 2727 ha->device_type |= DT_ZIO_SUPPORTED; 2728 ha->device_type |= DT_FWI2; 2729 ha->device_type |= DT_IIDMA; 2730 ha->device_type |= DT_T10_PI; 2731 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2732 break; 2733 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2734 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2735 ha->isp_type |= DT_ISP2081; 2736 ha->device_type |= DT_ZIO_SUPPORTED; 2737 ha->device_type |= DT_FWI2; 2738 ha->device_type |= DT_IIDMA; 2739 ha->device_type |= DT_T10_PI; 2740 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2741 break; 2742 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2743 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2744 ha->isp_type |= DT_ISP2281; 2745 ha->device_type |= DT_ZIO_SUPPORTED; 2746 ha->device_type |= DT_FWI2; 2747 ha->device_type |= DT_IIDMA; 2748 ha->device_type |= DT_T10_PI; 2749 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2750 break; 2751 } 2752 2753 if (IS_QLA82XX(ha)) 2754 ha->port_no = ha->portnum & 1; 2755 else { 2756 /* Get adapter physical port no from interrupt pin register. */ 2757 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2758 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2759 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2760 ha->port_no--; 2761 else 2762 ha->port_no = !(ha->port_no & 1); 2763 } 2764 2765 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2766 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2767 ha->device_type, ha->port_no, ha->fw_srisc_address); 2768 } 2769 2770 static void 2771 qla2xxx_scan_start(struct Scsi_Host *shost) 2772 { 2773 scsi_qla_host_t *vha = shost_priv(shost); 2774 2775 if (vha->hw->flags.running_gold_fw) 2776 return; 2777 2778 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2779 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2780 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2781 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2782 } 2783 2784 static int 2785 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2786 { 2787 scsi_qla_host_t *vha = shost_priv(shost); 2788 2789 if (test_bit(UNLOADING, &vha->dpc_flags)) 2790 return 1; 2791 if (!vha->host) 2792 return 1; 2793 if (time > vha->hw->loop_reset_delay * HZ) 2794 return 1; 2795 2796 return atomic_read(&vha->loop_state) == LOOP_READY; 2797 } 2798 2799 static void qla_heartbeat_work_fn(struct work_struct *work) 2800 { 2801 struct qla_hw_data *ha = container_of(work, 2802 struct qla_hw_data, heartbeat_work); 2803 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2804 2805 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2806 qla_no_op_mb(base_vha); 2807 } 2808 2809 static void qla2x00_iocb_work_fn(struct work_struct *work) 2810 { 2811 struct scsi_qla_host *vha = container_of(work, 2812 struct scsi_qla_host, iocb_work); 2813 struct qla_hw_data *ha = vha->hw; 2814 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2815 int i = 2; 2816 unsigned long flags; 2817 2818 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2819 return; 2820 2821 while (!list_empty(&vha->work_list) && i > 0) { 2822 qla2x00_do_work(vha); 2823 i--; 2824 } 2825 2826 spin_lock_irqsave(&vha->work_lock, flags); 2827 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2828 spin_unlock_irqrestore(&vha->work_lock, flags); 2829 } 2830 2831 /* 2832 * PCI driver interface 2833 */ 2834 static int 2835 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2836 { 2837 int ret = -ENODEV; 2838 struct Scsi_Host *host; 2839 scsi_qla_host_t *base_vha = NULL; 2840 struct qla_hw_data *ha; 2841 char pci_info[30]; 2842 char fw_str[30], wq_name[30]; 2843 struct scsi_host_template *sht; 2844 int bars, mem_only = 0; 2845 uint16_t req_length = 0, rsp_length = 0; 2846 struct req_que *req = NULL; 2847 struct rsp_que *rsp = NULL; 2848 int i; 2849 2850 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2851 sht = &qla2xxx_driver_template; 2852 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2853 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2854 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2855 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2856 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2857 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2858 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2859 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2860 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2861 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2862 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2863 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2864 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2865 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2866 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2867 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2868 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2869 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2870 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2871 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2872 mem_only = 1; 2873 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2874 "Mem only adapter.\n"); 2875 } 2876 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2877 "Bars=%d.\n", bars); 2878 2879 if (mem_only) { 2880 if (pci_enable_device_mem(pdev)) 2881 return ret; 2882 } else { 2883 if (pci_enable_device(pdev)) 2884 return ret; 2885 } 2886 2887 if (is_kdump_kernel()) { 2888 ql2xmqsupport = 0; 2889 ql2xallocfwdump = 0; 2890 } 2891 2892 /* This may fail but that's ok */ 2893 pci_enable_pcie_error_reporting(pdev); 2894 2895 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2896 if (!ha) { 2897 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2898 "Unable to allocate memory for ha.\n"); 2899 goto disable_device; 2900 } 2901 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2902 "Memory allocated for ha=%p.\n", ha); 2903 ha->pdev = pdev; 2904 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2905 spin_lock_init(&ha->tgt.q_full_lock); 2906 spin_lock_init(&ha->tgt.sess_lock); 2907 spin_lock_init(&ha->tgt.atio_lock); 2908 2909 spin_lock_init(&ha->sadb_lock); 2910 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2911 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2912 2913 spin_lock_init(&ha->sadb_fp_lock); 2914 2915 if (qla_edif_sadb_build_free_pool(ha)) { 2916 kfree(ha); 2917 goto disable_device; 2918 } 2919 2920 atomic_set(&ha->nvme_active_aen_cnt, 0); 2921 2922 /* Clear our data area */ 2923 ha->bars = bars; 2924 ha->mem_only = mem_only; 2925 spin_lock_init(&ha->hardware_lock); 2926 spin_lock_init(&ha->vport_slock); 2927 mutex_init(&ha->selflogin_lock); 2928 mutex_init(&ha->optrom_mutex); 2929 2930 /* Set ISP-type information. */ 2931 qla2x00_set_isp_flags(ha); 2932 2933 /* Set EEH reset type to fundamental if required by hba */ 2934 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2935 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2936 pdev->needs_freset = 1; 2937 2938 ha->prev_topology = 0; 2939 ha->init_cb_size = sizeof(init_cb_t); 2940 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2941 ha->optrom_size = OPTROM_SIZE_2300; 2942 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2943 atomic_set(&ha->num_pend_mbx_stage1, 0); 2944 atomic_set(&ha->num_pend_mbx_stage2, 0); 2945 atomic_set(&ha->num_pend_mbx_stage3, 0); 2946 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2947 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2948 2949 /* Assign ISP specific operations. */ 2950 if (IS_QLA2100(ha)) { 2951 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2952 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2953 req_length = REQUEST_ENTRY_CNT_2100; 2954 rsp_length = RESPONSE_ENTRY_CNT_2100; 2955 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2956 ha->gid_list_info_size = 4; 2957 ha->flash_conf_off = ~0; 2958 ha->flash_data_off = ~0; 2959 ha->nvram_conf_off = ~0; 2960 ha->nvram_data_off = ~0; 2961 ha->isp_ops = &qla2100_isp_ops; 2962 } else if (IS_QLA2200(ha)) { 2963 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2964 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2965 req_length = REQUEST_ENTRY_CNT_2200; 2966 rsp_length = RESPONSE_ENTRY_CNT_2100; 2967 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2968 ha->gid_list_info_size = 4; 2969 ha->flash_conf_off = ~0; 2970 ha->flash_data_off = ~0; 2971 ha->nvram_conf_off = ~0; 2972 ha->nvram_data_off = ~0; 2973 ha->isp_ops = &qla2100_isp_ops; 2974 } else if (IS_QLA23XX(ha)) { 2975 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2976 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2977 req_length = REQUEST_ENTRY_CNT_2200; 2978 rsp_length = RESPONSE_ENTRY_CNT_2300; 2979 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2980 ha->gid_list_info_size = 6; 2981 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2982 ha->optrom_size = OPTROM_SIZE_2322; 2983 ha->flash_conf_off = ~0; 2984 ha->flash_data_off = ~0; 2985 ha->nvram_conf_off = ~0; 2986 ha->nvram_data_off = ~0; 2987 ha->isp_ops = &qla2300_isp_ops; 2988 } else if (IS_QLA24XX_TYPE(ha)) { 2989 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2990 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2991 req_length = REQUEST_ENTRY_CNT_24XX; 2992 rsp_length = RESPONSE_ENTRY_CNT_2300; 2993 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2994 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2995 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2996 ha->gid_list_info_size = 8; 2997 ha->optrom_size = OPTROM_SIZE_24XX; 2998 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2999 ha->isp_ops = &qla24xx_isp_ops; 3000 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3001 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3002 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3003 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3004 } else if (IS_QLA25XX(ha)) { 3005 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3006 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3007 req_length = REQUEST_ENTRY_CNT_24XX; 3008 rsp_length = RESPONSE_ENTRY_CNT_2300; 3009 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3010 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3011 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3012 ha->gid_list_info_size = 8; 3013 ha->optrom_size = OPTROM_SIZE_25XX; 3014 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3015 ha->isp_ops = &qla25xx_isp_ops; 3016 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3017 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3018 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3019 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3020 } else if (IS_QLA81XX(ha)) { 3021 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3022 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3023 req_length = REQUEST_ENTRY_CNT_24XX; 3024 rsp_length = RESPONSE_ENTRY_CNT_2300; 3025 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3026 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3027 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3028 ha->gid_list_info_size = 8; 3029 ha->optrom_size = OPTROM_SIZE_81XX; 3030 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3031 ha->isp_ops = &qla81xx_isp_ops; 3032 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3033 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3034 ha->nvram_conf_off = ~0; 3035 ha->nvram_data_off = ~0; 3036 } else if (IS_QLA82XX(ha)) { 3037 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3038 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3039 req_length = REQUEST_ENTRY_CNT_82XX; 3040 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3041 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3042 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3043 ha->gid_list_info_size = 8; 3044 ha->optrom_size = OPTROM_SIZE_82XX; 3045 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3046 ha->isp_ops = &qla82xx_isp_ops; 3047 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3048 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3049 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3050 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3051 } else if (IS_QLA8044(ha)) { 3052 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3053 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3054 req_length = REQUEST_ENTRY_CNT_82XX; 3055 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3056 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3057 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3058 ha->gid_list_info_size = 8; 3059 ha->optrom_size = OPTROM_SIZE_83XX; 3060 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3061 ha->isp_ops = &qla8044_isp_ops; 3062 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3063 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3064 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3065 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3066 } else if (IS_QLA83XX(ha)) { 3067 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3068 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3069 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3070 req_length = REQUEST_ENTRY_CNT_83XX; 3071 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3072 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3073 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3074 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3075 ha->gid_list_info_size = 8; 3076 ha->optrom_size = OPTROM_SIZE_83XX; 3077 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3078 ha->isp_ops = &qla83xx_isp_ops; 3079 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3080 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3081 ha->nvram_conf_off = ~0; 3082 ha->nvram_data_off = ~0; 3083 } else if (IS_QLAFX00(ha)) { 3084 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3085 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3086 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3087 req_length = REQUEST_ENTRY_CNT_FX00; 3088 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3089 ha->isp_ops = &qlafx00_isp_ops; 3090 ha->port_down_retry_count = 30; /* default value */ 3091 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3092 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3093 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3094 ha->mr.fw_hbt_en = 1; 3095 ha->mr.host_info_resend = false; 3096 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3097 } else if (IS_QLA27XX(ha)) { 3098 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3099 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3100 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3101 req_length = REQUEST_ENTRY_CNT_83XX; 3102 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3103 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3104 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3105 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3106 ha->gid_list_info_size = 8; 3107 ha->optrom_size = OPTROM_SIZE_83XX; 3108 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3109 ha->isp_ops = &qla27xx_isp_ops; 3110 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3111 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3112 ha->nvram_conf_off = ~0; 3113 ha->nvram_data_off = ~0; 3114 } else if (IS_QLA28XX(ha)) { 3115 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3116 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3117 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3118 req_length = REQUEST_ENTRY_CNT_83XX; 3119 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3120 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3121 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3122 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3123 ha->gid_list_info_size = 8; 3124 ha->optrom_size = OPTROM_SIZE_28XX; 3125 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3126 ha->isp_ops = &qla27xx_isp_ops; 3127 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3128 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3129 ha->nvram_conf_off = ~0; 3130 ha->nvram_data_off = ~0; 3131 } 3132 3133 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3134 "mbx_count=%d, req_length=%d, " 3135 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3136 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3137 "max_fibre_devices=%d.\n", 3138 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3139 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3140 ha->nvram_npiv_size, ha->max_fibre_devices); 3141 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3142 "isp_ops=%p, flash_conf_off=%d, " 3143 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3144 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3145 ha->nvram_conf_off, ha->nvram_data_off); 3146 3147 /* Configure PCI I/O space */ 3148 ret = ha->isp_ops->iospace_config(ha); 3149 if (ret) 3150 goto iospace_config_failed; 3151 3152 ql_log_pci(ql_log_info, pdev, 0x001d, 3153 "Found an ISP%04X irq %d iobase 0x%p.\n", 3154 pdev->device, pdev->irq, ha->iobase); 3155 mutex_init(&ha->vport_lock); 3156 mutex_init(&ha->mq_lock); 3157 init_completion(&ha->mbx_cmd_comp); 3158 complete(&ha->mbx_cmd_comp); 3159 init_completion(&ha->mbx_intr_comp); 3160 init_completion(&ha->dcbx_comp); 3161 init_completion(&ha->lb_portup_comp); 3162 3163 set_bit(0, (unsigned long *) ha->vp_idx_map); 3164 3165 qla2x00_config_dma_addressing(ha); 3166 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3167 "64 Bit addressing is %s.\n", 3168 ha->flags.enable_64bit_addressing ? "enable" : 3169 "disable"); 3170 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3171 if (ret) { 3172 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3173 "Failed to allocate memory for adapter, aborting.\n"); 3174 3175 goto probe_hw_failed; 3176 } 3177 3178 req->max_q_depth = MAX_Q_DEPTH; 3179 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3180 req->max_q_depth = ql2xmaxqdepth; 3181 3182 3183 base_vha = qla2x00_create_host(sht, ha); 3184 if (!base_vha) { 3185 ret = -ENOMEM; 3186 goto probe_hw_failed; 3187 } 3188 3189 pci_set_drvdata(pdev, base_vha); 3190 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3191 3192 host = base_vha->host; 3193 base_vha->req = req; 3194 if (IS_QLA2XXX_MIDTYPE(ha)) 3195 base_vha->mgmt_svr_loop_id = 3196 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3197 else 3198 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3199 base_vha->vp_idx; 3200 3201 /* Setup fcport template structure. */ 3202 ha->mr.fcport.vha = base_vha; 3203 ha->mr.fcport.port_type = FCT_UNKNOWN; 3204 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3205 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3206 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3207 ha->mr.fcport.scan_state = 1; 3208 3209 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3210 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3211 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3212 3213 /* Set the SG table size based on ISP type */ 3214 if (!IS_FWI2_CAPABLE(ha)) { 3215 if (IS_QLA2100(ha)) 3216 host->sg_tablesize = 32; 3217 } else { 3218 if (!IS_QLA82XX(ha)) 3219 host->sg_tablesize = QLA_SG_ALL; 3220 } 3221 host->max_id = ha->max_fibre_devices; 3222 host->cmd_per_lun = 3; 3223 host->unique_id = host->host_no; 3224 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3225 host->max_cmd_len = 32; 3226 else 3227 host->max_cmd_len = MAX_CMDSZ; 3228 host->max_channel = MAX_BUSES - 1; 3229 /* Older HBAs support only 16-bit LUNs */ 3230 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3231 ql2xmaxlun > 0xffff) 3232 host->max_lun = 0xffff; 3233 else 3234 host->max_lun = ql2xmaxlun; 3235 host->transportt = qla2xxx_transport_template; 3236 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3237 3238 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3239 "max_id=%d this_id=%d " 3240 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3241 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3242 host->this_id, host->cmd_per_lun, host->unique_id, 3243 host->max_cmd_len, host->max_channel, host->max_lun, 3244 host->transportt, sht->vendor_id); 3245 3246 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3247 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3248 3249 /* Set up the irqs */ 3250 ret = qla2x00_request_irqs(ha, rsp); 3251 if (ret) 3252 goto probe_failed; 3253 3254 /* Alloc arrays of request and response ring ptrs */ 3255 ret = qla2x00_alloc_queues(ha, req, rsp); 3256 if (ret) { 3257 ql_log(ql_log_fatal, base_vha, 0x003d, 3258 "Failed to allocate memory for queue pointers..." 3259 "aborting.\n"); 3260 ret = -ENODEV; 3261 goto probe_failed; 3262 } 3263 3264 if (ha->mqenable) { 3265 /* number of hardware queues supported by blk/scsi-mq*/ 3266 host->nr_hw_queues = ha->max_qpairs; 3267 3268 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3269 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3270 } else { 3271 if (ql2xnvmeenable) { 3272 host->nr_hw_queues = ha->max_qpairs; 3273 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3274 "FC-NVMe support is enabled, HW queues=%d\n", 3275 host->nr_hw_queues); 3276 } else { 3277 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3278 "blk/scsi-mq disabled.\n"); 3279 } 3280 } 3281 3282 qlt_probe_one_stage1(base_vha, ha); 3283 3284 pci_save_state(pdev); 3285 3286 /* Assign back pointers */ 3287 rsp->req = req; 3288 req->rsp = rsp; 3289 3290 if (IS_QLAFX00(ha)) { 3291 ha->rsp_q_map[0] = rsp; 3292 ha->req_q_map[0] = req; 3293 set_bit(0, ha->req_qid_map); 3294 set_bit(0, ha->rsp_qid_map); 3295 } 3296 3297 /* FWI2-capable only. */ 3298 req->req_q_in = &ha->iobase->isp24.req_q_in; 3299 req->req_q_out = &ha->iobase->isp24.req_q_out; 3300 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3301 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3302 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3303 IS_QLA28XX(ha)) { 3304 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3305 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3306 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3307 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3308 } 3309 3310 if (IS_QLAFX00(ha)) { 3311 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3312 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3313 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3314 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3315 } 3316 3317 if (IS_P3P_TYPE(ha)) { 3318 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3319 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3320 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3321 } 3322 3323 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3324 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3325 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3326 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3327 "req->req_q_in=%p req->req_q_out=%p " 3328 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3329 req->req_q_in, req->req_q_out, 3330 rsp->rsp_q_in, rsp->rsp_q_out); 3331 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3332 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3333 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3334 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3335 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3336 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3337 3338 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3339 if (unlikely(!ha->wq)) { 3340 ret = -ENOMEM; 3341 goto probe_failed; 3342 } 3343 3344 if (ha->isp_ops->initialize_adapter(base_vha)) { 3345 ql_log(ql_log_fatal, base_vha, 0x00d6, 3346 "Failed to initialize adapter - Adapter flags %x.\n", 3347 base_vha->device_flags); 3348 3349 if (IS_QLA82XX(ha)) { 3350 qla82xx_idc_lock(ha); 3351 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3352 QLA8XXX_DEV_FAILED); 3353 qla82xx_idc_unlock(ha); 3354 ql_log(ql_log_fatal, base_vha, 0x00d7, 3355 "HW State: FAILED.\n"); 3356 } else if (IS_QLA8044(ha)) { 3357 qla8044_idc_lock(ha); 3358 qla8044_wr_direct(base_vha, 3359 QLA8044_CRB_DEV_STATE_INDEX, 3360 QLA8XXX_DEV_FAILED); 3361 qla8044_idc_unlock(ha); 3362 ql_log(ql_log_fatal, base_vha, 0x0150, 3363 "HW State: FAILED.\n"); 3364 } 3365 3366 ret = -ENODEV; 3367 goto probe_failed; 3368 } 3369 3370 if (IS_QLAFX00(ha)) 3371 host->can_queue = QLAFX00_MAX_CANQUEUE; 3372 else 3373 host->can_queue = req->num_outstanding_cmds - 10; 3374 3375 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3376 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3377 host->can_queue, base_vha->req, 3378 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3379 3380 /* Check if FW supports MQ or not for ISP25xx */ 3381 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3382 ha->mqenable = 0; 3383 3384 if (ha->mqenable) { 3385 bool startit = false; 3386 3387 if (QLA_TGT_MODE_ENABLED()) 3388 startit = false; 3389 3390 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3391 startit = true; 3392 3393 /* Create start of day qpairs for Block MQ */ 3394 for (i = 0; i < ha->max_qpairs; i++) 3395 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3396 } 3397 qla_init_iocb_limit(base_vha); 3398 3399 if (ha->flags.running_gold_fw) 3400 goto skip_dpc; 3401 3402 /* 3403 * Startup the kernel thread for this host adapter 3404 */ 3405 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3406 "%s_dpc", base_vha->host_str); 3407 if (IS_ERR(ha->dpc_thread)) { 3408 ql_log(ql_log_fatal, base_vha, 0x00ed, 3409 "Failed to start DPC thread.\n"); 3410 ret = PTR_ERR(ha->dpc_thread); 3411 ha->dpc_thread = NULL; 3412 goto probe_failed; 3413 } 3414 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3415 "DPC thread started successfully.\n"); 3416 3417 /* 3418 * If we're not coming up in initiator mode, we might sit for 3419 * a while without waking up the dpc thread, which leads to a 3420 * stuck process warning. So just kick the dpc once here and 3421 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3422 */ 3423 qla2xxx_wake_dpc(base_vha); 3424 3425 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3426 3427 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3428 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3429 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3430 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3431 3432 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3433 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3434 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3435 INIT_WORK(&ha->idc_state_handler, 3436 qla83xx_idc_state_handler_work); 3437 INIT_WORK(&ha->nic_core_unrecoverable, 3438 qla83xx_nic_core_unrecoverable_work); 3439 } 3440 3441 skip_dpc: 3442 list_add_tail(&base_vha->list, &ha->vp_list); 3443 base_vha->host->irq = ha->pdev->irq; 3444 3445 /* Initialized the timer */ 3446 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3447 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3448 "Started qla2x00_timer with " 3449 "interval=%d.\n", WATCH_INTERVAL); 3450 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3451 "Detected hba at address=%p.\n", 3452 ha); 3453 3454 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3455 if (ha->fw_attributes & BIT_4) { 3456 int prot = 0, guard; 3457 3458 base_vha->flags.difdix_supported = 1; 3459 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3460 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3461 if (ql2xenabledif == 1) 3462 prot = SHOST_DIX_TYPE0_PROTECTION; 3463 if (ql2xprotmask) 3464 scsi_host_set_prot(host, ql2xprotmask); 3465 else 3466 scsi_host_set_prot(host, 3467 prot | SHOST_DIF_TYPE1_PROTECTION 3468 | SHOST_DIF_TYPE2_PROTECTION 3469 | SHOST_DIF_TYPE3_PROTECTION 3470 | SHOST_DIX_TYPE1_PROTECTION 3471 | SHOST_DIX_TYPE2_PROTECTION 3472 | SHOST_DIX_TYPE3_PROTECTION); 3473 3474 guard = SHOST_DIX_GUARD_CRC; 3475 3476 if (IS_PI_IPGUARD_CAPABLE(ha) && 3477 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3478 guard |= SHOST_DIX_GUARD_IP; 3479 3480 if (ql2xprotguard) 3481 scsi_host_set_guard(host, ql2xprotguard); 3482 else 3483 scsi_host_set_guard(host, guard); 3484 } else 3485 base_vha->flags.difdix_supported = 0; 3486 } 3487 3488 ha->isp_ops->enable_intrs(ha); 3489 3490 if (IS_QLAFX00(ha)) { 3491 ret = qlafx00_fx_disc(base_vha, 3492 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3493 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3494 QLA_SG_ALL : 128; 3495 } 3496 3497 ret = scsi_add_host(host, &pdev->dev); 3498 if (ret) 3499 goto probe_failed; 3500 3501 base_vha->flags.init_done = 1; 3502 base_vha->flags.online = 1; 3503 ha->prev_minidump_failed = 0; 3504 3505 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3506 "Init done and hba is online.\n"); 3507 3508 if (qla_ini_mode_enabled(base_vha) || 3509 qla_dual_mode_enabled(base_vha)) 3510 scsi_scan_host(host); 3511 else 3512 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3513 "skipping scsi_scan_host() for non-initiator port\n"); 3514 3515 qla2x00_alloc_sysfs_attr(base_vha); 3516 3517 if (IS_QLAFX00(ha)) { 3518 ret = qlafx00_fx_disc(base_vha, 3519 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3520 3521 /* Register system information */ 3522 ret = qlafx00_fx_disc(base_vha, 3523 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3524 } 3525 3526 qla2x00_init_host_attr(base_vha); 3527 3528 qla2x00_dfs_setup(base_vha); 3529 3530 ql_log(ql_log_info, base_vha, 0x00fb, 3531 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3532 ql_log(ql_log_info, base_vha, 0x00fc, 3533 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3534 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3535 sizeof(pci_info)), 3536 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3537 base_vha->host_no, 3538 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3539 3540 qlt_add_target(ha, base_vha); 3541 3542 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3543 3544 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3545 return -ENODEV; 3546 3547 return 0; 3548 3549 probe_failed: 3550 qla_enode_stop(base_vha); 3551 qla_edb_stop(base_vha); 3552 if (base_vha->gnl.l) { 3553 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3554 base_vha->gnl.l, base_vha->gnl.ldma); 3555 base_vha->gnl.l = NULL; 3556 } 3557 3558 if (base_vha->timer_active) 3559 qla2x00_stop_timer(base_vha); 3560 base_vha->flags.online = 0; 3561 if (ha->dpc_thread) { 3562 struct task_struct *t = ha->dpc_thread; 3563 3564 ha->dpc_thread = NULL; 3565 kthread_stop(t); 3566 } 3567 3568 qla2x00_free_device(base_vha); 3569 scsi_host_put(base_vha->host); 3570 /* 3571 * Need to NULL out local req/rsp after 3572 * qla2x00_free_device => qla2x00_free_queues frees 3573 * what these are pointing to. Or else we'll 3574 * fall over below in qla2x00_free_req/rsp_que. 3575 */ 3576 req = NULL; 3577 rsp = NULL; 3578 3579 probe_hw_failed: 3580 qla2x00_mem_free(ha); 3581 qla2x00_free_req_que(ha, req); 3582 qla2x00_free_rsp_que(ha, rsp); 3583 qla2x00_clear_drv_active(ha); 3584 3585 iospace_config_failed: 3586 if (IS_P3P_TYPE(ha)) { 3587 if (!ha->nx_pcibase) 3588 iounmap((device_reg_t *)ha->nx_pcibase); 3589 if (!ql2xdbwr) 3590 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3591 } else { 3592 if (ha->iobase) 3593 iounmap(ha->iobase); 3594 if (ha->cregbase) 3595 iounmap(ha->cregbase); 3596 } 3597 pci_release_selected_regions(ha->pdev, ha->bars); 3598 kfree(ha); 3599 3600 disable_device: 3601 pci_disable_device(pdev); 3602 return ret; 3603 } 3604 3605 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3606 { 3607 scsi_qla_host_t *vp; 3608 unsigned long flags; 3609 struct qla_hw_data *ha; 3610 3611 if (!base_vha) 3612 return; 3613 3614 ha = base_vha->hw; 3615 3616 spin_lock_irqsave(&ha->vport_slock, flags); 3617 list_for_each_entry(vp, &ha->vp_list, list) 3618 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3619 3620 /* 3621 * Indicate device removal to prevent future board_disable 3622 * and wait until any pending board_disable has completed. 3623 */ 3624 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3625 spin_unlock_irqrestore(&ha->vport_slock, flags); 3626 } 3627 3628 static void 3629 qla2x00_shutdown(struct pci_dev *pdev) 3630 { 3631 scsi_qla_host_t *vha; 3632 struct qla_hw_data *ha; 3633 3634 vha = pci_get_drvdata(pdev); 3635 ha = vha->hw; 3636 3637 ql_log(ql_log_info, vha, 0xfffa, 3638 "Adapter shutdown\n"); 3639 3640 /* 3641 * Prevent future board_disable and wait 3642 * until any pending board_disable has completed. 3643 */ 3644 __qla_set_remove_flag(vha); 3645 cancel_work_sync(&ha->board_disable); 3646 3647 if (!atomic_read(&pdev->enable_cnt)) 3648 return; 3649 3650 /* Notify ISPFX00 firmware */ 3651 if (IS_QLAFX00(ha)) 3652 qlafx00_driver_shutdown(vha, 20); 3653 3654 /* Turn-off FCE trace */ 3655 if (ha->flags.fce_enabled) { 3656 qla2x00_disable_fce_trace(vha, NULL, NULL); 3657 ha->flags.fce_enabled = 0; 3658 } 3659 3660 /* Turn-off EFT trace */ 3661 if (ha->eft) 3662 qla2x00_disable_eft_trace(vha); 3663 3664 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3665 IS_QLA28XX(ha)) { 3666 if (ha->flags.fw_started) 3667 qla2x00_abort_isp_cleanup(vha); 3668 } else { 3669 /* Stop currently executing firmware. */ 3670 qla2x00_try_to_stop_firmware(vha); 3671 } 3672 3673 /* Disable timer */ 3674 if (vha->timer_active) 3675 qla2x00_stop_timer(vha); 3676 3677 /* Turn adapter off line */ 3678 vha->flags.online = 0; 3679 3680 /* turn-off interrupts on the card */ 3681 if (ha->interrupts_on) { 3682 vha->flags.init_done = 0; 3683 ha->isp_ops->disable_intrs(ha); 3684 } 3685 3686 qla2x00_free_irqs(vha); 3687 3688 qla2x00_free_fw_dump(ha); 3689 3690 pci_disable_device(pdev); 3691 ql_log(ql_log_info, vha, 0xfffe, 3692 "Adapter shutdown successfully.\n"); 3693 } 3694 3695 /* Deletes all the virtual ports for a given ha */ 3696 static void 3697 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3698 { 3699 scsi_qla_host_t *vha; 3700 unsigned long flags; 3701 3702 mutex_lock(&ha->vport_lock); 3703 while (ha->cur_vport_count) { 3704 spin_lock_irqsave(&ha->vport_slock, flags); 3705 3706 BUG_ON(base_vha->list.next == &ha->vp_list); 3707 /* This assumes first entry in ha->vp_list is always base vha */ 3708 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3709 scsi_host_get(vha->host); 3710 3711 spin_unlock_irqrestore(&ha->vport_slock, flags); 3712 mutex_unlock(&ha->vport_lock); 3713 3714 qla_nvme_delete(vha); 3715 3716 fc_vport_terminate(vha->fc_vport); 3717 scsi_host_put(vha->host); 3718 3719 mutex_lock(&ha->vport_lock); 3720 } 3721 mutex_unlock(&ha->vport_lock); 3722 } 3723 3724 /* Stops all deferred work threads */ 3725 static void 3726 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3727 { 3728 /* Cancel all work and destroy DPC workqueues */ 3729 if (ha->dpc_lp_wq) { 3730 cancel_work_sync(&ha->idc_aen); 3731 destroy_workqueue(ha->dpc_lp_wq); 3732 ha->dpc_lp_wq = NULL; 3733 } 3734 3735 if (ha->dpc_hp_wq) { 3736 cancel_work_sync(&ha->nic_core_reset); 3737 cancel_work_sync(&ha->idc_state_handler); 3738 cancel_work_sync(&ha->nic_core_unrecoverable); 3739 destroy_workqueue(ha->dpc_hp_wq); 3740 ha->dpc_hp_wq = NULL; 3741 } 3742 3743 /* Kill the kernel thread for this host */ 3744 if (ha->dpc_thread) { 3745 struct task_struct *t = ha->dpc_thread; 3746 3747 /* 3748 * qla2xxx_wake_dpc checks for ->dpc_thread 3749 * so we need to zero it out. 3750 */ 3751 ha->dpc_thread = NULL; 3752 kthread_stop(t); 3753 } 3754 } 3755 3756 static void 3757 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3758 { 3759 if (IS_QLA82XX(ha)) { 3760 3761 iounmap((device_reg_t *)ha->nx_pcibase); 3762 if (!ql2xdbwr) 3763 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3764 } else { 3765 if (ha->iobase) 3766 iounmap(ha->iobase); 3767 3768 if (ha->cregbase) 3769 iounmap(ha->cregbase); 3770 3771 if (ha->mqiobase) 3772 iounmap(ha->mqiobase); 3773 3774 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3775 ha->msixbase) 3776 iounmap(ha->msixbase); 3777 } 3778 } 3779 3780 static void 3781 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3782 { 3783 if (IS_QLA8044(ha)) { 3784 qla8044_idc_lock(ha); 3785 qla8044_clear_drv_active(ha); 3786 qla8044_idc_unlock(ha); 3787 } else if (IS_QLA82XX(ha)) { 3788 qla82xx_idc_lock(ha); 3789 qla82xx_clear_drv_active(ha); 3790 qla82xx_idc_unlock(ha); 3791 } 3792 } 3793 3794 static void 3795 qla2x00_remove_one(struct pci_dev *pdev) 3796 { 3797 scsi_qla_host_t *base_vha; 3798 struct qla_hw_data *ha; 3799 3800 base_vha = pci_get_drvdata(pdev); 3801 ha = base_vha->hw; 3802 ql_log(ql_log_info, base_vha, 0xb079, 3803 "Removing driver\n"); 3804 __qla_set_remove_flag(base_vha); 3805 cancel_work_sync(&ha->board_disable); 3806 3807 /* 3808 * If the PCI device is disabled then there was a PCI-disconnect and 3809 * qla2x00_disable_board_on_pci_error has taken care of most of the 3810 * resources. 3811 */ 3812 if (!atomic_read(&pdev->enable_cnt)) { 3813 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3814 base_vha->gnl.l, base_vha->gnl.ldma); 3815 base_vha->gnl.l = NULL; 3816 scsi_host_put(base_vha->host); 3817 kfree(ha); 3818 pci_set_drvdata(pdev, NULL); 3819 return; 3820 } 3821 qla2x00_wait_for_hba_ready(base_vha); 3822 3823 /* 3824 * if UNLOADING flag is already set, then continue unload, 3825 * where it was set first. 3826 */ 3827 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3828 return; 3829 3830 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3831 IS_QLA28XX(ha)) { 3832 if (ha->flags.fw_started) 3833 qla2x00_abort_isp_cleanup(base_vha); 3834 } else if (!IS_QLAFX00(ha)) { 3835 if (IS_QLA8031(ha)) { 3836 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3837 "Clearing fcoe driver presence.\n"); 3838 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3839 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3840 "Error while clearing DRV-Presence.\n"); 3841 } 3842 3843 qla2x00_try_to_stop_firmware(base_vha); 3844 } 3845 3846 qla2x00_wait_for_sess_deletion(base_vha); 3847 3848 qla_nvme_delete(base_vha); 3849 3850 dma_free_coherent(&ha->pdev->dev, 3851 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3852 3853 base_vha->gnl.l = NULL; 3854 qla_enode_stop(base_vha); 3855 qla_edb_stop(base_vha); 3856 3857 vfree(base_vha->scan.l); 3858 3859 if (IS_QLAFX00(ha)) 3860 qlafx00_driver_shutdown(base_vha, 20); 3861 3862 qla2x00_delete_all_vps(ha, base_vha); 3863 3864 qla2x00_dfs_remove(base_vha); 3865 3866 qla84xx_put_chip(base_vha); 3867 3868 /* Disable timer */ 3869 if (base_vha->timer_active) 3870 qla2x00_stop_timer(base_vha); 3871 3872 base_vha->flags.online = 0; 3873 3874 /* free DMA memory */ 3875 if (ha->exlogin_buf) 3876 qla2x00_free_exlogin_buffer(ha); 3877 3878 /* free DMA memory */ 3879 if (ha->exchoffld_buf) 3880 qla2x00_free_exchoffld_buffer(ha); 3881 3882 qla2x00_destroy_deferred_work(ha); 3883 3884 qlt_remove_target(ha, base_vha); 3885 3886 qla2x00_free_sysfs_attr(base_vha, true); 3887 3888 fc_remove_host(base_vha->host); 3889 3890 scsi_remove_host(base_vha->host); 3891 3892 qla2x00_free_device(base_vha); 3893 3894 qla2x00_clear_drv_active(ha); 3895 3896 scsi_host_put(base_vha->host); 3897 3898 qla2x00_unmap_iobases(ha); 3899 3900 pci_release_selected_regions(ha->pdev, ha->bars); 3901 kfree(ha); 3902 3903 pci_disable_pcie_error_reporting(pdev); 3904 3905 pci_disable_device(pdev); 3906 } 3907 3908 static inline void 3909 qla24xx_free_purex_list(struct purex_list *list) 3910 { 3911 struct list_head *item, *next; 3912 ulong flags; 3913 3914 spin_lock_irqsave(&list->lock, flags); 3915 list_for_each_safe(item, next, &list->head) { 3916 list_del(item); 3917 kfree(list_entry(item, struct purex_item, list)); 3918 } 3919 spin_unlock_irqrestore(&list->lock, flags); 3920 } 3921 3922 static void 3923 qla2x00_free_device(scsi_qla_host_t *vha) 3924 { 3925 struct qla_hw_data *ha = vha->hw; 3926 3927 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3928 3929 /* Disable timer */ 3930 if (vha->timer_active) 3931 qla2x00_stop_timer(vha); 3932 3933 qla25xx_delete_queues(vha); 3934 vha->flags.online = 0; 3935 3936 /* turn-off interrupts on the card */ 3937 if (ha->interrupts_on) { 3938 vha->flags.init_done = 0; 3939 ha->isp_ops->disable_intrs(ha); 3940 } 3941 3942 qla2x00_free_fcports(vha); 3943 3944 qla2x00_free_irqs(vha); 3945 3946 /* Flush the work queue and remove it */ 3947 if (ha->wq) { 3948 flush_workqueue(ha->wq); 3949 destroy_workqueue(ha->wq); 3950 ha->wq = NULL; 3951 } 3952 3953 3954 qla24xx_free_purex_list(&vha->purex_list); 3955 3956 qla2x00_mem_free(ha); 3957 3958 qla82xx_md_free(vha); 3959 3960 qla_edif_sadb_release_free_pool(ha); 3961 qla_edif_sadb_release(ha); 3962 3963 qla2x00_free_queues(ha); 3964 } 3965 3966 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3967 { 3968 fc_port_t *fcport, *tfcport; 3969 3970 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3971 qla2x00_free_fcport(fcport); 3972 } 3973 3974 static inline void 3975 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3976 { 3977 int now; 3978 3979 if (!fcport->rport) 3980 return; 3981 3982 if (fcport->rport) { 3983 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3984 "%s %8phN. rport %p roles %x\n", 3985 __func__, fcport->port_name, fcport->rport, 3986 fcport->rport->roles); 3987 fc_remote_port_delete(fcport->rport); 3988 } 3989 qlt_do_generation_tick(vha, &now); 3990 } 3991 3992 /* 3993 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3994 * 3995 * Input: ha = adapter block pointer. fcport = port structure pointer. 3996 * 3997 * Return: None. 3998 * 3999 * Context: 4000 */ 4001 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4002 int do_login) 4003 { 4004 if (IS_QLAFX00(vha->hw)) { 4005 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4006 qla2x00_schedule_rport_del(vha, fcport); 4007 return; 4008 } 4009 4010 if (atomic_read(&fcport->state) == FCS_ONLINE && 4011 vha->vp_idx == fcport->vha->vp_idx) { 4012 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4013 qla2x00_schedule_rport_del(vha, fcport); 4014 } 4015 4016 /* 4017 * We may need to retry the login, so don't change the state of the 4018 * port but do the retries. 4019 */ 4020 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4021 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4022 4023 if (!do_login) 4024 return; 4025 4026 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4027 } 4028 4029 void 4030 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4031 { 4032 fc_port_t *fcport; 4033 4034 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4035 "Mark all dev lost\n"); 4036 4037 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4038 if (fcport->loop_id != FC_NO_LOOP_ID && 4039 (fcport->flags & FCF_FCP2_DEVICE) && 4040 fcport->port_type == FCT_TARGET && 4041 !qla2x00_reset_active(vha)) { 4042 ql_dbg(ql_dbg_disc, vha, 0x211a, 4043 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4044 fcport->flags, fcport->port_type, 4045 fcport->d_id.b24, fcport->port_name); 4046 continue; 4047 } 4048 fcport->scan_state = 0; 4049 qlt_schedule_sess_for_deletion(fcport); 4050 } 4051 } 4052 4053 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4054 { 4055 int i; 4056 4057 if (IS_FWI2_CAPABLE(ha)) 4058 return; 4059 4060 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4061 set_bit(i, ha->loop_id_map); 4062 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4063 set_bit(BROADCAST, ha->loop_id_map); 4064 } 4065 4066 /* 4067 * qla2x00_mem_alloc 4068 * Allocates adapter memory. 4069 * 4070 * Returns: 4071 * 0 = success. 4072 * !0 = failure. 4073 */ 4074 static int 4075 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4076 struct req_que **req, struct rsp_que **rsp) 4077 { 4078 char name[16]; 4079 int rc; 4080 4081 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4082 &ha->init_cb_dma, GFP_KERNEL); 4083 if (!ha->init_cb) 4084 goto fail; 4085 4086 rc = btree_init32(&ha->host_map); 4087 if (rc) 4088 goto fail_free_init_cb; 4089 4090 if (qlt_mem_alloc(ha) < 0) 4091 goto fail_free_btree; 4092 4093 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4094 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4095 if (!ha->gid_list) 4096 goto fail_free_tgt_mem; 4097 4098 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4099 if (!ha->srb_mempool) 4100 goto fail_free_gid_list; 4101 4102 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4103 /* Allocate cache for CT6 Ctx. */ 4104 if (!ctx_cachep) { 4105 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4106 sizeof(struct ct6_dsd), 0, 4107 SLAB_HWCACHE_ALIGN, NULL); 4108 if (!ctx_cachep) 4109 goto fail_free_srb_mempool; 4110 } 4111 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4112 ctx_cachep); 4113 if (!ha->ctx_mempool) 4114 goto fail_free_srb_mempool; 4115 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4116 "ctx_cachep=%p ctx_mempool=%p.\n", 4117 ctx_cachep, ha->ctx_mempool); 4118 } 4119 4120 /* Get memory for cached NVRAM */ 4121 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4122 if (!ha->nvram) 4123 goto fail_free_ctx_mempool; 4124 4125 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4126 ha->pdev->device); 4127 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4128 DMA_POOL_SIZE, 8, 0); 4129 if (!ha->s_dma_pool) 4130 goto fail_free_nvram; 4131 4132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4133 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4134 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4135 4136 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4137 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4138 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4139 if (!ha->dl_dma_pool) { 4140 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4141 "Failed to allocate memory for dl_dma_pool.\n"); 4142 goto fail_s_dma_pool; 4143 } 4144 4145 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4146 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4147 if (!ha->fcp_cmnd_dma_pool) { 4148 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4149 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4150 goto fail_dl_dma_pool; 4151 } 4152 4153 if (ql2xenabledif) { 4154 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4155 struct dsd_dma *dsd, *nxt; 4156 uint i; 4157 /* Creata a DMA pool of buffers for DIF bundling */ 4158 ha->dif_bundl_pool = dma_pool_create(name, 4159 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4160 if (!ha->dif_bundl_pool) { 4161 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4162 "%s: failed create dif_bundl_pool\n", 4163 __func__); 4164 goto fail_dif_bundl_dma_pool; 4165 } 4166 4167 INIT_LIST_HEAD(&ha->pool.good.head); 4168 INIT_LIST_HEAD(&ha->pool.unusable.head); 4169 ha->pool.good.count = 0; 4170 ha->pool.unusable.count = 0; 4171 for (i = 0; i < 128; i++) { 4172 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4173 if (!dsd) { 4174 ql_dbg_pci(ql_dbg_init, ha->pdev, 4175 0xe0ee, "%s: failed alloc dsd\n", 4176 __func__); 4177 return 1; 4178 } 4179 ha->dif_bundle_kallocs++; 4180 4181 dsd->dsd_addr = dma_pool_alloc( 4182 ha->dif_bundl_pool, GFP_ATOMIC, 4183 &dsd->dsd_list_dma); 4184 if (!dsd->dsd_addr) { 4185 ql_dbg_pci(ql_dbg_init, ha->pdev, 4186 0xe0ee, 4187 "%s: failed alloc ->dsd_addr\n", 4188 __func__); 4189 kfree(dsd); 4190 ha->dif_bundle_kallocs--; 4191 continue; 4192 } 4193 ha->dif_bundle_dma_allocs++; 4194 4195 /* 4196 * if DMA buffer crosses 4G boundary, 4197 * put it on bad list 4198 */ 4199 if (MSD(dsd->dsd_list_dma) ^ 4200 MSD(dsd->dsd_list_dma + bufsize)) { 4201 list_add_tail(&dsd->list, 4202 &ha->pool.unusable.head); 4203 ha->pool.unusable.count++; 4204 } else { 4205 list_add_tail(&dsd->list, 4206 &ha->pool.good.head); 4207 ha->pool.good.count++; 4208 } 4209 } 4210 4211 /* return the good ones back to the pool */ 4212 list_for_each_entry_safe(dsd, nxt, 4213 &ha->pool.good.head, list) { 4214 list_del(&dsd->list); 4215 dma_pool_free(ha->dif_bundl_pool, 4216 dsd->dsd_addr, dsd->dsd_list_dma); 4217 ha->dif_bundle_dma_allocs--; 4218 kfree(dsd); 4219 ha->dif_bundle_kallocs--; 4220 } 4221 4222 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4223 "%s: dif dma pool (good=%u unusable=%u)\n", 4224 __func__, ha->pool.good.count, 4225 ha->pool.unusable.count); 4226 } 4227 4228 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4229 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4230 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4231 ha->dif_bundl_pool); 4232 } 4233 4234 /* Allocate memory for SNS commands */ 4235 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4236 /* Get consistent memory allocated for SNS commands */ 4237 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4238 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4239 if (!ha->sns_cmd) 4240 goto fail_dma_pool; 4241 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4242 "sns_cmd: %p.\n", ha->sns_cmd); 4243 } else { 4244 /* Get consistent memory allocated for MS IOCB */ 4245 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4246 &ha->ms_iocb_dma); 4247 if (!ha->ms_iocb) 4248 goto fail_dma_pool; 4249 /* Get consistent memory allocated for CT SNS commands */ 4250 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4251 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4252 if (!ha->ct_sns) 4253 goto fail_free_ms_iocb; 4254 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4255 "ms_iocb=%p ct_sns=%p.\n", 4256 ha->ms_iocb, ha->ct_sns); 4257 } 4258 4259 /* Allocate memory for request ring */ 4260 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4261 if (!*req) { 4262 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4263 "Failed to allocate memory for req.\n"); 4264 goto fail_req; 4265 } 4266 (*req)->length = req_len; 4267 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4268 ((*req)->length + 1) * sizeof(request_t), 4269 &(*req)->dma, GFP_KERNEL); 4270 if (!(*req)->ring) { 4271 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4272 "Failed to allocate memory for req_ring.\n"); 4273 goto fail_req_ring; 4274 } 4275 /* Allocate memory for response ring */ 4276 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4277 if (!*rsp) { 4278 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4279 "Failed to allocate memory for rsp.\n"); 4280 goto fail_rsp; 4281 } 4282 (*rsp)->hw = ha; 4283 (*rsp)->length = rsp_len; 4284 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4285 ((*rsp)->length + 1) * sizeof(response_t), 4286 &(*rsp)->dma, GFP_KERNEL); 4287 if (!(*rsp)->ring) { 4288 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4289 "Failed to allocate memory for rsp_ring.\n"); 4290 goto fail_rsp_ring; 4291 } 4292 (*req)->rsp = *rsp; 4293 (*rsp)->req = *req; 4294 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4295 "req=%p req->length=%d req->ring=%p rsp=%p " 4296 "rsp->length=%d rsp->ring=%p.\n", 4297 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4298 (*rsp)->ring); 4299 /* Allocate memory for NVRAM data for vports */ 4300 if (ha->nvram_npiv_size) { 4301 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4302 sizeof(struct qla_npiv_entry), 4303 GFP_KERNEL); 4304 if (!ha->npiv_info) { 4305 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4306 "Failed to allocate memory for npiv_info.\n"); 4307 goto fail_npiv_info; 4308 } 4309 } else 4310 ha->npiv_info = NULL; 4311 4312 /* Get consistent memory allocated for EX-INIT-CB. */ 4313 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4314 IS_QLA28XX(ha)) { 4315 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4316 &ha->ex_init_cb_dma); 4317 if (!ha->ex_init_cb) 4318 goto fail_ex_init_cb; 4319 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4320 "ex_init_cb=%p.\n", ha->ex_init_cb); 4321 } 4322 4323 /* Get consistent memory allocated for Special Features-CB. */ 4324 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4325 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4326 &ha->sf_init_cb_dma); 4327 if (!ha->sf_init_cb) 4328 goto fail_sf_init_cb; 4329 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4330 "sf_init_cb=%p.\n", ha->sf_init_cb); 4331 } 4332 4333 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4334 4335 /* Get consistent memory allocated for Async Port-Database. */ 4336 if (!IS_FWI2_CAPABLE(ha)) { 4337 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4338 &ha->async_pd_dma); 4339 if (!ha->async_pd) 4340 goto fail_async_pd; 4341 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4342 "async_pd=%p.\n", ha->async_pd); 4343 } 4344 4345 INIT_LIST_HEAD(&ha->vp_list); 4346 4347 /* Allocate memory for our loop_id bitmap */ 4348 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4349 sizeof(long), 4350 GFP_KERNEL); 4351 if (!ha->loop_id_map) 4352 goto fail_loop_id_map; 4353 else { 4354 qla2x00_set_reserved_loop_ids(ha); 4355 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4356 "loop_id_map=%p.\n", ha->loop_id_map); 4357 } 4358 4359 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4360 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4361 if (!ha->sfp_data) { 4362 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4363 "Unable to allocate memory for SFP read-data.\n"); 4364 goto fail_sfp_data; 4365 } 4366 4367 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4368 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4369 GFP_KERNEL); 4370 if (!ha->flt) { 4371 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4372 "Unable to allocate memory for FLT.\n"); 4373 goto fail_flt_buffer; 4374 } 4375 4376 /* allocate the purex dma pool */ 4377 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4378 MAX_PAYLOAD, 8, 0); 4379 4380 if (!ha->purex_dma_pool) { 4381 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4382 "Unable to allocate purex_dma_pool.\n"); 4383 goto fail_flt; 4384 } 4385 4386 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4387 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4388 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4389 4390 if (!ha->elsrej.c) { 4391 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4392 "Alloc failed for els reject cmd.\n"); 4393 goto fail_elsrej; 4394 } 4395 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4396 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4397 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4398 return 0; 4399 4400 fail_elsrej: 4401 dma_pool_destroy(ha->purex_dma_pool); 4402 fail_flt: 4403 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4404 ha->flt, ha->flt_dma); 4405 4406 fail_flt_buffer: 4407 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4408 ha->sfp_data, ha->sfp_data_dma); 4409 fail_sfp_data: 4410 kfree(ha->loop_id_map); 4411 fail_loop_id_map: 4412 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4413 fail_async_pd: 4414 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4415 fail_sf_init_cb: 4416 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4417 fail_ex_init_cb: 4418 kfree(ha->npiv_info); 4419 fail_npiv_info: 4420 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4421 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4422 (*rsp)->ring = NULL; 4423 (*rsp)->dma = 0; 4424 fail_rsp_ring: 4425 kfree(*rsp); 4426 *rsp = NULL; 4427 fail_rsp: 4428 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4429 sizeof(request_t), (*req)->ring, (*req)->dma); 4430 (*req)->ring = NULL; 4431 (*req)->dma = 0; 4432 fail_req_ring: 4433 kfree(*req); 4434 *req = NULL; 4435 fail_req: 4436 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4437 ha->ct_sns, ha->ct_sns_dma); 4438 ha->ct_sns = NULL; 4439 ha->ct_sns_dma = 0; 4440 fail_free_ms_iocb: 4441 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4442 ha->ms_iocb = NULL; 4443 ha->ms_iocb_dma = 0; 4444 4445 if (ha->sns_cmd) 4446 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4447 ha->sns_cmd, ha->sns_cmd_dma); 4448 fail_dma_pool: 4449 if (ql2xenabledif) { 4450 struct dsd_dma *dsd, *nxt; 4451 4452 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4453 list) { 4454 list_del(&dsd->list); 4455 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4456 dsd->dsd_list_dma); 4457 ha->dif_bundle_dma_allocs--; 4458 kfree(dsd); 4459 ha->dif_bundle_kallocs--; 4460 ha->pool.unusable.count--; 4461 } 4462 dma_pool_destroy(ha->dif_bundl_pool); 4463 ha->dif_bundl_pool = NULL; 4464 } 4465 4466 fail_dif_bundl_dma_pool: 4467 if (IS_QLA82XX(ha) || ql2xenabledif) { 4468 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4469 ha->fcp_cmnd_dma_pool = NULL; 4470 } 4471 fail_dl_dma_pool: 4472 if (IS_QLA82XX(ha) || ql2xenabledif) { 4473 dma_pool_destroy(ha->dl_dma_pool); 4474 ha->dl_dma_pool = NULL; 4475 } 4476 fail_s_dma_pool: 4477 dma_pool_destroy(ha->s_dma_pool); 4478 ha->s_dma_pool = NULL; 4479 fail_free_nvram: 4480 kfree(ha->nvram); 4481 ha->nvram = NULL; 4482 fail_free_ctx_mempool: 4483 mempool_destroy(ha->ctx_mempool); 4484 ha->ctx_mempool = NULL; 4485 fail_free_srb_mempool: 4486 mempool_destroy(ha->srb_mempool); 4487 ha->srb_mempool = NULL; 4488 fail_free_gid_list: 4489 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4490 ha->gid_list, 4491 ha->gid_list_dma); 4492 ha->gid_list = NULL; 4493 ha->gid_list_dma = 0; 4494 fail_free_tgt_mem: 4495 qlt_mem_free(ha); 4496 fail_free_btree: 4497 btree_destroy32(&ha->host_map); 4498 fail_free_init_cb: 4499 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4500 ha->init_cb_dma); 4501 ha->init_cb = NULL; 4502 ha->init_cb_dma = 0; 4503 fail: 4504 ql_log(ql_log_fatal, NULL, 0x0030, 4505 "Memory allocation failure.\n"); 4506 return -ENOMEM; 4507 } 4508 4509 int 4510 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4511 { 4512 int rval; 4513 uint16_t size, max_cnt; 4514 uint32_t temp; 4515 struct qla_hw_data *ha = vha->hw; 4516 4517 /* Return if we don't need to alloacate any extended logins */ 4518 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4519 return QLA_SUCCESS; 4520 4521 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4522 return QLA_SUCCESS; 4523 4524 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4525 max_cnt = 0; 4526 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4527 if (rval != QLA_SUCCESS) { 4528 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4529 "Failed to get exlogin status.\n"); 4530 return rval; 4531 } 4532 4533 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4534 temp *= size; 4535 4536 if (temp != ha->exlogin_size) { 4537 qla2x00_free_exlogin_buffer(ha); 4538 ha->exlogin_size = temp; 4539 4540 ql_log(ql_log_info, vha, 0xd024, 4541 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4542 max_cnt, size, temp); 4543 4544 ql_log(ql_log_info, vha, 0xd025, 4545 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4546 4547 /* Get consistent memory for extended logins */ 4548 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4549 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4550 if (!ha->exlogin_buf) { 4551 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4552 "Failed to allocate memory for exlogin_buf_dma.\n"); 4553 return -ENOMEM; 4554 } 4555 } 4556 4557 /* Now configure the dma buffer */ 4558 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4559 if (rval) { 4560 ql_log(ql_log_fatal, vha, 0xd033, 4561 "Setup extended login buffer ****FAILED****.\n"); 4562 qla2x00_free_exlogin_buffer(ha); 4563 } 4564 4565 return rval; 4566 } 4567 4568 /* 4569 * qla2x00_free_exlogin_buffer 4570 * 4571 * Input: 4572 * ha = adapter block pointer 4573 */ 4574 void 4575 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4576 { 4577 if (ha->exlogin_buf) { 4578 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4579 ha->exlogin_buf, ha->exlogin_buf_dma); 4580 ha->exlogin_buf = NULL; 4581 ha->exlogin_size = 0; 4582 } 4583 } 4584 4585 static void 4586 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4587 { 4588 u32 temp; 4589 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4590 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4591 4592 if (max_cnt > vha->hw->max_exchg) 4593 max_cnt = vha->hw->max_exchg; 4594 4595 if (qla_ini_mode_enabled(vha)) { 4596 if (vha->ql2xiniexchg > max_cnt) 4597 vha->ql2xiniexchg = max_cnt; 4598 4599 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4600 *ret_cnt = vha->ql2xiniexchg; 4601 4602 } else if (qla_tgt_mode_enabled(vha)) { 4603 if (vha->ql2xexchoffld > max_cnt) { 4604 vha->ql2xexchoffld = max_cnt; 4605 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4606 } 4607 4608 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4609 *ret_cnt = vha->ql2xexchoffld; 4610 } else if (qla_dual_mode_enabled(vha)) { 4611 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4612 if (temp > max_cnt) { 4613 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4614 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4615 temp = max_cnt; 4616 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4617 } 4618 4619 if (temp > FW_DEF_EXCHANGES_CNT) 4620 *ret_cnt = temp; 4621 } 4622 } 4623 4624 int 4625 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4626 { 4627 int rval; 4628 u16 size, max_cnt; 4629 u32 actual_cnt, totsz; 4630 struct qla_hw_data *ha = vha->hw; 4631 4632 if (!ha->flags.exchoffld_enabled) 4633 return QLA_SUCCESS; 4634 4635 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4636 return QLA_SUCCESS; 4637 4638 max_cnt = 0; 4639 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4640 if (rval != QLA_SUCCESS) { 4641 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4642 "Failed to get exlogin status.\n"); 4643 return rval; 4644 } 4645 4646 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4647 ql_log(ql_log_info, vha, 0xd014, 4648 "Actual exchange offload count: %d.\n", actual_cnt); 4649 4650 totsz = actual_cnt * size; 4651 4652 if (totsz != ha->exchoffld_size) { 4653 qla2x00_free_exchoffld_buffer(ha); 4654 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4655 ha->exchoffld_size = 0; 4656 ha->flags.exchoffld_enabled = 0; 4657 return QLA_SUCCESS; 4658 } 4659 4660 ha->exchoffld_size = totsz; 4661 4662 ql_log(ql_log_info, vha, 0xd016, 4663 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4664 max_cnt, actual_cnt, size, totsz); 4665 4666 ql_log(ql_log_info, vha, 0xd017, 4667 "Exchange Buffers requested size = 0x%x\n", 4668 ha->exchoffld_size); 4669 4670 /* Get consistent memory for extended logins */ 4671 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4672 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4673 if (!ha->exchoffld_buf) { 4674 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4675 "Failed to allocate memory for Exchange Offload.\n"); 4676 4677 if (ha->max_exchg > 4678 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4679 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4680 } else if (ha->max_exchg > 4681 (FW_DEF_EXCHANGES_CNT + 512)) { 4682 ha->max_exchg -= 512; 4683 } else { 4684 ha->flags.exchoffld_enabled = 0; 4685 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4686 "Disabling Exchange offload due to lack of memory\n"); 4687 } 4688 ha->exchoffld_size = 0; 4689 4690 return -ENOMEM; 4691 } 4692 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4693 /* pathological case */ 4694 qla2x00_free_exchoffld_buffer(ha); 4695 ha->exchoffld_size = 0; 4696 ha->flags.exchoffld_enabled = 0; 4697 ql_log(ql_log_info, vha, 0xd016, 4698 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4699 ha->exchoffld_size, actual_cnt, size, totsz); 4700 return 0; 4701 } 4702 4703 /* Now configure the dma buffer */ 4704 rval = qla_set_exchoffld_mem_cfg(vha); 4705 if (rval) { 4706 ql_log(ql_log_fatal, vha, 0xd02e, 4707 "Setup exchange offload buffer ****FAILED****.\n"); 4708 qla2x00_free_exchoffld_buffer(ha); 4709 } else { 4710 /* re-adjust number of target exchange */ 4711 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4712 4713 if (qla_ini_mode_enabled(vha)) 4714 icb->exchange_count = 0; 4715 else 4716 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4717 } 4718 4719 return rval; 4720 } 4721 4722 /* 4723 * qla2x00_free_exchoffld_buffer 4724 * 4725 * Input: 4726 * ha = adapter block pointer 4727 */ 4728 void 4729 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4730 { 4731 if (ha->exchoffld_buf) { 4732 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4733 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4734 ha->exchoffld_buf = NULL; 4735 ha->exchoffld_size = 0; 4736 } 4737 } 4738 4739 /* 4740 * qla2x00_free_fw_dump 4741 * Frees fw dump stuff. 4742 * 4743 * Input: 4744 * ha = adapter block pointer 4745 */ 4746 static void 4747 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4748 { 4749 struct fwdt *fwdt = ha->fwdt; 4750 uint j; 4751 4752 if (ha->fce) 4753 dma_free_coherent(&ha->pdev->dev, 4754 FCE_SIZE, ha->fce, ha->fce_dma); 4755 4756 if (ha->eft) 4757 dma_free_coherent(&ha->pdev->dev, 4758 EFT_SIZE, ha->eft, ha->eft_dma); 4759 4760 vfree(ha->fw_dump); 4761 4762 ha->fce = NULL; 4763 ha->fce_dma = 0; 4764 ha->flags.fce_enabled = 0; 4765 ha->eft = NULL; 4766 ha->eft_dma = 0; 4767 ha->fw_dumped = false; 4768 ha->fw_dump_cap_flags = 0; 4769 ha->fw_dump_reading = 0; 4770 ha->fw_dump = NULL; 4771 ha->fw_dump_len = 0; 4772 4773 for (j = 0; j < 2; j++, fwdt++) { 4774 vfree(fwdt->template); 4775 fwdt->template = NULL; 4776 fwdt->length = 0; 4777 } 4778 } 4779 4780 /* 4781 * qla2x00_mem_free 4782 * Frees all adapter allocated memory. 4783 * 4784 * Input: 4785 * ha = adapter block pointer. 4786 */ 4787 static void 4788 qla2x00_mem_free(struct qla_hw_data *ha) 4789 { 4790 qla2x00_free_fw_dump(ha); 4791 4792 if (ha->mctp_dump) 4793 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4794 ha->mctp_dump_dma); 4795 ha->mctp_dump = NULL; 4796 4797 mempool_destroy(ha->srb_mempool); 4798 ha->srb_mempool = NULL; 4799 4800 if (ha->dcbx_tlv) 4801 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4802 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4803 ha->dcbx_tlv = NULL; 4804 4805 if (ha->xgmac_data) 4806 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4807 ha->xgmac_data, ha->xgmac_data_dma); 4808 ha->xgmac_data = NULL; 4809 4810 if (ha->sns_cmd) 4811 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4812 ha->sns_cmd, ha->sns_cmd_dma); 4813 ha->sns_cmd = NULL; 4814 ha->sns_cmd_dma = 0; 4815 4816 if (ha->ct_sns) 4817 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4818 ha->ct_sns, ha->ct_sns_dma); 4819 ha->ct_sns = NULL; 4820 ha->ct_sns_dma = 0; 4821 4822 if (ha->sfp_data) 4823 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4824 ha->sfp_data_dma); 4825 ha->sfp_data = NULL; 4826 4827 if (ha->flt) 4828 dma_free_coherent(&ha->pdev->dev, 4829 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4830 ha->flt, ha->flt_dma); 4831 ha->flt = NULL; 4832 ha->flt_dma = 0; 4833 4834 if (ha->ms_iocb) 4835 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4836 ha->ms_iocb = NULL; 4837 ha->ms_iocb_dma = 0; 4838 4839 if (ha->sf_init_cb) 4840 dma_pool_free(ha->s_dma_pool, 4841 ha->sf_init_cb, ha->sf_init_cb_dma); 4842 4843 if (ha->ex_init_cb) 4844 dma_pool_free(ha->s_dma_pool, 4845 ha->ex_init_cb, ha->ex_init_cb_dma); 4846 ha->ex_init_cb = NULL; 4847 ha->ex_init_cb_dma = 0; 4848 4849 if (ha->async_pd) 4850 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4851 ha->async_pd = NULL; 4852 ha->async_pd_dma = 0; 4853 4854 dma_pool_destroy(ha->s_dma_pool); 4855 ha->s_dma_pool = NULL; 4856 4857 if (ha->gid_list) 4858 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4859 ha->gid_list, ha->gid_list_dma); 4860 ha->gid_list = NULL; 4861 ha->gid_list_dma = 0; 4862 4863 if (IS_QLA82XX(ha)) { 4864 if (!list_empty(&ha->gbl_dsd_list)) { 4865 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4866 4867 /* clean up allocated prev pool */ 4868 list_for_each_entry_safe(dsd_ptr, 4869 tdsd_ptr, &ha->gbl_dsd_list, list) { 4870 dma_pool_free(ha->dl_dma_pool, 4871 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4872 list_del(&dsd_ptr->list); 4873 kfree(dsd_ptr); 4874 } 4875 } 4876 } 4877 4878 dma_pool_destroy(ha->dl_dma_pool); 4879 ha->dl_dma_pool = NULL; 4880 4881 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4882 ha->fcp_cmnd_dma_pool = NULL; 4883 4884 mempool_destroy(ha->ctx_mempool); 4885 ha->ctx_mempool = NULL; 4886 4887 if (ql2xenabledif && ha->dif_bundl_pool) { 4888 struct dsd_dma *dsd, *nxt; 4889 4890 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4891 list) { 4892 list_del(&dsd->list); 4893 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4894 dsd->dsd_list_dma); 4895 ha->dif_bundle_dma_allocs--; 4896 kfree(dsd); 4897 ha->dif_bundle_kallocs--; 4898 ha->pool.unusable.count--; 4899 } 4900 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4901 list_del(&dsd->list); 4902 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4903 dsd->dsd_list_dma); 4904 ha->dif_bundle_dma_allocs--; 4905 kfree(dsd); 4906 ha->dif_bundle_kallocs--; 4907 } 4908 } 4909 4910 dma_pool_destroy(ha->dif_bundl_pool); 4911 ha->dif_bundl_pool = NULL; 4912 4913 qlt_mem_free(ha); 4914 qla_remove_hostmap(ha); 4915 4916 if (ha->init_cb) 4917 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4918 ha->init_cb, ha->init_cb_dma); 4919 4920 dma_pool_destroy(ha->purex_dma_pool); 4921 ha->purex_dma_pool = NULL; 4922 4923 if (ha->elsrej.c) { 4924 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4925 ha->elsrej.c, ha->elsrej.cdma); 4926 ha->elsrej.c = NULL; 4927 } 4928 4929 ha->init_cb = NULL; 4930 ha->init_cb_dma = 0; 4931 4932 vfree(ha->optrom_buffer); 4933 ha->optrom_buffer = NULL; 4934 kfree(ha->nvram); 4935 ha->nvram = NULL; 4936 kfree(ha->npiv_info); 4937 ha->npiv_info = NULL; 4938 kfree(ha->swl); 4939 ha->swl = NULL; 4940 kfree(ha->loop_id_map); 4941 ha->sf_init_cb = NULL; 4942 ha->sf_init_cb_dma = 0; 4943 ha->loop_id_map = NULL; 4944 } 4945 4946 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4947 struct qla_hw_data *ha) 4948 { 4949 struct Scsi_Host *host; 4950 struct scsi_qla_host *vha = NULL; 4951 4952 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4953 if (!host) { 4954 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4955 "Failed to allocate host from the scsi layer, aborting.\n"); 4956 return NULL; 4957 } 4958 4959 /* Clear our data area */ 4960 vha = shost_priv(host); 4961 memset(vha, 0, sizeof(scsi_qla_host_t)); 4962 4963 vha->host = host; 4964 vha->host_no = host->host_no; 4965 vha->hw = ha; 4966 4967 vha->qlini_mode = ql2x_ini_mode; 4968 vha->ql2xexchoffld = ql2xexchoffld; 4969 vha->ql2xiniexchg = ql2xiniexchg; 4970 4971 INIT_LIST_HEAD(&vha->vp_fcports); 4972 INIT_LIST_HEAD(&vha->work_list); 4973 INIT_LIST_HEAD(&vha->list); 4974 INIT_LIST_HEAD(&vha->qla_cmd_list); 4975 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4976 INIT_LIST_HEAD(&vha->logo_list); 4977 INIT_LIST_HEAD(&vha->plogi_ack_list); 4978 INIT_LIST_HEAD(&vha->qp_list); 4979 INIT_LIST_HEAD(&vha->gnl.fcports); 4980 INIT_LIST_HEAD(&vha->gpnid_list); 4981 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4982 4983 INIT_LIST_HEAD(&vha->purex_list.head); 4984 spin_lock_init(&vha->purex_list.lock); 4985 4986 spin_lock_init(&vha->work_lock); 4987 spin_lock_init(&vha->cmd_list_lock); 4988 init_waitqueue_head(&vha->fcport_waitQ); 4989 init_waitqueue_head(&vha->vref_waitq); 4990 qla_enode_init(vha); 4991 qla_edb_init(vha); 4992 4993 4994 vha->gnl.size = sizeof(struct get_name_list_extended) * 4995 (ha->max_loop_id + 1); 4996 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4997 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4998 if (!vha->gnl.l) { 4999 ql_log(ql_log_fatal, vha, 0xd04a, 5000 "Alloc failed for name list.\n"); 5001 scsi_host_put(vha->host); 5002 return NULL; 5003 } 5004 5005 /* todo: what about ext login? */ 5006 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5007 vha->scan.l = vmalloc(vha->scan.size); 5008 if (!vha->scan.l) { 5009 ql_log(ql_log_fatal, vha, 0xd04a, 5010 "Alloc failed for scan database.\n"); 5011 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5012 vha->gnl.l, vha->gnl.ldma); 5013 vha->gnl.l = NULL; 5014 scsi_host_put(vha->host); 5015 return NULL; 5016 } 5017 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5018 5019 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5020 ql_dbg(ql_dbg_init, vha, 0x0041, 5021 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5022 vha->host, vha->hw, vha, 5023 dev_name(&(ha->pdev->dev))); 5024 5025 return vha; 5026 } 5027 5028 struct qla_work_evt * 5029 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5030 { 5031 struct qla_work_evt *e; 5032 uint8_t bail; 5033 5034 if (test_bit(UNLOADING, &vha->dpc_flags)) 5035 return NULL; 5036 5037 QLA_VHA_MARK_BUSY(vha, bail); 5038 if (bail) 5039 return NULL; 5040 5041 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5042 if (!e) { 5043 QLA_VHA_MARK_NOT_BUSY(vha); 5044 return NULL; 5045 } 5046 5047 INIT_LIST_HEAD(&e->list); 5048 e->type = type; 5049 e->flags = QLA_EVT_FLAG_FREE; 5050 return e; 5051 } 5052 5053 int 5054 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5055 { 5056 unsigned long flags; 5057 bool q = false; 5058 5059 spin_lock_irqsave(&vha->work_lock, flags); 5060 list_add_tail(&e->list, &vha->work_list); 5061 5062 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5063 q = true; 5064 5065 spin_unlock_irqrestore(&vha->work_lock, flags); 5066 5067 if (q) 5068 queue_work(vha->hw->wq, &vha->iocb_work); 5069 5070 return QLA_SUCCESS; 5071 } 5072 5073 int 5074 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5075 u32 data) 5076 { 5077 struct qla_work_evt *e; 5078 5079 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5080 if (!e) 5081 return QLA_FUNCTION_FAILED; 5082 5083 e->u.aen.code = code; 5084 e->u.aen.data = data; 5085 return qla2x00_post_work(vha, e); 5086 } 5087 5088 int 5089 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5090 { 5091 struct qla_work_evt *e; 5092 5093 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5094 if (!e) 5095 return QLA_FUNCTION_FAILED; 5096 5097 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5098 return qla2x00_post_work(vha, e); 5099 } 5100 5101 #define qla2x00_post_async_work(name, type) \ 5102 int qla2x00_post_async_##name##_work( \ 5103 struct scsi_qla_host *vha, \ 5104 fc_port_t *fcport, uint16_t *data) \ 5105 { \ 5106 struct qla_work_evt *e; \ 5107 \ 5108 e = qla2x00_alloc_work(vha, type); \ 5109 if (!e) \ 5110 return QLA_FUNCTION_FAILED; \ 5111 \ 5112 e->u.logio.fcport = fcport; \ 5113 if (data) { \ 5114 e->u.logio.data[0] = data[0]; \ 5115 e->u.logio.data[1] = data[1]; \ 5116 } \ 5117 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5118 return qla2x00_post_work(vha, e); \ 5119 } 5120 5121 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5122 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5123 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5124 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5125 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5126 5127 int 5128 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5129 { 5130 struct qla_work_evt *e; 5131 5132 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5133 if (!e) 5134 return QLA_FUNCTION_FAILED; 5135 5136 e->u.uevent.code = code; 5137 return qla2x00_post_work(vha, e); 5138 } 5139 5140 static void 5141 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5142 { 5143 char event_string[40]; 5144 char *envp[] = { event_string, NULL }; 5145 5146 switch (code) { 5147 case QLA_UEVENT_CODE_FW_DUMP: 5148 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5149 vha->host_no); 5150 break; 5151 default: 5152 /* do nothing */ 5153 break; 5154 } 5155 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5156 } 5157 5158 int 5159 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5160 uint32_t *data, int cnt) 5161 { 5162 struct qla_work_evt *e; 5163 5164 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5165 if (!e) 5166 return QLA_FUNCTION_FAILED; 5167 5168 e->u.aenfx.evtcode = evtcode; 5169 e->u.aenfx.count = cnt; 5170 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5171 return qla2x00_post_work(vha, e); 5172 } 5173 5174 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5175 { 5176 unsigned long flags; 5177 5178 if (IS_SW_RESV_ADDR(fcport->d_id)) 5179 return; 5180 5181 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5182 if (fcport->disc_state == DSC_UPD_FCPORT) { 5183 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5184 return; 5185 } 5186 fcport->jiffies_at_registration = jiffies; 5187 fcport->sec_since_registration = 0; 5188 fcport->next_disc_state = DSC_DELETED; 5189 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5190 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5191 5192 queue_work(system_unbound_wq, &fcport->reg_work); 5193 } 5194 5195 static 5196 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5197 { 5198 unsigned long flags; 5199 fc_port_t *fcport = NULL, *tfcp; 5200 struct qlt_plogi_ack_t *pla = 5201 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5202 uint8_t free_fcport = 0; 5203 5204 ql_dbg(ql_dbg_disc, vha, 0xffff, 5205 "%s %d %8phC enter\n", 5206 __func__, __LINE__, e->u.new_sess.port_name); 5207 5208 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5209 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5210 if (fcport) { 5211 fcport->d_id = e->u.new_sess.id; 5212 if (pla) { 5213 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5214 memcpy(fcport->node_name, 5215 pla->iocb.u.isp24.u.plogi.node_name, 5216 WWN_SIZE); 5217 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5218 /* we took an extra ref_count to prevent PLOGI ACK when 5219 * fcport/sess has not been created. 5220 */ 5221 pla->ref_count--; 5222 } 5223 } else { 5224 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5225 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5226 if (fcport) { 5227 fcport->d_id = e->u.new_sess.id; 5228 fcport->flags |= FCF_FABRIC_DEVICE; 5229 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5230 fcport->tgt_short_link_down_cnt = 0; 5231 5232 memcpy(fcport->port_name, e->u.new_sess.port_name, 5233 WWN_SIZE); 5234 5235 fcport->fc4_type = e->u.new_sess.fc4_type; 5236 if (NVME_PRIORITY(vha->hw, fcport)) 5237 fcport->do_prli_nvme = 1; 5238 else 5239 fcport->do_prli_nvme = 0; 5240 5241 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5242 fcport->dm_login_expire = jiffies + 5243 QLA_N2N_WAIT_TIME * HZ; 5244 fcport->fc4_type = FS_FC4TYPE_FCP; 5245 fcport->n2n_flag = 1; 5246 if (vha->flags.nvme_enabled) 5247 fcport->fc4_type |= FS_FC4TYPE_NVME; 5248 } 5249 5250 } else { 5251 ql_dbg(ql_dbg_disc, vha, 0xffff, 5252 "%s %8phC mem alloc fail.\n", 5253 __func__, e->u.new_sess.port_name); 5254 5255 if (pla) { 5256 list_del(&pla->list); 5257 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5258 } 5259 return; 5260 } 5261 5262 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5263 /* search again to make sure no one else got ahead */ 5264 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5265 e->u.new_sess.port_name, 1); 5266 if (tfcp) { 5267 /* should rarily happen */ 5268 ql_dbg(ql_dbg_disc, vha, 0xffff, 5269 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5270 __func__, tfcp->port_name, tfcp->disc_state, 5271 tfcp->fw_login_state); 5272 5273 free_fcport = 1; 5274 } else { 5275 list_add_tail(&fcport->list, &vha->vp_fcports); 5276 5277 } 5278 if (pla) { 5279 qlt_plogi_ack_link(vha, pla, fcport, 5280 QLT_PLOGI_LINK_SAME_WWN); 5281 pla->ref_count--; 5282 } 5283 } 5284 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5285 5286 if (fcport) { 5287 fcport->id_changed = 1; 5288 fcport->scan_state = QLA_FCPORT_FOUND; 5289 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5290 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5291 5292 if (pla) { 5293 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5294 u16 wd3_lo; 5295 5296 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5297 fcport->local = 0; 5298 fcport->loop_id = 5299 le16_to_cpu( 5300 pla->iocb.u.isp24.nport_handle); 5301 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5302 wd3_lo = 5303 le16_to_cpu( 5304 pla->iocb.u.isp24.u.prli.wd3_lo); 5305 5306 if (wd3_lo & BIT_7) 5307 fcport->conf_compl_supported = 1; 5308 5309 if ((wd3_lo & BIT_4) == 0) 5310 fcport->port_type = FCT_INITIATOR; 5311 else 5312 fcport->port_type = FCT_TARGET; 5313 } 5314 qlt_plogi_ack_unref(vha, pla); 5315 } else { 5316 fc_port_t *dfcp = NULL; 5317 5318 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5319 tfcp = qla2x00_find_fcport_by_nportid(vha, 5320 &e->u.new_sess.id, 1); 5321 if (tfcp && (tfcp != fcport)) { 5322 /* 5323 * We have a conflict fcport with same NportID. 5324 */ 5325 ql_dbg(ql_dbg_disc, vha, 0xffff, 5326 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5327 __func__, tfcp->port_name, tfcp->disc_state, 5328 tfcp->fw_login_state); 5329 5330 switch (tfcp->disc_state) { 5331 case DSC_DELETED: 5332 break; 5333 case DSC_DELETE_PEND: 5334 fcport->login_pause = 1; 5335 tfcp->conflict = fcport; 5336 break; 5337 default: 5338 fcport->login_pause = 1; 5339 tfcp->conflict = fcport; 5340 dfcp = tfcp; 5341 break; 5342 } 5343 } 5344 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5345 if (dfcp) 5346 qlt_schedule_sess_for_deletion(tfcp); 5347 5348 if (N2N_TOPO(vha->hw)) { 5349 fcport->flags &= ~FCF_FABRIC_DEVICE; 5350 fcport->keep_nport_handle = 1; 5351 if (vha->flags.nvme_enabled) { 5352 fcport->fc4_type = 5353 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5354 fcport->n2n_flag = 1; 5355 } 5356 fcport->fw_login_state = 0; 5357 5358 schedule_delayed_work(&vha->scan.scan_work, 5); 5359 } else { 5360 qla24xx_fcport_handle_login(vha, fcport); 5361 } 5362 } 5363 } 5364 5365 if (free_fcport) { 5366 qla2x00_free_fcport(fcport); 5367 if (pla) { 5368 list_del(&pla->list); 5369 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5370 } 5371 } 5372 } 5373 5374 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5375 { 5376 struct srb *sp = e->u.iosb.sp; 5377 int rval; 5378 5379 rval = qla2x00_start_sp(sp); 5380 if (rval != QLA_SUCCESS) { 5381 ql_dbg(ql_dbg_disc, vha, 0x2043, 5382 "%s: %s: Re-issue IOCB failed (%d).\n", 5383 __func__, sp->name, rval); 5384 qla24xx_sp_unmap(vha, sp); 5385 } 5386 } 5387 5388 void 5389 qla2x00_do_work(struct scsi_qla_host *vha) 5390 { 5391 struct qla_work_evt *e, *tmp; 5392 unsigned long flags; 5393 LIST_HEAD(work); 5394 int rc; 5395 5396 spin_lock_irqsave(&vha->work_lock, flags); 5397 list_splice_init(&vha->work_list, &work); 5398 spin_unlock_irqrestore(&vha->work_lock, flags); 5399 5400 list_for_each_entry_safe(e, tmp, &work, list) { 5401 rc = QLA_SUCCESS; 5402 switch (e->type) { 5403 case QLA_EVT_AEN: 5404 fc_host_post_event(vha->host, fc_get_event_number(), 5405 e->u.aen.code, e->u.aen.data); 5406 break; 5407 case QLA_EVT_IDC_ACK: 5408 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5409 break; 5410 case QLA_EVT_ASYNC_LOGIN: 5411 qla2x00_async_login(vha, e->u.logio.fcport, 5412 e->u.logio.data); 5413 break; 5414 case QLA_EVT_ASYNC_LOGOUT: 5415 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5416 break; 5417 case QLA_EVT_ASYNC_ADISC: 5418 qla2x00_async_adisc(vha, e->u.logio.fcport, 5419 e->u.logio.data); 5420 break; 5421 case QLA_EVT_UEVENT: 5422 qla2x00_uevent_emit(vha, e->u.uevent.code); 5423 break; 5424 case QLA_EVT_AENFX: 5425 qlafx00_process_aen(vha, e); 5426 break; 5427 case QLA_EVT_GPNID: 5428 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5429 break; 5430 case QLA_EVT_UNMAP: 5431 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5432 break; 5433 case QLA_EVT_RELOGIN: 5434 qla2x00_relogin(vha); 5435 break; 5436 case QLA_EVT_NEW_SESS: 5437 qla24xx_create_new_sess(vha, e); 5438 break; 5439 case QLA_EVT_GPDB: 5440 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5441 e->u.fcport.opt); 5442 break; 5443 case QLA_EVT_PRLI: 5444 qla24xx_async_prli(vha, e->u.fcport.fcport); 5445 break; 5446 case QLA_EVT_GPSC: 5447 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5448 break; 5449 case QLA_EVT_GNL: 5450 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5451 break; 5452 case QLA_EVT_NACK: 5453 qla24xx_do_nack_work(vha, e); 5454 break; 5455 case QLA_EVT_ASYNC_PRLO: 5456 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5457 break; 5458 case QLA_EVT_ASYNC_PRLO_DONE: 5459 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5460 e->u.logio.data); 5461 break; 5462 case QLA_EVT_GPNFT: 5463 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5464 e->u.gpnft.sp); 5465 break; 5466 case QLA_EVT_GPNFT_DONE: 5467 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5468 break; 5469 case QLA_EVT_GNNFT_DONE: 5470 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5471 break; 5472 case QLA_EVT_GNNID: 5473 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5474 break; 5475 case QLA_EVT_GFPNID: 5476 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5477 break; 5478 case QLA_EVT_SP_RETRY: 5479 qla_sp_retry(vha, e); 5480 break; 5481 case QLA_EVT_IIDMA: 5482 qla_do_iidma_work(vha, e->u.fcport.fcport); 5483 break; 5484 case QLA_EVT_ELS_PLOGI: 5485 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5486 e->u.fcport.fcport, false); 5487 break; 5488 case QLA_EVT_SA_REPLACE: 5489 qla24xx_issue_sa_replace_iocb(vha, e); 5490 break; 5491 } 5492 5493 if (rc == EAGAIN) { 5494 /* put 'work' at head of 'vha->work_list' */ 5495 spin_lock_irqsave(&vha->work_lock, flags); 5496 list_splice(&work, &vha->work_list); 5497 spin_unlock_irqrestore(&vha->work_lock, flags); 5498 break; 5499 } 5500 list_del_init(&e->list); 5501 if (e->flags & QLA_EVT_FLAG_FREE) 5502 kfree(e); 5503 5504 /* For each work completed decrement vha ref count */ 5505 QLA_VHA_MARK_NOT_BUSY(vha); 5506 } 5507 } 5508 5509 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5510 { 5511 struct qla_work_evt *e; 5512 5513 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5514 5515 if (!e) { 5516 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5517 return QLA_FUNCTION_FAILED; 5518 } 5519 5520 return qla2x00_post_work(vha, e); 5521 } 5522 5523 /* Relogins all the fcports of a vport 5524 * Context: dpc thread 5525 */ 5526 void qla2x00_relogin(struct scsi_qla_host *vha) 5527 { 5528 fc_port_t *fcport; 5529 int status, relogin_needed = 0; 5530 struct event_arg ea; 5531 5532 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5533 /* 5534 * If the port is not ONLINE then try to login 5535 * to it if we haven't run out of retries. 5536 */ 5537 if (atomic_read(&fcport->state) != FCS_ONLINE && 5538 fcport->login_retry) { 5539 if (fcport->scan_state != QLA_FCPORT_FOUND || 5540 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5541 fcport->disc_state == DSC_LOGIN_COMPLETE) 5542 continue; 5543 5544 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5545 fcport->disc_state == DSC_DELETE_PEND) { 5546 relogin_needed = 1; 5547 } else { 5548 if (vha->hw->current_topology != ISP_CFG_NL) { 5549 memset(&ea, 0, sizeof(ea)); 5550 ea.fcport = fcport; 5551 qla24xx_handle_relogin_event(vha, &ea); 5552 } else if (vha->hw->current_topology == 5553 ISP_CFG_NL) { 5554 fcport->login_retry--; 5555 status = 5556 qla2x00_local_device_login(vha, 5557 fcport); 5558 if (status == QLA_SUCCESS) { 5559 fcport->old_loop_id = 5560 fcport->loop_id; 5561 ql_dbg(ql_dbg_disc, vha, 0x2003, 5562 "Port login OK: logged in ID 0x%x.\n", 5563 fcport->loop_id); 5564 qla2x00_update_fcport 5565 (vha, fcport); 5566 } else if (status == 1) { 5567 set_bit(RELOGIN_NEEDED, 5568 &vha->dpc_flags); 5569 /* retry the login again */ 5570 ql_dbg(ql_dbg_disc, vha, 0x2007, 5571 "Retrying %d login again loop_id 0x%x.\n", 5572 fcport->login_retry, 5573 fcport->loop_id); 5574 } else { 5575 fcport->login_retry = 0; 5576 } 5577 5578 if (fcport->login_retry == 0 && 5579 status != QLA_SUCCESS) 5580 qla2x00_clear_loop_id(fcport); 5581 } 5582 } 5583 } 5584 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5585 break; 5586 } 5587 5588 if (relogin_needed) 5589 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5590 5591 ql_dbg(ql_dbg_disc, vha, 0x400e, 5592 "Relogin end.\n"); 5593 } 5594 5595 /* Schedule work on any of the dpc-workqueues */ 5596 void 5597 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5598 { 5599 struct qla_hw_data *ha = base_vha->hw; 5600 5601 switch (work_code) { 5602 case MBA_IDC_AEN: /* 0x8200 */ 5603 if (ha->dpc_lp_wq) 5604 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5605 break; 5606 5607 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5608 if (!ha->flags.nic_core_reset_hdlr_active) { 5609 if (ha->dpc_hp_wq) 5610 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5611 } else 5612 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5613 "NIC Core reset is already active. Skip " 5614 "scheduling it again.\n"); 5615 break; 5616 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5617 if (ha->dpc_hp_wq) 5618 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5619 break; 5620 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5621 if (ha->dpc_hp_wq) 5622 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5623 break; 5624 default: 5625 ql_log(ql_log_warn, base_vha, 0xb05f, 5626 "Unknown work-code=0x%x.\n", work_code); 5627 } 5628 5629 return; 5630 } 5631 5632 /* Work: Perform NIC Core Unrecoverable state handling */ 5633 void 5634 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5635 { 5636 struct qla_hw_data *ha = 5637 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5638 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5639 uint32_t dev_state = 0; 5640 5641 qla83xx_idc_lock(base_vha, 0); 5642 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5643 qla83xx_reset_ownership(base_vha); 5644 if (ha->flags.nic_core_reset_owner) { 5645 ha->flags.nic_core_reset_owner = 0; 5646 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5647 QLA8XXX_DEV_FAILED); 5648 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5649 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5650 } 5651 qla83xx_idc_unlock(base_vha, 0); 5652 } 5653 5654 /* Work: Execute IDC state handler */ 5655 void 5656 qla83xx_idc_state_handler_work(struct work_struct *work) 5657 { 5658 struct qla_hw_data *ha = 5659 container_of(work, struct qla_hw_data, idc_state_handler); 5660 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5661 uint32_t dev_state = 0; 5662 5663 qla83xx_idc_lock(base_vha, 0); 5664 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5665 if (dev_state == QLA8XXX_DEV_FAILED || 5666 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5667 qla83xx_idc_state_handler(base_vha); 5668 qla83xx_idc_unlock(base_vha, 0); 5669 } 5670 5671 static int 5672 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5673 { 5674 int rval = QLA_SUCCESS; 5675 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5676 uint32_t heart_beat_counter1, heart_beat_counter2; 5677 5678 do { 5679 if (time_after(jiffies, heart_beat_wait)) { 5680 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5681 "Nic Core f/w is not alive.\n"); 5682 rval = QLA_FUNCTION_FAILED; 5683 break; 5684 } 5685 5686 qla83xx_idc_lock(base_vha, 0); 5687 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5688 &heart_beat_counter1); 5689 qla83xx_idc_unlock(base_vha, 0); 5690 msleep(100); 5691 qla83xx_idc_lock(base_vha, 0); 5692 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5693 &heart_beat_counter2); 5694 qla83xx_idc_unlock(base_vha, 0); 5695 } while (heart_beat_counter1 == heart_beat_counter2); 5696 5697 return rval; 5698 } 5699 5700 /* Work: Perform NIC Core Reset handling */ 5701 void 5702 qla83xx_nic_core_reset_work(struct work_struct *work) 5703 { 5704 struct qla_hw_data *ha = 5705 container_of(work, struct qla_hw_data, nic_core_reset); 5706 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5707 uint32_t dev_state = 0; 5708 5709 if (IS_QLA2031(ha)) { 5710 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5711 ql_log(ql_log_warn, base_vha, 0xb081, 5712 "Failed to dump mctp\n"); 5713 return; 5714 } 5715 5716 if (!ha->flags.nic_core_reset_hdlr_active) { 5717 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5718 qla83xx_idc_lock(base_vha, 0); 5719 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5720 &dev_state); 5721 qla83xx_idc_unlock(base_vha, 0); 5722 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5723 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5724 "Nic Core f/w is alive.\n"); 5725 return; 5726 } 5727 } 5728 5729 ha->flags.nic_core_reset_hdlr_active = 1; 5730 if (qla83xx_nic_core_reset(base_vha)) { 5731 /* NIC Core reset failed. */ 5732 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5733 "NIC Core reset failed.\n"); 5734 } 5735 ha->flags.nic_core_reset_hdlr_active = 0; 5736 } 5737 } 5738 5739 /* Work: Handle 8200 IDC aens */ 5740 void 5741 qla83xx_service_idc_aen(struct work_struct *work) 5742 { 5743 struct qla_hw_data *ha = 5744 container_of(work, struct qla_hw_data, idc_aen); 5745 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5746 uint32_t dev_state, idc_control; 5747 5748 qla83xx_idc_lock(base_vha, 0); 5749 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5750 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5751 qla83xx_idc_unlock(base_vha, 0); 5752 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5753 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5754 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5755 "Application requested NIC Core Reset.\n"); 5756 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5757 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5758 QLA_SUCCESS) { 5759 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5760 "Other protocol driver requested NIC Core Reset.\n"); 5761 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5762 } 5763 } else if (dev_state == QLA8XXX_DEV_FAILED || 5764 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5765 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5766 } 5767 } 5768 5769 /* 5770 * Control the frequency of IDC lock retries 5771 */ 5772 #define QLA83XX_WAIT_LOGIC_MS 100 5773 5774 static int 5775 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5776 { 5777 int rval; 5778 uint32_t data; 5779 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5780 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5781 struct qla_hw_data *ha = base_vha->hw; 5782 5783 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5784 "Trying force recovery of the IDC lock.\n"); 5785 5786 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5787 if (rval) 5788 return rval; 5789 5790 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5791 return QLA_SUCCESS; 5792 } else { 5793 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5794 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5795 data); 5796 if (rval) 5797 return rval; 5798 5799 msleep(200); 5800 5801 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5802 &data); 5803 if (rval) 5804 return rval; 5805 5806 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5807 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5808 ~(idc_lck_rcvry_stage_mask)); 5809 rval = qla83xx_wr_reg(base_vha, 5810 QLA83XX_IDC_LOCK_RECOVERY, data); 5811 if (rval) 5812 return rval; 5813 5814 /* Forcefully perform IDC UnLock */ 5815 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5816 &data); 5817 if (rval) 5818 return rval; 5819 /* Clear lock-id by setting 0xff */ 5820 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5821 0xff); 5822 if (rval) 5823 return rval; 5824 /* Clear lock-recovery by setting 0x0 */ 5825 rval = qla83xx_wr_reg(base_vha, 5826 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5827 if (rval) 5828 return rval; 5829 } else 5830 return QLA_SUCCESS; 5831 } 5832 5833 return rval; 5834 } 5835 5836 static int 5837 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5838 { 5839 int rval = QLA_SUCCESS; 5840 uint32_t o_drv_lockid, n_drv_lockid; 5841 unsigned long lock_recovery_timeout; 5842 5843 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5844 retry_lockid: 5845 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5846 if (rval) 5847 goto exit; 5848 5849 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5850 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5851 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5852 return QLA_SUCCESS; 5853 else 5854 return QLA_FUNCTION_FAILED; 5855 } 5856 5857 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5858 if (rval) 5859 goto exit; 5860 5861 if (o_drv_lockid == n_drv_lockid) { 5862 msleep(QLA83XX_WAIT_LOGIC_MS); 5863 goto retry_lockid; 5864 } else 5865 return QLA_SUCCESS; 5866 5867 exit: 5868 return rval; 5869 } 5870 5871 /* 5872 * Context: task, can sleep 5873 */ 5874 void 5875 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5876 { 5877 uint32_t data; 5878 uint32_t lock_owner; 5879 struct qla_hw_data *ha = base_vha->hw; 5880 5881 might_sleep(); 5882 5883 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5884 retry_lock: 5885 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5886 == QLA_SUCCESS) { 5887 if (data) { 5888 /* Setting lock-id to our function-number */ 5889 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5890 ha->portnum); 5891 } else { 5892 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5893 &lock_owner); 5894 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5895 "Failed to acquire IDC lock, acquired by %d, " 5896 "retrying...\n", lock_owner); 5897 5898 /* Retry/Perform IDC-Lock recovery */ 5899 if (qla83xx_idc_lock_recovery(base_vha) 5900 == QLA_SUCCESS) { 5901 msleep(QLA83XX_WAIT_LOGIC_MS); 5902 goto retry_lock; 5903 } else 5904 ql_log(ql_log_warn, base_vha, 0xb075, 5905 "IDC Lock recovery FAILED.\n"); 5906 } 5907 5908 } 5909 5910 return; 5911 } 5912 5913 static bool 5914 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5915 struct purex_entry_24xx *purex) 5916 { 5917 char fwstr[16]; 5918 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5919 struct port_database_24xx *pdb; 5920 5921 /* Domain Controller is always logged-out. */ 5922 /* if RDP request is not from Domain Controller: */ 5923 if (sid != 0xfffc01) 5924 return false; 5925 5926 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5927 5928 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5929 if (!pdb) { 5930 ql_dbg(ql_dbg_init, vha, 0x0181, 5931 "%s: Failed allocate pdb\n", __func__); 5932 } else if (qla24xx_get_port_database(vha, 5933 le16_to_cpu(purex->nport_handle), pdb)) { 5934 ql_dbg(ql_dbg_init, vha, 0x0181, 5935 "%s: Failed get pdb sid=%x\n", __func__, sid); 5936 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5937 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5938 ql_dbg(ql_dbg_init, vha, 0x0181, 5939 "%s: Port not logged in sid=%#x\n", __func__, sid); 5940 } else { 5941 /* RDP request is from logged in port */ 5942 kfree(pdb); 5943 return false; 5944 } 5945 kfree(pdb); 5946 5947 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5948 fwstr[strcspn(fwstr, " ")] = 0; 5949 /* if FW version allows RDP response length upto 2048 bytes: */ 5950 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5951 return false; 5952 5953 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5954 5955 /* RDP response length is to be reduced to maximum 256 bytes */ 5956 return true; 5957 } 5958 5959 /* 5960 * Function Name: qla24xx_process_purex_iocb 5961 * 5962 * Description: 5963 * Prepare a RDP response and send to Fabric switch 5964 * 5965 * PARAMETERS: 5966 * vha: SCSI qla host 5967 * purex: RDP request received by HBA 5968 */ 5969 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5970 struct purex_item *item) 5971 { 5972 struct qla_hw_data *ha = vha->hw; 5973 struct purex_entry_24xx *purex = 5974 (struct purex_entry_24xx *)&item->iocb; 5975 dma_addr_t rsp_els_dma; 5976 dma_addr_t rsp_payload_dma; 5977 dma_addr_t stat_dma; 5978 dma_addr_t sfp_dma; 5979 struct els_entry_24xx *rsp_els = NULL; 5980 struct rdp_rsp_payload *rsp_payload = NULL; 5981 struct link_statistics *stat = NULL; 5982 uint8_t *sfp = NULL; 5983 uint16_t sfp_flags = 0; 5984 uint rsp_payload_length = sizeof(*rsp_payload); 5985 int rval; 5986 5987 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5988 "%s: Enter\n", __func__); 5989 5990 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5991 "-------- ELS REQ -------\n"); 5992 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5993 purex, sizeof(*purex)); 5994 5995 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5996 rsp_payload_length = 5997 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5998 ql_dbg(ql_dbg_init, vha, 0x0181, 5999 "Reducing RSP payload length to %u bytes...\n", 6000 rsp_payload_length); 6001 } 6002 6003 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6004 &rsp_els_dma, GFP_KERNEL); 6005 if (!rsp_els) { 6006 ql_log(ql_log_warn, vha, 0x0183, 6007 "Failed allocate dma buffer ELS RSP.\n"); 6008 goto dealloc; 6009 } 6010 6011 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6012 &rsp_payload_dma, GFP_KERNEL); 6013 if (!rsp_payload) { 6014 ql_log(ql_log_warn, vha, 0x0184, 6015 "Failed allocate dma buffer ELS RSP payload.\n"); 6016 goto dealloc; 6017 } 6018 6019 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6020 &sfp_dma, GFP_KERNEL); 6021 6022 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6023 &stat_dma, GFP_KERNEL); 6024 6025 /* Prepare Response IOCB */ 6026 rsp_els->entry_type = ELS_IOCB_TYPE; 6027 rsp_els->entry_count = 1; 6028 rsp_els->sys_define = 0; 6029 rsp_els->entry_status = 0; 6030 rsp_els->handle = 0; 6031 rsp_els->nport_handle = purex->nport_handle; 6032 rsp_els->tx_dsd_count = cpu_to_le16(1); 6033 rsp_els->vp_index = purex->vp_idx; 6034 rsp_els->sof_type = EST_SOFI3; 6035 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6036 rsp_els->rx_dsd_count = 0; 6037 rsp_els->opcode = purex->els_frame_payload[0]; 6038 6039 rsp_els->d_id[0] = purex->s_id[0]; 6040 rsp_els->d_id[1] = purex->s_id[1]; 6041 rsp_els->d_id[2] = purex->s_id[2]; 6042 6043 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6044 rsp_els->rx_byte_count = 0; 6045 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6046 6047 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6048 rsp_els->tx_len = rsp_els->tx_byte_count; 6049 6050 rsp_els->rx_address = 0; 6051 rsp_els->rx_len = 0; 6052 6053 /* Prepare Response Payload */ 6054 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6055 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6056 sizeof(rsp_payload->hdr)); 6057 6058 /* Link service Request Info Descriptor */ 6059 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6060 rsp_payload->ls_req_info_desc.desc_len = 6061 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6062 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6063 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6064 6065 /* Link service Request Info Descriptor 2 */ 6066 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6067 rsp_payload->ls_req_info_desc2.desc_len = 6068 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6069 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6070 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6071 6072 6073 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6074 rsp_payload->sfp_diag_desc.desc_len = 6075 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6076 6077 if (sfp) { 6078 /* SFP Flags */ 6079 memset(sfp, 0, SFP_RTDI_LEN); 6080 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6081 if (!rval) { 6082 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6083 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6084 sfp_flags |= BIT_0; /* short wave */ 6085 else if (sfp[0] & BIT_1) 6086 sfp_flags |= BIT_1; /* long wave 1310nm */ 6087 else if (sfp[1] & BIT_4) 6088 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6089 } 6090 6091 /* SFP Type */ 6092 memset(sfp, 0, SFP_RTDI_LEN); 6093 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6094 if (!rval) { 6095 sfp_flags |= BIT_4; /* optical */ 6096 if (sfp[0] == 0x3) 6097 sfp_flags |= BIT_6; /* sfp+ */ 6098 } 6099 6100 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6101 6102 /* SFP Diagnostics */ 6103 memset(sfp, 0, SFP_RTDI_LEN); 6104 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6105 if (!rval) { 6106 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6107 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6108 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6109 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6110 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6111 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6112 } 6113 } 6114 6115 /* Port Speed Descriptor */ 6116 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6117 rsp_payload->port_speed_desc.desc_len = 6118 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6119 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6120 qla25xx_fdmi_port_speed_capability(ha)); 6121 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6122 qla25xx_fdmi_port_speed_currently(ha)); 6123 6124 /* Link Error Status Descriptor */ 6125 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6126 rsp_payload->ls_err_desc.desc_len = 6127 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6128 6129 if (stat) { 6130 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6131 if (!rval) { 6132 rsp_payload->ls_err_desc.link_fail_cnt = 6133 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6134 rsp_payload->ls_err_desc.loss_sync_cnt = 6135 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6136 rsp_payload->ls_err_desc.loss_sig_cnt = 6137 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6138 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6139 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6140 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6141 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6142 rsp_payload->ls_err_desc.inval_crc_cnt = 6143 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6144 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6145 } 6146 } 6147 6148 /* Portname Descriptor */ 6149 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6150 rsp_payload->port_name_diag_desc.desc_len = 6151 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6152 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6153 vha->node_name, 6154 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6155 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6156 vha->port_name, 6157 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6158 6159 /* F-Port Portname Descriptor */ 6160 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6161 rsp_payload->port_name_direct_desc.desc_len = 6162 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6163 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6164 vha->fabric_node_name, 6165 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6166 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6167 vha->fabric_port_name, 6168 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6169 6170 /* Bufer Credit Descriptor */ 6171 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6172 rsp_payload->buffer_credit_desc.desc_len = 6173 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6174 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6175 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6176 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6177 6178 if (ha->flags.plogi_template_valid) { 6179 uint32_t tmp = 6180 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6181 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6182 } 6183 6184 if (rsp_payload_length < sizeof(*rsp_payload)) 6185 goto send; 6186 6187 /* Optical Element Descriptor, Temperature */ 6188 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6189 rsp_payload->optical_elmt_desc[0].desc_len = 6190 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6191 /* Optical Element Descriptor, Voltage */ 6192 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6193 rsp_payload->optical_elmt_desc[1].desc_len = 6194 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6195 /* Optical Element Descriptor, Tx Bias Current */ 6196 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6197 rsp_payload->optical_elmt_desc[2].desc_len = 6198 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6199 /* Optical Element Descriptor, Tx Power */ 6200 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6201 rsp_payload->optical_elmt_desc[3].desc_len = 6202 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6203 /* Optical Element Descriptor, Rx Power */ 6204 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6205 rsp_payload->optical_elmt_desc[4].desc_len = 6206 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6207 6208 if (sfp) { 6209 memset(sfp, 0, SFP_RTDI_LEN); 6210 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6211 if (!rval) { 6212 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6213 6214 /* Optical Element Descriptor, Temperature */ 6215 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6216 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6217 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6218 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6219 rsp_payload->optical_elmt_desc[0].element_flags = 6220 cpu_to_be32(1 << 28); 6221 6222 /* Optical Element Descriptor, Voltage */ 6223 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6224 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6225 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6226 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6227 rsp_payload->optical_elmt_desc[1].element_flags = 6228 cpu_to_be32(2 << 28); 6229 6230 /* Optical Element Descriptor, Tx Bias Current */ 6231 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6232 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6233 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6234 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6235 rsp_payload->optical_elmt_desc[2].element_flags = 6236 cpu_to_be32(3 << 28); 6237 6238 /* Optical Element Descriptor, Tx Power */ 6239 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6240 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6241 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6242 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6243 rsp_payload->optical_elmt_desc[3].element_flags = 6244 cpu_to_be32(4 << 28); 6245 6246 /* Optical Element Descriptor, Rx Power */ 6247 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6248 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6249 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6250 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6251 rsp_payload->optical_elmt_desc[4].element_flags = 6252 cpu_to_be32(5 << 28); 6253 } 6254 6255 memset(sfp, 0, SFP_RTDI_LEN); 6256 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6257 if (!rval) { 6258 /* Temperature high/low alarm/warning */ 6259 rsp_payload->optical_elmt_desc[0].element_flags |= 6260 cpu_to_be32( 6261 (sfp[0] >> 7 & 1) << 3 | 6262 (sfp[0] >> 6 & 1) << 2 | 6263 (sfp[4] >> 7 & 1) << 1 | 6264 (sfp[4] >> 6 & 1) << 0); 6265 6266 /* Voltage high/low alarm/warning */ 6267 rsp_payload->optical_elmt_desc[1].element_flags |= 6268 cpu_to_be32( 6269 (sfp[0] >> 5 & 1) << 3 | 6270 (sfp[0] >> 4 & 1) << 2 | 6271 (sfp[4] >> 5 & 1) << 1 | 6272 (sfp[4] >> 4 & 1) << 0); 6273 6274 /* Tx Bias Current high/low alarm/warning */ 6275 rsp_payload->optical_elmt_desc[2].element_flags |= 6276 cpu_to_be32( 6277 (sfp[0] >> 3 & 1) << 3 | 6278 (sfp[0] >> 2 & 1) << 2 | 6279 (sfp[4] >> 3 & 1) << 1 | 6280 (sfp[4] >> 2 & 1) << 0); 6281 6282 /* Tx Power high/low alarm/warning */ 6283 rsp_payload->optical_elmt_desc[3].element_flags |= 6284 cpu_to_be32( 6285 (sfp[0] >> 1 & 1) << 3 | 6286 (sfp[0] >> 0 & 1) << 2 | 6287 (sfp[4] >> 1 & 1) << 1 | 6288 (sfp[4] >> 0 & 1) << 0); 6289 6290 /* Rx Power high/low alarm/warning */ 6291 rsp_payload->optical_elmt_desc[4].element_flags |= 6292 cpu_to_be32( 6293 (sfp[1] >> 7 & 1) << 3 | 6294 (sfp[1] >> 6 & 1) << 2 | 6295 (sfp[5] >> 7 & 1) << 1 | 6296 (sfp[5] >> 6 & 1) << 0); 6297 } 6298 } 6299 6300 /* Optical Product Data Descriptor */ 6301 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6302 rsp_payload->optical_prod_desc.desc_len = 6303 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6304 6305 if (sfp) { 6306 memset(sfp, 0, SFP_RTDI_LEN); 6307 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6308 if (!rval) { 6309 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6310 sfp + 0, 6311 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6312 memcpy(rsp_payload->optical_prod_desc.part_number, 6313 sfp + 20, 6314 sizeof(rsp_payload->optical_prod_desc.part_number)); 6315 memcpy(rsp_payload->optical_prod_desc.revision, 6316 sfp + 36, 6317 sizeof(rsp_payload->optical_prod_desc.revision)); 6318 memcpy(rsp_payload->optical_prod_desc.serial_number, 6319 sfp + 48, 6320 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6321 } 6322 6323 memset(sfp, 0, SFP_RTDI_LEN); 6324 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6325 if (!rval) { 6326 memcpy(rsp_payload->optical_prod_desc.date, 6327 sfp + 0, 6328 sizeof(rsp_payload->optical_prod_desc.date)); 6329 } 6330 } 6331 6332 send: 6333 ql_dbg(ql_dbg_init, vha, 0x0183, 6334 "Sending ELS Response to RDP Request...\n"); 6335 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6336 "-------- ELS RSP -------\n"); 6337 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6338 rsp_els, sizeof(*rsp_els)); 6339 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6340 "-------- ELS RSP PAYLOAD -------\n"); 6341 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6342 rsp_payload, rsp_payload_length); 6343 6344 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6345 6346 if (rval) { 6347 ql_log(ql_log_warn, vha, 0x0188, 6348 "%s: iocb failed to execute -> %x\n", __func__, rval); 6349 } else if (rsp_els->comp_status) { 6350 ql_log(ql_log_warn, vha, 0x0189, 6351 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6352 __func__, rsp_els->comp_status, 6353 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6354 } else { 6355 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6356 } 6357 6358 dealloc: 6359 if (stat) 6360 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6361 stat, stat_dma); 6362 if (sfp) 6363 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6364 sfp, sfp_dma); 6365 if (rsp_payload) 6366 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6367 rsp_payload, rsp_payload_dma); 6368 if (rsp_els) 6369 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6370 rsp_els, rsp_els_dma); 6371 } 6372 6373 void 6374 qla24xx_free_purex_item(struct purex_item *item) 6375 { 6376 if (item == &item->vha->default_item) 6377 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6378 else 6379 kfree(item); 6380 } 6381 6382 void qla24xx_process_purex_list(struct purex_list *list) 6383 { 6384 struct list_head head = LIST_HEAD_INIT(head); 6385 struct purex_item *item, *next; 6386 ulong flags; 6387 6388 spin_lock_irqsave(&list->lock, flags); 6389 list_splice_init(&list->head, &head); 6390 spin_unlock_irqrestore(&list->lock, flags); 6391 6392 list_for_each_entry_safe(item, next, &head, list) { 6393 list_del(&item->list); 6394 item->process_item(item->vha, item); 6395 qla24xx_free_purex_item(item); 6396 } 6397 } 6398 6399 /* 6400 * Context: task, can sleep 6401 */ 6402 void 6403 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6404 { 6405 #if 0 6406 uint16_t options = (requester_id << 15) | BIT_7; 6407 #endif 6408 uint16_t retry; 6409 uint32_t data; 6410 struct qla_hw_data *ha = base_vha->hw; 6411 6412 might_sleep(); 6413 6414 /* IDC-unlock implementation using driver-unlock/lock-id 6415 * remote registers 6416 */ 6417 retry = 0; 6418 retry_unlock: 6419 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6420 == QLA_SUCCESS) { 6421 if (data == ha->portnum) { 6422 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6423 /* Clearing lock-id by setting 0xff */ 6424 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6425 } else if (retry < 10) { 6426 /* SV: XXX: IDC unlock retrying needed here? */ 6427 6428 /* Retry for IDC-unlock */ 6429 msleep(QLA83XX_WAIT_LOGIC_MS); 6430 retry++; 6431 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6432 "Failed to release IDC lock, retrying=%d\n", retry); 6433 goto retry_unlock; 6434 } 6435 } else if (retry < 10) { 6436 /* Retry for IDC-unlock */ 6437 msleep(QLA83XX_WAIT_LOGIC_MS); 6438 retry++; 6439 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6440 "Failed to read drv-lockid, retrying=%d\n", retry); 6441 goto retry_unlock; 6442 } 6443 6444 return; 6445 6446 #if 0 6447 /* XXX: IDC-unlock implementation using access-control mbx */ 6448 retry = 0; 6449 retry_unlock2: 6450 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6451 if (retry < 10) { 6452 /* Retry for IDC-unlock */ 6453 msleep(QLA83XX_WAIT_LOGIC_MS); 6454 retry++; 6455 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6456 "Failed to release IDC lock, retrying=%d\n", retry); 6457 goto retry_unlock2; 6458 } 6459 } 6460 6461 return; 6462 #endif 6463 } 6464 6465 int 6466 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6467 { 6468 int rval = QLA_SUCCESS; 6469 struct qla_hw_data *ha = vha->hw; 6470 uint32_t drv_presence; 6471 6472 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6473 if (rval == QLA_SUCCESS) { 6474 drv_presence |= (1 << ha->portnum); 6475 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6476 drv_presence); 6477 } 6478 6479 return rval; 6480 } 6481 6482 int 6483 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6484 { 6485 int rval = QLA_SUCCESS; 6486 6487 qla83xx_idc_lock(vha, 0); 6488 rval = __qla83xx_set_drv_presence(vha); 6489 qla83xx_idc_unlock(vha, 0); 6490 6491 return rval; 6492 } 6493 6494 int 6495 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6496 { 6497 int rval = QLA_SUCCESS; 6498 struct qla_hw_data *ha = vha->hw; 6499 uint32_t drv_presence; 6500 6501 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6502 if (rval == QLA_SUCCESS) { 6503 drv_presence &= ~(1 << ha->portnum); 6504 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6505 drv_presence); 6506 } 6507 6508 return rval; 6509 } 6510 6511 int 6512 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6513 { 6514 int rval = QLA_SUCCESS; 6515 6516 qla83xx_idc_lock(vha, 0); 6517 rval = __qla83xx_clear_drv_presence(vha); 6518 qla83xx_idc_unlock(vha, 0); 6519 6520 return rval; 6521 } 6522 6523 static void 6524 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6525 { 6526 struct qla_hw_data *ha = vha->hw; 6527 uint32_t drv_ack, drv_presence; 6528 unsigned long ack_timeout; 6529 6530 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6531 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6532 while (1) { 6533 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6534 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6535 if ((drv_ack & drv_presence) == drv_presence) 6536 break; 6537 6538 if (time_after_eq(jiffies, ack_timeout)) { 6539 ql_log(ql_log_warn, vha, 0xb067, 6540 "RESET ACK TIMEOUT! drv_presence=0x%x " 6541 "drv_ack=0x%x\n", drv_presence, drv_ack); 6542 /* 6543 * The function(s) which did not ack in time are forced 6544 * to withdraw any further participation in the IDC 6545 * reset. 6546 */ 6547 if (drv_ack != drv_presence) 6548 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6549 drv_ack); 6550 break; 6551 } 6552 6553 qla83xx_idc_unlock(vha, 0); 6554 msleep(1000); 6555 qla83xx_idc_lock(vha, 0); 6556 } 6557 6558 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6559 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6560 } 6561 6562 static int 6563 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6564 { 6565 int rval = QLA_SUCCESS; 6566 uint32_t idc_control; 6567 6568 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6569 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6570 6571 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6572 __qla83xx_get_idc_control(vha, &idc_control); 6573 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6574 __qla83xx_set_idc_control(vha, 0); 6575 6576 qla83xx_idc_unlock(vha, 0); 6577 rval = qla83xx_restart_nic_firmware(vha); 6578 qla83xx_idc_lock(vha, 0); 6579 6580 if (rval != QLA_SUCCESS) { 6581 ql_log(ql_log_fatal, vha, 0xb06a, 6582 "Failed to restart NIC f/w.\n"); 6583 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6584 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6585 } else { 6586 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6587 "Success in restarting nic f/w.\n"); 6588 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6589 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6590 } 6591 6592 return rval; 6593 } 6594 6595 /* Assumes idc_lock always held on entry */ 6596 int 6597 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6598 { 6599 struct qla_hw_data *ha = base_vha->hw; 6600 int rval = QLA_SUCCESS; 6601 unsigned long dev_init_timeout; 6602 uint32_t dev_state; 6603 6604 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6605 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6606 6607 while (1) { 6608 6609 if (time_after_eq(jiffies, dev_init_timeout)) { 6610 ql_log(ql_log_warn, base_vha, 0xb06e, 6611 "Initialization TIMEOUT!\n"); 6612 /* Init timeout. Disable further NIC Core 6613 * communication. 6614 */ 6615 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6616 QLA8XXX_DEV_FAILED); 6617 ql_log(ql_log_info, base_vha, 0xb06f, 6618 "HW State: FAILED.\n"); 6619 } 6620 6621 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6622 switch (dev_state) { 6623 case QLA8XXX_DEV_READY: 6624 if (ha->flags.nic_core_reset_owner) 6625 qla83xx_idc_audit(base_vha, 6626 IDC_AUDIT_COMPLETION); 6627 ha->flags.nic_core_reset_owner = 0; 6628 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6629 "Reset_owner reset by 0x%x.\n", 6630 ha->portnum); 6631 goto exit; 6632 case QLA8XXX_DEV_COLD: 6633 if (ha->flags.nic_core_reset_owner) 6634 rval = qla83xx_device_bootstrap(base_vha); 6635 else { 6636 /* Wait for AEN to change device-state */ 6637 qla83xx_idc_unlock(base_vha, 0); 6638 msleep(1000); 6639 qla83xx_idc_lock(base_vha, 0); 6640 } 6641 break; 6642 case QLA8XXX_DEV_INITIALIZING: 6643 /* Wait for AEN to change device-state */ 6644 qla83xx_idc_unlock(base_vha, 0); 6645 msleep(1000); 6646 qla83xx_idc_lock(base_vha, 0); 6647 break; 6648 case QLA8XXX_DEV_NEED_RESET: 6649 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6650 qla83xx_need_reset_handler(base_vha); 6651 else { 6652 /* Wait for AEN to change device-state */ 6653 qla83xx_idc_unlock(base_vha, 0); 6654 msleep(1000); 6655 qla83xx_idc_lock(base_vha, 0); 6656 } 6657 /* reset timeout value after need reset handler */ 6658 dev_init_timeout = jiffies + 6659 (ha->fcoe_dev_init_timeout * HZ); 6660 break; 6661 case QLA8XXX_DEV_NEED_QUIESCENT: 6662 /* XXX: DEBUG for now */ 6663 qla83xx_idc_unlock(base_vha, 0); 6664 msleep(1000); 6665 qla83xx_idc_lock(base_vha, 0); 6666 break; 6667 case QLA8XXX_DEV_QUIESCENT: 6668 /* XXX: DEBUG for now */ 6669 if (ha->flags.quiesce_owner) 6670 goto exit; 6671 6672 qla83xx_idc_unlock(base_vha, 0); 6673 msleep(1000); 6674 qla83xx_idc_lock(base_vha, 0); 6675 dev_init_timeout = jiffies + 6676 (ha->fcoe_dev_init_timeout * HZ); 6677 break; 6678 case QLA8XXX_DEV_FAILED: 6679 if (ha->flags.nic_core_reset_owner) 6680 qla83xx_idc_audit(base_vha, 6681 IDC_AUDIT_COMPLETION); 6682 ha->flags.nic_core_reset_owner = 0; 6683 __qla83xx_clear_drv_presence(base_vha); 6684 qla83xx_idc_unlock(base_vha, 0); 6685 qla8xxx_dev_failed_handler(base_vha); 6686 rval = QLA_FUNCTION_FAILED; 6687 qla83xx_idc_lock(base_vha, 0); 6688 goto exit; 6689 case QLA8XXX_BAD_VALUE: 6690 qla83xx_idc_unlock(base_vha, 0); 6691 msleep(1000); 6692 qla83xx_idc_lock(base_vha, 0); 6693 break; 6694 default: 6695 ql_log(ql_log_warn, base_vha, 0xb071, 6696 "Unknown Device State: %x.\n", dev_state); 6697 qla83xx_idc_unlock(base_vha, 0); 6698 qla8xxx_dev_failed_handler(base_vha); 6699 rval = QLA_FUNCTION_FAILED; 6700 qla83xx_idc_lock(base_vha, 0); 6701 goto exit; 6702 } 6703 } 6704 6705 exit: 6706 return rval; 6707 } 6708 6709 void 6710 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6711 { 6712 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6713 board_disable); 6714 struct pci_dev *pdev = ha->pdev; 6715 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6716 6717 ql_log(ql_log_warn, base_vha, 0x015b, 6718 "Disabling adapter.\n"); 6719 6720 if (!atomic_read(&pdev->enable_cnt)) { 6721 ql_log(ql_log_info, base_vha, 0xfffc, 6722 "PCI device disabled, no action req for PCI error=%lx\n", 6723 base_vha->pci_flags); 6724 return; 6725 } 6726 6727 /* 6728 * if UNLOADING flag is already set, then continue unload, 6729 * where it was set first. 6730 */ 6731 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6732 return; 6733 6734 qla2x00_wait_for_sess_deletion(base_vha); 6735 6736 qla2x00_delete_all_vps(ha, base_vha); 6737 6738 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6739 6740 qla2x00_dfs_remove(base_vha); 6741 6742 qla84xx_put_chip(base_vha); 6743 6744 if (base_vha->timer_active) 6745 qla2x00_stop_timer(base_vha); 6746 6747 base_vha->flags.online = 0; 6748 6749 qla2x00_destroy_deferred_work(ha); 6750 6751 /* 6752 * Do not try to stop beacon blink as it will issue a mailbox 6753 * command. 6754 */ 6755 qla2x00_free_sysfs_attr(base_vha, false); 6756 6757 fc_remove_host(base_vha->host); 6758 6759 scsi_remove_host(base_vha->host); 6760 6761 base_vha->flags.init_done = 0; 6762 qla25xx_delete_queues(base_vha); 6763 qla2x00_free_fcports(base_vha); 6764 qla2x00_free_irqs(base_vha); 6765 qla2x00_mem_free(ha); 6766 qla82xx_md_free(base_vha); 6767 qla2x00_free_queues(ha); 6768 6769 qla2x00_unmap_iobases(ha); 6770 6771 pci_release_selected_regions(ha->pdev, ha->bars); 6772 pci_disable_pcie_error_reporting(pdev); 6773 pci_disable_device(pdev); 6774 6775 /* 6776 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6777 */ 6778 } 6779 6780 /************************************************************************** 6781 * qla2x00_do_dpc 6782 * This kernel thread is a task that is schedule by the interrupt handler 6783 * to perform the background processing for interrupts. 6784 * 6785 * Notes: 6786 * This task always run in the context of a kernel thread. It 6787 * is kick-off by the driver's detect code and starts up 6788 * up one per adapter. It immediately goes to sleep and waits for 6789 * some fibre event. When either the interrupt handler or 6790 * the timer routine detects a event it will one of the task 6791 * bits then wake us up. 6792 **************************************************************************/ 6793 static int 6794 qla2x00_do_dpc(void *data) 6795 { 6796 scsi_qla_host_t *base_vha; 6797 struct qla_hw_data *ha; 6798 uint32_t online; 6799 struct qla_qpair *qpair; 6800 6801 ha = (struct qla_hw_data *)data; 6802 base_vha = pci_get_drvdata(ha->pdev); 6803 6804 set_user_nice(current, MIN_NICE); 6805 6806 set_current_state(TASK_INTERRUPTIBLE); 6807 while (!kthread_should_stop()) { 6808 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6809 "DPC handler sleeping.\n"); 6810 6811 schedule(); 6812 6813 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6814 qla_pci_set_eeh_busy(base_vha); 6815 6816 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6817 goto end_loop; 6818 6819 if (ha->flags.eeh_busy) { 6820 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6821 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6822 goto end_loop; 6823 } 6824 6825 ha->dpc_active = 1; 6826 6827 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6828 "DPC handler waking up, dpc_flags=0x%lx.\n", 6829 base_vha->dpc_flags); 6830 6831 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6832 break; 6833 6834 if (IS_P3P_TYPE(ha)) { 6835 if (IS_QLA8044(ha)) { 6836 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6837 &base_vha->dpc_flags)) { 6838 qla8044_idc_lock(ha); 6839 qla8044_wr_direct(base_vha, 6840 QLA8044_CRB_DEV_STATE_INDEX, 6841 QLA8XXX_DEV_FAILED); 6842 qla8044_idc_unlock(ha); 6843 ql_log(ql_log_info, base_vha, 0x4004, 6844 "HW State: FAILED.\n"); 6845 qla8044_device_state_handler(base_vha); 6846 continue; 6847 } 6848 6849 } else { 6850 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6851 &base_vha->dpc_flags)) { 6852 qla82xx_idc_lock(ha); 6853 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6854 QLA8XXX_DEV_FAILED); 6855 qla82xx_idc_unlock(ha); 6856 ql_log(ql_log_info, base_vha, 0x0151, 6857 "HW State: FAILED.\n"); 6858 qla82xx_device_state_handler(base_vha); 6859 continue; 6860 } 6861 } 6862 6863 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6864 &base_vha->dpc_flags)) { 6865 6866 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6867 "FCoE context reset scheduled.\n"); 6868 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6869 &base_vha->dpc_flags))) { 6870 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6871 /* FCoE-ctx reset failed. 6872 * Escalate to chip-reset 6873 */ 6874 set_bit(ISP_ABORT_NEEDED, 6875 &base_vha->dpc_flags); 6876 } 6877 clear_bit(ABORT_ISP_ACTIVE, 6878 &base_vha->dpc_flags); 6879 } 6880 6881 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6882 "FCoE context reset end.\n"); 6883 } 6884 } else if (IS_QLAFX00(ha)) { 6885 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6886 &base_vha->dpc_flags)) { 6887 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6888 "Firmware Reset Recovery\n"); 6889 if (qlafx00_reset_initialize(base_vha)) { 6890 /* Failed. Abort isp later. */ 6891 if (!test_bit(UNLOADING, 6892 &base_vha->dpc_flags)) { 6893 set_bit(ISP_UNRECOVERABLE, 6894 &base_vha->dpc_flags); 6895 ql_dbg(ql_dbg_dpc, base_vha, 6896 0x4021, 6897 "Reset Recovery Failed\n"); 6898 } 6899 } 6900 } 6901 6902 if (test_and_clear_bit(FX00_TARGET_SCAN, 6903 &base_vha->dpc_flags)) { 6904 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6905 "ISPFx00 Target Scan scheduled\n"); 6906 if (qlafx00_rescan_isp(base_vha)) { 6907 if (!test_bit(UNLOADING, 6908 &base_vha->dpc_flags)) 6909 set_bit(ISP_UNRECOVERABLE, 6910 &base_vha->dpc_flags); 6911 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6912 "ISPFx00 Target Scan Failed\n"); 6913 } 6914 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6915 "ISPFx00 Target Scan End\n"); 6916 } 6917 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6918 &base_vha->dpc_flags)) { 6919 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6920 "ISPFx00 Host Info resend scheduled\n"); 6921 qlafx00_fx_disc(base_vha, 6922 &base_vha->hw->mr.fcport, 6923 FXDISC_REG_HOST_INFO); 6924 } 6925 } 6926 6927 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6928 &base_vha->dpc_flags)) { 6929 /* Semantic: 6930 * - NO-OP -- await next ISP-ABORT. Preferred method 6931 * to minimize disruptions that will occur 6932 * when a forced chip-reset occurs. 6933 * - Force -- ISP-ABORT scheduled. 6934 */ 6935 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6936 } 6937 6938 if (test_and_clear_bit 6939 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6940 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6941 bool do_reset = true; 6942 6943 switch (base_vha->qlini_mode) { 6944 case QLA2XXX_INI_MODE_ENABLED: 6945 break; 6946 case QLA2XXX_INI_MODE_DISABLED: 6947 if (!qla_tgt_mode_enabled(base_vha) && 6948 !ha->flags.fw_started) 6949 do_reset = false; 6950 break; 6951 case QLA2XXX_INI_MODE_DUAL: 6952 if (!qla_dual_mode_enabled(base_vha) && 6953 !ha->flags.fw_started) 6954 do_reset = false; 6955 break; 6956 default: 6957 break; 6958 } 6959 6960 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6961 &base_vha->dpc_flags))) { 6962 base_vha->flags.online = 1; 6963 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6964 "ISP abort scheduled.\n"); 6965 if (ha->isp_ops->abort_isp(base_vha)) { 6966 /* failed. retry later */ 6967 set_bit(ISP_ABORT_NEEDED, 6968 &base_vha->dpc_flags); 6969 } 6970 clear_bit(ABORT_ISP_ACTIVE, 6971 &base_vha->dpc_flags); 6972 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6973 "ISP abort end.\n"); 6974 } 6975 } 6976 6977 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6978 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6979 qla24xx_process_purex_list 6980 (&base_vha->purex_list); 6981 clear_bit(PROCESS_PUREX_IOCB, 6982 &base_vha->dpc_flags); 6983 } 6984 } 6985 6986 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6987 &base_vha->dpc_flags)) { 6988 qla2x00_update_fcports(base_vha); 6989 } 6990 6991 if (IS_QLAFX00(ha)) 6992 goto loop_resync_check; 6993 6994 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6995 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6996 "Quiescence mode scheduled.\n"); 6997 if (IS_P3P_TYPE(ha)) { 6998 if (IS_QLA82XX(ha)) 6999 qla82xx_device_state_handler(base_vha); 7000 if (IS_QLA8044(ha)) 7001 qla8044_device_state_handler(base_vha); 7002 clear_bit(ISP_QUIESCE_NEEDED, 7003 &base_vha->dpc_flags); 7004 if (!ha->flags.quiesce_owner) { 7005 qla2x00_perform_loop_resync(base_vha); 7006 if (IS_QLA82XX(ha)) { 7007 qla82xx_idc_lock(ha); 7008 qla82xx_clear_qsnt_ready( 7009 base_vha); 7010 qla82xx_idc_unlock(ha); 7011 } else if (IS_QLA8044(ha)) { 7012 qla8044_idc_lock(ha); 7013 qla8044_clear_qsnt_ready( 7014 base_vha); 7015 qla8044_idc_unlock(ha); 7016 } 7017 } 7018 } else { 7019 clear_bit(ISP_QUIESCE_NEEDED, 7020 &base_vha->dpc_flags); 7021 qla2x00_quiesce_io(base_vha); 7022 } 7023 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7024 "Quiescence mode end.\n"); 7025 } 7026 7027 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7028 &base_vha->dpc_flags) && 7029 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7030 7031 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7032 "Reset marker scheduled.\n"); 7033 qla2x00_rst_aen(base_vha); 7034 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7035 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7036 "Reset marker end.\n"); 7037 } 7038 7039 /* Retry each device up to login retry count */ 7040 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7041 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7042 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7043 7044 if (!base_vha->relogin_jif || 7045 time_after_eq(jiffies, base_vha->relogin_jif)) { 7046 base_vha->relogin_jif = jiffies + HZ; 7047 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7048 7049 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7050 "Relogin scheduled.\n"); 7051 qla24xx_post_relogin_work(base_vha); 7052 } 7053 } 7054 loop_resync_check: 7055 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 7056 &base_vha->dpc_flags)) { 7057 7058 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7059 "Loop resync scheduled.\n"); 7060 7061 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7062 &base_vha->dpc_flags))) { 7063 7064 qla2x00_loop_resync(base_vha); 7065 7066 clear_bit(LOOP_RESYNC_ACTIVE, 7067 &base_vha->dpc_flags); 7068 } 7069 7070 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7071 "Loop resync end.\n"); 7072 } 7073 7074 if (IS_QLAFX00(ha)) 7075 goto intr_on_check; 7076 7077 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7078 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7079 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7080 qla2xxx_flash_npiv_conf(base_vha); 7081 } 7082 7083 intr_on_check: 7084 if (!ha->interrupts_on) 7085 ha->isp_ops->enable_intrs(ha); 7086 7087 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7088 &base_vha->dpc_flags)) { 7089 if (ha->beacon_blink_led == 1) 7090 ha->isp_ops->beacon_blink(base_vha); 7091 } 7092 7093 /* qpair online check */ 7094 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7095 &base_vha->dpc_flags)) { 7096 if (ha->flags.eeh_busy || 7097 ha->flags.pci_channel_io_perm_failure) 7098 online = 0; 7099 else 7100 online = 1; 7101 7102 mutex_lock(&ha->mq_lock); 7103 list_for_each_entry(qpair, &base_vha->qp_list, 7104 qp_list_elem) 7105 qpair->online = online; 7106 mutex_unlock(&ha->mq_lock); 7107 } 7108 7109 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7110 &base_vha->dpc_flags)) { 7111 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7112 7113 if (threshold > ha->orig_fw_xcb_count) 7114 threshold = ha->orig_fw_xcb_count; 7115 7116 ql_log(ql_log_info, base_vha, 0xffffff, 7117 "SET ZIO Activity exchange threshold to %d.\n", 7118 threshold); 7119 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7120 ql_log(ql_log_info, base_vha, 0xffffff, 7121 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7122 threshold); 7123 } 7124 } 7125 7126 if (!IS_QLAFX00(ha)) 7127 qla2x00_do_dpc_all_vps(base_vha); 7128 7129 if (test_and_clear_bit(N2N_LINK_RESET, 7130 &base_vha->dpc_flags)) { 7131 qla2x00_lip_reset(base_vha); 7132 } 7133 7134 ha->dpc_active = 0; 7135 end_loop: 7136 set_current_state(TASK_INTERRUPTIBLE); 7137 } /* End of while(1) */ 7138 __set_current_state(TASK_RUNNING); 7139 7140 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7141 "DPC handler exiting.\n"); 7142 7143 /* 7144 * Make sure that nobody tries to wake us up again. 7145 */ 7146 ha->dpc_active = 0; 7147 7148 /* Cleanup any residual CTX SRBs. */ 7149 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7150 7151 return 0; 7152 } 7153 7154 void 7155 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7156 { 7157 struct qla_hw_data *ha = vha->hw; 7158 struct task_struct *t = ha->dpc_thread; 7159 7160 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7161 wake_up_process(t); 7162 } 7163 7164 /* 7165 * qla2x00_rst_aen 7166 * Processes asynchronous reset. 7167 * 7168 * Input: 7169 * ha = adapter block pointer. 7170 */ 7171 static void 7172 qla2x00_rst_aen(scsi_qla_host_t *vha) 7173 { 7174 if (vha->flags.online && !vha->flags.reset_active && 7175 !atomic_read(&vha->loop_down_timer) && 7176 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7177 do { 7178 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7179 7180 /* 7181 * Issue marker command only when we are going to start 7182 * the I/O. 7183 */ 7184 vha->marker_needed = 1; 7185 } while (!atomic_read(&vha->loop_down_timer) && 7186 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7187 } 7188 } 7189 7190 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7191 { 7192 struct qla_hw_data *ha = vha->hw; 7193 u32 cmpl_cnt; 7194 u16 i; 7195 bool do_heartbeat = false; 7196 7197 /* 7198 * Allow do_heartbeat only if we don’t have any active interrupts, 7199 * but there are still IOs outstanding with firmware. 7200 */ 7201 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7202 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7203 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7204 do_heartbeat = true; 7205 goto skip; 7206 } 7207 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7208 7209 for (i = 0; i < ha->max_qpairs; i++) { 7210 if (ha->queue_pair_map[i]) { 7211 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7212 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7213 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7214 do_heartbeat = true; 7215 break; 7216 } 7217 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7218 } 7219 } 7220 7221 skip: 7222 return do_heartbeat; 7223 } 7224 7225 static void qla_heart_beat(struct scsi_qla_host *vha) 7226 { 7227 struct qla_hw_data *ha = vha->hw; 7228 7229 if (vha->vp_idx) 7230 return; 7231 7232 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7233 return; 7234 7235 if (qla_do_heartbeat(vha)) 7236 queue_work(ha->wq, &ha->heartbeat_work); 7237 } 7238 7239 /************************************************************************** 7240 * qla2x00_timer 7241 * 7242 * Description: 7243 * One second timer 7244 * 7245 * Context: Interrupt 7246 ***************************************************************************/ 7247 void 7248 qla2x00_timer(struct timer_list *t) 7249 { 7250 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7251 unsigned long cpu_flags = 0; 7252 int start_dpc = 0; 7253 int index; 7254 srb_t *sp; 7255 uint16_t w; 7256 struct qla_hw_data *ha = vha->hw; 7257 struct req_que *req; 7258 unsigned long flags; 7259 fc_port_t *fcport = NULL; 7260 7261 if (ha->flags.eeh_busy) { 7262 ql_dbg(ql_dbg_timer, vha, 0x6000, 7263 "EEH = %d, restarting timer.\n", 7264 ha->flags.eeh_busy); 7265 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7266 return; 7267 } 7268 7269 /* 7270 * Hardware read to raise pending EEH errors during mailbox waits. If 7271 * the read returns -1 then disable the board. 7272 */ 7273 if (!pci_channel_offline(ha->pdev)) { 7274 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7275 qla2x00_check_reg16_for_disconnect(vha, w); 7276 } 7277 7278 /* Make sure qla82xx_watchdog is run only for physical port */ 7279 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7280 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7281 start_dpc++; 7282 if (IS_QLA82XX(ha)) 7283 qla82xx_watchdog(vha); 7284 else if (IS_QLA8044(ha)) 7285 qla8044_watchdog(vha); 7286 } 7287 7288 if (!vha->vp_idx && IS_QLAFX00(ha)) 7289 qlafx00_timer_routine(vha); 7290 7291 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7292 vha->link_down_time++; 7293 7294 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7295 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7296 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7297 fcport->tgt_link_down_time++; 7298 } 7299 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7300 7301 /* Loop down handler. */ 7302 if (atomic_read(&vha->loop_down_timer) > 0 && 7303 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7304 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7305 && vha->flags.online) { 7306 7307 if (atomic_read(&vha->loop_down_timer) == 7308 vha->loop_down_abort_time) { 7309 7310 ql_log(ql_log_info, vha, 0x6008, 7311 "Loop down - aborting the queues before time expires.\n"); 7312 7313 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7314 atomic_set(&vha->loop_state, LOOP_DEAD); 7315 7316 /* 7317 * Schedule an ISP abort to return any FCP2-device 7318 * commands. 7319 */ 7320 /* NPIV - scan physical port only */ 7321 if (!vha->vp_idx) { 7322 spin_lock_irqsave(&ha->hardware_lock, 7323 cpu_flags); 7324 req = ha->req_q_map[0]; 7325 for (index = 1; 7326 index < req->num_outstanding_cmds; 7327 index++) { 7328 fc_port_t *sfcp; 7329 7330 sp = req->outstanding_cmds[index]; 7331 if (!sp) 7332 continue; 7333 if (sp->cmd_type != TYPE_SRB) 7334 continue; 7335 if (sp->type != SRB_SCSI_CMD) 7336 continue; 7337 sfcp = sp->fcport; 7338 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7339 continue; 7340 7341 if (IS_QLA82XX(ha)) 7342 set_bit(FCOE_CTX_RESET_NEEDED, 7343 &vha->dpc_flags); 7344 else 7345 set_bit(ISP_ABORT_NEEDED, 7346 &vha->dpc_flags); 7347 break; 7348 } 7349 spin_unlock_irqrestore(&ha->hardware_lock, 7350 cpu_flags); 7351 } 7352 start_dpc++; 7353 } 7354 7355 /* if the loop has been down for 4 minutes, reinit adapter */ 7356 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7357 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7358 ql_log(ql_log_warn, vha, 0x6009, 7359 "Loop down - aborting ISP.\n"); 7360 7361 if (IS_QLA82XX(ha)) 7362 set_bit(FCOE_CTX_RESET_NEEDED, 7363 &vha->dpc_flags); 7364 else 7365 set_bit(ISP_ABORT_NEEDED, 7366 &vha->dpc_flags); 7367 } 7368 } 7369 ql_dbg(ql_dbg_timer, vha, 0x600a, 7370 "Loop down - seconds remaining %d.\n", 7371 atomic_read(&vha->loop_down_timer)); 7372 } 7373 /* Check if beacon LED needs to be blinked for physical host only */ 7374 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7375 /* There is no beacon_blink function for ISP82xx */ 7376 if (!IS_P3P_TYPE(ha)) { 7377 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7378 start_dpc++; 7379 } 7380 } 7381 7382 /* check if edif running */ 7383 if (vha->hw->flags.edif_enabled) 7384 qla_edif_timer(vha); 7385 7386 /* Process any deferred work. */ 7387 if (!list_empty(&vha->work_list)) { 7388 unsigned long flags; 7389 bool q = false; 7390 7391 spin_lock_irqsave(&vha->work_lock, flags); 7392 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7393 q = true; 7394 spin_unlock_irqrestore(&vha->work_lock, flags); 7395 if (q) 7396 queue_work(vha->hw->wq, &vha->iocb_work); 7397 } 7398 7399 /* 7400 * FC-NVME 7401 * see if the active AEN count has changed from what was last reported. 7402 */ 7403 index = atomic_read(&ha->nvme_active_aen_cnt); 7404 if (!vha->vp_idx && 7405 (index != ha->nvme_last_rptd_aen) && 7406 ha->zio_mode == QLA_ZIO_MODE_6 && 7407 !ha->flags.host_shutting_down) { 7408 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7409 ql_log(ql_log_info, vha, 0x3002, 7410 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7411 ha->nvme_last_rptd_aen); 7412 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7413 start_dpc++; 7414 } 7415 7416 if (!vha->vp_idx && 7417 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7418 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7419 ql_log(ql_log_info, vha, 0x3002, 7420 "Sched: Set ZIO exchange threshold to %d.\n", 7421 ha->last_zio_threshold); 7422 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7423 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7424 start_dpc++; 7425 } 7426 7427 /* Schedule the DPC routine if needed */ 7428 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7429 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7430 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7431 start_dpc || 7432 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7433 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7434 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7435 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7436 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7437 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7438 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7439 ql_dbg(ql_dbg_timer, vha, 0x600b, 7440 "isp_abort_needed=%d loop_resync_needed=%d " 7441 "fcport_update_needed=%d start_dpc=%d " 7442 "reset_marker_needed=%d", 7443 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7444 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7445 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7446 start_dpc, 7447 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7448 ql_dbg(ql_dbg_timer, vha, 0x600c, 7449 "beacon_blink_needed=%d isp_unrecoverable=%d " 7450 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7451 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7452 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7453 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7454 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7455 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7456 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7457 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7458 qla2xxx_wake_dpc(vha); 7459 } 7460 7461 qla_heart_beat(vha); 7462 7463 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7464 } 7465 7466 /* Firmware interface routines. */ 7467 7468 #define FW_ISP21XX 0 7469 #define FW_ISP22XX 1 7470 #define FW_ISP2300 2 7471 #define FW_ISP2322 3 7472 #define FW_ISP24XX 4 7473 #define FW_ISP25XX 5 7474 #define FW_ISP81XX 6 7475 #define FW_ISP82XX 7 7476 #define FW_ISP2031 8 7477 #define FW_ISP8031 9 7478 #define FW_ISP27XX 10 7479 #define FW_ISP28XX 11 7480 7481 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7482 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7483 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7484 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7485 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7486 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7487 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7488 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7489 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7490 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7491 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7492 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7493 7494 7495 static DEFINE_MUTEX(qla_fw_lock); 7496 7497 static struct fw_blob qla_fw_blobs[] = { 7498 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7499 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7500 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7501 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7502 { .name = FW_FILE_ISP24XX, }, 7503 { .name = FW_FILE_ISP25XX, }, 7504 { .name = FW_FILE_ISP81XX, }, 7505 { .name = FW_FILE_ISP82XX, }, 7506 { .name = FW_FILE_ISP2031, }, 7507 { .name = FW_FILE_ISP8031, }, 7508 { .name = FW_FILE_ISP27XX, }, 7509 { .name = FW_FILE_ISP28XX, }, 7510 { .name = NULL, }, 7511 }; 7512 7513 struct fw_blob * 7514 qla2x00_request_firmware(scsi_qla_host_t *vha) 7515 { 7516 struct qla_hw_data *ha = vha->hw; 7517 struct fw_blob *blob; 7518 7519 if (IS_QLA2100(ha)) { 7520 blob = &qla_fw_blobs[FW_ISP21XX]; 7521 } else if (IS_QLA2200(ha)) { 7522 blob = &qla_fw_blobs[FW_ISP22XX]; 7523 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7524 blob = &qla_fw_blobs[FW_ISP2300]; 7525 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7526 blob = &qla_fw_blobs[FW_ISP2322]; 7527 } else if (IS_QLA24XX_TYPE(ha)) { 7528 blob = &qla_fw_blobs[FW_ISP24XX]; 7529 } else if (IS_QLA25XX(ha)) { 7530 blob = &qla_fw_blobs[FW_ISP25XX]; 7531 } else if (IS_QLA81XX(ha)) { 7532 blob = &qla_fw_blobs[FW_ISP81XX]; 7533 } else if (IS_QLA82XX(ha)) { 7534 blob = &qla_fw_blobs[FW_ISP82XX]; 7535 } else if (IS_QLA2031(ha)) { 7536 blob = &qla_fw_blobs[FW_ISP2031]; 7537 } else if (IS_QLA8031(ha)) { 7538 blob = &qla_fw_blobs[FW_ISP8031]; 7539 } else if (IS_QLA27XX(ha)) { 7540 blob = &qla_fw_blobs[FW_ISP27XX]; 7541 } else if (IS_QLA28XX(ha)) { 7542 blob = &qla_fw_blobs[FW_ISP28XX]; 7543 } else { 7544 return NULL; 7545 } 7546 7547 if (!blob->name) 7548 return NULL; 7549 7550 mutex_lock(&qla_fw_lock); 7551 if (blob->fw) 7552 goto out; 7553 7554 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7555 ql_log(ql_log_warn, vha, 0x0063, 7556 "Failed to load firmware image (%s).\n", blob->name); 7557 blob->fw = NULL; 7558 blob = NULL; 7559 } 7560 7561 out: 7562 mutex_unlock(&qla_fw_lock); 7563 return blob; 7564 } 7565 7566 static void 7567 qla2x00_release_firmware(void) 7568 { 7569 struct fw_blob *blob; 7570 7571 mutex_lock(&qla_fw_lock); 7572 for (blob = qla_fw_blobs; blob->name; blob++) 7573 release_firmware(blob->fw); 7574 mutex_unlock(&qla_fw_lock); 7575 } 7576 7577 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7578 { 7579 struct qla_hw_data *ha = vha->hw; 7580 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7581 struct qla_qpair *qpair = NULL; 7582 struct scsi_qla_host *vp, *tvp; 7583 fc_port_t *fcport; 7584 int i; 7585 unsigned long flags; 7586 7587 ql_dbg(ql_dbg_aer, vha, 0x9000, 7588 "%s\n", __func__); 7589 ha->chip_reset++; 7590 7591 ha->base_qpair->chip_reset = ha->chip_reset; 7592 for (i = 0; i < ha->max_qpairs; i++) { 7593 if (ha->queue_pair_map[i]) 7594 ha->queue_pair_map[i]->chip_reset = 7595 ha->base_qpair->chip_reset; 7596 } 7597 7598 /* 7599 * purge mailbox might take a while. Slot Reset/chip reset 7600 * will take care of the purge 7601 */ 7602 7603 mutex_lock(&ha->mq_lock); 7604 ha->base_qpair->online = 0; 7605 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7606 qpair->online = 0; 7607 wmb(); 7608 mutex_unlock(&ha->mq_lock); 7609 7610 qla2x00_mark_all_devices_lost(vha); 7611 7612 spin_lock_irqsave(&ha->vport_slock, flags); 7613 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7614 atomic_inc(&vp->vref_count); 7615 spin_unlock_irqrestore(&ha->vport_slock, flags); 7616 qla2x00_mark_all_devices_lost(vp); 7617 spin_lock_irqsave(&ha->vport_slock, flags); 7618 atomic_dec(&vp->vref_count); 7619 } 7620 spin_unlock_irqrestore(&ha->vport_slock, flags); 7621 7622 /* Clear all async request states across all VPs. */ 7623 list_for_each_entry(fcport, &vha->vp_fcports, list) 7624 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7625 7626 spin_lock_irqsave(&ha->vport_slock, flags); 7627 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7628 atomic_inc(&vp->vref_count); 7629 spin_unlock_irqrestore(&ha->vport_slock, flags); 7630 list_for_each_entry(fcport, &vp->vp_fcports, list) 7631 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7632 spin_lock_irqsave(&ha->vport_slock, flags); 7633 atomic_dec(&vp->vref_count); 7634 } 7635 spin_unlock_irqrestore(&ha->vport_slock, flags); 7636 } 7637 7638 7639 static pci_ers_result_t 7640 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7641 { 7642 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7643 struct qla_hw_data *ha = vha->hw; 7644 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7645 7646 ql_log(ql_log_warn, vha, 0x9000, 7647 "PCI error detected, state %x.\n", state); 7648 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7649 7650 if (!atomic_read(&pdev->enable_cnt)) { 7651 ql_log(ql_log_info, vha, 0xffff, 7652 "PCI device is disabled,state %x\n", state); 7653 ret = PCI_ERS_RESULT_NEED_RESET; 7654 goto out; 7655 } 7656 7657 switch (state) { 7658 case pci_channel_io_normal: 7659 ha->flags.eeh_busy = 0; 7660 if (ql2xmqsupport || ql2xnvmeenable) { 7661 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7662 qla2xxx_wake_dpc(vha); 7663 } 7664 ret = PCI_ERS_RESULT_CAN_RECOVER; 7665 break; 7666 case pci_channel_io_frozen: 7667 qla_pci_set_eeh_busy(vha); 7668 ret = PCI_ERS_RESULT_NEED_RESET; 7669 break; 7670 case pci_channel_io_perm_failure: 7671 ha->flags.pci_channel_io_perm_failure = 1; 7672 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7673 if (ql2xmqsupport || ql2xnvmeenable) { 7674 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7675 qla2xxx_wake_dpc(vha); 7676 } 7677 ret = PCI_ERS_RESULT_DISCONNECT; 7678 } 7679 out: 7680 ql_dbg(ql_dbg_aer, vha, 0x600d, 7681 "PCI error detected returning [%x].\n", ret); 7682 return ret; 7683 } 7684 7685 static pci_ers_result_t 7686 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7687 { 7688 int risc_paused = 0; 7689 uint32_t stat; 7690 unsigned long flags; 7691 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7692 struct qla_hw_data *ha = base_vha->hw; 7693 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7694 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7695 7696 ql_log(ql_log_warn, base_vha, 0x9000, 7697 "mmio enabled\n"); 7698 7699 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7700 if (IS_QLA82XX(ha)) 7701 return PCI_ERS_RESULT_RECOVERED; 7702 7703 spin_lock_irqsave(&ha->hardware_lock, flags); 7704 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7705 stat = rd_reg_word(®->hccr); 7706 if (stat & HCCR_RISC_PAUSE) 7707 risc_paused = 1; 7708 } else if (IS_QLA23XX(ha)) { 7709 stat = rd_reg_dword(®->u.isp2300.host_status); 7710 if (stat & HSR_RISC_PAUSED) 7711 risc_paused = 1; 7712 } else if (IS_FWI2_CAPABLE(ha)) { 7713 stat = rd_reg_dword(®24->host_status); 7714 if (stat & HSRX_RISC_PAUSED) 7715 risc_paused = 1; 7716 } 7717 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7718 7719 if (risc_paused) { 7720 ql_log(ql_log_info, base_vha, 0x9003, 7721 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7722 qla2xxx_dump_fw(base_vha); 7723 } 7724 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7725 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7726 "mmio enabled returning.\n"); 7727 return PCI_ERS_RESULT_NEED_RESET; 7728 } 7729 7730 static pci_ers_result_t 7731 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7732 { 7733 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7734 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7735 struct qla_hw_data *ha = base_vha->hw; 7736 int rc; 7737 struct qla_qpair *qpair = NULL; 7738 7739 ql_log(ql_log_warn, base_vha, 0x9004, 7740 "Slot Reset.\n"); 7741 7742 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7743 /* Workaround: qla2xxx driver which access hardware earlier 7744 * needs error state to be pci_channel_io_online. 7745 * Otherwise mailbox command timesout. 7746 */ 7747 pdev->error_state = pci_channel_io_normal; 7748 7749 pci_restore_state(pdev); 7750 7751 /* pci_restore_state() clears the saved_state flag of the device 7752 * save restored state which resets saved_state flag 7753 */ 7754 pci_save_state(pdev); 7755 7756 if (ha->mem_only) 7757 rc = pci_enable_device_mem(pdev); 7758 else 7759 rc = pci_enable_device(pdev); 7760 7761 if (rc) { 7762 ql_log(ql_log_warn, base_vha, 0x9005, 7763 "Can't re-enable PCI device after reset.\n"); 7764 goto exit_slot_reset; 7765 } 7766 7767 7768 if (ha->isp_ops->pci_config(base_vha)) 7769 goto exit_slot_reset; 7770 7771 mutex_lock(&ha->mq_lock); 7772 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7773 qpair->online = 1; 7774 mutex_unlock(&ha->mq_lock); 7775 7776 ha->flags.eeh_busy = 0; 7777 base_vha->flags.online = 1; 7778 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7779 ha->isp_ops->abort_isp(base_vha); 7780 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7781 7782 if (qla2x00_isp_reg_stat(ha)) { 7783 ha->flags.eeh_busy = 1; 7784 qla_pci_error_cleanup(base_vha); 7785 ql_log(ql_log_warn, base_vha, 0x9005, 7786 "Device unable to recover from PCI error.\n"); 7787 } else { 7788 ret = PCI_ERS_RESULT_RECOVERED; 7789 } 7790 7791 exit_slot_reset: 7792 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7793 "Slot Reset returning %x.\n", ret); 7794 7795 return ret; 7796 } 7797 7798 static void 7799 qla2xxx_pci_resume(struct pci_dev *pdev) 7800 { 7801 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7802 struct qla_hw_data *ha = base_vha->hw; 7803 int ret; 7804 7805 ql_log(ql_log_warn, base_vha, 0x900f, 7806 "Pci Resume.\n"); 7807 7808 7809 ret = qla2x00_wait_for_hba_online(base_vha); 7810 if (ret != QLA_SUCCESS) { 7811 ql_log(ql_log_fatal, base_vha, 0x9002, 7812 "The device failed to resume I/O from slot/link_reset.\n"); 7813 } 7814 ha->pci_error_state = QLA_PCI_RESUME; 7815 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7816 "Pci Resume returning.\n"); 7817 } 7818 7819 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7820 { 7821 struct qla_hw_data *ha = vha->hw; 7822 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7823 bool do_cleanup = false; 7824 unsigned long flags; 7825 7826 if (ha->flags.eeh_busy) 7827 return; 7828 7829 spin_lock_irqsave(&base_vha->work_lock, flags); 7830 if (!ha->flags.eeh_busy) { 7831 ha->flags.eeh_busy = 1; 7832 do_cleanup = true; 7833 } 7834 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7835 7836 if (do_cleanup) 7837 qla_pci_error_cleanup(base_vha); 7838 } 7839 7840 /* 7841 * this routine will schedule a task to pause IO from interrupt context 7842 * if caller sees a PCIE error event (register read = 0xf's) 7843 */ 7844 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7845 { 7846 struct qla_hw_data *ha = vha->hw; 7847 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7848 7849 if (ha->flags.eeh_busy) 7850 return; 7851 7852 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7853 qla2xxx_wake_dpc(base_vha); 7854 } 7855 7856 static void 7857 qla_pci_reset_prepare(struct pci_dev *pdev) 7858 { 7859 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7860 struct qla_hw_data *ha = base_vha->hw; 7861 struct qla_qpair *qpair; 7862 7863 ql_log(ql_log_warn, base_vha, 0xffff, 7864 "%s.\n", __func__); 7865 7866 /* 7867 * PCI FLR/function reset is about to reset the 7868 * slot. Stop the chip to stop all DMA access. 7869 * It is assumed that pci_reset_done will be called 7870 * after FLR to resume Chip operation. 7871 */ 7872 ha->flags.eeh_busy = 1; 7873 mutex_lock(&ha->mq_lock); 7874 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7875 qpair->online = 0; 7876 mutex_unlock(&ha->mq_lock); 7877 7878 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7879 qla2x00_abort_isp_cleanup(base_vha); 7880 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7881 } 7882 7883 static void 7884 qla_pci_reset_done(struct pci_dev *pdev) 7885 { 7886 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7887 struct qla_hw_data *ha = base_vha->hw; 7888 struct qla_qpair *qpair; 7889 7890 ql_log(ql_log_warn, base_vha, 0xffff, 7891 "%s.\n", __func__); 7892 7893 /* 7894 * FLR just completed by PCI layer. Resume adapter 7895 */ 7896 ha->flags.eeh_busy = 0; 7897 mutex_lock(&ha->mq_lock); 7898 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7899 qpair->online = 1; 7900 mutex_unlock(&ha->mq_lock); 7901 7902 base_vha->flags.online = 1; 7903 ha->isp_ops->abort_isp(base_vha); 7904 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7905 } 7906 7907 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7908 { 7909 int rc; 7910 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7911 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7912 7913 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7914 rc = blk_mq_map_queues(qmap); 7915 else 7916 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7917 return rc; 7918 } 7919 7920 struct scsi_host_template qla2xxx_driver_template = { 7921 .module = THIS_MODULE, 7922 .name = QLA2XXX_DRIVER_NAME, 7923 .queuecommand = qla2xxx_queuecommand, 7924 7925 .eh_timed_out = fc_eh_timed_out, 7926 .eh_abort_handler = qla2xxx_eh_abort, 7927 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 7928 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7929 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7930 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7931 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7932 7933 .slave_configure = qla2xxx_slave_configure, 7934 7935 .slave_alloc = qla2xxx_slave_alloc, 7936 .slave_destroy = qla2xxx_slave_destroy, 7937 .scan_finished = qla2xxx_scan_finished, 7938 .scan_start = qla2xxx_scan_start, 7939 .change_queue_depth = scsi_change_queue_depth, 7940 .map_queues = qla2xxx_map_queues, 7941 .this_id = -1, 7942 .cmd_per_lun = 3, 7943 .sg_tablesize = SG_ALL, 7944 7945 .max_sectors = 0xFFFF, 7946 .shost_groups = qla2x00_host_groups, 7947 7948 .supported_mode = MODE_INITIATOR, 7949 .track_queue_depth = 1, 7950 .cmd_size = sizeof(srb_t), 7951 }; 7952 7953 static const struct pci_error_handlers qla2xxx_err_handler = { 7954 .error_detected = qla2xxx_pci_error_detected, 7955 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7956 .slot_reset = qla2xxx_pci_slot_reset, 7957 .resume = qla2xxx_pci_resume, 7958 .reset_prepare = qla_pci_reset_prepare, 7959 .reset_done = qla_pci_reset_done, 7960 }; 7961 7962 static struct pci_device_id qla2xxx_pci_tbl[] = { 7963 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7964 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7965 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7966 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7967 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7968 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7969 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7970 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7971 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7972 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7973 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7974 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7975 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7976 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7985 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7986 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7987 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7988 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7989 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7990 { 0 }, 7991 }; 7992 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7993 7994 static struct pci_driver qla2xxx_pci_driver = { 7995 .name = QLA2XXX_DRIVER_NAME, 7996 .driver = { 7997 .owner = THIS_MODULE, 7998 }, 7999 .id_table = qla2xxx_pci_tbl, 8000 .probe = qla2x00_probe_one, 8001 .remove = qla2x00_remove_one, 8002 .shutdown = qla2x00_shutdown, 8003 .err_handler = &qla2xxx_err_handler, 8004 }; 8005 8006 static const struct file_operations apidev_fops = { 8007 .owner = THIS_MODULE, 8008 .llseek = noop_llseek, 8009 }; 8010 8011 /** 8012 * qla2x00_module_init - Module initialization. 8013 **/ 8014 static int __init 8015 qla2x00_module_init(void) 8016 { 8017 int ret = 0; 8018 8019 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8020 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8021 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8022 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8023 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8024 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8025 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8026 BUILD_BUG_ON(sizeof(request_t) != 64); 8027 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8028 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8029 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8030 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8031 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8032 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8033 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8034 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8035 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8036 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8037 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8038 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8039 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8040 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8041 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8042 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8043 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8044 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8045 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8046 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8047 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8048 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8049 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8050 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8051 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8052 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8053 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8054 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8055 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8056 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8057 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8058 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8059 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8060 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8061 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8062 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8063 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8064 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8065 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8066 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8067 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8068 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8069 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8070 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8071 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8072 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8073 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8074 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8075 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8076 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8077 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8078 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8079 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8080 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8081 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8082 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8083 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8084 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8085 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8086 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8087 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8088 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8089 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8090 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8091 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8092 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8093 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8094 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8095 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8096 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8097 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8098 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8099 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8100 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8101 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8102 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8103 8104 /* Allocate cache for SRBs. */ 8105 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8106 SLAB_HWCACHE_ALIGN, NULL); 8107 if (srb_cachep == NULL) { 8108 ql_log(ql_log_fatal, NULL, 0x0001, 8109 "Unable to allocate SRB cache...Failing load!.\n"); 8110 return -ENOMEM; 8111 } 8112 8113 /* Initialize target kmem_cache and mem_pools */ 8114 ret = qlt_init(); 8115 if (ret < 0) { 8116 goto destroy_cache; 8117 } else if (ret > 0) { 8118 /* 8119 * If initiator mode is explictly disabled by qlt_init(), 8120 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8121 * performing scsi_scan_target() during LOOP UP event. 8122 */ 8123 qla2xxx_transport_functions.disable_target_scan = 1; 8124 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8125 } 8126 8127 /* Derive version string. */ 8128 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8129 if (ql2xextended_error_logging) 8130 strcat(qla2x00_version_str, "-debug"); 8131 if (ql2xextended_error_logging == 1) 8132 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8133 8134 qla2xxx_transport_template = 8135 fc_attach_transport(&qla2xxx_transport_functions); 8136 if (!qla2xxx_transport_template) { 8137 ql_log(ql_log_fatal, NULL, 0x0002, 8138 "fc_attach_transport failed...Failing load!.\n"); 8139 ret = -ENODEV; 8140 goto qlt_exit; 8141 } 8142 8143 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8144 if (apidev_major < 0) { 8145 ql_log(ql_log_fatal, NULL, 0x0003, 8146 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8147 } 8148 8149 qla2xxx_transport_vport_template = 8150 fc_attach_transport(&qla2xxx_transport_vport_functions); 8151 if (!qla2xxx_transport_vport_template) { 8152 ql_log(ql_log_fatal, NULL, 0x0004, 8153 "fc_attach_transport vport failed...Failing load!.\n"); 8154 ret = -ENODEV; 8155 goto unreg_chrdev; 8156 } 8157 ql_log(ql_log_info, NULL, 0x0005, 8158 "QLogic Fibre Channel HBA Driver: %s.\n", 8159 qla2x00_version_str); 8160 ret = pci_register_driver(&qla2xxx_pci_driver); 8161 if (ret) { 8162 ql_log(ql_log_fatal, NULL, 0x0006, 8163 "pci_register_driver failed...ret=%d Failing load!.\n", 8164 ret); 8165 goto release_vport_transport; 8166 } 8167 return ret; 8168 8169 release_vport_transport: 8170 fc_release_transport(qla2xxx_transport_vport_template); 8171 8172 unreg_chrdev: 8173 if (apidev_major >= 0) 8174 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8175 fc_release_transport(qla2xxx_transport_template); 8176 8177 qlt_exit: 8178 qlt_exit(); 8179 8180 destroy_cache: 8181 kmem_cache_destroy(srb_cachep); 8182 return ret; 8183 } 8184 8185 /** 8186 * qla2x00_module_exit - Module cleanup. 8187 **/ 8188 static void __exit 8189 qla2x00_module_exit(void) 8190 { 8191 pci_unregister_driver(&qla2xxx_pci_driver); 8192 qla2x00_release_firmware(); 8193 kmem_cache_destroy(ctx_cachep); 8194 fc_release_transport(qla2xxx_transport_vport_template); 8195 if (apidev_major >= 0) 8196 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8197 fc_release_transport(qla2xxx_transport_template); 8198 qlt_exit(); 8199 kmem_cache_destroy(srb_cachep); 8200 } 8201 8202 module_init(qla2x00_module_init); 8203 module_exit(qla2x00_module_exit); 8204 8205 MODULE_AUTHOR("QLogic Corporation"); 8206 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8207 MODULE_LICENSE("GPL"); 8208 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8209 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8210 MODULE_FIRMWARE(FW_FILE_ISP2300); 8211 MODULE_FIRMWARE(FW_FILE_ISP2322); 8212 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8213 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8214