1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 /* 272 * SCSI host template entry points 273 */ 274 static int qla2xxx_slave_configure(struct scsi_device * device); 275 static int qla2xxx_slave_alloc(struct scsi_device *); 276 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 277 static void qla2xxx_scan_start(struct Scsi_Host *); 278 static void qla2xxx_slave_destroy(struct scsi_device *); 279 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 280 static int qla2xxx_eh_abort(struct scsi_cmnd *); 281 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 282 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 283 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 284 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 285 286 static void qla2x00_clear_drv_active(struct qla_hw_data *); 287 static void qla2x00_free_device(scsi_qla_host_t *); 288 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 289 static int qla2xxx_map_queues(struct Scsi_Host *shost); 290 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 291 292 struct scsi_host_template qla2xxx_driver_template = { 293 .module = THIS_MODULE, 294 .name = QLA2XXX_DRIVER_NAME, 295 .queuecommand = qla2xxx_queuecommand, 296 297 .eh_timed_out = fc_eh_timed_out, 298 .eh_abort_handler = qla2xxx_eh_abort, 299 .eh_device_reset_handler = qla2xxx_eh_device_reset, 300 .eh_target_reset_handler = qla2xxx_eh_target_reset, 301 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 302 .eh_host_reset_handler = qla2xxx_eh_host_reset, 303 304 .slave_configure = qla2xxx_slave_configure, 305 306 .slave_alloc = qla2xxx_slave_alloc, 307 .slave_destroy = qla2xxx_slave_destroy, 308 .scan_finished = qla2xxx_scan_finished, 309 .scan_start = qla2xxx_scan_start, 310 .change_queue_depth = scsi_change_queue_depth, 311 .map_queues = qla2xxx_map_queues, 312 .this_id = -1, 313 .cmd_per_lun = 3, 314 .use_clustering = ENABLE_CLUSTERING, 315 .sg_tablesize = SG_ALL, 316 317 .max_sectors = 0xFFFF, 318 .shost_attrs = qla2x00_host_attrs, 319 320 .supported_mode = MODE_INITIATOR, 321 .track_queue_depth = 1, 322 }; 323 324 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 325 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 326 327 /* TODO Convert to inlines 328 * 329 * Timer routines 330 */ 331 332 __inline__ void 333 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 334 { 335 init_timer(&vha->timer); 336 vha->timer.expires = jiffies + interval * HZ; 337 vha->timer.data = (unsigned long)vha; 338 vha->timer.function = (void (*)(unsigned long))func; 339 add_timer(&vha->timer); 340 vha->timer_active = 1; 341 } 342 343 static inline void 344 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 345 { 346 /* Currently used for 82XX only. */ 347 if (vha->device_flags & DFLG_DEV_FAILED) { 348 ql_dbg(ql_dbg_timer, vha, 0x600d, 349 "Device in a failed state, returning.\n"); 350 return; 351 } 352 353 mod_timer(&vha->timer, jiffies + interval * HZ); 354 } 355 356 static __inline__ void 357 qla2x00_stop_timer(scsi_qla_host_t *vha) 358 { 359 del_timer_sync(&vha->timer); 360 vha->timer_active = 0; 361 } 362 363 static int qla2x00_do_dpc(void *data); 364 365 static void qla2x00_rst_aen(scsi_qla_host_t *); 366 367 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 368 struct req_que **, struct rsp_que **); 369 static void qla2x00_free_fw_dump(struct qla_hw_data *); 370 static void qla2x00_mem_free(struct qla_hw_data *); 371 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 372 struct qla_qpair *qpair); 373 374 /* -------------------------------------------------------------------------- */ 375 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 376 struct rsp_que *rsp) 377 { 378 struct qla_hw_data *ha = vha->hw; 379 rsp->qpair = ha->base_qpair; 380 rsp->req = req; 381 ha->base_qpair->req = req; 382 ha->base_qpair->rsp = rsp; 383 ha->base_qpair->vha = vha; 384 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 385 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 386 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 387 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 388 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list); 389 ha->base_qpair->enable_class_2 = ql2xenableclass2; 390 /* init qpair to this cpu. Will adjust at run time. */ 391 qla_cpu_update(rsp->qpair, smp_processor_id()); 392 ha->base_qpair->pdev = ha->pdev; 393 394 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 395 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 396 } 397 398 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 399 struct rsp_que *rsp) 400 { 401 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 402 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 403 GFP_KERNEL); 404 if (!ha->req_q_map) { 405 ql_log(ql_log_fatal, vha, 0x003b, 406 "Unable to allocate memory for request queue ptrs.\n"); 407 goto fail_req_map; 408 } 409 410 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 411 GFP_KERNEL); 412 if (!ha->rsp_q_map) { 413 ql_log(ql_log_fatal, vha, 0x003c, 414 "Unable to allocate memory for response queue ptrs.\n"); 415 goto fail_rsp_map; 416 } 417 418 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 419 if (ha->base_qpair == NULL) { 420 ql_log(ql_log_warn, vha, 0x00e0, 421 "Failed to allocate base queue pair memory.\n"); 422 goto fail_base_qpair; 423 } 424 425 qla_init_base_qpair(vha, req, rsp); 426 427 if (ql2xmqsupport && ha->max_qpairs) { 428 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 429 GFP_KERNEL); 430 if (!ha->queue_pair_map) { 431 ql_log(ql_log_fatal, vha, 0x0180, 432 "Unable to allocate memory for queue pair ptrs.\n"); 433 goto fail_qpair_map; 434 } 435 } 436 437 /* 438 * Make sure we record at least the request and response queue zero in 439 * case we need to free them if part of the probe fails. 440 */ 441 ha->rsp_q_map[0] = rsp; 442 ha->req_q_map[0] = req; 443 set_bit(0, ha->rsp_qid_map); 444 set_bit(0, ha->req_qid_map); 445 return 1; 446 447 fail_qpair_map: 448 kfree(ha->base_qpair); 449 ha->base_qpair = NULL; 450 fail_base_qpair: 451 kfree(ha->rsp_q_map); 452 ha->rsp_q_map = NULL; 453 fail_rsp_map: 454 kfree(ha->req_q_map); 455 ha->req_q_map = NULL; 456 fail_req_map: 457 return -ENOMEM; 458 } 459 460 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 461 { 462 if (IS_QLAFX00(ha)) { 463 if (req && req->ring_fx00) 464 dma_free_coherent(&ha->pdev->dev, 465 (req->length_fx00 + 1) * sizeof(request_t), 466 req->ring_fx00, req->dma_fx00); 467 } else if (req && req->ring) 468 dma_free_coherent(&ha->pdev->dev, 469 (req->length + 1) * sizeof(request_t), 470 req->ring, req->dma); 471 472 if (req) 473 kfree(req->outstanding_cmds); 474 475 kfree(req); 476 } 477 478 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 479 { 480 if (IS_QLAFX00(ha)) { 481 if (rsp && rsp->ring) 482 dma_free_coherent(&ha->pdev->dev, 483 (rsp->length_fx00 + 1) * sizeof(request_t), 484 rsp->ring_fx00, rsp->dma_fx00); 485 } else if (rsp && rsp->ring) { 486 dma_free_coherent(&ha->pdev->dev, 487 (rsp->length + 1) * sizeof(response_t), 488 rsp->ring, rsp->dma); 489 } 490 kfree(rsp); 491 } 492 493 static void qla2x00_free_queues(struct qla_hw_data *ha) 494 { 495 struct req_que *req; 496 struct rsp_que *rsp; 497 int cnt; 498 unsigned long flags; 499 500 if (ha->queue_pair_map) { 501 kfree(ha->queue_pair_map); 502 ha->queue_pair_map = NULL; 503 } 504 if (ha->base_qpair) { 505 kfree(ha->base_qpair); 506 ha->base_qpair = NULL; 507 } 508 509 spin_lock_irqsave(&ha->hardware_lock, flags); 510 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 511 if (!test_bit(cnt, ha->req_qid_map)) 512 continue; 513 514 req = ha->req_q_map[cnt]; 515 clear_bit(cnt, ha->req_qid_map); 516 ha->req_q_map[cnt] = NULL; 517 518 spin_unlock_irqrestore(&ha->hardware_lock, flags); 519 qla2x00_free_req_que(ha, req); 520 spin_lock_irqsave(&ha->hardware_lock, flags); 521 } 522 spin_unlock_irqrestore(&ha->hardware_lock, flags); 523 524 kfree(ha->req_q_map); 525 ha->req_q_map = NULL; 526 527 528 spin_lock_irqsave(&ha->hardware_lock, flags); 529 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 530 if (!test_bit(cnt, ha->rsp_qid_map)) 531 continue; 532 533 rsp = ha->rsp_q_map[cnt]; 534 clear_bit(cnt, ha->rsp_qid_map); 535 ha->rsp_q_map[cnt] = NULL; 536 spin_unlock_irqrestore(&ha->hardware_lock, flags); 537 qla2x00_free_rsp_que(ha, rsp); 538 spin_lock_irqsave(&ha->hardware_lock, flags); 539 } 540 spin_unlock_irqrestore(&ha->hardware_lock, flags); 541 542 kfree(ha->rsp_q_map); 543 ha->rsp_q_map = NULL; 544 } 545 546 static char * 547 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 548 { 549 struct qla_hw_data *ha = vha->hw; 550 static char *pci_bus_modes[] = { 551 "33", "66", "100", "133", 552 }; 553 uint16_t pci_bus; 554 555 strcpy(str, "PCI"); 556 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 557 if (pci_bus) { 558 strcat(str, "-X ("); 559 strcat(str, pci_bus_modes[pci_bus]); 560 } else { 561 pci_bus = (ha->pci_attr & BIT_8) >> 8; 562 strcat(str, " ("); 563 strcat(str, pci_bus_modes[pci_bus]); 564 } 565 strcat(str, " MHz)"); 566 567 return (str); 568 } 569 570 static char * 571 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 572 { 573 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 574 struct qla_hw_data *ha = vha->hw; 575 uint32_t pci_bus; 576 577 if (pci_is_pcie(ha->pdev)) { 578 char lwstr[6]; 579 uint32_t lstat, lspeed, lwidth; 580 581 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 582 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 583 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 584 585 strcpy(str, "PCIe ("); 586 switch (lspeed) { 587 case 1: 588 strcat(str, "2.5GT/s "); 589 break; 590 case 2: 591 strcat(str, "5.0GT/s "); 592 break; 593 case 3: 594 strcat(str, "8.0GT/s "); 595 break; 596 default: 597 strcat(str, "<unknown> "); 598 break; 599 } 600 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 601 strcat(str, lwstr); 602 603 return str; 604 } 605 606 strcpy(str, "PCI"); 607 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 608 if (pci_bus == 0 || pci_bus == 8) { 609 strcat(str, " ("); 610 strcat(str, pci_bus_modes[pci_bus >> 3]); 611 } else { 612 strcat(str, "-X "); 613 if (pci_bus & BIT_2) 614 strcat(str, "Mode 2"); 615 else 616 strcat(str, "Mode 1"); 617 strcat(str, " ("); 618 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 619 } 620 strcat(str, " MHz)"); 621 622 return str; 623 } 624 625 static char * 626 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 627 { 628 char un_str[10]; 629 struct qla_hw_data *ha = vha->hw; 630 631 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 632 ha->fw_minor_version, ha->fw_subminor_version); 633 634 if (ha->fw_attributes & BIT_9) { 635 strcat(str, "FLX"); 636 return (str); 637 } 638 639 switch (ha->fw_attributes & 0xFF) { 640 case 0x7: 641 strcat(str, "EF"); 642 break; 643 case 0x17: 644 strcat(str, "TP"); 645 break; 646 case 0x37: 647 strcat(str, "IP"); 648 break; 649 case 0x77: 650 strcat(str, "VI"); 651 break; 652 default: 653 sprintf(un_str, "(%x)", ha->fw_attributes); 654 strcat(str, un_str); 655 break; 656 } 657 if (ha->fw_attributes & 0x100) 658 strcat(str, "X"); 659 660 return (str); 661 } 662 663 static char * 664 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 665 { 666 struct qla_hw_data *ha = vha->hw; 667 668 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 669 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 670 return str; 671 } 672 673 void 674 qla2x00_sp_free_dma(void *ptr) 675 { 676 srb_t *sp = ptr; 677 struct qla_hw_data *ha = sp->vha->hw; 678 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 679 void *ctx = GET_CMD_CTX_SP(sp); 680 681 if (sp->flags & SRB_DMA_VALID) { 682 scsi_dma_unmap(cmd); 683 sp->flags &= ~SRB_DMA_VALID; 684 } 685 686 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 687 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 688 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 689 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 690 } 691 692 if (!ctx) 693 goto end; 694 695 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 696 /* List assured to be having elements */ 697 qla2x00_clean_dsd_pool(ha, ctx); 698 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 699 } 700 701 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 702 struct crc_context *ctx0 = ctx; 703 704 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 705 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 706 } 707 708 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 709 struct ct6_dsd *ctx1 = ctx; 710 711 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 712 ctx1->fcp_cmnd_dma); 713 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 714 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 715 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 716 mempool_free(ctx1, ha->ctx_mempool); 717 } 718 719 end: 720 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 721 CMD_SP(cmd) = NULL; 722 qla2x00_rel_sp(sp); 723 } 724 } 725 726 void 727 qla2x00_sp_compl(void *ptr, int res) 728 { 729 srb_t *sp = ptr; 730 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 731 732 cmd->result = res; 733 734 if (atomic_read(&sp->ref_count) == 0) { 735 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 737 sp, GET_CMD_SP(sp)); 738 if (ql2xextended_error_logging & ql_dbg_io) 739 WARN_ON(atomic_read(&sp->ref_count) == 0); 740 return; 741 } 742 if (!atomic_dec_and_test(&sp->ref_count)) 743 return; 744 745 sp->free(sp); 746 cmd->scsi_done(cmd); 747 } 748 749 void 750 qla2xxx_qpair_sp_free_dma(void *ptr) 751 { 752 srb_t *sp = (srb_t *)ptr; 753 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 754 struct qla_hw_data *ha = sp->fcport->vha->hw; 755 void *ctx = GET_CMD_CTX_SP(sp); 756 757 if (sp->flags & SRB_DMA_VALID) { 758 scsi_dma_unmap(cmd); 759 sp->flags &= ~SRB_DMA_VALID; 760 } 761 762 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 763 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 764 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 765 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 766 } 767 768 if (!ctx) 769 goto end; 770 771 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 772 /* List assured to be having elements */ 773 qla2x00_clean_dsd_pool(ha, ctx); 774 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 775 } 776 777 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 778 struct crc_context *ctx0 = ctx; 779 780 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 781 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 782 } 783 784 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 785 struct ct6_dsd *ctx1 = ctx; 786 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 787 ctx1->fcp_cmnd_dma); 788 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 789 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 790 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 791 mempool_free(ctx1, ha->ctx_mempool); 792 } 793 end: 794 CMD_SP(cmd) = NULL; 795 qla2xxx_rel_qpair_sp(sp->qpair, sp); 796 } 797 798 void 799 qla2xxx_qpair_sp_compl(void *ptr, int res) 800 { 801 srb_t *sp = ptr; 802 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 803 804 cmd->result = res; 805 806 if (atomic_read(&sp->ref_count) == 0) { 807 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 808 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 809 sp, GET_CMD_SP(sp)); 810 if (ql2xextended_error_logging & ql_dbg_io) 811 WARN_ON(atomic_read(&sp->ref_count) == 0); 812 return; 813 } 814 if (!atomic_dec_and_test(&sp->ref_count)) 815 return; 816 817 sp->free(sp); 818 cmd->scsi_done(cmd); 819 } 820 821 /* If we are SP1 here, we need to still take and release the host_lock as SP1 822 * does not have the changes necessary to avoid taking host->host_lock. 823 */ 824 static int 825 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 826 { 827 scsi_qla_host_t *vha = shost_priv(host); 828 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 829 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 830 struct qla_hw_data *ha = vha->hw; 831 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 832 srb_t *sp; 833 int rval; 834 struct qla_qpair *qpair = NULL; 835 uint32_t tag; 836 uint16_t hwq; 837 838 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 839 cmd->result = DID_NO_CONNECT << 16; 840 goto qc24_fail_command; 841 } 842 843 if (ha->mqenable) { 844 if (shost_use_blk_mq(vha->host)) { 845 tag = blk_mq_unique_tag(cmd->request); 846 hwq = blk_mq_unique_tag_to_hwq(tag); 847 qpair = ha->queue_pair_map[hwq]; 848 } else if (vha->vp_idx && vha->qpair) { 849 qpair = vha->qpair; 850 } 851 852 if (qpair) 853 return qla2xxx_mqueuecommand(host, cmd, qpair); 854 } 855 856 if (ha->flags.eeh_busy) { 857 if (ha->flags.pci_channel_io_perm_failure) { 858 ql_dbg(ql_dbg_aer, vha, 0x9010, 859 "PCI Channel IO permanent failure, exiting " 860 "cmd=%p.\n", cmd); 861 cmd->result = DID_NO_CONNECT << 16; 862 } else { 863 ql_dbg(ql_dbg_aer, vha, 0x9011, 864 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 865 cmd->result = DID_REQUEUE << 16; 866 } 867 goto qc24_fail_command; 868 } 869 870 rval = fc_remote_port_chkready(rport); 871 if (rval) { 872 cmd->result = rval; 873 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 874 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 875 cmd, rval); 876 goto qc24_fail_command; 877 } 878 879 if (!vha->flags.difdix_supported && 880 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 881 ql_dbg(ql_dbg_io, vha, 0x3004, 882 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 883 cmd); 884 cmd->result = DID_NO_CONNECT << 16; 885 goto qc24_fail_command; 886 } 887 888 if (!fcport) { 889 cmd->result = DID_NO_CONNECT << 16; 890 goto qc24_fail_command; 891 } 892 893 if (atomic_read(&fcport->state) != FCS_ONLINE) { 894 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 895 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 896 ql_dbg(ql_dbg_io, vha, 0x3005, 897 "Returning DNC, fcport_state=%d loop_state=%d.\n", 898 atomic_read(&fcport->state), 899 atomic_read(&base_vha->loop_state)); 900 cmd->result = DID_NO_CONNECT << 16; 901 goto qc24_fail_command; 902 } 903 goto qc24_target_busy; 904 } 905 906 /* 907 * Return target busy if we've received a non-zero retry_delay_timer 908 * in a FCP_RSP. 909 */ 910 if (fcport->retry_delay_timestamp == 0) { 911 /* retry delay not set */ 912 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 913 fcport->retry_delay_timestamp = 0; 914 else 915 goto qc24_target_busy; 916 917 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 918 if (!sp) 919 goto qc24_host_busy; 920 921 sp->u.scmd.cmd = cmd; 922 sp->type = SRB_SCSI_CMD; 923 atomic_set(&sp->ref_count, 1); 924 CMD_SP(cmd) = (void *)sp; 925 sp->free = qla2x00_sp_free_dma; 926 sp->done = qla2x00_sp_compl; 927 928 rval = ha->isp_ops->start_scsi(sp); 929 if (rval != QLA_SUCCESS) { 930 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 931 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 932 goto qc24_host_busy_free_sp; 933 } 934 935 return 0; 936 937 qc24_host_busy_free_sp: 938 sp->free(sp); 939 940 qc24_host_busy: 941 return SCSI_MLQUEUE_HOST_BUSY; 942 943 qc24_target_busy: 944 return SCSI_MLQUEUE_TARGET_BUSY; 945 946 qc24_fail_command: 947 cmd->scsi_done(cmd); 948 949 return 0; 950 } 951 952 /* For MQ supported I/O */ 953 int 954 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 955 struct qla_qpair *qpair) 956 { 957 scsi_qla_host_t *vha = shost_priv(host); 958 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 959 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 960 struct qla_hw_data *ha = vha->hw; 961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 962 srb_t *sp; 963 int rval; 964 965 rval = fc_remote_port_chkready(rport); 966 if (rval) { 967 cmd->result = rval; 968 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 969 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 970 cmd, rval); 971 goto qc24_fail_command; 972 } 973 974 if (!fcport) { 975 cmd->result = DID_NO_CONNECT << 16; 976 goto qc24_fail_command; 977 } 978 979 if (atomic_read(&fcport->state) != FCS_ONLINE) { 980 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 981 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 982 ql_dbg(ql_dbg_io, vha, 0x3077, 983 "Returning DNC, fcport_state=%d loop_state=%d.\n", 984 atomic_read(&fcport->state), 985 atomic_read(&base_vha->loop_state)); 986 cmd->result = DID_NO_CONNECT << 16; 987 goto qc24_fail_command; 988 } 989 goto qc24_target_busy; 990 } 991 992 /* 993 * Return target busy if we've received a non-zero retry_delay_timer 994 * in a FCP_RSP. 995 */ 996 if (fcport->retry_delay_timestamp == 0) { 997 /* retry delay not set */ 998 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 999 fcport->retry_delay_timestamp = 0; 1000 else 1001 goto qc24_target_busy; 1002 1003 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1004 if (!sp) 1005 goto qc24_host_busy; 1006 1007 sp->u.scmd.cmd = cmd; 1008 sp->type = SRB_SCSI_CMD; 1009 atomic_set(&sp->ref_count, 1); 1010 CMD_SP(cmd) = (void *)sp; 1011 sp->free = qla2xxx_qpair_sp_free_dma; 1012 sp->done = qla2xxx_qpair_sp_compl; 1013 sp->qpair = qpair; 1014 1015 rval = ha->isp_ops->start_scsi_mq(sp); 1016 if (rval != QLA_SUCCESS) { 1017 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1018 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1019 if (rval == QLA_INTERFACE_ERROR) 1020 goto qc24_fail_command; 1021 goto qc24_host_busy_free_sp; 1022 } 1023 1024 return 0; 1025 1026 qc24_host_busy_free_sp: 1027 sp->free(sp); 1028 1029 qc24_host_busy: 1030 return SCSI_MLQUEUE_HOST_BUSY; 1031 1032 qc24_target_busy: 1033 return SCSI_MLQUEUE_TARGET_BUSY; 1034 1035 qc24_fail_command: 1036 cmd->scsi_done(cmd); 1037 1038 return 0; 1039 } 1040 1041 /* 1042 * qla2x00_eh_wait_on_command 1043 * Waits for the command to be returned by the Firmware for some 1044 * max time. 1045 * 1046 * Input: 1047 * cmd = Scsi Command to wait on. 1048 * 1049 * Return: 1050 * Not Found : 0 1051 * Found : 1 1052 */ 1053 static int 1054 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1055 { 1056 #define ABORT_POLLING_PERIOD 1000 1057 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1058 unsigned long wait_iter = ABORT_WAIT_ITER; 1059 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1060 struct qla_hw_data *ha = vha->hw; 1061 int ret = QLA_SUCCESS; 1062 1063 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1064 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1065 "Return:eh_wait.\n"); 1066 return ret; 1067 } 1068 1069 while (CMD_SP(cmd) && wait_iter--) { 1070 msleep(ABORT_POLLING_PERIOD); 1071 } 1072 if (CMD_SP(cmd)) 1073 ret = QLA_FUNCTION_FAILED; 1074 1075 return ret; 1076 } 1077 1078 /* 1079 * qla2x00_wait_for_hba_online 1080 * Wait till the HBA is online after going through 1081 * <= MAX_RETRIES_OF_ISP_ABORT or 1082 * finally HBA is disabled ie marked offline 1083 * 1084 * Input: 1085 * ha - pointer to host adapter structure 1086 * 1087 * Note: 1088 * Does context switching-Release SPIN_LOCK 1089 * (if any) before calling this routine. 1090 * 1091 * Return: 1092 * Success (Adapter is online) : 0 1093 * Failed (Adapter is offline/disabled) : 1 1094 */ 1095 int 1096 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1097 { 1098 int return_status; 1099 unsigned long wait_online; 1100 struct qla_hw_data *ha = vha->hw; 1101 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1102 1103 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1104 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1105 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1106 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1107 ha->dpc_active) && time_before(jiffies, wait_online)) { 1108 1109 msleep(1000); 1110 } 1111 if (base_vha->flags.online) 1112 return_status = QLA_SUCCESS; 1113 else 1114 return_status = QLA_FUNCTION_FAILED; 1115 1116 return (return_status); 1117 } 1118 1119 static inline int test_fcport_count(scsi_qla_host_t *vha) 1120 { 1121 struct qla_hw_data *ha = vha->hw; 1122 unsigned long flags; 1123 int res; 1124 1125 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1126 ql_dbg(ql_dbg_init, vha, 0x00ec, 1127 "tgt %p, fcport_count=%d\n", 1128 vha, vha->fcport_count); 1129 res = (vha->fcport_count == 0); 1130 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1131 1132 return res; 1133 } 1134 1135 /* 1136 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1137 * it has dependency on UNLOADING flag to stop device discovery 1138 */ 1139 static void 1140 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1141 { 1142 qla2x00_mark_all_devices_lost(vha, 0); 1143 1144 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1145 } 1146 1147 /* 1148 * qla2x00_wait_for_hba_ready 1149 * Wait till the HBA is ready before doing driver unload 1150 * 1151 * Input: 1152 * ha - pointer to host adapter structure 1153 * 1154 * Note: 1155 * Does context switching-Release SPIN_LOCK 1156 * (if any) before calling this routine. 1157 * 1158 */ 1159 static void 1160 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1161 { 1162 struct qla_hw_data *ha = vha->hw; 1163 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1164 1165 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1166 ha->flags.mbox_busy) || 1167 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1168 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1169 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1170 break; 1171 msleep(1000); 1172 } 1173 } 1174 1175 int 1176 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1177 { 1178 int return_status; 1179 unsigned long wait_reset; 1180 struct qla_hw_data *ha = vha->hw; 1181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1182 1183 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1184 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1185 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1186 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1187 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1188 1189 msleep(1000); 1190 1191 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1192 ha->flags.chip_reset_done) 1193 break; 1194 } 1195 if (ha->flags.chip_reset_done) 1196 return_status = QLA_SUCCESS; 1197 else 1198 return_status = QLA_FUNCTION_FAILED; 1199 1200 return return_status; 1201 } 1202 1203 static void 1204 sp_get(struct srb *sp) 1205 { 1206 atomic_inc(&sp->ref_count); 1207 } 1208 1209 #define ISP_REG_DISCONNECT 0xffffffffU 1210 /************************************************************************** 1211 * qla2x00_isp_reg_stat 1212 * 1213 * Description: 1214 * Read the host status register of ISP before aborting the command. 1215 * 1216 * Input: 1217 * ha = pointer to host adapter structure. 1218 * 1219 * 1220 * Returns: 1221 * Either true or false. 1222 * 1223 * Note: Return true if there is register disconnect. 1224 **************************************************************************/ 1225 static inline 1226 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1227 { 1228 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1229 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1230 1231 if (IS_P3P_TYPE(ha)) 1232 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1233 else 1234 return ((RD_REG_DWORD(®->host_status)) == 1235 ISP_REG_DISCONNECT); 1236 } 1237 1238 /************************************************************************** 1239 * qla2xxx_eh_abort 1240 * 1241 * Description: 1242 * The abort function will abort the specified command. 1243 * 1244 * Input: 1245 * cmd = Linux SCSI command packet to be aborted. 1246 * 1247 * Returns: 1248 * Either SUCCESS or FAILED. 1249 * 1250 * Note: 1251 * Only return FAILED if command not returned by firmware. 1252 **************************************************************************/ 1253 static int 1254 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1255 { 1256 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1257 srb_t *sp; 1258 int ret; 1259 unsigned int id; 1260 uint64_t lun; 1261 unsigned long flags; 1262 int rval, wait = 0; 1263 struct qla_hw_data *ha = vha->hw; 1264 1265 if (qla2x00_isp_reg_stat(ha)) { 1266 ql_log(ql_log_info, vha, 0x8042, 1267 "PCI/Register disconnect, exiting.\n"); 1268 return FAILED; 1269 } 1270 if (!CMD_SP(cmd)) 1271 return SUCCESS; 1272 1273 ret = fc_block_scsi_eh(cmd); 1274 if (ret != 0) 1275 return ret; 1276 ret = SUCCESS; 1277 1278 id = cmd->device->id; 1279 lun = cmd->device->lun; 1280 1281 spin_lock_irqsave(&ha->hardware_lock, flags); 1282 sp = (srb_t *) CMD_SP(cmd); 1283 if (!sp) { 1284 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1285 return SUCCESS; 1286 } 1287 1288 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1289 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1290 vha->host_no, id, lun, sp, cmd, sp->handle); 1291 1292 /* Get a reference to the sp and drop the lock.*/ 1293 sp_get(sp); 1294 1295 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1296 rval = ha->isp_ops->abort_command(sp); 1297 if (rval) { 1298 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1299 ret = SUCCESS; 1300 else 1301 ret = FAILED; 1302 1303 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1304 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1305 } else { 1306 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1307 "Abort command mbx success cmd=%p.\n", cmd); 1308 wait = 1; 1309 } 1310 1311 spin_lock_irqsave(&ha->hardware_lock, flags); 1312 sp->done(sp, 0); 1313 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1314 1315 /* Did the command return during mailbox execution? */ 1316 if (ret == FAILED && !CMD_SP(cmd)) 1317 ret = SUCCESS; 1318 1319 /* Wait for the command to be returned. */ 1320 if (wait) { 1321 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1322 ql_log(ql_log_warn, vha, 0x8006, 1323 "Abort handler timed out cmd=%p.\n", cmd); 1324 ret = FAILED; 1325 } 1326 } 1327 1328 ql_log(ql_log_info, vha, 0x801c, 1329 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1330 vha->host_no, id, lun, wait, ret); 1331 1332 return ret; 1333 } 1334 1335 int 1336 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1337 uint64_t l, enum nexus_wait_type type) 1338 { 1339 int cnt, match, status; 1340 unsigned long flags; 1341 struct qla_hw_data *ha = vha->hw; 1342 struct req_que *req; 1343 srb_t *sp; 1344 struct scsi_cmnd *cmd; 1345 1346 status = QLA_SUCCESS; 1347 1348 spin_lock_irqsave(&ha->hardware_lock, flags); 1349 req = vha->req; 1350 for (cnt = 1; status == QLA_SUCCESS && 1351 cnt < req->num_outstanding_cmds; cnt++) { 1352 sp = req->outstanding_cmds[cnt]; 1353 if (!sp) 1354 continue; 1355 if (sp->type != SRB_SCSI_CMD) 1356 continue; 1357 if (vha->vp_idx != sp->vha->vp_idx) 1358 continue; 1359 match = 0; 1360 cmd = GET_CMD_SP(sp); 1361 switch (type) { 1362 case WAIT_HOST: 1363 match = 1; 1364 break; 1365 case WAIT_TARGET: 1366 match = cmd->device->id == t; 1367 break; 1368 case WAIT_LUN: 1369 match = (cmd->device->id == t && 1370 cmd->device->lun == l); 1371 break; 1372 } 1373 if (!match) 1374 continue; 1375 1376 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1377 status = qla2x00_eh_wait_on_command(cmd); 1378 spin_lock_irqsave(&ha->hardware_lock, flags); 1379 } 1380 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1381 1382 return status; 1383 } 1384 1385 static char *reset_errors[] = { 1386 "HBA not online", 1387 "HBA not ready", 1388 "Task management failed", 1389 "Waiting for command completions", 1390 }; 1391 1392 static int 1393 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1394 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1395 { 1396 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1397 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1398 int err; 1399 1400 if (!fcport) { 1401 return FAILED; 1402 } 1403 1404 err = fc_block_scsi_eh(cmd); 1405 if (err != 0) 1406 return err; 1407 1408 ql_log(ql_log_info, vha, 0x8009, 1409 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1410 cmd->device->id, cmd->device->lun, cmd); 1411 1412 err = 0; 1413 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1414 ql_log(ql_log_warn, vha, 0x800a, 1415 "Wait for hba online failed for cmd=%p.\n", cmd); 1416 goto eh_reset_failed; 1417 } 1418 err = 2; 1419 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1420 != QLA_SUCCESS) { 1421 ql_log(ql_log_warn, vha, 0x800c, 1422 "do_reset failed for cmd=%p.\n", cmd); 1423 goto eh_reset_failed; 1424 } 1425 err = 3; 1426 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1427 cmd->device->lun, type) != QLA_SUCCESS) { 1428 ql_log(ql_log_warn, vha, 0x800d, 1429 "wait for pending cmds failed for cmd=%p.\n", cmd); 1430 goto eh_reset_failed; 1431 } 1432 1433 ql_log(ql_log_info, vha, 0x800e, 1434 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1435 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1436 1437 return SUCCESS; 1438 1439 eh_reset_failed: 1440 ql_log(ql_log_info, vha, 0x800f, 1441 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1442 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1443 cmd); 1444 return FAILED; 1445 } 1446 1447 static int 1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1451 struct qla_hw_data *ha = vha->hw; 1452 1453 if (qla2x00_isp_reg_stat(ha)) { 1454 ql_log(ql_log_info, vha, 0x803e, 1455 "PCI/Register disconnect, exiting.\n"); 1456 return FAILED; 1457 } 1458 1459 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1460 ha->isp_ops->lun_reset); 1461 } 1462 1463 static int 1464 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1465 { 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1467 struct qla_hw_data *ha = vha->hw; 1468 1469 if (qla2x00_isp_reg_stat(ha)) { 1470 ql_log(ql_log_info, vha, 0x803f, 1471 "PCI/Register disconnect, exiting.\n"); 1472 return FAILED; 1473 } 1474 1475 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1476 ha->isp_ops->target_reset); 1477 } 1478 1479 /************************************************************************** 1480 * qla2xxx_eh_bus_reset 1481 * 1482 * Description: 1483 * The bus reset function will reset the bus and abort any executing 1484 * commands. 1485 * 1486 * Input: 1487 * cmd = Linux SCSI command packet of the command that cause the 1488 * bus reset. 1489 * 1490 * Returns: 1491 * SUCCESS/FAILURE (defined as macro in scsi.h). 1492 * 1493 **************************************************************************/ 1494 static int 1495 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1496 { 1497 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1498 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1499 int ret = FAILED; 1500 unsigned int id; 1501 uint64_t lun; 1502 struct qla_hw_data *ha = vha->hw; 1503 1504 if (qla2x00_isp_reg_stat(ha)) { 1505 ql_log(ql_log_info, vha, 0x8040, 1506 "PCI/Register disconnect, exiting.\n"); 1507 return FAILED; 1508 } 1509 1510 id = cmd->device->id; 1511 lun = cmd->device->lun; 1512 1513 if (!fcport) { 1514 return ret; 1515 } 1516 1517 ret = fc_block_scsi_eh(cmd); 1518 if (ret != 0) 1519 return ret; 1520 ret = FAILED; 1521 1522 ql_log(ql_log_info, vha, 0x8012, 1523 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1524 1525 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1526 ql_log(ql_log_fatal, vha, 0x8013, 1527 "Wait for hba online failed board disabled.\n"); 1528 goto eh_bus_reset_done; 1529 } 1530 1531 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1532 ret = SUCCESS; 1533 1534 if (ret == FAILED) 1535 goto eh_bus_reset_done; 1536 1537 /* Flush outstanding commands. */ 1538 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1539 QLA_SUCCESS) { 1540 ql_log(ql_log_warn, vha, 0x8014, 1541 "Wait for pending commands failed.\n"); 1542 ret = FAILED; 1543 } 1544 1545 eh_bus_reset_done: 1546 ql_log(ql_log_warn, vha, 0x802b, 1547 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1548 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1549 1550 return ret; 1551 } 1552 1553 /************************************************************************** 1554 * qla2xxx_eh_host_reset 1555 * 1556 * Description: 1557 * The reset function will reset the Adapter. 1558 * 1559 * Input: 1560 * cmd = Linux SCSI command packet of the command that cause the 1561 * adapter reset. 1562 * 1563 * Returns: 1564 * Either SUCCESS or FAILED. 1565 * 1566 * Note: 1567 **************************************************************************/ 1568 static int 1569 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1570 { 1571 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1572 struct qla_hw_data *ha = vha->hw; 1573 int ret = FAILED; 1574 unsigned int id; 1575 uint64_t lun; 1576 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1577 1578 if (qla2x00_isp_reg_stat(ha)) { 1579 ql_log(ql_log_info, vha, 0x8041, 1580 "PCI/Register disconnect, exiting.\n"); 1581 schedule_work(&ha->board_disable); 1582 return SUCCESS; 1583 } 1584 1585 id = cmd->device->id; 1586 lun = cmd->device->lun; 1587 1588 ql_log(ql_log_info, vha, 0x8018, 1589 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1590 1591 /* 1592 * No point in issuing another reset if one is active. Also do not 1593 * attempt a reset if we are updating flash. 1594 */ 1595 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1596 goto eh_host_reset_lock; 1597 1598 if (vha != base_vha) { 1599 if (qla2x00_vp_abort_isp(vha)) 1600 goto eh_host_reset_lock; 1601 } else { 1602 if (IS_P3P_TYPE(vha->hw)) { 1603 if (!qla82xx_fcoe_ctx_reset(vha)) { 1604 /* Ctx reset success */ 1605 ret = SUCCESS; 1606 goto eh_host_reset_lock; 1607 } 1608 /* fall thru if ctx reset failed */ 1609 } 1610 if (ha->wq) 1611 flush_workqueue(ha->wq); 1612 1613 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1614 if (ha->isp_ops->abort_isp(base_vha)) { 1615 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1616 /* failed. schedule dpc to try */ 1617 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1618 1619 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1620 ql_log(ql_log_warn, vha, 0x802a, 1621 "wait for hba online failed.\n"); 1622 goto eh_host_reset_lock; 1623 } 1624 } 1625 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 } 1627 1628 /* Waiting for command to be returned to OS.*/ 1629 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1630 QLA_SUCCESS) 1631 ret = SUCCESS; 1632 1633 eh_host_reset_lock: 1634 ql_log(ql_log_info, vha, 0x8017, 1635 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1636 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1637 1638 return ret; 1639 } 1640 1641 /* 1642 * qla2x00_loop_reset 1643 * Issue loop reset. 1644 * 1645 * Input: 1646 * ha = adapter block pointer. 1647 * 1648 * Returns: 1649 * 0 = success 1650 */ 1651 int 1652 qla2x00_loop_reset(scsi_qla_host_t *vha) 1653 { 1654 int ret; 1655 struct fc_port *fcport; 1656 struct qla_hw_data *ha = vha->hw; 1657 1658 if (IS_QLAFX00(ha)) { 1659 return qlafx00_loop_reset(vha); 1660 } 1661 1662 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1663 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1664 if (fcport->port_type != FCT_TARGET) 1665 continue; 1666 1667 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1668 if (ret != QLA_SUCCESS) { 1669 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1670 "Bus Reset failed: Reset=%d " 1671 "d_id=%x.\n", ret, fcport->d_id.b24); 1672 } 1673 } 1674 } 1675 1676 1677 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1678 atomic_set(&vha->loop_state, LOOP_DOWN); 1679 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1680 qla2x00_mark_all_devices_lost(vha, 0); 1681 ret = qla2x00_full_login_lip(vha); 1682 if (ret != QLA_SUCCESS) { 1683 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1684 "full_login_lip=%d.\n", ret); 1685 } 1686 } 1687 1688 if (ha->flags.enable_lip_reset) { 1689 ret = qla2x00_lip_reset(vha); 1690 if (ret != QLA_SUCCESS) 1691 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1692 "lip_reset failed (%d).\n", ret); 1693 } 1694 1695 /* Issue marker command only when we are going to start the I/O */ 1696 vha->marker_needed = 1; 1697 1698 return QLA_SUCCESS; 1699 } 1700 1701 void 1702 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1703 { 1704 int que, cnt, status; 1705 unsigned long flags; 1706 srb_t *sp; 1707 struct qla_hw_data *ha = vha->hw; 1708 struct req_que *req; 1709 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1710 struct qla_tgt_cmd *cmd; 1711 uint8_t trace = 0; 1712 1713 spin_lock_irqsave(&ha->hardware_lock, flags); 1714 for (que = 0; que < ha->max_req_queues; que++) { 1715 req = ha->req_q_map[que]; 1716 if (!req) 1717 continue; 1718 if (!req->outstanding_cmds) 1719 continue; 1720 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1721 sp = req->outstanding_cmds[cnt]; 1722 if (sp) { 1723 req->outstanding_cmds[cnt] = NULL; 1724 if (sp->cmd_type == TYPE_SRB) { 1725 if (sp->type == SRB_NVME_CMD || 1726 sp->type == SRB_NVME_LS) { 1727 sp_get(sp); 1728 spin_unlock_irqrestore( 1729 &ha->hardware_lock, flags); 1730 qla_nvme_abort(ha, sp); 1731 spin_lock_irqsave( 1732 &ha->hardware_lock, flags); 1733 } else if (GET_CMD_SP(sp) && 1734 !ha->flags.eeh_busy && 1735 (!test_bit(ABORT_ISP_ACTIVE, 1736 &vha->dpc_flags)) && 1737 (sp->type == SRB_SCSI_CMD)) { 1738 /* 1739 * Don't abort commands in 1740 * adapter during EEH 1741 * recovery as it's not 1742 * accessible/responding. 1743 * 1744 * Get a reference to the sp 1745 * and drop the lock. The 1746 * reference ensures this 1747 * sp->done() call and not the 1748 * call in qla2xxx_eh_abort() 1749 * ends the SCSI command (with 1750 * result 'res'). 1751 */ 1752 sp_get(sp); 1753 spin_unlock_irqrestore( 1754 &ha->hardware_lock, flags); 1755 status = qla2xxx_eh_abort( 1756 GET_CMD_SP(sp)); 1757 spin_lock_irqsave( 1758 &ha->hardware_lock, flags); 1759 /* 1760 * Get rid of extra reference 1761 * if immediate exit from 1762 * ql2xxx_eh_abort 1763 */ 1764 if (status == FAILED && 1765 (qla2x00_isp_reg_stat(ha))) 1766 atomic_dec( 1767 &sp->ref_count); 1768 } 1769 sp->done(sp, res); 1770 } else { 1771 if (!vha->hw->tgt.tgt_ops || !tgt || 1772 qla_ini_mode_enabled(vha)) { 1773 if (!trace) 1774 ql_dbg(ql_dbg_tgt_mgt, 1775 vha, 0xf003, 1776 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1777 vha->dpc_flags); 1778 continue; 1779 } 1780 cmd = (struct qla_tgt_cmd *)sp; 1781 qlt_abort_cmd_on_host_reset(cmd->vha, 1782 cmd); 1783 } 1784 } 1785 } 1786 } 1787 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1788 } 1789 1790 static int 1791 qla2xxx_slave_alloc(struct scsi_device *sdev) 1792 { 1793 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1794 1795 if (!rport || fc_remote_port_chkready(rport)) 1796 return -ENXIO; 1797 1798 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1799 1800 return 0; 1801 } 1802 1803 static int 1804 qla2xxx_slave_configure(struct scsi_device *sdev) 1805 { 1806 scsi_qla_host_t *vha = shost_priv(sdev->host); 1807 struct req_que *req = vha->req; 1808 1809 if (IS_T10_PI_CAPABLE(vha->hw)) 1810 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1811 1812 scsi_change_queue_depth(sdev, req->max_q_depth); 1813 return 0; 1814 } 1815 1816 static void 1817 qla2xxx_slave_destroy(struct scsi_device *sdev) 1818 { 1819 sdev->hostdata = NULL; 1820 } 1821 1822 /** 1823 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1824 * @ha: HA context 1825 * 1826 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1827 * supported addressing method. 1828 */ 1829 static void 1830 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1831 { 1832 /* Assume a 32bit DMA mask. */ 1833 ha->flags.enable_64bit_addressing = 0; 1834 1835 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1836 /* Any upper-dword bits set? */ 1837 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1838 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1839 /* Ok, a 64bit DMA mask is applicable. */ 1840 ha->flags.enable_64bit_addressing = 1; 1841 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1842 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1843 return; 1844 } 1845 } 1846 1847 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1848 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1849 } 1850 1851 static void 1852 qla2x00_enable_intrs(struct qla_hw_data *ha) 1853 { 1854 unsigned long flags = 0; 1855 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1856 1857 spin_lock_irqsave(&ha->hardware_lock, flags); 1858 ha->interrupts_on = 1; 1859 /* enable risc and host interrupts */ 1860 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1861 RD_REG_WORD(®->ictrl); 1862 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1863 1864 } 1865 1866 static void 1867 qla2x00_disable_intrs(struct qla_hw_data *ha) 1868 { 1869 unsigned long flags = 0; 1870 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1871 1872 spin_lock_irqsave(&ha->hardware_lock, flags); 1873 ha->interrupts_on = 0; 1874 /* disable risc and host interrupts */ 1875 WRT_REG_WORD(®->ictrl, 0); 1876 RD_REG_WORD(®->ictrl); 1877 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1878 } 1879 1880 static void 1881 qla24xx_enable_intrs(struct qla_hw_data *ha) 1882 { 1883 unsigned long flags = 0; 1884 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1885 1886 spin_lock_irqsave(&ha->hardware_lock, flags); 1887 ha->interrupts_on = 1; 1888 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1889 RD_REG_DWORD(®->ictrl); 1890 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1891 } 1892 1893 static void 1894 qla24xx_disable_intrs(struct qla_hw_data *ha) 1895 { 1896 unsigned long flags = 0; 1897 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1898 1899 if (IS_NOPOLLING_TYPE(ha)) 1900 return; 1901 spin_lock_irqsave(&ha->hardware_lock, flags); 1902 ha->interrupts_on = 0; 1903 WRT_REG_DWORD(®->ictrl, 0); 1904 RD_REG_DWORD(®->ictrl); 1905 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1906 } 1907 1908 static int 1909 qla2x00_iospace_config(struct qla_hw_data *ha) 1910 { 1911 resource_size_t pio; 1912 uint16_t msix; 1913 1914 if (pci_request_selected_regions(ha->pdev, ha->bars, 1915 QLA2XXX_DRIVER_NAME)) { 1916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1917 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1918 pci_name(ha->pdev)); 1919 goto iospace_error_exit; 1920 } 1921 if (!(ha->bars & 1)) 1922 goto skip_pio; 1923 1924 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1925 pio = pci_resource_start(ha->pdev, 0); 1926 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1927 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1928 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1929 "Invalid pci I/O region size (%s).\n", 1930 pci_name(ha->pdev)); 1931 pio = 0; 1932 } 1933 } else { 1934 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1935 "Region #0 no a PIO resource (%s).\n", 1936 pci_name(ha->pdev)); 1937 pio = 0; 1938 } 1939 ha->pio_address = pio; 1940 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1941 "PIO address=%llu.\n", 1942 (unsigned long long)ha->pio_address); 1943 1944 skip_pio: 1945 /* Use MMIO operations for all accesses. */ 1946 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1947 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1948 "Region #1 not an MMIO resource (%s), aborting.\n", 1949 pci_name(ha->pdev)); 1950 goto iospace_error_exit; 1951 } 1952 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1953 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1954 "Invalid PCI mem region size (%s), aborting.\n", 1955 pci_name(ha->pdev)); 1956 goto iospace_error_exit; 1957 } 1958 1959 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1960 if (!ha->iobase) { 1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1962 "Cannot remap MMIO (%s), aborting.\n", 1963 pci_name(ha->pdev)); 1964 goto iospace_error_exit; 1965 } 1966 1967 /* Determine queue resources */ 1968 ha->max_req_queues = ha->max_rsp_queues = 1; 1969 ha->msix_count = QLA_BASE_VECTORS; 1970 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1971 goto mqiobase_exit; 1972 1973 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1974 pci_resource_len(ha->pdev, 3)); 1975 if (ha->mqiobase) { 1976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1977 "MQIO Base=%p.\n", ha->mqiobase); 1978 /* Read MSIX vector size of the board */ 1979 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1980 ha->msix_count = msix + 1; 1981 /* Max queues are bounded by available msix vectors */ 1982 /* MB interrupt uses 1 vector */ 1983 ha->max_req_queues = ha->msix_count - 1; 1984 ha->max_rsp_queues = ha->max_req_queues; 1985 /* Queue pairs is the max value minus the base queue pair */ 1986 ha->max_qpairs = ha->max_rsp_queues - 1; 1987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 1988 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1989 1990 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1991 "MSI-X vector count: %d.\n", ha->msix_count); 1992 } else 1993 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1994 "BAR 3 not enabled.\n"); 1995 1996 mqiobase_exit: 1997 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1998 "MSIX Count: %d.\n", ha->msix_count); 1999 return (0); 2000 2001 iospace_error_exit: 2002 return (-ENOMEM); 2003 } 2004 2005 2006 static int 2007 qla83xx_iospace_config(struct qla_hw_data *ha) 2008 { 2009 uint16_t msix; 2010 2011 if (pci_request_selected_regions(ha->pdev, ha->bars, 2012 QLA2XXX_DRIVER_NAME)) { 2013 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2014 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2015 pci_name(ha->pdev)); 2016 2017 goto iospace_error_exit; 2018 } 2019 2020 /* Use MMIO operations for all accesses. */ 2021 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2022 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2023 "Invalid pci I/O region size (%s).\n", 2024 pci_name(ha->pdev)); 2025 goto iospace_error_exit; 2026 } 2027 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2028 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2029 "Invalid PCI mem region size (%s), aborting\n", 2030 pci_name(ha->pdev)); 2031 goto iospace_error_exit; 2032 } 2033 2034 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2035 if (!ha->iobase) { 2036 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2037 "Cannot remap MMIO (%s), aborting.\n", 2038 pci_name(ha->pdev)); 2039 goto iospace_error_exit; 2040 } 2041 2042 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2043 /* 83XX 26XX always use MQ type access for queues 2044 * - mbar 2, a.k.a region 4 */ 2045 ha->max_req_queues = ha->max_rsp_queues = 1; 2046 ha->msix_count = QLA_BASE_VECTORS; 2047 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2048 pci_resource_len(ha->pdev, 4)); 2049 2050 if (!ha->mqiobase) { 2051 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2052 "BAR2/region4 not enabled\n"); 2053 goto mqiobase_exit; 2054 } 2055 2056 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2057 pci_resource_len(ha->pdev, 2)); 2058 if (ha->msixbase) { 2059 /* Read MSIX vector size of the board */ 2060 pci_read_config_word(ha->pdev, 2061 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2062 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2063 /* 2064 * By default, driver uses at least two msix vectors 2065 * (default & rspq) 2066 */ 2067 if (ql2xmqsupport) { 2068 /* MB interrupt uses 1 vector */ 2069 ha->max_req_queues = ha->msix_count - 1; 2070 2071 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2072 if (QLA_TGT_MODE_ENABLED()) 2073 ha->max_req_queues--; 2074 2075 ha->max_rsp_queues = ha->max_req_queues; 2076 2077 /* Queue pairs is the max value minus 2078 * the base queue pair */ 2079 ha->max_qpairs = ha->max_req_queues - 1; 2080 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2081 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2082 } 2083 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2084 "MSI-X vector count: %d.\n", ha->msix_count); 2085 } else 2086 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2087 "BAR 1 not enabled.\n"); 2088 2089 mqiobase_exit: 2090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2091 "MSIX Count: %d.\n", ha->msix_count); 2092 return 0; 2093 2094 iospace_error_exit: 2095 return -ENOMEM; 2096 } 2097 2098 static struct isp_operations qla2100_isp_ops = { 2099 .pci_config = qla2100_pci_config, 2100 .reset_chip = qla2x00_reset_chip, 2101 .chip_diag = qla2x00_chip_diag, 2102 .config_rings = qla2x00_config_rings, 2103 .reset_adapter = qla2x00_reset_adapter, 2104 .nvram_config = qla2x00_nvram_config, 2105 .update_fw_options = qla2x00_update_fw_options, 2106 .load_risc = qla2x00_load_risc, 2107 .pci_info_str = qla2x00_pci_info_str, 2108 .fw_version_str = qla2x00_fw_version_str, 2109 .intr_handler = qla2100_intr_handler, 2110 .enable_intrs = qla2x00_enable_intrs, 2111 .disable_intrs = qla2x00_disable_intrs, 2112 .abort_command = qla2x00_abort_command, 2113 .target_reset = qla2x00_abort_target, 2114 .lun_reset = qla2x00_lun_reset, 2115 .fabric_login = qla2x00_login_fabric, 2116 .fabric_logout = qla2x00_fabric_logout, 2117 .calc_req_entries = qla2x00_calc_iocbs_32, 2118 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2119 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2120 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2121 .read_nvram = qla2x00_read_nvram_data, 2122 .write_nvram = qla2x00_write_nvram_data, 2123 .fw_dump = qla2100_fw_dump, 2124 .beacon_on = NULL, 2125 .beacon_off = NULL, 2126 .beacon_blink = NULL, 2127 .read_optrom = qla2x00_read_optrom_data, 2128 .write_optrom = qla2x00_write_optrom_data, 2129 .get_flash_version = qla2x00_get_flash_version, 2130 .start_scsi = qla2x00_start_scsi, 2131 .start_scsi_mq = NULL, 2132 .abort_isp = qla2x00_abort_isp, 2133 .iospace_config = qla2x00_iospace_config, 2134 .initialize_adapter = qla2x00_initialize_adapter, 2135 }; 2136 2137 static struct isp_operations qla2300_isp_ops = { 2138 .pci_config = qla2300_pci_config, 2139 .reset_chip = qla2x00_reset_chip, 2140 .chip_diag = qla2x00_chip_diag, 2141 .config_rings = qla2x00_config_rings, 2142 .reset_adapter = qla2x00_reset_adapter, 2143 .nvram_config = qla2x00_nvram_config, 2144 .update_fw_options = qla2x00_update_fw_options, 2145 .load_risc = qla2x00_load_risc, 2146 .pci_info_str = qla2x00_pci_info_str, 2147 .fw_version_str = qla2x00_fw_version_str, 2148 .intr_handler = qla2300_intr_handler, 2149 .enable_intrs = qla2x00_enable_intrs, 2150 .disable_intrs = qla2x00_disable_intrs, 2151 .abort_command = qla2x00_abort_command, 2152 .target_reset = qla2x00_abort_target, 2153 .lun_reset = qla2x00_lun_reset, 2154 .fabric_login = qla2x00_login_fabric, 2155 .fabric_logout = qla2x00_fabric_logout, 2156 .calc_req_entries = qla2x00_calc_iocbs_32, 2157 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2158 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2159 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2160 .read_nvram = qla2x00_read_nvram_data, 2161 .write_nvram = qla2x00_write_nvram_data, 2162 .fw_dump = qla2300_fw_dump, 2163 .beacon_on = qla2x00_beacon_on, 2164 .beacon_off = qla2x00_beacon_off, 2165 .beacon_blink = qla2x00_beacon_blink, 2166 .read_optrom = qla2x00_read_optrom_data, 2167 .write_optrom = qla2x00_write_optrom_data, 2168 .get_flash_version = qla2x00_get_flash_version, 2169 .start_scsi = qla2x00_start_scsi, 2170 .start_scsi_mq = NULL, 2171 .abort_isp = qla2x00_abort_isp, 2172 .iospace_config = qla2x00_iospace_config, 2173 .initialize_adapter = qla2x00_initialize_adapter, 2174 }; 2175 2176 static struct isp_operations qla24xx_isp_ops = { 2177 .pci_config = qla24xx_pci_config, 2178 .reset_chip = qla24xx_reset_chip, 2179 .chip_diag = qla24xx_chip_diag, 2180 .config_rings = qla24xx_config_rings, 2181 .reset_adapter = qla24xx_reset_adapter, 2182 .nvram_config = qla24xx_nvram_config, 2183 .update_fw_options = qla24xx_update_fw_options, 2184 .load_risc = qla24xx_load_risc, 2185 .pci_info_str = qla24xx_pci_info_str, 2186 .fw_version_str = qla24xx_fw_version_str, 2187 .intr_handler = qla24xx_intr_handler, 2188 .enable_intrs = qla24xx_enable_intrs, 2189 .disable_intrs = qla24xx_disable_intrs, 2190 .abort_command = qla24xx_abort_command, 2191 .target_reset = qla24xx_abort_target, 2192 .lun_reset = qla24xx_lun_reset, 2193 .fabric_login = qla24xx_login_fabric, 2194 .fabric_logout = qla24xx_fabric_logout, 2195 .calc_req_entries = NULL, 2196 .build_iocbs = NULL, 2197 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2198 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2199 .read_nvram = qla24xx_read_nvram_data, 2200 .write_nvram = qla24xx_write_nvram_data, 2201 .fw_dump = qla24xx_fw_dump, 2202 .beacon_on = qla24xx_beacon_on, 2203 .beacon_off = qla24xx_beacon_off, 2204 .beacon_blink = qla24xx_beacon_blink, 2205 .read_optrom = qla24xx_read_optrom_data, 2206 .write_optrom = qla24xx_write_optrom_data, 2207 .get_flash_version = qla24xx_get_flash_version, 2208 .start_scsi = qla24xx_start_scsi, 2209 .start_scsi_mq = NULL, 2210 .abort_isp = qla2x00_abort_isp, 2211 .iospace_config = qla2x00_iospace_config, 2212 .initialize_adapter = qla2x00_initialize_adapter, 2213 }; 2214 2215 static struct isp_operations qla25xx_isp_ops = { 2216 .pci_config = qla25xx_pci_config, 2217 .reset_chip = qla24xx_reset_chip, 2218 .chip_diag = qla24xx_chip_diag, 2219 .config_rings = qla24xx_config_rings, 2220 .reset_adapter = qla24xx_reset_adapter, 2221 .nvram_config = qla24xx_nvram_config, 2222 .update_fw_options = qla24xx_update_fw_options, 2223 .load_risc = qla24xx_load_risc, 2224 .pci_info_str = qla24xx_pci_info_str, 2225 .fw_version_str = qla24xx_fw_version_str, 2226 .intr_handler = qla24xx_intr_handler, 2227 .enable_intrs = qla24xx_enable_intrs, 2228 .disable_intrs = qla24xx_disable_intrs, 2229 .abort_command = qla24xx_abort_command, 2230 .target_reset = qla24xx_abort_target, 2231 .lun_reset = qla24xx_lun_reset, 2232 .fabric_login = qla24xx_login_fabric, 2233 .fabric_logout = qla24xx_fabric_logout, 2234 .calc_req_entries = NULL, 2235 .build_iocbs = NULL, 2236 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2237 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2238 .read_nvram = qla25xx_read_nvram_data, 2239 .write_nvram = qla25xx_write_nvram_data, 2240 .fw_dump = qla25xx_fw_dump, 2241 .beacon_on = qla24xx_beacon_on, 2242 .beacon_off = qla24xx_beacon_off, 2243 .beacon_blink = qla24xx_beacon_blink, 2244 .read_optrom = qla25xx_read_optrom_data, 2245 .write_optrom = qla24xx_write_optrom_data, 2246 .get_flash_version = qla24xx_get_flash_version, 2247 .start_scsi = qla24xx_dif_start_scsi, 2248 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2249 .abort_isp = qla2x00_abort_isp, 2250 .iospace_config = qla2x00_iospace_config, 2251 .initialize_adapter = qla2x00_initialize_adapter, 2252 }; 2253 2254 static struct isp_operations qla81xx_isp_ops = { 2255 .pci_config = qla25xx_pci_config, 2256 .reset_chip = qla24xx_reset_chip, 2257 .chip_diag = qla24xx_chip_diag, 2258 .config_rings = qla24xx_config_rings, 2259 .reset_adapter = qla24xx_reset_adapter, 2260 .nvram_config = qla81xx_nvram_config, 2261 .update_fw_options = qla81xx_update_fw_options, 2262 .load_risc = qla81xx_load_risc, 2263 .pci_info_str = qla24xx_pci_info_str, 2264 .fw_version_str = qla24xx_fw_version_str, 2265 .intr_handler = qla24xx_intr_handler, 2266 .enable_intrs = qla24xx_enable_intrs, 2267 .disable_intrs = qla24xx_disable_intrs, 2268 .abort_command = qla24xx_abort_command, 2269 .target_reset = qla24xx_abort_target, 2270 .lun_reset = qla24xx_lun_reset, 2271 .fabric_login = qla24xx_login_fabric, 2272 .fabric_logout = qla24xx_fabric_logout, 2273 .calc_req_entries = NULL, 2274 .build_iocbs = NULL, 2275 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2276 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2277 .read_nvram = NULL, 2278 .write_nvram = NULL, 2279 .fw_dump = qla81xx_fw_dump, 2280 .beacon_on = qla24xx_beacon_on, 2281 .beacon_off = qla24xx_beacon_off, 2282 .beacon_blink = qla83xx_beacon_blink, 2283 .read_optrom = qla25xx_read_optrom_data, 2284 .write_optrom = qla24xx_write_optrom_data, 2285 .get_flash_version = qla24xx_get_flash_version, 2286 .start_scsi = qla24xx_dif_start_scsi, 2287 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2288 .abort_isp = qla2x00_abort_isp, 2289 .iospace_config = qla2x00_iospace_config, 2290 .initialize_adapter = qla2x00_initialize_adapter, 2291 }; 2292 2293 static struct isp_operations qla82xx_isp_ops = { 2294 .pci_config = qla82xx_pci_config, 2295 .reset_chip = qla82xx_reset_chip, 2296 .chip_diag = qla24xx_chip_diag, 2297 .config_rings = qla82xx_config_rings, 2298 .reset_adapter = qla24xx_reset_adapter, 2299 .nvram_config = qla81xx_nvram_config, 2300 .update_fw_options = qla24xx_update_fw_options, 2301 .load_risc = qla82xx_load_risc, 2302 .pci_info_str = qla24xx_pci_info_str, 2303 .fw_version_str = qla24xx_fw_version_str, 2304 .intr_handler = qla82xx_intr_handler, 2305 .enable_intrs = qla82xx_enable_intrs, 2306 .disable_intrs = qla82xx_disable_intrs, 2307 .abort_command = qla24xx_abort_command, 2308 .target_reset = qla24xx_abort_target, 2309 .lun_reset = qla24xx_lun_reset, 2310 .fabric_login = qla24xx_login_fabric, 2311 .fabric_logout = qla24xx_fabric_logout, 2312 .calc_req_entries = NULL, 2313 .build_iocbs = NULL, 2314 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2315 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2316 .read_nvram = qla24xx_read_nvram_data, 2317 .write_nvram = qla24xx_write_nvram_data, 2318 .fw_dump = qla82xx_fw_dump, 2319 .beacon_on = qla82xx_beacon_on, 2320 .beacon_off = qla82xx_beacon_off, 2321 .beacon_blink = NULL, 2322 .read_optrom = qla82xx_read_optrom_data, 2323 .write_optrom = qla82xx_write_optrom_data, 2324 .get_flash_version = qla82xx_get_flash_version, 2325 .start_scsi = qla82xx_start_scsi, 2326 .start_scsi_mq = NULL, 2327 .abort_isp = qla82xx_abort_isp, 2328 .iospace_config = qla82xx_iospace_config, 2329 .initialize_adapter = qla2x00_initialize_adapter, 2330 }; 2331 2332 static struct isp_operations qla8044_isp_ops = { 2333 .pci_config = qla82xx_pci_config, 2334 .reset_chip = qla82xx_reset_chip, 2335 .chip_diag = qla24xx_chip_diag, 2336 .config_rings = qla82xx_config_rings, 2337 .reset_adapter = qla24xx_reset_adapter, 2338 .nvram_config = qla81xx_nvram_config, 2339 .update_fw_options = qla24xx_update_fw_options, 2340 .load_risc = qla82xx_load_risc, 2341 .pci_info_str = qla24xx_pci_info_str, 2342 .fw_version_str = qla24xx_fw_version_str, 2343 .intr_handler = qla8044_intr_handler, 2344 .enable_intrs = qla82xx_enable_intrs, 2345 .disable_intrs = qla82xx_disable_intrs, 2346 .abort_command = qla24xx_abort_command, 2347 .target_reset = qla24xx_abort_target, 2348 .lun_reset = qla24xx_lun_reset, 2349 .fabric_login = qla24xx_login_fabric, 2350 .fabric_logout = qla24xx_fabric_logout, 2351 .calc_req_entries = NULL, 2352 .build_iocbs = NULL, 2353 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2354 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2355 .read_nvram = NULL, 2356 .write_nvram = NULL, 2357 .fw_dump = qla8044_fw_dump, 2358 .beacon_on = qla82xx_beacon_on, 2359 .beacon_off = qla82xx_beacon_off, 2360 .beacon_blink = NULL, 2361 .read_optrom = qla8044_read_optrom_data, 2362 .write_optrom = qla8044_write_optrom_data, 2363 .get_flash_version = qla82xx_get_flash_version, 2364 .start_scsi = qla82xx_start_scsi, 2365 .start_scsi_mq = NULL, 2366 .abort_isp = qla8044_abort_isp, 2367 .iospace_config = qla82xx_iospace_config, 2368 .initialize_adapter = qla2x00_initialize_adapter, 2369 }; 2370 2371 static struct isp_operations qla83xx_isp_ops = { 2372 .pci_config = qla25xx_pci_config, 2373 .reset_chip = qla24xx_reset_chip, 2374 .chip_diag = qla24xx_chip_diag, 2375 .config_rings = qla24xx_config_rings, 2376 .reset_adapter = qla24xx_reset_adapter, 2377 .nvram_config = qla81xx_nvram_config, 2378 .update_fw_options = qla81xx_update_fw_options, 2379 .load_risc = qla81xx_load_risc, 2380 .pci_info_str = qla24xx_pci_info_str, 2381 .fw_version_str = qla24xx_fw_version_str, 2382 .intr_handler = qla24xx_intr_handler, 2383 .enable_intrs = qla24xx_enable_intrs, 2384 .disable_intrs = qla24xx_disable_intrs, 2385 .abort_command = qla24xx_abort_command, 2386 .target_reset = qla24xx_abort_target, 2387 .lun_reset = qla24xx_lun_reset, 2388 .fabric_login = qla24xx_login_fabric, 2389 .fabric_logout = qla24xx_fabric_logout, 2390 .calc_req_entries = NULL, 2391 .build_iocbs = NULL, 2392 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2393 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2394 .read_nvram = NULL, 2395 .write_nvram = NULL, 2396 .fw_dump = qla83xx_fw_dump, 2397 .beacon_on = qla24xx_beacon_on, 2398 .beacon_off = qla24xx_beacon_off, 2399 .beacon_blink = qla83xx_beacon_blink, 2400 .read_optrom = qla25xx_read_optrom_data, 2401 .write_optrom = qla24xx_write_optrom_data, 2402 .get_flash_version = qla24xx_get_flash_version, 2403 .start_scsi = qla24xx_dif_start_scsi, 2404 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2405 .abort_isp = qla2x00_abort_isp, 2406 .iospace_config = qla83xx_iospace_config, 2407 .initialize_adapter = qla2x00_initialize_adapter, 2408 }; 2409 2410 static struct isp_operations qlafx00_isp_ops = { 2411 .pci_config = qlafx00_pci_config, 2412 .reset_chip = qlafx00_soft_reset, 2413 .chip_diag = qlafx00_chip_diag, 2414 .config_rings = qlafx00_config_rings, 2415 .reset_adapter = qlafx00_soft_reset, 2416 .nvram_config = NULL, 2417 .update_fw_options = NULL, 2418 .load_risc = NULL, 2419 .pci_info_str = qlafx00_pci_info_str, 2420 .fw_version_str = qlafx00_fw_version_str, 2421 .intr_handler = qlafx00_intr_handler, 2422 .enable_intrs = qlafx00_enable_intrs, 2423 .disable_intrs = qlafx00_disable_intrs, 2424 .abort_command = qla24xx_async_abort_command, 2425 .target_reset = qlafx00_abort_target, 2426 .lun_reset = qlafx00_lun_reset, 2427 .fabric_login = NULL, 2428 .fabric_logout = NULL, 2429 .calc_req_entries = NULL, 2430 .build_iocbs = NULL, 2431 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2432 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2433 .read_nvram = qla24xx_read_nvram_data, 2434 .write_nvram = qla24xx_write_nvram_data, 2435 .fw_dump = NULL, 2436 .beacon_on = qla24xx_beacon_on, 2437 .beacon_off = qla24xx_beacon_off, 2438 .beacon_blink = NULL, 2439 .read_optrom = qla24xx_read_optrom_data, 2440 .write_optrom = qla24xx_write_optrom_data, 2441 .get_flash_version = qla24xx_get_flash_version, 2442 .start_scsi = qlafx00_start_scsi, 2443 .start_scsi_mq = NULL, 2444 .abort_isp = qlafx00_abort_isp, 2445 .iospace_config = qlafx00_iospace_config, 2446 .initialize_adapter = qlafx00_initialize_adapter, 2447 }; 2448 2449 static struct isp_operations qla27xx_isp_ops = { 2450 .pci_config = qla25xx_pci_config, 2451 .reset_chip = qla24xx_reset_chip, 2452 .chip_diag = qla24xx_chip_diag, 2453 .config_rings = qla24xx_config_rings, 2454 .reset_adapter = qla24xx_reset_adapter, 2455 .nvram_config = qla81xx_nvram_config, 2456 .update_fw_options = qla81xx_update_fw_options, 2457 .load_risc = qla81xx_load_risc, 2458 .pci_info_str = qla24xx_pci_info_str, 2459 .fw_version_str = qla24xx_fw_version_str, 2460 .intr_handler = qla24xx_intr_handler, 2461 .enable_intrs = qla24xx_enable_intrs, 2462 .disable_intrs = qla24xx_disable_intrs, 2463 .abort_command = qla24xx_abort_command, 2464 .target_reset = qla24xx_abort_target, 2465 .lun_reset = qla24xx_lun_reset, 2466 .fabric_login = qla24xx_login_fabric, 2467 .fabric_logout = qla24xx_fabric_logout, 2468 .calc_req_entries = NULL, 2469 .build_iocbs = NULL, 2470 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2471 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2472 .read_nvram = NULL, 2473 .write_nvram = NULL, 2474 .fw_dump = qla27xx_fwdump, 2475 .beacon_on = qla24xx_beacon_on, 2476 .beacon_off = qla24xx_beacon_off, 2477 .beacon_blink = qla83xx_beacon_blink, 2478 .read_optrom = qla25xx_read_optrom_data, 2479 .write_optrom = qla24xx_write_optrom_data, 2480 .get_flash_version = qla24xx_get_flash_version, 2481 .start_scsi = qla24xx_dif_start_scsi, 2482 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2483 .abort_isp = qla2x00_abort_isp, 2484 .iospace_config = qla83xx_iospace_config, 2485 .initialize_adapter = qla2x00_initialize_adapter, 2486 }; 2487 2488 static inline void 2489 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2490 { 2491 ha->device_type = DT_EXTENDED_IDS; 2492 switch (ha->pdev->device) { 2493 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2494 ha->isp_type |= DT_ISP2100; 2495 ha->device_type &= ~DT_EXTENDED_IDS; 2496 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2497 break; 2498 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2499 ha->isp_type |= DT_ISP2200; 2500 ha->device_type &= ~DT_EXTENDED_IDS; 2501 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2502 break; 2503 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2504 ha->isp_type |= DT_ISP2300; 2505 ha->device_type |= DT_ZIO_SUPPORTED; 2506 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2507 break; 2508 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2509 ha->isp_type |= DT_ISP2312; 2510 ha->device_type |= DT_ZIO_SUPPORTED; 2511 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2512 break; 2513 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2514 ha->isp_type |= DT_ISP2322; 2515 ha->device_type |= DT_ZIO_SUPPORTED; 2516 if (ha->pdev->subsystem_vendor == 0x1028 && 2517 ha->pdev->subsystem_device == 0x0170) 2518 ha->device_type |= DT_OEM_001; 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2520 break; 2521 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2522 ha->isp_type |= DT_ISP6312; 2523 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2524 break; 2525 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2526 ha->isp_type |= DT_ISP6322; 2527 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2528 break; 2529 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2530 ha->isp_type |= DT_ISP2422; 2531 ha->device_type |= DT_ZIO_SUPPORTED; 2532 ha->device_type |= DT_FWI2; 2533 ha->device_type |= DT_IIDMA; 2534 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2535 break; 2536 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2537 ha->isp_type |= DT_ISP2432; 2538 ha->device_type |= DT_ZIO_SUPPORTED; 2539 ha->device_type |= DT_FWI2; 2540 ha->device_type |= DT_IIDMA; 2541 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2542 break; 2543 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2544 ha->isp_type |= DT_ISP8432; 2545 ha->device_type |= DT_ZIO_SUPPORTED; 2546 ha->device_type |= DT_FWI2; 2547 ha->device_type |= DT_IIDMA; 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2549 break; 2550 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2551 ha->isp_type |= DT_ISP5422; 2552 ha->device_type |= DT_FWI2; 2553 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2554 break; 2555 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2556 ha->isp_type |= DT_ISP5432; 2557 ha->device_type |= DT_FWI2; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2561 ha->isp_type |= DT_ISP2532; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->device_type |= DT_FWI2; 2564 ha->device_type |= DT_IIDMA; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2568 ha->isp_type |= DT_ISP8001; 2569 ha->device_type |= DT_ZIO_SUPPORTED; 2570 ha->device_type |= DT_FWI2; 2571 ha->device_type |= DT_IIDMA; 2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2573 break; 2574 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2575 ha->isp_type |= DT_ISP8021; 2576 ha->device_type |= DT_ZIO_SUPPORTED; 2577 ha->device_type |= DT_FWI2; 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2579 /* Initialize 82XX ISP flags */ 2580 qla82xx_init_flags(ha); 2581 break; 2582 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2583 ha->isp_type |= DT_ISP8044; 2584 ha->device_type |= DT_ZIO_SUPPORTED; 2585 ha->device_type |= DT_FWI2; 2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2587 /* Initialize 82XX ISP flags */ 2588 qla82xx_init_flags(ha); 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2591 ha->isp_type |= DT_ISP2031; 2592 ha->device_type |= DT_ZIO_SUPPORTED; 2593 ha->device_type |= DT_FWI2; 2594 ha->device_type |= DT_IIDMA; 2595 ha->device_type |= DT_T10_PI; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2599 ha->isp_type |= DT_ISP8031; 2600 ha->device_type |= DT_ZIO_SUPPORTED; 2601 ha->device_type |= DT_FWI2; 2602 ha->device_type |= DT_IIDMA; 2603 ha->device_type |= DT_T10_PI; 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2607 ha->isp_type |= DT_ISPFX00; 2608 break; 2609 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2610 ha->isp_type |= DT_ISP2071; 2611 ha->device_type |= DT_ZIO_SUPPORTED; 2612 ha->device_type |= DT_FWI2; 2613 ha->device_type |= DT_IIDMA; 2614 ha->device_type |= DT_T10_PI; 2615 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2616 break; 2617 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2618 ha->isp_type |= DT_ISP2271; 2619 ha->device_type |= DT_ZIO_SUPPORTED; 2620 ha->device_type |= DT_FWI2; 2621 ha->device_type |= DT_IIDMA; 2622 ha->device_type |= DT_T10_PI; 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2624 break; 2625 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2626 ha->isp_type |= DT_ISP2261; 2627 ha->device_type |= DT_ZIO_SUPPORTED; 2628 ha->device_type |= DT_FWI2; 2629 ha->device_type |= DT_IIDMA; 2630 ha->device_type |= DT_T10_PI; 2631 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2632 break; 2633 } 2634 2635 if (IS_QLA82XX(ha)) 2636 ha->port_no = ha->portnum & 1; 2637 else { 2638 /* Get adapter physical port no from interrupt pin register. */ 2639 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2640 if (IS_QLA27XX(ha)) 2641 ha->port_no--; 2642 else 2643 ha->port_no = !(ha->port_no & 1); 2644 } 2645 2646 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2647 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2648 ha->device_type, ha->port_no, ha->fw_srisc_address); 2649 } 2650 2651 static void 2652 qla2xxx_scan_start(struct Scsi_Host *shost) 2653 { 2654 scsi_qla_host_t *vha = shost_priv(shost); 2655 2656 if (vha->hw->flags.running_gold_fw) 2657 return; 2658 2659 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2660 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2661 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2662 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2663 } 2664 2665 static int 2666 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2667 { 2668 scsi_qla_host_t *vha = shost_priv(shost); 2669 2670 if (test_bit(UNLOADING, &vha->dpc_flags)) 2671 return 1; 2672 if (!vha->host) 2673 return 1; 2674 if (time > vha->hw->loop_reset_delay * HZ) 2675 return 1; 2676 2677 return atomic_read(&vha->loop_state) == LOOP_READY; 2678 } 2679 2680 static void qla2x00_iocb_work_fn(struct work_struct *work) 2681 { 2682 struct scsi_qla_host *vha = container_of(work, 2683 struct scsi_qla_host, iocb_work); 2684 int cnt = 0; 2685 2686 while (!list_empty(&vha->work_list)) { 2687 qla2x00_do_work(vha); 2688 cnt++; 2689 if (cnt > 10) 2690 break; 2691 } 2692 } 2693 2694 /* 2695 * PCI driver interface 2696 */ 2697 static int 2698 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2699 { 2700 int ret = -ENODEV; 2701 struct Scsi_Host *host; 2702 scsi_qla_host_t *base_vha = NULL; 2703 struct qla_hw_data *ha; 2704 char pci_info[30]; 2705 char fw_str[30], wq_name[30]; 2706 struct scsi_host_template *sht; 2707 int bars, mem_only = 0; 2708 uint16_t req_length = 0, rsp_length = 0; 2709 struct req_que *req = NULL; 2710 struct rsp_que *rsp = NULL; 2711 int i; 2712 2713 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2714 sht = &qla2xxx_driver_template; 2715 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2716 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2717 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2718 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2719 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2720 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2721 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2722 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2723 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2724 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2730 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2731 mem_only = 1; 2732 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2733 "Mem only adapter.\n"); 2734 } 2735 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2736 "Bars=%d.\n", bars); 2737 2738 if (mem_only) { 2739 if (pci_enable_device_mem(pdev)) 2740 return ret; 2741 } else { 2742 if (pci_enable_device(pdev)) 2743 return ret; 2744 } 2745 2746 /* This may fail but that's ok */ 2747 pci_enable_pcie_error_reporting(pdev); 2748 2749 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2750 if (!ha) { 2751 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2752 "Unable to allocate memory for ha.\n"); 2753 goto disable_device; 2754 } 2755 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2756 "Memory allocated for ha=%p.\n", ha); 2757 ha->pdev = pdev; 2758 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2759 spin_lock_init(&ha->tgt.q_full_lock); 2760 spin_lock_init(&ha->tgt.sess_lock); 2761 spin_lock_init(&ha->tgt.atio_lock); 2762 2763 atomic_set(&ha->nvme_active_aen_cnt, 0); 2764 2765 /* Clear our data area */ 2766 ha->bars = bars; 2767 ha->mem_only = mem_only; 2768 spin_lock_init(&ha->hardware_lock); 2769 spin_lock_init(&ha->vport_slock); 2770 mutex_init(&ha->selflogin_lock); 2771 mutex_init(&ha->optrom_mutex); 2772 2773 /* Set ISP-type information. */ 2774 qla2x00_set_isp_flags(ha); 2775 2776 /* Set EEH reset type to fundamental if required by hba */ 2777 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2778 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2779 pdev->needs_freset = 1; 2780 2781 ha->prev_topology = 0; 2782 ha->init_cb_size = sizeof(init_cb_t); 2783 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2784 ha->optrom_size = OPTROM_SIZE_2300; 2785 2786 /* Assign ISP specific operations. */ 2787 if (IS_QLA2100(ha)) { 2788 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2789 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2790 req_length = REQUEST_ENTRY_CNT_2100; 2791 rsp_length = RESPONSE_ENTRY_CNT_2100; 2792 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2793 ha->gid_list_info_size = 4; 2794 ha->flash_conf_off = ~0; 2795 ha->flash_data_off = ~0; 2796 ha->nvram_conf_off = ~0; 2797 ha->nvram_data_off = ~0; 2798 ha->isp_ops = &qla2100_isp_ops; 2799 } else if (IS_QLA2200(ha)) { 2800 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2801 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2802 req_length = REQUEST_ENTRY_CNT_2200; 2803 rsp_length = RESPONSE_ENTRY_CNT_2100; 2804 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2805 ha->gid_list_info_size = 4; 2806 ha->flash_conf_off = ~0; 2807 ha->flash_data_off = ~0; 2808 ha->nvram_conf_off = ~0; 2809 ha->nvram_data_off = ~0; 2810 ha->isp_ops = &qla2100_isp_ops; 2811 } else if (IS_QLA23XX(ha)) { 2812 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2813 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2814 req_length = REQUEST_ENTRY_CNT_2200; 2815 rsp_length = RESPONSE_ENTRY_CNT_2300; 2816 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2817 ha->gid_list_info_size = 6; 2818 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2819 ha->optrom_size = OPTROM_SIZE_2322; 2820 ha->flash_conf_off = ~0; 2821 ha->flash_data_off = ~0; 2822 ha->nvram_conf_off = ~0; 2823 ha->nvram_data_off = ~0; 2824 ha->isp_ops = &qla2300_isp_ops; 2825 } else if (IS_QLA24XX_TYPE(ha)) { 2826 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2827 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2828 req_length = REQUEST_ENTRY_CNT_24XX; 2829 rsp_length = RESPONSE_ENTRY_CNT_2300; 2830 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2831 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2832 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2833 ha->gid_list_info_size = 8; 2834 ha->optrom_size = OPTROM_SIZE_24XX; 2835 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2836 ha->isp_ops = &qla24xx_isp_ops; 2837 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2838 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2839 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2840 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2841 } else if (IS_QLA25XX(ha)) { 2842 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2843 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2844 req_length = REQUEST_ENTRY_CNT_24XX; 2845 rsp_length = RESPONSE_ENTRY_CNT_2300; 2846 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2847 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2848 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2849 ha->gid_list_info_size = 8; 2850 ha->optrom_size = OPTROM_SIZE_25XX; 2851 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2852 ha->isp_ops = &qla25xx_isp_ops; 2853 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2854 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2855 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2856 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2857 } else if (IS_QLA81XX(ha)) { 2858 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2859 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2860 req_length = REQUEST_ENTRY_CNT_24XX; 2861 rsp_length = RESPONSE_ENTRY_CNT_2300; 2862 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2863 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2864 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2865 ha->gid_list_info_size = 8; 2866 ha->optrom_size = OPTROM_SIZE_81XX; 2867 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2868 ha->isp_ops = &qla81xx_isp_ops; 2869 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2870 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2871 ha->nvram_conf_off = ~0; 2872 ha->nvram_data_off = ~0; 2873 } else if (IS_QLA82XX(ha)) { 2874 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2875 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2876 req_length = REQUEST_ENTRY_CNT_82XX; 2877 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2878 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2879 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2880 ha->gid_list_info_size = 8; 2881 ha->optrom_size = OPTROM_SIZE_82XX; 2882 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2883 ha->isp_ops = &qla82xx_isp_ops; 2884 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2885 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2886 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2887 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2888 } else if (IS_QLA8044(ha)) { 2889 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2890 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2891 req_length = REQUEST_ENTRY_CNT_82XX; 2892 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2893 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2894 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2895 ha->gid_list_info_size = 8; 2896 ha->optrom_size = OPTROM_SIZE_83XX; 2897 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2898 ha->isp_ops = &qla8044_isp_ops; 2899 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2900 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2901 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2902 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2903 } else if (IS_QLA83XX(ha)) { 2904 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2905 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2906 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2907 req_length = REQUEST_ENTRY_CNT_83XX; 2908 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2909 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2911 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2912 ha->gid_list_info_size = 8; 2913 ha->optrom_size = OPTROM_SIZE_83XX; 2914 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2915 ha->isp_ops = &qla83xx_isp_ops; 2916 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2917 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2918 ha->nvram_conf_off = ~0; 2919 ha->nvram_data_off = ~0; 2920 } else if (IS_QLAFX00(ha)) { 2921 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2922 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2923 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2924 req_length = REQUEST_ENTRY_CNT_FX00; 2925 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2926 ha->isp_ops = &qlafx00_isp_ops; 2927 ha->port_down_retry_count = 30; /* default value */ 2928 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2929 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2930 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2931 ha->mr.fw_hbt_en = 1; 2932 ha->mr.host_info_resend = false; 2933 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2934 } else if (IS_QLA27XX(ha)) { 2935 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2936 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2937 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2938 req_length = REQUEST_ENTRY_CNT_83XX; 2939 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2940 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2941 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2942 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2943 ha->gid_list_info_size = 8; 2944 ha->optrom_size = OPTROM_SIZE_83XX; 2945 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2946 ha->isp_ops = &qla27xx_isp_ops; 2947 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2948 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2949 ha->nvram_conf_off = ~0; 2950 ha->nvram_data_off = ~0; 2951 } 2952 2953 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2954 "mbx_count=%d, req_length=%d, " 2955 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2956 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2957 "max_fibre_devices=%d.\n", 2958 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2959 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2960 ha->nvram_npiv_size, ha->max_fibre_devices); 2961 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2962 "isp_ops=%p, flash_conf_off=%d, " 2963 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2964 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2965 ha->nvram_conf_off, ha->nvram_data_off); 2966 2967 /* Configure PCI I/O space */ 2968 ret = ha->isp_ops->iospace_config(ha); 2969 if (ret) 2970 goto iospace_config_failed; 2971 2972 ql_log_pci(ql_log_info, pdev, 0x001d, 2973 "Found an ISP%04X irq %d iobase 0x%p.\n", 2974 pdev->device, pdev->irq, ha->iobase); 2975 mutex_init(&ha->vport_lock); 2976 mutex_init(&ha->mq_lock); 2977 init_completion(&ha->mbx_cmd_comp); 2978 complete(&ha->mbx_cmd_comp); 2979 init_completion(&ha->mbx_intr_comp); 2980 init_completion(&ha->dcbx_comp); 2981 init_completion(&ha->lb_portup_comp); 2982 2983 set_bit(0, (unsigned long *) ha->vp_idx_map); 2984 2985 qla2x00_config_dma_addressing(ha); 2986 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2987 "64 Bit addressing is %s.\n", 2988 ha->flags.enable_64bit_addressing ? "enable" : 2989 "disable"); 2990 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2991 if (ret) { 2992 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2993 "Failed to allocate memory for adapter, aborting.\n"); 2994 2995 goto probe_hw_failed; 2996 } 2997 2998 req->max_q_depth = MAX_Q_DEPTH; 2999 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3000 req->max_q_depth = ql2xmaxqdepth; 3001 3002 3003 base_vha = qla2x00_create_host(sht, ha); 3004 if (!base_vha) { 3005 ret = -ENOMEM; 3006 qla2x00_mem_free(ha); 3007 qla2x00_free_req_que(ha, req); 3008 qla2x00_free_rsp_que(ha, rsp); 3009 goto probe_hw_failed; 3010 } 3011 3012 pci_set_drvdata(pdev, base_vha); 3013 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3014 3015 host = base_vha->host; 3016 base_vha->req = req; 3017 if (IS_QLA2XXX_MIDTYPE(ha)) 3018 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 3019 else 3020 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3021 base_vha->vp_idx; 3022 3023 /* Setup fcport template structure. */ 3024 ha->mr.fcport.vha = base_vha; 3025 ha->mr.fcport.port_type = FCT_UNKNOWN; 3026 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3027 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3028 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3029 ha->mr.fcport.scan_state = 1; 3030 3031 /* Set the SG table size based on ISP type */ 3032 if (!IS_FWI2_CAPABLE(ha)) { 3033 if (IS_QLA2100(ha)) 3034 host->sg_tablesize = 32; 3035 } else { 3036 if (!IS_QLA82XX(ha)) 3037 host->sg_tablesize = QLA_SG_ALL; 3038 } 3039 host->max_id = ha->max_fibre_devices; 3040 host->cmd_per_lun = 3; 3041 host->unique_id = host->host_no; 3042 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3043 host->max_cmd_len = 32; 3044 else 3045 host->max_cmd_len = MAX_CMDSZ; 3046 host->max_channel = MAX_BUSES - 1; 3047 /* Older HBAs support only 16-bit LUNs */ 3048 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3049 ql2xmaxlun > 0xffff) 3050 host->max_lun = 0xffff; 3051 else 3052 host->max_lun = ql2xmaxlun; 3053 host->transportt = qla2xxx_transport_template; 3054 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3055 3056 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3057 "max_id=%d this_id=%d " 3058 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3059 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3060 host->this_id, host->cmd_per_lun, host->unique_id, 3061 host->max_cmd_len, host->max_channel, host->max_lun, 3062 host->transportt, sht->vendor_id); 3063 3064 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3065 3066 /* Set up the irqs */ 3067 ret = qla2x00_request_irqs(ha, rsp); 3068 if (ret) 3069 goto probe_init_failed; 3070 3071 /* Alloc arrays of request and response ring ptrs */ 3072 if (!qla2x00_alloc_queues(ha, req, rsp)) { 3073 ql_log(ql_log_fatal, base_vha, 0x003d, 3074 "Failed to allocate memory for queue pointers..." 3075 "aborting.\n"); 3076 goto probe_init_failed; 3077 } 3078 3079 if (ha->mqenable && shost_use_blk_mq(host)) { 3080 /* number of hardware queues supported by blk/scsi-mq*/ 3081 host->nr_hw_queues = ha->max_qpairs; 3082 3083 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3084 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3085 } else 3086 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3087 "blk/scsi-mq disabled.\n"); 3088 3089 qlt_probe_one_stage1(base_vha, ha); 3090 3091 pci_save_state(pdev); 3092 3093 /* Assign back pointers */ 3094 rsp->req = req; 3095 req->rsp = rsp; 3096 3097 if (IS_QLAFX00(ha)) { 3098 ha->rsp_q_map[0] = rsp; 3099 ha->req_q_map[0] = req; 3100 set_bit(0, ha->req_qid_map); 3101 set_bit(0, ha->rsp_qid_map); 3102 } 3103 3104 /* FWI2-capable only. */ 3105 req->req_q_in = &ha->iobase->isp24.req_q_in; 3106 req->req_q_out = &ha->iobase->isp24.req_q_out; 3107 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3108 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3109 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3110 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3111 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3112 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3113 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3114 } 3115 3116 if (IS_QLAFX00(ha)) { 3117 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3118 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3119 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3120 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3121 } 3122 3123 if (IS_P3P_TYPE(ha)) { 3124 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3125 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3126 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3127 } 3128 3129 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3130 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3131 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3132 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3133 "req->req_q_in=%p req->req_q_out=%p " 3134 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3135 req->req_q_in, req->req_q_out, 3136 rsp->rsp_q_in, rsp->rsp_q_out); 3137 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3138 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3139 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3140 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3141 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3142 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3143 3144 if (ha->isp_ops->initialize_adapter(base_vha)) { 3145 ql_log(ql_log_fatal, base_vha, 0x00d6, 3146 "Failed to initialize adapter - Adapter flags %x.\n", 3147 base_vha->device_flags); 3148 3149 if (IS_QLA82XX(ha)) { 3150 qla82xx_idc_lock(ha); 3151 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3152 QLA8XXX_DEV_FAILED); 3153 qla82xx_idc_unlock(ha); 3154 ql_log(ql_log_fatal, base_vha, 0x00d7, 3155 "HW State: FAILED.\n"); 3156 } else if (IS_QLA8044(ha)) { 3157 qla8044_idc_lock(ha); 3158 qla8044_wr_direct(base_vha, 3159 QLA8044_CRB_DEV_STATE_INDEX, 3160 QLA8XXX_DEV_FAILED); 3161 qla8044_idc_unlock(ha); 3162 ql_log(ql_log_fatal, base_vha, 0x0150, 3163 "HW State: FAILED.\n"); 3164 } 3165 3166 ret = -ENODEV; 3167 goto probe_failed; 3168 } 3169 3170 if (IS_QLAFX00(ha)) 3171 host->can_queue = QLAFX00_MAX_CANQUEUE; 3172 else 3173 host->can_queue = req->num_outstanding_cmds - 10; 3174 3175 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3176 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3177 host->can_queue, base_vha->req, 3178 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3179 3180 if (ha->mqenable) { 3181 bool mq = false; 3182 bool startit = false; 3183 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3184 3185 if (QLA_TGT_MODE_ENABLED()) { 3186 mq = true; 3187 startit = false; 3188 } 3189 3190 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3191 shost_use_blk_mq(host)) { 3192 mq = true; 3193 startit = true; 3194 } 3195 3196 if (mq) { 3197 /* Create start of day qpairs for Block MQ */ 3198 for (i = 0; i < ha->max_qpairs; i++) 3199 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3200 } 3201 } 3202 3203 if (ha->flags.running_gold_fw) 3204 goto skip_dpc; 3205 3206 /* 3207 * Startup the kernel thread for this host adapter 3208 */ 3209 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3210 "%s_dpc", base_vha->host_str); 3211 if (IS_ERR(ha->dpc_thread)) { 3212 ql_log(ql_log_fatal, base_vha, 0x00ed, 3213 "Failed to start DPC thread.\n"); 3214 ret = PTR_ERR(ha->dpc_thread); 3215 ha->dpc_thread = NULL; 3216 goto probe_failed; 3217 } 3218 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3219 "DPC thread started successfully.\n"); 3220 3221 /* 3222 * If we're not coming up in initiator mode, we might sit for 3223 * a while without waking up the dpc thread, which leads to a 3224 * stuck process warning. So just kick the dpc once here and 3225 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3226 */ 3227 qla2xxx_wake_dpc(base_vha); 3228 3229 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3230 3231 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3232 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3233 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3234 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3235 3236 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3237 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3238 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3239 INIT_WORK(&ha->idc_state_handler, 3240 qla83xx_idc_state_handler_work); 3241 INIT_WORK(&ha->nic_core_unrecoverable, 3242 qla83xx_nic_core_unrecoverable_work); 3243 } 3244 3245 skip_dpc: 3246 list_add_tail(&base_vha->list, &ha->vp_list); 3247 base_vha->host->irq = ha->pdev->irq; 3248 3249 /* Initialized the timer */ 3250 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 3251 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3252 "Started qla2x00_timer with " 3253 "interval=%d.\n", WATCH_INTERVAL); 3254 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3255 "Detected hba at address=%p.\n", 3256 ha); 3257 3258 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3259 if (ha->fw_attributes & BIT_4) { 3260 int prot = 0, guard; 3261 base_vha->flags.difdix_supported = 1; 3262 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3263 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3264 if (ql2xenabledif == 1) 3265 prot = SHOST_DIX_TYPE0_PROTECTION; 3266 scsi_host_set_prot(host, 3267 prot | SHOST_DIF_TYPE1_PROTECTION 3268 | SHOST_DIF_TYPE2_PROTECTION 3269 | SHOST_DIF_TYPE3_PROTECTION 3270 | SHOST_DIX_TYPE1_PROTECTION 3271 | SHOST_DIX_TYPE2_PROTECTION 3272 | SHOST_DIX_TYPE3_PROTECTION); 3273 3274 guard = SHOST_DIX_GUARD_CRC; 3275 3276 if (IS_PI_IPGUARD_CAPABLE(ha) && 3277 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3278 guard |= SHOST_DIX_GUARD_IP; 3279 3280 scsi_host_set_guard(host, guard); 3281 } else 3282 base_vha->flags.difdix_supported = 0; 3283 } 3284 3285 ha->isp_ops->enable_intrs(ha); 3286 3287 if (IS_QLAFX00(ha)) { 3288 ret = qlafx00_fx_disc(base_vha, 3289 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3290 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3291 QLA_SG_ALL : 128; 3292 } 3293 3294 ret = scsi_add_host(host, &pdev->dev); 3295 if (ret) 3296 goto probe_failed; 3297 3298 base_vha->flags.init_done = 1; 3299 base_vha->flags.online = 1; 3300 ha->prev_minidump_failed = 0; 3301 3302 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3303 "Init done and hba is online.\n"); 3304 3305 if (qla_ini_mode_enabled(base_vha) || 3306 qla_dual_mode_enabled(base_vha)) 3307 scsi_scan_host(host); 3308 else 3309 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3310 "skipping scsi_scan_host() for non-initiator port\n"); 3311 3312 qla2x00_alloc_sysfs_attr(base_vha); 3313 3314 if (IS_QLAFX00(ha)) { 3315 ret = qlafx00_fx_disc(base_vha, 3316 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3317 3318 /* Register system information */ 3319 ret = qlafx00_fx_disc(base_vha, 3320 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3321 } 3322 3323 qla2x00_init_host_attr(base_vha); 3324 3325 qla2x00_dfs_setup(base_vha); 3326 3327 ql_log(ql_log_info, base_vha, 0x00fb, 3328 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3329 ql_log(ql_log_info, base_vha, 0x00fc, 3330 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3331 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3332 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3333 base_vha->host_no, 3334 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3335 3336 qlt_add_target(ha, base_vha); 3337 3338 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3339 3340 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3341 return -ENODEV; 3342 3343 if (ha->flags.detected_lr_sfp) { 3344 ql_log(ql_log_info, base_vha, 0xffff, 3345 "Reset chip to pick up LR SFP setting\n"); 3346 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3347 qla2xxx_wake_dpc(base_vha); 3348 } 3349 3350 return 0; 3351 3352 probe_init_failed: 3353 qla2x00_free_req_que(ha, req); 3354 ha->req_q_map[0] = NULL; 3355 clear_bit(0, ha->req_qid_map); 3356 qla2x00_free_rsp_que(ha, rsp); 3357 ha->rsp_q_map[0] = NULL; 3358 clear_bit(0, ha->rsp_qid_map); 3359 ha->max_req_queues = ha->max_rsp_queues = 0; 3360 3361 probe_failed: 3362 if (base_vha->timer_active) 3363 qla2x00_stop_timer(base_vha); 3364 base_vha->flags.online = 0; 3365 if (ha->dpc_thread) { 3366 struct task_struct *t = ha->dpc_thread; 3367 3368 ha->dpc_thread = NULL; 3369 kthread_stop(t); 3370 } 3371 3372 qla2x00_free_device(base_vha); 3373 3374 scsi_host_put(base_vha->host); 3375 3376 probe_hw_failed: 3377 qla2x00_clear_drv_active(ha); 3378 3379 iospace_config_failed: 3380 if (IS_P3P_TYPE(ha)) { 3381 if (!ha->nx_pcibase) 3382 iounmap((device_reg_t *)ha->nx_pcibase); 3383 if (!ql2xdbwr) 3384 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3385 } else { 3386 if (ha->iobase) 3387 iounmap(ha->iobase); 3388 if (ha->cregbase) 3389 iounmap(ha->cregbase); 3390 } 3391 pci_release_selected_regions(ha->pdev, ha->bars); 3392 kfree(ha); 3393 3394 disable_device: 3395 pci_disable_device(pdev); 3396 return ret; 3397 } 3398 3399 static void 3400 qla2x00_shutdown(struct pci_dev *pdev) 3401 { 3402 scsi_qla_host_t *vha; 3403 struct qla_hw_data *ha; 3404 3405 vha = pci_get_drvdata(pdev); 3406 ha = vha->hw; 3407 3408 ql_log(ql_log_info, vha, 0xfffa, 3409 "Adapter shutdown\n"); 3410 3411 /* 3412 * Prevent future board_disable and wait 3413 * until any pending board_disable has completed. 3414 */ 3415 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3416 cancel_work_sync(&ha->board_disable); 3417 3418 if (!atomic_read(&pdev->enable_cnt)) 3419 return; 3420 3421 /* Notify ISPFX00 firmware */ 3422 if (IS_QLAFX00(ha)) 3423 qlafx00_driver_shutdown(vha, 20); 3424 3425 /* Turn-off FCE trace */ 3426 if (ha->flags.fce_enabled) { 3427 qla2x00_disable_fce_trace(vha, NULL, NULL); 3428 ha->flags.fce_enabled = 0; 3429 } 3430 3431 /* Turn-off EFT trace */ 3432 if (ha->eft) 3433 qla2x00_disable_eft_trace(vha); 3434 3435 /* Stop currently executing firmware. */ 3436 qla2x00_try_to_stop_firmware(vha); 3437 3438 /* Turn adapter off line */ 3439 vha->flags.online = 0; 3440 3441 /* turn-off interrupts on the card */ 3442 if (ha->interrupts_on) { 3443 vha->flags.init_done = 0; 3444 ha->isp_ops->disable_intrs(ha); 3445 } 3446 3447 qla2x00_free_irqs(vha); 3448 3449 qla2x00_free_fw_dump(ha); 3450 3451 pci_disable_device(pdev); 3452 ql_log(ql_log_info, vha, 0xfffe, 3453 "Adapter shutdown successfully.\n"); 3454 } 3455 3456 /* Deletes all the virtual ports for a given ha */ 3457 static void 3458 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3459 { 3460 scsi_qla_host_t *vha; 3461 unsigned long flags; 3462 3463 mutex_lock(&ha->vport_lock); 3464 while (ha->cur_vport_count) { 3465 spin_lock_irqsave(&ha->vport_slock, flags); 3466 3467 BUG_ON(base_vha->list.next == &ha->vp_list); 3468 /* This assumes first entry in ha->vp_list is always base vha */ 3469 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3470 scsi_host_get(vha->host); 3471 3472 spin_unlock_irqrestore(&ha->vport_slock, flags); 3473 mutex_unlock(&ha->vport_lock); 3474 3475 fc_vport_terminate(vha->fc_vport); 3476 scsi_host_put(vha->host); 3477 3478 mutex_lock(&ha->vport_lock); 3479 } 3480 mutex_unlock(&ha->vport_lock); 3481 } 3482 3483 /* Stops all deferred work threads */ 3484 static void 3485 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3486 { 3487 /* Cancel all work and destroy DPC workqueues */ 3488 if (ha->dpc_lp_wq) { 3489 cancel_work_sync(&ha->idc_aen); 3490 destroy_workqueue(ha->dpc_lp_wq); 3491 ha->dpc_lp_wq = NULL; 3492 } 3493 3494 if (ha->dpc_hp_wq) { 3495 cancel_work_sync(&ha->nic_core_reset); 3496 cancel_work_sync(&ha->idc_state_handler); 3497 cancel_work_sync(&ha->nic_core_unrecoverable); 3498 destroy_workqueue(ha->dpc_hp_wq); 3499 ha->dpc_hp_wq = NULL; 3500 } 3501 3502 /* Kill the kernel thread for this host */ 3503 if (ha->dpc_thread) { 3504 struct task_struct *t = ha->dpc_thread; 3505 3506 /* 3507 * qla2xxx_wake_dpc checks for ->dpc_thread 3508 * so we need to zero it out. 3509 */ 3510 ha->dpc_thread = NULL; 3511 kthread_stop(t); 3512 } 3513 } 3514 3515 static void 3516 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3517 { 3518 if (IS_QLA82XX(ha)) { 3519 3520 iounmap((device_reg_t *)ha->nx_pcibase); 3521 if (!ql2xdbwr) 3522 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3523 } else { 3524 if (ha->iobase) 3525 iounmap(ha->iobase); 3526 3527 if (ha->cregbase) 3528 iounmap(ha->cregbase); 3529 3530 if (ha->mqiobase) 3531 iounmap(ha->mqiobase); 3532 3533 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3534 iounmap(ha->msixbase); 3535 } 3536 } 3537 3538 static void 3539 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3540 { 3541 if (IS_QLA8044(ha)) { 3542 qla8044_idc_lock(ha); 3543 qla8044_clear_drv_active(ha); 3544 qla8044_idc_unlock(ha); 3545 } else if (IS_QLA82XX(ha)) { 3546 qla82xx_idc_lock(ha); 3547 qla82xx_clear_drv_active(ha); 3548 qla82xx_idc_unlock(ha); 3549 } 3550 } 3551 3552 static void 3553 qla2x00_remove_one(struct pci_dev *pdev) 3554 { 3555 scsi_qla_host_t *base_vha; 3556 struct qla_hw_data *ha; 3557 3558 base_vha = pci_get_drvdata(pdev); 3559 ha = base_vha->hw; 3560 3561 /* Indicate device removal to prevent future board_disable and wait 3562 * until any pending board_disable has completed. */ 3563 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3564 cancel_work_sync(&ha->board_disable); 3565 3566 /* 3567 * If the PCI device is disabled then there was a PCI-disconnect and 3568 * qla2x00_disable_board_on_pci_error has taken care of most of the 3569 * resources. 3570 */ 3571 if (!atomic_read(&pdev->enable_cnt)) { 3572 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3573 base_vha->gnl.l, base_vha->gnl.ldma); 3574 3575 scsi_host_put(base_vha->host); 3576 kfree(ha); 3577 pci_set_drvdata(pdev, NULL); 3578 return; 3579 } 3580 qla2x00_wait_for_hba_ready(base_vha); 3581 3582 /* 3583 * if UNLOAD flag is already set, then continue unload, 3584 * where it was set first. 3585 */ 3586 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3587 return; 3588 3589 set_bit(UNLOADING, &base_vha->dpc_flags); 3590 3591 qla_nvme_delete(base_vha); 3592 3593 dma_free_coherent(&ha->pdev->dev, 3594 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3595 3596 if (IS_QLAFX00(ha)) 3597 qlafx00_driver_shutdown(base_vha, 20); 3598 3599 qla2x00_delete_all_vps(ha, base_vha); 3600 3601 if (IS_QLA8031(ha)) { 3602 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3603 "Clearing fcoe driver presence.\n"); 3604 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3605 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3606 "Error while clearing DRV-Presence.\n"); 3607 } 3608 3609 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3610 3611 qla2x00_dfs_remove(base_vha); 3612 3613 qla84xx_put_chip(base_vha); 3614 3615 /* Laser should be disabled only for ISP2031 */ 3616 if (IS_QLA2031(ha)) 3617 qla83xx_disable_laser(base_vha); 3618 3619 /* Disable timer */ 3620 if (base_vha->timer_active) 3621 qla2x00_stop_timer(base_vha); 3622 3623 base_vha->flags.online = 0; 3624 3625 /* free DMA memory */ 3626 if (ha->exlogin_buf) 3627 qla2x00_free_exlogin_buffer(ha); 3628 3629 /* free DMA memory */ 3630 if (ha->exchoffld_buf) 3631 qla2x00_free_exchoffld_buffer(ha); 3632 3633 qla2x00_destroy_deferred_work(ha); 3634 3635 qlt_remove_target(ha, base_vha); 3636 3637 qla2x00_free_sysfs_attr(base_vha, true); 3638 3639 fc_remove_host(base_vha->host); 3640 qlt_remove_target_resources(ha); 3641 3642 scsi_remove_host(base_vha->host); 3643 3644 qla2x00_free_device(base_vha); 3645 3646 qla2x00_clear_drv_active(ha); 3647 3648 scsi_host_put(base_vha->host); 3649 3650 qla2x00_unmap_iobases(ha); 3651 3652 pci_release_selected_regions(ha->pdev, ha->bars); 3653 kfree(ha); 3654 3655 pci_disable_pcie_error_reporting(pdev); 3656 3657 pci_disable_device(pdev); 3658 } 3659 3660 static void 3661 qla2x00_free_device(scsi_qla_host_t *vha) 3662 { 3663 struct qla_hw_data *ha = vha->hw; 3664 3665 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3666 3667 /* Disable timer */ 3668 if (vha->timer_active) 3669 qla2x00_stop_timer(vha); 3670 3671 qla25xx_delete_queues(vha); 3672 3673 if (ha->flags.fce_enabled) 3674 qla2x00_disable_fce_trace(vha, NULL, NULL); 3675 3676 if (ha->eft) 3677 qla2x00_disable_eft_trace(vha); 3678 3679 /* Stop currently executing firmware. */ 3680 qla2x00_try_to_stop_firmware(vha); 3681 3682 vha->flags.online = 0; 3683 3684 /* turn-off interrupts on the card */ 3685 if (ha->interrupts_on) { 3686 vha->flags.init_done = 0; 3687 ha->isp_ops->disable_intrs(ha); 3688 } 3689 3690 qla2x00_free_fcports(vha); 3691 3692 qla2x00_free_irqs(vha); 3693 3694 /* Flush the work queue and remove it */ 3695 if (ha->wq) { 3696 flush_workqueue(ha->wq); 3697 destroy_workqueue(ha->wq); 3698 ha->wq = NULL; 3699 } 3700 3701 3702 qla2x00_mem_free(ha); 3703 3704 qla82xx_md_free(vha); 3705 3706 qla2x00_free_queues(ha); 3707 } 3708 3709 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3710 { 3711 fc_port_t *fcport, *tfcport; 3712 3713 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3714 list_del(&fcport->list); 3715 qla2x00_clear_loop_id(fcport); 3716 kfree(fcport); 3717 } 3718 } 3719 3720 static inline void 3721 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3722 int defer) 3723 { 3724 struct fc_rport *rport; 3725 scsi_qla_host_t *base_vha; 3726 unsigned long flags; 3727 3728 if (!fcport->rport) 3729 return; 3730 3731 rport = fcport->rport; 3732 if (defer) { 3733 base_vha = pci_get_drvdata(vha->hw->pdev); 3734 spin_lock_irqsave(vha->host->host_lock, flags); 3735 fcport->drport = rport; 3736 spin_unlock_irqrestore(vha->host->host_lock, flags); 3737 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3738 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3739 qla2xxx_wake_dpc(base_vha); 3740 } else { 3741 int now; 3742 if (rport) { 3743 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3744 "%s %8phN. rport %p roles %x\n", 3745 __func__, fcport->port_name, rport, 3746 rport->roles); 3747 fc_remote_port_delete(rport); 3748 } 3749 qlt_do_generation_tick(vha, &now); 3750 } 3751 } 3752 3753 /* 3754 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3755 * 3756 * Input: ha = adapter block pointer. fcport = port structure pointer. 3757 * 3758 * Return: None. 3759 * 3760 * Context: 3761 */ 3762 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3763 int do_login, int defer) 3764 { 3765 if (IS_QLAFX00(vha->hw)) { 3766 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3767 qla2x00_schedule_rport_del(vha, fcport, defer); 3768 return; 3769 } 3770 3771 if (atomic_read(&fcport->state) == FCS_ONLINE && 3772 vha->vp_idx == fcport->vha->vp_idx) { 3773 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3774 qla2x00_schedule_rport_del(vha, fcport, defer); 3775 } 3776 /* 3777 * We may need to retry the login, so don't change the state of the 3778 * port but do the retries. 3779 */ 3780 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3781 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3782 3783 if (!do_login) 3784 return; 3785 3786 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3787 3788 if (fcport->login_retry == 0) { 3789 fcport->login_retry = vha->hw->login_retry_count; 3790 3791 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3792 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3793 fcport->port_name, fcport->loop_id, fcport->login_retry); 3794 } 3795 } 3796 3797 /* 3798 * qla2x00_mark_all_devices_lost 3799 * Updates fcport state when device goes offline. 3800 * 3801 * Input: 3802 * ha = adapter block pointer. 3803 * fcport = port structure pointer. 3804 * 3805 * Return: 3806 * None. 3807 * 3808 * Context: 3809 */ 3810 void 3811 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3812 { 3813 fc_port_t *fcport; 3814 3815 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3816 "Mark all dev lost\n"); 3817 3818 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3819 fcport->scan_state = 0; 3820 qlt_schedule_sess_for_deletion_lock(fcport); 3821 3822 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3823 continue; 3824 3825 /* 3826 * No point in marking the device as lost, if the device is 3827 * already DEAD. 3828 */ 3829 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3830 continue; 3831 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3832 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3833 if (defer) 3834 qla2x00_schedule_rport_del(vha, fcport, defer); 3835 else if (vha->vp_idx == fcport->vha->vp_idx) 3836 qla2x00_schedule_rport_del(vha, fcport, defer); 3837 } 3838 } 3839 } 3840 3841 /* 3842 * qla2x00_mem_alloc 3843 * Allocates adapter memory. 3844 * 3845 * Returns: 3846 * 0 = success. 3847 * !0 = failure. 3848 */ 3849 static int 3850 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3851 struct req_que **req, struct rsp_que **rsp) 3852 { 3853 char name[16]; 3854 3855 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3856 &ha->init_cb_dma, GFP_KERNEL); 3857 if (!ha->init_cb) 3858 goto fail; 3859 3860 if (qlt_mem_alloc(ha) < 0) 3861 goto fail_free_init_cb; 3862 3863 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3864 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3865 if (!ha->gid_list) 3866 goto fail_free_tgt_mem; 3867 3868 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3869 if (!ha->srb_mempool) 3870 goto fail_free_gid_list; 3871 3872 if (IS_P3P_TYPE(ha)) { 3873 /* Allocate cache for CT6 Ctx. */ 3874 if (!ctx_cachep) { 3875 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3876 sizeof(struct ct6_dsd), 0, 3877 SLAB_HWCACHE_ALIGN, NULL); 3878 if (!ctx_cachep) 3879 goto fail_free_srb_mempool; 3880 } 3881 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3882 ctx_cachep); 3883 if (!ha->ctx_mempool) 3884 goto fail_free_srb_mempool; 3885 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3886 "ctx_cachep=%p ctx_mempool=%p.\n", 3887 ctx_cachep, ha->ctx_mempool); 3888 } 3889 3890 /* Get memory for cached NVRAM */ 3891 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3892 if (!ha->nvram) 3893 goto fail_free_ctx_mempool; 3894 3895 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3896 ha->pdev->device); 3897 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3898 DMA_POOL_SIZE, 8, 0); 3899 if (!ha->s_dma_pool) 3900 goto fail_free_nvram; 3901 3902 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3903 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3904 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3905 3906 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3907 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3908 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3909 if (!ha->dl_dma_pool) { 3910 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3911 "Failed to allocate memory for dl_dma_pool.\n"); 3912 goto fail_s_dma_pool; 3913 } 3914 3915 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3916 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3917 if (!ha->fcp_cmnd_dma_pool) { 3918 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3919 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3920 goto fail_dl_dma_pool; 3921 } 3922 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3923 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3924 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3925 } 3926 3927 /* Allocate memory for SNS commands */ 3928 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3929 /* Get consistent memory allocated for SNS commands */ 3930 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3931 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3932 if (!ha->sns_cmd) 3933 goto fail_dma_pool; 3934 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3935 "sns_cmd: %p.\n", ha->sns_cmd); 3936 } else { 3937 /* Get consistent memory allocated for MS IOCB */ 3938 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3939 &ha->ms_iocb_dma); 3940 if (!ha->ms_iocb) 3941 goto fail_dma_pool; 3942 /* Get consistent memory allocated for CT SNS commands */ 3943 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3944 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3945 if (!ha->ct_sns) 3946 goto fail_free_ms_iocb; 3947 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3948 "ms_iocb=%p ct_sns=%p.\n", 3949 ha->ms_iocb, ha->ct_sns); 3950 } 3951 3952 /* Allocate memory for request ring */ 3953 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3954 if (!*req) { 3955 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3956 "Failed to allocate memory for req.\n"); 3957 goto fail_req; 3958 } 3959 (*req)->length = req_len; 3960 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3961 ((*req)->length + 1) * sizeof(request_t), 3962 &(*req)->dma, GFP_KERNEL); 3963 if (!(*req)->ring) { 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3965 "Failed to allocate memory for req_ring.\n"); 3966 goto fail_req_ring; 3967 } 3968 /* Allocate memory for response ring */ 3969 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3970 if (!*rsp) { 3971 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3972 "Failed to allocate memory for rsp.\n"); 3973 goto fail_rsp; 3974 } 3975 (*rsp)->hw = ha; 3976 (*rsp)->length = rsp_len; 3977 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3978 ((*rsp)->length + 1) * sizeof(response_t), 3979 &(*rsp)->dma, GFP_KERNEL); 3980 if (!(*rsp)->ring) { 3981 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3982 "Failed to allocate memory for rsp_ring.\n"); 3983 goto fail_rsp_ring; 3984 } 3985 (*req)->rsp = *rsp; 3986 (*rsp)->req = *req; 3987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3988 "req=%p req->length=%d req->ring=%p rsp=%p " 3989 "rsp->length=%d rsp->ring=%p.\n", 3990 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3991 (*rsp)->ring); 3992 /* Allocate memory for NVRAM data for vports */ 3993 if (ha->nvram_npiv_size) { 3994 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3995 ha->nvram_npiv_size, GFP_KERNEL); 3996 if (!ha->npiv_info) { 3997 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3998 "Failed to allocate memory for npiv_info.\n"); 3999 goto fail_npiv_info; 4000 } 4001 } else 4002 ha->npiv_info = NULL; 4003 4004 /* Get consistent memory allocated for EX-INIT-CB. */ 4005 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4006 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4007 &ha->ex_init_cb_dma); 4008 if (!ha->ex_init_cb) 4009 goto fail_ex_init_cb; 4010 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4011 "ex_init_cb=%p.\n", ha->ex_init_cb); 4012 } 4013 4014 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4015 4016 /* Get consistent memory allocated for Async Port-Database. */ 4017 if (!IS_FWI2_CAPABLE(ha)) { 4018 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4019 &ha->async_pd_dma); 4020 if (!ha->async_pd) 4021 goto fail_async_pd; 4022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4023 "async_pd=%p.\n", ha->async_pd); 4024 } 4025 4026 INIT_LIST_HEAD(&ha->vp_list); 4027 4028 /* Allocate memory for our loop_id bitmap */ 4029 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 4030 GFP_KERNEL); 4031 if (!ha->loop_id_map) 4032 goto fail_loop_id_map; 4033 else { 4034 qla2x00_set_reserved_loop_ids(ha); 4035 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4036 "loop_id_map=%p.\n", ha->loop_id_map); 4037 } 4038 4039 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4040 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4041 if (!ha->sfp_data) { 4042 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4043 "Unable to allocate memory for SFP read-data.\n"); 4044 goto fail_sfp_data; 4045 } 4046 4047 return 0; 4048 4049 fail_sfp_data: 4050 kfree(ha->loop_id_map); 4051 fail_loop_id_map: 4052 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4053 fail_async_pd: 4054 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4055 fail_ex_init_cb: 4056 kfree(ha->npiv_info); 4057 fail_npiv_info: 4058 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4059 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4060 (*rsp)->ring = NULL; 4061 (*rsp)->dma = 0; 4062 fail_rsp_ring: 4063 kfree(*rsp); 4064 fail_rsp: 4065 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4066 sizeof(request_t), (*req)->ring, (*req)->dma); 4067 (*req)->ring = NULL; 4068 (*req)->dma = 0; 4069 fail_req_ring: 4070 kfree(*req); 4071 fail_req: 4072 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4073 ha->ct_sns, ha->ct_sns_dma); 4074 ha->ct_sns = NULL; 4075 ha->ct_sns_dma = 0; 4076 fail_free_ms_iocb: 4077 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4078 ha->ms_iocb = NULL; 4079 ha->ms_iocb_dma = 0; 4080 4081 if (ha->sns_cmd) 4082 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4083 ha->sns_cmd, ha->sns_cmd_dma); 4084 fail_dma_pool: 4085 if (IS_QLA82XX(ha) || ql2xenabledif) { 4086 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4087 ha->fcp_cmnd_dma_pool = NULL; 4088 } 4089 fail_dl_dma_pool: 4090 if (IS_QLA82XX(ha) || ql2xenabledif) { 4091 dma_pool_destroy(ha->dl_dma_pool); 4092 ha->dl_dma_pool = NULL; 4093 } 4094 fail_s_dma_pool: 4095 dma_pool_destroy(ha->s_dma_pool); 4096 ha->s_dma_pool = NULL; 4097 fail_free_nvram: 4098 kfree(ha->nvram); 4099 ha->nvram = NULL; 4100 fail_free_ctx_mempool: 4101 if (ha->ctx_mempool) 4102 mempool_destroy(ha->ctx_mempool); 4103 ha->ctx_mempool = NULL; 4104 fail_free_srb_mempool: 4105 if (ha->srb_mempool) 4106 mempool_destroy(ha->srb_mempool); 4107 ha->srb_mempool = NULL; 4108 fail_free_gid_list: 4109 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4110 ha->gid_list, 4111 ha->gid_list_dma); 4112 ha->gid_list = NULL; 4113 ha->gid_list_dma = 0; 4114 fail_free_tgt_mem: 4115 qlt_mem_free(ha); 4116 fail_free_init_cb: 4117 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4118 ha->init_cb_dma); 4119 ha->init_cb = NULL; 4120 ha->init_cb_dma = 0; 4121 fail: 4122 ql_log(ql_log_fatal, NULL, 0x0030, 4123 "Memory allocation failure.\n"); 4124 return -ENOMEM; 4125 } 4126 4127 int 4128 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4129 { 4130 int rval; 4131 uint16_t size, max_cnt, temp; 4132 struct qla_hw_data *ha = vha->hw; 4133 4134 /* Return if we don't need to alloacate any extended logins */ 4135 if (!ql2xexlogins) 4136 return QLA_SUCCESS; 4137 4138 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4139 return QLA_SUCCESS; 4140 4141 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4142 max_cnt = 0; 4143 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4144 if (rval != QLA_SUCCESS) { 4145 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4146 "Failed to get exlogin status.\n"); 4147 return rval; 4148 } 4149 4150 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4151 temp *= size; 4152 4153 if (temp != ha->exlogin_size) { 4154 qla2x00_free_exlogin_buffer(ha); 4155 ha->exlogin_size = temp; 4156 4157 ql_log(ql_log_info, vha, 0xd024, 4158 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4159 max_cnt, size, temp); 4160 4161 ql_log(ql_log_info, vha, 0xd025, 4162 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4163 4164 /* Get consistent memory for extended logins */ 4165 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4166 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4167 if (!ha->exlogin_buf) { 4168 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4169 "Failed to allocate memory for exlogin_buf_dma.\n"); 4170 return -ENOMEM; 4171 } 4172 } 4173 4174 /* Now configure the dma buffer */ 4175 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4176 if (rval) { 4177 ql_log(ql_log_fatal, vha, 0xd033, 4178 "Setup extended login buffer ****FAILED****.\n"); 4179 qla2x00_free_exlogin_buffer(ha); 4180 } 4181 4182 return rval; 4183 } 4184 4185 /* 4186 * qla2x00_free_exlogin_buffer 4187 * 4188 * Input: 4189 * ha = adapter block pointer 4190 */ 4191 void 4192 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4193 { 4194 if (ha->exlogin_buf) { 4195 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4196 ha->exlogin_buf, ha->exlogin_buf_dma); 4197 ha->exlogin_buf = NULL; 4198 ha->exlogin_size = 0; 4199 } 4200 } 4201 4202 static void 4203 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4204 { 4205 u32 temp; 4206 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4207 4208 if (qla_ini_mode_enabled(vha)) { 4209 if (ql2xiniexchg > max_cnt) 4210 ql2xiniexchg = max_cnt; 4211 4212 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4213 *ret_cnt = ql2xiniexchg; 4214 } else if (qla_tgt_mode_enabled(vha)) { 4215 if (ql2xexchoffld > max_cnt) 4216 ql2xexchoffld = max_cnt; 4217 4218 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4219 *ret_cnt = ql2xexchoffld; 4220 } else if (qla_dual_mode_enabled(vha)) { 4221 temp = ql2xiniexchg + ql2xexchoffld; 4222 if (temp > max_cnt) { 4223 ql2xiniexchg -= (temp - max_cnt)/2; 4224 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4225 temp = max_cnt; 4226 } 4227 4228 if (temp > FW_DEF_EXCHANGES_CNT) 4229 *ret_cnt = temp; 4230 } 4231 } 4232 4233 int 4234 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4235 { 4236 int rval; 4237 u16 size, max_cnt; 4238 u32 temp; 4239 struct qla_hw_data *ha = vha->hw; 4240 4241 if (!ha->flags.exchoffld_enabled) 4242 return QLA_SUCCESS; 4243 4244 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4245 return QLA_SUCCESS; 4246 4247 max_cnt = 0; 4248 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4249 if (rval != QLA_SUCCESS) { 4250 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4251 "Failed to get exlogin status.\n"); 4252 return rval; 4253 } 4254 4255 qla2x00_number_of_exch(vha, &temp, max_cnt); 4256 temp *= size; 4257 4258 if (temp != ha->exchoffld_size) { 4259 qla2x00_free_exchoffld_buffer(ha); 4260 ha->exchoffld_size = temp; 4261 4262 ql_log(ql_log_info, vha, 0xd016, 4263 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 4264 max_cnt, size, temp); 4265 4266 ql_log(ql_log_info, vha, 0xd017, 4267 "Exchange Buffers requested size = 0x%x\n", 4268 ha->exchoffld_size); 4269 4270 /* Get consistent memory for extended logins */ 4271 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4272 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4273 if (!ha->exchoffld_buf) { 4274 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4275 "Failed to allocate memory for exchoffld_buf_dma.\n"); 4276 return -ENOMEM; 4277 } 4278 } 4279 4280 /* Now configure the dma buffer */ 4281 rval = qla_set_exchoffld_mem_cfg(vha); 4282 if (rval) { 4283 ql_log(ql_log_fatal, vha, 0xd02e, 4284 "Setup exchange offload buffer ****FAILED****.\n"); 4285 qla2x00_free_exchoffld_buffer(ha); 4286 } else { 4287 /* re-adjust number of target exchange */ 4288 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4289 4290 if (qla_ini_mode_enabled(vha)) 4291 icb->exchange_count = 0; 4292 else 4293 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4294 } 4295 4296 return rval; 4297 } 4298 4299 /* 4300 * qla2x00_free_exchoffld_buffer 4301 * 4302 * Input: 4303 * ha = adapter block pointer 4304 */ 4305 void 4306 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4307 { 4308 if (ha->exchoffld_buf) { 4309 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4310 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4311 ha->exchoffld_buf = NULL; 4312 ha->exchoffld_size = 0; 4313 } 4314 } 4315 4316 /* 4317 * qla2x00_free_fw_dump 4318 * Frees fw dump stuff. 4319 * 4320 * Input: 4321 * ha = adapter block pointer 4322 */ 4323 static void 4324 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4325 { 4326 if (ha->fce) 4327 dma_free_coherent(&ha->pdev->dev, 4328 FCE_SIZE, ha->fce, ha->fce_dma); 4329 4330 if (ha->eft) 4331 dma_free_coherent(&ha->pdev->dev, 4332 EFT_SIZE, ha->eft, ha->eft_dma); 4333 4334 if (ha->fw_dump) 4335 vfree(ha->fw_dump); 4336 if (ha->fw_dump_template) 4337 vfree(ha->fw_dump_template); 4338 4339 ha->fce = NULL; 4340 ha->fce_dma = 0; 4341 ha->eft = NULL; 4342 ha->eft_dma = 0; 4343 ha->fw_dumped = 0; 4344 ha->fw_dump_cap_flags = 0; 4345 ha->fw_dump_reading = 0; 4346 ha->fw_dump = NULL; 4347 ha->fw_dump_len = 0; 4348 ha->fw_dump_template = NULL; 4349 ha->fw_dump_template_len = 0; 4350 } 4351 4352 /* 4353 * qla2x00_mem_free 4354 * Frees all adapter allocated memory. 4355 * 4356 * Input: 4357 * ha = adapter block pointer. 4358 */ 4359 static void 4360 qla2x00_mem_free(struct qla_hw_data *ha) 4361 { 4362 qla2x00_free_fw_dump(ha); 4363 4364 if (ha->mctp_dump) 4365 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4366 ha->mctp_dump_dma); 4367 4368 if (ha->srb_mempool) 4369 mempool_destroy(ha->srb_mempool); 4370 4371 if (ha->dcbx_tlv) 4372 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4373 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4374 4375 if (ha->xgmac_data) 4376 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4377 ha->xgmac_data, ha->xgmac_data_dma); 4378 4379 if (ha->sns_cmd) 4380 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4381 ha->sns_cmd, ha->sns_cmd_dma); 4382 4383 if (ha->ct_sns) 4384 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4385 ha->ct_sns, ha->ct_sns_dma); 4386 4387 if (ha->sfp_data) 4388 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4389 ha->sfp_data_dma); 4390 4391 if (ha->ms_iocb) 4392 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4393 4394 if (ha->ex_init_cb) 4395 dma_pool_free(ha->s_dma_pool, 4396 ha->ex_init_cb, ha->ex_init_cb_dma); 4397 4398 if (ha->async_pd) 4399 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4400 4401 if (ha->s_dma_pool) 4402 dma_pool_destroy(ha->s_dma_pool); 4403 4404 if (ha->gid_list) 4405 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4406 ha->gid_list, ha->gid_list_dma); 4407 4408 if (IS_QLA82XX(ha)) { 4409 if (!list_empty(&ha->gbl_dsd_list)) { 4410 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4411 4412 /* clean up allocated prev pool */ 4413 list_for_each_entry_safe(dsd_ptr, 4414 tdsd_ptr, &ha->gbl_dsd_list, list) { 4415 dma_pool_free(ha->dl_dma_pool, 4416 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4417 list_del(&dsd_ptr->list); 4418 kfree(dsd_ptr); 4419 } 4420 } 4421 } 4422 4423 if (ha->dl_dma_pool) 4424 dma_pool_destroy(ha->dl_dma_pool); 4425 4426 if (ha->fcp_cmnd_dma_pool) 4427 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4428 4429 if (ha->ctx_mempool) 4430 mempool_destroy(ha->ctx_mempool); 4431 4432 qlt_mem_free(ha); 4433 4434 if (ha->init_cb) 4435 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4436 ha->init_cb, ha->init_cb_dma); 4437 vfree(ha->optrom_buffer); 4438 kfree(ha->nvram); 4439 kfree(ha->npiv_info); 4440 kfree(ha->swl); 4441 kfree(ha->loop_id_map); 4442 4443 ha->srb_mempool = NULL; 4444 ha->ctx_mempool = NULL; 4445 ha->sns_cmd = NULL; 4446 ha->sns_cmd_dma = 0; 4447 ha->ct_sns = NULL; 4448 ha->ct_sns_dma = 0; 4449 ha->ms_iocb = NULL; 4450 ha->ms_iocb_dma = 0; 4451 ha->init_cb = NULL; 4452 ha->init_cb_dma = 0; 4453 ha->ex_init_cb = NULL; 4454 ha->ex_init_cb_dma = 0; 4455 ha->async_pd = NULL; 4456 ha->async_pd_dma = 0; 4457 4458 ha->s_dma_pool = NULL; 4459 ha->dl_dma_pool = NULL; 4460 ha->fcp_cmnd_dma_pool = NULL; 4461 4462 ha->gid_list = NULL; 4463 ha->gid_list_dma = 0; 4464 4465 ha->tgt.atio_ring = NULL; 4466 ha->tgt.atio_dma = 0; 4467 ha->tgt.tgt_vp_map = NULL; 4468 } 4469 4470 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4471 struct qla_hw_data *ha) 4472 { 4473 struct Scsi_Host *host; 4474 struct scsi_qla_host *vha = NULL; 4475 4476 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4477 if (!host) { 4478 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4479 "Failed to allocate host from the scsi layer, aborting.\n"); 4480 return NULL; 4481 } 4482 4483 /* Clear our data area */ 4484 vha = shost_priv(host); 4485 memset(vha, 0, sizeof(scsi_qla_host_t)); 4486 4487 vha->host = host; 4488 vha->host_no = host->host_no; 4489 vha->hw = ha; 4490 4491 INIT_LIST_HEAD(&vha->vp_fcports); 4492 INIT_LIST_HEAD(&vha->work_list); 4493 INIT_LIST_HEAD(&vha->list); 4494 INIT_LIST_HEAD(&vha->qla_cmd_list); 4495 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4496 INIT_LIST_HEAD(&vha->logo_list); 4497 INIT_LIST_HEAD(&vha->plogi_ack_list); 4498 INIT_LIST_HEAD(&vha->qp_list); 4499 INIT_LIST_HEAD(&vha->gnl.fcports); 4500 INIT_LIST_HEAD(&vha->nvme_rport_list); 4501 4502 spin_lock_init(&vha->work_lock); 4503 spin_lock_init(&vha->cmd_list_lock); 4504 init_waitqueue_head(&vha->fcport_waitQ); 4505 init_waitqueue_head(&vha->vref_waitq); 4506 4507 vha->gnl.size = sizeof(struct get_name_list_extended) * 4508 (ha->max_loop_id + 1); 4509 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4510 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4511 if (!vha->gnl.l) { 4512 ql_log(ql_log_fatal, vha, 0xd04a, 4513 "Alloc failed for name list.\n"); 4514 scsi_remove_host(vha->host); 4515 return NULL; 4516 } 4517 4518 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4519 ql_dbg(ql_dbg_init, vha, 0x0041, 4520 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4521 vha->host, vha->hw, vha, 4522 dev_name(&(ha->pdev->dev))); 4523 4524 return vha; 4525 } 4526 4527 struct qla_work_evt * 4528 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4529 { 4530 struct qla_work_evt *e; 4531 uint8_t bail; 4532 4533 QLA_VHA_MARK_BUSY(vha, bail); 4534 if (bail) 4535 return NULL; 4536 4537 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4538 if (!e) { 4539 QLA_VHA_MARK_NOT_BUSY(vha); 4540 return NULL; 4541 } 4542 4543 INIT_LIST_HEAD(&e->list); 4544 e->type = type; 4545 e->flags = QLA_EVT_FLAG_FREE; 4546 return e; 4547 } 4548 4549 int 4550 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4551 { 4552 unsigned long flags; 4553 4554 spin_lock_irqsave(&vha->work_lock, flags); 4555 list_add_tail(&e->list, &vha->work_list); 4556 spin_unlock_irqrestore(&vha->work_lock, flags); 4557 4558 if (QLA_EARLY_LINKUP(vha->hw)) 4559 schedule_work(&vha->iocb_work); 4560 else 4561 qla2xxx_wake_dpc(vha); 4562 4563 return QLA_SUCCESS; 4564 } 4565 4566 int 4567 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4568 u32 data) 4569 { 4570 struct qla_work_evt *e; 4571 4572 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4573 if (!e) 4574 return QLA_FUNCTION_FAILED; 4575 4576 e->u.aen.code = code; 4577 e->u.aen.data = data; 4578 return qla2x00_post_work(vha, e); 4579 } 4580 4581 int 4582 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4583 { 4584 struct qla_work_evt *e; 4585 4586 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4587 if (!e) 4588 return QLA_FUNCTION_FAILED; 4589 4590 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4591 return qla2x00_post_work(vha, e); 4592 } 4593 4594 #define qla2x00_post_async_work(name, type) \ 4595 int qla2x00_post_async_##name##_work( \ 4596 struct scsi_qla_host *vha, \ 4597 fc_port_t *fcport, uint16_t *data) \ 4598 { \ 4599 struct qla_work_evt *e; \ 4600 \ 4601 e = qla2x00_alloc_work(vha, type); \ 4602 if (!e) \ 4603 return QLA_FUNCTION_FAILED; \ 4604 \ 4605 e->u.logio.fcport = fcport; \ 4606 if (data) { \ 4607 e->u.logio.data[0] = data[0]; \ 4608 e->u.logio.data[1] = data[1]; \ 4609 } \ 4610 return qla2x00_post_work(vha, e); \ 4611 } 4612 4613 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4614 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4615 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4616 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4617 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4618 4619 int 4620 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4621 { 4622 struct qla_work_evt *e; 4623 4624 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4625 if (!e) 4626 return QLA_FUNCTION_FAILED; 4627 4628 e->u.uevent.code = code; 4629 return qla2x00_post_work(vha, e); 4630 } 4631 4632 static void 4633 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4634 { 4635 char event_string[40]; 4636 char *envp[] = { event_string, NULL }; 4637 4638 switch (code) { 4639 case QLA_UEVENT_CODE_FW_DUMP: 4640 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4641 vha->host_no); 4642 break; 4643 default: 4644 /* do nothing */ 4645 break; 4646 } 4647 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4648 } 4649 4650 int 4651 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4652 uint32_t *data, int cnt) 4653 { 4654 struct qla_work_evt *e; 4655 4656 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4657 if (!e) 4658 return QLA_FUNCTION_FAILED; 4659 4660 e->u.aenfx.evtcode = evtcode; 4661 e->u.aenfx.count = cnt; 4662 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4663 return qla2x00_post_work(vha, e); 4664 } 4665 4666 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4667 { 4668 struct qla_work_evt *e; 4669 4670 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4671 if (!e) 4672 return QLA_FUNCTION_FAILED; 4673 4674 e->u.fcport.fcport = fcport; 4675 return qla2x00_post_work(vha, e); 4676 } 4677 4678 static 4679 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4680 { 4681 unsigned long flags; 4682 fc_port_t *fcport = NULL, *tfcp; 4683 struct qlt_plogi_ack_t *pla = 4684 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4685 uint8_t free_fcport = 0; 4686 4687 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4688 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4689 if (fcport) { 4690 fcport->d_id = e->u.new_sess.id; 4691 if (pla) { 4692 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4693 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4694 /* we took an extra ref_count to prevent PLOGI ACK when 4695 * fcport/sess has not been created. 4696 */ 4697 pla->ref_count--; 4698 } 4699 } else { 4700 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4701 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4702 if (fcport) { 4703 fcport->d_id = e->u.new_sess.id; 4704 fcport->scan_state = QLA_FCPORT_FOUND; 4705 fcport->flags |= FCF_FABRIC_DEVICE; 4706 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4707 4708 memcpy(fcport->port_name, e->u.new_sess.port_name, 4709 WWN_SIZE); 4710 } else { 4711 ql_dbg(ql_dbg_disc, vha, 0xffff, 4712 "%s %8phC mem alloc fail.\n", 4713 __func__, e->u.new_sess.port_name); 4714 4715 if (pla) 4716 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4717 return; 4718 } 4719 4720 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4721 /* search again to make sure one else got ahead */ 4722 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4723 e->u.new_sess.port_name, 1); 4724 if (tfcp) { 4725 /* should rarily happen */ 4726 ql_dbg(ql_dbg_disc, vha, 0xffff, 4727 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4728 __func__, tfcp->port_name, tfcp->disc_state, 4729 tfcp->fw_login_state); 4730 4731 free_fcport = 1; 4732 } else { 4733 list_add_tail(&fcport->list, &vha->vp_fcports); 4734 4735 if (pla) { 4736 qlt_plogi_ack_link(vha, pla, fcport, 4737 QLT_PLOGI_LINK_SAME_WWN); 4738 pla->ref_count--; 4739 } 4740 } 4741 } 4742 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4743 4744 if (fcport) { 4745 if (pla) 4746 qlt_plogi_ack_unref(vha, pla); 4747 else 4748 qla24xx_async_gnl(vha, fcport); 4749 } 4750 4751 if (free_fcport) { 4752 qla2x00_free_fcport(fcport); 4753 if (pla) 4754 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4755 } 4756 } 4757 4758 void 4759 qla2x00_do_work(struct scsi_qla_host *vha) 4760 { 4761 struct qla_work_evt *e, *tmp; 4762 unsigned long flags; 4763 LIST_HEAD(work); 4764 4765 spin_lock_irqsave(&vha->work_lock, flags); 4766 list_splice_init(&vha->work_list, &work); 4767 spin_unlock_irqrestore(&vha->work_lock, flags); 4768 4769 list_for_each_entry_safe(e, tmp, &work, list) { 4770 list_del_init(&e->list); 4771 4772 switch (e->type) { 4773 case QLA_EVT_AEN: 4774 fc_host_post_event(vha->host, fc_get_event_number(), 4775 e->u.aen.code, e->u.aen.data); 4776 break; 4777 case QLA_EVT_IDC_ACK: 4778 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4779 break; 4780 case QLA_EVT_ASYNC_LOGIN: 4781 qla2x00_async_login(vha, e->u.logio.fcport, 4782 e->u.logio.data); 4783 break; 4784 case QLA_EVT_ASYNC_LOGOUT: 4785 qla2x00_async_logout(vha, e->u.logio.fcport); 4786 break; 4787 case QLA_EVT_ASYNC_LOGOUT_DONE: 4788 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4789 e->u.logio.data); 4790 break; 4791 case QLA_EVT_ASYNC_ADISC: 4792 qla2x00_async_adisc(vha, e->u.logio.fcport, 4793 e->u.logio.data); 4794 break; 4795 case QLA_EVT_ASYNC_ADISC_DONE: 4796 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4797 e->u.logio.data); 4798 break; 4799 case QLA_EVT_UEVENT: 4800 qla2x00_uevent_emit(vha, e->u.uevent.code); 4801 break; 4802 case QLA_EVT_AENFX: 4803 qlafx00_process_aen(vha, e); 4804 break; 4805 case QLA_EVT_GIDPN: 4806 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 4807 break; 4808 case QLA_EVT_GPNID: 4809 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 4810 break; 4811 case QLA_EVT_GPNID_DONE: 4812 qla24xx_async_gpnid_done(vha, e->u.iosb.sp); 4813 break; 4814 case QLA_EVT_NEW_SESS: 4815 qla24xx_create_new_sess(vha, e); 4816 break; 4817 case QLA_EVT_GPDB: 4818 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 4819 e->u.fcport.opt); 4820 break; 4821 case QLA_EVT_PRLI: 4822 qla24xx_async_prli(vha, e->u.fcport.fcport); 4823 break; 4824 case QLA_EVT_GPSC: 4825 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 4826 break; 4827 case QLA_EVT_UPD_FCPORT: 4828 qla2x00_update_fcport(vha, e->u.fcport.fcport); 4829 break; 4830 case QLA_EVT_GNL: 4831 qla24xx_async_gnl(vha, e->u.fcport.fcport); 4832 break; 4833 case QLA_EVT_NACK: 4834 qla24xx_do_nack_work(vha, e); 4835 break; 4836 } 4837 if (e->flags & QLA_EVT_FLAG_FREE) 4838 kfree(e); 4839 4840 /* For each work completed decrement vha ref count */ 4841 QLA_VHA_MARK_NOT_BUSY(vha); 4842 } 4843 } 4844 4845 /* Relogins all the fcports of a vport 4846 * Context: dpc thread 4847 */ 4848 void qla2x00_relogin(struct scsi_qla_host *vha) 4849 { 4850 fc_port_t *fcport; 4851 int status; 4852 struct event_arg ea; 4853 4854 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4855 /* 4856 * If the port is not ONLINE then try to login 4857 * to it if we haven't run out of retries. 4858 */ 4859 if (atomic_read(&fcport->state) != FCS_ONLINE && 4860 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4861 fcport->login_retry--; 4862 if (fcport->flags & FCF_FABRIC_DEVICE) { 4863 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 4864 "%s %8phC DS %d LS %d\n", __func__, 4865 fcport->port_name, fcport->disc_state, 4866 fcport->fw_login_state); 4867 memset(&ea, 0, sizeof(ea)); 4868 ea.event = FCME_RELOGIN; 4869 ea.fcport = fcport; 4870 qla2x00_fcport_event_handler(vha, &ea); 4871 } else { 4872 status = qla2x00_local_device_login(vha, 4873 fcport); 4874 if (status == QLA_SUCCESS) { 4875 fcport->old_loop_id = fcport->loop_id; 4876 ql_dbg(ql_dbg_disc, vha, 0x2003, 4877 "Port login OK: logged in ID 0x%x.\n", 4878 fcport->loop_id); 4879 qla2x00_update_fcport(vha, fcport); 4880 } else if (status == 1) { 4881 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4882 /* retry the login again */ 4883 ql_dbg(ql_dbg_disc, vha, 0x2007, 4884 "Retrying %d login again loop_id 0x%x.\n", 4885 fcport->login_retry, 4886 fcport->loop_id); 4887 } else { 4888 fcport->login_retry = 0; 4889 } 4890 4891 if (fcport->login_retry == 0 && 4892 status != QLA_SUCCESS) 4893 qla2x00_clear_loop_id(fcport); 4894 } 4895 } 4896 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4897 break; 4898 } 4899 } 4900 4901 /* Schedule work on any of the dpc-workqueues */ 4902 void 4903 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4904 { 4905 struct qla_hw_data *ha = base_vha->hw; 4906 4907 switch (work_code) { 4908 case MBA_IDC_AEN: /* 0x8200 */ 4909 if (ha->dpc_lp_wq) 4910 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4911 break; 4912 4913 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4914 if (!ha->flags.nic_core_reset_hdlr_active) { 4915 if (ha->dpc_hp_wq) 4916 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4917 } else 4918 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4919 "NIC Core reset is already active. Skip " 4920 "scheduling it again.\n"); 4921 break; 4922 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4923 if (ha->dpc_hp_wq) 4924 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4925 break; 4926 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4927 if (ha->dpc_hp_wq) 4928 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4929 break; 4930 default: 4931 ql_log(ql_log_warn, base_vha, 0xb05f, 4932 "Unknown work-code=0x%x.\n", work_code); 4933 } 4934 4935 return; 4936 } 4937 4938 /* Work: Perform NIC Core Unrecoverable state handling */ 4939 void 4940 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4941 { 4942 struct qla_hw_data *ha = 4943 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4944 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4945 uint32_t dev_state = 0; 4946 4947 qla83xx_idc_lock(base_vha, 0); 4948 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4949 qla83xx_reset_ownership(base_vha); 4950 if (ha->flags.nic_core_reset_owner) { 4951 ha->flags.nic_core_reset_owner = 0; 4952 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4953 QLA8XXX_DEV_FAILED); 4954 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4955 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4956 } 4957 qla83xx_idc_unlock(base_vha, 0); 4958 } 4959 4960 /* Work: Execute IDC state handler */ 4961 void 4962 qla83xx_idc_state_handler_work(struct work_struct *work) 4963 { 4964 struct qla_hw_data *ha = 4965 container_of(work, struct qla_hw_data, idc_state_handler); 4966 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4967 uint32_t dev_state = 0; 4968 4969 qla83xx_idc_lock(base_vha, 0); 4970 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4971 if (dev_state == QLA8XXX_DEV_FAILED || 4972 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4973 qla83xx_idc_state_handler(base_vha); 4974 qla83xx_idc_unlock(base_vha, 0); 4975 } 4976 4977 static int 4978 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4979 { 4980 int rval = QLA_SUCCESS; 4981 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4982 uint32_t heart_beat_counter1, heart_beat_counter2; 4983 4984 do { 4985 if (time_after(jiffies, heart_beat_wait)) { 4986 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4987 "Nic Core f/w is not alive.\n"); 4988 rval = QLA_FUNCTION_FAILED; 4989 break; 4990 } 4991 4992 qla83xx_idc_lock(base_vha, 0); 4993 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4994 &heart_beat_counter1); 4995 qla83xx_idc_unlock(base_vha, 0); 4996 msleep(100); 4997 qla83xx_idc_lock(base_vha, 0); 4998 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4999 &heart_beat_counter2); 5000 qla83xx_idc_unlock(base_vha, 0); 5001 } while (heart_beat_counter1 == heart_beat_counter2); 5002 5003 return rval; 5004 } 5005 5006 /* Work: Perform NIC Core Reset handling */ 5007 void 5008 qla83xx_nic_core_reset_work(struct work_struct *work) 5009 { 5010 struct qla_hw_data *ha = 5011 container_of(work, struct qla_hw_data, nic_core_reset); 5012 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5013 uint32_t dev_state = 0; 5014 5015 if (IS_QLA2031(ha)) { 5016 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5017 ql_log(ql_log_warn, base_vha, 0xb081, 5018 "Failed to dump mctp\n"); 5019 return; 5020 } 5021 5022 if (!ha->flags.nic_core_reset_hdlr_active) { 5023 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5024 qla83xx_idc_lock(base_vha, 0); 5025 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5026 &dev_state); 5027 qla83xx_idc_unlock(base_vha, 0); 5028 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5029 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5030 "Nic Core f/w is alive.\n"); 5031 return; 5032 } 5033 } 5034 5035 ha->flags.nic_core_reset_hdlr_active = 1; 5036 if (qla83xx_nic_core_reset(base_vha)) { 5037 /* NIC Core reset failed. */ 5038 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5039 "NIC Core reset failed.\n"); 5040 } 5041 ha->flags.nic_core_reset_hdlr_active = 0; 5042 } 5043 } 5044 5045 /* Work: Handle 8200 IDC aens */ 5046 void 5047 qla83xx_service_idc_aen(struct work_struct *work) 5048 { 5049 struct qla_hw_data *ha = 5050 container_of(work, struct qla_hw_data, idc_aen); 5051 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5052 uint32_t dev_state, idc_control; 5053 5054 qla83xx_idc_lock(base_vha, 0); 5055 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5056 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5057 qla83xx_idc_unlock(base_vha, 0); 5058 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5059 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5060 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5061 "Application requested NIC Core Reset.\n"); 5062 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5063 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5064 QLA_SUCCESS) { 5065 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5066 "Other protocol driver requested NIC Core Reset.\n"); 5067 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5068 } 5069 } else if (dev_state == QLA8XXX_DEV_FAILED || 5070 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5071 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5072 } 5073 } 5074 5075 static void 5076 qla83xx_wait_logic(void) 5077 { 5078 int i; 5079 5080 /* Yield CPU */ 5081 if (!in_interrupt()) { 5082 /* 5083 * Wait about 200ms before retrying again. 5084 * This controls the number of retries for single 5085 * lock operation. 5086 */ 5087 msleep(100); 5088 schedule(); 5089 } else { 5090 for (i = 0; i < 20; i++) 5091 cpu_relax(); /* This a nop instr on i386 */ 5092 } 5093 } 5094 5095 static int 5096 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5097 { 5098 int rval; 5099 uint32_t data; 5100 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5101 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5102 struct qla_hw_data *ha = base_vha->hw; 5103 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5104 "Trying force recovery of the IDC lock.\n"); 5105 5106 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5107 if (rval) 5108 return rval; 5109 5110 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5111 return QLA_SUCCESS; 5112 } else { 5113 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5114 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5115 data); 5116 if (rval) 5117 return rval; 5118 5119 msleep(200); 5120 5121 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5122 &data); 5123 if (rval) 5124 return rval; 5125 5126 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5127 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5128 ~(idc_lck_rcvry_stage_mask)); 5129 rval = qla83xx_wr_reg(base_vha, 5130 QLA83XX_IDC_LOCK_RECOVERY, data); 5131 if (rval) 5132 return rval; 5133 5134 /* Forcefully perform IDC UnLock */ 5135 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5136 &data); 5137 if (rval) 5138 return rval; 5139 /* Clear lock-id by setting 0xff */ 5140 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5141 0xff); 5142 if (rval) 5143 return rval; 5144 /* Clear lock-recovery by setting 0x0 */ 5145 rval = qla83xx_wr_reg(base_vha, 5146 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5147 if (rval) 5148 return rval; 5149 } else 5150 return QLA_SUCCESS; 5151 } 5152 5153 return rval; 5154 } 5155 5156 static int 5157 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5158 { 5159 int rval = QLA_SUCCESS; 5160 uint32_t o_drv_lockid, n_drv_lockid; 5161 unsigned long lock_recovery_timeout; 5162 5163 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5164 retry_lockid: 5165 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5166 if (rval) 5167 goto exit; 5168 5169 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5170 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5171 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5172 return QLA_SUCCESS; 5173 else 5174 return QLA_FUNCTION_FAILED; 5175 } 5176 5177 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5178 if (rval) 5179 goto exit; 5180 5181 if (o_drv_lockid == n_drv_lockid) { 5182 qla83xx_wait_logic(); 5183 goto retry_lockid; 5184 } else 5185 return QLA_SUCCESS; 5186 5187 exit: 5188 return rval; 5189 } 5190 5191 void 5192 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5193 { 5194 uint16_t options = (requester_id << 15) | BIT_6; 5195 uint32_t data; 5196 uint32_t lock_owner; 5197 struct qla_hw_data *ha = base_vha->hw; 5198 5199 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5200 retry_lock: 5201 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5202 == QLA_SUCCESS) { 5203 if (data) { 5204 /* Setting lock-id to our function-number */ 5205 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5206 ha->portnum); 5207 } else { 5208 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5209 &lock_owner); 5210 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5211 "Failed to acquire IDC lock, acquired by %d, " 5212 "retrying...\n", lock_owner); 5213 5214 /* Retry/Perform IDC-Lock recovery */ 5215 if (qla83xx_idc_lock_recovery(base_vha) 5216 == QLA_SUCCESS) { 5217 qla83xx_wait_logic(); 5218 goto retry_lock; 5219 } else 5220 ql_log(ql_log_warn, base_vha, 0xb075, 5221 "IDC Lock recovery FAILED.\n"); 5222 } 5223 5224 } 5225 5226 return; 5227 5228 /* XXX: IDC-lock implementation using access-control mbx */ 5229 retry_lock2: 5230 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5231 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5232 "Failed to acquire IDC lock. retrying...\n"); 5233 /* Retry/Perform IDC-Lock recovery */ 5234 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5235 qla83xx_wait_logic(); 5236 goto retry_lock2; 5237 } else 5238 ql_log(ql_log_warn, base_vha, 0xb076, 5239 "IDC Lock recovery FAILED.\n"); 5240 } 5241 5242 return; 5243 } 5244 5245 void 5246 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5247 { 5248 #if 0 5249 uint16_t options = (requester_id << 15) | BIT_7; 5250 #endif 5251 uint16_t retry; 5252 uint32_t data; 5253 struct qla_hw_data *ha = base_vha->hw; 5254 5255 /* IDC-unlock implementation using driver-unlock/lock-id 5256 * remote registers 5257 */ 5258 retry = 0; 5259 retry_unlock: 5260 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5261 == QLA_SUCCESS) { 5262 if (data == ha->portnum) { 5263 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5264 /* Clearing lock-id by setting 0xff */ 5265 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5266 } else if (retry < 10) { 5267 /* SV: XXX: IDC unlock retrying needed here? */ 5268 5269 /* Retry for IDC-unlock */ 5270 qla83xx_wait_logic(); 5271 retry++; 5272 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5273 "Failed to release IDC lock, retrying=%d\n", retry); 5274 goto retry_unlock; 5275 } 5276 } else if (retry < 10) { 5277 /* Retry for IDC-unlock */ 5278 qla83xx_wait_logic(); 5279 retry++; 5280 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5281 "Failed to read drv-lockid, retrying=%d\n", retry); 5282 goto retry_unlock; 5283 } 5284 5285 return; 5286 5287 #if 0 5288 /* XXX: IDC-unlock implementation using access-control mbx */ 5289 retry = 0; 5290 retry_unlock2: 5291 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5292 if (retry < 10) { 5293 /* Retry for IDC-unlock */ 5294 qla83xx_wait_logic(); 5295 retry++; 5296 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5297 "Failed to release IDC lock, retrying=%d\n", retry); 5298 goto retry_unlock2; 5299 } 5300 } 5301 5302 return; 5303 #endif 5304 } 5305 5306 int 5307 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5308 { 5309 int rval = QLA_SUCCESS; 5310 struct qla_hw_data *ha = vha->hw; 5311 uint32_t drv_presence; 5312 5313 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5314 if (rval == QLA_SUCCESS) { 5315 drv_presence |= (1 << ha->portnum); 5316 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5317 drv_presence); 5318 } 5319 5320 return rval; 5321 } 5322 5323 int 5324 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5325 { 5326 int rval = QLA_SUCCESS; 5327 5328 qla83xx_idc_lock(vha, 0); 5329 rval = __qla83xx_set_drv_presence(vha); 5330 qla83xx_idc_unlock(vha, 0); 5331 5332 return rval; 5333 } 5334 5335 int 5336 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5337 { 5338 int rval = QLA_SUCCESS; 5339 struct qla_hw_data *ha = vha->hw; 5340 uint32_t drv_presence; 5341 5342 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5343 if (rval == QLA_SUCCESS) { 5344 drv_presence &= ~(1 << ha->portnum); 5345 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5346 drv_presence); 5347 } 5348 5349 return rval; 5350 } 5351 5352 int 5353 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5354 { 5355 int rval = QLA_SUCCESS; 5356 5357 qla83xx_idc_lock(vha, 0); 5358 rval = __qla83xx_clear_drv_presence(vha); 5359 qla83xx_idc_unlock(vha, 0); 5360 5361 return rval; 5362 } 5363 5364 static void 5365 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5366 { 5367 struct qla_hw_data *ha = vha->hw; 5368 uint32_t drv_ack, drv_presence; 5369 unsigned long ack_timeout; 5370 5371 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5372 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5373 while (1) { 5374 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5375 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5376 if ((drv_ack & drv_presence) == drv_presence) 5377 break; 5378 5379 if (time_after_eq(jiffies, ack_timeout)) { 5380 ql_log(ql_log_warn, vha, 0xb067, 5381 "RESET ACK TIMEOUT! drv_presence=0x%x " 5382 "drv_ack=0x%x\n", drv_presence, drv_ack); 5383 /* 5384 * The function(s) which did not ack in time are forced 5385 * to withdraw any further participation in the IDC 5386 * reset. 5387 */ 5388 if (drv_ack != drv_presence) 5389 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5390 drv_ack); 5391 break; 5392 } 5393 5394 qla83xx_idc_unlock(vha, 0); 5395 msleep(1000); 5396 qla83xx_idc_lock(vha, 0); 5397 } 5398 5399 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5400 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5401 } 5402 5403 static int 5404 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5405 { 5406 int rval = QLA_SUCCESS; 5407 uint32_t idc_control; 5408 5409 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5410 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5411 5412 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5413 __qla83xx_get_idc_control(vha, &idc_control); 5414 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5415 __qla83xx_set_idc_control(vha, 0); 5416 5417 qla83xx_idc_unlock(vha, 0); 5418 rval = qla83xx_restart_nic_firmware(vha); 5419 qla83xx_idc_lock(vha, 0); 5420 5421 if (rval != QLA_SUCCESS) { 5422 ql_log(ql_log_fatal, vha, 0xb06a, 5423 "Failed to restart NIC f/w.\n"); 5424 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5425 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5426 } else { 5427 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5428 "Success in restarting nic f/w.\n"); 5429 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5430 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5431 } 5432 5433 return rval; 5434 } 5435 5436 /* Assumes idc_lock always held on entry */ 5437 int 5438 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5439 { 5440 struct qla_hw_data *ha = base_vha->hw; 5441 int rval = QLA_SUCCESS; 5442 unsigned long dev_init_timeout; 5443 uint32_t dev_state; 5444 5445 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5446 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5447 5448 while (1) { 5449 5450 if (time_after_eq(jiffies, dev_init_timeout)) { 5451 ql_log(ql_log_warn, base_vha, 0xb06e, 5452 "Initialization TIMEOUT!\n"); 5453 /* Init timeout. Disable further NIC Core 5454 * communication. 5455 */ 5456 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5457 QLA8XXX_DEV_FAILED); 5458 ql_log(ql_log_info, base_vha, 0xb06f, 5459 "HW State: FAILED.\n"); 5460 } 5461 5462 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5463 switch (dev_state) { 5464 case QLA8XXX_DEV_READY: 5465 if (ha->flags.nic_core_reset_owner) 5466 qla83xx_idc_audit(base_vha, 5467 IDC_AUDIT_COMPLETION); 5468 ha->flags.nic_core_reset_owner = 0; 5469 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5470 "Reset_owner reset by 0x%x.\n", 5471 ha->portnum); 5472 goto exit; 5473 case QLA8XXX_DEV_COLD: 5474 if (ha->flags.nic_core_reset_owner) 5475 rval = qla83xx_device_bootstrap(base_vha); 5476 else { 5477 /* Wait for AEN to change device-state */ 5478 qla83xx_idc_unlock(base_vha, 0); 5479 msleep(1000); 5480 qla83xx_idc_lock(base_vha, 0); 5481 } 5482 break; 5483 case QLA8XXX_DEV_INITIALIZING: 5484 /* Wait for AEN to change device-state */ 5485 qla83xx_idc_unlock(base_vha, 0); 5486 msleep(1000); 5487 qla83xx_idc_lock(base_vha, 0); 5488 break; 5489 case QLA8XXX_DEV_NEED_RESET: 5490 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5491 qla83xx_need_reset_handler(base_vha); 5492 else { 5493 /* Wait for AEN to change device-state */ 5494 qla83xx_idc_unlock(base_vha, 0); 5495 msleep(1000); 5496 qla83xx_idc_lock(base_vha, 0); 5497 } 5498 /* reset timeout value after need reset handler */ 5499 dev_init_timeout = jiffies + 5500 (ha->fcoe_dev_init_timeout * HZ); 5501 break; 5502 case QLA8XXX_DEV_NEED_QUIESCENT: 5503 /* XXX: DEBUG for now */ 5504 qla83xx_idc_unlock(base_vha, 0); 5505 msleep(1000); 5506 qla83xx_idc_lock(base_vha, 0); 5507 break; 5508 case QLA8XXX_DEV_QUIESCENT: 5509 /* XXX: DEBUG for now */ 5510 if (ha->flags.quiesce_owner) 5511 goto exit; 5512 5513 qla83xx_idc_unlock(base_vha, 0); 5514 msleep(1000); 5515 qla83xx_idc_lock(base_vha, 0); 5516 dev_init_timeout = jiffies + 5517 (ha->fcoe_dev_init_timeout * HZ); 5518 break; 5519 case QLA8XXX_DEV_FAILED: 5520 if (ha->flags.nic_core_reset_owner) 5521 qla83xx_idc_audit(base_vha, 5522 IDC_AUDIT_COMPLETION); 5523 ha->flags.nic_core_reset_owner = 0; 5524 __qla83xx_clear_drv_presence(base_vha); 5525 qla83xx_idc_unlock(base_vha, 0); 5526 qla8xxx_dev_failed_handler(base_vha); 5527 rval = QLA_FUNCTION_FAILED; 5528 qla83xx_idc_lock(base_vha, 0); 5529 goto exit; 5530 case QLA8XXX_BAD_VALUE: 5531 qla83xx_idc_unlock(base_vha, 0); 5532 msleep(1000); 5533 qla83xx_idc_lock(base_vha, 0); 5534 break; 5535 default: 5536 ql_log(ql_log_warn, base_vha, 0xb071, 5537 "Unknown Device State: %x.\n", dev_state); 5538 qla83xx_idc_unlock(base_vha, 0); 5539 qla8xxx_dev_failed_handler(base_vha); 5540 rval = QLA_FUNCTION_FAILED; 5541 qla83xx_idc_lock(base_vha, 0); 5542 goto exit; 5543 } 5544 } 5545 5546 exit: 5547 return rval; 5548 } 5549 5550 void 5551 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5552 { 5553 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5554 board_disable); 5555 struct pci_dev *pdev = ha->pdev; 5556 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5557 5558 /* 5559 * if UNLOAD flag is already set, then continue unload, 5560 * where it was set first. 5561 */ 5562 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5563 return; 5564 5565 ql_log(ql_log_warn, base_vha, 0x015b, 5566 "Disabling adapter.\n"); 5567 5568 if (!atomic_read(&pdev->enable_cnt)) { 5569 ql_log(ql_log_info, base_vha, 0xfffc, 5570 "PCI device disabled, no action req for PCI error=%lx\n", 5571 base_vha->pci_flags); 5572 return; 5573 } 5574 5575 qla2x00_wait_for_sess_deletion(base_vha); 5576 5577 set_bit(UNLOADING, &base_vha->dpc_flags); 5578 5579 qla2x00_delete_all_vps(ha, base_vha); 5580 5581 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5582 5583 qla2x00_dfs_remove(base_vha); 5584 5585 qla84xx_put_chip(base_vha); 5586 5587 if (base_vha->timer_active) 5588 qla2x00_stop_timer(base_vha); 5589 5590 base_vha->flags.online = 0; 5591 5592 qla2x00_destroy_deferred_work(ha); 5593 5594 /* 5595 * Do not try to stop beacon blink as it will issue a mailbox 5596 * command. 5597 */ 5598 qla2x00_free_sysfs_attr(base_vha, false); 5599 5600 fc_remove_host(base_vha->host); 5601 5602 scsi_remove_host(base_vha->host); 5603 5604 base_vha->flags.init_done = 0; 5605 qla25xx_delete_queues(base_vha); 5606 qla2x00_free_fcports(base_vha); 5607 qla2x00_free_irqs(base_vha); 5608 qla2x00_mem_free(ha); 5609 qla82xx_md_free(base_vha); 5610 qla2x00_free_queues(ha); 5611 5612 qla2x00_unmap_iobases(ha); 5613 5614 pci_release_selected_regions(ha->pdev, ha->bars); 5615 pci_disable_pcie_error_reporting(pdev); 5616 pci_disable_device(pdev); 5617 5618 /* 5619 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5620 */ 5621 } 5622 5623 /************************************************************************** 5624 * qla2x00_do_dpc 5625 * This kernel thread is a task that is schedule by the interrupt handler 5626 * to perform the background processing for interrupts. 5627 * 5628 * Notes: 5629 * This task always run in the context of a kernel thread. It 5630 * is kick-off by the driver's detect code and starts up 5631 * up one per adapter. It immediately goes to sleep and waits for 5632 * some fibre event. When either the interrupt handler or 5633 * the timer routine detects a event it will one of the task 5634 * bits then wake us up. 5635 **************************************************************************/ 5636 static int 5637 qla2x00_do_dpc(void *data) 5638 { 5639 scsi_qla_host_t *base_vha; 5640 struct qla_hw_data *ha; 5641 uint32_t online; 5642 struct qla_qpair *qpair; 5643 5644 ha = (struct qla_hw_data *)data; 5645 base_vha = pci_get_drvdata(ha->pdev); 5646 5647 set_user_nice(current, MIN_NICE); 5648 5649 set_current_state(TASK_INTERRUPTIBLE); 5650 while (!kthread_should_stop()) { 5651 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5652 "DPC handler sleeping.\n"); 5653 5654 schedule(); 5655 5656 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5657 goto end_loop; 5658 5659 if (ha->flags.eeh_busy) { 5660 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5661 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5662 goto end_loop; 5663 } 5664 5665 ha->dpc_active = 1; 5666 5667 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5668 "DPC handler waking up, dpc_flags=0x%lx.\n", 5669 base_vha->dpc_flags); 5670 5671 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5672 break; 5673 5674 qla2x00_do_work(base_vha); 5675 5676 if (IS_P3P_TYPE(ha)) { 5677 if (IS_QLA8044(ha)) { 5678 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5679 &base_vha->dpc_flags)) { 5680 qla8044_idc_lock(ha); 5681 qla8044_wr_direct(base_vha, 5682 QLA8044_CRB_DEV_STATE_INDEX, 5683 QLA8XXX_DEV_FAILED); 5684 qla8044_idc_unlock(ha); 5685 ql_log(ql_log_info, base_vha, 0x4004, 5686 "HW State: FAILED.\n"); 5687 qla8044_device_state_handler(base_vha); 5688 continue; 5689 } 5690 5691 } else { 5692 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5693 &base_vha->dpc_flags)) { 5694 qla82xx_idc_lock(ha); 5695 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5696 QLA8XXX_DEV_FAILED); 5697 qla82xx_idc_unlock(ha); 5698 ql_log(ql_log_info, base_vha, 0x0151, 5699 "HW State: FAILED.\n"); 5700 qla82xx_device_state_handler(base_vha); 5701 continue; 5702 } 5703 } 5704 5705 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5706 &base_vha->dpc_flags)) { 5707 5708 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5709 "FCoE context reset scheduled.\n"); 5710 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5711 &base_vha->dpc_flags))) { 5712 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5713 /* FCoE-ctx reset failed. 5714 * Escalate to chip-reset 5715 */ 5716 set_bit(ISP_ABORT_NEEDED, 5717 &base_vha->dpc_flags); 5718 } 5719 clear_bit(ABORT_ISP_ACTIVE, 5720 &base_vha->dpc_flags); 5721 } 5722 5723 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5724 "FCoE context reset end.\n"); 5725 } 5726 } else if (IS_QLAFX00(ha)) { 5727 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5728 &base_vha->dpc_flags)) { 5729 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5730 "Firmware Reset Recovery\n"); 5731 if (qlafx00_reset_initialize(base_vha)) { 5732 /* Failed. Abort isp later. */ 5733 if (!test_bit(UNLOADING, 5734 &base_vha->dpc_flags)) { 5735 set_bit(ISP_UNRECOVERABLE, 5736 &base_vha->dpc_flags); 5737 ql_dbg(ql_dbg_dpc, base_vha, 5738 0x4021, 5739 "Reset Recovery Failed\n"); 5740 } 5741 } 5742 } 5743 5744 if (test_and_clear_bit(FX00_TARGET_SCAN, 5745 &base_vha->dpc_flags)) { 5746 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5747 "ISPFx00 Target Scan scheduled\n"); 5748 if (qlafx00_rescan_isp(base_vha)) { 5749 if (!test_bit(UNLOADING, 5750 &base_vha->dpc_flags)) 5751 set_bit(ISP_UNRECOVERABLE, 5752 &base_vha->dpc_flags); 5753 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5754 "ISPFx00 Target Scan Failed\n"); 5755 } 5756 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5757 "ISPFx00 Target Scan End\n"); 5758 } 5759 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5760 &base_vha->dpc_flags)) { 5761 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5762 "ISPFx00 Host Info resend scheduled\n"); 5763 qlafx00_fx_disc(base_vha, 5764 &base_vha->hw->mr.fcport, 5765 FXDISC_REG_HOST_INFO); 5766 } 5767 } 5768 5769 if (test_and_clear_bit(DETECT_SFP_CHANGE, 5770 &base_vha->dpc_flags) && 5771 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 5772 qla24xx_detect_sfp(base_vha); 5773 5774 if (ha->flags.detected_lr_sfp != 5775 ha->flags.using_lr_setting) 5776 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 5777 } 5778 5779 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5780 &base_vha->dpc_flags)) { 5781 5782 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5783 "ISP abort scheduled.\n"); 5784 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5785 &base_vha->dpc_flags))) { 5786 5787 if (ha->isp_ops->abort_isp(base_vha)) { 5788 /* failed. retry later */ 5789 set_bit(ISP_ABORT_NEEDED, 5790 &base_vha->dpc_flags); 5791 } 5792 clear_bit(ABORT_ISP_ACTIVE, 5793 &base_vha->dpc_flags); 5794 } 5795 5796 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5797 "ISP abort end.\n"); 5798 } 5799 5800 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5801 &base_vha->dpc_flags)) { 5802 qla2x00_update_fcports(base_vha); 5803 } 5804 5805 if (IS_QLAFX00(ha)) 5806 goto loop_resync_check; 5807 5808 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5809 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5810 "Quiescence mode scheduled.\n"); 5811 if (IS_P3P_TYPE(ha)) { 5812 if (IS_QLA82XX(ha)) 5813 qla82xx_device_state_handler(base_vha); 5814 if (IS_QLA8044(ha)) 5815 qla8044_device_state_handler(base_vha); 5816 clear_bit(ISP_QUIESCE_NEEDED, 5817 &base_vha->dpc_flags); 5818 if (!ha->flags.quiesce_owner) { 5819 qla2x00_perform_loop_resync(base_vha); 5820 if (IS_QLA82XX(ha)) { 5821 qla82xx_idc_lock(ha); 5822 qla82xx_clear_qsnt_ready( 5823 base_vha); 5824 qla82xx_idc_unlock(ha); 5825 } else if (IS_QLA8044(ha)) { 5826 qla8044_idc_lock(ha); 5827 qla8044_clear_qsnt_ready( 5828 base_vha); 5829 qla8044_idc_unlock(ha); 5830 } 5831 } 5832 } else { 5833 clear_bit(ISP_QUIESCE_NEEDED, 5834 &base_vha->dpc_flags); 5835 qla2x00_quiesce_io(base_vha); 5836 } 5837 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5838 "Quiescence mode end.\n"); 5839 } 5840 5841 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5842 &base_vha->dpc_flags) && 5843 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5844 5845 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5846 "Reset marker scheduled.\n"); 5847 qla2x00_rst_aen(base_vha); 5848 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5849 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5850 "Reset marker end.\n"); 5851 } 5852 5853 /* Retry each device up to login retry count */ 5854 if ((test_and_clear_bit(RELOGIN_NEEDED, 5855 &base_vha->dpc_flags)) && 5856 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5857 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5858 5859 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5860 "Relogin scheduled.\n"); 5861 qla2x00_relogin(base_vha); 5862 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5863 "Relogin end.\n"); 5864 } 5865 loop_resync_check: 5866 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5867 &base_vha->dpc_flags)) { 5868 5869 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5870 "Loop resync scheduled.\n"); 5871 5872 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5873 &base_vha->dpc_flags))) { 5874 5875 qla2x00_loop_resync(base_vha); 5876 5877 clear_bit(LOOP_RESYNC_ACTIVE, 5878 &base_vha->dpc_flags); 5879 } 5880 5881 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5882 "Loop resync end.\n"); 5883 } 5884 5885 if (IS_QLAFX00(ha)) 5886 goto intr_on_check; 5887 5888 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5889 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5890 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5891 qla2xxx_flash_npiv_conf(base_vha); 5892 } 5893 5894 intr_on_check: 5895 if (!ha->interrupts_on) 5896 ha->isp_ops->enable_intrs(ha); 5897 5898 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5899 &base_vha->dpc_flags)) { 5900 if (ha->beacon_blink_led == 1) 5901 ha->isp_ops->beacon_blink(base_vha); 5902 } 5903 5904 /* qpair online check */ 5905 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 5906 &base_vha->dpc_flags)) { 5907 if (ha->flags.eeh_busy || 5908 ha->flags.pci_channel_io_perm_failure) 5909 online = 0; 5910 else 5911 online = 1; 5912 5913 mutex_lock(&ha->mq_lock); 5914 list_for_each_entry(qpair, &base_vha->qp_list, 5915 qp_list_elem) 5916 qpair->online = online; 5917 mutex_unlock(&ha->mq_lock); 5918 } 5919 5920 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 5921 ql_log(ql_log_info, base_vha, 0xffffff, 5922 "nvme: SET ZIO Activity exchange threshold to %d.\n", 5923 ha->nvme_last_rptd_aen); 5924 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 5925 ql_log(ql_log_info, base_vha, 0xffffff, 5926 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 5927 ha->nvme_last_rptd_aen); 5928 } 5929 } 5930 5931 if (!IS_QLAFX00(ha)) 5932 qla2x00_do_dpc_all_vps(base_vha); 5933 5934 ha->dpc_active = 0; 5935 end_loop: 5936 set_current_state(TASK_INTERRUPTIBLE); 5937 } /* End of while(1) */ 5938 __set_current_state(TASK_RUNNING); 5939 5940 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5941 "DPC handler exiting.\n"); 5942 5943 /* 5944 * Make sure that nobody tries to wake us up again. 5945 */ 5946 ha->dpc_active = 0; 5947 5948 /* Cleanup any residual CTX SRBs. */ 5949 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5950 5951 return 0; 5952 } 5953 5954 void 5955 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5956 { 5957 struct qla_hw_data *ha = vha->hw; 5958 struct task_struct *t = ha->dpc_thread; 5959 5960 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5961 wake_up_process(t); 5962 } 5963 5964 /* 5965 * qla2x00_rst_aen 5966 * Processes asynchronous reset. 5967 * 5968 * Input: 5969 * ha = adapter block pointer. 5970 */ 5971 static void 5972 qla2x00_rst_aen(scsi_qla_host_t *vha) 5973 { 5974 if (vha->flags.online && !vha->flags.reset_active && 5975 !atomic_read(&vha->loop_down_timer) && 5976 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5977 do { 5978 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5979 5980 /* 5981 * Issue marker command only when we are going to start 5982 * the I/O. 5983 */ 5984 vha->marker_needed = 1; 5985 } while (!atomic_read(&vha->loop_down_timer) && 5986 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5987 } 5988 } 5989 5990 /************************************************************************** 5991 * qla2x00_timer 5992 * 5993 * Description: 5994 * One second timer 5995 * 5996 * Context: Interrupt 5997 ***************************************************************************/ 5998 void 5999 qla2x00_timer(scsi_qla_host_t *vha) 6000 { 6001 unsigned long cpu_flags = 0; 6002 int start_dpc = 0; 6003 int index; 6004 srb_t *sp; 6005 uint16_t w; 6006 struct qla_hw_data *ha = vha->hw; 6007 struct req_que *req; 6008 6009 if (ha->flags.eeh_busy) { 6010 ql_dbg(ql_dbg_timer, vha, 0x6000, 6011 "EEH = %d, restarting timer.\n", 6012 ha->flags.eeh_busy); 6013 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6014 return; 6015 } 6016 6017 /* 6018 * Hardware read to raise pending EEH errors during mailbox waits. If 6019 * the read returns -1 then disable the board. 6020 */ 6021 if (!pci_channel_offline(ha->pdev)) { 6022 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6023 qla2x00_check_reg16_for_disconnect(vha, w); 6024 } 6025 6026 /* Make sure qla82xx_watchdog is run only for physical port */ 6027 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6028 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6029 start_dpc++; 6030 if (IS_QLA82XX(ha)) 6031 qla82xx_watchdog(vha); 6032 else if (IS_QLA8044(ha)) 6033 qla8044_watchdog(vha); 6034 } 6035 6036 if (!vha->vp_idx && IS_QLAFX00(ha)) 6037 qlafx00_timer_routine(vha); 6038 6039 /* Loop down handler. */ 6040 if (atomic_read(&vha->loop_down_timer) > 0 && 6041 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6042 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6043 && vha->flags.online) { 6044 6045 if (atomic_read(&vha->loop_down_timer) == 6046 vha->loop_down_abort_time) { 6047 6048 ql_log(ql_log_info, vha, 0x6008, 6049 "Loop down - aborting the queues before time expires.\n"); 6050 6051 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6052 atomic_set(&vha->loop_state, LOOP_DEAD); 6053 6054 /* 6055 * Schedule an ISP abort to return any FCP2-device 6056 * commands. 6057 */ 6058 /* NPIV - scan physical port only */ 6059 if (!vha->vp_idx) { 6060 spin_lock_irqsave(&ha->hardware_lock, 6061 cpu_flags); 6062 req = ha->req_q_map[0]; 6063 for (index = 1; 6064 index < req->num_outstanding_cmds; 6065 index++) { 6066 fc_port_t *sfcp; 6067 6068 sp = req->outstanding_cmds[index]; 6069 if (!sp) 6070 continue; 6071 if (sp->cmd_type != TYPE_SRB) 6072 continue; 6073 if (sp->type != SRB_SCSI_CMD) 6074 continue; 6075 sfcp = sp->fcport; 6076 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6077 continue; 6078 6079 if (IS_QLA82XX(ha)) 6080 set_bit(FCOE_CTX_RESET_NEEDED, 6081 &vha->dpc_flags); 6082 else 6083 set_bit(ISP_ABORT_NEEDED, 6084 &vha->dpc_flags); 6085 break; 6086 } 6087 spin_unlock_irqrestore(&ha->hardware_lock, 6088 cpu_flags); 6089 } 6090 start_dpc++; 6091 } 6092 6093 /* if the loop has been down for 4 minutes, reinit adapter */ 6094 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6095 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6096 ql_log(ql_log_warn, vha, 0x6009, 6097 "Loop down - aborting ISP.\n"); 6098 6099 if (IS_QLA82XX(ha)) 6100 set_bit(FCOE_CTX_RESET_NEEDED, 6101 &vha->dpc_flags); 6102 else 6103 set_bit(ISP_ABORT_NEEDED, 6104 &vha->dpc_flags); 6105 } 6106 } 6107 ql_dbg(ql_dbg_timer, vha, 0x600a, 6108 "Loop down - seconds remaining %d.\n", 6109 atomic_read(&vha->loop_down_timer)); 6110 } 6111 /* Check if beacon LED needs to be blinked for physical host only */ 6112 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6113 /* There is no beacon_blink function for ISP82xx */ 6114 if (!IS_P3P_TYPE(ha)) { 6115 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6116 start_dpc++; 6117 } 6118 } 6119 6120 /* Process any deferred work. */ 6121 if (!list_empty(&vha->work_list)) 6122 start_dpc++; 6123 6124 /* 6125 * FC-NVME 6126 * see if the active AEN count has changed from what was last reported. 6127 */ 6128 if (!vha->vp_idx && 6129 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6130 ha->zio_mode == QLA_ZIO_MODE_6) { 6131 ql_log(ql_log_info, vha, 0x3002, 6132 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6133 ha->nvme_last_rptd_aen); 6134 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6135 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6136 start_dpc++; 6137 } 6138 6139 /* Schedule the DPC routine if needed */ 6140 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6141 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6142 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6143 start_dpc || 6144 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6145 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6146 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6147 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6148 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6149 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6150 ql_dbg(ql_dbg_timer, vha, 0x600b, 6151 "isp_abort_needed=%d loop_resync_needed=%d " 6152 "fcport_update_needed=%d start_dpc=%d " 6153 "reset_marker_needed=%d", 6154 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6155 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6156 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6157 start_dpc, 6158 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6159 ql_dbg(ql_dbg_timer, vha, 0x600c, 6160 "beacon_blink_needed=%d isp_unrecoverable=%d " 6161 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6162 "relogin_needed=%d.\n", 6163 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6164 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6165 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6166 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6167 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6168 qla2xxx_wake_dpc(vha); 6169 } 6170 6171 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6172 } 6173 6174 /* Firmware interface routines. */ 6175 6176 #define FW_BLOBS 11 6177 #define FW_ISP21XX 0 6178 #define FW_ISP22XX 1 6179 #define FW_ISP2300 2 6180 #define FW_ISP2322 3 6181 #define FW_ISP24XX 4 6182 #define FW_ISP25XX 5 6183 #define FW_ISP81XX 6 6184 #define FW_ISP82XX 7 6185 #define FW_ISP2031 8 6186 #define FW_ISP8031 9 6187 #define FW_ISP27XX 10 6188 6189 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6190 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6191 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6192 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6193 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6194 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6195 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6196 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6197 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6198 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6199 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6200 6201 6202 static DEFINE_MUTEX(qla_fw_lock); 6203 6204 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6205 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6206 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6207 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6208 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6209 { .name = FW_FILE_ISP24XX, }, 6210 { .name = FW_FILE_ISP25XX, }, 6211 { .name = FW_FILE_ISP81XX, }, 6212 { .name = FW_FILE_ISP82XX, }, 6213 { .name = FW_FILE_ISP2031, }, 6214 { .name = FW_FILE_ISP8031, }, 6215 { .name = FW_FILE_ISP27XX, }, 6216 }; 6217 6218 struct fw_blob * 6219 qla2x00_request_firmware(scsi_qla_host_t *vha) 6220 { 6221 struct qla_hw_data *ha = vha->hw; 6222 struct fw_blob *blob; 6223 6224 if (IS_QLA2100(ha)) { 6225 blob = &qla_fw_blobs[FW_ISP21XX]; 6226 } else if (IS_QLA2200(ha)) { 6227 blob = &qla_fw_blobs[FW_ISP22XX]; 6228 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6229 blob = &qla_fw_blobs[FW_ISP2300]; 6230 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6231 blob = &qla_fw_blobs[FW_ISP2322]; 6232 } else if (IS_QLA24XX_TYPE(ha)) { 6233 blob = &qla_fw_blobs[FW_ISP24XX]; 6234 } else if (IS_QLA25XX(ha)) { 6235 blob = &qla_fw_blobs[FW_ISP25XX]; 6236 } else if (IS_QLA81XX(ha)) { 6237 blob = &qla_fw_blobs[FW_ISP81XX]; 6238 } else if (IS_QLA82XX(ha)) { 6239 blob = &qla_fw_blobs[FW_ISP82XX]; 6240 } else if (IS_QLA2031(ha)) { 6241 blob = &qla_fw_blobs[FW_ISP2031]; 6242 } else if (IS_QLA8031(ha)) { 6243 blob = &qla_fw_blobs[FW_ISP8031]; 6244 } else if (IS_QLA27XX(ha)) { 6245 blob = &qla_fw_blobs[FW_ISP27XX]; 6246 } else { 6247 return NULL; 6248 } 6249 6250 mutex_lock(&qla_fw_lock); 6251 if (blob->fw) 6252 goto out; 6253 6254 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6255 ql_log(ql_log_warn, vha, 0x0063, 6256 "Failed to load firmware image (%s).\n", blob->name); 6257 blob->fw = NULL; 6258 blob = NULL; 6259 goto out; 6260 } 6261 6262 out: 6263 mutex_unlock(&qla_fw_lock); 6264 return blob; 6265 } 6266 6267 static void 6268 qla2x00_release_firmware(void) 6269 { 6270 int idx; 6271 6272 mutex_lock(&qla_fw_lock); 6273 for (idx = 0; idx < FW_BLOBS; idx++) 6274 release_firmware(qla_fw_blobs[idx].fw); 6275 mutex_unlock(&qla_fw_lock); 6276 } 6277 6278 static pci_ers_result_t 6279 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6280 { 6281 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6282 struct qla_hw_data *ha = vha->hw; 6283 6284 ql_dbg(ql_dbg_aer, vha, 0x9000, 6285 "PCI error detected, state %x.\n", state); 6286 6287 if (!atomic_read(&pdev->enable_cnt)) { 6288 ql_log(ql_log_info, vha, 0xffff, 6289 "PCI device is disabled,state %x\n", state); 6290 return PCI_ERS_RESULT_NEED_RESET; 6291 } 6292 6293 switch (state) { 6294 case pci_channel_io_normal: 6295 ha->flags.eeh_busy = 0; 6296 if (ql2xmqsupport) { 6297 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6298 qla2xxx_wake_dpc(vha); 6299 } 6300 return PCI_ERS_RESULT_CAN_RECOVER; 6301 case pci_channel_io_frozen: 6302 ha->flags.eeh_busy = 1; 6303 /* For ISP82XX complete any pending mailbox cmd */ 6304 if (IS_QLA82XX(ha)) { 6305 ha->flags.isp82xx_fw_hung = 1; 6306 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6307 qla82xx_clear_pending_mbx(vha); 6308 } 6309 qla2x00_free_irqs(vha); 6310 pci_disable_device(pdev); 6311 /* Return back all IOs */ 6312 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6313 if (ql2xmqsupport) { 6314 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6315 qla2xxx_wake_dpc(vha); 6316 } 6317 return PCI_ERS_RESULT_NEED_RESET; 6318 case pci_channel_io_perm_failure: 6319 ha->flags.pci_channel_io_perm_failure = 1; 6320 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6321 if (ql2xmqsupport) { 6322 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6323 qla2xxx_wake_dpc(vha); 6324 } 6325 return PCI_ERS_RESULT_DISCONNECT; 6326 } 6327 return PCI_ERS_RESULT_NEED_RESET; 6328 } 6329 6330 static pci_ers_result_t 6331 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6332 { 6333 int risc_paused = 0; 6334 uint32_t stat; 6335 unsigned long flags; 6336 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6337 struct qla_hw_data *ha = base_vha->hw; 6338 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6339 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6340 6341 if (IS_QLA82XX(ha)) 6342 return PCI_ERS_RESULT_RECOVERED; 6343 6344 spin_lock_irqsave(&ha->hardware_lock, flags); 6345 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6346 stat = RD_REG_DWORD(®->hccr); 6347 if (stat & HCCR_RISC_PAUSE) 6348 risc_paused = 1; 6349 } else if (IS_QLA23XX(ha)) { 6350 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6351 if (stat & HSR_RISC_PAUSED) 6352 risc_paused = 1; 6353 } else if (IS_FWI2_CAPABLE(ha)) { 6354 stat = RD_REG_DWORD(®24->host_status); 6355 if (stat & HSRX_RISC_PAUSED) 6356 risc_paused = 1; 6357 } 6358 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6359 6360 if (risc_paused) { 6361 ql_log(ql_log_info, base_vha, 0x9003, 6362 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6363 ha->isp_ops->fw_dump(base_vha, 0); 6364 6365 return PCI_ERS_RESULT_NEED_RESET; 6366 } else 6367 return PCI_ERS_RESULT_RECOVERED; 6368 } 6369 6370 static uint32_t 6371 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6372 { 6373 uint32_t rval = QLA_FUNCTION_FAILED; 6374 uint32_t drv_active = 0; 6375 struct qla_hw_data *ha = base_vha->hw; 6376 int fn; 6377 struct pci_dev *other_pdev = NULL; 6378 6379 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6380 "Entered %s.\n", __func__); 6381 6382 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6383 6384 if (base_vha->flags.online) { 6385 /* Abort all outstanding commands, 6386 * so as to be requeued later */ 6387 qla2x00_abort_isp_cleanup(base_vha); 6388 } 6389 6390 6391 fn = PCI_FUNC(ha->pdev->devfn); 6392 while (fn > 0) { 6393 fn--; 6394 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6395 "Finding pci device at function = 0x%x.\n", fn); 6396 other_pdev = 6397 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6398 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6399 fn)); 6400 6401 if (!other_pdev) 6402 continue; 6403 if (atomic_read(&other_pdev->enable_cnt)) { 6404 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6405 "Found PCI func available and enable at 0x%x.\n", 6406 fn); 6407 pci_dev_put(other_pdev); 6408 break; 6409 } 6410 pci_dev_put(other_pdev); 6411 } 6412 6413 if (!fn) { 6414 /* Reset owner */ 6415 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6416 "This devfn is reset owner = 0x%x.\n", 6417 ha->pdev->devfn); 6418 qla82xx_idc_lock(ha); 6419 6420 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6421 QLA8XXX_DEV_INITIALIZING); 6422 6423 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6424 QLA82XX_IDC_VERSION); 6425 6426 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6427 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6428 "drv_active = 0x%x.\n", drv_active); 6429 6430 qla82xx_idc_unlock(ha); 6431 /* Reset if device is not already reset 6432 * drv_active would be 0 if a reset has already been done 6433 */ 6434 if (drv_active) 6435 rval = qla82xx_start_firmware(base_vha); 6436 else 6437 rval = QLA_SUCCESS; 6438 qla82xx_idc_lock(ha); 6439 6440 if (rval != QLA_SUCCESS) { 6441 ql_log(ql_log_info, base_vha, 0x900b, 6442 "HW State: FAILED.\n"); 6443 qla82xx_clear_drv_active(ha); 6444 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6445 QLA8XXX_DEV_FAILED); 6446 } else { 6447 ql_log(ql_log_info, base_vha, 0x900c, 6448 "HW State: READY.\n"); 6449 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6450 QLA8XXX_DEV_READY); 6451 qla82xx_idc_unlock(ha); 6452 ha->flags.isp82xx_fw_hung = 0; 6453 rval = qla82xx_restart_isp(base_vha); 6454 qla82xx_idc_lock(ha); 6455 /* Clear driver state register */ 6456 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6457 qla82xx_set_drv_active(base_vha); 6458 } 6459 qla82xx_idc_unlock(ha); 6460 } else { 6461 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6462 "This devfn is not reset owner = 0x%x.\n", 6463 ha->pdev->devfn); 6464 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6465 QLA8XXX_DEV_READY)) { 6466 ha->flags.isp82xx_fw_hung = 0; 6467 rval = qla82xx_restart_isp(base_vha); 6468 qla82xx_idc_lock(ha); 6469 qla82xx_set_drv_active(base_vha); 6470 qla82xx_idc_unlock(ha); 6471 } 6472 } 6473 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6474 6475 return rval; 6476 } 6477 6478 static pci_ers_result_t 6479 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6480 { 6481 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6482 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6483 struct qla_hw_data *ha = base_vha->hw; 6484 struct rsp_que *rsp; 6485 int rc, retries = 10; 6486 6487 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6488 "Slot Reset.\n"); 6489 6490 /* Workaround: qla2xxx driver which access hardware earlier 6491 * needs error state to be pci_channel_io_online. 6492 * Otherwise mailbox command timesout. 6493 */ 6494 pdev->error_state = pci_channel_io_normal; 6495 6496 pci_restore_state(pdev); 6497 6498 /* pci_restore_state() clears the saved_state flag of the device 6499 * save restored state which resets saved_state flag 6500 */ 6501 pci_save_state(pdev); 6502 6503 if (ha->mem_only) 6504 rc = pci_enable_device_mem(pdev); 6505 else 6506 rc = pci_enable_device(pdev); 6507 6508 if (rc) { 6509 ql_log(ql_log_warn, base_vha, 0x9005, 6510 "Can't re-enable PCI device after reset.\n"); 6511 goto exit_slot_reset; 6512 } 6513 6514 rsp = ha->rsp_q_map[0]; 6515 if (qla2x00_request_irqs(ha, rsp)) 6516 goto exit_slot_reset; 6517 6518 if (ha->isp_ops->pci_config(base_vha)) 6519 goto exit_slot_reset; 6520 6521 if (IS_QLA82XX(ha)) { 6522 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6523 ret = PCI_ERS_RESULT_RECOVERED; 6524 goto exit_slot_reset; 6525 } else 6526 goto exit_slot_reset; 6527 } 6528 6529 while (ha->flags.mbox_busy && retries--) 6530 msleep(1000); 6531 6532 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6533 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6534 ret = PCI_ERS_RESULT_RECOVERED; 6535 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6536 6537 6538 exit_slot_reset: 6539 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6540 "slot_reset return %x.\n", ret); 6541 6542 return ret; 6543 } 6544 6545 static void 6546 qla2xxx_pci_resume(struct pci_dev *pdev) 6547 { 6548 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6549 struct qla_hw_data *ha = base_vha->hw; 6550 int ret; 6551 6552 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6553 "pci_resume.\n"); 6554 6555 ret = qla2x00_wait_for_hba_online(base_vha); 6556 if (ret != QLA_SUCCESS) { 6557 ql_log(ql_log_fatal, base_vha, 0x9002, 6558 "The device failed to resume I/O from slot/link_reset.\n"); 6559 } 6560 6561 pci_cleanup_aer_uncorrect_error_status(pdev); 6562 6563 ha->flags.eeh_busy = 0; 6564 } 6565 6566 static void 6567 qla83xx_disable_laser(scsi_qla_host_t *vha) 6568 { 6569 uint32_t reg, data, fn; 6570 struct qla_hw_data *ha = vha->hw; 6571 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 6572 6573 /* pci func #/port # */ 6574 ql_dbg(ql_dbg_init, vha, 0x004b, 6575 "Disabling Laser for hba: %p\n", vha); 6576 6577 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 6578 (BIT_15|BIT_14|BIT_13|BIT_12)); 6579 6580 fn = (fn >> 12); 6581 6582 if (fn & 1) 6583 reg = PORT_1_2031; 6584 else 6585 reg = PORT_0_2031; 6586 6587 data = LASER_OFF_2031; 6588 6589 qla83xx_wr_reg(vha, reg, data); 6590 } 6591 6592 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6593 { 6594 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6595 6596 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6597 } 6598 6599 static const struct pci_error_handlers qla2xxx_err_handler = { 6600 .error_detected = qla2xxx_pci_error_detected, 6601 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6602 .slot_reset = qla2xxx_pci_slot_reset, 6603 .resume = qla2xxx_pci_resume, 6604 }; 6605 6606 static struct pci_device_id qla2xxx_pci_tbl[] = { 6607 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6608 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6609 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6610 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6611 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6612 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6613 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6614 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6615 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6616 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6617 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6618 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6629 { 0 }, 6630 }; 6631 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6632 6633 static struct pci_driver qla2xxx_pci_driver = { 6634 .name = QLA2XXX_DRIVER_NAME, 6635 .driver = { 6636 .owner = THIS_MODULE, 6637 }, 6638 .id_table = qla2xxx_pci_tbl, 6639 .probe = qla2x00_probe_one, 6640 .remove = qla2x00_remove_one, 6641 .shutdown = qla2x00_shutdown, 6642 .err_handler = &qla2xxx_err_handler, 6643 }; 6644 6645 static const struct file_operations apidev_fops = { 6646 .owner = THIS_MODULE, 6647 .llseek = noop_llseek, 6648 }; 6649 6650 /** 6651 * qla2x00_module_init - Module initialization. 6652 **/ 6653 static int __init 6654 qla2x00_module_init(void) 6655 { 6656 int ret = 0; 6657 6658 /* Allocate cache for SRBs. */ 6659 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6660 SLAB_HWCACHE_ALIGN, NULL); 6661 if (srb_cachep == NULL) { 6662 ql_log(ql_log_fatal, NULL, 0x0001, 6663 "Unable to allocate SRB cache...Failing load!.\n"); 6664 return -ENOMEM; 6665 } 6666 6667 /* Initialize target kmem_cache and mem_pools */ 6668 ret = qlt_init(); 6669 if (ret < 0) { 6670 kmem_cache_destroy(srb_cachep); 6671 return ret; 6672 } else if (ret > 0) { 6673 /* 6674 * If initiator mode is explictly disabled by qlt_init(), 6675 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6676 * performing scsi_scan_target() during LOOP UP event. 6677 */ 6678 qla2xxx_transport_functions.disable_target_scan = 1; 6679 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6680 } 6681 6682 /* Derive version string. */ 6683 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6684 if (ql2xextended_error_logging) 6685 strcat(qla2x00_version_str, "-debug"); 6686 if (ql2xextended_error_logging == 1) 6687 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6688 6689 qla2xxx_transport_template = 6690 fc_attach_transport(&qla2xxx_transport_functions); 6691 if (!qla2xxx_transport_template) { 6692 kmem_cache_destroy(srb_cachep); 6693 ql_log(ql_log_fatal, NULL, 0x0002, 6694 "fc_attach_transport failed...Failing load!.\n"); 6695 qlt_exit(); 6696 return -ENODEV; 6697 } 6698 6699 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6700 if (apidev_major < 0) { 6701 ql_log(ql_log_fatal, NULL, 0x0003, 6702 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6703 } 6704 6705 qla2xxx_transport_vport_template = 6706 fc_attach_transport(&qla2xxx_transport_vport_functions); 6707 if (!qla2xxx_transport_vport_template) { 6708 kmem_cache_destroy(srb_cachep); 6709 qlt_exit(); 6710 fc_release_transport(qla2xxx_transport_template); 6711 ql_log(ql_log_fatal, NULL, 0x0004, 6712 "fc_attach_transport vport failed...Failing load!.\n"); 6713 return -ENODEV; 6714 } 6715 ql_log(ql_log_info, NULL, 0x0005, 6716 "QLogic Fibre Channel HBA Driver: %s.\n", 6717 qla2x00_version_str); 6718 ret = pci_register_driver(&qla2xxx_pci_driver); 6719 if (ret) { 6720 kmem_cache_destroy(srb_cachep); 6721 qlt_exit(); 6722 fc_release_transport(qla2xxx_transport_template); 6723 fc_release_transport(qla2xxx_transport_vport_template); 6724 ql_log(ql_log_fatal, NULL, 0x0006, 6725 "pci_register_driver failed...ret=%d Failing load!.\n", 6726 ret); 6727 } 6728 return ret; 6729 } 6730 6731 /** 6732 * qla2x00_module_exit - Module cleanup. 6733 **/ 6734 static void __exit 6735 qla2x00_module_exit(void) 6736 { 6737 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6738 pci_unregister_driver(&qla2xxx_pci_driver); 6739 qla2x00_release_firmware(); 6740 kmem_cache_destroy(srb_cachep); 6741 qlt_exit(); 6742 if (ctx_cachep) 6743 kmem_cache_destroy(ctx_cachep); 6744 fc_release_transport(qla2xxx_transport_template); 6745 fc_release_transport(qla2xxx_transport_vport_template); 6746 } 6747 6748 module_init(qla2x00_module_init); 6749 module_exit(qla2x00_module_exit); 6750 6751 MODULE_AUTHOR("QLogic Corporation"); 6752 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6753 MODULE_LICENSE("GPL"); 6754 MODULE_VERSION(QLA2XXX_VERSION); 6755 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6756 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6757 MODULE_FIRMWARE(FW_FILE_ISP2300); 6758 MODULE_FIRMWARE(FW_FILE_ISP2322); 6759 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6760 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6761