1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 struct scsi_host_template qla2xxx_driver_template = { 307 .module = THIS_MODULE, 308 .name = QLA2XXX_DRIVER_NAME, 309 .queuecommand = qla2xxx_queuecommand, 310 311 .eh_timed_out = fc_eh_timed_out, 312 .eh_abort_handler = qla2xxx_eh_abort, 313 .eh_device_reset_handler = qla2xxx_eh_device_reset, 314 .eh_target_reset_handler = qla2xxx_eh_target_reset, 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 316 .eh_host_reset_handler = qla2xxx_eh_host_reset, 317 318 .slave_configure = qla2xxx_slave_configure, 319 320 .slave_alloc = qla2xxx_slave_alloc, 321 .slave_destroy = qla2xxx_slave_destroy, 322 .scan_finished = qla2xxx_scan_finished, 323 .scan_start = qla2xxx_scan_start, 324 .change_queue_depth = scsi_change_queue_depth, 325 .map_queues = qla2xxx_map_queues, 326 .this_id = -1, 327 .cmd_per_lun = 3, 328 .use_clustering = ENABLE_CLUSTERING, 329 .sg_tablesize = SG_ALL, 330 331 .max_sectors = 0xFFFF, 332 .shost_attrs = qla2x00_host_attrs, 333 334 .supported_mode = MODE_INITIATOR, 335 .track_queue_depth = 1, 336 }; 337 338 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 339 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 340 341 /* TODO Convert to inlines 342 * 343 * Timer routines 344 */ 345 346 __inline__ void 347 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 348 { 349 timer_setup(&vha->timer, qla2x00_timer, 0); 350 vha->timer.expires = jiffies + interval * HZ; 351 add_timer(&vha->timer); 352 vha->timer_active = 1; 353 } 354 355 static inline void 356 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 357 { 358 /* Currently used for 82XX only. */ 359 if (vha->device_flags & DFLG_DEV_FAILED) { 360 ql_dbg(ql_dbg_timer, vha, 0x600d, 361 "Device in a failed state, returning.\n"); 362 return; 363 } 364 365 mod_timer(&vha->timer, jiffies + interval * HZ); 366 } 367 368 static __inline__ void 369 qla2x00_stop_timer(scsi_qla_host_t *vha) 370 { 371 del_timer_sync(&vha->timer); 372 vha->timer_active = 0; 373 } 374 375 static int qla2x00_do_dpc(void *data); 376 377 static void qla2x00_rst_aen(scsi_qla_host_t *); 378 379 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 380 struct req_que **, struct rsp_que **); 381 static void qla2x00_free_fw_dump(struct qla_hw_data *); 382 static void qla2x00_mem_free(struct qla_hw_data *); 383 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 384 struct qla_qpair *qpair); 385 386 /* -------------------------------------------------------------------------- */ 387 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 388 struct rsp_que *rsp) 389 { 390 struct qla_hw_data *ha = vha->hw; 391 rsp->qpair = ha->base_qpair; 392 rsp->req = req; 393 ha->base_qpair->req = req; 394 ha->base_qpair->rsp = rsp; 395 ha->base_qpair->vha = vha; 396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 399 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 400 ha->base_qpair->enable_class_2 = ql2xenableclass2; 401 /* init qpair to this cpu. Will adjust at run time. */ 402 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 403 ha->base_qpair->pdev = ha->pdev; 404 405 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 406 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 407 } 408 409 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 410 struct rsp_que *rsp) 411 { 412 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 413 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 414 GFP_KERNEL); 415 if (!ha->req_q_map) { 416 ql_log(ql_log_fatal, vha, 0x003b, 417 "Unable to allocate memory for request queue ptrs.\n"); 418 goto fail_req_map; 419 } 420 421 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 422 GFP_KERNEL); 423 if (!ha->rsp_q_map) { 424 ql_log(ql_log_fatal, vha, 0x003c, 425 "Unable to allocate memory for response queue ptrs.\n"); 426 goto fail_rsp_map; 427 } 428 429 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 430 if (ha->base_qpair == NULL) { 431 ql_log(ql_log_warn, vha, 0x00e0, 432 "Failed to allocate base queue pair memory.\n"); 433 goto fail_base_qpair; 434 } 435 436 qla_init_base_qpair(vha, req, rsp); 437 438 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 439 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 440 GFP_KERNEL); 441 if (!ha->queue_pair_map) { 442 ql_log(ql_log_fatal, vha, 0x0180, 443 "Unable to allocate memory for queue pair ptrs.\n"); 444 goto fail_qpair_map; 445 } 446 } 447 448 /* 449 * Make sure we record at least the request and response queue zero in 450 * case we need to free them if part of the probe fails. 451 */ 452 ha->rsp_q_map[0] = rsp; 453 ha->req_q_map[0] = req; 454 set_bit(0, ha->rsp_qid_map); 455 set_bit(0, ha->req_qid_map); 456 return 0; 457 458 fail_qpair_map: 459 kfree(ha->base_qpair); 460 ha->base_qpair = NULL; 461 fail_base_qpair: 462 kfree(ha->rsp_q_map); 463 ha->rsp_q_map = NULL; 464 fail_rsp_map: 465 kfree(ha->req_q_map); 466 ha->req_q_map = NULL; 467 fail_req_map: 468 return -ENOMEM; 469 } 470 471 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 472 { 473 if (!ha->req_q_map) 474 return; 475 476 if (IS_QLAFX00(ha)) { 477 if (req && req->ring_fx00) 478 dma_free_coherent(&ha->pdev->dev, 479 (req->length_fx00 + 1) * sizeof(request_t), 480 req->ring_fx00, req->dma_fx00); 481 } else if (req && req->ring) 482 dma_free_coherent(&ha->pdev->dev, 483 (req->length + 1) * sizeof(request_t), 484 req->ring, req->dma); 485 486 if (req) { 487 kfree(req->outstanding_cmds); 488 kfree(req); 489 } 490 } 491 492 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 493 { 494 if (!ha->rsp_q_map) 495 return; 496 497 if (IS_QLAFX00(ha)) { 498 if (rsp && rsp->ring_fx00) 499 dma_free_coherent(&ha->pdev->dev, 500 (rsp->length_fx00 + 1) * sizeof(request_t), 501 rsp->ring_fx00, rsp->dma_fx00); 502 } else if (rsp && rsp->ring) { 503 dma_free_coherent(&ha->pdev->dev, 504 (rsp->length + 1) * sizeof(response_t), 505 rsp->ring, rsp->dma); 506 } 507 if (rsp) 508 kfree(rsp); 509 } 510 511 static void qla2x00_free_queues(struct qla_hw_data *ha) 512 { 513 struct req_que *req; 514 struct rsp_que *rsp; 515 int cnt; 516 unsigned long flags; 517 518 if (ha->queue_pair_map) { 519 kfree(ha->queue_pair_map); 520 ha->queue_pair_map = NULL; 521 } 522 if (ha->base_qpair) { 523 kfree(ha->base_qpair); 524 ha->base_qpair = NULL; 525 } 526 527 spin_lock_irqsave(&ha->hardware_lock, flags); 528 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 529 if (!test_bit(cnt, ha->req_qid_map)) 530 continue; 531 532 req = ha->req_q_map[cnt]; 533 clear_bit(cnt, ha->req_qid_map); 534 ha->req_q_map[cnt] = NULL; 535 536 spin_unlock_irqrestore(&ha->hardware_lock, flags); 537 qla2x00_free_req_que(ha, req); 538 spin_lock_irqsave(&ha->hardware_lock, flags); 539 } 540 spin_unlock_irqrestore(&ha->hardware_lock, flags); 541 542 kfree(ha->req_q_map); 543 ha->req_q_map = NULL; 544 545 546 spin_lock_irqsave(&ha->hardware_lock, flags); 547 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 548 if (!test_bit(cnt, ha->rsp_qid_map)) 549 continue; 550 551 rsp = ha->rsp_q_map[cnt]; 552 clear_bit(cnt, ha->rsp_qid_map); 553 ha->rsp_q_map[cnt] = NULL; 554 spin_unlock_irqrestore(&ha->hardware_lock, flags); 555 qla2x00_free_rsp_que(ha, rsp); 556 spin_lock_irqsave(&ha->hardware_lock, flags); 557 } 558 spin_unlock_irqrestore(&ha->hardware_lock, flags); 559 560 kfree(ha->rsp_q_map); 561 ha->rsp_q_map = NULL; 562 } 563 564 static char * 565 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 566 { 567 struct qla_hw_data *ha = vha->hw; 568 static char *pci_bus_modes[] = { 569 "33", "66", "100", "133", 570 }; 571 uint16_t pci_bus; 572 573 strcpy(str, "PCI"); 574 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 575 if (pci_bus) { 576 strcat(str, "-X ("); 577 strcat(str, pci_bus_modes[pci_bus]); 578 } else { 579 pci_bus = (ha->pci_attr & BIT_8) >> 8; 580 strcat(str, " ("); 581 strcat(str, pci_bus_modes[pci_bus]); 582 } 583 strcat(str, " MHz)"); 584 585 return (str); 586 } 587 588 static char * 589 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 590 { 591 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 592 struct qla_hw_data *ha = vha->hw; 593 uint32_t pci_bus; 594 595 if (pci_is_pcie(ha->pdev)) { 596 char lwstr[6]; 597 uint32_t lstat, lspeed, lwidth; 598 599 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 600 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 601 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 602 603 strcpy(str, "PCIe ("); 604 switch (lspeed) { 605 case 1: 606 strcat(str, "2.5GT/s "); 607 break; 608 case 2: 609 strcat(str, "5.0GT/s "); 610 break; 611 case 3: 612 strcat(str, "8.0GT/s "); 613 break; 614 default: 615 strcat(str, "<unknown> "); 616 break; 617 } 618 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 619 strcat(str, lwstr); 620 621 return str; 622 } 623 624 strcpy(str, "PCI"); 625 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 626 if (pci_bus == 0 || pci_bus == 8) { 627 strcat(str, " ("); 628 strcat(str, pci_bus_modes[pci_bus >> 3]); 629 } else { 630 strcat(str, "-X "); 631 if (pci_bus & BIT_2) 632 strcat(str, "Mode 2"); 633 else 634 strcat(str, "Mode 1"); 635 strcat(str, " ("); 636 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 637 } 638 strcat(str, " MHz)"); 639 640 return str; 641 } 642 643 static char * 644 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 645 { 646 char un_str[10]; 647 struct qla_hw_data *ha = vha->hw; 648 649 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 650 ha->fw_minor_version, ha->fw_subminor_version); 651 652 if (ha->fw_attributes & BIT_9) { 653 strcat(str, "FLX"); 654 return (str); 655 } 656 657 switch (ha->fw_attributes & 0xFF) { 658 case 0x7: 659 strcat(str, "EF"); 660 break; 661 case 0x17: 662 strcat(str, "TP"); 663 break; 664 case 0x37: 665 strcat(str, "IP"); 666 break; 667 case 0x77: 668 strcat(str, "VI"); 669 break; 670 default: 671 sprintf(un_str, "(%x)", ha->fw_attributes); 672 strcat(str, un_str); 673 break; 674 } 675 if (ha->fw_attributes & 0x100) 676 strcat(str, "X"); 677 678 return (str); 679 } 680 681 static char * 682 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 683 { 684 struct qla_hw_data *ha = vha->hw; 685 686 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 687 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 688 return str; 689 } 690 691 void 692 qla2x00_sp_free_dma(void *ptr) 693 { 694 srb_t *sp = ptr; 695 struct qla_hw_data *ha = sp->vha->hw; 696 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 697 void *ctx = GET_CMD_CTX_SP(sp); 698 699 if (sp->flags & SRB_DMA_VALID) { 700 scsi_dma_unmap(cmd); 701 sp->flags &= ~SRB_DMA_VALID; 702 } 703 704 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 705 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 706 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 707 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 708 } 709 710 if (!ctx) 711 goto end; 712 713 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 714 /* List assured to be having elements */ 715 qla2x00_clean_dsd_pool(ha, ctx); 716 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 717 } 718 719 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 720 struct crc_context *ctx0 = ctx; 721 722 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 723 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 724 } 725 726 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 727 struct ct6_dsd *ctx1 = ctx; 728 729 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 730 ctx1->fcp_cmnd_dma); 731 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 732 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 733 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 734 mempool_free(ctx1, ha->ctx_mempool); 735 } 736 737 end: 738 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 739 CMD_SP(cmd) = NULL; 740 qla2x00_rel_sp(sp); 741 } 742 } 743 744 void 745 qla2x00_sp_compl(void *ptr, int res) 746 { 747 srb_t *sp = ptr; 748 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 749 750 cmd->result = res; 751 752 if (atomic_read(&sp->ref_count) == 0) { 753 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 754 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 755 sp, GET_CMD_SP(sp)); 756 if (ql2xextended_error_logging & ql_dbg_io) 757 WARN_ON(atomic_read(&sp->ref_count) == 0); 758 return; 759 } 760 if (!atomic_dec_and_test(&sp->ref_count)) 761 return; 762 763 sp->free(sp); 764 cmd->scsi_done(cmd); 765 } 766 767 void 768 qla2xxx_qpair_sp_free_dma(void *ptr) 769 { 770 srb_t *sp = (srb_t *)ptr; 771 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 772 struct qla_hw_data *ha = sp->fcport->vha->hw; 773 void *ctx = GET_CMD_CTX_SP(sp); 774 775 if (sp->flags & SRB_DMA_VALID) { 776 scsi_dma_unmap(cmd); 777 sp->flags &= ~SRB_DMA_VALID; 778 } 779 780 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 781 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 782 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 783 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 784 } 785 786 if (!ctx) 787 goto end; 788 789 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 790 /* List assured to be having elements */ 791 qla2x00_clean_dsd_pool(ha, ctx); 792 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 793 } 794 795 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 796 struct crc_context *ctx0 = ctx; 797 798 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 799 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 800 } 801 802 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 803 struct ct6_dsd *ctx1 = ctx; 804 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 805 ctx1->fcp_cmnd_dma); 806 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 807 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 808 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 809 mempool_free(ctx1, ha->ctx_mempool); 810 } 811 end: 812 CMD_SP(cmd) = NULL; 813 qla2xxx_rel_qpair_sp(sp->qpair, sp); 814 } 815 816 void 817 qla2xxx_qpair_sp_compl(void *ptr, int res) 818 { 819 srb_t *sp = ptr; 820 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 821 822 cmd->result = res; 823 824 if (atomic_read(&sp->ref_count) == 0) { 825 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 826 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 827 sp, GET_CMD_SP(sp)); 828 if (ql2xextended_error_logging & ql_dbg_io) 829 WARN_ON(atomic_read(&sp->ref_count) == 0); 830 return; 831 } 832 if (!atomic_dec_and_test(&sp->ref_count)) 833 return; 834 835 sp->free(sp); 836 cmd->scsi_done(cmd); 837 } 838 839 /* If we are SP1 here, we need to still take and release the host_lock as SP1 840 * does not have the changes necessary to avoid taking host->host_lock. 841 */ 842 static int 843 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 844 { 845 scsi_qla_host_t *vha = shost_priv(host); 846 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 847 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 848 struct qla_hw_data *ha = vha->hw; 849 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 850 srb_t *sp; 851 int rval; 852 struct qla_qpair *qpair = NULL; 853 uint32_t tag; 854 uint16_t hwq; 855 856 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 857 cmd->result = DID_NO_CONNECT << 16; 858 goto qc24_fail_command; 859 } 860 861 if (ha->mqenable) { 862 if (shost_use_blk_mq(vha->host)) { 863 tag = blk_mq_unique_tag(cmd->request); 864 hwq = blk_mq_unique_tag_to_hwq(tag); 865 qpair = ha->queue_pair_map[hwq]; 866 } else if (vha->vp_idx && vha->qpair) { 867 qpair = vha->qpair; 868 } 869 870 if (qpair) 871 return qla2xxx_mqueuecommand(host, cmd, qpair); 872 } 873 874 if (ha->flags.eeh_busy) { 875 if (ha->flags.pci_channel_io_perm_failure) { 876 ql_dbg(ql_dbg_aer, vha, 0x9010, 877 "PCI Channel IO permanent failure, exiting " 878 "cmd=%p.\n", cmd); 879 cmd->result = DID_NO_CONNECT << 16; 880 } else { 881 ql_dbg(ql_dbg_aer, vha, 0x9011, 882 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 883 cmd->result = DID_REQUEUE << 16; 884 } 885 goto qc24_fail_command; 886 } 887 888 rval = fc_remote_port_chkready(rport); 889 if (rval) { 890 cmd->result = rval; 891 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 892 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 893 cmd, rval); 894 goto qc24_fail_command; 895 } 896 897 if (!vha->flags.difdix_supported && 898 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 899 ql_dbg(ql_dbg_io, vha, 0x3004, 900 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 901 cmd); 902 cmd->result = DID_NO_CONNECT << 16; 903 goto qc24_fail_command; 904 } 905 906 if (!fcport) { 907 cmd->result = DID_NO_CONNECT << 16; 908 goto qc24_fail_command; 909 } 910 911 if (atomic_read(&fcport->state) != FCS_ONLINE) { 912 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 913 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 914 ql_dbg(ql_dbg_io, vha, 0x3005, 915 "Returning DNC, fcport_state=%d loop_state=%d.\n", 916 atomic_read(&fcport->state), 917 atomic_read(&base_vha->loop_state)); 918 cmd->result = DID_NO_CONNECT << 16; 919 goto qc24_fail_command; 920 } 921 goto qc24_target_busy; 922 } 923 924 /* 925 * Return target busy if we've received a non-zero retry_delay_timer 926 * in a FCP_RSP. 927 */ 928 if (fcport->retry_delay_timestamp == 0) { 929 /* retry delay not set */ 930 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 931 fcport->retry_delay_timestamp = 0; 932 else 933 goto qc24_target_busy; 934 935 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 936 if (!sp) 937 goto qc24_host_busy; 938 939 sp->u.scmd.cmd = cmd; 940 sp->type = SRB_SCSI_CMD; 941 atomic_set(&sp->ref_count, 1); 942 CMD_SP(cmd) = (void *)sp; 943 sp->free = qla2x00_sp_free_dma; 944 sp->done = qla2x00_sp_compl; 945 946 rval = ha->isp_ops->start_scsi(sp); 947 if (rval != QLA_SUCCESS) { 948 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 949 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 950 goto qc24_host_busy_free_sp; 951 } 952 953 return 0; 954 955 qc24_host_busy_free_sp: 956 sp->free(sp); 957 958 qc24_host_busy: 959 return SCSI_MLQUEUE_HOST_BUSY; 960 961 qc24_target_busy: 962 return SCSI_MLQUEUE_TARGET_BUSY; 963 964 qc24_fail_command: 965 cmd->scsi_done(cmd); 966 967 return 0; 968 } 969 970 /* For MQ supported I/O */ 971 int 972 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 973 struct qla_qpair *qpair) 974 { 975 scsi_qla_host_t *vha = shost_priv(host); 976 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 977 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 978 struct qla_hw_data *ha = vha->hw; 979 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 980 srb_t *sp; 981 int rval; 982 983 rval = fc_remote_port_chkready(rport); 984 if (rval) { 985 cmd->result = rval; 986 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 987 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 988 cmd, rval); 989 goto qc24_fail_command; 990 } 991 992 if (!fcport) { 993 cmd->result = DID_NO_CONNECT << 16; 994 goto qc24_fail_command; 995 } 996 997 if (atomic_read(&fcport->state) != FCS_ONLINE) { 998 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 999 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1000 ql_dbg(ql_dbg_io, vha, 0x3077, 1001 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1002 atomic_read(&fcport->state), 1003 atomic_read(&base_vha->loop_state)); 1004 cmd->result = DID_NO_CONNECT << 16; 1005 goto qc24_fail_command; 1006 } 1007 goto qc24_target_busy; 1008 } 1009 1010 /* 1011 * Return target busy if we've received a non-zero retry_delay_timer 1012 * in a FCP_RSP. 1013 */ 1014 if (fcport->retry_delay_timestamp == 0) { 1015 /* retry delay not set */ 1016 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1017 fcport->retry_delay_timestamp = 0; 1018 else 1019 goto qc24_target_busy; 1020 1021 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1022 if (!sp) 1023 goto qc24_host_busy; 1024 1025 sp->u.scmd.cmd = cmd; 1026 sp->type = SRB_SCSI_CMD; 1027 atomic_set(&sp->ref_count, 1); 1028 CMD_SP(cmd) = (void *)sp; 1029 sp->free = qla2xxx_qpair_sp_free_dma; 1030 sp->done = qla2xxx_qpair_sp_compl; 1031 sp->qpair = qpair; 1032 1033 rval = ha->isp_ops->start_scsi_mq(sp); 1034 if (rval != QLA_SUCCESS) { 1035 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1036 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1037 if (rval == QLA_INTERFACE_ERROR) 1038 goto qc24_fail_command; 1039 goto qc24_host_busy_free_sp; 1040 } 1041 1042 return 0; 1043 1044 qc24_host_busy_free_sp: 1045 sp->free(sp); 1046 1047 qc24_host_busy: 1048 return SCSI_MLQUEUE_HOST_BUSY; 1049 1050 qc24_target_busy: 1051 return SCSI_MLQUEUE_TARGET_BUSY; 1052 1053 qc24_fail_command: 1054 cmd->scsi_done(cmd); 1055 1056 return 0; 1057 } 1058 1059 /* 1060 * qla2x00_eh_wait_on_command 1061 * Waits for the command to be returned by the Firmware for some 1062 * max time. 1063 * 1064 * Input: 1065 * cmd = Scsi Command to wait on. 1066 * 1067 * Return: 1068 * Not Found : 0 1069 * Found : 1 1070 */ 1071 static int 1072 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1073 { 1074 #define ABORT_POLLING_PERIOD 1000 1075 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1076 unsigned long wait_iter = ABORT_WAIT_ITER; 1077 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1078 struct qla_hw_data *ha = vha->hw; 1079 int ret = QLA_SUCCESS; 1080 1081 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1082 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1083 "Return:eh_wait.\n"); 1084 return ret; 1085 } 1086 1087 while (CMD_SP(cmd) && wait_iter--) { 1088 msleep(ABORT_POLLING_PERIOD); 1089 } 1090 if (CMD_SP(cmd)) 1091 ret = QLA_FUNCTION_FAILED; 1092 1093 return ret; 1094 } 1095 1096 /* 1097 * qla2x00_wait_for_hba_online 1098 * Wait till the HBA is online after going through 1099 * <= MAX_RETRIES_OF_ISP_ABORT or 1100 * finally HBA is disabled ie marked offline 1101 * 1102 * Input: 1103 * ha - pointer to host adapter structure 1104 * 1105 * Note: 1106 * Does context switching-Release SPIN_LOCK 1107 * (if any) before calling this routine. 1108 * 1109 * Return: 1110 * Success (Adapter is online) : 0 1111 * Failed (Adapter is offline/disabled) : 1 1112 */ 1113 int 1114 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1115 { 1116 int return_status; 1117 unsigned long wait_online; 1118 struct qla_hw_data *ha = vha->hw; 1119 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1120 1121 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1122 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1123 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1124 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1125 ha->dpc_active) && time_before(jiffies, wait_online)) { 1126 1127 msleep(1000); 1128 } 1129 if (base_vha->flags.online) 1130 return_status = QLA_SUCCESS; 1131 else 1132 return_status = QLA_FUNCTION_FAILED; 1133 1134 return (return_status); 1135 } 1136 1137 static inline int test_fcport_count(scsi_qla_host_t *vha) 1138 { 1139 struct qla_hw_data *ha = vha->hw; 1140 unsigned long flags; 1141 int res; 1142 1143 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1144 ql_dbg(ql_dbg_init, vha, 0x00ec, 1145 "tgt %p, fcport_count=%d\n", 1146 vha, vha->fcport_count); 1147 res = (vha->fcport_count == 0); 1148 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1149 1150 return res; 1151 } 1152 1153 /* 1154 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1155 * it has dependency on UNLOADING flag to stop device discovery 1156 */ 1157 static void 1158 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1159 { 1160 qla2x00_mark_all_devices_lost(vha, 0); 1161 1162 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1163 } 1164 1165 /* 1166 * qla2x00_wait_for_hba_ready 1167 * Wait till the HBA is ready before doing driver unload 1168 * 1169 * Input: 1170 * ha - pointer to host adapter structure 1171 * 1172 * Note: 1173 * Does context switching-Release SPIN_LOCK 1174 * (if any) before calling this routine. 1175 * 1176 */ 1177 static void 1178 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1179 { 1180 struct qla_hw_data *ha = vha->hw; 1181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1182 1183 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1184 ha->flags.mbox_busy) || 1185 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1186 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1187 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1188 break; 1189 msleep(1000); 1190 } 1191 } 1192 1193 int 1194 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1195 { 1196 int return_status; 1197 unsigned long wait_reset; 1198 struct qla_hw_data *ha = vha->hw; 1199 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1200 1201 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1202 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1203 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1204 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1205 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1206 1207 msleep(1000); 1208 1209 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1210 ha->flags.chip_reset_done) 1211 break; 1212 } 1213 if (ha->flags.chip_reset_done) 1214 return_status = QLA_SUCCESS; 1215 else 1216 return_status = QLA_FUNCTION_FAILED; 1217 1218 return return_status; 1219 } 1220 1221 static void 1222 sp_get(struct srb *sp) 1223 { 1224 atomic_inc(&sp->ref_count); 1225 } 1226 1227 #define ISP_REG_DISCONNECT 0xffffffffU 1228 /************************************************************************** 1229 * qla2x00_isp_reg_stat 1230 * 1231 * Description: 1232 * Read the host status register of ISP before aborting the command. 1233 * 1234 * Input: 1235 * ha = pointer to host adapter structure. 1236 * 1237 * 1238 * Returns: 1239 * Either true or false. 1240 * 1241 * Note: Return true if there is register disconnect. 1242 **************************************************************************/ 1243 static inline 1244 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1245 { 1246 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1247 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1248 1249 if (IS_P3P_TYPE(ha)) 1250 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1251 else 1252 return ((RD_REG_DWORD(®->host_status)) == 1253 ISP_REG_DISCONNECT); 1254 } 1255 1256 /************************************************************************** 1257 * qla2xxx_eh_abort 1258 * 1259 * Description: 1260 * The abort function will abort the specified command. 1261 * 1262 * Input: 1263 * cmd = Linux SCSI command packet to be aborted. 1264 * 1265 * Returns: 1266 * Either SUCCESS or FAILED. 1267 * 1268 * Note: 1269 * Only return FAILED if command not returned by firmware. 1270 **************************************************************************/ 1271 static int 1272 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1273 { 1274 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1275 srb_t *sp; 1276 int ret; 1277 unsigned int id; 1278 uint64_t lun; 1279 unsigned long flags; 1280 int rval, wait = 0; 1281 struct qla_hw_data *ha = vha->hw; 1282 1283 if (qla2x00_isp_reg_stat(ha)) { 1284 ql_log(ql_log_info, vha, 0x8042, 1285 "PCI/Register disconnect, exiting.\n"); 1286 return FAILED; 1287 } 1288 if (!CMD_SP(cmd)) 1289 return SUCCESS; 1290 1291 ret = fc_block_scsi_eh(cmd); 1292 if (ret != 0) 1293 return ret; 1294 ret = SUCCESS; 1295 1296 id = cmd->device->id; 1297 lun = cmd->device->lun; 1298 1299 spin_lock_irqsave(&ha->hardware_lock, flags); 1300 sp = (srb_t *) CMD_SP(cmd); 1301 if (!sp) { 1302 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1303 return SUCCESS; 1304 } 1305 1306 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1307 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1308 vha->host_no, id, lun, sp, cmd, sp->handle); 1309 1310 /* Get a reference to the sp and drop the lock.*/ 1311 sp_get(sp); 1312 1313 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1314 rval = ha->isp_ops->abort_command(sp); 1315 if (rval) { 1316 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1317 ret = SUCCESS; 1318 else 1319 ret = FAILED; 1320 1321 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1322 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1323 } else { 1324 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1325 "Abort command mbx success cmd=%p.\n", cmd); 1326 wait = 1; 1327 } 1328 1329 spin_lock_irqsave(&ha->hardware_lock, flags); 1330 sp->done(sp, 0); 1331 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1332 1333 /* Did the command return during mailbox execution? */ 1334 if (ret == FAILED && !CMD_SP(cmd)) 1335 ret = SUCCESS; 1336 1337 /* Wait for the command to be returned. */ 1338 if (wait) { 1339 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1340 ql_log(ql_log_warn, vha, 0x8006, 1341 "Abort handler timed out cmd=%p.\n", cmd); 1342 ret = FAILED; 1343 } 1344 } 1345 1346 ql_log(ql_log_info, vha, 0x801c, 1347 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1348 vha->host_no, id, lun, wait, ret); 1349 1350 return ret; 1351 } 1352 1353 int 1354 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1355 uint64_t l, enum nexus_wait_type type) 1356 { 1357 int cnt, match, status; 1358 unsigned long flags; 1359 struct qla_hw_data *ha = vha->hw; 1360 struct req_que *req; 1361 srb_t *sp; 1362 struct scsi_cmnd *cmd; 1363 1364 status = QLA_SUCCESS; 1365 1366 spin_lock_irqsave(&ha->hardware_lock, flags); 1367 req = vha->req; 1368 for (cnt = 1; status == QLA_SUCCESS && 1369 cnt < req->num_outstanding_cmds; cnt++) { 1370 sp = req->outstanding_cmds[cnt]; 1371 if (!sp) 1372 continue; 1373 if (sp->type != SRB_SCSI_CMD) 1374 continue; 1375 if (vha->vp_idx != sp->vha->vp_idx) 1376 continue; 1377 match = 0; 1378 cmd = GET_CMD_SP(sp); 1379 switch (type) { 1380 case WAIT_HOST: 1381 match = 1; 1382 break; 1383 case WAIT_TARGET: 1384 match = cmd->device->id == t; 1385 break; 1386 case WAIT_LUN: 1387 match = (cmd->device->id == t && 1388 cmd->device->lun == l); 1389 break; 1390 } 1391 if (!match) 1392 continue; 1393 1394 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1395 status = qla2x00_eh_wait_on_command(cmd); 1396 spin_lock_irqsave(&ha->hardware_lock, flags); 1397 } 1398 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1399 1400 return status; 1401 } 1402 1403 static char *reset_errors[] = { 1404 "HBA not online", 1405 "HBA not ready", 1406 "Task management failed", 1407 "Waiting for command completions", 1408 }; 1409 1410 static int 1411 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1412 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1413 { 1414 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1415 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1416 int err; 1417 1418 if (!fcport) { 1419 return FAILED; 1420 } 1421 1422 err = fc_block_scsi_eh(cmd); 1423 if (err != 0) 1424 return err; 1425 1426 ql_log(ql_log_info, vha, 0x8009, 1427 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1428 cmd->device->id, cmd->device->lun, cmd); 1429 1430 err = 0; 1431 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1432 ql_log(ql_log_warn, vha, 0x800a, 1433 "Wait for hba online failed for cmd=%p.\n", cmd); 1434 goto eh_reset_failed; 1435 } 1436 err = 2; 1437 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1438 != QLA_SUCCESS) { 1439 ql_log(ql_log_warn, vha, 0x800c, 1440 "do_reset failed for cmd=%p.\n", cmd); 1441 goto eh_reset_failed; 1442 } 1443 err = 3; 1444 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1445 cmd->device->lun, type) != QLA_SUCCESS) { 1446 ql_log(ql_log_warn, vha, 0x800d, 1447 "wait for pending cmds failed for cmd=%p.\n", cmd); 1448 goto eh_reset_failed; 1449 } 1450 1451 ql_log(ql_log_info, vha, 0x800e, 1452 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1453 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1454 1455 return SUCCESS; 1456 1457 eh_reset_failed: 1458 ql_log(ql_log_info, vha, 0x800f, 1459 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1460 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1461 cmd); 1462 return FAILED; 1463 } 1464 1465 static int 1466 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1467 { 1468 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1469 struct qla_hw_data *ha = vha->hw; 1470 1471 if (qla2x00_isp_reg_stat(ha)) { 1472 ql_log(ql_log_info, vha, 0x803e, 1473 "PCI/Register disconnect, exiting.\n"); 1474 return FAILED; 1475 } 1476 1477 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1478 ha->isp_ops->lun_reset); 1479 } 1480 1481 static int 1482 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1483 { 1484 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1485 struct qla_hw_data *ha = vha->hw; 1486 1487 if (qla2x00_isp_reg_stat(ha)) { 1488 ql_log(ql_log_info, vha, 0x803f, 1489 "PCI/Register disconnect, exiting.\n"); 1490 return FAILED; 1491 } 1492 1493 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1494 ha->isp_ops->target_reset); 1495 } 1496 1497 /************************************************************************** 1498 * qla2xxx_eh_bus_reset 1499 * 1500 * Description: 1501 * The bus reset function will reset the bus and abort any executing 1502 * commands. 1503 * 1504 * Input: 1505 * cmd = Linux SCSI command packet of the command that cause the 1506 * bus reset. 1507 * 1508 * Returns: 1509 * SUCCESS/FAILURE (defined as macro in scsi.h). 1510 * 1511 **************************************************************************/ 1512 static int 1513 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1514 { 1515 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1516 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1517 int ret = FAILED; 1518 unsigned int id; 1519 uint64_t lun; 1520 struct qla_hw_data *ha = vha->hw; 1521 1522 if (qla2x00_isp_reg_stat(ha)) { 1523 ql_log(ql_log_info, vha, 0x8040, 1524 "PCI/Register disconnect, exiting.\n"); 1525 return FAILED; 1526 } 1527 1528 id = cmd->device->id; 1529 lun = cmd->device->lun; 1530 1531 if (!fcport) { 1532 return ret; 1533 } 1534 1535 ret = fc_block_scsi_eh(cmd); 1536 if (ret != 0) 1537 return ret; 1538 ret = FAILED; 1539 1540 ql_log(ql_log_info, vha, 0x8012, 1541 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1542 1543 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1544 ql_log(ql_log_fatal, vha, 0x8013, 1545 "Wait for hba online failed board disabled.\n"); 1546 goto eh_bus_reset_done; 1547 } 1548 1549 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1550 ret = SUCCESS; 1551 1552 if (ret == FAILED) 1553 goto eh_bus_reset_done; 1554 1555 /* Flush outstanding commands. */ 1556 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1557 QLA_SUCCESS) { 1558 ql_log(ql_log_warn, vha, 0x8014, 1559 "Wait for pending commands failed.\n"); 1560 ret = FAILED; 1561 } 1562 1563 eh_bus_reset_done: 1564 ql_log(ql_log_warn, vha, 0x802b, 1565 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1566 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1567 1568 return ret; 1569 } 1570 1571 /************************************************************************** 1572 * qla2xxx_eh_host_reset 1573 * 1574 * Description: 1575 * The reset function will reset the Adapter. 1576 * 1577 * Input: 1578 * cmd = Linux SCSI command packet of the command that cause the 1579 * adapter reset. 1580 * 1581 * Returns: 1582 * Either SUCCESS or FAILED. 1583 * 1584 * Note: 1585 **************************************************************************/ 1586 static int 1587 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1588 { 1589 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1590 struct qla_hw_data *ha = vha->hw; 1591 int ret = FAILED; 1592 unsigned int id; 1593 uint64_t lun; 1594 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1595 1596 if (qla2x00_isp_reg_stat(ha)) { 1597 ql_log(ql_log_info, vha, 0x8041, 1598 "PCI/Register disconnect, exiting.\n"); 1599 schedule_work(&ha->board_disable); 1600 return SUCCESS; 1601 } 1602 1603 id = cmd->device->id; 1604 lun = cmd->device->lun; 1605 1606 ql_log(ql_log_info, vha, 0x8018, 1607 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1608 1609 /* 1610 * No point in issuing another reset if one is active. Also do not 1611 * attempt a reset if we are updating flash. 1612 */ 1613 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1614 goto eh_host_reset_lock; 1615 1616 if (vha != base_vha) { 1617 if (qla2x00_vp_abort_isp(vha)) 1618 goto eh_host_reset_lock; 1619 } else { 1620 if (IS_P3P_TYPE(vha->hw)) { 1621 if (!qla82xx_fcoe_ctx_reset(vha)) { 1622 /* Ctx reset success */ 1623 ret = SUCCESS; 1624 goto eh_host_reset_lock; 1625 } 1626 /* fall thru if ctx reset failed */ 1627 } 1628 if (ha->wq) 1629 flush_workqueue(ha->wq); 1630 1631 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1632 if (ha->isp_ops->abort_isp(base_vha)) { 1633 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1634 /* failed. schedule dpc to try */ 1635 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1636 1637 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1638 ql_log(ql_log_warn, vha, 0x802a, 1639 "wait for hba online failed.\n"); 1640 goto eh_host_reset_lock; 1641 } 1642 } 1643 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1644 } 1645 1646 /* Waiting for command to be returned to OS.*/ 1647 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1648 QLA_SUCCESS) 1649 ret = SUCCESS; 1650 1651 eh_host_reset_lock: 1652 ql_log(ql_log_info, vha, 0x8017, 1653 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1654 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1655 1656 return ret; 1657 } 1658 1659 /* 1660 * qla2x00_loop_reset 1661 * Issue loop reset. 1662 * 1663 * Input: 1664 * ha = adapter block pointer. 1665 * 1666 * Returns: 1667 * 0 = success 1668 */ 1669 int 1670 qla2x00_loop_reset(scsi_qla_host_t *vha) 1671 { 1672 int ret; 1673 struct fc_port *fcport; 1674 struct qla_hw_data *ha = vha->hw; 1675 1676 if (IS_QLAFX00(ha)) { 1677 return qlafx00_loop_reset(vha); 1678 } 1679 1680 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1681 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1682 if (fcport->port_type != FCT_TARGET) 1683 continue; 1684 1685 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1686 if (ret != QLA_SUCCESS) { 1687 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1688 "Bus Reset failed: Reset=%d " 1689 "d_id=%x.\n", ret, fcport->d_id.b24); 1690 } 1691 } 1692 } 1693 1694 1695 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1696 atomic_set(&vha->loop_state, LOOP_DOWN); 1697 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1698 qla2x00_mark_all_devices_lost(vha, 0); 1699 ret = qla2x00_full_login_lip(vha); 1700 if (ret != QLA_SUCCESS) { 1701 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1702 "full_login_lip=%d.\n", ret); 1703 } 1704 } 1705 1706 if (ha->flags.enable_lip_reset) { 1707 ret = qla2x00_lip_reset(vha); 1708 if (ret != QLA_SUCCESS) 1709 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1710 "lip_reset failed (%d).\n", ret); 1711 } 1712 1713 /* Issue marker command only when we are going to start the I/O */ 1714 vha->marker_needed = 1; 1715 1716 return QLA_SUCCESS; 1717 } 1718 1719 static void 1720 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1721 { 1722 int cnt, status; 1723 unsigned long flags; 1724 srb_t *sp; 1725 scsi_qla_host_t *vha = qp->vha; 1726 struct qla_hw_data *ha = vha->hw; 1727 struct req_que *req; 1728 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1729 struct qla_tgt_cmd *cmd; 1730 uint8_t trace = 0; 1731 1732 if (!ha->req_q_map) 1733 return; 1734 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1735 req = qp->req; 1736 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1737 sp = req->outstanding_cmds[cnt]; 1738 if (sp) { 1739 req->outstanding_cmds[cnt] = NULL; 1740 if (sp->cmd_type == TYPE_SRB) { 1741 if (sp->type == SRB_NVME_CMD || 1742 sp->type == SRB_NVME_LS) { 1743 sp_get(sp); 1744 spin_unlock_irqrestore(qp->qp_lock_ptr, 1745 flags); 1746 qla_nvme_abort(ha, sp, res); 1747 spin_lock_irqsave(qp->qp_lock_ptr, 1748 flags); 1749 } else if (GET_CMD_SP(sp) && 1750 !ha->flags.eeh_busy && 1751 (!test_bit(ABORT_ISP_ACTIVE, 1752 &vha->dpc_flags)) && 1753 (sp->type == SRB_SCSI_CMD)) { 1754 /* 1755 * Don't abort commands in 1756 * adapter during EEH 1757 * recovery as it's not 1758 * accessible/responding. 1759 * 1760 * Get a reference to the sp 1761 * and drop the lock. The 1762 * reference ensures this 1763 * sp->done() call and not the 1764 * call in qla2xxx_eh_abort() 1765 * ends the SCSI command (with 1766 * result 'res'). 1767 */ 1768 sp_get(sp); 1769 spin_unlock_irqrestore(qp->qp_lock_ptr, 1770 flags); 1771 status = qla2xxx_eh_abort( 1772 GET_CMD_SP(sp)); 1773 spin_lock_irqsave(qp->qp_lock_ptr, 1774 flags); 1775 /* 1776 * Get rid of extra reference 1777 * if immediate exit from 1778 * ql2xxx_eh_abort 1779 */ 1780 if (status == FAILED && 1781 (qla2x00_isp_reg_stat(ha))) 1782 atomic_dec( 1783 &sp->ref_count); 1784 } 1785 sp->done(sp, res); 1786 } else { 1787 if (!vha->hw->tgt.tgt_ops || !tgt || 1788 qla_ini_mode_enabled(vha)) { 1789 if (!trace) 1790 ql_dbg(ql_dbg_tgt_mgt, 1791 vha, 0xf003, 1792 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1793 vha->dpc_flags); 1794 continue; 1795 } 1796 cmd = (struct qla_tgt_cmd *)sp; 1797 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1798 } 1799 } 1800 } 1801 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1802 } 1803 1804 void 1805 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1806 { 1807 int que; 1808 struct qla_hw_data *ha = vha->hw; 1809 1810 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1811 1812 for (que = 0; que < ha->max_qpairs; que++) { 1813 if (!ha->queue_pair_map[que]) 1814 continue; 1815 1816 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1817 } 1818 } 1819 1820 static int 1821 qla2xxx_slave_alloc(struct scsi_device *sdev) 1822 { 1823 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1824 1825 if (!rport || fc_remote_port_chkready(rport)) 1826 return -ENXIO; 1827 1828 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1829 1830 return 0; 1831 } 1832 1833 static int 1834 qla2xxx_slave_configure(struct scsi_device *sdev) 1835 { 1836 scsi_qla_host_t *vha = shost_priv(sdev->host); 1837 struct req_que *req = vha->req; 1838 1839 if (IS_T10_PI_CAPABLE(vha->hw)) 1840 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1841 1842 scsi_change_queue_depth(sdev, req->max_q_depth); 1843 return 0; 1844 } 1845 1846 static void 1847 qla2xxx_slave_destroy(struct scsi_device *sdev) 1848 { 1849 sdev->hostdata = NULL; 1850 } 1851 1852 /** 1853 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1854 * @ha: HA context 1855 * 1856 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1857 * supported addressing method. 1858 */ 1859 static void 1860 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1861 { 1862 /* Assume a 32bit DMA mask. */ 1863 ha->flags.enable_64bit_addressing = 0; 1864 1865 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1866 /* Any upper-dword bits set? */ 1867 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1868 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1869 /* Ok, a 64bit DMA mask is applicable. */ 1870 ha->flags.enable_64bit_addressing = 1; 1871 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1872 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1873 return; 1874 } 1875 } 1876 1877 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1878 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1879 } 1880 1881 static void 1882 qla2x00_enable_intrs(struct qla_hw_data *ha) 1883 { 1884 unsigned long flags = 0; 1885 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1886 1887 spin_lock_irqsave(&ha->hardware_lock, flags); 1888 ha->interrupts_on = 1; 1889 /* enable risc and host interrupts */ 1890 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1891 RD_REG_WORD(®->ictrl); 1892 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1893 1894 } 1895 1896 static void 1897 qla2x00_disable_intrs(struct qla_hw_data *ha) 1898 { 1899 unsigned long flags = 0; 1900 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1901 1902 spin_lock_irqsave(&ha->hardware_lock, flags); 1903 ha->interrupts_on = 0; 1904 /* disable risc and host interrupts */ 1905 WRT_REG_WORD(®->ictrl, 0); 1906 RD_REG_WORD(®->ictrl); 1907 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1908 } 1909 1910 static void 1911 qla24xx_enable_intrs(struct qla_hw_data *ha) 1912 { 1913 unsigned long flags = 0; 1914 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1915 1916 spin_lock_irqsave(&ha->hardware_lock, flags); 1917 ha->interrupts_on = 1; 1918 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1919 RD_REG_DWORD(®->ictrl); 1920 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1921 } 1922 1923 static void 1924 qla24xx_disable_intrs(struct qla_hw_data *ha) 1925 { 1926 unsigned long flags = 0; 1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1928 1929 if (IS_NOPOLLING_TYPE(ha)) 1930 return; 1931 spin_lock_irqsave(&ha->hardware_lock, flags); 1932 ha->interrupts_on = 0; 1933 WRT_REG_DWORD(®->ictrl, 0); 1934 RD_REG_DWORD(®->ictrl); 1935 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1936 } 1937 1938 static int 1939 qla2x00_iospace_config(struct qla_hw_data *ha) 1940 { 1941 resource_size_t pio; 1942 uint16_t msix; 1943 1944 if (pci_request_selected_regions(ha->pdev, ha->bars, 1945 QLA2XXX_DRIVER_NAME)) { 1946 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1947 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1948 pci_name(ha->pdev)); 1949 goto iospace_error_exit; 1950 } 1951 if (!(ha->bars & 1)) 1952 goto skip_pio; 1953 1954 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1955 pio = pci_resource_start(ha->pdev, 0); 1956 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1957 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1958 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1959 "Invalid pci I/O region size (%s).\n", 1960 pci_name(ha->pdev)); 1961 pio = 0; 1962 } 1963 } else { 1964 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1965 "Region #0 no a PIO resource (%s).\n", 1966 pci_name(ha->pdev)); 1967 pio = 0; 1968 } 1969 ha->pio_address = pio; 1970 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1971 "PIO address=%llu.\n", 1972 (unsigned long long)ha->pio_address); 1973 1974 skip_pio: 1975 /* Use MMIO operations for all accesses. */ 1976 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1978 "Region #1 not an MMIO resource (%s), aborting.\n", 1979 pci_name(ha->pdev)); 1980 goto iospace_error_exit; 1981 } 1982 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1983 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1984 "Invalid PCI mem region size (%s), aborting.\n", 1985 pci_name(ha->pdev)); 1986 goto iospace_error_exit; 1987 } 1988 1989 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1990 if (!ha->iobase) { 1991 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1992 "Cannot remap MMIO (%s), aborting.\n", 1993 pci_name(ha->pdev)); 1994 goto iospace_error_exit; 1995 } 1996 1997 /* Determine queue resources */ 1998 ha->max_req_queues = ha->max_rsp_queues = 1; 1999 ha->msix_count = QLA_BASE_VECTORS; 2000 if (!ql2xmqsupport || !ql2xnvmeenable || 2001 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2002 goto mqiobase_exit; 2003 2004 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2005 pci_resource_len(ha->pdev, 3)); 2006 if (ha->mqiobase) { 2007 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2008 "MQIO Base=%p.\n", ha->mqiobase); 2009 /* Read MSIX vector size of the board */ 2010 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2011 ha->msix_count = msix + 1; 2012 /* Max queues are bounded by available msix vectors */ 2013 /* MB interrupt uses 1 vector */ 2014 ha->max_req_queues = ha->msix_count - 1; 2015 ha->max_rsp_queues = ha->max_req_queues; 2016 /* Queue pairs is the max value minus the base queue pair */ 2017 ha->max_qpairs = ha->max_rsp_queues - 1; 2018 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2019 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2020 2021 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2022 "MSI-X vector count: %d.\n", ha->msix_count); 2023 } else 2024 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2025 "BAR 3 not enabled.\n"); 2026 2027 mqiobase_exit: 2028 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2029 "MSIX Count: %d.\n", ha->msix_count); 2030 return (0); 2031 2032 iospace_error_exit: 2033 return (-ENOMEM); 2034 } 2035 2036 2037 static int 2038 qla83xx_iospace_config(struct qla_hw_data *ha) 2039 { 2040 uint16_t msix; 2041 2042 if (pci_request_selected_regions(ha->pdev, ha->bars, 2043 QLA2XXX_DRIVER_NAME)) { 2044 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2045 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2046 pci_name(ha->pdev)); 2047 2048 goto iospace_error_exit; 2049 } 2050 2051 /* Use MMIO operations for all accesses. */ 2052 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2053 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2054 "Invalid pci I/O region size (%s).\n", 2055 pci_name(ha->pdev)); 2056 goto iospace_error_exit; 2057 } 2058 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2059 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2060 "Invalid PCI mem region size (%s), aborting\n", 2061 pci_name(ha->pdev)); 2062 goto iospace_error_exit; 2063 } 2064 2065 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2066 if (!ha->iobase) { 2067 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2068 "Cannot remap MMIO (%s), aborting.\n", 2069 pci_name(ha->pdev)); 2070 goto iospace_error_exit; 2071 } 2072 2073 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2074 /* 83XX 26XX always use MQ type access for queues 2075 * - mbar 2, a.k.a region 4 */ 2076 ha->max_req_queues = ha->max_rsp_queues = 1; 2077 ha->msix_count = QLA_BASE_VECTORS; 2078 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2079 pci_resource_len(ha->pdev, 4)); 2080 2081 if (!ha->mqiobase) { 2082 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2083 "BAR2/region4 not enabled\n"); 2084 goto mqiobase_exit; 2085 } 2086 2087 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2088 pci_resource_len(ha->pdev, 2)); 2089 if (ha->msixbase) { 2090 /* Read MSIX vector size of the board */ 2091 pci_read_config_word(ha->pdev, 2092 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2093 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2094 /* 2095 * By default, driver uses at least two msix vectors 2096 * (default & rspq) 2097 */ 2098 if (ql2xmqsupport || ql2xnvmeenable) { 2099 /* MB interrupt uses 1 vector */ 2100 ha->max_req_queues = ha->msix_count - 1; 2101 2102 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2103 if (QLA_TGT_MODE_ENABLED()) 2104 ha->max_req_queues--; 2105 2106 ha->max_rsp_queues = ha->max_req_queues; 2107 2108 /* Queue pairs is the max value minus 2109 * the base queue pair */ 2110 ha->max_qpairs = ha->max_req_queues - 1; 2111 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2112 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2113 } 2114 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2115 "MSI-X vector count: %d.\n", ha->msix_count); 2116 } else 2117 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2118 "BAR 1 not enabled.\n"); 2119 2120 mqiobase_exit: 2121 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2122 "MSIX Count: %d.\n", ha->msix_count); 2123 return 0; 2124 2125 iospace_error_exit: 2126 return -ENOMEM; 2127 } 2128 2129 static struct isp_operations qla2100_isp_ops = { 2130 .pci_config = qla2100_pci_config, 2131 .reset_chip = qla2x00_reset_chip, 2132 .chip_diag = qla2x00_chip_diag, 2133 .config_rings = qla2x00_config_rings, 2134 .reset_adapter = qla2x00_reset_adapter, 2135 .nvram_config = qla2x00_nvram_config, 2136 .update_fw_options = qla2x00_update_fw_options, 2137 .load_risc = qla2x00_load_risc, 2138 .pci_info_str = qla2x00_pci_info_str, 2139 .fw_version_str = qla2x00_fw_version_str, 2140 .intr_handler = qla2100_intr_handler, 2141 .enable_intrs = qla2x00_enable_intrs, 2142 .disable_intrs = qla2x00_disable_intrs, 2143 .abort_command = qla2x00_abort_command, 2144 .target_reset = qla2x00_abort_target, 2145 .lun_reset = qla2x00_lun_reset, 2146 .fabric_login = qla2x00_login_fabric, 2147 .fabric_logout = qla2x00_fabric_logout, 2148 .calc_req_entries = qla2x00_calc_iocbs_32, 2149 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2150 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2151 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2152 .read_nvram = qla2x00_read_nvram_data, 2153 .write_nvram = qla2x00_write_nvram_data, 2154 .fw_dump = qla2100_fw_dump, 2155 .beacon_on = NULL, 2156 .beacon_off = NULL, 2157 .beacon_blink = NULL, 2158 .read_optrom = qla2x00_read_optrom_data, 2159 .write_optrom = qla2x00_write_optrom_data, 2160 .get_flash_version = qla2x00_get_flash_version, 2161 .start_scsi = qla2x00_start_scsi, 2162 .start_scsi_mq = NULL, 2163 .abort_isp = qla2x00_abort_isp, 2164 .iospace_config = qla2x00_iospace_config, 2165 .initialize_adapter = qla2x00_initialize_adapter, 2166 }; 2167 2168 static struct isp_operations qla2300_isp_ops = { 2169 .pci_config = qla2300_pci_config, 2170 .reset_chip = qla2x00_reset_chip, 2171 .chip_diag = qla2x00_chip_diag, 2172 .config_rings = qla2x00_config_rings, 2173 .reset_adapter = qla2x00_reset_adapter, 2174 .nvram_config = qla2x00_nvram_config, 2175 .update_fw_options = qla2x00_update_fw_options, 2176 .load_risc = qla2x00_load_risc, 2177 .pci_info_str = qla2x00_pci_info_str, 2178 .fw_version_str = qla2x00_fw_version_str, 2179 .intr_handler = qla2300_intr_handler, 2180 .enable_intrs = qla2x00_enable_intrs, 2181 .disable_intrs = qla2x00_disable_intrs, 2182 .abort_command = qla2x00_abort_command, 2183 .target_reset = qla2x00_abort_target, 2184 .lun_reset = qla2x00_lun_reset, 2185 .fabric_login = qla2x00_login_fabric, 2186 .fabric_logout = qla2x00_fabric_logout, 2187 .calc_req_entries = qla2x00_calc_iocbs_32, 2188 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2189 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2190 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2191 .read_nvram = qla2x00_read_nvram_data, 2192 .write_nvram = qla2x00_write_nvram_data, 2193 .fw_dump = qla2300_fw_dump, 2194 .beacon_on = qla2x00_beacon_on, 2195 .beacon_off = qla2x00_beacon_off, 2196 .beacon_blink = qla2x00_beacon_blink, 2197 .read_optrom = qla2x00_read_optrom_data, 2198 .write_optrom = qla2x00_write_optrom_data, 2199 .get_flash_version = qla2x00_get_flash_version, 2200 .start_scsi = qla2x00_start_scsi, 2201 .start_scsi_mq = NULL, 2202 .abort_isp = qla2x00_abort_isp, 2203 .iospace_config = qla2x00_iospace_config, 2204 .initialize_adapter = qla2x00_initialize_adapter, 2205 }; 2206 2207 static struct isp_operations qla24xx_isp_ops = { 2208 .pci_config = qla24xx_pci_config, 2209 .reset_chip = qla24xx_reset_chip, 2210 .chip_diag = qla24xx_chip_diag, 2211 .config_rings = qla24xx_config_rings, 2212 .reset_adapter = qla24xx_reset_adapter, 2213 .nvram_config = qla24xx_nvram_config, 2214 .update_fw_options = qla24xx_update_fw_options, 2215 .load_risc = qla24xx_load_risc, 2216 .pci_info_str = qla24xx_pci_info_str, 2217 .fw_version_str = qla24xx_fw_version_str, 2218 .intr_handler = qla24xx_intr_handler, 2219 .enable_intrs = qla24xx_enable_intrs, 2220 .disable_intrs = qla24xx_disable_intrs, 2221 .abort_command = qla24xx_abort_command, 2222 .target_reset = qla24xx_abort_target, 2223 .lun_reset = qla24xx_lun_reset, 2224 .fabric_login = qla24xx_login_fabric, 2225 .fabric_logout = qla24xx_fabric_logout, 2226 .calc_req_entries = NULL, 2227 .build_iocbs = NULL, 2228 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2229 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2230 .read_nvram = qla24xx_read_nvram_data, 2231 .write_nvram = qla24xx_write_nvram_data, 2232 .fw_dump = qla24xx_fw_dump, 2233 .beacon_on = qla24xx_beacon_on, 2234 .beacon_off = qla24xx_beacon_off, 2235 .beacon_blink = qla24xx_beacon_blink, 2236 .read_optrom = qla24xx_read_optrom_data, 2237 .write_optrom = qla24xx_write_optrom_data, 2238 .get_flash_version = qla24xx_get_flash_version, 2239 .start_scsi = qla24xx_start_scsi, 2240 .start_scsi_mq = NULL, 2241 .abort_isp = qla2x00_abort_isp, 2242 .iospace_config = qla2x00_iospace_config, 2243 .initialize_adapter = qla2x00_initialize_adapter, 2244 }; 2245 2246 static struct isp_operations qla25xx_isp_ops = { 2247 .pci_config = qla25xx_pci_config, 2248 .reset_chip = qla24xx_reset_chip, 2249 .chip_diag = qla24xx_chip_diag, 2250 .config_rings = qla24xx_config_rings, 2251 .reset_adapter = qla24xx_reset_adapter, 2252 .nvram_config = qla24xx_nvram_config, 2253 .update_fw_options = qla24xx_update_fw_options, 2254 .load_risc = qla24xx_load_risc, 2255 .pci_info_str = qla24xx_pci_info_str, 2256 .fw_version_str = qla24xx_fw_version_str, 2257 .intr_handler = qla24xx_intr_handler, 2258 .enable_intrs = qla24xx_enable_intrs, 2259 .disable_intrs = qla24xx_disable_intrs, 2260 .abort_command = qla24xx_abort_command, 2261 .target_reset = qla24xx_abort_target, 2262 .lun_reset = qla24xx_lun_reset, 2263 .fabric_login = qla24xx_login_fabric, 2264 .fabric_logout = qla24xx_fabric_logout, 2265 .calc_req_entries = NULL, 2266 .build_iocbs = NULL, 2267 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2268 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2269 .read_nvram = qla25xx_read_nvram_data, 2270 .write_nvram = qla25xx_write_nvram_data, 2271 .fw_dump = qla25xx_fw_dump, 2272 .beacon_on = qla24xx_beacon_on, 2273 .beacon_off = qla24xx_beacon_off, 2274 .beacon_blink = qla24xx_beacon_blink, 2275 .read_optrom = qla25xx_read_optrom_data, 2276 .write_optrom = qla24xx_write_optrom_data, 2277 .get_flash_version = qla24xx_get_flash_version, 2278 .start_scsi = qla24xx_dif_start_scsi, 2279 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2280 .abort_isp = qla2x00_abort_isp, 2281 .iospace_config = qla2x00_iospace_config, 2282 .initialize_adapter = qla2x00_initialize_adapter, 2283 }; 2284 2285 static struct isp_operations qla81xx_isp_ops = { 2286 .pci_config = qla25xx_pci_config, 2287 .reset_chip = qla24xx_reset_chip, 2288 .chip_diag = qla24xx_chip_diag, 2289 .config_rings = qla24xx_config_rings, 2290 .reset_adapter = qla24xx_reset_adapter, 2291 .nvram_config = qla81xx_nvram_config, 2292 .update_fw_options = qla81xx_update_fw_options, 2293 .load_risc = qla81xx_load_risc, 2294 .pci_info_str = qla24xx_pci_info_str, 2295 .fw_version_str = qla24xx_fw_version_str, 2296 .intr_handler = qla24xx_intr_handler, 2297 .enable_intrs = qla24xx_enable_intrs, 2298 .disable_intrs = qla24xx_disable_intrs, 2299 .abort_command = qla24xx_abort_command, 2300 .target_reset = qla24xx_abort_target, 2301 .lun_reset = qla24xx_lun_reset, 2302 .fabric_login = qla24xx_login_fabric, 2303 .fabric_logout = qla24xx_fabric_logout, 2304 .calc_req_entries = NULL, 2305 .build_iocbs = NULL, 2306 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2307 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2308 .read_nvram = NULL, 2309 .write_nvram = NULL, 2310 .fw_dump = qla81xx_fw_dump, 2311 .beacon_on = qla24xx_beacon_on, 2312 .beacon_off = qla24xx_beacon_off, 2313 .beacon_blink = qla83xx_beacon_blink, 2314 .read_optrom = qla25xx_read_optrom_data, 2315 .write_optrom = qla24xx_write_optrom_data, 2316 .get_flash_version = qla24xx_get_flash_version, 2317 .start_scsi = qla24xx_dif_start_scsi, 2318 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2319 .abort_isp = qla2x00_abort_isp, 2320 .iospace_config = qla2x00_iospace_config, 2321 .initialize_adapter = qla2x00_initialize_adapter, 2322 }; 2323 2324 static struct isp_operations qla82xx_isp_ops = { 2325 .pci_config = qla82xx_pci_config, 2326 .reset_chip = qla82xx_reset_chip, 2327 .chip_diag = qla24xx_chip_diag, 2328 .config_rings = qla82xx_config_rings, 2329 .reset_adapter = qla24xx_reset_adapter, 2330 .nvram_config = qla81xx_nvram_config, 2331 .update_fw_options = qla24xx_update_fw_options, 2332 .load_risc = qla82xx_load_risc, 2333 .pci_info_str = qla24xx_pci_info_str, 2334 .fw_version_str = qla24xx_fw_version_str, 2335 .intr_handler = qla82xx_intr_handler, 2336 .enable_intrs = qla82xx_enable_intrs, 2337 .disable_intrs = qla82xx_disable_intrs, 2338 .abort_command = qla24xx_abort_command, 2339 .target_reset = qla24xx_abort_target, 2340 .lun_reset = qla24xx_lun_reset, 2341 .fabric_login = qla24xx_login_fabric, 2342 .fabric_logout = qla24xx_fabric_logout, 2343 .calc_req_entries = NULL, 2344 .build_iocbs = NULL, 2345 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2346 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2347 .read_nvram = qla24xx_read_nvram_data, 2348 .write_nvram = qla24xx_write_nvram_data, 2349 .fw_dump = qla82xx_fw_dump, 2350 .beacon_on = qla82xx_beacon_on, 2351 .beacon_off = qla82xx_beacon_off, 2352 .beacon_blink = NULL, 2353 .read_optrom = qla82xx_read_optrom_data, 2354 .write_optrom = qla82xx_write_optrom_data, 2355 .get_flash_version = qla82xx_get_flash_version, 2356 .start_scsi = qla82xx_start_scsi, 2357 .start_scsi_mq = NULL, 2358 .abort_isp = qla82xx_abort_isp, 2359 .iospace_config = qla82xx_iospace_config, 2360 .initialize_adapter = qla2x00_initialize_adapter, 2361 }; 2362 2363 static struct isp_operations qla8044_isp_ops = { 2364 .pci_config = qla82xx_pci_config, 2365 .reset_chip = qla82xx_reset_chip, 2366 .chip_diag = qla24xx_chip_diag, 2367 .config_rings = qla82xx_config_rings, 2368 .reset_adapter = qla24xx_reset_adapter, 2369 .nvram_config = qla81xx_nvram_config, 2370 .update_fw_options = qla24xx_update_fw_options, 2371 .load_risc = qla82xx_load_risc, 2372 .pci_info_str = qla24xx_pci_info_str, 2373 .fw_version_str = qla24xx_fw_version_str, 2374 .intr_handler = qla8044_intr_handler, 2375 .enable_intrs = qla82xx_enable_intrs, 2376 .disable_intrs = qla82xx_disable_intrs, 2377 .abort_command = qla24xx_abort_command, 2378 .target_reset = qla24xx_abort_target, 2379 .lun_reset = qla24xx_lun_reset, 2380 .fabric_login = qla24xx_login_fabric, 2381 .fabric_logout = qla24xx_fabric_logout, 2382 .calc_req_entries = NULL, 2383 .build_iocbs = NULL, 2384 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2385 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2386 .read_nvram = NULL, 2387 .write_nvram = NULL, 2388 .fw_dump = qla8044_fw_dump, 2389 .beacon_on = qla82xx_beacon_on, 2390 .beacon_off = qla82xx_beacon_off, 2391 .beacon_blink = NULL, 2392 .read_optrom = qla8044_read_optrom_data, 2393 .write_optrom = qla8044_write_optrom_data, 2394 .get_flash_version = qla82xx_get_flash_version, 2395 .start_scsi = qla82xx_start_scsi, 2396 .start_scsi_mq = NULL, 2397 .abort_isp = qla8044_abort_isp, 2398 .iospace_config = qla82xx_iospace_config, 2399 .initialize_adapter = qla2x00_initialize_adapter, 2400 }; 2401 2402 static struct isp_operations qla83xx_isp_ops = { 2403 .pci_config = qla25xx_pci_config, 2404 .reset_chip = qla24xx_reset_chip, 2405 .chip_diag = qla24xx_chip_diag, 2406 .config_rings = qla24xx_config_rings, 2407 .reset_adapter = qla24xx_reset_adapter, 2408 .nvram_config = qla81xx_nvram_config, 2409 .update_fw_options = qla81xx_update_fw_options, 2410 .load_risc = qla81xx_load_risc, 2411 .pci_info_str = qla24xx_pci_info_str, 2412 .fw_version_str = qla24xx_fw_version_str, 2413 .intr_handler = qla24xx_intr_handler, 2414 .enable_intrs = qla24xx_enable_intrs, 2415 .disable_intrs = qla24xx_disable_intrs, 2416 .abort_command = qla24xx_abort_command, 2417 .target_reset = qla24xx_abort_target, 2418 .lun_reset = qla24xx_lun_reset, 2419 .fabric_login = qla24xx_login_fabric, 2420 .fabric_logout = qla24xx_fabric_logout, 2421 .calc_req_entries = NULL, 2422 .build_iocbs = NULL, 2423 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2424 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2425 .read_nvram = NULL, 2426 .write_nvram = NULL, 2427 .fw_dump = qla83xx_fw_dump, 2428 .beacon_on = qla24xx_beacon_on, 2429 .beacon_off = qla24xx_beacon_off, 2430 .beacon_blink = qla83xx_beacon_blink, 2431 .read_optrom = qla25xx_read_optrom_data, 2432 .write_optrom = qla24xx_write_optrom_data, 2433 .get_flash_version = qla24xx_get_flash_version, 2434 .start_scsi = qla24xx_dif_start_scsi, 2435 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2436 .abort_isp = qla2x00_abort_isp, 2437 .iospace_config = qla83xx_iospace_config, 2438 .initialize_adapter = qla2x00_initialize_adapter, 2439 }; 2440 2441 static struct isp_operations qlafx00_isp_ops = { 2442 .pci_config = qlafx00_pci_config, 2443 .reset_chip = qlafx00_soft_reset, 2444 .chip_diag = qlafx00_chip_diag, 2445 .config_rings = qlafx00_config_rings, 2446 .reset_adapter = qlafx00_soft_reset, 2447 .nvram_config = NULL, 2448 .update_fw_options = NULL, 2449 .load_risc = NULL, 2450 .pci_info_str = qlafx00_pci_info_str, 2451 .fw_version_str = qlafx00_fw_version_str, 2452 .intr_handler = qlafx00_intr_handler, 2453 .enable_intrs = qlafx00_enable_intrs, 2454 .disable_intrs = qlafx00_disable_intrs, 2455 .abort_command = qla24xx_async_abort_command, 2456 .target_reset = qlafx00_abort_target, 2457 .lun_reset = qlafx00_lun_reset, 2458 .fabric_login = NULL, 2459 .fabric_logout = NULL, 2460 .calc_req_entries = NULL, 2461 .build_iocbs = NULL, 2462 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2463 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2464 .read_nvram = qla24xx_read_nvram_data, 2465 .write_nvram = qla24xx_write_nvram_data, 2466 .fw_dump = NULL, 2467 .beacon_on = qla24xx_beacon_on, 2468 .beacon_off = qla24xx_beacon_off, 2469 .beacon_blink = NULL, 2470 .read_optrom = qla24xx_read_optrom_data, 2471 .write_optrom = qla24xx_write_optrom_data, 2472 .get_flash_version = qla24xx_get_flash_version, 2473 .start_scsi = qlafx00_start_scsi, 2474 .start_scsi_mq = NULL, 2475 .abort_isp = qlafx00_abort_isp, 2476 .iospace_config = qlafx00_iospace_config, 2477 .initialize_adapter = qlafx00_initialize_adapter, 2478 }; 2479 2480 static struct isp_operations qla27xx_isp_ops = { 2481 .pci_config = qla25xx_pci_config, 2482 .reset_chip = qla24xx_reset_chip, 2483 .chip_diag = qla24xx_chip_diag, 2484 .config_rings = qla24xx_config_rings, 2485 .reset_adapter = qla24xx_reset_adapter, 2486 .nvram_config = qla81xx_nvram_config, 2487 .update_fw_options = qla81xx_update_fw_options, 2488 .load_risc = qla81xx_load_risc, 2489 .pci_info_str = qla24xx_pci_info_str, 2490 .fw_version_str = qla24xx_fw_version_str, 2491 .intr_handler = qla24xx_intr_handler, 2492 .enable_intrs = qla24xx_enable_intrs, 2493 .disable_intrs = qla24xx_disable_intrs, 2494 .abort_command = qla24xx_abort_command, 2495 .target_reset = qla24xx_abort_target, 2496 .lun_reset = qla24xx_lun_reset, 2497 .fabric_login = qla24xx_login_fabric, 2498 .fabric_logout = qla24xx_fabric_logout, 2499 .calc_req_entries = NULL, 2500 .build_iocbs = NULL, 2501 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2502 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2503 .read_nvram = NULL, 2504 .write_nvram = NULL, 2505 .fw_dump = qla27xx_fwdump, 2506 .beacon_on = qla24xx_beacon_on, 2507 .beacon_off = qla24xx_beacon_off, 2508 .beacon_blink = qla83xx_beacon_blink, 2509 .read_optrom = qla25xx_read_optrom_data, 2510 .write_optrom = qla24xx_write_optrom_data, 2511 .get_flash_version = qla24xx_get_flash_version, 2512 .start_scsi = qla24xx_dif_start_scsi, 2513 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2514 .abort_isp = qla2x00_abort_isp, 2515 .iospace_config = qla83xx_iospace_config, 2516 .initialize_adapter = qla2x00_initialize_adapter, 2517 }; 2518 2519 static inline void 2520 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2521 { 2522 ha->device_type = DT_EXTENDED_IDS; 2523 switch (ha->pdev->device) { 2524 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2525 ha->isp_type |= DT_ISP2100; 2526 ha->device_type &= ~DT_EXTENDED_IDS; 2527 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2528 break; 2529 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2530 ha->isp_type |= DT_ISP2200; 2531 ha->device_type &= ~DT_EXTENDED_IDS; 2532 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2533 break; 2534 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2535 ha->isp_type |= DT_ISP2300; 2536 ha->device_type |= DT_ZIO_SUPPORTED; 2537 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2538 break; 2539 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2540 ha->isp_type |= DT_ISP2312; 2541 ha->device_type |= DT_ZIO_SUPPORTED; 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2543 break; 2544 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2545 ha->isp_type |= DT_ISP2322; 2546 ha->device_type |= DT_ZIO_SUPPORTED; 2547 if (ha->pdev->subsystem_vendor == 0x1028 && 2548 ha->pdev->subsystem_device == 0x0170) 2549 ha->device_type |= DT_OEM_001; 2550 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2551 break; 2552 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2553 ha->isp_type |= DT_ISP6312; 2554 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2555 break; 2556 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2557 ha->isp_type |= DT_ISP6322; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2561 ha->isp_type |= DT_ISP2422; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->device_type |= DT_FWI2; 2564 ha->device_type |= DT_IIDMA; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2568 ha->isp_type |= DT_ISP2432; 2569 ha->device_type |= DT_ZIO_SUPPORTED; 2570 ha->device_type |= DT_FWI2; 2571 ha->device_type |= DT_IIDMA; 2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2573 break; 2574 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2575 ha->isp_type |= DT_ISP8432; 2576 ha->device_type |= DT_ZIO_SUPPORTED; 2577 ha->device_type |= DT_FWI2; 2578 ha->device_type |= DT_IIDMA; 2579 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2580 break; 2581 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2582 ha->isp_type |= DT_ISP5422; 2583 ha->device_type |= DT_FWI2; 2584 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2585 break; 2586 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2587 ha->isp_type |= DT_ISP5432; 2588 ha->device_type |= DT_FWI2; 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2590 break; 2591 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2592 ha->isp_type |= DT_ISP2532; 2593 ha->device_type |= DT_ZIO_SUPPORTED; 2594 ha->device_type |= DT_FWI2; 2595 ha->device_type |= DT_IIDMA; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2599 ha->isp_type |= DT_ISP8001; 2600 ha->device_type |= DT_ZIO_SUPPORTED; 2601 ha->device_type |= DT_FWI2; 2602 ha->device_type |= DT_IIDMA; 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2604 break; 2605 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2606 ha->isp_type |= DT_ISP8021; 2607 ha->device_type |= DT_ZIO_SUPPORTED; 2608 ha->device_type |= DT_FWI2; 2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2610 /* Initialize 82XX ISP flags */ 2611 qla82xx_init_flags(ha); 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2614 ha->isp_type |= DT_ISP8044; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2618 /* Initialize 82XX ISP flags */ 2619 qla82xx_init_flags(ha); 2620 break; 2621 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2622 ha->isp_type |= DT_ISP2031; 2623 ha->device_type |= DT_ZIO_SUPPORTED; 2624 ha->device_type |= DT_FWI2; 2625 ha->device_type |= DT_IIDMA; 2626 ha->device_type |= DT_T10_PI; 2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2628 break; 2629 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2630 ha->isp_type |= DT_ISP8031; 2631 ha->device_type |= DT_ZIO_SUPPORTED; 2632 ha->device_type |= DT_FWI2; 2633 ha->device_type |= DT_IIDMA; 2634 ha->device_type |= DT_T10_PI; 2635 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2636 break; 2637 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2638 ha->isp_type |= DT_ISPFX00; 2639 break; 2640 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2641 ha->isp_type |= DT_ISP2071; 2642 ha->device_type |= DT_ZIO_SUPPORTED; 2643 ha->device_type |= DT_FWI2; 2644 ha->device_type |= DT_IIDMA; 2645 ha->device_type |= DT_T10_PI; 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2647 break; 2648 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2649 ha->isp_type |= DT_ISP2271; 2650 ha->device_type |= DT_ZIO_SUPPORTED; 2651 ha->device_type |= DT_FWI2; 2652 ha->device_type |= DT_IIDMA; 2653 ha->device_type |= DT_T10_PI; 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2655 break; 2656 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2657 ha->isp_type |= DT_ISP2261; 2658 ha->device_type |= DT_ZIO_SUPPORTED; 2659 ha->device_type |= DT_FWI2; 2660 ha->device_type |= DT_IIDMA; 2661 ha->device_type |= DT_T10_PI; 2662 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2663 break; 2664 } 2665 2666 if (IS_QLA82XX(ha)) 2667 ha->port_no = ha->portnum & 1; 2668 else { 2669 /* Get adapter physical port no from interrupt pin register. */ 2670 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2671 if (IS_QLA27XX(ha)) 2672 ha->port_no--; 2673 else 2674 ha->port_no = !(ha->port_no & 1); 2675 } 2676 2677 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2678 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2679 ha->device_type, ha->port_no, ha->fw_srisc_address); 2680 } 2681 2682 static void 2683 qla2xxx_scan_start(struct Scsi_Host *shost) 2684 { 2685 scsi_qla_host_t *vha = shost_priv(shost); 2686 2687 if (vha->hw->flags.running_gold_fw) 2688 return; 2689 2690 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2691 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2692 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2693 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2694 } 2695 2696 static int 2697 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2698 { 2699 scsi_qla_host_t *vha = shost_priv(shost); 2700 2701 if (test_bit(UNLOADING, &vha->dpc_flags)) 2702 return 1; 2703 if (!vha->host) 2704 return 1; 2705 if (time > vha->hw->loop_reset_delay * HZ) 2706 return 1; 2707 2708 return atomic_read(&vha->loop_state) == LOOP_READY; 2709 } 2710 2711 static void qla2x00_iocb_work_fn(struct work_struct *work) 2712 { 2713 struct scsi_qla_host *vha = container_of(work, 2714 struct scsi_qla_host, iocb_work); 2715 struct qla_hw_data *ha = vha->hw; 2716 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2717 int i = 20; 2718 unsigned long flags; 2719 2720 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2721 return; 2722 2723 while (!list_empty(&vha->work_list) && i > 0) { 2724 qla2x00_do_work(vha); 2725 i--; 2726 } 2727 2728 spin_lock_irqsave(&vha->work_lock, flags); 2729 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2730 spin_unlock_irqrestore(&vha->work_lock, flags); 2731 } 2732 2733 /* 2734 * PCI driver interface 2735 */ 2736 static int 2737 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2738 { 2739 int ret = -ENODEV; 2740 struct Scsi_Host *host; 2741 scsi_qla_host_t *base_vha = NULL; 2742 struct qla_hw_data *ha; 2743 char pci_info[30]; 2744 char fw_str[30], wq_name[30]; 2745 struct scsi_host_template *sht; 2746 int bars, mem_only = 0; 2747 uint16_t req_length = 0, rsp_length = 0; 2748 struct req_que *req = NULL; 2749 struct rsp_que *rsp = NULL; 2750 int i; 2751 2752 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2753 sht = &qla2xxx_driver_template; 2754 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2763 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2764 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2765 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2766 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2769 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2770 mem_only = 1; 2771 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2772 "Mem only adapter.\n"); 2773 } 2774 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2775 "Bars=%d.\n", bars); 2776 2777 if (mem_only) { 2778 if (pci_enable_device_mem(pdev)) 2779 return ret; 2780 } else { 2781 if (pci_enable_device(pdev)) 2782 return ret; 2783 } 2784 2785 /* This may fail but that's ok */ 2786 pci_enable_pcie_error_reporting(pdev); 2787 2788 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2789 if (!ha) { 2790 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2791 "Unable to allocate memory for ha.\n"); 2792 goto disable_device; 2793 } 2794 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2795 "Memory allocated for ha=%p.\n", ha); 2796 ha->pdev = pdev; 2797 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2798 spin_lock_init(&ha->tgt.q_full_lock); 2799 spin_lock_init(&ha->tgt.sess_lock); 2800 spin_lock_init(&ha->tgt.atio_lock); 2801 2802 atomic_set(&ha->nvme_active_aen_cnt, 0); 2803 2804 /* Clear our data area */ 2805 ha->bars = bars; 2806 ha->mem_only = mem_only; 2807 spin_lock_init(&ha->hardware_lock); 2808 spin_lock_init(&ha->vport_slock); 2809 mutex_init(&ha->selflogin_lock); 2810 mutex_init(&ha->optrom_mutex); 2811 2812 /* Set ISP-type information. */ 2813 qla2x00_set_isp_flags(ha); 2814 2815 /* Set EEH reset type to fundamental if required by hba */ 2816 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2817 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2818 pdev->needs_freset = 1; 2819 2820 ha->prev_topology = 0; 2821 ha->init_cb_size = sizeof(init_cb_t); 2822 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2823 ha->optrom_size = OPTROM_SIZE_2300; 2824 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2825 2826 /* Assign ISP specific operations. */ 2827 if (IS_QLA2100(ha)) { 2828 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2829 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2830 req_length = REQUEST_ENTRY_CNT_2100; 2831 rsp_length = RESPONSE_ENTRY_CNT_2100; 2832 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2833 ha->gid_list_info_size = 4; 2834 ha->flash_conf_off = ~0; 2835 ha->flash_data_off = ~0; 2836 ha->nvram_conf_off = ~0; 2837 ha->nvram_data_off = ~0; 2838 ha->isp_ops = &qla2100_isp_ops; 2839 } else if (IS_QLA2200(ha)) { 2840 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2841 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2842 req_length = REQUEST_ENTRY_CNT_2200; 2843 rsp_length = RESPONSE_ENTRY_CNT_2100; 2844 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2845 ha->gid_list_info_size = 4; 2846 ha->flash_conf_off = ~0; 2847 ha->flash_data_off = ~0; 2848 ha->nvram_conf_off = ~0; 2849 ha->nvram_data_off = ~0; 2850 ha->isp_ops = &qla2100_isp_ops; 2851 } else if (IS_QLA23XX(ha)) { 2852 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2853 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2854 req_length = REQUEST_ENTRY_CNT_2200; 2855 rsp_length = RESPONSE_ENTRY_CNT_2300; 2856 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2857 ha->gid_list_info_size = 6; 2858 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2859 ha->optrom_size = OPTROM_SIZE_2322; 2860 ha->flash_conf_off = ~0; 2861 ha->flash_data_off = ~0; 2862 ha->nvram_conf_off = ~0; 2863 ha->nvram_data_off = ~0; 2864 ha->isp_ops = &qla2300_isp_ops; 2865 } else if (IS_QLA24XX_TYPE(ha)) { 2866 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2867 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2868 req_length = REQUEST_ENTRY_CNT_24XX; 2869 rsp_length = RESPONSE_ENTRY_CNT_2300; 2870 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2871 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2872 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2873 ha->gid_list_info_size = 8; 2874 ha->optrom_size = OPTROM_SIZE_24XX; 2875 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2876 ha->isp_ops = &qla24xx_isp_ops; 2877 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2878 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2879 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2880 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2881 } else if (IS_QLA25XX(ha)) { 2882 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2883 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2884 req_length = REQUEST_ENTRY_CNT_24XX; 2885 rsp_length = RESPONSE_ENTRY_CNT_2300; 2886 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2887 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2888 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2889 ha->gid_list_info_size = 8; 2890 ha->optrom_size = OPTROM_SIZE_25XX; 2891 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2892 ha->isp_ops = &qla25xx_isp_ops; 2893 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2894 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2895 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2896 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2897 } else if (IS_QLA81XX(ha)) { 2898 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2899 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2900 req_length = REQUEST_ENTRY_CNT_24XX; 2901 rsp_length = RESPONSE_ENTRY_CNT_2300; 2902 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2903 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2904 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2905 ha->gid_list_info_size = 8; 2906 ha->optrom_size = OPTROM_SIZE_81XX; 2907 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2908 ha->isp_ops = &qla81xx_isp_ops; 2909 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2910 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2911 ha->nvram_conf_off = ~0; 2912 ha->nvram_data_off = ~0; 2913 } else if (IS_QLA82XX(ha)) { 2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2915 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2916 req_length = REQUEST_ENTRY_CNT_82XX; 2917 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2918 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2919 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2920 ha->gid_list_info_size = 8; 2921 ha->optrom_size = OPTROM_SIZE_82XX; 2922 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2923 ha->isp_ops = &qla82xx_isp_ops; 2924 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2925 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2926 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2927 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2928 } else if (IS_QLA8044(ha)) { 2929 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2930 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2931 req_length = REQUEST_ENTRY_CNT_82XX; 2932 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2933 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2934 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2935 ha->gid_list_info_size = 8; 2936 ha->optrom_size = OPTROM_SIZE_83XX; 2937 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2938 ha->isp_ops = &qla8044_isp_ops; 2939 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2940 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2941 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2942 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2943 } else if (IS_QLA83XX(ha)) { 2944 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2946 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2947 req_length = REQUEST_ENTRY_CNT_83XX; 2948 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2949 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2950 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2951 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2952 ha->gid_list_info_size = 8; 2953 ha->optrom_size = OPTROM_SIZE_83XX; 2954 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2955 ha->isp_ops = &qla83xx_isp_ops; 2956 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2957 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2958 ha->nvram_conf_off = ~0; 2959 ha->nvram_data_off = ~0; 2960 } else if (IS_QLAFX00(ha)) { 2961 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2962 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2963 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2964 req_length = REQUEST_ENTRY_CNT_FX00; 2965 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2966 ha->isp_ops = &qlafx00_isp_ops; 2967 ha->port_down_retry_count = 30; /* default value */ 2968 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2969 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2970 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2971 ha->mr.fw_hbt_en = 1; 2972 ha->mr.host_info_resend = false; 2973 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2974 } else if (IS_QLA27XX(ha)) { 2975 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2976 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2977 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2978 req_length = REQUEST_ENTRY_CNT_83XX; 2979 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2980 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2981 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2982 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2983 ha->gid_list_info_size = 8; 2984 ha->optrom_size = OPTROM_SIZE_83XX; 2985 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2986 ha->isp_ops = &qla27xx_isp_ops; 2987 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2988 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2989 ha->nvram_conf_off = ~0; 2990 ha->nvram_data_off = ~0; 2991 } 2992 2993 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2994 "mbx_count=%d, req_length=%d, " 2995 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2996 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2997 "max_fibre_devices=%d.\n", 2998 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2999 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3000 ha->nvram_npiv_size, ha->max_fibre_devices); 3001 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3002 "isp_ops=%p, flash_conf_off=%d, " 3003 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3004 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3005 ha->nvram_conf_off, ha->nvram_data_off); 3006 3007 /* Configure PCI I/O space */ 3008 ret = ha->isp_ops->iospace_config(ha); 3009 if (ret) 3010 goto iospace_config_failed; 3011 3012 ql_log_pci(ql_log_info, pdev, 0x001d, 3013 "Found an ISP%04X irq %d iobase 0x%p.\n", 3014 pdev->device, pdev->irq, ha->iobase); 3015 mutex_init(&ha->vport_lock); 3016 mutex_init(&ha->mq_lock); 3017 init_completion(&ha->mbx_cmd_comp); 3018 complete(&ha->mbx_cmd_comp); 3019 init_completion(&ha->mbx_intr_comp); 3020 init_completion(&ha->dcbx_comp); 3021 init_completion(&ha->lb_portup_comp); 3022 3023 set_bit(0, (unsigned long *) ha->vp_idx_map); 3024 3025 qla2x00_config_dma_addressing(ha); 3026 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3027 "64 Bit addressing is %s.\n", 3028 ha->flags.enable_64bit_addressing ? "enable" : 3029 "disable"); 3030 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3031 if (ret) { 3032 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3033 "Failed to allocate memory for adapter, aborting.\n"); 3034 3035 goto probe_hw_failed; 3036 } 3037 3038 req->max_q_depth = MAX_Q_DEPTH; 3039 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3040 req->max_q_depth = ql2xmaxqdepth; 3041 3042 3043 base_vha = qla2x00_create_host(sht, ha); 3044 if (!base_vha) { 3045 ret = -ENOMEM; 3046 goto probe_hw_failed; 3047 } 3048 3049 pci_set_drvdata(pdev, base_vha); 3050 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3051 3052 host = base_vha->host; 3053 base_vha->req = req; 3054 if (IS_QLA2XXX_MIDTYPE(ha)) 3055 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER; 3056 else 3057 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3058 base_vha->vp_idx; 3059 3060 /* Setup fcport template structure. */ 3061 ha->mr.fcport.vha = base_vha; 3062 ha->mr.fcport.port_type = FCT_UNKNOWN; 3063 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3064 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3065 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3066 ha->mr.fcport.scan_state = 1; 3067 3068 /* Set the SG table size based on ISP type */ 3069 if (!IS_FWI2_CAPABLE(ha)) { 3070 if (IS_QLA2100(ha)) 3071 host->sg_tablesize = 32; 3072 } else { 3073 if (!IS_QLA82XX(ha)) 3074 host->sg_tablesize = QLA_SG_ALL; 3075 } 3076 host->max_id = ha->max_fibre_devices; 3077 host->cmd_per_lun = 3; 3078 host->unique_id = host->host_no; 3079 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3080 host->max_cmd_len = 32; 3081 else 3082 host->max_cmd_len = MAX_CMDSZ; 3083 host->max_channel = MAX_BUSES - 1; 3084 /* Older HBAs support only 16-bit LUNs */ 3085 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3086 ql2xmaxlun > 0xffff) 3087 host->max_lun = 0xffff; 3088 else 3089 host->max_lun = ql2xmaxlun; 3090 host->transportt = qla2xxx_transport_template; 3091 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3092 3093 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3094 "max_id=%d this_id=%d " 3095 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3096 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3097 host->this_id, host->cmd_per_lun, host->unique_id, 3098 host->max_cmd_len, host->max_channel, host->max_lun, 3099 host->transportt, sht->vendor_id); 3100 3101 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3102 3103 /* Set up the irqs */ 3104 ret = qla2x00_request_irqs(ha, rsp); 3105 if (ret) 3106 goto probe_failed; 3107 3108 /* Alloc arrays of request and response ring ptrs */ 3109 if (qla2x00_alloc_queues(ha, req, rsp)) { 3110 ql_log(ql_log_fatal, base_vha, 0x003d, 3111 "Failed to allocate memory for queue pointers..." 3112 "aborting.\n"); 3113 goto probe_failed; 3114 } 3115 3116 if (ha->mqenable && shost_use_blk_mq(host)) { 3117 /* number of hardware queues supported by blk/scsi-mq*/ 3118 host->nr_hw_queues = ha->max_qpairs; 3119 3120 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3121 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3122 } else { 3123 if (ql2xnvmeenable) { 3124 host->nr_hw_queues = ha->max_qpairs; 3125 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3126 "FC-NVMe support is enabled, HW queues=%d\n", 3127 host->nr_hw_queues); 3128 } else { 3129 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3130 "blk/scsi-mq disabled.\n"); 3131 } 3132 } 3133 3134 qlt_probe_one_stage1(base_vha, ha); 3135 3136 pci_save_state(pdev); 3137 3138 /* Assign back pointers */ 3139 rsp->req = req; 3140 req->rsp = rsp; 3141 3142 if (IS_QLAFX00(ha)) { 3143 ha->rsp_q_map[0] = rsp; 3144 ha->req_q_map[0] = req; 3145 set_bit(0, ha->req_qid_map); 3146 set_bit(0, ha->rsp_qid_map); 3147 } 3148 3149 /* FWI2-capable only. */ 3150 req->req_q_in = &ha->iobase->isp24.req_q_in; 3151 req->req_q_out = &ha->iobase->isp24.req_q_out; 3152 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3153 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3154 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3155 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3156 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3157 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3158 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3159 } 3160 3161 if (IS_QLAFX00(ha)) { 3162 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3163 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3164 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3165 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3166 } 3167 3168 if (IS_P3P_TYPE(ha)) { 3169 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3170 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3171 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3172 } 3173 3174 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3175 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3176 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3177 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3178 "req->req_q_in=%p req->req_q_out=%p " 3179 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3180 req->req_q_in, req->req_q_out, 3181 rsp->rsp_q_in, rsp->rsp_q_out); 3182 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3183 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3184 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3185 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3186 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3187 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3188 3189 if (ha->isp_ops->initialize_adapter(base_vha)) { 3190 ql_log(ql_log_fatal, base_vha, 0x00d6, 3191 "Failed to initialize adapter - Adapter flags %x.\n", 3192 base_vha->device_flags); 3193 3194 if (IS_QLA82XX(ha)) { 3195 qla82xx_idc_lock(ha); 3196 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3197 QLA8XXX_DEV_FAILED); 3198 qla82xx_idc_unlock(ha); 3199 ql_log(ql_log_fatal, base_vha, 0x00d7, 3200 "HW State: FAILED.\n"); 3201 } else if (IS_QLA8044(ha)) { 3202 qla8044_idc_lock(ha); 3203 qla8044_wr_direct(base_vha, 3204 QLA8044_CRB_DEV_STATE_INDEX, 3205 QLA8XXX_DEV_FAILED); 3206 qla8044_idc_unlock(ha); 3207 ql_log(ql_log_fatal, base_vha, 0x0150, 3208 "HW State: FAILED.\n"); 3209 } 3210 3211 ret = -ENODEV; 3212 goto probe_failed; 3213 } 3214 3215 if (IS_QLAFX00(ha)) 3216 host->can_queue = QLAFX00_MAX_CANQUEUE; 3217 else 3218 host->can_queue = req->num_outstanding_cmds - 10; 3219 3220 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3221 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3222 host->can_queue, base_vha->req, 3223 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3224 3225 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3226 3227 if (ha->mqenable) { 3228 bool mq = false; 3229 bool startit = false; 3230 3231 if (QLA_TGT_MODE_ENABLED()) { 3232 mq = true; 3233 startit = false; 3234 } 3235 3236 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3237 shost_use_blk_mq(host)) { 3238 mq = true; 3239 startit = true; 3240 } 3241 3242 if (mq) { 3243 /* Create start of day qpairs for Block MQ */ 3244 for (i = 0; i < ha->max_qpairs; i++) 3245 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3246 } 3247 } 3248 3249 if (ha->flags.running_gold_fw) 3250 goto skip_dpc; 3251 3252 /* 3253 * Startup the kernel thread for this host adapter 3254 */ 3255 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3256 "%s_dpc", base_vha->host_str); 3257 if (IS_ERR(ha->dpc_thread)) { 3258 ql_log(ql_log_fatal, base_vha, 0x00ed, 3259 "Failed to start DPC thread.\n"); 3260 ret = PTR_ERR(ha->dpc_thread); 3261 ha->dpc_thread = NULL; 3262 goto probe_failed; 3263 } 3264 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3265 "DPC thread started successfully.\n"); 3266 3267 /* 3268 * If we're not coming up in initiator mode, we might sit for 3269 * a while without waking up the dpc thread, which leads to a 3270 * stuck process warning. So just kick the dpc once here and 3271 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3272 */ 3273 qla2xxx_wake_dpc(base_vha); 3274 3275 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3276 3277 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3278 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3279 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3280 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3281 3282 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3283 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3284 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3285 INIT_WORK(&ha->idc_state_handler, 3286 qla83xx_idc_state_handler_work); 3287 INIT_WORK(&ha->nic_core_unrecoverable, 3288 qla83xx_nic_core_unrecoverable_work); 3289 } 3290 3291 skip_dpc: 3292 list_add_tail(&base_vha->list, &ha->vp_list); 3293 base_vha->host->irq = ha->pdev->irq; 3294 3295 /* Initialized the timer */ 3296 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3297 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3298 "Started qla2x00_timer with " 3299 "interval=%d.\n", WATCH_INTERVAL); 3300 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3301 "Detected hba at address=%p.\n", 3302 ha); 3303 3304 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3305 if (ha->fw_attributes & BIT_4) { 3306 int prot = 0, guard; 3307 base_vha->flags.difdix_supported = 1; 3308 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3309 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3310 if (ql2xenabledif == 1) 3311 prot = SHOST_DIX_TYPE0_PROTECTION; 3312 scsi_host_set_prot(host, 3313 prot | SHOST_DIF_TYPE1_PROTECTION 3314 | SHOST_DIF_TYPE2_PROTECTION 3315 | SHOST_DIF_TYPE3_PROTECTION 3316 | SHOST_DIX_TYPE1_PROTECTION 3317 | SHOST_DIX_TYPE2_PROTECTION 3318 | SHOST_DIX_TYPE3_PROTECTION); 3319 3320 guard = SHOST_DIX_GUARD_CRC; 3321 3322 if (IS_PI_IPGUARD_CAPABLE(ha) && 3323 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3324 guard |= SHOST_DIX_GUARD_IP; 3325 3326 scsi_host_set_guard(host, guard); 3327 } else 3328 base_vha->flags.difdix_supported = 0; 3329 } 3330 3331 ha->isp_ops->enable_intrs(ha); 3332 3333 if (IS_QLAFX00(ha)) { 3334 ret = qlafx00_fx_disc(base_vha, 3335 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3336 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3337 QLA_SG_ALL : 128; 3338 } 3339 3340 ret = scsi_add_host(host, &pdev->dev); 3341 if (ret) 3342 goto probe_failed; 3343 3344 base_vha->flags.init_done = 1; 3345 base_vha->flags.online = 1; 3346 ha->prev_minidump_failed = 0; 3347 3348 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3349 "Init done and hba is online.\n"); 3350 3351 if (qla_ini_mode_enabled(base_vha) || 3352 qla_dual_mode_enabled(base_vha)) 3353 scsi_scan_host(host); 3354 else 3355 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3356 "skipping scsi_scan_host() for non-initiator port\n"); 3357 3358 qla2x00_alloc_sysfs_attr(base_vha); 3359 3360 if (IS_QLAFX00(ha)) { 3361 ret = qlafx00_fx_disc(base_vha, 3362 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3363 3364 /* Register system information */ 3365 ret = qlafx00_fx_disc(base_vha, 3366 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3367 } 3368 3369 qla2x00_init_host_attr(base_vha); 3370 3371 qla2x00_dfs_setup(base_vha); 3372 3373 ql_log(ql_log_info, base_vha, 0x00fb, 3374 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3375 ql_log(ql_log_info, base_vha, 0x00fc, 3376 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3377 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3378 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3379 base_vha->host_no, 3380 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3381 3382 qlt_add_target(ha, base_vha); 3383 3384 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3385 3386 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3387 return -ENODEV; 3388 3389 if (ha->flags.detected_lr_sfp) { 3390 ql_log(ql_log_info, base_vha, 0xffff, 3391 "Reset chip to pick up LR SFP setting\n"); 3392 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3393 qla2xxx_wake_dpc(base_vha); 3394 } 3395 3396 return 0; 3397 3398 probe_failed: 3399 if (base_vha->timer_active) 3400 qla2x00_stop_timer(base_vha); 3401 base_vha->flags.online = 0; 3402 if (ha->dpc_thread) { 3403 struct task_struct *t = ha->dpc_thread; 3404 3405 ha->dpc_thread = NULL; 3406 kthread_stop(t); 3407 } 3408 3409 qla2x00_free_device(base_vha); 3410 3411 scsi_host_put(base_vha->host); 3412 3413 probe_hw_failed: 3414 qla2x00_mem_free(ha); 3415 qla2x00_free_req_que(ha, req); 3416 qla2x00_free_rsp_que(ha, rsp); 3417 qla2x00_clear_drv_active(ha); 3418 3419 iospace_config_failed: 3420 if (IS_P3P_TYPE(ha)) { 3421 if (!ha->nx_pcibase) 3422 iounmap((device_reg_t *)ha->nx_pcibase); 3423 if (!ql2xdbwr) 3424 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3425 } else { 3426 if (ha->iobase) 3427 iounmap(ha->iobase); 3428 if (ha->cregbase) 3429 iounmap(ha->cregbase); 3430 } 3431 pci_release_selected_regions(ha->pdev, ha->bars); 3432 kfree(ha); 3433 3434 disable_device: 3435 pci_disable_device(pdev); 3436 return ret; 3437 } 3438 3439 static void 3440 qla2x00_shutdown(struct pci_dev *pdev) 3441 { 3442 scsi_qla_host_t *vha; 3443 struct qla_hw_data *ha; 3444 3445 vha = pci_get_drvdata(pdev); 3446 ha = vha->hw; 3447 3448 ql_log(ql_log_info, vha, 0xfffa, 3449 "Adapter shutdown\n"); 3450 3451 /* 3452 * Prevent future board_disable and wait 3453 * until any pending board_disable has completed. 3454 */ 3455 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3456 cancel_work_sync(&ha->board_disable); 3457 3458 if (!atomic_read(&pdev->enable_cnt)) 3459 return; 3460 3461 /* Notify ISPFX00 firmware */ 3462 if (IS_QLAFX00(ha)) 3463 qlafx00_driver_shutdown(vha, 20); 3464 3465 /* Turn-off FCE trace */ 3466 if (ha->flags.fce_enabled) { 3467 qla2x00_disable_fce_trace(vha, NULL, NULL); 3468 ha->flags.fce_enabled = 0; 3469 } 3470 3471 /* Turn-off EFT trace */ 3472 if (ha->eft) 3473 qla2x00_disable_eft_trace(vha); 3474 3475 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3476 if (ha->flags.fw_started) 3477 qla2x00_abort_isp_cleanup(vha); 3478 } else { 3479 /* Stop currently executing firmware. */ 3480 qla2x00_try_to_stop_firmware(vha); 3481 } 3482 3483 /* Turn adapter off line */ 3484 vha->flags.online = 0; 3485 3486 /* turn-off interrupts on the card */ 3487 if (ha->interrupts_on) { 3488 vha->flags.init_done = 0; 3489 ha->isp_ops->disable_intrs(ha); 3490 } 3491 3492 qla2x00_free_irqs(vha); 3493 3494 qla2x00_free_fw_dump(ha); 3495 3496 pci_disable_device(pdev); 3497 ql_log(ql_log_info, vha, 0xfffe, 3498 "Adapter shutdown successfully.\n"); 3499 } 3500 3501 /* Deletes all the virtual ports for a given ha */ 3502 static void 3503 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3504 { 3505 scsi_qla_host_t *vha; 3506 unsigned long flags; 3507 3508 mutex_lock(&ha->vport_lock); 3509 while (ha->cur_vport_count) { 3510 spin_lock_irqsave(&ha->vport_slock, flags); 3511 3512 BUG_ON(base_vha->list.next == &ha->vp_list); 3513 /* This assumes first entry in ha->vp_list is always base vha */ 3514 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3515 scsi_host_get(vha->host); 3516 3517 spin_unlock_irqrestore(&ha->vport_slock, flags); 3518 mutex_unlock(&ha->vport_lock); 3519 3520 fc_vport_terminate(vha->fc_vport); 3521 scsi_host_put(vha->host); 3522 3523 mutex_lock(&ha->vport_lock); 3524 } 3525 mutex_unlock(&ha->vport_lock); 3526 } 3527 3528 /* Stops all deferred work threads */ 3529 static void 3530 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3531 { 3532 /* Cancel all work and destroy DPC workqueues */ 3533 if (ha->dpc_lp_wq) { 3534 cancel_work_sync(&ha->idc_aen); 3535 destroy_workqueue(ha->dpc_lp_wq); 3536 ha->dpc_lp_wq = NULL; 3537 } 3538 3539 if (ha->dpc_hp_wq) { 3540 cancel_work_sync(&ha->nic_core_reset); 3541 cancel_work_sync(&ha->idc_state_handler); 3542 cancel_work_sync(&ha->nic_core_unrecoverable); 3543 destroy_workqueue(ha->dpc_hp_wq); 3544 ha->dpc_hp_wq = NULL; 3545 } 3546 3547 /* Kill the kernel thread for this host */ 3548 if (ha->dpc_thread) { 3549 struct task_struct *t = ha->dpc_thread; 3550 3551 /* 3552 * qla2xxx_wake_dpc checks for ->dpc_thread 3553 * so we need to zero it out. 3554 */ 3555 ha->dpc_thread = NULL; 3556 kthread_stop(t); 3557 } 3558 } 3559 3560 static void 3561 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3562 { 3563 if (IS_QLA82XX(ha)) { 3564 3565 iounmap((device_reg_t *)ha->nx_pcibase); 3566 if (!ql2xdbwr) 3567 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3568 } else { 3569 if (ha->iobase) 3570 iounmap(ha->iobase); 3571 3572 if (ha->cregbase) 3573 iounmap(ha->cregbase); 3574 3575 if (ha->mqiobase) 3576 iounmap(ha->mqiobase); 3577 3578 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3579 iounmap(ha->msixbase); 3580 } 3581 } 3582 3583 static void 3584 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3585 { 3586 if (IS_QLA8044(ha)) { 3587 qla8044_idc_lock(ha); 3588 qla8044_clear_drv_active(ha); 3589 qla8044_idc_unlock(ha); 3590 } else if (IS_QLA82XX(ha)) { 3591 qla82xx_idc_lock(ha); 3592 qla82xx_clear_drv_active(ha); 3593 qla82xx_idc_unlock(ha); 3594 } 3595 } 3596 3597 static void 3598 qla2x00_remove_one(struct pci_dev *pdev) 3599 { 3600 scsi_qla_host_t *base_vha; 3601 struct qla_hw_data *ha; 3602 3603 base_vha = pci_get_drvdata(pdev); 3604 ha = base_vha->hw; 3605 3606 /* Indicate device removal to prevent future board_disable and wait 3607 * until any pending board_disable has completed. */ 3608 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3609 cancel_work_sync(&ha->board_disable); 3610 3611 /* 3612 * If the PCI device is disabled then there was a PCI-disconnect and 3613 * qla2x00_disable_board_on_pci_error has taken care of most of the 3614 * resources. 3615 */ 3616 if (!atomic_read(&pdev->enable_cnt)) { 3617 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3618 base_vha->gnl.l, base_vha->gnl.ldma); 3619 3620 scsi_host_put(base_vha->host); 3621 kfree(ha); 3622 pci_set_drvdata(pdev, NULL); 3623 return; 3624 } 3625 qla2x00_wait_for_hba_ready(base_vha); 3626 3627 qla2x00_wait_for_sess_deletion(base_vha); 3628 3629 /* 3630 * if UNLOAD flag is already set, then continue unload, 3631 * where it was set first. 3632 */ 3633 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3634 return; 3635 3636 set_bit(UNLOADING, &base_vha->dpc_flags); 3637 3638 qla_nvme_delete(base_vha); 3639 3640 dma_free_coherent(&ha->pdev->dev, 3641 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3642 3643 vfree(base_vha->scan.l); 3644 3645 if (IS_QLAFX00(ha)) 3646 qlafx00_driver_shutdown(base_vha, 20); 3647 3648 qla2x00_delete_all_vps(ha, base_vha); 3649 3650 if (IS_QLA8031(ha)) { 3651 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3652 "Clearing fcoe driver presence.\n"); 3653 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3654 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3655 "Error while clearing DRV-Presence.\n"); 3656 } 3657 3658 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3659 3660 qla2x00_dfs_remove(base_vha); 3661 3662 qla84xx_put_chip(base_vha); 3663 3664 /* Disable timer */ 3665 if (base_vha->timer_active) 3666 qla2x00_stop_timer(base_vha); 3667 3668 base_vha->flags.online = 0; 3669 3670 /* free DMA memory */ 3671 if (ha->exlogin_buf) 3672 qla2x00_free_exlogin_buffer(ha); 3673 3674 /* free DMA memory */ 3675 if (ha->exchoffld_buf) 3676 qla2x00_free_exchoffld_buffer(ha); 3677 3678 qla2x00_destroy_deferred_work(ha); 3679 3680 qlt_remove_target(ha, base_vha); 3681 3682 qla2x00_free_sysfs_attr(base_vha, true); 3683 3684 fc_remove_host(base_vha->host); 3685 qlt_remove_target_resources(ha); 3686 3687 scsi_remove_host(base_vha->host); 3688 3689 qla2x00_free_device(base_vha); 3690 3691 qla2x00_clear_drv_active(ha); 3692 3693 scsi_host_put(base_vha->host); 3694 3695 qla2x00_unmap_iobases(ha); 3696 3697 pci_release_selected_regions(ha->pdev, ha->bars); 3698 kfree(ha); 3699 3700 pci_disable_pcie_error_reporting(pdev); 3701 3702 pci_disable_device(pdev); 3703 } 3704 3705 static void 3706 qla2x00_free_device(scsi_qla_host_t *vha) 3707 { 3708 struct qla_hw_data *ha = vha->hw; 3709 3710 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3711 3712 /* Disable timer */ 3713 if (vha->timer_active) 3714 qla2x00_stop_timer(vha); 3715 3716 qla25xx_delete_queues(vha); 3717 3718 if (ha->flags.fce_enabled) 3719 qla2x00_disable_fce_trace(vha, NULL, NULL); 3720 3721 if (ha->eft) 3722 qla2x00_disable_eft_trace(vha); 3723 3724 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3725 if (ha->flags.fw_started) 3726 qla2x00_abort_isp_cleanup(vha); 3727 } else { 3728 if (ha->flags.fw_started) { 3729 /* Stop currently executing firmware. */ 3730 qla2x00_try_to_stop_firmware(vha); 3731 ha->flags.fw_started = 0; 3732 } 3733 } 3734 3735 vha->flags.online = 0; 3736 3737 /* turn-off interrupts on the card */ 3738 if (ha->interrupts_on) { 3739 vha->flags.init_done = 0; 3740 ha->isp_ops->disable_intrs(ha); 3741 } 3742 3743 qla2x00_free_fcports(vha); 3744 3745 qla2x00_free_irqs(vha); 3746 3747 /* Flush the work queue and remove it */ 3748 if (ha->wq) { 3749 flush_workqueue(ha->wq); 3750 destroy_workqueue(ha->wq); 3751 ha->wq = NULL; 3752 } 3753 3754 3755 qla2x00_mem_free(ha); 3756 3757 qla82xx_md_free(vha); 3758 3759 qla2x00_free_queues(ha); 3760 } 3761 3762 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3763 { 3764 fc_port_t *fcport, *tfcport; 3765 3766 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3767 list_del(&fcport->list); 3768 qla2x00_clear_loop_id(fcport); 3769 kfree(fcport); 3770 } 3771 } 3772 3773 static inline void 3774 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3775 int defer) 3776 { 3777 struct fc_rport *rport; 3778 scsi_qla_host_t *base_vha; 3779 unsigned long flags; 3780 3781 if (!fcport->rport) 3782 return; 3783 3784 rport = fcport->rport; 3785 if (defer) { 3786 base_vha = pci_get_drvdata(vha->hw->pdev); 3787 spin_lock_irqsave(vha->host->host_lock, flags); 3788 fcport->drport = rport; 3789 spin_unlock_irqrestore(vha->host->host_lock, flags); 3790 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3791 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3792 qla2xxx_wake_dpc(base_vha); 3793 } else { 3794 int now; 3795 if (rport) { 3796 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3797 "%s %8phN. rport %p roles %x\n", 3798 __func__, fcport->port_name, rport, 3799 rport->roles); 3800 fc_remote_port_delete(rport); 3801 } 3802 qlt_do_generation_tick(vha, &now); 3803 } 3804 } 3805 3806 /* 3807 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3808 * 3809 * Input: ha = adapter block pointer. fcport = port structure pointer. 3810 * 3811 * Return: None. 3812 * 3813 * Context: 3814 */ 3815 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3816 int do_login, int defer) 3817 { 3818 if (IS_QLAFX00(vha->hw)) { 3819 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3820 qla2x00_schedule_rport_del(vha, fcport, defer); 3821 return; 3822 } 3823 3824 if (atomic_read(&fcport->state) == FCS_ONLINE && 3825 vha->vp_idx == fcport->vha->vp_idx) { 3826 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3827 qla2x00_schedule_rport_del(vha, fcport, defer); 3828 } 3829 /* 3830 * We may need to retry the login, so don't change the state of the 3831 * port but do the retries. 3832 */ 3833 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3834 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3835 3836 if (!do_login) 3837 return; 3838 3839 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3840 3841 if (fcport->login_retry == 0) { 3842 fcport->login_retry = vha->hw->login_retry_count; 3843 3844 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3845 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3846 fcport->port_name, fcport->loop_id, fcport->login_retry); 3847 } 3848 } 3849 3850 /* 3851 * qla2x00_mark_all_devices_lost 3852 * Updates fcport state when device goes offline. 3853 * 3854 * Input: 3855 * ha = adapter block pointer. 3856 * fcport = port structure pointer. 3857 * 3858 * Return: 3859 * None. 3860 * 3861 * Context: 3862 */ 3863 void 3864 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3865 { 3866 fc_port_t *fcport; 3867 3868 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3869 "Mark all dev lost\n"); 3870 3871 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3872 fcport->scan_state = 0; 3873 qlt_schedule_sess_for_deletion(fcport); 3874 3875 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3876 continue; 3877 3878 /* 3879 * No point in marking the device as lost, if the device is 3880 * already DEAD. 3881 */ 3882 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3883 continue; 3884 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3885 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3886 if (defer) 3887 qla2x00_schedule_rport_del(vha, fcport, defer); 3888 else if (vha->vp_idx == fcport->vha->vp_idx) 3889 qla2x00_schedule_rport_del(vha, fcport, defer); 3890 } 3891 } 3892 } 3893 3894 /* 3895 * qla2x00_mem_alloc 3896 * Allocates adapter memory. 3897 * 3898 * Returns: 3899 * 0 = success. 3900 * !0 = failure. 3901 */ 3902 static int 3903 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3904 struct req_que **req, struct rsp_que **rsp) 3905 { 3906 char name[16]; 3907 3908 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3909 &ha->init_cb_dma, GFP_KERNEL); 3910 if (!ha->init_cb) 3911 goto fail; 3912 3913 if (qlt_mem_alloc(ha) < 0) 3914 goto fail_free_init_cb; 3915 3916 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3917 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3918 if (!ha->gid_list) 3919 goto fail_free_tgt_mem; 3920 3921 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3922 if (!ha->srb_mempool) 3923 goto fail_free_gid_list; 3924 3925 if (IS_P3P_TYPE(ha)) { 3926 /* Allocate cache for CT6 Ctx. */ 3927 if (!ctx_cachep) { 3928 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3929 sizeof(struct ct6_dsd), 0, 3930 SLAB_HWCACHE_ALIGN, NULL); 3931 if (!ctx_cachep) 3932 goto fail_free_srb_mempool; 3933 } 3934 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3935 ctx_cachep); 3936 if (!ha->ctx_mempool) 3937 goto fail_free_srb_mempool; 3938 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3939 "ctx_cachep=%p ctx_mempool=%p.\n", 3940 ctx_cachep, ha->ctx_mempool); 3941 } 3942 3943 /* Get memory for cached NVRAM */ 3944 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3945 if (!ha->nvram) 3946 goto fail_free_ctx_mempool; 3947 3948 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3949 ha->pdev->device); 3950 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3951 DMA_POOL_SIZE, 8, 0); 3952 if (!ha->s_dma_pool) 3953 goto fail_free_nvram; 3954 3955 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3956 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3957 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3958 3959 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3960 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3961 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3962 if (!ha->dl_dma_pool) { 3963 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3964 "Failed to allocate memory for dl_dma_pool.\n"); 3965 goto fail_s_dma_pool; 3966 } 3967 3968 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3969 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3970 if (!ha->fcp_cmnd_dma_pool) { 3971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3972 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3973 goto fail_dl_dma_pool; 3974 } 3975 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3976 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3977 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3978 } 3979 3980 /* Allocate memory for SNS commands */ 3981 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3982 /* Get consistent memory allocated for SNS commands */ 3983 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3984 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3985 if (!ha->sns_cmd) 3986 goto fail_dma_pool; 3987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3988 "sns_cmd: %p.\n", ha->sns_cmd); 3989 } else { 3990 /* Get consistent memory allocated for MS IOCB */ 3991 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3992 &ha->ms_iocb_dma); 3993 if (!ha->ms_iocb) 3994 goto fail_dma_pool; 3995 /* Get consistent memory allocated for CT SNS commands */ 3996 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3997 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3998 if (!ha->ct_sns) 3999 goto fail_free_ms_iocb; 4000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4001 "ms_iocb=%p ct_sns=%p.\n", 4002 ha->ms_iocb, ha->ct_sns); 4003 } 4004 4005 /* Allocate memory for request ring */ 4006 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4007 if (!*req) { 4008 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4009 "Failed to allocate memory for req.\n"); 4010 goto fail_req; 4011 } 4012 (*req)->length = req_len; 4013 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4014 ((*req)->length + 1) * sizeof(request_t), 4015 &(*req)->dma, GFP_KERNEL); 4016 if (!(*req)->ring) { 4017 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4018 "Failed to allocate memory for req_ring.\n"); 4019 goto fail_req_ring; 4020 } 4021 /* Allocate memory for response ring */ 4022 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4023 if (!*rsp) { 4024 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4025 "Failed to allocate memory for rsp.\n"); 4026 goto fail_rsp; 4027 } 4028 (*rsp)->hw = ha; 4029 (*rsp)->length = rsp_len; 4030 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4031 ((*rsp)->length + 1) * sizeof(response_t), 4032 &(*rsp)->dma, GFP_KERNEL); 4033 if (!(*rsp)->ring) { 4034 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4035 "Failed to allocate memory for rsp_ring.\n"); 4036 goto fail_rsp_ring; 4037 } 4038 (*req)->rsp = *rsp; 4039 (*rsp)->req = *req; 4040 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4041 "req=%p req->length=%d req->ring=%p rsp=%p " 4042 "rsp->length=%d rsp->ring=%p.\n", 4043 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4044 (*rsp)->ring); 4045 /* Allocate memory for NVRAM data for vports */ 4046 if (ha->nvram_npiv_size) { 4047 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 4048 ha->nvram_npiv_size, GFP_KERNEL); 4049 if (!ha->npiv_info) { 4050 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4051 "Failed to allocate memory for npiv_info.\n"); 4052 goto fail_npiv_info; 4053 } 4054 } else 4055 ha->npiv_info = NULL; 4056 4057 /* Get consistent memory allocated for EX-INIT-CB. */ 4058 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4059 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4060 &ha->ex_init_cb_dma); 4061 if (!ha->ex_init_cb) 4062 goto fail_ex_init_cb; 4063 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4064 "ex_init_cb=%p.\n", ha->ex_init_cb); 4065 } 4066 4067 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4068 4069 /* Get consistent memory allocated for Async Port-Database. */ 4070 if (!IS_FWI2_CAPABLE(ha)) { 4071 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4072 &ha->async_pd_dma); 4073 if (!ha->async_pd) 4074 goto fail_async_pd; 4075 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4076 "async_pd=%p.\n", ha->async_pd); 4077 } 4078 4079 INIT_LIST_HEAD(&ha->vp_list); 4080 4081 /* Allocate memory for our loop_id bitmap */ 4082 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 4083 GFP_KERNEL); 4084 if (!ha->loop_id_map) 4085 goto fail_loop_id_map; 4086 else { 4087 qla2x00_set_reserved_loop_ids(ha); 4088 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4089 "loop_id_map=%p.\n", ha->loop_id_map); 4090 } 4091 4092 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4093 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4094 if (!ha->sfp_data) { 4095 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4096 "Unable to allocate memory for SFP read-data.\n"); 4097 goto fail_sfp_data; 4098 } 4099 4100 return 0; 4101 4102 fail_sfp_data: 4103 kfree(ha->loop_id_map); 4104 fail_loop_id_map: 4105 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4106 fail_async_pd: 4107 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4108 fail_ex_init_cb: 4109 kfree(ha->npiv_info); 4110 fail_npiv_info: 4111 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4112 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4113 (*rsp)->ring = NULL; 4114 (*rsp)->dma = 0; 4115 fail_rsp_ring: 4116 kfree(*rsp); 4117 fail_rsp: 4118 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4119 sizeof(request_t), (*req)->ring, (*req)->dma); 4120 (*req)->ring = NULL; 4121 (*req)->dma = 0; 4122 fail_req_ring: 4123 kfree(*req); 4124 fail_req: 4125 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4126 ha->ct_sns, ha->ct_sns_dma); 4127 ha->ct_sns = NULL; 4128 ha->ct_sns_dma = 0; 4129 fail_free_ms_iocb: 4130 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4131 ha->ms_iocb = NULL; 4132 ha->ms_iocb_dma = 0; 4133 4134 if (ha->sns_cmd) 4135 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4136 ha->sns_cmd, ha->sns_cmd_dma); 4137 fail_dma_pool: 4138 if (IS_QLA82XX(ha) || ql2xenabledif) { 4139 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4140 ha->fcp_cmnd_dma_pool = NULL; 4141 } 4142 fail_dl_dma_pool: 4143 if (IS_QLA82XX(ha) || ql2xenabledif) { 4144 dma_pool_destroy(ha->dl_dma_pool); 4145 ha->dl_dma_pool = NULL; 4146 } 4147 fail_s_dma_pool: 4148 dma_pool_destroy(ha->s_dma_pool); 4149 ha->s_dma_pool = NULL; 4150 fail_free_nvram: 4151 kfree(ha->nvram); 4152 ha->nvram = NULL; 4153 fail_free_ctx_mempool: 4154 if (ha->ctx_mempool) 4155 mempool_destroy(ha->ctx_mempool); 4156 ha->ctx_mempool = NULL; 4157 fail_free_srb_mempool: 4158 if (ha->srb_mempool) 4159 mempool_destroy(ha->srb_mempool); 4160 ha->srb_mempool = NULL; 4161 fail_free_gid_list: 4162 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4163 ha->gid_list, 4164 ha->gid_list_dma); 4165 ha->gid_list = NULL; 4166 ha->gid_list_dma = 0; 4167 fail_free_tgt_mem: 4168 qlt_mem_free(ha); 4169 fail_free_init_cb: 4170 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4171 ha->init_cb_dma); 4172 ha->init_cb = NULL; 4173 ha->init_cb_dma = 0; 4174 fail: 4175 ql_log(ql_log_fatal, NULL, 0x0030, 4176 "Memory allocation failure.\n"); 4177 return -ENOMEM; 4178 } 4179 4180 int 4181 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4182 { 4183 int rval; 4184 uint16_t size, max_cnt, temp; 4185 struct qla_hw_data *ha = vha->hw; 4186 4187 /* Return if we don't need to alloacate any extended logins */ 4188 if (!ql2xexlogins) 4189 return QLA_SUCCESS; 4190 4191 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4192 return QLA_SUCCESS; 4193 4194 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4195 max_cnt = 0; 4196 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4197 if (rval != QLA_SUCCESS) { 4198 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4199 "Failed to get exlogin status.\n"); 4200 return rval; 4201 } 4202 4203 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4204 temp *= size; 4205 4206 if (temp != ha->exlogin_size) { 4207 qla2x00_free_exlogin_buffer(ha); 4208 ha->exlogin_size = temp; 4209 4210 ql_log(ql_log_info, vha, 0xd024, 4211 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4212 max_cnt, size, temp); 4213 4214 ql_log(ql_log_info, vha, 0xd025, 4215 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4216 4217 /* Get consistent memory for extended logins */ 4218 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4219 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4220 if (!ha->exlogin_buf) { 4221 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4222 "Failed to allocate memory for exlogin_buf_dma.\n"); 4223 return -ENOMEM; 4224 } 4225 } 4226 4227 /* Now configure the dma buffer */ 4228 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4229 if (rval) { 4230 ql_log(ql_log_fatal, vha, 0xd033, 4231 "Setup extended login buffer ****FAILED****.\n"); 4232 qla2x00_free_exlogin_buffer(ha); 4233 } 4234 4235 return rval; 4236 } 4237 4238 /* 4239 * qla2x00_free_exlogin_buffer 4240 * 4241 * Input: 4242 * ha = adapter block pointer 4243 */ 4244 void 4245 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4246 { 4247 if (ha->exlogin_buf) { 4248 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4249 ha->exlogin_buf, ha->exlogin_buf_dma); 4250 ha->exlogin_buf = NULL; 4251 ha->exlogin_size = 0; 4252 } 4253 } 4254 4255 static void 4256 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4257 { 4258 u32 temp; 4259 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4260 4261 if (max_cnt > vha->hw->max_exchg) 4262 max_cnt = vha->hw->max_exchg; 4263 4264 if (qla_ini_mode_enabled(vha)) { 4265 if (ql2xiniexchg > max_cnt) 4266 ql2xiniexchg = max_cnt; 4267 4268 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4269 *ret_cnt = ql2xiniexchg; 4270 } else if (qla_tgt_mode_enabled(vha)) { 4271 if (ql2xexchoffld > max_cnt) 4272 ql2xexchoffld = max_cnt; 4273 4274 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4275 *ret_cnt = ql2xexchoffld; 4276 } else if (qla_dual_mode_enabled(vha)) { 4277 temp = ql2xiniexchg + ql2xexchoffld; 4278 if (temp > max_cnt) { 4279 ql2xiniexchg -= (temp - max_cnt)/2; 4280 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4281 temp = max_cnt; 4282 } 4283 4284 if (temp > FW_DEF_EXCHANGES_CNT) 4285 *ret_cnt = temp; 4286 } 4287 } 4288 4289 int 4290 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4291 { 4292 int rval; 4293 u16 size, max_cnt; 4294 u32 actual_cnt, totsz; 4295 struct qla_hw_data *ha = vha->hw; 4296 4297 if (!ha->flags.exchoffld_enabled) 4298 return QLA_SUCCESS; 4299 4300 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4301 return QLA_SUCCESS; 4302 4303 max_cnt = 0; 4304 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4305 if (rval != QLA_SUCCESS) { 4306 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4307 "Failed to get exlogin status.\n"); 4308 return rval; 4309 } 4310 4311 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4312 ql_log(ql_log_info, vha, 0xd014, 4313 "Actual exchange offload count: %d.\n", actual_cnt); 4314 4315 totsz = actual_cnt * size; 4316 4317 if (totsz != ha->exchoffld_size) { 4318 qla2x00_free_exchoffld_buffer(ha); 4319 ha->exchoffld_size = totsz; 4320 4321 ql_log(ql_log_info, vha, 0xd016, 4322 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4323 max_cnt, actual_cnt, size, totsz); 4324 4325 ql_log(ql_log_info, vha, 0xd017, 4326 "Exchange Buffers requested size = 0x%x\n", 4327 ha->exchoffld_size); 4328 4329 /* Get consistent memory for extended logins */ 4330 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4331 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4332 if (!ha->exchoffld_buf) { 4333 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4334 "Failed to allocate memory for Exchange Offload.\n"); 4335 4336 if (ha->max_exchg > 4337 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4338 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4339 } else if (ha->max_exchg > 4340 (FW_DEF_EXCHANGES_CNT + 512)) { 4341 ha->max_exchg -= 512; 4342 } else { 4343 ha->flags.exchoffld_enabled = 0; 4344 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4345 "Disabling Exchange offload due to lack of memory\n"); 4346 } 4347 ha->exchoffld_size = 0; 4348 4349 return -ENOMEM; 4350 } 4351 } 4352 4353 /* Now configure the dma buffer */ 4354 rval = qla_set_exchoffld_mem_cfg(vha); 4355 if (rval) { 4356 ql_log(ql_log_fatal, vha, 0xd02e, 4357 "Setup exchange offload buffer ****FAILED****.\n"); 4358 qla2x00_free_exchoffld_buffer(ha); 4359 } else { 4360 /* re-adjust number of target exchange */ 4361 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4362 4363 if (qla_ini_mode_enabled(vha)) 4364 icb->exchange_count = 0; 4365 else 4366 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4367 } 4368 4369 return rval; 4370 } 4371 4372 /* 4373 * qla2x00_free_exchoffld_buffer 4374 * 4375 * Input: 4376 * ha = adapter block pointer 4377 */ 4378 void 4379 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4380 { 4381 if (ha->exchoffld_buf) { 4382 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4383 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4384 ha->exchoffld_buf = NULL; 4385 ha->exchoffld_size = 0; 4386 } 4387 } 4388 4389 /* 4390 * qla2x00_free_fw_dump 4391 * Frees fw dump stuff. 4392 * 4393 * Input: 4394 * ha = adapter block pointer 4395 */ 4396 static void 4397 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4398 { 4399 if (ha->fce) 4400 dma_free_coherent(&ha->pdev->dev, 4401 FCE_SIZE, ha->fce, ha->fce_dma); 4402 4403 if (ha->eft) 4404 dma_free_coherent(&ha->pdev->dev, 4405 EFT_SIZE, ha->eft, ha->eft_dma); 4406 4407 if (ha->fw_dump) 4408 vfree(ha->fw_dump); 4409 if (ha->fw_dump_template) 4410 vfree(ha->fw_dump_template); 4411 4412 ha->fce = NULL; 4413 ha->fce_dma = 0; 4414 ha->eft = NULL; 4415 ha->eft_dma = 0; 4416 ha->fw_dumped = 0; 4417 ha->fw_dump_cap_flags = 0; 4418 ha->fw_dump_reading = 0; 4419 ha->fw_dump = NULL; 4420 ha->fw_dump_len = 0; 4421 ha->fw_dump_template = NULL; 4422 ha->fw_dump_template_len = 0; 4423 } 4424 4425 /* 4426 * qla2x00_mem_free 4427 * Frees all adapter allocated memory. 4428 * 4429 * Input: 4430 * ha = adapter block pointer. 4431 */ 4432 static void 4433 qla2x00_mem_free(struct qla_hw_data *ha) 4434 { 4435 qla2x00_free_fw_dump(ha); 4436 4437 if (ha->mctp_dump) 4438 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4439 ha->mctp_dump_dma); 4440 4441 if (ha->srb_mempool) 4442 mempool_destroy(ha->srb_mempool); 4443 4444 if (ha->dcbx_tlv) 4445 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4446 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4447 4448 if (ha->xgmac_data) 4449 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4450 ha->xgmac_data, ha->xgmac_data_dma); 4451 4452 if (ha->sns_cmd) 4453 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4454 ha->sns_cmd, ha->sns_cmd_dma); 4455 4456 if (ha->ct_sns) 4457 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4458 ha->ct_sns, ha->ct_sns_dma); 4459 4460 if (ha->sfp_data) 4461 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4462 ha->sfp_data_dma); 4463 4464 if (ha->ms_iocb) 4465 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4466 4467 if (ha->ex_init_cb) 4468 dma_pool_free(ha->s_dma_pool, 4469 ha->ex_init_cb, ha->ex_init_cb_dma); 4470 4471 if (ha->async_pd) 4472 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4473 4474 if (ha->s_dma_pool) 4475 dma_pool_destroy(ha->s_dma_pool); 4476 4477 if (ha->gid_list) 4478 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4479 ha->gid_list, ha->gid_list_dma); 4480 4481 if (IS_QLA82XX(ha)) { 4482 if (!list_empty(&ha->gbl_dsd_list)) { 4483 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4484 4485 /* clean up allocated prev pool */ 4486 list_for_each_entry_safe(dsd_ptr, 4487 tdsd_ptr, &ha->gbl_dsd_list, list) { 4488 dma_pool_free(ha->dl_dma_pool, 4489 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4490 list_del(&dsd_ptr->list); 4491 kfree(dsd_ptr); 4492 } 4493 } 4494 } 4495 4496 if (ha->dl_dma_pool) 4497 dma_pool_destroy(ha->dl_dma_pool); 4498 4499 if (ha->fcp_cmnd_dma_pool) 4500 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4501 4502 if (ha->ctx_mempool) 4503 mempool_destroy(ha->ctx_mempool); 4504 4505 qlt_mem_free(ha); 4506 4507 if (ha->init_cb) 4508 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4509 ha->init_cb, ha->init_cb_dma); 4510 4511 if (ha->optrom_buffer) 4512 vfree(ha->optrom_buffer); 4513 if (ha->nvram) 4514 kfree(ha->nvram); 4515 if (ha->npiv_info) 4516 kfree(ha->npiv_info); 4517 if (ha->swl) 4518 kfree(ha->swl); 4519 if (ha->loop_id_map) 4520 kfree(ha->loop_id_map); 4521 4522 ha->srb_mempool = NULL; 4523 ha->ctx_mempool = NULL; 4524 ha->sns_cmd = NULL; 4525 ha->sns_cmd_dma = 0; 4526 ha->ct_sns = NULL; 4527 ha->ct_sns_dma = 0; 4528 ha->ms_iocb = NULL; 4529 ha->ms_iocb_dma = 0; 4530 ha->init_cb = NULL; 4531 ha->init_cb_dma = 0; 4532 ha->ex_init_cb = NULL; 4533 ha->ex_init_cb_dma = 0; 4534 ha->async_pd = NULL; 4535 ha->async_pd_dma = 0; 4536 ha->loop_id_map = NULL; 4537 ha->npiv_info = NULL; 4538 ha->optrom_buffer = NULL; 4539 ha->swl = NULL; 4540 ha->nvram = NULL; 4541 ha->mctp_dump = NULL; 4542 ha->dcbx_tlv = NULL; 4543 ha->xgmac_data = NULL; 4544 ha->sfp_data = NULL; 4545 4546 ha->s_dma_pool = NULL; 4547 ha->dl_dma_pool = NULL; 4548 ha->fcp_cmnd_dma_pool = NULL; 4549 4550 ha->gid_list = NULL; 4551 ha->gid_list_dma = 0; 4552 4553 ha->tgt.atio_ring = NULL; 4554 ha->tgt.atio_dma = 0; 4555 ha->tgt.tgt_vp_map = NULL; 4556 } 4557 4558 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4559 struct qla_hw_data *ha) 4560 { 4561 struct Scsi_Host *host; 4562 struct scsi_qla_host *vha = NULL; 4563 4564 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4565 if (!host) { 4566 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4567 "Failed to allocate host from the scsi layer, aborting.\n"); 4568 return NULL; 4569 } 4570 4571 /* Clear our data area */ 4572 vha = shost_priv(host); 4573 memset(vha, 0, sizeof(scsi_qla_host_t)); 4574 4575 vha->host = host; 4576 vha->host_no = host->host_no; 4577 vha->hw = ha; 4578 4579 INIT_LIST_HEAD(&vha->vp_fcports); 4580 INIT_LIST_HEAD(&vha->work_list); 4581 INIT_LIST_HEAD(&vha->list); 4582 INIT_LIST_HEAD(&vha->qla_cmd_list); 4583 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4584 INIT_LIST_HEAD(&vha->logo_list); 4585 INIT_LIST_HEAD(&vha->plogi_ack_list); 4586 INIT_LIST_HEAD(&vha->qp_list); 4587 INIT_LIST_HEAD(&vha->gnl.fcports); 4588 INIT_LIST_HEAD(&vha->nvme_rport_list); 4589 INIT_LIST_HEAD(&vha->gpnid_list); 4590 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4591 4592 spin_lock_init(&vha->work_lock); 4593 spin_lock_init(&vha->cmd_list_lock); 4594 spin_lock_init(&vha->gnl.fcports_lock); 4595 init_waitqueue_head(&vha->fcport_waitQ); 4596 init_waitqueue_head(&vha->vref_waitq); 4597 4598 vha->gnl.size = sizeof(struct get_name_list_extended) * 4599 (ha->max_loop_id + 1); 4600 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4601 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4602 if (!vha->gnl.l) { 4603 ql_log(ql_log_fatal, vha, 0xd04a, 4604 "Alloc failed for name list.\n"); 4605 scsi_remove_host(vha->host); 4606 return NULL; 4607 } 4608 4609 /* todo: what about ext login? */ 4610 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4611 vha->scan.l = vmalloc(vha->scan.size); 4612 if (!vha->scan.l) { 4613 ql_log(ql_log_fatal, vha, 0xd04a, 4614 "Alloc failed for scan database.\n"); 4615 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4616 vha->gnl.l, vha->gnl.ldma); 4617 scsi_remove_host(vha->host); 4618 return NULL; 4619 } 4620 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4621 4622 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4623 ql_dbg(ql_dbg_init, vha, 0x0041, 4624 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4625 vha->host, vha->hw, vha, 4626 dev_name(&(ha->pdev->dev))); 4627 4628 return vha; 4629 } 4630 4631 struct qla_work_evt * 4632 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4633 { 4634 struct qla_work_evt *e; 4635 uint8_t bail; 4636 4637 QLA_VHA_MARK_BUSY(vha, bail); 4638 if (bail) 4639 return NULL; 4640 4641 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4642 if (!e) { 4643 QLA_VHA_MARK_NOT_BUSY(vha); 4644 return NULL; 4645 } 4646 4647 INIT_LIST_HEAD(&e->list); 4648 e->type = type; 4649 e->flags = QLA_EVT_FLAG_FREE; 4650 return e; 4651 } 4652 4653 int 4654 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4655 { 4656 unsigned long flags; 4657 bool q = false; 4658 4659 spin_lock_irqsave(&vha->work_lock, flags); 4660 list_add_tail(&e->list, &vha->work_list); 4661 4662 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4663 q = true; 4664 4665 spin_unlock_irqrestore(&vha->work_lock, flags); 4666 4667 if (q) 4668 queue_work(vha->hw->wq, &vha->iocb_work); 4669 4670 return QLA_SUCCESS; 4671 } 4672 4673 int 4674 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4675 u32 data) 4676 { 4677 struct qla_work_evt *e; 4678 4679 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4680 if (!e) 4681 return QLA_FUNCTION_FAILED; 4682 4683 e->u.aen.code = code; 4684 e->u.aen.data = data; 4685 return qla2x00_post_work(vha, e); 4686 } 4687 4688 int 4689 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4690 { 4691 struct qla_work_evt *e; 4692 4693 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4694 if (!e) 4695 return QLA_FUNCTION_FAILED; 4696 4697 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4698 return qla2x00_post_work(vha, e); 4699 } 4700 4701 #define qla2x00_post_async_work(name, type) \ 4702 int qla2x00_post_async_##name##_work( \ 4703 struct scsi_qla_host *vha, \ 4704 fc_port_t *fcport, uint16_t *data) \ 4705 { \ 4706 struct qla_work_evt *e; \ 4707 \ 4708 e = qla2x00_alloc_work(vha, type); \ 4709 if (!e) \ 4710 return QLA_FUNCTION_FAILED; \ 4711 \ 4712 e->u.logio.fcport = fcport; \ 4713 if (data) { \ 4714 e->u.logio.data[0] = data[0]; \ 4715 e->u.logio.data[1] = data[1]; \ 4716 } \ 4717 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4718 return qla2x00_post_work(vha, e); \ 4719 } 4720 4721 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4722 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4723 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4724 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4725 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4726 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4727 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4728 4729 int 4730 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4731 { 4732 struct qla_work_evt *e; 4733 4734 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4735 if (!e) 4736 return QLA_FUNCTION_FAILED; 4737 4738 e->u.uevent.code = code; 4739 return qla2x00_post_work(vha, e); 4740 } 4741 4742 static void 4743 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4744 { 4745 char event_string[40]; 4746 char *envp[] = { event_string, NULL }; 4747 4748 switch (code) { 4749 case QLA_UEVENT_CODE_FW_DUMP: 4750 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4751 vha->host_no); 4752 break; 4753 default: 4754 /* do nothing */ 4755 break; 4756 } 4757 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4758 } 4759 4760 int 4761 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4762 uint32_t *data, int cnt) 4763 { 4764 struct qla_work_evt *e; 4765 4766 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4767 if (!e) 4768 return QLA_FUNCTION_FAILED; 4769 4770 e->u.aenfx.evtcode = evtcode; 4771 e->u.aenfx.count = cnt; 4772 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4773 return qla2x00_post_work(vha, e); 4774 } 4775 4776 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4777 { 4778 struct qla_work_evt *e; 4779 4780 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4781 if (!e) 4782 return QLA_FUNCTION_FAILED; 4783 4784 e->u.fcport.fcport = fcport; 4785 return qla2x00_post_work(vha, e); 4786 } 4787 4788 static 4789 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4790 { 4791 unsigned long flags; 4792 fc_port_t *fcport = NULL, *tfcp; 4793 struct qlt_plogi_ack_t *pla = 4794 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4795 uint8_t free_fcport = 0; 4796 u64 wwn; 4797 4798 ql_dbg(ql_dbg_disc, vha, 0xffff, 4799 "%s %d %8phC enter\n", 4800 __func__, __LINE__, e->u.new_sess.port_name); 4801 4802 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4803 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4804 if (fcport) { 4805 fcport->d_id = e->u.new_sess.id; 4806 if (pla) { 4807 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4808 memcpy(fcport->node_name, 4809 pla->iocb.u.isp24.u.plogi.node_name, 4810 WWN_SIZE); 4811 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4812 /* we took an extra ref_count to prevent PLOGI ACK when 4813 * fcport/sess has not been created. 4814 */ 4815 pla->ref_count--; 4816 } 4817 } else { 4818 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4819 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4820 if (fcport) { 4821 fcport->d_id = e->u.new_sess.id; 4822 fcport->flags |= FCF_FABRIC_DEVICE; 4823 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4824 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP) 4825 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4826 4827 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) { 4828 fcport->fc4_type = FC4_TYPE_OTHER; 4829 fcport->fc4f_nvme = FC4_TYPE_NVME; 4830 } 4831 4832 memcpy(fcport->port_name, e->u.new_sess.port_name, 4833 WWN_SIZE); 4834 } else { 4835 ql_dbg(ql_dbg_disc, vha, 0xffff, 4836 "%s %8phC mem alloc fail.\n", 4837 __func__, e->u.new_sess.port_name); 4838 4839 if (pla) 4840 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4841 return; 4842 } 4843 4844 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4845 /* search again to make sure no one else got ahead */ 4846 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4847 e->u.new_sess.port_name, 1); 4848 if (tfcp) { 4849 /* should rarily happen */ 4850 ql_dbg(ql_dbg_disc, vha, 0xffff, 4851 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4852 __func__, tfcp->port_name, tfcp->disc_state, 4853 tfcp->fw_login_state); 4854 4855 free_fcport = 1; 4856 } else { 4857 list_add_tail(&fcport->list, &vha->vp_fcports); 4858 4859 } 4860 if (pla) { 4861 qlt_plogi_ack_link(vha, pla, fcport, 4862 QLT_PLOGI_LINK_SAME_WWN); 4863 pla->ref_count--; 4864 } 4865 } 4866 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4867 4868 if (fcport) { 4869 if (N2N_TOPO(vha->hw)) 4870 fcport->flags &= ~FCF_FABRIC_DEVICE; 4871 4872 fcport->id_changed = 1; 4873 fcport->scan_state = QLA_FCPORT_FOUND; 4874 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4875 4876 if (pla) { 4877 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4878 u16 wd3_lo; 4879 4880 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4881 fcport->local = 0; 4882 fcport->loop_id = 4883 le16_to_cpu( 4884 pla->iocb.u.isp24.nport_handle); 4885 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4886 wd3_lo = 4887 le16_to_cpu( 4888 pla->iocb.u.isp24.u.prli.wd3_lo); 4889 4890 if (wd3_lo & BIT_7) 4891 fcport->conf_compl_supported = 1; 4892 4893 if ((wd3_lo & BIT_4) == 0) 4894 fcport->port_type = FCT_INITIATOR; 4895 else 4896 fcport->port_type = FCT_TARGET; 4897 } 4898 qlt_plogi_ack_unref(vha, pla); 4899 } else { 4900 fc_port_t *dfcp = NULL; 4901 4902 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4903 tfcp = qla2x00_find_fcport_by_nportid(vha, 4904 &e->u.new_sess.id, 1); 4905 if (tfcp && (tfcp != fcport)) { 4906 /* 4907 * We have a conflict fcport with same NportID. 4908 */ 4909 ql_dbg(ql_dbg_disc, vha, 0xffff, 4910 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4911 __func__, tfcp->port_name, tfcp->disc_state, 4912 tfcp->fw_login_state); 4913 4914 switch (tfcp->disc_state) { 4915 case DSC_DELETED: 4916 break; 4917 case DSC_DELETE_PEND: 4918 fcport->login_pause = 1; 4919 tfcp->conflict = fcport; 4920 break; 4921 default: 4922 fcport->login_pause = 1; 4923 tfcp->conflict = fcport; 4924 dfcp = tfcp; 4925 break; 4926 } 4927 } 4928 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4929 if (dfcp) 4930 qlt_schedule_sess_for_deletion(tfcp); 4931 4932 wwn = wwn_to_u64(fcport->node_name); 4933 4934 if (!wwn) 4935 qla24xx_async_gnnid(vha, fcport); 4936 else 4937 qla24xx_async_gnl(vha, fcport); 4938 } 4939 } 4940 4941 if (free_fcport) { 4942 qla2x00_free_fcport(fcport); 4943 if (pla) 4944 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4945 } 4946 } 4947 4948 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4949 { 4950 struct srb *sp = e->u.iosb.sp; 4951 int rval; 4952 4953 rval = qla2x00_start_sp(sp); 4954 if (rval != QLA_SUCCESS) { 4955 ql_dbg(ql_dbg_disc, vha, 0x2043, 4956 "%s: %s: Re-issue IOCB failed (%d).\n", 4957 __func__, sp->name, rval); 4958 qla24xx_sp_unmap(vha, sp); 4959 } 4960 } 4961 4962 void 4963 qla2x00_do_work(struct scsi_qla_host *vha) 4964 { 4965 struct qla_work_evt *e, *tmp; 4966 unsigned long flags; 4967 LIST_HEAD(work); 4968 4969 spin_lock_irqsave(&vha->work_lock, flags); 4970 list_splice_init(&vha->work_list, &work); 4971 spin_unlock_irqrestore(&vha->work_lock, flags); 4972 4973 list_for_each_entry_safe(e, tmp, &work, list) { 4974 list_del_init(&e->list); 4975 4976 switch (e->type) { 4977 case QLA_EVT_AEN: 4978 fc_host_post_event(vha->host, fc_get_event_number(), 4979 e->u.aen.code, e->u.aen.data); 4980 break; 4981 case QLA_EVT_IDC_ACK: 4982 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4983 break; 4984 case QLA_EVT_ASYNC_LOGIN: 4985 qla2x00_async_login(vha, e->u.logio.fcport, 4986 e->u.logio.data); 4987 break; 4988 case QLA_EVT_ASYNC_LOGOUT: 4989 qla2x00_async_logout(vha, e->u.logio.fcport); 4990 break; 4991 case QLA_EVT_ASYNC_LOGOUT_DONE: 4992 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4993 e->u.logio.data); 4994 break; 4995 case QLA_EVT_ASYNC_ADISC: 4996 qla2x00_async_adisc(vha, e->u.logio.fcport, 4997 e->u.logio.data); 4998 break; 4999 case QLA_EVT_ASYNC_ADISC_DONE: 5000 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 5001 e->u.logio.data); 5002 break; 5003 case QLA_EVT_UEVENT: 5004 qla2x00_uevent_emit(vha, e->u.uevent.code); 5005 break; 5006 case QLA_EVT_AENFX: 5007 qlafx00_process_aen(vha, e); 5008 break; 5009 case QLA_EVT_GIDPN: 5010 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 5011 break; 5012 case QLA_EVT_GPNID: 5013 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5014 break; 5015 case QLA_EVT_UNMAP: 5016 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5017 break; 5018 case QLA_EVT_RELOGIN: 5019 qla2x00_relogin(vha); 5020 break; 5021 case QLA_EVT_NEW_SESS: 5022 qla24xx_create_new_sess(vha, e); 5023 break; 5024 case QLA_EVT_GPDB: 5025 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5026 e->u.fcport.opt); 5027 break; 5028 case QLA_EVT_PRLI: 5029 qla24xx_async_prli(vha, e->u.fcport.fcport); 5030 break; 5031 case QLA_EVT_GPSC: 5032 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5033 break; 5034 case QLA_EVT_UPD_FCPORT: 5035 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5036 break; 5037 case QLA_EVT_GNL: 5038 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5039 break; 5040 case QLA_EVT_NACK: 5041 qla24xx_do_nack_work(vha, e); 5042 break; 5043 case QLA_EVT_ASYNC_PRLO: 5044 qla2x00_async_prlo(vha, e->u.logio.fcport); 5045 break; 5046 case QLA_EVT_ASYNC_PRLO_DONE: 5047 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5048 e->u.logio.data); 5049 break; 5050 case QLA_EVT_GPNFT: 5051 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5052 e->u.gpnft.sp); 5053 break; 5054 case QLA_EVT_GPNFT_DONE: 5055 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5056 break; 5057 case QLA_EVT_GNNFT_DONE: 5058 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5059 break; 5060 case QLA_EVT_GNNID: 5061 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5062 break; 5063 case QLA_EVT_GFPNID: 5064 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5065 break; 5066 case QLA_EVT_SP_RETRY: 5067 qla_sp_retry(vha, e); 5068 } 5069 if (e->flags & QLA_EVT_FLAG_FREE) 5070 kfree(e); 5071 5072 /* For each work completed decrement vha ref count */ 5073 QLA_VHA_MARK_NOT_BUSY(vha); 5074 } 5075 } 5076 5077 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5078 { 5079 struct qla_work_evt *e; 5080 5081 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5082 5083 if (!e) { 5084 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5085 return QLA_FUNCTION_FAILED; 5086 } 5087 5088 return qla2x00_post_work(vha, e); 5089 } 5090 5091 /* Relogins all the fcports of a vport 5092 * Context: dpc thread 5093 */ 5094 void qla2x00_relogin(struct scsi_qla_host *vha) 5095 { 5096 fc_port_t *fcport; 5097 int status; 5098 struct event_arg ea; 5099 5100 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5101 /* 5102 * If the port is not ONLINE then try to login 5103 * to it if we haven't run out of retries. 5104 */ 5105 if (atomic_read(&fcport->state) != FCS_ONLINE && 5106 fcport->login_retry && 5107 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) { 5108 if (vha->hw->current_topology != ISP_CFG_NL) { 5109 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 5110 "%s %8phC DS %d LS %d\n", __func__, 5111 fcport->port_name, fcport->disc_state, 5112 fcport->fw_login_state); 5113 memset(&ea, 0, sizeof(ea)); 5114 ea.event = FCME_RELOGIN; 5115 ea.fcport = fcport; 5116 qla2x00_fcport_event_handler(vha, &ea); 5117 } else if (vha->hw->current_topology == ISP_CFG_NL) { 5118 fcport->login_retry--; 5119 status = qla2x00_local_device_login(vha, 5120 fcport); 5121 if (status == QLA_SUCCESS) { 5122 fcport->old_loop_id = fcport->loop_id; 5123 ql_dbg(ql_dbg_disc, vha, 0x2003, 5124 "Port login OK: logged in ID 0x%x.\n", 5125 fcport->loop_id); 5126 qla2x00_update_fcport(vha, fcport); 5127 } else if (status == 1) { 5128 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5129 /* retry the login again */ 5130 ql_dbg(ql_dbg_disc, vha, 0x2007, 5131 "Retrying %d login again loop_id 0x%x.\n", 5132 fcport->login_retry, 5133 fcport->loop_id); 5134 } else { 5135 fcport->login_retry = 0; 5136 } 5137 5138 if (fcport->login_retry == 0 && 5139 status != QLA_SUCCESS) 5140 qla2x00_clear_loop_id(fcport); 5141 } 5142 } 5143 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5144 break; 5145 } 5146 5147 ql_dbg(ql_dbg_disc, vha, 0x400e, 5148 "Relogin end.\n"); 5149 } 5150 5151 /* Schedule work on any of the dpc-workqueues */ 5152 void 5153 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5154 { 5155 struct qla_hw_data *ha = base_vha->hw; 5156 5157 switch (work_code) { 5158 case MBA_IDC_AEN: /* 0x8200 */ 5159 if (ha->dpc_lp_wq) 5160 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5161 break; 5162 5163 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5164 if (!ha->flags.nic_core_reset_hdlr_active) { 5165 if (ha->dpc_hp_wq) 5166 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5167 } else 5168 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5169 "NIC Core reset is already active. Skip " 5170 "scheduling it again.\n"); 5171 break; 5172 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5173 if (ha->dpc_hp_wq) 5174 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5175 break; 5176 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5177 if (ha->dpc_hp_wq) 5178 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5179 break; 5180 default: 5181 ql_log(ql_log_warn, base_vha, 0xb05f, 5182 "Unknown work-code=0x%x.\n", work_code); 5183 } 5184 5185 return; 5186 } 5187 5188 /* Work: Perform NIC Core Unrecoverable state handling */ 5189 void 5190 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5191 { 5192 struct qla_hw_data *ha = 5193 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5194 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5195 uint32_t dev_state = 0; 5196 5197 qla83xx_idc_lock(base_vha, 0); 5198 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5199 qla83xx_reset_ownership(base_vha); 5200 if (ha->flags.nic_core_reset_owner) { 5201 ha->flags.nic_core_reset_owner = 0; 5202 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5203 QLA8XXX_DEV_FAILED); 5204 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5205 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5206 } 5207 qla83xx_idc_unlock(base_vha, 0); 5208 } 5209 5210 /* Work: Execute IDC state handler */ 5211 void 5212 qla83xx_idc_state_handler_work(struct work_struct *work) 5213 { 5214 struct qla_hw_data *ha = 5215 container_of(work, struct qla_hw_data, idc_state_handler); 5216 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5217 uint32_t dev_state = 0; 5218 5219 qla83xx_idc_lock(base_vha, 0); 5220 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5221 if (dev_state == QLA8XXX_DEV_FAILED || 5222 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5223 qla83xx_idc_state_handler(base_vha); 5224 qla83xx_idc_unlock(base_vha, 0); 5225 } 5226 5227 static int 5228 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5229 { 5230 int rval = QLA_SUCCESS; 5231 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5232 uint32_t heart_beat_counter1, heart_beat_counter2; 5233 5234 do { 5235 if (time_after(jiffies, heart_beat_wait)) { 5236 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5237 "Nic Core f/w is not alive.\n"); 5238 rval = QLA_FUNCTION_FAILED; 5239 break; 5240 } 5241 5242 qla83xx_idc_lock(base_vha, 0); 5243 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5244 &heart_beat_counter1); 5245 qla83xx_idc_unlock(base_vha, 0); 5246 msleep(100); 5247 qla83xx_idc_lock(base_vha, 0); 5248 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5249 &heart_beat_counter2); 5250 qla83xx_idc_unlock(base_vha, 0); 5251 } while (heart_beat_counter1 == heart_beat_counter2); 5252 5253 return rval; 5254 } 5255 5256 /* Work: Perform NIC Core Reset handling */ 5257 void 5258 qla83xx_nic_core_reset_work(struct work_struct *work) 5259 { 5260 struct qla_hw_data *ha = 5261 container_of(work, struct qla_hw_data, nic_core_reset); 5262 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5263 uint32_t dev_state = 0; 5264 5265 if (IS_QLA2031(ha)) { 5266 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5267 ql_log(ql_log_warn, base_vha, 0xb081, 5268 "Failed to dump mctp\n"); 5269 return; 5270 } 5271 5272 if (!ha->flags.nic_core_reset_hdlr_active) { 5273 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5274 qla83xx_idc_lock(base_vha, 0); 5275 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5276 &dev_state); 5277 qla83xx_idc_unlock(base_vha, 0); 5278 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5279 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5280 "Nic Core f/w is alive.\n"); 5281 return; 5282 } 5283 } 5284 5285 ha->flags.nic_core_reset_hdlr_active = 1; 5286 if (qla83xx_nic_core_reset(base_vha)) { 5287 /* NIC Core reset failed. */ 5288 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5289 "NIC Core reset failed.\n"); 5290 } 5291 ha->flags.nic_core_reset_hdlr_active = 0; 5292 } 5293 } 5294 5295 /* Work: Handle 8200 IDC aens */ 5296 void 5297 qla83xx_service_idc_aen(struct work_struct *work) 5298 { 5299 struct qla_hw_data *ha = 5300 container_of(work, struct qla_hw_data, idc_aen); 5301 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5302 uint32_t dev_state, idc_control; 5303 5304 qla83xx_idc_lock(base_vha, 0); 5305 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5306 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5307 qla83xx_idc_unlock(base_vha, 0); 5308 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5309 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5310 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5311 "Application requested NIC Core Reset.\n"); 5312 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5313 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5314 QLA_SUCCESS) { 5315 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5316 "Other protocol driver requested NIC Core Reset.\n"); 5317 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5318 } 5319 } else if (dev_state == QLA8XXX_DEV_FAILED || 5320 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5321 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5322 } 5323 } 5324 5325 static void 5326 qla83xx_wait_logic(void) 5327 { 5328 int i; 5329 5330 /* Yield CPU */ 5331 if (!in_interrupt()) { 5332 /* 5333 * Wait about 200ms before retrying again. 5334 * This controls the number of retries for single 5335 * lock operation. 5336 */ 5337 msleep(100); 5338 schedule(); 5339 } else { 5340 for (i = 0; i < 20; i++) 5341 cpu_relax(); /* This a nop instr on i386 */ 5342 } 5343 } 5344 5345 static int 5346 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5347 { 5348 int rval; 5349 uint32_t data; 5350 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5351 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5352 struct qla_hw_data *ha = base_vha->hw; 5353 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5354 "Trying force recovery of the IDC lock.\n"); 5355 5356 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5357 if (rval) 5358 return rval; 5359 5360 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5361 return QLA_SUCCESS; 5362 } else { 5363 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5364 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5365 data); 5366 if (rval) 5367 return rval; 5368 5369 msleep(200); 5370 5371 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5372 &data); 5373 if (rval) 5374 return rval; 5375 5376 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5377 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5378 ~(idc_lck_rcvry_stage_mask)); 5379 rval = qla83xx_wr_reg(base_vha, 5380 QLA83XX_IDC_LOCK_RECOVERY, data); 5381 if (rval) 5382 return rval; 5383 5384 /* Forcefully perform IDC UnLock */ 5385 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5386 &data); 5387 if (rval) 5388 return rval; 5389 /* Clear lock-id by setting 0xff */ 5390 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5391 0xff); 5392 if (rval) 5393 return rval; 5394 /* Clear lock-recovery by setting 0x0 */ 5395 rval = qla83xx_wr_reg(base_vha, 5396 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5397 if (rval) 5398 return rval; 5399 } else 5400 return QLA_SUCCESS; 5401 } 5402 5403 return rval; 5404 } 5405 5406 static int 5407 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5408 { 5409 int rval = QLA_SUCCESS; 5410 uint32_t o_drv_lockid, n_drv_lockid; 5411 unsigned long lock_recovery_timeout; 5412 5413 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5414 retry_lockid: 5415 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5416 if (rval) 5417 goto exit; 5418 5419 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5420 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5421 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5422 return QLA_SUCCESS; 5423 else 5424 return QLA_FUNCTION_FAILED; 5425 } 5426 5427 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5428 if (rval) 5429 goto exit; 5430 5431 if (o_drv_lockid == n_drv_lockid) { 5432 qla83xx_wait_logic(); 5433 goto retry_lockid; 5434 } else 5435 return QLA_SUCCESS; 5436 5437 exit: 5438 return rval; 5439 } 5440 5441 void 5442 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5443 { 5444 uint16_t options = (requester_id << 15) | BIT_6; 5445 uint32_t data; 5446 uint32_t lock_owner; 5447 struct qla_hw_data *ha = base_vha->hw; 5448 5449 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5450 retry_lock: 5451 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5452 == QLA_SUCCESS) { 5453 if (data) { 5454 /* Setting lock-id to our function-number */ 5455 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5456 ha->portnum); 5457 } else { 5458 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5459 &lock_owner); 5460 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5461 "Failed to acquire IDC lock, acquired by %d, " 5462 "retrying...\n", lock_owner); 5463 5464 /* Retry/Perform IDC-Lock recovery */ 5465 if (qla83xx_idc_lock_recovery(base_vha) 5466 == QLA_SUCCESS) { 5467 qla83xx_wait_logic(); 5468 goto retry_lock; 5469 } else 5470 ql_log(ql_log_warn, base_vha, 0xb075, 5471 "IDC Lock recovery FAILED.\n"); 5472 } 5473 5474 } 5475 5476 return; 5477 5478 /* XXX: IDC-lock implementation using access-control mbx */ 5479 retry_lock2: 5480 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5481 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5482 "Failed to acquire IDC lock. retrying...\n"); 5483 /* Retry/Perform IDC-Lock recovery */ 5484 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5485 qla83xx_wait_logic(); 5486 goto retry_lock2; 5487 } else 5488 ql_log(ql_log_warn, base_vha, 0xb076, 5489 "IDC Lock recovery FAILED.\n"); 5490 } 5491 5492 return; 5493 } 5494 5495 void 5496 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5497 { 5498 #if 0 5499 uint16_t options = (requester_id << 15) | BIT_7; 5500 #endif 5501 uint16_t retry; 5502 uint32_t data; 5503 struct qla_hw_data *ha = base_vha->hw; 5504 5505 /* IDC-unlock implementation using driver-unlock/lock-id 5506 * remote registers 5507 */ 5508 retry = 0; 5509 retry_unlock: 5510 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5511 == QLA_SUCCESS) { 5512 if (data == ha->portnum) { 5513 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5514 /* Clearing lock-id by setting 0xff */ 5515 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5516 } else if (retry < 10) { 5517 /* SV: XXX: IDC unlock retrying needed here? */ 5518 5519 /* Retry for IDC-unlock */ 5520 qla83xx_wait_logic(); 5521 retry++; 5522 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5523 "Failed to release IDC lock, retrying=%d\n", retry); 5524 goto retry_unlock; 5525 } 5526 } else if (retry < 10) { 5527 /* Retry for IDC-unlock */ 5528 qla83xx_wait_logic(); 5529 retry++; 5530 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5531 "Failed to read drv-lockid, retrying=%d\n", retry); 5532 goto retry_unlock; 5533 } 5534 5535 return; 5536 5537 #if 0 5538 /* XXX: IDC-unlock implementation using access-control mbx */ 5539 retry = 0; 5540 retry_unlock2: 5541 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5542 if (retry < 10) { 5543 /* Retry for IDC-unlock */ 5544 qla83xx_wait_logic(); 5545 retry++; 5546 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5547 "Failed to release IDC lock, retrying=%d\n", retry); 5548 goto retry_unlock2; 5549 } 5550 } 5551 5552 return; 5553 #endif 5554 } 5555 5556 int 5557 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5558 { 5559 int rval = QLA_SUCCESS; 5560 struct qla_hw_data *ha = vha->hw; 5561 uint32_t drv_presence; 5562 5563 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5564 if (rval == QLA_SUCCESS) { 5565 drv_presence |= (1 << ha->portnum); 5566 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5567 drv_presence); 5568 } 5569 5570 return rval; 5571 } 5572 5573 int 5574 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5575 { 5576 int rval = QLA_SUCCESS; 5577 5578 qla83xx_idc_lock(vha, 0); 5579 rval = __qla83xx_set_drv_presence(vha); 5580 qla83xx_idc_unlock(vha, 0); 5581 5582 return rval; 5583 } 5584 5585 int 5586 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5587 { 5588 int rval = QLA_SUCCESS; 5589 struct qla_hw_data *ha = vha->hw; 5590 uint32_t drv_presence; 5591 5592 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5593 if (rval == QLA_SUCCESS) { 5594 drv_presence &= ~(1 << ha->portnum); 5595 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5596 drv_presence); 5597 } 5598 5599 return rval; 5600 } 5601 5602 int 5603 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5604 { 5605 int rval = QLA_SUCCESS; 5606 5607 qla83xx_idc_lock(vha, 0); 5608 rval = __qla83xx_clear_drv_presence(vha); 5609 qla83xx_idc_unlock(vha, 0); 5610 5611 return rval; 5612 } 5613 5614 static void 5615 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5616 { 5617 struct qla_hw_data *ha = vha->hw; 5618 uint32_t drv_ack, drv_presence; 5619 unsigned long ack_timeout; 5620 5621 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5622 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5623 while (1) { 5624 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5625 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5626 if ((drv_ack & drv_presence) == drv_presence) 5627 break; 5628 5629 if (time_after_eq(jiffies, ack_timeout)) { 5630 ql_log(ql_log_warn, vha, 0xb067, 5631 "RESET ACK TIMEOUT! drv_presence=0x%x " 5632 "drv_ack=0x%x\n", drv_presence, drv_ack); 5633 /* 5634 * The function(s) which did not ack in time are forced 5635 * to withdraw any further participation in the IDC 5636 * reset. 5637 */ 5638 if (drv_ack != drv_presence) 5639 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5640 drv_ack); 5641 break; 5642 } 5643 5644 qla83xx_idc_unlock(vha, 0); 5645 msleep(1000); 5646 qla83xx_idc_lock(vha, 0); 5647 } 5648 5649 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5650 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5651 } 5652 5653 static int 5654 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5655 { 5656 int rval = QLA_SUCCESS; 5657 uint32_t idc_control; 5658 5659 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5660 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5661 5662 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5663 __qla83xx_get_idc_control(vha, &idc_control); 5664 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5665 __qla83xx_set_idc_control(vha, 0); 5666 5667 qla83xx_idc_unlock(vha, 0); 5668 rval = qla83xx_restart_nic_firmware(vha); 5669 qla83xx_idc_lock(vha, 0); 5670 5671 if (rval != QLA_SUCCESS) { 5672 ql_log(ql_log_fatal, vha, 0xb06a, 5673 "Failed to restart NIC f/w.\n"); 5674 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5675 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5676 } else { 5677 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5678 "Success in restarting nic f/w.\n"); 5679 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5680 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5681 } 5682 5683 return rval; 5684 } 5685 5686 /* Assumes idc_lock always held on entry */ 5687 int 5688 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5689 { 5690 struct qla_hw_data *ha = base_vha->hw; 5691 int rval = QLA_SUCCESS; 5692 unsigned long dev_init_timeout; 5693 uint32_t dev_state; 5694 5695 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5696 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5697 5698 while (1) { 5699 5700 if (time_after_eq(jiffies, dev_init_timeout)) { 5701 ql_log(ql_log_warn, base_vha, 0xb06e, 5702 "Initialization TIMEOUT!\n"); 5703 /* Init timeout. Disable further NIC Core 5704 * communication. 5705 */ 5706 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5707 QLA8XXX_DEV_FAILED); 5708 ql_log(ql_log_info, base_vha, 0xb06f, 5709 "HW State: FAILED.\n"); 5710 } 5711 5712 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5713 switch (dev_state) { 5714 case QLA8XXX_DEV_READY: 5715 if (ha->flags.nic_core_reset_owner) 5716 qla83xx_idc_audit(base_vha, 5717 IDC_AUDIT_COMPLETION); 5718 ha->flags.nic_core_reset_owner = 0; 5719 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5720 "Reset_owner reset by 0x%x.\n", 5721 ha->portnum); 5722 goto exit; 5723 case QLA8XXX_DEV_COLD: 5724 if (ha->flags.nic_core_reset_owner) 5725 rval = qla83xx_device_bootstrap(base_vha); 5726 else { 5727 /* Wait for AEN to change device-state */ 5728 qla83xx_idc_unlock(base_vha, 0); 5729 msleep(1000); 5730 qla83xx_idc_lock(base_vha, 0); 5731 } 5732 break; 5733 case QLA8XXX_DEV_INITIALIZING: 5734 /* Wait for AEN to change device-state */ 5735 qla83xx_idc_unlock(base_vha, 0); 5736 msleep(1000); 5737 qla83xx_idc_lock(base_vha, 0); 5738 break; 5739 case QLA8XXX_DEV_NEED_RESET: 5740 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5741 qla83xx_need_reset_handler(base_vha); 5742 else { 5743 /* Wait for AEN to change device-state */ 5744 qla83xx_idc_unlock(base_vha, 0); 5745 msleep(1000); 5746 qla83xx_idc_lock(base_vha, 0); 5747 } 5748 /* reset timeout value after need reset handler */ 5749 dev_init_timeout = jiffies + 5750 (ha->fcoe_dev_init_timeout * HZ); 5751 break; 5752 case QLA8XXX_DEV_NEED_QUIESCENT: 5753 /* XXX: DEBUG for now */ 5754 qla83xx_idc_unlock(base_vha, 0); 5755 msleep(1000); 5756 qla83xx_idc_lock(base_vha, 0); 5757 break; 5758 case QLA8XXX_DEV_QUIESCENT: 5759 /* XXX: DEBUG for now */ 5760 if (ha->flags.quiesce_owner) 5761 goto exit; 5762 5763 qla83xx_idc_unlock(base_vha, 0); 5764 msleep(1000); 5765 qla83xx_idc_lock(base_vha, 0); 5766 dev_init_timeout = jiffies + 5767 (ha->fcoe_dev_init_timeout * HZ); 5768 break; 5769 case QLA8XXX_DEV_FAILED: 5770 if (ha->flags.nic_core_reset_owner) 5771 qla83xx_idc_audit(base_vha, 5772 IDC_AUDIT_COMPLETION); 5773 ha->flags.nic_core_reset_owner = 0; 5774 __qla83xx_clear_drv_presence(base_vha); 5775 qla83xx_idc_unlock(base_vha, 0); 5776 qla8xxx_dev_failed_handler(base_vha); 5777 rval = QLA_FUNCTION_FAILED; 5778 qla83xx_idc_lock(base_vha, 0); 5779 goto exit; 5780 case QLA8XXX_BAD_VALUE: 5781 qla83xx_idc_unlock(base_vha, 0); 5782 msleep(1000); 5783 qla83xx_idc_lock(base_vha, 0); 5784 break; 5785 default: 5786 ql_log(ql_log_warn, base_vha, 0xb071, 5787 "Unknown Device State: %x.\n", dev_state); 5788 qla83xx_idc_unlock(base_vha, 0); 5789 qla8xxx_dev_failed_handler(base_vha); 5790 rval = QLA_FUNCTION_FAILED; 5791 qla83xx_idc_lock(base_vha, 0); 5792 goto exit; 5793 } 5794 } 5795 5796 exit: 5797 return rval; 5798 } 5799 5800 void 5801 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5802 { 5803 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5804 board_disable); 5805 struct pci_dev *pdev = ha->pdev; 5806 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5807 5808 /* 5809 * if UNLOAD flag is already set, then continue unload, 5810 * where it was set first. 5811 */ 5812 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5813 return; 5814 5815 ql_log(ql_log_warn, base_vha, 0x015b, 5816 "Disabling adapter.\n"); 5817 5818 if (!atomic_read(&pdev->enable_cnt)) { 5819 ql_log(ql_log_info, base_vha, 0xfffc, 5820 "PCI device disabled, no action req for PCI error=%lx\n", 5821 base_vha->pci_flags); 5822 return; 5823 } 5824 5825 qla2x00_wait_for_sess_deletion(base_vha); 5826 5827 set_bit(UNLOADING, &base_vha->dpc_flags); 5828 5829 qla2x00_delete_all_vps(ha, base_vha); 5830 5831 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5832 5833 qla2x00_dfs_remove(base_vha); 5834 5835 qla84xx_put_chip(base_vha); 5836 5837 if (base_vha->timer_active) 5838 qla2x00_stop_timer(base_vha); 5839 5840 base_vha->flags.online = 0; 5841 5842 qla2x00_destroy_deferred_work(ha); 5843 5844 /* 5845 * Do not try to stop beacon blink as it will issue a mailbox 5846 * command. 5847 */ 5848 qla2x00_free_sysfs_attr(base_vha, false); 5849 5850 fc_remove_host(base_vha->host); 5851 5852 scsi_remove_host(base_vha->host); 5853 5854 base_vha->flags.init_done = 0; 5855 qla25xx_delete_queues(base_vha); 5856 qla2x00_free_fcports(base_vha); 5857 qla2x00_free_irqs(base_vha); 5858 qla2x00_mem_free(ha); 5859 qla82xx_md_free(base_vha); 5860 qla2x00_free_queues(ha); 5861 5862 qla2x00_unmap_iobases(ha); 5863 5864 pci_release_selected_regions(ha->pdev, ha->bars); 5865 pci_disable_pcie_error_reporting(pdev); 5866 pci_disable_device(pdev); 5867 5868 /* 5869 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5870 */ 5871 } 5872 5873 /************************************************************************** 5874 * qla2x00_do_dpc 5875 * This kernel thread is a task that is schedule by the interrupt handler 5876 * to perform the background processing for interrupts. 5877 * 5878 * Notes: 5879 * This task always run in the context of a kernel thread. It 5880 * is kick-off by the driver's detect code and starts up 5881 * up one per adapter. It immediately goes to sleep and waits for 5882 * some fibre event. When either the interrupt handler or 5883 * the timer routine detects a event it will one of the task 5884 * bits then wake us up. 5885 **************************************************************************/ 5886 static int 5887 qla2x00_do_dpc(void *data) 5888 { 5889 scsi_qla_host_t *base_vha; 5890 struct qla_hw_data *ha; 5891 uint32_t online; 5892 struct qla_qpair *qpair; 5893 5894 ha = (struct qla_hw_data *)data; 5895 base_vha = pci_get_drvdata(ha->pdev); 5896 5897 set_user_nice(current, MIN_NICE); 5898 5899 set_current_state(TASK_INTERRUPTIBLE); 5900 while (!kthread_should_stop()) { 5901 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5902 "DPC handler sleeping.\n"); 5903 5904 schedule(); 5905 5906 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5907 goto end_loop; 5908 5909 if (ha->flags.eeh_busy) { 5910 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5911 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5912 goto end_loop; 5913 } 5914 5915 ha->dpc_active = 1; 5916 5917 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5918 "DPC handler waking up, dpc_flags=0x%lx.\n", 5919 base_vha->dpc_flags); 5920 5921 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5922 break; 5923 5924 if (IS_P3P_TYPE(ha)) { 5925 if (IS_QLA8044(ha)) { 5926 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5927 &base_vha->dpc_flags)) { 5928 qla8044_idc_lock(ha); 5929 qla8044_wr_direct(base_vha, 5930 QLA8044_CRB_DEV_STATE_INDEX, 5931 QLA8XXX_DEV_FAILED); 5932 qla8044_idc_unlock(ha); 5933 ql_log(ql_log_info, base_vha, 0x4004, 5934 "HW State: FAILED.\n"); 5935 qla8044_device_state_handler(base_vha); 5936 continue; 5937 } 5938 5939 } else { 5940 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5941 &base_vha->dpc_flags)) { 5942 qla82xx_idc_lock(ha); 5943 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5944 QLA8XXX_DEV_FAILED); 5945 qla82xx_idc_unlock(ha); 5946 ql_log(ql_log_info, base_vha, 0x0151, 5947 "HW State: FAILED.\n"); 5948 qla82xx_device_state_handler(base_vha); 5949 continue; 5950 } 5951 } 5952 5953 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5954 &base_vha->dpc_flags)) { 5955 5956 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5957 "FCoE context reset scheduled.\n"); 5958 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5959 &base_vha->dpc_flags))) { 5960 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5961 /* FCoE-ctx reset failed. 5962 * Escalate to chip-reset 5963 */ 5964 set_bit(ISP_ABORT_NEEDED, 5965 &base_vha->dpc_flags); 5966 } 5967 clear_bit(ABORT_ISP_ACTIVE, 5968 &base_vha->dpc_flags); 5969 } 5970 5971 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5972 "FCoE context reset end.\n"); 5973 } 5974 } else if (IS_QLAFX00(ha)) { 5975 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5976 &base_vha->dpc_flags)) { 5977 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5978 "Firmware Reset Recovery\n"); 5979 if (qlafx00_reset_initialize(base_vha)) { 5980 /* Failed. Abort isp later. */ 5981 if (!test_bit(UNLOADING, 5982 &base_vha->dpc_flags)) { 5983 set_bit(ISP_UNRECOVERABLE, 5984 &base_vha->dpc_flags); 5985 ql_dbg(ql_dbg_dpc, base_vha, 5986 0x4021, 5987 "Reset Recovery Failed\n"); 5988 } 5989 } 5990 } 5991 5992 if (test_and_clear_bit(FX00_TARGET_SCAN, 5993 &base_vha->dpc_flags)) { 5994 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5995 "ISPFx00 Target Scan scheduled\n"); 5996 if (qlafx00_rescan_isp(base_vha)) { 5997 if (!test_bit(UNLOADING, 5998 &base_vha->dpc_flags)) 5999 set_bit(ISP_UNRECOVERABLE, 6000 &base_vha->dpc_flags); 6001 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6002 "ISPFx00 Target Scan Failed\n"); 6003 } 6004 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6005 "ISPFx00 Target Scan End\n"); 6006 } 6007 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6008 &base_vha->dpc_flags)) { 6009 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6010 "ISPFx00 Host Info resend scheduled\n"); 6011 qlafx00_fx_disc(base_vha, 6012 &base_vha->hw->mr.fcport, 6013 FXDISC_REG_HOST_INFO); 6014 } 6015 } 6016 6017 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6018 &base_vha->dpc_flags) && 6019 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6020 qla24xx_detect_sfp(base_vha); 6021 6022 if (ha->flags.detected_lr_sfp != 6023 ha->flags.using_lr_setting) 6024 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6025 } 6026 6027 if (test_and_clear_bit(ISP_ABORT_NEEDED, 6028 &base_vha->dpc_flags)) { 6029 6030 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6031 "ISP abort scheduled.\n"); 6032 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6033 &base_vha->dpc_flags))) { 6034 6035 if (ha->isp_ops->abort_isp(base_vha)) { 6036 /* failed. retry later */ 6037 set_bit(ISP_ABORT_NEEDED, 6038 &base_vha->dpc_flags); 6039 } 6040 clear_bit(ABORT_ISP_ACTIVE, 6041 &base_vha->dpc_flags); 6042 } 6043 6044 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6045 "ISP abort end.\n"); 6046 } 6047 6048 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6049 &base_vha->dpc_flags)) { 6050 qla2x00_update_fcports(base_vha); 6051 } 6052 6053 if (IS_QLAFX00(ha)) 6054 goto loop_resync_check; 6055 6056 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6057 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6058 "Quiescence mode scheduled.\n"); 6059 if (IS_P3P_TYPE(ha)) { 6060 if (IS_QLA82XX(ha)) 6061 qla82xx_device_state_handler(base_vha); 6062 if (IS_QLA8044(ha)) 6063 qla8044_device_state_handler(base_vha); 6064 clear_bit(ISP_QUIESCE_NEEDED, 6065 &base_vha->dpc_flags); 6066 if (!ha->flags.quiesce_owner) { 6067 qla2x00_perform_loop_resync(base_vha); 6068 if (IS_QLA82XX(ha)) { 6069 qla82xx_idc_lock(ha); 6070 qla82xx_clear_qsnt_ready( 6071 base_vha); 6072 qla82xx_idc_unlock(ha); 6073 } else if (IS_QLA8044(ha)) { 6074 qla8044_idc_lock(ha); 6075 qla8044_clear_qsnt_ready( 6076 base_vha); 6077 qla8044_idc_unlock(ha); 6078 } 6079 } 6080 } else { 6081 clear_bit(ISP_QUIESCE_NEEDED, 6082 &base_vha->dpc_flags); 6083 qla2x00_quiesce_io(base_vha); 6084 } 6085 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6086 "Quiescence mode end.\n"); 6087 } 6088 6089 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6090 &base_vha->dpc_flags) && 6091 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6092 6093 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6094 "Reset marker scheduled.\n"); 6095 qla2x00_rst_aen(base_vha); 6096 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6097 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6098 "Reset marker end.\n"); 6099 } 6100 6101 /* Retry each device up to login retry count */ 6102 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6103 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6104 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6105 6106 if (!base_vha->relogin_jif || 6107 time_after_eq(jiffies, base_vha->relogin_jif)) { 6108 base_vha->relogin_jif = jiffies + HZ; 6109 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6110 6111 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6112 "Relogin scheduled.\n"); 6113 qla24xx_post_relogin_work(base_vha); 6114 } 6115 } 6116 loop_resync_check: 6117 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6118 &base_vha->dpc_flags)) { 6119 6120 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6121 "Loop resync scheduled.\n"); 6122 6123 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6124 &base_vha->dpc_flags))) { 6125 6126 qla2x00_loop_resync(base_vha); 6127 6128 clear_bit(LOOP_RESYNC_ACTIVE, 6129 &base_vha->dpc_flags); 6130 } 6131 6132 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6133 "Loop resync end.\n"); 6134 } 6135 6136 if (IS_QLAFX00(ha)) 6137 goto intr_on_check; 6138 6139 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6140 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6141 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6142 qla2xxx_flash_npiv_conf(base_vha); 6143 } 6144 6145 intr_on_check: 6146 if (!ha->interrupts_on) 6147 ha->isp_ops->enable_intrs(ha); 6148 6149 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6150 &base_vha->dpc_flags)) { 6151 if (ha->beacon_blink_led == 1) 6152 ha->isp_ops->beacon_blink(base_vha); 6153 } 6154 6155 /* qpair online check */ 6156 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6157 &base_vha->dpc_flags)) { 6158 if (ha->flags.eeh_busy || 6159 ha->flags.pci_channel_io_perm_failure) 6160 online = 0; 6161 else 6162 online = 1; 6163 6164 mutex_lock(&ha->mq_lock); 6165 list_for_each_entry(qpair, &base_vha->qp_list, 6166 qp_list_elem) 6167 qpair->online = online; 6168 mutex_unlock(&ha->mq_lock); 6169 } 6170 6171 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6172 ql_log(ql_log_info, base_vha, 0xffffff, 6173 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6174 ha->nvme_last_rptd_aen); 6175 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6176 ql_log(ql_log_info, base_vha, 0xffffff, 6177 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6178 ha->nvme_last_rptd_aen); 6179 } 6180 } 6181 6182 if (!IS_QLAFX00(ha)) 6183 qla2x00_do_dpc_all_vps(base_vha); 6184 6185 ha->dpc_active = 0; 6186 end_loop: 6187 set_current_state(TASK_INTERRUPTIBLE); 6188 } /* End of while(1) */ 6189 __set_current_state(TASK_RUNNING); 6190 6191 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6192 "DPC handler exiting.\n"); 6193 6194 /* 6195 * Make sure that nobody tries to wake us up again. 6196 */ 6197 ha->dpc_active = 0; 6198 6199 /* Cleanup any residual CTX SRBs. */ 6200 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6201 6202 return 0; 6203 } 6204 6205 void 6206 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6207 { 6208 struct qla_hw_data *ha = vha->hw; 6209 struct task_struct *t = ha->dpc_thread; 6210 6211 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6212 wake_up_process(t); 6213 } 6214 6215 /* 6216 * qla2x00_rst_aen 6217 * Processes asynchronous reset. 6218 * 6219 * Input: 6220 * ha = adapter block pointer. 6221 */ 6222 static void 6223 qla2x00_rst_aen(scsi_qla_host_t *vha) 6224 { 6225 if (vha->flags.online && !vha->flags.reset_active && 6226 !atomic_read(&vha->loop_down_timer) && 6227 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6228 do { 6229 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6230 6231 /* 6232 * Issue marker command only when we are going to start 6233 * the I/O. 6234 */ 6235 vha->marker_needed = 1; 6236 } while (!atomic_read(&vha->loop_down_timer) && 6237 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6238 } 6239 } 6240 6241 /************************************************************************** 6242 * qla2x00_timer 6243 * 6244 * Description: 6245 * One second timer 6246 * 6247 * Context: Interrupt 6248 ***************************************************************************/ 6249 void 6250 qla2x00_timer(struct timer_list *t) 6251 { 6252 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6253 unsigned long cpu_flags = 0; 6254 int start_dpc = 0; 6255 int index; 6256 srb_t *sp; 6257 uint16_t w; 6258 struct qla_hw_data *ha = vha->hw; 6259 struct req_que *req; 6260 6261 if (ha->flags.eeh_busy) { 6262 ql_dbg(ql_dbg_timer, vha, 0x6000, 6263 "EEH = %d, restarting timer.\n", 6264 ha->flags.eeh_busy); 6265 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6266 return; 6267 } 6268 6269 /* 6270 * Hardware read to raise pending EEH errors during mailbox waits. If 6271 * the read returns -1 then disable the board. 6272 */ 6273 if (!pci_channel_offline(ha->pdev)) { 6274 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6275 qla2x00_check_reg16_for_disconnect(vha, w); 6276 } 6277 6278 /* Make sure qla82xx_watchdog is run only for physical port */ 6279 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6280 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6281 start_dpc++; 6282 if (IS_QLA82XX(ha)) 6283 qla82xx_watchdog(vha); 6284 else if (IS_QLA8044(ha)) 6285 qla8044_watchdog(vha); 6286 } 6287 6288 if (!vha->vp_idx && IS_QLAFX00(ha)) 6289 qlafx00_timer_routine(vha); 6290 6291 /* Loop down handler. */ 6292 if (atomic_read(&vha->loop_down_timer) > 0 && 6293 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6294 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6295 && vha->flags.online) { 6296 6297 if (atomic_read(&vha->loop_down_timer) == 6298 vha->loop_down_abort_time) { 6299 6300 ql_log(ql_log_info, vha, 0x6008, 6301 "Loop down - aborting the queues before time expires.\n"); 6302 6303 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6304 atomic_set(&vha->loop_state, LOOP_DEAD); 6305 6306 /* 6307 * Schedule an ISP abort to return any FCP2-device 6308 * commands. 6309 */ 6310 /* NPIV - scan physical port only */ 6311 if (!vha->vp_idx) { 6312 spin_lock_irqsave(&ha->hardware_lock, 6313 cpu_flags); 6314 req = ha->req_q_map[0]; 6315 for (index = 1; 6316 index < req->num_outstanding_cmds; 6317 index++) { 6318 fc_port_t *sfcp; 6319 6320 sp = req->outstanding_cmds[index]; 6321 if (!sp) 6322 continue; 6323 if (sp->cmd_type != TYPE_SRB) 6324 continue; 6325 if (sp->type != SRB_SCSI_CMD) 6326 continue; 6327 sfcp = sp->fcport; 6328 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6329 continue; 6330 6331 if (IS_QLA82XX(ha)) 6332 set_bit(FCOE_CTX_RESET_NEEDED, 6333 &vha->dpc_flags); 6334 else 6335 set_bit(ISP_ABORT_NEEDED, 6336 &vha->dpc_flags); 6337 break; 6338 } 6339 spin_unlock_irqrestore(&ha->hardware_lock, 6340 cpu_flags); 6341 } 6342 start_dpc++; 6343 } 6344 6345 /* if the loop has been down for 4 minutes, reinit adapter */ 6346 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6347 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6348 ql_log(ql_log_warn, vha, 0x6009, 6349 "Loop down - aborting ISP.\n"); 6350 6351 if (IS_QLA82XX(ha)) 6352 set_bit(FCOE_CTX_RESET_NEEDED, 6353 &vha->dpc_flags); 6354 else 6355 set_bit(ISP_ABORT_NEEDED, 6356 &vha->dpc_flags); 6357 } 6358 } 6359 ql_dbg(ql_dbg_timer, vha, 0x600a, 6360 "Loop down - seconds remaining %d.\n", 6361 atomic_read(&vha->loop_down_timer)); 6362 } 6363 /* Check if beacon LED needs to be blinked for physical host only */ 6364 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6365 /* There is no beacon_blink function for ISP82xx */ 6366 if (!IS_P3P_TYPE(ha)) { 6367 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6368 start_dpc++; 6369 } 6370 } 6371 6372 /* Process any deferred work. */ 6373 if (!list_empty(&vha->work_list)) { 6374 unsigned long flags; 6375 bool q = false; 6376 6377 spin_lock_irqsave(&vha->work_lock, flags); 6378 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6379 q = true; 6380 spin_unlock_irqrestore(&vha->work_lock, flags); 6381 if (q) 6382 queue_work(vha->hw->wq, &vha->iocb_work); 6383 } 6384 6385 /* 6386 * FC-NVME 6387 * see if the active AEN count has changed from what was last reported. 6388 */ 6389 if (!vha->vp_idx && 6390 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6391 ha->zio_mode == QLA_ZIO_MODE_6) { 6392 ql_log(ql_log_info, vha, 0x3002, 6393 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6394 ha->nvme_last_rptd_aen); 6395 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6396 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6397 start_dpc++; 6398 } 6399 6400 /* Schedule the DPC routine if needed */ 6401 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6402 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6403 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6404 start_dpc || 6405 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6406 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6407 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6408 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6409 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6410 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6411 ql_dbg(ql_dbg_timer, vha, 0x600b, 6412 "isp_abort_needed=%d loop_resync_needed=%d " 6413 "fcport_update_needed=%d start_dpc=%d " 6414 "reset_marker_needed=%d", 6415 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6416 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6417 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6418 start_dpc, 6419 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6420 ql_dbg(ql_dbg_timer, vha, 0x600c, 6421 "beacon_blink_needed=%d isp_unrecoverable=%d " 6422 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6423 "relogin_needed=%d.\n", 6424 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6425 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6426 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6427 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6428 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6429 qla2xxx_wake_dpc(vha); 6430 } 6431 6432 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6433 } 6434 6435 /* Firmware interface routines. */ 6436 6437 #define FW_BLOBS 11 6438 #define FW_ISP21XX 0 6439 #define FW_ISP22XX 1 6440 #define FW_ISP2300 2 6441 #define FW_ISP2322 3 6442 #define FW_ISP24XX 4 6443 #define FW_ISP25XX 5 6444 #define FW_ISP81XX 6 6445 #define FW_ISP82XX 7 6446 #define FW_ISP2031 8 6447 #define FW_ISP8031 9 6448 #define FW_ISP27XX 10 6449 6450 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6451 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6452 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6453 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6454 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6455 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6456 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6457 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6458 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6459 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6460 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6461 6462 6463 static DEFINE_MUTEX(qla_fw_lock); 6464 6465 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6466 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6467 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6468 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6469 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6470 { .name = FW_FILE_ISP24XX, }, 6471 { .name = FW_FILE_ISP25XX, }, 6472 { .name = FW_FILE_ISP81XX, }, 6473 { .name = FW_FILE_ISP82XX, }, 6474 { .name = FW_FILE_ISP2031, }, 6475 { .name = FW_FILE_ISP8031, }, 6476 { .name = FW_FILE_ISP27XX, }, 6477 }; 6478 6479 struct fw_blob * 6480 qla2x00_request_firmware(scsi_qla_host_t *vha) 6481 { 6482 struct qla_hw_data *ha = vha->hw; 6483 struct fw_blob *blob; 6484 6485 if (IS_QLA2100(ha)) { 6486 blob = &qla_fw_blobs[FW_ISP21XX]; 6487 } else if (IS_QLA2200(ha)) { 6488 blob = &qla_fw_blobs[FW_ISP22XX]; 6489 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6490 blob = &qla_fw_blobs[FW_ISP2300]; 6491 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6492 blob = &qla_fw_blobs[FW_ISP2322]; 6493 } else if (IS_QLA24XX_TYPE(ha)) { 6494 blob = &qla_fw_blobs[FW_ISP24XX]; 6495 } else if (IS_QLA25XX(ha)) { 6496 blob = &qla_fw_blobs[FW_ISP25XX]; 6497 } else if (IS_QLA81XX(ha)) { 6498 blob = &qla_fw_blobs[FW_ISP81XX]; 6499 } else if (IS_QLA82XX(ha)) { 6500 blob = &qla_fw_blobs[FW_ISP82XX]; 6501 } else if (IS_QLA2031(ha)) { 6502 blob = &qla_fw_blobs[FW_ISP2031]; 6503 } else if (IS_QLA8031(ha)) { 6504 blob = &qla_fw_blobs[FW_ISP8031]; 6505 } else if (IS_QLA27XX(ha)) { 6506 blob = &qla_fw_blobs[FW_ISP27XX]; 6507 } else { 6508 return NULL; 6509 } 6510 6511 mutex_lock(&qla_fw_lock); 6512 if (blob->fw) 6513 goto out; 6514 6515 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6516 ql_log(ql_log_warn, vha, 0x0063, 6517 "Failed to load firmware image (%s).\n", blob->name); 6518 blob->fw = NULL; 6519 blob = NULL; 6520 goto out; 6521 } 6522 6523 out: 6524 mutex_unlock(&qla_fw_lock); 6525 return blob; 6526 } 6527 6528 static void 6529 qla2x00_release_firmware(void) 6530 { 6531 int idx; 6532 6533 mutex_lock(&qla_fw_lock); 6534 for (idx = 0; idx < FW_BLOBS; idx++) 6535 release_firmware(qla_fw_blobs[idx].fw); 6536 mutex_unlock(&qla_fw_lock); 6537 } 6538 6539 static pci_ers_result_t 6540 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6541 { 6542 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6543 struct qla_hw_data *ha = vha->hw; 6544 6545 ql_dbg(ql_dbg_aer, vha, 0x9000, 6546 "PCI error detected, state %x.\n", state); 6547 6548 if (!atomic_read(&pdev->enable_cnt)) { 6549 ql_log(ql_log_info, vha, 0xffff, 6550 "PCI device is disabled,state %x\n", state); 6551 return PCI_ERS_RESULT_NEED_RESET; 6552 } 6553 6554 switch (state) { 6555 case pci_channel_io_normal: 6556 ha->flags.eeh_busy = 0; 6557 if (ql2xmqsupport || ql2xnvmeenable) { 6558 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6559 qla2xxx_wake_dpc(vha); 6560 } 6561 return PCI_ERS_RESULT_CAN_RECOVER; 6562 case pci_channel_io_frozen: 6563 ha->flags.eeh_busy = 1; 6564 /* For ISP82XX complete any pending mailbox cmd */ 6565 if (IS_QLA82XX(ha)) { 6566 ha->flags.isp82xx_fw_hung = 1; 6567 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6568 qla82xx_clear_pending_mbx(vha); 6569 } 6570 qla2x00_free_irqs(vha); 6571 pci_disable_device(pdev); 6572 /* Return back all IOs */ 6573 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6574 if (ql2xmqsupport || ql2xnvmeenable) { 6575 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6576 qla2xxx_wake_dpc(vha); 6577 } 6578 return PCI_ERS_RESULT_NEED_RESET; 6579 case pci_channel_io_perm_failure: 6580 ha->flags.pci_channel_io_perm_failure = 1; 6581 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6582 if (ql2xmqsupport || ql2xnvmeenable) { 6583 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6584 qla2xxx_wake_dpc(vha); 6585 } 6586 return PCI_ERS_RESULT_DISCONNECT; 6587 } 6588 return PCI_ERS_RESULT_NEED_RESET; 6589 } 6590 6591 static pci_ers_result_t 6592 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6593 { 6594 int risc_paused = 0; 6595 uint32_t stat; 6596 unsigned long flags; 6597 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6598 struct qla_hw_data *ha = base_vha->hw; 6599 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6600 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6601 6602 if (IS_QLA82XX(ha)) 6603 return PCI_ERS_RESULT_RECOVERED; 6604 6605 spin_lock_irqsave(&ha->hardware_lock, flags); 6606 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6607 stat = RD_REG_DWORD(®->hccr); 6608 if (stat & HCCR_RISC_PAUSE) 6609 risc_paused = 1; 6610 } else if (IS_QLA23XX(ha)) { 6611 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6612 if (stat & HSR_RISC_PAUSED) 6613 risc_paused = 1; 6614 } else if (IS_FWI2_CAPABLE(ha)) { 6615 stat = RD_REG_DWORD(®24->host_status); 6616 if (stat & HSRX_RISC_PAUSED) 6617 risc_paused = 1; 6618 } 6619 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6620 6621 if (risc_paused) { 6622 ql_log(ql_log_info, base_vha, 0x9003, 6623 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6624 ha->isp_ops->fw_dump(base_vha, 0); 6625 6626 return PCI_ERS_RESULT_NEED_RESET; 6627 } else 6628 return PCI_ERS_RESULT_RECOVERED; 6629 } 6630 6631 static uint32_t 6632 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6633 { 6634 uint32_t rval = QLA_FUNCTION_FAILED; 6635 uint32_t drv_active = 0; 6636 struct qla_hw_data *ha = base_vha->hw; 6637 int fn; 6638 struct pci_dev *other_pdev = NULL; 6639 6640 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6641 "Entered %s.\n", __func__); 6642 6643 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6644 6645 if (base_vha->flags.online) { 6646 /* Abort all outstanding commands, 6647 * so as to be requeued later */ 6648 qla2x00_abort_isp_cleanup(base_vha); 6649 } 6650 6651 6652 fn = PCI_FUNC(ha->pdev->devfn); 6653 while (fn > 0) { 6654 fn--; 6655 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6656 "Finding pci device at function = 0x%x.\n", fn); 6657 other_pdev = 6658 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6659 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6660 fn)); 6661 6662 if (!other_pdev) 6663 continue; 6664 if (atomic_read(&other_pdev->enable_cnt)) { 6665 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6666 "Found PCI func available and enable at 0x%x.\n", 6667 fn); 6668 pci_dev_put(other_pdev); 6669 break; 6670 } 6671 pci_dev_put(other_pdev); 6672 } 6673 6674 if (!fn) { 6675 /* Reset owner */ 6676 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6677 "This devfn is reset owner = 0x%x.\n", 6678 ha->pdev->devfn); 6679 qla82xx_idc_lock(ha); 6680 6681 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6682 QLA8XXX_DEV_INITIALIZING); 6683 6684 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6685 QLA82XX_IDC_VERSION); 6686 6687 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6688 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6689 "drv_active = 0x%x.\n", drv_active); 6690 6691 qla82xx_idc_unlock(ha); 6692 /* Reset if device is not already reset 6693 * drv_active would be 0 if a reset has already been done 6694 */ 6695 if (drv_active) 6696 rval = qla82xx_start_firmware(base_vha); 6697 else 6698 rval = QLA_SUCCESS; 6699 qla82xx_idc_lock(ha); 6700 6701 if (rval != QLA_SUCCESS) { 6702 ql_log(ql_log_info, base_vha, 0x900b, 6703 "HW State: FAILED.\n"); 6704 qla82xx_clear_drv_active(ha); 6705 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6706 QLA8XXX_DEV_FAILED); 6707 } else { 6708 ql_log(ql_log_info, base_vha, 0x900c, 6709 "HW State: READY.\n"); 6710 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6711 QLA8XXX_DEV_READY); 6712 qla82xx_idc_unlock(ha); 6713 ha->flags.isp82xx_fw_hung = 0; 6714 rval = qla82xx_restart_isp(base_vha); 6715 qla82xx_idc_lock(ha); 6716 /* Clear driver state register */ 6717 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6718 qla82xx_set_drv_active(base_vha); 6719 } 6720 qla82xx_idc_unlock(ha); 6721 } else { 6722 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6723 "This devfn is not reset owner = 0x%x.\n", 6724 ha->pdev->devfn); 6725 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6726 QLA8XXX_DEV_READY)) { 6727 ha->flags.isp82xx_fw_hung = 0; 6728 rval = qla82xx_restart_isp(base_vha); 6729 qla82xx_idc_lock(ha); 6730 qla82xx_set_drv_active(base_vha); 6731 qla82xx_idc_unlock(ha); 6732 } 6733 } 6734 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6735 6736 return rval; 6737 } 6738 6739 static pci_ers_result_t 6740 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6741 { 6742 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6743 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6744 struct qla_hw_data *ha = base_vha->hw; 6745 struct rsp_que *rsp; 6746 int rc, retries = 10; 6747 6748 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6749 "Slot Reset.\n"); 6750 6751 /* Workaround: qla2xxx driver which access hardware earlier 6752 * needs error state to be pci_channel_io_online. 6753 * Otherwise mailbox command timesout. 6754 */ 6755 pdev->error_state = pci_channel_io_normal; 6756 6757 pci_restore_state(pdev); 6758 6759 /* pci_restore_state() clears the saved_state flag of the device 6760 * save restored state which resets saved_state flag 6761 */ 6762 pci_save_state(pdev); 6763 6764 if (ha->mem_only) 6765 rc = pci_enable_device_mem(pdev); 6766 else 6767 rc = pci_enable_device(pdev); 6768 6769 if (rc) { 6770 ql_log(ql_log_warn, base_vha, 0x9005, 6771 "Can't re-enable PCI device after reset.\n"); 6772 goto exit_slot_reset; 6773 } 6774 6775 rsp = ha->rsp_q_map[0]; 6776 if (qla2x00_request_irqs(ha, rsp)) 6777 goto exit_slot_reset; 6778 6779 if (ha->isp_ops->pci_config(base_vha)) 6780 goto exit_slot_reset; 6781 6782 if (IS_QLA82XX(ha)) { 6783 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6784 ret = PCI_ERS_RESULT_RECOVERED; 6785 goto exit_slot_reset; 6786 } else 6787 goto exit_slot_reset; 6788 } 6789 6790 while (ha->flags.mbox_busy && retries--) 6791 msleep(1000); 6792 6793 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6794 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6795 ret = PCI_ERS_RESULT_RECOVERED; 6796 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6797 6798 6799 exit_slot_reset: 6800 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6801 "slot_reset return %x.\n", ret); 6802 6803 return ret; 6804 } 6805 6806 static void 6807 qla2xxx_pci_resume(struct pci_dev *pdev) 6808 { 6809 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6810 struct qla_hw_data *ha = base_vha->hw; 6811 int ret; 6812 6813 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6814 "pci_resume.\n"); 6815 6816 ret = qla2x00_wait_for_hba_online(base_vha); 6817 if (ret != QLA_SUCCESS) { 6818 ql_log(ql_log_fatal, base_vha, 0x9002, 6819 "The device failed to resume I/O from slot/link_reset.\n"); 6820 } 6821 6822 pci_cleanup_aer_uncorrect_error_status(pdev); 6823 6824 ha->flags.eeh_busy = 0; 6825 } 6826 6827 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6828 { 6829 int rc; 6830 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6831 6832 if (USER_CTRL_IRQ(vha->hw)) 6833 rc = blk_mq_map_queues(&shost->tag_set); 6834 else 6835 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); 6836 return rc; 6837 } 6838 6839 static const struct pci_error_handlers qla2xxx_err_handler = { 6840 .error_detected = qla2xxx_pci_error_detected, 6841 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6842 .slot_reset = qla2xxx_pci_slot_reset, 6843 .resume = qla2xxx_pci_resume, 6844 }; 6845 6846 static struct pci_device_id qla2xxx_pci_tbl[] = { 6847 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6848 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6849 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6850 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6869 { 0 }, 6870 }; 6871 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6872 6873 static struct pci_driver qla2xxx_pci_driver = { 6874 .name = QLA2XXX_DRIVER_NAME, 6875 .driver = { 6876 .owner = THIS_MODULE, 6877 }, 6878 .id_table = qla2xxx_pci_tbl, 6879 .probe = qla2x00_probe_one, 6880 .remove = qla2x00_remove_one, 6881 .shutdown = qla2x00_shutdown, 6882 .err_handler = &qla2xxx_err_handler, 6883 }; 6884 6885 static const struct file_operations apidev_fops = { 6886 .owner = THIS_MODULE, 6887 .llseek = noop_llseek, 6888 }; 6889 6890 /** 6891 * qla2x00_module_init - Module initialization. 6892 **/ 6893 static int __init 6894 qla2x00_module_init(void) 6895 { 6896 int ret = 0; 6897 6898 /* Allocate cache for SRBs. */ 6899 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6900 SLAB_HWCACHE_ALIGN, NULL); 6901 if (srb_cachep == NULL) { 6902 ql_log(ql_log_fatal, NULL, 0x0001, 6903 "Unable to allocate SRB cache...Failing load!.\n"); 6904 return -ENOMEM; 6905 } 6906 6907 /* Initialize target kmem_cache and mem_pools */ 6908 ret = qlt_init(); 6909 if (ret < 0) { 6910 kmem_cache_destroy(srb_cachep); 6911 return ret; 6912 } else if (ret > 0) { 6913 /* 6914 * If initiator mode is explictly disabled by qlt_init(), 6915 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6916 * performing scsi_scan_target() during LOOP UP event. 6917 */ 6918 qla2xxx_transport_functions.disable_target_scan = 1; 6919 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6920 } 6921 6922 /* Derive version string. */ 6923 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6924 if (ql2xextended_error_logging) 6925 strcat(qla2x00_version_str, "-debug"); 6926 if (ql2xextended_error_logging == 1) 6927 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6928 6929 qla2xxx_transport_template = 6930 fc_attach_transport(&qla2xxx_transport_functions); 6931 if (!qla2xxx_transport_template) { 6932 kmem_cache_destroy(srb_cachep); 6933 ql_log(ql_log_fatal, NULL, 0x0002, 6934 "fc_attach_transport failed...Failing load!.\n"); 6935 qlt_exit(); 6936 return -ENODEV; 6937 } 6938 6939 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6940 if (apidev_major < 0) { 6941 ql_log(ql_log_fatal, NULL, 0x0003, 6942 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6943 } 6944 6945 qla2xxx_transport_vport_template = 6946 fc_attach_transport(&qla2xxx_transport_vport_functions); 6947 if (!qla2xxx_transport_vport_template) { 6948 kmem_cache_destroy(srb_cachep); 6949 qlt_exit(); 6950 fc_release_transport(qla2xxx_transport_template); 6951 ql_log(ql_log_fatal, NULL, 0x0004, 6952 "fc_attach_transport vport failed...Failing load!.\n"); 6953 return -ENODEV; 6954 } 6955 ql_log(ql_log_info, NULL, 0x0005, 6956 "QLogic Fibre Channel HBA Driver: %s.\n", 6957 qla2x00_version_str); 6958 ret = pci_register_driver(&qla2xxx_pci_driver); 6959 if (ret) { 6960 kmem_cache_destroy(srb_cachep); 6961 qlt_exit(); 6962 fc_release_transport(qla2xxx_transport_template); 6963 fc_release_transport(qla2xxx_transport_vport_template); 6964 ql_log(ql_log_fatal, NULL, 0x0006, 6965 "pci_register_driver failed...ret=%d Failing load!.\n", 6966 ret); 6967 } 6968 return ret; 6969 } 6970 6971 /** 6972 * qla2x00_module_exit - Module cleanup. 6973 **/ 6974 static void __exit 6975 qla2x00_module_exit(void) 6976 { 6977 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6978 pci_unregister_driver(&qla2xxx_pci_driver); 6979 qla2x00_release_firmware(); 6980 kmem_cache_destroy(srb_cachep); 6981 qlt_exit(); 6982 if (ctx_cachep) 6983 kmem_cache_destroy(ctx_cachep); 6984 fc_release_transport(qla2xxx_transport_template); 6985 fc_release_transport(qla2xxx_transport_vport_template); 6986 } 6987 6988 module_init(qla2x00_module_init); 6989 module_exit(qla2x00_module_exit); 6990 6991 MODULE_AUTHOR("QLogic Corporation"); 6992 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6993 MODULE_LICENSE("GPL"); 6994 MODULE_VERSION(QLA2XXX_VERSION); 6995 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6996 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6997 MODULE_FIRMWARE(FW_FILE_ISP2300); 6998 MODULE_FIRMWARE(FW_FILE_ISP2322); 6999 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7000 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7001