1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 307 struct scsi_host_template qla2xxx_driver_template = { 308 .module = THIS_MODULE, 309 .name = QLA2XXX_DRIVER_NAME, 310 .queuecommand = qla2xxx_queuecommand, 311 312 .eh_timed_out = fc_eh_timed_out, 313 .eh_abort_handler = qla2xxx_eh_abort, 314 .eh_device_reset_handler = qla2xxx_eh_device_reset, 315 .eh_target_reset_handler = qla2xxx_eh_target_reset, 316 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 317 .eh_host_reset_handler = qla2xxx_eh_host_reset, 318 319 .slave_configure = qla2xxx_slave_configure, 320 321 .slave_alloc = qla2xxx_slave_alloc, 322 .slave_destroy = qla2xxx_slave_destroy, 323 .scan_finished = qla2xxx_scan_finished, 324 .scan_start = qla2xxx_scan_start, 325 .change_queue_depth = scsi_change_queue_depth, 326 .map_queues = qla2xxx_map_queues, 327 .this_id = -1, 328 .cmd_per_lun = 3, 329 .use_clustering = ENABLE_CLUSTERING, 330 .sg_tablesize = SG_ALL, 331 332 .max_sectors = 0xFFFF, 333 .shost_attrs = qla2x00_host_attrs, 334 335 .supported_mode = MODE_INITIATOR, 336 .track_queue_depth = 1, 337 }; 338 339 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 340 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 341 342 /* TODO Convert to inlines 343 * 344 * Timer routines 345 */ 346 347 __inline__ void 348 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 349 { 350 timer_setup(&vha->timer, qla2x00_timer, 0); 351 vha->timer.expires = jiffies + interval * HZ; 352 add_timer(&vha->timer); 353 vha->timer_active = 1; 354 } 355 356 static inline void 357 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 358 { 359 /* Currently used for 82XX only. */ 360 if (vha->device_flags & DFLG_DEV_FAILED) { 361 ql_dbg(ql_dbg_timer, vha, 0x600d, 362 "Device in a failed state, returning.\n"); 363 return; 364 } 365 366 mod_timer(&vha->timer, jiffies + interval * HZ); 367 } 368 369 static __inline__ void 370 qla2x00_stop_timer(scsi_qla_host_t *vha) 371 { 372 del_timer_sync(&vha->timer); 373 vha->timer_active = 0; 374 } 375 376 static int qla2x00_do_dpc(void *data); 377 378 static void qla2x00_rst_aen(scsi_qla_host_t *); 379 380 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 381 struct req_que **, struct rsp_que **); 382 static void qla2x00_free_fw_dump(struct qla_hw_data *); 383 static void qla2x00_mem_free(struct qla_hw_data *); 384 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 385 struct qla_qpair *qpair); 386 387 /* -------------------------------------------------------------------------- */ 388 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 389 struct rsp_que *rsp) 390 { 391 struct qla_hw_data *ha = vha->hw; 392 rsp->qpair = ha->base_qpair; 393 rsp->req = req; 394 ha->base_qpair->req = req; 395 ha->base_qpair->rsp = rsp; 396 ha->base_qpair->vha = vha; 397 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 398 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 399 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 400 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 401 ha->base_qpair->enable_class_2 = ql2xenableclass2; 402 /* init qpair to this cpu. Will adjust at run time. */ 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 404 ha->base_qpair->pdev = ha->pdev; 405 406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 408 } 409 410 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 414 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 415 GFP_KERNEL); 416 if (!ha->req_q_map) { 417 ql_log(ql_log_fatal, vha, 0x003b, 418 "Unable to allocate memory for request queue ptrs.\n"); 419 goto fail_req_map; 420 } 421 422 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 423 GFP_KERNEL); 424 if (!ha->rsp_q_map) { 425 ql_log(ql_log_fatal, vha, 0x003c, 426 "Unable to allocate memory for response queue ptrs.\n"); 427 goto fail_rsp_map; 428 } 429 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 431 if (ha->base_qpair == NULL) { 432 ql_log(ql_log_warn, vha, 0x00e0, 433 "Failed to allocate base queue pair memory.\n"); 434 goto fail_base_qpair; 435 } 436 437 qla_init_base_qpair(vha, req, rsp); 438 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 441 GFP_KERNEL); 442 if (!ha->queue_pair_map) { 443 ql_log(ql_log_fatal, vha, 0x0180, 444 "Unable to allocate memory for queue pair ptrs.\n"); 445 goto fail_qpair_map; 446 } 447 } 448 449 /* 450 * Make sure we record at least the request and response queue zero in 451 * case we need to free them if part of the probe fails. 452 */ 453 ha->rsp_q_map[0] = rsp; 454 ha->req_q_map[0] = req; 455 set_bit(0, ha->rsp_qid_map); 456 set_bit(0, ha->req_qid_map); 457 return 0; 458 459 fail_qpair_map: 460 kfree(ha->base_qpair); 461 ha->base_qpair = NULL; 462 fail_base_qpair: 463 kfree(ha->rsp_q_map); 464 ha->rsp_q_map = NULL; 465 fail_rsp_map: 466 kfree(ha->req_q_map); 467 ha->req_q_map = NULL; 468 fail_req_map: 469 return -ENOMEM; 470 } 471 472 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 473 { 474 if (IS_QLAFX00(ha)) { 475 if (req && req->ring_fx00) 476 dma_free_coherent(&ha->pdev->dev, 477 (req->length_fx00 + 1) * sizeof(request_t), 478 req->ring_fx00, req->dma_fx00); 479 } else if (req && req->ring) 480 dma_free_coherent(&ha->pdev->dev, 481 (req->length + 1) * sizeof(request_t), 482 req->ring, req->dma); 483 484 if (req) 485 kfree(req->outstanding_cmds); 486 487 kfree(req); 488 } 489 490 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 491 { 492 if (IS_QLAFX00(ha)) { 493 if (rsp && rsp->ring_fx00) 494 dma_free_coherent(&ha->pdev->dev, 495 (rsp->length_fx00 + 1) * sizeof(request_t), 496 rsp->ring_fx00, rsp->dma_fx00); 497 } else if (rsp && rsp->ring) { 498 dma_free_coherent(&ha->pdev->dev, 499 (rsp->length + 1) * sizeof(response_t), 500 rsp->ring, rsp->dma); 501 } 502 kfree(rsp); 503 } 504 505 static void qla2x00_free_queues(struct qla_hw_data *ha) 506 { 507 struct req_que *req; 508 struct rsp_que *rsp; 509 int cnt; 510 unsigned long flags; 511 512 if (ha->queue_pair_map) { 513 kfree(ha->queue_pair_map); 514 ha->queue_pair_map = NULL; 515 } 516 if (ha->base_qpair) { 517 kfree(ha->base_qpair); 518 ha->base_qpair = NULL; 519 } 520 521 spin_lock_irqsave(&ha->hardware_lock, flags); 522 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 523 if (!test_bit(cnt, ha->req_qid_map)) 524 continue; 525 526 req = ha->req_q_map[cnt]; 527 clear_bit(cnt, ha->req_qid_map); 528 ha->req_q_map[cnt] = NULL; 529 530 spin_unlock_irqrestore(&ha->hardware_lock, flags); 531 qla2x00_free_req_que(ha, req); 532 spin_lock_irqsave(&ha->hardware_lock, flags); 533 } 534 spin_unlock_irqrestore(&ha->hardware_lock, flags); 535 536 kfree(ha->req_q_map); 537 ha->req_q_map = NULL; 538 539 540 spin_lock_irqsave(&ha->hardware_lock, flags); 541 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 542 if (!test_bit(cnt, ha->rsp_qid_map)) 543 continue; 544 545 rsp = ha->rsp_q_map[cnt]; 546 clear_bit(cnt, ha->rsp_qid_map); 547 ha->rsp_q_map[cnt] = NULL; 548 spin_unlock_irqrestore(&ha->hardware_lock, flags); 549 qla2x00_free_rsp_que(ha, rsp); 550 spin_lock_irqsave(&ha->hardware_lock, flags); 551 } 552 spin_unlock_irqrestore(&ha->hardware_lock, flags); 553 554 kfree(ha->rsp_q_map); 555 ha->rsp_q_map = NULL; 556 } 557 558 static char * 559 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 560 { 561 struct qla_hw_data *ha = vha->hw; 562 static char *pci_bus_modes[] = { 563 "33", "66", "100", "133", 564 }; 565 uint16_t pci_bus; 566 567 strcpy(str, "PCI"); 568 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 569 if (pci_bus) { 570 strcat(str, "-X ("); 571 strcat(str, pci_bus_modes[pci_bus]); 572 } else { 573 pci_bus = (ha->pci_attr & BIT_8) >> 8; 574 strcat(str, " ("); 575 strcat(str, pci_bus_modes[pci_bus]); 576 } 577 strcat(str, " MHz)"); 578 579 return (str); 580 } 581 582 static char * 583 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 584 { 585 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 586 struct qla_hw_data *ha = vha->hw; 587 uint32_t pci_bus; 588 589 if (pci_is_pcie(ha->pdev)) { 590 char lwstr[6]; 591 uint32_t lstat, lspeed, lwidth; 592 593 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 594 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 595 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 596 597 strcpy(str, "PCIe ("); 598 switch (lspeed) { 599 case 1: 600 strcat(str, "2.5GT/s "); 601 break; 602 case 2: 603 strcat(str, "5.0GT/s "); 604 break; 605 case 3: 606 strcat(str, "8.0GT/s "); 607 break; 608 default: 609 strcat(str, "<unknown> "); 610 break; 611 } 612 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 613 strcat(str, lwstr); 614 615 return str; 616 } 617 618 strcpy(str, "PCI"); 619 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 620 if (pci_bus == 0 || pci_bus == 8) { 621 strcat(str, " ("); 622 strcat(str, pci_bus_modes[pci_bus >> 3]); 623 } else { 624 strcat(str, "-X "); 625 if (pci_bus & BIT_2) 626 strcat(str, "Mode 2"); 627 else 628 strcat(str, "Mode 1"); 629 strcat(str, " ("); 630 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 631 } 632 strcat(str, " MHz)"); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void 686 qla2x00_sp_free_dma(void *ptr) 687 { 688 srb_t *sp = ptr; 689 struct qla_hw_data *ha = sp->vha->hw; 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 691 void *ctx = GET_CMD_CTX_SP(sp); 692 693 if (sp->flags & SRB_DMA_VALID) { 694 scsi_dma_unmap(cmd); 695 sp->flags &= ~SRB_DMA_VALID; 696 } 697 698 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 699 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 700 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 701 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 702 } 703 704 if (!ctx) 705 goto end; 706 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 708 /* List assured to be having elements */ 709 qla2x00_clean_dsd_pool(ha, ctx); 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 711 } 712 713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 714 struct crc_context *ctx0 = ctx; 715 716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 718 } 719 720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 721 struct ct6_dsd *ctx1 = ctx; 722 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 724 ctx1->fcp_cmnd_dma); 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 728 mempool_free(ctx1, ha->ctx_mempool); 729 } 730 731 end: 732 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 733 CMD_SP(cmd) = NULL; 734 qla2x00_rel_sp(sp); 735 } 736 } 737 738 void 739 qla2x00_sp_compl(void *ptr, int res) 740 { 741 srb_t *sp = ptr; 742 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 743 744 cmd->result = res; 745 746 if (atomic_read(&sp->ref_count) == 0) { 747 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 748 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 749 sp, GET_CMD_SP(sp)); 750 if (ql2xextended_error_logging & ql_dbg_io) 751 WARN_ON(atomic_read(&sp->ref_count) == 0); 752 return; 753 } 754 if (!atomic_dec_and_test(&sp->ref_count)) 755 return; 756 757 sp->free(sp); 758 cmd->scsi_done(cmd); 759 } 760 761 void 762 qla2xxx_qpair_sp_free_dma(void *ptr) 763 { 764 srb_t *sp = (srb_t *)ptr; 765 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 766 struct qla_hw_data *ha = sp->fcport->vha->hw; 767 void *ctx = GET_CMD_CTX_SP(sp); 768 769 if (sp->flags & SRB_DMA_VALID) { 770 scsi_dma_unmap(cmd); 771 sp->flags &= ~SRB_DMA_VALID; 772 } 773 774 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 775 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 776 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 777 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 778 } 779 780 if (!ctx) 781 goto end; 782 783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 784 /* List assured to be having elements */ 785 qla2x00_clean_dsd_pool(ha, ctx); 786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 787 } 788 789 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 790 struct crc_context *ctx0 = ctx; 791 792 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 793 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 794 } 795 796 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 797 struct ct6_dsd *ctx1 = ctx; 798 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 799 ctx1->fcp_cmnd_dma); 800 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 801 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 802 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 803 mempool_free(ctx1, ha->ctx_mempool); 804 } 805 end: 806 CMD_SP(cmd) = NULL; 807 qla2xxx_rel_qpair_sp(sp->qpair, sp); 808 } 809 810 void 811 qla2xxx_qpair_sp_compl(void *ptr, int res) 812 { 813 srb_t *sp = ptr; 814 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 815 816 cmd->result = res; 817 818 if (atomic_read(&sp->ref_count) == 0) { 819 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 820 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 821 sp, GET_CMD_SP(sp)); 822 if (ql2xextended_error_logging & ql_dbg_io) 823 WARN_ON(atomic_read(&sp->ref_count) == 0); 824 return; 825 } 826 if (!atomic_dec_and_test(&sp->ref_count)) 827 return; 828 829 sp->free(sp); 830 cmd->scsi_done(cmd); 831 } 832 833 /* If we are SP1 here, we need to still take and release the host_lock as SP1 834 * does not have the changes necessary to avoid taking host->host_lock. 835 */ 836 static int 837 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 838 { 839 scsi_qla_host_t *vha = shost_priv(host); 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 842 struct qla_hw_data *ha = vha->hw; 843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 844 srb_t *sp; 845 int rval; 846 struct qla_qpair *qpair = NULL; 847 uint32_t tag; 848 uint16_t hwq; 849 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 851 cmd->result = DID_NO_CONNECT << 16; 852 goto qc24_fail_command; 853 } 854 855 if (ha->mqenable) { 856 if (shost_use_blk_mq(vha->host)) { 857 tag = blk_mq_unique_tag(cmd->request); 858 hwq = blk_mq_unique_tag_to_hwq(tag); 859 qpair = ha->queue_pair_map[hwq]; 860 } else if (vha->vp_idx && vha->qpair) { 861 qpair = vha->qpair; 862 } 863 864 if (qpair) 865 return qla2xxx_mqueuecommand(host, cmd, qpair); 866 } 867 868 if (ha->flags.eeh_busy) { 869 if (ha->flags.pci_channel_io_perm_failure) { 870 ql_dbg(ql_dbg_aer, vha, 0x9010, 871 "PCI Channel IO permanent failure, exiting " 872 "cmd=%p.\n", cmd); 873 cmd->result = DID_NO_CONNECT << 16; 874 } else { 875 ql_dbg(ql_dbg_aer, vha, 0x9011, 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 877 cmd->result = DID_REQUEUE << 16; 878 } 879 goto qc24_fail_command; 880 } 881 882 rval = fc_remote_port_chkready(rport); 883 if (rval) { 884 cmd->result = rval; 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 887 cmd, rval); 888 goto qc24_fail_command; 889 } 890 891 if (!vha->flags.difdix_supported && 892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 893 ql_dbg(ql_dbg_io, vha, 0x3004, 894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 895 cmd); 896 cmd->result = DID_NO_CONNECT << 16; 897 goto qc24_fail_command; 898 } 899 900 if (!fcport) { 901 cmd->result = DID_NO_CONNECT << 16; 902 goto qc24_fail_command; 903 } 904 905 if (atomic_read(&fcport->state) != FCS_ONLINE) { 906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 908 ql_dbg(ql_dbg_io, vha, 0x3005, 909 "Returning DNC, fcport_state=%d loop_state=%d.\n", 910 atomic_read(&fcport->state), 911 atomic_read(&base_vha->loop_state)); 912 cmd->result = DID_NO_CONNECT << 16; 913 goto qc24_fail_command; 914 } 915 goto qc24_target_busy; 916 } 917 918 /* 919 * Return target busy if we've received a non-zero retry_delay_timer 920 * in a FCP_RSP. 921 */ 922 if (fcport->retry_delay_timestamp == 0) { 923 /* retry delay not set */ 924 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 925 fcport->retry_delay_timestamp = 0; 926 else 927 goto qc24_target_busy; 928 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 930 if (!sp) 931 goto qc24_host_busy; 932 933 sp->u.scmd.cmd = cmd; 934 sp->type = SRB_SCSI_CMD; 935 atomic_set(&sp->ref_count, 1); 936 CMD_SP(cmd) = (void *)sp; 937 sp->free = qla2x00_sp_free_dma; 938 sp->done = qla2x00_sp_compl; 939 940 rval = ha->isp_ops->start_scsi(sp); 941 if (rval != QLA_SUCCESS) { 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 944 goto qc24_host_busy_free_sp; 945 } 946 947 return 0; 948 949 qc24_host_busy_free_sp: 950 sp->free(sp); 951 952 qc24_host_busy: 953 return SCSI_MLQUEUE_HOST_BUSY; 954 955 qc24_target_busy: 956 return SCSI_MLQUEUE_TARGET_BUSY; 957 958 qc24_fail_command: 959 cmd->scsi_done(cmd); 960 961 return 0; 962 } 963 964 /* For MQ supported I/O */ 965 int 966 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 967 struct qla_qpair *qpair) 968 { 969 scsi_qla_host_t *vha = shost_priv(host); 970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 972 struct qla_hw_data *ha = vha->hw; 973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 974 srb_t *sp; 975 int rval; 976 977 rval = fc_remote_port_chkready(rport); 978 if (rval) { 979 cmd->result = rval; 980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 982 cmd, rval); 983 goto qc24_fail_command; 984 } 985 986 if (!fcport) { 987 cmd->result = DID_NO_CONNECT << 16; 988 goto qc24_fail_command; 989 } 990 991 if (atomic_read(&fcport->state) != FCS_ONLINE) { 992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 994 ql_dbg(ql_dbg_io, vha, 0x3077, 995 "Returning DNC, fcport_state=%d loop_state=%d.\n", 996 atomic_read(&fcport->state), 997 atomic_read(&base_vha->loop_state)); 998 cmd->result = DID_NO_CONNECT << 16; 999 goto qc24_fail_command; 1000 } 1001 goto qc24_target_busy; 1002 } 1003 1004 /* 1005 * Return target busy if we've received a non-zero retry_delay_timer 1006 * in a FCP_RSP. 1007 */ 1008 if (fcport->retry_delay_timestamp == 0) { 1009 /* retry delay not set */ 1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1011 fcport->retry_delay_timestamp = 0; 1012 else 1013 goto qc24_target_busy; 1014 1015 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1016 if (!sp) 1017 goto qc24_host_busy; 1018 1019 sp->u.scmd.cmd = cmd; 1020 sp->type = SRB_SCSI_CMD; 1021 atomic_set(&sp->ref_count, 1); 1022 CMD_SP(cmd) = (void *)sp; 1023 sp->free = qla2xxx_qpair_sp_free_dma; 1024 sp->done = qla2xxx_qpair_sp_compl; 1025 sp->qpair = qpair; 1026 1027 rval = ha->isp_ops->start_scsi_mq(sp); 1028 if (rval != QLA_SUCCESS) { 1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1031 if (rval == QLA_INTERFACE_ERROR) 1032 goto qc24_fail_command; 1033 goto qc24_host_busy_free_sp; 1034 } 1035 1036 return 0; 1037 1038 qc24_host_busy_free_sp: 1039 sp->free(sp); 1040 1041 qc24_host_busy: 1042 return SCSI_MLQUEUE_HOST_BUSY; 1043 1044 qc24_target_busy: 1045 return SCSI_MLQUEUE_TARGET_BUSY; 1046 1047 qc24_fail_command: 1048 cmd->scsi_done(cmd); 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * qla2x00_eh_wait_on_command 1055 * Waits for the command to be returned by the Firmware for some 1056 * max time. 1057 * 1058 * Input: 1059 * cmd = Scsi Command to wait on. 1060 * 1061 * Return: 1062 * Not Found : 0 1063 * Found : 1 1064 */ 1065 static int 1066 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1067 { 1068 #define ABORT_POLLING_PERIOD 1000 1069 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1070 unsigned long wait_iter = ABORT_WAIT_ITER; 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1072 struct qla_hw_data *ha = vha->hw; 1073 int ret = QLA_SUCCESS; 1074 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1077 "Return:eh_wait.\n"); 1078 return ret; 1079 } 1080 1081 while (CMD_SP(cmd) && wait_iter--) { 1082 msleep(ABORT_POLLING_PERIOD); 1083 } 1084 if (CMD_SP(cmd)) 1085 ret = QLA_FUNCTION_FAILED; 1086 1087 return ret; 1088 } 1089 1090 /* 1091 * qla2x00_wait_for_hba_online 1092 * Wait till the HBA is online after going through 1093 * <= MAX_RETRIES_OF_ISP_ABORT or 1094 * finally HBA is disabled ie marked offline 1095 * 1096 * Input: 1097 * ha - pointer to host adapter structure 1098 * 1099 * Note: 1100 * Does context switching-Release SPIN_LOCK 1101 * (if any) before calling this routine. 1102 * 1103 * Return: 1104 * Success (Adapter is online) : 0 1105 * Failed (Adapter is offline/disabled) : 1 1106 */ 1107 int 1108 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1109 { 1110 int return_status; 1111 unsigned long wait_online; 1112 struct qla_hw_data *ha = vha->hw; 1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1114 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1119 ha->dpc_active) && time_before(jiffies, wait_online)) { 1120 1121 msleep(1000); 1122 } 1123 if (base_vha->flags.online) 1124 return_status = QLA_SUCCESS; 1125 else 1126 return_status = QLA_FUNCTION_FAILED; 1127 1128 return (return_status); 1129 } 1130 1131 static inline int test_fcport_count(scsi_qla_host_t *vha) 1132 { 1133 struct qla_hw_data *ha = vha->hw; 1134 unsigned long flags; 1135 int res; 1136 1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1138 ql_dbg(ql_dbg_init, vha, 0x00ec, 1139 "tgt %p, fcport_count=%d\n", 1140 vha, vha->fcport_count); 1141 res = (vha->fcport_count == 0); 1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1143 1144 return res; 1145 } 1146 1147 /* 1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1149 * it has dependency on UNLOADING flag to stop device discovery 1150 */ 1151 void 1152 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1153 { 1154 qla2x00_mark_all_devices_lost(vha, 0); 1155 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1157 } 1158 1159 /* 1160 * qla2x00_wait_for_hba_ready 1161 * Wait till the HBA is ready before doing driver unload 1162 * 1163 * Input: 1164 * ha - pointer to host adapter structure 1165 * 1166 * Note: 1167 * Does context switching-Release SPIN_LOCK 1168 * (if any) before calling this routine. 1169 * 1170 */ 1171 static void 1172 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1173 { 1174 struct qla_hw_data *ha = vha->hw; 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1176 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1178 ha->flags.mbox_busy) || 1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1181 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1182 break; 1183 msleep(1000); 1184 } 1185 } 1186 1187 int 1188 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1189 { 1190 int return_status; 1191 unsigned long wait_reset; 1192 struct qla_hw_data *ha = vha->hw; 1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1194 1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1199 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1200 1201 msleep(1000); 1202 1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1204 ha->flags.chip_reset_done) 1205 break; 1206 } 1207 if (ha->flags.chip_reset_done) 1208 return_status = QLA_SUCCESS; 1209 else 1210 return_status = QLA_FUNCTION_FAILED; 1211 1212 return return_status; 1213 } 1214 1215 static void 1216 sp_get(struct srb *sp) 1217 { 1218 atomic_inc(&sp->ref_count); 1219 } 1220 1221 #define ISP_REG_DISCONNECT 0xffffffffU 1222 /************************************************************************** 1223 * qla2x00_isp_reg_stat 1224 * 1225 * Description: 1226 * Read the host status register of ISP before aborting the command. 1227 * 1228 * Input: 1229 * ha = pointer to host adapter structure. 1230 * 1231 * 1232 * Returns: 1233 * Either true or false. 1234 * 1235 * Note: Return true if there is register disconnect. 1236 **************************************************************************/ 1237 static inline 1238 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1239 { 1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1241 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1242 1243 if (IS_P3P_TYPE(ha)) 1244 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1245 else 1246 return ((RD_REG_DWORD(®->host_status)) == 1247 ISP_REG_DISCONNECT); 1248 } 1249 1250 /************************************************************************** 1251 * qla2xxx_eh_abort 1252 * 1253 * Description: 1254 * The abort function will abort the specified command. 1255 * 1256 * Input: 1257 * cmd = Linux SCSI command packet to be aborted. 1258 * 1259 * Returns: 1260 * Either SUCCESS or FAILED. 1261 * 1262 * Note: 1263 * Only return FAILED if command not returned by firmware. 1264 **************************************************************************/ 1265 static int 1266 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1267 { 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1269 srb_t *sp; 1270 int ret; 1271 unsigned int id; 1272 uint64_t lun; 1273 unsigned long flags; 1274 int rval, wait = 0; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 if (qla2x00_isp_reg_stat(ha)) { 1278 ql_log(ql_log_info, vha, 0x8042, 1279 "PCI/Register disconnect, exiting.\n"); 1280 return FAILED; 1281 } 1282 if (!CMD_SP(cmd)) 1283 return SUCCESS; 1284 1285 ret = fc_block_scsi_eh(cmd); 1286 if (ret != 0) 1287 return ret; 1288 ret = SUCCESS; 1289 1290 id = cmd->device->id; 1291 lun = cmd->device->lun; 1292 1293 spin_lock_irqsave(&ha->hardware_lock, flags); 1294 sp = (srb_t *) CMD_SP(cmd); 1295 if (!sp) { 1296 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1297 return SUCCESS; 1298 } 1299 1300 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1302 vha->host_no, id, lun, sp, cmd, sp->handle); 1303 1304 /* Get a reference to the sp and drop the lock.*/ 1305 sp_get(sp); 1306 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1308 rval = ha->isp_ops->abort_command(sp); 1309 if (rval) { 1310 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1311 ret = SUCCESS; 1312 else 1313 ret = FAILED; 1314 1315 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1316 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1317 } else { 1318 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1319 "Abort command mbx success cmd=%p.\n", cmd); 1320 wait = 1; 1321 } 1322 1323 spin_lock_irqsave(&ha->hardware_lock, flags); 1324 sp->done(sp, 0); 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1326 1327 /* Did the command return during mailbox execution? */ 1328 if (ret == FAILED && !CMD_SP(cmd)) 1329 ret = SUCCESS; 1330 1331 /* Wait for the command to be returned. */ 1332 if (wait) { 1333 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1334 ql_log(ql_log_warn, vha, 0x8006, 1335 "Abort handler timed out cmd=%p.\n", cmd); 1336 ret = FAILED; 1337 } 1338 } 1339 1340 ql_log(ql_log_info, vha, 0x801c, 1341 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1342 vha->host_no, id, lun, wait, ret); 1343 1344 return ret; 1345 } 1346 1347 int 1348 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1349 uint64_t l, enum nexus_wait_type type) 1350 { 1351 int cnt, match, status; 1352 unsigned long flags; 1353 struct qla_hw_data *ha = vha->hw; 1354 struct req_que *req; 1355 srb_t *sp; 1356 struct scsi_cmnd *cmd; 1357 1358 status = QLA_SUCCESS; 1359 1360 spin_lock_irqsave(&ha->hardware_lock, flags); 1361 req = vha->req; 1362 for (cnt = 1; status == QLA_SUCCESS && 1363 cnt < req->num_outstanding_cmds; cnt++) { 1364 sp = req->outstanding_cmds[cnt]; 1365 if (!sp) 1366 continue; 1367 if (sp->type != SRB_SCSI_CMD) 1368 continue; 1369 if (vha->vp_idx != sp->vha->vp_idx) 1370 continue; 1371 match = 0; 1372 cmd = GET_CMD_SP(sp); 1373 switch (type) { 1374 case WAIT_HOST: 1375 match = 1; 1376 break; 1377 case WAIT_TARGET: 1378 match = cmd->device->id == t; 1379 break; 1380 case WAIT_LUN: 1381 match = (cmd->device->id == t && 1382 cmd->device->lun == l); 1383 break; 1384 } 1385 if (!match) 1386 continue; 1387 1388 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1389 status = qla2x00_eh_wait_on_command(cmd); 1390 spin_lock_irqsave(&ha->hardware_lock, flags); 1391 } 1392 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1393 1394 return status; 1395 } 1396 1397 static char *reset_errors[] = { 1398 "HBA not online", 1399 "HBA not ready", 1400 "Task management failed", 1401 "Waiting for command completions", 1402 }; 1403 1404 static int 1405 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1406 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1407 { 1408 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1409 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1410 int err; 1411 1412 if (!fcport) { 1413 return FAILED; 1414 } 1415 1416 err = fc_block_scsi_eh(cmd); 1417 if (err != 0) 1418 return err; 1419 1420 ql_log(ql_log_info, vha, 0x8009, 1421 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1422 cmd->device->id, cmd->device->lun, cmd); 1423 1424 err = 0; 1425 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1426 ql_log(ql_log_warn, vha, 0x800a, 1427 "Wait for hba online failed for cmd=%p.\n", cmd); 1428 goto eh_reset_failed; 1429 } 1430 err = 2; 1431 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1432 != QLA_SUCCESS) { 1433 ql_log(ql_log_warn, vha, 0x800c, 1434 "do_reset failed for cmd=%p.\n", cmd); 1435 goto eh_reset_failed; 1436 } 1437 err = 3; 1438 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1439 cmd->device->lun, type) != QLA_SUCCESS) { 1440 ql_log(ql_log_warn, vha, 0x800d, 1441 "wait for pending cmds failed for cmd=%p.\n", cmd); 1442 goto eh_reset_failed; 1443 } 1444 1445 ql_log(ql_log_info, vha, 0x800e, 1446 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1447 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1448 1449 return SUCCESS; 1450 1451 eh_reset_failed: 1452 ql_log(ql_log_info, vha, 0x800f, 1453 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1454 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1455 cmd); 1456 return FAILED; 1457 } 1458 1459 static int 1460 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1461 { 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1463 struct qla_hw_data *ha = vha->hw; 1464 1465 if (qla2x00_isp_reg_stat(ha)) { 1466 ql_log(ql_log_info, vha, 0x803e, 1467 "PCI/Register disconnect, exiting.\n"); 1468 return FAILED; 1469 } 1470 1471 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1472 ha->isp_ops->lun_reset); 1473 } 1474 1475 static int 1476 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1477 { 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1479 struct qla_hw_data *ha = vha->hw; 1480 1481 if (qla2x00_isp_reg_stat(ha)) { 1482 ql_log(ql_log_info, vha, 0x803f, 1483 "PCI/Register disconnect, exiting.\n"); 1484 return FAILED; 1485 } 1486 1487 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1488 ha->isp_ops->target_reset); 1489 } 1490 1491 /************************************************************************** 1492 * qla2xxx_eh_bus_reset 1493 * 1494 * Description: 1495 * The bus reset function will reset the bus and abort any executing 1496 * commands. 1497 * 1498 * Input: 1499 * cmd = Linux SCSI command packet of the command that cause the 1500 * bus reset. 1501 * 1502 * Returns: 1503 * SUCCESS/FAILURE (defined as macro in scsi.h). 1504 * 1505 **************************************************************************/ 1506 static int 1507 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1508 { 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1510 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1511 int ret = FAILED; 1512 unsigned int id; 1513 uint64_t lun; 1514 struct qla_hw_data *ha = vha->hw; 1515 1516 if (qla2x00_isp_reg_stat(ha)) { 1517 ql_log(ql_log_info, vha, 0x8040, 1518 "PCI/Register disconnect, exiting.\n"); 1519 return FAILED; 1520 } 1521 1522 id = cmd->device->id; 1523 lun = cmd->device->lun; 1524 1525 if (!fcport) { 1526 return ret; 1527 } 1528 1529 ret = fc_block_scsi_eh(cmd); 1530 if (ret != 0) 1531 return ret; 1532 ret = FAILED; 1533 1534 ql_log(ql_log_info, vha, 0x8012, 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1536 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1538 ql_log(ql_log_fatal, vha, 0x8013, 1539 "Wait for hba online failed board disabled.\n"); 1540 goto eh_bus_reset_done; 1541 } 1542 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1544 ret = SUCCESS; 1545 1546 if (ret == FAILED) 1547 goto eh_bus_reset_done; 1548 1549 /* Flush outstanding commands. */ 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1551 QLA_SUCCESS) { 1552 ql_log(ql_log_warn, vha, 0x8014, 1553 "Wait for pending commands failed.\n"); 1554 ret = FAILED; 1555 } 1556 1557 eh_bus_reset_done: 1558 ql_log(ql_log_warn, vha, 0x802b, 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1561 1562 return ret; 1563 } 1564 1565 /************************************************************************** 1566 * qla2xxx_eh_host_reset 1567 * 1568 * Description: 1569 * The reset function will reset the Adapter. 1570 * 1571 * Input: 1572 * cmd = Linux SCSI command packet of the command that cause the 1573 * adapter reset. 1574 * 1575 * Returns: 1576 * Either SUCCESS or FAILED. 1577 * 1578 * Note: 1579 **************************************************************************/ 1580 static int 1581 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1582 { 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1584 struct qla_hw_data *ha = vha->hw; 1585 int ret = FAILED; 1586 unsigned int id; 1587 uint64_t lun; 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1589 1590 if (qla2x00_isp_reg_stat(ha)) { 1591 ql_log(ql_log_info, vha, 0x8041, 1592 "PCI/Register disconnect, exiting.\n"); 1593 schedule_work(&ha->board_disable); 1594 return SUCCESS; 1595 } 1596 1597 id = cmd->device->id; 1598 lun = cmd->device->lun; 1599 1600 ql_log(ql_log_info, vha, 0x8018, 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1602 1603 /* 1604 * No point in issuing another reset if one is active. Also do not 1605 * attempt a reset if we are updating flash. 1606 */ 1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1608 goto eh_host_reset_lock; 1609 1610 if (vha != base_vha) { 1611 if (qla2x00_vp_abort_isp(vha)) 1612 goto eh_host_reset_lock; 1613 } else { 1614 if (IS_P3P_TYPE(vha->hw)) { 1615 if (!qla82xx_fcoe_ctx_reset(vha)) { 1616 /* Ctx reset success */ 1617 ret = SUCCESS; 1618 goto eh_host_reset_lock; 1619 } 1620 /* fall thru if ctx reset failed */ 1621 } 1622 if (ha->wq) 1623 flush_workqueue(ha->wq); 1624 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1626 if (ha->isp_ops->abort_isp(base_vha)) { 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1628 /* failed. schedule dpc to try */ 1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1630 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1632 ql_log(ql_log_warn, vha, 0x802a, 1633 "wait for hba online failed.\n"); 1634 goto eh_host_reset_lock; 1635 } 1636 } 1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1638 } 1639 1640 /* Waiting for command to be returned to OS.*/ 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1642 QLA_SUCCESS) 1643 ret = SUCCESS; 1644 1645 eh_host_reset_lock: 1646 ql_log(ql_log_info, vha, 0x8017, 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1649 1650 return ret; 1651 } 1652 1653 /* 1654 * qla2x00_loop_reset 1655 * Issue loop reset. 1656 * 1657 * Input: 1658 * ha = adapter block pointer. 1659 * 1660 * Returns: 1661 * 0 = success 1662 */ 1663 int 1664 qla2x00_loop_reset(scsi_qla_host_t *vha) 1665 { 1666 int ret; 1667 struct fc_port *fcport; 1668 struct qla_hw_data *ha = vha->hw; 1669 1670 if (IS_QLAFX00(ha)) { 1671 return qlafx00_loop_reset(vha); 1672 } 1673 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1676 if (fcport->port_type != FCT_TARGET) 1677 continue; 1678 1679 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1680 if (ret != QLA_SUCCESS) { 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1682 "Bus Reset failed: Reset=%d " 1683 "d_id=%x.\n", ret, fcport->d_id.b24); 1684 } 1685 } 1686 } 1687 1688 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1690 atomic_set(&vha->loop_state, LOOP_DOWN); 1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1692 qla2x00_mark_all_devices_lost(vha, 0); 1693 ret = qla2x00_full_login_lip(vha); 1694 if (ret != QLA_SUCCESS) { 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1696 "full_login_lip=%d.\n", ret); 1697 } 1698 } 1699 1700 if (ha->flags.enable_lip_reset) { 1701 ret = qla2x00_lip_reset(vha); 1702 if (ret != QLA_SUCCESS) 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1704 "lip_reset failed (%d).\n", ret); 1705 } 1706 1707 /* Issue marker command only when we are going to start the I/O */ 1708 vha->marker_needed = 1; 1709 1710 return QLA_SUCCESS; 1711 } 1712 1713 static void 1714 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1715 { 1716 int cnt, status; 1717 unsigned long flags; 1718 srb_t *sp; 1719 scsi_qla_host_t *vha = qp->vha; 1720 struct qla_hw_data *ha = vha->hw; 1721 struct req_que *req; 1722 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1723 struct qla_tgt_cmd *cmd; 1724 uint8_t trace = 0; 1725 1726 if (!ha->req_q_map) 1727 return; 1728 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1729 req = qp->req; 1730 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1731 sp = req->outstanding_cmds[cnt]; 1732 if (sp) { 1733 req->outstanding_cmds[cnt] = NULL; 1734 if (sp->cmd_type == TYPE_SRB) { 1735 if (sp->type == SRB_NVME_CMD || 1736 sp->type == SRB_NVME_LS) { 1737 sp_get(sp); 1738 spin_unlock_irqrestore(qp->qp_lock_ptr, 1739 flags); 1740 qla_nvme_abort(ha, sp, res); 1741 spin_lock_irqsave(qp->qp_lock_ptr, 1742 flags); 1743 } else if (GET_CMD_SP(sp) && 1744 !ha->flags.eeh_busy && 1745 (!test_bit(ABORT_ISP_ACTIVE, 1746 &vha->dpc_flags)) && 1747 (sp->type == SRB_SCSI_CMD)) { 1748 /* 1749 * Don't abort commands in 1750 * adapter during EEH 1751 * recovery as it's not 1752 * accessible/responding. 1753 * 1754 * Get a reference to the sp 1755 * and drop the lock. The 1756 * reference ensures this 1757 * sp->done() call and not the 1758 * call in qla2xxx_eh_abort() 1759 * ends the SCSI command (with 1760 * result 'res'). 1761 */ 1762 sp_get(sp); 1763 spin_unlock_irqrestore(qp->qp_lock_ptr, 1764 flags); 1765 status = qla2xxx_eh_abort( 1766 GET_CMD_SP(sp)); 1767 spin_lock_irqsave(qp->qp_lock_ptr, 1768 flags); 1769 /* 1770 * Get rid of extra reference 1771 * if immediate exit from 1772 * ql2xxx_eh_abort 1773 */ 1774 if (status == FAILED && 1775 (qla2x00_isp_reg_stat(ha))) 1776 atomic_dec( 1777 &sp->ref_count); 1778 } 1779 sp->done(sp, res); 1780 } else { 1781 if (!vha->hw->tgt.tgt_ops || !tgt || 1782 qla_ini_mode_enabled(vha)) { 1783 if (!trace) 1784 ql_dbg(ql_dbg_tgt_mgt, 1785 vha, 0xf003, 1786 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1787 vha->dpc_flags); 1788 continue; 1789 } 1790 cmd = (struct qla_tgt_cmd *)sp; 1791 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1792 } 1793 } 1794 } 1795 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1796 } 1797 1798 void 1799 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1800 { 1801 int que; 1802 struct qla_hw_data *ha = vha->hw; 1803 1804 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1805 1806 for (que = 0; que < ha->max_qpairs; que++) { 1807 if (!ha->queue_pair_map[que]) 1808 continue; 1809 1810 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1811 } 1812 } 1813 1814 static int 1815 qla2xxx_slave_alloc(struct scsi_device *sdev) 1816 { 1817 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1818 1819 if (!rport || fc_remote_port_chkready(rport)) 1820 return -ENXIO; 1821 1822 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1823 1824 return 0; 1825 } 1826 1827 static int 1828 qla2xxx_slave_configure(struct scsi_device *sdev) 1829 { 1830 scsi_qla_host_t *vha = shost_priv(sdev->host); 1831 struct req_que *req = vha->req; 1832 1833 if (IS_T10_PI_CAPABLE(vha->hw)) 1834 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1835 1836 scsi_change_queue_depth(sdev, req->max_q_depth); 1837 return 0; 1838 } 1839 1840 static void 1841 qla2xxx_slave_destroy(struct scsi_device *sdev) 1842 { 1843 sdev->hostdata = NULL; 1844 } 1845 1846 /** 1847 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1848 * @ha: HA context 1849 * 1850 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1851 * supported addressing method. 1852 */ 1853 static void 1854 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1855 { 1856 /* Assume a 32bit DMA mask. */ 1857 ha->flags.enable_64bit_addressing = 0; 1858 1859 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1860 /* Any upper-dword bits set? */ 1861 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1862 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1863 /* Ok, a 64bit DMA mask is applicable. */ 1864 ha->flags.enable_64bit_addressing = 1; 1865 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1866 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1867 return; 1868 } 1869 } 1870 1871 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1872 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1873 } 1874 1875 static void 1876 qla2x00_enable_intrs(struct qla_hw_data *ha) 1877 { 1878 unsigned long flags = 0; 1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1880 1881 spin_lock_irqsave(&ha->hardware_lock, flags); 1882 ha->interrupts_on = 1; 1883 /* enable risc and host interrupts */ 1884 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1885 RD_REG_WORD(®->ictrl); 1886 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1887 1888 } 1889 1890 static void 1891 qla2x00_disable_intrs(struct qla_hw_data *ha) 1892 { 1893 unsigned long flags = 0; 1894 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1895 1896 spin_lock_irqsave(&ha->hardware_lock, flags); 1897 ha->interrupts_on = 0; 1898 /* disable risc and host interrupts */ 1899 WRT_REG_WORD(®->ictrl, 0); 1900 RD_REG_WORD(®->ictrl); 1901 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1902 } 1903 1904 static void 1905 qla24xx_enable_intrs(struct qla_hw_data *ha) 1906 { 1907 unsigned long flags = 0; 1908 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1909 1910 spin_lock_irqsave(&ha->hardware_lock, flags); 1911 ha->interrupts_on = 1; 1912 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1913 RD_REG_DWORD(®->ictrl); 1914 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1915 } 1916 1917 static void 1918 qla24xx_disable_intrs(struct qla_hw_data *ha) 1919 { 1920 unsigned long flags = 0; 1921 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1922 1923 if (IS_NOPOLLING_TYPE(ha)) 1924 return; 1925 spin_lock_irqsave(&ha->hardware_lock, flags); 1926 ha->interrupts_on = 0; 1927 WRT_REG_DWORD(®->ictrl, 0); 1928 RD_REG_DWORD(®->ictrl); 1929 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1930 } 1931 1932 static int 1933 qla2x00_iospace_config(struct qla_hw_data *ha) 1934 { 1935 resource_size_t pio; 1936 uint16_t msix; 1937 1938 if (pci_request_selected_regions(ha->pdev, ha->bars, 1939 QLA2XXX_DRIVER_NAME)) { 1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1941 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1942 pci_name(ha->pdev)); 1943 goto iospace_error_exit; 1944 } 1945 if (!(ha->bars & 1)) 1946 goto skip_pio; 1947 1948 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1949 pio = pci_resource_start(ha->pdev, 0); 1950 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1951 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1952 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1953 "Invalid pci I/O region size (%s).\n", 1954 pci_name(ha->pdev)); 1955 pio = 0; 1956 } 1957 } else { 1958 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1959 "Region #0 no a PIO resource (%s).\n", 1960 pci_name(ha->pdev)); 1961 pio = 0; 1962 } 1963 ha->pio_address = pio; 1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1965 "PIO address=%llu.\n", 1966 (unsigned long long)ha->pio_address); 1967 1968 skip_pio: 1969 /* Use MMIO operations for all accesses. */ 1970 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1972 "Region #1 not an MMIO resource (%s), aborting.\n", 1973 pci_name(ha->pdev)); 1974 goto iospace_error_exit; 1975 } 1976 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1978 "Invalid PCI mem region size (%s), aborting.\n", 1979 pci_name(ha->pdev)); 1980 goto iospace_error_exit; 1981 } 1982 1983 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1984 if (!ha->iobase) { 1985 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1986 "Cannot remap MMIO (%s), aborting.\n", 1987 pci_name(ha->pdev)); 1988 goto iospace_error_exit; 1989 } 1990 1991 /* Determine queue resources */ 1992 ha->max_req_queues = ha->max_rsp_queues = 1; 1993 ha->msix_count = QLA_BASE_VECTORS; 1994 if (!ql2xmqsupport || !ql2xnvmeenable || 1995 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1996 goto mqiobase_exit; 1997 1998 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1999 pci_resource_len(ha->pdev, 3)); 2000 if (ha->mqiobase) { 2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2002 "MQIO Base=%p.\n", ha->mqiobase); 2003 /* Read MSIX vector size of the board */ 2004 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2005 ha->msix_count = msix + 1; 2006 /* Max queues are bounded by available msix vectors */ 2007 /* MB interrupt uses 1 vector */ 2008 ha->max_req_queues = ha->msix_count - 1; 2009 ha->max_rsp_queues = ha->max_req_queues; 2010 /* Queue pairs is the max value minus the base queue pair */ 2011 ha->max_qpairs = ha->max_rsp_queues - 1; 2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2013 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2014 2015 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2016 "MSI-X vector count: %d.\n", ha->msix_count); 2017 } else 2018 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2019 "BAR 3 not enabled.\n"); 2020 2021 mqiobase_exit: 2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2023 "MSIX Count: %d.\n", ha->msix_count); 2024 return (0); 2025 2026 iospace_error_exit: 2027 return (-ENOMEM); 2028 } 2029 2030 2031 static int 2032 qla83xx_iospace_config(struct qla_hw_data *ha) 2033 { 2034 uint16_t msix; 2035 2036 if (pci_request_selected_regions(ha->pdev, ha->bars, 2037 QLA2XXX_DRIVER_NAME)) { 2038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2039 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2040 pci_name(ha->pdev)); 2041 2042 goto iospace_error_exit; 2043 } 2044 2045 /* Use MMIO operations for all accesses. */ 2046 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2047 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2048 "Invalid pci I/O region size (%s).\n", 2049 pci_name(ha->pdev)); 2050 goto iospace_error_exit; 2051 } 2052 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2053 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2054 "Invalid PCI mem region size (%s), aborting\n", 2055 pci_name(ha->pdev)); 2056 goto iospace_error_exit; 2057 } 2058 2059 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2060 if (!ha->iobase) { 2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2062 "Cannot remap MMIO (%s), aborting.\n", 2063 pci_name(ha->pdev)); 2064 goto iospace_error_exit; 2065 } 2066 2067 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2068 /* 83XX 26XX always use MQ type access for queues 2069 * - mbar 2, a.k.a region 4 */ 2070 ha->max_req_queues = ha->max_rsp_queues = 1; 2071 ha->msix_count = QLA_BASE_VECTORS; 2072 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2073 pci_resource_len(ha->pdev, 4)); 2074 2075 if (!ha->mqiobase) { 2076 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2077 "BAR2/region4 not enabled\n"); 2078 goto mqiobase_exit; 2079 } 2080 2081 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2082 pci_resource_len(ha->pdev, 2)); 2083 if (ha->msixbase) { 2084 /* Read MSIX vector size of the board */ 2085 pci_read_config_word(ha->pdev, 2086 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2087 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2088 /* 2089 * By default, driver uses at least two msix vectors 2090 * (default & rspq) 2091 */ 2092 if (ql2xmqsupport || ql2xnvmeenable) { 2093 /* MB interrupt uses 1 vector */ 2094 ha->max_req_queues = ha->msix_count - 1; 2095 2096 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2097 if (QLA_TGT_MODE_ENABLED()) 2098 ha->max_req_queues--; 2099 2100 ha->max_rsp_queues = ha->max_req_queues; 2101 2102 /* Queue pairs is the max value minus 2103 * the base queue pair */ 2104 ha->max_qpairs = ha->max_req_queues - 1; 2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2106 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2107 } 2108 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2109 "MSI-X vector count: %d.\n", ha->msix_count); 2110 } else 2111 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2112 "BAR 1 not enabled.\n"); 2113 2114 mqiobase_exit: 2115 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2116 "MSIX Count: %d.\n", ha->msix_count); 2117 return 0; 2118 2119 iospace_error_exit: 2120 return -ENOMEM; 2121 } 2122 2123 static struct isp_operations qla2100_isp_ops = { 2124 .pci_config = qla2100_pci_config, 2125 .reset_chip = qla2x00_reset_chip, 2126 .chip_diag = qla2x00_chip_diag, 2127 .config_rings = qla2x00_config_rings, 2128 .reset_adapter = qla2x00_reset_adapter, 2129 .nvram_config = qla2x00_nvram_config, 2130 .update_fw_options = qla2x00_update_fw_options, 2131 .load_risc = qla2x00_load_risc, 2132 .pci_info_str = qla2x00_pci_info_str, 2133 .fw_version_str = qla2x00_fw_version_str, 2134 .intr_handler = qla2100_intr_handler, 2135 .enable_intrs = qla2x00_enable_intrs, 2136 .disable_intrs = qla2x00_disable_intrs, 2137 .abort_command = qla2x00_abort_command, 2138 .target_reset = qla2x00_abort_target, 2139 .lun_reset = qla2x00_lun_reset, 2140 .fabric_login = qla2x00_login_fabric, 2141 .fabric_logout = qla2x00_fabric_logout, 2142 .calc_req_entries = qla2x00_calc_iocbs_32, 2143 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2144 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2145 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2146 .read_nvram = qla2x00_read_nvram_data, 2147 .write_nvram = qla2x00_write_nvram_data, 2148 .fw_dump = qla2100_fw_dump, 2149 .beacon_on = NULL, 2150 .beacon_off = NULL, 2151 .beacon_blink = NULL, 2152 .read_optrom = qla2x00_read_optrom_data, 2153 .write_optrom = qla2x00_write_optrom_data, 2154 .get_flash_version = qla2x00_get_flash_version, 2155 .start_scsi = qla2x00_start_scsi, 2156 .start_scsi_mq = NULL, 2157 .abort_isp = qla2x00_abort_isp, 2158 .iospace_config = qla2x00_iospace_config, 2159 .initialize_adapter = qla2x00_initialize_adapter, 2160 }; 2161 2162 static struct isp_operations qla2300_isp_ops = { 2163 .pci_config = qla2300_pci_config, 2164 .reset_chip = qla2x00_reset_chip, 2165 .chip_diag = qla2x00_chip_diag, 2166 .config_rings = qla2x00_config_rings, 2167 .reset_adapter = qla2x00_reset_adapter, 2168 .nvram_config = qla2x00_nvram_config, 2169 .update_fw_options = qla2x00_update_fw_options, 2170 .load_risc = qla2x00_load_risc, 2171 .pci_info_str = qla2x00_pci_info_str, 2172 .fw_version_str = qla2x00_fw_version_str, 2173 .intr_handler = qla2300_intr_handler, 2174 .enable_intrs = qla2x00_enable_intrs, 2175 .disable_intrs = qla2x00_disable_intrs, 2176 .abort_command = qla2x00_abort_command, 2177 .target_reset = qla2x00_abort_target, 2178 .lun_reset = qla2x00_lun_reset, 2179 .fabric_login = qla2x00_login_fabric, 2180 .fabric_logout = qla2x00_fabric_logout, 2181 .calc_req_entries = qla2x00_calc_iocbs_32, 2182 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2183 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2184 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2185 .read_nvram = qla2x00_read_nvram_data, 2186 .write_nvram = qla2x00_write_nvram_data, 2187 .fw_dump = qla2300_fw_dump, 2188 .beacon_on = qla2x00_beacon_on, 2189 .beacon_off = qla2x00_beacon_off, 2190 .beacon_blink = qla2x00_beacon_blink, 2191 .read_optrom = qla2x00_read_optrom_data, 2192 .write_optrom = qla2x00_write_optrom_data, 2193 .get_flash_version = qla2x00_get_flash_version, 2194 .start_scsi = qla2x00_start_scsi, 2195 .start_scsi_mq = NULL, 2196 .abort_isp = qla2x00_abort_isp, 2197 .iospace_config = qla2x00_iospace_config, 2198 .initialize_adapter = qla2x00_initialize_adapter, 2199 }; 2200 2201 static struct isp_operations qla24xx_isp_ops = { 2202 .pci_config = qla24xx_pci_config, 2203 .reset_chip = qla24xx_reset_chip, 2204 .chip_diag = qla24xx_chip_diag, 2205 .config_rings = qla24xx_config_rings, 2206 .reset_adapter = qla24xx_reset_adapter, 2207 .nvram_config = qla24xx_nvram_config, 2208 .update_fw_options = qla24xx_update_fw_options, 2209 .load_risc = qla24xx_load_risc, 2210 .pci_info_str = qla24xx_pci_info_str, 2211 .fw_version_str = qla24xx_fw_version_str, 2212 .intr_handler = qla24xx_intr_handler, 2213 .enable_intrs = qla24xx_enable_intrs, 2214 .disable_intrs = qla24xx_disable_intrs, 2215 .abort_command = qla24xx_abort_command, 2216 .target_reset = qla24xx_abort_target, 2217 .lun_reset = qla24xx_lun_reset, 2218 .fabric_login = qla24xx_login_fabric, 2219 .fabric_logout = qla24xx_fabric_logout, 2220 .calc_req_entries = NULL, 2221 .build_iocbs = NULL, 2222 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2223 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2224 .read_nvram = qla24xx_read_nvram_data, 2225 .write_nvram = qla24xx_write_nvram_data, 2226 .fw_dump = qla24xx_fw_dump, 2227 .beacon_on = qla24xx_beacon_on, 2228 .beacon_off = qla24xx_beacon_off, 2229 .beacon_blink = qla24xx_beacon_blink, 2230 .read_optrom = qla24xx_read_optrom_data, 2231 .write_optrom = qla24xx_write_optrom_data, 2232 .get_flash_version = qla24xx_get_flash_version, 2233 .start_scsi = qla24xx_start_scsi, 2234 .start_scsi_mq = NULL, 2235 .abort_isp = qla2x00_abort_isp, 2236 .iospace_config = qla2x00_iospace_config, 2237 .initialize_adapter = qla2x00_initialize_adapter, 2238 }; 2239 2240 static struct isp_operations qla25xx_isp_ops = { 2241 .pci_config = qla25xx_pci_config, 2242 .reset_chip = qla24xx_reset_chip, 2243 .chip_diag = qla24xx_chip_diag, 2244 .config_rings = qla24xx_config_rings, 2245 .reset_adapter = qla24xx_reset_adapter, 2246 .nvram_config = qla24xx_nvram_config, 2247 .update_fw_options = qla24xx_update_fw_options, 2248 .load_risc = qla24xx_load_risc, 2249 .pci_info_str = qla24xx_pci_info_str, 2250 .fw_version_str = qla24xx_fw_version_str, 2251 .intr_handler = qla24xx_intr_handler, 2252 .enable_intrs = qla24xx_enable_intrs, 2253 .disable_intrs = qla24xx_disable_intrs, 2254 .abort_command = qla24xx_abort_command, 2255 .target_reset = qla24xx_abort_target, 2256 .lun_reset = qla24xx_lun_reset, 2257 .fabric_login = qla24xx_login_fabric, 2258 .fabric_logout = qla24xx_fabric_logout, 2259 .calc_req_entries = NULL, 2260 .build_iocbs = NULL, 2261 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2262 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2263 .read_nvram = qla25xx_read_nvram_data, 2264 .write_nvram = qla25xx_write_nvram_data, 2265 .fw_dump = qla25xx_fw_dump, 2266 .beacon_on = qla24xx_beacon_on, 2267 .beacon_off = qla24xx_beacon_off, 2268 .beacon_blink = qla24xx_beacon_blink, 2269 .read_optrom = qla25xx_read_optrom_data, 2270 .write_optrom = qla24xx_write_optrom_data, 2271 .get_flash_version = qla24xx_get_flash_version, 2272 .start_scsi = qla24xx_dif_start_scsi, 2273 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2274 .abort_isp = qla2x00_abort_isp, 2275 .iospace_config = qla2x00_iospace_config, 2276 .initialize_adapter = qla2x00_initialize_adapter, 2277 }; 2278 2279 static struct isp_operations qla81xx_isp_ops = { 2280 .pci_config = qla25xx_pci_config, 2281 .reset_chip = qla24xx_reset_chip, 2282 .chip_diag = qla24xx_chip_diag, 2283 .config_rings = qla24xx_config_rings, 2284 .reset_adapter = qla24xx_reset_adapter, 2285 .nvram_config = qla81xx_nvram_config, 2286 .update_fw_options = qla81xx_update_fw_options, 2287 .load_risc = qla81xx_load_risc, 2288 .pci_info_str = qla24xx_pci_info_str, 2289 .fw_version_str = qla24xx_fw_version_str, 2290 .intr_handler = qla24xx_intr_handler, 2291 .enable_intrs = qla24xx_enable_intrs, 2292 .disable_intrs = qla24xx_disable_intrs, 2293 .abort_command = qla24xx_abort_command, 2294 .target_reset = qla24xx_abort_target, 2295 .lun_reset = qla24xx_lun_reset, 2296 .fabric_login = qla24xx_login_fabric, 2297 .fabric_logout = qla24xx_fabric_logout, 2298 .calc_req_entries = NULL, 2299 .build_iocbs = NULL, 2300 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2301 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2302 .read_nvram = NULL, 2303 .write_nvram = NULL, 2304 .fw_dump = qla81xx_fw_dump, 2305 .beacon_on = qla24xx_beacon_on, 2306 .beacon_off = qla24xx_beacon_off, 2307 .beacon_blink = qla83xx_beacon_blink, 2308 .read_optrom = qla25xx_read_optrom_data, 2309 .write_optrom = qla24xx_write_optrom_data, 2310 .get_flash_version = qla24xx_get_flash_version, 2311 .start_scsi = qla24xx_dif_start_scsi, 2312 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2313 .abort_isp = qla2x00_abort_isp, 2314 .iospace_config = qla2x00_iospace_config, 2315 .initialize_adapter = qla2x00_initialize_adapter, 2316 }; 2317 2318 static struct isp_operations qla82xx_isp_ops = { 2319 .pci_config = qla82xx_pci_config, 2320 .reset_chip = qla82xx_reset_chip, 2321 .chip_diag = qla24xx_chip_diag, 2322 .config_rings = qla82xx_config_rings, 2323 .reset_adapter = qla24xx_reset_adapter, 2324 .nvram_config = qla81xx_nvram_config, 2325 .update_fw_options = qla24xx_update_fw_options, 2326 .load_risc = qla82xx_load_risc, 2327 .pci_info_str = qla24xx_pci_info_str, 2328 .fw_version_str = qla24xx_fw_version_str, 2329 .intr_handler = qla82xx_intr_handler, 2330 .enable_intrs = qla82xx_enable_intrs, 2331 .disable_intrs = qla82xx_disable_intrs, 2332 .abort_command = qla24xx_abort_command, 2333 .target_reset = qla24xx_abort_target, 2334 .lun_reset = qla24xx_lun_reset, 2335 .fabric_login = qla24xx_login_fabric, 2336 .fabric_logout = qla24xx_fabric_logout, 2337 .calc_req_entries = NULL, 2338 .build_iocbs = NULL, 2339 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2340 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2341 .read_nvram = qla24xx_read_nvram_data, 2342 .write_nvram = qla24xx_write_nvram_data, 2343 .fw_dump = qla82xx_fw_dump, 2344 .beacon_on = qla82xx_beacon_on, 2345 .beacon_off = qla82xx_beacon_off, 2346 .beacon_blink = NULL, 2347 .read_optrom = qla82xx_read_optrom_data, 2348 .write_optrom = qla82xx_write_optrom_data, 2349 .get_flash_version = qla82xx_get_flash_version, 2350 .start_scsi = qla82xx_start_scsi, 2351 .start_scsi_mq = NULL, 2352 .abort_isp = qla82xx_abort_isp, 2353 .iospace_config = qla82xx_iospace_config, 2354 .initialize_adapter = qla2x00_initialize_adapter, 2355 }; 2356 2357 static struct isp_operations qla8044_isp_ops = { 2358 .pci_config = qla82xx_pci_config, 2359 .reset_chip = qla82xx_reset_chip, 2360 .chip_diag = qla24xx_chip_diag, 2361 .config_rings = qla82xx_config_rings, 2362 .reset_adapter = qla24xx_reset_adapter, 2363 .nvram_config = qla81xx_nvram_config, 2364 .update_fw_options = qla24xx_update_fw_options, 2365 .load_risc = qla82xx_load_risc, 2366 .pci_info_str = qla24xx_pci_info_str, 2367 .fw_version_str = qla24xx_fw_version_str, 2368 .intr_handler = qla8044_intr_handler, 2369 .enable_intrs = qla82xx_enable_intrs, 2370 .disable_intrs = qla82xx_disable_intrs, 2371 .abort_command = qla24xx_abort_command, 2372 .target_reset = qla24xx_abort_target, 2373 .lun_reset = qla24xx_lun_reset, 2374 .fabric_login = qla24xx_login_fabric, 2375 .fabric_logout = qla24xx_fabric_logout, 2376 .calc_req_entries = NULL, 2377 .build_iocbs = NULL, 2378 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2379 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2380 .read_nvram = NULL, 2381 .write_nvram = NULL, 2382 .fw_dump = qla8044_fw_dump, 2383 .beacon_on = qla82xx_beacon_on, 2384 .beacon_off = qla82xx_beacon_off, 2385 .beacon_blink = NULL, 2386 .read_optrom = qla8044_read_optrom_data, 2387 .write_optrom = qla8044_write_optrom_data, 2388 .get_flash_version = qla82xx_get_flash_version, 2389 .start_scsi = qla82xx_start_scsi, 2390 .start_scsi_mq = NULL, 2391 .abort_isp = qla8044_abort_isp, 2392 .iospace_config = qla82xx_iospace_config, 2393 .initialize_adapter = qla2x00_initialize_adapter, 2394 }; 2395 2396 static struct isp_operations qla83xx_isp_ops = { 2397 .pci_config = qla25xx_pci_config, 2398 .reset_chip = qla24xx_reset_chip, 2399 .chip_diag = qla24xx_chip_diag, 2400 .config_rings = qla24xx_config_rings, 2401 .reset_adapter = qla24xx_reset_adapter, 2402 .nvram_config = qla81xx_nvram_config, 2403 .update_fw_options = qla81xx_update_fw_options, 2404 .load_risc = qla81xx_load_risc, 2405 .pci_info_str = qla24xx_pci_info_str, 2406 .fw_version_str = qla24xx_fw_version_str, 2407 .intr_handler = qla24xx_intr_handler, 2408 .enable_intrs = qla24xx_enable_intrs, 2409 .disable_intrs = qla24xx_disable_intrs, 2410 .abort_command = qla24xx_abort_command, 2411 .target_reset = qla24xx_abort_target, 2412 .lun_reset = qla24xx_lun_reset, 2413 .fabric_login = qla24xx_login_fabric, 2414 .fabric_logout = qla24xx_fabric_logout, 2415 .calc_req_entries = NULL, 2416 .build_iocbs = NULL, 2417 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2418 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2419 .read_nvram = NULL, 2420 .write_nvram = NULL, 2421 .fw_dump = qla83xx_fw_dump, 2422 .beacon_on = qla24xx_beacon_on, 2423 .beacon_off = qla24xx_beacon_off, 2424 .beacon_blink = qla83xx_beacon_blink, 2425 .read_optrom = qla25xx_read_optrom_data, 2426 .write_optrom = qla24xx_write_optrom_data, 2427 .get_flash_version = qla24xx_get_flash_version, 2428 .start_scsi = qla24xx_dif_start_scsi, 2429 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2430 .abort_isp = qla2x00_abort_isp, 2431 .iospace_config = qla83xx_iospace_config, 2432 .initialize_adapter = qla2x00_initialize_adapter, 2433 }; 2434 2435 static struct isp_operations qlafx00_isp_ops = { 2436 .pci_config = qlafx00_pci_config, 2437 .reset_chip = qlafx00_soft_reset, 2438 .chip_diag = qlafx00_chip_diag, 2439 .config_rings = qlafx00_config_rings, 2440 .reset_adapter = qlafx00_soft_reset, 2441 .nvram_config = NULL, 2442 .update_fw_options = NULL, 2443 .load_risc = NULL, 2444 .pci_info_str = qlafx00_pci_info_str, 2445 .fw_version_str = qlafx00_fw_version_str, 2446 .intr_handler = qlafx00_intr_handler, 2447 .enable_intrs = qlafx00_enable_intrs, 2448 .disable_intrs = qlafx00_disable_intrs, 2449 .abort_command = qla24xx_async_abort_command, 2450 .target_reset = qlafx00_abort_target, 2451 .lun_reset = qlafx00_lun_reset, 2452 .fabric_login = NULL, 2453 .fabric_logout = NULL, 2454 .calc_req_entries = NULL, 2455 .build_iocbs = NULL, 2456 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2457 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2458 .read_nvram = qla24xx_read_nvram_data, 2459 .write_nvram = qla24xx_write_nvram_data, 2460 .fw_dump = NULL, 2461 .beacon_on = qla24xx_beacon_on, 2462 .beacon_off = qla24xx_beacon_off, 2463 .beacon_blink = NULL, 2464 .read_optrom = qla24xx_read_optrom_data, 2465 .write_optrom = qla24xx_write_optrom_data, 2466 .get_flash_version = qla24xx_get_flash_version, 2467 .start_scsi = qlafx00_start_scsi, 2468 .start_scsi_mq = NULL, 2469 .abort_isp = qlafx00_abort_isp, 2470 .iospace_config = qlafx00_iospace_config, 2471 .initialize_adapter = qlafx00_initialize_adapter, 2472 }; 2473 2474 static struct isp_operations qla27xx_isp_ops = { 2475 .pci_config = qla25xx_pci_config, 2476 .reset_chip = qla24xx_reset_chip, 2477 .chip_diag = qla24xx_chip_diag, 2478 .config_rings = qla24xx_config_rings, 2479 .reset_adapter = qla24xx_reset_adapter, 2480 .nvram_config = qla81xx_nvram_config, 2481 .update_fw_options = qla81xx_update_fw_options, 2482 .load_risc = qla81xx_load_risc, 2483 .pci_info_str = qla24xx_pci_info_str, 2484 .fw_version_str = qla24xx_fw_version_str, 2485 .intr_handler = qla24xx_intr_handler, 2486 .enable_intrs = qla24xx_enable_intrs, 2487 .disable_intrs = qla24xx_disable_intrs, 2488 .abort_command = qla24xx_abort_command, 2489 .target_reset = qla24xx_abort_target, 2490 .lun_reset = qla24xx_lun_reset, 2491 .fabric_login = qla24xx_login_fabric, 2492 .fabric_logout = qla24xx_fabric_logout, 2493 .calc_req_entries = NULL, 2494 .build_iocbs = NULL, 2495 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2496 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2497 .read_nvram = NULL, 2498 .write_nvram = NULL, 2499 .fw_dump = qla27xx_fwdump, 2500 .beacon_on = qla24xx_beacon_on, 2501 .beacon_off = qla24xx_beacon_off, 2502 .beacon_blink = qla83xx_beacon_blink, 2503 .read_optrom = qla25xx_read_optrom_data, 2504 .write_optrom = qla24xx_write_optrom_data, 2505 .get_flash_version = qla24xx_get_flash_version, 2506 .start_scsi = qla24xx_dif_start_scsi, 2507 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2508 .abort_isp = qla2x00_abort_isp, 2509 .iospace_config = qla83xx_iospace_config, 2510 .initialize_adapter = qla2x00_initialize_adapter, 2511 }; 2512 2513 static inline void 2514 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2515 { 2516 ha->device_type = DT_EXTENDED_IDS; 2517 switch (ha->pdev->device) { 2518 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2519 ha->isp_type |= DT_ISP2100; 2520 ha->device_type &= ~DT_EXTENDED_IDS; 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2522 break; 2523 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2524 ha->isp_type |= DT_ISP2200; 2525 ha->device_type &= ~DT_EXTENDED_IDS; 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2527 break; 2528 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2529 ha->isp_type |= DT_ISP2300; 2530 ha->device_type |= DT_ZIO_SUPPORTED; 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2532 break; 2533 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2534 ha->isp_type |= DT_ISP2312; 2535 ha->device_type |= DT_ZIO_SUPPORTED; 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2537 break; 2538 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2539 ha->isp_type |= DT_ISP2322; 2540 ha->device_type |= DT_ZIO_SUPPORTED; 2541 if (ha->pdev->subsystem_vendor == 0x1028 && 2542 ha->pdev->subsystem_device == 0x0170) 2543 ha->device_type |= DT_OEM_001; 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2545 break; 2546 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2547 ha->isp_type |= DT_ISP6312; 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2549 break; 2550 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2551 ha->isp_type |= DT_ISP6322; 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2553 break; 2554 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2555 ha->isp_type |= DT_ISP2422; 2556 ha->device_type |= DT_ZIO_SUPPORTED; 2557 ha->device_type |= DT_FWI2; 2558 ha->device_type |= DT_IIDMA; 2559 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2560 break; 2561 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2562 ha->isp_type |= DT_ISP2432; 2563 ha->device_type |= DT_ZIO_SUPPORTED; 2564 ha->device_type |= DT_FWI2; 2565 ha->device_type |= DT_IIDMA; 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2567 break; 2568 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2569 ha->isp_type |= DT_ISP8432; 2570 ha->device_type |= DT_ZIO_SUPPORTED; 2571 ha->device_type |= DT_FWI2; 2572 ha->device_type |= DT_IIDMA; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2576 ha->isp_type |= DT_ISP5422; 2577 ha->device_type |= DT_FWI2; 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2579 break; 2580 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2581 ha->isp_type |= DT_ISP5432; 2582 ha->device_type |= DT_FWI2; 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2584 break; 2585 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2586 ha->isp_type |= DT_ISP2532; 2587 ha->device_type |= DT_ZIO_SUPPORTED; 2588 ha->device_type |= DT_FWI2; 2589 ha->device_type |= DT_IIDMA; 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2591 break; 2592 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2593 ha->isp_type |= DT_ISP8001; 2594 ha->device_type |= DT_ZIO_SUPPORTED; 2595 ha->device_type |= DT_FWI2; 2596 ha->device_type |= DT_IIDMA; 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2600 ha->isp_type |= DT_ISP8021; 2601 ha->device_type |= DT_ZIO_SUPPORTED; 2602 ha->device_type |= DT_FWI2; 2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2604 /* Initialize 82XX ISP flags */ 2605 qla82xx_init_flags(ha); 2606 break; 2607 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2608 ha->isp_type |= DT_ISP8044; 2609 ha->device_type |= DT_ZIO_SUPPORTED; 2610 ha->device_type |= DT_FWI2; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 /* Initialize 82XX ISP flags */ 2613 qla82xx_init_flags(ha); 2614 break; 2615 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2616 ha->isp_type |= DT_ISP2031; 2617 ha->device_type |= DT_ZIO_SUPPORTED; 2618 ha->device_type |= DT_FWI2; 2619 ha->device_type |= DT_IIDMA; 2620 ha->device_type |= DT_T10_PI; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2622 break; 2623 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2624 ha->isp_type |= DT_ISP8031; 2625 ha->device_type |= DT_ZIO_SUPPORTED; 2626 ha->device_type |= DT_FWI2; 2627 ha->device_type |= DT_IIDMA; 2628 ha->device_type |= DT_T10_PI; 2629 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2630 break; 2631 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2632 ha->isp_type |= DT_ISPFX00; 2633 break; 2634 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2635 ha->isp_type |= DT_ISP2071; 2636 ha->device_type |= DT_ZIO_SUPPORTED; 2637 ha->device_type |= DT_FWI2; 2638 ha->device_type |= DT_IIDMA; 2639 ha->device_type |= DT_T10_PI; 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2643 ha->isp_type |= DT_ISP2271; 2644 ha->device_type |= DT_ZIO_SUPPORTED; 2645 ha->device_type |= DT_FWI2; 2646 ha->device_type |= DT_IIDMA; 2647 ha->device_type |= DT_T10_PI; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2651 ha->isp_type |= DT_ISP2261; 2652 ha->device_type |= DT_ZIO_SUPPORTED; 2653 ha->device_type |= DT_FWI2; 2654 ha->device_type |= DT_IIDMA; 2655 ha->device_type |= DT_T10_PI; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2657 break; 2658 } 2659 2660 if (IS_QLA82XX(ha)) 2661 ha->port_no = ha->portnum & 1; 2662 else { 2663 /* Get adapter physical port no from interrupt pin register. */ 2664 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2665 if (IS_QLA27XX(ha)) 2666 ha->port_no--; 2667 else 2668 ha->port_no = !(ha->port_no & 1); 2669 } 2670 2671 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2672 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2673 ha->device_type, ha->port_no, ha->fw_srisc_address); 2674 } 2675 2676 static void 2677 qla2xxx_scan_start(struct Scsi_Host *shost) 2678 { 2679 scsi_qla_host_t *vha = shost_priv(shost); 2680 2681 if (vha->hw->flags.running_gold_fw) 2682 return; 2683 2684 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2685 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2686 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2687 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2688 } 2689 2690 static int 2691 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2692 { 2693 scsi_qla_host_t *vha = shost_priv(shost); 2694 2695 if (test_bit(UNLOADING, &vha->dpc_flags)) 2696 return 1; 2697 if (!vha->host) 2698 return 1; 2699 if (time > vha->hw->loop_reset_delay * HZ) 2700 return 1; 2701 2702 return atomic_read(&vha->loop_state) == LOOP_READY; 2703 } 2704 2705 static void qla2x00_iocb_work_fn(struct work_struct *work) 2706 { 2707 struct scsi_qla_host *vha = container_of(work, 2708 struct scsi_qla_host, iocb_work); 2709 struct qla_hw_data *ha = vha->hw; 2710 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2711 int i = 20; 2712 unsigned long flags; 2713 2714 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2715 return; 2716 2717 while (!list_empty(&vha->work_list) && i > 0) { 2718 qla2x00_do_work(vha); 2719 i--; 2720 } 2721 2722 spin_lock_irqsave(&vha->work_lock, flags); 2723 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2724 spin_unlock_irqrestore(&vha->work_lock, flags); 2725 } 2726 2727 /* 2728 * PCI driver interface 2729 */ 2730 static int 2731 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2732 { 2733 int ret = -ENODEV; 2734 struct Scsi_Host *host; 2735 scsi_qla_host_t *base_vha = NULL; 2736 struct qla_hw_data *ha; 2737 char pci_info[30]; 2738 char fw_str[30], wq_name[30]; 2739 struct scsi_host_template *sht; 2740 int bars, mem_only = 0; 2741 uint16_t req_length = 0, rsp_length = 0; 2742 struct req_que *req = NULL; 2743 struct rsp_que *rsp = NULL; 2744 int i; 2745 2746 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2747 sht = &qla2xxx_driver_template; 2748 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2763 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2764 mem_only = 1; 2765 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2766 "Mem only adapter.\n"); 2767 } 2768 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2769 "Bars=%d.\n", bars); 2770 2771 if (mem_only) { 2772 if (pci_enable_device_mem(pdev)) 2773 return ret; 2774 } else { 2775 if (pci_enable_device(pdev)) 2776 return ret; 2777 } 2778 2779 /* This may fail but that's ok */ 2780 pci_enable_pcie_error_reporting(pdev); 2781 2782 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2783 if (!ha) { 2784 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2785 "Unable to allocate memory for ha.\n"); 2786 goto disable_device; 2787 } 2788 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2789 "Memory allocated for ha=%p.\n", ha); 2790 ha->pdev = pdev; 2791 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2792 spin_lock_init(&ha->tgt.q_full_lock); 2793 spin_lock_init(&ha->tgt.sess_lock); 2794 spin_lock_init(&ha->tgt.atio_lock); 2795 2796 atomic_set(&ha->nvme_active_aen_cnt, 0); 2797 2798 /* Clear our data area */ 2799 ha->bars = bars; 2800 ha->mem_only = mem_only; 2801 spin_lock_init(&ha->hardware_lock); 2802 spin_lock_init(&ha->vport_slock); 2803 mutex_init(&ha->selflogin_lock); 2804 mutex_init(&ha->optrom_mutex); 2805 2806 /* Set ISP-type information. */ 2807 qla2x00_set_isp_flags(ha); 2808 2809 /* Set EEH reset type to fundamental if required by hba */ 2810 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2811 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2812 pdev->needs_freset = 1; 2813 2814 ha->prev_topology = 0; 2815 ha->init_cb_size = sizeof(init_cb_t); 2816 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2817 ha->optrom_size = OPTROM_SIZE_2300; 2818 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2819 atomic_set(&ha->num_pend_mbx_stage1, 0); 2820 atomic_set(&ha->num_pend_mbx_stage2, 0); 2821 atomic_set(&ha->num_pend_mbx_stage3, 0); 2822 2823 /* Assign ISP specific operations. */ 2824 if (IS_QLA2100(ha)) { 2825 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2826 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2827 req_length = REQUEST_ENTRY_CNT_2100; 2828 rsp_length = RESPONSE_ENTRY_CNT_2100; 2829 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2830 ha->gid_list_info_size = 4; 2831 ha->flash_conf_off = ~0; 2832 ha->flash_data_off = ~0; 2833 ha->nvram_conf_off = ~0; 2834 ha->nvram_data_off = ~0; 2835 ha->isp_ops = &qla2100_isp_ops; 2836 } else if (IS_QLA2200(ha)) { 2837 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2838 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2839 req_length = REQUEST_ENTRY_CNT_2200; 2840 rsp_length = RESPONSE_ENTRY_CNT_2100; 2841 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2842 ha->gid_list_info_size = 4; 2843 ha->flash_conf_off = ~0; 2844 ha->flash_data_off = ~0; 2845 ha->nvram_conf_off = ~0; 2846 ha->nvram_data_off = ~0; 2847 ha->isp_ops = &qla2100_isp_ops; 2848 } else if (IS_QLA23XX(ha)) { 2849 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2850 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2851 req_length = REQUEST_ENTRY_CNT_2200; 2852 rsp_length = RESPONSE_ENTRY_CNT_2300; 2853 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2854 ha->gid_list_info_size = 6; 2855 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2856 ha->optrom_size = OPTROM_SIZE_2322; 2857 ha->flash_conf_off = ~0; 2858 ha->flash_data_off = ~0; 2859 ha->nvram_conf_off = ~0; 2860 ha->nvram_data_off = ~0; 2861 ha->isp_ops = &qla2300_isp_ops; 2862 } else if (IS_QLA24XX_TYPE(ha)) { 2863 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2864 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2865 req_length = REQUEST_ENTRY_CNT_24XX; 2866 rsp_length = RESPONSE_ENTRY_CNT_2300; 2867 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2868 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2869 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2870 ha->gid_list_info_size = 8; 2871 ha->optrom_size = OPTROM_SIZE_24XX; 2872 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2873 ha->isp_ops = &qla24xx_isp_ops; 2874 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2875 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2876 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2877 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2878 } else if (IS_QLA25XX(ha)) { 2879 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2880 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2881 req_length = REQUEST_ENTRY_CNT_24XX; 2882 rsp_length = RESPONSE_ENTRY_CNT_2300; 2883 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2884 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2885 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2886 ha->gid_list_info_size = 8; 2887 ha->optrom_size = OPTROM_SIZE_25XX; 2888 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2889 ha->isp_ops = &qla25xx_isp_ops; 2890 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2891 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2892 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2893 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2894 } else if (IS_QLA81XX(ha)) { 2895 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2896 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2897 req_length = REQUEST_ENTRY_CNT_24XX; 2898 rsp_length = RESPONSE_ENTRY_CNT_2300; 2899 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2900 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2901 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2902 ha->gid_list_info_size = 8; 2903 ha->optrom_size = OPTROM_SIZE_81XX; 2904 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2905 ha->isp_ops = &qla81xx_isp_ops; 2906 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2907 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2908 ha->nvram_conf_off = ~0; 2909 ha->nvram_data_off = ~0; 2910 } else if (IS_QLA82XX(ha)) { 2911 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2912 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2913 req_length = REQUEST_ENTRY_CNT_82XX; 2914 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2915 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2916 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2917 ha->gid_list_info_size = 8; 2918 ha->optrom_size = OPTROM_SIZE_82XX; 2919 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2920 ha->isp_ops = &qla82xx_isp_ops; 2921 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2922 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2923 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2924 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2925 } else if (IS_QLA8044(ha)) { 2926 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2927 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2928 req_length = REQUEST_ENTRY_CNT_82XX; 2929 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2930 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2931 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2932 ha->gid_list_info_size = 8; 2933 ha->optrom_size = OPTROM_SIZE_83XX; 2934 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2935 ha->isp_ops = &qla8044_isp_ops; 2936 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2937 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2938 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2939 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2940 } else if (IS_QLA83XX(ha)) { 2941 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2942 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2943 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2944 req_length = REQUEST_ENTRY_CNT_83XX; 2945 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2946 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2947 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2948 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2949 ha->gid_list_info_size = 8; 2950 ha->optrom_size = OPTROM_SIZE_83XX; 2951 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2952 ha->isp_ops = &qla83xx_isp_ops; 2953 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2954 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2955 ha->nvram_conf_off = ~0; 2956 ha->nvram_data_off = ~0; 2957 } else if (IS_QLAFX00(ha)) { 2958 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2959 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2960 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2961 req_length = REQUEST_ENTRY_CNT_FX00; 2962 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2963 ha->isp_ops = &qlafx00_isp_ops; 2964 ha->port_down_retry_count = 30; /* default value */ 2965 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2966 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2967 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2968 ha->mr.fw_hbt_en = 1; 2969 ha->mr.host_info_resend = false; 2970 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2971 } else if (IS_QLA27XX(ha)) { 2972 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2973 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2974 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2975 req_length = REQUEST_ENTRY_CNT_83XX; 2976 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2977 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2978 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2979 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2980 ha->gid_list_info_size = 8; 2981 ha->optrom_size = OPTROM_SIZE_83XX; 2982 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2983 ha->isp_ops = &qla27xx_isp_ops; 2984 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2985 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2986 ha->nvram_conf_off = ~0; 2987 ha->nvram_data_off = ~0; 2988 } 2989 2990 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2991 "mbx_count=%d, req_length=%d, " 2992 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2993 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2994 "max_fibre_devices=%d.\n", 2995 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2996 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2997 ha->nvram_npiv_size, ha->max_fibre_devices); 2998 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2999 "isp_ops=%p, flash_conf_off=%d, " 3000 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3001 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3002 ha->nvram_conf_off, ha->nvram_data_off); 3003 3004 /* Configure PCI I/O space */ 3005 ret = ha->isp_ops->iospace_config(ha); 3006 if (ret) 3007 goto iospace_config_failed; 3008 3009 ql_log_pci(ql_log_info, pdev, 0x001d, 3010 "Found an ISP%04X irq %d iobase 0x%p.\n", 3011 pdev->device, pdev->irq, ha->iobase); 3012 mutex_init(&ha->vport_lock); 3013 mutex_init(&ha->mq_lock); 3014 init_completion(&ha->mbx_cmd_comp); 3015 complete(&ha->mbx_cmd_comp); 3016 init_completion(&ha->mbx_intr_comp); 3017 init_completion(&ha->dcbx_comp); 3018 init_completion(&ha->lb_portup_comp); 3019 3020 set_bit(0, (unsigned long *) ha->vp_idx_map); 3021 3022 qla2x00_config_dma_addressing(ha); 3023 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3024 "64 Bit addressing is %s.\n", 3025 ha->flags.enable_64bit_addressing ? "enable" : 3026 "disable"); 3027 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3028 if (ret) { 3029 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3030 "Failed to allocate memory for adapter, aborting.\n"); 3031 3032 goto probe_hw_failed; 3033 } 3034 3035 req->max_q_depth = MAX_Q_DEPTH; 3036 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3037 req->max_q_depth = ql2xmaxqdepth; 3038 3039 3040 base_vha = qla2x00_create_host(sht, ha); 3041 if (!base_vha) { 3042 ret = -ENOMEM; 3043 goto probe_hw_failed; 3044 } 3045 3046 pci_set_drvdata(pdev, base_vha); 3047 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3048 3049 host = base_vha->host; 3050 base_vha->req = req; 3051 if (IS_QLA2XXX_MIDTYPE(ha)) 3052 base_vha->mgmt_svr_loop_id = 3053 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3054 else 3055 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3056 base_vha->vp_idx; 3057 3058 /* Setup fcport template structure. */ 3059 ha->mr.fcport.vha = base_vha; 3060 ha->mr.fcport.port_type = FCT_UNKNOWN; 3061 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3062 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3063 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3064 ha->mr.fcport.scan_state = 1; 3065 3066 /* Set the SG table size based on ISP type */ 3067 if (!IS_FWI2_CAPABLE(ha)) { 3068 if (IS_QLA2100(ha)) 3069 host->sg_tablesize = 32; 3070 } else { 3071 if (!IS_QLA82XX(ha)) 3072 host->sg_tablesize = QLA_SG_ALL; 3073 } 3074 host->max_id = ha->max_fibre_devices; 3075 host->cmd_per_lun = 3; 3076 host->unique_id = host->host_no; 3077 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3078 host->max_cmd_len = 32; 3079 else 3080 host->max_cmd_len = MAX_CMDSZ; 3081 host->max_channel = MAX_BUSES - 1; 3082 /* Older HBAs support only 16-bit LUNs */ 3083 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3084 ql2xmaxlun > 0xffff) 3085 host->max_lun = 0xffff; 3086 else 3087 host->max_lun = ql2xmaxlun; 3088 host->transportt = qla2xxx_transport_template; 3089 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3090 3091 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3092 "max_id=%d this_id=%d " 3093 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3094 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3095 host->this_id, host->cmd_per_lun, host->unique_id, 3096 host->max_cmd_len, host->max_channel, host->max_lun, 3097 host->transportt, sht->vendor_id); 3098 3099 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3100 3101 /* Set up the irqs */ 3102 ret = qla2x00_request_irqs(ha, rsp); 3103 if (ret) 3104 goto probe_failed; 3105 3106 /* Alloc arrays of request and response ring ptrs */ 3107 ret = qla2x00_alloc_queues(ha, req, rsp); 3108 if (ret) { 3109 ql_log(ql_log_fatal, base_vha, 0x003d, 3110 "Failed to allocate memory for queue pointers..." 3111 "aborting.\n"); 3112 goto probe_failed; 3113 } 3114 3115 if (ha->mqenable && shost_use_blk_mq(host)) { 3116 /* number of hardware queues supported by blk/scsi-mq*/ 3117 host->nr_hw_queues = ha->max_qpairs; 3118 3119 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3120 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3121 } else { 3122 if (ql2xnvmeenable) { 3123 host->nr_hw_queues = ha->max_qpairs; 3124 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3125 "FC-NVMe support is enabled, HW queues=%d\n", 3126 host->nr_hw_queues); 3127 } else { 3128 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3129 "blk/scsi-mq disabled.\n"); 3130 } 3131 } 3132 3133 qlt_probe_one_stage1(base_vha, ha); 3134 3135 pci_save_state(pdev); 3136 3137 /* Assign back pointers */ 3138 rsp->req = req; 3139 req->rsp = rsp; 3140 3141 if (IS_QLAFX00(ha)) { 3142 ha->rsp_q_map[0] = rsp; 3143 ha->req_q_map[0] = req; 3144 set_bit(0, ha->req_qid_map); 3145 set_bit(0, ha->rsp_qid_map); 3146 } 3147 3148 /* FWI2-capable only. */ 3149 req->req_q_in = &ha->iobase->isp24.req_q_in; 3150 req->req_q_out = &ha->iobase->isp24.req_q_out; 3151 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3152 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3153 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3154 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3155 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3156 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3157 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3158 } 3159 3160 if (IS_QLAFX00(ha)) { 3161 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3162 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3163 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3164 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3165 } 3166 3167 if (IS_P3P_TYPE(ha)) { 3168 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3169 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3170 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3171 } 3172 3173 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3174 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3175 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3176 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3177 "req->req_q_in=%p req->req_q_out=%p " 3178 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3179 req->req_q_in, req->req_q_out, 3180 rsp->rsp_q_in, rsp->rsp_q_out); 3181 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3182 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3183 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3184 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3185 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3186 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3187 3188 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3189 3190 if (ha->isp_ops->initialize_adapter(base_vha)) { 3191 ql_log(ql_log_fatal, base_vha, 0x00d6, 3192 "Failed to initialize adapter - Adapter flags %x.\n", 3193 base_vha->device_flags); 3194 3195 if (IS_QLA82XX(ha)) { 3196 qla82xx_idc_lock(ha); 3197 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3198 QLA8XXX_DEV_FAILED); 3199 qla82xx_idc_unlock(ha); 3200 ql_log(ql_log_fatal, base_vha, 0x00d7, 3201 "HW State: FAILED.\n"); 3202 } else if (IS_QLA8044(ha)) { 3203 qla8044_idc_lock(ha); 3204 qla8044_wr_direct(base_vha, 3205 QLA8044_CRB_DEV_STATE_INDEX, 3206 QLA8XXX_DEV_FAILED); 3207 qla8044_idc_unlock(ha); 3208 ql_log(ql_log_fatal, base_vha, 0x0150, 3209 "HW State: FAILED.\n"); 3210 } 3211 3212 ret = -ENODEV; 3213 goto probe_failed; 3214 } 3215 3216 if (IS_QLAFX00(ha)) 3217 host->can_queue = QLAFX00_MAX_CANQUEUE; 3218 else 3219 host->can_queue = req->num_outstanding_cmds - 10; 3220 3221 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3222 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3223 host->can_queue, base_vha->req, 3224 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3225 3226 if (ha->mqenable) { 3227 bool mq = false; 3228 bool startit = false; 3229 3230 if (QLA_TGT_MODE_ENABLED()) { 3231 mq = true; 3232 startit = false; 3233 } 3234 3235 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3236 shost_use_blk_mq(host)) { 3237 mq = true; 3238 startit = true; 3239 } 3240 3241 if (mq) { 3242 /* Create start of day qpairs for Block MQ */ 3243 for (i = 0; i < ha->max_qpairs; i++) 3244 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3245 } 3246 } 3247 3248 if (ha->flags.running_gold_fw) 3249 goto skip_dpc; 3250 3251 /* 3252 * Startup the kernel thread for this host adapter 3253 */ 3254 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3255 "%s_dpc", base_vha->host_str); 3256 if (IS_ERR(ha->dpc_thread)) { 3257 ql_log(ql_log_fatal, base_vha, 0x00ed, 3258 "Failed to start DPC thread.\n"); 3259 ret = PTR_ERR(ha->dpc_thread); 3260 ha->dpc_thread = NULL; 3261 goto probe_failed; 3262 } 3263 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3264 "DPC thread started successfully.\n"); 3265 3266 /* 3267 * If we're not coming up in initiator mode, we might sit for 3268 * a while without waking up the dpc thread, which leads to a 3269 * stuck process warning. So just kick the dpc once here and 3270 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3271 */ 3272 qla2xxx_wake_dpc(base_vha); 3273 3274 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3275 3276 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3277 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3278 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3279 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3280 3281 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3282 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3283 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3284 INIT_WORK(&ha->idc_state_handler, 3285 qla83xx_idc_state_handler_work); 3286 INIT_WORK(&ha->nic_core_unrecoverable, 3287 qla83xx_nic_core_unrecoverable_work); 3288 } 3289 3290 skip_dpc: 3291 list_add_tail(&base_vha->list, &ha->vp_list); 3292 base_vha->host->irq = ha->pdev->irq; 3293 3294 /* Initialized the timer */ 3295 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3296 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3297 "Started qla2x00_timer with " 3298 "interval=%d.\n", WATCH_INTERVAL); 3299 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3300 "Detected hba at address=%p.\n", 3301 ha); 3302 3303 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3304 if (ha->fw_attributes & BIT_4) { 3305 int prot = 0, guard; 3306 base_vha->flags.difdix_supported = 1; 3307 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3308 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3309 if (ql2xenabledif == 1) 3310 prot = SHOST_DIX_TYPE0_PROTECTION; 3311 scsi_host_set_prot(host, 3312 prot | SHOST_DIF_TYPE1_PROTECTION 3313 | SHOST_DIF_TYPE2_PROTECTION 3314 | SHOST_DIF_TYPE3_PROTECTION 3315 | SHOST_DIX_TYPE1_PROTECTION 3316 | SHOST_DIX_TYPE2_PROTECTION 3317 | SHOST_DIX_TYPE3_PROTECTION); 3318 3319 guard = SHOST_DIX_GUARD_CRC; 3320 3321 if (IS_PI_IPGUARD_CAPABLE(ha) && 3322 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3323 guard |= SHOST_DIX_GUARD_IP; 3324 3325 scsi_host_set_guard(host, guard); 3326 } else 3327 base_vha->flags.difdix_supported = 0; 3328 } 3329 3330 ha->isp_ops->enable_intrs(ha); 3331 3332 if (IS_QLAFX00(ha)) { 3333 ret = qlafx00_fx_disc(base_vha, 3334 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3335 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3336 QLA_SG_ALL : 128; 3337 } 3338 3339 ret = scsi_add_host(host, &pdev->dev); 3340 if (ret) 3341 goto probe_failed; 3342 3343 base_vha->flags.init_done = 1; 3344 base_vha->flags.online = 1; 3345 ha->prev_minidump_failed = 0; 3346 3347 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3348 "Init done and hba is online.\n"); 3349 3350 if (qla_ini_mode_enabled(base_vha) || 3351 qla_dual_mode_enabled(base_vha)) 3352 scsi_scan_host(host); 3353 else 3354 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3355 "skipping scsi_scan_host() for non-initiator port\n"); 3356 3357 qla2x00_alloc_sysfs_attr(base_vha); 3358 3359 if (IS_QLAFX00(ha)) { 3360 ret = qlafx00_fx_disc(base_vha, 3361 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3362 3363 /* Register system information */ 3364 ret = qlafx00_fx_disc(base_vha, 3365 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3366 } 3367 3368 qla2x00_init_host_attr(base_vha); 3369 3370 qla2x00_dfs_setup(base_vha); 3371 3372 ql_log(ql_log_info, base_vha, 0x00fb, 3373 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3374 ql_log(ql_log_info, base_vha, 0x00fc, 3375 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3376 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3377 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3378 base_vha->host_no, 3379 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3380 3381 qlt_add_target(ha, base_vha); 3382 3383 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3384 3385 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3386 return -ENODEV; 3387 3388 if (ha->flags.detected_lr_sfp) { 3389 ql_log(ql_log_info, base_vha, 0xffff, 3390 "Reset chip to pick up LR SFP setting\n"); 3391 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3392 qla2xxx_wake_dpc(base_vha); 3393 } 3394 3395 return 0; 3396 3397 probe_failed: 3398 if (base_vha->timer_active) 3399 qla2x00_stop_timer(base_vha); 3400 base_vha->flags.online = 0; 3401 if (ha->dpc_thread) { 3402 struct task_struct *t = ha->dpc_thread; 3403 3404 ha->dpc_thread = NULL; 3405 kthread_stop(t); 3406 } 3407 3408 qla2x00_free_device(base_vha); 3409 scsi_host_put(base_vha->host); 3410 /* 3411 * Need to NULL out local req/rsp after 3412 * qla2x00_free_device => qla2x00_free_queues frees 3413 * what these are pointing to. Or else we'll 3414 * fall over below in qla2x00_free_req/rsp_que. 3415 */ 3416 req = NULL; 3417 rsp = NULL; 3418 3419 probe_hw_failed: 3420 qla2x00_mem_free(ha); 3421 qla2x00_free_req_que(ha, req); 3422 qla2x00_free_rsp_que(ha, rsp); 3423 qla2x00_clear_drv_active(ha); 3424 3425 iospace_config_failed: 3426 if (IS_P3P_TYPE(ha)) { 3427 if (!ha->nx_pcibase) 3428 iounmap((device_reg_t *)ha->nx_pcibase); 3429 if (!ql2xdbwr) 3430 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3431 } else { 3432 if (ha->iobase) 3433 iounmap(ha->iobase); 3434 if (ha->cregbase) 3435 iounmap(ha->cregbase); 3436 } 3437 pci_release_selected_regions(ha->pdev, ha->bars); 3438 kfree(ha); 3439 3440 disable_device: 3441 pci_disable_device(pdev); 3442 return ret; 3443 } 3444 3445 static void 3446 qla2x00_shutdown(struct pci_dev *pdev) 3447 { 3448 scsi_qla_host_t *vha; 3449 struct qla_hw_data *ha; 3450 3451 vha = pci_get_drvdata(pdev); 3452 ha = vha->hw; 3453 3454 ql_log(ql_log_info, vha, 0xfffa, 3455 "Adapter shutdown\n"); 3456 3457 /* 3458 * Prevent future board_disable and wait 3459 * until any pending board_disable has completed. 3460 */ 3461 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3462 cancel_work_sync(&ha->board_disable); 3463 3464 if (!atomic_read(&pdev->enable_cnt)) 3465 return; 3466 3467 /* Notify ISPFX00 firmware */ 3468 if (IS_QLAFX00(ha)) 3469 qlafx00_driver_shutdown(vha, 20); 3470 3471 /* Turn-off FCE trace */ 3472 if (ha->flags.fce_enabled) { 3473 qla2x00_disable_fce_trace(vha, NULL, NULL); 3474 ha->flags.fce_enabled = 0; 3475 } 3476 3477 /* Turn-off EFT trace */ 3478 if (ha->eft) 3479 qla2x00_disable_eft_trace(vha); 3480 3481 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3482 if (ha->flags.fw_started) 3483 qla2x00_abort_isp_cleanup(vha); 3484 } else { 3485 /* Stop currently executing firmware. */ 3486 qla2x00_try_to_stop_firmware(vha); 3487 } 3488 3489 /* Turn adapter off line */ 3490 vha->flags.online = 0; 3491 3492 /* turn-off interrupts on the card */ 3493 if (ha->interrupts_on) { 3494 vha->flags.init_done = 0; 3495 ha->isp_ops->disable_intrs(ha); 3496 } 3497 3498 qla2x00_free_irqs(vha); 3499 3500 qla2x00_free_fw_dump(ha); 3501 3502 pci_disable_device(pdev); 3503 ql_log(ql_log_info, vha, 0xfffe, 3504 "Adapter shutdown successfully.\n"); 3505 } 3506 3507 /* Deletes all the virtual ports for a given ha */ 3508 static void 3509 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3510 { 3511 scsi_qla_host_t *vha; 3512 unsigned long flags; 3513 3514 mutex_lock(&ha->vport_lock); 3515 while (ha->cur_vport_count) { 3516 spin_lock_irqsave(&ha->vport_slock, flags); 3517 3518 BUG_ON(base_vha->list.next == &ha->vp_list); 3519 /* This assumes first entry in ha->vp_list is always base vha */ 3520 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3521 scsi_host_get(vha->host); 3522 3523 spin_unlock_irqrestore(&ha->vport_slock, flags); 3524 mutex_unlock(&ha->vport_lock); 3525 3526 fc_vport_terminate(vha->fc_vport); 3527 scsi_host_put(vha->host); 3528 3529 mutex_lock(&ha->vport_lock); 3530 } 3531 mutex_unlock(&ha->vport_lock); 3532 } 3533 3534 /* Stops all deferred work threads */ 3535 static void 3536 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3537 { 3538 /* Cancel all work and destroy DPC workqueues */ 3539 if (ha->dpc_lp_wq) { 3540 cancel_work_sync(&ha->idc_aen); 3541 destroy_workqueue(ha->dpc_lp_wq); 3542 ha->dpc_lp_wq = NULL; 3543 } 3544 3545 if (ha->dpc_hp_wq) { 3546 cancel_work_sync(&ha->nic_core_reset); 3547 cancel_work_sync(&ha->idc_state_handler); 3548 cancel_work_sync(&ha->nic_core_unrecoverable); 3549 destroy_workqueue(ha->dpc_hp_wq); 3550 ha->dpc_hp_wq = NULL; 3551 } 3552 3553 /* Kill the kernel thread for this host */ 3554 if (ha->dpc_thread) { 3555 struct task_struct *t = ha->dpc_thread; 3556 3557 /* 3558 * qla2xxx_wake_dpc checks for ->dpc_thread 3559 * so we need to zero it out. 3560 */ 3561 ha->dpc_thread = NULL; 3562 kthread_stop(t); 3563 } 3564 } 3565 3566 static void 3567 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3568 { 3569 if (IS_QLA82XX(ha)) { 3570 3571 iounmap((device_reg_t *)ha->nx_pcibase); 3572 if (!ql2xdbwr) 3573 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3574 } else { 3575 if (ha->iobase) 3576 iounmap(ha->iobase); 3577 3578 if (ha->cregbase) 3579 iounmap(ha->cregbase); 3580 3581 if (ha->mqiobase) 3582 iounmap(ha->mqiobase); 3583 3584 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3585 iounmap(ha->msixbase); 3586 } 3587 } 3588 3589 static void 3590 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3591 { 3592 if (IS_QLA8044(ha)) { 3593 qla8044_idc_lock(ha); 3594 qla8044_clear_drv_active(ha); 3595 qla8044_idc_unlock(ha); 3596 } else if (IS_QLA82XX(ha)) { 3597 qla82xx_idc_lock(ha); 3598 qla82xx_clear_drv_active(ha); 3599 qla82xx_idc_unlock(ha); 3600 } 3601 } 3602 3603 static void 3604 qla2x00_remove_one(struct pci_dev *pdev) 3605 { 3606 scsi_qla_host_t *base_vha; 3607 struct qla_hw_data *ha; 3608 3609 base_vha = pci_get_drvdata(pdev); 3610 ha = base_vha->hw; 3611 ql_log(ql_log_info, base_vha, 0xb079, 3612 "Removing driver\n"); 3613 3614 /* Indicate device removal to prevent future board_disable and wait 3615 * until any pending board_disable has completed. */ 3616 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3617 cancel_work_sync(&ha->board_disable); 3618 3619 /* 3620 * If the PCI device is disabled then there was a PCI-disconnect and 3621 * qla2x00_disable_board_on_pci_error has taken care of most of the 3622 * resources. 3623 */ 3624 if (!atomic_read(&pdev->enable_cnt)) { 3625 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3626 base_vha->gnl.l, base_vha->gnl.ldma); 3627 3628 scsi_host_put(base_vha->host); 3629 kfree(ha); 3630 pci_set_drvdata(pdev, NULL); 3631 return; 3632 } 3633 qla2x00_wait_for_hba_ready(base_vha); 3634 3635 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3636 if (ha->flags.fw_started) 3637 qla2x00_abort_isp_cleanup(base_vha); 3638 } else if (!IS_QLAFX00(ha)) { 3639 if (IS_QLA8031(ha)) { 3640 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3641 "Clearing fcoe driver presence.\n"); 3642 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3643 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3644 "Error while clearing DRV-Presence.\n"); 3645 } 3646 3647 qla2x00_try_to_stop_firmware(base_vha); 3648 } 3649 3650 qla2x00_wait_for_sess_deletion(base_vha); 3651 3652 /* 3653 * if UNLOAD flag is already set, then continue unload, 3654 * where it was set first. 3655 */ 3656 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3657 return; 3658 3659 set_bit(UNLOADING, &base_vha->dpc_flags); 3660 3661 qla_nvme_delete(base_vha); 3662 3663 dma_free_coherent(&ha->pdev->dev, 3664 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3665 3666 vfree(base_vha->scan.l); 3667 3668 if (IS_QLAFX00(ha)) 3669 qlafx00_driver_shutdown(base_vha, 20); 3670 3671 qla2x00_delete_all_vps(ha, base_vha); 3672 3673 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3674 3675 qla2x00_dfs_remove(base_vha); 3676 3677 qla84xx_put_chip(base_vha); 3678 3679 /* Disable timer */ 3680 if (base_vha->timer_active) 3681 qla2x00_stop_timer(base_vha); 3682 3683 base_vha->flags.online = 0; 3684 3685 /* free DMA memory */ 3686 if (ha->exlogin_buf) 3687 qla2x00_free_exlogin_buffer(ha); 3688 3689 /* free DMA memory */ 3690 if (ha->exchoffld_buf) 3691 qla2x00_free_exchoffld_buffer(ha); 3692 3693 qla2x00_destroy_deferred_work(ha); 3694 3695 qlt_remove_target(ha, base_vha); 3696 3697 qla2x00_free_sysfs_attr(base_vha, true); 3698 3699 fc_remove_host(base_vha->host); 3700 qlt_remove_target_resources(ha); 3701 3702 scsi_remove_host(base_vha->host); 3703 3704 qla2x00_free_device(base_vha); 3705 3706 qla2x00_clear_drv_active(ha); 3707 3708 scsi_host_put(base_vha->host); 3709 3710 qla2x00_unmap_iobases(ha); 3711 3712 pci_release_selected_regions(ha->pdev, ha->bars); 3713 kfree(ha); 3714 3715 pci_disable_pcie_error_reporting(pdev); 3716 3717 pci_disable_device(pdev); 3718 } 3719 3720 static void 3721 qla2x00_free_device(scsi_qla_host_t *vha) 3722 { 3723 struct qla_hw_data *ha = vha->hw; 3724 3725 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3726 3727 /* Disable timer */ 3728 if (vha->timer_active) 3729 qla2x00_stop_timer(vha); 3730 3731 qla25xx_delete_queues(vha); 3732 vha->flags.online = 0; 3733 3734 /* turn-off interrupts on the card */ 3735 if (ha->interrupts_on) { 3736 vha->flags.init_done = 0; 3737 ha->isp_ops->disable_intrs(ha); 3738 } 3739 3740 qla2x00_free_fcports(vha); 3741 3742 qla2x00_free_irqs(vha); 3743 3744 /* Flush the work queue and remove it */ 3745 if (ha->wq) { 3746 flush_workqueue(ha->wq); 3747 destroy_workqueue(ha->wq); 3748 ha->wq = NULL; 3749 } 3750 3751 3752 qla2x00_mem_free(ha); 3753 3754 qla82xx_md_free(vha); 3755 3756 qla2x00_free_queues(ha); 3757 } 3758 3759 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3760 { 3761 fc_port_t *fcport, *tfcport; 3762 3763 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3764 list_del(&fcport->list); 3765 qla2x00_clear_loop_id(fcport); 3766 kfree(fcport); 3767 } 3768 } 3769 3770 static inline void 3771 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3772 int defer) 3773 { 3774 struct fc_rport *rport; 3775 scsi_qla_host_t *base_vha; 3776 unsigned long flags; 3777 3778 if (!fcport->rport) 3779 return; 3780 3781 rport = fcport->rport; 3782 if (defer) { 3783 base_vha = pci_get_drvdata(vha->hw->pdev); 3784 spin_lock_irqsave(vha->host->host_lock, flags); 3785 fcport->drport = rport; 3786 spin_unlock_irqrestore(vha->host->host_lock, flags); 3787 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3788 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3789 qla2xxx_wake_dpc(base_vha); 3790 } else { 3791 int now; 3792 if (rport) { 3793 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3794 "%s %8phN. rport %p roles %x\n", 3795 __func__, fcport->port_name, rport, 3796 rport->roles); 3797 fc_remote_port_delete(rport); 3798 } 3799 qlt_do_generation_tick(vha, &now); 3800 } 3801 } 3802 3803 /* 3804 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3805 * 3806 * Input: ha = adapter block pointer. fcport = port structure pointer. 3807 * 3808 * Return: None. 3809 * 3810 * Context: 3811 */ 3812 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3813 int do_login, int defer) 3814 { 3815 if (IS_QLAFX00(vha->hw)) { 3816 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3817 qla2x00_schedule_rport_del(vha, fcport, defer); 3818 return; 3819 } 3820 3821 if (atomic_read(&fcport->state) == FCS_ONLINE && 3822 vha->vp_idx == fcport->vha->vp_idx) { 3823 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3824 qla2x00_schedule_rport_del(vha, fcport, defer); 3825 } 3826 /* 3827 * We may need to retry the login, so don't change the state of the 3828 * port but do the retries. 3829 */ 3830 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3831 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3832 3833 if (!do_login) 3834 return; 3835 3836 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3837 } 3838 3839 /* 3840 * qla2x00_mark_all_devices_lost 3841 * Updates fcport state when device goes offline. 3842 * 3843 * Input: 3844 * ha = adapter block pointer. 3845 * fcport = port structure pointer. 3846 * 3847 * Return: 3848 * None. 3849 * 3850 * Context: 3851 */ 3852 void 3853 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3854 { 3855 fc_port_t *fcport; 3856 3857 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3858 "Mark all dev lost\n"); 3859 3860 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3861 fcport->scan_state = 0; 3862 qlt_schedule_sess_for_deletion(fcport); 3863 3864 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3865 continue; 3866 3867 /* 3868 * No point in marking the device as lost, if the device is 3869 * already DEAD. 3870 */ 3871 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3872 continue; 3873 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3874 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3875 if (defer) 3876 qla2x00_schedule_rport_del(vha, fcport, defer); 3877 else if (vha->vp_idx == fcport->vha->vp_idx) 3878 qla2x00_schedule_rport_del(vha, fcport, defer); 3879 } 3880 } 3881 } 3882 3883 /* 3884 * qla2x00_mem_alloc 3885 * Allocates adapter memory. 3886 * 3887 * Returns: 3888 * 0 = success. 3889 * !0 = failure. 3890 */ 3891 static int 3892 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3893 struct req_que **req, struct rsp_que **rsp) 3894 { 3895 char name[16]; 3896 3897 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3898 &ha->init_cb_dma, GFP_KERNEL); 3899 if (!ha->init_cb) 3900 goto fail; 3901 3902 if (qlt_mem_alloc(ha) < 0) 3903 goto fail_free_init_cb; 3904 3905 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3906 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3907 if (!ha->gid_list) 3908 goto fail_free_tgt_mem; 3909 3910 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3911 if (!ha->srb_mempool) 3912 goto fail_free_gid_list; 3913 3914 if (IS_P3P_TYPE(ha)) { 3915 /* Allocate cache for CT6 Ctx. */ 3916 if (!ctx_cachep) { 3917 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3918 sizeof(struct ct6_dsd), 0, 3919 SLAB_HWCACHE_ALIGN, NULL); 3920 if (!ctx_cachep) 3921 goto fail_free_srb_mempool; 3922 } 3923 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3924 ctx_cachep); 3925 if (!ha->ctx_mempool) 3926 goto fail_free_srb_mempool; 3927 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3928 "ctx_cachep=%p ctx_mempool=%p.\n", 3929 ctx_cachep, ha->ctx_mempool); 3930 } 3931 3932 /* Get memory for cached NVRAM */ 3933 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3934 if (!ha->nvram) 3935 goto fail_free_ctx_mempool; 3936 3937 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3938 ha->pdev->device); 3939 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3940 DMA_POOL_SIZE, 8, 0); 3941 if (!ha->s_dma_pool) 3942 goto fail_free_nvram; 3943 3944 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3945 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3946 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3947 3948 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3949 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3950 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3951 if (!ha->dl_dma_pool) { 3952 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3953 "Failed to allocate memory for dl_dma_pool.\n"); 3954 goto fail_s_dma_pool; 3955 } 3956 3957 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3958 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3959 if (!ha->fcp_cmnd_dma_pool) { 3960 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3961 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3962 goto fail_dl_dma_pool; 3963 } 3964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3965 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3966 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3967 } 3968 3969 /* Allocate memory for SNS commands */ 3970 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3971 /* Get consistent memory allocated for SNS commands */ 3972 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3973 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3974 if (!ha->sns_cmd) 3975 goto fail_dma_pool; 3976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3977 "sns_cmd: %p.\n", ha->sns_cmd); 3978 } else { 3979 /* Get consistent memory allocated for MS IOCB */ 3980 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3981 &ha->ms_iocb_dma); 3982 if (!ha->ms_iocb) 3983 goto fail_dma_pool; 3984 /* Get consistent memory allocated for CT SNS commands */ 3985 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3986 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3987 if (!ha->ct_sns) 3988 goto fail_free_ms_iocb; 3989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3990 "ms_iocb=%p ct_sns=%p.\n", 3991 ha->ms_iocb, ha->ct_sns); 3992 } 3993 3994 /* Allocate memory for request ring */ 3995 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3996 if (!*req) { 3997 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3998 "Failed to allocate memory for req.\n"); 3999 goto fail_req; 4000 } 4001 (*req)->length = req_len; 4002 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4003 ((*req)->length + 1) * sizeof(request_t), 4004 &(*req)->dma, GFP_KERNEL); 4005 if (!(*req)->ring) { 4006 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4007 "Failed to allocate memory for req_ring.\n"); 4008 goto fail_req_ring; 4009 } 4010 /* Allocate memory for response ring */ 4011 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4012 if (!*rsp) { 4013 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4014 "Failed to allocate memory for rsp.\n"); 4015 goto fail_rsp; 4016 } 4017 (*rsp)->hw = ha; 4018 (*rsp)->length = rsp_len; 4019 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4020 ((*rsp)->length + 1) * sizeof(response_t), 4021 &(*rsp)->dma, GFP_KERNEL); 4022 if (!(*rsp)->ring) { 4023 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4024 "Failed to allocate memory for rsp_ring.\n"); 4025 goto fail_rsp_ring; 4026 } 4027 (*req)->rsp = *rsp; 4028 (*rsp)->req = *req; 4029 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4030 "req=%p req->length=%d req->ring=%p rsp=%p " 4031 "rsp->length=%d rsp->ring=%p.\n", 4032 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4033 (*rsp)->ring); 4034 /* Allocate memory for NVRAM data for vports */ 4035 if (ha->nvram_npiv_size) { 4036 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4037 sizeof(struct qla_npiv_entry), 4038 GFP_KERNEL); 4039 if (!ha->npiv_info) { 4040 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4041 "Failed to allocate memory for npiv_info.\n"); 4042 goto fail_npiv_info; 4043 } 4044 } else 4045 ha->npiv_info = NULL; 4046 4047 /* Get consistent memory allocated for EX-INIT-CB. */ 4048 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4049 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4050 &ha->ex_init_cb_dma); 4051 if (!ha->ex_init_cb) 4052 goto fail_ex_init_cb; 4053 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4054 "ex_init_cb=%p.\n", ha->ex_init_cb); 4055 } 4056 4057 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4058 4059 /* Get consistent memory allocated for Async Port-Database. */ 4060 if (!IS_FWI2_CAPABLE(ha)) { 4061 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4062 &ha->async_pd_dma); 4063 if (!ha->async_pd) 4064 goto fail_async_pd; 4065 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4066 "async_pd=%p.\n", ha->async_pd); 4067 } 4068 4069 INIT_LIST_HEAD(&ha->vp_list); 4070 4071 /* Allocate memory for our loop_id bitmap */ 4072 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4073 sizeof(long), 4074 GFP_KERNEL); 4075 if (!ha->loop_id_map) 4076 goto fail_loop_id_map; 4077 else { 4078 qla2x00_set_reserved_loop_ids(ha); 4079 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4080 "loop_id_map=%p.\n", ha->loop_id_map); 4081 } 4082 4083 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4084 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4085 if (!ha->sfp_data) { 4086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4087 "Unable to allocate memory for SFP read-data.\n"); 4088 goto fail_sfp_data; 4089 } 4090 4091 return 0; 4092 4093 fail_sfp_data: 4094 kfree(ha->loop_id_map); 4095 fail_loop_id_map: 4096 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4097 fail_async_pd: 4098 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4099 fail_ex_init_cb: 4100 kfree(ha->npiv_info); 4101 fail_npiv_info: 4102 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4103 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4104 (*rsp)->ring = NULL; 4105 (*rsp)->dma = 0; 4106 fail_rsp_ring: 4107 kfree(*rsp); 4108 *rsp = NULL; 4109 fail_rsp: 4110 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4111 sizeof(request_t), (*req)->ring, (*req)->dma); 4112 (*req)->ring = NULL; 4113 (*req)->dma = 0; 4114 fail_req_ring: 4115 kfree(*req); 4116 *req = NULL; 4117 fail_req: 4118 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4119 ha->ct_sns, ha->ct_sns_dma); 4120 ha->ct_sns = NULL; 4121 ha->ct_sns_dma = 0; 4122 fail_free_ms_iocb: 4123 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4124 ha->ms_iocb = NULL; 4125 ha->ms_iocb_dma = 0; 4126 4127 if (ha->sns_cmd) 4128 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4129 ha->sns_cmd, ha->sns_cmd_dma); 4130 fail_dma_pool: 4131 if (IS_QLA82XX(ha) || ql2xenabledif) { 4132 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4133 ha->fcp_cmnd_dma_pool = NULL; 4134 } 4135 fail_dl_dma_pool: 4136 if (IS_QLA82XX(ha) || ql2xenabledif) { 4137 dma_pool_destroy(ha->dl_dma_pool); 4138 ha->dl_dma_pool = NULL; 4139 } 4140 fail_s_dma_pool: 4141 dma_pool_destroy(ha->s_dma_pool); 4142 ha->s_dma_pool = NULL; 4143 fail_free_nvram: 4144 kfree(ha->nvram); 4145 ha->nvram = NULL; 4146 fail_free_ctx_mempool: 4147 if (ha->ctx_mempool) 4148 mempool_destroy(ha->ctx_mempool); 4149 ha->ctx_mempool = NULL; 4150 fail_free_srb_mempool: 4151 if (ha->srb_mempool) 4152 mempool_destroy(ha->srb_mempool); 4153 ha->srb_mempool = NULL; 4154 fail_free_gid_list: 4155 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4156 ha->gid_list, 4157 ha->gid_list_dma); 4158 ha->gid_list = NULL; 4159 ha->gid_list_dma = 0; 4160 fail_free_tgt_mem: 4161 qlt_mem_free(ha); 4162 fail_free_init_cb: 4163 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4164 ha->init_cb_dma); 4165 ha->init_cb = NULL; 4166 ha->init_cb_dma = 0; 4167 fail: 4168 ql_log(ql_log_fatal, NULL, 0x0030, 4169 "Memory allocation failure.\n"); 4170 return -ENOMEM; 4171 } 4172 4173 int 4174 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4175 { 4176 int rval; 4177 uint16_t size, max_cnt, temp; 4178 struct qla_hw_data *ha = vha->hw; 4179 4180 /* Return if we don't need to alloacate any extended logins */ 4181 if (!ql2xexlogins) 4182 return QLA_SUCCESS; 4183 4184 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4185 return QLA_SUCCESS; 4186 4187 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4188 max_cnt = 0; 4189 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4190 if (rval != QLA_SUCCESS) { 4191 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4192 "Failed to get exlogin status.\n"); 4193 return rval; 4194 } 4195 4196 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4197 temp *= size; 4198 4199 if (temp != ha->exlogin_size) { 4200 qla2x00_free_exlogin_buffer(ha); 4201 ha->exlogin_size = temp; 4202 4203 ql_log(ql_log_info, vha, 0xd024, 4204 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4205 max_cnt, size, temp); 4206 4207 ql_log(ql_log_info, vha, 0xd025, 4208 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4209 4210 /* Get consistent memory for extended logins */ 4211 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4212 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4213 if (!ha->exlogin_buf) { 4214 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4215 "Failed to allocate memory for exlogin_buf_dma.\n"); 4216 return -ENOMEM; 4217 } 4218 } 4219 4220 /* Now configure the dma buffer */ 4221 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4222 if (rval) { 4223 ql_log(ql_log_fatal, vha, 0xd033, 4224 "Setup extended login buffer ****FAILED****.\n"); 4225 qla2x00_free_exlogin_buffer(ha); 4226 } 4227 4228 return rval; 4229 } 4230 4231 /* 4232 * qla2x00_free_exlogin_buffer 4233 * 4234 * Input: 4235 * ha = adapter block pointer 4236 */ 4237 void 4238 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4239 { 4240 if (ha->exlogin_buf) { 4241 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4242 ha->exlogin_buf, ha->exlogin_buf_dma); 4243 ha->exlogin_buf = NULL; 4244 ha->exlogin_size = 0; 4245 } 4246 } 4247 4248 static void 4249 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4250 { 4251 u32 temp; 4252 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4253 4254 if (max_cnt > vha->hw->max_exchg) 4255 max_cnt = vha->hw->max_exchg; 4256 4257 if (qla_ini_mode_enabled(vha)) { 4258 if (ql2xiniexchg > max_cnt) 4259 ql2xiniexchg = max_cnt; 4260 4261 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4262 *ret_cnt = ql2xiniexchg; 4263 } else if (qla_tgt_mode_enabled(vha)) { 4264 if (ql2xexchoffld > max_cnt) 4265 ql2xexchoffld = max_cnt; 4266 4267 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4268 *ret_cnt = ql2xexchoffld; 4269 } else if (qla_dual_mode_enabled(vha)) { 4270 temp = ql2xiniexchg + ql2xexchoffld; 4271 if (temp > max_cnt) { 4272 ql2xiniexchg -= (temp - max_cnt)/2; 4273 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4274 temp = max_cnt; 4275 } 4276 4277 if (temp > FW_DEF_EXCHANGES_CNT) 4278 *ret_cnt = temp; 4279 } 4280 } 4281 4282 int 4283 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4284 { 4285 int rval; 4286 u16 size, max_cnt; 4287 u32 actual_cnt, totsz; 4288 struct qla_hw_data *ha = vha->hw; 4289 4290 if (!ha->flags.exchoffld_enabled) 4291 return QLA_SUCCESS; 4292 4293 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4294 return QLA_SUCCESS; 4295 4296 max_cnt = 0; 4297 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4298 if (rval != QLA_SUCCESS) { 4299 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4300 "Failed to get exlogin status.\n"); 4301 return rval; 4302 } 4303 4304 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4305 ql_log(ql_log_info, vha, 0xd014, 4306 "Actual exchange offload count: %d.\n", actual_cnt); 4307 4308 totsz = actual_cnt * size; 4309 4310 if (totsz != ha->exchoffld_size) { 4311 qla2x00_free_exchoffld_buffer(ha); 4312 ha->exchoffld_size = totsz; 4313 4314 ql_log(ql_log_info, vha, 0xd016, 4315 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4316 max_cnt, actual_cnt, size, totsz); 4317 4318 ql_log(ql_log_info, vha, 0xd017, 4319 "Exchange Buffers requested size = 0x%x\n", 4320 ha->exchoffld_size); 4321 4322 /* Get consistent memory for extended logins */ 4323 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4324 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4325 if (!ha->exchoffld_buf) { 4326 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4327 "Failed to allocate memory for Exchange Offload.\n"); 4328 4329 if (ha->max_exchg > 4330 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4331 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4332 } else if (ha->max_exchg > 4333 (FW_DEF_EXCHANGES_CNT + 512)) { 4334 ha->max_exchg -= 512; 4335 } else { 4336 ha->flags.exchoffld_enabled = 0; 4337 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4338 "Disabling Exchange offload due to lack of memory\n"); 4339 } 4340 ha->exchoffld_size = 0; 4341 4342 return -ENOMEM; 4343 } 4344 } 4345 4346 /* Now configure the dma buffer */ 4347 rval = qla_set_exchoffld_mem_cfg(vha); 4348 if (rval) { 4349 ql_log(ql_log_fatal, vha, 0xd02e, 4350 "Setup exchange offload buffer ****FAILED****.\n"); 4351 qla2x00_free_exchoffld_buffer(ha); 4352 } else { 4353 /* re-adjust number of target exchange */ 4354 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4355 4356 if (qla_ini_mode_enabled(vha)) 4357 icb->exchange_count = 0; 4358 else 4359 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4360 } 4361 4362 return rval; 4363 } 4364 4365 /* 4366 * qla2x00_free_exchoffld_buffer 4367 * 4368 * Input: 4369 * ha = adapter block pointer 4370 */ 4371 void 4372 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4373 { 4374 if (ha->exchoffld_buf) { 4375 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4376 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4377 ha->exchoffld_buf = NULL; 4378 ha->exchoffld_size = 0; 4379 } 4380 } 4381 4382 /* 4383 * qla2x00_free_fw_dump 4384 * Frees fw dump stuff. 4385 * 4386 * Input: 4387 * ha = adapter block pointer 4388 */ 4389 static void 4390 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4391 { 4392 if (ha->fce) 4393 dma_free_coherent(&ha->pdev->dev, 4394 FCE_SIZE, ha->fce, ha->fce_dma); 4395 4396 if (ha->eft) 4397 dma_free_coherent(&ha->pdev->dev, 4398 EFT_SIZE, ha->eft, ha->eft_dma); 4399 4400 if (ha->fw_dump) 4401 vfree(ha->fw_dump); 4402 if (ha->fw_dump_template) 4403 vfree(ha->fw_dump_template); 4404 4405 ha->fce = NULL; 4406 ha->fce_dma = 0; 4407 ha->eft = NULL; 4408 ha->eft_dma = 0; 4409 ha->fw_dumped = 0; 4410 ha->fw_dump_cap_flags = 0; 4411 ha->fw_dump_reading = 0; 4412 ha->fw_dump = NULL; 4413 ha->fw_dump_len = 0; 4414 ha->fw_dump_template = NULL; 4415 ha->fw_dump_template_len = 0; 4416 } 4417 4418 /* 4419 * qla2x00_mem_free 4420 * Frees all adapter allocated memory. 4421 * 4422 * Input: 4423 * ha = adapter block pointer. 4424 */ 4425 static void 4426 qla2x00_mem_free(struct qla_hw_data *ha) 4427 { 4428 qla2x00_free_fw_dump(ha); 4429 4430 if (ha->mctp_dump) 4431 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4432 ha->mctp_dump_dma); 4433 4434 if (ha->srb_mempool) 4435 mempool_destroy(ha->srb_mempool); 4436 4437 if (ha->dcbx_tlv) 4438 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4439 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4440 4441 if (ha->xgmac_data) 4442 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4443 ha->xgmac_data, ha->xgmac_data_dma); 4444 4445 if (ha->sns_cmd) 4446 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4447 ha->sns_cmd, ha->sns_cmd_dma); 4448 4449 if (ha->ct_sns) 4450 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4451 ha->ct_sns, ha->ct_sns_dma); 4452 4453 if (ha->sfp_data) 4454 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4455 ha->sfp_data_dma); 4456 4457 if (ha->ms_iocb) 4458 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4459 4460 if (ha->ex_init_cb) 4461 dma_pool_free(ha->s_dma_pool, 4462 ha->ex_init_cb, ha->ex_init_cb_dma); 4463 4464 if (ha->async_pd) 4465 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4466 4467 if (ha->s_dma_pool) 4468 dma_pool_destroy(ha->s_dma_pool); 4469 4470 if (ha->gid_list) 4471 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4472 ha->gid_list, ha->gid_list_dma); 4473 4474 if (IS_QLA82XX(ha)) { 4475 if (!list_empty(&ha->gbl_dsd_list)) { 4476 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4477 4478 /* clean up allocated prev pool */ 4479 list_for_each_entry_safe(dsd_ptr, 4480 tdsd_ptr, &ha->gbl_dsd_list, list) { 4481 dma_pool_free(ha->dl_dma_pool, 4482 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4483 list_del(&dsd_ptr->list); 4484 kfree(dsd_ptr); 4485 } 4486 } 4487 } 4488 4489 if (ha->dl_dma_pool) 4490 dma_pool_destroy(ha->dl_dma_pool); 4491 4492 if (ha->fcp_cmnd_dma_pool) 4493 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4494 4495 if (ha->ctx_mempool) 4496 mempool_destroy(ha->ctx_mempool); 4497 4498 qlt_mem_free(ha); 4499 4500 if (ha->init_cb) 4501 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4502 ha->init_cb, ha->init_cb_dma); 4503 4504 vfree(ha->optrom_buffer); 4505 kfree(ha->nvram); 4506 kfree(ha->npiv_info); 4507 kfree(ha->swl); 4508 kfree(ha->loop_id_map); 4509 4510 ha->srb_mempool = NULL; 4511 ha->ctx_mempool = NULL; 4512 ha->sns_cmd = NULL; 4513 ha->sns_cmd_dma = 0; 4514 ha->ct_sns = NULL; 4515 ha->ct_sns_dma = 0; 4516 ha->ms_iocb = NULL; 4517 ha->ms_iocb_dma = 0; 4518 ha->init_cb = NULL; 4519 ha->init_cb_dma = 0; 4520 ha->ex_init_cb = NULL; 4521 ha->ex_init_cb_dma = 0; 4522 ha->async_pd = NULL; 4523 ha->async_pd_dma = 0; 4524 ha->loop_id_map = NULL; 4525 ha->npiv_info = NULL; 4526 ha->optrom_buffer = NULL; 4527 ha->swl = NULL; 4528 ha->nvram = NULL; 4529 ha->mctp_dump = NULL; 4530 ha->dcbx_tlv = NULL; 4531 ha->xgmac_data = NULL; 4532 ha->sfp_data = NULL; 4533 4534 ha->s_dma_pool = NULL; 4535 ha->dl_dma_pool = NULL; 4536 ha->fcp_cmnd_dma_pool = NULL; 4537 4538 ha->gid_list = NULL; 4539 ha->gid_list_dma = 0; 4540 4541 ha->tgt.atio_ring = NULL; 4542 ha->tgt.atio_dma = 0; 4543 ha->tgt.tgt_vp_map = NULL; 4544 } 4545 4546 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4547 struct qla_hw_data *ha) 4548 { 4549 struct Scsi_Host *host; 4550 struct scsi_qla_host *vha = NULL; 4551 4552 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4553 if (!host) { 4554 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4555 "Failed to allocate host from the scsi layer, aborting.\n"); 4556 return NULL; 4557 } 4558 4559 /* Clear our data area */ 4560 vha = shost_priv(host); 4561 memset(vha, 0, sizeof(scsi_qla_host_t)); 4562 4563 vha->host = host; 4564 vha->host_no = host->host_no; 4565 vha->hw = ha; 4566 4567 INIT_LIST_HEAD(&vha->vp_fcports); 4568 INIT_LIST_HEAD(&vha->work_list); 4569 INIT_LIST_HEAD(&vha->list); 4570 INIT_LIST_HEAD(&vha->qla_cmd_list); 4571 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4572 INIT_LIST_HEAD(&vha->logo_list); 4573 INIT_LIST_HEAD(&vha->plogi_ack_list); 4574 INIT_LIST_HEAD(&vha->qp_list); 4575 INIT_LIST_HEAD(&vha->gnl.fcports); 4576 INIT_LIST_HEAD(&vha->nvme_rport_list); 4577 INIT_LIST_HEAD(&vha->gpnid_list); 4578 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4579 4580 spin_lock_init(&vha->work_lock); 4581 spin_lock_init(&vha->cmd_list_lock); 4582 spin_lock_init(&vha->gnl.fcports_lock); 4583 init_waitqueue_head(&vha->fcport_waitQ); 4584 init_waitqueue_head(&vha->vref_waitq); 4585 4586 vha->gnl.size = sizeof(struct get_name_list_extended) * 4587 (ha->max_loop_id + 1); 4588 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4589 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4590 if (!vha->gnl.l) { 4591 ql_log(ql_log_fatal, vha, 0xd04a, 4592 "Alloc failed for name list.\n"); 4593 scsi_remove_host(vha->host); 4594 return NULL; 4595 } 4596 4597 /* todo: what about ext login? */ 4598 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4599 vha->scan.l = vmalloc(vha->scan.size); 4600 if (!vha->scan.l) { 4601 ql_log(ql_log_fatal, vha, 0xd04a, 4602 "Alloc failed for scan database.\n"); 4603 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4604 vha->gnl.l, vha->gnl.ldma); 4605 scsi_remove_host(vha->host); 4606 return NULL; 4607 } 4608 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4609 4610 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4611 ql_dbg(ql_dbg_init, vha, 0x0041, 4612 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4613 vha->host, vha->hw, vha, 4614 dev_name(&(ha->pdev->dev))); 4615 4616 return vha; 4617 } 4618 4619 struct qla_work_evt * 4620 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4621 { 4622 struct qla_work_evt *e; 4623 uint8_t bail; 4624 4625 QLA_VHA_MARK_BUSY(vha, bail); 4626 if (bail) 4627 return NULL; 4628 4629 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4630 if (!e) { 4631 QLA_VHA_MARK_NOT_BUSY(vha); 4632 return NULL; 4633 } 4634 4635 INIT_LIST_HEAD(&e->list); 4636 e->type = type; 4637 e->flags = QLA_EVT_FLAG_FREE; 4638 return e; 4639 } 4640 4641 int 4642 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4643 { 4644 unsigned long flags; 4645 bool q = false; 4646 4647 spin_lock_irqsave(&vha->work_lock, flags); 4648 list_add_tail(&e->list, &vha->work_list); 4649 4650 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4651 q = true; 4652 4653 spin_unlock_irqrestore(&vha->work_lock, flags); 4654 4655 if (q) 4656 queue_work(vha->hw->wq, &vha->iocb_work); 4657 4658 return QLA_SUCCESS; 4659 } 4660 4661 int 4662 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4663 u32 data) 4664 { 4665 struct qla_work_evt *e; 4666 4667 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4668 if (!e) 4669 return QLA_FUNCTION_FAILED; 4670 4671 e->u.aen.code = code; 4672 e->u.aen.data = data; 4673 return qla2x00_post_work(vha, e); 4674 } 4675 4676 int 4677 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4678 { 4679 struct qla_work_evt *e; 4680 4681 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4682 if (!e) 4683 return QLA_FUNCTION_FAILED; 4684 4685 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4686 return qla2x00_post_work(vha, e); 4687 } 4688 4689 #define qla2x00_post_async_work(name, type) \ 4690 int qla2x00_post_async_##name##_work( \ 4691 struct scsi_qla_host *vha, \ 4692 fc_port_t *fcport, uint16_t *data) \ 4693 { \ 4694 struct qla_work_evt *e; \ 4695 \ 4696 e = qla2x00_alloc_work(vha, type); \ 4697 if (!e) \ 4698 return QLA_FUNCTION_FAILED; \ 4699 \ 4700 e->u.logio.fcport = fcport; \ 4701 if (data) { \ 4702 e->u.logio.data[0] = data[0]; \ 4703 e->u.logio.data[1] = data[1]; \ 4704 } \ 4705 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4706 return qla2x00_post_work(vha, e); \ 4707 } 4708 4709 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4710 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4711 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4712 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4713 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4714 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4715 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4716 4717 int 4718 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4719 { 4720 struct qla_work_evt *e; 4721 4722 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4723 if (!e) 4724 return QLA_FUNCTION_FAILED; 4725 4726 e->u.uevent.code = code; 4727 return qla2x00_post_work(vha, e); 4728 } 4729 4730 static void 4731 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4732 { 4733 char event_string[40]; 4734 char *envp[] = { event_string, NULL }; 4735 4736 switch (code) { 4737 case QLA_UEVENT_CODE_FW_DUMP: 4738 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4739 vha->host_no); 4740 break; 4741 default: 4742 /* do nothing */ 4743 break; 4744 } 4745 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4746 } 4747 4748 int 4749 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4750 uint32_t *data, int cnt) 4751 { 4752 struct qla_work_evt *e; 4753 4754 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4755 if (!e) 4756 return QLA_FUNCTION_FAILED; 4757 4758 e->u.aenfx.evtcode = evtcode; 4759 e->u.aenfx.count = cnt; 4760 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4761 return qla2x00_post_work(vha, e); 4762 } 4763 4764 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4765 { 4766 struct qla_work_evt *e; 4767 4768 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4769 if (!e) 4770 return QLA_FUNCTION_FAILED; 4771 4772 e->u.fcport.fcport = fcport; 4773 return qla2x00_post_work(vha, e); 4774 } 4775 4776 static 4777 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4778 { 4779 unsigned long flags; 4780 fc_port_t *fcport = NULL, *tfcp; 4781 struct qlt_plogi_ack_t *pla = 4782 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4783 uint8_t free_fcport = 0; 4784 4785 ql_dbg(ql_dbg_disc, vha, 0xffff, 4786 "%s %d %8phC enter\n", 4787 __func__, __LINE__, e->u.new_sess.port_name); 4788 4789 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4790 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4791 if (fcport) { 4792 fcport->d_id = e->u.new_sess.id; 4793 if (pla) { 4794 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4795 memcpy(fcport->node_name, 4796 pla->iocb.u.isp24.u.plogi.node_name, 4797 WWN_SIZE); 4798 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4799 /* we took an extra ref_count to prevent PLOGI ACK when 4800 * fcport/sess has not been created. 4801 */ 4802 pla->ref_count--; 4803 } 4804 } else { 4805 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4806 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4807 if (fcport) { 4808 fcport->d_id = e->u.new_sess.id; 4809 fcport->flags |= FCF_FABRIC_DEVICE; 4810 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4811 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP) 4812 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4813 4814 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) { 4815 fcport->fc4_type = FC4_TYPE_OTHER; 4816 fcport->fc4f_nvme = FC4_TYPE_NVME; 4817 } 4818 4819 memcpy(fcport->port_name, e->u.new_sess.port_name, 4820 WWN_SIZE); 4821 } else { 4822 ql_dbg(ql_dbg_disc, vha, 0xffff, 4823 "%s %8phC mem alloc fail.\n", 4824 __func__, e->u.new_sess.port_name); 4825 4826 if (pla) 4827 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4828 return; 4829 } 4830 4831 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4832 /* search again to make sure no one else got ahead */ 4833 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4834 e->u.new_sess.port_name, 1); 4835 if (tfcp) { 4836 /* should rarily happen */ 4837 ql_dbg(ql_dbg_disc, vha, 0xffff, 4838 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4839 __func__, tfcp->port_name, tfcp->disc_state, 4840 tfcp->fw_login_state); 4841 4842 free_fcport = 1; 4843 } else { 4844 list_add_tail(&fcport->list, &vha->vp_fcports); 4845 4846 } 4847 if (pla) { 4848 qlt_plogi_ack_link(vha, pla, fcport, 4849 QLT_PLOGI_LINK_SAME_WWN); 4850 pla->ref_count--; 4851 } 4852 } 4853 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4854 4855 if (fcport) { 4856 fcport->id_changed = 1; 4857 fcport->scan_state = QLA_FCPORT_FOUND; 4858 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4859 4860 if (pla) { 4861 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4862 u16 wd3_lo; 4863 4864 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4865 fcport->local = 0; 4866 fcport->loop_id = 4867 le16_to_cpu( 4868 pla->iocb.u.isp24.nport_handle); 4869 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4870 wd3_lo = 4871 le16_to_cpu( 4872 pla->iocb.u.isp24.u.prli.wd3_lo); 4873 4874 if (wd3_lo & BIT_7) 4875 fcport->conf_compl_supported = 1; 4876 4877 if ((wd3_lo & BIT_4) == 0) 4878 fcport->port_type = FCT_INITIATOR; 4879 else 4880 fcport->port_type = FCT_TARGET; 4881 } 4882 qlt_plogi_ack_unref(vha, pla); 4883 } else { 4884 fc_port_t *dfcp = NULL; 4885 4886 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4887 tfcp = qla2x00_find_fcport_by_nportid(vha, 4888 &e->u.new_sess.id, 1); 4889 if (tfcp && (tfcp != fcport)) { 4890 /* 4891 * We have a conflict fcport with same NportID. 4892 */ 4893 ql_dbg(ql_dbg_disc, vha, 0xffff, 4894 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4895 __func__, tfcp->port_name, tfcp->disc_state, 4896 tfcp->fw_login_state); 4897 4898 switch (tfcp->disc_state) { 4899 case DSC_DELETED: 4900 break; 4901 case DSC_DELETE_PEND: 4902 fcport->login_pause = 1; 4903 tfcp->conflict = fcport; 4904 break; 4905 default: 4906 fcport->login_pause = 1; 4907 tfcp->conflict = fcport; 4908 dfcp = tfcp; 4909 break; 4910 } 4911 } 4912 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4913 if (dfcp) 4914 qlt_schedule_sess_for_deletion(tfcp); 4915 4916 4917 if (N2N_TOPO(vha->hw)) 4918 fcport->flags &= ~FCF_FABRIC_DEVICE; 4919 4920 if (N2N_TOPO(vha->hw)) { 4921 if (vha->flags.nvme_enabled) { 4922 fcport->fc4f_nvme = 1; 4923 fcport->n2n_flag = 1; 4924 } 4925 fcport->fw_login_state = 0; 4926 /* 4927 * wait link init done before sending login 4928 */ 4929 } else { 4930 qla24xx_fcport_handle_login(vha, fcport); 4931 } 4932 } 4933 } 4934 4935 if (free_fcport) { 4936 qla2x00_free_fcport(fcport); 4937 if (pla) 4938 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4939 } 4940 } 4941 4942 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4943 { 4944 struct srb *sp = e->u.iosb.sp; 4945 int rval; 4946 4947 rval = qla2x00_start_sp(sp); 4948 if (rval != QLA_SUCCESS) { 4949 ql_dbg(ql_dbg_disc, vha, 0x2043, 4950 "%s: %s: Re-issue IOCB failed (%d).\n", 4951 __func__, sp->name, rval); 4952 qla24xx_sp_unmap(vha, sp); 4953 } 4954 } 4955 4956 void 4957 qla2x00_do_work(struct scsi_qla_host *vha) 4958 { 4959 struct qla_work_evt *e, *tmp; 4960 unsigned long flags; 4961 LIST_HEAD(work); 4962 4963 spin_lock_irqsave(&vha->work_lock, flags); 4964 list_splice_init(&vha->work_list, &work); 4965 spin_unlock_irqrestore(&vha->work_lock, flags); 4966 4967 list_for_each_entry_safe(e, tmp, &work, list) { 4968 list_del_init(&e->list); 4969 4970 switch (e->type) { 4971 case QLA_EVT_AEN: 4972 fc_host_post_event(vha->host, fc_get_event_number(), 4973 e->u.aen.code, e->u.aen.data); 4974 break; 4975 case QLA_EVT_IDC_ACK: 4976 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4977 break; 4978 case QLA_EVT_ASYNC_LOGIN: 4979 qla2x00_async_login(vha, e->u.logio.fcport, 4980 e->u.logio.data); 4981 break; 4982 case QLA_EVT_ASYNC_LOGOUT: 4983 qla2x00_async_logout(vha, e->u.logio.fcport); 4984 break; 4985 case QLA_EVT_ASYNC_LOGOUT_DONE: 4986 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4987 e->u.logio.data); 4988 break; 4989 case QLA_EVT_ASYNC_ADISC: 4990 qla2x00_async_adisc(vha, e->u.logio.fcport, 4991 e->u.logio.data); 4992 break; 4993 case QLA_EVT_ASYNC_ADISC_DONE: 4994 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4995 e->u.logio.data); 4996 break; 4997 case QLA_EVT_UEVENT: 4998 qla2x00_uevent_emit(vha, e->u.uevent.code); 4999 break; 5000 case QLA_EVT_AENFX: 5001 qlafx00_process_aen(vha, e); 5002 break; 5003 case QLA_EVT_GIDPN: 5004 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 5005 break; 5006 case QLA_EVT_GPNID: 5007 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5008 break; 5009 case QLA_EVT_UNMAP: 5010 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5011 break; 5012 case QLA_EVT_RELOGIN: 5013 qla2x00_relogin(vha); 5014 break; 5015 case QLA_EVT_NEW_SESS: 5016 qla24xx_create_new_sess(vha, e); 5017 break; 5018 case QLA_EVT_GPDB: 5019 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5020 e->u.fcport.opt); 5021 break; 5022 case QLA_EVT_PRLI: 5023 qla24xx_async_prli(vha, e->u.fcport.fcport); 5024 break; 5025 case QLA_EVT_GPSC: 5026 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5027 break; 5028 case QLA_EVT_UPD_FCPORT: 5029 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5030 break; 5031 case QLA_EVT_GNL: 5032 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5033 break; 5034 case QLA_EVT_NACK: 5035 qla24xx_do_nack_work(vha, e); 5036 break; 5037 case QLA_EVT_ASYNC_PRLO: 5038 qla2x00_async_prlo(vha, e->u.logio.fcport); 5039 break; 5040 case QLA_EVT_ASYNC_PRLO_DONE: 5041 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5042 e->u.logio.data); 5043 break; 5044 case QLA_EVT_GPNFT: 5045 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5046 e->u.gpnft.sp); 5047 break; 5048 case QLA_EVT_GPNFT_DONE: 5049 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5050 break; 5051 case QLA_EVT_GNNFT_DONE: 5052 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5053 break; 5054 case QLA_EVT_GNNID: 5055 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5056 break; 5057 case QLA_EVT_GFPNID: 5058 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5059 break; 5060 case QLA_EVT_SP_RETRY: 5061 qla_sp_retry(vha, e); 5062 break; 5063 case QLA_EVT_IIDMA: 5064 qla_do_iidma_work(vha, e->u.fcport.fcport); 5065 break; 5066 case QLA_EVT_ELS_PLOGI: 5067 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5068 e->u.fcport.fcport, false); 5069 break; 5070 } 5071 if (e->flags & QLA_EVT_FLAG_FREE) 5072 kfree(e); 5073 5074 /* For each work completed decrement vha ref count */ 5075 QLA_VHA_MARK_NOT_BUSY(vha); 5076 } 5077 } 5078 5079 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5080 { 5081 struct qla_work_evt *e; 5082 5083 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5084 5085 if (!e) { 5086 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5087 return QLA_FUNCTION_FAILED; 5088 } 5089 5090 return qla2x00_post_work(vha, e); 5091 } 5092 5093 /* Relogins all the fcports of a vport 5094 * Context: dpc thread 5095 */ 5096 void qla2x00_relogin(struct scsi_qla_host *vha) 5097 { 5098 fc_port_t *fcport; 5099 int status, relogin_needed = 0; 5100 struct event_arg ea; 5101 5102 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5103 /* 5104 * If the port is not ONLINE then try to login 5105 * to it if we haven't run out of retries. 5106 */ 5107 if (atomic_read(&fcport->state) != FCS_ONLINE && 5108 fcport->login_retry) { 5109 if (fcport->scan_state != QLA_FCPORT_FOUND || 5110 fcport->disc_state == DSC_LOGIN_COMPLETE) 5111 continue; 5112 5113 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5114 fcport->disc_state == DSC_DELETE_PEND) { 5115 relogin_needed = 1; 5116 } else { 5117 if (vha->hw->current_topology != ISP_CFG_NL) { 5118 memset(&ea, 0, sizeof(ea)); 5119 ea.event = FCME_RELOGIN; 5120 ea.fcport = fcport; 5121 qla2x00_fcport_event_handler(vha, &ea); 5122 } else if (vha->hw->current_topology == 5123 ISP_CFG_NL) { 5124 fcport->login_retry--; 5125 status = 5126 qla2x00_local_device_login(vha, 5127 fcport); 5128 if (status == QLA_SUCCESS) { 5129 fcport->old_loop_id = 5130 fcport->loop_id; 5131 ql_dbg(ql_dbg_disc, vha, 0x2003, 5132 "Port login OK: logged in ID 0x%x.\n", 5133 fcport->loop_id); 5134 qla2x00_update_fcport 5135 (vha, fcport); 5136 } else if (status == 1) { 5137 set_bit(RELOGIN_NEEDED, 5138 &vha->dpc_flags); 5139 /* retry the login again */ 5140 ql_dbg(ql_dbg_disc, vha, 0x2007, 5141 "Retrying %d login again loop_id 0x%x.\n", 5142 fcport->login_retry, 5143 fcport->loop_id); 5144 } else { 5145 fcport->login_retry = 0; 5146 } 5147 5148 if (fcport->login_retry == 0 && 5149 status != QLA_SUCCESS) 5150 qla2x00_clear_loop_id(fcport); 5151 } 5152 } 5153 } 5154 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5155 break; 5156 } 5157 5158 if (relogin_needed) 5159 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5160 5161 ql_dbg(ql_dbg_disc, vha, 0x400e, 5162 "Relogin end.\n"); 5163 } 5164 5165 /* Schedule work on any of the dpc-workqueues */ 5166 void 5167 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5168 { 5169 struct qla_hw_data *ha = base_vha->hw; 5170 5171 switch (work_code) { 5172 case MBA_IDC_AEN: /* 0x8200 */ 5173 if (ha->dpc_lp_wq) 5174 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5175 break; 5176 5177 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5178 if (!ha->flags.nic_core_reset_hdlr_active) { 5179 if (ha->dpc_hp_wq) 5180 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5181 } else 5182 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5183 "NIC Core reset is already active. Skip " 5184 "scheduling it again.\n"); 5185 break; 5186 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5187 if (ha->dpc_hp_wq) 5188 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5189 break; 5190 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5191 if (ha->dpc_hp_wq) 5192 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5193 break; 5194 default: 5195 ql_log(ql_log_warn, base_vha, 0xb05f, 5196 "Unknown work-code=0x%x.\n", work_code); 5197 } 5198 5199 return; 5200 } 5201 5202 /* Work: Perform NIC Core Unrecoverable state handling */ 5203 void 5204 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5205 { 5206 struct qla_hw_data *ha = 5207 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5208 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5209 uint32_t dev_state = 0; 5210 5211 qla83xx_idc_lock(base_vha, 0); 5212 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5213 qla83xx_reset_ownership(base_vha); 5214 if (ha->flags.nic_core_reset_owner) { 5215 ha->flags.nic_core_reset_owner = 0; 5216 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5217 QLA8XXX_DEV_FAILED); 5218 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5219 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5220 } 5221 qla83xx_idc_unlock(base_vha, 0); 5222 } 5223 5224 /* Work: Execute IDC state handler */ 5225 void 5226 qla83xx_idc_state_handler_work(struct work_struct *work) 5227 { 5228 struct qla_hw_data *ha = 5229 container_of(work, struct qla_hw_data, idc_state_handler); 5230 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5231 uint32_t dev_state = 0; 5232 5233 qla83xx_idc_lock(base_vha, 0); 5234 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5235 if (dev_state == QLA8XXX_DEV_FAILED || 5236 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5237 qla83xx_idc_state_handler(base_vha); 5238 qla83xx_idc_unlock(base_vha, 0); 5239 } 5240 5241 static int 5242 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5243 { 5244 int rval = QLA_SUCCESS; 5245 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5246 uint32_t heart_beat_counter1, heart_beat_counter2; 5247 5248 do { 5249 if (time_after(jiffies, heart_beat_wait)) { 5250 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5251 "Nic Core f/w is not alive.\n"); 5252 rval = QLA_FUNCTION_FAILED; 5253 break; 5254 } 5255 5256 qla83xx_idc_lock(base_vha, 0); 5257 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5258 &heart_beat_counter1); 5259 qla83xx_idc_unlock(base_vha, 0); 5260 msleep(100); 5261 qla83xx_idc_lock(base_vha, 0); 5262 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5263 &heart_beat_counter2); 5264 qla83xx_idc_unlock(base_vha, 0); 5265 } while (heart_beat_counter1 == heart_beat_counter2); 5266 5267 return rval; 5268 } 5269 5270 /* Work: Perform NIC Core Reset handling */ 5271 void 5272 qla83xx_nic_core_reset_work(struct work_struct *work) 5273 { 5274 struct qla_hw_data *ha = 5275 container_of(work, struct qla_hw_data, nic_core_reset); 5276 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5277 uint32_t dev_state = 0; 5278 5279 if (IS_QLA2031(ha)) { 5280 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5281 ql_log(ql_log_warn, base_vha, 0xb081, 5282 "Failed to dump mctp\n"); 5283 return; 5284 } 5285 5286 if (!ha->flags.nic_core_reset_hdlr_active) { 5287 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5288 qla83xx_idc_lock(base_vha, 0); 5289 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5290 &dev_state); 5291 qla83xx_idc_unlock(base_vha, 0); 5292 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5293 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5294 "Nic Core f/w is alive.\n"); 5295 return; 5296 } 5297 } 5298 5299 ha->flags.nic_core_reset_hdlr_active = 1; 5300 if (qla83xx_nic_core_reset(base_vha)) { 5301 /* NIC Core reset failed. */ 5302 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5303 "NIC Core reset failed.\n"); 5304 } 5305 ha->flags.nic_core_reset_hdlr_active = 0; 5306 } 5307 } 5308 5309 /* Work: Handle 8200 IDC aens */ 5310 void 5311 qla83xx_service_idc_aen(struct work_struct *work) 5312 { 5313 struct qla_hw_data *ha = 5314 container_of(work, struct qla_hw_data, idc_aen); 5315 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5316 uint32_t dev_state, idc_control; 5317 5318 qla83xx_idc_lock(base_vha, 0); 5319 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5320 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5321 qla83xx_idc_unlock(base_vha, 0); 5322 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5323 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5324 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5325 "Application requested NIC Core Reset.\n"); 5326 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5327 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5328 QLA_SUCCESS) { 5329 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5330 "Other protocol driver requested NIC Core Reset.\n"); 5331 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5332 } 5333 } else if (dev_state == QLA8XXX_DEV_FAILED || 5334 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5335 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5336 } 5337 } 5338 5339 static void 5340 qla83xx_wait_logic(void) 5341 { 5342 int i; 5343 5344 /* Yield CPU */ 5345 if (!in_interrupt()) { 5346 /* 5347 * Wait about 200ms before retrying again. 5348 * This controls the number of retries for single 5349 * lock operation. 5350 */ 5351 msleep(100); 5352 schedule(); 5353 } else { 5354 for (i = 0; i < 20; i++) 5355 cpu_relax(); /* This a nop instr on i386 */ 5356 } 5357 } 5358 5359 static int 5360 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5361 { 5362 int rval; 5363 uint32_t data; 5364 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5365 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5366 struct qla_hw_data *ha = base_vha->hw; 5367 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5368 "Trying force recovery of the IDC lock.\n"); 5369 5370 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5371 if (rval) 5372 return rval; 5373 5374 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5375 return QLA_SUCCESS; 5376 } else { 5377 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5378 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5379 data); 5380 if (rval) 5381 return rval; 5382 5383 msleep(200); 5384 5385 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5386 &data); 5387 if (rval) 5388 return rval; 5389 5390 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5391 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5392 ~(idc_lck_rcvry_stage_mask)); 5393 rval = qla83xx_wr_reg(base_vha, 5394 QLA83XX_IDC_LOCK_RECOVERY, data); 5395 if (rval) 5396 return rval; 5397 5398 /* Forcefully perform IDC UnLock */ 5399 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5400 &data); 5401 if (rval) 5402 return rval; 5403 /* Clear lock-id by setting 0xff */ 5404 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5405 0xff); 5406 if (rval) 5407 return rval; 5408 /* Clear lock-recovery by setting 0x0 */ 5409 rval = qla83xx_wr_reg(base_vha, 5410 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5411 if (rval) 5412 return rval; 5413 } else 5414 return QLA_SUCCESS; 5415 } 5416 5417 return rval; 5418 } 5419 5420 static int 5421 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5422 { 5423 int rval = QLA_SUCCESS; 5424 uint32_t o_drv_lockid, n_drv_lockid; 5425 unsigned long lock_recovery_timeout; 5426 5427 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5428 retry_lockid: 5429 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5430 if (rval) 5431 goto exit; 5432 5433 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5434 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5435 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5436 return QLA_SUCCESS; 5437 else 5438 return QLA_FUNCTION_FAILED; 5439 } 5440 5441 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5442 if (rval) 5443 goto exit; 5444 5445 if (o_drv_lockid == n_drv_lockid) { 5446 qla83xx_wait_logic(); 5447 goto retry_lockid; 5448 } else 5449 return QLA_SUCCESS; 5450 5451 exit: 5452 return rval; 5453 } 5454 5455 void 5456 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5457 { 5458 uint16_t options = (requester_id << 15) | BIT_6; 5459 uint32_t data; 5460 uint32_t lock_owner; 5461 struct qla_hw_data *ha = base_vha->hw; 5462 5463 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5464 retry_lock: 5465 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5466 == QLA_SUCCESS) { 5467 if (data) { 5468 /* Setting lock-id to our function-number */ 5469 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5470 ha->portnum); 5471 } else { 5472 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5473 &lock_owner); 5474 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5475 "Failed to acquire IDC lock, acquired by %d, " 5476 "retrying...\n", lock_owner); 5477 5478 /* Retry/Perform IDC-Lock recovery */ 5479 if (qla83xx_idc_lock_recovery(base_vha) 5480 == QLA_SUCCESS) { 5481 qla83xx_wait_logic(); 5482 goto retry_lock; 5483 } else 5484 ql_log(ql_log_warn, base_vha, 0xb075, 5485 "IDC Lock recovery FAILED.\n"); 5486 } 5487 5488 } 5489 5490 return; 5491 5492 /* XXX: IDC-lock implementation using access-control mbx */ 5493 retry_lock2: 5494 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5495 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5496 "Failed to acquire IDC lock. retrying...\n"); 5497 /* Retry/Perform IDC-Lock recovery */ 5498 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5499 qla83xx_wait_logic(); 5500 goto retry_lock2; 5501 } else 5502 ql_log(ql_log_warn, base_vha, 0xb076, 5503 "IDC Lock recovery FAILED.\n"); 5504 } 5505 5506 return; 5507 } 5508 5509 void 5510 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5511 { 5512 #if 0 5513 uint16_t options = (requester_id << 15) | BIT_7; 5514 #endif 5515 uint16_t retry; 5516 uint32_t data; 5517 struct qla_hw_data *ha = base_vha->hw; 5518 5519 /* IDC-unlock implementation using driver-unlock/lock-id 5520 * remote registers 5521 */ 5522 retry = 0; 5523 retry_unlock: 5524 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5525 == QLA_SUCCESS) { 5526 if (data == ha->portnum) { 5527 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5528 /* Clearing lock-id by setting 0xff */ 5529 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5530 } else if (retry < 10) { 5531 /* SV: XXX: IDC unlock retrying needed here? */ 5532 5533 /* Retry for IDC-unlock */ 5534 qla83xx_wait_logic(); 5535 retry++; 5536 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5537 "Failed to release IDC lock, retrying=%d\n", retry); 5538 goto retry_unlock; 5539 } 5540 } else if (retry < 10) { 5541 /* Retry for IDC-unlock */ 5542 qla83xx_wait_logic(); 5543 retry++; 5544 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5545 "Failed to read drv-lockid, retrying=%d\n", retry); 5546 goto retry_unlock; 5547 } 5548 5549 return; 5550 5551 #if 0 5552 /* XXX: IDC-unlock implementation using access-control mbx */ 5553 retry = 0; 5554 retry_unlock2: 5555 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5556 if (retry < 10) { 5557 /* Retry for IDC-unlock */ 5558 qla83xx_wait_logic(); 5559 retry++; 5560 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5561 "Failed to release IDC lock, retrying=%d\n", retry); 5562 goto retry_unlock2; 5563 } 5564 } 5565 5566 return; 5567 #endif 5568 } 5569 5570 int 5571 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5572 { 5573 int rval = QLA_SUCCESS; 5574 struct qla_hw_data *ha = vha->hw; 5575 uint32_t drv_presence; 5576 5577 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5578 if (rval == QLA_SUCCESS) { 5579 drv_presence |= (1 << ha->portnum); 5580 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5581 drv_presence); 5582 } 5583 5584 return rval; 5585 } 5586 5587 int 5588 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5589 { 5590 int rval = QLA_SUCCESS; 5591 5592 qla83xx_idc_lock(vha, 0); 5593 rval = __qla83xx_set_drv_presence(vha); 5594 qla83xx_idc_unlock(vha, 0); 5595 5596 return rval; 5597 } 5598 5599 int 5600 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5601 { 5602 int rval = QLA_SUCCESS; 5603 struct qla_hw_data *ha = vha->hw; 5604 uint32_t drv_presence; 5605 5606 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5607 if (rval == QLA_SUCCESS) { 5608 drv_presence &= ~(1 << ha->portnum); 5609 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5610 drv_presence); 5611 } 5612 5613 return rval; 5614 } 5615 5616 int 5617 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5618 { 5619 int rval = QLA_SUCCESS; 5620 5621 qla83xx_idc_lock(vha, 0); 5622 rval = __qla83xx_clear_drv_presence(vha); 5623 qla83xx_idc_unlock(vha, 0); 5624 5625 return rval; 5626 } 5627 5628 static void 5629 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5630 { 5631 struct qla_hw_data *ha = vha->hw; 5632 uint32_t drv_ack, drv_presence; 5633 unsigned long ack_timeout; 5634 5635 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5636 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5637 while (1) { 5638 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5639 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5640 if ((drv_ack & drv_presence) == drv_presence) 5641 break; 5642 5643 if (time_after_eq(jiffies, ack_timeout)) { 5644 ql_log(ql_log_warn, vha, 0xb067, 5645 "RESET ACK TIMEOUT! drv_presence=0x%x " 5646 "drv_ack=0x%x\n", drv_presence, drv_ack); 5647 /* 5648 * The function(s) which did not ack in time are forced 5649 * to withdraw any further participation in the IDC 5650 * reset. 5651 */ 5652 if (drv_ack != drv_presence) 5653 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5654 drv_ack); 5655 break; 5656 } 5657 5658 qla83xx_idc_unlock(vha, 0); 5659 msleep(1000); 5660 qla83xx_idc_lock(vha, 0); 5661 } 5662 5663 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5664 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5665 } 5666 5667 static int 5668 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5669 { 5670 int rval = QLA_SUCCESS; 5671 uint32_t idc_control; 5672 5673 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5674 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5675 5676 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5677 __qla83xx_get_idc_control(vha, &idc_control); 5678 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5679 __qla83xx_set_idc_control(vha, 0); 5680 5681 qla83xx_idc_unlock(vha, 0); 5682 rval = qla83xx_restart_nic_firmware(vha); 5683 qla83xx_idc_lock(vha, 0); 5684 5685 if (rval != QLA_SUCCESS) { 5686 ql_log(ql_log_fatal, vha, 0xb06a, 5687 "Failed to restart NIC f/w.\n"); 5688 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5689 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5690 } else { 5691 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5692 "Success in restarting nic f/w.\n"); 5693 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5694 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5695 } 5696 5697 return rval; 5698 } 5699 5700 /* Assumes idc_lock always held on entry */ 5701 int 5702 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5703 { 5704 struct qla_hw_data *ha = base_vha->hw; 5705 int rval = QLA_SUCCESS; 5706 unsigned long dev_init_timeout; 5707 uint32_t dev_state; 5708 5709 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5710 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5711 5712 while (1) { 5713 5714 if (time_after_eq(jiffies, dev_init_timeout)) { 5715 ql_log(ql_log_warn, base_vha, 0xb06e, 5716 "Initialization TIMEOUT!\n"); 5717 /* Init timeout. Disable further NIC Core 5718 * communication. 5719 */ 5720 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5721 QLA8XXX_DEV_FAILED); 5722 ql_log(ql_log_info, base_vha, 0xb06f, 5723 "HW State: FAILED.\n"); 5724 } 5725 5726 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5727 switch (dev_state) { 5728 case QLA8XXX_DEV_READY: 5729 if (ha->flags.nic_core_reset_owner) 5730 qla83xx_idc_audit(base_vha, 5731 IDC_AUDIT_COMPLETION); 5732 ha->flags.nic_core_reset_owner = 0; 5733 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5734 "Reset_owner reset by 0x%x.\n", 5735 ha->portnum); 5736 goto exit; 5737 case QLA8XXX_DEV_COLD: 5738 if (ha->flags.nic_core_reset_owner) 5739 rval = qla83xx_device_bootstrap(base_vha); 5740 else { 5741 /* Wait for AEN to change device-state */ 5742 qla83xx_idc_unlock(base_vha, 0); 5743 msleep(1000); 5744 qla83xx_idc_lock(base_vha, 0); 5745 } 5746 break; 5747 case QLA8XXX_DEV_INITIALIZING: 5748 /* Wait for AEN to change device-state */ 5749 qla83xx_idc_unlock(base_vha, 0); 5750 msleep(1000); 5751 qla83xx_idc_lock(base_vha, 0); 5752 break; 5753 case QLA8XXX_DEV_NEED_RESET: 5754 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5755 qla83xx_need_reset_handler(base_vha); 5756 else { 5757 /* Wait for AEN to change device-state */ 5758 qla83xx_idc_unlock(base_vha, 0); 5759 msleep(1000); 5760 qla83xx_idc_lock(base_vha, 0); 5761 } 5762 /* reset timeout value after need reset handler */ 5763 dev_init_timeout = jiffies + 5764 (ha->fcoe_dev_init_timeout * HZ); 5765 break; 5766 case QLA8XXX_DEV_NEED_QUIESCENT: 5767 /* XXX: DEBUG for now */ 5768 qla83xx_idc_unlock(base_vha, 0); 5769 msleep(1000); 5770 qla83xx_idc_lock(base_vha, 0); 5771 break; 5772 case QLA8XXX_DEV_QUIESCENT: 5773 /* XXX: DEBUG for now */ 5774 if (ha->flags.quiesce_owner) 5775 goto exit; 5776 5777 qla83xx_idc_unlock(base_vha, 0); 5778 msleep(1000); 5779 qla83xx_idc_lock(base_vha, 0); 5780 dev_init_timeout = jiffies + 5781 (ha->fcoe_dev_init_timeout * HZ); 5782 break; 5783 case QLA8XXX_DEV_FAILED: 5784 if (ha->flags.nic_core_reset_owner) 5785 qla83xx_idc_audit(base_vha, 5786 IDC_AUDIT_COMPLETION); 5787 ha->flags.nic_core_reset_owner = 0; 5788 __qla83xx_clear_drv_presence(base_vha); 5789 qla83xx_idc_unlock(base_vha, 0); 5790 qla8xxx_dev_failed_handler(base_vha); 5791 rval = QLA_FUNCTION_FAILED; 5792 qla83xx_idc_lock(base_vha, 0); 5793 goto exit; 5794 case QLA8XXX_BAD_VALUE: 5795 qla83xx_idc_unlock(base_vha, 0); 5796 msleep(1000); 5797 qla83xx_idc_lock(base_vha, 0); 5798 break; 5799 default: 5800 ql_log(ql_log_warn, base_vha, 0xb071, 5801 "Unknown Device State: %x.\n", dev_state); 5802 qla83xx_idc_unlock(base_vha, 0); 5803 qla8xxx_dev_failed_handler(base_vha); 5804 rval = QLA_FUNCTION_FAILED; 5805 qla83xx_idc_lock(base_vha, 0); 5806 goto exit; 5807 } 5808 } 5809 5810 exit: 5811 return rval; 5812 } 5813 5814 void 5815 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5816 { 5817 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5818 board_disable); 5819 struct pci_dev *pdev = ha->pdev; 5820 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5821 5822 /* 5823 * if UNLOAD flag is already set, then continue unload, 5824 * where it was set first. 5825 */ 5826 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5827 return; 5828 5829 ql_log(ql_log_warn, base_vha, 0x015b, 5830 "Disabling adapter.\n"); 5831 5832 if (!atomic_read(&pdev->enable_cnt)) { 5833 ql_log(ql_log_info, base_vha, 0xfffc, 5834 "PCI device disabled, no action req for PCI error=%lx\n", 5835 base_vha->pci_flags); 5836 return; 5837 } 5838 5839 qla2x00_wait_for_sess_deletion(base_vha); 5840 5841 set_bit(UNLOADING, &base_vha->dpc_flags); 5842 5843 qla2x00_delete_all_vps(ha, base_vha); 5844 5845 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5846 5847 qla2x00_dfs_remove(base_vha); 5848 5849 qla84xx_put_chip(base_vha); 5850 5851 if (base_vha->timer_active) 5852 qla2x00_stop_timer(base_vha); 5853 5854 base_vha->flags.online = 0; 5855 5856 qla2x00_destroy_deferred_work(ha); 5857 5858 /* 5859 * Do not try to stop beacon blink as it will issue a mailbox 5860 * command. 5861 */ 5862 qla2x00_free_sysfs_attr(base_vha, false); 5863 5864 fc_remove_host(base_vha->host); 5865 5866 scsi_remove_host(base_vha->host); 5867 5868 base_vha->flags.init_done = 0; 5869 qla25xx_delete_queues(base_vha); 5870 qla2x00_free_fcports(base_vha); 5871 qla2x00_free_irqs(base_vha); 5872 qla2x00_mem_free(ha); 5873 qla82xx_md_free(base_vha); 5874 qla2x00_free_queues(ha); 5875 5876 qla2x00_unmap_iobases(ha); 5877 5878 pci_release_selected_regions(ha->pdev, ha->bars); 5879 pci_disable_pcie_error_reporting(pdev); 5880 pci_disable_device(pdev); 5881 5882 /* 5883 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5884 */ 5885 } 5886 5887 /************************************************************************** 5888 * qla2x00_do_dpc 5889 * This kernel thread is a task that is schedule by the interrupt handler 5890 * to perform the background processing for interrupts. 5891 * 5892 * Notes: 5893 * This task always run in the context of a kernel thread. It 5894 * is kick-off by the driver's detect code and starts up 5895 * up one per adapter. It immediately goes to sleep and waits for 5896 * some fibre event. When either the interrupt handler or 5897 * the timer routine detects a event it will one of the task 5898 * bits then wake us up. 5899 **************************************************************************/ 5900 static int 5901 qla2x00_do_dpc(void *data) 5902 { 5903 scsi_qla_host_t *base_vha; 5904 struct qla_hw_data *ha; 5905 uint32_t online; 5906 struct qla_qpair *qpair; 5907 5908 ha = (struct qla_hw_data *)data; 5909 base_vha = pci_get_drvdata(ha->pdev); 5910 5911 set_user_nice(current, MIN_NICE); 5912 5913 set_current_state(TASK_INTERRUPTIBLE); 5914 while (!kthread_should_stop()) { 5915 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5916 "DPC handler sleeping.\n"); 5917 5918 schedule(); 5919 5920 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5921 goto end_loop; 5922 5923 if (ha->flags.eeh_busy) { 5924 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5925 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5926 goto end_loop; 5927 } 5928 5929 ha->dpc_active = 1; 5930 5931 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5932 "DPC handler waking up, dpc_flags=0x%lx.\n", 5933 base_vha->dpc_flags); 5934 5935 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5936 break; 5937 5938 if (IS_P3P_TYPE(ha)) { 5939 if (IS_QLA8044(ha)) { 5940 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5941 &base_vha->dpc_flags)) { 5942 qla8044_idc_lock(ha); 5943 qla8044_wr_direct(base_vha, 5944 QLA8044_CRB_DEV_STATE_INDEX, 5945 QLA8XXX_DEV_FAILED); 5946 qla8044_idc_unlock(ha); 5947 ql_log(ql_log_info, base_vha, 0x4004, 5948 "HW State: FAILED.\n"); 5949 qla8044_device_state_handler(base_vha); 5950 continue; 5951 } 5952 5953 } else { 5954 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5955 &base_vha->dpc_flags)) { 5956 qla82xx_idc_lock(ha); 5957 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5958 QLA8XXX_DEV_FAILED); 5959 qla82xx_idc_unlock(ha); 5960 ql_log(ql_log_info, base_vha, 0x0151, 5961 "HW State: FAILED.\n"); 5962 qla82xx_device_state_handler(base_vha); 5963 continue; 5964 } 5965 } 5966 5967 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5968 &base_vha->dpc_flags)) { 5969 5970 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5971 "FCoE context reset scheduled.\n"); 5972 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5973 &base_vha->dpc_flags))) { 5974 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5975 /* FCoE-ctx reset failed. 5976 * Escalate to chip-reset 5977 */ 5978 set_bit(ISP_ABORT_NEEDED, 5979 &base_vha->dpc_flags); 5980 } 5981 clear_bit(ABORT_ISP_ACTIVE, 5982 &base_vha->dpc_flags); 5983 } 5984 5985 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5986 "FCoE context reset end.\n"); 5987 } 5988 } else if (IS_QLAFX00(ha)) { 5989 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5990 &base_vha->dpc_flags)) { 5991 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5992 "Firmware Reset Recovery\n"); 5993 if (qlafx00_reset_initialize(base_vha)) { 5994 /* Failed. Abort isp later. */ 5995 if (!test_bit(UNLOADING, 5996 &base_vha->dpc_flags)) { 5997 set_bit(ISP_UNRECOVERABLE, 5998 &base_vha->dpc_flags); 5999 ql_dbg(ql_dbg_dpc, base_vha, 6000 0x4021, 6001 "Reset Recovery Failed\n"); 6002 } 6003 } 6004 } 6005 6006 if (test_and_clear_bit(FX00_TARGET_SCAN, 6007 &base_vha->dpc_flags)) { 6008 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6009 "ISPFx00 Target Scan scheduled\n"); 6010 if (qlafx00_rescan_isp(base_vha)) { 6011 if (!test_bit(UNLOADING, 6012 &base_vha->dpc_flags)) 6013 set_bit(ISP_UNRECOVERABLE, 6014 &base_vha->dpc_flags); 6015 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6016 "ISPFx00 Target Scan Failed\n"); 6017 } 6018 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6019 "ISPFx00 Target Scan End\n"); 6020 } 6021 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6022 &base_vha->dpc_flags)) { 6023 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6024 "ISPFx00 Host Info resend scheduled\n"); 6025 qlafx00_fx_disc(base_vha, 6026 &base_vha->hw->mr.fcport, 6027 FXDISC_REG_HOST_INFO); 6028 } 6029 } 6030 6031 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6032 &base_vha->dpc_flags) && 6033 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6034 qla24xx_detect_sfp(base_vha); 6035 6036 if (ha->flags.detected_lr_sfp != 6037 ha->flags.using_lr_setting) 6038 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6039 } 6040 6041 if (test_and_clear_bit 6042 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6043 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6044 6045 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6046 "ISP abort scheduled.\n"); 6047 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6048 &base_vha->dpc_flags))) { 6049 6050 if (ha->isp_ops->abort_isp(base_vha)) { 6051 /* failed. retry later */ 6052 set_bit(ISP_ABORT_NEEDED, 6053 &base_vha->dpc_flags); 6054 } 6055 clear_bit(ABORT_ISP_ACTIVE, 6056 &base_vha->dpc_flags); 6057 } 6058 6059 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6060 "ISP abort end.\n"); 6061 } 6062 6063 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6064 &base_vha->dpc_flags)) { 6065 qla2x00_update_fcports(base_vha); 6066 } 6067 6068 if (IS_QLAFX00(ha)) 6069 goto loop_resync_check; 6070 6071 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6072 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6073 "Quiescence mode scheduled.\n"); 6074 if (IS_P3P_TYPE(ha)) { 6075 if (IS_QLA82XX(ha)) 6076 qla82xx_device_state_handler(base_vha); 6077 if (IS_QLA8044(ha)) 6078 qla8044_device_state_handler(base_vha); 6079 clear_bit(ISP_QUIESCE_NEEDED, 6080 &base_vha->dpc_flags); 6081 if (!ha->flags.quiesce_owner) { 6082 qla2x00_perform_loop_resync(base_vha); 6083 if (IS_QLA82XX(ha)) { 6084 qla82xx_idc_lock(ha); 6085 qla82xx_clear_qsnt_ready( 6086 base_vha); 6087 qla82xx_idc_unlock(ha); 6088 } else if (IS_QLA8044(ha)) { 6089 qla8044_idc_lock(ha); 6090 qla8044_clear_qsnt_ready( 6091 base_vha); 6092 qla8044_idc_unlock(ha); 6093 } 6094 } 6095 } else { 6096 clear_bit(ISP_QUIESCE_NEEDED, 6097 &base_vha->dpc_flags); 6098 qla2x00_quiesce_io(base_vha); 6099 } 6100 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6101 "Quiescence mode end.\n"); 6102 } 6103 6104 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6105 &base_vha->dpc_flags) && 6106 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6107 6108 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6109 "Reset marker scheduled.\n"); 6110 qla2x00_rst_aen(base_vha); 6111 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6112 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6113 "Reset marker end.\n"); 6114 } 6115 6116 /* Retry each device up to login retry count */ 6117 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6118 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6119 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6120 6121 if (!base_vha->relogin_jif || 6122 time_after_eq(jiffies, base_vha->relogin_jif)) { 6123 base_vha->relogin_jif = jiffies + HZ; 6124 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6125 6126 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6127 "Relogin scheduled.\n"); 6128 qla24xx_post_relogin_work(base_vha); 6129 } 6130 } 6131 loop_resync_check: 6132 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6133 &base_vha->dpc_flags)) { 6134 6135 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6136 "Loop resync scheduled.\n"); 6137 6138 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6139 &base_vha->dpc_flags))) { 6140 6141 qla2x00_loop_resync(base_vha); 6142 6143 clear_bit(LOOP_RESYNC_ACTIVE, 6144 &base_vha->dpc_flags); 6145 } 6146 6147 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6148 "Loop resync end.\n"); 6149 } 6150 6151 if (IS_QLAFX00(ha)) 6152 goto intr_on_check; 6153 6154 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6155 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6156 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6157 qla2xxx_flash_npiv_conf(base_vha); 6158 } 6159 6160 intr_on_check: 6161 if (!ha->interrupts_on) 6162 ha->isp_ops->enable_intrs(ha); 6163 6164 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6165 &base_vha->dpc_flags)) { 6166 if (ha->beacon_blink_led == 1) 6167 ha->isp_ops->beacon_blink(base_vha); 6168 } 6169 6170 /* qpair online check */ 6171 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6172 &base_vha->dpc_flags)) { 6173 if (ha->flags.eeh_busy || 6174 ha->flags.pci_channel_io_perm_failure) 6175 online = 0; 6176 else 6177 online = 1; 6178 6179 mutex_lock(&ha->mq_lock); 6180 list_for_each_entry(qpair, &base_vha->qp_list, 6181 qp_list_elem) 6182 qpair->online = online; 6183 mutex_unlock(&ha->mq_lock); 6184 } 6185 6186 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6187 ql_log(ql_log_info, base_vha, 0xffffff, 6188 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6189 ha->nvme_last_rptd_aen); 6190 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6191 ql_log(ql_log_info, base_vha, 0xffffff, 6192 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6193 ha->nvme_last_rptd_aen); 6194 } 6195 } 6196 6197 if (!IS_QLAFX00(ha)) 6198 qla2x00_do_dpc_all_vps(base_vha); 6199 6200 if (test_and_clear_bit(N2N_LINK_RESET, 6201 &base_vha->dpc_flags)) { 6202 qla2x00_lip_reset(base_vha); 6203 } 6204 6205 ha->dpc_active = 0; 6206 end_loop: 6207 set_current_state(TASK_INTERRUPTIBLE); 6208 } /* End of while(1) */ 6209 __set_current_state(TASK_RUNNING); 6210 6211 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6212 "DPC handler exiting.\n"); 6213 6214 /* 6215 * Make sure that nobody tries to wake us up again. 6216 */ 6217 ha->dpc_active = 0; 6218 6219 /* Cleanup any residual CTX SRBs. */ 6220 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6221 6222 return 0; 6223 } 6224 6225 void 6226 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6227 { 6228 struct qla_hw_data *ha = vha->hw; 6229 struct task_struct *t = ha->dpc_thread; 6230 6231 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6232 wake_up_process(t); 6233 } 6234 6235 /* 6236 * qla2x00_rst_aen 6237 * Processes asynchronous reset. 6238 * 6239 * Input: 6240 * ha = adapter block pointer. 6241 */ 6242 static void 6243 qla2x00_rst_aen(scsi_qla_host_t *vha) 6244 { 6245 if (vha->flags.online && !vha->flags.reset_active && 6246 !atomic_read(&vha->loop_down_timer) && 6247 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6248 do { 6249 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6250 6251 /* 6252 * Issue marker command only when we are going to start 6253 * the I/O. 6254 */ 6255 vha->marker_needed = 1; 6256 } while (!atomic_read(&vha->loop_down_timer) && 6257 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6258 } 6259 } 6260 6261 /************************************************************************** 6262 * qla2x00_timer 6263 * 6264 * Description: 6265 * One second timer 6266 * 6267 * Context: Interrupt 6268 ***************************************************************************/ 6269 void 6270 qla2x00_timer(struct timer_list *t) 6271 { 6272 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6273 unsigned long cpu_flags = 0; 6274 int start_dpc = 0; 6275 int index; 6276 srb_t *sp; 6277 uint16_t w; 6278 struct qla_hw_data *ha = vha->hw; 6279 struct req_que *req; 6280 6281 if (ha->flags.eeh_busy) { 6282 ql_dbg(ql_dbg_timer, vha, 0x6000, 6283 "EEH = %d, restarting timer.\n", 6284 ha->flags.eeh_busy); 6285 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6286 return; 6287 } 6288 6289 /* 6290 * Hardware read to raise pending EEH errors during mailbox waits. If 6291 * the read returns -1 then disable the board. 6292 */ 6293 if (!pci_channel_offline(ha->pdev)) { 6294 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6295 qla2x00_check_reg16_for_disconnect(vha, w); 6296 } 6297 6298 /* Make sure qla82xx_watchdog is run only for physical port */ 6299 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6300 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6301 start_dpc++; 6302 if (IS_QLA82XX(ha)) 6303 qla82xx_watchdog(vha); 6304 else if (IS_QLA8044(ha)) 6305 qla8044_watchdog(vha); 6306 } 6307 6308 if (!vha->vp_idx && IS_QLAFX00(ha)) 6309 qlafx00_timer_routine(vha); 6310 6311 /* Loop down handler. */ 6312 if (atomic_read(&vha->loop_down_timer) > 0 && 6313 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6314 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6315 && vha->flags.online) { 6316 6317 if (atomic_read(&vha->loop_down_timer) == 6318 vha->loop_down_abort_time) { 6319 6320 ql_log(ql_log_info, vha, 0x6008, 6321 "Loop down - aborting the queues before time expires.\n"); 6322 6323 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6324 atomic_set(&vha->loop_state, LOOP_DEAD); 6325 6326 /* 6327 * Schedule an ISP abort to return any FCP2-device 6328 * commands. 6329 */ 6330 /* NPIV - scan physical port only */ 6331 if (!vha->vp_idx) { 6332 spin_lock_irqsave(&ha->hardware_lock, 6333 cpu_flags); 6334 req = ha->req_q_map[0]; 6335 for (index = 1; 6336 index < req->num_outstanding_cmds; 6337 index++) { 6338 fc_port_t *sfcp; 6339 6340 sp = req->outstanding_cmds[index]; 6341 if (!sp) 6342 continue; 6343 if (sp->cmd_type != TYPE_SRB) 6344 continue; 6345 if (sp->type != SRB_SCSI_CMD) 6346 continue; 6347 sfcp = sp->fcport; 6348 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6349 continue; 6350 6351 if (IS_QLA82XX(ha)) 6352 set_bit(FCOE_CTX_RESET_NEEDED, 6353 &vha->dpc_flags); 6354 else 6355 set_bit(ISP_ABORT_NEEDED, 6356 &vha->dpc_flags); 6357 break; 6358 } 6359 spin_unlock_irqrestore(&ha->hardware_lock, 6360 cpu_flags); 6361 } 6362 start_dpc++; 6363 } 6364 6365 /* if the loop has been down for 4 minutes, reinit adapter */ 6366 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6367 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6368 ql_log(ql_log_warn, vha, 0x6009, 6369 "Loop down - aborting ISP.\n"); 6370 6371 if (IS_QLA82XX(ha)) 6372 set_bit(FCOE_CTX_RESET_NEEDED, 6373 &vha->dpc_flags); 6374 else 6375 set_bit(ISP_ABORT_NEEDED, 6376 &vha->dpc_flags); 6377 } 6378 } 6379 ql_dbg(ql_dbg_timer, vha, 0x600a, 6380 "Loop down - seconds remaining %d.\n", 6381 atomic_read(&vha->loop_down_timer)); 6382 } 6383 /* Check if beacon LED needs to be blinked for physical host only */ 6384 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6385 /* There is no beacon_blink function for ISP82xx */ 6386 if (!IS_P3P_TYPE(ha)) { 6387 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6388 start_dpc++; 6389 } 6390 } 6391 6392 /* Process any deferred work. */ 6393 if (!list_empty(&vha->work_list)) { 6394 unsigned long flags; 6395 bool q = false; 6396 6397 spin_lock_irqsave(&vha->work_lock, flags); 6398 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6399 q = true; 6400 spin_unlock_irqrestore(&vha->work_lock, flags); 6401 if (q) 6402 queue_work(vha->hw->wq, &vha->iocb_work); 6403 } 6404 6405 /* 6406 * FC-NVME 6407 * see if the active AEN count has changed from what was last reported. 6408 */ 6409 if (!vha->vp_idx && 6410 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6411 ha->zio_mode == QLA_ZIO_MODE_6) { 6412 ql_log(ql_log_info, vha, 0x3002, 6413 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6414 ha->nvme_last_rptd_aen); 6415 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6416 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6417 start_dpc++; 6418 } 6419 6420 /* Schedule the DPC routine if needed */ 6421 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6422 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6423 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6424 start_dpc || 6425 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6426 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6427 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6428 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6429 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6430 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6431 ql_dbg(ql_dbg_timer, vha, 0x600b, 6432 "isp_abort_needed=%d loop_resync_needed=%d " 6433 "fcport_update_needed=%d start_dpc=%d " 6434 "reset_marker_needed=%d", 6435 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6436 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6437 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6438 start_dpc, 6439 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6440 ql_dbg(ql_dbg_timer, vha, 0x600c, 6441 "beacon_blink_needed=%d isp_unrecoverable=%d " 6442 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6443 "relogin_needed=%d.\n", 6444 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6445 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6446 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6447 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6448 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6449 qla2xxx_wake_dpc(vha); 6450 } 6451 6452 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6453 } 6454 6455 /* Firmware interface routines. */ 6456 6457 #define FW_BLOBS 11 6458 #define FW_ISP21XX 0 6459 #define FW_ISP22XX 1 6460 #define FW_ISP2300 2 6461 #define FW_ISP2322 3 6462 #define FW_ISP24XX 4 6463 #define FW_ISP25XX 5 6464 #define FW_ISP81XX 6 6465 #define FW_ISP82XX 7 6466 #define FW_ISP2031 8 6467 #define FW_ISP8031 9 6468 #define FW_ISP27XX 10 6469 6470 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6471 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6472 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6473 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6474 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6475 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6476 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6477 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6478 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6479 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6480 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6481 6482 6483 static DEFINE_MUTEX(qla_fw_lock); 6484 6485 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6486 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6487 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6488 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6489 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6490 { .name = FW_FILE_ISP24XX, }, 6491 { .name = FW_FILE_ISP25XX, }, 6492 { .name = FW_FILE_ISP81XX, }, 6493 { .name = FW_FILE_ISP82XX, }, 6494 { .name = FW_FILE_ISP2031, }, 6495 { .name = FW_FILE_ISP8031, }, 6496 { .name = FW_FILE_ISP27XX, }, 6497 }; 6498 6499 struct fw_blob * 6500 qla2x00_request_firmware(scsi_qla_host_t *vha) 6501 { 6502 struct qla_hw_data *ha = vha->hw; 6503 struct fw_blob *blob; 6504 6505 if (IS_QLA2100(ha)) { 6506 blob = &qla_fw_blobs[FW_ISP21XX]; 6507 } else if (IS_QLA2200(ha)) { 6508 blob = &qla_fw_blobs[FW_ISP22XX]; 6509 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6510 blob = &qla_fw_blobs[FW_ISP2300]; 6511 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6512 blob = &qla_fw_blobs[FW_ISP2322]; 6513 } else if (IS_QLA24XX_TYPE(ha)) { 6514 blob = &qla_fw_blobs[FW_ISP24XX]; 6515 } else if (IS_QLA25XX(ha)) { 6516 blob = &qla_fw_blobs[FW_ISP25XX]; 6517 } else if (IS_QLA81XX(ha)) { 6518 blob = &qla_fw_blobs[FW_ISP81XX]; 6519 } else if (IS_QLA82XX(ha)) { 6520 blob = &qla_fw_blobs[FW_ISP82XX]; 6521 } else if (IS_QLA2031(ha)) { 6522 blob = &qla_fw_blobs[FW_ISP2031]; 6523 } else if (IS_QLA8031(ha)) { 6524 blob = &qla_fw_blobs[FW_ISP8031]; 6525 } else if (IS_QLA27XX(ha)) { 6526 blob = &qla_fw_blobs[FW_ISP27XX]; 6527 } else { 6528 return NULL; 6529 } 6530 6531 mutex_lock(&qla_fw_lock); 6532 if (blob->fw) 6533 goto out; 6534 6535 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6536 ql_log(ql_log_warn, vha, 0x0063, 6537 "Failed to load firmware image (%s).\n", blob->name); 6538 blob->fw = NULL; 6539 blob = NULL; 6540 goto out; 6541 } 6542 6543 out: 6544 mutex_unlock(&qla_fw_lock); 6545 return blob; 6546 } 6547 6548 static void 6549 qla2x00_release_firmware(void) 6550 { 6551 int idx; 6552 6553 mutex_lock(&qla_fw_lock); 6554 for (idx = 0; idx < FW_BLOBS; idx++) 6555 release_firmware(qla_fw_blobs[idx].fw); 6556 mutex_unlock(&qla_fw_lock); 6557 } 6558 6559 static pci_ers_result_t 6560 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6561 { 6562 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6563 struct qla_hw_data *ha = vha->hw; 6564 6565 ql_dbg(ql_dbg_aer, vha, 0x9000, 6566 "PCI error detected, state %x.\n", state); 6567 6568 if (!atomic_read(&pdev->enable_cnt)) { 6569 ql_log(ql_log_info, vha, 0xffff, 6570 "PCI device is disabled,state %x\n", state); 6571 return PCI_ERS_RESULT_NEED_RESET; 6572 } 6573 6574 switch (state) { 6575 case pci_channel_io_normal: 6576 ha->flags.eeh_busy = 0; 6577 if (ql2xmqsupport || ql2xnvmeenable) { 6578 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6579 qla2xxx_wake_dpc(vha); 6580 } 6581 return PCI_ERS_RESULT_CAN_RECOVER; 6582 case pci_channel_io_frozen: 6583 ha->flags.eeh_busy = 1; 6584 /* For ISP82XX complete any pending mailbox cmd */ 6585 if (IS_QLA82XX(ha)) { 6586 ha->flags.isp82xx_fw_hung = 1; 6587 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6588 qla82xx_clear_pending_mbx(vha); 6589 } 6590 qla2x00_free_irqs(vha); 6591 pci_disable_device(pdev); 6592 /* Return back all IOs */ 6593 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6594 if (ql2xmqsupport || ql2xnvmeenable) { 6595 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6596 qla2xxx_wake_dpc(vha); 6597 } 6598 return PCI_ERS_RESULT_NEED_RESET; 6599 case pci_channel_io_perm_failure: 6600 ha->flags.pci_channel_io_perm_failure = 1; 6601 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6602 if (ql2xmqsupport || ql2xnvmeenable) { 6603 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6604 qla2xxx_wake_dpc(vha); 6605 } 6606 return PCI_ERS_RESULT_DISCONNECT; 6607 } 6608 return PCI_ERS_RESULT_NEED_RESET; 6609 } 6610 6611 static pci_ers_result_t 6612 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6613 { 6614 int risc_paused = 0; 6615 uint32_t stat; 6616 unsigned long flags; 6617 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6618 struct qla_hw_data *ha = base_vha->hw; 6619 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6620 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6621 6622 if (IS_QLA82XX(ha)) 6623 return PCI_ERS_RESULT_RECOVERED; 6624 6625 spin_lock_irqsave(&ha->hardware_lock, flags); 6626 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6627 stat = RD_REG_DWORD(®->hccr); 6628 if (stat & HCCR_RISC_PAUSE) 6629 risc_paused = 1; 6630 } else if (IS_QLA23XX(ha)) { 6631 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6632 if (stat & HSR_RISC_PAUSED) 6633 risc_paused = 1; 6634 } else if (IS_FWI2_CAPABLE(ha)) { 6635 stat = RD_REG_DWORD(®24->host_status); 6636 if (stat & HSRX_RISC_PAUSED) 6637 risc_paused = 1; 6638 } 6639 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6640 6641 if (risc_paused) { 6642 ql_log(ql_log_info, base_vha, 0x9003, 6643 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6644 ha->isp_ops->fw_dump(base_vha, 0); 6645 6646 return PCI_ERS_RESULT_NEED_RESET; 6647 } else 6648 return PCI_ERS_RESULT_RECOVERED; 6649 } 6650 6651 static uint32_t 6652 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6653 { 6654 uint32_t rval = QLA_FUNCTION_FAILED; 6655 uint32_t drv_active = 0; 6656 struct qla_hw_data *ha = base_vha->hw; 6657 int fn; 6658 struct pci_dev *other_pdev = NULL; 6659 6660 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6661 "Entered %s.\n", __func__); 6662 6663 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6664 6665 if (base_vha->flags.online) { 6666 /* Abort all outstanding commands, 6667 * so as to be requeued later */ 6668 qla2x00_abort_isp_cleanup(base_vha); 6669 } 6670 6671 6672 fn = PCI_FUNC(ha->pdev->devfn); 6673 while (fn > 0) { 6674 fn--; 6675 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6676 "Finding pci device at function = 0x%x.\n", fn); 6677 other_pdev = 6678 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6679 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6680 fn)); 6681 6682 if (!other_pdev) 6683 continue; 6684 if (atomic_read(&other_pdev->enable_cnt)) { 6685 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6686 "Found PCI func available and enable at 0x%x.\n", 6687 fn); 6688 pci_dev_put(other_pdev); 6689 break; 6690 } 6691 pci_dev_put(other_pdev); 6692 } 6693 6694 if (!fn) { 6695 /* Reset owner */ 6696 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6697 "This devfn is reset owner = 0x%x.\n", 6698 ha->pdev->devfn); 6699 qla82xx_idc_lock(ha); 6700 6701 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6702 QLA8XXX_DEV_INITIALIZING); 6703 6704 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6705 QLA82XX_IDC_VERSION); 6706 6707 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6708 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6709 "drv_active = 0x%x.\n", drv_active); 6710 6711 qla82xx_idc_unlock(ha); 6712 /* Reset if device is not already reset 6713 * drv_active would be 0 if a reset has already been done 6714 */ 6715 if (drv_active) 6716 rval = qla82xx_start_firmware(base_vha); 6717 else 6718 rval = QLA_SUCCESS; 6719 qla82xx_idc_lock(ha); 6720 6721 if (rval != QLA_SUCCESS) { 6722 ql_log(ql_log_info, base_vha, 0x900b, 6723 "HW State: FAILED.\n"); 6724 qla82xx_clear_drv_active(ha); 6725 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6726 QLA8XXX_DEV_FAILED); 6727 } else { 6728 ql_log(ql_log_info, base_vha, 0x900c, 6729 "HW State: READY.\n"); 6730 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6731 QLA8XXX_DEV_READY); 6732 qla82xx_idc_unlock(ha); 6733 ha->flags.isp82xx_fw_hung = 0; 6734 rval = qla82xx_restart_isp(base_vha); 6735 qla82xx_idc_lock(ha); 6736 /* Clear driver state register */ 6737 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6738 qla82xx_set_drv_active(base_vha); 6739 } 6740 qla82xx_idc_unlock(ha); 6741 } else { 6742 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6743 "This devfn is not reset owner = 0x%x.\n", 6744 ha->pdev->devfn); 6745 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6746 QLA8XXX_DEV_READY)) { 6747 ha->flags.isp82xx_fw_hung = 0; 6748 rval = qla82xx_restart_isp(base_vha); 6749 qla82xx_idc_lock(ha); 6750 qla82xx_set_drv_active(base_vha); 6751 qla82xx_idc_unlock(ha); 6752 } 6753 } 6754 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6755 6756 return rval; 6757 } 6758 6759 static pci_ers_result_t 6760 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6761 { 6762 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6763 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6764 struct qla_hw_data *ha = base_vha->hw; 6765 struct rsp_que *rsp; 6766 int rc, retries = 10; 6767 6768 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6769 "Slot Reset.\n"); 6770 6771 /* Workaround: qla2xxx driver which access hardware earlier 6772 * needs error state to be pci_channel_io_online. 6773 * Otherwise mailbox command timesout. 6774 */ 6775 pdev->error_state = pci_channel_io_normal; 6776 6777 pci_restore_state(pdev); 6778 6779 /* pci_restore_state() clears the saved_state flag of the device 6780 * save restored state which resets saved_state flag 6781 */ 6782 pci_save_state(pdev); 6783 6784 if (ha->mem_only) 6785 rc = pci_enable_device_mem(pdev); 6786 else 6787 rc = pci_enable_device(pdev); 6788 6789 if (rc) { 6790 ql_log(ql_log_warn, base_vha, 0x9005, 6791 "Can't re-enable PCI device after reset.\n"); 6792 goto exit_slot_reset; 6793 } 6794 6795 rsp = ha->rsp_q_map[0]; 6796 if (qla2x00_request_irqs(ha, rsp)) 6797 goto exit_slot_reset; 6798 6799 if (ha->isp_ops->pci_config(base_vha)) 6800 goto exit_slot_reset; 6801 6802 if (IS_QLA82XX(ha)) { 6803 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6804 ret = PCI_ERS_RESULT_RECOVERED; 6805 goto exit_slot_reset; 6806 } else 6807 goto exit_slot_reset; 6808 } 6809 6810 while (ha->flags.mbox_busy && retries--) 6811 msleep(1000); 6812 6813 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6814 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6815 ret = PCI_ERS_RESULT_RECOVERED; 6816 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6817 6818 6819 exit_slot_reset: 6820 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6821 "slot_reset return %x.\n", ret); 6822 6823 return ret; 6824 } 6825 6826 static void 6827 qla2xxx_pci_resume(struct pci_dev *pdev) 6828 { 6829 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6830 struct qla_hw_data *ha = base_vha->hw; 6831 int ret; 6832 6833 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6834 "pci_resume.\n"); 6835 6836 ret = qla2x00_wait_for_hba_online(base_vha); 6837 if (ret != QLA_SUCCESS) { 6838 ql_log(ql_log_fatal, base_vha, 0x9002, 6839 "The device failed to resume I/O from slot/link_reset.\n"); 6840 } 6841 6842 pci_cleanup_aer_uncorrect_error_status(pdev); 6843 6844 ha->flags.eeh_busy = 0; 6845 } 6846 6847 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6848 { 6849 int rc; 6850 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6851 6852 if (USER_CTRL_IRQ(vha->hw)) 6853 rc = blk_mq_map_queues(&shost->tag_set); 6854 else 6855 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); 6856 return rc; 6857 } 6858 6859 static const struct pci_error_handlers qla2xxx_err_handler = { 6860 .error_detected = qla2xxx_pci_error_detected, 6861 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6862 .slot_reset = qla2xxx_pci_slot_reset, 6863 .resume = qla2xxx_pci_resume, 6864 }; 6865 6866 static struct pci_device_id qla2xxx_pci_tbl[] = { 6867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6872 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6873 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6874 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6875 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6876 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6877 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6878 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6879 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6880 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6881 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6882 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6883 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6884 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6885 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6886 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6887 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6888 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6889 { 0 }, 6890 }; 6891 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6892 6893 static struct pci_driver qla2xxx_pci_driver = { 6894 .name = QLA2XXX_DRIVER_NAME, 6895 .driver = { 6896 .owner = THIS_MODULE, 6897 }, 6898 .id_table = qla2xxx_pci_tbl, 6899 .probe = qla2x00_probe_one, 6900 .remove = qla2x00_remove_one, 6901 .shutdown = qla2x00_shutdown, 6902 .err_handler = &qla2xxx_err_handler, 6903 }; 6904 6905 static const struct file_operations apidev_fops = { 6906 .owner = THIS_MODULE, 6907 .llseek = noop_llseek, 6908 }; 6909 6910 /** 6911 * qla2x00_module_init - Module initialization. 6912 **/ 6913 static int __init 6914 qla2x00_module_init(void) 6915 { 6916 int ret = 0; 6917 6918 /* Allocate cache for SRBs. */ 6919 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6920 SLAB_HWCACHE_ALIGN, NULL); 6921 if (srb_cachep == NULL) { 6922 ql_log(ql_log_fatal, NULL, 0x0001, 6923 "Unable to allocate SRB cache...Failing load!.\n"); 6924 return -ENOMEM; 6925 } 6926 6927 /* Initialize target kmem_cache and mem_pools */ 6928 ret = qlt_init(); 6929 if (ret < 0) { 6930 kmem_cache_destroy(srb_cachep); 6931 return ret; 6932 } else if (ret > 0) { 6933 /* 6934 * If initiator mode is explictly disabled by qlt_init(), 6935 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6936 * performing scsi_scan_target() during LOOP UP event. 6937 */ 6938 qla2xxx_transport_functions.disable_target_scan = 1; 6939 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6940 } 6941 6942 /* Derive version string. */ 6943 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6944 if (ql2xextended_error_logging) 6945 strcat(qla2x00_version_str, "-debug"); 6946 if (ql2xextended_error_logging == 1) 6947 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6948 6949 qla2xxx_transport_template = 6950 fc_attach_transport(&qla2xxx_transport_functions); 6951 if (!qla2xxx_transport_template) { 6952 kmem_cache_destroy(srb_cachep); 6953 ql_log(ql_log_fatal, NULL, 0x0002, 6954 "fc_attach_transport failed...Failing load!.\n"); 6955 qlt_exit(); 6956 return -ENODEV; 6957 } 6958 6959 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6960 if (apidev_major < 0) { 6961 ql_log(ql_log_fatal, NULL, 0x0003, 6962 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6963 } 6964 6965 qla2xxx_transport_vport_template = 6966 fc_attach_transport(&qla2xxx_transport_vport_functions); 6967 if (!qla2xxx_transport_vport_template) { 6968 kmem_cache_destroy(srb_cachep); 6969 qlt_exit(); 6970 fc_release_transport(qla2xxx_transport_template); 6971 ql_log(ql_log_fatal, NULL, 0x0004, 6972 "fc_attach_transport vport failed...Failing load!.\n"); 6973 return -ENODEV; 6974 } 6975 ql_log(ql_log_info, NULL, 0x0005, 6976 "QLogic Fibre Channel HBA Driver: %s.\n", 6977 qla2x00_version_str); 6978 ret = pci_register_driver(&qla2xxx_pci_driver); 6979 if (ret) { 6980 kmem_cache_destroy(srb_cachep); 6981 qlt_exit(); 6982 fc_release_transport(qla2xxx_transport_template); 6983 fc_release_transport(qla2xxx_transport_vport_template); 6984 ql_log(ql_log_fatal, NULL, 0x0006, 6985 "pci_register_driver failed...ret=%d Failing load!.\n", 6986 ret); 6987 } 6988 return ret; 6989 } 6990 6991 /** 6992 * qla2x00_module_exit - Module cleanup. 6993 **/ 6994 static void __exit 6995 qla2x00_module_exit(void) 6996 { 6997 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6998 pci_unregister_driver(&qla2xxx_pci_driver); 6999 qla2x00_release_firmware(); 7000 kmem_cache_destroy(srb_cachep); 7001 qlt_exit(); 7002 if (ctx_cachep) 7003 kmem_cache_destroy(ctx_cachep); 7004 fc_release_transport(qla2xxx_transport_template); 7005 fc_release_transport(qla2xxx_transport_vport_template); 7006 } 7007 7008 module_init(qla2x00_module_init); 7009 module_exit(qla2x00_module_exit); 7010 7011 MODULE_AUTHOR("QLogic Corporation"); 7012 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7013 MODULE_LICENSE("GPL"); 7014 MODULE_VERSION(QLA2XXX_VERSION); 7015 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7016 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7017 MODULE_FIRMWARE(FW_FILE_ISP2300); 7018 MODULE_FIRMWARE(FW_FILE_ISP2322); 7019 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7020 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7021