1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 32 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 32."); 122 123 int ql2xenabledif = 2; 124 module_param(ql2xenabledif, int, S_IRUGO); 125 MODULE_PARM_DESC(ql2xenabledif, 126 " Enable T10-CRC-DIF:\n" 127 " Default is 2.\n" 128 " 0 -- No DIF Support\n" 129 " 1 -- Enable DIF for all types\n" 130 " 2 -- Enable DIF for all types, except Type 0.\n"); 131 132 int ql2xenablehba_err_chk = 2; 133 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 134 MODULE_PARM_DESC(ql2xenablehba_err_chk, 135 " Enable T10-CRC-DIF Error isolation by HBA:\n" 136 " Default is 2.\n" 137 " 0 -- Error isolation disabled\n" 138 " 1 -- Error isolation enabled only for DIX Type 0\n" 139 " 2 -- Error isolation enabled for all Types\n"); 140 141 int ql2xiidmaenable=1; 142 module_param(ql2xiidmaenable, int, S_IRUGO); 143 MODULE_PARM_DESC(ql2xiidmaenable, 144 "Enables iIDMA settings " 145 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 146 147 int ql2xmqsupport = 1; 148 module_param(ql2xmqsupport, int, S_IRUGO); 149 MODULE_PARM_DESC(ql2xmqsupport, 150 "Enable on demand multiple queue pairs support " 151 "Default is 1 for supported. " 152 "Set it to 0 to turn off mq qpair support."); 153 154 int ql2xfwloadbin; 155 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 156 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 157 MODULE_PARM_DESC(ql2xfwloadbin, 158 "Option to specify location from which to load ISP firmware:.\n" 159 " 2 -- load firmware via the request_firmware() (hotplug).\n" 160 " interface.\n" 161 " 1 -- load firmware from flash.\n" 162 " 0 -- use default semantics.\n"); 163 164 int ql2xetsenable; 165 module_param(ql2xetsenable, int, S_IRUGO); 166 MODULE_PARM_DESC(ql2xetsenable, 167 "Enables firmware ETS burst." 168 "Default is 0 - skip ETS enablement."); 169 170 int ql2xdbwr = 1; 171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xdbwr, 173 "Option to specify scheme for request queue posting.\n" 174 " 0 -- Regular doorbell.\n" 175 " 1 -- CAMRAM doorbell (faster).\n"); 176 177 int ql2xtargetreset = 1; 178 module_param(ql2xtargetreset, int, S_IRUGO); 179 MODULE_PARM_DESC(ql2xtargetreset, 180 "Enable target reset." 181 "Default is 1 - use hw defaults."); 182 183 int ql2xgffidenable; 184 module_param(ql2xgffidenable, int, S_IRUGO); 185 MODULE_PARM_DESC(ql2xgffidenable, 186 "Enables GFF_ID checks of port type. " 187 "Default is 0 - Do not use GFF_ID information."); 188 189 int ql2xasynctmfenable; 190 module_param(ql2xasynctmfenable, int, S_IRUGO); 191 MODULE_PARM_DESC(ql2xasynctmfenable, 192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 193 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 194 195 int ql2xdontresethba; 196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 197 MODULE_PARM_DESC(ql2xdontresethba, 198 "Option to specify reset behaviour.\n" 199 " 0 (Default) -- Reset on failure.\n" 200 " 1 -- Do not reset on failure.\n"); 201 202 uint64_t ql2xmaxlun = MAX_LUNS; 203 module_param(ql2xmaxlun, ullong, S_IRUGO); 204 MODULE_PARM_DESC(ql2xmaxlun, 205 "Defines the maximum LU number to register with the SCSI " 206 "midlayer. Default is 65535."); 207 208 int ql2xmdcapmask = 0x1F; 209 module_param(ql2xmdcapmask, int, S_IRUGO); 210 MODULE_PARM_DESC(ql2xmdcapmask, 211 "Set the Minidump driver capture mask level. " 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 213 214 int ql2xmdenable = 1; 215 module_param(ql2xmdenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xmdenable, 217 "Enable/disable MiniDump. " 218 "0 - MiniDump disabled. " 219 "1 (Default) - MiniDump enabled."); 220 221 int ql2xexlogins = 0; 222 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 223 MODULE_PARM_DESC(ql2xexlogins, 224 "Number of extended Logins. " 225 "0 (Default)- Disabled."); 226 227 int ql2xexchoffld = 0; 228 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xexchoffld, 230 "Number of exchanges to offload. " 231 "0 (Default)- Disabled."); 232 233 int ql2xfwholdabts = 0; 234 module_param(ql2xfwholdabts, int, S_IRUGO); 235 MODULE_PARM_DESC(ql2xfwholdabts, 236 "Allow FW to hold status IOCB until ABTS rsp received. " 237 "0 (Default) Do not set fw option. " 238 "1 - Set fw option to hold ABTS."); 239 240 int ql2xmvasynctoatio = 1; 241 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 242 MODULE_PARM_DESC(ql2xmvasynctoatio, 243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 244 "0 (Default). Do not move IOCBs" 245 "1 - Move IOCBs."); 246 247 /* 248 * SCSI host template entry points 249 */ 250 static int qla2xxx_slave_configure(struct scsi_device * device); 251 static int qla2xxx_slave_alloc(struct scsi_device *); 252 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 253 static void qla2xxx_scan_start(struct Scsi_Host *); 254 static void qla2xxx_slave_destroy(struct scsi_device *); 255 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 256 static int qla2xxx_eh_abort(struct scsi_cmnd *); 257 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 258 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 259 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 260 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 261 262 static void qla2x00_clear_drv_active(struct qla_hw_data *); 263 static void qla2x00_free_device(scsi_qla_host_t *); 264 static void qla83xx_disable_laser(scsi_qla_host_t *vha); 265 static int qla2xxx_map_queues(struct Scsi_Host *shost); 266 267 struct scsi_host_template qla2xxx_driver_template = { 268 .module = THIS_MODULE, 269 .name = QLA2XXX_DRIVER_NAME, 270 .queuecommand = qla2xxx_queuecommand, 271 272 .eh_timed_out = fc_eh_timed_out, 273 .eh_abort_handler = qla2xxx_eh_abort, 274 .eh_device_reset_handler = qla2xxx_eh_device_reset, 275 .eh_target_reset_handler = qla2xxx_eh_target_reset, 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 277 .eh_host_reset_handler = qla2xxx_eh_host_reset, 278 279 .slave_configure = qla2xxx_slave_configure, 280 281 .slave_alloc = qla2xxx_slave_alloc, 282 .slave_destroy = qla2xxx_slave_destroy, 283 .scan_finished = qla2xxx_scan_finished, 284 .scan_start = qla2xxx_scan_start, 285 .change_queue_depth = scsi_change_queue_depth, 286 .map_queues = qla2xxx_map_queues, 287 .this_id = -1, 288 .cmd_per_lun = 3, 289 .use_clustering = ENABLE_CLUSTERING, 290 .sg_tablesize = SG_ALL, 291 292 .max_sectors = 0xFFFF, 293 .shost_attrs = qla2x00_host_attrs, 294 295 .supported_mode = MODE_INITIATOR, 296 .track_queue_depth = 1, 297 }; 298 299 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 300 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 301 302 /* TODO Convert to inlines 303 * 304 * Timer routines 305 */ 306 307 __inline__ void 308 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) 309 { 310 init_timer(&vha->timer); 311 vha->timer.expires = jiffies + interval * HZ; 312 vha->timer.data = (unsigned long)vha; 313 vha->timer.function = (void (*)(unsigned long))func; 314 add_timer(&vha->timer); 315 vha->timer_active = 1; 316 } 317 318 static inline void 319 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 320 { 321 /* Currently used for 82XX only. */ 322 if (vha->device_flags & DFLG_DEV_FAILED) { 323 ql_dbg(ql_dbg_timer, vha, 0x600d, 324 "Device in a failed state, returning.\n"); 325 return; 326 } 327 328 mod_timer(&vha->timer, jiffies + interval * HZ); 329 } 330 331 static __inline__ void 332 qla2x00_stop_timer(scsi_qla_host_t *vha) 333 { 334 del_timer_sync(&vha->timer); 335 vha->timer_active = 0; 336 } 337 338 static int qla2x00_do_dpc(void *data); 339 340 static void qla2x00_rst_aen(scsi_qla_host_t *); 341 342 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 343 struct req_que **, struct rsp_que **); 344 static void qla2x00_free_fw_dump(struct qla_hw_data *); 345 static void qla2x00_mem_free(struct qla_hw_data *); 346 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 347 struct qla_qpair *qpair); 348 349 /* -------------------------------------------------------------------------- */ 350 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 351 struct rsp_que *rsp) 352 { 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 355 GFP_KERNEL); 356 if (!ha->req_q_map) { 357 ql_log(ql_log_fatal, vha, 0x003b, 358 "Unable to allocate memory for request queue ptrs.\n"); 359 goto fail_req_map; 360 } 361 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 363 GFP_KERNEL); 364 if (!ha->rsp_q_map) { 365 ql_log(ql_log_fatal, vha, 0x003c, 366 "Unable to allocate memory for response queue ptrs.\n"); 367 goto fail_rsp_map; 368 } 369 370 if (ql2xmqsupport && ha->max_qpairs) { 371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 372 GFP_KERNEL); 373 if (!ha->queue_pair_map) { 374 ql_log(ql_log_fatal, vha, 0x0180, 375 "Unable to allocate memory for queue pair ptrs.\n"); 376 goto fail_qpair_map; 377 } 378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 379 if (ha->base_qpair == NULL) { 380 ql_log(ql_log_warn, vha, 0x0182, 381 "Failed to allocate base queue pair memory.\n"); 382 goto fail_base_qpair; 383 } 384 ha->base_qpair->req = req; 385 ha->base_qpair->rsp = rsp; 386 } 387 388 /* 389 * Make sure we record at least the request and response queue zero in 390 * case we need to free them if part of the probe fails. 391 */ 392 ha->rsp_q_map[0] = rsp; 393 ha->req_q_map[0] = req; 394 set_bit(0, ha->rsp_qid_map); 395 set_bit(0, ha->req_qid_map); 396 return 1; 397 398 fail_base_qpair: 399 kfree(ha->queue_pair_map); 400 fail_qpair_map: 401 kfree(ha->rsp_q_map); 402 ha->rsp_q_map = NULL; 403 fail_rsp_map: 404 kfree(ha->req_q_map); 405 ha->req_q_map = NULL; 406 fail_req_map: 407 return -ENOMEM; 408 } 409 410 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 411 { 412 if (IS_QLAFX00(ha)) { 413 if (req && req->ring_fx00) 414 dma_free_coherent(&ha->pdev->dev, 415 (req->length_fx00 + 1) * sizeof(request_t), 416 req->ring_fx00, req->dma_fx00); 417 } else if (req && req->ring) 418 dma_free_coherent(&ha->pdev->dev, 419 (req->length + 1) * sizeof(request_t), 420 req->ring, req->dma); 421 422 if (req) 423 kfree(req->outstanding_cmds); 424 425 kfree(req); 426 req = NULL; 427 } 428 429 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 430 { 431 if (IS_QLAFX00(ha)) { 432 if (rsp && rsp->ring) 433 dma_free_coherent(&ha->pdev->dev, 434 (rsp->length_fx00 + 1) * sizeof(request_t), 435 rsp->ring_fx00, rsp->dma_fx00); 436 } else if (rsp && rsp->ring) { 437 dma_free_coherent(&ha->pdev->dev, 438 (rsp->length + 1) * sizeof(response_t), 439 rsp->ring, rsp->dma); 440 } 441 kfree(rsp); 442 rsp = NULL; 443 } 444 445 static void qla2x00_free_queues(struct qla_hw_data *ha) 446 { 447 struct req_que *req; 448 struct rsp_que *rsp; 449 int cnt; 450 unsigned long flags; 451 452 spin_lock_irqsave(&ha->hardware_lock, flags); 453 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 454 if (!test_bit(cnt, ha->req_qid_map)) 455 continue; 456 457 req = ha->req_q_map[cnt]; 458 clear_bit(cnt, ha->req_qid_map); 459 ha->req_q_map[cnt] = NULL; 460 461 spin_unlock_irqrestore(&ha->hardware_lock, flags); 462 qla2x00_free_req_que(ha, req); 463 spin_lock_irqsave(&ha->hardware_lock, flags); 464 } 465 spin_unlock_irqrestore(&ha->hardware_lock, flags); 466 467 kfree(ha->req_q_map); 468 ha->req_q_map = NULL; 469 470 471 spin_lock_irqsave(&ha->hardware_lock, flags); 472 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 473 if (!test_bit(cnt, ha->rsp_qid_map)) 474 continue; 475 476 rsp = ha->rsp_q_map[cnt]; 477 clear_bit(cnt, ha->rsp_qid_map); 478 ha->rsp_q_map[cnt] = NULL; 479 spin_unlock_irqrestore(&ha->hardware_lock, flags); 480 qla2x00_free_rsp_que(ha, rsp); 481 spin_lock_irqsave(&ha->hardware_lock, flags); 482 } 483 spin_unlock_irqrestore(&ha->hardware_lock, flags); 484 485 kfree(ha->rsp_q_map); 486 ha->rsp_q_map = NULL; 487 } 488 489 static char * 490 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 491 { 492 struct qla_hw_data *ha = vha->hw; 493 static char *pci_bus_modes[] = { 494 "33", "66", "100", "133", 495 }; 496 uint16_t pci_bus; 497 498 strcpy(str, "PCI"); 499 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 500 if (pci_bus) { 501 strcat(str, "-X ("); 502 strcat(str, pci_bus_modes[pci_bus]); 503 } else { 504 pci_bus = (ha->pci_attr & BIT_8) >> 8; 505 strcat(str, " ("); 506 strcat(str, pci_bus_modes[pci_bus]); 507 } 508 strcat(str, " MHz)"); 509 510 return (str); 511 } 512 513 static char * 514 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 515 { 516 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 517 struct qla_hw_data *ha = vha->hw; 518 uint32_t pci_bus; 519 520 if (pci_is_pcie(ha->pdev)) { 521 char lwstr[6]; 522 uint32_t lstat, lspeed, lwidth; 523 524 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 525 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 526 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 527 528 strcpy(str, "PCIe ("); 529 switch (lspeed) { 530 case 1: 531 strcat(str, "2.5GT/s "); 532 break; 533 case 2: 534 strcat(str, "5.0GT/s "); 535 break; 536 case 3: 537 strcat(str, "8.0GT/s "); 538 break; 539 default: 540 strcat(str, "<unknown> "); 541 break; 542 } 543 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 544 strcat(str, lwstr); 545 546 return str; 547 } 548 549 strcpy(str, "PCI"); 550 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 551 if (pci_bus == 0 || pci_bus == 8) { 552 strcat(str, " ("); 553 strcat(str, pci_bus_modes[pci_bus >> 3]); 554 } else { 555 strcat(str, "-X "); 556 if (pci_bus & BIT_2) 557 strcat(str, "Mode 2"); 558 else 559 strcat(str, "Mode 1"); 560 strcat(str, " ("); 561 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 562 } 563 strcat(str, " MHz)"); 564 565 return str; 566 } 567 568 static char * 569 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 570 { 571 char un_str[10]; 572 struct qla_hw_data *ha = vha->hw; 573 574 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 575 ha->fw_minor_version, ha->fw_subminor_version); 576 577 if (ha->fw_attributes & BIT_9) { 578 strcat(str, "FLX"); 579 return (str); 580 } 581 582 switch (ha->fw_attributes & 0xFF) { 583 case 0x7: 584 strcat(str, "EF"); 585 break; 586 case 0x17: 587 strcat(str, "TP"); 588 break; 589 case 0x37: 590 strcat(str, "IP"); 591 break; 592 case 0x77: 593 strcat(str, "VI"); 594 break; 595 default: 596 sprintf(un_str, "(%x)", ha->fw_attributes); 597 strcat(str, un_str); 598 break; 599 } 600 if (ha->fw_attributes & 0x100) 601 strcat(str, "X"); 602 603 return (str); 604 } 605 606 static char * 607 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 608 { 609 struct qla_hw_data *ha = vha->hw; 610 611 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 612 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 613 return str; 614 } 615 616 void 617 qla2x00_sp_free_dma(void *ptr) 618 { 619 srb_t *sp = ptr; 620 struct qla_hw_data *ha = sp->vha->hw; 621 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 622 void *ctx = GET_CMD_CTX_SP(sp); 623 624 if (sp->flags & SRB_DMA_VALID) { 625 scsi_dma_unmap(cmd); 626 sp->flags &= ~SRB_DMA_VALID; 627 } 628 629 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 630 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 631 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 632 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 633 } 634 635 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 636 /* List assured to be having elements */ 637 qla2x00_clean_dsd_pool(ha, sp, NULL); 638 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 639 } 640 641 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 642 dma_pool_free(ha->dl_dma_pool, ctx, 643 ((struct crc_context *)ctx)->crc_ctx_dma); 644 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 645 } 646 647 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 648 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 649 650 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 651 ctx1->fcp_cmnd_dma); 652 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 653 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 654 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 655 mempool_free(ctx1, ha->ctx_mempool); 656 ctx1 = NULL; 657 } 658 659 CMD_SP(cmd) = NULL; 660 qla2x00_rel_sp(sp); 661 } 662 663 void 664 qla2x00_sp_compl(void *ptr, int res) 665 { 666 srb_t *sp = ptr; 667 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 668 669 cmd->result = res; 670 671 if (atomic_read(&sp->ref_count) == 0) { 672 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 673 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 674 sp, GET_CMD_SP(sp)); 675 if (ql2xextended_error_logging & ql_dbg_io) 676 WARN_ON(atomic_read(&sp->ref_count) == 0); 677 return; 678 } 679 if (!atomic_dec_and_test(&sp->ref_count)) 680 return; 681 682 qla2x00_sp_free_dma(sp); 683 cmd->scsi_done(cmd); 684 } 685 686 void 687 qla2xxx_qpair_sp_free_dma(void *ptr) 688 { 689 srb_t *sp = (srb_t *)ptr; 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 691 struct qla_hw_data *ha = sp->fcport->vha->hw; 692 void *ctx = GET_CMD_CTX_SP(sp); 693 694 if (sp->flags & SRB_DMA_VALID) { 695 scsi_dma_unmap(cmd); 696 sp->flags &= ~SRB_DMA_VALID; 697 } 698 699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 701 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 703 } 704 705 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 706 /* List assured to be having elements */ 707 qla2x00_clean_dsd_pool(ha, sp, NULL); 708 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 709 } 710 711 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 712 dma_pool_free(ha->dl_dma_pool, ctx, 713 ((struct crc_context *)ctx)->crc_ctx_dma); 714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 715 } 716 717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 718 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; 719 720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 721 ctx1->fcp_cmnd_dma); 722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 725 mempool_free(ctx1, ha->ctx_mempool); 726 } 727 728 CMD_SP(cmd) = NULL; 729 qla2xxx_rel_qpair_sp(sp->qpair, sp); 730 } 731 732 void 733 qla2xxx_qpair_sp_compl(void *ptr, int res) 734 { 735 srb_t *sp = ptr; 736 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 737 738 cmd->result = res; 739 740 if (atomic_read(&sp->ref_count) == 0) { 741 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 742 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 743 sp, GET_CMD_SP(sp)); 744 if (ql2xextended_error_logging & ql_dbg_io) 745 WARN_ON(atomic_read(&sp->ref_count) == 0); 746 return; 747 } 748 if (!atomic_dec_and_test(&sp->ref_count)) 749 return; 750 751 qla2xxx_qpair_sp_free_dma(sp); 752 cmd->scsi_done(cmd); 753 } 754 755 /* If we are SP1 here, we need to still take and release the host_lock as SP1 756 * does not have the changes necessary to avoid taking host->host_lock. 757 */ 758 static int 759 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 760 { 761 scsi_qla_host_t *vha = shost_priv(host); 762 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 763 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 764 struct qla_hw_data *ha = vha->hw; 765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 766 srb_t *sp; 767 int rval; 768 struct qla_qpair *qpair = NULL; 769 uint32_t tag; 770 uint16_t hwq; 771 772 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 773 cmd->result = DID_NO_CONNECT << 16; 774 goto qc24_fail_command; 775 } 776 777 if (ha->mqenable) { 778 if (shost_use_blk_mq(vha->host)) { 779 tag = blk_mq_unique_tag(cmd->request); 780 hwq = blk_mq_unique_tag_to_hwq(tag); 781 qpair = ha->queue_pair_map[hwq]; 782 } else if (vha->vp_idx && vha->qpair) { 783 qpair = vha->qpair; 784 } 785 786 if (qpair) 787 return qla2xxx_mqueuecommand(host, cmd, qpair); 788 } 789 790 if (ha->flags.eeh_busy) { 791 if (ha->flags.pci_channel_io_perm_failure) { 792 ql_dbg(ql_dbg_aer, vha, 0x9010, 793 "PCI Channel IO permanent failure, exiting " 794 "cmd=%p.\n", cmd); 795 cmd->result = DID_NO_CONNECT << 16; 796 } else { 797 ql_dbg(ql_dbg_aer, vha, 0x9011, 798 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 799 cmd->result = DID_REQUEUE << 16; 800 } 801 goto qc24_fail_command; 802 } 803 804 rval = fc_remote_port_chkready(rport); 805 if (rval) { 806 cmd->result = rval; 807 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 808 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 809 cmd, rval); 810 goto qc24_fail_command; 811 } 812 813 if (!vha->flags.difdix_supported && 814 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 815 ql_dbg(ql_dbg_io, vha, 0x3004, 816 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 817 cmd); 818 cmd->result = DID_NO_CONNECT << 16; 819 goto qc24_fail_command; 820 } 821 822 if (!fcport) { 823 cmd->result = DID_NO_CONNECT << 16; 824 goto qc24_fail_command; 825 } 826 827 if (atomic_read(&fcport->state) != FCS_ONLINE) { 828 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 829 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 830 ql_dbg(ql_dbg_io, vha, 0x3005, 831 "Returning DNC, fcport_state=%d loop_state=%d.\n", 832 atomic_read(&fcport->state), 833 atomic_read(&base_vha->loop_state)); 834 cmd->result = DID_NO_CONNECT << 16; 835 goto qc24_fail_command; 836 } 837 goto qc24_target_busy; 838 } 839 840 /* 841 * Return target busy if we've received a non-zero retry_delay_timer 842 * in a FCP_RSP. 843 */ 844 if (fcport->retry_delay_timestamp == 0) { 845 /* retry delay not set */ 846 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 847 fcport->retry_delay_timestamp = 0; 848 else 849 goto qc24_target_busy; 850 851 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 852 if (!sp) 853 goto qc24_host_busy; 854 855 sp->u.scmd.cmd = cmd; 856 sp->type = SRB_SCSI_CMD; 857 atomic_set(&sp->ref_count, 1); 858 CMD_SP(cmd) = (void *)sp; 859 sp->free = qla2x00_sp_free_dma; 860 sp->done = qla2x00_sp_compl; 861 862 rval = ha->isp_ops->start_scsi(sp); 863 if (rval != QLA_SUCCESS) { 864 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 865 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 866 goto qc24_host_busy_free_sp; 867 } 868 869 return 0; 870 871 qc24_host_busy_free_sp: 872 qla2x00_sp_free_dma(sp); 873 874 qc24_host_busy: 875 return SCSI_MLQUEUE_HOST_BUSY; 876 877 qc24_target_busy: 878 return SCSI_MLQUEUE_TARGET_BUSY; 879 880 qc24_fail_command: 881 cmd->scsi_done(cmd); 882 883 return 0; 884 } 885 886 /* For MQ supported I/O */ 887 int 888 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 889 struct qla_qpair *qpair) 890 { 891 scsi_qla_host_t *vha = shost_priv(host); 892 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 893 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 894 struct qla_hw_data *ha = vha->hw; 895 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 896 srb_t *sp; 897 int rval; 898 899 rval = fc_remote_port_chkready(rport); 900 if (rval) { 901 cmd->result = rval; 902 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 903 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 904 cmd, rval); 905 goto qc24_fail_command; 906 } 907 908 if (!fcport) { 909 cmd->result = DID_NO_CONNECT << 16; 910 goto qc24_fail_command; 911 } 912 913 if (atomic_read(&fcport->state) != FCS_ONLINE) { 914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 916 ql_dbg(ql_dbg_io, vha, 0x3077, 917 "Returning DNC, fcport_state=%d loop_state=%d.\n", 918 atomic_read(&fcport->state), 919 atomic_read(&base_vha->loop_state)); 920 cmd->result = DID_NO_CONNECT << 16; 921 goto qc24_fail_command; 922 } 923 goto qc24_target_busy; 924 } 925 926 /* 927 * Return target busy if we've received a non-zero retry_delay_timer 928 * in a FCP_RSP. 929 */ 930 if (fcport->retry_delay_timestamp == 0) { 931 /* retry delay not set */ 932 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 933 fcport->retry_delay_timestamp = 0; 934 else 935 goto qc24_target_busy; 936 937 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 938 if (!sp) 939 goto qc24_host_busy; 940 941 sp->u.scmd.cmd = cmd; 942 sp->type = SRB_SCSI_CMD; 943 atomic_set(&sp->ref_count, 1); 944 CMD_SP(cmd) = (void *)sp; 945 sp->free = qla2xxx_qpair_sp_free_dma; 946 sp->done = qla2xxx_qpair_sp_compl; 947 sp->qpair = qpair; 948 949 rval = ha->isp_ops->start_scsi_mq(sp); 950 if (rval != QLA_SUCCESS) { 951 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 952 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 953 if (rval == QLA_INTERFACE_ERROR) 954 goto qc24_fail_command; 955 goto qc24_host_busy_free_sp; 956 } 957 958 return 0; 959 960 qc24_host_busy_free_sp: 961 qla2xxx_qpair_sp_free_dma(sp); 962 963 qc24_host_busy: 964 return SCSI_MLQUEUE_HOST_BUSY; 965 966 qc24_target_busy: 967 return SCSI_MLQUEUE_TARGET_BUSY; 968 969 qc24_fail_command: 970 cmd->scsi_done(cmd); 971 972 return 0; 973 } 974 975 /* 976 * qla2x00_eh_wait_on_command 977 * Waits for the command to be returned by the Firmware for some 978 * max time. 979 * 980 * Input: 981 * cmd = Scsi Command to wait on. 982 * 983 * Return: 984 * Not Found : 0 985 * Found : 1 986 */ 987 static int 988 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 989 { 990 #define ABORT_POLLING_PERIOD 1000 991 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 992 unsigned long wait_iter = ABORT_WAIT_ITER; 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 994 struct qla_hw_data *ha = vha->hw; 995 int ret = QLA_SUCCESS; 996 997 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 998 ql_dbg(ql_dbg_taskm, vha, 0x8005, 999 "Return:eh_wait.\n"); 1000 return ret; 1001 } 1002 1003 while (CMD_SP(cmd) && wait_iter--) { 1004 msleep(ABORT_POLLING_PERIOD); 1005 } 1006 if (CMD_SP(cmd)) 1007 ret = QLA_FUNCTION_FAILED; 1008 1009 return ret; 1010 } 1011 1012 /* 1013 * qla2x00_wait_for_hba_online 1014 * Wait till the HBA is online after going through 1015 * <= MAX_RETRIES_OF_ISP_ABORT or 1016 * finally HBA is disabled ie marked offline 1017 * 1018 * Input: 1019 * ha - pointer to host adapter structure 1020 * 1021 * Note: 1022 * Does context switching-Release SPIN_LOCK 1023 * (if any) before calling this routine. 1024 * 1025 * Return: 1026 * Success (Adapter is online) : 0 1027 * Failed (Adapter is offline/disabled) : 1 1028 */ 1029 int 1030 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1031 { 1032 int return_status; 1033 unsigned long wait_online; 1034 struct qla_hw_data *ha = vha->hw; 1035 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1036 1037 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1038 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1039 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1040 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1041 ha->dpc_active) && time_before(jiffies, wait_online)) { 1042 1043 msleep(1000); 1044 } 1045 if (base_vha->flags.online) 1046 return_status = QLA_SUCCESS; 1047 else 1048 return_status = QLA_FUNCTION_FAILED; 1049 1050 return (return_status); 1051 } 1052 1053 static inline int test_fcport_count(scsi_qla_host_t *vha) 1054 { 1055 struct qla_hw_data *ha = vha->hw; 1056 unsigned long flags; 1057 int res; 1058 1059 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1060 ql_dbg(ql_dbg_init, vha, 0xffff, 1061 "tgt %p, fcport_count=%d\n", 1062 vha, vha->fcport_count); 1063 res = (vha->fcport_count == 0); 1064 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1065 1066 return res; 1067 } 1068 1069 /* 1070 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1071 * it has dependency on UNLOADING flag to stop device discovery 1072 */ 1073 static void 1074 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1075 { 1076 qla2x00_mark_all_devices_lost(vha, 0); 1077 1078 wait_event(vha->fcport_waitQ, test_fcport_count(vha)); 1079 } 1080 1081 /* 1082 * qla2x00_wait_for_hba_ready 1083 * Wait till the HBA is ready before doing driver unload 1084 * 1085 * Input: 1086 * ha - pointer to host adapter structure 1087 * 1088 * Note: 1089 * Does context switching-Release SPIN_LOCK 1090 * (if any) before calling this routine. 1091 * 1092 */ 1093 static void 1094 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1095 { 1096 struct qla_hw_data *ha = vha->hw; 1097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1098 1099 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1100 ha->flags.mbox_busy) || 1101 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1102 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1103 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1104 break; 1105 msleep(1000); 1106 } 1107 } 1108 1109 int 1110 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1111 { 1112 int return_status; 1113 unsigned long wait_reset; 1114 struct qla_hw_data *ha = vha->hw; 1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1116 1117 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1121 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1122 1123 msleep(1000); 1124 1125 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1126 ha->flags.chip_reset_done) 1127 break; 1128 } 1129 if (ha->flags.chip_reset_done) 1130 return_status = QLA_SUCCESS; 1131 else 1132 return_status = QLA_FUNCTION_FAILED; 1133 1134 return return_status; 1135 } 1136 1137 static void 1138 sp_get(struct srb *sp) 1139 { 1140 atomic_inc(&sp->ref_count); 1141 } 1142 1143 #define ISP_REG_DISCONNECT 0xffffffffU 1144 /************************************************************************** 1145 * qla2x00_isp_reg_stat 1146 * 1147 * Description: 1148 * Read the host status register of ISP before aborting the command. 1149 * 1150 * Input: 1151 * ha = pointer to host adapter structure. 1152 * 1153 * 1154 * Returns: 1155 * Either true or false. 1156 * 1157 * Note: Return true if there is register disconnect. 1158 **************************************************************************/ 1159 static inline 1160 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1161 { 1162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1163 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1164 1165 if (IS_P3P_TYPE(ha)) 1166 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1167 else 1168 return ((RD_REG_DWORD(®->host_status)) == 1169 ISP_REG_DISCONNECT); 1170 } 1171 1172 /************************************************************************** 1173 * qla2xxx_eh_abort 1174 * 1175 * Description: 1176 * The abort function will abort the specified command. 1177 * 1178 * Input: 1179 * cmd = Linux SCSI command packet to be aborted. 1180 * 1181 * Returns: 1182 * Either SUCCESS or FAILED. 1183 * 1184 * Note: 1185 * Only return FAILED if command not returned by firmware. 1186 **************************************************************************/ 1187 static int 1188 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1189 { 1190 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1191 srb_t *sp; 1192 int ret; 1193 unsigned int id; 1194 uint64_t lun; 1195 unsigned long flags; 1196 int rval, wait = 0; 1197 struct qla_hw_data *ha = vha->hw; 1198 1199 if (qla2x00_isp_reg_stat(ha)) { 1200 ql_log(ql_log_info, vha, 0x8042, 1201 "PCI/Register disconnect, exiting.\n"); 1202 return FAILED; 1203 } 1204 if (!CMD_SP(cmd)) 1205 return SUCCESS; 1206 1207 ret = fc_block_scsi_eh(cmd); 1208 if (ret != 0) 1209 return ret; 1210 ret = SUCCESS; 1211 1212 id = cmd->device->id; 1213 lun = cmd->device->lun; 1214 1215 spin_lock_irqsave(&ha->hardware_lock, flags); 1216 sp = (srb_t *) CMD_SP(cmd); 1217 if (!sp) { 1218 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1219 return SUCCESS; 1220 } 1221 1222 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1223 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1224 vha->host_no, id, lun, sp, cmd, sp->handle); 1225 1226 /* Get a reference to the sp and drop the lock.*/ 1227 sp_get(sp); 1228 1229 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1230 rval = ha->isp_ops->abort_command(sp); 1231 if (rval) { 1232 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1233 ret = SUCCESS; 1234 else 1235 ret = FAILED; 1236 1237 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1238 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1239 } else { 1240 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1241 "Abort command mbx success cmd=%p.\n", cmd); 1242 wait = 1; 1243 } 1244 1245 spin_lock_irqsave(&ha->hardware_lock, flags); 1246 sp->done(sp, 0); 1247 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1248 1249 /* Did the command return during mailbox execution? */ 1250 if (ret == FAILED && !CMD_SP(cmd)) 1251 ret = SUCCESS; 1252 1253 /* Wait for the command to be returned. */ 1254 if (wait) { 1255 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1256 ql_log(ql_log_warn, vha, 0x8006, 1257 "Abort handler timed out cmd=%p.\n", cmd); 1258 ret = FAILED; 1259 } 1260 } 1261 1262 ql_log(ql_log_info, vha, 0x801c, 1263 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1264 vha->host_no, id, lun, wait, ret); 1265 1266 return ret; 1267 } 1268 1269 int 1270 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1271 uint64_t l, enum nexus_wait_type type) 1272 { 1273 int cnt, match, status; 1274 unsigned long flags; 1275 struct qla_hw_data *ha = vha->hw; 1276 struct req_que *req; 1277 srb_t *sp; 1278 struct scsi_cmnd *cmd; 1279 1280 status = QLA_SUCCESS; 1281 1282 spin_lock_irqsave(&ha->hardware_lock, flags); 1283 req = vha->req; 1284 for (cnt = 1; status == QLA_SUCCESS && 1285 cnt < req->num_outstanding_cmds; cnt++) { 1286 sp = req->outstanding_cmds[cnt]; 1287 if (!sp) 1288 continue; 1289 if (sp->type != SRB_SCSI_CMD) 1290 continue; 1291 if (vha->vp_idx != sp->vha->vp_idx) 1292 continue; 1293 match = 0; 1294 cmd = GET_CMD_SP(sp); 1295 switch (type) { 1296 case WAIT_HOST: 1297 match = 1; 1298 break; 1299 case WAIT_TARGET: 1300 match = cmd->device->id == t; 1301 break; 1302 case WAIT_LUN: 1303 match = (cmd->device->id == t && 1304 cmd->device->lun == l); 1305 break; 1306 } 1307 if (!match) 1308 continue; 1309 1310 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1311 status = qla2x00_eh_wait_on_command(cmd); 1312 spin_lock_irqsave(&ha->hardware_lock, flags); 1313 } 1314 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1315 1316 return status; 1317 } 1318 1319 static char *reset_errors[] = { 1320 "HBA not online", 1321 "HBA not ready", 1322 "Task management failed", 1323 "Waiting for command completions", 1324 }; 1325 1326 static int 1327 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1328 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1329 { 1330 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1331 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1332 int err; 1333 1334 if (!fcport) { 1335 return FAILED; 1336 } 1337 1338 err = fc_block_scsi_eh(cmd); 1339 if (err != 0) 1340 return err; 1341 1342 ql_log(ql_log_info, vha, 0x8009, 1343 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1344 cmd->device->id, cmd->device->lun, cmd); 1345 1346 err = 0; 1347 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1348 ql_log(ql_log_warn, vha, 0x800a, 1349 "Wait for hba online failed for cmd=%p.\n", cmd); 1350 goto eh_reset_failed; 1351 } 1352 err = 2; 1353 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1354 != QLA_SUCCESS) { 1355 ql_log(ql_log_warn, vha, 0x800c, 1356 "do_reset failed for cmd=%p.\n", cmd); 1357 goto eh_reset_failed; 1358 } 1359 err = 3; 1360 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1361 cmd->device->lun, type) != QLA_SUCCESS) { 1362 ql_log(ql_log_warn, vha, 0x800d, 1363 "wait for pending cmds failed for cmd=%p.\n", cmd); 1364 goto eh_reset_failed; 1365 } 1366 1367 ql_log(ql_log_info, vha, 0x800e, 1368 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1369 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1370 1371 return SUCCESS; 1372 1373 eh_reset_failed: 1374 ql_log(ql_log_info, vha, 0x800f, 1375 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1376 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1377 cmd); 1378 return FAILED; 1379 } 1380 1381 static int 1382 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1383 { 1384 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1385 struct qla_hw_data *ha = vha->hw; 1386 1387 if (qla2x00_isp_reg_stat(ha)) { 1388 ql_log(ql_log_info, vha, 0x803e, 1389 "PCI/Register disconnect, exiting.\n"); 1390 return FAILED; 1391 } 1392 1393 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1394 ha->isp_ops->lun_reset); 1395 } 1396 1397 static int 1398 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1399 { 1400 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1401 struct qla_hw_data *ha = vha->hw; 1402 1403 if (qla2x00_isp_reg_stat(ha)) { 1404 ql_log(ql_log_info, vha, 0x803f, 1405 "PCI/Register disconnect, exiting.\n"); 1406 return FAILED; 1407 } 1408 1409 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1410 ha->isp_ops->target_reset); 1411 } 1412 1413 /************************************************************************** 1414 * qla2xxx_eh_bus_reset 1415 * 1416 * Description: 1417 * The bus reset function will reset the bus and abort any executing 1418 * commands. 1419 * 1420 * Input: 1421 * cmd = Linux SCSI command packet of the command that cause the 1422 * bus reset. 1423 * 1424 * Returns: 1425 * SUCCESS/FAILURE (defined as macro in scsi.h). 1426 * 1427 **************************************************************************/ 1428 static int 1429 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1430 { 1431 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1432 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1433 int ret = FAILED; 1434 unsigned int id; 1435 uint64_t lun; 1436 struct qla_hw_data *ha = vha->hw; 1437 1438 if (qla2x00_isp_reg_stat(ha)) { 1439 ql_log(ql_log_info, vha, 0x8040, 1440 "PCI/Register disconnect, exiting.\n"); 1441 return FAILED; 1442 } 1443 1444 id = cmd->device->id; 1445 lun = cmd->device->lun; 1446 1447 if (!fcport) { 1448 return ret; 1449 } 1450 1451 ret = fc_block_scsi_eh(cmd); 1452 if (ret != 0) 1453 return ret; 1454 ret = FAILED; 1455 1456 ql_log(ql_log_info, vha, 0x8012, 1457 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1458 1459 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1460 ql_log(ql_log_fatal, vha, 0x8013, 1461 "Wait for hba online failed board disabled.\n"); 1462 goto eh_bus_reset_done; 1463 } 1464 1465 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1466 ret = SUCCESS; 1467 1468 if (ret == FAILED) 1469 goto eh_bus_reset_done; 1470 1471 /* Flush outstanding commands. */ 1472 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1473 QLA_SUCCESS) { 1474 ql_log(ql_log_warn, vha, 0x8014, 1475 "Wait for pending commands failed.\n"); 1476 ret = FAILED; 1477 } 1478 1479 eh_bus_reset_done: 1480 ql_log(ql_log_warn, vha, 0x802b, 1481 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1482 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1483 1484 return ret; 1485 } 1486 1487 /************************************************************************** 1488 * qla2xxx_eh_host_reset 1489 * 1490 * Description: 1491 * The reset function will reset the Adapter. 1492 * 1493 * Input: 1494 * cmd = Linux SCSI command packet of the command that cause the 1495 * adapter reset. 1496 * 1497 * Returns: 1498 * Either SUCCESS or FAILED. 1499 * 1500 * Note: 1501 **************************************************************************/ 1502 static int 1503 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1504 { 1505 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1506 struct qla_hw_data *ha = vha->hw; 1507 int ret = FAILED; 1508 unsigned int id; 1509 uint64_t lun; 1510 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1511 1512 if (qla2x00_isp_reg_stat(ha)) { 1513 ql_log(ql_log_info, vha, 0x8041, 1514 "PCI/Register disconnect, exiting.\n"); 1515 schedule_work(&ha->board_disable); 1516 return SUCCESS; 1517 } 1518 1519 id = cmd->device->id; 1520 lun = cmd->device->lun; 1521 1522 ql_log(ql_log_info, vha, 0x8018, 1523 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1524 1525 /* 1526 * No point in issuing another reset if one is active. Also do not 1527 * attempt a reset if we are updating flash. 1528 */ 1529 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1530 goto eh_host_reset_lock; 1531 1532 if (vha != base_vha) { 1533 if (qla2x00_vp_abort_isp(vha)) 1534 goto eh_host_reset_lock; 1535 } else { 1536 if (IS_P3P_TYPE(vha->hw)) { 1537 if (!qla82xx_fcoe_ctx_reset(vha)) { 1538 /* Ctx reset success */ 1539 ret = SUCCESS; 1540 goto eh_host_reset_lock; 1541 } 1542 /* fall thru if ctx reset failed */ 1543 } 1544 if (ha->wq) 1545 flush_workqueue(ha->wq); 1546 1547 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1548 if (ha->isp_ops->abort_isp(base_vha)) { 1549 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1550 /* failed. schedule dpc to try */ 1551 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1552 1553 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1554 ql_log(ql_log_warn, vha, 0x802a, 1555 "wait for hba online failed.\n"); 1556 goto eh_host_reset_lock; 1557 } 1558 } 1559 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1560 } 1561 1562 /* Waiting for command to be returned to OS.*/ 1563 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1564 QLA_SUCCESS) 1565 ret = SUCCESS; 1566 1567 eh_host_reset_lock: 1568 ql_log(ql_log_info, vha, 0x8017, 1569 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1570 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1571 1572 return ret; 1573 } 1574 1575 /* 1576 * qla2x00_loop_reset 1577 * Issue loop reset. 1578 * 1579 * Input: 1580 * ha = adapter block pointer. 1581 * 1582 * Returns: 1583 * 0 = success 1584 */ 1585 int 1586 qla2x00_loop_reset(scsi_qla_host_t *vha) 1587 { 1588 int ret; 1589 struct fc_port *fcport; 1590 struct qla_hw_data *ha = vha->hw; 1591 1592 if (IS_QLAFX00(ha)) { 1593 return qlafx00_loop_reset(vha); 1594 } 1595 1596 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1597 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1598 if (fcport->port_type != FCT_TARGET) 1599 continue; 1600 1601 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1602 if (ret != QLA_SUCCESS) { 1603 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1604 "Bus Reset failed: Reset=%d " 1605 "d_id=%x.\n", ret, fcport->d_id.b24); 1606 } 1607 } 1608 } 1609 1610 1611 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1612 atomic_set(&vha->loop_state, LOOP_DOWN); 1613 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1614 qla2x00_mark_all_devices_lost(vha, 0); 1615 ret = qla2x00_full_login_lip(vha); 1616 if (ret != QLA_SUCCESS) { 1617 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1618 "full_login_lip=%d.\n", ret); 1619 } 1620 } 1621 1622 if (ha->flags.enable_lip_reset) { 1623 ret = qla2x00_lip_reset(vha); 1624 if (ret != QLA_SUCCESS) 1625 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1626 "lip_reset failed (%d).\n", ret); 1627 } 1628 1629 /* Issue marker command only when we are going to start the I/O */ 1630 vha->marker_needed = 1; 1631 1632 return QLA_SUCCESS; 1633 } 1634 1635 void 1636 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1637 { 1638 int que, cnt; 1639 unsigned long flags; 1640 srb_t *sp; 1641 struct qla_hw_data *ha = vha->hw; 1642 struct req_que *req; 1643 1644 qlt_host_reset_handler(ha); 1645 1646 spin_lock_irqsave(&ha->hardware_lock, flags); 1647 for (que = 0; que < ha->max_req_queues; que++) { 1648 req = ha->req_q_map[que]; 1649 if (!req) 1650 continue; 1651 if (!req->outstanding_cmds) 1652 continue; 1653 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1654 sp = req->outstanding_cmds[cnt]; 1655 if (sp) { 1656 /* Don't abort commands in adapter during EEH 1657 * recovery as it's not accessible/responding. 1658 */ 1659 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy && 1660 (sp->type == SRB_SCSI_CMD)) { 1661 /* Get a reference to the sp and drop the lock. 1662 * The reference ensures this sp->done() call 1663 * - and not the call in qla2xxx_eh_abort() - 1664 * ends the SCSI command (with result 'res'). 1665 */ 1666 sp_get(sp); 1667 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1668 qla2xxx_eh_abort(GET_CMD_SP(sp)); 1669 spin_lock_irqsave(&ha->hardware_lock, flags); 1670 } 1671 req->outstanding_cmds[cnt] = NULL; 1672 sp->done(sp, res); 1673 } 1674 } 1675 } 1676 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1677 } 1678 1679 static int 1680 qla2xxx_slave_alloc(struct scsi_device *sdev) 1681 { 1682 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1683 1684 if (!rport || fc_remote_port_chkready(rport)) 1685 return -ENXIO; 1686 1687 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1688 1689 return 0; 1690 } 1691 1692 static int 1693 qla2xxx_slave_configure(struct scsi_device *sdev) 1694 { 1695 scsi_qla_host_t *vha = shost_priv(sdev->host); 1696 struct req_que *req = vha->req; 1697 1698 if (IS_T10_PI_CAPABLE(vha->hw)) 1699 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1700 1701 scsi_change_queue_depth(sdev, req->max_q_depth); 1702 return 0; 1703 } 1704 1705 static void 1706 qla2xxx_slave_destroy(struct scsi_device *sdev) 1707 { 1708 sdev->hostdata = NULL; 1709 } 1710 1711 /** 1712 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1713 * @ha: HA context 1714 * 1715 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1716 * supported addressing method. 1717 */ 1718 static void 1719 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1720 { 1721 /* Assume a 32bit DMA mask. */ 1722 ha->flags.enable_64bit_addressing = 0; 1723 1724 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1725 /* Any upper-dword bits set? */ 1726 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1727 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1728 /* Ok, a 64bit DMA mask is applicable. */ 1729 ha->flags.enable_64bit_addressing = 1; 1730 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1731 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1732 return; 1733 } 1734 } 1735 1736 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1737 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1738 } 1739 1740 static void 1741 qla2x00_enable_intrs(struct qla_hw_data *ha) 1742 { 1743 unsigned long flags = 0; 1744 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1745 1746 spin_lock_irqsave(&ha->hardware_lock, flags); 1747 ha->interrupts_on = 1; 1748 /* enable risc and host interrupts */ 1749 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1750 RD_REG_WORD(®->ictrl); 1751 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1752 1753 } 1754 1755 static void 1756 qla2x00_disable_intrs(struct qla_hw_data *ha) 1757 { 1758 unsigned long flags = 0; 1759 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1760 1761 spin_lock_irqsave(&ha->hardware_lock, flags); 1762 ha->interrupts_on = 0; 1763 /* disable risc and host interrupts */ 1764 WRT_REG_WORD(®->ictrl, 0); 1765 RD_REG_WORD(®->ictrl); 1766 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1767 } 1768 1769 static void 1770 qla24xx_enable_intrs(struct qla_hw_data *ha) 1771 { 1772 unsigned long flags = 0; 1773 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1774 1775 spin_lock_irqsave(&ha->hardware_lock, flags); 1776 ha->interrupts_on = 1; 1777 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1778 RD_REG_DWORD(®->ictrl); 1779 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1780 } 1781 1782 static void 1783 qla24xx_disable_intrs(struct qla_hw_data *ha) 1784 { 1785 unsigned long flags = 0; 1786 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1787 1788 if (IS_NOPOLLING_TYPE(ha)) 1789 return; 1790 spin_lock_irqsave(&ha->hardware_lock, flags); 1791 ha->interrupts_on = 0; 1792 WRT_REG_DWORD(®->ictrl, 0); 1793 RD_REG_DWORD(®->ictrl); 1794 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1795 } 1796 1797 static int 1798 qla2x00_iospace_config(struct qla_hw_data *ha) 1799 { 1800 resource_size_t pio; 1801 uint16_t msix; 1802 1803 if (pci_request_selected_regions(ha->pdev, ha->bars, 1804 QLA2XXX_DRIVER_NAME)) { 1805 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1806 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1807 pci_name(ha->pdev)); 1808 goto iospace_error_exit; 1809 } 1810 if (!(ha->bars & 1)) 1811 goto skip_pio; 1812 1813 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1814 pio = pci_resource_start(ha->pdev, 0); 1815 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1816 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1817 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1818 "Invalid pci I/O region size (%s).\n", 1819 pci_name(ha->pdev)); 1820 pio = 0; 1821 } 1822 } else { 1823 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1824 "Region #0 no a PIO resource (%s).\n", 1825 pci_name(ha->pdev)); 1826 pio = 0; 1827 } 1828 ha->pio_address = pio; 1829 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1830 "PIO address=%llu.\n", 1831 (unsigned long long)ha->pio_address); 1832 1833 skip_pio: 1834 /* Use MMIO operations for all accesses. */ 1835 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1836 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1837 "Region #1 not an MMIO resource (%s), aborting.\n", 1838 pci_name(ha->pdev)); 1839 goto iospace_error_exit; 1840 } 1841 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1842 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1843 "Invalid PCI mem region size (%s), aborting.\n", 1844 pci_name(ha->pdev)); 1845 goto iospace_error_exit; 1846 } 1847 1848 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1849 if (!ha->iobase) { 1850 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1851 "Cannot remap MMIO (%s), aborting.\n", 1852 pci_name(ha->pdev)); 1853 goto iospace_error_exit; 1854 } 1855 1856 /* Determine queue resources */ 1857 ha->max_req_queues = ha->max_rsp_queues = 1; 1858 ha->msix_count = QLA_BASE_VECTORS; 1859 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1860 goto mqiobase_exit; 1861 1862 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1863 pci_resource_len(ha->pdev, 3)); 1864 if (ha->mqiobase) { 1865 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 1866 "MQIO Base=%p.\n", ha->mqiobase); 1867 /* Read MSIX vector size of the board */ 1868 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 1869 ha->msix_count = msix + 1; 1870 /* Max queues are bounded by available msix vectors */ 1871 /* MB interrupt uses 1 vector */ 1872 ha->max_req_queues = ha->msix_count - 1; 1873 ha->max_rsp_queues = ha->max_req_queues; 1874 /* Queue pairs is the max value minus the base queue pair */ 1875 ha->max_qpairs = ha->max_rsp_queues - 1; 1876 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 1877 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1878 1879 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 1880 "MSI-X vector count: %d.\n", ha->msix_count); 1881 } else 1882 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 1883 "BAR 3 not enabled.\n"); 1884 1885 mqiobase_exit: 1886 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 1887 "MSIX Count: %d.\n", ha->msix_count); 1888 return (0); 1889 1890 iospace_error_exit: 1891 return (-ENOMEM); 1892 } 1893 1894 1895 static int 1896 qla83xx_iospace_config(struct qla_hw_data *ha) 1897 { 1898 uint16_t msix; 1899 1900 if (pci_request_selected_regions(ha->pdev, ha->bars, 1901 QLA2XXX_DRIVER_NAME)) { 1902 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 1903 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1904 pci_name(ha->pdev)); 1905 1906 goto iospace_error_exit; 1907 } 1908 1909 /* Use MMIO operations for all accesses. */ 1910 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 1912 "Invalid pci I/O region size (%s).\n", 1913 pci_name(ha->pdev)); 1914 goto iospace_error_exit; 1915 } 1916 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1917 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 1918 "Invalid PCI mem region size (%s), aborting\n", 1919 pci_name(ha->pdev)); 1920 goto iospace_error_exit; 1921 } 1922 1923 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 1924 if (!ha->iobase) { 1925 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 1926 "Cannot remap MMIO (%s), aborting.\n", 1927 pci_name(ha->pdev)); 1928 goto iospace_error_exit; 1929 } 1930 1931 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 1932 /* 83XX 26XX always use MQ type access for queues 1933 * - mbar 2, a.k.a region 4 */ 1934 ha->max_req_queues = ha->max_rsp_queues = 1; 1935 ha->msix_count = QLA_BASE_VECTORS; 1936 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 1937 pci_resource_len(ha->pdev, 4)); 1938 1939 if (!ha->mqiobase) { 1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 1941 "BAR2/region4 not enabled\n"); 1942 goto mqiobase_exit; 1943 } 1944 1945 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 1946 pci_resource_len(ha->pdev, 2)); 1947 if (ha->msixbase) { 1948 /* Read MSIX vector size of the board */ 1949 pci_read_config_word(ha->pdev, 1950 QLA_83XX_PCI_MSIX_CONTROL, &msix); 1951 ha->msix_count = msix + 1; 1952 /* 1953 * By default, driver uses at least two msix vectors 1954 * (default & rspq) 1955 */ 1956 if (ql2xmqsupport) { 1957 /* MB interrupt uses 1 vector */ 1958 ha->max_req_queues = ha->msix_count - 1; 1959 1960 /* ATIOQ needs 1 vector. That's 1 less QPair */ 1961 if (QLA_TGT_MODE_ENABLED()) 1962 ha->max_req_queues--; 1963 1964 ha->max_rsp_queues = ha->max_req_queues; 1965 1966 /* Queue pairs is the max value minus 1967 * the base queue pair */ 1968 ha->max_qpairs = ha->max_req_queues - 1; 1969 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190, 1970 "Max no of queues pairs: %d.\n", ha->max_qpairs); 1971 } 1972 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 1973 "MSI-X vector count: %d.\n", ha->msix_count); 1974 } else 1975 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 1976 "BAR 1 not enabled.\n"); 1977 1978 mqiobase_exit: 1979 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 1980 "MSIX Count: %d.\n", ha->msix_count); 1981 return 0; 1982 1983 iospace_error_exit: 1984 return -ENOMEM; 1985 } 1986 1987 static struct isp_operations qla2100_isp_ops = { 1988 .pci_config = qla2100_pci_config, 1989 .reset_chip = qla2x00_reset_chip, 1990 .chip_diag = qla2x00_chip_diag, 1991 .config_rings = qla2x00_config_rings, 1992 .reset_adapter = qla2x00_reset_adapter, 1993 .nvram_config = qla2x00_nvram_config, 1994 .update_fw_options = qla2x00_update_fw_options, 1995 .load_risc = qla2x00_load_risc, 1996 .pci_info_str = qla2x00_pci_info_str, 1997 .fw_version_str = qla2x00_fw_version_str, 1998 .intr_handler = qla2100_intr_handler, 1999 .enable_intrs = qla2x00_enable_intrs, 2000 .disable_intrs = qla2x00_disable_intrs, 2001 .abort_command = qla2x00_abort_command, 2002 .target_reset = qla2x00_abort_target, 2003 .lun_reset = qla2x00_lun_reset, 2004 .fabric_login = qla2x00_login_fabric, 2005 .fabric_logout = qla2x00_fabric_logout, 2006 .calc_req_entries = qla2x00_calc_iocbs_32, 2007 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2008 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2009 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2010 .read_nvram = qla2x00_read_nvram_data, 2011 .write_nvram = qla2x00_write_nvram_data, 2012 .fw_dump = qla2100_fw_dump, 2013 .beacon_on = NULL, 2014 .beacon_off = NULL, 2015 .beacon_blink = NULL, 2016 .read_optrom = qla2x00_read_optrom_data, 2017 .write_optrom = qla2x00_write_optrom_data, 2018 .get_flash_version = qla2x00_get_flash_version, 2019 .start_scsi = qla2x00_start_scsi, 2020 .start_scsi_mq = NULL, 2021 .abort_isp = qla2x00_abort_isp, 2022 .iospace_config = qla2x00_iospace_config, 2023 .initialize_adapter = qla2x00_initialize_adapter, 2024 }; 2025 2026 static struct isp_operations qla2300_isp_ops = { 2027 .pci_config = qla2300_pci_config, 2028 .reset_chip = qla2x00_reset_chip, 2029 .chip_diag = qla2x00_chip_diag, 2030 .config_rings = qla2x00_config_rings, 2031 .reset_adapter = qla2x00_reset_adapter, 2032 .nvram_config = qla2x00_nvram_config, 2033 .update_fw_options = qla2x00_update_fw_options, 2034 .load_risc = qla2x00_load_risc, 2035 .pci_info_str = qla2x00_pci_info_str, 2036 .fw_version_str = qla2x00_fw_version_str, 2037 .intr_handler = qla2300_intr_handler, 2038 .enable_intrs = qla2x00_enable_intrs, 2039 .disable_intrs = qla2x00_disable_intrs, 2040 .abort_command = qla2x00_abort_command, 2041 .target_reset = qla2x00_abort_target, 2042 .lun_reset = qla2x00_lun_reset, 2043 .fabric_login = qla2x00_login_fabric, 2044 .fabric_logout = qla2x00_fabric_logout, 2045 .calc_req_entries = qla2x00_calc_iocbs_32, 2046 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2047 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2048 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2049 .read_nvram = qla2x00_read_nvram_data, 2050 .write_nvram = qla2x00_write_nvram_data, 2051 .fw_dump = qla2300_fw_dump, 2052 .beacon_on = qla2x00_beacon_on, 2053 .beacon_off = qla2x00_beacon_off, 2054 .beacon_blink = qla2x00_beacon_blink, 2055 .read_optrom = qla2x00_read_optrom_data, 2056 .write_optrom = qla2x00_write_optrom_data, 2057 .get_flash_version = qla2x00_get_flash_version, 2058 .start_scsi = qla2x00_start_scsi, 2059 .start_scsi_mq = NULL, 2060 .abort_isp = qla2x00_abort_isp, 2061 .iospace_config = qla2x00_iospace_config, 2062 .initialize_adapter = qla2x00_initialize_adapter, 2063 }; 2064 2065 static struct isp_operations qla24xx_isp_ops = { 2066 .pci_config = qla24xx_pci_config, 2067 .reset_chip = qla24xx_reset_chip, 2068 .chip_diag = qla24xx_chip_diag, 2069 .config_rings = qla24xx_config_rings, 2070 .reset_adapter = qla24xx_reset_adapter, 2071 .nvram_config = qla24xx_nvram_config, 2072 .update_fw_options = qla24xx_update_fw_options, 2073 .load_risc = qla24xx_load_risc, 2074 .pci_info_str = qla24xx_pci_info_str, 2075 .fw_version_str = qla24xx_fw_version_str, 2076 .intr_handler = qla24xx_intr_handler, 2077 .enable_intrs = qla24xx_enable_intrs, 2078 .disable_intrs = qla24xx_disable_intrs, 2079 .abort_command = qla24xx_abort_command, 2080 .target_reset = qla24xx_abort_target, 2081 .lun_reset = qla24xx_lun_reset, 2082 .fabric_login = qla24xx_login_fabric, 2083 .fabric_logout = qla24xx_fabric_logout, 2084 .calc_req_entries = NULL, 2085 .build_iocbs = NULL, 2086 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2087 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2088 .read_nvram = qla24xx_read_nvram_data, 2089 .write_nvram = qla24xx_write_nvram_data, 2090 .fw_dump = qla24xx_fw_dump, 2091 .beacon_on = qla24xx_beacon_on, 2092 .beacon_off = qla24xx_beacon_off, 2093 .beacon_blink = qla24xx_beacon_blink, 2094 .read_optrom = qla24xx_read_optrom_data, 2095 .write_optrom = qla24xx_write_optrom_data, 2096 .get_flash_version = qla24xx_get_flash_version, 2097 .start_scsi = qla24xx_start_scsi, 2098 .start_scsi_mq = NULL, 2099 .abort_isp = qla2x00_abort_isp, 2100 .iospace_config = qla2x00_iospace_config, 2101 .initialize_adapter = qla2x00_initialize_adapter, 2102 }; 2103 2104 static struct isp_operations qla25xx_isp_ops = { 2105 .pci_config = qla25xx_pci_config, 2106 .reset_chip = qla24xx_reset_chip, 2107 .chip_diag = qla24xx_chip_diag, 2108 .config_rings = qla24xx_config_rings, 2109 .reset_adapter = qla24xx_reset_adapter, 2110 .nvram_config = qla24xx_nvram_config, 2111 .update_fw_options = qla24xx_update_fw_options, 2112 .load_risc = qla24xx_load_risc, 2113 .pci_info_str = qla24xx_pci_info_str, 2114 .fw_version_str = qla24xx_fw_version_str, 2115 .intr_handler = qla24xx_intr_handler, 2116 .enable_intrs = qla24xx_enable_intrs, 2117 .disable_intrs = qla24xx_disable_intrs, 2118 .abort_command = qla24xx_abort_command, 2119 .target_reset = qla24xx_abort_target, 2120 .lun_reset = qla24xx_lun_reset, 2121 .fabric_login = qla24xx_login_fabric, 2122 .fabric_logout = qla24xx_fabric_logout, 2123 .calc_req_entries = NULL, 2124 .build_iocbs = NULL, 2125 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2126 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2127 .read_nvram = qla25xx_read_nvram_data, 2128 .write_nvram = qla25xx_write_nvram_data, 2129 .fw_dump = qla25xx_fw_dump, 2130 .beacon_on = qla24xx_beacon_on, 2131 .beacon_off = qla24xx_beacon_off, 2132 .beacon_blink = qla24xx_beacon_blink, 2133 .read_optrom = qla25xx_read_optrom_data, 2134 .write_optrom = qla24xx_write_optrom_data, 2135 .get_flash_version = qla24xx_get_flash_version, 2136 .start_scsi = qla24xx_dif_start_scsi, 2137 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2138 .abort_isp = qla2x00_abort_isp, 2139 .iospace_config = qla2x00_iospace_config, 2140 .initialize_adapter = qla2x00_initialize_adapter, 2141 }; 2142 2143 static struct isp_operations qla81xx_isp_ops = { 2144 .pci_config = qla25xx_pci_config, 2145 .reset_chip = qla24xx_reset_chip, 2146 .chip_diag = qla24xx_chip_diag, 2147 .config_rings = qla24xx_config_rings, 2148 .reset_adapter = qla24xx_reset_adapter, 2149 .nvram_config = qla81xx_nvram_config, 2150 .update_fw_options = qla81xx_update_fw_options, 2151 .load_risc = qla81xx_load_risc, 2152 .pci_info_str = qla24xx_pci_info_str, 2153 .fw_version_str = qla24xx_fw_version_str, 2154 .intr_handler = qla24xx_intr_handler, 2155 .enable_intrs = qla24xx_enable_intrs, 2156 .disable_intrs = qla24xx_disable_intrs, 2157 .abort_command = qla24xx_abort_command, 2158 .target_reset = qla24xx_abort_target, 2159 .lun_reset = qla24xx_lun_reset, 2160 .fabric_login = qla24xx_login_fabric, 2161 .fabric_logout = qla24xx_fabric_logout, 2162 .calc_req_entries = NULL, 2163 .build_iocbs = NULL, 2164 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2165 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2166 .read_nvram = NULL, 2167 .write_nvram = NULL, 2168 .fw_dump = qla81xx_fw_dump, 2169 .beacon_on = qla24xx_beacon_on, 2170 .beacon_off = qla24xx_beacon_off, 2171 .beacon_blink = qla83xx_beacon_blink, 2172 .read_optrom = qla25xx_read_optrom_data, 2173 .write_optrom = qla24xx_write_optrom_data, 2174 .get_flash_version = qla24xx_get_flash_version, 2175 .start_scsi = qla24xx_dif_start_scsi, 2176 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2177 .abort_isp = qla2x00_abort_isp, 2178 .iospace_config = qla2x00_iospace_config, 2179 .initialize_adapter = qla2x00_initialize_adapter, 2180 }; 2181 2182 static struct isp_operations qla82xx_isp_ops = { 2183 .pci_config = qla82xx_pci_config, 2184 .reset_chip = qla82xx_reset_chip, 2185 .chip_diag = qla24xx_chip_diag, 2186 .config_rings = qla82xx_config_rings, 2187 .reset_adapter = qla24xx_reset_adapter, 2188 .nvram_config = qla81xx_nvram_config, 2189 .update_fw_options = qla24xx_update_fw_options, 2190 .load_risc = qla82xx_load_risc, 2191 .pci_info_str = qla24xx_pci_info_str, 2192 .fw_version_str = qla24xx_fw_version_str, 2193 .intr_handler = qla82xx_intr_handler, 2194 .enable_intrs = qla82xx_enable_intrs, 2195 .disable_intrs = qla82xx_disable_intrs, 2196 .abort_command = qla24xx_abort_command, 2197 .target_reset = qla24xx_abort_target, 2198 .lun_reset = qla24xx_lun_reset, 2199 .fabric_login = qla24xx_login_fabric, 2200 .fabric_logout = qla24xx_fabric_logout, 2201 .calc_req_entries = NULL, 2202 .build_iocbs = NULL, 2203 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2204 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2205 .read_nvram = qla24xx_read_nvram_data, 2206 .write_nvram = qla24xx_write_nvram_data, 2207 .fw_dump = qla82xx_fw_dump, 2208 .beacon_on = qla82xx_beacon_on, 2209 .beacon_off = qla82xx_beacon_off, 2210 .beacon_blink = NULL, 2211 .read_optrom = qla82xx_read_optrom_data, 2212 .write_optrom = qla82xx_write_optrom_data, 2213 .get_flash_version = qla82xx_get_flash_version, 2214 .start_scsi = qla82xx_start_scsi, 2215 .start_scsi_mq = NULL, 2216 .abort_isp = qla82xx_abort_isp, 2217 .iospace_config = qla82xx_iospace_config, 2218 .initialize_adapter = qla2x00_initialize_adapter, 2219 }; 2220 2221 static struct isp_operations qla8044_isp_ops = { 2222 .pci_config = qla82xx_pci_config, 2223 .reset_chip = qla82xx_reset_chip, 2224 .chip_diag = qla24xx_chip_diag, 2225 .config_rings = qla82xx_config_rings, 2226 .reset_adapter = qla24xx_reset_adapter, 2227 .nvram_config = qla81xx_nvram_config, 2228 .update_fw_options = qla24xx_update_fw_options, 2229 .load_risc = qla82xx_load_risc, 2230 .pci_info_str = qla24xx_pci_info_str, 2231 .fw_version_str = qla24xx_fw_version_str, 2232 .intr_handler = qla8044_intr_handler, 2233 .enable_intrs = qla82xx_enable_intrs, 2234 .disable_intrs = qla82xx_disable_intrs, 2235 .abort_command = qla24xx_abort_command, 2236 .target_reset = qla24xx_abort_target, 2237 .lun_reset = qla24xx_lun_reset, 2238 .fabric_login = qla24xx_login_fabric, 2239 .fabric_logout = qla24xx_fabric_logout, 2240 .calc_req_entries = NULL, 2241 .build_iocbs = NULL, 2242 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2243 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2244 .read_nvram = NULL, 2245 .write_nvram = NULL, 2246 .fw_dump = qla8044_fw_dump, 2247 .beacon_on = qla82xx_beacon_on, 2248 .beacon_off = qla82xx_beacon_off, 2249 .beacon_blink = NULL, 2250 .read_optrom = qla8044_read_optrom_data, 2251 .write_optrom = qla8044_write_optrom_data, 2252 .get_flash_version = qla82xx_get_flash_version, 2253 .start_scsi = qla82xx_start_scsi, 2254 .start_scsi_mq = NULL, 2255 .abort_isp = qla8044_abort_isp, 2256 .iospace_config = qla82xx_iospace_config, 2257 .initialize_adapter = qla2x00_initialize_adapter, 2258 }; 2259 2260 static struct isp_operations qla83xx_isp_ops = { 2261 .pci_config = qla25xx_pci_config, 2262 .reset_chip = qla24xx_reset_chip, 2263 .chip_diag = qla24xx_chip_diag, 2264 .config_rings = qla24xx_config_rings, 2265 .reset_adapter = qla24xx_reset_adapter, 2266 .nvram_config = qla81xx_nvram_config, 2267 .update_fw_options = qla81xx_update_fw_options, 2268 .load_risc = qla81xx_load_risc, 2269 .pci_info_str = qla24xx_pci_info_str, 2270 .fw_version_str = qla24xx_fw_version_str, 2271 .intr_handler = qla24xx_intr_handler, 2272 .enable_intrs = qla24xx_enable_intrs, 2273 .disable_intrs = qla24xx_disable_intrs, 2274 .abort_command = qla24xx_abort_command, 2275 .target_reset = qla24xx_abort_target, 2276 .lun_reset = qla24xx_lun_reset, 2277 .fabric_login = qla24xx_login_fabric, 2278 .fabric_logout = qla24xx_fabric_logout, 2279 .calc_req_entries = NULL, 2280 .build_iocbs = NULL, 2281 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2282 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2283 .read_nvram = NULL, 2284 .write_nvram = NULL, 2285 .fw_dump = qla83xx_fw_dump, 2286 .beacon_on = qla24xx_beacon_on, 2287 .beacon_off = qla24xx_beacon_off, 2288 .beacon_blink = qla83xx_beacon_blink, 2289 .read_optrom = qla25xx_read_optrom_data, 2290 .write_optrom = qla24xx_write_optrom_data, 2291 .get_flash_version = qla24xx_get_flash_version, 2292 .start_scsi = qla24xx_dif_start_scsi, 2293 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2294 .abort_isp = qla2x00_abort_isp, 2295 .iospace_config = qla83xx_iospace_config, 2296 .initialize_adapter = qla2x00_initialize_adapter, 2297 }; 2298 2299 static struct isp_operations qlafx00_isp_ops = { 2300 .pci_config = qlafx00_pci_config, 2301 .reset_chip = qlafx00_soft_reset, 2302 .chip_diag = qlafx00_chip_diag, 2303 .config_rings = qlafx00_config_rings, 2304 .reset_adapter = qlafx00_soft_reset, 2305 .nvram_config = NULL, 2306 .update_fw_options = NULL, 2307 .load_risc = NULL, 2308 .pci_info_str = qlafx00_pci_info_str, 2309 .fw_version_str = qlafx00_fw_version_str, 2310 .intr_handler = qlafx00_intr_handler, 2311 .enable_intrs = qlafx00_enable_intrs, 2312 .disable_intrs = qlafx00_disable_intrs, 2313 .abort_command = qla24xx_async_abort_command, 2314 .target_reset = qlafx00_abort_target, 2315 .lun_reset = qlafx00_lun_reset, 2316 .fabric_login = NULL, 2317 .fabric_logout = NULL, 2318 .calc_req_entries = NULL, 2319 .build_iocbs = NULL, 2320 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2321 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2322 .read_nvram = qla24xx_read_nvram_data, 2323 .write_nvram = qla24xx_write_nvram_data, 2324 .fw_dump = NULL, 2325 .beacon_on = qla24xx_beacon_on, 2326 .beacon_off = qla24xx_beacon_off, 2327 .beacon_blink = NULL, 2328 .read_optrom = qla24xx_read_optrom_data, 2329 .write_optrom = qla24xx_write_optrom_data, 2330 .get_flash_version = qla24xx_get_flash_version, 2331 .start_scsi = qlafx00_start_scsi, 2332 .start_scsi_mq = NULL, 2333 .abort_isp = qlafx00_abort_isp, 2334 .iospace_config = qlafx00_iospace_config, 2335 .initialize_adapter = qlafx00_initialize_adapter, 2336 }; 2337 2338 static struct isp_operations qla27xx_isp_ops = { 2339 .pci_config = qla25xx_pci_config, 2340 .reset_chip = qla24xx_reset_chip, 2341 .chip_diag = qla24xx_chip_diag, 2342 .config_rings = qla24xx_config_rings, 2343 .reset_adapter = qla24xx_reset_adapter, 2344 .nvram_config = qla81xx_nvram_config, 2345 .update_fw_options = qla81xx_update_fw_options, 2346 .load_risc = qla81xx_load_risc, 2347 .pci_info_str = qla24xx_pci_info_str, 2348 .fw_version_str = qla24xx_fw_version_str, 2349 .intr_handler = qla24xx_intr_handler, 2350 .enable_intrs = qla24xx_enable_intrs, 2351 .disable_intrs = qla24xx_disable_intrs, 2352 .abort_command = qla24xx_abort_command, 2353 .target_reset = qla24xx_abort_target, 2354 .lun_reset = qla24xx_lun_reset, 2355 .fabric_login = qla24xx_login_fabric, 2356 .fabric_logout = qla24xx_fabric_logout, 2357 .calc_req_entries = NULL, 2358 .build_iocbs = NULL, 2359 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2360 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2361 .read_nvram = NULL, 2362 .write_nvram = NULL, 2363 .fw_dump = qla27xx_fwdump, 2364 .beacon_on = qla24xx_beacon_on, 2365 .beacon_off = qla24xx_beacon_off, 2366 .beacon_blink = qla83xx_beacon_blink, 2367 .read_optrom = qla25xx_read_optrom_data, 2368 .write_optrom = qla24xx_write_optrom_data, 2369 .get_flash_version = qla24xx_get_flash_version, 2370 .start_scsi = qla24xx_dif_start_scsi, 2371 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2372 .abort_isp = qla2x00_abort_isp, 2373 .iospace_config = qla83xx_iospace_config, 2374 .initialize_adapter = qla2x00_initialize_adapter, 2375 }; 2376 2377 static inline void 2378 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2379 { 2380 ha->device_type = DT_EXTENDED_IDS; 2381 switch (ha->pdev->device) { 2382 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2383 ha->isp_type |= DT_ISP2100; 2384 ha->device_type &= ~DT_EXTENDED_IDS; 2385 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2386 break; 2387 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2388 ha->isp_type |= DT_ISP2200; 2389 ha->device_type &= ~DT_EXTENDED_IDS; 2390 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2391 break; 2392 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2393 ha->isp_type |= DT_ISP2300; 2394 ha->device_type |= DT_ZIO_SUPPORTED; 2395 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2396 break; 2397 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2398 ha->isp_type |= DT_ISP2312; 2399 ha->device_type |= DT_ZIO_SUPPORTED; 2400 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2401 break; 2402 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2403 ha->isp_type |= DT_ISP2322; 2404 ha->device_type |= DT_ZIO_SUPPORTED; 2405 if (ha->pdev->subsystem_vendor == 0x1028 && 2406 ha->pdev->subsystem_device == 0x0170) 2407 ha->device_type |= DT_OEM_001; 2408 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2409 break; 2410 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2411 ha->isp_type |= DT_ISP6312; 2412 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2413 break; 2414 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2415 ha->isp_type |= DT_ISP6322; 2416 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2417 break; 2418 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2419 ha->isp_type |= DT_ISP2422; 2420 ha->device_type |= DT_ZIO_SUPPORTED; 2421 ha->device_type |= DT_FWI2; 2422 ha->device_type |= DT_IIDMA; 2423 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2424 break; 2425 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2426 ha->isp_type |= DT_ISP2432; 2427 ha->device_type |= DT_ZIO_SUPPORTED; 2428 ha->device_type |= DT_FWI2; 2429 ha->device_type |= DT_IIDMA; 2430 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2431 break; 2432 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2433 ha->isp_type |= DT_ISP8432; 2434 ha->device_type |= DT_ZIO_SUPPORTED; 2435 ha->device_type |= DT_FWI2; 2436 ha->device_type |= DT_IIDMA; 2437 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2438 break; 2439 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2440 ha->isp_type |= DT_ISP5422; 2441 ha->device_type |= DT_FWI2; 2442 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2443 break; 2444 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2445 ha->isp_type |= DT_ISP5432; 2446 ha->device_type |= DT_FWI2; 2447 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2448 break; 2449 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2450 ha->isp_type |= DT_ISP2532; 2451 ha->device_type |= DT_ZIO_SUPPORTED; 2452 ha->device_type |= DT_FWI2; 2453 ha->device_type |= DT_IIDMA; 2454 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2455 break; 2456 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2457 ha->isp_type |= DT_ISP8001; 2458 ha->device_type |= DT_ZIO_SUPPORTED; 2459 ha->device_type |= DT_FWI2; 2460 ha->device_type |= DT_IIDMA; 2461 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2462 break; 2463 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2464 ha->isp_type |= DT_ISP8021; 2465 ha->device_type |= DT_ZIO_SUPPORTED; 2466 ha->device_type |= DT_FWI2; 2467 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2468 /* Initialize 82XX ISP flags */ 2469 qla82xx_init_flags(ha); 2470 break; 2471 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2472 ha->isp_type |= DT_ISP8044; 2473 ha->device_type |= DT_ZIO_SUPPORTED; 2474 ha->device_type |= DT_FWI2; 2475 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2476 /* Initialize 82XX ISP flags */ 2477 qla82xx_init_flags(ha); 2478 break; 2479 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2480 ha->isp_type |= DT_ISP2031; 2481 ha->device_type |= DT_ZIO_SUPPORTED; 2482 ha->device_type |= DT_FWI2; 2483 ha->device_type |= DT_IIDMA; 2484 ha->device_type |= DT_T10_PI; 2485 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2486 break; 2487 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2488 ha->isp_type |= DT_ISP8031; 2489 ha->device_type |= DT_ZIO_SUPPORTED; 2490 ha->device_type |= DT_FWI2; 2491 ha->device_type |= DT_IIDMA; 2492 ha->device_type |= DT_T10_PI; 2493 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2494 break; 2495 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2496 ha->isp_type |= DT_ISPFX00; 2497 break; 2498 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2499 ha->isp_type |= DT_ISP2071; 2500 ha->device_type |= DT_ZIO_SUPPORTED; 2501 ha->device_type |= DT_FWI2; 2502 ha->device_type |= DT_IIDMA; 2503 ha->device_type |= DT_T10_PI; 2504 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2505 break; 2506 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2507 ha->isp_type |= DT_ISP2271; 2508 ha->device_type |= DT_ZIO_SUPPORTED; 2509 ha->device_type |= DT_FWI2; 2510 ha->device_type |= DT_IIDMA; 2511 ha->device_type |= DT_T10_PI; 2512 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2513 break; 2514 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2515 ha->isp_type |= DT_ISP2261; 2516 ha->device_type |= DT_ZIO_SUPPORTED; 2517 ha->device_type |= DT_FWI2; 2518 ha->device_type |= DT_IIDMA; 2519 ha->device_type |= DT_T10_PI; 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2521 break; 2522 } 2523 2524 if (IS_QLA82XX(ha)) 2525 ha->port_no = ha->portnum & 1; 2526 else { 2527 /* Get adapter physical port no from interrupt pin register. */ 2528 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2529 if (IS_QLA27XX(ha)) 2530 ha->port_no--; 2531 else 2532 ha->port_no = !(ha->port_no & 1); 2533 } 2534 2535 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2536 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2537 ha->device_type, ha->port_no, ha->fw_srisc_address); 2538 } 2539 2540 static void 2541 qla2xxx_scan_start(struct Scsi_Host *shost) 2542 { 2543 scsi_qla_host_t *vha = shost_priv(shost); 2544 2545 if (vha->hw->flags.running_gold_fw) 2546 return; 2547 2548 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2549 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2550 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2551 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2552 } 2553 2554 static int 2555 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2556 { 2557 scsi_qla_host_t *vha = shost_priv(shost); 2558 2559 if (test_bit(UNLOADING, &vha->dpc_flags)) 2560 return 1; 2561 if (!vha->host) 2562 return 1; 2563 if (time > vha->hw->loop_reset_delay * HZ) 2564 return 1; 2565 2566 return atomic_read(&vha->loop_state) == LOOP_READY; 2567 } 2568 2569 static void qla2x00_iocb_work_fn(struct work_struct *work) 2570 { 2571 struct scsi_qla_host *vha = container_of(work, 2572 struct scsi_qla_host, iocb_work); 2573 int cnt = 0; 2574 2575 while (!list_empty(&vha->work_list)) { 2576 qla2x00_do_work(vha); 2577 cnt++; 2578 if (cnt > 10) 2579 break; 2580 } 2581 } 2582 2583 /* 2584 * PCI driver interface 2585 */ 2586 static int 2587 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2588 { 2589 int ret = -ENODEV; 2590 struct Scsi_Host *host; 2591 scsi_qla_host_t *base_vha = NULL; 2592 struct qla_hw_data *ha; 2593 char pci_info[30]; 2594 char fw_str[30], wq_name[30]; 2595 struct scsi_host_template *sht; 2596 int bars, mem_only = 0; 2597 uint16_t req_length = 0, rsp_length = 0; 2598 struct req_que *req = NULL; 2599 struct rsp_que *rsp = NULL; 2600 int i; 2601 2602 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2603 sht = &qla2xxx_driver_template; 2604 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2605 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2606 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2607 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2608 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2609 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2610 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2611 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2612 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2613 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2614 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2615 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2616 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2617 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2618 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2619 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2620 mem_only = 1; 2621 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2622 "Mem only adapter.\n"); 2623 } 2624 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2625 "Bars=%d.\n", bars); 2626 2627 if (mem_only) { 2628 if (pci_enable_device_mem(pdev)) 2629 goto probe_out; 2630 } else { 2631 if (pci_enable_device(pdev)) 2632 goto probe_out; 2633 } 2634 2635 /* This may fail but that's ok */ 2636 pci_enable_pcie_error_reporting(pdev); 2637 2638 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2639 if (!ha) { 2640 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2641 "Unable to allocate memory for ha.\n"); 2642 goto probe_out; 2643 } 2644 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2645 "Memory allocated for ha=%p.\n", ha); 2646 ha->pdev = pdev; 2647 ha->tgt.enable_class_2 = ql2xenableclass2; 2648 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2649 spin_lock_init(&ha->tgt.q_full_lock); 2650 spin_lock_init(&ha->tgt.sess_lock); 2651 spin_lock_init(&ha->tgt.atio_lock); 2652 2653 2654 /* Clear our data area */ 2655 ha->bars = bars; 2656 ha->mem_only = mem_only; 2657 spin_lock_init(&ha->hardware_lock); 2658 spin_lock_init(&ha->vport_slock); 2659 mutex_init(&ha->selflogin_lock); 2660 mutex_init(&ha->optrom_mutex); 2661 2662 /* Set ISP-type information. */ 2663 qla2x00_set_isp_flags(ha); 2664 2665 /* Set EEH reset type to fundamental if required by hba */ 2666 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2667 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2668 pdev->needs_freset = 1; 2669 2670 ha->prev_topology = 0; 2671 ha->init_cb_size = sizeof(init_cb_t); 2672 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2673 ha->optrom_size = OPTROM_SIZE_2300; 2674 2675 /* Assign ISP specific operations. */ 2676 if (IS_QLA2100(ha)) { 2677 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2678 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2679 req_length = REQUEST_ENTRY_CNT_2100; 2680 rsp_length = RESPONSE_ENTRY_CNT_2100; 2681 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2682 ha->gid_list_info_size = 4; 2683 ha->flash_conf_off = ~0; 2684 ha->flash_data_off = ~0; 2685 ha->nvram_conf_off = ~0; 2686 ha->nvram_data_off = ~0; 2687 ha->isp_ops = &qla2100_isp_ops; 2688 } else if (IS_QLA2200(ha)) { 2689 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2690 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2691 req_length = REQUEST_ENTRY_CNT_2200; 2692 rsp_length = RESPONSE_ENTRY_CNT_2100; 2693 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2694 ha->gid_list_info_size = 4; 2695 ha->flash_conf_off = ~0; 2696 ha->flash_data_off = ~0; 2697 ha->nvram_conf_off = ~0; 2698 ha->nvram_data_off = ~0; 2699 ha->isp_ops = &qla2100_isp_ops; 2700 } else if (IS_QLA23XX(ha)) { 2701 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2702 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2703 req_length = REQUEST_ENTRY_CNT_2200; 2704 rsp_length = RESPONSE_ENTRY_CNT_2300; 2705 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2706 ha->gid_list_info_size = 6; 2707 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2708 ha->optrom_size = OPTROM_SIZE_2322; 2709 ha->flash_conf_off = ~0; 2710 ha->flash_data_off = ~0; 2711 ha->nvram_conf_off = ~0; 2712 ha->nvram_data_off = ~0; 2713 ha->isp_ops = &qla2300_isp_ops; 2714 } else if (IS_QLA24XX_TYPE(ha)) { 2715 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2716 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2717 req_length = REQUEST_ENTRY_CNT_24XX; 2718 rsp_length = RESPONSE_ENTRY_CNT_2300; 2719 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2720 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2721 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2722 ha->gid_list_info_size = 8; 2723 ha->optrom_size = OPTROM_SIZE_24XX; 2724 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2725 ha->isp_ops = &qla24xx_isp_ops; 2726 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2727 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2728 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2729 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2730 } else if (IS_QLA25XX(ha)) { 2731 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2732 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2733 req_length = REQUEST_ENTRY_CNT_24XX; 2734 rsp_length = RESPONSE_ENTRY_CNT_2300; 2735 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2736 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2737 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2738 ha->gid_list_info_size = 8; 2739 ha->optrom_size = OPTROM_SIZE_25XX; 2740 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2741 ha->isp_ops = &qla25xx_isp_ops; 2742 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2743 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2744 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2745 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2746 } else if (IS_QLA81XX(ha)) { 2747 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2748 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2749 req_length = REQUEST_ENTRY_CNT_24XX; 2750 rsp_length = RESPONSE_ENTRY_CNT_2300; 2751 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2752 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2753 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2754 ha->gid_list_info_size = 8; 2755 ha->optrom_size = OPTROM_SIZE_81XX; 2756 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2757 ha->isp_ops = &qla81xx_isp_ops; 2758 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2759 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2760 ha->nvram_conf_off = ~0; 2761 ha->nvram_data_off = ~0; 2762 } else if (IS_QLA82XX(ha)) { 2763 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2764 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2765 req_length = REQUEST_ENTRY_CNT_82XX; 2766 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2767 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2768 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2769 ha->gid_list_info_size = 8; 2770 ha->optrom_size = OPTROM_SIZE_82XX; 2771 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2772 ha->isp_ops = &qla82xx_isp_ops; 2773 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2774 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2775 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2776 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2777 } else if (IS_QLA8044(ha)) { 2778 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2779 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2780 req_length = REQUEST_ENTRY_CNT_82XX; 2781 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2782 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2783 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2784 ha->gid_list_info_size = 8; 2785 ha->optrom_size = OPTROM_SIZE_83XX; 2786 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2787 ha->isp_ops = &qla8044_isp_ops; 2788 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2789 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2790 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2791 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2792 } else if (IS_QLA83XX(ha)) { 2793 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2794 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2795 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2796 req_length = REQUEST_ENTRY_CNT_83XX; 2797 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2798 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2799 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2800 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2801 ha->gid_list_info_size = 8; 2802 ha->optrom_size = OPTROM_SIZE_83XX; 2803 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2804 ha->isp_ops = &qla83xx_isp_ops; 2805 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2806 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2807 ha->nvram_conf_off = ~0; 2808 ha->nvram_data_off = ~0; 2809 } else if (IS_QLAFX00(ha)) { 2810 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2811 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2812 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2813 req_length = REQUEST_ENTRY_CNT_FX00; 2814 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2815 ha->isp_ops = &qlafx00_isp_ops; 2816 ha->port_down_retry_count = 30; /* default value */ 2817 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2818 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2819 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2820 ha->mr.fw_hbt_en = 1; 2821 ha->mr.host_info_resend = false; 2822 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2823 } else if (IS_QLA27XX(ha)) { 2824 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2825 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2826 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2827 req_length = REQUEST_ENTRY_CNT_83XX; 2828 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2829 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2830 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2831 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2832 ha->gid_list_info_size = 8; 2833 ha->optrom_size = OPTROM_SIZE_83XX; 2834 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2835 ha->isp_ops = &qla27xx_isp_ops; 2836 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2837 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2838 ha->nvram_conf_off = ~0; 2839 ha->nvram_data_off = ~0; 2840 } 2841 2842 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2843 "mbx_count=%d, req_length=%d, " 2844 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2845 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2846 "max_fibre_devices=%d.\n", 2847 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2848 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2849 ha->nvram_npiv_size, ha->max_fibre_devices); 2850 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2851 "isp_ops=%p, flash_conf_off=%d, " 2852 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2853 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2854 ha->nvram_conf_off, ha->nvram_data_off); 2855 2856 /* Configure PCI I/O space */ 2857 ret = ha->isp_ops->iospace_config(ha); 2858 if (ret) 2859 goto iospace_config_failed; 2860 2861 ql_log_pci(ql_log_info, pdev, 0x001d, 2862 "Found an ISP%04X irq %d iobase 0x%p.\n", 2863 pdev->device, pdev->irq, ha->iobase); 2864 mutex_init(&ha->vport_lock); 2865 mutex_init(&ha->mq_lock); 2866 init_completion(&ha->mbx_cmd_comp); 2867 complete(&ha->mbx_cmd_comp); 2868 init_completion(&ha->mbx_intr_comp); 2869 init_completion(&ha->dcbx_comp); 2870 init_completion(&ha->lb_portup_comp); 2871 2872 set_bit(0, (unsigned long *) ha->vp_idx_map); 2873 2874 qla2x00_config_dma_addressing(ha); 2875 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 2876 "64 Bit addressing is %s.\n", 2877 ha->flags.enable_64bit_addressing ? "enable" : 2878 "disable"); 2879 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 2880 if (ret) { 2881 ql_log_pci(ql_log_fatal, pdev, 0x0031, 2882 "Failed to allocate memory for adapter, aborting.\n"); 2883 2884 goto probe_hw_failed; 2885 } 2886 2887 req->max_q_depth = MAX_Q_DEPTH; 2888 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 2889 req->max_q_depth = ql2xmaxqdepth; 2890 2891 2892 base_vha = qla2x00_create_host(sht, ha); 2893 if (!base_vha) { 2894 ret = -ENOMEM; 2895 qla2x00_mem_free(ha); 2896 qla2x00_free_req_que(ha, req); 2897 qla2x00_free_rsp_que(ha, rsp); 2898 goto probe_hw_failed; 2899 } 2900 2901 pci_set_drvdata(pdev, base_vha); 2902 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 2903 2904 host = base_vha->host; 2905 base_vha->req = req; 2906 if (IS_QLA2XXX_MIDTYPE(ha)) 2907 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; 2908 else 2909 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 2910 base_vha->vp_idx; 2911 2912 /* Setup fcport template structure. */ 2913 ha->mr.fcport.vha = base_vha; 2914 ha->mr.fcport.port_type = FCT_UNKNOWN; 2915 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 2916 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 2917 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 2918 ha->mr.fcport.scan_state = 1; 2919 2920 /* Set the SG table size based on ISP type */ 2921 if (!IS_FWI2_CAPABLE(ha)) { 2922 if (IS_QLA2100(ha)) 2923 host->sg_tablesize = 32; 2924 } else { 2925 if (!IS_QLA82XX(ha)) 2926 host->sg_tablesize = QLA_SG_ALL; 2927 } 2928 host->max_id = ha->max_fibre_devices; 2929 host->cmd_per_lun = 3; 2930 host->unique_id = host->host_no; 2931 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 2932 host->max_cmd_len = 32; 2933 else 2934 host->max_cmd_len = MAX_CMDSZ; 2935 host->max_channel = MAX_BUSES - 1; 2936 /* Older HBAs support only 16-bit LUNs */ 2937 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 2938 ql2xmaxlun > 0xffff) 2939 host->max_lun = 0xffff; 2940 else 2941 host->max_lun = ql2xmaxlun; 2942 host->transportt = qla2xxx_transport_template; 2943 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 2944 2945 ql_dbg(ql_dbg_init, base_vha, 0x0033, 2946 "max_id=%d this_id=%d " 2947 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 2948 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 2949 host->this_id, host->cmd_per_lun, host->unique_id, 2950 host->max_cmd_len, host->max_channel, host->max_lun, 2951 host->transportt, sht->vendor_id); 2952 2953 /* Set up the irqs */ 2954 ret = qla2x00_request_irqs(ha, rsp); 2955 if (ret) 2956 goto probe_init_failed; 2957 2958 /* Alloc arrays of request and response ring ptrs */ 2959 if (!qla2x00_alloc_queues(ha, req, rsp)) { 2960 ql_log(ql_log_fatal, base_vha, 0x003d, 2961 "Failed to allocate memory for queue pointers..." 2962 "aborting.\n"); 2963 goto probe_init_failed; 2964 } 2965 2966 if (ha->mqenable && shost_use_blk_mq(host)) { 2967 /* number of hardware queues supported by blk/scsi-mq*/ 2968 host->nr_hw_queues = ha->max_qpairs; 2969 2970 ql_dbg(ql_dbg_init, base_vha, 0x0192, 2971 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 2972 } else 2973 ql_dbg(ql_dbg_init, base_vha, 0x0193, 2974 "blk/scsi-mq disabled.\n"); 2975 2976 qlt_probe_one_stage1(base_vha, ha); 2977 2978 pci_save_state(pdev); 2979 2980 /* Assign back pointers */ 2981 rsp->req = req; 2982 req->rsp = rsp; 2983 2984 if (IS_QLAFX00(ha)) { 2985 ha->rsp_q_map[0] = rsp; 2986 ha->req_q_map[0] = req; 2987 set_bit(0, ha->req_qid_map); 2988 set_bit(0, ha->rsp_qid_map); 2989 } 2990 2991 /* FWI2-capable only. */ 2992 req->req_q_in = &ha->iobase->isp24.req_q_in; 2993 req->req_q_out = &ha->iobase->isp24.req_q_out; 2994 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 2995 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 2996 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2997 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 2998 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 2999 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3000 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3001 } 3002 3003 if (IS_QLAFX00(ha)) { 3004 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3005 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3006 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3007 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3008 } 3009 3010 if (IS_P3P_TYPE(ha)) { 3011 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3012 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3013 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3014 } 3015 3016 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3017 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3018 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3019 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3020 "req->req_q_in=%p req->req_q_out=%p " 3021 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3022 req->req_q_in, req->req_q_out, 3023 rsp->rsp_q_in, rsp->rsp_q_out); 3024 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3025 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3026 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3027 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3028 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3029 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3030 3031 if (ha->isp_ops->initialize_adapter(base_vha)) { 3032 ql_log(ql_log_fatal, base_vha, 0x00d6, 3033 "Failed to initialize adapter - Adapter flags %x.\n", 3034 base_vha->device_flags); 3035 3036 if (IS_QLA82XX(ha)) { 3037 qla82xx_idc_lock(ha); 3038 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3039 QLA8XXX_DEV_FAILED); 3040 qla82xx_idc_unlock(ha); 3041 ql_log(ql_log_fatal, base_vha, 0x00d7, 3042 "HW State: FAILED.\n"); 3043 } else if (IS_QLA8044(ha)) { 3044 qla8044_idc_lock(ha); 3045 qla8044_wr_direct(base_vha, 3046 QLA8044_CRB_DEV_STATE_INDEX, 3047 QLA8XXX_DEV_FAILED); 3048 qla8044_idc_unlock(ha); 3049 ql_log(ql_log_fatal, base_vha, 0x0150, 3050 "HW State: FAILED.\n"); 3051 } 3052 3053 ret = -ENODEV; 3054 goto probe_failed; 3055 } 3056 3057 if (IS_QLAFX00(ha)) 3058 host->can_queue = QLAFX00_MAX_CANQUEUE; 3059 else 3060 host->can_queue = req->num_outstanding_cmds - 10; 3061 3062 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3063 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3064 host->can_queue, base_vha->req, 3065 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3066 3067 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) { 3068 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); 3069 /* Create start of day qpairs for Block MQ */ 3070 if (shost_use_blk_mq(host)) { 3071 for (i = 0; i < ha->max_qpairs; i++) 3072 qla2xxx_create_qpair(base_vha, 5, 0); 3073 } 3074 } 3075 3076 if (ha->flags.running_gold_fw) 3077 goto skip_dpc; 3078 3079 /* 3080 * Startup the kernel thread for this host adapter 3081 */ 3082 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3083 "%s_dpc", base_vha->host_str); 3084 if (IS_ERR(ha->dpc_thread)) { 3085 ql_log(ql_log_fatal, base_vha, 0x00ed, 3086 "Failed to start DPC thread.\n"); 3087 ret = PTR_ERR(ha->dpc_thread); 3088 goto probe_failed; 3089 } 3090 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3091 "DPC thread started successfully.\n"); 3092 3093 /* 3094 * If we're not coming up in initiator mode, we might sit for 3095 * a while without waking up the dpc thread, which leads to a 3096 * stuck process warning. So just kick the dpc once here and 3097 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3098 */ 3099 qla2xxx_wake_dpc(base_vha); 3100 3101 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3102 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3103 3104 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3105 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3106 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3107 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3108 3109 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3110 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3111 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3112 INIT_WORK(&ha->idc_state_handler, 3113 qla83xx_idc_state_handler_work); 3114 INIT_WORK(&ha->nic_core_unrecoverable, 3115 qla83xx_nic_core_unrecoverable_work); 3116 } 3117 3118 skip_dpc: 3119 list_add_tail(&base_vha->list, &ha->vp_list); 3120 base_vha->host->irq = ha->pdev->irq; 3121 3122 /* Initialized the timer */ 3123 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); 3124 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3125 "Started qla2x00_timer with " 3126 "interval=%d.\n", WATCH_INTERVAL); 3127 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3128 "Detected hba at address=%p.\n", 3129 ha); 3130 3131 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3132 if (ha->fw_attributes & BIT_4) { 3133 int prot = 0, guard; 3134 base_vha->flags.difdix_supported = 1; 3135 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3136 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3137 if (ql2xenabledif == 1) 3138 prot = SHOST_DIX_TYPE0_PROTECTION; 3139 scsi_host_set_prot(host, 3140 prot | SHOST_DIF_TYPE1_PROTECTION 3141 | SHOST_DIF_TYPE2_PROTECTION 3142 | SHOST_DIF_TYPE3_PROTECTION 3143 | SHOST_DIX_TYPE1_PROTECTION 3144 | SHOST_DIX_TYPE2_PROTECTION 3145 | SHOST_DIX_TYPE3_PROTECTION); 3146 3147 guard = SHOST_DIX_GUARD_CRC; 3148 3149 if (IS_PI_IPGUARD_CAPABLE(ha) && 3150 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3151 guard |= SHOST_DIX_GUARD_IP; 3152 3153 scsi_host_set_guard(host, guard); 3154 } else 3155 base_vha->flags.difdix_supported = 0; 3156 } 3157 3158 ha->isp_ops->enable_intrs(ha); 3159 3160 if (IS_QLAFX00(ha)) { 3161 ret = qlafx00_fx_disc(base_vha, 3162 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3163 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3164 QLA_SG_ALL : 128; 3165 } 3166 3167 ret = scsi_add_host(host, &pdev->dev); 3168 if (ret) 3169 goto probe_failed; 3170 3171 base_vha->flags.init_done = 1; 3172 base_vha->flags.online = 1; 3173 ha->prev_minidump_failed = 0; 3174 3175 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3176 "Init done and hba is online.\n"); 3177 3178 if (qla_ini_mode_enabled(base_vha) || 3179 qla_dual_mode_enabled(base_vha)) 3180 scsi_scan_host(host); 3181 else 3182 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3183 "skipping scsi_scan_host() for non-initiator port\n"); 3184 3185 qla2x00_alloc_sysfs_attr(base_vha); 3186 3187 if (IS_QLAFX00(ha)) { 3188 ret = qlafx00_fx_disc(base_vha, 3189 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3190 3191 /* Register system information */ 3192 ret = qlafx00_fx_disc(base_vha, 3193 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3194 } 3195 3196 qla2x00_init_host_attr(base_vha); 3197 3198 qla2x00_dfs_setup(base_vha); 3199 3200 ql_log(ql_log_info, base_vha, 0x00fb, 3201 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3202 ql_log(ql_log_info, base_vha, 0x00fc, 3203 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3204 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3205 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3206 base_vha->host_no, 3207 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3208 3209 qlt_add_target(ha, base_vha); 3210 3211 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3212 3213 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3214 return -ENODEV; 3215 3216 return 0; 3217 3218 probe_init_failed: 3219 qla2x00_free_req_que(ha, req); 3220 ha->req_q_map[0] = NULL; 3221 clear_bit(0, ha->req_qid_map); 3222 qla2x00_free_rsp_que(ha, rsp); 3223 ha->rsp_q_map[0] = NULL; 3224 clear_bit(0, ha->rsp_qid_map); 3225 ha->max_req_queues = ha->max_rsp_queues = 0; 3226 3227 probe_failed: 3228 if (base_vha->timer_active) 3229 qla2x00_stop_timer(base_vha); 3230 base_vha->flags.online = 0; 3231 if (ha->dpc_thread) { 3232 struct task_struct *t = ha->dpc_thread; 3233 3234 ha->dpc_thread = NULL; 3235 kthread_stop(t); 3236 } 3237 3238 qla2x00_free_device(base_vha); 3239 3240 scsi_host_put(base_vha->host); 3241 3242 probe_hw_failed: 3243 qla2x00_clear_drv_active(ha); 3244 3245 iospace_config_failed: 3246 if (IS_P3P_TYPE(ha)) { 3247 if (!ha->nx_pcibase) 3248 iounmap((device_reg_t *)ha->nx_pcibase); 3249 if (!ql2xdbwr) 3250 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3251 } else { 3252 if (ha->iobase) 3253 iounmap(ha->iobase); 3254 if (ha->cregbase) 3255 iounmap(ha->cregbase); 3256 } 3257 pci_release_selected_regions(ha->pdev, ha->bars); 3258 kfree(ha); 3259 ha = NULL; 3260 3261 probe_out: 3262 pci_disable_device(pdev); 3263 return ret; 3264 } 3265 3266 static void 3267 qla2x00_shutdown(struct pci_dev *pdev) 3268 { 3269 scsi_qla_host_t *vha; 3270 struct qla_hw_data *ha; 3271 3272 if (!atomic_read(&pdev->enable_cnt)) 3273 return; 3274 3275 vha = pci_get_drvdata(pdev); 3276 ha = vha->hw; 3277 3278 /* Notify ISPFX00 firmware */ 3279 if (IS_QLAFX00(ha)) 3280 qlafx00_driver_shutdown(vha, 20); 3281 3282 /* Turn-off FCE trace */ 3283 if (ha->flags.fce_enabled) { 3284 qla2x00_disable_fce_trace(vha, NULL, NULL); 3285 ha->flags.fce_enabled = 0; 3286 } 3287 3288 /* Turn-off EFT trace */ 3289 if (ha->eft) 3290 qla2x00_disable_eft_trace(vha); 3291 3292 /* Stop currently executing firmware. */ 3293 qla2x00_try_to_stop_firmware(vha); 3294 3295 /* Turn adapter off line */ 3296 vha->flags.online = 0; 3297 3298 /* turn-off interrupts on the card */ 3299 if (ha->interrupts_on) { 3300 vha->flags.init_done = 0; 3301 ha->isp_ops->disable_intrs(ha); 3302 } 3303 3304 qla2x00_free_irqs(vha); 3305 3306 qla2x00_free_fw_dump(ha); 3307 3308 pci_disable_pcie_error_reporting(pdev); 3309 pci_disable_device(pdev); 3310 } 3311 3312 /* Deletes all the virtual ports for a given ha */ 3313 static void 3314 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3315 { 3316 scsi_qla_host_t *vha; 3317 unsigned long flags; 3318 3319 mutex_lock(&ha->vport_lock); 3320 while (ha->cur_vport_count) { 3321 spin_lock_irqsave(&ha->vport_slock, flags); 3322 3323 BUG_ON(base_vha->list.next == &ha->vp_list); 3324 /* This assumes first entry in ha->vp_list is always base vha */ 3325 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3326 scsi_host_get(vha->host); 3327 3328 spin_unlock_irqrestore(&ha->vport_slock, flags); 3329 mutex_unlock(&ha->vport_lock); 3330 3331 fc_vport_terminate(vha->fc_vport); 3332 scsi_host_put(vha->host); 3333 3334 mutex_lock(&ha->vport_lock); 3335 } 3336 mutex_unlock(&ha->vport_lock); 3337 } 3338 3339 /* Stops all deferred work threads */ 3340 static void 3341 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3342 { 3343 /* Cancel all work and destroy DPC workqueues */ 3344 if (ha->dpc_lp_wq) { 3345 cancel_work_sync(&ha->idc_aen); 3346 destroy_workqueue(ha->dpc_lp_wq); 3347 ha->dpc_lp_wq = NULL; 3348 } 3349 3350 if (ha->dpc_hp_wq) { 3351 cancel_work_sync(&ha->nic_core_reset); 3352 cancel_work_sync(&ha->idc_state_handler); 3353 cancel_work_sync(&ha->nic_core_unrecoverable); 3354 destroy_workqueue(ha->dpc_hp_wq); 3355 ha->dpc_hp_wq = NULL; 3356 } 3357 3358 /* Kill the kernel thread for this host */ 3359 if (ha->dpc_thread) { 3360 struct task_struct *t = ha->dpc_thread; 3361 3362 /* 3363 * qla2xxx_wake_dpc checks for ->dpc_thread 3364 * so we need to zero it out. 3365 */ 3366 ha->dpc_thread = NULL; 3367 kthread_stop(t); 3368 } 3369 } 3370 3371 static void 3372 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3373 { 3374 if (IS_QLA82XX(ha)) { 3375 3376 iounmap((device_reg_t *)ha->nx_pcibase); 3377 if (!ql2xdbwr) 3378 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3379 } else { 3380 if (ha->iobase) 3381 iounmap(ha->iobase); 3382 3383 if (ha->cregbase) 3384 iounmap(ha->cregbase); 3385 3386 if (ha->mqiobase) 3387 iounmap(ha->mqiobase); 3388 3389 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3390 iounmap(ha->msixbase); 3391 } 3392 } 3393 3394 static void 3395 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3396 { 3397 if (IS_QLA8044(ha)) { 3398 qla8044_idc_lock(ha); 3399 qla8044_clear_drv_active(ha); 3400 qla8044_idc_unlock(ha); 3401 } else if (IS_QLA82XX(ha)) { 3402 qla82xx_idc_lock(ha); 3403 qla82xx_clear_drv_active(ha); 3404 qla82xx_idc_unlock(ha); 3405 } 3406 } 3407 3408 static void 3409 qla2x00_remove_one(struct pci_dev *pdev) 3410 { 3411 scsi_qla_host_t *base_vha; 3412 struct qla_hw_data *ha; 3413 3414 base_vha = pci_get_drvdata(pdev); 3415 ha = base_vha->hw; 3416 3417 /* Indicate device removal to prevent future board_disable and wait 3418 * until any pending board_disable has completed. */ 3419 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3420 cancel_work_sync(&ha->board_disable); 3421 3422 /* 3423 * If the PCI device is disabled then there was a PCI-disconnect and 3424 * qla2x00_disable_board_on_pci_error has taken care of most of the 3425 * resources. 3426 */ 3427 if (!atomic_read(&pdev->enable_cnt)) { 3428 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3429 base_vha->gnl.l, base_vha->gnl.ldma); 3430 3431 scsi_host_put(base_vha->host); 3432 kfree(ha); 3433 pci_set_drvdata(pdev, NULL); 3434 return; 3435 } 3436 qla2x00_wait_for_hba_ready(base_vha); 3437 3438 /* 3439 * if UNLOAD flag is already set, then continue unload, 3440 * where it was set first. 3441 */ 3442 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3443 return; 3444 3445 set_bit(UNLOADING, &base_vha->dpc_flags); 3446 dma_free_coherent(&ha->pdev->dev, 3447 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3448 3449 if (IS_QLAFX00(ha)) 3450 qlafx00_driver_shutdown(base_vha, 20); 3451 3452 qla2x00_delete_all_vps(ha, base_vha); 3453 3454 if (IS_QLA8031(ha)) { 3455 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3456 "Clearing fcoe driver presence.\n"); 3457 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3458 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3459 "Error while clearing DRV-Presence.\n"); 3460 } 3461 3462 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3463 3464 qla2x00_dfs_remove(base_vha); 3465 3466 qla84xx_put_chip(base_vha); 3467 3468 /* Laser should be disabled only for ISP2031 */ 3469 if (IS_QLA2031(ha)) 3470 qla83xx_disable_laser(base_vha); 3471 3472 /* Disable timer */ 3473 if (base_vha->timer_active) 3474 qla2x00_stop_timer(base_vha); 3475 3476 base_vha->flags.online = 0; 3477 3478 /* free DMA memory */ 3479 if (ha->exlogin_buf) 3480 qla2x00_free_exlogin_buffer(ha); 3481 3482 /* free DMA memory */ 3483 if (ha->exchoffld_buf) 3484 qla2x00_free_exchoffld_buffer(ha); 3485 3486 qla2x00_destroy_deferred_work(ha); 3487 3488 qlt_remove_target(ha, base_vha); 3489 3490 qla2x00_free_sysfs_attr(base_vha, true); 3491 3492 fc_remove_host(base_vha->host); 3493 qlt_remove_target_resources(ha); 3494 3495 scsi_remove_host(base_vha->host); 3496 3497 qla2x00_free_device(base_vha); 3498 3499 qla2x00_clear_drv_active(ha); 3500 3501 scsi_host_put(base_vha->host); 3502 3503 qla2x00_unmap_iobases(ha); 3504 3505 pci_release_selected_regions(ha->pdev, ha->bars); 3506 kfree(ha); 3507 ha = NULL; 3508 3509 pci_disable_pcie_error_reporting(pdev); 3510 3511 pci_disable_device(pdev); 3512 } 3513 3514 static void 3515 qla2x00_free_device(scsi_qla_host_t *vha) 3516 { 3517 struct qla_hw_data *ha = vha->hw; 3518 3519 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3520 3521 /* Disable timer */ 3522 if (vha->timer_active) 3523 qla2x00_stop_timer(vha); 3524 3525 qla25xx_delete_queues(vha); 3526 3527 if (ha->flags.fce_enabled) 3528 qla2x00_disable_fce_trace(vha, NULL, NULL); 3529 3530 if (ha->eft) 3531 qla2x00_disable_eft_trace(vha); 3532 3533 /* Stop currently executing firmware. */ 3534 qla2x00_try_to_stop_firmware(vha); 3535 3536 vha->flags.online = 0; 3537 3538 /* turn-off interrupts on the card */ 3539 if (ha->interrupts_on) { 3540 vha->flags.init_done = 0; 3541 ha->isp_ops->disable_intrs(ha); 3542 } 3543 3544 qla2x00_free_fcports(vha); 3545 3546 qla2x00_free_irqs(vha); 3547 3548 /* Flush the work queue and remove it */ 3549 if (ha->wq) { 3550 flush_workqueue(ha->wq); 3551 destroy_workqueue(ha->wq); 3552 ha->wq = NULL; 3553 } 3554 3555 3556 qla2x00_mem_free(ha); 3557 3558 qla82xx_md_free(vha); 3559 3560 qla2x00_free_queues(ha); 3561 } 3562 3563 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3564 { 3565 fc_port_t *fcport, *tfcport; 3566 3567 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3568 list_del(&fcport->list); 3569 qla2x00_clear_loop_id(fcport); 3570 kfree(fcport); 3571 fcport = NULL; 3572 } 3573 } 3574 3575 static inline void 3576 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3577 int defer) 3578 { 3579 struct fc_rport *rport; 3580 scsi_qla_host_t *base_vha; 3581 unsigned long flags; 3582 3583 if (!fcport->rport) 3584 return; 3585 3586 rport = fcport->rport; 3587 if (defer) { 3588 base_vha = pci_get_drvdata(vha->hw->pdev); 3589 spin_lock_irqsave(vha->host->host_lock, flags); 3590 fcport->drport = rport; 3591 spin_unlock_irqrestore(vha->host->host_lock, flags); 3592 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3593 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3594 qla2xxx_wake_dpc(base_vha); 3595 } else { 3596 int now; 3597 if (rport) { 3598 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 3599 "%s %8phN. rport %p roles %x \n", 3600 __func__, fcport->port_name, rport, 3601 rport->roles); 3602 fc_remote_port_delete(rport); 3603 } 3604 qlt_do_generation_tick(vha, &now); 3605 } 3606 } 3607 3608 /* 3609 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3610 * 3611 * Input: ha = adapter block pointer. fcport = port structure pointer. 3612 * 3613 * Return: None. 3614 * 3615 * Context: 3616 */ 3617 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3618 int do_login, int defer) 3619 { 3620 if (IS_QLAFX00(vha->hw)) { 3621 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3622 qla2x00_schedule_rport_del(vha, fcport, defer); 3623 return; 3624 } 3625 3626 if (atomic_read(&fcport->state) == FCS_ONLINE && 3627 vha->vp_idx == fcport->vha->vp_idx) { 3628 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3629 qla2x00_schedule_rport_del(vha, fcport, defer); 3630 } 3631 /* 3632 * We may need to retry the login, so don't change the state of the 3633 * port but do the retries. 3634 */ 3635 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3636 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3637 3638 if (!do_login) 3639 return; 3640 3641 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3642 3643 if (fcport->login_retry == 0) { 3644 fcport->login_retry = vha->hw->login_retry_count; 3645 3646 ql_dbg(ql_dbg_disc, vha, 0x2067, 3647 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3648 fcport->port_name, fcport->loop_id, fcport->login_retry); 3649 } 3650 } 3651 3652 /* 3653 * qla2x00_mark_all_devices_lost 3654 * Updates fcport state when device goes offline. 3655 * 3656 * Input: 3657 * ha = adapter block pointer. 3658 * fcport = port structure pointer. 3659 * 3660 * Return: 3661 * None. 3662 * 3663 * Context: 3664 */ 3665 void 3666 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3667 { 3668 fc_port_t *fcport; 3669 3670 ql_dbg(ql_dbg_disc, vha, 0xffff, 3671 "Mark all dev lost\n"); 3672 3673 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3674 fcport->scan_state = 0; 3675 qlt_schedule_sess_for_deletion_lock(fcport); 3676 3677 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3678 continue; 3679 3680 /* 3681 * No point in marking the device as lost, if the device is 3682 * already DEAD. 3683 */ 3684 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3685 continue; 3686 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3687 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3688 if (defer) 3689 qla2x00_schedule_rport_del(vha, fcport, defer); 3690 else if (vha->vp_idx == fcport->vha->vp_idx) 3691 qla2x00_schedule_rport_del(vha, fcport, defer); 3692 } 3693 } 3694 } 3695 3696 /* 3697 * qla2x00_mem_alloc 3698 * Allocates adapter memory. 3699 * 3700 * Returns: 3701 * 0 = success. 3702 * !0 = failure. 3703 */ 3704 static int 3705 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3706 struct req_que **req, struct rsp_que **rsp) 3707 { 3708 char name[16]; 3709 3710 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3711 &ha->init_cb_dma, GFP_KERNEL); 3712 if (!ha->init_cb) 3713 goto fail; 3714 3715 if (qlt_mem_alloc(ha) < 0) 3716 goto fail_free_init_cb; 3717 3718 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3719 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3720 if (!ha->gid_list) 3721 goto fail_free_tgt_mem; 3722 3723 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3724 if (!ha->srb_mempool) 3725 goto fail_free_gid_list; 3726 3727 if (IS_P3P_TYPE(ha)) { 3728 /* Allocate cache for CT6 Ctx. */ 3729 if (!ctx_cachep) { 3730 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3731 sizeof(struct ct6_dsd), 0, 3732 SLAB_HWCACHE_ALIGN, NULL); 3733 if (!ctx_cachep) 3734 goto fail_free_srb_mempool; 3735 } 3736 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3737 ctx_cachep); 3738 if (!ha->ctx_mempool) 3739 goto fail_free_srb_mempool; 3740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3741 "ctx_cachep=%p ctx_mempool=%p.\n", 3742 ctx_cachep, ha->ctx_mempool); 3743 } 3744 3745 /* Get memory for cached NVRAM */ 3746 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3747 if (!ha->nvram) 3748 goto fail_free_ctx_mempool; 3749 3750 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3751 ha->pdev->device); 3752 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3753 DMA_POOL_SIZE, 8, 0); 3754 if (!ha->s_dma_pool) 3755 goto fail_free_nvram; 3756 3757 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3758 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3759 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3760 3761 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3762 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3763 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3764 if (!ha->dl_dma_pool) { 3765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3766 "Failed to allocate memory for dl_dma_pool.\n"); 3767 goto fail_s_dma_pool; 3768 } 3769 3770 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3771 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3772 if (!ha->fcp_cmnd_dma_pool) { 3773 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3774 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3775 goto fail_dl_dma_pool; 3776 } 3777 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3778 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3779 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3780 } 3781 3782 /* Allocate memory for SNS commands */ 3783 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3784 /* Get consistent memory allocated for SNS commands */ 3785 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3786 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3787 if (!ha->sns_cmd) 3788 goto fail_dma_pool; 3789 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3790 "sns_cmd: %p.\n", ha->sns_cmd); 3791 } else { 3792 /* Get consistent memory allocated for MS IOCB */ 3793 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3794 &ha->ms_iocb_dma); 3795 if (!ha->ms_iocb) 3796 goto fail_dma_pool; 3797 /* Get consistent memory allocated for CT SNS commands */ 3798 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3799 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3800 if (!ha->ct_sns) 3801 goto fail_free_ms_iocb; 3802 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 3803 "ms_iocb=%p ct_sns=%p.\n", 3804 ha->ms_iocb, ha->ct_sns); 3805 } 3806 3807 /* Allocate memory for request ring */ 3808 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 3809 if (!*req) { 3810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 3811 "Failed to allocate memory for req.\n"); 3812 goto fail_req; 3813 } 3814 (*req)->length = req_len; 3815 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 3816 ((*req)->length + 1) * sizeof(request_t), 3817 &(*req)->dma, GFP_KERNEL); 3818 if (!(*req)->ring) { 3819 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 3820 "Failed to allocate memory for req_ring.\n"); 3821 goto fail_req_ring; 3822 } 3823 /* Allocate memory for response ring */ 3824 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 3825 if (!*rsp) { 3826 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 3827 "Failed to allocate memory for rsp.\n"); 3828 goto fail_rsp; 3829 } 3830 (*rsp)->hw = ha; 3831 (*rsp)->length = rsp_len; 3832 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 3833 ((*rsp)->length + 1) * sizeof(response_t), 3834 &(*rsp)->dma, GFP_KERNEL); 3835 if (!(*rsp)->ring) { 3836 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 3837 "Failed to allocate memory for rsp_ring.\n"); 3838 goto fail_rsp_ring; 3839 } 3840 (*req)->rsp = *rsp; 3841 (*rsp)->req = *req; 3842 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 3843 "req=%p req->length=%d req->ring=%p rsp=%p " 3844 "rsp->length=%d rsp->ring=%p.\n", 3845 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 3846 (*rsp)->ring); 3847 /* Allocate memory for NVRAM data for vports */ 3848 if (ha->nvram_npiv_size) { 3849 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 3850 ha->nvram_npiv_size, GFP_KERNEL); 3851 if (!ha->npiv_info) { 3852 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 3853 "Failed to allocate memory for npiv_info.\n"); 3854 goto fail_npiv_info; 3855 } 3856 } else 3857 ha->npiv_info = NULL; 3858 3859 /* Get consistent memory allocated for EX-INIT-CB. */ 3860 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3861 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3862 &ha->ex_init_cb_dma); 3863 if (!ha->ex_init_cb) 3864 goto fail_ex_init_cb; 3865 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 3866 "ex_init_cb=%p.\n", ha->ex_init_cb); 3867 } 3868 3869 INIT_LIST_HEAD(&ha->gbl_dsd_list); 3870 3871 /* Get consistent memory allocated for Async Port-Database. */ 3872 if (!IS_FWI2_CAPABLE(ha)) { 3873 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3874 &ha->async_pd_dma); 3875 if (!ha->async_pd) 3876 goto fail_async_pd; 3877 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 3878 "async_pd=%p.\n", ha->async_pd); 3879 } 3880 3881 INIT_LIST_HEAD(&ha->vp_list); 3882 3883 /* Allocate memory for our loop_id bitmap */ 3884 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 3885 GFP_KERNEL); 3886 if (!ha->loop_id_map) 3887 goto fail_loop_id_map; 3888 else { 3889 qla2x00_set_reserved_loop_ids(ha); 3890 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 3891 "loop_id_map=%p.\n", ha->loop_id_map); 3892 } 3893 3894 return 0; 3895 3896 fail_loop_id_map: 3897 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 3898 fail_async_pd: 3899 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 3900 fail_ex_init_cb: 3901 kfree(ha->npiv_info); 3902 fail_npiv_info: 3903 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 3904 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 3905 (*rsp)->ring = NULL; 3906 (*rsp)->dma = 0; 3907 fail_rsp_ring: 3908 kfree(*rsp); 3909 fail_rsp: 3910 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 3911 sizeof(request_t), (*req)->ring, (*req)->dma); 3912 (*req)->ring = NULL; 3913 (*req)->dma = 0; 3914 fail_req_ring: 3915 kfree(*req); 3916 fail_req: 3917 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 3918 ha->ct_sns, ha->ct_sns_dma); 3919 ha->ct_sns = NULL; 3920 ha->ct_sns_dma = 0; 3921 fail_free_ms_iocb: 3922 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 3923 ha->ms_iocb = NULL; 3924 ha->ms_iocb_dma = 0; 3925 3926 if (ha->sns_cmd) 3927 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 3928 ha->sns_cmd, ha->sns_cmd_dma); 3929 fail_dma_pool: 3930 if (IS_QLA82XX(ha) || ql2xenabledif) { 3931 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 3932 ha->fcp_cmnd_dma_pool = NULL; 3933 } 3934 fail_dl_dma_pool: 3935 if (IS_QLA82XX(ha) || ql2xenabledif) { 3936 dma_pool_destroy(ha->dl_dma_pool); 3937 ha->dl_dma_pool = NULL; 3938 } 3939 fail_s_dma_pool: 3940 dma_pool_destroy(ha->s_dma_pool); 3941 ha->s_dma_pool = NULL; 3942 fail_free_nvram: 3943 kfree(ha->nvram); 3944 ha->nvram = NULL; 3945 fail_free_ctx_mempool: 3946 if (ha->ctx_mempool) 3947 mempool_destroy(ha->ctx_mempool); 3948 ha->ctx_mempool = NULL; 3949 fail_free_srb_mempool: 3950 if (ha->srb_mempool) 3951 mempool_destroy(ha->srb_mempool); 3952 ha->srb_mempool = NULL; 3953 fail_free_gid_list: 3954 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 3955 ha->gid_list, 3956 ha->gid_list_dma); 3957 ha->gid_list = NULL; 3958 ha->gid_list_dma = 0; 3959 fail_free_tgt_mem: 3960 qlt_mem_free(ha); 3961 fail_free_init_cb: 3962 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 3963 ha->init_cb_dma); 3964 ha->init_cb = NULL; 3965 ha->init_cb_dma = 0; 3966 fail: 3967 ql_log(ql_log_fatal, NULL, 0x0030, 3968 "Memory allocation failure.\n"); 3969 return -ENOMEM; 3970 } 3971 3972 int 3973 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 3974 { 3975 int rval; 3976 uint16_t size, max_cnt, temp; 3977 struct qla_hw_data *ha = vha->hw; 3978 3979 /* Return if we don't need to alloacate any extended logins */ 3980 if (!ql2xexlogins) 3981 return QLA_SUCCESS; 3982 3983 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 3984 max_cnt = 0; 3985 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 3986 if (rval != QLA_SUCCESS) { 3987 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 3988 "Failed to get exlogin status.\n"); 3989 return rval; 3990 } 3991 3992 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 3993 ha->exlogin_size = (size * temp); 3994 ql_log(ql_log_info, vha, 0xd024, 3995 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 3996 max_cnt, size, temp); 3997 3998 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", 3999 ha->exlogin_size); 4000 4001 /* Get consistent memory for extended logins */ 4002 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4003 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4004 if (!ha->exlogin_buf) { 4005 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4006 "Failed to allocate memory for exlogin_buf_dma.\n"); 4007 return -ENOMEM; 4008 } 4009 4010 /* Now configure the dma buffer */ 4011 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4012 if (rval) { 4013 ql_log(ql_log_fatal, vha, 0x00cf, 4014 "Setup extended login buffer ****FAILED****.\n"); 4015 qla2x00_free_exlogin_buffer(ha); 4016 } 4017 4018 return rval; 4019 } 4020 4021 /* 4022 * qla2x00_free_exlogin_buffer 4023 * 4024 * Input: 4025 * ha = adapter block pointer 4026 */ 4027 void 4028 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4029 { 4030 if (ha->exlogin_buf) { 4031 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4032 ha->exlogin_buf, ha->exlogin_buf_dma); 4033 ha->exlogin_buf = NULL; 4034 ha->exlogin_size = 0; 4035 } 4036 } 4037 4038 int 4039 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4040 { 4041 int rval; 4042 uint16_t size, max_cnt, temp; 4043 struct qla_hw_data *ha = vha->hw; 4044 4045 /* Return if we don't need to alloacate any extended logins */ 4046 if (!ql2xexchoffld) 4047 return QLA_SUCCESS; 4048 4049 ql_log(ql_log_info, vha, 0xd014, 4050 "Exchange offload count: %d.\n", ql2xexlogins); 4051 4052 max_cnt = 0; 4053 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4054 if (rval != QLA_SUCCESS) { 4055 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4056 "Failed to get exlogin status.\n"); 4057 return rval; 4058 } 4059 4060 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; 4061 ha->exchoffld_size = (size * temp); 4062 ql_log(ql_log_info, vha, 0xd016, 4063 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", 4064 max_cnt, size, temp); 4065 4066 ql_log(ql_log_info, vha, 0xd017, 4067 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); 4068 4069 /* Get consistent memory for extended logins */ 4070 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4071 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4072 if (!ha->exchoffld_buf) { 4073 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4074 "Failed to allocate memory for exchoffld_buf_dma.\n"); 4075 return -ENOMEM; 4076 } 4077 4078 /* Now configure the dma buffer */ 4079 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); 4080 if (rval) { 4081 ql_log(ql_log_fatal, vha, 0xd02e, 4082 "Setup exchange offload buffer ****FAILED****.\n"); 4083 qla2x00_free_exchoffld_buffer(ha); 4084 } 4085 4086 return rval; 4087 } 4088 4089 /* 4090 * qla2x00_free_exchoffld_buffer 4091 * 4092 * Input: 4093 * ha = adapter block pointer 4094 */ 4095 void 4096 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4097 { 4098 if (ha->exchoffld_buf) { 4099 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4100 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4101 ha->exchoffld_buf = NULL; 4102 ha->exchoffld_size = 0; 4103 } 4104 } 4105 4106 /* 4107 * qla2x00_free_fw_dump 4108 * Frees fw dump stuff. 4109 * 4110 * Input: 4111 * ha = adapter block pointer 4112 */ 4113 static void 4114 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4115 { 4116 if (ha->fce) 4117 dma_free_coherent(&ha->pdev->dev, 4118 FCE_SIZE, ha->fce, ha->fce_dma); 4119 4120 if (ha->eft) 4121 dma_free_coherent(&ha->pdev->dev, 4122 EFT_SIZE, ha->eft, ha->eft_dma); 4123 4124 if (ha->fw_dump) 4125 vfree(ha->fw_dump); 4126 if (ha->fw_dump_template) 4127 vfree(ha->fw_dump_template); 4128 4129 ha->fce = NULL; 4130 ha->fce_dma = 0; 4131 ha->eft = NULL; 4132 ha->eft_dma = 0; 4133 ha->fw_dumped = 0; 4134 ha->fw_dump_cap_flags = 0; 4135 ha->fw_dump_reading = 0; 4136 ha->fw_dump = NULL; 4137 ha->fw_dump_len = 0; 4138 ha->fw_dump_template = NULL; 4139 ha->fw_dump_template_len = 0; 4140 } 4141 4142 /* 4143 * qla2x00_mem_free 4144 * Frees all adapter allocated memory. 4145 * 4146 * Input: 4147 * ha = adapter block pointer. 4148 */ 4149 static void 4150 qla2x00_mem_free(struct qla_hw_data *ha) 4151 { 4152 qla2x00_free_fw_dump(ha); 4153 4154 if (ha->mctp_dump) 4155 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4156 ha->mctp_dump_dma); 4157 4158 if (ha->srb_mempool) 4159 mempool_destroy(ha->srb_mempool); 4160 4161 if (ha->dcbx_tlv) 4162 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4163 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4164 4165 if (ha->xgmac_data) 4166 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4167 ha->xgmac_data, ha->xgmac_data_dma); 4168 4169 if (ha->sns_cmd) 4170 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4171 ha->sns_cmd, ha->sns_cmd_dma); 4172 4173 if (ha->ct_sns) 4174 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4175 ha->ct_sns, ha->ct_sns_dma); 4176 4177 if (ha->sfp_data) 4178 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); 4179 4180 if (ha->ms_iocb) 4181 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4182 4183 if (ha->ex_init_cb) 4184 dma_pool_free(ha->s_dma_pool, 4185 ha->ex_init_cb, ha->ex_init_cb_dma); 4186 4187 if (ha->async_pd) 4188 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4189 4190 if (ha->s_dma_pool) 4191 dma_pool_destroy(ha->s_dma_pool); 4192 4193 if (ha->gid_list) 4194 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4195 ha->gid_list, ha->gid_list_dma); 4196 4197 if (IS_QLA82XX(ha)) { 4198 if (!list_empty(&ha->gbl_dsd_list)) { 4199 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4200 4201 /* clean up allocated prev pool */ 4202 list_for_each_entry_safe(dsd_ptr, 4203 tdsd_ptr, &ha->gbl_dsd_list, list) { 4204 dma_pool_free(ha->dl_dma_pool, 4205 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4206 list_del(&dsd_ptr->list); 4207 kfree(dsd_ptr); 4208 } 4209 } 4210 } 4211 4212 if (ha->dl_dma_pool) 4213 dma_pool_destroy(ha->dl_dma_pool); 4214 4215 if (ha->fcp_cmnd_dma_pool) 4216 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4217 4218 if (ha->ctx_mempool) 4219 mempool_destroy(ha->ctx_mempool); 4220 4221 qlt_mem_free(ha); 4222 4223 if (ha->init_cb) 4224 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4225 ha->init_cb, ha->init_cb_dma); 4226 vfree(ha->optrom_buffer); 4227 kfree(ha->nvram); 4228 kfree(ha->npiv_info); 4229 kfree(ha->swl); 4230 kfree(ha->loop_id_map); 4231 4232 ha->srb_mempool = NULL; 4233 ha->ctx_mempool = NULL; 4234 ha->sns_cmd = NULL; 4235 ha->sns_cmd_dma = 0; 4236 ha->ct_sns = NULL; 4237 ha->ct_sns_dma = 0; 4238 ha->ms_iocb = NULL; 4239 ha->ms_iocb_dma = 0; 4240 ha->init_cb = NULL; 4241 ha->init_cb_dma = 0; 4242 ha->ex_init_cb = NULL; 4243 ha->ex_init_cb_dma = 0; 4244 ha->async_pd = NULL; 4245 ha->async_pd_dma = 0; 4246 4247 ha->s_dma_pool = NULL; 4248 ha->dl_dma_pool = NULL; 4249 ha->fcp_cmnd_dma_pool = NULL; 4250 4251 ha->gid_list = NULL; 4252 ha->gid_list_dma = 0; 4253 4254 ha->tgt.atio_ring = NULL; 4255 ha->tgt.atio_dma = 0; 4256 ha->tgt.tgt_vp_map = NULL; 4257 } 4258 4259 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4260 struct qla_hw_data *ha) 4261 { 4262 struct Scsi_Host *host; 4263 struct scsi_qla_host *vha = NULL; 4264 4265 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4266 if (!host) { 4267 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4268 "Failed to allocate host from the scsi layer, aborting.\n"); 4269 return NULL; 4270 } 4271 4272 /* Clear our data area */ 4273 vha = shost_priv(host); 4274 memset(vha, 0, sizeof(scsi_qla_host_t)); 4275 4276 vha->host = host; 4277 vha->host_no = host->host_no; 4278 vha->hw = ha; 4279 4280 INIT_LIST_HEAD(&vha->vp_fcports); 4281 INIT_LIST_HEAD(&vha->work_list); 4282 INIT_LIST_HEAD(&vha->list); 4283 INIT_LIST_HEAD(&vha->qla_cmd_list); 4284 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4285 INIT_LIST_HEAD(&vha->logo_list); 4286 INIT_LIST_HEAD(&vha->plogi_ack_list); 4287 INIT_LIST_HEAD(&vha->qp_list); 4288 INIT_LIST_HEAD(&vha->gnl.fcports); 4289 4290 spin_lock_init(&vha->work_lock); 4291 spin_lock_init(&vha->cmd_list_lock); 4292 init_waitqueue_head(&vha->fcport_waitQ); 4293 init_waitqueue_head(&vha->vref_waitq); 4294 4295 vha->gnl.size = sizeof(struct get_name_list_extended) * 4296 (ha->max_loop_id + 1); 4297 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4298 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4299 if (!vha->gnl.l) { 4300 ql_log(ql_log_fatal, vha, 0xffff, 4301 "Alloc failed for name list.\n"); 4302 scsi_remove_host(vha->host); 4303 return NULL; 4304 } 4305 4306 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4307 ql_dbg(ql_dbg_init, vha, 0x0041, 4308 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4309 vha->host, vha->hw, vha, 4310 dev_name(&(ha->pdev->dev))); 4311 4312 return vha; 4313 } 4314 4315 struct qla_work_evt * 4316 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4317 { 4318 struct qla_work_evt *e; 4319 uint8_t bail; 4320 4321 QLA_VHA_MARK_BUSY(vha, bail); 4322 if (bail) 4323 return NULL; 4324 4325 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4326 if (!e) { 4327 QLA_VHA_MARK_NOT_BUSY(vha); 4328 return NULL; 4329 } 4330 4331 INIT_LIST_HEAD(&e->list); 4332 e->type = type; 4333 e->flags = QLA_EVT_FLAG_FREE; 4334 return e; 4335 } 4336 4337 int 4338 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4339 { 4340 unsigned long flags; 4341 4342 spin_lock_irqsave(&vha->work_lock, flags); 4343 list_add_tail(&e->list, &vha->work_list); 4344 spin_unlock_irqrestore(&vha->work_lock, flags); 4345 4346 if (QLA_EARLY_LINKUP(vha->hw)) 4347 schedule_work(&vha->iocb_work); 4348 else 4349 qla2xxx_wake_dpc(vha); 4350 4351 return QLA_SUCCESS; 4352 } 4353 4354 int 4355 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4356 u32 data) 4357 { 4358 struct qla_work_evt *e; 4359 4360 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4361 if (!e) 4362 return QLA_FUNCTION_FAILED; 4363 4364 e->u.aen.code = code; 4365 e->u.aen.data = data; 4366 return qla2x00_post_work(vha, e); 4367 } 4368 4369 int 4370 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4371 { 4372 struct qla_work_evt *e; 4373 4374 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4375 if (!e) 4376 return QLA_FUNCTION_FAILED; 4377 4378 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4379 return qla2x00_post_work(vha, e); 4380 } 4381 4382 #define qla2x00_post_async_work(name, type) \ 4383 int qla2x00_post_async_##name##_work( \ 4384 struct scsi_qla_host *vha, \ 4385 fc_port_t *fcport, uint16_t *data) \ 4386 { \ 4387 struct qla_work_evt *e; \ 4388 \ 4389 e = qla2x00_alloc_work(vha, type); \ 4390 if (!e) \ 4391 return QLA_FUNCTION_FAILED; \ 4392 \ 4393 e->u.logio.fcport = fcport; \ 4394 if (data) { \ 4395 e->u.logio.data[0] = data[0]; \ 4396 e->u.logio.data[1] = data[1]; \ 4397 } \ 4398 return qla2x00_post_work(vha, e); \ 4399 } 4400 4401 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4402 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4403 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4404 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4405 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4406 4407 int 4408 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4409 { 4410 struct qla_work_evt *e; 4411 4412 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4413 if (!e) 4414 return QLA_FUNCTION_FAILED; 4415 4416 e->u.uevent.code = code; 4417 return qla2x00_post_work(vha, e); 4418 } 4419 4420 static void 4421 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4422 { 4423 char event_string[40]; 4424 char *envp[] = { event_string, NULL }; 4425 4426 switch (code) { 4427 case QLA_UEVENT_CODE_FW_DUMP: 4428 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4429 vha->host_no); 4430 break; 4431 default: 4432 /* do nothing */ 4433 break; 4434 } 4435 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4436 } 4437 4438 int 4439 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4440 uint32_t *data, int cnt) 4441 { 4442 struct qla_work_evt *e; 4443 4444 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4445 if (!e) 4446 return QLA_FUNCTION_FAILED; 4447 4448 e->u.aenfx.evtcode = evtcode; 4449 e->u.aenfx.count = cnt; 4450 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4451 return qla2x00_post_work(vha, e); 4452 } 4453 4454 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4455 { 4456 struct qla_work_evt *e; 4457 4458 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4459 if (!e) 4460 return QLA_FUNCTION_FAILED; 4461 4462 e->u.fcport.fcport = fcport; 4463 return qla2x00_post_work(vha, e); 4464 } 4465 4466 static 4467 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4468 { 4469 unsigned long flags; 4470 fc_port_t *fcport = NULL; 4471 struct qlt_plogi_ack_t *pla = 4472 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4473 4474 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4475 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4476 if (fcport) { 4477 fcport->d_id = e->u.new_sess.id; 4478 if (pla) { 4479 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4480 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4481 /* we took an extra ref_count to prevent PLOGI ACK when 4482 * fcport/sess has not been created. 4483 */ 4484 pla->ref_count--; 4485 } 4486 } else { 4487 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4488 if (fcport) { 4489 fcport->d_id = e->u.new_sess.id; 4490 fcport->scan_state = QLA_FCPORT_FOUND; 4491 fcport->flags |= FCF_FABRIC_DEVICE; 4492 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4493 4494 memcpy(fcport->port_name, e->u.new_sess.port_name, 4495 WWN_SIZE); 4496 list_add_tail(&fcport->list, &vha->vp_fcports); 4497 4498 if (pla) { 4499 qlt_plogi_ack_link(vha, pla, fcport, 4500 QLT_PLOGI_LINK_SAME_WWN); 4501 pla->ref_count--; 4502 } 4503 } 4504 } 4505 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4506 4507 if (fcport) { 4508 if (pla) 4509 qlt_plogi_ack_unref(vha, pla); 4510 else 4511 qla24xx_async_gnl(vha, fcport); 4512 } 4513 } 4514 4515 void 4516 qla2x00_do_work(struct scsi_qla_host *vha) 4517 { 4518 struct qla_work_evt *e, *tmp; 4519 unsigned long flags; 4520 LIST_HEAD(work); 4521 4522 spin_lock_irqsave(&vha->work_lock, flags); 4523 list_splice_init(&vha->work_list, &work); 4524 spin_unlock_irqrestore(&vha->work_lock, flags); 4525 4526 list_for_each_entry_safe(e, tmp, &work, list) { 4527 list_del_init(&e->list); 4528 4529 switch (e->type) { 4530 case QLA_EVT_AEN: 4531 fc_host_post_event(vha->host, fc_get_event_number(), 4532 e->u.aen.code, e->u.aen.data); 4533 break; 4534 case QLA_EVT_IDC_ACK: 4535 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4536 break; 4537 case QLA_EVT_ASYNC_LOGIN: 4538 qla2x00_async_login(vha, e->u.logio.fcport, 4539 e->u.logio.data); 4540 break; 4541 case QLA_EVT_ASYNC_LOGOUT: 4542 qla2x00_async_logout(vha, e->u.logio.fcport); 4543 break; 4544 case QLA_EVT_ASYNC_LOGOUT_DONE: 4545 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4546 e->u.logio.data); 4547 break; 4548 case QLA_EVT_ASYNC_ADISC: 4549 qla2x00_async_adisc(vha, e->u.logio.fcport, 4550 e->u.logio.data); 4551 break; 4552 case QLA_EVT_ASYNC_ADISC_DONE: 4553 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4554 e->u.logio.data); 4555 break; 4556 case QLA_EVT_UEVENT: 4557 qla2x00_uevent_emit(vha, e->u.uevent.code); 4558 break; 4559 case QLA_EVT_AENFX: 4560 qlafx00_process_aen(vha, e); 4561 break; 4562 case QLA_EVT_GIDPN: 4563 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 4564 break; 4565 case QLA_EVT_GPNID: 4566 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 4567 break; 4568 case QLA_EVT_GPNID_DONE: 4569 qla24xx_async_gpnid_done(vha, e->u.iosb.sp); 4570 break; 4571 case QLA_EVT_NEW_SESS: 4572 qla24xx_create_new_sess(vha, e); 4573 break; 4574 case QLA_EVT_GPDB: 4575 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 4576 e->u.fcport.opt); 4577 break; 4578 case QLA_EVT_GPSC: 4579 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 4580 break; 4581 case QLA_EVT_UPD_FCPORT: 4582 qla2x00_update_fcport(vha, e->u.fcport.fcport); 4583 break; 4584 case QLA_EVT_GNL: 4585 qla24xx_async_gnl(vha, e->u.fcport.fcport); 4586 break; 4587 case QLA_EVT_NACK: 4588 qla24xx_do_nack_work(vha, e); 4589 break; 4590 } 4591 if (e->flags & QLA_EVT_FLAG_FREE) 4592 kfree(e); 4593 4594 /* For each work completed decrement vha ref count */ 4595 QLA_VHA_MARK_NOT_BUSY(vha); 4596 } 4597 } 4598 4599 /* Relogins all the fcports of a vport 4600 * Context: dpc thread 4601 */ 4602 void qla2x00_relogin(struct scsi_qla_host *vha) 4603 { 4604 fc_port_t *fcport; 4605 int status; 4606 struct event_arg ea; 4607 4608 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4609 /* 4610 * If the port is not ONLINE then try to login 4611 * to it if we haven't run out of retries. 4612 */ 4613 if (atomic_read(&fcport->state) != FCS_ONLINE && 4614 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { 4615 fcport->login_retry--; 4616 if (fcport->flags & FCF_FABRIC_DEVICE) { 4617 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 4618 "%s %8phC DS %d LS %d\n", __func__, 4619 fcport->port_name, fcport->disc_state, 4620 fcport->fw_login_state); 4621 memset(&ea, 0, sizeof(ea)); 4622 ea.event = FCME_RELOGIN; 4623 ea.fcport = fcport; 4624 qla2x00_fcport_event_handler(vha, &ea); 4625 } else { 4626 status = qla2x00_local_device_login(vha, 4627 fcport); 4628 if (status == QLA_SUCCESS) { 4629 fcport->old_loop_id = fcport->loop_id; 4630 ql_dbg(ql_dbg_disc, vha, 0x2003, 4631 "Port login OK: logged in ID 0x%x.\n", 4632 fcport->loop_id); 4633 qla2x00_update_fcport(vha, fcport); 4634 } else if (status == 1) { 4635 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4636 /* retry the login again */ 4637 ql_dbg(ql_dbg_disc, vha, 0x2007, 4638 "Retrying %d login again loop_id 0x%x.\n", 4639 fcport->login_retry, 4640 fcport->loop_id); 4641 } else { 4642 fcport->login_retry = 0; 4643 } 4644 4645 if (fcport->login_retry == 0 && 4646 status != QLA_SUCCESS) 4647 qla2x00_clear_loop_id(fcport); 4648 } 4649 } 4650 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4651 break; 4652 } 4653 } 4654 4655 /* Schedule work on any of the dpc-workqueues */ 4656 void 4657 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 4658 { 4659 struct qla_hw_data *ha = base_vha->hw; 4660 4661 switch (work_code) { 4662 case MBA_IDC_AEN: /* 0x8200 */ 4663 if (ha->dpc_lp_wq) 4664 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 4665 break; 4666 4667 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 4668 if (!ha->flags.nic_core_reset_hdlr_active) { 4669 if (ha->dpc_hp_wq) 4670 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 4671 } else 4672 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 4673 "NIC Core reset is already active. Skip " 4674 "scheduling it again.\n"); 4675 break; 4676 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 4677 if (ha->dpc_hp_wq) 4678 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 4679 break; 4680 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 4681 if (ha->dpc_hp_wq) 4682 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 4683 break; 4684 default: 4685 ql_log(ql_log_warn, base_vha, 0xb05f, 4686 "Unknown work-code=0x%x.\n", work_code); 4687 } 4688 4689 return; 4690 } 4691 4692 /* Work: Perform NIC Core Unrecoverable state handling */ 4693 void 4694 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 4695 { 4696 struct qla_hw_data *ha = 4697 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 4698 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4699 uint32_t dev_state = 0; 4700 4701 qla83xx_idc_lock(base_vha, 0); 4702 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4703 qla83xx_reset_ownership(base_vha); 4704 if (ha->flags.nic_core_reset_owner) { 4705 ha->flags.nic_core_reset_owner = 0; 4706 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4707 QLA8XXX_DEV_FAILED); 4708 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 4709 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4710 } 4711 qla83xx_idc_unlock(base_vha, 0); 4712 } 4713 4714 /* Work: Execute IDC state handler */ 4715 void 4716 qla83xx_idc_state_handler_work(struct work_struct *work) 4717 { 4718 struct qla_hw_data *ha = 4719 container_of(work, struct qla_hw_data, idc_state_handler); 4720 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4721 uint32_t dev_state = 0; 4722 4723 qla83xx_idc_lock(base_vha, 0); 4724 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4725 if (dev_state == QLA8XXX_DEV_FAILED || 4726 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 4727 qla83xx_idc_state_handler(base_vha); 4728 qla83xx_idc_unlock(base_vha, 0); 4729 } 4730 4731 static int 4732 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 4733 { 4734 int rval = QLA_SUCCESS; 4735 unsigned long heart_beat_wait = jiffies + (1 * HZ); 4736 uint32_t heart_beat_counter1, heart_beat_counter2; 4737 4738 do { 4739 if (time_after(jiffies, heart_beat_wait)) { 4740 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 4741 "Nic Core f/w is not alive.\n"); 4742 rval = QLA_FUNCTION_FAILED; 4743 break; 4744 } 4745 4746 qla83xx_idc_lock(base_vha, 0); 4747 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4748 &heart_beat_counter1); 4749 qla83xx_idc_unlock(base_vha, 0); 4750 msleep(100); 4751 qla83xx_idc_lock(base_vha, 0); 4752 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 4753 &heart_beat_counter2); 4754 qla83xx_idc_unlock(base_vha, 0); 4755 } while (heart_beat_counter1 == heart_beat_counter2); 4756 4757 return rval; 4758 } 4759 4760 /* Work: Perform NIC Core Reset handling */ 4761 void 4762 qla83xx_nic_core_reset_work(struct work_struct *work) 4763 { 4764 struct qla_hw_data *ha = 4765 container_of(work, struct qla_hw_data, nic_core_reset); 4766 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4767 uint32_t dev_state = 0; 4768 4769 if (IS_QLA2031(ha)) { 4770 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 4771 ql_log(ql_log_warn, base_vha, 0xb081, 4772 "Failed to dump mctp\n"); 4773 return; 4774 } 4775 4776 if (!ha->flags.nic_core_reset_hdlr_active) { 4777 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 4778 qla83xx_idc_lock(base_vha, 0); 4779 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 4780 &dev_state); 4781 qla83xx_idc_unlock(base_vha, 0); 4782 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 4783 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 4784 "Nic Core f/w is alive.\n"); 4785 return; 4786 } 4787 } 4788 4789 ha->flags.nic_core_reset_hdlr_active = 1; 4790 if (qla83xx_nic_core_reset(base_vha)) { 4791 /* NIC Core reset failed. */ 4792 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 4793 "NIC Core reset failed.\n"); 4794 } 4795 ha->flags.nic_core_reset_hdlr_active = 0; 4796 } 4797 } 4798 4799 /* Work: Handle 8200 IDC aens */ 4800 void 4801 qla83xx_service_idc_aen(struct work_struct *work) 4802 { 4803 struct qla_hw_data *ha = 4804 container_of(work, struct qla_hw_data, idc_aen); 4805 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4806 uint32_t dev_state, idc_control; 4807 4808 qla83xx_idc_lock(base_vha, 0); 4809 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4810 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 4811 qla83xx_idc_unlock(base_vha, 0); 4812 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 4813 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 4814 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 4815 "Application requested NIC Core Reset.\n"); 4816 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4817 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 4818 QLA_SUCCESS) { 4819 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 4820 "Other protocol driver requested NIC Core Reset.\n"); 4821 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 4822 } 4823 } else if (dev_state == QLA8XXX_DEV_FAILED || 4824 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 4825 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 4826 } 4827 } 4828 4829 static void 4830 qla83xx_wait_logic(void) 4831 { 4832 int i; 4833 4834 /* Yield CPU */ 4835 if (!in_interrupt()) { 4836 /* 4837 * Wait about 200ms before retrying again. 4838 * This controls the number of retries for single 4839 * lock operation. 4840 */ 4841 msleep(100); 4842 schedule(); 4843 } else { 4844 for (i = 0; i < 20; i++) 4845 cpu_relax(); /* This a nop instr on i386 */ 4846 } 4847 } 4848 4849 static int 4850 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 4851 { 4852 int rval; 4853 uint32_t data; 4854 uint32_t idc_lck_rcvry_stage_mask = 0x3; 4855 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 4856 struct qla_hw_data *ha = base_vha->hw; 4857 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 4858 "Trying force recovery of the IDC lock.\n"); 4859 4860 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 4861 if (rval) 4862 return rval; 4863 4864 if ((data & idc_lck_rcvry_stage_mask) > 0) { 4865 return QLA_SUCCESS; 4866 } else { 4867 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 4868 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4869 data); 4870 if (rval) 4871 return rval; 4872 4873 msleep(200); 4874 4875 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 4876 &data); 4877 if (rval) 4878 return rval; 4879 4880 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 4881 data &= (IDC_LOCK_RECOVERY_STAGE2 | 4882 ~(idc_lck_rcvry_stage_mask)); 4883 rval = qla83xx_wr_reg(base_vha, 4884 QLA83XX_IDC_LOCK_RECOVERY, data); 4885 if (rval) 4886 return rval; 4887 4888 /* Forcefully perform IDC UnLock */ 4889 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 4890 &data); 4891 if (rval) 4892 return rval; 4893 /* Clear lock-id by setting 0xff */ 4894 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4895 0xff); 4896 if (rval) 4897 return rval; 4898 /* Clear lock-recovery by setting 0x0 */ 4899 rval = qla83xx_wr_reg(base_vha, 4900 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 4901 if (rval) 4902 return rval; 4903 } else 4904 return QLA_SUCCESS; 4905 } 4906 4907 return rval; 4908 } 4909 4910 static int 4911 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 4912 { 4913 int rval = QLA_SUCCESS; 4914 uint32_t o_drv_lockid, n_drv_lockid; 4915 unsigned long lock_recovery_timeout; 4916 4917 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 4918 retry_lockid: 4919 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 4920 if (rval) 4921 goto exit; 4922 4923 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 4924 if (time_after_eq(jiffies, lock_recovery_timeout)) { 4925 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 4926 return QLA_SUCCESS; 4927 else 4928 return QLA_FUNCTION_FAILED; 4929 } 4930 4931 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 4932 if (rval) 4933 goto exit; 4934 4935 if (o_drv_lockid == n_drv_lockid) { 4936 qla83xx_wait_logic(); 4937 goto retry_lockid; 4938 } else 4939 return QLA_SUCCESS; 4940 4941 exit: 4942 return rval; 4943 } 4944 4945 void 4946 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 4947 { 4948 uint16_t options = (requester_id << 15) | BIT_6; 4949 uint32_t data; 4950 uint32_t lock_owner; 4951 struct qla_hw_data *ha = base_vha->hw; 4952 4953 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 4954 retry_lock: 4955 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 4956 == QLA_SUCCESS) { 4957 if (data) { 4958 /* Setting lock-id to our function-number */ 4959 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4960 ha->portnum); 4961 } else { 4962 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 4963 &lock_owner); 4964 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 4965 "Failed to acquire IDC lock, acquired by %d, " 4966 "retrying...\n", lock_owner); 4967 4968 /* Retry/Perform IDC-Lock recovery */ 4969 if (qla83xx_idc_lock_recovery(base_vha) 4970 == QLA_SUCCESS) { 4971 qla83xx_wait_logic(); 4972 goto retry_lock; 4973 } else 4974 ql_log(ql_log_warn, base_vha, 0xb075, 4975 "IDC Lock recovery FAILED.\n"); 4976 } 4977 4978 } 4979 4980 return; 4981 4982 /* XXX: IDC-lock implementation using access-control mbx */ 4983 retry_lock2: 4984 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 4985 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 4986 "Failed to acquire IDC lock. retrying...\n"); 4987 /* Retry/Perform IDC-Lock recovery */ 4988 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 4989 qla83xx_wait_logic(); 4990 goto retry_lock2; 4991 } else 4992 ql_log(ql_log_warn, base_vha, 0xb076, 4993 "IDC Lock recovery FAILED.\n"); 4994 } 4995 4996 return; 4997 } 4998 4999 void 5000 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5001 { 5002 #if 0 5003 uint16_t options = (requester_id << 15) | BIT_7; 5004 #endif 5005 uint16_t retry; 5006 uint32_t data; 5007 struct qla_hw_data *ha = base_vha->hw; 5008 5009 /* IDC-unlock implementation using driver-unlock/lock-id 5010 * remote registers 5011 */ 5012 retry = 0; 5013 retry_unlock: 5014 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5015 == QLA_SUCCESS) { 5016 if (data == ha->portnum) { 5017 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5018 /* Clearing lock-id by setting 0xff */ 5019 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5020 } else if (retry < 10) { 5021 /* SV: XXX: IDC unlock retrying needed here? */ 5022 5023 /* Retry for IDC-unlock */ 5024 qla83xx_wait_logic(); 5025 retry++; 5026 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5027 "Failed to release IDC lock, retrying=%d\n", retry); 5028 goto retry_unlock; 5029 } 5030 } else if (retry < 10) { 5031 /* Retry for IDC-unlock */ 5032 qla83xx_wait_logic(); 5033 retry++; 5034 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5035 "Failed to read drv-lockid, retrying=%d\n", retry); 5036 goto retry_unlock; 5037 } 5038 5039 return; 5040 5041 #if 0 5042 /* XXX: IDC-unlock implementation using access-control mbx */ 5043 retry = 0; 5044 retry_unlock2: 5045 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5046 if (retry < 10) { 5047 /* Retry for IDC-unlock */ 5048 qla83xx_wait_logic(); 5049 retry++; 5050 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5051 "Failed to release IDC lock, retrying=%d\n", retry); 5052 goto retry_unlock2; 5053 } 5054 } 5055 5056 return; 5057 #endif 5058 } 5059 5060 int 5061 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5062 { 5063 int rval = QLA_SUCCESS; 5064 struct qla_hw_data *ha = vha->hw; 5065 uint32_t drv_presence; 5066 5067 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5068 if (rval == QLA_SUCCESS) { 5069 drv_presence |= (1 << ha->portnum); 5070 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5071 drv_presence); 5072 } 5073 5074 return rval; 5075 } 5076 5077 int 5078 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5079 { 5080 int rval = QLA_SUCCESS; 5081 5082 qla83xx_idc_lock(vha, 0); 5083 rval = __qla83xx_set_drv_presence(vha); 5084 qla83xx_idc_unlock(vha, 0); 5085 5086 return rval; 5087 } 5088 5089 int 5090 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5091 { 5092 int rval = QLA_SUCCESS; 5093 struct qla_hw_data *ha = vha->hw; 5094 uint32_t drv_presence; 5095 5096 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5097 if (rval == QLA_SUCCESS) { 5098 drv_presence &= ~(1 << ha->portnum); 5099 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5100 drv_presence); 5101 } 5102 5103 return rval; 5104 } 5105 5106 int 5107 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5108 { 5109 int rval = QLA_SUCCESS; 5110 5111 qla83xx_idc_lock(vha, 0); 5112 rval = __qla83xx_clear_drv_presence(vha); 5113 qla83xx_idc_unlock(vha, 0); 5114 5115 return rval; 5116 } 5117 5118 static void 5119 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5120 { 5121 struct qla_hw_data *ha = vha->hw; 5122 uint32_t drv_ack, drv_presence; 5123 unsigned long ack_timeout; 5124 5125 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5126 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5127 while (1) { 5128 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5129 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5130 if ((drv_ack & drv_presence) == drv_presence) 5131 break; 5132 5133 if (time_after_eq(jiffies, ack_timeout)) { 5134 ql_log(ql_log_warn, vha, 0xb067, 5135 "RESET ACK TIMEOUT! drv_presence=0x%x " 5136 "drv_ack=0x%x\n", drv_presence, drv_ack); 5137 /* 5138 * The function(s) which did not ack in time are forced 5139 * to withdraw any further participation in the IDC 5140 * reset. 5141 */ 5142 if (drv_ack != drv_presence) 5143 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5144 drv_ack); 5145 break; 5146 } 5147 5148 qla83xx_idc_unlock(vha, 0); 5149 msleep(1000); 5150 qla83xx_idc_lock(vha, 0); 5151 } 5152 5153 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5154 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5155 } 5156 5157 static int 5158 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5159 { 5160 int rval = QLA_SUCCESS; 5161 uint32_t idc_control; 5162 5163 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5164 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5165 5166 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5167 __qla83xx_get_idc_control(vha, &idc_control); 5168 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5169 __qla83xx_set_idc_control(vha, 0); 5170 5171 qla83xx_idc_unlock(vha, 0); 5172 rval = qla83xx_restart_nic_firmware(vha); 5173 qla83xx_idc_lock(vha, 0); 5174 5175 if (rval != QLA_SUCCESS) { 5176 ql_log(ql_log_fatal, vha, 0xb06a, 5177 "Failed to restart NIC f/w.\n"); 5178 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5179 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5180 } else { 5181 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5182 "Success in restarting nic f/w.\n"); 5183 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5184 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5185 } 5186 5187 return rval; 5188 } 5189 5190 /* Assumes idc_lock always held on entry */ 5191 int 5192 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5193 { 5194 struct qla_hw_data *ha = base_vha->hw; 5195 int rval = QLA_SUCCESS; 5196 unsigned long dev_init_timeout; 5197 uint32_t dev_state; 5198 5199 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5200 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5201 5202 while (1) { 5203 5204 if (time_after_eq(jiffies, dev_init_timeout)) { 5205 ql_log(ql_log_warn, base_vha, 0xb06e, 5206 "Initialization TIMEOUT!\n"); 5207 /* Init timeout. Disable further NIC Core 5208 * communication. 5209 */ 5210 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5211 QLA8XXX_DEV_FAILED); 5212 ql_log(ql_log_info, base_vha, 0xb06f, 5213 "HW State: FAILED.\n"); 5214 } 5215 5216 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5217 switch (dev_state) { 5218 case QLA8XXX_DEV_READY: 5219 if (ha->flags.nic_core_reset_owner) 5220 qla83xx_idc_audit(base_vha, 5221 IDC_AUDIT_COMPLETION); 5222 ha->flags.nic_core_reset_owner = 0; 5223 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5224 "Reset_owner reset by 0x%x.\n", 5225 ha->portnum); 5226 goto exit; 5227 case QLA8XXX_DEV_COLD: 5228 if (ha->flags.nic_core_reset_owner) 5229 rval = qla83xx_device_bootstrap(base_vha); 5230 else { 5231 /* Wait for AEN to change device-state */ 5232 qla83xx_idc_unlock(base_vha, 0); 5233 msleep(1000); 5234 qla83xx_idc_lock(base_vha, 0); 5235 } 5236 break; 5237 case QLA8XXX_DEV_INITIALIZING: 5238 /* Wait for AEN to change device-state */ 5239 qla83xx_idc_unlock(base_vha, 0); 5240 msleep(1000); 5241 qla83xx_idc_lock(base_vha, 0); 5242 break; 5243 case QLA8XXX_DEV_NEED_RESET: 5244 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5245 qla83xx_need_reset_handler(base_vha); 5246 else { 5247 /* Wait for AEN to change device-state */ 5248 qla83xx_idc_unlock(base_vha, 0); 5249 msleep(1000); 5250 qla83xx_idc_lock(base_vha, 0); 5251 } 5252 /* reset timeout value after need reset handler */ 5253 dev_init_timeout = jiffies + 5254 (ha->fcoe_dev_init_timeout * HZ); 5255 break; 5256 case QLA8XXX_DEV_NEED_QUIESCENT: 5257 /* XXX: DEBUG for now */ 5258 qla83xx_idc_unlock(base_vha, 0); 5259 msleep(1000); 5260 qla83xx_idc_lock(base_vha, 0); 5261 break; 5262 case QLA8XXX_DEV_QUIESCENT: 5263 /* XXX: DEBUG for now */ 5264 if (ha->flags.quiesce_owner) 5265 goto exit; 5266 5267 qla83xx_idc_unlock(base_vha, 0); 5268 msleep(1000); 5269 qla83xx_idc_lock(base_vha, 0); 5270 dev_init_timeout = jiffies + 5271 (ha->fcoe_dev_init_timeout * HZ); 5272 break; 5273 case QLA8XXX_DEV_FAILED: 5274 if (ha->flags.nic_core_reset_owner) 5275 qla83xx_idc_audit(base_vha, 5276 IDC_AUDIT_COMPLETION); 5277 ha->flags.nic_core_reset_owner = 0; 5278 __qla83xx_clear_drv_presence(base_vha); 5279 qla83xx_idc_unlock(base_vha, 0); 5280 qla8xxx_dev_failed_handler(base_vha); 5281 rval = QLA_FUNCTION_FAILED; 5282 qla83xx_idc_lock(base_vha, 0); 5283 goto exit; 5284 case QLA8XXX_BAD_VALUE: 5285 qla83xx_idc_unlock(base_vha, 0); 5286 msleep(1000); 5287 qla83xx_idc_lock(base_vha, 0); 5288 break; 5289 default: 5290 ql_log(ql_log_warn, base_vha, 0xb071, 5291 "Unknown Device State: %x.\n", dev_state); 5292 qla83xx_idc_unlock(base_vha, 0); 5293 qla8xxx_dev_failed_handler(base_vha); 5294 rval = QLA_FUNCTION_FAILED; 5295 qla83xx_idc_lock(base_vha, 0); 5296 goto exit; 5297 } 5298 } 5299 5300 exit: 5301 return rval; 5302 } 5303 5304 void 5305 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5306 { 5307 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5308 board_disable); 5309 struct pci_dev *pdev = ha->pdev; 5310 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5311 5312 /* 5313 * if UNLOAD flag is already set, then continue unload, 5314 * where it was set first. 5315 */ 5316 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5317 return; 5318 5319 ql_log(ql_log_warn, base_vha, 0x015b, 5320 "Disabling adapter.\n"); 5321 5322 qla2x00_wait_for_sess_deletion(base_vha); 5323 5324 set_bit(UNLOADING, &base_vha->dpc_flags); 5325 5326 qla2x00_delete_all_vps(ha, base_vha); 5327 5328 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5329 5330 qla2x00_dfs_remove(base_vha); 5331 5332 qla84xx_put_chip(base_vha); 5333 5334 if (base_vha->timer_active) 5335 qla2x00_stop_timer(base_vha); 5336 5337 base_vha->flags.online = 0; 5338 5339 qla2x00_destroy_deferred_work(ha); 5340 5341 /* 5342 * Do not try to stop beacon blink as it will issue a mailbox 5343 * command. 5344 */ 5345 qla2x00_free_sysfs_attr(base_vha, false); 5346 5347 fc_remove_host(base_vha->host); 5348 5349 scsi_remove_host(base_vha->host); 5350 5351 base_vha->flags.init_done = 0; 5352 qla25xx_delete_queues(base_vha); 5353 qla2x00_free_fcports(base_vha); 5354 qla2x00_free_irqs(base_vha); 5355 qla2x00_mem_free(ha); 5356 qla82xx_md_free(base_vha); 5357 qla2x00_free_queues(ha); 5358 5359 qla2x00_unmap_iobases(ha); 5360 5361 pci_release_selected_regions(ha->pdev, ha->bars); 5362 pci_disable_pcie_error_reporting(pdev); 5363 pci_disable_device(pdev); 5364 5365 /* 5366 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5367 */ 5368 } 5369 5370 /************************************************************************** 5371 * qla2x00_do_dpc 5372 * This kernel thread is a task that is schedule by the interrupt handler 5373 * to perform the background processing for interrupts. 5374 * 5375 * Notes: 5376 * This task always run in the context of a kernel thread. It 5377 * is kick-off by the driver's detect code and starts up 5378 * up one per adapter. It immediately goes to sleep and waits for 5379 * some fibre event. When either the interrupt handler or 5380 * the timer routine detects a event it will one of the task 5381 * bits then wake us up. 5382 **************************************************************************/ 5383 static int 5384 qla2x00_do_dpc(void *data) 5385 { 5386 scsi_qla_host_t *base_vha; 5387 struct qla_hw_data *ha; 5388 uint32_t online; 5389 struct qla_qpair *qpair; 5390 5391 ha = (struct qla_hw_data *)data; 5392 base_vha = pci_get_drvdata(ha->pdev); 5393 5394 set_user_nice(current, MIN_NICE); 5395 5396 set_current_state(TASK_INTERRUPTIBLE); 5397 while (!kthread_should_stop()) { 5398 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5399 "DPC handler sleeping.\n"); 5400 5401 schedule(); 5402 5403 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5404 goto end_loop; 5405 5406 if (ha->flags.eeh_busy) { 5407 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5408 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5409 goto end_loop; 5410 } 5411 5412 ha->dpc_active = 1; 5413 5414 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5415 "DPC handler waking up, dpc_flags=0x%lx.\n", 5416 base_vha->dpc_flags); 5417 5418 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5419 break; 5420 5421 qla2x00_do_work(base_vha); 5422 5423 if (IS_P3P_TYPE(ha)) { 5424 if (IS_QLA8044(ha)) { 5425 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5426 &base_vha->dpc_flags)) { 5427 qla8044_idc_lock(ha); 5428 qla8044_wr_direct(base_vha, 5429 QLA8044_CRB_DEV_STATE_INDEX, 5430 QLA8XXX_DEV_FAILED); 5431 qla8044_idc_unlock(ha); 5432 ql_log(ql_log_info, base_vha, 0x4004, 5433 "HW State: FAILED.\n"); 5434 qla8044_device_state_handler(base_vha); 5435 continue; 5436 } 5437 5438 } else { 5439 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5440 &base_vha->dpc_flags)) { 5441 qla82xx_idc_lock(ha); 5442 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5443 QLA8XXX_DEV_FAILED); 5444 qla82xx_idc_unlock(ha); 5445 ql_log(ql_log_info, base_vha, 0x0151, 5446 "HW State: FAILED.\n"); 5447 qla82xx_device_state_handler(base_vha); 5448 continue; 5449 } 5450 } 5451 5452 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5453 &base_vha->dpc_flags)) { 5454 5455 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5456 "FCoE context reset scheduled.\n"); 5457 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5458 &base_vha->dpc_flags))) { 5459 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5460 /* FCoE-ctx reset failed. 5461 * Escalate to chip-reset 5462 */ 5463 set_bit(ISP_ABORT_NEEDED, 5464 &base_vha->dpc_flags); 5465 } 5466 clear_bit(ABORT_ISP_ACTIVE, 5467 &base_vha->dpc_flags); 5468 } 5469 5470 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5471 "FCoE context reset end.\n"); 5472 } 5473 } else if (IS_QLAFX00(ha)) { 5474 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5475 &base_vha->dpc_flags)) { 5476 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5477 "Firmware Reset Recovery\n"); 5478 if (qlafx00_reset_initialize(base_vha)) { 5479 /* Failed. Abort isp later. */ 5480 if (!test_bit(UNLOADING, 5481 &base_vha->dpc_flags)) { 5482 set_bit(ISP_UNRECOVERABLE, 5483 &base_vha->dpc_flags); 5484 ql_dbg(ql_dbg_dpc, base_vha, 5485 0x4021, 5486 "Reset Recovery Failed\n"); 5487 } 5488 } 5489 } 5490 5491 if (test_and_clear_bit(FX00_TARGET_SCAN, 5492 &base_vha->dpc_flags)) { 5493 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5494 "ISPFx00 Target Scan scheduled\n"); 5495 if (qlafx00_rescan_isp(base_vha)) { 5496 if (!test_bit(UNLOADING, 5497 &base_vha->dpc_flags)) 5498 set_bit(ISP_UNRECOVERABLE, 5499 &base_vha->dpc_flags); 5500 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 5501 "ISPFx00 Target Scan Failed\n"); 5502 } 5503 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 5504 "ISPFx00 Target Scan End\n"); 5505 } 5506 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 5507 &base_vha->dpc_flags)) { 5508 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 5509 "ISPFx00 Host Info resend scheduled\n"); 5510 qlafx00_fx_disc(base_vha, 5511 &base_vha->hw->mr.fcport, 5512 FXDISC_REG_HOST_INFO); 5513 } 5514 } 5515 5516 if (test_and_clear_bit(ISP_ABORT_NEEDED, 5517 &base_vha->dpc_flags)) { 5518 5519 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 5520 "ISP abort scheduled.\n"); 5521 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5522 &base_vha->dpc_flags))) { 5523 5524 if (ha->isp_ops->abort_isp(base_vha)) { 5525 /* failed. retry later */ 5526 set_bit(ISP_ABORT_NEEDED, 5527 &base_vha->dpc_flags); 5528 } 5529 clear_bit(ABORT_ISP_ACTIVE, 5530 &base_vha->dpc_flags); 5531 } 5532 5533 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 5534 "ISP abort end.\n"); 5535 } 5536 5537 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 5538 &base_vha->dpc_flags)) { 5539 qla2x00_update_fcports(base_vha); 5540 } 5541 5542 if (IS_QLAFX00(ha)) 5543 goto loop_resync_check; 5544 5545 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 5546 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 5547 "Quiescence mode scheduled.\n"); 5548 if (IS_P3P_TYPE(ha)) { 5549 if (IS_QLA82XX(ha)) 5550 qla82xx_device_state_handler(base_vha); 5551 if (IS_QLA8044(ha)) 5552 qla8044_device_state_handler(base_vha); 5553 clear_bit(ISP_QUIESCE_NEEDED, 5554 &base_vha->dpc_flags); 5555 if (!ha->flags.quiesce_owner) { 5556 qla2x00_perform_loop_resync(base_vha); 5557 if (IS_QLA82XX(ha)) { 5558 qla82xx_idc_lock(ha); 5559 qla82xx_clear_qsnt_ready( 5560 base_vha); 5561 qla82xx_idc_unlock(ha); 5562 } else if (IS_QLA8044(ha)) { 5563 qla8044_idc_lock(ha); 5564 qla8044_clear_qsnt_ready( 5565 base_vha); 5566 qla8044_idc_unlock(ha); 5567 } 5568 } 5569 } else { 5570 clear_bit(ISP_QUIESCE_NEEDED, 5571 &base_vha->dpc_flags); 5572 qla2x00_quiesce_io(base_vha); 5573 } 5574 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 5575 "Quiescence mode end.\n"); 5576 } 5577 5578 if (test_and_clear_bit(RESET_MARKER_NEEDED, 5579 &base_vha->dpc_flags) && 5580 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 5581 5582 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 5583 "Reset marker scheduled.\n"); 5584 qla2x00_rst_aen(base_vha); 5585 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 5586 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 5587 "Reset marker end.\n"); 5588 } 5589 5590 /* Retry each device up to login retry count */ 5591 if ((test_and_clear_bit(RELOGIN_NEEDED, 5592 &base_vha->dpc_flags)) && 5593 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 5594 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 5595 5596 ql_dbg(ql_dbg_dpc, base_vha, 0x400d, 5597 "Relogin scheduled.\n"); 5598 qla2x00_relogin(base_vha); 5599 ql_dbg(ql_dbg_dpc, base_vha, 0x400e, 5600 "Relogin end.\n"); 5601 } 5602 loop_resync_check: 5603 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 5604 &base_vha->dpc_flags)) { 5605 5606 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 5607 "Loop resync scheduled.\n"); 5608 5609 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 5610 &base_vha->dpc_flags))) { 5611 5612 qla2x00_loop_resync(base_vha); 5613 5614 clear_bit(LOOP_RESYNC_ACTIVE, 5615 &base_vha->dpc_flags); 5616 } 5617 5618 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 5619 "Loop resync end.\n"); 5620 } 5621 5622 if (IS_QLAFX00(ha)) 5623 goto intr_on_check; 5624 5625 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 5626 atomic_read(&base_vha->loop_state) == LOOP_READY) { 5627 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 5628 qla2xxx_flash_npiv_conf(base_vha); 5629 } 5630 5631 intr_on_check: 5632 if (!ha->interrupts_on) 5633 ha->isp_ops->enable_intrs(ha); 5634 5635 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 5636 &base_vha->dpc_flags)) { 5637 if (ha->beacon_blink_led == 1) 5638 ha->isp_ops->beacon_blink(base_vha); 5639 } 5640 5641 /* qpair online check */ 5642 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 5643 &base_vha->dpc_flags)) { 5644 if (ha->flags.eeh_busy || 5645 ha->flags.pci_channel_io_perm_failure) 5646 online = 0; 5647 else 5648 online = 1; 5649 5650 mutex_lock(&ha->mq_lock); 5651 list_for_each_entry(qpair, &base_vha->qp_list, 5652 qp_list_elem) 5653 qpair->online = online; 5654 mutex_unlock(&ha->mq_lock); 5655 } 5656 5657 if (!IS_QLAFX00(ha)) 5658 qla2x00_do_dpc_all_vps(base_vha); 5659 5660 ha->dpc_active = 0; 5661 end_loop: 5662 set_current_state(TASK_INTERRUPTIBLE); 5663 } /* End of while(1) */ 5664 __set_current_state(TASK_RUNNING); 5665 5666 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 5667 "DPC handler exiting.\n"); 5668 5669 /* 5670 * Make sure that nobody tries to wake us up again. 5671 */ 5672 ha->dpc_active = 0; 5673 5674 /* Cleanup any residual CTX SRBs. */ 5675 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5676 5677 return 0; 5678 } 5679 5680 void 5681 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 5682 { 5683 struct qla_hw_data *ha = vha->hw; 5684 struct task_struct *t = ha->dpc_thread; 5685 5686 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 5687 wake_up_process(t); 5688 } 5689 5690 /* 5691 * qla2x00_rst_aen 5692 * Processes asynchronous reset. 5693 * 5694 * Input: 5695 * ha = adapter block pointer. 5696 */ 5697 static void 5698 qla2x00_rst_aen(scsi_qla_host_t *vha) 5699 { 5700 if (vha->flags.online && !vha->flags.reset_active && 5701 !atomic_read(&vha->loop_down_timer) && 5702 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 5703 do { 5704 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5705 5706 /* 5707 * Issue marker command only when we are going to start 5708 * the I/O. 5709 */ 5710 vha->marker_needed = 1; 5711 } while (!atomic_read(&vha->loop_down_timer) && 5712 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 5713 } 5714 } 5715 5716 /************************************************************************** 5717 * qla2x00_timer 5718 * 5719 * Description: 5720 * One second timer 5721 * 5722 * Context: Interrupt 5723 ***************************************************************************/ 5724 void 5725 qla2x00_timer(scsi_qla_host_t *vha) 5726 { 5727 unsigned long cpu_flags = 0; 5728 int start_dpc = 0; 5729 int index; 5730 srb_t *sp; 5731 uint16_t w; 5732 struct qla_hw_data *ha = vha->hw; 5733 struct req_que *req; 5734 5735 if (ha->flags.eeh_busy) { 5736 ql_dbg(ql_dbg_timer, vha, 0x6000, 5737 "EEH = %d, restarting timer.\n", 5738 ha->flags.eeh_busy); 5739 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5740 return; 5741 } 5742 5743 /* 5744 * Hardware read to raise pending EEH errors during mailbox waits. If 5745 * the read returns -1 then disable the board. 5746 */ 5747 if (!pci_channel_offline(ha->pdev)) { 5748 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 5749 qla2x00_check_reg16_for_disconnect(vha, w); 5750 } 5751 5752 /* Make sure qla82xx_watchdog is run only for physical port */ 5753 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 5754 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 5755 start_dpc++; 5756 if (IS_QLA82XX(ha)) 5757 qla82xx_watchdog(vha); 5758 else if (IS_QLA8044(ha)) 5759 qla8044_watchdog(vha); 5760 } 5761 5762 if (!vha->vp_idx && IS_QLAFX00(ha)) 5763 qlafx00_timer_routine(vha); 5764 5765 /* Loop down handler. */ 5766 if (atomic_read(&vha->loop_down_timer) > 0 && 5767 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 5768 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 5769 && vha->flags.online) { 5770 5771 if (atomic_read(&vha->loop_down_timer) == 5772 vha->loop_down_abort_time) { 5773 5774 ql_log(ql_log_info, vha, 0x6008, 5775 "Loop down - aborting the queues before time expires.\n"); 5776 5777 if (!IS_QLA2100(ha) && vha->link_down_timeout) 5778 atomic_set(&vha->loop_state, LOOP_DEAD); 5779 5780 /* 5781 * Schedule an ISP abort to return any FCP2-device 5782 * commands. 5783 */ 5784 /* NPIV - scan physical port only */ 5785 if (!vha->vp_idx) { 5786 spin_lock_irqsave(&ha->hardware_lock, 5787 cpu_flags); 5788 req = ha->req_q_map[0]; 5789 for (index = 1; 5790 index < req->num_outstanding_cmds; 5791 index++) { 5792 fc_port_t *sfcp; 5793 5794 sp = req->outstanding_cmds[index]; 5795 if (!sp) 5796 continue; 5797 if (sp->type != SRB_SCSI_CMD) 5798 continue; 5799 sfcp = sp->fcport; 5800 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 5801 continue; 5802 5803 if (IS_QLA82XX(ha)) 5804 set_bit(FCOE_CTX_RESET_NEEDED, 5805 &vha->dpc_flags); 5806 else 5807 set_bit(ISP_ABORT_NEEDED, 5808 &vha->dpc_flags); 5809 break; 5810 } 5811 spin_unlock_irqrestore(&ha->hardware_lock, 5812 cpu_flags); 5813 } 5814 start_dpc++; 5815 } 5816 5817 /* if the loop has been down for 4 minutes, reinit adapter */ 5818 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 5819 if (!(vha->device_flags & DFLG_NO_CABLE)) { 5820 ql_log(ql_log_warn, vha, 0x6009, 5821 "Loop down - aborting ISP.\n"); 5822 5823 if (IS_QLA82XX(ha)) 5824 set_bit(FCOE_CTX_RESET_NEEDED, 5825 &vha->dpc_flags); 5826 else 5827 set_bit(ISP_ABORT_NEEDED, 5828 &vha->dpc_flags); 5829 } 5830 } 5831 ql_dbg(ql_dbg_timer, vha, 0x600a, 5832 "Loop down - seconds remaining %d.\n", 5833 atomic_read(&vha->loop_down_timer)); 5834 } 5835 /* Check if beacon LED needs to be blinked for physical host only */ 5836 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 5837 /* There is no beacon_blink function for ISP82xx */ 5838 if (!IS_P3P_TYPE(ha)) { 5839 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 5840 start_dpc++; 5841 } 5842 } 5843 5844 /* Process any deferred work. */ 5845 if (!list_empty(&vha->work_list)) 5846 start_dpc++; 5847 5848 /* Schedule the DPC routine if needed */ 5849 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 5850 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 5851 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 5852 start_dpc || 5853 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 5854 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 5855 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 5856 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 5857 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 5858 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 5859 ql_dbg(ql_dbg_timer, vha, 0x600b, 5860 "isp_abort_needed=%d loop_resync_needed=%d " 5861 "fcport_update_needed=%d start_dpc=%d " 5862 "reset_marker_needed=%d", 5863 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 5864 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 5865 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 5866 start_dpc, 5867 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 5868 ql_dbg(ql_dbg_timer, vha, 0x600c, 5869 "beacon_blink_needed=%d isp_unrecoverable=%d " 5870 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 5871 "relogin_needed=%d.\n", 5872 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 5873 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 5874 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 5875 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 5876 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 5877 qla2xxx_wake_dpc(vha); 5878 } 5879 5880 qla2x00_restart_timer(vha, WATCH_INTERVAL); 5881 } 5882 5883 /* Firmware interface routines. */ 5884 5885 #define FW_BLOBS 11 5886 #define FW_ISP21XX 0 5887 #define FW_ISP22XX 1 5888 #define FW_ISP2300 2 5889 #define FW_ISP2322 3 5890 #define FW_ISP24XX 4 5891 #define FW_ISP25XX 5 5892 #define FW_ISP81XX 6 5893 #define FW_ISP82XX 7 5894 #define FW_ISP2031 8 5895 #define FW_ISP8031 9 5896 #define FW_ISP27XX 10 5897 5898 #define FW_FILE_ISP21XX "ql2100_fw.bin" 5899 #define FW_FILE_ISP22XX "ql2200_fw.bin" 5900 #define FW_FILE_ISP2300 "ql2300_fw.bin" 5901 #define FW_FILE_ISP2322 "ql2322_fw.bin" 5902 #define FW_FILE_ISP24XX "ql2400_fw.bin" 5903 #define FW_FILE_ISP25XX "ql2500_fw.bin" 5904 #define FW_FILE_ISP81XX "ql8100_fw.bin" 5905 #define FW_FILE_ISP82XX "ql8200_fw.bin" 5906 #define FW_FILE_ISP2031 "ql2600_fw.bin" 5907 #define FW_FILE_ISP8031 "ql8300_fw.bin" 5908 #define FW_FILE_ISP27XX "ql2700_fw.bin" 5909 5910 5911 static DEFINE_MUTEX(qla_fw_lock); 5912 5913 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 5914 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 5915 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 5916 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 5917 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 5918 { .name = FW_FILE_ISP24XX, }, 5919 { .name = FW_FILE_ISP25XX, }, 5920 { .name = FW_FILE_ISP81XX, }, 5921 { .name = FW_FILE_ISP82XX, }, 5922 { .name = FW_FILE_ISP2031, }, 5923 { .name = FW_FILE_ISP8031, }, 5924 { .name = FW_FILE_ISP27XX, }, 5925 }; 5926 5927 struct fw_blob * 5928 qla2x00_request_firmware(scsi_qla_host_t *vha) 5929 { 5930 struct qla_hw_data *ha = vha->hw; 5931 struct fw_blob *blob; 5932 5933 if (IS_QLA2100(ha)) { 5934 blob = &qla_fw_blobs[FW_ISP21XX]; 5935 } else if (IS_QLA2200(ha)) { 5936 blob = &qla_fw_blobs[FW_ISP22XX]; 5937 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 5938 blob = &qla_fw_blobs[FW_ISP2300]; 5939 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 5940 blob = &qla_fw_blobs[FW_ISP2322]; 5941 } else if (IS_QLA24XX_TYPE(ha)) { 5942 blob = &qla_fw_blobs[FW_ISP24XX]; 5943 } else if (IS_QLA25XX(ha)) { 5944 blob = &qla_fw_blobs[FW_ISP25XX]; 5945 } else if (IS_QLA81XX(ha)) { 5946 blob = &qla_fw_blobs[FW_ISP81XX]; 5947 } else if (IS_QLA82XX(ha)) { 5948 blob = &qla_fw_blobs[FW_ISP82XX]; 5949 } else if (IS_QLA2031(ha)) { 5950 blob = &qla_fw_blobs[FW_ISP2031]; 5951 } else if (IS_QLA8031(ha)) { 5952 blob = &qla_fw_blobs[FW_ISP8031]; 5953 } else if (IS_QLA27XX(ha)) { 5954 blob = &qla_fw_blobs[FW_ISP27XX]; 5955 } else { 5956 return NULL; 5957 } 5958 5959 mutex_lock(&qla_fw_lock); 5960 if (blob->fw) 5961 goto out; 5962 5963 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 5964 ql_log(ql_log_warn, vha, 0x0063, 5965 "Failed to load firmware image (%s).\n", blob->name); 5966 blob->fw = NULL; 5967 blob = NULL; 5968 goto out; 5969 } 5970 5971 out: 5972 mutex_unlock(&qla_fw_lock); 5973 return blob; 5974 } 5975 5976 static void 5977 qla2x00_release_firmware(void) 5978 { 5979 int idx; 5980 5981 mutex_lock(&qla_fw_lock); 5982 for (idx = 0; idx < FW_BLOBS; idx++) 5983 release_firmware(qla_fw_blobs[idx].fw); 5984 mutex_unlock(&qla_fw_lock); 5985 } 5986 5987 static pci_ers_result_t 5988 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 5989 { 5990 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 5991 struct qla_hw_data *ha = vha->hw; 5992 5993 ql_dbg(ql_dbg_aer, vha, 0x9000, 5994 "PCI error detected, state %x.\n", state); 5995 5996 switch (state) { 5997 case pci_channel_io_normal: 5998 ha->flags.eeh_busy = 0; 5999 if (ql2xmqsupport) { 6000 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6001 qla2xxx_wake_dpc(vha); 6002 } 6003 return PCI_ERS_RESULT_CAN_RECOVER; 6004 case pci_channel_io_frozen: 6005 ha->flags.eeh_busy = 1; 6006 /* For ISP82XX complete any pending mailbox cmd */ 6007 if (IS_QLA82XX(ha)) { 6008 ha->flags.isp82xx_fw_hung = 1; 6009 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6010 qla82xx_clear_pending_mbx(vha); 6011 } 6012 qla2x00_free_irqs(vha); 6013 pci_disable_device(pdev); 6014 /* Return back all IOs */ 6015 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6016 if (ql2xmqsupport) { 6017 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6018 qla2xxx_wake_dpc(vha); 6019 } 6020 return PCI_ERS_RESULT_NEED_RESET; 6021 case pci_channel_io_perm_failure: 6022 ha->flags.pci_channel_io_perm_failure = 1; 6023 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6024 if (ql2xmqsupport) { 6025 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6026 qla2xxx_wake_dpc(vha); 6027 } 6028 return PCI_ERS_RESULT_DISCONNECT; 6029 } 6030 return PCI_ERS_RESULT_NEED_RESET; 6031 } 6032 6033 static pci_ers_result_t 6034 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6035 { 6036 int risc_paused = 0; 6037 uint32_t stat; 6038 unsigned long flags; 6039 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6040 struct qla_hw_data *ha = base_vha->hw; 6041 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6042 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6043 6044 if (IS_QLA82XX(ha)) 6045 return PCI_ERS_RESULT_RECOVERED; 6046 6047 spin_lock_irqsave(&ha->hardware_lock, flags); 6048 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6049 stat = RD_REG_DWORD(®->hccr); 6050 if (stat & HCCR_RISC_PAUSE) 6051 risc_paused = 1; 6052 } else if (IS_QLA23XX(ha)) { 6053 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6054 if (stat & HSR_RISC_PAUSED) 6055 risc_paused = 1; 6056 } else if (IS_FWI2_CAPABLE(ha)) { 6057 stat = RD_REG_DWORD(®24->host_status); 6058 if (stat & HSRX_RISC_PAUSED) 6059 risc_paused = 1; 6060 } 6061 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6062 6063 if (risc_paused) { 6064 ql_log(ql_log_info, base_vha, 0x9003, 6065 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6066 ha->isp_ops->fw_dump(base_vha, 0); 6067 6068 return PCI_ERS_RESULT_NEED_RESET; 6069 } else 6070 return PCI_ERS_RESULT_RECOVERED; 6071 } 6072 6073 static uint32_t 6074 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6075 { 6076 uint32_t rval = QLA_FUNCTION_FAILED; 6077 uint32_t drv_active = 0; 6078 struct qla_hw_data *ha = base_vha->hw; 6079 int fn; 6080 struct pci_dev *other_pdev = NULL; 6081 6082 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6083 "Entered %s.\n", __func__); 6084 6085 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6086 6087 if (base_vha->flags.online) { 6088 /* Abort all outstanding commands, 6089 * so as to be requeued later */ 6090 qla2x00_abort_isp_cleanup(base_vha); 6091 } 6092 6093 6094 fn = PCI_FUNC(ha->pdev->devfn); 6095 while (fn > 0) { 6096 fn--; 6097 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6098 "Finding pci device at function = 0x%x.\n", fn); 6099 other_pdev = 6100 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6101 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6102 fn)); 6103 6104 if (!other_pdev) 6105 continue; 6106 if (atomic_read(&other_pdev->enable_cnt)) { 6107 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6108 "Found PCI func available and enable at 0x%x.\n", 6109 fn); 6110 pci_dev_put(other_pdev); 6111 break; 6112 } 6113 pci_dev_put(other_pdev); 6114 } 6115 6116 if (!fn) { 6117 /* Reset owner */ 6118 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6119 "This devfn is reset owner = 0x%x.\n", 6120 ha->pdev->devfn); 6121 qla82xx_idc_lock(ha); 6122 6123 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6124 QLA8XXX_DEV_INITIALIZING); 6125 6126 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6127 QLA82XX_IDC_VERSION); 6128 6129 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6130 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6131 "drv_active = 0x%x.\n", drv_active); 6132 6133 qla82xx_idc_unlock(ha); 6134 /* Reset if device is not already reset 6135 * drv_active would be 0 if a reset has already been done 6136 */ 6137 if (drv_active) 6138 rval = qla82xx_start_firmware(base_vha); 6139 else 6140 rval = QLA_SUCCESS; 6141 qla82xx_idc_lock(ha); 6142 6143 if (rval != QLA_SUCCESS) { 6144 ql_log(ql_log_info, base_vha, 0x900b, 6145 "HW State: FAILED.\n"); 6146 qla82xx_clear_drv_active(ha); 6147 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6148 QLA8XXX_DEV_FAILED); 6149 } else { 6150 ql_log(ql_log_info, base_vha, 0x900c, 6151 "HW State: READY.\n"); 6152 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6153 QLA8XXX_DEV_READY); 6154 qla82xx_idc_unlock(ha); 6155 ha->flags.isp82xx_fw_hung = 0; 6156 rval = qla82xx_restart_isp(base_vha); 6157 qla82xx_idc_lock(ha); 6158 /* Clear driver state register */ 6159 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6160 qla82xx_set_drv_active(base_vha); 6161 } 6162 qla82xx_idc_unlock(ha); 6163 } else { 6164 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6165 "This devfn is not reset owner = 0x%x.\n", 6166 ha->pdev->devfn); 6167 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6168 QLA8XXX_DEV_READY)) { 6169 ha->flags.isp82xx_fw_hung = 0; 6170 rval = qla82xx_restart_isp(base_vha); 6171 qla82xx_idc_lock(ha); 6172 qla82xx_set_drv_active(base_vha); 6173 qla82xx_idc_unlock(ha); 6174 } 6175 } 6176 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6177 6178 return rval; 6179 } 6180 6181 static pci_ers_result_t 6182 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6183 { 6184 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6185 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6186 struct qla_hw_data *ha = base_vha->hw; 6187 struct rsp_que *rsp; 6188 int rc, retries = 10; 6189 6190 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6191 "Slot Reset.\n"); 6192 6193 /* Workaround: qla2xxx driver which access hardware earlier 6194 * needs error state to be pci_channel_io_online. 6195 * Otherwise mailbox command timesout. 6196 */ 6197 pdev->error_state = pci_channel_io_normal; 6198 6199 pci_restore_state(pdev); 6200 6201 /* pci_restore_state() clears the saved_state flag of the device 6202 * save restored state which resets saved_state flag 6203 */ 6204 pci_save_state(pdev); 6205 6206 if (ha->mem_only) 6207 rc = pci_enable_device_mem(pdev); 6208 else 6209 rc = pci_enable_device(pdev); 6210 6211 if (rc) { 6212 ql_log(ql_log_warn, base_vha, 0x9005, 6213 "Can't re-enable PCI device after reset.\n"); 6214 goto exit_slot_reset; 6215 } 6216 6217 rsp = ha->rsp_q_map[0]; 6218 if (qla2x00_request_irqs(ha, rsp)) 6219 goto exit_slot_reset; 6220 6221 if (ha->isp_ops->pci_config(base_vha)) 6222 goto exit_slot_reset; 6223 6224 if (IS_QLA82XX(ha)) { 6225 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6226 ret = PCI_ERS_RESULT_RECOVERED; 6227 goto exit_slot_reset; 6228 } else 6229 goto exit_slot_reset; 6230 } 6231 6232 while (ha->flags.mbox_busy && retries--) 6233 msleep(1000); 6234 6235 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6236 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6237 ret = PCI_ERS_RESULT_RECOVERED; 6238 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6239 6240 6241 exit_slot_reset: 6242 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6243 "slot_reset return %x.\n", ret); 6244 6245 return ret; 6246 } 6247 6248 static void 6249 qla2xxx_pci_resume(struct pci_dev *pdev) 6250 { 6251 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6252 struct qla_hw_data *ha = base_vha->hw; 6253 int ret; 6254 6255 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6256 "pci_resume.\n"); 6257 6258 ret = qla2x00_wait_for_hba_online(base_vha); 6259 if (ret != QLA_SUCCESS) { 6260 ql_log(ql_log_fatal, base_vha, 0x9002, 6261 "The device failed to resume I/O from slot/link_reset.\n"); 6262 } 6263 6264 pci_cleanup_aer_uncorrect_error_status(pdev); 6265 6266 ha->flags.eeh_busy = 0; 6267 } 6268 6269 static void 6270 qla83xx_disable_laser(scsi_qla_host_t *vha) 6271 { 6272 uint32_t reg, data, fn; 6273 struct qla_hw_data *ha = vha->hw; 6274 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; 6275 6276 /* pci func #/port # */ 6277 ql_dbg(ql_dbg_init, vha, 0x004b, 6278 "Disabling Laser for hba: %p\n", vha); 6279 6280 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & 6281 (BIT_15|BIT_14|BIT_13|BIT_12)); 6282 6283 fn = (fn >> 12); 6284 6285 if (fn & 1) 6286 reg = PORT_1_2031; 6287 else 6288 reg = PORT_0_2031; 6289 6290 data = LASER_OFF_2031; 6291 6292 qla83xx_wr_reg(vha, reg, data); 6293 } 6294 6295 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6296 { 6297 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6298 6299 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); 6300 } 6301 6302 static const struct pci_error_handlers qla2xxx_err_handler = { 6303 .error_detected = qla2xxx_pci_error_detected, 6304 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6305 .slot_reset = qla2xxx_pci_slot_reset, 6306 .resume = qla2xxx_pci_resume, 6307 }; 6308 6309 static struct pci_device_id qla2xxx_pci_tbl[] = { 6310 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6332 { 0 }, 6333 }; 6334 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6335 6336 static struct pci_driver qla2xxx_pci_driver = { 6337 .name = QLA2XXX_DRIVER_NAME, 6338 .driver = { 6339 .owner = THIS_MODULE, 6340 }, 6341 .id_table = qla2xxx_pci_tbl, 6342 .probe = qla2x00_probe_one, 6343 .remove = qla2x00_remove_one, 6344 .shutdown = qla2x00_shutdown, 6345 .err_handler = &qla2xxx_err_handler, 6346 }; 6347 6348 static const struct file_operations apidev_fops = { 6349 .owner = THIS_MODULE, 6350 .llseek = noop_llseek, 6351 }; 6352 6353 /** 6354 * qla2x00_module_init - Module initialization. 6355 **/ 6356 static int __init 6357 qla2x00_module_init(void) 6358 { 6359 int ret = 0; 6360 6361 /* Allocate cache for SRBs. */ 6362 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6363 SLAB_HWCACHE_ALIGN, NULL); 6364 if (srb_cachep == NULL) { 6365 ql_log(ql_log_fatal, NULL, 0x0001, 6366 "Unable to allocate SRB cache...Failing load!.\n"); 6367 return -ENOMEM; 6368 } 6369 6370 /* Initialize target kmem_cache and mem_pools */ 6371 ret = qlt_init(); 6372 if (ret < 0) { 6373 kmem_cache_destroy(srb_cachep); 6374 return ret; 6375 } else if (ret > 0) { 6376 /* 6377 * If initiator mode is explictly disabled by qlt_init(), 6378 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6379 * performing scsi_scan_target() during LOOP UP event. 6380 */ 6381 qla2xxx_transport_functions.disable_target_scan = 1; 6382 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6383 } 6384 6385 /* Derive version string. */ 6386 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6387 if (ql2xextended_error_logging) 6388 strcat(qla2x00_version_str, "-debug"); 6389 6390 qla2xxx_transport_template = 6391 fc_attach_transport(&qla2xxx_transport_functions); 6392 if (!qla2xxx_transport_template) { 6393 kmem_cache_destroy(srb_cachep); 6394 ql_log(ql_log_fatal, NULL, 0x0002, 6395 "fc_attach_transport failed...Failing load!.\n"); 6396 qlt_exit(); 6397 return -ENODEV; 6398 } 6399 6400 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6401 if (apidev_major < 0) { 6402 ql_log(ql_log_fatal, NULL, 0x0003, 6403 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6404 } 6405 6406 qla2xxx_transport_vport_template = 6407 fc_attach_transport(&qla2xxx_transport_vport_functions); 6408 if (!qla2xxx_transport_vport_template) { 6409 kmem_cache_destroy(srb_cachep); 6410 qlt_exit(); 6411 fc_release_transport(qla2xxx_transport_template); 6412 ql_log(ql_log_fatal, NULL, 0x0004, 6413 "fc_attach_transport vport failed...Failing load!.\n"); 6414 return -ENODEV; 6415 } 6416 ql_log(ql_log_info, NULL, 0x0005, 6417 "QLogic Fibre Channel HBA Driver: %s.\n", 6418 qla2x00_version_str); 6419 ret = pci_register_driver(&qla2xxx_pci_driver); 6420 if (ret) { 6421 kmem_cache_destroy(srb_cachep); 6422 qlt_exit(); 6423 fc_release_transport(qla2xxx_transport_template); 6424 fc_release_transport(qla2xxx_transport_vport_template); 6425 ql_log(ql_log_fatal, NULL, 0x0006, 6426 "pci_register_driver failed...ret=%d Failing load!.\n", 6427 ret); 6428 } 6429 return ret; 6430 } 6431 6432 /** 6433 * qla2x00_module_exit - Module cleanup. 6434 **/ 6435 static void __exit 6436 qla2x00_module_exit(void) 6437 { 6438 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6439 pci_unregister_driver(&qla2xxx_pci_driver); 6440 qla2x00_release_firmware(); 6441 kmem_cache_destroy(srb_cachep); 6442 qlt_exit(); 6443 if (ctx_cachep) 6444 kmem_cache_destroy(ctx_cachep); 6445 fc_release_transport(qla2xxx_transport_template); 6446 fc_release_transport(qla2xxx_transport_vport_template); 6447 } 6448 6449 module_init(qla2x00_module_init); 6450 module_exit(qla2x00_module_exit); 6451 6452 MODULE_AUTHOR("QLogic Corporation"); 6453 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6454 MODULE_LICENSE("GPL"); 6455 MODULE_VERSION(QLA2XXX_VERSION); 6456 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6457 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6458 MODULE_FIRMWARE(FW_FILE_ISP2300); 6459 MODULE_FIRMWARE(FW_FILE_ISP2322); 6460 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6461 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6462