1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 int ql_errlev = ql_log_all; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount = 0; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable=1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI. Default is 1 - perform FDMI."); 117 118 #define MAX_Q_DEPTH 64 119 static int ql2xmaxqdepth = MAX_Q_DEPTH; 120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xmaxqdepth, 122 "Maximum queue depth to set for each LUN. " 123 "Default is 64."); 124 125 #if (IS_ENABLED(CONFIG_NVME_FC)) 126 int ql2xenabledif; 127 #else 128 int ql2xenabledif = 2; 129 #endif 130 module_param(ql2xenabledif, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xenabledif, 132 " Enable T10-CRC-DIF:\n" 133 " Default is 2.\n" 134 " 0 -- No DIF Support\n" 135 " 1 -- Enable DIF for all types\n" 136 " 2 -- Enable DIF for all types, except Type 0.\n"); 137 138 #if (IS_ENABLED(CONFIG_NVME_FC)) 139 int ql2xnvmeenable = 1; 140 #else 141 int ql2xnvmeenable; 142 #endif 143 module_param(ql2xnvmeenable, int, 0644); 144 MODULE_PARM_DESC(ql2xnvmeenable, 145 "Enables NVME support. " 146 "0 - no NVMe. Default is Y"); 147 148 int ql2xenablehba_err_chk = 2; 149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xenablehba_err_chk, 151 " Enable T10-CRC-DIF Error isolation by HBA:\n" 152 " Default is 2.\n" 153 " 0 -- Error isolation disabled\n" 154 " 1 -- Error isolation enabled only for DIX Type 0\n" 155 " 2 -- Error isolation enabled for all Types\n"); 156 157 int ql2xiidmaenable=1; 158 module_param(ql2xiidmaenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xiidmaenable, 160 "Enables iIDMA settings " 161 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 162 163 int ql2xmqsupport = 1; 164 module_param(ql2xmqsupport, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xmqsupport, 166 "Enable on demand multiple queue pairs support " 167 "Default is 1 for supported. " 168 "Set it to 0 to turn off mq qpair support."); 169 170 int ql2xfwloadbin; 171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xfwloadbin, 174 "Option to specify location from which to load ISP firmware:.\n" 175 " 2 -- load firmware via the request_firmware() (hotplug).\n" 176 " interface.\n" 177 " 1 -- load firmware from flash.\n" 178 " 0 -- use default semantics.\n"); 179 180 int ql2xetsenable; 181 module_param(ql2xetsenable, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xetsenable, 183 "Enables firmware ETS burst." 184 "Default is 0 - skip ETS enablement."); 185 186 int ql2xdbwr = 1; 187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 188 MODULE_PARM_DESC(ql2xdbwr, 189 "Option to specify scheme for request queue posting.\n" 190 " 0 -- Regular doorbell.\n" 191 " 1 -- CAMRAM doorbell (faster).\n"); 192 193 int ql2xtargetreset = 1; 194 module_param(ql2xtargetreset, int, S_IRUGO); 195 MODULE_PARM_DESC(ql2xtargetreset, 196 "Enable target reset." 197 "Default is 1 - use hw defaults."); 198 199 int ql2xgffidenable; 200 module_param(ql2xgffidenable, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xgffidenable, 202 "Enables GFF_ID checks of port type. " 203 "Default is 0 - Do not use GFF_ID information."); 204 205 int ql2xasynctmfenable = 1; 206 module_param(ql2xasynctmfenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xasynctmfenable, 208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 210 211 int ql2xdontresethba; 212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 213 MODULE_PARM_DESC(ql2xdontresethba, 214 "Option to specify reset behaviour.\n" 215 " 0 (Default) -- Reset on failure.\n" 216 " 1 -- Do not reset on failure.\n"); 217 218 uint64_t ql2xmaxlun = MAX_LUNS; 219 module_param(ql2xmaxlun, ullong, S_IRUGO); 220 MODULE_PARM_DESC(ql2xmaxlun, 221 "Defines the maximum LU number to register with the SCSI " 222 "midlayer. Default is 65535."); 223 224 int ql2xmdcapmask = 0x1F; 225 module_param(ql2xmdcapmask, int, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmdcapmask, 227 "Set the Minidump driver capture mask level. " 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 229 230 int ql2xmdenable = 1; 231 module_param(ql2xmdenable, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdenable, 233 "Enable/disable MiniDump. " 234 "0 - MiniDump disabled. " 235 "1 (Default) - MiniDump enabled."); 236 237 int ql2xexlogins = 0; 238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 239 MODULE_PARM_DESC(ql2xexlogins, 240 "Number of extended Logins. " 241 "0 (Default)- Disabled."); 242 243 int ql2xexchoffld = 1024; 244 module_param(ql2xexchoffld, uint, 0644); 245 MODULE_PARM_DESC(ql2xexchoffld, 246 "Number of target exchanges."); 247 248 int ql2xiniexchg = 1024; 249 module_param(ql2xiniexchg, uint, 0644); 250 MODULE_PARM_DESC(ql2xiniexchg, 251 "Number of initiator exchanges."); 252 253 int ql2xfwholdabts = 0; 254 module_param(ql2xfwholdabts, int, S_IRUGO); 255 MODULE_PARM_DESC(ql2xfwholdabts, 256 "Allow FW to hold status IOCB until ABTS rsp received. " 257 "0 (Default) Do not set fw option. " 258 "1 - Set fw option to hold ABTS."); 259 260 int ql2xmvasynctoatio = 1; 261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 262 MODULE_PARM_DESC(ql2xmvasynctoatio, 263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 264 "0 (Default). Do not move IOCBs" 265 "1 - Move IOCBs."); 266 267 int ql2xautodetectsfp = 1; 268 module_param(ql2xautodetectsfp, int, 0444); 269 MODULE_PARM_DESC(ql2xautodetectsfp, 270 "Detect SFP range and set appropriate distance.\n" 271 "1 (Default): Enable\n"); 272 273 int ql2xenablemsix = 1; 274 module_param(ql2xenablemsix, int, 0444); 275 MODULE_PARM_DESC(ql2xenablemsix, 276 "Set to enable MSI or MSI-X interrupt mechanism.\n" 277 " Default is 1, enable MSI-X interrupt mechanism.\n" 278 " 0 -- enable traditional pin-based mechanism.\n" 279 " 1 -- enable MSI-X interrupt mechanism.\n" 280 " 2 -- enable MSI interrupt mechanism.\n"); 281 282 int qla2xuseresexchforels; 283 module_param(qla2xuseresexchforels, int, 0444); 284 MODULE_PARM_DESC(qla2xuseresexchforels, 285 "Reserve 1/2 of emergency exchanges for ELS.\n" 286 " 0 (default): disabled"); 287 288 /* 289 * SCSI host template entry points 290 */ 291 static int qla2xxx_slave_configure(struct scsi_device * device); 292 static int qla2xxx_slave_alloc(struct scsi_device *); 293 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 294 static void qla2xxx_scan_start(struct Scsi_Host *); 295 static void qla2xxx_slave_destroy(struct scsi_device *); 296 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 297 static int qla2xxx_eh_abort(struct scsi_cmnd *); 298 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 300 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 301 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 302 303 static void qla2x00_clear_drv_active(struct qla_hw_data *); 304 static void qla2x00_free_device(scsi_qla_host_t *); 305 static int qla2xxx_map_queues(struct Scsi_Host *shost); 306 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 307 308 309 struct scsi_host_template qla2xxx_driver_template = { 310 .module = THIS_MODULE, 311 .name = QLA2XXX_DRIVER_NAME, 312 .queuecommand = qla2xxx_queuecommand, 313 314 .eh_timed_out = fc_eh_timed_out, 315 .eh_abort_handler = qla2xxx_eh_abort, 316 .eh_device_reset_handler = qla2xxx_eh_device_reset, 317 .eh_target_reset_handler = qla2xxx_eh_target_reset, 318 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 319 .eh_host_reset_handler = qla2xxx_eh_host_reset, 320 321 .slave_configure = qla2xxx_slave_configure, 322 323 .slave_alloc = qla2xxx_slave_alloc, 324 .slave_destroy = qla2xxx_slave_destroy, 325 .scan_finished = qla2xxx_scan_finished, 326 .scan_start = qla2xxx_scan_start, 327 .change_queue_depth = scsi_change_queue_depth, 328 .map_queues = qla2xxx_map_queues, 329 .this_id = -1, 330 .cmd_per_lun = 3, 331 .use_clustering = ENABLE_CLUSTERING, 332 .sg_tablesize = SG_ALL, 333 334 .max_sectors = 0xFFFF, 335 .shost_attrs = qla2x00_host_attrs, 336 337 .supported_mode = MODE_INITIATOR, 338 .track_queue_depth = 1, 339 }; 340 341 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 342 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 343 344 /* TODO Convert to inlines 345 * 346 * Timer routines 347 */ 348 349 __inline__ void 350 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 351 { 352 timer_setup(&vha->timer, qla2x00_timer, 0); 353 vha->timer.expires = jiffies + interval * HZ; 354 add_timer(&vha->timer); 355 vha->timer_active = 1; 356 } 357 358 static inline void 359 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 360 { 361 /* Currently used for 82XX only. */ 362 if (vha->device_flags & DFLG_DEV_FAILED) { 363 ql_dbg(ql_dbg_timer, vha, 0x600d, 364 "Device in a failed state, returning.\n"); 365 return; 366 } 367 368 mod_timer(&vha->timer, jiffies + interval * HZ); 369 } 370 371 static __inline__ void 372 qla2x00_stop_timer(scsi_qla_host_t *vha) 373 { 374 del_timer_sync(&vha->timer); 375 vha->timer_active = 0; 376 } 377 378 static int qla2x00_do_dpc(void *data); 379 380 static void qla2x00_rst_aen(scsi_qla_host_t *); 381 382 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 383 struct req_que **, struct rsp_que **); 384 static void qla2x00_free_fw_dump(struct qla_hw_data *); 385 static void qla2x00_mem_free(struct qla_hw_data *); 386 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 387 struct qla_qpair *qpair); 388 389 /* -------------------------------------------------------------------------- */ 390 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 391 struct rsp_que *rsp) 392 { 393 struct qla_hw_data *ha = vha->hw; 394 rsp->qpair = ha->base_qpair; 395 rsp->req = req; 396 ha->base_qpair->hw = ha; 397 ha->base_qpair->req = req; 398 ha->base_qpair->rsp = rsp; 399 ha->base_qpair->vha = vha; 400 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 401 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 402 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 403 ha->base_qpair->srb_mempool = ha->srb_mempool; 404 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 405 ha->base_qpair->enable_class_2 = ql2xenableclass2; 406 /* init qpair to this cpu. Will adjust at run time. */ 407 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 408 ha->base_qpair->pdev = ha->pdev; 409 410 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 411 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 412 } 413 414 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 415 struct rsp_que *rsp) 416 { 417 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 418 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 419 GFP_KERNEL); 420 if (!ha->req_q_map) { 421 ql_log(ql_log_fatal, vha, 0x003b, 422 "Unable to allocate memory for request queue ptrs.\n"); 423 goto fail_req_map; 424 } 425 426 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 427 GFP_KERNEL); 428 if (!ha->rsp_q_map) { 429 ql_log(ql_log_fatal, vha, 0x003c, 430 "Unable to allocate memory for response queue ptrs.\n"); 431 goto fail_rsp_map; 432 } 433 434 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 435 if (ha->base_qpair == NULL) { 436 ql_log(ql_log_warn, vha, 0x00e0, 437 "Failed to allocate base queue pair memory.\n"); 438 goto fail_base_qpair; 439 } 440 441 qla_init_base_qpair(vha, req, rsp); 442 443 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 444 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 445 GFP_KERNEL); 446 if (!ha->queue_pair_map) { 447 ql_log(ql_log_fatal, vha, 0x0180, 448 "Unable to allocate memory for queue pair ptrs.\n"); 449 goto fail_qpair_map; 450 } 451 } 452 453 /* 454 * Make sure we record at least the request and response queue zero in 455 * case we need to free them if part of the probe fails. 456 */ 457 ha->rsp_q_map[0] = rsp; 458 ha->req_q_map[0] = req; 459 set_bit(0, ha->rsp_qid_map); 460 set_bit(0, ha->req_qid_map); 461 return 0; 462 463 fail_qpair_map: 464 kfree(ha->base_qpair); 465 ha->base_qpair = NULL; 466 fail_base_qpair: 467 kfree(ha->rsp_q_map); 468 ha->rsp_q_map = NULL; 469 fail_rsp_map: 470 kfree(ha->req_q_map); 471 ha->req_q_map = NULL; 472 fail_req_map: 473 return -ENOMEM; 474 } 475 476 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 477 { 478 if (IS_QLAFX00(ha)) { 479 if (req && req->ring_fx00) 480 dma_free_coherent(&ha->pdev->dev, 481 (req->length_fx00 + 1) * sizeof(request_t), 482 req->ring_fx00, req->dma_fx00); 483 } else if (req && req->ring) 484 dma_free_coherent(&ha->pdev->dev, 485 (req->length + 1) * sizeof(request_t), 486 req->ring, req->dma); 487 488 if (req) 489 kfree(req->outstanding_cmds); 490 491 kfree(req); 492 } 493 494 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 495 { 496 if (IS_QLAFX00(ha)) { 497 if (rsp && rsp->ring_fx00) 498 dma_free_coherent(&ha->pdev->dev, 499 (rsp->length_fx00 + 1) * sizeof(request_t), 500 rsp->ring_fx00, rsp->dma_fx00); 501 } else if (rsp && rsp->ring) { 502 dma_free_coherent(&ha->pdev->dev, 503 (rsp->length + 1) * sizeof(response_t), 504 rsp->ring, rsp->dma); 505 } 506 kfree(rsp); 507 } 508 509 static void qla2x00_free_queues(struct qla_hw_data *ha) 510 { 511 struct req_que *req; 512 struct rsp_que *rsp; 513 int cnt; 514 unsigned long flags; 515 516 if (ha->queue_pair_map) { 517 kfree(ha->queue_pair_map); 518 ha->queue_pair_map = NULL; 519 } 520 if (ha->base_qpair) { 521 kfree(ha->base_qpair); 522 ha->base_qpair = NULL; 523 } 524 525 spin_lock_irqsave(&ha->hardware_lock, flags); 526 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 527 if (!test_bit(cnt, ha->req_qid_map)) 528 continue; 529 530 req = ha->req_q_map[cnt]; 531 clear_bit(cnt, ha->req_qid_map); 532 ha->req_q_map[cnt] = NULL; 533 534 spin_unlock_irqrestore(&ha->hardware_lock, flags); 535 qla2x00_free_req_que(ha, req); 536 spin_lock_irqsave(&ha->hardware_lock, flags); 537 } 538 spin_unlock_irqrestore(&ha->hardware_lock, flags); 539 540 kfree(ha->req_q_map); 541 ha->req_q_map = NULL; 542 543 544 spin_lock_irqsave(&ha->hardware_lock, flags); 545 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 546 if (!test_bit(cnt, ha->rsp_qid_map)) 547 continue; 548 549 rsp = ha->rsp_q_map[cnt]; 550 clear_bit(cnt, ha->rsp_qid_map); 551 ha->rsp_q_map[cnt] = NULL; 552 spin_unlock_irqrestore(&ha->hardware_lock, flags); 553 qla2x00_free_rsp_que(ha, rsp); 554 spin_lock_irqsave(&ha->hardware_lock, flags); 555 } 556 spin_unlock_irqrestore(&ha->hardware_lock, flags); 557 558 kfree(ha->rsp_q_map); 559 ha->rsp_q_map = NULL; 560 } 561 562 static char * 563 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 564 { 565 struct qla_hw_data *ha = vha->hw; 566 static char *pci_bus_modes[] = { 567 "33", "66", "100", "133", 568 }; 569 uint16_t pci_bus; 570 571 strcpy(str, "PCI"); 572 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 573 if (pci_bus) { 574 strcat(str, "-X ("); 575 strcat(str, pci_bus_modes[pci_bus]); 576 } else { 577 pci_bus = (ha->pci_attr & BIT_8) >> 8; 578 strcat(str, " ("); 579 strcat(str, pci_bus_modes[pci_bus]); 580 } 581 strcat(str, " MHz)"); 582 583 return (str); 584 } 585 586 static char * 587 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 588 { 589 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 590 struct qla_hw_data *ha = vha->hw; 591 uint32_t pci_bus; 592 593 if (pci_is_pcie(ha->pdev)) { 594 char lwstr[6]; 595 uint32_t lstat, lspeed, lwidth; 596 597 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 598 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 599 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 600 601 strcpy(str, "PCIe ("); 602 switch (lspeed) { 603 case 1: 604 strcat(str, "2.5GT/s "); 605 break; 606 case 2: 607 strcat(str, "5.0GT/s "); 608 break; 609 case 3: 610 strcat(str, "8.0GT/s "); 611 break; 612 default: 613 strcat(str, "<unknown> "); 614 break; 615 } 616 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 617 strcat(str, lwstr); 618 619 return str; 620 } 621 622 strcpy(str, "PCI"); 623 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 624 if (pci_bus == 0 || pci_bus == 8) { 625 strcat(str, " ("); 626 strcat(str, pci_bus_modes[pci_bus >> 3]); 627 } else { 628 strcat(str, "-X "); 629 if (pci_bus & BIT_2) 630 strcat(str, "Mode 2"); 631 else 632 strcat(str, "Mode 1"); 633 strcat(str, " ("); 634 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 635 } 636 strcat(str, " MHz)"); 637 638 return str; 639 } 640 641 static char * 642 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 643 { 644 char un_str[10]; 645 struct qla_hw_data *ha = vha->hw; 646 647 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 648 ha->fw_minor_version, ha->fw_subminor_version); 649 650 if (ha->fw_attributes & BIT_9) { 651 strcat(str, "FLX"); 652 return (str); 653 } 654 655 switch (ha->fw_attributes & 0xFF) { 656 case 0x7: 657 strcat(str, "EF"); 658 break; 659 case 0x17: 660 strcat(str, "TP"); 661 break; 662 case 0x37: 663 strcat(str, "IP"); 664 break; 665 case 0x77: 666 strcat(str, "VI"); 667 break; 668 default: 669 sprintf(un_str, "(%x)", ha->fw_attributes); 670 strcat(str, un_str); 671 break; 672 } 673 if (ha->fw_attributes & 0x100) 674 strcat(str, "X"); 675 676 return (str); 677 } 678 679 static char * 680 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 681 { 682 struct qla_hw_data *ha = vha->hw; 683 684 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 685 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 686 return str; 687 } 688 689 void 690 qla2x00_sp_free_dma(void *ptr) 691 { 692 srb_t *sp = ptr; 693 struct qla_hw_data *ha = sp->vha->hw; 694 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 695 void *ctx = GET_CMD_CTX_SP(sp); 696 697 if (sp->flags & SRB_DMA_VALID) { 698 scsi_dma_unmap(cmd); 699 sp->flags &= ~SRB_DMA_VALID; 700 } 701 702 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 703 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 704 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 705 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 706 } 707 708 if (!ctx) 709 goto end; 710 711 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 712 /* List assured to be having elements */ 713 qla2x00_clean_dsd_pool(ha, ctx); 714 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 715 } 716 717 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 718 struct crc_context *ctx0 = ctx; 719 720 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 721 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 722 } 723 724 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 725 struct ct6_dsd *ctx1 = ctx; 726 727 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 728 ctx1->fcp_cmnd_dma); 729 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 730 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 731 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 732 mempool_free(ctx1, ha->ctx_mempool); 733 } 734 735 end: 736 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 737 CMD_SP(cmd) = NULL; 738 qla2x00_rel_sp(sp); 739 } 740 } 741 742 void 743 qla2x00_sp_compl(void *ptr, int res) 744 { 745 srb_t *sp = ptr; 746 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 747 748 cmd->result = res; 749 750 if (atomic_read(&sp->ref_count) == 0) { 751 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 752 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 753 sp, GET_CMD_SP(sp)); 754 if (ql2xextended_error_logging & ql_dbg_io) 755 WARN_ON(atomic_read(&sp->ref_count) == 0); 756 return; 757 } 758 if (!atomic_dec_and_test(&sp->ref_count)) 759 return; 760 761 sp->free(sp); 762 cmd->scsi_done(cmd); 763 } 764 765 void 766 qla2xxx_qpair_sp_free_dma(void *ptr) 767 { 768 srb_t *sp = (srb_t *)ptr; 769 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 770 struct qla_hw_data *ha = sp->fcport->vha->hw; 771 void *ctx = GET_CMD_CTX_SP(sp); 772 773 if (sp->flags & SRB_DMA_VALID) { 774 scsi_dma_unmap(cmd); 775 sp->flags &= ~SRB_DMA_VALID; 776 } 777 778 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 779 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 780 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 781 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 782 } 783 784 if (!ctx) 785 goto end; 786 787 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 788 /* List assured to be having elements */ 789 qla2x00_clean_dsd_pool(ha, ctx); 790 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 791 } 792 793 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 794 struct crc_context *ctx0 = ctx; 795 796 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 797 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 798 } 799 800 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 801 struct ct6_dsd *ctx1 = ctx; 802 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 803 ctx1->fcp_cmnd_dma); 804 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 805 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 806 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 807 mempool_free(ctx1, ha->ctx_mempool); 808 } 809 end: 810 CMD_SP(cmd) = NULL; 811 qla2xxx_rel_qpair_sp(sp->qpair, sp); 812 } 813 814 void 815 qla2xxx_qpair_sp_compl(void *ptr, int res) 816 { 817 srb_t *sp = ptr; 818 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 819 820 cmd->result = res; 821 822 if (atomic_read(&sp->ref_count) == 0) { 823 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 824 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 825 sp, GET_CMD_SP(sp)); 826 if (ql2xextended_error_logging & ql_dbg_io) 827 WARN_ON(atomic_read(&sp->ref_count) == 0); 828 return; 829 } 830 if (!atomic_dec_and_test(&sp->ref_count)) 831 return; 832 833 sp->free(sp); 834 cmd->scsi_done(cmd); 835 } 836 837 /* If we are SP1 here, we need to still take and release the host_lock as SP1 838 * does not have the changes necessary to avoid taking host->host_lock. 839 */ 840 static int 841 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 842 { 843 scsi_qla_host_t *vha = shost_priv(host); 844 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 845 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 846 struct qla_hw_data *ha = vha->hw; 847 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 848 srb_t *sp; 849 int rval; 850 struct qla_qpair *qpair = NULL; 851 uint32_t tag; 852 uint16_t hwq; 853 854 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 855 cmd->result = DID_NO_CONNECT << 16; 856 goto qc24_fail_command; 857 } 858 859 if (ha->mqenable) { 860 if (shost_use_blk_mq(vha->host)) { 861 tag = blk_mq_unique_tag(cmd->request); 862 hwq = blk_mq_unique_tag_to_hwq(tag); 863 qpair = ha->queue_pair_map[hwq]; 864 } else if (vha->vp_idx && vha->qpair) { 865 qpair = vha->qpair; 866 } 867 868 if (qpair) 869 return qla2xxx_mqueuecommand(host, cmd, qpair); 870 } 871 872 if (ha->flags.eeh_busy) { 873 if (ha->flags.pci_channel_io_perm_failure) { 874 ql_dbg(ql_dbg_aer, vha, 0x9010, 875 "PCI Channel IO permanent failure, exiting " 876 "cmd=%p.\n", cmd); 877 cmd->result = DID_NO_CONNECT << 16; 878 } else { 879 ql_dbg(ql_dbg_aer, vha, 0x9011, 880 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 881 cmd->result = DID_REQUEUE << 16; 882 } 883 goto qc24_fail_command; 884 } 885 886 rval = fc_remote_port_chkready(rport); 887 if (rval) { 888 cmd->result = rval; 889 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 890 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 891 cmd, rval); 892 goto qc24_fail_command; 893 } 894 895 if (!vha->flags.difdix_supported && 896 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 897 ql_dbg(ql_dbg_io, vha, 0x3004, 898 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 899 cmd); 900 cmd->result = DID_NO_CONNECT << 16; 901 goto qc24_fail_command; 902 } 903 904 if (!fcport) { 905 cmd->result = DID_NO_CONNECT << 16; 906 goto qc24_fail_command; 907 } 908 909 if (atomic_read(&fcport->state) != FCS_ONLINE) { 910 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 911 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 912 ql_dbg(ql_dbg_io, vha, 0x3005, 913 "Returning DNC, fcport_state=%d loop_state=%d.\n", 914 atomic_read(&fcport->state), 915 atomic_read(&base_vha->loop_state)); 916 cmd->result = DID_NO_CONNECT << 16; 917 goto qc24_fail_command; 918 } 919 goto qc24_target_busy; 920 } 921 922 /* 923 * Return target busy if we've received a non-zero retry_delay_timer 924 * in a FCP_RSP. 925 */ 926 if (fcport->retry_delay_timestamp == 0) { 927 /* retry delay not set */ 928 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 929 fcport->retry_delay_timestamp = 0; 930 else 931 goto qc24_target_busy; 932 933 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 934 if (!sp) 935 goto qc24_host_busy; 936 937 sp->u.scmd.cmd = cmd; 938 sp->type = SRB_SCSI_CMD; 939 atomic_set(&sp->ref_count, 1); 940 CMD_SP(cmd) = (void *)sp; 941 sp->free = qla2x00_sp_free_dma; 942 sp->done = qla2x00_sp_compl; 943 944 rval = ha->isp_ops->start_scsi(sp); 945 if (rval != QLA_SUCCESS) { 946 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 947 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 948 goto qc24_host_busy_free_sp; 949 } 950 951 return 0; 952 953 qc24_host_busy_free_sp: 954 sp->free(sp); 955 956 qc24_host_busy: 957 return SCSI_MLQUEUE_HOST_BUSY; 958 959 qc24_target_busy: 960 return SCSI_MLQUEUE_TARGET_BUSY; 961 962 qc24_fail_command: 963 cmd->scsi_done(cmd); 964 965 return 0; 966 } 967 968 /* For MQ supported I/O */ 969 int 970 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 971 struct qla_qpair *qpair) 972 { 973 scsi_qla_host_t *vha = shost_priv(host); 974 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 975 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 976 struct qla_hw_data *ha = vha->hw; 977 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 978 srb_t *sp; 979 int rval; 980 981 rval = fc_remote_port_chkready(rport); 982 if (rval) { 983 cmd->result = rval; 984 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 985 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 986 cmd, rval); 987 goto qc24_fail_command; 988 } 989 990 if (!fcport) { 991 cmd->result = DID_NO_CONNECT << 16; 992 goto qc24_fail_command; 993 } 994 995 if (atomic_read(&fcport->state) != FCS_ONLINE) { 996 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 997 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 998 ql_dbg(ql_dbg_io, vha, 0x3077, 999 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1000 atomic_read(&fcport->state), 1001 atomic_read(&base_vha->loop_state)); 1002 cmd->result = DID_NO_CONNECT << 16; 1003 goto qc24_fail_command; 1004 } 1005 goto qc24_target_busy; 1006 } 1007 1008 /* 1009 * Return target busy if we've received a non-zero retry_delay_timer 1010 * in a FCP_RSP. 1011 */ 1012 if (fcport->retry_delay_timestamp == 0) { 1013 /* retry delay not set */ 1014 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1015 fcport->retry_delay_timestamp = 0; 1016 else 1017 goto qc24_target_busy; 1018 1019 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC); 1020 if (!sp) 1021 goto qc24_host_busy; 1022 1023 sp->u.scmd.cmd = cmd; 1024 sp->type = SRB_SCSI_CMD; 1025 atomic_set(&sp->ref_count, 1); 1026 CMD_SP(cmd) = (void *)sp; 1027 sp->free = qla2xxx_qpair_sp_free_dma; 1028 sp->done = qla2xxx_qpair_sp_compl; 1029 sp->qpair = qpair; 1030 1031 rval = ha->isp_ops->start_scsi_mq(sp); 1032 if (rval != QLA_SUCCESS) { 1033 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1034 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1035 if (rval == QLA_INTERFACE_ERROR) 1036 goto qc24_fail_command; 1037 goto qc24_host_busy_free_sp; 1038 } 1039 1040 return 0; 1041 1042 qc24_host_busy_free_sp: 1043 sp->free(sp); 1044 1045 qc24_host_busy: 1046 return SCSI_MLQUEUE_HOST_BUSY; 1047 1048 qc24_target_busy: 1049 return SCSI_MLQUEUE_TARGET_BUSY; 1050 1051 qc24_fail_command: 1052 cmd->scsi_done(cmd); 1053 1054 return 0; 1055 } 1056 1057 /* 1058 * qla2x00_eh_wait_on_command 1059 * Waits for the command to be returned by the Firmware for some 1060 * max time. 1061 * 1062 * Input: 1063 * cmd = Scsi Command to wait on. 1064 * 1065 * Return: 1066 * Not Found : 0 1067 * Found : 1 1068 */ 1069 static int 1070 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1071 { 1072 #define ABORT_POLLING_PERIOD 1000 1073 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1074 unsigned long wait_iter = ABORT_WAIT_ITER; 1075 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1076 struct qla_hw_data *ha = vha->hw; 1077 int ret = QLA_SUCCESS; 1078 1079 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1080 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1081 "Return:eh_wait.\n"); 1082 return ret; 1083 } 1084 1085 while (CMD_SP(cmd) && wait_iter--) { 1086 msleep(ABORT_POLLING_PERIOD); 1087 } 1088 if (CMD_SP(cmd)) 1089 ret = QLA_FUNCTION_FAILED; 1090 1091 return ret; 1092 } 1093 1094 /* 1095 * qla2x00_wait_for_hba_online 1096 * Wait till the HBA is online after going through 1097 * <= MAX_RETRIES_OF_ISP_ABORT or 1098 * finally HBA is disabled ie marked offline 1099 * 1100 * Input: 1101 * ha - pointer to host adapter structure 1102 * 1103 * Note: 1104 * Does context switching-Release SPIN_LOCK 1105 * (if any) before calling this routine. 1106 * 1107 * Return: 1108 * Success (Adapter is online) : 0 1109 * Failed (Adapter is offline/disabled) : 1 1110 */ 1111 int 1112 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1113 { 1114 int return_status; 1115 unsigned long wait_online; 1116 struct qla_hw_data *ha = vha->hw; 1117 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1118 1119 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1120 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1121 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1122 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1123 ha->dpc_active) && time_before(jiffies, wait_online)) { 1124 1125 msleep(1000); 1126 } 1127 if (base_vha->flags.online) 1128 return_status = QLA_SUCCESS; 1129 else 1130 return_status = QLA_FUNCTION_FAILED; 1131 1132 return (return_status); 1133 } 1134 1135 static inline int test_fcport_count(scsi_qla_host_t *vha) 1136 { 1137 struct qla_hw_data *ha = vha->hw; 1138 unsigned long flags; 1139 int res; 1140 1141 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1142 ql_dbg(ql_dbg_init, vha, 0x00ec, 1143 "tgt %p, fcport_count=%d\n", 1144 vha, vha->fcport_count); 1145 res = (vha->fcport_count == 0); 1146 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1147 1148 return res; 1149 } 1150 1151 /* 1152 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1153 * it has dependency on UNLOADING flag to stop device discovery 1154 */ 1155 void 1156 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1157 { 1158 qla2x00_mark_all_devices_lost(vha, 0); 1159 1160 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1161 } 1162 1163 /* 1164 * qla2x00_wait_for_hba_ready 1165 * Wait till the HBA is ready before doing driver unload 1166 * 1167 * Input: 1168 * ha - pointer to host adapter structure 1169 * 1170 * Note: 1171 * Does context switching-Release SPIN_LOCK 1172 * (if any) before calling this routine. 1173 * 1174 */ 1175 static void 1176 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1177 { 1178 struct qla_hw_data *ha = vha->hw; 1179 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1180 1181 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1182 ha->flags.mbox_busy) || 1183 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1184 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1185 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1186 break; 1187 msleep(1000); 1188 } 1189 } 1190 1191 int 1192 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1193 { 1194 int return_status; 1195 unsigned long wait_reset; 1196 struct qla_hw_data *ha = vha->hw; 1197 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1198 1199 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1200 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1201 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1202 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1203 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1204 1205 msleep(1000); 1206 1207 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1208 ha->flags.chip_reset_done) 1209 break; 1210 } 1211 if (ha->flags.chip_reset_done) 1212 return_status = QLA_SUCCESS; 1213 else 1214 return_status = QLA_FUNCTION_FAILED; 1215 1216 return return_status; 1217 } 1218 1219 static int 1220 sp_get(struct srb *sp) 1221 { 1222 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count)) 1223 /* kref get fail */ 1224 return ENXIO; 1225 else 1226 return 0; 1227 } 1228 1229 #define ISP_REG_DISCONNECT 0xffffffffU 1230 /************************************************************************** 1231 * qla2x00_isp_reg_stat 1232 * 1233 * Description: 1234 * Read the host status register of ISP before aborting the command. 1235 * 1236 * Input: 1237 * ha = pointer to host adapter structure. 1238 * 1239 * 1240 * Returns: 1241 * Either true or false. 1242 * 1243 * Note: Return true if there is register disconnect. 1244 **************************************************************************/ 1245 static inline 1246 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1247 { 1248 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1249 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1250 1251 if (IS_P3P_TYPE(ha)) 1252 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1253 else 1254 return ((RD_REG_DWORD(®->host_status)) == 1255 ISP_REG_DISCONNECT); 1256 } 1257 1258 /************************************************************************** 1259 * qla2xxx_eh_abort 1260 * 1261 * Description: 1262 * The abort function will abort the specified command. 1263 * 1264 * Input: 1265 * cmd = Linux SCSI command packet to be aborted. 1266 * 1267 * Returns: 1268 * Either SUCCESS or FAILED. 1269 * 1270 * Note: 1271 * Only return FAILED if command not returned by firmware. 1272 **************************************************************************/ 1273 static int 1274 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1275 { 1276 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1277 srb_t *sp; 1278 int ret; 1279 unsigned int id; 1280 uint64_t lun; 1281 unsigned long flags; 1282 int rval, wait = 0; 1283 struct qla_hw_data *ha = vha->hw; 1284 struct qla_qpair *qpair; 1285 1286 if (qla2x00_isp_reg_stat(ha)) { 1287 ql_log(ql_log_info, vha, 0x8042, 1288 "PCI/Register disconnect, exiting.\n"); 1289 return FAILED; 1290 } 1291 1292 ret = fc_block_scsi_eh(cmd); 1293 if (ret != 0) 1294 return ret; 1295 ret = SUCCESS; 1296 1297 sp = (srb_t *) CMD_SP(cmd); 1298 if (!sp) 1299 return SUCCESS; 1300 1301 qpair = sp->qpair; 1302 if (!qpair) 1303 return SUCCESS; 1304 1305 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1306 if (!CMD_SP(cmd)) { 1307 /* there's a chance an interrupt could clear 1308 the ptr as part of done & free */ 1309 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1310 return SUCCESS; 1311 } 1312 1313 if (sp_get(sp)){ 1314 /* ref_count is already 0 */ 1315 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1316 return SUCCESS; 1317 } 1318 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1319 1320 id = cmd->device->id; 1321 lun = cmd->device->lun; 1322 1323 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1324 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1325 vha->host_no, id, lun, sp, cmd, sp->handle); 1326 1327 /* Get a reference to the sp and drop the lock.*/ 1328 1329 rval = ha->isp_ops->abort_command(sp); 1330 if (rval) { 1331 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1332 ret = SUCCESS; 1333 else 1334 ret = FAILED; 1335 1336 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1337 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1338 } else { 1339 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1340 "Abort command mbx success cmd=%p.\n", cmd); 1341 wait = 1; 1342 } 1343 1344 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1345 /* 1346 * Clear the slot in the oustanding_cmds array if we can't find the 1347 * command to reclaim the resources. 1348 */ 1349 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1350 vha->req->outstanding_cmds[sp->handle] = NULL; 1351 1352 /* 1353 * sp->done will do ref_count-- 1354 * sp_get() took an extra count above 1355 */ 1356 sp->done(sp, DID_RESET << 16); 1357 1358 /* Did the command return during mailbox execution? */ 1359 if (ret == FAILED && !CMD_SP(cmd)) 1360 ret = SUCCESS; 1361 1362 if (!CMD_SP(cmd)) 1363 wait = 0; 1364 1365 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1366 1367 /* Wait for the command to be returned. */ 1368 if (wait) { 1369 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1370 ql_log(ql_log_warn, vha, 0x8006, 1371 "Abort handler timed out cmd=%p.\n", cmd); 1372 ret = FAILED; 1373 } 1374 } 1375 1376 ql_log(ql_log_info, vha, 0x801c, 1377 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1378 vha->host_no, id, lun, wait, ret); 1379 1380 return ret; 1381 } 1382 1383 int 1384 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1385 uint64_t l, enum nexus_wait_type type) 1386 { 1387 int cnt, match, status; 1388 unsigned long flags; 1389 struct qla_hw_data *ha = vha->hw; 1390 struct req_que *req; 1391 srb_t *sp; 1392 struct scsi_cmnd *cmd; 1393 1394 status = QLA_SUCCESS; 1395 1396 spin_lock_irqsave(&ha->hardware_lock, flags); 1397 req = vha->req; 1398 for (cnt = 1; status == QLA_SUCCESS && 1399 cnt < req->num_outstanding_cmds; cnt++) { 1400 sp = req->outstanding_cmds[cnt]; 1401 if (!sp) 1402 continue; 1403 if (sp->type != SRB_SCSI_CMD) 1404 continue; 1405 if (vha->vp_idx != sp->vha->vp_idx) 1406 continue; 1407 match = 0; 1408 cmd = GET_CMD_SP(sp); 1409 switch (type) { 1410 case WAIT_HOST: 1411 match = 1; 1412 break; 1413 case WAIT_TARGET: 1414 match = cmd->device->id == t; 1415 break; 1416 case WAIT_LUN: 1417 match = (cmd->device->id == t && 1418 cmd->device->lun == l); 1419 break; 1420 } 1421 if (!match) 1422 continue; 1423 1424 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1425 status = qla2x00_eh_wait_on_command(cmd); 1426 spin_lock_irqsave(&ha->hardware_lock, flags); 1427 } 1428 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1429 1430 return status; 1431 } 1432 1433 static char *reset_errors[] = { 1434 "HBA not online", 1435 "HBA not ready", 1436 "Task management failed", 1437 "Waiting for command completions", 1438 }; 1439 1440 static int 1441 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1442 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1443 { 1444 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1445 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1446 int err; 1447 1448 if (!fcport) { 1449 return FAILED; 1450 } 1451 1452 err = fc_block_scsi_eh(cmd); 1453 if (err != 0) 1454 return err; 1455 1456 ql_log(ql_log_info, vha, 0x8009, 1457 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1458 cmd->device->id, cmd->device->lun, cmd); 1459 1460 err = 0; 1461 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1462 ql_log(ql_log_warn, vha, 0x800a, 1463 "Wait for hba online failed for cmd=%p.\n", cmd); 1464 goto eh_reset_failed; 1465 } 1466 err = 2; 1467 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1468 != QLA_SUCCESS) { 1469 ql_log(ql_log_warn, vha, 0x800c, 1470 "do_reset failed for cmd=%p.\n", cmd); 1471 goto eh_reset_failed; 1472 } 1473 err = 3; 1474 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1475 cmd->device->lun, type) != QLA_SUCCESS) { 1476 ql_log(ql_log_warn, vha, 0x800d, 1477 "wait for pending cmds failed for cmd=%p.\n", cmd); 1478 goto eh_reset_failed; 1479 } 1480 1481 ql_log(ql_log_info, vha, 0x800e, 1482 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1483 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1484 1485 return SUCCESS; 1486 1487 eh_reset_failed: 1488 ql_log(ql_log_info, vha, 0x800f, 1489 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1490 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1491 cmd); 1492 return FAILED; 1493 } 1494 1495 static int 1496 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1497 { 1498 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1499 struct qla_hw_data *ha = vha->hw; 1500 1501 if (qla2x00_isp_reg_stat(ha)) { 1502 ql_log(ql_log_info, vha, 0x803e, 1503 "PCI/Register disconnect, exiting.\n"); 1504 return FAILED; 1505 } 1506 1507 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1508 ha->isp_ops->lun_reset); 1509 } 1510 1511 static int 1512 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1513 { 1514 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1515 struct qla_hw_data *ha = vha->hw; 1516 1517 if (qla2x00_isp_reg_stat(ha)) { 1518 ql_log(ql_log_info, vha, 0x803f, 1519 "PCI/Register disconnect, exiting.\n"); 1520 return FAILED; 1521 } 1522 1523 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1524 ha->isp_ops->target_reset); 1525 } 1526 1527 /************************************************************************** 1528 * qla2xxx_eh_bus_reset 1529 * 1530 * Description: 1531 * The bus reset function will reset the bus and abort any executing 1532 * commands. 1533 * 1534 * Input: 1535 * cmd = Linux SCSI command packet of the command that cause the 1536 * bus reset. 1537 * 1538 * Returns: 1539 * SUCCESS/FAILURE (defined as macro in scsi.h). 1540 * 1541 **************************************************************************/ 1542 static int 1543 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1544 { 1545 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1546 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1547 int ret = FAILED; 1548 unsigned int id; 1549 uint64_t lun; 1550 struct qla_hw_data *ha = vha->hw; 1551 1552 if (qla2x00_isp_reg_stat(ha)) { 1553 ql_log(ql_log_info, vha, 0x8040, 1554 "PCI/Register disconnect, exiting.\n"); 1555 return FAILED; 1556 } 1557 1558 id = cmd->device->id; 1559 lun = cmd->device->lun; 1560 1561 if (!fcport) { 1562 return ret; 1563 } 1564 1565 ret = fc_block_scsi_eh(cmd); 1566 if (ret != 0) 1567 return ret; 1568 ret = FAILED; 1569 1570 ql_log(ql_log_info, vha, 0x8012, 1571 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1572 1573 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1574 ql_log(ql_log_fatal, vha, 0x8013, 1575 "Wait for hba online failed board disabled.\n"); 1576 goto eh_bus_reset_done; 1577 } 1578 1579 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1580 ret = SUCCESS; 1581 1582 if (ret == FAILED) 1583 goto eh_bus_reset_done; 1584 1585 /* Flush outstanding commands. */ 1586 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1587 QLA_SUCCESS) { 1588 ql_log(ql_log_warn, vha, 0x8014, 1589 "Wait for pending commands failed.\n"); 1590 ret = FAILED; 1591 } 1592 1593 eh_bus_reset_done: 1594 ql_log(ql_log_warn, vha, 0x802b, 1595 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1596 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1597 1598 return ret; 1599 } 1600 1601 /************************************************************************** 1602 * qla2xxx_eh_host_reset 1603 * 1604 * Description: 1605 * The reset function will reset the Adapter. 1606 * 1607 * Input: 1608 * cmd = Linux SCSI command packet of the command that cause the 1609 * adapter reset. 1610 * 1611 * Returns: 1612 * Either SUCCESS or FAILED. 1613 * 1614 * Note: 1615 **************************************************************************/ 1616 static int 1617 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1618 { 1619 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1620 struct qla_hw_data *ha = vha->hw; 1621 int ret = FAILED; 1622 unsigned int id; 1623 uint64_t lun; 1624 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1625 1626 if (qla2x00_isp_reg_stat(ha)) { 1627 ql_log(ql_log_info, vha, 0x8041, 1628 "PCI/Register disconnect, exiting.\n"); 1629 schedule_work(&ha->board_disable); 1630 return SUCCESS; 1631 } 1632 1633 id = cmd->device->id; 1634 lun = cmd->device->lun; 1635 1636 ql_log(ql_log_info, vha, 0x8018, 1637 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1638 1639 /* 1640 * No point in issuing another reset if one is active. Also do not 1641 * attempt a reset if we are updating flash. 1642 */ 1643 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1644 goto eh_host_reset_lock; 1645 1646 if (vha != base_vha) { 1647 if (qla2x00_vp_abort_isp(vha)) 1648 goto eh_host_reset_lock; 1649 } else { 1650 if (IS_P3P_TYPE(vha->hw)) { 1651 if (!qla82xx_fcoe_ctx_reset(vha)) { 1652 /* Ctx reset success */ 1653 ret = SUCCESS; 1654 goto eh_host_reset_lock; 1655 } 1656 /* fall thru if ctx reset failed */ 1657 } 1658 if (ha->wq) 1659 flush_workqueue(ha->wq); 1660 1661 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1662 if (ha->isp_ops->abort_isp(base_vha)) { 1663 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1664 /* failed. schedule dpc to try */ 1665 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1666 1667 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1668 ql_log(ql_log_warn, vha, 0x802a, 1669 "wait for hba online failed.\n"); 1670 goto eh_host_reset_lock; 1671 } 1672 } 1673 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1674 } 1675 1676 /* Waiting for command to be returned to OS.*/ 1677 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1678 QLA_SUCCESS) 1679 ret = SUCCESS; 1680 1681 eh_host_reset_lock: 1682 ql_log(ql_log_info, vha, 0x8017, 1683 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1684 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1685 1686 return ret; 1687 } 1688 1689 /* 1690 * qla2x00_loop_reset 1691 * Issue loop reset. 1692 * 1693 * Input: 1694 * ha = adapter block pointer. 1695 * 1696 * Returns: 1697 * 0 = success 1698 */ 1699 int 1700 qla2x00_loop_reset(scsi_qla_host_t *vha) 1701 { 1702 int ret; 1703 struct fc_port *fcport; 1704 struct qla_hw_data *ha = vha->hw; 1705 1706 if (IS_QLAFX00(ha)) { 1707 return qlafx00_loop_reset(vha); 1708 } 1709 1710 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1711 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1712 if (fcport->port_type != FCT_TARGET) 1713 continue; 1714 1715 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1716 if (ret != QLA_SUCCESS) { 1717 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1718 "Bus Reset failed: Reset=%d " 1719 "d_id=%x.\n", ret, fcport->d_id.b24); 1720 } 1721 } 1722 } 1723 1724 1725 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1726 atomic_set(&vha->loop_state, LOOP_DOWN); 1727 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1728 qla2x00_mark_all_devices_lost(vha, 0); 1729 ret = qla2x00_full_login_lip(vha); 1730 if (ret != QLA_SUCCESS) { 1731 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1732 "full_login_lip=%d.\n", ret); 1733 } 1734 } 1735 1736 if (ha->flags.enable_lip_reset) { 1737 ret = qla2x00_lip_reset(vha); 1738 if (ret != QLA_SUCCESS) 1739 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1740 "lip_reset failed (%d).\n", ret); 1741 } 1742 1743 /* Issue marker command only when we are going to start the I/O */ 1744 vha->marker_needed = 1; 1745 1746 return QLA_SUCCESS; 1747 } 1748 1749 static void 1750 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1751 { 1752 int cnt, status; 1753 unsigned long flags; 1754 srb_t *sp; 1755 scsi_qla_host_t *vha = qp->vha; 1756 struct qla_hw_data *ha = vha->hw; 1757 struct req_que *req; 1758 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1759 struct qla_tgt_cmd *cmd; 1760 1761 if (!ha->req_q_map) 1762 return; 1763 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1764 req = qp->req; 1765 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1766 sp = req->outstanding_cmds[cnt]; 1767 if (sp) { 1768 req->outstanding_cmds[cnt] = NULL; 1769 switch (sp->cmd_type) { 1770 case TYPE_SRB: 1771 if (sp->type == SRB_NVME_CMD || 1772 sp->type == SRB_NVME_LS) { 1773 if (!sp_get(sp)) { 1774 /* got sp */ 1775 spin_unlock_irqrestore 1776 (qp->qp_lock_ptr, 1777 flags); 1778 qla_nvme_abort(ha, sp, res); 1779 spin_lock_irqsave 1780 (qp->qp_lock_ptr, flags); 1781 } 1782 } else if (GET_CMD_SP(sp) && 1783 !ha->flags.eeh_busy && 1784 (!test_bit(ABORT_ISP_ACTIVE, 1785 &vha->dpc_flags)) && 1786 !qla2x00_isp_reg_stat(ha) && 1787 (sp->type == SRB_SCSI_CMD)) { 1788 /* 1789 * Don't abort commands in adapter 1790 * during EEH recovery as it's not 1791 * accessible/responding. 1792 * 1793 * Get a reference to the sp and drop 1794 * the lock. The reference ensures this 1795 * sp->done() call and not the call in 1796 * qla2xxx_eh_abort() ends the SCSI cmd 1797 * (with result 'res'). 1798 */ 1799 if (!sp_get(sp)) { 1800 spin_unlock_irqrestore 1801 (qp->qp_lock_ptr, flags); 1802 status = qla2xxx_eh_abort( 1803 GET_CMD_SP(sp)); 1804 spin_lock_irqsave 1805 (qp->qp_lock_ptr, flags); 1806 /* 1807 * Get rid of extra reference caused 1808 * by early exit from qla2xxx_eh_abort 1809 */ 1810 if (status == FAST_IO_FAIL) 1811 atomic_dec(&sp->ref_count); 1812 } 1813 } 1814 sp->done(sp, res); 1815 break; 1816 case TYPE_TGT_CMD: 1817 if (!vha->hw->tgt.tgt_ops || !tgt || 1818 qla_ini_mode_enabled(vha)) { 1819 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1820 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1821 vha->dpc_flags); 1822 continue; 1823 } 1824 cmd = (struct qla_tgt_cmd *)sp; 1825 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1826 break; 1827 case TYPE_TGT_TMCMD: 1828 /* 1829 * Currently, only ABTS response gets on the 1830 * outstanding_cmds[] 1831 */ 1832 ha->tgt.tgt_ops->free_mcmd( 1833 (struct qla_tgt_mgmt_cmd *)sp); 1834 break; 1835 default: 1836 break; 1837 } 1838 } 1839 } 1840 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1841 } 1842 1843 void 1844 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1845 { 1846 int que; 1847 struct qla_hw_data *ha = vha->hw; 1848 1849 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1850 1851 for (que = 0; que < ha->max_qpairs; que++) { 1852 if (!ha->queue_pair_map[que]) 1853 continue; 1854 1855 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1856 } 1857 } 1858 1859 static int 1860 qla2xxx_slave_alloc(struct scsi_device *sdev) 1861 { 1862 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1863 1864 if (!rport || fc_remote_port_chkready(rport)) 1865 return -ENXIO; 1866 1867 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1868 1869 return 0; 1870 } 1871 1872 static int 1873 qla2xxx_slave_configure(struct scsi_device *sdev) 1874 { 1875 scsi_qla_host_t *vha = shost_priv(sdev->host); 1876 struct req_que *req = vha->req; 1877 1878 if (IS_T10_PI_CAPABLE(vha->hw)) 1879 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1880 1881 scsi_change_queue_depth(sdev, req->max_q_depth); 1882 return 0; 1883 } 1884 1885 static void 1886 qla2xxx_slave_destroy(struct scsi_device *sdev) 1887 { 1888 sdev->hostdata = NULL; 1889 } 1890 1891 /** 1892 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1893 * @ha: HA context 1894 * 1895 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1896 * supported addressing method. 1897 */ 1898 static void 1899 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1900 { 1901 /* Assume a 32bit DMA mask. */ 1902 ha->flags.enable_64bit_addressing = 0; 1903 1904 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1905 /* Any upper-dword bits set? */ 1906 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1907 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1908 /* Ok, a 64bit DMA mask is applicable. */ 1909 ha->flags.enable_64bit_addressing = 1; 1910 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1911 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1912 return; 1913 } 1914 } 1915 1916 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1917 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1918 } 1919 1920 static void 1921 qla2x00_enable_intrs(struct qla_hw_data *ha) 1922 { 1923 unsigned long flags = 0; 1924 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1925 1926 spin_lock_irqsave(&ha->hardware_lock, flags); 1927 ha->interrupts_on = 1; 1928 /* enable risc and host interrupts */ 1929 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1930 RD_REG_WORD(®->ictrl); 1931 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1932 1933 } 1934 1935 static void 1936 qla2x00_disable_intrs(struct qla_hw_data *ha) 1937 { 1938 unsigned long flags = 0; 1939 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1940 1941 spin_lock_irqsave(&ha->hardware_lock, flags); 1942 ha->interrupts_on = 0; 1943 /* disable risc and host interrupts */ 1944 WRT_REG_WORD(®->ictrl, 0); 1945 RD_REG_WORD(®->ictrl); 1946 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1947 } 1948 1949 static void 1950 qla24xx_enable_intrs(struct qla_hw_data *ha) 1951 { 1952 unsigned long flags = 0; 1953 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1954 1955 spin_lock_irqsave(&ha->hardware_lock, flags); 1956 ha->interrupts_on = 1; 1957 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1958 RD_REG_DWORD(®->ictrl); 1959 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1960 } 1961 1962 static void 1963 qla24xx_disable_intrs(struct qla_hw_data *ha) 1964 { 1965 unsigned long flags = 0; 1966 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1967 1968 if (IS_NOPOLLING_TYPE(ha)) 1969 return; 1970 spin_lock_irqsave(&ha->hardware_lock, flags); 1971 ha->interrupts_on = 0; 1972 WRT_REG_DWORD(®->ictrl, 0); 1973 RD_REG_DWORD(®->ictrl); 1974 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1975 } 1976 1977 static int 1978 qla2x00_iospace_config(struct qla_hw_data *ha) 1979 { 1980 resource_size_t pio; 1981 uint16_t msix; 1982 1983 if (pci_request_selected_regions(ha->pdev, ha->bars, 1984 QLA2XXX_DRIVER_NAME)) { 1985 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1986 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1987 pci_name(ha->pdev)); 1988 goto iospace_error_exit; 1989 } 1990 if (!(ha->bars & 1)) 1991 goto skip_pio; 1992 1993 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1994 pio = pci_resource_start(ha->pdev, 0); 1995 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1996 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1997 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1998 "Invalid pci I/O region size (%s).\n", 1999 pci_name(ha->pdev)); 2000 pio = 0; 2001 } 2002 } else { 2003 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2004 "Region #0 no a PIO resource (%s).\n", 2005 pci_name(ha->pdev)); 2006 pio = 0; 2007 } 2008 ha->pio_address = pio; 2009 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2010 "PIO address=%llu.\n", 2011 (unsigned long long)ha->pio_address); 2012 2013 skip_pio: 2014 /* Use MMIO operations for all accesses. */ 2015 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2016 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2017 "Region #1 not an MMIO resource (%s), aborting.\n", 2018 pci_name(ha->pdev)); 2019 goto iospace_error_exit; 2020 } 2021 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2023 "Invalid PCI mem region size (%s), aborting.\n", 2024 pci_name(ha->pdev)); 2025 goto iospace_error_exit; 2026 } 2027 2028 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2029 if (!ha->iobase) { 2030 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2031 "Cannot remap MMIO (%s), aborting.\n", 2032 pci_name(ha->pdev)); 2033 goto iospace_error_exit; 2034 } 2035 2036 /* Determine queue resources */ 2037 ha->max_req_queues = ha->max_rsp_queues = 1; 2038 ha->msix_count = QLA_BASE_VECTORS; 2039 if (!ql2xmqsupport || !ql2xnvmeenable || 2040 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2041 goto mqiobase_exit; 2042 2043 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2044 pci_resource_len(ha->pdev, 3)); 2045 if (ha->mqiobase) { 2046 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2047 "MQIO Base=%p.\n", ha->mqiobase); 2048 /* Read MSIX vector size of the board */ 2049 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2050 ha->msix_count = msix + 1; 2051 /* Max queues are bounded by available msix vectors */ 2052 /* MB interrupt uses 1 vector */ 2053 ha->max_req_queues = ha->msix_count - 1; 2054 ha->max_rsp_queues = ha->max_req_queues; 2055 /* Queue pairs is the max value minus the base queue pair */ 2056 ha->max_qpairs = ha->max_rsp_queues - 1; 2057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2058 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2059 2060 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2061 "MSI-X vector count: %d.\n", ha->msix_count); 2062 } else 2063 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2064 "BAR 3 not enabled.\n"); 2065 2066 mqiobase_exit: 2067 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2068 "MSIX Count: %d.\n", ha->msix_count); 2069 return (0); 2070 2071 iospace_error_exit: 2072 return (-ENOMEM); 2073 } 2074 2075 2076 static int 2077 qla83xx_iospace_config(struct qla_hw_data *ha) 2078 { 2079 uint16_t msix; 2080 2081 if (pci_request_selected_regions(ha->pdev, ha->bars, 2082 QLA2XXX_DRIVER_NAME)) { 2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2084 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2085 pci_name(ha->pdev)); 2086 2087 goto iospace_error_exit; 2088 } 2089 2090 /* Use MMIO operations for all accesses. */ 2091 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2092 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2093 "Invalid pci I/O region size (%s).\n", 2094 pci_name(ha->pdev)); 2095 goto iospace_error_exit; 2096 } 2097 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2098 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2099 "Invalid PCI mem region size (%s), aborting\n", 2100 pci_name(ha->pdev)); 2101 goto iospace_error_exit; 2102 } 2103 2104 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2105 if (!ha->iobase) { 2106 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2107 "Cannot remap MMIO (%s), aborting.\n", 2108 pci_name(ha->pdev)); 2109 goto iospace_error_exit; 2110 } 2111 2112 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2113 /* 83XX 26XX always use MQ type access for queues 2114 * - mbar 2, a.k.a region 4 */ 2115 ha->max_req_queues = ha->max_rsp_queues = 1; 2116 ha->msix_count = QLA_BASE_VECTORS; 2117 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2118 pci_resource_len(ha->pdev, 4)); 2119 2120 if (!ha->mqiobase) { 2121 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2122 "BAR2/region4 not enabled\n"); 2123 goto mqiobase_exit; 2124 } 2125 2126 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2127 pci_resource_len(ha->pdev, 2)); 2128 if (ha->msixbase) { 2129 /* Read MSIX vector size of the board */ 2130 pci_read_config_word(ha->pdev, 2131 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2132 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2133 /* 2134 * By default, driver uses at least two msix vectors 2135 * (default & rspq) 2136 */ 2137 if (ql2xmqsupport || ql2xnvmeenable) { 2138 /* MB interrupt uses 1 vector */ 2139 ha->max_req_queues = ha->msix_count - 1; 2140 2141 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2142 if (QLA_TGT_MODE_ENABLED()) 2143 ha->max_req_queues--; 2144 2145 ha->max_rsp_queues = ha->max_req_queues; 2146 2147 /* Queue pairs is the max value minus 2148 * the base queue pair */ 2149 ha->max_qpairs = ha->max_req_queues - 1; 2150 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2151 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2152 } 2153 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2154 "MSI-X vector count: %d.\n", ha->msix_count); 2155 } else 2156 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2157 "BAR 1 not enabled.\n"); 2158 2159 mqiobase_exit: 2160 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2161 "MSIX Count: %d.\n", ha->msix_count); 2162 return 0; 2163 2164 iospace_error_exit: 2165 return -ENOMEM; 2166 } 2167 2168 static struct isp_operations qla2100_isp_ops = { 2169 .pci_config = qla2100_pci_config, 2170 .reset_chip = qla2x00_reset_chip, 2171 .chip_diag = qla2x00_chip_diag, 2172 .config_rings = qla2x00_config_rings, 2173 .reset_adapter = qla2x00_reset_adapter, 2174 .nvram_config = qla2x00_nvram_config, 2175 .update_fw_options = qla2x00_update_fw_options, 2176 .load_risc = qla2x00_load_risc, 2177 .pci_info_str = qla2x00_pci_info_str, 2178 .fw_version_str = qla2x00_fw_version_str, 2179 .intr_handler = qla2100_intr_handler, 2180 .enable_intrs = qla2x00_enable_intrs, 2181 .disable_intrs = qla2x00_disable_intrs, 2182 .abort_command = qla2x00_abort_command, 2183 .target_reset = qla2x00_abort_target, 2184 .lun_reset = qla2x00_lun_reset, 2185 .fabric_login = qla2x00_login_fabric, 2186 .fabric_logout = qla2x00_fabric_logout, 2187 .calc_req_entries = qla2x00_calc_iocbs_32, 2188 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2189 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2190 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2191 .read_nvram = qla2x00_read_nvram_data, 2192 .write_nvram = qla2x00_write_nvram_data, 2193 .fw_dump = qla2100_fw_dump, 2194 .beacon_on = NULL, 2195 .beacon_off = NULL, 2196 .beacon_blink = NULL, 2197 .read_optrom = qla2x00_read_optrom_data, 2198 .write_optrom = qla2x00_write_optrom_data, 2199 .get_flash_version = qla2x00_get_flash_version, 2200 .start_scsi = qla2x00_start_scsi, 2201 .start_scsi_mq = NULL, 2202 .abort_isp = qla2x00_abort_isp, 2203 .iospace_config = qla2x00_iospace_config, 2204 .initialize_adapter = qla2x00_initialize_adapter, 2205 }; 2206 2207 static struct isp_operations qla2300_isp_ops = { 2208 .pci_config = qla2300_pci_config, 2209 .reset_chip = qla2x00_reset_chip, 2210 .chip_diag = qla2x00_chip_diag, 2211 .config_rings = qla2x00_config_rings, 2212 .reset_adapter = qla2x00_reset_adapter, 2213 .nvram_config = qla2x00_nvram_config, 2214 .update_fw_options = qla2x00_update_fw_options, 2215 .load_risc = qla2x00_load_risc, 2216 .pci_info_str = qla2x00_pci_info_str, 2217 .fw_version_str = qla2x00_fw_version_str, 2218 .intr_handler = qla2300_intr_handler, 2219 .enable_intrs = qla2x00_enable_intrs, 2220 .disable_intrs = qla2x00_disable_intrs, 2221 .abort_command = qla2x00_abort_command, 2222 .target_reset = qla2x00_abort_target, 2223 .lun_reset = qla2x00_lun_reset, 2224 .fabric_login = qla2x00_login_fabric, 2225 .fabric_logout = qla2x00_fabric_logout, 2226 .calc_req_entries = qla2x00_calc_iocbs_32, 2227 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2228 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2229 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2230 .read_nvram = qla2x00_read_nvram_data, 2231 .write_nvram = qla2x00_write_nvram_data, 2232 .fw_dump = qla2300_fw_dump, 2233 .beacon_on = qla2x00_beacon_on, 2234 .beacon_off = qla2x00_beacon_off, 2235 .beacon_blink = qla2x00_beacon_blink, 2236 .read_optrom = qla2x00_read_optrom_data, 2237 .write_optrom = qla2x00_write_optrom_data, 2238 .get_flash_version = qla2x00_get_flash_version, 2239 .start_scsi = qla2x00_start_scsi, 2240 .start_scsi_mq = NULL, 2241 .abort_isp = qla2x00_abort_isp, 2242 .iospace_config = qla2x00_iospace_config, 2243 .initialize_adapter = qla2x00_initialize_adapter, 2244 }; 2245 2246 static struct isp_operations qla24xx_isp_ops = { 2247 .pci_config = qla24xx_pci_config, 2248 .reset_chip = qla24xx_reset_chip, 2249 .chip_diag = qla24xx_chip_diag, 2250 .config_rings = qla24xx_config_rings, 2251 .reset_adapter = qla24xx_reset_adapter, 2252 .nvram_config = qla24xx_nvram_config, 2253 .update_fw_options = qla24xx_update_fw_options, 2254 .load_risc = qla24xx_load_risc, 2255 .pci_info_str = qla24xx_pci_info_str, 2256 .fw_version_str = qla24xx_fw_version_str, 2257 .intr_handler = qla24xx_intr_handler, 2258 .enable_intrs = qla24xx_enable_intrs, 2259 .disable_intrs = qla24xx_disable_intrs, 2260 .abort_command = qla24xx_abort_command, 2261 .target_reset = qla24xx_abort_target, 2262 .lun_reset = qla24xx_lun_reset, 2263 .fabric_login = qla24xx_login_fabric, 2264 .fabric_logout = qla24xx_fabric_logout, 2265 .calc_req_entries = NULL, 2266 .build_iocbs = NULL, 2267 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2268 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2269 .read_nvram = qla24xx_read_nvram_data, 2270 .write_nvram = qla24xx_write_nvram_data, 2271 .fw_dump = qla24xx_fw_dump, 2272 .beacon_on = qla24xx_beacon_on, 2273 .beacon_off = qla24xx_beacon_off, 2274 .beacon_blink = qla24xx_beacon_blink, 2275 .read_optrom = qla24xx_read_optrom_data, 2276 .write_optrom = qla24xx_write_optrom_data, 2277 .get_flash_version = qla24xx_get_flash_version, 2278 .start_scsi = qla24xx_start_scsi, 2279 .start_scsi_mq = NULL, 2280 .abort_isp = qla2x00_abort_isp, 2281 .iospace_config = qla2x00_iospace_config, 2282 .initialize_adapter = qla2x00_initialize_adapter, 2283 }; 2284 2285 static struct isp_operations qla25xx_isp_ops = { 2286 .pci_config = qla25xx_pci_config, 2287 .reset_chip = qla24xx_reset_chip, 2288 .chip_diag = qla24xx_chip_diag, 2289 .config_rings = qla24xx_config_rings, 2290 .reset_adapter = qla24xx_reset_adapter, 2291 .nvram_config = qla24xx_nvram_config, 2292 .update_fw_options = qla24xx_update_fw_options, 2293 .load_risc = qla24xx_load_risc, 2294 .pci_info_str = qla24xx_pci_info_str, 2295 .fw_version_str = qla24xx_fw_version_str, 2296 .intr_handler = qla24xx_intr_handler, 2297 .enable_intrs = qla24xx_enable_intrs, 2298 .disable_intrs = qla24xx_disable_intrs, 2299 .abort_command = qla24xx_abort_command, 2300 .target_reset = qla24xx_abort_target, 2301 .lun_reset = qla24xx_lun_reset, 2302 .fabric_login = qla24xx_login_fabric, 2303 .fabric_logout = qla24xx_fabric_logout, 2304 .calc_req_entries = NULL, 2305 .build_iocbs = NULL, 2306 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2307 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2308 .read_nvram = qla25xx_read_nvram_data, 2309 .write_nvram = qla25xx_write_nvram_data, 2310 .fw_dump = qla25xx_fw_dump, 2311 .beacon_on = qla24xx_beacon_on, 2312 .beacon_off = qla24xx_beacon_off, 2313 .beacon_blink = qla24xx_beacon_blink, 2314 .read_optrom = qla25xx_read_optrom_data, 2315 .write_optrom = qla24xx_write_optrom_data, 2316 .get_flash_version = qla24xx_get_flash_version, 2317 .start_scsi = qla24xx_dif_start_scsi, 2318 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2319 .abort_isp = qla2x00_abort_isp, 2320 .iospace_config = qla2x00_iospace_config, 2321 .initialize_adapter = qla2x00_initialize_adapter, 2322 }; 2323 2324 static struct isp_operations qla81xx_isp_ops = { 2325 .pci_config = qla25xx_pci_config, 2326 .reset_chip = qla24xx_reset_chip, 2327 .chip_diag = qla24xx_chip_diag, 2328 .config_rings = qla24xx_config_rings, 2329 .reset_adapter = qla24xx_reset_adapter, 2330 .nvram_config = qla81xx_nvram_config, 2331 .update_fw_options = qla81xx_update_fw_options, 2332 .load_risc = qla81xx_load_risc, 2333 .pci_info_str = qla24xx_pci_info_str, 2334 .fw_version_str = qla24xx_fw_version_str, 2335 .intr_handler = qla24xx_intr_handler, 2336 .enable_intrs = qla24xx_enable_intrs, 2337 .disable_intrs = qla24xx_disable_intrs, 2338 .abort_command = qla24xx_abort_command, 2339 .target_reset = qla24xx_abort_target, 2340 .lun_reset = qla24xx_lun_reset, 2341 .fabric_login = qla24xx_login_fabric, 2342 .fabric_logout = qla24xx_fabric_logout, 2343 .calc_req_entries = NULL, 2344 .build_iocbs = NULL, 2345 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2346 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2347 .read_nvram = NULL, 2348 .write_nvram = NULL, 2349 .fw_dump = qla81xx_fw_dump, 2350 .beacon_on = qla24xx_beacon_on, 2351 .beacon_off = qla24xx_beacon_off, 2352 .beacon_blink = qla83xx_beacon_blink, 2353 .read_optrom = qla25xx_read_optrom_data, 2354 .write_optrom = qla24xx_write_optrom_data, 2355 .get_flash_version = qla24xx_get_flash_version, 2356 .start_scsi = qla24xx_dif_start_scsi, 2357 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2358 .abort_isp = qla2x00_abort_isp, 2359 .iospace_config = qla2x00_iospace_config, 2360 .initialize_adapter = qla2x00_initialize_adapter, 2361 }; 2362 2363 static struct isp_operations qla82xx_isp_ops = { 2364 .pci_config = qla82xx_pci_config, 2365 .reset_chip = qla82xx_reset_chip, 2366 .chip_diag = qla24xx_chip_diag, 2367 .config_rings = qla82xx_config_rings, 2368 .reset_adapter = qla24xx_reset_adapter, 2369 .nvram_config = qla81xx_nvram_config, 2370 .update_fw_options = qla24xx_update_fw_options, 2371 .load_risc = qla82xx_load_risc, 2372 .pci_info_str = qla24xx_pci_info_str, 2373 .fw_version_str = qla24xx_fw_version_str, 2374 .intr_handler = qla82xx_intr_handler, 2375 .enable_intrs = qla82xx_enable_intrs, 2376 .disable_intrs = qla82xx_disable_intrs, 2377 .abort_command = qla24xx_abort_command, 2378 .target_reset = qla24xx_abort_target, 2379 .lun_reset = qla24xx_lun_reset, 2380 .fabric_login = qla24xx_login_fabric, 2381 .fabric_logout = qla24xx_fabric_logout, 2382 .calc_req_entries = NULL, 2383 .build_iocbs = NULL, 2384 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2385 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2386 .read_nvram = qla24xx_read_nvram_data, 2387 .write_nvram = qla24xx_write_nvram_data, 2388 .fw_dump = qla82xx_fw_dump, 2389 .beacon_on = qla82xx_beacon_on, 2390 .beacon_off = qla82xx_beacon_off, 2391 .beacon_blink = NULL, 2392 .read_optrom = qla82xx_read_optrom_data, 2393 .write_optrom = qla82xx_write_optrom_data, 2394 .get_flash_version = qla82xx_get_flash_version, 2395 .start_scsi = qla82xx_start_scsi, 2396 .start_scsi_mq = NULL, 2397 .abort_isp = qla82xx_abort_isp, 2398 .iospace_config = qla82xx_iospace_config, 2399 .initialize_adapter = qla2x00_initialize_adapter, 2400 }; 2401 2402 static struct isp_operations qla8044_isp_ops = { 2403 .pci_config = qla82xx_pci_config, 2404 .reset_chip = qla82xx_reset_chip, 2405 .chip_diag = qla24xx_chip_diag, 2406 .config_rings = qla82xx_config_rings, 2407 .reset_adapter = qla24xx_reset_adapter, 2408 .nvram_config = qla81xx_nvram_config, 2409 .update_fw_options = qla24xx_update_fw_options, 2410 .load_risc = qla82xx_load_risc, 2411 .pci_info_str = qla24xx_pci_info_str, 2412 .fw_version_str = qla24xx_fw_version_str, 2413 .intr_handler = qla8044_intr_handler, 2414 .enable_intrs = qla82xx_enable_intrs, 2415 .disable_intrs = qla82xx_disable_intrs, 2416 .abort_command = qla24xx_abort_command, 2417 .target_reset = qla24xx_abort_target, 2418 .lun_reset = qla24xx_lun_reset, 2419 .fabric_login = qla24xx_login_fabric, 2420 .fabric_logout = qla24xx_fabric_logout, 2421 .calc_req_entries = NULL, 2422 .build_iocbs = NULL, 2423 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2424 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2425 .read_nvram = NULL, 2426 .write_nvram = NULL, 2427 .fw_dump = qla8044_fw_dump, 2428 .beacon_on = qla82xx_beacon_on, 2429 .beacon_off = qla82xx_beacon_off, 2430 .beacon_blink = NULL, 2431 .read_optrom = qla8044_read_optrom_data, 2432 .write_optrom = qla8044_write_optrom_data, 2433 .get_flash_version = qla82xx_get_flash_version, 2434 .start_scsi = qla82xx_start_scsi, 2435 .start_scsi_mq = NULL, 2436 .abort_isp = qla8044_abort_isp, 2437 .iospace_config = qla82xx_iospace_config, 2438 .initialize_adapter = qla2x00_initialize_adapter, 2439 }; 2440 2441 static struct isp_operations qla83xx_isp_ops = { 2442 .pci_config = qla25xx_pci_config, 2443 .reset_chip = qla24xx_reset_chip, 2444 .chip_diag = qla24xx_chip_diag, 2445 .config_rings = qla24xx_config_rings, 2446 .reset_adapter = qla24xx_reset_adapter, 2447 .nvram_config = qla81xx_nvram_config, 2448 .update_fw_options = qla81xx_update_fw_options, 2449 .load_risc = qla81xx_load_risc, 2450 .pci_info_str = qla24xx_pci_info_str, 2451 .fw_version_str = qla24xx_fw_version_str, 2452 .intr_handler = qla24xx_intr_handler, 2453 .enable_intrs = qla24xx_enable_intrs, 2454 .disable_intrs = qla24xx_disable_intrs, 2455 .abort_command = qla24xx_abort_command, 2456 .target_reset = qla24xx_abort_target, 2457 .lun_reset = qla24xx_lun_reset, 2458 .fabric_login = qla24xx_login_fabric, 2459 .fabric_logout = qla24xx_fabric_logout, 2460 .calc_req_entries = NULL, 2461 .build_iocbs = NULL, 2462 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2463 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2464 .read_nvram = NULL, 2465 .write_nvram = NULL, 2466 .fw_dump = qla83xx_fw_dump, 2467 .beacon_on = qla24xx_beacon_on, 2468 .beacon_off = qla24xx_beacon_off, 2469 .beacon_blink = qla83xx_beacon_blink, 2470 .read_optrom = qla25xx_read_optrom_data, 2471 .write_optrom = qla24xx_write_optrom_data, 2472 .get_flash_version = qla24xx_get_flash_version, 2473 .start_scsi = qla24xx_dif_start_scsi, 2474 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2475 .abort_isp = qla2x00_abort_isp, 2476 .iospace_config = qla83xx_iospace_config, 2477 .initialize_adapter = qla2x00_initialize_adapter, 2478 }; 2479 2480 static struct isp_operations qlafx00_isp_ops = { 2481 .pci_config = qlafx00_pci_config, 2482 .reset_chip = qlafx00_soft_reset, 2483 .chip_diag = qlafx00_chip_diag, 2484 .config_rings = qlafx00_config_rings, 2485 .reset_adapter = qlafx00_soft_reset, 2486 .nvram_config = NULL, 2487 .update_fw_options = NULL, 2488 .load_risc = NULL, 2489 .pci_info_str = qlafx00_pci_info_str, 2490 .fw_version_str = qlafx00_fw_version_str, 2491 .intr_handler = qlafx00_intr_handler, 2492 .enable_intrs = qlafx00_enable_intrs, 2493 .disable_intrs = qlafx00_disable_intrs, 2494 .abort_command = qla24xx_async_abort_command, 2495 .target_reset = qlafx00_abort_target, 2496 .lun_reset = qlafx00_lun_reset, 2497 .fabric_login = NULL, 2498 .fabric_logout = NULL, 2499 .calc_req_entries = NULL, 2500 .build_iocbs = NULL, 2501 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2502 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2503 .read_nvram = qla24xx_read_nvram_data, 2504 .write_nvram = qla24xx_write_nvram_data, 2505 .fw_dump = NULL, 2506 .beacon_on = qla24xx_beacon_on, 2507 .beacon_off = qla24xx_beacon_off, 2508 .beacon_blink = NULL, 2509 .read_optrom = qla24xx_read_optrom_data, 2510 .write_optrom = qla24xx_write_optrom_data, 2511 .get_flash_version = qla24xx_get_flash_version, 2512 .start_scsi = qlafx00_start_scsi, 2513 .start_scsi_mq = NULL, 2514 .abort_isp = qlafx00_abort_isp, 2515 .iospace_config = qlafx00_iospace_config, 2516 .initialize_adapter = qlafx00_initialize_adapter, 2517 }; 2518 2519 static struct isp_operations qla27xx_isp_ops = { 2520 .pci_config = qla25xx_pci_config, 2521 .reset_chip = qla24xx_reset_chip, 2522 .chip_diag = qla24xx_chip_diag, 2523 .config_rings = qla24xx_config_rings, 2524 .reset_adapter = qla24xx_reset_adapter, 2525 .nvram_config = qla81xx_nvram_config, 2526 .update_fw_options = qla81xx_update_fw_options, 2527 .load_risc = qla81xx_load_risc, 2528 .pci_info_str = qla24xx_pci_info_str, 2529 .fw_version_str = qla24xx_fw_version_str, 2530 .intr_handler = qla24xx_intr_handler, 2531 .enable_intrs = qla24xx_enable_intrs, 2532 .disable_intrs = qla24xx_disable_intrs, 2533 .abort_command = qla24xx_abort_command, 2534 .target_reset = qla24xx_abort_target, 2535 .lun_reset = qla24xx_lun_reset, 2536 .fabric_login = qla24xx_login_fabric, 2537 .fabric_logout = qla24xx_fabric_logout, 2538 .calc_req_entries = NULL, 2539 .build_iocbs = NULL, 2540 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2541 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2542 .read_nvram = NULL, 2543 .write_nvram = NULL, 2544 .fw_dump = qla27xx_fwdump, 2545 .beacon_on = qla24xx_beacon_on, 2546 .beacon_off = qla24xx_beacon_off, 2547 .beacon_blink = qla83xx_beacon_blink, 2548 .read_optrom = qla25xx_read_optrom_data, 2549 .write_optrom = qla24xx_write_optrom_data, 2550 .get_flash_version = qla24xx_get_flash_version, 2551 .start_scsi = qla24xx_dif_start_scsi, 2552 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2553 .abort_isp = qla2x00_abort_isp, 2554 .iospace_config = qla83xx_iospace_config, 2555 .initialize_adapter = qla2x00_initialize_adapter, 2556 }; 2557 2558 static inline void 2559 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2560 { 2561 ha->device_type = DT_EXTENDED_IDS; 2562 switch (ha->pdev->device) { 2563 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2564 ha->isp_type |= DT_ISP2100; 2565 ha->device_type &= ~DT_EXTENDED_IDS; 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2567 break; 2568 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2569 ha->isp_type |= DT_ISP2200; 2570 ha->device_type &= ~DT_EXTENDED_IDS; 2571 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2572 break; 2573 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2574 ha->isp_type |= DT_ISP2300; 2575 ha->device_type |= DT_ZIO_SUPPORTED; 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2577 break; 2578 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2579 ha->isp_type |= DT_ISP2312; 2580 ha->device_type |= DT_ZIO_SUPPORTED; 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2582 break; 2583 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2584 ha->isp_type |= DT_ISP2322; 2585 ha->device_type |= DT_ZIO_SUPPORTED; 2586 if (ha->pdev->subsystem_vendor == 0x1028 && 2587 ha->pdev->subsystem_device == 0x0170) 2588 ha->device_type |= DT_OEM_001; 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2590 break; 2591 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2592 ha->isp_type |= DT_ISP6312; 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2594 break; 2595 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2596 ha->isp_type |= DT_ISP6322; 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2600 ha->isp_type |= DT_ISP2422; 2601 ha->device_type |= DT_ZIO_SUPPORTED; 2602 ha->device_type |= DT_FWI2; 2603 ha->device_type |= DT_IIDMA; 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2607 ha->isp_type |= DT_ISP2432; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->device_type |= DT_IIDMA; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2614 ha->isp_type |= DT_ISP8432; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->device_type |= DT_IIDMA; 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2619 break; 2620 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2621 ha->isp_type |= DT_ISP5422; 2622 ha->device_type |= DT_FWI2; 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2624 break; 2625 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2626 ha->isp_type |= DT_ISP5432; 2627 ha->device_type |= DT_FWI2; 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2629 break; 2630 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2631 ha->isp_type |= DT_ISP2532; 2632 ha->device_type |= DT_ZIO_SUPPORTED; 2633 ha->device_type |= DT_FWI2; 2634 ha->device_type |= DT_IIDMA; 2635 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2636 break; 2637 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2638 ha->isp_type |= DT_ISP8001; 2639 ha->device_type |= DT_ZIO_SUPPORTED; 2640 ha->device_type |= DT_FWI2; 2641 ha->device_type |= DT_IIDMA; 2642 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2645 ha->isp_type |= DT_ISP8021; 2646 ha->device_type |= DT_ZIO_SUPPORTED; 2647 ha->device_type |= DT_FWI2; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 /* Initialize 82XX ISP flags */ 2650 qla82xx_init_flags(ha); 2651 break; 2652 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2653 ha->isp_type |= DT_ISP8044; 2654 ha->device_type |= DT_ZIO_SUPPORTED; 2655 ha->device_type |= DT_FWI2; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2657 /* Initialize 82XX ISP flags */ 2658 qla82xx_init_flags(ha); 2659 break; 2660 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2661 ha->isp_type |= DT_ISP2031; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 ha->device_type |= DT_FWI2; 2664 ha->device_type |= DT_IIDMA; 2665 ha->device_type |= DT_T10_PI; 2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2667 break; 2668 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2669 ha->isp_type |= DT_ISP8031; 2670 ha->device_type |= DT_ZIO_SUPPORTED; 2671 ha->device_type |= DT_FWI2; 2672 ha->device_type |= DT_IIDMA; 2673 ha->device_type |= DT_T10_PI; 2674 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2675 break; 2676 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2677 ha->isp_type |= DT_ISPFX00; 2678 break; 2679 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2680 ha->isp_type |= DT_ISP2071; 2681 ha->device_type |= DT_ZIO_SUPPORTED; 2682 ha->device_type |= DT_FWI2; 2683 ha->device_type |= DT_IIDMA; 2684 ha->device_type |= DT_T10_PI; 2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2686 break; 2687 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2688 ha->isp_type |= DT_ISP2271; 2689 ha->device_type |= DT_ZIO_SUPPORTED; 2690 ha->device_type |= DT_FWI2; 2691 ha->device_type |= DT_IIDMA; 2692 ha->device_type |= DT_T10_PI; 2693 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2694 break; 2695 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2696 ha->isp_type |= DT_ISP2261; 2697 ha->device_type |= DT_ZIO_SUPPORTED; 2698 ha->device_type |= DT_FWI2; 2699 ha->device_type |= DT_IIDMA; 2700 ha->device_type |= DT_T10_PI; 2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2702 break; 2703 } 2704 2705 if (IS_QLA82XX(ha)) 2706 ha->port_no = ha->portnum & 1; 2707 else { 2708 /* Get adapter physical port no from interrupt pin register. */ 2709 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2710 if (IS_QLA27XX(ha)) 2711 ha->port_no--; 2712 else 2713 ha->port_no = !(ha->port_no & 1); 2714 } 2715 2716 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2717 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2718 ha->device_type, ha->port_no, ha->fw_srisc_address); 2719 } 2720 2721 static void 2722 qla2xxx_scan_start(struct Scsi_Host *shost) 2723 { 2724 scsi_qla_host_t *vha = shost_priv(shost); 2725 2726 if (vha->hw->flags.running_gold_fw) 2727 return; 2728 2729 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2730 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2731 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2732 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2733 } 2734 2735 static int 2736 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2737 { 2738 scsi_qla_host_t *vha = shost_priv(shost); 2739 2740 if (test_bit(UNLOADING, &vha->dpc_flags)) 2741 return 1; 2742 if (!vha->host) 2743 return 1; 2744 if (time > vha->hw->loop_reset_delay * HZ) 2745 return 1; 2746 2747 return atomic_read(&vha->loop_state) == LOOP_READY; 2748 } 2749 2750 static void qla2x00_iocb_work_fn(struct work_struct *work) 2751 { 2752 struct scsi_qla_host *vha = container_of(work, 2753 struct scsi_qla_host, iocb_work); 2754 struct qla_hw_data *ha = vha->hw; 2755 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2756 int i = 2; 2757 unsigned long flags; 2758 2759 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2760 return; 2761 2762 while (!list_empty(&vha->work_list) && i > 0) { 2763 qla2x00_do_work(vha); 2764 i--; 2765 } 2766 2767 spin_lock_irqsave(&vha->work_lock, flags); 2768 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2769 spin_unlock_irqrestore(&vha->work_lock, flags); 2770 } 2771 2772 /* 2773 * PCI driver interface 2774 */ 2775 static int 2776 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2777 { 2778 int ret = -ENODEV; 2779 struct Scsi_Host *host; 2780 scsi_qla_host_t *base_vha = NULL; 2781 struct qla_hw_data *ha; 2782 char pci_info[30]; 2783 char fw_str[30], wq_name[30]; 2784 struct scsi_host_template *sht; 2785 int bars, mem_only = 0; 2786 uint16_t req_length = 0, rsp_length = 0; 2787 struct req_que *req = NULL; 2788 struct rsp_que *rsp = NULL; 2789 int i; 2790 2791 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2792 sht = &qla2xxx_driver_template; 2793 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2808 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2809 mem_only = 1; 2810 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2811 "Mem only adapter.\n"); 2812 } 2813 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2814 "Bars=%d.\n", bars); 2815 2816 if (mem_only) { 2817 if (pci_enable_device_mem(pdev)) 2818 return ret; 2819 } else { 2820 if (pci_enable_device(pdev)) 2821 return ret; 2822 } 2823 2824 /* This may fail but that's ok */ 2825 pci_enable_pcie_error_reporting(pdev); 2826 2827 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2828 if (!ha) { 2829 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2830 "Unable to allocate memory for ha.\n"); 2831 goto disable_device; 2832 } 2833 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2834 "Memory allocated for ha=%p.\n", ha); 2835 ha->pdev = pdev; 2836 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2837 spin_lock_init(&ha->tgt.q_full_lock); 2838 spin_lock_init(&ha->tgt.sess_lock); 2839 spin_lock_init(&ha->tgt.atio_lock); 2840 2841 atomic_set(&ha->nvme_active_aen_cnt, 0); 2842 2843 /* Clear our data area */ 2844 ha->bars = bars; 2845 ha->mem_only = mem_only; 2846 spin_lock_init(&ha->hardware_lock); 2847 spin_lock_init(&ha->vport_slock); 2848 mutex_init(&ha->selflogin_lock); 2849 mutex_init(&ha->optrom_mutex); 2850 2851 /* Set ISP-type information. */ 2852 qla2x00_set_isp_flags(ha); 2853 2854 /* Set EEH reset type to fundamental if required by hba */ 2855 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2856 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2857 pdev->needs_freset = 1; 2858 2859 ha->prev_topology = 0; 2860 ha->init_cb_size = sizeof(init_cb_t); 2861 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2862 ha->optrom_size = OPTROM_SIZE_2300; 2863 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2864 atomic_set(&ha->num_pend_mbx_stage1, 0); 2865 atomic_set(&ha->num_pend_mbx_stage2, 0); 2866 atomic_set(&ha->num_pend_mbx_stage3, 0); 2867 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2868 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2869 2870 /* Assign ISP specific operations. */ 2871 if (IS_QLA2100(ha)) { 2872 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2873 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2874 req_length = REQUEST_ENTRY_CNT_2100; 2875 rsp_length = RESPONSE_ENTRY_CNT_2100; 2876 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2877 ha->gid_list_info_size = 4; 2878 ha->flash_conf_off = ~0; 2879 ha->flash_data_off = ~0; 2880 ha->nvram_conf_off = ~0; 2881 ha->nvram_data_off = ~0; 2882 ha->isp_ops = &qla2100_isp_ops; 2883 } else if (IS_QLA2200(ha)) { 2884 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2885 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2886 req_length = REQUEST_ENTRY_CNT_2200; 2887 rsp_length = RESPONSE_ENTRY_CNT_2100; 2888 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2889 ha->gid_list_info_size = 4; 2890 ha->flash_conf_off = ~0; 2891 ha->flash_data_off = ~0; 2892 ha->nvram_conf_off = ~0; 2893 ha->nvram_data_off = ~0; 2894 ha->isp_ops = &qla2100_isp_ops; 2895 } else if (IS_QLA23XX(ha)) { 2896 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2897 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2898 req_length = REQUEST_ENTRY_CNT_2200; 2899 rsp_length = RESPONSE_ENTRY_CNT_2300; 2900 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2901 ha->gid_list_info_size = 6; 2902 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2903 ha->optrom_size = OPTROM_SIZE_2322; 2904 ha->flash_conf_off = ~0; 2905 ha->flash_data_off = ~0; 2906 ha->nvram_conf_off = ~0; 2907 ha->nvram_data_off = ~0; 2908 ha->isp_ops = &qla2300_isp_ops; 2909 } else if (IS_QLA24XX_TYPE(ha)) { 2910 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2911 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2912 req_length = REQUEST_ENTRY_CNT_24XX; 2913 rsp_length = RESPONSE_ENTRY_CNT_2300; 2914 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2915 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2916 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2917 ha->gid_list_info_size = 8; 2918 ha->optrom_size = OPTROM_SIZE_24XX; 2919 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2920 ha->isp_ops = &qla24xx_isp_ops; 2921 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2922 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2923 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2924 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2925 } else if (IS_QLA25XX(ha)) { 2926 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2927 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2928 req_length = REQUEST_ENTRY_CNT_24XX; 2929 rsp_length = RESPONSE_ENTRY_CNT_2300; 2930 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2931 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2932 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2933 ha->gid_list_info_size = 8; 2934 ha->optrom_size = OPTROM_SIZE_25XX; 2935 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2936 ha->isp_ops = &qla25xx_isp_ops; 2937 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2938 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2939 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2940 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2941 } else if (IS_QLA81XX(ha)) { 2942 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2943 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2944 req_length = REQUEST_ENTRY_CNT_24XX; 2945 rsp_length = RESPONSE_ENTRY_CNT_2300; 2946 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2947 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2948 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2949 ha->gid_list_info_size = 8; 2950 ha->optrom_size = OPTROM_SIZE_81XX; 2951 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2952 ha->isp_ops = &qla81xx_isp_ops; 2953 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2954 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2955 ha->nvram_conf_off = ~0; 2956 ha->nvram_data_off = ~0; 2957 } else if (IS_QLA82XX(ha)) { 2958 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2959 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2960 req_length = REQUEST_ENTRY_CNT_82XX; 2961 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2962 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2963 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2964 ha->gid_list_info_size = 8; 2965 ha->optrom_size = OPTROM_SIZE_82XX; 2966 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2967 ha->isp_ops = &qla82xx_isp_ops; 2968 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2969 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2970 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2971 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2972 } else if (IS_QLA8044(ha)) { 2973 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2974 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2975 req_length = REQUEST_ENTRY_CNT_82XX; 2976 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2977 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2978 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2979 ha->gid_list_info_size = 8; 2980 ha->optrom_size = OPTROM_SIZE_83XX; 2981 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2982 ha->isp_ops = &qla8044_isp_ops; 2983 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2984 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2985 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2986 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2987 } else if (IS_QLA83XX(ha)) { 2988 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2989 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2990 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2991 req_length = REQUEST_ENTRY_CNT_83XX; 2992 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2993 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2994 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2995 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2996 ha->gid_list_info_size = 8; 2997 ha->optrom_size = OPTROM_SIZE_83XX; 2998 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2999 ha->isp_ops = &qla83xx_isp_ops; 3000 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3001 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3002 ha->nvram_conf_off = ~0; 3003 ha->nvram_data_off = ~0; 3004 } else if (IS_QLAFX00(ha)) { 3005 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3006 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3007 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3008 req_length = REQUEST_ENTRY_CNT_FX00; 3009 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3010 ha->isp_ops = &qlafx00_isp_ops; 3011 ha->port_down_retry_count = 30; /* default value */ 3012 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3013 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3014 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3015 ha->mr.fw_hbt_en = 1; 3016 ha->mr.host_info_resend = false; 3017 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3018 } else if (IS_QLA27XX(ha)) { 3019 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3020 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3021 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3022 req_length = REQUEST_ENTRY_CNT_83XX; 3023 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3024 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3025 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3026 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3027 ha->gid_list_info_size = 8; 3028 ha->optrom_size = OPTROM_SIZE_83XX; 3029 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3030 ha->isp_ops = &qla27xx_isp_ops; 3031 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3032 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3033 ha->nvram_conf_off = ~0; 3034 ha->nvram_data_off = ~0; 3035 } 3036 3037 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3038 "mbx_count=%d, req_length=%d, " 3039 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3040 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3041 "max_fibre_devices=%d.\n", 3042 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3043 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3044 ha->nvram_npiv_size, ha->max_fibre_devices); 3045 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3046 "isp_ops=%p, flash_conf_off=%d, " 3047 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3048 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3049 ha->nvram_conf_off, ha->nvram_data_off); 3050 3051 /* Configure PCI I/O space */ 3052 ret = ha->isp_ops->iospace_config(ha); 3053 if (ret) 3054 goto iospace_config_failed; 3055 3056 ql_log_pci(ql_log_info, pdev, 0x001d, 3057 "Found an ISP%04X irq %d iobase 0x%p.\n", 3058 pdev->device, pdev->irq, ha->iobase); 3059 mutex_init(&ha->vport_lock); 3060 mutex_init(&ha->mq_lock); 3061 init_completion(&ha->mbx_cmd_comp); 3062 complete(&ha->mbx_cmd_comp); 3063 init_completion(&ha->mbx_intr_comp); 3064 init_completion(&ha->dcbx_comp); 3065 init_completion(&ha->lb_portup_comp); 3066 3067 set_bit(0, (unsigned long *) ha->vp_idx_map); 3068 3069 qla2x00_config_dma_addressing(ha); 3070 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3071 "64 Bit addressing is %s.\n", 3072 ha->flags.enable_64bit_addressing ? "enable" : 3073 "disable"); 3074 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3075 if (ret) { 3076 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3077 "Failed to allocate memory for adapter, aborting.\n"); 3078 3079 goto probe_hw_failed; 3080 } 3081 3082 req->max_q_depth = MAX_Q_DEPTH; 3083 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3084 req->max_q_depth = ql2xmaxqdepth; 3085 3086 3087 base_vha = qla2x00_create_host(sht, ha); 3088 if (!base_vha) { 3089 ret = -ENOMEM; 3090 goto probe_hw_failed; 3091 } 3092 3093 pci_set_drvdata(pdev, base_vha); 3094 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3095 3096 host = base_vha->host; 3097 base_vha->req = req; 3098 if (IS_QLA2XXX_MIDTYPE(ha)) 3099 base_vha->mgmt_svr_loop_id = 3100 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3101 else 3102 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3103 base_vha->vp_idx; 3104 3105 /* Setup fcport template structure. */ 3106 ha->mr.fcport.vha = base_vha; 3107 ha->mr.fcport.port_type = FCT_UNKNOWN; 3108 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3109 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3110 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3111 ha->mr.fcport.scan_state = 1; 3112 3113 /* Set the SG table size based on ISP type */ 3114 if (!IS_FWI2_CAPABLE(ha)) { 3115 if (IS_QLA2100(ha)) 3116 host->sg_tablesize = 32; 3117 } else { 3118 if (!IS_QLA82XX(ha)) 3119 host->sg_tablesize = QLA_SG_ALL; 3120 } 3121 host->max_id = ha->max_fibre_devices; 3122 host->cmd_per_lun = 3; 3123 host->unique_id = host->host_no; 3124 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3125 host->max_cmd_len = 32; 3126 else 3127 host->max_cmd_len = MAX_CMDSZ; 3128 host->max_channel = MAX_BUSES - 1; 3129 /* Older HBAs support only 16-bit LUNs */ 3130 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3131 ql2xmaxlun > 0xffff) 3132 host->max_lun = 0xffff; 3133 else 3134 host->max_lun = ql2xmaxlun; 3135 host->transportt = qla2xxx_transport_template; 3136 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3137 3138 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3139 "max_id=%d this_id=%d " 3140 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3141 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3142 host->this_id, host->cmd_per_lun, host->unique_id, 3143 host->max_cmd_len, host->max_channel, host->max_lun, 3144 host->transportt, sht->vendor_id); 3145 3146 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3147 3148 /* Set up the irqs */ 3149 ret = qla2x00_request_irqs(ha, rsp); 3150 if (ret) 3151 goto probe_failed; 3152 3153 /* Alloc arrays of request and response ring ptrs */ 3154 ret = qla2x00_alloc_queues(ha, req, rsp); 3155 if (ret) { 3156 ql_log(ql_log_fatal, base_vha, 0x003d, 3157 "Failed to allocate memory for queue pointers..." 3158 "aborting.\n"); 3159 goto probe_failed; 3160 } 3161 3162 if (ha->mqenable && shost_use_blk_mq(host)) { 3163 /* number of hardware queues supported by blk/scsi-mq*/ 3164 host->nr_hw_queues = ha->max_qpairs; 3165 3166 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3167 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3168 } else { 3169 if (ql2xnvmeenable) { 3170 host->nr_hw_queues = ha->max_qpairs; 3171 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3172 "FC-NVMe support is enabled, HW queues=%d\n", 3173 host->nr_hw_queues); 3174 } else { 3175 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3176 "blk/scsi-mq disabled.\n"); 3177 } 3178 } 3179 3180 qlt_probe_one_stage1(base_vha, ha); 3181 3182 pci_save_state(pdev); 3183 3184 /* Assign back pointers */ 3185 rsp->req = req; 3186 req->rsp = rsp; 3187 3188 if (IS_QLAFX00(ha)) { 3189 ha->rsp_q_map[0] = rsp; 3190 ha->req_q_map[0] = req; 3191 set_bit(0, ha->req_qid_map); 3192 set_bit(0, ha->rsp_qid_map); 3193 } 3194 3195 /* FWI2-capable only. */ 3196 req->req_q_in = &ha->iobase->isp24.req_q_in; 3197 req->req_q_out = &ha->iobase->isp24.req_q_out; 3198 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3199 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3200 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3201 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3202 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3203 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3204 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3205 } 3206 3207 if (IS_QLAFX00(ha)) { 3208 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3209 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3210 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3211 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3212 } 3213 3214 if (IS_P3P_TYPE(ha)) { 3215 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3216 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3217 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3218 } 3219 3220 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3221 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3222 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3223 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3224 "req->req_q_in=%p req->req_q_out=%p " 3225 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3226 req->req_q_in, req->req_q_out, 3227 rsp->rsp_q_in, rsp->rsp_q_out); 3228 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3229 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3230 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3231 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3232 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3233 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3234 3235 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3236 3237 if (ha->isp_ops->initialize_adapter(base_vha)) { 3238 ql_log(ql_log_fatal, base_vha, 0x00d6, 3239 "Failed to initialize adapter - Adapter flags %x.\n", 3240 base_vha->device_flags); 3241 3242 if (IS_QLA82XX(ha)) { 3243 qla82xx_idc_lock(ha); 3244 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3245 QLA8XXX_DEV_FAILED); 3246 qla82xx_idc_unlock(ha); 3247 ql_log(ql_log_fatal, base_vha, 0x00d7, 3248 "HW State: FAILED.\n"); 3249 } else if (IS_QLA8044(ha)) { 3250 qla8044_idc_lock(ha); 3251 qla8044_wr_direct(base_vha, 3252 QLA8044_CRB_DEV_STATE_INDEX, 3253 QLA8XXX_DEV_FAILED); 3254 qla8044_idc_unlock(ha); 3255 ql_log(ql_log_fatal, base_vha, 0x0150, 3256 "HW State: FAILED.\n"); 3257 } 3258 3259 ret = -ENODEV; 3260 goto probe_failed; 3261 } 3262 3263 if (IS_QLAFX00(ha)) 3264 host->can_queue = QLAFX00_MAX_CANQUEUE; 3265 else 3266 host->can_queue = req->num_outstanding_cmds - 10; 3267 3268 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3269 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3270 host->can_queue, base_vha->req, 3271 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3272 3273 if (ha->mqenable) { 3274 bool mq = false; 3275 bool startit = false; 3276 3277 if (QLA_TGT_MODE_ENABLED()) { 3278 mq = true; 3279 startit = false; 3280 } 3281 3282 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3283 shost_use_blk_mq(host)) { 3284 mq = true; 3285 startit = true; 3286 } 3287 3288 if (mq) { 3289 /* Create start of day qpairs for Block MQ */ 3290 for (i = 0; i < ha->max_qpairs; i++) 3291 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3292 } 3293 } 3294 3295 if (ha->flags.running_gold_fw) 3296 goto skip_dpc; 3297 3298 /* 3299 * Startup the kernel thread for this host adapter 3300 */ 3301 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3302 "%s_dpc", base_vha->host_str); 3303 if (IS_ERR(ha->dpc_thread)) { 3304 ql_log(ql_log_fatal, base_vha, 0x00ed, 3305 "Failed to start DPC thread.\n"); 3306 ret = PTR_ERR(ha->dpc_thread); 3307 ha->dpc_thread = NULL; 3308 goto probe_failed; 3309 } 3310 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3311 "DPC thread started successfully.\n"); 3312 3313 /* 3314 * If we're not coming up in initiator mode, we might sit for 3315 * a while without waking up the dpc thread, which leads to a 3316 * stuck process warning. So just kick the dpc once here and 3317 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3318 */ 3319 qla2xxx_wake_dpc(base_vha); 3320 3321 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3322 3323 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3324 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3325 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3326 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3327 3328 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3329 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3330 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3331 INIT_WORK(&ha->idc_state_handler, 3332 qla83xx_idc_state_handler_work); 3333 INIT_WORK(&ha->nic_core_unrecoverable, 3334 qla83xx_nic_core_unrecoverable_work); 3335 } 3336 3337 skip_dpc: 3338 list_add_tail(&base_vha->list, &ha->vp_list); 3339 base_vha->host->irq = ha->pdev->irq; 3340 3341 /* Initialized the timer */ 3342 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3343 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3344 "Started qla2x00_timer with " 3345 "interval=%d.\n", WATCH_INTERVAL); 3346 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3347 "Detected hba at address=%p.\n", 3348 ha); 3349 3350 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3351 if (ha->fw_attributes & BIT_4) { 3352 int prot = 0, guard; 3353 base_vha->flags.difdix_supported = 1; 3354 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3355 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3356 if (ql2xenabledif == 1) 3357 prot = SHOST_DIX_TYPE0_PROTECTION; 3358 scsi_host_set_prot(host, 3359 prot | SHOST_DIF_TYPE1_PROTECTION 3360 | SHOST_DIF_TYPE2_PROTECTION 3361 | SHOST_DIF_TYPE3_PROTECTION 3362 | SHOST_DIX_TYPE1_PROTECTION 3363 | SHOST_DIX_TYPE2_PROTECTION 3364 | SHOST_DIX_TYPE3_PROTECTION); 3365 3366 guard = SHOST_DIX_GUARD_CRC; 3367 3368 if (IS_PI_IPGUARD_CAPABLE(ha) && 3369 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3370 guard |= SHOST_DIX_GUARD_IP; 3371 3372 scsi_host_set_guard(host, guard); 3373 } else 3374 base_vha->flags.difdix_supported = 0; 3375 } 3376 3377 ha->isp_ops->enable_intrs(ha); 3378 3379 if (IS_QLAFX00(ha)) { 3380 ret = qlafx00_fx_disc(base_vha, 3381 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3382 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3383 QLA_SG_ALL : 128; 3384 } 3385 3386 ret = scsi_add_host(host, &pdev->dev); 3387 if (ret) 3388 goto probe_failed; 3389 3390 base_vha->flags.init_done = 1; 3391 base_vha->flags.online = 1; 3392 ha->prev_minidump_failed = 0; 3393 3394 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3395 "Init done and hba is online.\n"); 3396 3397 if (qla_ini_mode_enabled(base_vha) || 3398 qla_dual_mode_enabled(base_vha)) 3399 scsi_scan_host(host); 3400 else 3401 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3402 "skipping scsi_scan_host() for non-initiator port\n"); 3403 3404 qla2x00_alloc_sysfs_attr(base_vha); 3405 3406 if (IS_QLAFX00(ha)) { 3407 ret = qlafx00_fx_disc(base_vha, 3408 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3409 3410 /* Register system information */ 3411 ret = qlafx00_fx_disc(base_vha, 3412 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3413 } 3414 3415 qla2x00_init_host_attr(base_vha); 3416 3417 qla2x00_dfs_setup(base_vha); 3418 3419 ql_log(ql_log_info, base_vha, 0x00fb, 3420 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3421 ql_log(ql_log_info, base_vha, 0x00fc, 3422 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3423 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3424 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3425 base_vha->host_no, 3426 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3427 3428 qlt_add_target(ha, base_vha); 3429 3430 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3431 3432 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3433 return -ENODEV; 3434 3435 if (ha->flags.detected_lr_sfp) { 3436 ql_log(ql_log_info, base_vha, 0xffff, 3437 "Reset chip to pick up LR SFP setting\n"); 3438 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3439 qla2xxx_wake_dpc(base_vha); 3440 } 3441 3442 return 0; 3443 3444 probe_failed: 3445 if (base_vha->timer_active) 3446 qla2x00_stop_timer(base_vha); 3447 base_vha->flags.online = 0; 3448 if (ha->dpc_thread) { 3449 struct task_struct *t = ha->dpc_thread; 3450 3451 ha->dpc_thread = NULL; 3452 kthread_stop(t); 3453 } 3454 3455 qla2x00_free_device(base_vha); 3456 scsi_host_put(base_vha->host); 3457 /* 3458 * Need to NULL out local req/rsp after 3459 * qla2x00_free_device => qla2x00_free_queues frees 3460 * what these are pointing to. Or else we'll 3461 * fall over below in qla2x00_free_req/rsp_que. 3462 */ 3463 req = NULL; 3464 rsp = NULL; 3465 3466 probe_hw_failed: 3467 qla2x00_mem_free(ha); 3468 qla2x00_free_req_que(ha, req); 3469 qla2x00_free_rsp_que(ha, rsp); 3470 qla2x00_clear_drv_active(ha); 3471 3472 iospace_config_failed: 3473 if (IS_P3P_TYPE(ha)) { 3474 if (!ha->nx_pcibase) 3475 iounmap((device_reg_t *)ha->nx_pcibase); 3476 if (!ql2xdbwr) 3477 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3478 } else { 3479 if (ha->iobase) 3480 iounmap(ha->iobase); 3481 if (ha->cregbase) 3482 iounmap(ha->cregbase); 3483 } 3484 pci_release_selected_regions(ha->pdev, ha->bars); 3485 kfree(ha); 3486 3487 disable_device: 3488 pci_disable_device(pdev); 3489 return ret; 3490 } 3491 3492 static void 3493 qla2x00_shutdown(struct pci_dev *pdev) 3494 { 3495 scsi_qla_host_t *vha; 3496 struct qla_hw_data *ha; 3497 3498 vha = pci_get_drvdata(pdev); 3499 ha = vha->hw; 3500 3501 ql_log(ql_log_info, vha, 0xfffa, 3502 "Adapter shutdown\n"); 3503 3504 /* 3505 * Prevent future board_disable and wait 3506 * until any pending board_disable has completed. 3507 */ 3508 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3509 cancel_work_sync(&ha->board_disable); 3510 3511 if (!atomic_read(&pdev->enable_cnt)) 3512 return; 3513 3514 /* Notify ISPFX00 firmware */ 3515 if (IS_QLAFX00(ha)) 3516 qlafx00_driver_shutdown(vha, 20); 3517 3518 /* Turn-off FCE trace */ 3519 if (ha->flags.fce_enabled) { 3520 qla2x00_disable_fce_trace(vha, NULL, NULL); 3521 ha->flags.fce_enabled = 0; 3522 } 3523 3524 /* Turn-off EFT trace */ 3525 if (ha->eft) 3526 qla2x00_disable_eft_trace(vha); 3527 3528 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3529 if (ha->flags.fw_started) 3530 qla2x00_abort_isp_cleanup(vha); 3531 } else { 3532 /* Stop currently executing firmware. */ 3533 qla2x00_try_to_stop_firmware(vha); 3534 } 3535 3536 /* Turn adapter off line */ 3537 vha->flags.online = 0; 3538 3539 /* turn-off interrupts on the card */ 3540 if (ha->interrupts_on) { 3541 vha->flags.init_done = 0; 3542 ha->isp_ops->disable_intrs(ha); 3543 } 3544 3545 qla2x00_free_irqs(vha); 3546 3547 qla2x00_free_fw_dump(ha); 3548 3549 pci_disable_device(pdev); 3550 ql_log(ql_log_info, vha, 0xfffe, 3551 "Adapter shutdown successfully.\n"); 3552 } 3553 3554 /* Deletes all the virtual ports for a given ha */ 3555 static void 3556 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3557 { 3558 scsi_qla_host_t *vha; 3559 unsigned long flags; 3560 3561 mutex_lock(&ha->vport_lock); 3562 while (ha->cur_vport_count) { 3563 spin_lock_irqsave(&ha->vport_slock, flags); 3564 3565 BUG_ON(base_vha->list.next == &ha->vp_list); 3566 /* This assumes first entry in ha->vp_list is always base vha */ 3567 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3568 scsi_host_get(vha->host); 3569 3570 spin_unlock_irqrestore(&ha->vport_slock, flags); 3571 mutex_unlock(&ha->vport_lock); 3572 3573 fc_vport_terminate(vha->fc_vport); 3574 scsi_host_put(vha->host); 3575 3576 mutex_lock(&ha->vport_lock); 3577 } 3578 mutex_unlock(&ha->vport_lock); 3579 } 3580 3581 /* Stops all deferred work threads */ 3582 static void 3583 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3584 { 3585 /* Cancel all work and destroy DPC workqueues */ 3586 if (ha->dpc_lp_wq) { 3587 cancel_work_sync(&ha->idc_aen); 3588 destroy_workqueue(ha->dpc_lp_wq); 3589 ha->dpc_lp_wq = NULL; 3590 } 3591 3592 if (ha->dpc_hp_wq) { 3593 cancel_work_sync(&ha->nic_core_reset); 3594 cancel_work_sync(&ha->idc_state_handler); 3595 cancel_work_sync(&ha->nic_core_unrecoverable); 3596 destroy_workqueue(ha->dpc_hp_wq); 3597 ha->dpc_hp_wq = NULL; 3598 } 3599 3600 /* Kill the kernel thread for this host */ 3601 if (ha->dpc_thread) { 3602 struct task_struct *t = ha->dpc_thread; 3603 3604 /* 3605 * qla2xxx_wake_dpc checks for ->dpc_thread 3606 * so we need to zero it out. 3607 */ 3608 ha->dpc_thread = NULL; 3609 kthread_stop(t); 3610 } 3611 } 3612 3613 static void 3614 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3615 { 3616 if (IS_QLA82XX(ha)) { 3617 3618 iounmap((device_reg_t *)ha->nx_pcibase); 3619 if (!ql2xdbwr) 3620 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3621 } else { 3622 if (ha->iobase) 3623 iounmap(ha->iobase); 3624 3625 if (ha->cregbase) 3626 iounmap(ha->cregbase); 3627 3628 if (ha->mqiobase) 3629 iounmap(ha->mqiobase); 3630 3631 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3632 iounmap(ha->msixbase); 3633 } 3634 } 3635 3636 static void 3637 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3638 { 3639 if (IS_QLA8044(ha)) { 3640 qla8044_idc_lock(ha); 3641 qla8044_clear_drv_active(ha); 3642 qla8044_idc_unlock(ha); 3643 } else if (IS_QLA82XX(ha)) { 3644 qla82xx_idc_lock(ha); 3645 qla82xx_clear_drv_active(ha); 3646 qla82xx_idc_unlock(ha); 3647 } 3648 } 3649 3650 static void 3651 qla2x00_remove_one(struct pci_dev *pdev) 3652 { 3653 scsi_qla_host_t *base_vha; 3654 struct qla_hw_data *ha; 3655 3656 base_vha = pci_get_drvdata(pdev); 3657 ha = base_vha->hw; 3658 ql_log(ql_log_info, base_vha, 0xb079, 3659 "Removing driver\n"); 3660 3661 /* Indicate device removal to prevent future board_disable and wait 3662 * until any pending board_disable has completed. */ 3663 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3664 cancel_work_sync(&ha->board_disable); 3665 3666 /* 3667 * If the PCI device is disabled then there was a PCI-disconnect and 3668 * qla2x00_disable_board_on_pci_error has taken care of most of the 3669 * resources. 3670 */ 3671 if (!atomic_read(&pdev->enable_cnt)) { 3672 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3673 base_vha->gnl.l, base_vha->gnl.ldma); 3674 3675 scsi_host_put(base_vha->host); 3676 kfree(ha); 3677 pci_set_drvdata(pdev, NULL); 3678 return; 3679 } 3680 qla2x00_wait_for_hba_ready(base_vha); 3681 3682 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3683 if (ha->flags.fw_started) 3684 qla2x00_abort_isp_cleanup(base_vha); 3685 } else if (!IS_QLAFX00(ha)) { 3686 if (IS_QLA8031(ha)) { 3687 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3688 "Clearing fcoe driver presence.\n"); 3689 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3690 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3691 "Error while clearing DRV-Presence.\n"); 3692 } 3693 3694 qla2x00_try_to_stop_firmware(base_vha); 3695 } 3696 3697 qla2x00_wait_for_sess_deletion(base_vha); 3698 3699 /* 3700 * if UNLOAD flag is already set, then continue unload, 3701 * where it was set first. 3702 */ 3703 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3704 return; 3705 3706 set_bit(UNLOADING, &base_vha->dpc_flags); 3707 3708 qla_nvme_delete(base_vha); 3709 3710 dma_free_coherent(&ha->pdev->dev, 3711 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3712 3713 vfree(base_vha->scan.l); 3714 3715 if (IS_QLAFX00(ha)) 3716 qlafx00_driver_shutdown(base_vha, 20); 3717 3718 qla2x00_delete_all_vps(ha, base_vha); 3719 3720 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3721 3722 qla2x00_dfs_remove(base_vha); 3723 3724 qla84xx_put_chip(base_vha); 3725 3726 /* Disable timer */ 3727 if (base_vha->timer_active) 3728 qla2x00_stop_timer(base_vha); 3729 3730 base_vha->flags.online = 0; 3731 3732 /* free DMA memory */ 3733 if (ha->exlogin_buf) 3734 qla2x00_free_exlogin_buffer(ha); 3735 3736 /* free DMA memory */ 3737 if (ha->exchoffld_buf) 3738 qla2x00_free_exchoffld_buffer(ha); 3739 3740 qla2x00_destroy_deferred_work(ha); 3741 3742 qlt_remove_target(ha, base_vha); 3743 3744 qla2x00_free_sysfs_attr(base_vha, true); 3745 3746 fc_remove_host(base_vha->host); 3747 qlt_remove_target_resources(ha); 3748 3749 scsi_remove_host(base_vha->host); 3750 3751 qla2x00_free_device(base_vha); 3752 3753 qla2x00_clear_drv_active(ha); 3754 3755 scsi_host_put(base_vha->host); 3756 3757 qla2x00_unmap_iobases(ha); 3758 3759 pci_release_selected_regions(ha->pdev, ha->bars); 3760 kfree(ha); 3761 3762 pci_disable_pcie_error_reporting(pdev); 3763 3764 pci_disable_device(pdev); 3765 } 3766 3767 static void 3768 qla2x00_free_device(scsi_qla_host_t *vha) 3769 { 3770 struct qla_hw_data *ha = vha->hw; 3771 3772 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3773 3774 /* Disable timer */ 3775 if (vha->timer_active) 3776 qla2x00_stop_timer(vha); 3777 3778 qla25xx_delete_queues(vha); 3779 vha->flags.online = 0; 3780 3781 /* turn-off interrupts on the card */ 3782 if (ha->interrupts_on) { 3783 vha->flags.init_done = 0; 3784 ha->isp_ops->disable_intrs(ha); 3785 } 3786 3787 qla2x00_free_fcports(vha); 3788 3789 qla2x00_free_irqs(vha); 3790 3791 /* Flush the work queue and remove it */ 3792 if (ha->wq) { 3793 flush_workqueue(ha->wq); 3794 destroy_workqueue(ha->wq); 3795 ha->wq = NULL; 3796 } 3797 3798 3799 qla2x00_mem_free(ha); 3800 3801 qla82xx_md_free(vha); 3802 3803 qla2x00_free_queues(ha); 3804 } 3805 3806 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3807 { 3808 fc_port_t *fcport, *tfcport; 3809 3810 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3811 list_del(&fcport->list); 3812 qla2x00_clear_loop_id(fcport); 3813 kfree(fcport); 3814 } 3815 } 3816 3817 static inline void 3818 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3819 int defer) 3820 { 3821 struct fc_rport *rport; 3822 scsi_qla_host_t *base_vha; 3823 unsigned long flags; 3824 3825 if (!fcport->rport) 3826 return; 3827 3828 rport = fcport->rport; 3829 if (defer) { 3830 base_vha = pci_get_drvdata(vha->hw->pdev); 3831 spin_lock_irqsave(vha->host->host_lock, flags); 3832 fcport->drport = rport; 3833 spin_unlock_irqrestore(vha->host->host_lock, flags); 3834 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3835 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3836 qla2xxx_wake_dpc(base_vha); 3837 } else { 3838 int now; 3839 if (rport) { 3840 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3841 "%s %8phN. rport %p roles %x\n", 3842 __func__, fcport->port_name, rport, 3843 rport->roles); 3844 fc_remote_port_delete(rport); 3845 } 3846 qlt_do_generation_tick(vha, &now); 3847 } 3848 } 3849 3850 /* 3851 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3852 * 3853 * Input: ha = adapter block pointer. fcport = port structure pointer. 3854 * 3855 * Return: None. 3856 * 3857 * Context: 3858 */ 3859 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3860 int do_login, int defer) 3861 { 3862 if (IS_QLAFX00(vha->hw)) { 3863 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3864 qla2x00_schedule_rport_del(vha, fcport, defer); 3865 return; 3866 } 3867 3868 if (atomic_read(&fcport->state) == FCS_ONLINE && 3869 vha->vp_idx == fcport->vha->vp_idx) { 3870 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3871 qla2x00_schedule_rport_del(vha, fcport, defer); 3872 } 3873 /* 3874 * We may need to retry the login, so don't change the state of the 3875 * port but do the retries. 3876 */ 3877 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3878 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3879 3880 if (!do_login) 3881 return; 3882 3883 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3884 } 3885 3886 /* 3887 * qla2x00_mark_all_devices_lost 3888 * Updates fcport state when device goes offline. 3889 * 3890 * Input: 3891 * ha = adapter block pointer. 3892 * fcport = port structure pointer. 3893 * 3894 * Return: 3895 * None. 3896 * 3897 * Context: 3898 */ 3899 void 3900 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3901 { 3902 fc_port_t *fcport; 3903 3904 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3905 "Mark all dev lost\n"); 3906 3907 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3908 fcport->scan_state = 0; 3909 qlt_schedule_sess_for_deletion(fcport); 3910 3911 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3912 continue; 3913 3914 /* 3915 * No point in marking the device as lost, if the device is 3916 * already DEAD. 3917 */ 3918 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3919 continue; 3920 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3921 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3922 if (defer) 3923 qla2x00_schedule_rport_del(vha, fcport, defer); 3924 else if (vha->vp_idx == fcport->vha->vp_idx) 3925 qla2x00_schedule_rport_del(vha, fcport, defer); 3926 } 3927 } 3928 } 3929 3930 /* 3931 * qla2x00_mem_alloc 3932 * Allocates adapter memory. 3933 * 3934 * Returns: 3935 * 0 = success. 3936 * !0 = failure. 3937 */ 3938 static int 3939 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3940 struct req_que **req, struct rsp_que **rsp) 3941 { 3942 char name[16]; 3943 3944 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3945 &ha->init_cb_dma, GFP_KERNEL); 3946 if (!ha->init_cb) 3947 goto fail; 3948 3949 if (qlt_mem_alloc(ha) < 0) 3950 goto fail_free_init_cb; 3951 3952 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3953 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3954 if (!ha->gid_list) 3955 goto fail_free_tgt_mem; 3956 3957 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3958 if (!ha->srb_mempool) 3959 goto fail_free_gid_list; 3960 3961 if (IS_P3P_TYPE(ha)) { 3962 /* Allocate cache for CT6 Ctx. */ 3963 if (!ctx_cachep) { 3964 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3965 sizeof(struct ct6_dsd), 0, 3966 SLAB_HWCACHE_ALIGN, NULL); 3967 if (!ctx_cachep) 3968 goto fail_free_srb_mempool; 3969 } 3970 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3971 ctx_cachep); 3972 if (!ha->ctx_mempool) 3973 goto fail_free_srb_mempool; 3974 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3975 "ctx_cachep=%p ctx_mempool=%p.\n", 3976 ctx_cachep, ha->ctx_mempool); 3977 } 3978 3979 /* Get memory for cached NVRAM */ 3980 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3981 if (!ha->nvram) 3982 goto fail_free_ctx_mempool; 3983 3984 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3985 ha->pdev->device); 3986 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3987 DMA_POOL_SIZE, 8, 0); 3988 if (!ha->s_dma_pool) 3989 goto fail_free_nvram; 3990 3991 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3992 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3993 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3994 3995 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3996 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3997 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3998 if (!ha->dl_dma_pool) { 3999 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4000 "Failed to allocate memory for dl_dma_pool.\n"); 4001 goto fail_s_dma_pool; 4002 } 4003 4004 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4005 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4006 if (!ha->fcp_cmnd_dma_pool) { 4007 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4008 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4009 goto fail_dl_dma_pool; 4010 } 4011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4012 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 4013 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 4014 } 4015 4016 /* Allocate memory for SNS commands */ 4017 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4018 /* Get consistent memory allocated for SNS commands */ 4019 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4020 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4021 if (!ha->sns_cmd) 4022 goto fail_dma_pool; 4023 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4024 "sns_cmd: %p.\n", ha->sns_cmd); 4025 } else { 4026 /* Get consistent memory allocated for MS IOCB */ 4027 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4028 &ha->ms_iocb_dma); 4029 if (!ha->ms_iocb) 4030 goto fail_dma_pool; 4031 /* Get consistent memory allocated for CT SNS commands */ 4032 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4033 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4034 if (!ha->ct_sns) 4035 goto fail_free_ms_iocb; 4036 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4037 "ms_iocb=%p ct_sns=%p.\n", 4038 ha->ms_iocb, ha->ct_sns); 4039 } 4040 4041 /* Allocate memory for request ring */ 4042 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4043 if (!*req) { 4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4045 "Failed to allocate memory for req.\n"); 4046 goto fail_req; 4047 } 4048 (*req)->length = req_len; 4049 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4050 ((*req)->length + 1) * sizeof(request_t), 4051 &(*req)->dma, GFP_KERNEL); 4052 if (!(*req)->ring) { 4053 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4054 "Failed to allocate memory for req_ring.\n"); 4055 goto fail_req_ring; 4056 } 4057 /* Allocate memory for response ring */ 4058 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4059 if (!*rsp) { 4060 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4061 "Failed to allocate memory for rsp.\n"); 4062 goto fail_rsp; 4063 } 4064 (*rsp)->hw = ha; 4065 (*rsp)->length = rsp_len; 4066 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4067 ((*rsp)->length + 1) * sizeof(response_t), 4068 &(*rsp)->dma, GFP_KERNEL); 4069 if (!(*rsp)->ring) { 4070 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4071 "Failed to allocate memory for rsp_ring.\n"); 4072 goto fail_rsp_ring; 4073 } 4074 (*req)->rsp = *rsp; 4075 (*rsp)->req = *req; 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4077 "req=%p req->length=%d req->ring=%p rsp=%p " 4078 "rsp->length=%d rsp->ring=%p.\n", 4079 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4080 (*rsp)->ring); 4081 /* Allocate memory for NVRAM data for vports */ 4082 if (ha->nvram_npiv_size) { 4083 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4084 sizeof(struct qla_npiv_entry), 4085 GFP_KERNEL); 4086 if (!ha->npiv_info) { 4087 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4088 "Failed to allocate memory for npiv_info.\n"); 4089 goto fail_npiv_info; 4090 } 4091 } else 4092 ha->npiv_info = NULL; 4093 4094 /* Get consistent memory allocated for EX-INIT-CB. */ 4095 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4096 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4097 &ha->ex_init_cb_dma); 4098 if (!ha->ex_init_cb) 4099 goto fail_ex_init_cb; 4100 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4101 "ex_init_cb=%p.\n", ha->ex_init_cb); 4102 } 4103 4104 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4105 4106 /* Get consistent memory allocated for Async Port-Database. */ 4107 if (!IS_FWI2_CAPABLE(ha)) { 4108 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4109 &ha->async_pd_dma); 4110 if (!ha->async_pd) 4111 goto fail_async_pd; 4112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4113 "async_pd=%p.\n", ha->async_pd); 4114 } 4115 4116 INIT_LIST_HEAD(&ha->vp_list); 4117 4118 /* Allocate memory for our loop_id bitmap */ 4119 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4120 sizeof(long), 4121 GFP_KERNEL); 4122 if (!ha->loop_id_map) 4123 goto fail_loop_id_map; 4124 else { 4125 qla2x00_set_reserved_loop_ids(ha); 4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4127 "loop_id_map=%p.\n", ha->loop_id_map); 4128 } 4129 4130 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4131 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4132 if (!ha->sfp_data) { 4133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4134 "Unable to allocate memory for SFP read-data.\n"); 4135 goto fail_sfp_data; 4136 } 4137 4138 return 0; 4139 4140 fail_sfp_data: 4141 kfree(ha->loop_id_map); 4142 fail_loop_id_map: 4143 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4144 fail_async_pd: 4145 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4146 fail_ex_init_cb: 4147 kfree(ha->npiv_info); 4148 fail_npiv_info: 4149 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4150 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4151 (*rsp)->ring = NULL; 4152 (*rsp)->dma = 0; 4153 fail_rsp_ring: 4154 kfree(*rsp); 4155 *rsp = NULL; 4156 fail_rsp: 4157 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4158 sizeof(request_t), (*req)->ring, (*req)->dma); 4159 (*req)->ring = NULL; 4160 (*req)->dma = 0; 4161 fail_req_ring: 4162 kfree(*req); 4163 *req = NULL; 4164 fail_req: 4165 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4166 ha->ct_sns, ha->ct_sns_dma); 4167 ha->ct_sns = NULL; 4168 ha->ct_sns_dma = 0; 4169 fail_free_ms_iocb: 4170 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4171 ha->ms_iocb = NULL; 4172 ha->ms_iocb_dma = 0; 4173 4174 if (ha->sns_cmd) 4175 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4176 ha->sns_cmd, ha->sns_cmd_dma); 4177 fail_dma_pool: 4178 if (IS_QLA82XX(ha) || ql2xenabledif) { 4179 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4180 ha->fcp_cmnd_dma_pool = NULL; 4181 } 4182 fail_dl_dma_pool: 4183 if (IS_QLA82XX(ha) || ql2xenabledif) { 4184 dma_pool_destroy(ha->dl_dma_pool); 4185 ha->dl_dma_pool = NULL; 4186 } 4187 fail_s_dma_pool: 4188 dma_pool_destroy(ha->s_dma_pool); 4189 ha->s_dma_pool = NULL; 4190 fail_free_nvram: 4191 kfree(ha->nvram); 4192 ha->nvram = NULL; 4193 fail_free_ctx_mempool: 4194 if (ha->ctx_mempool) 4195 mempool_destroy(ha->ctx_mempool); 4196 ha->ctx_mempool = NULL; 4197 fail_free_srb_mempool: 4198 if (ha->srb_mempool) 4199 mempool_destroy(ha->srb_mempool); 4200 ha->srb_mempool = NULL; 4201 fail_free_gid_list: 4202 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4203 ha->gid_list, 4204 ha->gid_list_dma); 4205 ha->gid_list = NULL; 4206 ha->gid_list_dma = 0; 4207 fail_free_tgt_mem: 4208 qlt_mem_free(ha); 4209 fail_free_init_cb: 4210 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4211 ha->init_cb_dma); 4212 ha->init_cb = NULL; 4213 ha->init_cb_dma = 0; 4214 fail: 4215 ql_log(ql_log_fatal, NULL, 0x0030, 4216 "Memory allocation failure.\n"); 4217 return -ENOMEM; 4218 } 4219 4220 int 4221 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4222 { 4223 int rval; 4224 uint16_t size, max_cnt, temp; 4225 struct qla_hw_data *ha = vha->hw; 4226 4227 /* Return if we don't need to alloacate any extended logins */ 4228 if (!ql2xexlogins) 4229 return QLA_SUCCESS; 4230 4231 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4232 return QLA_SUCCESS; 4233 4234 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4235 max_cnt = 0; 4236 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4237 if (rval != QLA_SUCCESS) { 4238 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4239 "Failed to get exlogin status.\n"); 4240 return rval; 4241 } 4242 4243 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4244 temp *= size; 4245 4246 if (temp != ha->exlogin_size) { 4247 qla2x00_free_exlogin_buffer(ha); 4248 ha->exlogin_size = temp; 4249 4250 ql_log(ql_log_info, vha, 0xd024, 4251 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4252 max_cnt, size, temp); 4253 4254 ql_log(ql_log_info, vha, 0xd025, 4255 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4256 4257 /* Get consistent memory for extended logins */ 4258 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4259 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4260 if (!ha->exlogin_buf) { 4261 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4262 "Failed to allocate memory for exlogin_buf_dma.\n"); 4263 return -ENOMEM; 4264 } 4265 } 4266 4267 /* Now configure the dma buffer */ 4268 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4269 if (rval) { 4270 ql_log(ql_log_fatal, vha, 0xd033, 4271 "Setup extended login buffer ****FAILED****.\n"); 4272 qla2x00_free_exlogin_buffer(ha); 4273 } 4274 4275 return rval; 4276 } 4277 4278 /* 4279 * qla2x00_free_exlogin_buffer 4280 * 4281 * Input: 4282 * ha = adapter block pointer 4283 */ 4284 void 4285 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4286 { 4287 if (ha->exlogin_buf) { 4288 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4289 ha->exlogin_buf, ha->exlogin_buf_dma); 4290 ha->exlogin_buf = NULL; 4291 ha->exlogin_size = 0; 4292 } 4293 } 4294 4295 static void 4296 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4297 { 4298 u32 temp; 4299 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4300 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4301 4302 if (max_cnt > vha->hw->max_exchg) 4303 max_cnt = vha->hw->max_exchg; 4304 4305 if (qla_ini_mode_enabled(vha)) { 4306 if (vha->ql2xiniexchg > max_cnt) 4307 vha->ql2xiniexchg = max_cnt; 4308 4309 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4310 *ret_cnt = vha->ql2xiniexchg; 4311 4312 } else if (qla_tgt_mode_enabled(vha)) { 4313 if (vha->ql2xexchoffld > max_cnt) { 4314 vha->ql2xexchoffld = max_cnt; 4315 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4316 } 4317 4318 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4319 *ret_cnt = vha->ql2xexchoffld; 4320 } else if (qla_dual_mode_enabled(vha)) { 4321 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4322 if (temp > max_cnt) { 4323 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4324 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4325 temp = max_cnt; 4326 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4327 } 4328 4329 if (temp > FW_DEF_EXCHANGES_CNT) 4330 *ret_cnt = temp; 4331 } 4332 } 4333 4334 int 4335 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4336 { 4337 int rval; 4338 u16 size, max_cnt; 4339 u32 actual_cnt, totsz; 4340 struct qla_hw_data *ha = vha->hw; 4341 4342 if (!ha->flags.exchoffld_enabled) 4343 return QLA_SUCCESS; 4344 4345 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4346 return QLA_SUCCESS; 4347 4348 max_cnt = 0; 4349 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4350 if (rval != QLA_SUCCESS) { 4351 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4352 "Failed to get exlogin status.\n"); 4353 return rval; 4354 } 4355 4356 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4357 ql_log(ql_log_info, vha, 0xd014, 4358 "Actual exchange offload count: %d.\n", actual_cnt); 4359 4360 totsz = actual_cnt * size; 4361 4362 if (totsz != ha->exchoffld_size) { 4363 qla2x00_free_exchoffld_buffer(ha); 4364 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4365 ha->exchoffld_size = 0; 4366 ha->flags.exchoffld_enabled = 0; 4367 return QLA_SUCCESS; 4368 } 4369 4370 ha->exchoffld_size = totsz; 4371 4372 ql_log(ql_log_info, vha, 0xd016, 4373 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4374 max_cnt, actual_cnt, size, totsz); 4375 4376 ql_log(ql_log_info, vha, 0xd017, 4377 "Exchange Buffers requested size = 0x%x\n", 4378 ha->exchoffld_size); 4379 4380 /* Get consistent memory for extended logins */ 4381 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4382 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4383 if (!ha->exchoffld_buf) { 4384 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4385 "Failed to allocate memory for Exchange Offload.\n"); 4386 4387 if (ha->max_exchg > 4388 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4389 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4390 } else if (ha->max_exchg > 4391 (FW_DEF_EXCHANGES_CNT + 512)) { 4392 ha->max_exchg -= 512; 4393 } else { 4394 ha->flags.exchoffld_enabled = 0; 4395 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4396 "Disabling Exchange offload due to lack of memory\n"); 4397 } 4398 ha->exchoffld_size = 0; 4399 4400 return -ENOMEM; 4401 } 4402 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4403 /* pathological case */ 4404 qla2x00_free_exchoffld_buffer(ha); 4405 ha->exchoffld_size = 0; 4406 ha->flags.exchoffld_enabled = 0; 4407 ql_log(ql_log_info, vha, 0xd016, 4408 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4409 ha->exchoffld_size, actual_cnt, size, totsz); 4410 return 0; 4411 } 4412 4413 /* Now configure the dma buffer */ 4414 rval = qla_set_exchoffld_mem_cfg(vha); 4415 if (rval) { 4416 ql_log(ql_log_fatal, vha, 0xd02e, 4417 "Setup exchange offload buffer ****FAILED****.\n"); 4418 qla2x00_free_exchoffld_buffer(ha); 4419 } else { 4420 /* re-adjust number of target exchange */ 4421 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4422 4423 if (qla_ini_mode_enabled(vha)) 4424 icb->exchange_count = 0; 4425 else 4426 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4427 } 4428 4429 return rval; 4430 } 4431 4432 /* 4433 * qla2x00_free_exchoffld_buffer 4434 * 4435 * Input: 4436 * ha = adapter block pointer 4437 */ 4438 void 4439 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4440 { 4441 if (ha->exchoffld_buf) { 4442 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4443 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4444 ha->exchoffld_buf = NULL; 4445 ha->exchoffld_size = 0; 4446 } 4447 } 4448 4449 /* 4450 * qla2x00_free_fw_dump 4451 * Frees fw dump stuff. 4452 * 4453 * Input: 4454 * ha = adapter block pointer 4455 */ 4456 static void 4457 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4458 { 4459 if (ha->fce) 4460 dma_free_coherent(&ha->pdev->dev, 4461 FCE_SIZE, ha->fce, ha->fce_dma); 4462 4463 if (ha->eft) 4464 dma_free_coherent(&ha->pdev->dev, 4465 EFT_SIZE, ha->eft, ha->eft_dma); 4466 4467 if (ha->fw_dump) 4468 vfree(ha->fw_dump); 4469 if (ha->fw_dump_template) 4470 vfree(ha->fw_dump_template); 4471 4472 ha->fce = NULL; 4473 ha->fce_dma = 0; 4474 ha->eft = NULL; 4475 ha->eft_dma = 0; 4476 ha->fw_dumped = 0; 4477 ha->fw_dump_cap_flags = 0; 4478 ha->fw_dump_reading = 0; 4479 ha->fw_dump = NULL; 4480 ha->fw_dump_len = 0; 4481 ha->fw_dump_template = NULL; 4482 ha->fw_dump_template_len = 0; 4483 } 4484 4485 /* 4486 * qla2x00_mem_free 4487 * Frees all adapter allocated memory. 4488 * 4489 * Input: 4490 * ha = adapter block pointer. 4491 */ 4492 static void 4493 qla2x00_mem_free(struct qla_hw_data *ha) 4494 { 4495 qla2x00_free_fw_dump(ha); 4496 4497 if (ha->mctp_dump) 4498 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4499 ha->mctp_dump_dma); 4500 4501 if (ha->srb_mempool) 4502 mempool_destroy(ha->srb_mempool); 4503 4504 if (ha->dcbx_tlv) 4505 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4506 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4507 4508 if (ha->xgmac_data) 4509 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4510 ha->xgmac_data, ha->xgmac_data_dma); 4511 4512 if (ha->sns_cmd) 4513 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4514 ha->sns_cmd, ha->sns_cmd_dma); 4515 4516 if (ha->ct_sns) 4517 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4518 ha->ct_sns, ha->ct_sns_dma); 4519 4520 if (ha->sfp_data) 4521 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4522 ha->sfp_data_dma); 4523 4524 if (ha->ms_iocb) 4525 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4526 4527 if (ha->ex_init_cb) 4528 dma_pool_free(ha->s_dma_pool, 4529 ha->ex_init_cb, ha->ex_init_cb_dma); 4530 4531 if (ha->async_pd) 4532 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4533 4534 if (ha->s_dma_pool) 4535 dma_pool_destroy(ha->s_dma_pool); 4536 4537 if (ha->gid_list) 4538 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4539 ha->gid_list, ha->gid_list_dma); 4540 4541 if (IS_QLA82XX(ha)) { 4542 if (!list_empty(&ha->gbl_dsd_list)) { 4543 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4544 4545 /* clean up allocated prev pool */ 4546 list_for_each_entry_safe(dsd_ptr, 4547 tdsd_ptr, &ha->gbl_dsd_list, list) { 4548 dma_pool_free(ha->dl_dma_pool, 4549 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4550 list_del(&dsd_ptr->list); 4551 kfree(dsd_ptr); 4552 } 4553 } 4554 } 4555 4556 if (ha->dl_dma_pool) 4557 dma_pool_destroy(ha->dl_dma_pool); 4558 4559 if (ha->fcp_cmnd_dma_pool) 4560 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4561 4562 if (ha->ctx_mempool) 4563 mempool_destroy(ha->ctx_mempool); 4564 4565 qlt_mem_free(ha); 4566 4567 if (ha->init_cb) 4568 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4569 ha->init_cb, ha->init_cb_dma); 4570 4571 vfree(ha->optrom_buffer); 4572 kfree(ha->nvram); 4573 kfree(ha->npiv_info); 4574 kfree(ha->swl); 4575 kfree(ha->loop_id_map); 4576 4577 ha->srb_mempool = NULL; 4578 ha->ctx_mempool = NULL; 4579 ha->sns_cmd = NULL; 4580 ha->sns_cmd_dma = 0; 4581 ha->ct_sns = NULL; 4582 ha->ct_sns_dma = 0; 4583 ha->ms_iocb = NULL; 4584 ha->ms_iocb_dma = 0; 4585 ha->init_cb = NULL; 4586 ha->init_cb_dma = 0; 4587 ha->ex_init_cb = NULL; 4588 ha->ex_init_cb_dma = 0; 4589 ha->async_pd = NULL; 4590 ha->async_pd_dma = 0; 4591 ha->loop_id_map = NULL; 4592 ha->npiv_info = NULL; 4593 ha->optrom_buffer = NULL; 4594 ha->swl = NULL; 4595 ha->nvram = NULL; 4596 ha->mctp_dump = NULL; 4597 ha->dcbx_tlv = NULL; 4598 ha->xgmac_data = NULL; 4599 ha->sfp_data = NULL; 4600 4601 ha->s_dma_pool = NULL; 4602 ha->dl_dma_pool = NULL; 4603 ha->fcp_cmnd_dma_pool = NULL; 4604 4605 ha->gid_list = NULL; 4606 ha->gid_list_dma = 0; 4607 4608 ha->tgt.atio_ring = NULL; 4609 ha->tgt.atio_dma = 0; 4610 ha->tgt.tgt_vp_map = NULL; 4611 } 4612 4613 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4614 struct qla_hw_data *ha) 4615 { 4616 struct Scsi_Host *host; 4617 struct scsi_qla_host *vha = NULL; 4618 4619 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4620 if (!host) { 4621 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4622 "Failed to allocate host from the scsi layer, aborting.\n"); 4623 return NULL; 4624 } 4625 4626 /* Clear our data area */ 4627 vha = shost_priv(host); 4628 memset(vha, 0, sizeof(scsi_qla_host_t)); 4629 4630 vha->host = host; 4631 vha->host_no = host->host_no; 4632 vha->hw = ha; 4633 4634 vha->qlini_mode = ql2x_ini_mode; 4635 vha->ql2xexchoffld = ql2xexchoffld; 4636 vha->ql2xiniexchg = ql2xiniexchg; 4637 4638 INIT_LIST_HEAD(&vha->vp_fcports); 4639 INIT_LIST_HEAD(&vha->work_list); 4640 INIT_LIST_HEAD(&vha->list); 4641 INIT_LIST_HEAD(&vha->qla_cmd_list); 4642 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4643 INIT_LIST_HEAD(&vha->logo_list); 4644 INIT_LIST_HEAD(&vha->plogi_ack_list); 4645 INIT_LIST_HEAD(&vha->qp_list); 4646 INIT_LIST_HEAD(&vha->gnl.fcports); 4647 INIT_LIST_HEAD(&vha->nvme_rport_list); 4648 INIT_LIST_HEAD(&vha->gpnid_list); 4649 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4650 4651 spin_lock_init(&vha->work_lock); 4652 spin_lock_init(&vha->cmd_list_lock); 4653 init_waitqueue_head(&vha->fcport_waitQ); 4654 init_waitqueue_head(&vha->vref_waitq); 4655 4656 vha->gnl.size = sizeof(struct get_name_list_extended) * 4657 (ha->max_loop_id + 1); 4658 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4659 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4660 if (!vha->gnl.l) { 4661 ql_log(ql_log_fatal, vha, 0xd04a, 4662 "Alloc failed for name list.\n"); 4663 scsi_remove_host(vha->host); 4664 return NULL; 4665 } 4666 4667 /* todo: what about ext login? */ 4668 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4669 vha->scan.l = vmalloc(vha->scan.size); 4670 if (!vha->scan.l) { 4671 ql_log(ql_log_fatal, vha, 0xd04a, 4672 "Alloc failed for scan database.\n"); 4673 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4674 vha->gnl.l, vha->gnl.ldma); 4675 scsi_remove_host(vha->host); 4676 return NULL; 4677 } 4678 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4679 4680 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4681 ql_dbg(ql_dbg_init, vha, 0x0041, 4682 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4683 vha->host, vha->hw, vha, 4684 dev_name(&(ha->pdev->dev))); 4685 4686 return vha; 4687 } 4688 4689 struct qla_work_evt * 4690 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4691 { 4692 struct qla_work_evt *e; 4693 uint8_t bail; 4694 4695 QLA_VHA_MARK_BUSY(vha, bail); 4696 if (bail) 4697 return NULL; 4698 4699 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4700 if (!e) { 4701 QLA_VHA_MARK_NOT_BUSY(vha); 4702 return NULL; 4703 } 4704 4705 INIT_LIST_HEAD(&e->list); 4706 e->type = type; 4707 e->flags = QLA_EVT_FLAG_FREE; 4708 return e; 4709 } 4710 4711 int 4712 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4713 { 4714 unsigned long flags; 4715 bool q = false; 4716 4717 spin_lock_irqsave(&vha->work_lock, flags); 4718 list_add_tail(&e->list, &vha->work_list); 4719 4720 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4721 q = true; 4722 4723 spin_unlock_irqrestore(&vha->work_lock, flags); 4724 4725 if (q) 4726 queue_work(vha->hw->wq, &vha->iocb_work); 4727 4728 return QLA_SUCCESS; 4729 } 4730 4731 int 4732 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4733 u32 data) 4734 { 4735 struct qla_work_evt *e; 4736 4737 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4738 if (!e) 4739 return QLA_FUNCTION_FAILED; 4740 4741 e->u.aen.code = code; 4742 e->u.aen.data = data; 4743 return qla2x00_post_work(vha, e); 4744 } 4745 4746 int 4747 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4748 { 4749 struct qla_work_evt *e; 4750 4751 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4752 if (!e) 4753 return QLA_FUNCTION_FAILED; 4754 4755 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4756 return qla2x00_post_work(vha, e); 4757 } 4758 4759 #define qla2x00_post_async_work(name, type) \ 4760 int qla2x00_post_async_##name##_work( \ 4761 struct scsi_qla_host *vha, \ 4762 fc_port_t *fcport, uint16_t *data) \ 4763 { \ 4764 struct qla_work_evt *e; \ 4765 \ 4766 e = qla2x00_alloc_work(vha, type); \ 4767 if (!e) \ 4768 return QLA_FUNCTION_FAILED; \ 4769 \ 4770 e->u.logio.fcport = fcport; \ 4771 if (data) { \ 4772 e->u.logio.data[0] = data[0]; \ 4773 e->u.logio.data[1] = data[1]; \ 4774 } \ 4775 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4776 return qla2x00_post_work(vha, e); \ 4777 } 4778 4779 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4780 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4781 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4782 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4783 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4784 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4785 4786 int 4787 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4788 { 4789 struct qla_work_evt *e; 4790 4791 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4792 if (!e) 4793 return QLA_FUNCTION_FAILED; 4794 4795 e->u.uevent.code = code; 4796 return qla2x00_post_work(vha, e); 4797 } 4798 4799 static void 4800 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4801 { 4802 char event_string[40]; 4803 char *envp[] = { event_string, NULL }; 4804 4805 switch (code) { 4806 case QLA_UEVENT_CODE_FW_DUMP: 4807 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4808 vha->host_no); 4809 break; 4810 default: 4811 /* do nothing */ 4812 break; 4813 } 4814 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4815 } 4816 4817 int 4818 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4819 uint32_t *data, int cnt) 4820 { 4821 struct qla_work_evt *e; 4822 4823 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4824 if (!e) 4825 return QLA_FUNCTION_FAILED; 4826 4827 e->u.aenfx.evtcode = evtcode; 4828 e->u.aenfx.count = cnt; 4829 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4830 return qla2x00_post_work(vha, e); 4831 } 4832 4833 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 4834 { 4835 unsigned long flags; 4836 4837 if (IS_SW_RESV_ADDR(fcport->d_id)) 4838 return; 4839 4840 spin_lock_irqsave(&fcport->vha->work_lock, flags); 4841 if (fcport->disc_state == DSC_UPD_FCPORT) { 4842 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4843 return; 4844 } 4845 fcport->jiffies_at_registration = jiffies; 4846 fcport->sec_since_registration = 0; 4847 fcport->next_disc_state = DSC_DELETED; 4848 fcport->disc_state = DSC_UPD_FCPORT; 4849 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4850 4851 queue_work(system_unbound_wq, &fcport->reg_work); 4852 } 4853 4854 static 4855 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4856 { 4857 unsigned long flags; 4858 fc_port_t *fcport = NULL, *tfcp; 4859 struct qlt_plogi_ack_t *pla = 4860 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4861 uint8_t free_fcport = 0; 4862 4863 ql_dbg(ql_dbg_disc, vha, 0xffff, 4864 "%s %d %8phC enter\n", 4865 __func__, __LINE__, e->u.new_sess.port_name); 4866 4867 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4868 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4869 if (fcport) { 4870 fcport->d_id = e->u.new_sess.id; 4871 if (pla) { 4872 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4873 memcpy(fcport->node_name, 4874 pla->iocb.u.isp24.u.plogi.node_name, 4875 WWN_SIZE); 4876 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4877 /* we took an extra ref_count to prevent PLOGI ACK when 4878 * fcport/sess has not been created. 4879 */ 4880 pla->ref_count--; 4881 } 4882 } else { 4883 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4884 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4885 if (fcport) { 4886 fcport->d_id = e->u.new_sess.id; 4887 fcport->flags |= FCF_FABRIC_DEVICE; 4888 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4889 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP) 4890 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4891 4892 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) { 4893 fcport->fc4_type = FC4_TYPE_OTHER; 4894 fcport->fc4f_nvme = FC4_TYPE_NVME; 4895 } 4896 4897 memcpy(fcport->port_name, e->u.new_sess.port_name, 4898 WWN_SIZE); 4899 } else { 4900 ql_dbg(ql_dbg_disc, vha, 0xffff, 4901 "%s %8phC mem alloc fail.\n", 4902 __func__, e->u.new_sess.port_name); 4903 4904 if (pla) 4905 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4906 return; 4907 } 4908 4909 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4910 /* search again to make sure no one else got ahead */ 4911 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4912 e->u.new_sess.port_name, 1); 4913 if (tfcp) { 4914 /* should rarily happen */ 4915 ql_dbg(ql_dbg_disc, vha, 0xffff, 4916 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4917 __func__, tfcp->port_name, tfcp->disc_state, 4918 tfcp->fw_login_state); 4919 4920 free_fcport = 1; 4921 } else { 4922 list_add_tail(&fcport->list, &vha->vp_fcports); 4923 4924 } 4925 if (pla) { 4926 qlt_plogi_ack_link(vha, pla, fcport, 4927 QLT_PLOGI_LINK_SAME_WWN); 4928 pla->ref_count--; 4929 } 4930 } 4931 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4932 4933 if (fcport) { 4934 fcport->id_changed = 1; 4935 fcport->scan_state = QLA_FCPORT_FOUND; 4936 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4937 4938 if (pla) { 4939 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4940 u16 wd3_lo; 4941 4942 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4943 fcport->local = 0; 4944 fcport->loop_id = 4945 le16_to_cpu( 4946 pla->iocb.u.isp24.nport_handle); 4947 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4948 wd3_lo = 4949 le16_to_cpu( 4950 pla->iocb.u.isp24.u.prli.wd3_lo); 4951 4952 if (wd3_lo & BIT_7) 4953 fcport->conf_compl_supported = 1; 4954 4955 if ((wd3_lo & BIT_4) == 0) 4956 fcport->port_type = FCT_INITIATOR; 4957 else 4958 fcport->port_type = FCT_TARGET; 4959 } 4960 qlt_plogi_ack_unref(vha, pla); 4961 } else { 4962 fc_port_t *dfcp = NULL; 4963 4964 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4965 tfcp = qla2x00_find_fcport_by_nportid(vha, 4966 &e->u.new_sess.id, 1); 4967 if (tfcp && (tfcp != fcport)) { 4968 /* 4969 * We have a conflict fcport with same NportID. 4970 */ 4971 ql_dbg(ql_dbg_disc, vha, 0xffff, 4972 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4973 __func__, tfcp->port_name, tfcp->disc_state, 4974 tfcp->fw_login_state); 4975 4976 switch (tfcp->disc_state) { 4977 case DSC_DELETED: 4978 break; 4979 case DSC_DELETE_PEND: 4980 fcport->login_pause = 1; 4981 tfcp->conflict = fcport; 4982 break; 4983 default: 4984 fcport->login_pause = 1; 4985 tfcp->conflict = fcport; 4986 dfcp = tfcp; 4987 break; 4988 } 4989 } 4990 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4991 if (dfcp) 4992 qlt_schedule_sess_for_deletion(tfcp); 4993 4994 4995 if (N2N_TOPO(vha->hw)) 4996 fcport->flags &= ~FCF_FABRIC_DEVICE; 4997 4998 if (N2N_TOPO(vha->hw)) { 4999 if (vha->flags.nvme_enabled) { 5000 fcport->fc4f_nvme = 1; 5001 fcport->n2n_flag = 1; 5002 } 5003 fcport->fw_login_state = 0; 5004 /* 5005 * wait link init done before sending login 5006 */ 5007 } else { 5008 qla24xx_fcport_handle_login(vha, fcport); 5009 } 5010 } 5011 } 5012 5013 if (free_fcport) { 5014 qla2x00_free_fcport(fcport); 5015 if (pla) 5016 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5017 } 5018 } 5019 5020 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5021 { 5022 struct srb *sp = e->u.iosb.sp; 5023 int rval; 5024 5025 rval = qla2x00_start_sp(sp); 5026 if (rval != QLA_SUCCESS) { 5027 ql_dbg(ql_dbg_disc, vha, 0x2043, 5028 "%s: %s: Re-issue IOCB failed (%d).\n", 5029 __func__, sp->name, rval); 5030 qla24xx_sp_unmap(vha, sp); 5031 } 5032 } 5033 5034 void 5035 qla2x00_do_work(struct scsi_qla_host *vha) 5036 { 5037 struct qla_work_evt *e, *tmp; 5038 unsigned long flags; 5039 LIST_HEAD(work); 5040 5041 spin_lock_irqsave(&vha->work_lock, flags); 5042 list_splice_init(&vha->work_list, &work); 5043 spin_unlock_irqrestore(&vha->work_lock, flags); 5044 5045 list_for_each_entry_safe(e, tmp, &work, list) { 5046 list_del_init(&e->list); 5047 5048 switch (e->type) { 5049 case QLA_EVT_AEN: 5050 fc_host_post_event(vha->host, fc_get_event_number(), 5051 e->u.aen.code, e->u.aen.data); 5052 break; 5053 case QLA_EVT_IDC_ACK: 5054 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5055 break; 5056 case QLA_EVT_ASYNC_LOGIN: 5057 qla2x00_async_login(vha, e->u.logio.fcport, 5058 e->u.logio.data); 5059 break; 5060 case QLA_EVT_ASYNC_LOGOUT: 5061 qla2x00_async_logout(vha, e->u.logio.fcport); 5062 break; 5063 case QLA_EVT_ASYNC_LOGOUT_DONE: 5064 qla2x00_async_logout_done(vha, e->u.logio.fcport, 5065 e->u.logio.data); 5066 break; 5067 case QLA_EVT_ASYNC_ADISC: 5068 qla2x00_async_adisc(vha, e->u.logio.fcport, 5069 e->u.logio.data); 5070 break; 5071 case QLA_EVT_UEVENT: 5072 qla2x00_uevent_emit(vha, e->u.uevent.code); 5073 break; 5074 case QLA_EVT_AENFX: 5075 qlafx00_process_aen(vha, e); 5076 break; 5077 case QLA_EVT_GPNID: 5078 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5079 break; 5080 case QLA_EVT_UNMAP: 5081 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5082 break; 5083 case QLA_EVT_RELOGIN: 5084 qla2x00_relogin(vha); 5085 break; 5086 case QLA_EVT_NEW_SESS: 5087 qla24xx_create_new_sess(vha, e); 5088 break; 5089 case QLA_EVT_GPDB: 5090 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5091 e->u.fcport.opt); 5092 break; 5093 case QLA_EVT_PRLI: 5094 qla24xx_async_prli(vha, e->u.fcport.fcport); 5095 break; 5096 case QLA_EVT_GPSC: 5097 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5098 break; 5099 case QLA_EVT_GNL: 5100 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5101 break; 5102 case QLA_EVT_NACK: 5103 qla24xx_do_nack_work(vha, e); 5104 break; 5105 case QLA_EVT_ASYNC_PRLO: 5106 qla2x00_async_prlo(vha, e->u.logio.fcport); 5107 break; 5108 case QLA_EVT_ASYNC_PRLO_DONE: 5109 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5110 e->u.logio.data); 5111 break; 5112 case QLA_EVT_GPNFT: 5113 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5114 e->u.gpnft.sp); 5115 break; 5116 case QLA_EVT_GPNFT_DONE: 5117 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5118 break; 5119 case QLA_EVT_GNNFT_DONE: 5120 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5121 break; 5122 case QLA_EVT_GNNID: 5123 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5124 break; 5125 case QLA_EVT_GFPNID: 5126 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5127 break; 5128 case QLA_EVT_SP_RETRY: 5129 qla_sp_retry(vha, e); 5130 break; 5131 case QLA_EVT_IIDMA: 5132 qla_do_iidma_work(vha, e->u.fcport.fcport); 5133 break; 5134 case QLA_EVT_ELS_PLOGI: 5135 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5136 e->u.fcport.fcport, false); 5137 break; 5138 } 5139 if (e->flags & QLA_EVT_FLAG_FREE) 5140 kfree(e); 5141 5142 /* For each work completed decrement vha ref count */ 5143 QLA_VHA_MARK_NOT_BUSY(vha); 5144 } 5145 } 5146 5147 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5148 { 5149 struct qla_work_evt *e; 5150 5151 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5152 5153 if (!e) { 5154 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5155 return QLA_FUNCTION_FAILED; 5156 } 5157 5158 return qla2x00_post_work(vha, e); 5159 } 5160 5161 /* Relogins all the fcports of a vport 5162 * Context: dpc thread 5163 */ 5164 void qla2x00_relogin(struct scsi_qla_host *vha) 5165 { 5166 fc_port_t *fcport; 5167 int status, relogin_needed = 0; 5168 struct event_arg ea; 5169 5170 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5171 /* 5172 * If the port is not ONLINE then try to login 5173 * to it if we haven't run out of retries. 5174 */ 5175 if (atomic_read(&fcport->state) != FCS_ONLINE && 5176 fcport->login_retry) { 5177 if (fcport->scan_state != QLA_FCPORT_FOUND || 5178 fcport->disc_state == DSC_LOGIN_COMPLETE) 5179 continue; 5180 5181 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5182 fcport->disc_state == DSC_DELETE_PEND) { 5183 relogin_needed = 1; 5184 } else { 5185 if (vha->hw->current_topology != ISP_CFG_NL) { 5186 memset(&ea, 0, sizeof(ea)); 5187 ea.event = FCME_RELOGIN; 5188 ea.fcport = fcport; 5189 qla2x00_fcport_event_handler(vha, &ea); 5190 } else if (vha->hw->current_topology == 5191 ISP_CFG_NL) { 5192 fcport->login_retry--; 5193 status = 5194 qla2x00_local_device_login(vha, 5195 fcport); 5196 if (status == QLA_SUCCESS) { 5197 fcport->old_loop_id = 5198 fcport->loop_id; 5199 ql_dbg(ql_dbg_disc, vha, 0x2003, 5200 "Port login OK: logged in ID 0x%x.\n", 5201 fcport->loop_id); 5202 qla2x00_update_fcport 5203 (vha, fcport); 5204 } else if (status == 1) { 5205 set_bit(RELOGIN_NEEDED, 5206 &vha->dpc_flags); 5207 /* retry the login again */ 5208 ql_dbg(ql_dbg_disc, vha, 0x2007, 5209 "Retrying %d login again loop_id 0x%x.\n", 5210 fcport->login_retry, 5211 fcport->loop_id); 5212 } else { 5213 fcport->login_retry = 0; 5214 } 5215 5216 if (fcport->login_retry == 0 && 5217 status != QLA_SUCCESS) 5218 qla2x00_clear_loop_id(fcport); 5219 } 5220 } 5221 } 5222 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5223 break; 5224 } 5225 5226 if (relogin_needed) 5227 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5228 5229 ql_dbg(ql_dbg_disc, vha, 0x400e, 5230 "Relogin end.\n"); 5231 } 5232 5233 /* Schedule work on any of the dpc-workqueues */ 5234 void 5235 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5236 { 5237 struct qla_hw_data *ha = base_vha->hw; 5238 5239 switch (work_code) { 5240 case MBA_IDC_AEN: /* 0x8200 */ 5241 if (ha->dpc_lp_wq) 5242 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5243 break; 5244 5245 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5246 if (!ha->flags.nic_core_reset_hdlr_active) { 5247 if (ha->dpc_hp_wq) 5248 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5249 } else 5250 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5251 "NIC Core reset is already active. Skip " 5252 "scheduling it again.\n"); 5253 break; 5254 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5255 if (ha->dpc_hp_wq) 5256 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5257 break; 5258 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5259 if (ha->dpc_hp_wq) 5260 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5261 break; 5262 default: 5263 ql_log(ql_log_warn, base_vha, 0xb05f, 5264 "Unknown work-code=0x%x.\n", work_code); 5265 } 5266 5267 return; 5268 } 5269 5270 /* Work: Perform NIC Core Unrecoverable state handling */ 5271 void 5272 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5273 { 5274 struct qla_hw_data *ha = 5275 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5276 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5277 uint32_t dev_state = 0; 5278 5279 qla83xx_idc_lock(base_vha, 0); 5280 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5281 qla83xx_reset_ownership(base_vha); 5282 if (ha->flags.nic_core_reset_owner) { 5283 ha->flags.nic_core_reset_owner = 0; 5284 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5285 QLA8XXX_DEV_FAILED); 5286 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5287 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5288 } 5289 qla83xx_idc_unlock(base_vha, 0); 5290 } 5291 5292 /* Work: Execute IDC state handler */ 5293 void 5294 qla83xx_idc_state_handler_work(struct work_struct *work) 5295 { 5296 struct qla_hw_data *ha = 5297 container_of(work, struct qla_hw_data, idc_state_handler); 5298 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5299 uint32_t dev_state = 0; 5300 5301 qla83xx_idc_lock(base_vha, 0); 5302 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5303 if (dev_state == QLA8XXX_DEV_FAILED || 5304 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5305 qla83xx_idc_state_handler(base_vha); 5306 qla83xx_idc_unlock(base_vha, 0); 5307 } 5308 5309 static int 5310 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5311 { 5312 int rval = QLA_SUCCESS; 5313 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5314 uint32_t heart_beat_counter1, heart_beat_counter2; 5315 5316 do { 5317 if (time_after(jiffies, heart_beat_wait)) { 5318 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5319 "Nic Core f/w is not alive.\n"); 5320 rval = QLA_FUNCTION_FAILED; 5321 break; 5322 } 5323 5324 qla83xx_idc_lock(base_vha, 0); 5325 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5326 &heart_beat_counter1); 5327 qla83xx_idc_unlock(base_vha, 0); 5328 msleep(100); 5329 qla83xx_idc_lock(base_vha, 0); 5330 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5331 &heart_beat_counter2); 5332 qla83xx_idc_unlock(base_vha, 0); 5333 } while (heart_beat_counter1 == heart_beat_counter2); 5334 5335 return rval; 5336 } 5337 5338 /* Work: Perform NIC Core Reset handling */ 5339 void 5340 qla83xx_nic_core_reset_work(struct work_struct *work) 5341 { 5342 struct qla_hw_data *ha = 5343 container_of(work, struct qla_hw_data, nic_core_reset); 5344 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5345 uint32_t dev_state = 0; 5346 5347 if (IS_QLA2031(ha)) { 5348 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5349 ql_log(ql_log_warn, base_vha, 0xb081, 5350 "Failed to dump mctp\n"); 5351 return; 5352 } 5353 5354 if (!ha->flags.nic_core_reset_hdlr_active) { 5355 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5356 qla83xx_idc_lock(base_vha, 0); 5357 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5358 &dev_state); 5359 qla83xx_idc_unlock(base_vha, 0); 5360 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5361 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5362 "Nic Core f/w is alive.\n"); 5363 return; 5364 } 5365 } 5366 5367 ha->flags.nic_core_reset_hdlr_active = 1; 5368 if (qla83xx_nic_core_reset(base_vha)) { 5369 /* NIC Core reset failed. */ 5370 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5371 "NIC Core reset failed.\n"); 5372 } 5373 ha->flags.nic_core_reset_hdlr_active = 0; 5374 } 5375 } 5376 5377 /* Work: Handle 8200 IDC aens */ 5378 void 5379 qla83xx_service_idc_aen(struct work_struct *work) 5380 { 5381 struct qla_hw_data *ha = 5382 container_of(work, struct qla_hw_data, idc_aen); 5383 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5384 uint32_t dev_state, idc_control; 5385 5386 qla83xx_idc_lock(base_vha, 0); 5387 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5388 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5389 qla83xx_idc_unlock(base_vha, 0); 5390 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5391 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5392 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5393 "Application requested NIC Core Reset.\n"); 5394 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5395 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5396 QLA_SUCCESS) { 5397 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5398 "Other protocol driver requested NIC Core Reset.\n"); 5399 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5400 } 5401 } else if (dev_state == QLA8XXX_DEV_FAILED || 5402 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5403 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5404 } 5405 } 5406 5407 static void 5408 qla83xx_wait_logic(void) 5409 { 5410 int i; 5411 5412 /* Yield CPU */ 5413 if (!in_interrupt()) { 5414 /* 5415 * Wait about 200ms before retrying again. 5416 * This controls the number of retries for single 5417 * lock operation. 5418 */ 5419 msleep(100); 5420 schedule(); 5421 } else { 5422 for (i = 0; i < 20; i++) 5423 cpu_relax(); /* This a nop instr on i386 */ 5424 } 5425 } 5426 5427 static int 5428 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5429 { 5430 int rval; 5431 uint32_t data; 5432 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5433 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5434 struct qla_hw_data *ha = base_vha->hw; 5435 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5436 "Trying force recovery of the IDC lock.\n"); 5437 5438 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5439 if (rval) 5440 return rval; 5441 5442 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5443 return QLA_SUCCESS; 5444 } else { 5445 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5446 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5447 data); 5448 if (rval) 5449 return rval; 5450 5451 msleep(200); 5452 5453 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5454 &data); 5455 if (rval) 5456 return rval; 5457 5458 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5459 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5460 ~(idc_lck_rcvry_stage_mask)); 5461 rval = qla83xx_wr_reg(base_vha, 5462 QLA83XX_IDC_LOCK_RECOVERY, data); 5463 if (rval) 5464 return rval; 5465 5466 /* Forcefully perform IDC UnLock */ 5467 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5468 &data); 5469 if (rval) 5470 return rval; 5471 /* Clear lock-id by setting 0xff */ 5472 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5473 0xff); 5474 if (rval) 5475 return rval; 5476 /* Clear lock-recovery by setting 0x0 */ 5477 rval = qla83xx_wr_reg(base_vha, 5478 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5479 if (rval) 5480 return rval; 5481 } else 5482 return QLA_SUCCESS; 5483 } 5484 5485 return rval; 5486 } 5487 5488 static int 5489 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5490 { 5491 int rval = QLA_SUCCESS; 5492 uint32_t o_drv_lockid, n_drv_lockid; 5493 unsigned long lock_recovery_timeout; 5494 5495 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5496 retry_lockid: 5497 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5498 if (rval) 5499 goto exit; 5500 5501 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5502 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5503 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5504 return QLA_SUCCESS; 5505 else 5506 return QLA_FUNCTION_FAILED; 5507 } 5508 5509 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5510 if (rval) 5511 goto exit; 5512 5513 if (o_drv_lockid == n_drv_lockid) { 5514 qla83xx_wait_logic(); 5515 goto retry_lockid; 5516 } else 5517 return QLA_SUCCESS; 5518 5519 exit: 5520 return rval; 5521 } 5522 5523 void 5524 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5525 { 5526 uint16_t options = (requester_id << 15) | BIT_6; 5527 uint32_t data; 5528 uint32_t lock_owner; 5529 struct qla_hw_data *ha = base_vha->hw; 5530 5531 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5532 retry_lock: 5533 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5534 == QLA_SUCCESS) { 5535 if (data) { 5536 /* Setting lock-id to our function-number */ 5537 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5538 ha->portnum); 5539 } else { 5540 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5541 &lock_owner); 5542 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5543 "Failed to acquire IDC lock, acquired by %d, " 5544 "retrying...\n", lock_owner); 5545 5546 /* Retry/Perform IDC-Lock recovery */ 5547 if (qla83xx_idc_lock_recovery(base_vha) 5548 == QLA_SUCCESS) { 5549 qla83xx_wait_logic(); 5550 goto retry_lock; 5551 } else 5552 ql_log(ql_log_warn, base_vha, 0xb075, 5553 "IDC Lock recovery FAILED.\n"); 5554 } 5555 5556 } 5557 5558 return; 5559 5560 /* XXX: IDC-lock implementation using access-control mbx */ 5561 retry_lock2: 5562 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5563 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5564 "Failed to acquire IDC lock. retrying...\n"); 5565 /* Retry/Perform IDC-Lock recovery */ 5566 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5567 qla83xx_wait_logic(); 5568 goto retry_lock2; 5569 } else 5570 ql_log(ql_log_warn, base_vha, 0xb076, 5571 "IDC Lock recovery FAILED.\n"); 5572 } 5573 5574 return; 5575 } 5576 5577 void 5578 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5579 { 5580 #if 0 5581 uint16_t options = (requester_id << 15) | BIT_7; 5582 #endif 5583 uint16_t retry; 5584 uint32_t data; 5585 struct qla_hw_data *ha = base_vha->hw; 5586 5587 /* IDC-unlock implementation using driver-unlock/lock-id 5588 * remote registers 5589 */ 5590 retry = 0; 5591 retry_unlock: 5592 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5593 == QLA_SUCCESS) { 5594 if (data == ha->portnum) { 5595 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5596 /* Clearing lock-id by setting 0xff */ 5597 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5598 } else if (retry < 10) { 5599 /* SV: XXX: IDC unlock retrying needed here? */ 5600 5601 /* Retry for IDC-unlock */ 5602 qla83xx_wait_logic(); 5603 retry++; 5604 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5605 "Failed to release IDC lock, retrying=%d\n", retry); 5606 goto retry_unlock; 5607 } 5608 } else if (retry < 10) { 5609 /* Retry for IDC-unlock */ 5610 qla83xx_wait_logic(); 5611 retry++; 5612 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5613 "Failed to read drv-lockid, retrying=%d\n", retry); 5614 goto retry_unlock; 5615 } 5616 5617 return; 5618 5619 #if 0 5620 /* XXX: IDC-unlock implementation using access-control mbx */ 5621 retry = 0; 5622 retry_unlock2: 5623 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5624 if (retry < 10) { 5625 /* Retry for IDC-unlock */ 5626 qla83xx_wait_logic(); 5627 retry++; 5628 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5629 "Failed to release IDC lock, retrying=%d\n", retry); 5630 goto retry_unlock2; 5631 } 5632 } 5633 5634 return; 5635 #endif 5636 } 5637 5638 int 5639 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5640 { 5641 int rval = QLA_SUCCESS; 5642 struct qla_hw_data *ha = vha->hw; 5643 uint32_t drv_presence; 5644 5645 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5646 if (rval == QLA_SUCCESS) { 5647 drv_presence |= (1 << ha->portnum); 5648 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5649 drv_presence); 5650 } 5651 5652 return rval; 5653 } 5654 5655 int 5656 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5657 { 5658 int rval = QLA_SUCCESS; 5659 5660 qla83xx_idc_lock(vha, 0); 5661 rval = __qla83xx_set_drv_presence(vha); 5662 qla83xx_idc_unlock(vha, 0); 5663 5664 return rval; 5665 } 5666 5667 int 5668 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5669 { 5670 int rval = QLA_SUCCESS; 5671 struct qla_hw_data *ha = vha->hw; 5672 uint32_t drv_presence; 5673 5674 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5675 if (rval == QLA_SUCCESS) { 5676 drv_presence &= ~(1 << ha->portnum); 5677 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5678 drv_presence); 5679 } 5680 5681 return rval; 5682 } 5683 5684 int 5685 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5686 { 5687 int rval = QLA_SUCCESS; 5688 5689 qla83xx_idc_lock(vha, 0); 5690 rval = __qla83xx_clear_drv_presence(vha); 5691 qla83xx_idc_unlock(vha, 0); 5692 5693 return rval; 5694 } 5695 5696 static void 5697 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5698 { 5699 struct qla_hw_data *ha = vha->hw; 5700 uint32_t drv_ack, drv_presence; 5701 unsigned long ack_timeout; 5702 5703 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5704 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5705 while (1) { 5706 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5707 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5708 if ((drv_ack & drv_presence) == drv_presence) 5709 break; 5710 5711 if (time_after_eq(jiffies, ack_timeout)) { 5712 ql_log(ql_log_warn, vha, 0xb067, 5713 "RESET ACK TIMEOUT! drv_presence=0x%x " 5714 "drv_ack=0x%x\n", drv_presence, drv_ack); 5715 /* 5716 * The function(s) which did not ack in time are forced 5717 * to withdraw any further participation in the IDC 5718 * reset. 5719 */ 5720 if (drv_ack != drv_presence) 5721 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5722 drv_ack); 5723 break; 5724 } 5725 5726 qla83xx_idc_unlock(vha, 0); 5727 msleep(1000); 5728 qla83xx_idc_lock(vha, 0); 5729 } 5730 5731 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5732 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5733 } 5734 5735 static int 5736 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5737 { 5738 int rval = QLA_SUCCESS; 5739 uint32_t idc_control; 5740 5741 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5742 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5743 5744 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5745 __qla83xx_get_idc_control(vha, &idc_control); 5746 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5747 __qla83xx_set_idc_control(vha, 0); 5748 5749 qla83xx_idc_unlock(vha, 0); 5750 rval = qla83xx_restart_nic_firmware(vha); 5751 qla83xx_idc_lock(vha, 0); 5752 5753 if (rval != QLA_SUCCESS) { 5754 ql_log(ql_log_fatal, vha, 0xb06a, 5755 "Failed to restart NIC f/w.\n"); 5756 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5757 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5758 } else { 5759 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5760 "Success in restarting nic f/w.\n"); 5761 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5762 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5763 } 5764 5765 return rval; 5766 } 5767 5768 /* Assumes idc_lock always held on entry */ 5769 int 5770 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5771 { 5772 struct qla_hw_data *ha = base_vha->hw; 5773 int rval = QLA_SUCCESS; 5774 unsigned long dev_init_timeout; 5775 uint32_t dev_state; 5776 5777 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5778 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5779 5780 while (1) { 5781 5782 if (time_after_eq(jiffies, dev_init_timeout)) { 5783 ql_log(ql_log_warn, base_vha, 0xb06e, 5784 "Initialization TIMEOUT!\n"); 5785 /* Init timeout. Disable further NIC Core 5786 * communication. 5787 */ 5788 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5789 QLA8XXX_DEV_FAILED); 5790 ql_log(ql_log_info, base_vha, 0xb06f, 5791 "HW State: FAILED.\n"); 5792 } 5793 5794 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5795 switch (dev_state) { 5796 case QLA8XXX_DEV_READY: 5797 if (ha->flags.nic_core_reset_owner) 5798 qla83xx_idc_audit(base_vha, 5799 IDC_AUDIT_COMPLETION); 5800 ha->flags.nic_core_reset_owner = 0; 5801 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5802 "Reset_owner reset by 0x%x.\n", 5803 ha->portnum); 5804 goto exit; 5805 case QLA8XXX_DEV_COLD: 5806 if (ha->flags.nic_core_reset_owner) 5807 rval = qla83xx_device_bootstrap(base_vha); 5808 else { 5809 /* Wait for AEN to change device-state */ 5810 qla83xx_idc_unlock(base_vha, 0); 5811 msleep(1000); 5812 qla83xx_idc_lock(base_vha, 0); 5813 } 5814 break; 5815 case QLA8XXX_DEV_INITIALIZING: 5816 /* Wait for AEN to change device-state */ 5817 qla83xx_idc_unlock(base_vha, 0); 5818 msleep(1000); 5819 qla83xx_idc_lock(base_vha, 0); 5820 break; 5821 case QLA8XXX_DEV_NEED_RESET: 5822 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5823 qla83xx_need_reset_handler(base_vha); 5824 else { 5825 /* Wait for AEN to change device-state */ 5826 qla83xx_idc_unlock(base_vha, 0); 5827 msleep(1000); 5828 qla83xx_idc_lock(base_vha, 0); 5829 } 5830 /* reset timeout value after need reset handler */ 5831 dev_init_timeout = jiffies + 5832 (ha->fcoe_dev_init_timeout * HZ); 5833 break; 5834 case QLA8XXX_DEV_NEED_QUIESCENT: 5835 /* XXX: DEBUG for now */ 5836 qla83xx_idc_unlock(base_vha, 0); 5837 msleep(1000); 5838 qla83xx_idc_lock(base_vha, 0); 5839 break; 5840 case QLA8XXX_DEV_QUIESCENT: 5841 /* XXX: DEBUG for now */ 5842 if (ha->flags.quiesce_owner) 5843 goto exit; 5844 5845 qla83xx_idc_unlock(base_vha, 0); 5846 msleep(1000); 5847 qla83xx_idc_lock(base_vha, 0); 5848 dev_init_timeout = jiffies + 5849 (ha->fcoe_dev_init_timeout * HZ); 5850 break; 5851 case QLA8XXX_DEV_FAILED: 5852 if (ha->flags.nic_core_reset_owner) 5853 qla83xx_idc_audit(base_vha, 5854 IDC_AUDIT_COMPLETION); 5855 ha->flags.nic_core_reset_owner = 0; 5856 __qla83xx_clear_drv_presence(base_vha); 5857 qla83xx_idc_unlock(base_vha, 0); 5858 qla8xxx_dev_failed_handler(base_vha); 5859 rval = QLA_FUNCTION_FAILED; 5860 qla83xx_idc_lock(base_vha, 0); 5861 goto exit; 5862 case QLA8XXX_BAD_VALUE: 5863 qla83xx_idc_unlock(base_vha, 0); 5864 msleep(1000); 5865 qla83xx_idc_lock(base_vha, 0); 5866 break; 5867 default: 5868 ql_log(ql_log_warn, base_vha, 0xb071, 5869 "Unknown Device State: %x.\n", dev_state); 5870 qla83xx_idc_unlock(base_vha, 0); 5871 qla8xxx_dev_failed_handler(base_vha); 5872 rval = QLA_FUNCTION_FAILED; 5873 qla83xx_idc_lock(base_vha, 0); 5874 goto exit; 5875 } 5876 } 5877 5878 exit: 5879 return rval; 5880 } 5881 5882 void 5883 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5884 { 5885 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5886 board_disable); 5887 struct pci_dev *pdev = ha->pdev; 5888 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5889 5890 /* 5891 * if UNLOAD flag is already set, then continue unload, 5892 * where it was set first. 5893 */ 5894 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5895 return; 5896 5897 ql_log(ql_log_warn, base_vha, 0x015b, 5898 "Disabling adapter.\n"); 5899 5900 if (!atomic_read(&pdev->enable_cnt)) { 5901 ql_log(ql_log_info, base_vha, 0xfffc, 5902 "PCI device disabled, no action req for PCI error=%lx\n", 5903 base_vha->pci_flags); 5904 return; 5905 } 5906 5907 qla2x00_wait_for_sess_deletion(base_vha); 5908 5909 set_bit(UNLOADING, &base_vha->dpc_flags); 5910 5911 qla2x00_delete_all_vps(ha, base_vha); 5912 5913 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5914 5915 qla2x00_dfs_remove(base_vha); 5916 5917 qla84xx_put_chip(base_vha); 5918 5919 if (base_vha->timer_active) 5920 qla2x00_stop_timer(base_vha); 5921 5922 base_vha->flags.online = 0; 5923 5924 qla2x00_destroy_deferred_work(ha); 5925 5926 /* 5927 * Do not try to stop beacon blink as it will issue a mailbox 5928 * command. 5929 */ 5930 qla2x00_free_sysfs_attr(base_vha, false); 5931 5932 fc_remove_host(base_vha->host); 5933 5934 scsi_remove_host(base_vha->host); 5935 5936 base_vha->flags.init_done = 0; 5937 qla25xx_delete_queues(base_vha); 5938 qla2x00_free_fcports(base_vha); 5939 qla2x00_free_irqs(base_vha); 5940 qla2x00_mem_free(ha); 5941 qla82xx_md_free(base_vha); 5942 qla2x00_free_queues(ha); 5943 5944 qla2x00_unmap_iobases(ha); 5945 5946 pci_release_selected_regions(ha->pdev, ha->bars); 5947 pci_disable_pcie_error_reporting(pdev); 5948 pci_disable_device(pdev); 5949 5950 /* 5951 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5952 */ 5953 } 5954 5955 /************************************************************************** 5956 * qla2x00_do_dpc 5957 * This kernel thread is a task that is schedule by the interrupt handler 5958 * to perform the background processing for interrupts. 5959 * 5960 * Notes: 5961 * This task always run in the context of a kernel thread. It 5962 * is kick-off by the driver's detect code and starts up 5963 * up one per adapter. It immediately goes to sleep and waits for 5964 * some fibre event. When either the interrupt handler or 5965 * the timer routine detects a event it will one of the task 5966 * bits then wake us up. 5967 **************************************************************************/ 5968 static int 5969 qla2x00_do_dpc(void *data) 5970 { 5971 scsi_qla_host_t *base_vha; 5972 struct qla_hw_data *ha; 5973 uint32_t online; 5974 struct qla_qpair *qpair; 5975 5976 ha = (struct qla_hw_data *)data; 5977 base_vha = pci_get_drvdata(ha->pdev); 5978 5979 set_user_nice(current, MIN_NICE); 5980 5981 set_current_state(TASK_INTERRUPTIBLE); 5982 while (!kthread_should_stop()) { 5983 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5984 "DPC handler sleeping.\n"); 5985 5986 schedule(); 5987 5988 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5989 goto end_loop; 5990 5991 if (ha->flags.eeh_busy) { 5992 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5993 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5994 goto end_loop; 5995 } 5996 5997 ha->dpc_active = 1; 5998 5999 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6000 "DPC handler waking up, dpc_flags=0x%lx.\n", 6001 base_vha->dpc_flags); 6002 6003 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6004 break; 6005 6006 if (IS_P3P_TYPE(ha)) { 6007 if (IS_QLA8044(ha)) { 6008 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6009 &base_vha->dpc_flags)) { 6010 qla8044_idc_lock(ha); 6011 qla8044_wr_direct(base_vha, 6012 QLA8044_CRB_DEV_STATE_INDEX, 6013 QLA8XXX_DEV_FAILED); 6014 qla8044_idc_unlock(ha); 6015 ql_log(ql_log_info, base_vha, 0x4004, 6016 "HW State: FAILED.\n"); 6017 qla8044_device_state_handler(base_vha); 6018 continue; 6019 } 6020 6021 } else { 6022 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6023 &base_vha->dpc_flags)) { 6024 qla82xx_idc_lock(ha); 6025 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6026 QLA8XXX_DEV_FAILED); 6027 qla82xx_idc_unlock(ha); 6028 ql_log(ql_log_info, base_vha, 0x0151, 6029 "HW State: FAILED.\n"); 6030 qla82xx_device_state_handler(base_vha); 6031 continue; 6032 } 6033 } 6034 6035 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6036 &base_vha->dpc_flags)) { 6037 6038 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6039 "FCoE context reset scheduled.\n"); 6040 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6041 &base_vha->dpc_flags))) { 6042 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6043 /* FCoE-ctx reset failed. 6044 * Escalate to chip-reset 6045 */ 6046 set_bit(ISP_ABORT_NEEDED, 6047 &base_vha->dpc_flags); 6048 } 6049 clear_bit(ABORT_ISP_ACTIVE, 6050 &base_vha->dpc_flags); 6051 } 6052 6053 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6054 "FCoE context reset end.\n"); 6055 } 6056 } else if (IS_QLAFX00(ha)) { 6057 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6058 &base_vha->dpc_flags)) { 6059 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6060 "Firmware Reset Recovery\n"); 6061 if (qlafx00_reset_initialize(base_vha)) { 6062 /* Failed. Abort isp later. */ 6063 if (!test_bit(UNLOADING, 6064 &base_vha->dpc_flags)) { 6065 set_bit(ISP_UNRECOVERABLE, 6066 &base_vha->dpc_flags); 6067 ql_dbg(ql_dbg_dpc, base_vha, 6068 0x4021, 6069 "Reset Recovery Failed\n"); 6070 } 6071 } 6072 } 6073 6074 if (test_and_clear_bit(FX00_TARGET_SCAN, 6075 &base_vha->dpc_flags)) { 6076 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6077 "ISPFx00 Target Scan scheduled\n"); 6078 if (qlafx00_rescan_isp(base_vha)) { 6079 if (!test_bit(UNLOADING, 6080 &base_vha->dpc_flags)) 6081 set_bit(ISP_UNRECOVERABLE, 6082 &base_vha->dpc_flags); 6083 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6084 "ISPFx00 Target Scan Failed\n"); 6085 } 6086 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6087 "ISPFx00 Target Scan End\n"); 6088 } 6089 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6090 &base_vha->dpc_flags)) { 6091 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6092 "ISPFx00 Host Info resend scheduled\n"); 6093 qlafx00_fx_disc(base_vha, 6094 &base_vha->hw->mr.fcport, 6095 FXDISC_REG_HOST_INFO); 6096 } 6097 } 6098 6099 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6100 &base_vha->dpc_flags) && 6101 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6102 qla24xx_detect_sfp(base_vha); 6103 6104 if (ha->flags.detected_lr_sfp != 6105 ha->flags.using_lr_setting) 6106 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6107 } 6108 6109 if (test_and_clear_bit 6110 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6111 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6112 bool do_reset = true; 6113 6114 switch (base_vha->qlini_mode) { 6115 case QLA2XXX_INI_MODE_ENABLED: 6116 break; 6117 case QLA2XXX_INI_MODE_DISABLED: 6118 if (!qla_tgt_mode_enabled(base_vha) && 6119 !ha->flags.fw_started) 6120 do_reset = false; 6121 break; 6122 case QLA2XXX_INI_MODE_DUAL: 6123 if (!qla_dual_mode_enabled(base_vha) && 6124 !ha->flags.fw_started) 6125 do_reset = false; 6126 break; 6127 default: 6128 break; 6129 } 6130 6131 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6132 &base_vha->dpc_flags))) { 6133 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6134 "ISP abort scheduled.\n"); 6135 if (ha->isp_ops->abort_isp(base_vha)) { 6136 /* failed. retry later */ 6137 set_bit(ISP_ABORT_NEEDED, 6138 &base_vha->dpc_flags); 6139 } 6140 clear_bit(ABORT_ISP_ACTIVE, 6141 &base_vha->dpc_flags); 6142 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6143 "ISP abort end.\n"); 6144 } 6145 } 6146 6147 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6148 &base_vha->dpc_flags)) { 6149 qla2x00_update_fcports(base_vha); 6150 } 6151 6152 if (IS_QLAFX00(ha)) 6153 goto loop_resync_check; 6154 6155 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6156 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6157 "Quiescence mode scheduled.\n"); 6158 if (IS_P3P_TYPE(ha)) { 6159 if (IS_QLA82XX(ha)) 6160 qla82xx_device_state_handler(base_vha); 6161 if (IS_QLA8044(ha)) 6162 qla8044_device_state_handler(base_vha); 6163 clear_bit(ISP_QUIESCE_NEEDED, 6164 &base_vha->dpc_flags); 6165 if (!ha->flags.quiesce_owner) { 6166 qla2x00_perform_loop_resync(base_vha); 6167 if (IS_QLA82XX(ha)) { 6168 qla82xx_idc_lock(ha); 6169 qla82xx_clear_qsnt_ready( 6170 base_vha); 6171 qla82xx_idc_unlock(ha); 6172 } else if (IS_QLA8044(ha)) { 6173 qla8044_idc_lock(ha); 6174 qla8044_clear_qsnt_ready( 6175 base_vha); 6176 qla8044_idc_unlock(ha); 6177 } 6178 } 6179 } else { 6180 clear_bit(ISP_QUIESCE_NEEDED, 6181 &base_vha->dpc_flags); 6182 qla2x00_quiesce_io(base_vha); 6183 } 6184 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6185 "Quiescence mode end.\n"); 6186 } 6187 6188 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6189 &base_vha->dpc_flags) && 6190 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6191 6192 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6193 "Reset marker scheduled.\n"); 6194 qla2x00_rst_aen(base_vha); 6195 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6196 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6197 "Reset marker end.\n"); 6198 } 6199 6200 /* Retry each device up to login retry count */ 6201 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6202 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6203 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6204 6205 if (!base_vha->relogin_jif || 6206 time_after_eq(jiffies, base_vha->relogin_jif)) { 6207 base_vha->relogin_jif = jiffies + HZ; 6208 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6209 6210 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6211 "Relogin scheduled.\n"); 6212 qla24xx_post_relogin_work(base_vha); 6213 } 6214 } 6215 loop_resync_check: 6216 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6217 &base_vha->dpc_flags)) { 6218 6219 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6220 "Loop resync scheduled.\n"); 6221 6222 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6223 &base_vha->dpc_flags))) { 6224 6225 qla2x00_loop_resync(base_vha); 6226 6227 clear_bit(LOOP_RESYNC_ACTIVE, 6228 &base_vha->dpc_flags); 6229 } 6230 6231 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6232 "Loop resync end.\n"); 6233 } 6234 6235 if (IS_QLAFX00(ha)) 6236 goto intr_on_check; 6237 6238 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6239 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6240 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6241 qla2xxx_flash_npiv_conf(base_vha); 6242 } 6243 6244 intr_on_check: 6245 if (!ha->interrupts_on) 6246 ha->isp_ops->enable_intrs(ha); 6247 6248 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6249 &base_vha->dpc_flags)) { 6250 if (ha->beacon_blink_led == 1) 6251 ha->isp_ops->beacon_blink(base_vha); 6252 } 6253 6254 /* qpair online check */ 6255 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6256 &base_vha->dpc_flags)) { 6257 if (ha->flags.eeh_busy || 6258 ha->flags.pci_channel_io_perm_failure) 6259 online = 0; 6260 else 6261 online = 1; 6262 6263 mutex_lock(&ha->mq_lock); 6264 list_for_each_entry(qpair, &base_vha->qp_list, 6265 qp_list_elem) 6266 qpair->online = online; 6267 mutex_unlock(&ha->mq_lock); 6268 } 6269 6270 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6271 &base_vha->dpc_flags)) { 6272 ql_log(ql_log_info, base_vha, 0xffffff, 6273 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6274 ha->nvme_last_rptd_aen); 6275 if (qla27xx_set_zio_threshold(base_vha, 6276 ha->nvme_last_rptd_aen)) { 6277 ql_log(ql_log_info, base_vha, 0xffffff, 6278 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6279 ha->nvme_last_rptd_aen); 6280 } 6281 } 6282 6283 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6284 &base_vha->dpc_flags)) { 6285 ql_log(ql_log_info, base_vha, 0xffffff, 6286 "SET ZIO Activity exchange threshold to %d.\n", 6287 ha->last_zio_threshold); 6288 qla27xx_set_zio_threshold(base_vha, 6289 ha->last_zio_threshold); 6290 } 6291 6292 if (!IS_QLAFX00(ha)) 6293 qla2x00_do_dpc_all_vps(base_vha); 6294 6295 if (test_and_clear_bit(N2N_LINK_RESET, 6296 &base_vha->dpc_flags)) { 6297 qla2x00_lip_reset(base_vha); 6298 } 6299 6300 ha->dpc_active = 0; 6301 end_loop: 6302 set_current_state(TASK_INTERRUPTIBLE); 6303 } /* End of while(1) */ 6304 __set_current_state(TASK_RUNNING); 6305 6306 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6307 "DPC handler exiting.\n"); 6308 6309 /* 6310 * Make sure that nobody tries to wake us up again. 6311 */ 6312 ha->dpc_active = 0; 6313 6314 /* Cleanup any residual CTX SRBs. */ 6315 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6316 6317 return 0; 6318 } 6319 6320 void 6321 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6322 { 6323 struct qla_hw_data *ha = vha->hw; 6324 struct task_struct *t = ha->dpc_thread; 6325 6326 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6327 wake_up_process(t); 6328 } 6329 6330 /* 6331 * qla2x00_rst_aen 6332 * Processes asynchronous reset. 6333 * 6334 * Input: 6335 * ha = adapter block pointer. 6336 */ 6337 static void 6338 qla2x00_rst_aen(scsi_qla_host_t *vha) 6339 { 6340 if (vha->flags.online && !vha->flags.reset_active && 6341 !atomic_read(&vha->loop_down_timer) && 6342 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6343 do { 6344 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6345 6346 /* 6347 * Issue marker command only when we are going to start 6348 * the I/O. 6349 */ 6350 vha->marker_needed = 1; 6351 } while (!atomic_read(&vha->loop_down_timer) && 6352 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6353 } 6354 } 6355 6356 /************************************************************************** 6357 * qla2x00_timer 6358 * 6359 * Description: 6360 * One second timer 6361 * 6362 * Context: Interrupt 6363 ***************************************************************************/ 6364 void 6365 qla2x00_timer(struct timer_list *t) 6366 { 6367 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6368 unsigned long cpu_flags = 0; 6369 int start_dpc = 0; 6370 int index; 6371 srb_t *sp; 6372 uint16_t w; 6373 struct qla_hw_data *ha = vha->hw; 6374 struct req_que *req; 6375 6376 if (ha->flags.eeh_busy) { 6377 ql_dbg(ql_dbg_timer, vha, 0x6000, 6378 "EEH = %d, restarting timer.\n", 6379 ha->flags.eeh_busy); 6380 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6381 return; 6382 } 6383 6384 /* 6385 * Hardware read to raise pending EEH errors during mailbox waits. If 6386 * the read returns -1 then disable the board. 6387 */ 6388 if (!pci_channel_offline(ha->pdev)) { 6389 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6390 qla2x00_check_reg16_for_disconnect(vha, w); 6391 } 6392 6393 /* Make sure qla82xx_watchdog is run only for physical port */ 6394 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6395 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6396 start_dpc++; 6397 if (IS_QLA82XX(ha)) 6398 qla82xx_watchdog(vha); 6399 else if (IS_QLA8044(ha)) 6400 qla8044_watchdog(vha); 6401 } 6402 6403 if (!vha->vp_idx && IS_QLAFX00(ha)) 6404 qlafx00_timer_routine(vha); 6405 6406 /* Loop down handler. */ 6407 if (atomic_read(&vha->loop_down_timer) > 0 && 6408 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6409 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6410 && vha->flags.online) { 6411 6412 if (atomic_read(&vha->loop_down_timer) == 6413 vha->loop_down_abort_time) { 6414 6415 ql_log(ql_log_info, vha, 0x6008, 6416 "Loop down - aborting the queues before time expires.\n"); 6417 6418 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6419 atomic_set(&vha->loop_state, LOOP_DEAD); 6420 6421 /* 6422 * Schedule an ISP abort to return any FCP2-device 6423 * commands. 6424 */ 6425 /* NPIV - scan physical port only */ 6426 if (!vha->vp_idx) { 6427 spin_lock_irqsave(&ha->hardware_lock, 6428 cpu_flags); 6429 req = ha->req_q_map[0]; 6430 for (index = 1; 6431 index < req->num_outstanding_cmds; 6432 index++) { 6433 fc_port_t *sfcp; 6434 6435 sp = req->outstanding_cmds[index]; 6436 if (!sp) 6437 continue; 6438 if (sp->cmd_type != TYPE_SRB) 6439 continue; 6440 if (sp->type != SRB_SCSI_CMD) 6441 continue; 6442 sfcp = sp->fcport; 6443 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6444 continue; 6445 6446 if (IS_QLA82XX(ha)) 6447 set_bit(FCOE_CTX_RESET_NEEDED, 6448 &vha->dpc_flags); 6449 else 6450 set_bit(ISP_ABORT_NEEDED, 6451 &vha->dpc_flags); 6452 break; 6453 } 6454 spin_unlock_irqrestore(&ha->hardware_lock, 6455 cpu_flags); 6456 } 6457 start_dpc++; 6458 } 6459 6460 /* if the loop has been down for 4 minutes, reinit adapter */ 6461 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6462 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6463 ql_log(ql_log_warn, vha, 0x6009, 6464 "Loop down - aborting ISP.\n"); 6465 6466 if (IS_QLA82XX(ha)) 6467 set_bit(FCOE_CTX_RESET_NEEDED, 6468 &vha->dpc_flags); 6469 else 6470 set_bit(ISP_ABORT_NEEDED, 6471 &vha->dpc_flags); 6472 } 6473 } 6474 ql_dbg(ql_dbg_timer, vha, 0x600a, 6475 "Loop down - seconds remaining %d.\n", 6476 atomic_read(&vha->loop_down_timer)); 6477 } 6478 /* Check if beacon LED needs to be blinked for physical host only */ 6479 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6480 /* There is no beacon_blink function for ISP82xx */ 6481 if (!IS_P3P_TYPE(ha)) { 6482 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6483 start_dpc++; 6484 } 6485 } 6486 6487 /* Process any deferred work. */ 6488 if (!list_empty(&vha->work_list)) { 6489 unsigned long flags; 6490 bool q = false; 6491 6492 spin_lock_irqsave(&vha->work_lock, flags); 6493 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6494 q = true; 6495 spin_unlock_irqrestore(&vha->work_lock, flags); 6496 if (q) 6497 queue_work(vha->hw->wq, &vha->iocb_work); 6498 } 6499 6500 /* 6501 * FC-NVME 6502 * see if the active AEN count has changed from what was last reported. 6503 */ 6504 if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) != 6505 ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) { 6506 ql_log(ql_log_info, vha, 0x3002, 6507 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6508 ha->nvme_last_rptd_aen); 6509 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6510 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6511 start_dpc++; 6512 } 6513 6514 if (!vha->vp_idx && 6515 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 6516 (ha->zio_mode == QLA_ZIO_MODE_6) && 6517 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) { 6518 ql_log(ql_log_info, vha, 0x3002, 6519 "Sched: Set ZIO exchange threshold to %d.\n", 6520 ha->last_zio_threshold); 6521 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 6522 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6523 start_dpc++; 6524 } 6525 6526 /* Schedule the DPC routine if needed */ 6527 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6528 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6529 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6530 start_dpc || 6531 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6532 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6533 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6534 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6535 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6536 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6537 ql_dbg(ql_dbg_timer, vha, 0x600b, 6538 "isp_abort_needed=%d loop_resync_needed=%d " 6539 "fcport_update_needed=%d start_dpc=%d " 6540 "reset_marker_needed=%d", 6541 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6542 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6543 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6544 start_dpc, 6545 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6546 ql_dbg(ql_dbg_timer, vha, 0x600c, 6547 "beacon_blink_needed=%d isp_unrecoverable=%d " 6548 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6549 "relogin_needed=%d.\n", 6550 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6551 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6552 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6553 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6554 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6555 qla2xxx_wake_dpc(vha); 6556 } 6557 6558 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6559 } 6560 6561 /* Firmware interface routines. */ 6562 6563 #define FW_BLOBS 11 6564 #define FW_ISP21XX 0 6565 #define FW_ISP22XX 1 6566 #define FW_ISP2300 2 6567 #define FW_ISP2322 3 6568 #define FW_ISP24XX 4 6569 #define FW_ISP25XX 5 6570 #define FW_ISP81XX 6 6571 #define FW_ISP82XX 7 6572 #define FW_ISP2031 8 6573 #define FW_ISP8031 9 6574 #define FW_ISP27XX 10 6575 6576 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6577 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6578 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6579 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6580 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6581 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6582 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6583 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6584 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6585 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6586 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6587 6588 6589 static DEFINE_MUTEX(qla_fw_lock); 6590 6591 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6592 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6593 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6594 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6595 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6596 { .name = FW_FILE_ISP24XX, }, 6597 { .name = FW_FILE_ISP25XX, }, 6598 { .name = FW_FILE_ISP81XX, }, 6599 { .name = FW_FILE_ISP82XX, }, 6600 { .name = FW_FILE_ISP2031, }, 6601 { .name = FW_FILE_ISP8031, }, 6602 { .name = FW_FILE_ISP27XX, }, 6603 }; 6604 6605 struct fw_blob * 6606 qla2x00_request_firmware(scsi_qla_host_t *vha) 6607 { 6608 struct qla_hw_data *ha = vha->hw; 6609 struct fw_blob *blob; 6610 6611 if (IS_QLA2100(ha)) { 6612 blob = &qla_fw_blobs[FW_ISP21XX]; 6613 } else if (IS_QLA2200(ha)) { 6614 blob = &qla_fw_blobs[FW_ISP22XX]; 6615 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6616 blob = &qla_fw_blobs[FW_ISP2300]; 6617 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6618 blob = &qla_fw_blobs[FW_ISP2322]; 6619 } else if (IS_QLA24XX_TYPE(ha)) { 6620 blob = &qla_fw_blobs[FW_ISP24XX]; 6621 } else if (IS_QLA25XX(ha)) { 6622 blob = &qla_fw_blobs[FW_ISP25XX]; 6623 } else if (IS_QLA81XX(ha)) { 6624 blob = &qla_fw_blobs[FW_ISP81XX]; 6625 } else if (IS_QLA82XX(ha)) { 6626 blob = &qla_fw_blobs[FW_ISP82XX]; 6627 } else if (IS_QLA2031(ha)) { 6628 blob = &qla_fw_blobs[FW_ISP2031]; 6629 } else if (IS_QLA8031(ha)) { 6630 blob = &qla_fw_blobs[FW_ISP8031]; 6631 } else if (IS_QLA27XX(ha)) { 6632 blob = &qla_fw_blobs[FW_ISP27XX]; 6633 } else { 6634 return NULL; 6635 } 6636 6637 mutex_lock(&qla_fw_lock); 6638 if (blob->fw) 6639 goto out; 6640 6641 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6642 ql_log(ql_log_warn, vha, 0x0063, 6643 "Failed to load firmware image (%s).\n", blob->name); 6644 blob->fw = NULL; 6645 blob = NULL; 6646 goto out; 6647 } 6648 6649 out: 6650 mutex_unlock(&qla_fw_lock); 6651 return blob; 6652 } 6653 6654 static void 6655 qla2x00_release_firmware(void) 6656 { 6657 int idx; 6658 6659 mutex_lock(&qla_fw_lock); 6660 for (idx = 0; idx < FW_BLOBS; idx++) 6661 release_firmware(qla_fw_blobs[idx].fw); 6662 mutex_unlock(&qla_fw_lock); 6663 } 6664 6665 static pci_ers_result_t 6666 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6667 { 6668 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6669 struct qla_hw_data *ha = vha->hw; 6670 6671 ql_dbg(ql_dbg_aer, vha, 0x9000, 6672 "PCI error detected, state %x.\n", state); 6673 6674 if (!atomic_read(&pdev->enable_cnt)) { 6675 ql_log(ql_log_info, vha, 0xffff, 6676 "PCI device is disabled,state %x\n", state); 6677 return PCI_ERS_RESULT_NEED_RESET; 6678 } 6679 6680 switch (state) { 6681 case pci_channel_io_normal: 6682 ha->flags.eeh_busy = 0; 6683 if (ql2xmqsupport || ql2xnvmeenable) { 6684 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6685 qla2xxx_wake_dpc(vha); 6686 } 6687 return PCI_ERS_RESULT_CAN_RECOVER; 6688 case pci_channel_io_frozen: 6689 ha->flags.eeh_busy = 1; 6690 /* For ISP82XX complete any pending mailbox cmd */ 6691 if (IS_QLA82XX(ha)) { 6692 ha->flags.isp82xx_fw_hung = 1; 6693 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6694 qla82xx_clear_pending_mbx(vha); 6695 } 6696 qla2x00_free_irqs(vha); 6697 pci_disable_device(pdev); 6698 /* Return back all IOs */ 6699 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6700 if (ql2xmqsupport || ql2xnvmeenable) { 6701 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6702 qla2xxx_wake_dpc(vha); 6703 } 6704 return PCI_ERS_RESULT_NEED_RESET; 6705 case pci_channel_io_perm_failure: 6706 ha->flags.pci_channel_io_perm_failure = 1; 6707 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6708 if (ql2xmqsupport || ql2xnvmeenable) { 6709 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6710 qla2xxx_wake_dpc(vha); 6711 } 6712 return PCI_ERS_RESULT_DISCONNECT; 6713 } 6714 return PCI_ERS_RESULT_NEED_RESET; 6715 } 6716 6717 static pci_ers_result_t 6718 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6719 { 6720 int risc_paused = 0; 6721 uint32_t stat; 6722 unsigned long flags; 6723 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6724 struct qla_hw_data *ha = base_vha->hw; 6725 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6726 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6727 6728 if (IS_QLA82XX(ha)) 6729 return PCI_ERS_RESULT_RECOVERED; 6730 6731 spin_lock_irqsave(&ha->hardware_lock, flags); 6732 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6733 stat = RD_REG_DWORD(®->hccr); 6734 if (stat & HCCR_RISC_PAUSE) 6735 risc_paused = 1; 6736 } else if (IS_QLA23XX(ha)) { 6737 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6738 if (stat & HSR_RISC_PAUSED) 6739 risc_paused = 1; 6740 } else if (IS_FWI2_CAPABLE(ha)) { 6741 stat = RD_REG_DWORD(®24->host_status); 6742 if (stat & HSRX_RISC_PAUSED) 6743 risc_paused = 1; 6744 } 6745 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6746 6747 if (risc_paused) { 6748 ql_log(ql_log_info, base_vha, 0x9003, 6749 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6750 ha->isp_ops->fw_dump(base_vha, 0); 6751 6752 return PCI_ERS_RESULT_NEED_RESET; 6753 } else 6754 return PCI_ERS_RESULT_RECOVERED; 6755 } 6756 6757 static uint32_t 6758 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6759 { 6760 uint32_t rval = QLA_FUNCTION_FAILED; 6761 uint32_t drv_active = 0; 6762 struct qla_hw_data *ha = base_vha->hw; 6763 int fn; 6764 struct pci_dev *other_pdev = NULL; 6765 6766 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6767 "Entered %s.\n", __func__); 6768 6769 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6770 6771 if (base_vha->flags.online) { 6772 /* Abort all outstanding commands, 6773 * so as to be requeued later */ 6774 qla2x00_abort_isp_cleanup(base_vha); 6775 } 6776 6777 6778 fn = PCI_FUNC(ha->pdev->devfn); 6779 while (fn > 0) { 6780 fn--; 6781 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6782 "Finding pci device at function = 0x%x.\n", fn); 6783 other_pdev = 6784 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6785 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6786 fn)); 6787 6788 if (!other_pdev) 6789 continue; 6790 if (atomic_read(&other_pdev->enable_cnt)) { 6791 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6792 "Found PCI func available and enable at 0x%x.\n", 6793 fn); 6794 pci_dev_put(other_pdev); 6795 break; 6796 } 6797 pci_dev_put(other_pdev); 6798 } 6799 6800 if (!fn) { 6801 /* Reset owner */ 6802 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6803 "This devfn is reset owner = 0x%x.\n", 6804 ha->pdev->devfn); 6805 qla82xx_idc_lock(ha); 6806 6807 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6808 QLA8XXX_DEV_INITIALIZING); 6809 6810 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6811 QLA82XX_IDC_VERSION); 6812 6813 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6814 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6815 "drv_active = 0x%x.\n", drv_active); 6816 6817 qla82xx_idc_unlock(ha); 6818 /* Reset if device is not already reset 6819 * drv_active would be 0 if a reset has already been done 6820 */ 6821 if (drv_active) 6822 rval = qla82xx_start_firmware(base_vha); 6823 else 6824 rval = QLA_SUCCESS; 6825 qla82xx_idc_lock(ha); 6826 6827 if (rval != QLA_SUCCESS) { 6828 ql_log(ql_log_info, base_vha, 0x900b, 6829 "HW State: FAILED.\n"); 6830 qla82xx_clear_drv_active(ha); 6831 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6832 QLA8XXX_DEV_FAILED); 6833 } else { 6834 ql_log(ql_log_info, base_vha, 0x900c, 6835 "HW State: READY.\n"); 6836 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6837 QLA8XXX_DEV_READY); 6838 qla82xx_idc_unlock(ha); 6839 ha->flags.isp82xx_fw_hung = 0; 6840 rval = qla82xx_restart_isp(base_vha); 6841 qla82xx_idc_lock(ha); 6842 /* Clear driver state register */ 6843 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6844 qla82xx_set_drv_active(base_vha); 6845 } 6846 qla82xx_idc_unlock(ha); 6847 } else { 6848 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6849 "This devfn is not reset owner = 0x%x.\n", 6850 ha->pdev->devfn); 6851 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6852 QLA8XXX_DEV_READY)) { 6853 ha->flags.isp82xx_fw_hung = 0; 6854 rval = qla82xx_restart_isp(base_vha); 6855 qla82xx_idc_lock(ha); 6856 qla82xx_set_drv_active(base_vha); 6857 qla82xx_idc_unlock(ha); 6858 } 6859 } 6860 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6861 6862 return rval; 6863 } 6864 6865 static pci_ers_result_t 6866 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6867 { 6868 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6869 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6870 struct qla_hw_data *ha = base_vha->hw; 6871 struct rsp_que *rsp; 6872 int rc, retries = 10; 6873 6874 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6875 "Slot Reset.\n"); 6876 6877 /* Workaround: qla2xxx driver which access hardware earlier 6878 * needs error state to be pci_channel_io_online. 6879 * Otherwise mailbox command timesout. 6880 */ 6881 pdev->error_state = pci_channel_io_normal; 6882 6883 pci_restore_state(pdev); 6884 6885 /* pci_restore_state() clears the saved_state flag of the device 6886 * save restored state which resets saved_state flag 6887 */ 6888 pci_save_state(pdev); 6889 6890 if (ha->mem_only) 6891 rc = pci_enable_device_mem(pdev); 6892 else 6893 rc = pci_enable_device(pdev); 6894 6895 if (rc) { 6896 ql_log(ql_log_warn, base_vha, 0x9005, 6897 "Can't re-enable PCI device after reset.\n"); 6898 goto exit_slot_reset; 6899 } 6900 6901 rsp = ha->rsp_q_map[0]; 6902 if (qla2x00_request_irqs(ha, rsp)) 6903 goto exit_slot_reset; 6904 6905 if (ha->isp_ops->pci_config(base_vha)) 6906 goto exit_slot_reset; 6907 6908 if (IS_QLA82XX(ha)) { 6909 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6910 ret = PCI_ERS_RESULT_RECOVERED; 6911 goto exit_slot_reset; 6912 } else 6913 goto exit_slot_reset; 6914 } 6915 6916 while (ha->flags.mbox_busy && retries--) 6917 msleep(1000); 6918 6919 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6920 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6921 ret = PCI_ERS_RESULT_RECOVERED; 6922 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6923 6924 6925 exit_slot_reset: 6926 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6927 "slot_reset return %x.\n", ret); 6928 6929 return ret; 6930 } 6931 6932 static void 6933 qla2xxx_pci_resume(struct pci_dev *pdev) 6934 { 6935 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6936 struct qla_hw_data *ha = base_vha->hw; 6937 int ret; 6938 6939 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6940 "pci_resume.\n"); 6941 6942 ret = qla2x00_wait_for_hba_online(base_vha); 6943 if (ret != QLA_SUCCESS) { 6944 ql_log(ql_log_fatal, base_vha, 0x9002, 6945 "The device failed to resume I/O from slot/link_reset.\n"); 6946 } 6947 6948 ha->flags.eeh_busy = 0; 6949 } 6950 6951 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6952 { 6953 int rc; 6954 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6955 6956 if (USER_CTRL_IRQ(vha->hw)) 6957 rc = blk_mq_map_queues(&shost->tag_set); 6958 else 6959 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); 6960 return rc; 6961 } 6962 6963 static const struct pci_error_handlers qla2xxx_err_handler = { 6964 .error_detected = qla2xxx_pci_error_detected, 6965 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6966 .slot_reset = qla2xxx_pci_slot_reset, 6967 .resume = qla2xxx_pci_resume, 6968 }; 6969 6970 static struct pci_device_id qla2xxx_pci_tbl[] = { 6971 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6972 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6973 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6974 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6975 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6976 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6985 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6986 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6987 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6988 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6989 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6990 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6991 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6992 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6993 { 0 }, 6994 }; 6995 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6996 6997 static struct pci_driver qla2xxx_pci_driver = { 6998 .name = QLA2XXX_DRIVER_NAME, 6999 .driver = { 7000 .owner = THIS_MODULE, 7001 }, 7002 .id_table = qla2xxx_pci_tbl, 7003 .probe = qla2x00_probe_one, 7004 .remove = qla2x00_remove_one, 7005 .shutdown = qla2x00_shutdown, 7006 .err_handler = &qla2xxx_err_handler, 7007 }; 7008 7009 static const struct file_operations apidev_fops = { 7010 .owner = THIS_MODULE, 7011 .llseek = noop_llseek, 7012 }; 7013 7014 /** 7015 * qla2x00_module_init - Module initialization. 7016 **/ 7017 static int __init 7018 qla2x00_module_init(void) 7019 { 7020 int ret = 0; 7021 7022 /* Allocate cache for SRBs. */ 7023 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7024 SLAB_HWCACHE_ALIGN, NULL); 7025 if (srb_cachep == NULL) { 7026 ql_log(ql_log_fatal, NULL, 0x0001, 7027 "Unable to allocate SRB cache...Failing load!.\n"); 7028 return -ENOMEM; 7029 } 7030 7031 /* Initialize target kmem_cache and mem_pools */ 7032 ret = qlt_init(); 7033 if (ret < 0) { 7034 kmem_cache_destroy(srb_cachep); 7035 return ret; 7036 } else if (ret > 0) { 7037 /* 7038 * If initiator mode is explictly disabled by qlt_init(), 7039 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7040 * performing scsi_scan_target() during LOOP UP event. 7041 */ 7042 qla2xxx_transport_functions.disable_target_scan = 1; 7043 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7044 } 7045 7046 /* Derive version string. */ 7047 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7048 if (ql2xextended_error_logging) 7049 strcat(qla2x00_version_str, "-debug"); 7050 if (ql2xextended_error_logging == 1) 7051 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7052 7053 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7054 qla_insert_tgt_attrs(); 7055 7056 qla2xxx_transport_template = 7057 fc_attach_transport(&qla2xxx_transport_functions); 7058 if (!qla2xxx_transport_template) { 7059 kmem_cache_destroy(srb_cachep); 7060 ql_log(ql_log_fatal, NULL, 0x0002, 7061 "fc_attach_transport failed...Failing load!.\n"); 7062 qlt_exit(); 7063 return -ENODEV; 7064 } 7065 7066 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7067 if (apidev_major < 0) { 7068 ql_log(ql_log_fatal, NULL, 0x0003, 7069 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7070 } 7071 7072 qla2xxx_transport_vport_template = 7073 fc_attach_transport(&qla2xxx_transport_vport_functions); 7074 if (!qla2xxx_transport_vport_template) { 7075 kmem_cache_destroy(srb_cachep); 7076 qlt_exit(); 7077 fc_release_transport(qla2xxx_transport_template); 7078 ql_log(ql_log_fatal, NULL, 0x0004, 7079 "fc_attach_transport vport failed...Failing load!.\n"); 7080 return -ENODEV; 7081 } 7082 ql_log(ql_log_info, NULL, 0x0005, 7083 "QLogic Fibre Channel HBA Driver: %s.\n", 7084 qla2x00_version_str); 7085 ret = pci_register_driver(&qla2xxx_pci_driver); 7086 if (ret) { 7087 kmem_cache_destroy(srb_cachep); 7088 qlt_exit(); 7089 fc_release_transport(qla2xxx_transport_template); 7090 fc_release_transport(qla2xxx_transport_vport_template); 7091 ql_log(ql_log_fatal, NULL, 0x0006, 7092 "pci_register_driver failed...ret=%d Failing load!.\n", 7093 ret); 7094 } 7095 return ret; 7096 } 7097 7098 /** 7099 * qla2x00_module_exit - Module cleanup. 7100 **/ 7101 static void __exit 7102 qla2x00_module_exit(void) 7103 { 7104 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7105 pci_unregister_driver(&qla2xxx_pci_driver); 7106 qla2x00_release_firmware(); 7107 kmem_cache_destroy(srb_cachep); 7108 qlt_exit(); 7109 if (ctx_cachep) 7110 kmem_cache_destroy(ctx_cachep); 7111 fc_release_transport(qla2xxx_transport_template); 7112 fc_release_transport(qla2xxx_transport_vport_template); 7113 } 7114 7115 module_init(qla2x00_module_init); 7116 module_exit(qla2x00_module_exit); 7117 7118 MODULE_AUTHOR("QLogic Corporation"); 7119 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7120 MODULE_LICENSE("GPL"); 7121 MODULE_VERSION(QLA2XXX_VERSION); 7122 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7123 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7124 MODULE_FIRMWARE(FW_FILE_ISP2300); 7125 MODULE_FIRMWARE(FW_FILE_ISP2322); 7126 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7127 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7128