1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 int ql2xfc2target = 1; 364 module_param(ql2xfc2target, int, 0444); 365 MODULE_PARM_DESC(qla2xfc2target, 366 "Enables FC2 Target support. " 367 "0 - FC2 Target support is disabled. " 368 "1 - FC2 Target support is enabled (default)."); 369 370 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 371 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 372 373 /* TODO Convert to inlines 374 * 375 * Timer routines 376 */ 377 378 __inline__ void 379 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 timer_setup(&vha->timer, qla2x00_timer, 0); 382 vha->timer.expires = jiffies + interval * HZ; 383 add_timer(&vha->timer); 384 vha->timer_active = 1; 385 } 386 387 static inline void 388 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 389 { 390 /* Currently used for 82XX only. */ 391 if (vha->device_flags & DFLG_DEV_FAILED) { 392 ql_dbg(ql_dbg_timer, vha, 0x600d, 393 "Device in a failed state, returning.\n"); 394 return; 395 } 396 397 mod_timer(&vha->timer, jiffies + interval * HZ); 398 } 399 400 static __inline__ void 401 qla2x00_stop_timer(scsi_qla_host_t *vha) 402 { 403 del_timer_sync(&vha->timer); 404 vha->timer_active = 0; 405 } 406 407 static int qla2x00_do_dpc(void *data); 408 409 static void qla2x00_rst_aen(scsi_qla_host_t *); 410 411 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 412 struct req_que **, struct rsp_que **); 413 static void qla2x00_free_fw_dump(struct qla_hw_data *); 414 static void qla2x00_mem_free(struct qla_hw_data *); 415 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 416 struct qla_qpair *qpair); 417 418 /* -------------------------------------------------------------------------- */ 419 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 420 struct rsp_que *rsp) 421 { 422 struct qla_hw_data *ha = vha->hw; 423 424 rsp->qpair = ha->base_qpair; 425 rsp->req = req; 426 ha->base_qpair->hw = ha; 427 ha->base_qpair->req = req; 428 ha->base_qpair->rsp = rsp; 429 ha->base_qpair->vha = vha; 430 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 431 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 432 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 433 ha->base_qpair->srb_mempool = ha->srb_mempool; 434 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 435 ha->base_qpair->enable_class_2 = ql2xenableclass2; 436 /* init qpair to this cpu. Will adjust at run time. */ 437 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 438 ha->base_qpair->pdev = ha->pdev; 439 440 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 441 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 442 } 443 444 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 445 struct rsp_que *rsp) 446 { 447 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 448 449 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 450 GFP_KERNEL); 451 if (!ha->req_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003b, 453 "Unable to allocate memory for request queue ptrs.\n"); 454 goto fail_req_map; 455 } 456 457 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 458 GFP_KERNEL); 459 if (!ha->rsp_q_map) { 460 ql_log(ql_log_fatal, vha, 0x003c, 461 "Unable to allocate memory for response queue ptrs.\n"); 462 goto fail_rsp_map; 463 } 464 465 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 466 if (ha->base_qpair == NULL) { 467 ql_log(ql_log_warn, vha, 0x00e0, 468 "Failed to allocate base queue pair memory.\n"); 469 goto fail_base_qpair; 470 } 471 472 qla_init_base_qpair(vha, req, rsp); 473 474 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 475 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 476 GFP_KERNEL); 477 if (!ha->queue_pair_map) { 478 ql_log(ql_log_fatal, vha, 0x0180, 479 "Unable to allocate memory for queue pair ptrs.\n"); 480 goto fail_qpair_map; 481 } 482 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 483 kfree(ha->queue_pair_map); 484 ha->queue_pair_map = NULL; 485 goto fail_qpair_map; 486 } 487 } 488 489 /* 490 * Make sure we record at least the request and response queue zero in 491 * case we need to free them if part of the probe fails. 492 */ 493 ha->rsp_q_map[0] = rsp; 494 ha->req_q_map[0] = req; 495 set_bit(0, ha->rsp_qid_map); 496 set_bit(0, ha->req_qid_map); 497 return 0; 498 499 fail_qpair_map: 500 kfree(ha->base_qpair); 501 ha->base_qpair = NULL; 502 fail_base_qpair: 503 kfree(ha->rsp_q_map); 504 ha->rsp_q_map = NULL; 505 fail_rsp_map: 506 kfree(ha->req_q_map); 507 ha->req_q_map = NULL; 508 fail_req_map: 509 return -ENOMEM; 510 } 511 512 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 513 { 514 if (IS_QLAFX00(ha)) { 515 if (req && req->ring_fx00) 516 dma_free_coherent(&ha->pdev->dev, 517 (req->length_fx00 + 1) * sizeof(request_t), 518 req->ring_fx00, req->dma_fx00); 519 } else if (req && req->ring) 520 dma_free_coherent(&ha->pdev->dev, 521 (req->length + 1) * sizeof(request_t), 522 req->ring, req->dma); 523 524 if (req) 525 kfree(req->outstanding_cmds); 526 527 kfree(req); 528 } 529 530 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 531 { 532 if (IS_QLAFX00(ha)) { 533 if (rsp && rsp->ring_fx00) 534 dma_free_coherent(&ha->pdev->dev, 535 (rsp->length_fx00 + 1) * sizeof(request_t), 536 rsp->ring_fx00, rsp->dma_fx00); 537 } else if (rsp && rsp->ring) { 538 dma_free_coherent(&ha->pdev->dev, 539 (rsp->length + 1) * sizeof(response_t), 540 rsp->ring, rsp->dma); 541 } 542 kfree(rsp); 543 } 544 545 static void qla2x00_free_queues(struct qla_hw_data *ha) 546 { 547 struct req_que *req; 548 struct rsp_que *rsp; 549 int cnt; 550 unsigned long flags; 551 552 if (ha->queue_pair_map) { 553 kfree(ha->queue_pair_map); 554 ha->queue_pair_map = NULL; 555 } 556 if (ha->base_qpair) { 557 kfree(ha->base_qpair); 558 ha->base_qpair = NULL; 559 } 560 561 qla_mapq_free_qp_cpu_map(ha); 562 spin_lock_irqsave(&ha->hardware_lock, flags); 563 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 564 if (!test_bit(cnt, ha->req_qid_map)) 565 continue; 566 567 req = ha->req_q_map[cnt]; 568 clear_bit(cnt, ha->req_qid_map); 569 ha->req_q_map[cnt] = NULL; 570 571 spin_unlock_irqrestore(&ha->hardware_lock, flags); 572 qla2x00_free_req_que(ha, req); 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 } 575 spin_unlock_irqrestore(&ha->hardware_lock, flags); 576 577 kfree(ha->req_q_map); 578 ha->req_q_map = NULL; 579 580 581 spin_lock_irqsave(&ha->hardware_lock, flags); 582 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 583 if (!test_bit(cnt, ha->rsp_qid_map)) 584 continue; 585 586 rsp = ha->rsp_q_map[cnt]; 587 clear_bit(cnt, ha->rsp_qid_map); 588 ha->rsp_q_map[cnt] = NULL; 589 spin_unlock_irqrestore(&ha->hardware_lock, flags); 590 qla2x00_free_rsp_que(ha, rsp); 591 spin_lock_irqsave(&ha->hardware_lock, flags); 592 } 593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 594 595 kfree(ha->rsp_q_map); 596 ha->rsp_q_map = NULL; 597 } 598 599 static char * 600 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 static const char *const pci_bus_modes[] = { 604 "33", "66", "100", "133", 605 }; 606 uint16_t pci_bus; 607 608 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 609 if (pci_bus) { 610 snprintf(str, str_len, "PCI-X (%s MHz)", 611 pci_bus_modes[pci_bus]); 612 } else { 613 pci_bus = (ha->pci_attr & BIT_8) >> 8; 614 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 615 } 616 617 return str; 618 } 619 620 static char * 621 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 622 { 623 static const char *const pci_bus_modes[] = { 624 "33", "66", "100", "133", 625 }; 626 struct qla_hw_data *ha = vha->hw; 627 uint32_t pci_bus; 628 629 if (pci_is_pcie(ha->pdev)) { 630 uint32_t lstat, lspeed, lwidth; 631 const char *speed_str; 632 633 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 634 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 635 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 636 637 switch (lspeed) { 638 case 1: 639 speed_str = "2.5GT/s"; 640 break; 641 case 2: 642 speed_str = "5.0GT/s"; 643 break; 644 case 3: 645 speed_str = "8.0GT/s"; 646 break; 647 case 4: 648 speed_str = "16.0GT/s"; 649 break; 650 default: 651 speed_str = "<unknown>"; 652 break; 653 } 654 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 655 656 return str; 657 } 658 659 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 660 if (pci_bus == 0 || pci_bus == 8) 661 snprintf(str, str_len, "PCI (%s MHz)", 662 pci_bus_modes[pci_bus >> 3]); 663 else 664 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 665 pci_bus & 4 ? 2 : 1, 666 pci_bus_modes[pci_bus & 3]); 667 668 return str; 669 } 670 671 static char * 672 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 673 { 674 char un_str[10]; 675 struct qla_hw_data *ha = vha->hw; 676 677 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 678 ha->fw_minor_version, ha->fw_subminor_version); 679 680 if (ha->fw_attributes & BIT_9) { 681 strcat(str, "FLX"); 682 return (str); 683 } 684 685 switch (ha->fw_attributes & 0xFF) { 686 case 0x7: 687 strcat(str, "EF"); 688 break; 689 case 0x17: 690 strcat(str, "TP"); 691 break; 692 case 0x37: 693 strcat(str, "IP"); 694 break; 695 case 0x77: 696 strcat(str, "VI"); 697 break; 698 default: 699 sprintf(un_str, "(%x)", ha->fw_attributes); 700 strcat(str, un_str); 701 break; 702 } 703 if (ha->fw_attributes & 0x100) 704 strcat(str, "X"); 705 706 return (str); 707 } 708 709 static char * 710 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 711 { 712 struct qla_hw_data *ha = vha->hw; 713 714 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 715 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 716 return str; 717 } 718 719 void qla2x00_sp_free_dma(srb_t *sp) 720 { 721 struct qla_hw_data *ha = sp->vha->hw; 722 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 723 724 if (sp->flags & SRB_DMA_VALID) { 725 scsi_dma_unmap(cmd); 726 sp->flags &= ~SRB_DMA_VALID; 727 } 728 729 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 730 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 731 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 732 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 736 /* List assured to be having elements */ 737 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 738 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 742 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 743 744 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 745 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 746 } 747 748 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 749 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 750 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 752 ctx1->fcp_cmnd_dma); 753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 756 } 757 758 if (sp->flags & SRB_GOT_BUF) 759 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 760 } 761 762 void qla2x00_sp_compl(srb_t *sp, int res) 763 { 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct completion *comp = sp->comp; 766 767 /* kref: INIT */ 768 kref_put(&sp->cmd_kref, qla2x00_sp_release); 769 cmd->result = res; 770 sp->type = 0; 771 scsi_done(cmd); 772 if (comp) 773 complete(comp); 774 } 775 776 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 777 { 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 779 struct qla_hw_data *ha = sp->fcport->vha->hw; 780 781 if (sp->flags & SRB_DMA_VALID) { 782 scsi_dma_unmap(cmd); 783 sp->flags &= ~SRB_DMA_VALID; 784 } 785 786 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 787 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 788 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 789 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 790 } 791 792 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 793 /* List assured to be having elements */ 794 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 795 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 796 } 797 798 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 799 struct crc_context *difctx = sp->u.scmd.crc_ctx; 800 struct dsd_dma *dif_dsd, *nxt_dsd; 801 802 list_for_each_entry_safe(dif_dsd, nxt_dsd, 803 &difctx->ldif_dma_hndl_list, list) { 804 list_del(&dif_dsd->list); 805 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 806 dif_dsd->dsd_list_dma); 807 kfree(dif_dsd); 808 difctx->no_dif_bundl--; 809 } 810 811 list_for_each_entry_safe(dif_dsd, nxt_dsd, 812 &difctx->ldif_dsd_list, list) { 813 list_del(&dif_dsd->list); 814 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 815 dif_dsd->dsd_list_dma); 816 kfree(dif_dsd); 817 difctx->no_ldif_dsd--; 818 } 819 820 if (difctx->no_ldif_dsd) { 821 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 822 "%s: difctx->no_ldif_dsd=%x\n", 823 __func__, difctx->no_ldif_dsd); 824 } 825 826 if (difctx->no_dif_bundl) { 827 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 828 "%s: difctx->no_dif_bundl=%x\n", 829 __func__, difctx->no_dif_bundl); 830 } 831 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 832 } 833 834 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 835 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 836 837 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 838 ctx1->fcp_cmnd_dma); 839 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 840 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 841 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 842 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 843 } 844 845 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 846 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 847 848 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 849 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 850 } 851 852 if (sp->flags & SRB_GOT_BUF) 853 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 854 } 855 856 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 857 { 858 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 859 struct completion *comp = sp->comp; 860 861 /* ref: INIT */ 862 kref_put(&sp->cmd_kref, qla2x00_sp_release); 863 cmd->result = res; 864 sp->type = 0; 865 scsi_done(cmd); 866 if (comp) 867 complete(comp); 868 } 869 870 static int 871 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 872 { 873 scsi_qla_host_t *vha = shost_priv(host); 874 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 875 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 876 struct qla_hw_data *ha = vha->hw; 877 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 878 srb_t *sp; 879 int rval; 880 881 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 882 WARN_ON_ONCE(!rport)) { 883 cmd->result = DID_NO_CONNECT << 16; 884 goto qc24_fail_command; 885 } 886 887 if (ha->mqenable) { 888 uint32_t tag; 889 uint16_t hwq; 890 struct qla_qpair *qpair = NULL; 891 892 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 893 hwq = blk_mq_unique_tag_to_hwq(tag); 894 qpair = ha->queue_pair_map[hwq]; 895 896 if (qpair) 897 return qla2xxx_mqueuecommand(host, cmd, qpair); 898 } 899 900 if (ha->flags.eeh_busy) { 901 if (ha->flags.pci_channel_io_perm_failure) { 902 ql_dbg(ql_dbg_aer, vha, 0x9010, 903 "PCI Channel IO permanent failure, exiting " 904 "cmd=%p.\n", cmd); 905 cmd->result = DID_NO_CONNECT << 16; 906 } else { 907 ql_dbg(ql_dbg_aer, vha, 0x9011, 908 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 909 cmd->result = DID_REQUEUE << 16; 910 } 911 goto qc24_fail_command; 912 } 913 914 rval = fc_remote_port_chkready(rport); 915 if (rval) { 916 cmd->result = rval; 917 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 918 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 919 cmd, rval); 920 goto qc24_fail_command; 921 } 922 923 if (!vha->flags.difdix_supported && 924 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 925 ql_dbg(ql_dbg_io, vha, 0x3004, 926 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 927 cmd); 928 cmd->result = DID_NO_CONNECT << 16; 929 goto qc24_fail_command; 930 } 931 932 if (!fcport || fcport->deleted) { 933 cmd->result = DID_IMM_RETRY << 16; 934 goto qc24_fail_command; 935 } 936 937 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 938 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 939 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 940 ql_dbg(ql_dbg_io, vha, 0x3005, 941 "Returning DNC, fcport_state=%d loop_state=%d.\n", 942 atomic_read(&fcport->state), 943 atomic_read(&base_vha->loop_state)); 944 cmd->result = DID_NO_CONNECT << 16; 945 goto qc24_fail_command; 946 } 947 goto qc24_target_busy; 948 } 949 950 /* 951 * Return target busy if we've received a non-zero retry_delay_timer 952 * in a FCP_RSP. 953 */ 954 if (fcport->retry_delay_timestamp == 0) { 955 /* retry delay not set */ 956 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 957 fcport->retry_delay_timestamp = 0; 958 else 959 goto qc24_target_busy; 960 961 sp = scsi_cmd_priv(cmd); 962 /* ref: INIT */ 963 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 964 965 sp->u.scmd.cmd = cmd; 966 sp->type = SRB_SCSI_CMD; 967 sp->free = qla2x00_sp_free_dma; 968 sp->done = qla2x00_sp_compl; 969 970 rval = ha->isp_ops->start_scsi(sp); 971 if (rval != QLA_SUCCESS) { 972 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 973 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 974 goto qc24_host_busy_free_sp; 975 } 976 977 return 0; 978 979 qc24_host_busy_free_sp: 980 /* ref: INIT */ 981 kref_put(&sp->cmd_kref, qla2x00_sp_release); 982 983 qc24_target_busy: 984 return SCSI_MLQUEUE_TARGET_BUSY; 985 986 qc24_fail_command: 987 scsi_done(cmd); 988 989 return 0; 990 } 991 992 /* For MQ supported I/O */ 993 int 994 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 995 struct qla_qpair *qpair) 996 { 997 scsi_qla_host_t *vha = shost_priv(host); 998 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 999 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1000 struct qla_hw_data *ha = vha->hw; 1001 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1002 srb_t *sp; 1003 int rval; 1004 1005 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1006 if (rval) { 1007 cmd->result = rval; 1008 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1009 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1010 cmd, rval); 1011 goto qc24_fail_command; 1012 } 1013 1014 if (!qpair->online) { 1015 ql_dbg(ql_dbg_io, vha, 0x3077, 1016 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1017 cmd->result = DID_NO_CONNECT << 16; 1018 goto qc24_fail_command; 1019 } 1020 1021 if (!fcport || fcport->deleted) { 1022 cmd->result = DID_IMM_RETRY << 16; 1023 goto qc24_fail_command; 1024 } 1025 1026 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1027 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1028 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1029 ql_dbg(ql_dbg_io, vha, 0x3077, 1030 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1031 atomic_read(&fcport->state), 1032 atomic_read(&base_vha->loop_state)); 1033 cmd->result = DID_NO_CONNECT << 16; 1034 goto qc24_fail_command; 1035 } 1036 goto qc24_target_busy; 1037 } 1038 1039 /* 1040 * Return target busy if we've received a non-zero retry_delay_timer 1041 * in a FCP_RSP. 1042 */ 1043 if (fcport->retry_delay_timestamp == 0) { 1044 /* retry delay not set */ 1045 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1046 fcport->retry_delay_timestamp = 0; 1047 else 1048 goto qc24_target_busy; 1049 1050 sp = scsi_cmd_priv(cmd); 1051 /* ref: INIT */ 1052 qla2xxx_init_sp(sp, vha, qpair, fcport); 1053 1054 sp->u.scmd.cmd = cmd; 1055 sp->type = SRB_SCSI_CMD; 1056 sp->free = qla2xxx_qpair_sp_free_dma; 1057 sp->done = qla2xxx_qpair_sp_compl; 1058 1059 rval = ha->isp_ops->start_scsi_mq(sp); 1060 if (rval != QLA_SUCCESS) { 1061 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1062 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1063 goto qc24_host_busy_free_sp; 1064 } 1065 1066 return 0; 1067 1068 qc24_host_busy_free_sp: 1069 /* ref: INIT */ 1070 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1071 1072 qc24_target_busy: 1073 return SCSI_MLQUEUE_TARGET_BUSY; 1074 1075 qc24_fail_command: 1076 scsi_done(cmd); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * qla2x00_eh_wait_on_command 1083 * Waits for the command to be returned by the Firmware for some 1084 * max time. 1085 * 1086 * Input: 1087 * cmd = Scsi Command to wait on. 1088 * 1089 * Return: 1090 * Completed in time : QLA_SUCCESS 1091 * Did not complete in time : QLA_FUNCTION_FAILED 1092 */ 1093 static int 1094 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1095 { 1096 #define ABORT_POLLING_PERIOD 1000 1097 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1098 unsigned long wait_iter = ABORT_WAIT_ITER; 1099 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1100 struct qla_hw_data *ha = vha->hw; 1101 srb_t *sp = scsi_cmd_priv(cmd); 1102 int ret = QLA_SUCCESS; 1103 1104 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1105 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1106 "Return:eh_wait.\n"); 1107 return ret; 1108 } 1109 1110 while (sp->type && wait_iter--) 1111 msleep(ABORT_POLLING_PERIOD); 1112 if (sp->type) 1113 ret = QLA_FUNCTION_FAILED; 1114 1115 return ret; 1116 } 1117 1118 /* 1119 * qla2x00_wait_for_hba_online 1120 * Wait till the HBA is online after going through 1121 * <= MAX_RETRIES_OF_ISP_ABORT or 1122 * finally HBA is disabled ie marked offline 1123 * 1124 * Input: 1125 * ha - pointer to host adapter structure 1126 * 1127 * Note: 1128 * Does context switching-Release SPIN_LOCK 1129 * (if any) before calling this routine. 1130 * 1131 * Return: 1132 * Success (Adapter is online) : 0 1133 * Failed (Adapter is offline/disabled) : 1 1134 */ 1135 int 1136 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1137 { 1138 int return_status; 1139 unsigned long wait_online; 1140 struct qla_hw_data *ha = vha->hw; 1141 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1142 1143 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1144 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1145 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1146 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1147 ha->dpc_active) && time_before(jiffies, wait_online)) { 1148 1149 msleep(1000); 1150 } 1151 if (base_vha->flags.online) 1152 return_status = QLA_SUCCESS; 1153 else 1154 return_status = QLA_FUNCTION_FAILED; 1155 1156 return (return_status); 1157 } 1158 1159 static inline int test_fcport_count(scsi_qla_host_t *vha) 1160 { 1161 struct qla_hw_data *ha = vha->hw; 1162 unsigned long flags; 1163 int res; 1164 /* Return 0 = sleep, x=wake */ 1165 1166 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1167 ql_dbg(ql_dbg_init, vha, 0x00ec, 1168 "tgt %p, fcport_count=%d\n", 1169 vha, vha->fcport_count); 1170 res = (vha->fcport_count == 0); 1171 if (res) { 1172 struct fc_port *fcport; 1173 1174 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1175 if (fcport->deleted != QLA_SESS_DELETED) { 1176 /* session(s) may not be fully logged in 1177 * (ie fcport_count=0), but session 1178 * deletion thread(s) may be inflight. 1179 */ 1180 1181 res = 0; 1182 break; 1183 } 1184 } 1185 } 1186 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1187 1188 return res; 1189 } 1190 1191 /* 1192 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1193 * it has dependency on UNLOADING flag to stop device discovery 1194 */ 1195 void 1196 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1197 { 1198 u8 i; 1199 1200 qla2x00_mark_all_devices_lost(vha); 1201 1202 for (i = 0; i < 10; i++) { 1203 if (wait_event_timeout(vha->fcport_waitQ, 1204 test_fcport_count(vha), HZ) > 0) 1205 break; 1206 } 1207 1208 flush_workqueue(vha->hw->wq); 1209 } 1210 1211 /* 1212 * qla2x00_wait_for_hba_ready 1213 * Wait till the HBA is ready before doing driver unload 1214 * 1215 * Input: 1216 * ha - pointer to host adapter structure 1217 * 1218 * Note: 1219 * Does context switching-Release SPIN_LOCK 1220 * (if any) before calling this routine. 1221 * 1222 */ 1223 static void 1224 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1225 { 1226 struct qla_hw_data *ha = vha->hw; 1227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1228 1229 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1230 ha->flags.mbox_busy) || 1231 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1232 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1233 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1234 break; 1235 msleep(1000); 1236 } 1237 } 1238 1239 int 1240 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1241 { 1242 int return_status; 1243 unsigned long wait_reset; 1244 struct qla_hw_data *ha = vha->hw; 1245 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1246 1247 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1248 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1249 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1250 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1251 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1252 1253 msleep(1000); 1254 1255 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1256 ha->flags.chip_reset_done) 1257 break; 1258 } 1259 if (ha->flags.chip_reset_done) 1260 return_status = QLA_SUCCESS; 1261 else 1262 return_status = QLA_FUNCTION_FAILED; 1263 1264 return return_status; 1265 } 1266 1267 /************************************************************************** 1268 * qla2xxx_eh_abort 1269 * 1270 * Description: 1271 * The abort function will abort the specified command. 1272 * 1273 * Input: 1274 * cmd = Linux SCSI command packet to be aborted. 1275 * 1276 * Returns: 1277 * Either SUCCESS or FAILED. 1278 * 1279 * Note: 1280 * Only return FAILED if command not returned by firmware. 1281 **************************************************************************/ 1282 static int 1283 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1284 { 1285 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1286 DECLARE_COMPLETION_ONSTACK(comp); 1287 srb_t *sp; 1288 int ret; 1289 unsigned int id; 1290 uint64_t lun; 1291 int rval; 1292 struct qla_hw_data *ha = vha->hw; 1293 uint32_t ratov_j; 1294 struct qla_qpair *qpair; 1295 unsigned long flags; 1296 int fast_fail_status = SUCCESS; 1297 1298 if (qla2x00_isp_reg_stat(ha)) { 1299 ql_log(ql_log_info, vha, 0x8042, 1300 "PCI/Register disconnect, exiting.\n"); 1301 qla_pci_set_eeh_busy(vha); 1302 return FAILED; 1303 } 1304 1305 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1306 ret = fc_block_scsi_eh(cmd); 1307 if (ret != 0) 1308 fast_fail_status = ret; 1309 1310 sp = scsi_cmd_priv(cmd); 1311 qpair = sp->qpair; 1312 1313 vha->cmd_timeout_cnt++; 1314 1315 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1316 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1317 1318 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1319 sp->comp = ∁ 1320 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1321 1322 1323 id = cmd->device->id; 1324 lun = cmd->device->lun; 1325 1326 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1327 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1328 vha->host_no, id, lun, sp, cmd, sp->handle); 1329 1330 /* 1331 * Abort will release the original Command/sp from FW. Let the 1332 * original command call scsi_done. In return, he will wakeup 1333 * this sleeping thread. 1334 */ 1335 rval = ha->isp_ops->abort_command(sp); 1336 1337 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1338 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1339 1340 /* Wait for the command completion. */ 1341 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1342 ratov_j = msecs_to_jiffies(ratov_j); 1343 switch (rval) { 1344 case QLA_SUCCESS: 1345 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1346 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1347 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1348 __func__, ha->r_a_tov/10); 1349 ret = FAILED; 1350 } else { 1351 ret = fast_fail_status; 1352 } 1353 break; 1354 default: 1355 ret = FAILED; 1356 break; 1357 } 1358 1359 sp->comp = NULL; 1360 1361 ql_log(ql_log_info, vha, 0x801c, 1362 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1363 vha->host_no, id, lun, ret); 1364 1365 return ret; 1366 } 1367 1368 /* 1369 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1370 */ 1371 static int 1372 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1373 uint64_t l, enum nexus_wait_type type) 1374 { 1375 int cnt, match, status; 1376 unsigned long flags; 1377 scsi_qla_host_t *vha = qpair->vha; 1378 struct req_que *req = qpair->req; 1379 srb_t *sp; 1380 struct scsi_cmnd *cmd; 1381 1382 status = QLA_SUCCESS; 1383 1384 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1385 for (cnt = 1; status == QLA_SUCCESS && 1386 cnt < req->num_outstanding_cmds; cnt++) { 1387 sp = req->outstanding_cmds[cnt]; 1388 if (!sp) 1389 continue; 1390 if (sp->type != SRB_SCSI_CMD) 1391 continue; 1392 if (vha->vp_idx != sp->vha->vp_idx) 1393 continue; 1394 match = 0; 1395 cmd = GET_CMD_SP(sp); 1396 switch (type) { 1397 case WAIT_HOST: 1398 match = 1; 1399 break; 1400 case WAIT_TARGET: 1401 match = cmd->device->id == t; 1402 break; 1403 case WAIT_LUN: 1404 match = (cmd->device->id == t && 1405 cmd->device->lun == l); 1406 break; 1407 } 1408 if (!match) 1409 continue; 1410 1411 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1412 status = qla2x00_eh_wait_on_command(cmd); 1413 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1414 } 1415 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1416 1417 return status; 1418 } 1419 1420 int 1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1422 uint64_t l, enum nexus_wait_type type) 1423 { 1424 struct qla_qpair *qpair; 1425 struct qla_hw_data *ha = vha->hw; 1426 int i, status = QLA_SUCCESS; 1427 1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1429 type); 1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1431 qpair = ha->queue_pair_map[i]; 1432 if (!qpair) 1433 continue; 1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1435 type); 1436 } 1437 return status; 1438 } 1439 1440 static char *reset_errors[] = { 1441 "HBA not online", 1442 "HBA not ready", 1443 "Task management failed", 1444 "Waiting for command completions", 1445 }; 1446 1447 static int 1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 struct scsi_device *sdev = cmd->device; 1451 scsi_qla_host_t *vha = shost_priv(sdev->host); 1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1454 struct qla_hw_data *ha = vha->hw; 1455 int err; 1456 1457 if (qla2x00_isp_reg_stat(ha)) { 1458 ql_log(ql_log_info, vha, 0x803e, 1459 "PCI/Register disconnect, exiting.\n"); 1460 qla_pci_set_eeh_busy(vha); 1461 return FAILED; 1462 } 1463 1464 if (!fcport) { 1465 return FAILED; 1466 } 1467 1468 err = fc_block_rport(rport); 1469 if (err != 0) 1470 return err; 1471 1472 if (fcport->deleted) 1473 return FAILED; 1474 1475 ql_log(ql_log_info, vha, 0x8009, 1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1477 sdev->id, sdev->lun, cmd); 1478 1479 err = 0; 1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1481 ql_log(ql_log_warn, vha, 0x800a, 1482 "Wait for hba online failed for cmd=%p.\n", cmd); 1483 goto eh_reset_failed; 1484 } 1485 err = 2; 1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1487 != QLA_SUCCESS) { 1488 ql_log(ql_log_warn, vha, 0x800c, 1489 "do_reset failed for cmd=%p.\n", cmd); 1490 goto eh_reset_failed; 1491 } 1492 err = 3; 1493 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1494 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1495 ql_log(ql_log_warn, vha, 0x800d, 1496 "wait for pending cmds failed for cmd=%p.\n", cmd); 1497 goto eh_reset_failed; 1498 } 1499 1500 ql_log(ql_log_info, vha, 0x800e, 1501 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1502 vha->host_no, sdev->id, sdev->lun, cmd); 1503 1504 return SUCCESS; 1505 1506 eh_reset_failed: 1507 ql_log(ql_log_info, vha, 0x800f, 1508 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1509 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1510 cmd); 1511 vha->reset_cmd_err_cnt++; 1512 return FAILED; 1513 } 1514 1515 static int 1516 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1517 { 1518 struct scsi_device *sdev = cmd->device; 1519 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1520 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1521 struct qla_hw_data *ha = vha->hw; 1522 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1523 int err; 1524 1525 if (qla2x00_isp_reg_stat(ha)) { 1526 ql_log(ql_log_info, vha, 0x803f, 1527 "PCI/Register disconnect, exiting.\n"); 1528 qla_pci_set_eeh_busy(vha); 1529 return FAILED; 1530 } 1531 1532 if (!fcport) { 1533 return FAILED; 1534 } 1535 1536 err = fc_block_rport(rport); 1537 if (err != 0) 1538 return err; 1539 1540 if (fcport->deleted) 1541 return FAILED; 1542 1543 ql_log(ql_log_info, vha, 0x8009, 1544 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1545 sdev->id, cmd); 1546 1547 err = 0; 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1549 ql_log(ql_log_warn, vha, 0x800a, 1550 "Wait for hba online failed for cmd=%p.\n", cmd); 1551 goto eh_reset_failed; 1552 } 1553 err = 2; 1554 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1555 ql_log(ql_log_warn, vha, 0x800c, 1556 "target_reset failed for cmd=%p.\n", cmd); 1557 goto eh_reset_failed; 1558 } 1559 err = 3; 1560 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1561 0, WAIT_TARGET) != QLA_SUCCESS) { 1562 ql_log(ql_log_warn, vha, 0x800d, 1563 "wait for pending cmds failed for cmd=%p.\n", cmd); 1564 goto eh_reset_failed; 1565 } 1566 1567 ql_log(ql_log_info, vha, 0x800e, 1568 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1569 vha->host_no, sdev->id, cmd); 1570 1571 return SUCCESS; 1572 1573 eh_reset_failed: 1574 ql_log(ql_log_info, vha, 0x800f, 1575 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1576 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1577 cmd); 1578 vha->reset_cmd_err_cnt++; 1579 return FAILED; 1580 } 1581 1582 /************************************************************************** 1583 * qla2xxx_eh_bus_reset 1584 * 1585 * Description: 1586 * The bus reset function will reset the bus and abort any executing 1587 * commands. 1588 * 1589 * Input: 1590 * cmd = Linux SCSI command packet of the command that cause the 1591 * bus reset. 1592 * 1593 * Returns: 1594 * SUCCESS/FAILURE (defined as macro in scsi.h). 1595 * 1596 **************************************************************************/ 1597 static int 1598 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1599 { 1600 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1601 int ret = FAILED; 1602 unsigned int id; 1603 uint64_t lun; 1604 struct qla_hw_data *ha = vha->hw; 1605 1606 if (qla2x00_isp_reg_stat(ha)) { 1607 ql_log(ql_log_info, vha, 0x8040, 1608 "PCI/Register disconnect, exiting.\n"); 1609 qla_pci_set_eeh_busy(vha); 1610 return FAILED; 1611 } 1612 1613 id = cmd->device->id; 1614 lun = cmd->device->lun; 1615 1616 if (qla2x00_chip_is_down(vha)) 1617 return ret; 1618 1619 ql_log(ql_log_info, vha, 0x8012, 1620 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1621 1622 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1623 ql_log(ql_log_fatal, vha, 0x8013, 1624 "Wait for hba online failed board disabled.\n"); 1625 goto eh_bus_reset_done; 1626 } 1627 1628 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1629 ret = SUCCESS; 1630 1631 if (ret == FAILED) 1632 goto eh_bus_reset_done; 1633 1634 /* Flush outstanding commands. */ 1635 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1636 QLA_SUCCESS) { 1637 ql_log(ql_log_warn, vha, 0x8014, 1638 "Wait for pending commands failed.\n"); 1639 ret = FAILED; 1640 } 1641 1642 eh_bus_reset_done: 1643 ql_log(ql_log_warn, vha, 0x802b, 1644 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1645 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1646 1647 return ret; 1648 } 1649 1650 /************************************************************************** 1651 * qla2xxx_eh_host_reset 1652 * 1653 * Description: 1654 * The reset function will reset the Adapter. 1655 * 1656 * Input: 1657 * cmd = Linux SCSI command packet of the command that cause the 1658 * adapter reset. 1659 * 1660 * Returns: 1661 * Either SUCCESS or FAILED. 1662 * 1663 * Note: 1664 **************************************************************************/ 1665 static int 1666 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1667 { 1668 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1669 struct qla_hw_data *ha = vha->hw; 1670 int ret = FAILED; 1671 unsigned int id; 1672 uint64_t lun; 1673 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1674 1675 if (qla2x00_isp_reg_stat(ha)) { 1676 ql_log(ql_log_info, vha, 0x8041, 1677 "PCI/Register disconnect, exiting.\n"); 1678 qla_pci_set_eeh_busy(vha); 1679 return SUCCESS; 1680 } 1681 1682 id = cmd->device->id; 1683 lun = cmd->device->lun; 1684 1685 ql_log(ql_log_info, vha, 0x8018, 1686 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1687 1688 /* 1689 * No point in issuing another reset if one is active. Also do not 1690 * attempt a reset if we are updating flash. 1691 */ 1692 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1693 goto eh_host_reset_lock; 1694 1695 if (vha != base_vha) { 1696 if (qla2x00_vp_abort_isp(vha)) 1697 goto eh_host_reset_lock; 1698 } else { 1699 if (IS_P3P_TYPE(vha->hw)) { 1700 if (!qla82xx_fcoe_ctx_reset(vha)) { 1701 /* Ctx reset success */ 1702 ret = SUCCESS; 1703 goto eh_host_reset_lock; 1704 } 1705 /* fall thru if ctx reset failed */ 1706 } 1707 if (ha->wq) 1708 flush_workqueue(ha->wq); 1709 1710 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1711 if (ha->isp_ops->abort_isp(base_vha)) { 1712 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1713 /* failed. schedule dpc to try */ 1714 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1715 1716 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1717 ql_log(ql_log_warn, vha, 0x802a, 1718 "wait for hba online failed.\n"); 1719 goto eh_host_reset_lock; 1720 } 1721 } 1722 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1723 } 1724 1725 /* Waiting for command to be returned to OS.*/ 1726 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1727 QLA_SUCCESS) 1728 ret = SUCCESS; 1729 1730 eh_host_reset_lock: 1731 ql_log(ql_log_info, vha, 0x8017, 1732 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1733 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1734 1735 return ret; 1736 } 1737 1738 /* 1739 * qla2x00_loop_reset 1740 * Issue loop reset. 1741 * 1742 * Input: 1743 * ha = adapter block pointer. 1744 * 1745 * Returns: 1746 * 0 = success 1747 */ 1748 int 1749 qla2x00_loop_reset(scsi_qla_host_t *vha) 1750 { 1751 int ret; 1752 struct qla_hw_data *ha = vha->hw; 1753 1754 if (IS_QLAFX00(ha)) 1755 return QLA_SUCCESS; 1756 1757 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1758 atomic_set(&vha->loop_state, LOOP_DOWN); 1759 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1760 qla2x00_mark_all_devices_lost(vha); 1761 ret = qla2x00_full_login_lip(vha); 1762 if (ret != QLA_SUCCESS) { 1763 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1764 "full_login_lip=%d.\n", ret); 1765 } 1766 } 1767 1768 if (ha->flags.enable_lip_reset) { 1769 ret = qla2x00_lip_reset(vha); 1770 if (ret != QLA_SUCCESS) 1771 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1772 "lip_reset failed (%d).\n", ret); 1773 } 1774 1775 /* Issue marker command only when we are going to start the I/O */ 1776 vha->marker_needed = 1; 1777 1778 return QLA_SUCCESS; 1779 } 1780 1781 /* 1782 * The caller must ensure that no completion interrupts will happen 1783 * while this function is in progress. 1784 */ 1785 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1786 unsigned long *flags) 1787 __releases(qp->qp_lock_ptr) 1788 __acquires(qp->qp_lock_ptr) 1789 { 1790 DECLARE_COMPLETION_ONSTACK(comp); 1791 scsi_qla_host_t *vha = qp->vha; 1792 struct qla_hw_data *ha = vha->hw; 1793 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1794 int rval; 1795 bool ret_cmd; 1796 uint32_t ratov_j; 1797 1798 lockdep_assert_held(qp->qp_lock_ptr); 1799 1800 if (qla2x00_chip_is_down(vha)) { 1801 sp->done(sp, res); 1802 return; 1803 } 1804 1805 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1806 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1807 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1808 !qla2x00_isp_reg_stat(ha))) { 1809 if (sp->comp) { 1810 sp->done(sp, res); 1811 return; 1812 } 1813 1814 sp->comp = ∁ 1815 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1816 1817 rval = ha->isp_ops->abort_command(sp); 1818 /* Wait for command completion. */ 1819 ret_cmd = false; 1820 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1821 ratov_j = msecs_to_jiffies(ratov_j); 1822 switch (rval) { 1823 case QLA_SUCCESS: 1824 if (wait_for_completion_timeout(&comp, ratov_j)) { 1825 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1826 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1827 __func__, ha->r_a_tov/10); 1828 ret_cmd = true; 1829 } 1830 /* else FW return SP to driver */ 1831 break; 1832 default: 1833 ret_cmd = true; 1834 break; 1835 } 1836 1837 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1838 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1839 sp->done(sp, res); 1840 } else { 1841 sp->done(sp, res); 1842 } 1843 } 1844 1845 /* 1846 * The caller must ensure that no completion interrupts will happen 1847 * while this function is in progress. 1848 */ 1849 static void 1850 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1851 { 1852 int cnt; 1853 unsigned long flags; 1854 srb_t *sp; 1855 scsi_qla_host_t *vha = qp->vha; 1856 struct qla_hw_data *ha = vha->hw; 1857 struct req_que *req; 1858 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1859 struct qla_tgt_cmd *cmd; 1860 1861 if (!ha->req_q_map) 1862 return; 1863 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1864 req = qp->req; 1865 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1866 sp = req->outstanding_cmds[cnt]; 1867 if (sp) { 1868 /* 1869 * perform lockless completion during driver unload 1870 */ 1871 if (qla2x00_chip_is_down(vha)) { 1872 req->outstanding_cmds[cnt] = NULL; 1873 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1874 sp->done(sp, res); 1875 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1876 continue; 1877 } 1878 1879 switch (sp->cmd_type) { 1880 case TYPE_SRB: 1881 qla2x00_abort_srb(qp, sp, res, &flags); 1882 break; 1883 case TYPE_TGT_CMD: 1884 if (!vha->hw->tgt.tgt_ops || !tgt || 1885 qla_ini_mode_enabled(vha)) { 1886 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1887 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1888 vha->dpc_flags); 1889 continue; 1890 } 1891 cmd = (struct qla_tgt_cmd *)sp; 1892 cmd->aborted = 1; 1893 break; 1894 case TYPE_TGT_TMCMD: 1895 /* Skip task management functions. */ 1896 break; 1897 default: 1898 break; 1899 } 1900 req->outstanding_cmds[cnt] = NULL; 1901 } 1902 } 1903 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1904 } 1905 1906 /* 1907 * The caller must ensure that no completion interrupts will happen 1908 * while this function is in progress. 1909 */ 1910 void 1911 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1912 { 1913 int que; 1914 struct qla_hw_data *ha = vha->hw; 1915 1916 /* Continue only if initialization complete. */ 1917 if (!ha->base_qpair) 1918 return; 1919 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1920 1921 if (!ha->queue_pair_map) 1922 return; 1923 for (que = 0; que < ha->max_qpairs; que++) { 1924 if (!ha->queue_pair_map[que]) 1925 continue; 1926 1927 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1928 } 1929 } 1930 1931 static int 1932 qla2xxx_slave_alloc(struct scsi_device *sdev) 1933 { 1934 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1935 1936 if (!rport || fc_remote_port_chkready(rport)) 1937 return -ENXIO; 1938 1939 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1940 1941 return 0; 1942 } 1943 1944 static int 1945 qla2xxx_slave_configure(struct scsi_device *sdev) 1946 { 1947 scsi_qla_host_t *vha = shost_priv(sdev->host); 1948 struct req_que *req = vha->req; 1949 1950 if (IS_T10_PI_CAPABLE(vha->hw)) 1951 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1952 1953 scsi_change_queue_depth(sdev, req->max_q_depth); 1954 return 0; 1955 } 1956 1957 static void 1958 qla2xxx_slave_destroy(struct scsi_device *sdev) 1959 { 1960 sdev->hostdata = NULL; 1961 } 1962 1963 /** 1964 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1965 * @ha: HA context 1966 * 1967 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1968 * supported addressing method. 1969 */ 1970 static void 1971 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1972 { 1973 /* Assume a 32bit DMA mask. */ 1974 ha->flags.enable_64bit_addressing = 0; 1975 1976 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1977 /* Any upper-dword bits set? */ 1978 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1979 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1980 /* Ok, a 64bit DMA mask is applicable. */ 1981 ha->flags.enable_64bit_addressing = 1; 1982 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1983 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1984 return; 1985 } 1986 } 1987 1988 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1989 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1990 } 1991 1992 static void 1993 qla2x00_enable_intrs(struct qla_hw_data *ha) 1994 { 1995 unsigned long flags = 0; 1996 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1997 1998 spin_lock_irqsave(&ha->hardware_lock, flags); 1999 ha->interrupts_on = 1; 2000 /* enable risc and host interrupts */ 2001 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2002 rd_reg_word(®->ictrl); 2003 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2004 2005 } 2006 2007 static void 2008 qla2x00_disable_intrs(struct qla_hw_data *ha) 2009 { 2010 unsigned long flags = 0; 2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2012 2013 spin_lock_irqsave(&ha->hardware_lock, flags); 2014 ha->interrupts_on = 0; 2015 /* disable risc and host interrupts */ 2016 wrt_reg_word(®->ictrl, 0); 2017 rd_reg_word(®->ictrl); 2018 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2019 } 2020 2021 static void 2022 qla24xx_enable_intrs(struct qla_hw_data *ha) 2023 { 2024 unsigned long flags = 0; 2025 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2026 2027 spin_lock_irqsave(&ha->hardware_lock, flags); 2028 ha->interrupts_on = 1; 2029 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2030 rd_reg_dword(®->ictrl); 2031 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2032 } 2033 2034 static void 2035 qla24xx_disable_intrs(struct qla_hw_data *ha) 2036 { 2037 unsigned long flags = 0; 2038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2039 2040 if (IS_NOPOLLING_TYPE(ha)) 2041 return; 2042 spin_lock_irqsave(&ha->hardware_lock, flags); 2043 ha->interrupts_on = 0; 2044 wrt_reg_dword(®->ictrl, 0); 2045 rd_reg_dword(®->ictrl); 2046 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2047 } 2048 2049 static int 2050 qla2x00_iospace_config(struct qla_hw_data *ha) 2051 { 2052 resource_size_t pio; 2053 uint16_t msix; 2054 2055 if (pci_request_selected_regions(ha->pdev, ha->bars, 2056 QLA2XXX_DRIVER_NAME)) { 2057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2058 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2059 pci_name(ha->pdev)); 2060 goto iospace_error_exit; 2061 } 2062 if (!(ha->bars & 1)) 2063 goto skip_pio; 2064 2065 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2066 pio = pci_resource_start(ha->pdev, 0); 2067 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2068 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2069 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2070 "Invalid pci I/O region size (%s).\n", 2071 pci_name(ha->pdev)); 2072 pio = 0; 2073 } 2074 } else { 2075 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2076 "Region #0 no a PIO resource (%s).\n", 2077 pci_name(ha->pdev)); 2078 pio = 0; 2079 } 2080 ha->pio_address = pio; 2081 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2082 "PIO address=%llu.\n", 2083 (unsigned long long)ha->pio_address); 2084 2085 skip_pio: 2086 /* Use MMIO operations for all accesses. */ 2087 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2088 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2089 "Region #1 not an MMIO resource (%s), aborting.\n", 2090 pci_name(ha->pdev)); 2091 goto iospace_error_exit; 2092 } 2093 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2094 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2095 "Invalid PCI mem region size (%s), aborting.\n", 2096 pci_name(ha->pdev)); 2097 goto iospace_error_exit; 2098 } 2099 2100 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2101 if (!ha->iobase) { 2102 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2103 "Cannot remap MMIO (%s), aborting.\n", 2104 pci_name(ha->pdev)); 2105 goto iospace_error_exit; 2106 } 2107 2108 /* Determine queue resources */ 2109 ha->max_req_queues = ha->max_rsp_queues = 1; 2110 ha->msix_count = QLA_BASE_VECTORS; 2111 2112 /* Check if FW supports MQ or not */ 2113 if (!(ha->fw_attributes & BIT_6)) 2114 goto mqiobase_exit; 2115 2116 if (!ql2xmqsupport || !ql2xnvmeenable || 2117 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2118 goto mqiobase_exit; 2119 2120 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2121 pci_resource_len(ha->pdev, 3)); 2122 if (ha->mqiobase) { 2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2124 "MQIO Base=%p.\n", ha->mqiobase); 2125 /* Read MSIX vector size of the board */ 2126 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2127 ha->msix_count = msix + 1; 2128 /* Max queues are bounded by available msix vectors */ 2129 /* MB interrupt uses 1 vector */ 2130 ha->max_req_queues = ha->msix_count - 1; 2131 ha->max_rsp_queues = ha->max_req_queues; 2132 /* Queue pairs is the max value minus the base queue pair */ 2133 ha->max_qpairs = ha->max_rsp_queues - 1; 2134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2135 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2136 2137 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2138 "MSI-X vector count: %d.\n", ha->msix_count); 2139 } else 2140 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2141 "BAR 3 not enabled.\n"); 2142 2143 mqiobase_exit: 2144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2145 "MSIX Count: %d.\n", ha->msix_count); 2146 return (0); 2147 2148 iospace_error_exit: 2149 return (-ENOMEM); 2150 } 2151 2152 2153 static int 2154 qla83xx_iospace_config(struct qla_hw_data *ha) 2155 { 2156 uint16_t msix; 2157 2158 if (pci_request_selected_regions(ha->pdev, ha->bars, 2159 QLA2XXX_DRIVER_NAME)) { 2160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2161 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2162 pci_name(ha->pdev)); 2163 2164 goto iospace_error_exit; 2165 } 2166 2167 /* Use MMIO operations for all accesses. */ 2168 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2169 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2170 "Invalid pci I/O region size (%s).\n", 2171 pci_name(ha->pdev)); 2172 goto iospace_error_exit; 2173 } 2174 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2175 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2176 "Invalid PCI mem region size (%s), aborting\n", 2177 pci_name(ha->pdev)); 2178 goto iospace_error_exit; 2179 } 2180 2181 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2182 if (!ha->iobase) { 2183 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2184 "Cannot remap MMIO (%s), aborting.\n", 2185 pci_name(ha->pdev)); 2186 goto iospace_error_exit; 2187 } 2188 2189 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2190 /* 83XX 26XX always use MQ type access for queues 2191 * - mbar 2, a.k.a region 4 */ 2192 ha->max_req_queues = ha->max_rsp_queues = 1; 2193 ha->msix_count = QLA_BASE_VECTORS; 2194 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2195 pci_resource_len(ha->pdev, 4)); 2196 2197 if (!ha->mqiobase) { 2198 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2199 "BAR2/region4 not enabled\n"); 2200 goto mqiobase_exit; 2201 } 2202 2203 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2204 pci_resource_len(ha->pdev, 2)); 2205 if (ha->msixbase) { 2206 /* Read MSIX vector size of the board */ 2207 pci_read_config_word(ha->pdev, 2208 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2209 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2210 /* 2211 * By default, driver uses at least two msix vectors 2212 * (default & rspq) 2213 */ 2214 if (ql2xmqsupport || ql2xnvmeenable) { 2215 /* MB interrupt uses 1 vector */ 2216 ha->max_req_queues = ha->msix_count - 1; 2217 2218 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2219 if (QLA_TGT_MODE_ENABLED()) 2220 ha->max_req_queues--; 2221 2222 ha->max_rsp_queues = ha->max_req_queues; 2223 2224 /* Queue pairs is the max value minus 2225 * the base queue pair */ 2226 ha->max_qpairs = ha->max_req_queues - 1; 2227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2228 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2229 } 2230 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2231 "MSI-X vector count: %d.\n", ha->msix_count); 2232 } else 2233 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2234 "BAR 1 not enabled.\n"); 2235 2236 mqiobase_exit: 2237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2238 "MSIX Count: %d.\n", ha->msix_count); 2239 return 0; 2240 2241 iospace_error_exit: 2242 return -ENOMEM; 2243 } 2244 2245 static struct isp_operations qla2100_isp_ops = { 2246 .pci_config = qla2100_pci_config, 2247 .reset_chip = qla2x00_reset_chip, 2248 .chip_diag = qla2x00_chip_diag, 2249 .config_rings = qla2x00_config_rings, 2250 .reset_adapter = qla2x00_reset_adapter, 2251 .nvram_config = qla2x00_nvram_config, 2252 .update_fw_options = qla2x00_update_fw_options, 2253 .load_risc = qla2x00_load_risc, 2254 .pci_info_str = qla2x00_pci_info_str, 2255 .fw_version_str = qla2x00_fw_version_str, 2256 .intr_handler = qla2100_intr_handler, 2257 .enable_intrs = qla2x00_enable_intrs, 2258 .disable_intrs = qla2x00_disable_intrs, 2259 .abort_command = qla2x00_abort_command, 2260 .target_reset = qla2x00_abort_target, 2261 .lun_reset = qla2x00_lun_reset, 2262 .fabric_login = qla2x00_login_fabric, 2263 .fabric_logout = qla2x00_fabric_logout, 2264 .calc_req_entries = qla2x00_calc_iocbs_32, 2265 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2266 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2267 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2268 .read_nvram = qla2x00_read_nvram_data, 2269 .write_nvram = qla2x00_write_nvram_data, 2270 .fw_dump = qla2100_fw_dump, 2271 .beacon_on = NULL, 2272 .beacon_off = NULL, 2273 .beacon_blink = NULL, 2274 .read_optrom = qla2x00_read_optrom_data, 2275 .write_optrom = qla2x00_write_optrom_data, 2276 .get_flash_version = qla2x00_get_flash_version, 2277 .start_scsi = qla2x00_start_scsi, 2278 .start_scsi_mq = NULL, 2279 .abort_isp = qla2x00_abort_isp, 2280 .iospace_config = qla2x00_iospace_config, 2281 .initialize_adapter = qla2x00_initialize_adapter, 2282 }; 2283 2284 static struct isp_operations qla2300_isp_ops = { 2285 .pci_config = qla2300_pci_config, 2286 .reset_chip = qla2x00_reset_chip, 2287 .chip_diag = qla2x00_chip_diag, 2288 .config_rings = qla2x00_config_rings, 2289 .reset_adapter = qla2x00_reset_adapter, 2290 .nvram_config = qla2x00_nvram_config, 2291 .update_fw_options = qla2x00_update_fw_options, 2292 .load_risc = qla2x00_load_risc, 2293 .pci_info_str = qla2x00_pci_info_str, 2294 .fw_version_str = qla2x00_fw_version_str, 2295 .intr_handler = qla2300_intr_handler, 2296 .enable_intrs = qla2x00_enable_intrs, 2297 .disable_intrs = qla2x00_disable_intrs, 2298 .abort_command = qla2x00_abort_command, 2299 .target_reset = qla2x00_abort_target, 2300 .lun_reset = qla2x00_lun_reset, 2301 .fabric_login = qla2x00_login_fabric, 2302 .fabric_logout = qla2x00_fabric_logout, 2303 .calc_req_entries = qla2x00_calc_iocbs_32, 2304 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2305 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2306 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2307 .read_nvram = qla2x00_read_nvram_data, 2308 .write_nvram = qla2x00_write_nvram_data, 2309 .fw_dump = qla2300_fw_dump, 2310 .beacon_on = qla2x00_beacon_on, 2311 .beacon_off = qla2x00_beacon_off, 2312 .beacon_blink = qla2x00_beacon_blink, 2313 .read_optrom = qla2x00_read_optrom_data, 2314 .write_optrom = qla2x00_write_optrom_data, 2315 .get_flash_version = qla2x00_get_flash_version, 2316 .start_scsi = qla2x00_start_scsi, 2317 .start_scsi_mq = NULL, 2318 .abort_isp = qla2x00_abort_isp, 2319 .iospace_config = qla2x00_iospace_config, 2320 .initialize_adapter = qla2x00_initialize_adapter, 2321 }; 2322 2323 static struct isp_operations qla24xx_isp_ops = { 2324 .pci_config = qla24xx_pci_config, 2325 .reset_chip = qla24xx_reset_chip, 2326 .chip_diag = qla24xx_chip_diag, 2327 .config_rings = qla24xx_config_rings, 2328 .reset_adapter = qla24xx_reset_adapter, 2329 .nvram_config = qla24xx_nvram_config, 2330 .update_fw_options = qla24xx_update_fw_options, 2331 .load_risc = qla24xx_load_risc, 2332 .pci_info_str = qla24xx_pci_info_str, 2333 .fw_version_str = qla24xx_fw_version_str, 2334 .intr_handler = qla24xx_intr_handler, 2335 .enable_intrs = qla24xx_enable_intrs, 2336 .disable_intrs = qla24xx_disable_intrs, 2337 .abort_command = qla24xx_abort_command, 2338 .target_reset = qla24xx_abort_target, 2339 .lun_reset = qla24xx_lun_reset, 2340 .fabric_login = qla24xx_login_fabric, 2341 .fabric_logout = qla24xx_fabric_logout, 2342 .calc_req_entries = NULL, 2343 .build_iocbs = NULL, 2344 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2345 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2346 .read_nvram = qla24xx_read_nvram_data, 2347 .write_nvram = qla24xx_write_nvram_data, 2348 .fw_dump = qla24xx_fw_dump, 2349 .beacon_on = qla24xx_beacon_on, 2350 .beacon_off = qla24xx_beacon_off, 2351 .beacon_blink = qla24xx_beacon_blink, 2352 .read_optrom = qla24xx_read_optrom_data, 2353 .write_optrom = qla24xx_write_optrom_data, 2354 .get_flash_version = qla24xx_get_flash_version, 2355 .start_scsi = qla24xx_start_scsi, 2356 .start_scsi_mq = NULL, 2357 .abort_isp = qla2x00_abort_isp, 2358 .iospace_config = qla2x00_iospace_config, 2359 .initialize_adapter = qla2x00_initialize_adapter, 2360 }; 2361 2362 static struct isp_operations qla25xx_isp_ops = { 2363 .pci_config = qla25xx_pci_config, 2364 .reset_chip = qla24xx_reset_chip, 2365 .chip_diag = qla24xx_chip_diag, 2366 .config_rings = qla24xx_config_rings, 2367 .reset_adapter = qla24xx_reset_adapter, 2368 .nvram_config = qla24xx_nvram_config, 2369 .update_fw_options = qla24xx_update_fw_options, 2370 .load_risc = qla24xx_load_risc, 2371 .pci_info_str = qla24xx_pci_info_str, 2372 .fw_version_str = qla24xx_fw_version_str, 2373 .intr_handler = qla24xx_intr_handler, 2374 .enable_intrs = qla24xx_enable_intrs, 2375 .disable_intrs = qla24xx_disable_intrs, 2376 .abort_command = qla24xx_abort_command, 2377 .target_reset = qla24xx_abort_target, 2378 .lun_reset = qla24xx_lun_reset, 2379 .fabric_login = qla24xx_login_fabric, 2380 .fabric_logout = qla24xx_fabric_logout, 2381 .calc_req_entries = NULL, 2382 .build_iocbs = NULL, 2383 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2384 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2385 .read_nvram = qla25xx_read_nvram_data, 2386 .write_nvram = qla25xx_write_nvram_data, 2387 .fw_dump = qla25xx_fw_dump, 2388 .beacon_on = qla24xx_beacon_on, 2389 .beacon_off = qla24xx_beacon_off, 2390 .beacon_blink = qla24xx_beacon_blink, 2391 .read_optrom = qla25xx_read_optrom_data, 2392 .write_optrom = qla24xx_write_optrom_data, 2393 .get_flash_version = qla24xx_get_flash_version, 2394 .start_scsi = qla24xx_dif_start_scsi, 2395 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2396 .abort_isp = qla2x00_abort_isp, 2397 .iospace_config = qla2x00_iospace_config, 2398 .initialize_adapter = qla2x00_initialize_adapter, 2399 }; 2400 2401 static struct isp_operations qla81xx_isp_ops = { 2402 .pci_config = qla25xx_pci_config, 2403 .reset_chip = qla24xx_reset_chip, 2404 .chip_diag = qla24xx_chip_diag, 2405 .config_rings = qla24xx_config_rings, 2406 .reset_adapter = qla24xx_reset_adapter, 2407 .nvram_config = qla81xx_nvram_config, 2408 .update_fw_options = qla24xx_update_fw_options, 2409 .load_risc = qla81xx_load_risc, 2410 .pci_info_str = qla24xx_pci_info_str, 2411 .fw_version_str = qla24xx_fw_version_str, 2412 .intr_handler = qla24xx_intr_handler, 2413 .enable_intrs = qla24xx_enable_intrs, 2414 .disable_intrs = qla24xx_disable_intrs, 2415 .abort_command = qla24xx_abort_command, 2416 .target_reset = qla24xx_abort_target, 2417 .lun_reset = qla24xx_lun_reset, 2418 .fabric_login = qla24xx_login_fabric, 2419 .fabric_logout = qla24xx_fabric_logout, 2420 .calc_req_entries = NULL, 2421 .build_iocbs = NULL, 2422 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2423 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2424 .read_nvram = NULL, 2425 .write_nvram = NULL, 2426 .fw_dump = qla81xx_fw_dump, 2427 .beacon_on = qla24xx_beacon_on, 2428 .beacon_off = qla24xx_beacon_off, 2429 .beacon_blink = qla83xx_beacon_blink, 2430 .read_optrom = qla25xx_read_optrom_data, 2431 .write_optrom = qla24xx_write_optrom_data, 2432 .get_flash_version = qla24xx_get_flash_version, 2433 .start_scsi = qla24xx_dif_start_scsi, 2434 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2435 .abort_isp = qla2x00_abort_isp, 2436 .iospace_config = qla2x00_iospace_config, 2437 .initialize_adapter = qla2x00_initialize_adapter, 2438 }; 2439 2440 static struct isp_operations qla82xx_isp_ops = { 2441 .pci_config = qla82xx_pci_config, 2442 .reset_chip = qla82xx_reset_chip, 2443 .chip_diag = qla24xx_chip_diag, 2444 .config_rings = qla82xx_config_rings, 2445 .reset_adapter = qla24xx_reset_adapter, 2446 .nvram_config = qla81xx_nvram_config, 2447 .update_fw_options = qla24xx_update_fw_options, 2448 .load_risc = qla82xx_load_risc, 2449 .pci_info_str = qla24xx_pci_info_str, 2450 .fw_version_str = qla24xx_fw_version_str, 2451 .intr_handler = qla82xx_intr_handler, 2452 .enable_intrs = qla82xx_enable_intrs, 2453 .disable_intrs = qla82xx_disable_intrs, 2454 .abort_command = qla24xx_abort_command, 2455 .target_reset = qla24xx_abort_target, 2456 .lun_reset = qla24xx_lun_reset, 2457 .fabric_login = qla24xx_login_fabric, 2458 .fabric_logout = qla24xx_fabric_logout, 2459 .calc_req_entries = NULL, 2460 .build_iocbs = NULL, 2461 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2462 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2463 .read_nvram = qla24xx_read_nvram_data, 2464 .write_nvram = qla24xx_write_nvram_data, 2465 .fw_dump = qla82xx_fw_dump, 2466 .beacon_on = qla82xx_beacon_on, 2467 .beacon_off = qla82xx_beacon_off, 2468 .beacon_blink = NULL, 2469 .read_optrom = qla82xx_read_optrom_data, 2470 .write_optrom = qla82xx_write_optrom_data, 2471 .get_flash_version = qla82xx_get_flash_version, 2472 .start_scsi = qla82xx_start_scsi, 2473 .start_scsi_mq = NULL, 2474 .abort_isp = qla82xx_abort_isp, 2475 .iospace_config = qla82xx_iospace_config, 2476 .initialize_adapter = qla2x00_initialize_adapter, 2477 }; 2478 2479 static struct isp_operations qla8044_isp_ops = { 2480 .pci_config = qla82xx_pci_config, 2481 .reset_chip = qla82xx_reset_chip, 2482 .chip_diag = qla24xx_chip_diag, 2483 .config_rings = qla82xx_config_rings, 2484 .reset_adapter = qla24xx_reset_adapter, 2485 .nvram_config = qla81xx_nvram_config, 2486 .update_fw_options = qla24xx_update_fw_options, 2487 .load_risc = qla82xx_load_risc, 2488 .pci_info_str = qla24xx_pci_info_str, 2489 .fw_version_str = qla24xx_fw_version_str, 2490 .intr_handler = qla8044_intr_handler, 2491 .enable_intrs = qla82xx_enable_intrs, 2492 .disable_intrs = qla82xx_disable_intrs, 2493 .abort_command = qla24xx_abort_command, 2494 .target_reset = qla24xx_abort_target, 2495 .lun_reset = qla24xx_lun_reset, 2496 .fabric_login = qla24xx_login_fabric, 2497 .fabric_logout = qla24xx_fabric_logout, 2498 .calc_req_entries = NULL, 2499 .build_iocbs = NULL, 2500 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2501 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2502 .read_nvram = NULL, 2503 .write_nvram = NULL, 2504 .fw_dump = qla8044_fw_dump, 2505 .beacon_on = qla82xx_beacon_on, 2506 .beacon_off = qla82xx_beacon_off, 2507 .beacon_blink = NULL, 2508 .read_optrom = qla8044_read_optrom_data, 2509 .write_optrom = qla8044_write_optrom_data, 2510 .get_flash_version = qla82xx_get_flash_version, 2511 .start_scsi = qla82xx_start_scsi, 2512 .start_scsi_mq = NULL, 2513 .abort_isp = qla8044_abort_isp, 2514 .iospace_config = qla82xx_iospace_config, 2515 .initialize_adapter = qla2x00_initialize_adapter, 2516 }; 2517 2518 static struct isp_operations qla83xx_isp_ops = { 2519 .pci_config = qla25xx_pci_config, 2520 .reset_chip = qla24xx_reset_chip, 2521 .chip_diag = qla24xx_chip_diag, 2522 .config_rings = qla24xx_config_rings, 2523 .reset_adapter = qla24xx_reset_adapter, 2524 .nvram_config = qla81xx_nvram_config, 2525 .update_fw_options = qla24xx_update_fw_options, 2526 .load_risc = qla81xx_load_risc, 2527 .pci_info_str = qla24xx_pci_info_str, 2528 .fw_version_str = qla24xx_fw_version_str, 2529 .intr_handler = qla24xx_intr_handler, 2530 .enable_intrs = qla24xx_enable_intrs, 2531 .disable_intrs = qla24xx_disable_intrs, 2532 .abort_command = qla24xx_abort_command, 2533 .target_reset = qla24xx_abort_target, 2534 .lun_reset = qla24xx_lun_reset, 2535 .fabric_login = qla24xx_login_fabric, 2536 .fabric_logout = qla24xx_fabric_logout, 2537 .calc_req_entries = NULL, 2538 .build_iocbs = NULL, 2539 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2540 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2541 .read_nvram = NULL, 2542 .write_nvram = NULL, 2543 .fw_dump = qla83xx_fw_dump, 2544 .beacon_on = qla24xx_beacon_on, 2545 .beacon_off = qla24xx_beacon_off, 2546 .beacon_blink = qla83xx_beacon_blink, 2547 .read_optrom = qla25xx_read_optrom_data, 2548 .write_optrom = qla24xx_write_optrom_data, 2549 .get_flash_version = qla24xx_get_flash_version, 2550 .start_scsi = qla24xx_dif_start_scsi, 2551 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2552 .abort_isp = qla2x00_abort_isp, 2553 .iospace_config = qla83xx_iospace_config, 2554 .initialize_adapter = qla2x00_initialize_adapter, 2555 }; 2556 2557 static struct isp_operations qlafx00_isp_ops = { 2558 .pci_config = qlafx00_pci_config, 2559 .reset_chip = qlafx00_soft_reset, 2560 .chip_diag = qlafx00_chip_diag, 2561 .config_rings = qlafx00_config_rings, 2562 .reset_adapter = qlafx00_soft_reset, 2563 .nvram_config = NULL, 2564 .update_fw_options = NULL, 2565 .load_risc = NULL, 2566 .pci_info_str = qlafx00_pci_info_str, 2567 .fw_version_str = qlafx00_fw_version_str, 2568 .intr_handler = qlafx00_intr_handler, 2569 .enable_intrs = qlafx00_enable_intrs, 2570 .disable_intrs = qlafx00_disable_intrs, 2571 .abort_command = qla24xx_async_abort_command, 2572 .target_reset = qlafx00_abort_target, 2573 .lun_reset = qlafx00_lun_reset, 2574 .fabric_login = NULL, 2575 .fabric_logout = NULL, 2576 .calc_req_entries = NULL, 2577 .build_iocbs = NULL, 2578 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2579 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2580 .read_nvram = qla24xx_read_nvram_data, 2581 .write_nvram = qla24xx_write_nvram_data, 2582 .fw_dump = NULL, 2583 .beacon_on = qla24xx_beacon_on, 2584 .beacon_off = qla24xx_beacon_off, 2585 .beacon_blink = NULL, 2586 .read_optrom = qla24xx_read_optrom_data, 2587 .write_optrom = qla24xx_write_optrom_data, 2588 .get_flash_version = qla24xx_get_flash_version, 2589 .start_scsi = qlafx00_start_scsi, 2590 .start_scsi_mq = NULL, 2591 .abort_isp = qlafx00_abort_isp, 2592 .iospace_config = qlafx00_iospace_config, 2593 .initialize_adapter = qlafx00_initialize_adapter, 2594 }; 2595 2596 static struct isp_operations qla27xx_isp_ops = { 2597 .pci_config = qla25xx_pci_config, 2598 .reset_chip = qla24xx_reset_chip, 2599 .chip_diag = qla24xx_chip_diag, 2600 .config_rings = qla24xx_config_rings, 2601 .reset_adapter = qla24xx_reset_adapter, 2602 .nvram_config = qla81xx_nvram_config, 2603 .update_fw_options = qla24xx_update_fw_options, 2604 .load_risc = qla81xx_load_risc, 2605 .pci_info_str = qla24xx_pci_info_str, 2606 .fw_version_str = qla24xx_fw_version_str, 2607 .intr_handler = qla24xx_intr_handler, 2608 .enable_intrs = qla24xx_enable_intrs, 2609 .disable_intrs = qla24xx_disable_intrs, 2610 .abort_command = qla24xx_abort_command, 2611 .target_reset = qla24xx_abort_target, 2612 .lun_reset = qla24xx_lun_reset, 2613 .fabric_login = qla24xx_login_fabric, 2614 .fabric_logout = qla24xx_fabric_logout, 2615 .calc_req_entries = NULL, 2616 .build_iocbs = NULL, 2617 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2618 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2619 .read_nvram = NULL, 2620 .write_nvram = NULL, 2621 .fw_dump = qla27xx_fwdump, 2622 .mpi_fw_dump = qla27xx_mpi_fwdump, 2623 .beacon_on = qla24xx_beacon_on, 2624 .beacon_off = qla24xx_beacon_off, 2625 .beacon_blink = qla83xx_beacon_blink, 2626 .read_optrom = qla25xx_read_optrom_data, 2627 .write_optrom = qla24xx_write_optrom_data, 2628 .get_flash_version = qla24xx_get_flash_version, 2629 .start_scsi = qla24xx_dif_start_scsi, 2630 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2631 .abort_isp = qla2x00_abort_isp, 2632 .iospace_config = qla83xx_iospace_config, 2633 .initialize_adapter = qla2x00_initialize_adapter, 2634 }; 2635 2636 static inline void 2637 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2638 { 2639 ha->device_type = DT_EXTENDED_IDS; 2640 switch (ha->pdev->device) { 2641 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2642 ha->isp_type |= DT_ISP2100; 2643 ha->device_type &= ~DT_EXTENDED_IDS; 2644 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2645 break; 2646 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2647 ha->isp_type |= DT_ISP2200; 2648 ha->device_type &= ~DT_EXTENDED_IDS; 2649 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2650 break; 2651 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2652 ha->isp_type |= DT_ISP2300; 2653 ha->device_type |= DT_ZIO_SUPPORTED; 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2655 break; 2656 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2657 ha->isp_type |= DT_ISP2312; 2658 ha->device_type |= DT_ZIO_SUPPORTED; 2659 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2660 break; 2661 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2662 ha->isp_type |= DT_ISP2322; 2663 ha->device_type |= DT_ZIO_SUPPORTED; 2664 if (ha->pdev->subsystem_vendor == 0x1028 && 2665 ha->pdev->subsystem_device == 0x0170) 2666 ha->device_type |= DT_OEM_001; 2667 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2668 break; 2669 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2670 ha->isp_type |= DT_ISP6312; 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2672 break; 2673 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2674 ha->isp_type |= DT_ISP6322; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2678 ha->isp_type |= DT_ISP2422; 2679 ha->device_type |= DT_ZIO_SUPPORTED; 2680 ha->device_type |= DT_FWI2; 2681 ha->device_type |= DT_IIDMA; 2682 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2683 break; 2684 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2685 ha->isp_type |= DT_ISP2432; 2686 ha->device_type |= DT_ZIO_SUPPORTED; 2687 ha->device_type |= DT_FWI2; 2688 ha->device_type |= DT_IIDMA; 2689 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2690 break; 2691 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2692 ha->isp_type |= DT_ISP8432; 2693 ha->device_type |= DT_ZIO_SUPPORTED; 2694 ha->device_type |= DT_FWI2; 2695 ha->device_type |= DT_IIDMA; 2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2697 break; 2698 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2699 ha->isp_type |= DT_ISP5422; 2700 ha->device_type |= DT_FWI2; 2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2702 break; 2703 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2704 ha->isp_type |= DT_ISP5432; 2705 ha->device_type |= DT_FWI2; 2706 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2707 break; 2708 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2709 ha->isp_type |= DT_ISP2532; 2710 ha->device_type |= DT_ZIO_SUPPORTED; 2711 ha->device_type |= DT_FWI2; 2712 ha->device_type |= DT_IIDMA; 2713 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2714 break; 2715 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2716 ha->isp_type |= DT_ISP8001; 2717 ha->device_type |= DT_ZIO_SUPPORTED; 2718 ha->device_type |= DT_FWI2; 2719 ha->device_type |= DT_IIDMA; 2720 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2721 break; 2722 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2723 ha->isp_type |= DT_ISP8021; 2724 ha->device_type |= DT_ZIO_SUPPORTED; 2725 ha->device_type |= DT_FWI2; 2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2727 /* Initialize 82XX ISP flags */ 2728 qla82xx_init_flags(ha); 2729 break; 2730 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2731 ha->isp_type |= DT_ISP8044; 2732 ha->device_type |= DT_ZIO_SUPPORTED; 2733 ha->device_type |= DT_FWI2; 2734 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2735 /* Initialize 82XX ISP flags */ 2736 qla82xx_init_flags(ha); 2737 break; 2738 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2739 ha->isp_type |= DT_ISP2031; 2740 ha->device_type |= DT_ZIO_SUPPORTED; 2741 ha->device_type |= DT_FWI2; 2742 ha->device_type |= DT_IIDMA; 2743 ha->device_type |= DT_T10_PI; 2744 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2745 break; 2746 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2747 ha->isp_type |= DT_ISP8031; 2748 ha->device_type |= DT_ZIO_SUPPORTED; 2749 ha->device_type |= DT_FWI2; 2750 ha->device_type |= DT_IIDMA; 2751 ha->device_type |= DT_T10_PI; 2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2753 break; 2754 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2755 ha->isp_type |= DT_ISPFX00; 2756 break; 2757 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2758 ha->isp_type |= DT_ISP2071; 2759 ha->device_type |= DT_ZIO_SUPPORTED; 2760 ha->device_type |= DT_FWI2; 2761 ha->device_type |= DT_IIDMA; 2762 ha->device_type |= DT_T10_PI; 2763 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2764 break; 2765 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2766 ha->isp_type |= DT_ISP2271; 2767 ha->device_type |= DT_ZIO_SUPPORTED; 2768 ha->device_type |= DT_FWI2; 2769 ha->device_type |= DT_IIDMA; 2770 ha->device_type |= DT_T10_PI; 2771 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2772 break; 2773 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2774 ha->isp_type |= DT_ISP2261; 2775 ha->device_type |= DT_ZIO_SUPPORTED; 2776 ha->device_type |= DT_FWI2; 2777 ha->device_type |= DT_IIDMA; 2778 ha->device_type |= DT_T10_PI; 2779 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2780 break; 2781 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2782 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2783 ha->isp_type |= DT_ISP2081; 2784 ha->device_type |= DT_ZIO_SUPPORTED; 2785 ha->device_type |= DT_FWI2; 2786 ha->device_type |= DT_IIDMA; 2787 ha->device_type |= DT_T10_PI; 2788 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2789 break; 2790 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2791 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2792 ha->isp_type |= DT_ISP2281; 2793 ha->device_type |= DT_ZIO_SUPPORTED; 2794 ha->device_type |= DT_FWI2; 2795 ha->device_type |= DT_IIDMA; 2796 ha->device_type |= DT_T10_PI; 2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2798 break; 2799 } 2800 2801 if (IS_QLA82XX(ha)) 2802 ha->port_no = ha->portnum & 1; 2803 else { 2804 /* Get adapter physical port no from interrupt pin register. */ 2805 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2806 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2807 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2808 ha->port_no--; 2809 else 2810 ha->port_no = !(ha->port_no & 1); 2811 } 2812 2813 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2814 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2815 ha->device_type, ha->port_no, ha->fw_srisc_address); 2816 } 2817 2818 static void 2819 qla2xxx_scan_start(struct Scsi_Host *shost) 2820 { 2821 scsi_qla_host_t *vha = shost_priv(shost); 2822 2823 if (vha->hw->flags.running_gold_fw) 2824 return; 2825 2826 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2827 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2828 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2829 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2830 } 2831 2832 static int 2833 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2834 { 2835 scsi_qla_host_t *vha = shost_priv(shost); 2836 2837 if (test_bit(UNLOADING, &vha->dpc_flags)) 2838 return 1; 2839 if (!vha->host) 2840 return 1; 2841 if (time > vha->hw->loop_reset_delay * HZ) 2842 return 1; 2843 2844 return atomic_read(&vha->loop_state) == LOOP_READY; 2845 } 2846 2847 static void qla_heartbeat_work_fn(struct work_struct *work) 2848 { 2849 struct qla_hw_data *ha = container_of(work, 2850 struct qla_hw_data, heartbeat_work); 2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2852 2853 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2854 qla_no_op_mb(base_vha); 2855 } 2856 2857 static void qla2x00_iocb_work_fn(struct work_struct *work) 2858 { 2859 struct scsi_qla_host *vha = container_of(work, 2860 struct scsi_qla_host, iocb_work); 2861 struct qla_hw_data *ha = vha->hw; 2862 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2863 int i = 2; 2864 unsigned long flags; 2865 2866 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2867 return; 2868 2869 while (!list_empty(&vha->work_list) && i > 0) { 2870 qla2x00_do_work(vha); 2871 i--; 2872 } 2873 2874 spin_lock_irqsave(&vha->work_lock, flags); 2875 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2876 spin_unlock_irqrestore(&vha->work_lock, flags); 2877 } 2878 2879 static void 2880 qla_trace_init(void) 2881 { 2882 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2883 if (!qla_trc_array) { 2884 ql_log(ql_log_fatal, NULL, 0x0001, 2885 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2886 return; 2887 } 2888 2889 QLA_TRACE_ENABLE(qla_trc_array); 2890 } 2891 2892 static void 2893 qla_trace_uninit(void) 2894 { 2895 if (!qla_trc_array) 2896 return; 2897 trace_array_put(qla_trc_array); 2898 } 2899 2900 /* 2901 * PCI driver interface 2902 */ 2903 static int 2904 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2905 { 2906 int ret = -ENODEV; 2907 struct Scsi_Host *host; 2908 scsi_qla_host_t *base_vha = NULL; 2909 struct qla_hw_data *ha; 2910 char pci_info[30]; 2911 char fw_str[30], wq_name[30]; 2912 struct scsi_host_template *sht; 2913 int bars, mem_only = 0; 2914 uint16_t req_length = 0, rsp_length = 0; 2915 struct req_que *req = NULL; 2916 struct rsp_que *rsp = NULL; 2917 int i; 2918 2919 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2920 sht = &qla2xxx_driver_template; 2921 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2940 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2941 mem_only = 1; 2942 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2943 "Mem only adapter.\n"); 2944 } 2945 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2946 "Bars=%d.\n", bars); 2947 2948 if (mem_only) { 2949 if (pci_enable_device_mem(pdev)) 2950 return ret; 2951 } else { 2952 if (pci_enable_device(pdev)) 2953 return ret; 2954 } 2955 2956 if (is_kdump_kernel()) { 2957 ql2xmqsupport = 0; 2958 ql2xallocfwdump = 0; 2959 } 2960 2961 /* This may fail but that's ok */ 2962 pci_enable_pcie_error_reporting(pdev); 2963 2964 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2965 if (!ha) { 2966 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2967 "Unable to allocate memory for ha.\n"); 2968 goto disable_device; 2969 } 2970 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2971 "Memory allocated for ha=%p.\n", ha); 2972 ha->pdev = pdev; 2973 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2974 spin_lock_init(&ha->tgt.q_full_lock); 2975 spin_lock_init(&ha->tgt.sess_lock); 2976 spin_lock_init(&ha->tgt.atio_lock); 2977 2978 spin_lock_init(&ha->sadb_lock); 2979 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2980 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2981 2982 spin_lock_init(&ha->sadb_fp_lock); 2983 2984 if (qla_edif_sadb_build_free_pool(ha)) { 2985 kfree(ha); 2986 goto disable_device; 2987 } 2988 2989 atomic_set(&ha->nvme_active_aen_cnt, 0); 2990 2991 /* Clear our data area */ 2992 ha->bars = bars; 2993 ha->mem_only = mem_only; 2994 spin_lock_init(&ha->hardware_lock); 2995 spin_lock_init(&ha->vport_slock); 2996 mutex_init(&ha->selflogin_lock); 2997 mutex_init(&ha->optrom_mutex); 2998 2999 /* Set ISP-type information. */ 3000 qla2x00_set_isp_flags(ha); 3001 3002 /* Set EEH reset type to fundamental if required by hba */ 3003 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3004 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3005 pdev->needs_freset = 1; 3006 3007 ha->prev_topology = 0; 3008 ha->init_cb_size = sizeof(init_cb_t); 3009 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3010 ha->optrom_size = OPTROM_SIZE_2300; 3011 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3012 atomic_set(&ha->num_pend_mbx_stage1, 0); 3013 atomic_set(&ha->num_pend_mbx_stage2, 0); 3014 atomic_set(&ha->num_pend_mbx_stage3, 0); 3015 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3016 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3017 3018 /* Assign ISP specific operations. */ 3019 if (IS_QLA2100(ha)) { 3020 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3021 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3022 req_length = REQUEST_ENTRY_CNT_2100; 3023 rsp_length = RESPONSE_ENTRY_CNT_2100; 3024 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3025 ha->gid_list_info_size = 4; 3026 ha->flash_conf_off = ~0; 3027 ha->flash_data_off = ~0; 3028 ha->nvram_conf_off = ~0; 3029 ha->nvram_data_off = ~0; 3030 ha->isp_ops = &qla2100_isp_ops; 3031 } else if (IS_QLA2200(ha)) { 3032 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3033 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3034 req_length = REQUEST_ENTRY_CNT_2200; 3035 rsp_length = RESPONSE_ENTRY_CNT_2100; 3036 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3037 ha->gid_list_info_size = 4; 3038 ha->flash_conf_off = ~0; 3039 ha->flash_data_off = ~0; 3040 ha->nvram_conf_off = ~0; 3041 ha->nvram_data_off = ~0; 3042 ha->isp_ops = &qla2100_isp_ops; 3043 } else if (IS_QLA23XX(ha)) { 3044 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3045 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3046 req_length = REQUEST_ENTRY_CNT_2200; 3047 rsp_length = RESPONSE_ENTRY_CNT_2300; 3048 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3049 ha->gid_list_info_size = 6; 3050 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3051 ha->optrom_size = OPTROM_SIZE_2322; 3052 ha->flash_conf_off = ~0; 3053 ha->flash_data_off = ~0; 3054 ha->nvram_conf_off = ~0; 3055 ha->nvram_data_off = ~0; 3056 ha->isp_ops = &qla2300_isp_ops; 3057 } else if (IS_QLA24XX_TYPE(ha)) { 3058 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3059 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3060 req_length = REQUEST_ENTRY_CNT_24XX; 3061 rsp_length = RESPONSE_ENTRY_CNT_2300; 3062 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3063 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3064 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3065 ha->gid_list_info_size = 8; 3066 ha->optrom_size = OPTROM_SIZE_24XX; 3067 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3068 ha->isp_ops = &qla24xx_isp_ops; 3069 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3070 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3071 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3072 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3073 } else if (IS_QLA25XX(ha)) { 3074 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3075 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3076 req_length = REQUEST_ENTRY_CNT_24XX; 3077 rsp_length = RESPONSE_ENTRY_CNT_2300; 3078 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3079 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3080 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3081 ha->gid_list_info_size = 8; 3082 ha->optrom_size = OPTROM_SIZE_25XX; 3083 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3084 ha->isp_ops = &qla25xx_isp_ops; 3085 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3086 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3087 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3088 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3089 } else if (IS_QLA81XX(ha)) { 3090 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3091 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3092 req_length = REQUEST_ENTRY_CNT_24XX; 3093 rsp_length = RESPONSE_ENTRY_CNT_2300; 3094 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3095 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3096 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3097 ha->gid_list_info_size = 8; 3098 ha->optrom_size = OPTROM_SIZE_81XX; 3099 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3100 ha->isp_ops = &qla81xx_isp_ops; 3101 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3102 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3103 ha->nvram_conf_off = ~0; 3104 ha->nvram_data_off = ~0; 3105 } else if (IS_QLA82XX(ha)) { 3106 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3107 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3108 req_length = REQUEST_ENTRY_CNT_82XX; 3109 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3110 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3111 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3112 ha->gid_list_info_size = 8; 3113 ha->optrom_size = OPTROM_SIZE_82XX; 3114 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3115 ha->isp_ops = &qla82xx_isp_ops; 3116 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3117 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3118 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3119 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3120 } else if (IS_QLA8044(ha)) { 3121 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3122 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3123 req_length = REQUEST_ENTRY_CNT_82XX; 3124 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3125 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3126 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3127 ha->gid_list_info_size = 8; 3128 ha->optrom_size = OPTROM_SIZE_83XX; 3129 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3130 ha->isp_ops = &qla8044_isp_ops; 3131 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3132 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3133 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3134 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3135 } else if (IS_QLA83XX(ha)) { 3136 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3137 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3138 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3139 req_length = REQUEST_ENTRY_CNT_83XX; 3140 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3141 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3142 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3143 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3144 ha->gid_list_info_size = 8; 3145 ha->optrom_size = OPTROM_SIZE_83XX; 3146 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3147 ha->isp_ops = &qla83xx_isp_ops; 3148 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3149 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3150 ha->nvram_conf_off = ~0; 3151 ha->nvram_data_off = ~0; 3152 } else if (IS_QLAFX00(ha)) { 3153 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3154 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3155 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3156 req_length = REQUEST_ENTRY_CNT_FX00; 3157 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3158 ha->isp_ops = &qlafx00_isp_ops; 3159 ha->port_down_retry_count = 30; /* default value */ 3160 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3161 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3162 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3163 ha->mr.fw_hbt_en = 1; 3164 ha->mr.host_info_resend = false; 3165 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3166 } else if (IS_QLA27XX(ha)) { 3167 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3168 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3169 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3170 req_length = REQUEST_ENTRY_CNT_83XX; 3171 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3172 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3173 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3174 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3175 ha->gid_list_info_size = 8; 3176 ha->optrom_size = OPTROM_SIZE_83XX; 3177 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3178 ha->isp_ops = &qla27xx_isp_ops; 3179 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3180 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3181 ha->nvram_conf_off = ~0; 3182 ha->nvram_data_off = ~0; 3183 } else if (IS_QLA28XX(ha)) { 3184 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3185 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3186 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3187 req_length = REQUEST_ENTRY_CNT_83XX; 3188 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3189 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3190 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3191 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3192 ha->gid_list_info_size = 8; 3193 ha->optrom_size = OPTROM_SIZE_28XX; 3194 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3195 ha->isp_ops = &qla27xx_isp_ops; 3196 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3197 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3198 ha->nvram_conf_off = ~0; 3199 ha->nvram_data_off = ~0; 3200 } 3201 3202 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3203 "mbx_count=%d, req_length=%d, " 3204 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3205 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3206 "max_fibre_devices=%d.\n", 3207 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3208 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3209 ha->nvram_npiv_size, ha->max_fibre_devices); 3210 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3211 "isp_ops=%p, flash_conf_off=%d, " 3212 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3213 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3214 ha->nvram_conf_off, ha->nvram_data_off); 3215 3216 /* Configure PCI I/O space */ 3217 ret = ha->isp_ops->iospace_config(ha); 3218 if (ret) 3219 goto iospace_config_failed; 3220 3221 ql_log_pci(ql_log_info, pdev, 0x001d, 3222 "Found an ISP%04X irq %d iobase 0x%p.\n", 3223 pdev->device, pdev->irq, ha->iobase); 3224 mutex_init(&ha->vport_lock); 3225 mutex_init(&ha->mq_lock); 3226 init_completion(&ha->mbx_cmd_comp); 3227 complete(&ha->mbx_cmd_comp); 3228 init_completion(&ha->mbx_intr_comp); 3229 init_completion(&ha->dcbx_comp); 3230 init_completion(&ha->lb_portup_comp); 3231 3232 set_bit(0, (unsigned long *) ha->vp_idx_map); 3233 3234 qla2x00_config_dma_addressing(ha); 3235 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3236 "64 Bit addressing is %s.\n", 3237 ha->flags.enable_64bit_addressing ? "enable" : 3238 "disable"); 3239 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3240 if (ret) { 3241 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3242 "Failed to allocate memory for adapter, aborting.\n"); 3243 3244 goto probe_hw_failed; 3245 } 3246 3247 req->max_q_depth = MAX_Q_DEPTH; 3248 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3249 req->max_q_depth = ql2xmaxqdepth; 3250 3251 3252 base_vha = qla2x00_create_host(sht, ha); 3253 if (!base_vha) { 3254 ret = -ENOMEM; 3255 goto probe_hw_failed; 3256 } 3257 3258 pci_set_drvdata(pdev, base_vha); 3259 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3260 3261 host = base_vha->host; 3262 base_vha->req = req; 3263 if (IS_QLA2XXX_MIDTYPE(ha)) 3264 base_vha->mgmt_svr_loop_id = 3265 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3266 else 3267 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3268 base_vha->vp_idx; 3269 3270 /* Setup fcport template structure. */ 3271 ha->mr.fcport.vha = base_vha; 3272 ha->mr.fcport.port_type = FCT_UNKNOWN; 3273 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3274 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3275 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3276 ha->mr.fcport.scan_state = 1; 3277 3278 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3279 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3280 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3281 3282 /* Set the SG table size based on ISP type */ 3283 if (!IS_FWI2_CAPABLE(ha)) { 3284 if (IS_QLA2100(ha)) 3285 host->sg_tablesize = 32; 3286 } else { 3287 if (!IS_QLA82XX(ha)) 3288 host->sg_tablesize = QLA_SG_ALL; 3289 } 3290 host->max_id = ha->max_fibre_devices; 3291 host->cmd_per_lun = 3; 3292 host->unique_id = host->host_no; 3293 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3294 host->max_cmd_len = 32; 3295 else 3296 host->max_cmd_len = MAX_CMDSZ; 3297 host->max_channel = MAX_BUSES - 1; 3298 /* Older HBAs support only 16-bit LUNs */ 3299 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3300 ql2xmaxlun > 0xffff) 3301 host->max_lun = 0xffff; 3302 else 3303 host->max_lun = ql2xmaxlun; 3304 host->transportt = qla2xxx_transport_template; 3305 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3306 3307 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3308 "max_id=%d this_id=%d " 3309 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3310 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3311 host->this_id, host->cmd_per_lun, host->unique_id, 3312 host->max_cmd_len, host->max_channel, host->max_lun, 3313 host->transportt, sht->vendor_id); 3314 3315 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3316 3317 /* Set up the irqs */ 3318 ret = qla2x00_request_irqs(ha, rsp); 3319 if (ret) 3320 goto probe_failed; 3321 3322 /* Alloc arrays of request and response ring ptrs */ 3323 ret = qla2x00_alloc_queues(ha, req, rsp); 3324 if (ret) { 3325 ql_log(ql_log_fatal, base_vha, 0x003d, 3326 "Failed to allocate memory for queue pointers..." 3327 "aborting.\n"); 3328 ret = -ENODEV; 3329 goto probe_failed; 3330 } 3331 3332 if (ha->mqenable) { 3333 /* number of hardware queues supported by blk/scsi-mq*/ 3334 host->nr_hw_queues = ha->max_qpairs; 3335 3336 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3337 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3338 } else { 3339 if (ql2xnvmeenable) { 3340 host->nr_hw_queues = ha->max_qpairs; 3341 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3342 "FC-NVMe support is enabled, HW queues=%d\n", 3343 host->nr_hw_queues); 3344 } else { 3345 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3346 "blk/scsi-mq disabled.\n"); 3347 } 3348 } 3349 3350 qlt_probe_one_stage1(base_vha, ha); 3351 3352 pci_save_state(pdev); 3353 3354 /* Assign back pointers */ 3355 rsp->req = req; 3356 req->rsp = rsp; 3357 3358 if (IS_QLAFX00(ha)) { 3359 ha->rsp_q_map[0] = rsp; 3360 ha->req_q_map[0] = req; 3361 set_bit(0, ha->req_qid_map); 3362 set_bit(0, ha->rsp_qid_map); 3363 } 3364 3365 /* FWI2-capable only. */ 3366 req->req_q_in = &ha->iobase->isp24.req_q_in; 3367 req->req_q_out = &ha->iobase->isp24.req_q_out; 3368 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3369 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3370 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3371 IS_QLA28XX(ha)) { 3372 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3373 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3374 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3375 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3376 } 3377 3378 if (IS_QLAFX00(ha)) { 3379 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3380 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3381 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3382 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3383 } 3384 3385 if (IS_P3P_TYPE(ha)) { 3386 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3387 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3388 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3389 } 3390 3391 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3392 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3393 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3394 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3395 "req->req_q_in=%p req->req_q_out=%p " 3396 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3397 req->req_q_in, req->req_q_out, 3398 rsp->rsp_q_in, rsp->rsp_q_out); 3399 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3400 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3401 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3402 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3403 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3404 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3405 3406 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3407 if (unlikely(!ha->wq)) { 3408 ret = -ENOMEM; 3409 goto probe_failed; 3410 } 3411 3412 if (ha->isp_ops->initialize_adapter(base_vha)) { 3413 ql_log(ql_log_fatal, base_vha, 0x00d6, 3414 "Failed to initialize adapter - Adapter flags %x.\n", 3415 base_vha->device_flags); 3416 3417 if (IS_QLA82XX(ha)) { 3418 qla82xx_idc_lock(ha); 3419 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3420 QLA8XXX_DEV_FAILED); 3421 qla82xx_idc_unlock(ha); 3422 ql_log(ql_log_fatal, base_vha, 0x00d7, 3423 "HW State: FAILED.\n"); 3424 } else if (IS_QLA8044(ha)) { 3425 qla8044_idc_lock(ha); 3426 qla8044_wr_direct(base_vha, 3427 QLA8044_CRB_DEV_STATE_INDEX, 3428 QLA8XXX_DEV_FAILED); 3429 qla8044_idc_unlock(ha); 3430 ql_log(ql_log_fatal, base_vha, 0x0150, 3431 "HW State: FAILED.\n"); 3432 } 3433 3434 ret = -ENODEV; 3435 goto probe_failed; 3436 } 3437 3438 if (IS_QLAFX00(ha)) 3439 host->can_queue = QLAFX00_MAX_CANQUEUE; 3440 else 3441 host->can_queue = req->num_outstanding_cmds - 10; 3442 3443 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3444 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3445 host->can_queue, base_vha->req, 3446 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3447 3448 /* Check if FW supports MQ or not for ISP25xx */ 3449 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3450 ha->mqenable = 0; 3451 3452 if (ha->mqenable) { 3453 bool startit = false; 3454 3455 if (QLA_TGT_MODE_ENABLED()) 3456 startit = false; 3457 3458 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3459 startit = true; 3460 3461 /* Create start of day qpairs for Block MQ */ 3462 for (i = 0; i < ha->max_qpairs; i++) 3463 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3464 } 3465 qla_init_iocb_limit(base_vha); 3466 3467 if (ha->flags.running_gold_fw) 3468 goto skip_dpc; 3469 3470 /* 3471 * Startup the kernel thread for this host adapter 3472 */ 3473 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3474 "%s_dpc", base_vha->host_str); 3475 if (IS_ERR(ha->dpc_thread)) { 3476 ql_log(ql_log_fatal, base_vha, 0x00ed, 3477 "Failed to start DPC thread.\n"); 3478 ret = PTR_ERR(ha->dpc_thread); 3479 ha->dpc_thread = NULL; 3480 goto probe_failed; 3481 } 3482 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3483 "DPC thread started successfully.\n"); 3484 3485 /* 3486 * If we're not coming up in initiator mode, we might sit for 3487 * a while without waking up the dpc thread, which leads to a 3488 * stuck process warning. So just kick the dpc once here and 3489 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3490 */ 3491 qla2xxx_wake_dpc(base_vha); 3492 3493 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3494 3495 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3496 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3497 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3498 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3499 3500 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3501 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3502 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3503 INIT_WORK(&ha->idc_state_handler, 3504 qla83xx_idc_state_handler_work); 3505 INIT_WORK(&ha->nic_core_unrecoverable, 3506 qla83xx_nic_core_unrecoverable_work); 3507 } 3508 3509 skip_dpc: 3510 list_add_tail(&base_vha->list, &ha->vp_list); 3511 base_vha->host->irq = ha->pdev->irq; 3512 3513 /* Initialized the timer */ 3514 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3515 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3516 "Started qla2x00_timer with " 3517 "interval=%d.\n", WATCH_INTERVAL); 3518 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3519 "Detected hba at address=%p.\n", 3520 ha); 3521 3522 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3523 if (ha->fw_attributes & BIT_4) { 3524 int prot = 0, guard; 3525 3526 base_vha->flags.difdix_supported = 1; 3527 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3528 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3529 if (ql2xenabledif == 1) 3530 prot = SHOST_DIX_TYPE0_PROTECTION; 3531 if (ql2xprotmask) 3532 scsi_host_set_prot(host, ql2xprotmask); 3533 else 3534 scsi_host_set_prot(host, 3535 prot | SHOST_DIF_TYPE1_PROTECTION 3536 | SHOST_DIF_TYPE2_PROTECTION 3537 | SHOST_DIF_TYPE3_PROTECTION 3538 | SHOST_DIX_TYPE1_PROTECTION 3539 | SHOST_DIX_TYPE2_PROTECTION 3540 | SHOST_DIX_TYPE3_PROTECTION); 3541 3542 guard = SHOST_DIX_GUARD_CRC; 3543 3544 if (IS_PI_IPGUARD_CAPABLE(ha) && 3545 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3546 guard |= SHOST_DIX_GUARD_IP; 3547 3548 if (ql2xprotguard) 3549 scsi_host_set_guard(host, ql2xprotguard); 3550 else 3551 scsi_host_set_guard(host, guard); 3552 } else 3553 base_vha->flags.difdix_supported = 0; 3554 } 3555 3556 ha->isp_ops->enable_intrs(ha); 3557 3558 if (IS_QLAFX00(ha)) { 3559 ret = qlafx00_fx_disc(base_vha, 3560 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3561 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3562 QLA_SG_ALL : 128; 3563 } 3564 3565 ret = scsi_add_host(host, &pdev->dev); 3566 if (ret) 3567 goto probe_failed; 3568 3569 base_vha->flags.init_done = 1; 3570 base_vha->flags.online = 1; 3571 ha->prev_minidump_failed = 0; 3572 3573 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3574 "Init done and hba is online.\n"); 3575 3576 if (qla_ini_mode_enabled(base_vha) || 3577 qla_dual_mode_enabled(base_vha)) 3578 scsi_scan_host(host); 3579 else 3580 ql_log(ql_log_info, base_vha, 0x0122, 3581 "skipping scsi_scan_host() for non-initiator port\n"); 3582 3583 qla2x00_alloc_sysfs_attr(base_vha); 3584 3585 if (IS_QLAFX00(ha)) { 3586 ret = qlafx00_fx_disc(base_vha, 3587 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3588 3589 /* Register system information */ 3590 ret = qlafx00_fx_disc(base_vha, 3591 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3592 } 3593 3594 qla2x00_init_host_attr(base_vha); 3595 3596 qla2x00_dfs_setup(base_vha); 3597 3598 ql_log(ql_log_info, base_vha, 0x00fb, 3599 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3600 ql_log(ql_log_info, base_vha, 0x00fc, 3601 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3602 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3603 sizeof(pci_info)), 3604 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3605 base_vha->host_no, 3606 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3607 3608 qlt_add_target(ha, base_vha); 3609 3610 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3611 3612 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3613 return -ENODEV; 3614 3615 return 0; 3616 3617 probe_failed: 3618 qla_enode_stop(base_vha); 3619 qla_edb_stop(base_vha); 3620 vfree(base_vha->scan.l); 3621 if (base_vha->gnl.l) { 3622 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3623 base_vha->gnl.l, base_vha->gnl.ldma); 3624 base_vha->gnl.l = NULL; 3625 } 3626 3627 if (base_vha->timer_active) 3628 qla2x00_stop_timer(base_vha); 3629 base_vha->flags.online = 0; 3630 if (ha->dpc_thread) { 3631 struct task_struct *t = ha->dpc_thread; 3632 3633 ha->dpc_thread = NULL; 3634 kthread_stop(t); 3635 } 3636 3637 qla2x00_free_device(base_vha); 3638 scsi_host_put(base_vha->host); 3639 /* 3640 * Need to NULL out local req/rsp after 3641 * qla2x00_free_device => qla2x00_free_queues frees 3642 * what these are pointing to. Or else we'll 3643 * fall over below in qla2x00_free_req/rsp_que. 3644 */ 3645 req = NULL; 3646 rsp = NULL; 3647 3648 probe_hw_failed: 3649 qla2x00_mem_free(ha); 3650 qla2x00_free_req_que(ha, req); 3651 qla2x00_free_rsp_que(ha, rsp); 3652 qla2x00_clear_drv_active(ha); 3653 3654 iospace_config_failed: 3655 if (IS_P3P_TYPE(ha)) { 3656 if (!ha->nx_pcibase) 3657 iounmap((device_reg_t *)ha->nx_pcibase); 3658 if (!ql2xdbwr) 3659 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3660 } else { 3661 if (ha->iobase) 3662 iounmap(ha->iobase); 3663 if (ha->cregbase) 3664 iounmap(ha->cregbase); 3665 } 3666 pci_release_selected_regions(ha->pdev, ha->bars); 3667 kfree(ha); 3668 3669 disable_device: 3670 pci_disable_device(pdev); 3671 return ret; 3672 } 3673 3674 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3675 { 3676 scsi_qla_host_t *vp; 3677 unsigned long flags; 3678 struct qla_hw_data *ha; 3679 3680 if (!base_vha) 3681 return; 3682 3683 ha = base_vha->hw; 3684 3685 spin_lock_irqsave(&ha->vport_slock, flags); 3686 list_for_each_entry(vp, &ha->vp_list, list) 3687 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3688 3689 /* 3690 * Indicate device removal to prevent future board_disable 3691 * and wait until any pending board_disable has completed. 3692 */ 3693 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3694 spin_unlock_irqrestore(&ha->vport_slock, flags); 3695 } 3696 3697 static void 3698 qla2x00_shutdown(struct pci_dev *pdev) 3699 { 3700 scsi_qla_host_t *vha; 3701 struct qla_hw_data *ha; 3702 3703 vha = pci_get_drvdata(pdev); 3704 ha = vha->hw; 3705 3706 ql_log(ql_log_info, vha, 0xfffa, 3707 "Adapter shutdown\n"); 3708 3709 /* 3710 * Prevent future board_disable and wait 3711 * until any pending board_disable has completed. 3712 */ 3713 __qla_set_remove_flag(vha); 3714 cancel_work_sync(&ha->board_disable); 3715 3716 if (!atomic_read(&pdev->enable_cnt)) 3717 return; 3718 3719 /* Notify ISPFX00 firmware */ 3720 if (IS_QLAFX00(ha)) 3721 qlafx00_driver_shutdown(vha, 20); 3722 3723 /* Turn-off FCE trace */ 3724 if (ha->flags.fce_enabled) { 3725 qla2x00_disable_fce_trace(vha, NULL, NULL); 3726 ha->flags.fce_enabled = 0; 3727 } 3728 3729 /* Turn-off EFT trace */ 3730 if (ha->eft) 3731 qla2x00_disable_eft_trace(vha); 3732 3733 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3734 IS_QLA28XX(ha)) { 3735 if (ha->flags.fw_started) 3736 qla2x00_abort_isp_cleanup(vha); 3737 } else { 3738 /* Stop currently executing firmware. */ 3739 qla2x00_try_to_stop_firmware(vha); 3740 } 3741 3742 /* Disable timer */ 3743 if (vha->timer_active) 3744 qla2x00_stop_timer(vha); 3745 3746 /* Turn adapter off line */ 3747 vha->flags.online = 0; 3748 3749 /* turn-off interrupts on the card */ 3750 if (ha->interrupts_on) { 3751 vha->flags.init_done = 0; 3752 ha->isp_ops->disable_intrs(ha); 3753 } 3754 3755 qla2x00_free_irqs(vha); 3756 3757 qla2x00_free_fw_dump(ha); 3758 3759 pci_disable_device(pdev); 3760 ql_log(ql_log_info, vha, 0xfffe, 3761 "Adapter shutdown successfully.\n"); 3762 } 3763 3764 /* Deletes all the virtual ports for a given ha */ 3765 static void 3766 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3767 { 3768 scsi_qla_host_t *vha; 3769 unsigned long flags; 3770 3771 mutex_lock(&ha->vport_lock); 3772 while (ha->cur_vport_count) { 3773 spin_lock_irqsave(&ha->vport_slock, flags); 3774 3775 BUG_ON(base_vha->list.next == &ha->vp_list); 3776 /* This assumes first entry in ha->vp_list is always base vha */ 3777 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3778 scsi_host_get(vha->host); 3779 3780 spin_unlock_irqrestore(&ha->vport_slock, flags); 3781 mutex_unlock(&ha->vport_lock); 3782 3783 qla_nvme_delete(vha); 3784 3785 fc_vport_terminate(vha->fc_vport); 3786 scsi_host_put(vha->host); 3787 3788 mutex_lock(&ha->vport_lock); 3789 } 3790 mutex_unlock(&ha->vport_lock); 3791 } 3792 3793 /* Stops all deferred work threads */ 3794 static void 3795 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3796 { 3797 /* Cancel all work and destroy DPC workqueues */ 3798 if (ha->dpc_lp_wq) { 3799 cancel_work_sync(&ha->idc_aen); 3800 destroy_workqueue(ha->dpc_lp_wq); 3801 ha->dpc_lp_wq = NULL; 3802 } 3803 3804 if (ha->dpc_hp_wq) { 3805 cancel_work_sync(&ha->nic_core_reset); 3806 cancel_work_sync(&ha->idc_state_handler); 3807 cancel_work_sync(&ha->nic_core_unrecoverable); 3808 destroy_workqueue(ha->dpc_hp_wq); 3809 ha->dpc_hp_wq = NULL; 3810 } 3811 3812 /* Kill the kernel thread for this host */ 3813 if (ha->dpc_thread) { 3814 struct task_struct *t = ha->dpc_thread; 3815 3816 /* 3817 * qla2xxx_wake_dpc checks for ->dpc_thread 3818 * so we need to zero it out. 3819 */ 3820 ha->dpc_thread = NULL; 3821 kthread_stop(t); 3822 } 3823 } 3824 3825 static void 3826 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3827 { 3828 if (IS_QLA82XX(ha)) { 3829 3830 iounmap((device_reg_t *)ha->nx_pcibase); 3831 if (!ql2xdbwr) 3832 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3833 } else { 3834 if (ha->iobase) 3835 iounmap(ha->iobase); 3836 3837 if (ha->cregbase) 3838 iounmap(ha->cregbase); 3839 3840 if (ha->mqiobase) 3841 iounmap(ha->mqiobase); 3842 3843 if (ha->msixbase) 3844 iounmap(ha->msixbase); 3845 } 3846 } 3847 3848 static void 3849 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3850 { 3851 if (IS_QLA8044(ha)) { 3852 qla8044_idc_lock(ha); 3853 qla8044_clear_drv_active(ha); 3854 qla8044_idc_unlock(ha); 3855 } else if (IS_QLA82XX(ha)) { 3856 qla82xx_idc_lock(ha); 3857 qla82xx_clear_drv_active(ha); 3858 qla82xx_idc_unlock(ha); 3859 } 3860 } 3861 3862 static void 3863 qla2x00_remove_one(struct pci_dev *pdev) 3864 { 3865 scsi_qla_host_t *base_vha; 3866 struct qla_hw_data *ha; 3867 3868 base_vha = pci_get_drvdata(pdev); 3869 ha = base_vha->hw; 3870 ql_log(ql_log_info, base_vha, 0xb079, 3871 "Removing driver\n"); 3872 __qla_set_remove_flag(base_vha); 3873 cancel_work_sync(&ha->board_disable); 3874 3875 /* 3876 * If the PCI device is disabled then there was a PCI-disconnect and 3877 * qla2x00_disable_board_on_pci_error has taken care of most of the 3878 * resources. 3879 */ 3880 if (!atomic_read(&pdev->enable_cnt)) { 3881 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3882 base_vha->gnl.l, base_vha->gnl.ldma); 3883 base_vha->gnl.l = NULL; 3884 scsi_host_put(base_vha->host); 3885 kfree(ha); 3886 pci_set_drvdata(pdev, NULL); 3887 return; 3888 } 3889 qla2x00_wait_for_hba_ready(base_vha); 3890 3891 /* 3892 * if UNLOADING flag is already set, then continue unload, 3893 * where it was set first. 3894 */ 3895 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3896 return; 3897 3898 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3899 IS_QLA28XX(ha)) { 3900 if (ha->flags.fw_started) 3901 qla2x00_abort_isp_cleanup(base_vha); 3902 } else if (!IS_QLAFX00(ha)) { 3903 if (IS_QLA8031(ha)) { 3904 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3905 "Clearing fcoe driver presence.\n"); 3906 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3907 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3908 "Error while clearing DRV-Presence.\n"); 3909 } 3910 3911 qla2x00_try_to_stop_firmware(base_vha); 3912 } 3913 3914 qla2x00_wait_for_sess_deletion(base_vha); 3915 3916 qla_nvme_delete(base_vha); 3917 3918 dma_free_coherent(&ha->pdev->dev, 3919 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3920 3921 base_vha->gnl.l = NULL; 3922 qla_enode_stop(base_vha); 3923 qla_edb_stop(base_vha); 3924 3925 vfree(base_vha->scan.l); 3926 3927 if (IS_QLAFX00(ha)) 3928 qlafx00_driver_shutdown(base_vha, 20); 3929 3930 qla2x00_delete_all_vps(ha, base_vha); 3931 3932 qla2x00_dfs_remove(base_vha); 3933 3934 qla84xx_put_chip(base_vha); 3935 3936 /* Disable timer */ 3937 if (base_vha->timer_active) 3938 qla2x00_stop_timer(base_vha); 3939 3940 base_vha->flags.online = 0; 3941 3942 /* free DMA memory */ 3943 if (ha->exlogin_buf) 3944 qla2x00_free_exlogin_buffer(ha); 3945 3946 /* free DMA memory */ 3947 if (ha->exchoffld_buf) 3948 qla2x00_free_exchoffld_buffer(ha); 3949 3950 qla2x00_destroy_deferred_work(ha); 3951 3952 qlt_remove_target(ha, base_vha); 3953 3954 qla2x00_free_sysfs_attr(base_vha, true); 3955 3956 fc_remove_host(base_vha->host); 3957 3958 scsi_remove_host(base_vha->host); 3959 3960 qla2x00_free_device(base_vha); 3961 3962 qla2x00_clear_drv_active(ha); 3963 3964 scsi_host_put(base_vha->host); 3965 3966 qla2x00_unmap_iobases(ha); 3967 3968 pci_release_selected_regions(ha->pdev, ha->bars); 3969 kfree(ha); 3970 3971 pci_disable_pcie_error_reporting(pdev); 3972 3973 pci_disable_device(pdev); 3974 } 3975 3976 static inline void 3977 qla24xx_free_purex_list(struct purex_list *list) 3978 { 3979 struct purex_item *item, *next; 3980 ulong flags; 3981 3982 spin_lock_irqsave(&list->lock, flags); 3983 list_for_each_entry_safe(item, next, &list->head, list) { 3984 list_del(&item->list); 3985 if (item == &item->vha->default_item) 3986 continue; 3987 kfree(item); 3988 } 3989 spin_unlock_irqrestore(&list->lock, flags); 3990 } 3991 3992 static void 3993 qla2x00_free_device(scsi_qla_host_t *vha) 3994 { 3995 struct qla_hw_data *ha = vha->hw; 3996 3997 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3998 3999 /* Disable timer */ 4000 if (vha->timer_active) 4001 qla2x00_stop_timer(vha); 4002 4003 qla25xx_delete_queues(vha); 4004 vha->flags.online = 0; 4005 4006 /* turn-off interrupts on the card */ 4007 if (ha->interrupts_on) { 4008 vha->flags.init_done = 0; 4009 ha->isp_ops->disable_intrs(ha); 4010 } 4011 4012 qla2x00_free_fcports(vha); 4013 4014 qla2x00_free_irqs(vha); 4015 4016 /* Flush the work queue and remove it */ 4017 if (ha->wq) { 4018 destroy_workqueue(ha->wq); 4019 ha->wq = NULL; 4020 } 4021 4022 4023 qla24xx_free_purex_list(&vha->purex_list); 4024 4025 qla2x00_mem_free(ha); 4026 4027 qla82xx_md_free(vha); 4028 4029 qla_edif_sadb_release_free_pool(ha); 4030 qla_edif_sadb_release(ha); 4031 4032 qla2x00_free_queues(ha); 4033 } 4034 4035 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4036 { 4037 fc_port_t *fcport, *tfcport; 4038 4039 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4040 qla2x00_free_fcport(fcport); 4041 } 4042 4043 static inline void 4044 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4045 { 4046 int now; 4047 4048 if (!fcport->rport) 4049 return; 4050 4051 if (fcport->rport) { 4052 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4053 "%s %8phN. rport %p roles %x\n", 4054 __func__, fcport->port_name, fcport->rport, 4055 fcport->rport->roles); 4056 fc_remote_port_delete(fcport->rport); 4057 } 4058 qlt_do_generation_tick(vha, &now); 4059 } 4060 4061 /* 4062 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4063 * 4064 * Input: ha = adapter block pointer. fcport = port structure pointer. 4065 * 4066 * Return: None. 4067 * 4068 * Context: 4069 */ 4070 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4071 int do_login) 4072 { 4073 if (IS_QLAFX00(vha->hw)) { 4074 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4075 qla2x00_schedule_rport_del(vha, fcport); 4076 return; 4077 } 4078 4079 if (atomic_read(&fcport->state) == FCS_ONLINE && 4080 vha->vp_idx == fcport->vha->vp_idx) { 4081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4082 qla2x00_schedule_rport_del(vha, fcport); 4083 } 4084 4085 /* 4086 * We may need to retry the login, so don't change the state of the 4087 * port but do the retries. 4088 */ 4089 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4090 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4091 4092 if (!do_login) 4093 return; 4094 4095 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4096 } 4097 4098 void 4099 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4100 { 4101 fc_port_t *fcport; 4102 4103 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4104 "Mark all dev lost\n"); 4105 4106 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4107 if (ql2xfc2target && 4108 fcport->loop_id != FC_NO_LOOP_ID && 4109 (fcport->flags & FCF_FCP2_DEVICE) && 4110 fcport->port_type == FCT_TARGET && 4111 !qla2x00_reset_active(vha)) { 4112 ql_dbg(ql_dbg_disc, vha, 0x211a, 4113 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4114 fcport->flags, fcport->port_type, 4115 fcport->d_id.b24, fcport->port_name); 4116 continue; 4117 } 4118 fcport->scan_state = 0; 4119 qlt_schedule_sess_for_deletion(fcport); 4120 } 4121 } 4122 4123 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4124 { 4125 int i; 4126 4127 if (IS_FWI2_CAPABLE(ha)) 4128 return; 4129 4130 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4131 set_bit(i, ha->loop_id_map); 4132 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4133 set_bit(BROADCAST, ha->loop_id_map); 4134 } 4135 4136 /* 4137 * qla2x00_mem_alloc 4138 * Allocates adapter memory. 4139 * 4140 * Returns: 4141 * 0 = success. 4142 * !0 = failure. 4143 */ 4144 static int 4145 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4146 struct req_que **req, struct rsp_que **rsp) 4147 { 4148 char name[16]; 4149 int rc; 4150 4151 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4152 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4153 if (!ha->vp_map) 4154 goto fail; 4155 } 4156 4157 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4158 &ha->init_cb_dma, GFP_KERNEL); 4159 if (!ha->init_cb) 4160 goto fail_free_vp_map; 4161 4162 rc = btree_init32(&ha->host_map); 4163 if (rc) 4164 goto fail_free_init_cb; 4165 4166 if (qlt_mem_alloc(ha) < 0) 4167 goto fail_free_btree; 4168 4169 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4170 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4171 if (!ha->gid_list) 4172 goto fail_free_tgt_mem; 4173 4174 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4175 if (!ha->srb_mempool) 4176 goto fail_free_gid_list; 4177 4178 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4179 /* Allocate cache for CT6 Ctx. */ 4180 if (!ctx_cachep) { 4181 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4182 sizeof(struct ct6_dsd), 0, 4183 SLAB_HWCACHE_ALIGN, NULL); 4184 if (!ctx_cachep) 4185 goto fail_free_srb_mempool; 4186 } 4187 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4188 ctx_cachep); 4189 if (!ha->ctx_mempool) 4190 goto fail_free_srb_mempool; 4191 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4192 "ctx_cachep=%p ctx_mempool=%p.\n", 4193 ctx_cachep, ha->ctx_mempool); 4194 } 4195 4196 /* Get memory for cached NVRAM */ 4197 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4198 if (!ha->nvram) 4199 goto fail_free_ctx_mempool; 4200 4201 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4202 ha->pdev->device); 4203 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4204 DMA_POOL_SIZE, 8, 0); 4205 if (!ha->s_dma_pool) 4206 goto fail_free_nvram; 4207 4208 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4209 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4210 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4211 4212 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4213 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4214 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4215 if (!ha->dl_dma_pool) { 4216 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4217 "Failed to allocate memory for dl_dma_pool.\n"); 4218 goto fail_s_dma_pool; 4219 } 4220 4221 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4222 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4223 if (!ha->fcp_cmnd_dma_pool) { 4224 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4225 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4226 goto fail_dl_dma_pool; 4227 } 4228 4229 if (ql2xenabledif) { 4230 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4231 struct dsd_dma *dsd, *nxt; 4232 uint i; 4233 /* Creata a DMA pool of buffers for DIF bundling */ 4234 ha->dif_bundl_pool = dma_pool_create(name, 4235 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4236 if (!ha->dif_bundl_pool) { 4237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4238 "%s: failed create dif_bundl_pool\n", 4239 __func__); 4240 goto fail_dif_bundl_dma_pool; 4241 } 4242 4243 INIT_LIST_HEAD(&ha->pool.good.head); 4244 INIT_LIST_HEAD(&ha->pool.unusable.head); 4245 ha->pool.good.count = 0; 4246 ha->pool.unusable.count = 0; 4247 for (i = 0; i < 128; i++) { 4248 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4249 if (!dsd) { 4250 ql_dbg_pci(ql_dbg_init, ha->pdev, 4251 0xe0ee, "%s: failed alloc dsd\n", 4252 __func__); 4253 return -ENOMEM; 4254 } 4255 ha->dif_bundle_kallocs++; 4256 4257 dsd->dsd_addr = dma_pool_alloc( 4258 ha->dif_bundl_pool, GFP_ATOMIC, 4259 &dsd->dsd_list_dma); 4260 if (!dsd->dsd_addr) { 4261 ql_dbg_pci(ql_dbg_init, ha->pdev, 4262 0xe0ee, 4263 "%s: failed alloc ->dsd_addr\n", 4264 __func__); 4265 kfree(dsd); 4266 ha->dif_bundle_kallocs--; 4267 continue; 4268 } 4269 ha->dif_bundle_dma_allocs++; 4270 4271 /* 4272 * if DMA buffer crosses 4G boundary, 4273 * put it on bad list 4274 */ 4275 if (MSD(dsd->dsd_list_dma) ^ 4276 MSD(dsd->dsd_list_dma + bufsize)) { 4277 list_add_tail(&dsd->list, 4278 &ha->pool.unusable.head); 4279 ha->pool.unusable.count++; 4280 } else { 4281 list_add_tail(&dsd->list, 4282 &ha->pool.good.head); 4283 ha->pool.good.count++; 4284 } 4285 } 4286 4287 /* return the good ones back to the pool */ 4288 list_for_each_entry_safe(dsd, nxt, 4289 &ha->pool.good.head, list) { 4290 list_del(&dsd->list); 4291 dma_pool_free(ha->dif_bundl_pool, 4292 dsd->dsd_addr, dsd->dsd_list_dma); 4293 ha->dif_bundle_dma_allocs--; 4294 kfree(dsd); 4295 ha->dif_bundle_kallocs--; 4296 } 4297 4298 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4299 "%s: dif dma pool (good=%u unusable=%u)\n", 4300 __func__, ha->pool.good.count, 4301 ha->pool.unusable.count); 4302 } 4303 4304 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4305 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4306 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4307 ha->dif_bundl_pool); 4308 } 4309 4310 /* Allocate memory for SNS commands */ 4311 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4312 /* Get consistent memory allocated for SNS commands */ 4313 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4314 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4315 if (!ha->sns_cmd) 4316 goto fail_dma_pool; 4317 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4318 "sns_cmd: %p.\n", ha->sns_cmd); 4319 } else { 4320 /* Get consistent memory allocated for MS IOCB */ 4321 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4322 &ha->ms_iocb_dma); 4323 if (!ha->ms_iocb) 4324 goto fail_dma_pool; 4325 /* Get consistent memory allocated for CT SNS commands */ 4326 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4327 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4328 if (!ha->ct_sns) 4329 goto fail_free_ms_iocb; 4330 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4331 "ms_iocb=%p ct_sns=%p.\n", 4332 ha->ms_iocb, ha->ct_sns); 4333 } 4334 4335 /* Allocate memory for request ring */ 4336 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4337 if (!*req) { 4338 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4339 "Failed to allocate memory for req.\n"); 4340 goto fail_req; 4341 } 4342 (*req)->length = req_len; 4343 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4344 ((*req)->length + 1) * sizeof(request_t), 4345 &(*req)->dma, GFP_KERNEL); 4346 if (!(*req)->ring) { 4347 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4348 "Failed to allocate memory for req_ring.\n"); 4349 goto fail_req_ring; 4350 } 4351 /* Allocate memory for response ring */ 4352 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4353 if (!*rsp) { 4354 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4355 "Failed to allocate memory for rsp.\n"); 4356 goto fail_rsp; 4357 } 4358 (*rsp)->hw = ha; 4359 (*rsp)->length = rsp_len; 4360 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4361 ((*rsp)->length + 1) * sizeof(response_t), 4362 &(*rsp)->dma, GFP_KERNEL); 4363 if (!(*rsp)->ring) { 4364 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4365 "Failed to allocate memory for rsp_ring.\n"); 4366 goto fail_rsp_ring; 4367 } 4368 (*req)->rsp = *rsp; 4369 (*rsp)->req = *req; 4370 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4371 "req=%p req->length=%d req->ring=%p rsp=%p " 4372 "rsp->length=%d rsp->ring=%p.\n", 4373 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4374 (*rsp)->ring); 4375 /* Allocate memory for NVRAM data for vports */ 4376 if (ha->nvram_npiv_size) { 4377 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4378 sizeof(struct qla_npiv_entry), 4379 GFP_KERNEL); 4380 if (!ha->npiv_info) { 4381 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4382 "Failed to allocate memory for npiv_info.\n"); 4383 goto fail_npiv_info; 4384 } 4385 } else 4386 ha->npiv_info = NULL; 4387 4388 /* Get consistent memory allocated for EX-INIT-CB. */ 4389 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4390 IS_QLA28XX(ha)) { 4391 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4392 &ha->ex_init_cb_dma); 4393 if (!ha->ex_init_cb) 4394 goto fail_ex_init_cb; 4395 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4396 "ex_init_cb=%p.\n", ha->ex_init_cb); 4397 } 4398 4399 /* Get consistent memory allocated for Special Features-CB. */ 4400 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4401 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4402 &ha->sf_init_cb_dma); 4403 if (!ha->sf_init_cb) 4404 goto fail_sf_init_cb; 4405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4406 "sf_init_cb=%p.\n", ha->sf_init_cb); 4407 } 4408 4409 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4410 4411 /* Get consistent memory allocated for Async Port-Database. */ 4412 if (!IS_FWI2_CAPABLE(ha)) { 4413 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4414 &ha->async_pd_dma); 4415 if (!ha->async_pd) 4416 goto fail_async_pd; 4417 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4418 "async_pd=%p.\n", ha->async_pd); 4419 } 4420 4421 INIT_LIST_HEAD(&ha->vp_list); 4422 4423 /* Allocate memory for our loop_id bitmap */ 4424 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4425 sizeof(long), 4426 GFP_KERNEL); 4427 if (!ha->loop_id_map) 4428 goto fail_loop_id_map; 4429 else { 4430 qla2x00_set_reserved_loop_ids(ha); 4431 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4432 "loop_id_map=%p.\n", ha->loop_id_map); 4433 } 4434 4435 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4436 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4437 if (!ha->sfp_data) { 4438 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4439 "Unable to allocate memory for SFP read-data.\n"); 4440 goto fail_sfp_data; 4441 } 4442 4443 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4444 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4445 GFP_KERNEL); 4446 if (!ha->flt) { 4447 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4448 "Unable to allocate memory for FLT.\n"); 4449 goto fail_flt_buffer; 4450 } 4451 4452 /* allocate the purex dma pool */ 4453 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4454 ELS_MAX_PAYLOAD, 8, 0); 4455 4456 if (!ha->purex_dma_pool) { 4457 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4458 "Unable to allocate purex_dma_pool.\n"); 4459 goto fail_flt; 4460 } 4461 4462 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4463 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4464 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4465 4466 if (!ha->elsrej.c) { 4467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4468 "Alloc failed for els reject cmd.\n"); 4469 goto fail_elsrej; 4470 } 4471 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4472 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4473 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4474 return 0; 4475 4476 fail_elsrej: 4477 dma_pool_destroy(ha->purex_dma_pool); 4478 fail_flt: 4479 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4480 ha->flt, ha->flt_dma); 4481 4482 fail_flt_buffer: 4483 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4484 ha->sfp_data, ha->sfp_data_dma); 4485 fail_sfp_data: 4486 kfree(ha->loop_id_map); 4487 fail_loop_id_map: 4488 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4489 fail_async_pd: 4490 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4491 fail_sf_init_cb: 4492 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4493 fail_ex_init_cb: 4494 kfree(ha->npiv_info); 4495 fail_npiv_info: 4496 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4497 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4498 (*rsp)->ring = NULL; 4499 (*rsp)->dma = 0; 4500 fail_rsp_ring: 4501 kfree(*rsp); 4502 *rsp = NULL; 4503 fail_rsp: 4504 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4505 sizeof(request_t), (*req)->ring, (*req)->dma); 4506 (*req)->ring = NULL; 4507 (*req)->dma = 0; 4508 fail_req_ring: 4509 kfree(*req); 4510 *req = NULL; 4511 fail_req: 4512 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4513 ha->ct_sns, ha->ct_sns_dma); 4514 ha->ct_sns = NULL; 4515 ha->ct_sns_dma = 0; 4516 fail_free_ms_iocb: 4517 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4518 ha->ms_iocb = NULL; 4519 ha->ms_iocb_dma = 0; 4520 4521 if (ha->sns_cmd) 4522 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4523 ha->sns_cmd, ha->sns_cmd_dma); 4524 fail_dma_pool: 4525 if (ql2xenabledif) { 4526 struct dsd_dma *dsd, *nxt; 4527 4528 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4529 list) { 4530 list_del(&dsd->list); 4531 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4532 dsd->dsd_list_dma); 4533 ha->dif_bundle_dma_allocs--; 4534 kfree(dsd); 4535 ha->dif_bundle_kallocs--; 4536 ha->pool.unusable.count--; 4537 } 4538 dma_pool_destroy(ha->dif_bundl_pool); 4539 ha->dif_bundl_pool = NULL; 4540 } 4541 4542 fail_dif_bundl_dma_pool: 4543 if (IS_QLA82XX(ha) || ql2xenabledif) { 4544 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4545 ha->fcp_cmnd_dma_pool = NULL; 4546 } 4547 fail_dl_dma_pool: 4548 if (IS_QLA82XX(ha) || ql2xenabledif) { 4549 dma_pool_destroy(ha->dl_dma_pool); 4550 ha->dl_dma_pool = NULL; 4551 } 4552 fail_s_dma_pool: 4553 dma_pool_destroy(ha->s_dma_pool); 4554 ha->s_dma_pool = NULL; 4555 fail_free_nvram: 4556 kfree(ha->nvram); 4557 ha->nvram = NULL; 4558 fail_free_ctx_mempool: 4559 mempool_destroy(ha->ctx_mempool); 4560 ha->ctx_mempool = NULL; 4561 fail_free_srb_mempool: 4562 mempool_destroy(ha->srb_mempool); 4563 ha->srb_mempool = NULL; 4564 fail_free_gid_list: 4565 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4566 ha->gid_list, 4567 ha->gid_list_dma); 4568 ha->gid_list = NULL; 4569 ha->gid_list_dma = 0; 4570 fail_free_tgt_mem: 4571 qlt_mem_free(ha); 4572 fail_free_btree: 4573 btree_destroy32(&ha->host_map); 4574 fail_free_init_cb: 4575 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4576 ha->init_cb_dma); 4577 ha->init_cb = NULL; 4578 ha->init_cb_dma = 0; 4579 fail_free_vp_map: 4580 kfree(ha->vp_map); 4581 fail: 4582 ql_log(ql_log_fatal, NULL, 0x0030, 4583 "Memory allocation failure.\n"); 4584 return -ENOMEM; 4585 } 4586 4587 int 4588 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4589 { 4590 int rval; 4591 uint16_t size, max_cnt; 4592 uint32_t temp; 4593 struct qla_hw_data *ha = vha->hw; 4594 4595 /* Return if we don't need to alloacate any extended logins */ 4596 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4597 return QLA_SUCCESS; 4598 4599 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4600 return QLA_SUCCESS; 4601 4602 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4603 max_cnt = 0; 4604 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4605 if (rval != QLA_SUCCESS) { 4606 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4607 "Failed to get exlogin status.\n"); 4608 return rval; 4609 } 4610 4611 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4612 temp *= size; 4613 4614 if (temp != ha->exlogin_size) { 4615 qla2x00_free_exlogin_buffer(ha); 4616 ha->exlogin_size = temp; 4617 4618 ql_log(ql_log_info, vha, 0xd024, 4619 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4620 max_cnt, size, temp); 4621 4622 ql_log(ql_log_info, vha, 0xd025, 4623 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4624 4625 /* Get consistent memory for extended logins */ 4626 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4627 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4628 if (!ha->exlogin_buf) { 4629 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4630 "Failed to allocate memory for exlogin_buf_dma.\n"); 4631 return -ENOMEM; 4632 } 4633 } 4634 4635 /* Now configure the dma buffer */ 4636 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4637 if (rval) { 4638 ql_log(ql_log_fatal, vha, 0xd033, 4639 "Setup extended login buffer ****FAILED****.\n"); 4640 qla2x00_free_exlogin_buffer(ha); 4641 } 4642 4643 return rval; 4644 } 4645 4646 /* 4647 * qla2x00_free_exlogin_buffer 4648 * 4649 * Input: 4650 * ha = adapter block pointer 4651 */ 4652 void 4653 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4654 { 4655 if (ha->exlogin_buf) { 4656 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4657 ha->exlogin_buf, ha->exlogin_buf_dma); 4658 ha->exlogin_buf = NULL; 4659 ha->exlogin_size = 0; 4660 } 4661 } 4662 4663 static void 4664 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4665 { 4666 u32 temp; 4667 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4668 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4669 4670 if (max_cnt > vha->hw->max_exchg) 4671 max_cnt = vha->hw->max_exchg; 4672 4673 if (qla_ini_mode_enabled(vha)) { 4674 if (vha->ql2xiniexchg > max_cnt) 4675 vha->ql2xiniexchg = max_cnt; 4676 4677 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4678 *ret_cnt = vha->ql2xiniexchg; 4679 4680 } else if (qla_tgt_mode_enabled(vha)) { 4681 if (vha->ql2xexchoffld > max_cnt) { 4682 vha->ql2xexchoffld = max_cnt; 4683 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4684 } 4685 4686 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4687 *ret_cnt = vha->ql2xexchoffld; 4688 } else if (qla_dual_mode_enabled(vha)) { 4689 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4690 if (temp > max_cnt) { 4691 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4692 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4693 temp = max_cnt; 4694 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4695 } 4696 4697 if (temp > FW_DEF_EXCHANGES_CNT) 4698 *ret_cnt = temp; 4699 } 4700 } 4701 4702 int 4703 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4704 { 4705 int rval; 4706 u16 size, max_cnt; 4707 u32 actual_cnt, totsz; 4708 struct qla_hw_data *ha = vha->hw; 4709 4710 if (!ha->flags.exchoffld_enabled) 4711 return QLA_SUCCESS; 4712 4713 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4714 return QLA_SUCCESS; 4715 4716 max_cnt = 0; 4717 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4718 if (rval != QLA_SUCCESS) { 4719 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4720 "Failed to get exlogin status.\n"); 4721 return rval; 4722 } 4723 4724 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4725 ql_log(ql_log_info, vha, 0xd014, 4726 "Actual exchange offload count: %d.\n", actual_cnt); 4727 4728 totsz = actual_cnt * size; 4729 4730 if (totsz != ha->exchoffld_size) { 4731 qla2x00_free_exchoffld_buffer(ha); 4732 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4733 ha->exchoffld_size = 0; 4734 ha->flags.exchoffld_enabled = 0; 4735 return QLA_SUCCESS; 4736 } 4737 4738 ha->exchoffld_size = totsz; 4739 4740 ql_log(ql_log_info, vha, 0xd016, 4741 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4742 max_cnt, actual_cnt, size, totsz); 4743 4744 ql_log(ql_log_info, vha, 0xd017, 4745 "Exchange Buffers requested size = 0x%x\n", 4746 ha->exchoffld_size); 4747 4748 /* Get consistent memory for extended logins */ 4749 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4750 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4751 if (!ha->exchoffld_buf) { 4752 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4753 "Failed to allocate memory for Exchange Offload.\n"); 4754 4755 if (ha->max_exchg > 4756 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4757 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4758 } else if (ha->max_exchg > 4759 (FW_DEF_EXCHANGES_CNT + 512)) { 4760 ha->max_exchg -= 512; 4761 } else { 4762 ha->flags.exchoffld_enabled = 0; 4763 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4764 "Disabling Exchange offload due to lack of memory\n"); 4765 } 4766 ha->exchoffld_size = 0; 4767 4768 return -ENOMEM; 4769 } 4770 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4771 /* pathological case */ 4772 qla2x00_free_exchoffld_buffer(ha); 4773 ha->exchoffld_size = 0; 4774 ha->flags.exchoffld_enabled = 0; 4775 ql_log(ql_log_info, vha, 0xd016, 4776 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4777 ha->exchoffld_size, actual_cnt, size, totsz); 4778 return 0; 4779 } 4780 4781 /* Now configure the dma buffer */ 4782 rval = qla_set_exchoffld_mem_cfg(vha); 4783 if (rval) { 4784 ql_log(ql_log_fatal, vha, 0xd02e, 4785 "Setup exchange offload buffer ****FAILED****.\n"); 4786 qla2x00_free_exchoffld_buffer(ha); 4787 } else { 4788 /* re-adjust number of target exchange */ 4789 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4790 4791 if (qla_ini_mode_enabled(vha)) 4792 icb->exchange_count = 0; 4793 else 4794 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4795 } 4796 4797 return rval; 4798 } 4799 4800 /* 4801 * qla2x00_free_exchoffld_buffer 4802 * 4803 * Input: 4804 * ha = adapter block pointer 4805 */ 4806 void 4807 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4808 { 4809 if (ha->exchoffld_buf) { 4810 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4811 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4812 ha->exchoffld_buf = NULL; 4813 ha->exchoffld_size = 0; 4814 } 4815 } 4816 4817 /* 4818 * qla2x00_free_fw_dump 4819 * Frees fw dump stuff. 4820 * 4821 * Input: 4822 * ha = adapter block pointer 4823 */ 4824 static void 4825 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4826 { 4827 struct fwdt *fwdt = ha->fwdt; 4828 uint j; 4829 4830 if (ha->fce) 4831 dma_free_coherent(&ha->pdev->dev, 4832 FCE_SIZE, ha->fce, ha->fce_dma); 4833 4834 if (ha->eft) 4835 dma_free_coherent(&ha->pdev->dev, 4836 EFT_SIZE, ha->eft, ha->eft_dma); 4837 4838 vfree(ha->fw_dump); 4839 4840 ha->fce = NULL; 4841 ha->fce_dma = 0; 4842 ha->flags.fce_enabled = 0; 4843 ha->eft = NULL; 4844 ha->eft_dma = 0; 4845 ha->fw_dumped = false; 4846 ha->fw_dump_cap_flags = 0; 4847 ha->fw_dump_reading = 0; 4848 ha->fw_dump = NULL; 4849 ha->fw_dump_len = 0; 4850 4851 for (j = 0; j < 2; j++, fwdt++) { 4852 vfree(fwdt->template); 4853 fwdt->template = NULL; 4854 fwdt->length = 0; 4855 } 4856 } 4857 4858 /* 4859 * qla2x00_mem_free 4860 * Frees all adapter allocated memory. 4861 * 4862 * Input: 4863 * ha = adapter block pointer. 4864 */ 4865 static void 4866 qla2x00_mem_free(struct qla_hw_data *ha) 4867 { 4868 qla2x00_free_fw_dump(ha); 4869 4870 if (ha->mctp_dump) 4871 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4872 ha->mctp_dump_dma); 4873 ha->mctp_dump = NULL; 4874 4875 mempool_destroy(ha->srb_mempool); 4876 ha->srb_mempool = NULL; 4877 4878 if (ha->dcbx_tlv) 4879 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4880 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4881 ha->dcbx_tlv = NULL; 4882 4883 if (ha->xgmac_data) 4884 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4885 ha->xgmac_data, ha->xgmac_data_dma); 4886 ha->xgmac_data = NULL; 4887 4888 if (ha->sns_cmd) 4889 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4890 ha->sns_cmd, ha->sns_cmd_dma); 4891 ha->sns_cmd = NULL; 4892 ha->sns_cmd_dma = 0; 4893 4894 if (ha->ct_sns) 4895 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4896 ha->ct_sns, ha->ct_sns_dma); 4897 ha->ct_sns = NULL; 4898 ha->ct_sns_dma = 0; 4899 4900 if (ha->sfp_data) 4901 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4902 ha->sfp_data_dma); 4903 ha->sfp_data = NULL; 4904 4905 if (ha->flt) 4906 dma_free_coherent(&ha->pdev->dev, 4907 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4908 ha->flt, ha->flt_dma); 4909 ha->flt = NULL; 4910 ha->flt_dma = 0; 4911 4912 if (ha->ms_iocb) 4913 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4914 ha->ms_iocb = NULL; 4915 ha->ms_iocb_dma = 0; 4916 4917 if (ha->sf_init_cb) 4918 dma_pool_free(ha->s_dma_pool, 4919 ha->sf_init_cb, ha->sf_init_cb_dma); 4920 4921 if (ha->ex_init_cb) 4922 dma_pool_free(ha->s_dma_pool, 4923 ha->ex_init_cb, ha->ex_init_cb_dma); 4924 ha->ex_init_cb = NULL; 4925 ha->ex_init_cb_dma = 0; 4926 4927 if (ha->async_pd) 4928 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4929 ha->async_pd = NULL; 4930 ha->async_pd_dma = 0; 4931 4932 dma_pool_destroy(ha->s_dma_pool); 4933 ha->s_dma_pool = NULL; 4934 4935 if (ha->gid_list) 4936 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4937 ha->gid_list, ha->gid_list_dma); 4938 ha->gid_list = NULL; 4939 ha->gid_list_dma = 0; 4940 4941 if (IS_QLA82XX(ha)) { 4942 if (!list_empty(&ha->gbl_dsd_list)) { 4943 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4944 4945 /* clean up allocated prev pool */ 4946 list_for_each_entry_safe(dsd_ptr, 4947 tdsd_ptr, &ha->gbl_dsd_list, list) { 4948 dma_pool_free(ha->dl_dma_pool, 4949 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4950 list_del(&dsd_ptr->list); 4951 kfree(dsd_ptr); 4952 } 4953 } 4954 } 4955 4956 dma_pool_destroy(ha->dl_dma_pool); 4957 ha->dl_dma_pool = NULL; 4958 4959 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4960 ha->fcp_cmnd_dma_pool = NULL; 4961 4962 mempool_destroy(ha->ctx_mempool); 4963 ha->ctx_mempool = NULL; 4964 4965 if (ql2xenabledif && ha->dif_bundl_pool) { 4966 struct dsd_dma *dsd, *nxt; 4967 4968 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4969 list) { 4970 list_del(&dsd->list); 4971 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4972 dsd->dsd_list_dma); 4973 ha->dif_bundle_dma_allocs--; 4974 kfree(dsd); 4975 ha->dif_bundle_kallocs--; 4976 ha->pool.unusable.count--; 4977 } 4978 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4979 list_del(&dsd->list); 4980 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4981 dsd->dsd_list_dma); 4982 ha->dif_bundle_dma_allocs--; 4983 kfree(dsd); 4984 ha->dif_bundle_kallocs--; 4985 } 4986 } 4987 4988 dma_pool_destroy(ha->dif_bundl_pool); 4989 ha->dif_bundl_pool = NULL; 4990 4991 qlt_mem_free(ha); 4992 qla_remove_hostmap(ha); 4993 4994 if (ha->init_cb) 4995 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4996 ha->init_cb, ha->init_cb_dma); 4997 4998 dma_pool_destroy(ha->purex_dma_pool); 4999 ha->purex_dma_pool = NULL; 5000 5001 if (ha->elsrej.c) { 5002 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 5003 ha->elsrej.c, ha->elsrej.cdma); 5004 ha->elsrej.c = NULL; 5005 } 5006 5007 ha->init_cb = NULL; 5008 ha->init_cb_dma = 0; 5009 5010 vfree(ha->optrom_buffer); 5011 ha->optrom_buffer = NULL; 5012 kfree(ha->nvram); 5013 ha->nvram = NULL; 5014 kfree(ha->npiv_info); 5015 ha->npiv_info = NULL; 5016 kfree(ha->swl); 5017 ha->swl = NULL; 5018 kfree(ha->loop_id_map); 5019 ha->sf_init_cb = NULL; 5020 ha->sf_init_cb_dma = 0; 5021 ha->loop_id_map = NULL; 5022 5023 kfree(ha->vp_map); 5024 ha->vp_map = NULL; 5025 } 5026 5027 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 5028 struct qla_hw_data *ha) 5029 { 5030 struct Scsi_Host *host; 5031 struct scsi_qla_host *vha = NULL; 5032 5033 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5034 if (!host) { 5035 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5036 "Failed to allocate host from the scsi layer, aborting.\n"); 5037 return NULL; 5038 } 5039 5040 /* Clear our data area */ 5041 vha = shost_priv(host); 5042 memset(vha, 0, sizeof(scsi_qla_host_t)); 5043 5044 vha->host = host; 5045 vha->host_no = host->host_no; 5046 vha->hw = ha; 5047 5048 vha->qlini_mode = ql2x_ini_mode; 5049 vha->ql2xexchoffld = ql2xexchoffld; 5050 vha->ql2xiniexchg = ql2xiniexchg; 5051 5052 INIT_LIST_HEAD(&vha->vp_fcports); 5053 INIT_LIST_HEAD(&vha->work_list); 5054 INIT_LIST_HEAD(&vha->list); 5055 INIT_LIST_HEAD(&vha->qla_cmd_list); 5056 INIT_LIST_HEAD(&vha->logo_list); 5057 INIT_LIST_HEAD(&vha->plogi_ack_list); 5058 INIT_LIST_HEAD(&vha->qp_list); 5059 INIT_LIST_HEAD(&vha->gnl.fcports); 5060 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5061 5062 INIT_LIST_HEAD(&vha->purex_list.head); 5063 spin_lock_init(&vha->purex_list.lock); 5064 5065 spin_lock_init(&vha->work_lock); 5066 spin_lock_init(&vha->cmd_list_lock); 5067 init_waitqueue_head(&vha->fcport_waitQ); 5068 init_waitqueue_head(&vha->vref_waitq); 5069 qla_enode_init(vha); 5070 qla_edb_init(vha); 5071 5072 5073 vha->gnl.size = sizeof(struct get_name_list_extended) * 5074 (ha->max_loop_id + 1); 5075 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5076 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5077 if (!vha->gnl.l) { 5078 ql_log(ql_log_fatal, vha, 0xd04a, 5079 "Alloc failed for name list.\n"); 5080 scsi_host_put(vha->host); 5081 return NULL; 5082 } 5083 5084 /* todo: what about ext login? */ 5085 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5086 vha->scan.l = vmalloc(vha->scan.size); 5087 if (!vha->scan.l) { 5088 ql_log(ql_log_fatal, vha, 0xd04a, 5089 "Alloc failed for scan database.\n"); 5090 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5091 vha->gnl.l, vha->gnl.ldma); 5092 vha->gnl.l = NULL; 5093 scsi_host_put(vha->host); 5094 return NULL; 5095 } 5096 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5097 5098 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5099 ql_dbg(ql_dbg_init, vha, 0x0041, 5100 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5101 vha->host, vha->hw, vha, 5102 dev_name(&(ha->pdev->dev))); 5103 5104 return vha; 5105 } 5106 5107 struct qla_work_evt * 5108 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5109 { 5110 struct qla_work_evt *e; 5111 5112 if (test_bit(UNLOADING, &vha->dpc_flags)) 5113 return NULL; 5114 5115 if (qla_vha_mark_busy(vha)) 5116 return NULL; 5117 5118 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5119 if (!e) { 5120 QLA_VHA_MARK_NOT_BUSY(vha); 5121 return NULL; 5122 } 5123 5124 INIT_LIST_HEAD(&e->list); 5125 e->type = type; 5126 e->flags = QLA_EVT_FLAG_FREE; 5127 return e; 5128 } 5129 5130 int 5131 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5132 { 5133 unsigned long flags; 5134 bool q = false; 5135 5136 spin_lock_irqsave(&vha->work_lock, flags); 5137 list_add_tail(&e->list, &vha->work_list); 5138 5139 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5140 q = true; 5141 5142 spin_unlock_irqrestore(&vha->work_lock, flags); 5143 5144 if (q) 5145 queue_work(vha->hw->wq, &vha->iocb_work); 5146 5147 return QLA_SUCCESS; 5148 } 5149 5150 int 5151 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5152 u32 data) 5153 { 5154 struct qla_work_evt *e; 5155 5156 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5157 if (!e) 5158 return QLA_FUNCTION_FAILED; 5159 5160 e->u.aen.code = code; 5161 e->u.aen.data = data; 5162 return qla2x00_post_work(vha, e); 5163 } 5164 5165 int 5166 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5167 { 5168 struct qla_work_evt *e; 5169 5170 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5171 if (!e) 5172 return QLA_FUNCTION_FAILED; 5173 5174 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5175 return qla2x00_post_work(vha, e); 5176 } 5177 5178 #define qla2x00_post_async_work(name, type) \ 5179 int qla2x00_post_async_##name##_work( \ 5180 struct scsi_qla_host *vha, \ 5181 fc_port_t *fcport, uint16_t *data) \ 5182 { \ 5183 struct qla_work_evt *e; \ 5184 \ 5185 e = qla2x00_alloc_work(vha, type); \ 5186 if (!e) \ 5187 return QLA_FUNCTION_FAILED; \ 5188 \ 5189 e->u.logio.fcport = fcport; \ 5190 if (data) { \ 5191 e->u.logio.data[0] = data[0]; \ 5192 e->u.logio.data[1] = data[1]; \ 5193 } \ 5194 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5195 return qla2x00_post_work(vha, e); \ 5196 } 5197 5198 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5199 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5200 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5201 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5202 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5203 5204 int 5205 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5206 { 5207 struct qla_work_evt *e; 5208 5209 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5210 if (!e) 5211 return QLA_FUNCTION_FAILED; 5212 5213 e->u.uevent.code = code; 5214 return qla2x00_post_work(vha, e); 5215 } 5216 5217 static void 5218 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5219 { 5220 char event_string[40]; 5221 char *envp[] = { event_string, NULL }; 5222 5223 switch (code) { 5224 case QLA_UEVENT_CODE_FW_DUMP: 5225 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5226 vha->host_no); 5227 break; 5228 default: 5229 /* do nothing */ 5230 break; 5231 } 5232 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5233 } 5234 5235 int 5236 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5237 uint32_t *data, int cnt) 5238 { 5239 struct qla_work_evt *e; 5240 5241 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5242 if (!e) 5243 return QLA_FUNCTION_FAILED; 5244 5245 e->u.aenfx.evtcode = evtcode; 5246 e->u.aenfx.count = cnt; 5247 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5248 return qla2x00_post_work(vha, e); 5249 } 5250 5251 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5252 { 5253 unsigned long flags; 5254 5255 if (IS_SW_RESV_ADDR(fcport->d_id)) 5256 return; 5257 5258 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5259 if (fcport->disc_state == DSC_UPD_FCPORT) { 5260 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5261 return; 5262 } 5263 fcport->jiffies_at_registration = jiffies; 5264 fcport->sec_since_registration = 0; 5265 fcport->next_disc_state = DSC_DELETED; 5266 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5267 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5268 5269 queue_work(system_unbound_wq, &fcport->reg_work); 5270 } 5271 5272 static 5273 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5274 { 5275 unsigned long flags; 5276 fc_port_t *fcport = NULL, *tfcp; 5277 struct qlt_plogi_ack_t *pla = 5278 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5279 uint8_t free_fcport = 0; 5280 5281 ql_dbg(ql_dbg_disc, vha, 0xffff, 5282 "%s %d %8phC enter\n", 5283 __func__, __LINE__, e->u.new_sess.port_name); 5284 5285 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5286 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5287 if (fcport) { 5288 fcport->d_id = e->u.new_sess.id; 5289 if (pla) { 5290 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5291 memcpy(fcport->node_name, 5292 pla->iocb.u.isp24.u.plogi.node_name, 5293 WWN_SIZE); 5294 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5295 /* we took an extra ref_count to prevent PLOGI ACK when 5296 * fcport/sess has not been created. 5297 */ 5298 pla->ref_count--; 5299 } 5300 } else { 5301 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5302 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5303 if (fcport) { 5304 fcport->d_id = e->u.new_sess.id; 5305 fcport->flags |= FCF_FABRIC_DEVICE; 5306 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5307 fcport->tgt_short_link_down_cnt = 0; 5308 5309 memcpy(fcport->port_name, e->u.new_sess.port_name, 5310 WWN_SIZE); 5311 5312 fcport->fc4_type = e->u.new_sess.fc4_type; 5313 if (NVME_PRIORITY(vha->hw, fcport)) 5314 fcport->do_prli_nvme = 1; 5315 else 5316 fcport->do_prli_nvme = 0; 5317 5318 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5319 fcport->dm_login_expire = jiffies + 5320 QLA_N2N_WAIT_TIME * HZ; 5321 fcport->fc4_type = FS_FC4TYPE_FCP; 5322 fcport->n2n_flag = 1; 5323 if (vha->flags.nvme_enabled) 5324 fcport->fc4_type |= FS_FC4TYPE_NVME; 5325 } 5326 5327 } else { 5328 ql_dbg(ql_dbg_disc, vha, 0xffff, 5329 "%s %8phC mem alloc fail.\n", 5330 __func__, e->u.new_sess.port_name); 5331 5332 if (pla) { 5333 list_del(&pla->list); 5334 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5335 } 5336 return; 5337 } 5338 5339 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5340 /* search again to make sure no one else got ahead */ 5341 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5342 e->u.new_sess.port_name, 1); 5343 if (tfcp) { 5344 /* should rarily happen */ 5345 ql_dbg(ql_dbg_disc, vha, 0xffff, 5346 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5347 __func__, tfcp->port_name, tfcp->disc_state, 5348 tfcp->fw_login_state); 5349 5350 free_fcport = 1; 5351 } else { 5352 list_add_tail(&fcport->list, &vha->vp_fcports); 5353 5354 } 5355 if (pla) { 5356 qlt_plogi_ack_link(vha, pla, fcport, 5357 QLT_PLOGI_LINK_SAME_WWN); 5358 pla->ref_count--; 5359 } 5360 } 5361 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5362 5363 if (fcport) { 5364 fcport->id_changed = 1; 5365 fcport->scan_state = QLA_FCPORT_FOUND; 5366 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5367 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5368 5369 if (pla) { 5370 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5371 u16 wd3_lo; 5372 5373 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5374 fcport->local = 0; 5375 fcport->loop_id = 5376 le16_to_cpu( 5377 pla->iocb.u.isp24.nport_handle); 5378 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5379 wd3_lo = 5380 le16_to_cpu( 5381 pla->iocb.u.isp24.u.prli.wd3_lo); 5382 5383 if (wd3_lo & BIT_7) 5384 fcport->conf_compl_supported = 1; 5385 5386 if ((wd3_lo & BIT_4) == 0) 5387 fcport->port_type = FCT_INITIATOR; 5388 else 5389 fcport->port_type = FCT_TARGET; 5390 } 5391 qlt_plogi_ack_unref(vha, pla); 5392 } else { 5393 fc_port_t *dfcp = NULL; 5394 5395 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5396 tfcp = qla2x00_find_fcport_by_nportid(vha, 5397 &e->u.new_sess.id, 1); 5398 if (tfcp && (tfcp != fcport)) { 5399 /* 5400 * We have a conflict fcport with same NportID. 5401 */ 5402 ql_dbg(ql_dbg_disc, vha, 0xffff, 5403 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5404 __func__, tfcp->port_name, tfcp->disc_state, 5405 tfcp->fw_login_state); 5406 5407 switch (tfcp->disc_state) { 5408 case DSC_DELETED: 5409 break; 5410 case DSC_DELETE_PEND: 5411 fcport->login_pause = 1; 5412 tfcp->conflict = fcport; 5413 break; 5414 default: 5415 fcport->login_pause = 1; 5416 tfcp->conflict = fcport; 5417 dfcp = tfcp; 5418 break; 5419 } 5420 } 5421 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5422 if (dfcp) 5423 qlt_schedule_sess_for_deletion(tfcp); 5424 5425 if (N2N_TOPO(vha->hw)) { 5426 fcport->flags &= ~FCF_FABRIC_DEVICE; 5427 fcport->keep_nport_handle = 1; 5428 if (vha->flags.nvme_enabled) { 5429 fcport->fc4_type = 5430 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5431 fcport->n2n_flag = 1; 5432 } 5433 fcport->fw_login_state = 0; 5434 5435 schedule_delayed_work(&vha->scan.scan_work, 5); 5436 } else { 5437 qla24xx_fcport_handle_login(vha, fcport); 5438 } 5439 } 5440 } 5441 5442 if (free_fcport) { 5443 qla2x00_free_fcport(fcport); 5444 if (pla) { 5445 list_del(&pla->list); 5446 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5447 } 5448 } 5449 } 5450 5451 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5452 { 5453 struct srb *sp = e->u.iosb.sp; 5454 int rval; 5455 5456 rval = qla2x00_start_sp(sp); 5457 if (rval != QLA_SUCCESS) { 5458 ql_dbg(ql_dbg_disc, vha, 0x2043, 5459 "%s: %s: Re-issue IOCB failed (%d).\n", 5460 __func__, sp->name, rval); 5461 qla24xx_sp_unmap(vha, sp); 5462 } 5463 } 5464 5465 void 5466 qla2x00_do_work(struct scsi_qla_host *vha) 5467 { 5468 struct qla_work_evt *e, *tmp; 5469 unsigned long flags; 5470 LIST_HEAD(work); 5471 int rc; 5472 5473 spin_lock_irqsave(&vha->work_lock, flags); 5474 list_splice_init(&vha->work_list, &work); 5475 spin_unlock_irqrestore(&vha->work_lock, flags); 5476 5477 list_for_each_entry_safe(e, tmp, &work, list) { 5478 rc = QLA_SUCCESS; 5479 switch (e->type) { 5480 case QLA_EVT_AEN: 5481 fc_host_post_event(vha->host, fc_get_event_number(), 5482 e->u.aen.code, e->u.aen.data); 5483 break; 5484 case QLA_EVT_IDC_ACK: 5485 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5486 break; 5487 case QLA_EVT_ASYNC_LOGIN: 5488 qla2x00_async_login(vha, e->u.logio.fcport, 5489 e->u.logio.data); 5490 break; 5491 case QLA_EVT_ASYNC_LOGOUT: 5492 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5493 break; 5494 case QLA_EVT_ASYNC_ADISC: 5495 qla2x00_async_adisc(vha, e->u.logio.fcport, 5496 e->u.logio.data); 5497 break; 5498 case QLA_EVT_UEVENT: 5499 qla2x00_uevent_emit(vha, e->u.uevent.code); 5500 break; 5501 case QLA_EVT_AENFX: 5502 qlafx00_process_aen(vha, e); 5503 break; 5504 case QLA_EVT_UNMAP: 5505 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5506 break; 5507 case QLA_EVT_RELOGIN: 5508 qla2x00_relogin(vha); 5509 break; 5510 case QLA_EVT_NEW_SESS: 5511 qla24xx_create_new_sess(vha, e); 5512 break; 5513 case QLA_EVT_GPDB: 5514 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5515 e->u.fcport.opt); 5516 break; 5517 case QLA_EVT_PRLI: 5518 qla24xx_async_prli(vha, e->u.fcport.fcport); 5519 break; 5520 case QLA_EVT_GPSC: 5521 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5522 break; 5523 case QLA_EVT_GNL: 5524 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5525 break; 5526 case QLA_EVT_NACK: 5527 qla24xx_do_nack_work(vha, e); 5528 break; 5529 case QLA_EVT_ASYNC_PRLO: 5530 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5531 break; 5532 case QLA_EVT_ASYNC_PRLO_DONE: 5533 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5534 e->u.logio.data); 5535 break; 5536 case QLA_EVT_GPNFT: 5537 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5538 e->u.gpnft.sp); 5539 break; 5540 case QLA_EVT_GPNFT_DONE: 5541 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5542 break; 5543 case QLA_EVT_GNNFT_DONE: 5544 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5545 break; 5546 case QLA_EVT_GFPNID: 5547 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5548 break; 5549 case QLA_EVT_SP_RETRY: 5550 qla_sp_retry(vha, e); 5551 break; 5552 case QLA_EVT_IIDMA: 5553 qla_do_iidma_work(vha, e->u.fcport.fcport); 5554 break; 5555 case QLA_EVT_ELS_PLOGI: 5556 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5557 e->u.fcport.fcport, false); 5558 break; 5559 case QLA_EVT_SA_REPLACE: 5560 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5561 break; 5562 } 5563 5564 if (rc == EAGAIN) { 5565 /* put 'work' at head of 'vha->work_list' */ 5566 spin_lock_irqsave(&vha->work_lock, flags); 5567 list_splice(&work, &vha->work_list); 5568 spin_unlock_irqrestore(&vha->work_lock, flags); 5569 break; 5570 } 5571 list_del_init(&e->list); 5572 if (e->flags & QLA_EVT_FLAG_FREE) 5573 kfree(e); 5574 5575 /* For each work completed decrement vha ref count */ 5576 QLA_VHA_MARK_NOT_BUSY(vha); 5577 } 5578 } 5579 5580 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5581 { 5582 struct qla_work_evt *e; 5583 5584 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5585 5586 if (!e) { 5587 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5588 return QLA_FUNCTION_FAILED; 5589 } 5590 5591 return qla2x00_post_work(vha, e); 5592 } 5593 5594 /* Relogins all the fcports of a vport 5595 * Context: dpc thread 5596 */ 5597 void qla2x00_relogin(struct scsi_qla_host *vha) 5598 { 5599 fc_port_t *fcport; 5600 int status, relogin_needed = 0; 5601 struct event_arg ea; 5602 5603 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5604 /* 5605 * If the port is not ONLINE then try to login 5606 * to it if we haven't run out of retries. 5607 */ 5608 if (atomic_read(&fcport->state) != FCS_ONLINE && 5609 fcport->login_retry) { 5610 if (fcport->scan_state != QLA_FCPORT_FOUND || 5611 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5612 fcport->disc_state == DSC_LOGIN_COMPLETE) 5613 continue; 5614 5615 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5616 fcport->disc_state == DSC_DELETE_PEND) { 5617 relogin_needed = 1; 5618 } else { 5619 if (vha->hw->current_topology != ISP_CFG_NL) { 5620 memset(&ea, 0, sizeof(ea)); 5621 ea.fcport = fcport; 5622 qla24xx_handle_relogin_event(vha, &ea); 5623 } else if (vha->hw->current_topology == 5624 ISP_CFG_NL && 5625 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5626 (void)qla24xx_fcport_handle_login(vha, 5627 fcport); 5628 } else if (vha->hw->current_topology == 5629 ISP_CFG_NL) { 5630 fcport->login_retry--; 5631 status = 5632 qla2x00_local_device_login(vha, 5633 fcport); 5634 if (status == QLA_SUCCESS) { 5635 fcport->old_loop_id = 5636 fcport->loop_id; 5637 ql_dbg(ql_dbg_disc, vha, 0x2003, 5638 "Port login OK: logged in ID 0x%x.\n", 5639 fcport->loop_id); 5640 qla2x00_update_fcport 5641 (vha, fcport); 5642 } else if (status == 1) { 5643 set_bit(RELOGIN_NEEDED, 5644 &vha->dpc_flags); 5645 /* retry the login again */ 5646 ql_dbg(ql_dbg_disc, vha, 0x2007, 5647 "Retrying %d login again loop_id 0x%x.\n", 5648 fcport->login_retry, 5649 fcport->loop_id); 5650 } else { 5651 fcport->login_retry = 0; 5652 } 5653 5654 if (fcport->login_retry == 0 && 5655 status != QLA_SUCCESS) 5656 qla2x00_clear_loop_id(fcport); 5657 } 5658 } 5659 } 5660 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5661 break; 5662 } 5663 5664 if (relogin_needed) 5665 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5666 5667 ql_dbg(ql_dbg_disc, vha, 0x400e, 5668 "Relogin end.\n"); 5669 } 5670 5671 /* Schedule work on any of the dpc-workqueues */ 5672 void 5673 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5674 { 5675 struct qla_hw_data *ha = base_vha->hw; 5676 5677 switch (work_code) { 5678 case MBA_IDC_AEN: /* 0x8200 */ 5679 if (ha->dpc_lp_wq) 5680 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5681 break; 5682 5683 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5684 if (!ha->flags.nic_core_reset_hdlr_active) { 5685 if (ha->dpc_hp_wq) 5686 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5687 } else 5688 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5689 "NIC Core reset is already active. Skip " 5690 "scheduling it again.\n"); 5691 break; 5692 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5693 if (ha->dpc_hp_wq) 5694 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5695 break; 5696 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5697 if (ha->dpc_hp_wq) 5698 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5699 break; 5700 default: 5701 ql_log(ql_log_warn, base_vha, 0xb05f, 5702 "Unknown work-code=0x%x.\n", work_code); 5703 } 5704 5705 return; 5706 } 5707 5708 /* Work: Perform NIC Core Unrecoverable state handling */ 5709 void 5710 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5711 { 5712 struct qla_hw_data *ha = 5713 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5714 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5715 uint32_t dev_state = 0; 5716 5717 qla83xx_idc_lock(base_vha, 0); 5718 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5719 qla83xx_reset_ownership(base_vha); 5720 if (ha->flags.nic_core_reset_owner) { 5721 ha->flags.nic_core_reset_owner = 0; 5722 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5723 QLA8XXX_DEV_FAILED); 5724 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5725 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5726 } 5727 qla83xx_idc_unlock(base_vha, 0); 5728 } 5729 5730 /* Work: Execute IDC state handler */ 5731 void 5732 qla83xx_idc_state_handler_work(struct work_struct *work) 5733 { 5734 struct qla_hw_data *ha = 5735 container_of(work, struct qla_hw_data, idc_state_handler); 5736 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5737 uint32_t dev_state = 0; 5738 5739 qla83xx_idc_lock(base_vha, 0); 5740 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5741 if (dev_state == QLA8XXX_DEV_FAILED || 5742 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5743 qla83xx_idc_state_handler(base_vha); 5744 qla83xx_idc_unlock(base_vha, 0); 5745 } 5746 5747 static int 5748 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5749 { 5750 int rval = QLA_SUCCESS; 5751 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5752 uint32_t heart_beat_counter1, heart_beat_counter2; 5753 5754 do { 5755 if (time_after(jiffies, heart_beat_wait)) { 5756 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5757 "Nic Core f/w is not alive.\n"); 5758 rval = QLA_FUNCTION_FAILED; 5759 break; 5760 } 5761 5762 qla83xx_idc_lock(base_vha, 0); 5763 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5764 &heart_beat_counter1); 5765 qla83xx_idc_unlock(base_vha, 0); 5766 msleep(100); 5767 qla83xx_idc_lock(base_vha, 0); 5768 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5769 &heart_beat_counter2); 5770 qla83xx_idc_unlock(base_vha, 0); 5771 } while (heart_beat_counter1 == heart_beat_counter2); 5772 5773 return rval; 5774 } 5775 5776 /* Work: Perform NIC Core Reset handling */ 5777 void 5778 qla83xx_nic_core_reset_work(struct work_struct *work) 5779 { 5780 struct qla_hw_data *ha = 5781 container_of(work, struct qla_hw_data, nic_core_reset); 5782 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5783 uint32_t dev_state = 0; 5784 5785 if (IS_QLA2031(ha)) { 5786 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5787 ql_log(ql_log_warn, base_vha, 0xb081, 5788 "Failed to dump mctp\n"); 5789 return; 5790 } 5791 5792 if (!ha->flags.nic_core_reset_hdlr_active) { 5793 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5794 qla83xx_idc_lock(base_vha, 0); 5795 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5796 &dev_state); 5797 qla83xx_idc_unlock(base_vha, 0); 5798 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5799 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5800 "Nic Core f/w is alive.\n"); 5801 return; 5802 } 5803 } 5804 5805 ha->flags.nic_core_reset_hdlr_active = 1; 5806 if (qla83xx_nic_core_reset(base_vha)) { 5807 /* NIC Core reset failed. */ 5808 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5809 "NIC Core reset failed.\n"); 5810 } 5811 ha->flags.nic_core_reset_hdlr_active = 0; 5812 } 5813 } 5814 5815 /* Work: Handle 8200 IDC aens */ 5816 void 5817 qla83xx_service_idc_aen(struct work_struct *work) 5818 { 5819 struct qla_hw_data *ha = 5820 container_of(work, struct qla_hw_data, idc_aen); 5821 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5822 uint32_t dev_state, idc_control; 5823 5824 qla83xx_idc_lock(base_vha, 0); 5825 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5826 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5827 qla83xx_idc_unlock(base_vha, 0); 5828 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5829 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5830 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5831 "Application requested NIC Core Reset.\n"); 5832 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5833 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5834 QLA_SUCCESS) { 5835 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5836 "Other protocol driver requested NIC Core Reset.\n"); 5837 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5838 } 5839 } else if (dev_state == QLA8XXX_DEV_FAILED || 5840 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5841 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5842 } 5843 } 5844 5845 /* 5846 * Control the frequency of IDC lock retries 5847 */ 5848 #define QLA83XX_WAIT_LOGIC_MS 100 5849 5850 static int 5851 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5852 { 5853 int rval; 5854 uint32_t data; 5855 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5856 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5857 struct qla_hw_data *ha = base_vha->hw; 5858 5859 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5860 "Trying force recovery of the IDC lock.\n"); 5861 5862 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5863 if (rval) 5864 return rval; 5865 5866 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5867 return QLA_SUCCESS; 5868 } else { 5869 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5870 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5871 data); 5872 if (rval) 5873 return rval; 5874 5875 msleep(200); 5876 5877 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5878 &data); 5879 if (rval) 5880 return rval; 5881 5882 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5883 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5884 ~(idc_lck_rcvry_stage_mask)); 5885 rval = qla83xx_wr_reg(base_vha, 5886 QLA83XX_IDC_LOCK_RECOVERY, data); 5887 if (rval) 5888 return rval; 5889 5890 /* Forcefully perform IDC UnLock */ 5891 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5892 &data); 5893 if (rval) 5894 return rval; 5895 /* Clear lock-id by setting 0xff */ 5896 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5897 0xff); 5898 if (rval) 5899 return rval; 5900 /* Clear lock-recovery by setting 0x0 */ 5901 rval = qla83xx_wr_reg(base_vha, 5902 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5903 if (rval) 5904 return rval; 5905 } else 5906 return QLA_SUCCESS; 5907 } 5908 5909 return rval; 5910 } 5911 5912 static int 5913 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5914 { 5915 int rval = QLA_SUCCESS; 5916 uint32_t o_drv_lockid, n_drv_lockid; 5917 unsigned long lock_recovery_timeout; 5918 5919 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5920 retry_lockid: 5921 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5922 if (rval) 5923 goto exit; 5924 5925 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5926 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5927 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5928 return QLA_SUCCESS; 5929 else 5930 return QLA_FUNCTION_FAILED; 5931 } 5932 5933 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5934 if (rval) 5935 goto exit; 5936 5937 if (o_drv_lockid == n_drv_lockid) { 5938 msleep(QLA83XX_WAIT_LOGIC_MS); 5939 goto retry_lockid; 5940 } else 5941 return QLA_SUCCESS; 5942 5943 exit: 5944 return rval; 5945 } 5946 5947 /* 5948 * Context: task, can sleep 5949 */ 5950 void 5951 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5952 { 5953 uint32_t data; 5954 uint32_t lock_owner; 5955 struct qla_hw_data *ha = base_vha->hw; 5956 5957 might_sleep(); 5958 5959 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5960 retry_lock: 5961 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5962 == QLA_SUCCESS) { 5963 if (data) { 5964 /* Setting lock-id to our function-number */ 5965 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5966 ha->portnum); 5967 } else { 5968 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5969 &lock_owner); 5970 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5971 "Failed to acquire IDC lock, acquired by %d, " 5972 "retrying...\n", lock_owner); 5973 5974 /* Retry/Perform IDC-Lock recovery */ 5975 if (qla83xx_idc_lock_recovery(base_vha) 5976 == QLA_SUCCESS) { 5977 msleep(QLA83XX_WAIT_LOGIC_MS); 5978 goto retry_lock; 5979 } else 5980 ql_log(ql_log_warn, base_vha, 0xb075, 5981 "IDC Lock recovery FAILED.\n"); 5982 } 5983 5984 } 5985 5986 return; 5987 } 5988 5989 static bool 5990 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5991 struct purex_entry_24xx *purex) 5992 { 5993 char fwstr[16]; 5994 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5995 struct port_database_24xx *pdb; 5996 5997 /* Domain Controller is always logged-out. */ 5998 /* if RDP request is not from Domain Controller: */ 5999 if (sid != 0xfffc01) 6000 return false; 6001 6002 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 6003 6004 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6005 if (!pdb) { 6006 ql_dbg(ql_dbg_init, vha, 0x0181, 6007 "%s: Failed allocate pdb\n", __func__); 6008 } else if (qla24xx_get_port_database(vha, 6009 le16_to_cpu(purex->nport_handle), pdb)) { 6010 ql_dbg(ql_dbg_init, vha, 0x0181, 6011 "%s: Failed get pdb sid=%x\n", __func__, sid); 6012 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6013 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6014 ql_dbg(ql_dbg_init, vha, 0x0181, 6015 "%s: Port not logged in sid=%#x\n", __func__, sid); 6016 } else { 6017 /* RDP request is from logged in port */ 6018 kfree(pdb); 6019 return false; 6020 } 6021 kfree(pdb); 6022 6023 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6024 fwstr[strcspn(fwstr, " ")] = 0; 6025 /* if FW version allows RDP response length upto 2048 bytes: */ 6026 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6027 return false; 6028 6029 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6030 6031 /* RDP response length is to be reduced to maximum 256 bytes */ 6032 return true; 6033 } 6034 6035 /* 6036 * Function Name: qla24xx_process_purex_iocb 6037 * 6038 * Description: 6039 * Prepare a RDP response and send to Fabric switch 6040 * 6041 * PARAMETERS: 6042 * vha: SCSI qla host 6043 * purex: RDP request received by HBA 6044 */ 6045 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6046 struct purex_item *item) 6047 { 6048 struct qla_hw_data *ha = vha->hw; 6049 struct purex_entry_24xx *purex = 6050 (struct purex_entry_24xx *)&item->iocb; 6051 dma_addr_t rsp_els_dma; 6052 dma_addr_t rsp_payload_dma; 6053 dma_addr_t stat_dma; 6054 dma_addr_t sfp_dma; 6055 struct els_entry_24xx *rsp_els = NULL; 6056 struct rdp_rsp_payload *rsp_payload = NULL; 6057 struct link_statistics *stat = NULL; 6058 uint8_t *sfp = NULL; 6059 uint16_t sfp_flags = 0; 6060 uint rsp_payload_length = sizeof(*rsp_payload); 6061 int rval; 6062 6063 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6064 "%s: Enter\n", __func__); 6065 6066 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6067 "-------- ELS REQ -------\n"); 6068 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6069 purex, sizeof(*purex)); 6070 6071 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6072 rsp_payload_length = 6073 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6074 ql_dbg(ql_dbg_init, vha, 0x0181, 6075 "Reducing RSP payload length to %u bytes...\n", 6076 rsp_payload_length); 6077 } 6078 6079 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6080 &rsp_els_dma, GFP_KERNEL); 6081 if (!rsp_els) { 6082 ql_log(ql_log_warn, vha, 0x0183, 6083 "Failed allocate dma buffer ELS RSP.\n"); 6084 goto dealloc; 6085 } 6086 6087 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6088 &rsp_payload_dma, GFP_KERNEL); 6089 if (!rsp_payload) { 6090 ql_log(ql_log_warn, vha, 0x0184, 6091 "Failed allocate dma buffer ELS RSP payload.\n"); 6092 goto dealloc; 6093 } 6094 6095 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6096 &sfp_dma, GFP_KERNEL); 6097 6098 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6099 &stat_dma, GFP_KERNEL); 6100 6101 /* Prepare Response IOCB */ 6102 rsp_els->entry_type = ELS_IOCB_TYPE; 6103 rsp_els->entry_count = 1; 6104 rsp_els->sys_define = 0; 6105 rsp_els->entry_status = 0; 6106 rsp_els->handle = 0; 6107 rsp_els->nport_handle = purex->nport_handle; 6108 rsp_els->tx_dsd_count = cpu_to_le16(1); 6109 rsp_els->vp_index = purex->vp_idx; 6110 rsp_els->sof_type = EST_SOFI3; 6111 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6112 rsp_els->rx_dsd_count = 0; 6113 rsp_els->opcode = purex->els_frame_payload[0]; 6114 6115 rsp_els->d_id[0] = purex->s_id[0]; 6116 rsp_els->d_id[1] = purex->s_id[1]; 6117 rsp_els->d_id[2] = purex->s_id[2]; 6118 6119 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6120 rsp_els->rx_byte_count = 0; 6121 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6122 6123 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6124 rsp_els->tx_len = rsp_els->tx_byte_count; 6125 6126 rsp_els->rx_address = 0; 6127 rsp_els->rx_len = 0; 6128 6129 /* Prepare Response Payload */ 6130 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6131 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6132 sizeof(rsp_payload->hdr)); 6133 6134 /* Link service Request Info Descriptor */ 6135 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6136 rsp_payload->ls_req_info_desc.desc_len = 6137 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6138 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6139 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6140 6141 /* Link service Request Info Descriptor 2 */ 6142 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6143 rsp_payload->ls_req_info_desc2.desc_len = 6144 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6145 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6146 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6147 6148 6149 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6150 rsp_payload->sfp_diag_desc.desc_len = 6151 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6152 6153 if (sfp) { 6154 /* SFP Flags */ 6155 memset(sfp, 0, SFP_RTDI_LEN); 6156 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6157 if (!rval) { 6158 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6159 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6160 sfp_flags |= BIT_0; /* short wave */ 6161 else if (sfp[0] & BIT_1) 6162 sfp_flags |= BIT_1; /* long wave 1310nm */ 6163 else if (sfp[1] & BIT_4) 6164 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6165 } 6166 6167 /* SFP Type */ 6168 memset(sfp, 0, SFP_RTDI_LEN); 6169 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6170 if (!rval) { 6171 sfp_flags |= BIT_4; /* optical */ 6172 if (sfp[0] == 0x3) 6173 sfp_flags |= BIT_6; /* sfp+ */ 6174 } 6175 6176 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6177 6178 /* SFP Diagnostics */ 6179 memset(sfp, 0, SFP_RTDI_LEN); 6180 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6181 if (!rval) { 6182 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6183 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6184 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6185 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6186 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6187 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6188 } 6189 } 6190 6191 /* Port Speed Descriptor */ 6192 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6193 rsp_payload->port_speed_desc.desc_len = 6194 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6195 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6196 qla25xx_fdmi_port_speed_capability(ha)); 6197 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6198 qla25xx_fdmi_port_speed_currently(ha)); 6199 6200 /* Link Error Status Descriptor */ 6201 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6202 rsp_payload->ls_err_desc.desc_len = 6203 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6204 6205 if (stat) { 6206 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6207 if (!rval) { 6208 rsp_payload->ls_err_desc.link_fail_cnt = 6209 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6210 rsp_payload->ls_err_desc.loss_sync_cnt = 6211 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6212 rsp_payload->ls_err_desc.loss_sig_cnt = 6213 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6214 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6215 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6216 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6217 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6218 rsp_payload->ls_err_desc.inval_crc_cnt = 6219 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6220 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6221 } 6222 } 6223 6224 /* Portname Descriptor */ 6225 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6226 rsp_payload->port_name_diag_desc.desc_len = 6227 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6228 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6229 vha->node_name, 6230 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6231 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6232 vha->port_name, 6233 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6234 6235 /* F-Port Portname Descriptor */ 6236 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6237 rsp_payload->port_name_direct_desc.desc_len = 6238 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6239 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6240 vha->fabric_node_name, 6241 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6242 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6243 vha->fabric_port_name, 6244 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6245 6246 /* Bufer Credit Descriptor */ 6247 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6248 rsp_payload->buffer_credit_desc.desc_len = 6249 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6250 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6251 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6252 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6253 6254 if (ha->flags.plogi_template_valid) { 6255 uint32_t tmp = 6256 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6257 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6258 } 6259 6260 if (rsp_payload_length < sizeof(*rsp_payload)) 6261 goto send; 6262 6263 /* Optical Element Descriptor, Temperature */ 6264 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6265 rsp_payload->optical_elmt_desc[0].desc_len = 6266 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6267 /* Optical Element Descriptor, Voltage */ 6268 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6269 rsp_payload->optical_elmt_desc[1].desc_len = 6270 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6271 /* Optical Element Descriptor, Tx Bias Current */ 6272 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6273 rsp_payload->optical_elmt_desc[2].desc_len = 6274 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6275 /* Optical Element Descriptor, Tx Power */ 6276 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6277 rsp_payload->optical_elmt_desc[3].desc_len = 6278 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6279 /* Optical Element Descriptor, Rx Power */ 6280 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6281 rsp_payload->optical_elmt_desc[4].desc_len = 6282 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6283 6284 if (sfp) { 6285 memset(sfp, 0, SFP_RTDI_LEN); 6286 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6287 if (!rval) { 6288 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6289 6290 /* Optical Element Descriptor, Temperature */ 6291 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6292 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6293 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6294 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6295 rsp_payload->optical_elmt_desc[0].element_flags = 6296 cpu_to_be32(1 << 28); 6297 6298 /* Optical Element Descriptor, Voltage */ 6299 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6300 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6301 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6302 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6303 rsp_payload->optical_elmt_desc[1].element_flags = 6304 cpu_to_be32(2 << 28); 6305 6306 /* Optical Element Descriptor, Tx Bias Current */ 6307 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6308 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6309 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6310 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6311 rsp_payload->optical_elmt_desc[2].element_flags = 6312 cpu_to_be32(3 << 28); 6313 6314 /* Optical Element Descriptor, Tx Power */ 6315 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6316 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6317 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6318 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6319 rsp_payload->optical_elmt_desc[3].element_flags = 6320 cpu_to_be32(4 << 28); 6321 6322 /* Optical Element Descriptor, Rx Power */ 6323 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6324 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6325 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6326 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6327 rsp_payload->optical_elmt_desc[4].element_flags = 6328 cpu_to_be32(5 << 28); 6329 } 6330 6331 memset(sfp, 0, SFP_RTDI_LEN); 6332 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6333 if (!rval) { 6334 /* Temperature high/low alarm/warning */ 6335 rsp_payload->optical_elmt_desc[0].element_flags |= 6336 cpu_to_be32( 6337 (sfp[0] >> 7 & 1) << 3 | 6338 (sfp[0] >> 6 & 1) << 2 | 6339 (sfp[4] >> 7 & 1) << 1 | 6340 (sfp[4] >> 6 & 1) << 0); 6341 6342 /* Voltage high/low alarm/warning */ 6343 rsp_payload->optical_elmt_desc[1].element_flags |= 6344 cpu_to_be32( 6345 (sfp[0] >> 5 & 1) << 3 | 6346 (sfp[0] >> 4 & 1) << 2 | 6347 (sfp[4] >> 5 & 1) << 1 | 6348 (sfp[4] >> 4 & 1) << 0); 6349 6350 /* Tx Bias Current high/low alarm/warning */ 6351 rsp_payload->optical_elmt_desc[2].element_flags |= 6352 cpu_to_be32( 6353 (sfp[0] >> 3 & 1) << 3 | 6354 (sfp[0] >> 2 & 1) << 2 | 6355 (sfp[4] >> 3 & 1) << 1 | 6356 (sfp[4] >> 2 & 1) << 0); 6357 6358 /* Tx Power high/low alarm/warning */ 6359 rsp_payload->optical_elmt_desc[3].element_flags |= 6360 cpu_to_be32( 6361 (sfp[0] >> 1 & 1) << 3 | 6362 (sfp[0] >> 0 & 1) << 2 | 6363 (sfp[4] >> 1 & 1) << 1 | 6364 (sfp[4] >> 0 & 1) << 0); 6365 6366 /* Rx Power high/low alarm/warning */ 6367 rsp_payload->optical_elmt_desc[4].element_flags |= 6368 cpu_to_be32( 6369 (sfp[1] >> 7 & 1) << 3 | 6370 (sfp[1] >> 6 & 1) << 2 | 6371 (sfp[5] >> 7 & 1) << 1 | 6372 (sfp[5] >> 6 & 1) << 0); 6373 } 6374 } 6375 6376 /* Optical Product Data Descriptor */ 6377 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6378 rsp_payload->optical_prod_desc.desc_len = 6379 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6380 6381 if (sfp) { 6382 memset(sfp, 0, SFP_RTDI_LEN); 6383 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6384 if (!rval) { 6385 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6386 sfp + 0, 6387 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6388 memcpy(rsp_payload->optical_prod_desc.part_number, 6389 sfp + 20, 6390 sizeof(rsp_payload->optical_prod_desc.part_number)); 6391 memcpy(rsp_payload->optical_prod_desc.revision, 6392 sfp + 36, 6393 sizeof(rsp_payload->optical_prod_desc.revision)); 6394 memcpy(rsp_payload->optical_prod_desc.serial_number, 6395 sfp + 48, 6396 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6397 } 6398 6399 memset(sfp, 0, SFP_RTDI_LEN); 6400 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6401 if (!rval) { 6402 memcpy(rsp_payload->optical_prod_desc.date, 6403 sfp + 0, 6404 sizeof(rsp_payload->optical_prod_desc.date)); 6405 } 6406 } 6407 6408 send: 6409 ql_dbg(ql_dbg_init, vha, 0x0183, 6410 "Sending ELS Response to RDP Request...\n"); 6411 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6412 "-------- ELS RSP -------\n"); 6413 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6414 rsp_els, sizeof(*rsp_els)); 6415 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6416 "-------- ELS RSP PAYLOAD -------\n"); 6417 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6418 rsp_payload, rsp_payload_length); 6419 6420 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6421 6422 if (rval) { 6423 ql_log(ql_log_warn, vha, 0x0188, 6424 "%s: iocb failed to execute -> %x\n", __func__, rval); 6425 } else if (rsp_els->comp_status) { 6426 ql_log(ql_log_warn, vha, 0x0189, 6427 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6428 __func__, rsp_els->comp_status, 6429 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6430 } else { 6431 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6432 } 6433 6434 dealloc: 6435 if (stat) 6436 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6437 stat, stat_dma); 6438 if (sfp) 6439 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6440 sfp, sfp_dma); 6441 if (rsp_payload) 6442 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6443 rsp_payload, rsp_payload_dma); 6444 if (rsp_els) 6445 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6446 rsp_els, rsp_els_dma); 6447 } 6448 6449 void 6450 qla24xx_free_purex_item(struct purex_item *item) 6451 { 6452 if (item == &item->vha->default_item) 6453 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6454 else 6455 kfree(item); 6456 } 6457 6458 void qla24xx_process_purex_list(struct purex_list *list) 6459 { 6460 struct list_head head = LIST_HEAD_INIT(head); 6461 struct purex_item *item, *next; 6462 ulong flags; 6463 6464 spin_lock_irqsave(&list->lock, flags); 6465 list_splice_init(&list->head, &head); 6466 spin_unlock_irqrestore(&list->lock, flags); 6467 6468 list_for_each_entry_safe(item, next, &head, list) { 6469 list_del(&item->list); 6470 item->process_item(item->vha, item); 6471 qla24xx_free_purex_item(item); 6472 } 6473 } 6474 6475 /* 6476 * Context: task, can sleep 6477 */ 6478 void 6479 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6480 { 6481 #if 0 6482 uint16_t options = (requester_id << 15) | BIT_7; 6483 #endif 6484 uint16_t retry; 6485 uint32_t data; 6486 struct qla_hw_data *ha = base_vha->hw; 6487 6488 might_sleep(); 6489 6490 /* IDC-unlock implementation using driver-unlock/lock-id 6491 * remote registers 6492 */ 6493 retry = 0; 6494 retry_unlock: 6495 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6496 == QLA_SUCCESS) { 6497 if (data == ha->portnum) { 6498 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6499 /* Clearing lock-id by setting 0xff */ 6500 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6501 } else if (retry < 10) { 6502 /* SV: XXX: IDC unlock retrying needed here? */ 6503 6504 /* Retry for IDC-unlock */ 6505 msleep(QLA83XX_WAIT_LOGIC_MS); 6506 retry++; 6507 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6508 "Failed to release IDC lock, retrying=%d\n", retry); 6509 goto retry_unlock; 6510 } 6511 } else if (retry < 10) { 6512 /* Retry for IDC-unlock */ 6513 msleep(QLA83XX_WAIT_LOGIC_MS); 6514 retry++; 6515 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6516 "Failed to read drv-lockid, retrying=%d\n", retry); 6517 goto retry_unlock; 6518 } 6519 6520 return; 6521 6522 #if 0 6523 /* XXX: IDC-unlock implementation using access-control mbx */ 6524 retry = 0; 6525 retry_unlock2: 6526 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6527 if (retry < 10) { 6528 /* Retry for IDC-unlock */ 6529 msleep(QLA83XX_WAIT_LOGIC_MS); 6530 retry++; 6531 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6532 "Failed to release IDC lock, retrying=%d\n", retry); 6533 goto retry_unlock2; 6534 } 6535 } 6536 6537 return; 6538 #endif 6539 } 6540 6541 int 6542 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6543 { 6544 int rval = QLA_SUCCESS; 6545 struct qla_hw_data *ha = vha->hw; 6546 uint32_t drv_presence; 6547 6548 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6549 if (rval == QLA_SUCCESS) { 6550 drv_presence |= (1 << ha->portnum); 6551 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6552 drv_presence); 6553 } 6554 6555 return rval; 6556 } 6557 6558 int 6559 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6560 { 6561 int rval = QLA_SUCCESS; 6562 6563 qla83xx_idc_lock(vha, 0); 6564 rval = __qla83xx_set_drv_presence(vha); 6565 qla83xx_idc_unlock(vha, 0); 6566 6567 return rval; 6568 } 6569 6570 int 6571 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6572 { 6573 int rval = QLA_SUCCESS; 6574 struct qla_hw_data *ha = vha->hw; 6575 uint32_t drv_presence; 6576 6577 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6578 if (rval == QLA_SUCCESS) { 6579 drv_presence &= ~(1 << ha->portnum); 6580 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6581 drv_presence); 6582 } 6583 6584 return rval; 6585 } 6586 6587 int 6588 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6589 { 6590 int rval = QLA_SUCCESS; 6591 6592 qla83xx_idc_lock(vha, 0); 6593 rval = __qla83xx_clear_drv_presence(vha); 6594 qla83xx_idc_unlock(vha, 0); 6595 6596 return rval; 6597 } 6598 6599 static void 6600 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6601 { 6602 struct qla_hw_data *ha = vha->hw; 6603 uint32_t drv_ack, drv_presence; 6604 unsigned long ack_timeout; 6605 6606 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6607 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6608 while (1) { 6609 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6610 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6611 if ((drv_ack & drv_presence) == drv_presence) 6612 break; 6613 6614 if (time_after_eq(jiffies, ack_timeout)) { 6615 ql_log(ql_log_warn, vha, 0xb067, 6616 "RESET ACK TIMEOUT! drv_presence=0x%x " 6617 "drv_ack=0x%x\n", drv_presence, drv_ack); 6618 /* 6619 * The function(s) which did not ack in time are forced 6620 * to withdraw any further participation in the IDC 6621 * reset. 6622 */ 6623 if (drv_ack != drv_presence) 6624 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6625 drv_ack); 6626 break; 6627 } 6628 6629 qla83xx_idc_unlock(vha, 0); 6630 msleep(1000); 6631 qla83xx_idc_lock(vha, 0); 6632 } 6633 6634 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6635 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6636 } 6637 6638 static int 6639 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6640 { 6641 int rval = QLA_SUCCESS; 6642 uint32_t idc_control; 6643 6644 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6645 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6646 6647 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6648 __qla83xx_get_idc_control(vha, &idc_control); 6649 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6650 __qla83xx_set_idc_control(vha, 0); 6651 6652 qla83xx_idc_unlock(vha, 0); 6653 rval = qla83xx_restart_nic_firmware(vha); 6654 qla83xx_idc_lock(vha, 0); 6655 6656 if (rval != QLA_SUCCESS) { 6657 ql_log(ql_log_fatal, vha, 0xb06a, 6658 "Failed to restart NIC f/w.\n"); 6659 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6660 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6661 } else { 6662 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6663 "Success in restarting nic f/w.\n"); 6664 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6665 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6666 } 6667 6668 return rval; 6669 } 6670 6671 /* Assumes idc_lock always held on entry */ 6672 int 6673 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6674 { 6675 struct qla_hw_data *ha = base_vha->hw; 6676 int rval = QLA_SUCCESS; 6677 unsigned long dev_init_timeout; 6678 uint32_t dev_state; 6679 6680 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6681 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6682 6683 while (1) { 6684 6685 if (time_after_eq(jiffies, dev_init_timeout)) { 6686 ql_log(ql_log_warn, base_vha, 0xb06e, 6687 "Initialization TIMEOUT!\n"); 6688 /* Init timeout. Disable further NIC Core 6689 * communication. 6690 */ 6691 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6692 QLA8XXX_DEV_FAILED); 6693 ql_log(ql_log_info, base_vha, 0xb06f, 6694 "HW State: FAILED.\n"); 6695 } 6696 6697 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6698 switch (dev_state) { 6699 case QLA8XXX_DEV_READY: 6700 if (ha->flags.nic_core_reset_owner) 6701 qla83xx_idc_audit(base_vha, 6702 IDC_AUDIT_COMPLETION); 6703 ha->flags.nic_core_reset_owner = 0; 6704 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6705 "Reset_owner reset by 0x%x.\n", 6706 ha->portnum); 6707 goto exit; 6708 case QLA8XXX_DEV_COLD: 6709 if (ha->flags.nic_core_reset_owner) 6710 rval = qla83xx_device_bootstrap(base_vha); 6711 else { 6712 /* Wait for AEN to change device-state */ 6713 qla83xx_idc_unlock(base_vha, 0); 6714 msleep(1000); 6715 qla83xx_idc_lock(base_vha, 0); 6716 } 6717 break; 6718 case QLA8XXX_DEV_INITIALIZING: 6719 /* Wait for AEN to change device-state */ 6720 qla83xx_idc_unlock(base_vha, 0); 6721 msleep(1000); 6722 qla83xx_idc_lock(base_vha, 0); 6723 break; 6724 case QLA8XXX_DEV_NEED_RESET: 6725 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6726 qla83xx_need_reset_handler(base_vha); 6727 else { 6728 /* Wait for AEN to change device-state */ 6729 qla83xx_idc_unlock(base_vha, 0); 6730 msleep(1000); 6731 qla83xx_idc_lock(base_vha, 0); 6732 } 6733 /* reset timeout value after need reset handler */ 6734 dev_init_timeout = jiffies + 6735 (ha->fcoe_dev_init_timeout * HZ); 6736 break; 6737 case QLA8XXX_DEV_NEED_QUIESCENT: 6738 /* XXX: DEBUG for now */ 6739 qla83xx_idc_unlock(base_vha, 0); 6740 msleep(1000); 6741 qla83xx_idc_lock(base_vha, 0); 6742 break; 6743 case QLA8XXX_DEV_QUIESCENT: 6744 /* XXX: DEBUG for now */ 6745 if (ha->flags.quiesce_owner) 6746 goto exit; 6747 6748 qla83xx_idc_unlock(base_vha, 0); 6749 msleep(1000); 6750 qla83xx_idc_lock(base_vha, 0); 6751 dev_init_timeout = jiffies + 6752 (ha->fcoe_dev_init_timeout * HZ); 6753 break; 6754 case QLA8XXX_DEV_FAILED: 6755 if (ha->flags.nic_core_reset_owner) 6756 qla83xx_idc_audit(base_vha, 6757 IDC_AUDIT_COMPLETION); 6758 ha->flags.nic_core_reset_owner = 0; 6759 __qla83xx_clear_drv_presence(base_vha); 6760 qla83xx_idc_unlock(base_vha, 0); 6761 qla8xxx_dev_failed_handler(base_vha); 6762 rval = QLA_FUNCTION_FAILED; 6763 qla83xx_idc_lock(base_vha, 0); 6764 goto exit; 6765 case QLA8XXX_BAD_VALUE: 6766 qla83xx_idc_unlock(base_vha, 0); 6767 msleep(1000); 6768 qla83xx_idc_lock(base_vha, 0); 6769 break; 6770 default: 6771 ql_log(ql_log_warn, base_vha, 0xb071, 6772 "Unknown Device State: %x.\n", dev_state); 6773 qla83xx_idc_unlock(base_vha, 0); 6774 qla8xxx_dev_failed_handler(base_vha); 6775 rval = QLA_FUNCTION_FAILED; 6776 qla83xx_idc_lock(base_vha, 0); 6777 goto exit; 6778 } 6779 } 6780 6781 exit: 6782 return rval; 6783 } 6784 6785 void 6786 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6787 { 6788 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6789 board_disable); 6790 struct pci_dev *pdev = ha->pdev; 6791 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6792 6793 ql_log(ql_log_warn, base_vha, 0x015b, 6794 "Disabling adapter.\n"); 6795 6796 if (!atomic_read(&pdev->enable_cnt)) { 6797 ql_log(ql_log_info, base_vha, 0xfffc, 6798 "PCI device disabled, no action req for PCI error=%lx\n", 6799 base_vha->pci_flags); 6800 return; 6801 } 6802 6803 /* 6804 * if UNLOADING flag is already set, then continue unload, 6805 * where it was set first. 6806 */ 6807 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6808 return; 6809 6810 qla2x00_wait_for_sess_deletion(base_vha); 6811 6812 qla2x00_delete_all_vps(ha, base_vha); 6813 6814 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6815 6816 qla2x00_dfs_remove(base_vha); 6817 6818 qla84xx_put_chip(base_vha); 6819 6820 if (base_vha->timer_active) 6821 qla2x00_stop_timer(base_vha); 6822 6823 base_vha->flags.online = 0; 6824 6825 qla2x00_destroy_deferred_work(ha); 6826 6827 /* 6828 * Do not try to stop beacon blink as it will issue a mailbox 6829 * command. 6830 */ 6831 qla2x00_free_sysfs_attr(base_vha, false); 6832 6833 fc_remove_host(base_vha->host); 6834 6835 scsi_remove_host(base_vha->host); 6836 6837 base_vha->flags.init_done = 0; 6838 qla25xx_delete_queues(base_vha); 6839 qla2x00_free_fcports(base_vha); 6840 qla2x00_free_irqs(base_vha); 6841 qla2x00_mem_free(ha); 6842 qla82xx_md_free(base_vha); 6843 qla2x00_free_queues(ha); 6844 6845 qla2x00_unmap_iobases(ha); 6846 6847 pci_release_selected_regions(ha->pdev, ha->bars); 6848 pci_disable_pcie_error_reporting(pdev); 6849 pci_disable_device(pdev); 6850 6851 /* 6852 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6853 */ 6854 } 6855 6856 /************************************************************************** 6857 * qla2x00_do_dpc 6858 * This kernel thread is a task that is schedule by the interrupt handler 6859 * to perform the background processing for interrupts. 6860 * 6861 * Notes: 6862 * This task always run in the context of a kernel thread. It 6863 * is kick-off by the driver's detect code and starts up 6864 * up one per adapter. It immediately goes to sleep and waits for 6865 * some fibre event. When either the interrupt handler or 6866 * the timer routine detects a event it will one of the task 6867 * bits then wake us up. 6868 **************************************************************************/ 6869 static int 6870 qla2x00_do_dpc(void *data) 6871 { 6872 scsi_qla_host_t *base_vha; 6873 struct qla_hw_data *ha; 6874 uint32_t online; 6875 struct qla_qpair *qpair; 6876 6877 ha = (struct qla_hw_data *)data; 6878 base_vha = pci_get_drvdata(ha->pdev); 6879 6880 set_user_nice(current, MIN_NICE); 6881 6882 set_current_state(TASK_INTERRUPTIBLE); 6883 while (!kthread_should_stop()) { 6884 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6885 "DPC handler sleeping.\n"); 6886 6887 schedule(); 6888 6889 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6890 qla_pci_set_eeh_busy(base_vha); 6891 6892 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6893 goto end_loop; 6894 6895 if (ha->flags.eeh_busy) { 6896 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6897 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6898 goto end_loop; 6899 } 6900 6901 ha->dpc_active = 1; 6902 6903 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6904 "DPC handler waking up, dpc_flags=0x%lx.\n", 6905 base_vha->dpc_flags); 6906 6907 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6908 break; 6909 6910 if (IS_P3P_TYPE(ha)) { 6911 if (IS_QLA8044(ha)) { 6912 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6913 &base_vha->dpc_flags)) { 6914 qla8044_idc_lock(ha); 6915 qla8044_wr_direct(base_vha, 6916 QLA8044_CRB_DEV_STATE_INDEX, 6917 QLA8XXX_DEV_FAILED); 6918 qla8044_idc_unlock(ha); 6919 ql_log(ql_log_info, base_vha, 0x4004, 6920 "HW State: FAILED.\n"); 6921 qla8044_device_state_handler(base_vha); 6922 continue; 6923 } 6924 6925 } else { 6926 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6927 &base_vha->dpc_flags)) { 6928 qla82xx_idc_lock(ha); 6929 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6930 QLA8XXX_DEV_FAILED); 6931 qla82xx_idc_unlock(ha); 6932 ql_log(ql_log_info, base_vha, 0x0151, 6933 "HW State: FAILED.\n"); 6934 qla82xx_device_state_handler(base_vha); 6935 continue; 6936 } 6937 } 6938 6939 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6940 &base_vha->dpc_flags)) { 6941 6942 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6943 "FCoE context reset scheduled.\n"); 6944 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6945 &base_vha->dpc_flags))) { 6946 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6947 /* FCoE-ctx reset failed. 6948 * Escalate to chip-reset 6949 */ 6950 set_bit(ISP_ABORT_NEEDED, 6951 &base_vha->dpc_flags); 6952 } 6953 clear_bit(ABORT_ISP_ACTIVE, 6954 &base_vha->dpc_flags); 6955 } 6956 6957 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6958 "FCoE context reset end.\n"); 6959 } 6960 } else if (IS_QLAFX00(ha)) { 6961 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6962 &base_vha->dpc_flags)) { 6963 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6964 "Firmware Reset Recovery\n"); 6965 if (qlafx00_reset_initialize(base_vha)) { 6966 /* Failed. Abort isp later. */ 6967 if (!test_bit(UNLOADING, 6968 &base_vha->dpc_flags)) { 6969 set_bit(ISP_UNRECOVERABLE, 6970 &base_vha->dpc_flags); 6971 ql_dbg(ql_dbg_dpc, base_vha, 6972 0x4021, 6973 "Reset Recovery Failed\n"); 6974 } 6975 } 6976 } 6977 6978 if (test_and_clear_bit(FX00_TARGET_SCAN, 6979 &base_vha->dpc_flags)) { 6980 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6981 "ISPFx00 Target Scan scheduled\n"); 6982 if (qlafx00_rescan_isp(base_vha)) { 6983 if (!test_bit(UNLOADING, 6984 &base_vha->dpc_flags)) 6985 set_bit(ISP_UNRECOVERABLE, 6986 &base_vha->dpc_flags); 6987 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6988 "ISPFx00 Target Scan Failed\n"); 6989 } 6990 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6991 "ISPFx00 Target Scan End\n"); 6992 } 6993 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6994 &base_vha->dpc_flags)) { 6995 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6996 "ISPFx00 Host Info resend scheduled\n"); 6997 qlafx00_fx_disc(base_vha, 6998 &base_vha->hw->mr.fcport, 6999 FXDISC_REG_HOST_INFO); 7000 } 7001 } 7002 7003 if (test_and_clear_bit(DETECT_SFP_CHANGE, 7004 &base_vha->dpc_flags)) { 7005 /* Semantic: 7006 * - NO-OP -- await next ISP-ABORT. Preferred method 7007 * to minimize disruptions that will occur 7008 * when a forced chip-reset occurs. 7009 * - Force -- ISP-ABORT scheduled. 7010 */ 7011 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7012 } 7013 7014 if (test_and_clear_bit 7015 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7016 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7017 bool do_reset = true; 7018 7019 switch (base_vha->qlini_mode) { 7020 case QLA2XXX_INI_MODE_ENABLED: 7021 break; 7022 case QLA2XXX_INI_MODE_DISABLED: 7023 if (!qla_tgt_mode_enabled(base_vha) && 7024 !ha->flags.fw_started) 7025 do_reset = false; 7026 break; 7027 case QLA2XXX_INI_MODE_DUAL: 7028 if (!qla_dual_mode_enabled(base_vha) && 7029 !ha->flags.fw_started) 7030 do_reset = false; 7031 break; 7032 default: 7033 break; 7034 } 7035 7036 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7037 &base_vha->dpc_flags))) { 7038 base_vha->flags.online = 1; 7039 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7040 "ISP abort scheduled.\n"); 7041 if (ha->isp_ops->abort_isp(base_vha)) { 7042 /* failed. retry later */ 7043 set_bit(ISP_ABORT_NEEDED, 7044 &base_vha->dpc_flags); 7045 } 7046 clear_bit(ABORT_ISP_ACTIVE, 7047 &base_vha->dpc_flags); 7048 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7049 "ISP abort end.\n"); 7050 } 7051 } 7052 7053 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7054 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7055 qla24xx_process_purex_list 7056 (&base_vha->purex_list); 7057 clear_bit(PROCESS_PUREX_IOCB, 7058 &base_vha->dpc_flags); 7059 } 7060 } 7061 7062 if (IS_QLAFX00(ha)) 7063 goto loop_resync_check; 7064 7065 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7066 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7067 "Quiescence mode scheduled.\n"); 7068 if (IS_P3P_TYPE(ha)) { 7069 if (IS_QLA82XX(ha)) 7070 qla82xx_device_state_handler(base_vha); 7071 if (IS_QLA8044(ha)) 7072 qla8044_device_state_handler(base_vha); 7073 clear_bit(ISP_QUIESCE_NEEDED, 7074 &base_vha->dpc_flags); 7075 if (!ha->flags.quiesce_owner) { 7076 qla2x00_perform_loop_resync(base_vha); 7077 if (IS_QLA82XX(ha)) { 7078 qla82xx_idc_lock(ha); 7079 qla82xx_clear_qsnt_ready( 7080 base_vha); 7081 qla82xx_idc_unlock(ha); 7082 } else if (IS_QLA8044(ha)) { 7083 qla8044_idc_lock(ha); 7084 qla8044_clear_qsnt_ready( 7085 base_vha); 7086 qla8044_idc_unlock(ha); 7087 } 7088 } 7089 } else { 7090 clear_bit(ISP_QUIESCE_NEEDED, 7091 &base_vha->dpc_flags); 7092 qla2x00_quiesce_io(base_vha); 7093 } 7094 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7095 "Quiescence mode end.\n"); 7096 } 7097 7098 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7099 &base_vha->dpc_flags) && 7100 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7101 7102 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7103 "Reset marker scheduled.\n"); 7104 qla2x00_rst_aen(base_vha); 7105 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7106 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7107 "Reset marker end.\n"); 7108 } 7109 7110 /* Retry each device up to login retry count */ 7111 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7112 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7113 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7114 7115 if (!base_vha->relogin_jif || 7116 time_after_eq(jiffies, base_vha->relogin_jif)) { 7117 base_vha->relogin_jif = jiffies + HZ; 7118 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7119 7120 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7121 "Relogin scheduled.\n"); 7122 qla24xx_post_relogin_work(base_vha); 7123 } 7124 } 7125 loop_resync_check: 7126 if (!qla2x00_reset_active(base_vha) && 7127 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7128 &base_vha->dpc_flags)) { 7129 /* 7130 * Allow abort_isp to complete before moving on to scanning. 7131 */ 7132 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7133 "Loop resync scheduled.\n"); 7134 7135 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7136 &base_vha->dpc_flags))) { 7137 7138 qla2x00_loop_resync(base_vha); 7139 7140 clear_bit(LOOP_RESYNC_ACTIVE, 7141 &base_vha->dpc_flags); 7142 } 7143 7144 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7145 "Loop resync end.\n"); 7146 } 7147 7148 if (IS_QLAFX00(ha)) 7149 goto intr_on_check; 7150 7151 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7152 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7153 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7154 qla2xxx_flash_npiv_conf(base_vha); 7155 } 7156 7157 intr_on_check: 7158 if (!ha->interrupts_on) 7159 ha->isp_ops->enable_intrs(ha); 7160 7161 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7162 &base_vha->dpc_flags)) { 7163 if (ha->beacon_blink_led == 1) 7164 ha->isp_ops->beacon_blink(base_vha); 7165 } 7166 7167 /* qpair online check */ 7168 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7169 &base_vha->dpc_flags)) { 7170 if (ha->flags.eeh_busy || 7171 ha->flags.pci_channel_io_perm_failure) 7172 online = 0; 7173 else 7174 online = 1; 7175 7176 mutex_lock(&ha->mq_lock); 7177 list_for_each_entry(qpair, &base_vha->qp_list, 7178 qp_list_elem) 7179 qpair->online = online; 7180 mutex_unlock(&ha->mq_lock); 7181 } 7182 7183 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7184 &base_vha->dpc_flags)) { 7185 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7186 7187 if (threshold > ha->orig_fw_xcb_count) 7188 threshold = ha->orig_fw_xcb_count; 7189 7190 ql_log(ql_log_info, base_vha, 0xffffff, 7191 "SET ZIO Activity exchange threshold to %d.\n", 7192 threshold); 7193 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7194 ql_log(ql_log_info, base_vha, 0xffffff, 7195 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7196 threshold); 7197 } 7198 } 7199 7200 if (!IS_QLAFX00(ha)) 7201 qla2x00_do_dpc_all_vps(base_vha); 7202 7203 if (test_and_clear_bit(N2N_LINK_RESET, 7204 &base_vha->dpc_flags)) { 7205 qla2x00_lip_reset(base_vha); 7206 } 7207 7208 ha->dpc_active = 0; 7209 end_loop: 7210 set_current_state(TASK_INTERRUPTIBLE); 7211 } /* End of while(1) */ 7212 __set_current_state(TASK_RUNNING); 7213 7214 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7215 "DPC handler exiting.\n"); 7216 7217 /* 7218 * Make sure that nobody tries to wake us up again. 7219 */ 7220 ha->dpc_active = 0; 7221 7222 /* Cleanup any residual CTX SRBs. */ 7223 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7224 7225 return 0; 7226 } 7227 7228 void 7229 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7230 { 7231 struct qla_hw_data *ha = vha->hw; 7232 struct task_struct *t = ha->dpc_thread; 7233 7234 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7235 wake_up_process(t); 7236 } 7237 7238 /* 7239 * qla2x00_rst_aen 7240 * Processes asynchronous reset. 7241 * 7242 * Input: 7243 * ha = adapter block pointer. 7244 */ 7245 static void 7246 qla2x00_rst_aen(scsi_qla_host_t *vha) 7247 { 7248 if (vha->flags.online && !vha->flags.reset_active && 7249 !atomic_read(&vha->loop_down_timer) && 7250 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7251 do { 7252 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7253 7254 /* 7255 * Issue marker command only when we are going to start 7256 * the I/O. 7257 */ 7258 vha->marker_needed = 1; 7259 } while (!atomic_read(&vha->loop_down_timer) && 7260 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7261 } 7262 } 7263 7264 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7265 { 7266 struct qla_hw_data *ha = vha->hw; 7267 u32 cmpl_cnt; 7268 u16 i; 7269 bool do_heartbeat = false; 7270 7271 /* 7272 * Allow do_heartbeat only if we don’t have any active interrupts, 7273 * but there are still IOs outstanding with firmware. 7274 */ 7275 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7276 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7277 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7278 do_heartbeat = true; 7279 goto skip; 7280 } 7281 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7282 7283 for (i = 0; i < ha->max_qpairs; i++) { 7284 if (ha->queue_pair_map[i]) { 7285 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7286 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7287 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7288 do_heartbeat = true; 7289 break; 7290 } 7291 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7292 } 7293 } 7294 7295 skip: 7296 return do_heartbeat; 7297 } 7298 7299 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7300 { 7301 struct qla_hw_data *ha = vha->hw; 7302 7303 if (vha->vp_idx) 7304 return; 7305 7306 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7307 return; 7308 7309 /* 7310 * dpc thread cannot run if heartbeat is running at the same time. 7311 * We also do not want to starve heartbeat task. Therefore, do 7312 * heartbeat task at least once every 5 seconds. 7313 */ 7314 if (dpc_started && 7315 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7316 return; 7317 7318 if (qla_do_heartbeat(vha)) { 7319 ha->last_heartbeat_run_jiffies = jiffies; 7320 queue_work(ha->wq, &ha->heartbeat_work); 7321 } 7322 } 7323 7324 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7325 { 7326 struct qla_hw_data *ha = vha->hw; 7327 7328 if (!ha->flags.eeh_busy) 7329 return; 7330 if (ha->pci_error_state) 7331 /* system is trying to recover */ 7332 return; 7333 7334 /* 7335 * Current system is not handling PCIE error. At this point, this is 7336 * best effort to wind down the adapter. 7337 */ 7338 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7339 !ha->flags.eeh_flush) { 7340 ql_log(ql_log_info, vha, 0x9009, 7341 "PCI Error detected, attempting to reset hardware.\n"); 7342 7343 ha->isp_ops->reset_chip(vha); 7344 ha->isp_ops->disable_intrs(ha); 7345 7346 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7347 ha->eeh_jif = jiffies; 7348 7349 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7350 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7351 pci_clear_master(ha->pdev); 7352 7353 /* flush all command */ 7354 qla2x00_abort_isp_cleanup(vha); 7355 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7356 7357 ql_log(ql_log_info, vha, 0x900a, 7358 "PCI Error handling complete, all IOs aborted.\n"); 7359 } 7360 } 7361 7362 /************************************************************************** 7363 * qla2x00_timer 7364 * 7365 * Description: 7366 * One second timer 7367 * 7368 * Context: Interrupt 7369 ***************************************************************************/ 7370 void 7371 qla2x00_timer(struct timer_list *t) 7372 { 7373 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7374 unsigned long cpu_flags = 0; 7375 int start_dpc = 0; 7376 int index; 7377 srb_t *sp; 7378 uint16_t w; 7379 struct qla_hw_data *ha = vha->hw; 7380 struct req_que *req; 7381 unsigned long flags; 7382 fc_port_t *fcport = NULL; 7383 7384 if (ha->flags.eeh_busy) { 7385 qla_wind_down_chip(vha); 7386 7387 ql_dbg(ql_dbg_timer, vha, 0x6000, 7388 "EEH = %d, restarting timer.\n", 7389 ha->flags.eeh_busy); 7390 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7391 return; 7392 } 7393 7394 /* 7395 * Hardware read to raise pending EEH errors during mailbox waits. If 7396 * the read returns -1 then disable the board. 7397 */ 7398 if (!pci_channel_offline(ha->pdev)) { 7399 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7400 qla2x00_check_reg16_for_disconnect(vha, w); 7401 } 7402 7403 /* Make sure qla82xx_watchdog is run only for physical port */ 7404 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7405 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7406 start_dpc++; 7407 if (IS_QLA82XX(ha)) 7408 qla82xx_watchdog(vha); 7409 else if (IS_QLA8044(ha)) 7410 qla8044_watchdog(vha); 7411 } 7412 7413 if (!vha->vp_idx && IS_QLAFX00(ha)) 7414 qlafx00_timer_routine(vha); 7415 7416 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7417 vha->link_down_time++; 7418 7419 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7420 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7421 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7422 fcport->tgt_link_down_time++; 7423 } 7424 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7425 7426 /* Loop down handler. */ 7427 if (atomic_read(&vha->loop_down_timer) > 0 && 7428 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7429 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7430 && vha->flags.online) { 7431 7432 if (atomic_read(&vha->loop_down_timer) == 7433 vha->loop_down_abort_time) { 7434 7435 ql_log(ql_log_info, vha, 0x6008, 7436 "Loop down - aborting the queues before time expires.\n"); 7437 7438 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7439 atomic_set(&vha->loop_state, LOOP_DEAD); 7440 7441 /* 7442 * Schedule an ISP abort to return any FCP2-device 7443 * commands. 7444 */ 7445 /* NPIV - scan physical port only */ 7446 if (!vha->vp_idx) { 7447 spin_lock_irqsave(&ha->hardware_lock, 7448 cpu_flags); 7449 req = ha->req_q_map[0]; 7450 for (index = 1; 7451 index < req->num_outstanding_cmds; 7452 index++) { 7453 fc_port_t *sfcp; 7454 7455 sp = req->outstanding_cmds[index]; 7456 if (!sp) 7457 continue; 7458 if (sp->cmd_type != TYPE_SRB) 7459 continue; 7460 if (sp->type != SRB_SCSI_CMD) 7461 continue; 7462 sfcp = sp->fcport; 7463 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7464 continue; 7465 7466 if (IS_QLA82XX(ha)) 7467 set_bit(FCOE_CTX_RESET_NEEDED, 7468 &vha->dpc_flags); 7469 else 7470 set_bit(ISP_ABORT_NEEDED, 7471 &vha->dpc_flags); 7472 break; 7473 } 7474 spin_unlock_irqrestore(&ha->hardware_lock, 7475 cpu_flags); 7476 } 7477 start_dpc++; 7478 } 7479 7480 /* if the loop has been down for 4 minutes, reinit adapter */ 7481 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7482 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7483 ql_log(ql_log_warn, vha, 0x6009, 7484 "Loop down - aborting ISP.\n"); 7485 7486 if (IS_QLA82XX(ha)) 7487 set_bit(FCOE_CTX_RESET_NEEDED, 7488 &vha->dpc_flags); 7489 else 7490 set_bit(ISP_ABORT_NEEDED, 7491 &vha->dpc_flags); 7492 } 7493 } 7494 ql_dbg(ql_dbg_timer, vha, 0x600a, 7495 "Loop down - seconds remaining %d.\n", 7496 atomic_read(&vha->loop_down_timer)); 7497 } 7498 /* Check if beacon LED needs to be blinked for physical host only */ 7499 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7500 /* There is no beacon_blink function for ISP82xx */ 7501 if (!IS_P3P_TYPE(ha)) { 7502 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7503 start_dpc++; 7504 } 7505 } 7506 7507 /* check if edif running */ 7508 if (vha->hw->flags.edif_enabled) 7509 qla_edif_timer(vha); 7510 7511 /* Process any deferred work. */ 7512 if (!list_empty(&vha->work_list)) { 7513 unsigned long flags; 7514 bool q = false; 7515 7516 spin_lock_irqsave(&vha->work_lock, flags); 7517 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7518 q = true; 7519 spin_unlock_irqrestore(&vha->work_lock, flags); 7520 if (q) 7521 queue_work(vha->hw->wq, &vha->iocb_work); 7522 } 7523 7524 /* 7525 * FC-NVME 7526 * see if the active AEN count has changed from what was last reported. 7527 */ 7528 index = atomic_read(&ha->nvme_active_aen_cnt); 7529 if (!vha->vp_idx && 7530 (index != ha->nvme_last_rptd_aen) && 7531 ha->zio_mode == QLA_ZIO_MODE_6 && 7532 !ha->flags.host_shutting_down) { 7533 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7534 ql_log(ql_log_info, vha, 0x3002, 7535 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7536 ha->nvme_last_rptd_aen); 7537 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7538 start_dpc++; 7539 } 7540 7541 if (!vha->vp_idx && 7542 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7543 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7544 ql_log(ql_log_info, vha, 0x3002, 7545 "Sched: Set ZIO exchange threshold to %d.\n", 7546 ha->last_zio_threshold); 7547 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7548 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7549 start_dpc++; 7550 } 7551 qla_adjust_buf(vha); 7552 7553 /* borrowing w to signify dpc will run */ 7554 w = 0; 7555 /* Schedule the DPC routine if needed */ 7556 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7557 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7558 start_dpc || 7559 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7560 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7561 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7562 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7563 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7564 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7565 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7566 ql_dbg(ql_dbg_timer, vha, 0x600b, 7567 "isp_abort_needed=%d loop_resync_needed=%d " 7568 "start_dpc=%d reset_marker_needed=%d", 7569 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7570 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7571 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7572 ql_dbg(ql_dbg_timer, vha, 0x600c, 7573 "beacon_blink_needed=%d isp_unrecoverable=%d " 7574 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7575 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7576 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7577 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7578 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7579 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7580 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7581 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7582 qla2xxx_wake_dpc(vha); 7583 w = 1; 7584 } 7585 7586 qla_heart_beat(vha, w); 7587 7588 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7589 } 7590 7591 /* Firmware interface routines. */ 7592 7593 #define FW_ISP21XX 0 7594 #define FW_ISP22XX 1 7595 #define FW_ISP2300 2 7596 #define FW_ISP2322 3 7597 #define FW_ISP24XX 4 7598 #define FW_ISP25XX 5 7599 #define FW_ISP81XX 6 7600 #define FW_ISP82XX 7 7601 #define FW_ISP2031 8 7602 #define FW_ISP8031 9 7603 #define FW_ISP27XX 10 7604 #define FW_ISP28XX 11 7605 7606 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7607 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7608 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7609 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7610 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7611 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7612 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7613 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7614 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7615 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7616 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7617 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7618 7619 7620 static DEFINE_MUTEX(qla_fw_lock); 7621 7622 static struct fw_blob qla_fw_blobs[] = { 7623 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7624 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7625 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7626 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7627 { .name = FW_FILE_ISP24XX, }, 7628 { .name = FW_FILE_ISP25XX, }, 7629 { .name = FW_FILE_ISP81XX, }, 7630 { .name = FW_FILE_ISP82XX, }, 7631 { .name = FW_FILE_ISP2031, }, 7632 { .name = FW_FILE_ISP8031, }, 7633 { .name = FW_FILE_ISP27XX, }, 7634 { .name = FW_FILE_ISP28XX, }, 7635 { .name = NULL, }, 7636 }; 7637 7638 struct fw_blob * 7639 qla2x00_request_firmware(scsi_qla_host_t *vha) 7640 { 7641 struct qla_hw_data *ha = vha->hw; 7642 struct fw_blob *blob; 7643 7644 if (IS_QLA2100(ha)) { 7645 blob = &qla_fw_blobs[FW_ISP21XX]; 7646 } else if (IS_QLA2200(ha)) { 7647 blob = &qla_fw_blobs[FW_ISP22XX]; 7648 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7649 blob = &qla_fw_blobs[FW_ISP2300]; 7650 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7651 blob = &qla_fw_blobs[FW_ISP2322]; 7652 } else if (IS_QLA24XX_TYPE(ha)) { 7653 blob = &qla_fw_blobs[FW_ISP24XX]; 7654 } else if (IS_QLA25XX(ha)) { 7655 blob = &qla_fw_blobs[FW_ISP25XX]; 7656 } else if (IS_QLA81XX(ha)) { 7657 blob = &qla_fw_blobs[FW_ISP81XX]; 7658 } else if (IS_QLA82XX(ha)) { 7659 blob = &qla_fw_blobs[FW_ISP82XX]; 7660 } else if (IS_QLA2031(ha)) { 7661 blob = &qla_fw_blobs[FW_ISP2031]; 7662 } else if (IS_QLA8031(ha)) { 7663 blob = &qla_fw_blobs[FW_ISP8031]; 7664 } else if (IS_QLA27XX(ha)) { 7665 blob = &qla_fw_blobs[FW_ISP27XX]; 7666 } else if (IS_QLA28XX(ha)) { 7667 blob = &qla_fw_blobs[FW_ISP28XX]; 7668 } else { 7669 return NULL; 7670 } 7671 7672 if (!blob->name) 7673 return NULL; 7674 7675 mutex_lock(&qla_fw_lock); 7676 if (blob->fw) 7677 goto out; 7678 7679 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7680 ql_log(ql_log_warn, vha, 0x0063, 7681 "Failed to load firmware image (%s).\n", blob->name); 7682 blob->fw = NULL; 7683 blob = NULL; 7684 } 7685 7686 out: 7687 mutex_unlock(&qla_fw_lock); 7688 return blob; 7689 } 7690 7691 static void 7692 qla2x00_release_firmware(void) 7693 { 7694 struct fw_blob *blob; 7695 7696 mutex_lock(&qla_fw_lock); 7697 for (blob = qla_fw_blobs; blob->name; blob++) 7698 release_firmware(blob->fw); 7699 mutex_unlock(&qla_fw_lock); 7700 } 7701 7702 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7703 { 7704 struct qla_hw_data *ha = vha->hw; 7705 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7706 struct qla_qpair *qpair = NULL; 7707 struct scsi_qla_host *vp, *tvp; 7708 fc_port_t *fcport; 7709 int i; 7710 unsigned long flags; 7711 7712 ql_dbg(ql_dbg_aer, vha, 0x9000, 7713 "%s\n", __func__); 7714 ha->chip_reset++; 7715 7716 ha->base_qpair->chip_reset = ha->chip_reset; 7717 for (i = 0; i < ha->max_qpairs; i++) { 7718 if (ha->queue_pair_map[i]) 7719 ha->queue_pair_map[i]->chip_reset = 7720 ha->base_qpair->chip_reset; 7721 } 7722 7723 /* 7724 * purge mailbox might take a while. Slot Reset/chip reset 7725 * will take care of the purge 7726 */ 7727 7728 mutex_lock(&ha->mq_lock); 7729 ha->base_qpair->online = 0; 7730 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7731 qpair->online = 0; 7732 wmb(); 7733 mutex_unlock(&ha->mq_lock); 7734 7735 qla2x00_mark_all_devices_lost(vha); 7736 7737 spin_lock_irqsave(&ha->vport_slock, flags); 7738 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7739 atomic_inc(&vp->vref_count); 7740 spin_unlock_irqrestore(&ha->vport_slock, flags); 7741 qla2x00_mark_all_devices_lost(vp); 7742 spin_lock_irqsave(&ha->vport_slock, flags); 7743 atomic_dec(&vp->vref_count); 7744 } 7745 spin_unlock_irqrestore(&ha->vport_slock, flags); 7746 7747 /* Clear all async request states across all VPs. */ 7748 list_for_each_entry(fcport, &vha->vp_fcports, list) 7749 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7750 7751 spin_lock_irqsave(&ha->vport_slock, flags); 7752 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7753 atomic_inc(&vp->vref_count); 7754 spin_unlock_irqrestore(&ha->vport_slock, flags); 7755 list_for_each_entry(fcport, &vp->vp_fcports, list) 7756 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7757 spin_lock_irqsave(&ha->vport_slock, flags); 7758 atomic_dec(&vp->vref_count); 7759 } 7760 spin_unlock_irqrestore(&ha->vport_slock, flags); 7761 } 7762 7763 7764 static pci_ers_result_t 7765 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7766 { 7767 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7768 struct qla_hw_data *ha = vha->hw; 7769 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7770 7771 ql_log(ql_log_warn, vha, 0x9000, 7772 "PCI error detected, state %x.\n", state); 7773 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7774 7775 if (!atomic_read(&pdev->enable_cnt)) { 7776 ql_log(ql_log_info, vha, 0xffff, 7777 "PCI device is disabled,state %x\n", state); 7778 ret = PCI_ERS_RESULT_NEED_RESET; 7779 goto out; 7780 } 7781 7782 switch (state) { 7783 case pci_channel_io_normal: 7784 qla_pci_set_eeh_busy(vha); 7785 if (ql2xmqsupport || ql2xnvmeenable) { 7786 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7787 qla2xxx_wake_dpc(vha); 7788 } 7789 ret = PCI_ERS_RESULT_CAN_RECOVER; 7790 break; 7791 case pci_channel_io_frozen: 7792 qla_pci_set_eeh_busy(vha); 7793 ret = PCI_ERS_RESULT_NEED_RESET; 7794 break; 7795 case pci_channel_io_perm_failure: 7796 ha->flags.pci_channel_io_perm_failure = 1; 7797 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7798 if (ql2xmqsupport || ql2xnvmeenable) { 7799 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7800 qla2xxx_wake_dpc(vha); 7801 } 7802 ret = PCI_ERS_RESULT_DISCONNECT; 7803 } 7804 out: 7805 ql_dbg(ql_dbg_aer, vha, 0x600d, 7806 "PCI error detected returning [%x].\n", ret); 7807 return ret; 7808 } 7809 7810 static pci_ers_result_t 7811 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7812 { 7813 int risc_paused = 0; 7814 uint32_t stat; 7815 unsigned long flags; 7816 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7817 struct qla_hw_data *ha = base_vha->hw; 7818 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7819 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7820 7821 ql_log(ql_log_warn, base_vha, 0x9000, 7822 "mmio enabled\n"); 7823 7824 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7825 7826 if (IS_QLA82XX(ha)) 7827 return PCI_ERS_RESULT_RECOVERED; 7828 7829 if (qla2x00_isp_reg_stat(ha)) { 7830 ql_log(ql_log_info, base_vha, 0x803f, 7831 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7832 goto out; 7833 } 7834 7835 spin_lock_irqsave(&ha->hardware_lock, flags); 7836 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7837 stat = rd_reg_word(®->hccr); 7838 if (stat & HCCR_RISC_PAUSE) 7839 risc_paused = 1; 7840 } else if (IS_QLA23XX(ha)) { 7841 stat = rd_reg_dword(®->u.isp2300.host_status); 7842 if (stat & HSR_RISC_PAUSED) 7843 risc_paused = 1; 7844 } else if (IS_FWI2_CAPABLE(ha)) { 7845 stat = rd_reg_dword(®24->host_status); 7846 if (stat & HSRX_RISC_PAUSED) 7847 risc_paused = 1; 7848 } 7849 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7850 7851 if (risc_paused) { 7852 ql_log(ql_log_info, base_vha, 0x9003, 7853 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7854 qla2xxx_dump_fw(base_vha); 7855 } 7856 out: 7857 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7858 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7859 "mmio enabled returning.\n"); 7860 return PCI_ERS_RESULT_NEED_RESET; 7861 } 7862 7863 static pci_ers_result_t 7864 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7865 { 7866 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7867 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7868 struct qla_hw_data *ha = base_vha->hw; 7869 int rc; 7870 struct qla_qpair *qpair = NULL; 7871 7872 ql_log(ql_log_warn, base_vha, 0x9004, 7873 "Slot Reset.\n"); 7874 7875 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7876 /* Workaround: qla2xxx driver which access hardware earlier 7877 * needs error state to be pci_channel_io_online. 7878 * Otherwise mailbox command timesout. 7879 */ 7880 pdev->error_state = pci_channel_io_normal; 7881 7882 pci_restore_state(pdev); 7883 7884 /* pci_restore_state() clears the saved_state flag of the device 7885 * save restored state which resets saved_state flag 7886 */ 7887 pci_save_state(pdev); 7888 7889 if (ha->mem_only) 7890 rc = pci_enable_device_mem(pdev); 7891 else 7892 rc = pci_enable_device(pdev); 7893 7894 if (rc) { 7895 ql_log(ql_log_warn, base_vha, 0x9005, 7896 "Can't re-enable PCI device after reset.\n"); 7897 goto exit_slot_reset; 7898 } 7899 7900 7901 if (ha->isp_ops->pci_config(base_vha)) 7902 goto exit_slot_reset; 7903 7904 mutex_lock(&ha->mq_lock); 7905 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7906 qpair->online = 1; 7907 mutex_unlock(&ha->mq_lock); 7908 7909 ha->flags.eeh_busy = 0; 7910 base_vha->flags.online = 1; 7911 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7912 ha->isp_ops->abort_isp(base_vha); 7913 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7914 7915 if (qla2x00_isp_reg_stat(ha)) { 7916 ha->flags.eeh_busy = 1; 7917 qla_pci_error_cleanup(base_vha); 7918 ql_log(ql_log_warn, base_vha, 0x9005, 7919 "Device unable to recover from PCI error.\n"); 7920 } else { 7921 ret = PCI_ERS_RESULT_RECOVERED; 7922 } 7923 7924 exit_slot_reset: 7925 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7926 "Slot Reset returning %x.\n", ret); 7927 7928 return ret; 7929 } 7930 7931 static void 7932 qla2xxx_pci_resume(struct pci_dev *pdev) 7933 { 7934 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7935 struct qla_hw_data *ha = base_vha->hw; 7936 int ret; 7937 7938 ql_log(ql_log_warn, base_vha, 0x900f, 7939 "Pci Resume.\n"); 7940 7941 7942 ret = qla2x00_wait_for_hba_online(base_vha); 7943 if (ret != QLA_SUCCESS) { 7944 ql_log(ql_log_fatal, base_vha, 0x9002, 7945 "The device failed to resume I/O from slot/link_reset.\n"); 7946 } 7947 ha->pci_error_state = QLA_PCI_RESUME; 7948 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7949 "Pci Resume returning.\n"); 7950 } 7951 7952 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7953 { 7954 struct qla_hw_data *ha = vha->hw; 7955 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7956 bool do_cleanup = false; 7957 unsigned long flags; 7958 7959 if (ha->flags.eeh_busy) 7960 return; 7961 7962 spin_lock_irqsave(&base_vha->work_lock, flags); 7963 if (!ha->flags.eeh_busy) { 7964 ha->eeh_jif = jiffies; 7965 ha->flags.eeh_flush = 0; 7966 7967 ha->flags.eeh_busy = 1; 7968 do_cleanup = true; 7969 } 7970 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7971 7972 if (do_cleanup) 7973 qla_pci_error_cleanup(base_vha); 7974 } 7975 7976 /* 7977 * this routine will schedule a task to pause IO from interrupt context 7978 * if caller sees a PCIE error event (register read = 0xf's) 7979 */ 7980 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7981 { 7982 struct qla_hw_data *ha = vha->hw; 7983 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7984 7985 if (ha->flags.eeh_busy) 7986 return; 7987 7988 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7989 qla2xxx_wake_dpc(base_vha); 7990 } 7991 7992 static void 7993 qla_pci_reset_prepare(struct pci_dev *pdev) 7994 { 7995 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7996 struct qla_hw_data *ha = base_vha->hw; 7997 struct qla_qpair *qpair; 7998 7999 ql_log(ql_log_warn, base_vha, 0xffff, 8000 "%s.\n", __func__); 8001 8002 /* 8003 * PCI FLR/function reset is about to reset the 8004 * slot. Stop the chip to stop all DMA access. 8005 * It is assumed that pci_reset_done will be called 8006 * after FLR to resume Chip operation. 8007 */ 8008 ha->flags.eeh_busy = 1; 8009 mutex_lock(&ha->mq_lock); 8010 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8011 qpair->online = 0; 8012 mutex_unlock(&ha->mq_lock); 8013 8014 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8015 qla2x00_abort_isp_cleanup(base_vha); 8016 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8017 } 8018 8019 static void 8020 qla_pci_reset_done(struct pci_dev *pdev) 8021 { 8022 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8023 struct qla_hw_data *ha = base_vha->hw; 8024 struct qla_qpair *qpair; 8025 8026 ql_log(ql_log_warn, base_vha, 0xffff, 8027 "%s.\n", __func__); 8028 8029 /* 8030 * FLR just completed by PCI layer. Resume adapter 8031 */ 8032 ha->flags.eeh_busy = 0; 8033 mutex_lock(&ha->mq_lock); 8034 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8035 qpair->online = 1; 8036 mutex_unlock(&ha->mq_lock); 8037 8038 base_vha->flags.online = 1; 8039 ha->isp_ops->abort_isp(base_vha); 8040 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8041 } 8042 8043 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8044 { 8045 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8046 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8047 8048 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8049 blk_mq_map_queues(qmap); 8050 else 8051 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8052 } 8053 8054 struct scsi_host_template qla2xxx_driver_template = { 8055 .module = THIS_MODULE, 8056 .name = QLA2XXX_DRIVER_NAME, 8057 .queuecommand = qla2xxx_queuecommand, 8058 8059 .eh_timed_out = fc_eh_timed_out, 8060 .eh_abort_handler = qla2xxx_eh_abort, 8061 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8062 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8063 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8064 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8065 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8066 8067 .slave_configure = qla2xxx_slave_configure, 8068 8069 .slave_alloc = qla2xxx_slave_alloc, 8070 .slave_destroy = qla2xxx_slave_destroy, 8071 .scan_finished = qla2xxx_scan_finished, 8072 .scan_start = qla2xxx_scan_start, 8073 .change_queue_depth = scsi_change_queue_depth, 8074 .map_queues = qla2xxx_map_queues, 8075 .this_id = -1, 8076 .cmd_per_lun = 3, 8077 .sg_tablesize = SG_ALL, 8078 8079 .max_sectors = 0xFFFF, 8080 .shost_groups = qla2x00_host_groups, 8081 8082 .supported_mode = MODE_INITIATOR, 8083 .track_queue_depth = 1, 8084 .cmd_size = sizeof(srb_t), 8085 }; 8086 8087 static const struct pci_error_handlers qla2xxx_err_handler = { 8088 .error_detected = qla2xxx_pci_error_detected, 8089 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8090 .slot_reset = qla2xxx_pci_slot_reset, 8091 .resume = qla2xxx_pci_resume, 8092 .reset_prepare = qla_pci_reset_prepare, 8093 .reset_done = qla_pci_reset_done, 8094 }; 8095 8096 static struct pci_device_id qla2xxx_pci_tbl[] = { 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8098 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8099 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8100 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8101 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8102 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8116 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8118 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8119 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8124 { 0 }, 8125 }; 8126 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8127 8128 static struct pci_driver qla2xxx_pci_driver = { 8129 .name = QLA2XXX_DRIVER_NAME, 8130 .driver = { 8131 .owner = THIS_MODULE, 8132 }, 8133 .id_table = qla2xxx_pci_tbl, 8134 .probe = qla2x00_probe_one, 8135 .remove = qla2x00_remove_one, 8136 .shutdown = qla2x00_shutdown, 8137 .err_handler = &qla2xxx_err_handler, 8138 }; 8139 8140 static const struct file_operations apidev_fops = { 8141 .owner = THIS_MODULE, 8142 .llseek = noop_llseek, 8143 }; 8144 8145 /** 8146 * qla2x00_module_init - Module initialization. 8147 **/ 8148 static int __init 8149 qla2x00_module_init(void) 8150 { 8151 int ret = 0; 8152 8153 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8154 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8155 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8156 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8157 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8158 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8159 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8160 BUILD_BUG_ON(sizeof(request_t) != 64); 8161 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8162 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8163 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8164 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8165 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8166 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8167 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8168 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8169 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8170 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8171 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8172 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8173 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8174 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8175 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8176 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8177 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8178 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8179 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8180 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8181 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8182 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8183 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8184 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8185 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8186 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8187 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8188 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8189 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8190 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8191 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8192 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8193 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8194 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8195 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8196 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8197 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8198 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8199 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8200 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8201 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8202 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8203 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8204 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8205 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8206 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8207 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8208 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8209 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8210 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8211 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8212 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8213 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8214 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8215 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8216 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8217 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8218 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8219 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8220 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8221 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8222 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8223 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8224 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8225 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8226 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8227 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8228 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8229 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8230 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8231 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8232 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8233 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8234 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8235 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8236 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8237 8238 qla_trace_init(); 8239 8240 /* Allocate cache for SRBs. */ 8241 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8242 SLAB_HWCACHE_ALIGN, NULL); 8243 if (srb_cachep == NULL) { 8244 ql_log(ql_log_fatal, NULL, 0x0001, 8245 "Unable to allocate SRB cache...Failing load!.\n"); 8246 return -ENOMEM; 8247 } 8248 8249 /* Initialize target kmem_cache and mem_pools */ 8250 ret = qlt_init(); 8251 if (ret < 0) { 8252 goto destroy_cache; 8253 } else if (ret > 0) { 8254 /* 8255 * If initiator mode is explictly disabled by qlt_init(), 8256 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8257 * performing scsi_scan_target() during LOOP UP event. 8258 */ 8259 qla2xxx_transport_functions.disable_target_scan = 1; 8260 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8261 } 8262 8263 /* Derive version string. */ 8264 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8265 if (ql2xextended_error_logging) 8266 strcat(qla2x00_version_str, "-debug"); 8267 if (ql2xextended_error_logging == 1) 8268 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8269 8270 qla2xxx_transport_template = 8271 fc_attach_transport(&qla2xxx_transport_functions); 8272 if (!qla2xxx_transport_template) { 8273 ql_log(ql_log_fatal, NULL, 0x0002, 8274 "fc_attach_transport failed...Failing load!.\n"); 8275 ret = -ENODEV; 8276 goto qlt_exit; 8277 } 8278 8279 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8280 if (apidev_major < 0) { 8281 ql_log(ql_log_fatal, NULL, 0x0003, 8282 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8283 } 8284 8285 qla2xxx_transport_vport_template = 8286 fc_attach_transport(&qla2xxx_transport_vport_functions); 8287 if (!qla2xxx_transport_vport_template) { 8288 ql_log(ql_log_fatal, NULL, 0x0004, 8289 "fc_attach_transport vport failed...Failing load!.\n"); 8290 ret = -ENODEV; 8291 goto unreg_chrdev; 8292 } 8293 ql_log(ql_log_info, NULL, 0x0005, 8294 "QLogic Fibre Channel HBA Driver: %s.\n", 8295 qla2x00_version_str); 8296 ret = pci_register_driver(&qla2xxx_pci_driver); 8297 if (ret) { 8298 ql_log(ql_log_fatal, NULL, 0x0006, 8299 "pci_register_driver failed...ret=%d Failing load!.\n", 8300 ret); 8301 goto release_vport_transport; 8302 } 8303 return ret; 8304 8305 release_vport_transport: 8306 fc_release_transport(qla2xxx_transport_vport_template); 8307 8308 unreg_chrdev: 8309 if (apidev_major >= 0) 8310 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8311 fc_release_transport(qla2xxx_transport_template); 8312 8313 qlt_exit: 8314 qlt_exit(); 8315 8316 destroy_cache: 8317 kmem_cache_destroy(srb_cachep); 8318 8319 qla_trace_uninit(); 8320 return ret; 8321 } 8322 8323 /** 8324 * qla2x00_module_exit - Module cleanup. 8325 **/ 8326 static void __exit 8327 qla2x00_module_exit(void) 8328 { 8329 pci_unregister_driver(&qla2xxx_pci_driver); 8330 qla2x00_release_firmware(); 8331 kmem_cache_destroy(ctx_cachep); 8332 fc_release_transport(qla2xxx_transport_vport_template); 8333 if (apidev_major >= 0) 8334 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8335 fc_release_transport(qla2xxx_transport_template); 8336 qlt_exit(); 8337 kmem_cache_destroy(srb_cachep); 8338 qla_trace_uninit(); 8339 } 8340 8341 module_init(qla2x00_module_init); 8342 module_exit(qla2x00_module_exit); 8343 8344 MODULE_AUTHOR("QLogic Corporation"); 8345 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8346 MODULE_LICENSE("GPL"); 8347 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8348 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8349 MODULE_FIRMWARE(FW_FILE_ISP2300); 8350 MODULE_FIRMWARE(FW_FILE_ISP2322); 8351 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8352 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8353