1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QLA_NX2_H 9 #define __QLA_NX2_H 10 11 #define QSNT_ACK_TOV 30 12 #define INTENT_TO_RECOVER 0x01 13 #define PROCEED_TO_RECOVER 0x02 14 #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C 15 #define IDC_LOCK_RECOVERY_STATE_MASK 0x3 16 #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2 17 18 #define QLA8044_DRV_LOCK_MSLEEP 200 19 #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL) 20 #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 21 22 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0 23 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4 24 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0 25 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4 26 27 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 28 #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE) 29 #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \ 30 MIU_TA_CTL_START) 31 #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE) 32 33 /* Imbus address bit used to indicate a host address. This bit is 34 * eliminated by the pcie bar and bar select before presentation 35 * over pcie. */ 36 /* host memory via IMBUS */ 37 #define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL) 38 #define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL) 39 #define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 40 #define QLA8044_ADDR_OCM0 (0x0000000200000000ULL) 41 #define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL) 42 #define QLA8044_ADDR_OCM1 (0x0000000200400000ULL) 43 #define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL) 44 #define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL) 45 #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 46 #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 47 #define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL) 48 #define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000) 49 #define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000) 50 #define QLA8044_PCI_CAMQM ((unsigned long)0x04800000) 51 #define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff) 52 #define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000) 53 #define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000) 54 #define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff) 55 56 /* PCI Windowing for DDR regions. */ 57 static inline bool addr_in_range(u64 addr, u64 low, u64 high) 58 { 59 return addr <= high && addr >= low; 60 } 61 62 /* Indirectly Mapped Registers */ 63 #define QLA8044_FLASH_SPI_STATUS 0x2808E010 64 #define QLA8044_FLASH_SPI_CONTROL 0x2808E014 65 #define QLA8044_FLASH_STATUS 0x42100004 66 #define QLA8044_FLASH_CONTROL 0x42110004 67 #define QLA8044_FLASH_ADDR 0x42110008 68 #define QLA8044_FLASH_WRDATA 0x4211000C 69 #define QLA8044_FLASH_RDDATA 0x42110018 70 #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030 71 #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 72 73 /* Flash access regs */ 74 #define QLA8044_FLASH_LOCK 0x3850 75 #define QLA8044_FLASH_UNLOCK 0x3854 76 #define QLA8044_FLASH_LOCK_ID 0x3500 77 78 /* Driver Lock regs */ 79 #define QLA8044_DRV_LOCK 0x3868 80 #define QLA8044_DRV_UNLOCK 0x386C 81 #define QLA8044_DRV_LOCK_ID 0x3504 82 #define QLA8044_DRV_LOCKRECOVERY 0x379C 83 84 /* IDC version */ 85 #define QLA8044_IDC_VER_MAJ_VALUE 0x1 86 #define QLA8044_IDC_VER_MIN_VALUE 0x0 87 88 /* IDC Registers : Driver Coexistence Defines */ 89 #define QLA8044_CRB_IDC_VER_MAJOR 0x3780 90 #define QLA8044_CRB_IDC_VER_MINOR 0x3798 91 #define QLA8044_IDC_DRV_AUDIT 0x3794 92 #define QLA8044_SRE_SHIM_CONTROL 0x0D200284 93 #define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4 94 #define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4 95 #define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388 96 #define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388 97 #define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C 98 #define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C 99 #define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704 100 #define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704 101 102 /* set value to pause threshold value */ 103 #define QLA8044_SET_PAUSE_VAL 0x0 104 #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF 105 #define QLA8044_PEG_HALT_STATUS1 0x34A8 106 #define QLA8044_PEG_HALT_STATUS2 0x34AC 107 #define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */ 108 #define QLA8044_FW_CAPABILITIES 0x3528 109 #define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */ 110 #define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */ 111 #define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */ 112 #define QLA8044_CRB_DRV_SCRATCH 0x3548 113 #define QLA8044_CRB_DEV_PART_INFO1 0x37E0 114 #define QLA8044_CRB_DEV_PART_INFO2 0x37E4 115 #define QLA8044_FW_VER_MAJOR 0x3550 116 #define QLA8044_FW_VER_MINOR 0x3554 117 #define QLA8044_FW_VER_SUB 0x3558 118 #define QLA8044_NPAR_STATE 0x359C 119 #define QLA8044_FW_IMAGE_VALID 0x35FC 120 #define QLA8044_CMDPEG_STATE 0x3650 121 #define QLA8044_ASIC_TEMP 0x37B4 122 #define QLA8044_FW_API 0x356C 123 #define QLA8044_DRV_OP_MODE 0x3570 124 #define QLA8044_CRB_WIN_BASE 0x3800 125 #define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4)) 126 #define QLA8044_SEM_LOCK_BASE 0x3840 127 #define QLA8044_SEM_UNLOCK_BASE 0x3844 128 #define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8)) 129 #define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8)) 130 #define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 131 #define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 132 #define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4)) 133 #define QLA8044_LINK_SPEED_FACTOR 10 134 #define QLA8044_FUN7_ACTIVE_INDEX 0x80 135 136 /* FLASH API Defines */ 137 #define QLA8044_FLASH_MAX_WAIT_USEC 100 138 #define QLA8044_FLASH_LOCK_TIMEOUT 10000 139 #define QLA8044_FLASH_SECTOR_SIZE 65536 140 #define QLA8044_DRV_LOCK_TIMEOUT 2000 141 #define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 142 #define QLA8044_FLASH_WRITE_CMD 0xdacdacda 143 #define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca 144 #define QLA8044_FLASH_READ_RETRY_COUNT 2000 145 #define QLA8044_FLASH_STATUS_READY 0x6 146 #define QLA8044_FLASH_BUFFER_WRITE_MIN 2 147 #define QLA8044_FLASH_BUFFER_WRITE_MAX 64 148 #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1 149 #define QLA8044_ERASE_MODE 1 150 #define QLA8044_WRITE_MODE 2 151 #define QLA8044_DWORD_WRITE_MODE 3 152 #define QLA8044_GLOBAL_RESET 0x38CC 153 #define QLA8044_WILDCARD 0x38F0 154 #define QLA8044_INFORMANT 0x38FC 155 #define QLA8044_HOST_MBX_CTRL 0x3038 156 #define QLA8044_FW_MBX_CTRL 0x303C 157 #define QLA8044_BOOTLOADER_ADDR 0x355C 158 #define QLA8044_BOOTLOADER_SIZE 0x3560 159 #define QLA8044_FW_IMAGE_ADDR 0x3564 160 #define QLA8044_MBX_INTR_ENABLE 0x1000 161 #define QLA8044_MBX_INTR_MASK 0x1200 162 163 /* IDC Control Register bit defines */ 164 #define DONTRESET_BIT0 0x1 165 #define GRACEFUL_RESET_BIT1 0x2 166 167 /* ISP8044 PEG_HALT_STATUS1 bits */ 168 #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29) 169 #define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29) 170 #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29) 171 172 /* Firmware image definitions */ 173 #define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000 174 #define QLA8044_BOOT_FROM_FLASH 0 175 #define QLA8044_IDC_PARAM_ADDR 0x3e8020 176 177 /* FLASH related definitions */ 178 #define QLA8044_OPTROM_BURST_SIZE 0x100 179 #define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4) 180 #define QLA8044_MIN_OPTROM_BURST_DWORDS 2 181 #define QLA8044_SECTOR_SIZE (64 * 1024) 182 183 #define QLA8044_FLASH_SPI_CTL 0x4 184 #define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000 185 #define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001 186 #define QLA8044_FLASH_FIRST_MS_PATTERN 0x43 187 #define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F 188 #define QLA8044_FLASH_LAST_MS_PATTERN 0x7D 189 #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100 190 #define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5 191 #define QLA8044_FLASH_ERASE_SIG 0xFD0300 192 #define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D 193 194 /* Reset template definitions */ 195 #define QLA8044_MAX_RESET_SEQ_ENTRIES 16 196 #define QLA8044_RESTART_TEMPLATE_SIZE 0x2000 197 #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000 198 #define QLA8044_RESET_SEQ_VERSION 0x0101 199 200 /* Reset template entry opcodes */ 201 #define OPCODE_NOP 0x0000 202 #define OPCODE_WRITE_LIST 0x0001 203 #define OPCODE_READ_WRITE_LIST 0x0002 204 #define OPCODE_POLL_LIST 0x0004 205 #define OPCODE_POLL_WRITE_LIST 0x0008 206 #define OPCODE_READ_MODIFY_WRITE 0x0010 207 #define OPCODE_SEQ_PAUSE 0x0020 208 #define OPCODE_SEQ_END 0x0040 209 #define OPCODE_TMPL_END 0x0080 210 #define OPCODE_POLL_READ_LIST 0x0100 211 212 /* Template Header */ 213 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE 214 #define QLA8044_IDC_DRV_CTRL 0x3790 215 #define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */ 216 217 #define MINIDUMP_SIZE_36K 36864 218 219 struct qla8044_reset_template_hdr { 220 uint16_t version; 221 uint16_t signature; 222 uint16_t size; 223 uint16_t entries; 224 uint16_t hdr_size; 225 uint16_t checksum; 226 uint16_t init_seq_offset; 227 uint16_t start_seq_offset; 228 } __packed; 229 230 /* Common Entry Header. */ 231 struct qla8044_reset_entry_hdr { 232 uint16_t cmd; 233 uint16_t size; 234 uint16_t count; 235 uint16_t delay; 236 } __packed; 237 238 /* Generic poll entry type. */ 239 struct qla8044_poll { 240 uint32_t test_mask; 241 uint32_t test_value; 242 } __packed; 243 244 /* Read modify write entry type. */ 245 struct qla8044_rmw { 246 uint32_t test_mask; 247 uint32_t xor_value; 248 uint32_t or_value; 249 uint8_t shl; 250 uint8_t shr; 251 uint8_t index_a; 252 uint8_t rsvd; 253 } __packed; 254 255 /* Generic Entry Item with 2 DWords. */ 256 struct qla8044_entry { 257 uint32_t arg1; 258 uint32_t arg2; 259 } __packed; 260 261 /* Generic Entry Item with 4 DWords.*/ 262 struct qla8044_quad_entry { 263 uint32_t dr_addr; 264 uint32_t dr_value; 265 uint32_t ar_addr; 266 uint32_t ar_value; 267 } __packed; 268 269 struct qla8044_reset_template { 270 int seq_index; 271 int seq_error; 272 int array_index; 273 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES]; 274 uint8_t *buff; 275 uint8_t *stop_offset; 276 uint8_t *start_offset; 277 uint8_t *init_offset; 278 struct qla8044_reset_template_hdr *hdr; 279 uint8_t seq_end; 280 uint8_t template_end; 281 }; 282 283 /* Driver_code is for driver to write some info about the entry 284 * currently not used. 285 */ 286 struct qla8044_minidump_entry_hdr { 287 uint32_t entry_type; 288 uint32_t entry_size; 289 uint32_t entry_capture_size; 290 struct { 291 uint8_t entry_capture_mask; 292 uint8_t entry_code; 293 uint8_t driver_code; 294 uint8_t driver_flags; 295 } d_ctrl; 296 } __packed; 297 298 /* Read CRB entry header */ 299 struct qla8044_minidump_entry_crb { 300 struct qla8044_minidump_entry_hdr h; 301 uint32_t addr; 302 struct { 303 uint8_t addr_stride; 304 uint8_t state_index_a; 305 uint16_t poll_timeout; 306 } crb_strd; 307 uint32_t data_size; 308 uint32_t op_count; 309 310 struct { 311 uint8_t opcode; 312 uint8_t state_index_v; 313 uint8_t shl; 314 uint8_t shr; 315 } crb_ctrl; 316 317 uint32_t value_1; 318 uint32_t value_2; 319 uint32_t value_3; 320 } __packed; 321 322 struct qla8044_minidump_entry_cache { 323 struct qla8044_minidump_entry_hdr h; 324 uint32_t tag_reg_addr; 325 struct { 326 uint16_t tag_value_stride; 327 uint16_t init_tag_value; 328 } addr_ctrl; 329 uint32_t data_size; 330 uint32_t op_count; 331 uint32_t control_addr; 332 struct { 333 uint16_t write_value; 334 uint8_t poll_mask; 335 uint8_t poll_wait; 336 } cache_ctrl; 337 uint32_t read_addr; 338 struct { 339 uint8_t read_addr_stride; 340 uint8_t read_addr_cnt; 341 uint16_t rsvd_1; 342 } read_ctrl; 343 } __packed; 344 345 /* Read OCM */ 346 struct qla8044_minidump_entry_rdocm { 347 struct qla8044_minidump_entry_hdr h; 348 uint32_t rsvd_0; 349 uint32_t rsvd_1; 350 uint32_t data_size; 351 uint32_t op_count; 352 uint32_t rsvd_2; 353 uint32_t rsvd_3; 354 uint32_t read_addr; 355 uint32_t read_addr_stride; 356 } __packed; 357 358 /* Read Memory */ 359 struct qla8044_minidump_entry_rdmem { 360 struct qla8044_minidump_entry_hdr h; 361 uint32_t rsvd[6]; 362 uint32_t read_addr; 363 uint32_t read_data_size; 364 }; 365 366 /* Read Memory: For Pex-DMA */ 367 struct qla8044_minidump_entry_rdmem_pex_dma { 368 struct qla8044_minidump_entry_hdr h; 369 uint32_t desc_card_addr; 370 uint16_t dma_desc_cmd; 371 uint8_t rsvd[2]; 372 uint32_t start_dma_cmd; 373 uint8_t rsvd2[12]; 374 uint32_t read_addr; 375 uint32_t read_data_size; 376 } __packed; 377 378 /* Read ROM */ 379 struct qla8044_minidump_entry_rdrom { 380 struct qla8044_minidump_entry_hdr h; 381 uint32_t rsvd[6]; 382 uint32_t read_addr; 383 uint32_t read_data_size; 384 } __packed; 385 386 /* Mux entry */ 387 struct qla8044_minidump_entry_mux { 388 struct qla8044_minidump_entry_hdr h; 389 uint32_t select_addr; 390 uint32_t rsvd_0; 391 uint32_t data_size; 392 uint32_t op_count; 393 uint32_t select_value; 394 uint32_t select_value_stride; 395 uint32_t read_addr; 396 uint32_t rsvd_1; 397 } __packed; 398 399 /* Queue entry */ 400 struct qla8044_minidump_entry_queue { 401 struct qla8044_minidump_entry_hdr h; 402 uint32_t select_addr; 403 struct { 404 uint16_t queue_id_stride; 405 uint16_t rsvd_0; 406 } q_strd; 407 uint32_t data_size; 408 uint32_t op_count; 409 uint32_t rsvd_1; 410 uint32_t rsvd_2; 411 uint32_t read_addr; 412 struct { 413 uint8_t read_addr_stride; 414 uint8_t read_addr_cnt; 415 uint16_t rsvd_3; 416 } rd_strd; 417 } __packed; 418 419 /* POLLRD Entry */ 420 struct qla8044_minidump_entry_pollrd { 421 struct qla8044_minidump_entry_hdr h; 422 uint32_t select_addr; 423 uint32_t read_addr; 424 uint32_t select_value; 425 uint16_t select_value_stride; 426 uint16_t op_count; 427 uint32_t poll_wait; 428 uint32_t poll_mask; 429 uint32_t data_size; 430 uint32_t rsvd_1; 431 } __packed; 432 433 struct qla8044_minidump_entry_rddfe { 434 struct qla8044_minidump_entry_hdr h; 435 uint32_t addr_1; 436 uint32_t value; 437 uint8_t stride; 438 uint8_t stride2; 439 uint16_t count; 440 uint32_t poll; 441 uint32_t mask; 442 uint32_t modify_mask; 443 uint32_t data_size; 444 uint32_t rsvd; 445 446 } __packed; 447 448 struct qla8044_minidump_entry_rdmdio { 449 struct qla8044_minidump_entry_hdr h; 450 451 uint32_t addr_1; 452 uint32_t addr_2; 453 uint32_t value_1; 454 uint8_t stride_1; 455 uint8_t stride_2; 456 uint16_t count; 457 uint32_t poll; 458 uint32_t mask; 459 uint32_t value_2; 460 uint32_t data_size; 461 462 } __packed; 463 464 struct qla8044_minidump_entry_pollwr { 465 struct qla8044_minidump_entry_hdr h; 466 uint32_t addr_1; 467 uint32_t addr_2; 468 uint32_t value_1; 469 uint32_t value_2; 470 uint32_t poll; 471 uint32_t mask; 472 uint32_t data_size; 473 uint32_t rsvd; 474 475 } __packed; 476 477 /* RDMUX2 Entry */ 478 struct qla8044_minidump_entry_rdmux2 { 479 struct qla8044_minidump_entry_hdr h; 480 uint32_t select_addr_1; 481 uint32_t select_addr_2; 482 uint32_t select_value_1; 483 uint32_t select_value_2; 484 uint32_t op_count; 485 uint32_t select_value_mask; 486 uint32_t read_addr; 487 uint8_t select_value_stride; 488 uint8_t data_size; 489 uint8_t rsvd[2]; 490 } __packed; 491 492 /* POLLRDMWR Entry */ 493 struct qla8044_minidump_entry_pollrdmwr { 494 struct qla8044_minidump_entry_hdr h; 495 uint32_t addr_1; 496 uint32_t addr_2; 497 uint32_t value_1; 498 uint32_t value_2; 499 uint32_t poll_wait; 500 uint32_t poll_mask; 501 uint32_t modify_mask; 502 uint32_t data_size; 503 } __packed; 504 505 /* IDC additional information */ 506 struct qla8044_idc_information { 507 uint32_t request_desc; /* IDC request descriptor */ 508 uint32_t info1; /* IDC additional info */ 509 uint32_t info2; /* IDC additional info */ 510 uint32_t info3; /* IDC additional info */ 511 } __packed; 512 513 enum qla_regs { 514 QLA8044_PEG_HALT_STATUS1_INDEX = 0, 515 QLA8044_PEG_HALT_STATUS2_INDEX, 516 QLA8044_PEG_ALIVE_COUNTER_INDEX, 517 QLA8044_CRB_DRV_ACTIVE_INDEX, 518 QLA8044_CRB_DEV_STATE_INDEX, 519 QLA8044_CRB_DRV_STATE_INDEX, 520 QLA8044_CRB_DRV_SCRATCH_INDEX, 521 QLA8044_CRB_DEV_PART_INFO_INDEX, 522 QLA8044_CRB_DRV_IDC_VERSION_INDEX, 523 QLA8044_FW_VERSION_MAJOR_INDEX, 524 QLA8044_FW_VERSION_MINOR_INDEX, 525 QLA8044_FW_VERSION_SUB_INDEX, 526 QLA8044_CRB_CMDPEG_STATE_INDEX, 527 QLA8044_CRB_TEMP_STATE_INDEX, 528 } __packed; 529 530 #define CRB_REG_INDEX_MAX 14 531 #define CRB_CMDPEG_CHECK_RETRY_COUNT 60 532 #define CRB_CMDPEG_CHECK_DELAY 500 533 534 /* MiniDump Structures */ 535 536 /* Driver_code is for driver to write some info about the entry 537 * currently not used. 538 */ 539 #define QLA8044_SS_OCM_WNDREG_INDEX 3 540 #define QLA8044_DBG_STATE_ARRAY_LEN 16 541 #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8 542 #define QLA8044_DBG_RSVD_ARRAY_LEN 8 543 #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16 544 #define QLA8044_SS_PCI_INDEX 0 545 #define QLA8044_RDDFE 38 546 #define QLA8044_RDMDIO 39 547 #define QLA8044_POLLWR 40 548 549 struct qla8044_minidump_template_hdr { 550 uint32_t entry_type; 551 uint32_t first_entry_offset; 552 uint32_t size_of_template; 553 uint32_t capture_debug_level; 554 uint32_t num_of_entries; 555 uint32_t version; 556 uint32_t driver_timestamp; 557 uint32_t checksum; 558 559 uint32_t driver_capture_mask; 560 uint32_t driver_info_word2; 561 uint32_t driver_info_word3; 562 uint32_t driver_info_word4; 563 564 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN]; 565 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN]; 566 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN]; 567 }; 568 569 struct qla8044_pex_dma_descriptor { 570 struct { 571 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */ 572 uint8_t rsvd[2]; 573 uint16_t dma_desc_cmd; 574 } cmd; 575 uint64_t src_addr; 576 uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/ 577 uint8_t rsvd[24]; 578 } __packed; 579 580 #endif 581