1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_NX_H 7 #define __QLA_NX_H 8 9 #include <scsi/scsi.h> 10 11 /* 12 * Following are the states of the Phantom. Phantom will set them and 13 * Host will read to check if the fields are correct. 14 */ 15 #define PHAN_INITIALIZE_FAILED 0xffff 16 #define PHAN_INITIALIZE_COMPLETE 0xff01 17 18 /* Host writes the following to notify that it has done the init-handshake */ 19 #define PHAN_INITIALIZE_ACK 0xf00f 20 #define PHAN_PEG_RCV_INITIALIZED 0xff01 21 22 /*CRB_RELATED*/ 23 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200) 24 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X)) 25 26 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50) 27 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c) 28 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54) 29 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc) 30 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4) 31 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555 32 33 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05 34 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E 35 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03 36 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01 37 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06 38 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07 39 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08 40 41 /* Hub 0 */ 42 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15 43 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25 44 45 /* Hub 1 */ 46 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73 47 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00 48 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b 49 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01 50 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02 51 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03 52 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04 53 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58 54 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59 55 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a 56 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a 57 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c 58 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f 59 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12 60 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18 61 62 /* Hub 2 */ 63 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31 64 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19 65 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29 66 67 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10 68 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20 69 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22 70 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21 71 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66 72 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60 73 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61 74 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62 75 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63 76 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09 77 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d 78 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e 79 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11 80 81 /* Hub 3 */ 82 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A 83 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50 84 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51 85 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08 86 87 /* Hub 4 */ 88 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40 89 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41 90 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42 91 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43 92 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44 93 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45 94 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46 95 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47 96 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48 97 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49 98 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a 99 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b 100 101 /* Hub 5 */ 102 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40 103 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41 104 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42 105 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43 106 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44 107 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45 108 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46 109 110 /* Hub 6 */ 111 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46 112 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47 113 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48 114 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49 115 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16 116 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17 117 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05 118 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06 119 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07 120 121 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 122 /* */ 123 #define QLA82XX_HW_PX_MAP_CRB_PH 0 124 #define QLA82XX_HW_PX_MAP_CRB_PS 1 125 #define QLA82XX_HW_PX_MAP_CRB_MN 2 126 #define QLA82XX_HW_PX_MAP_CRB_MS 3 127 #define QLA82XX_HW_PX_MAP_CRB_SRE 5 128 #define QLA82XX_HW_PX_MAP_CRB_NIU 6 129 #define QLA82XX_HW_PX_MAP_CRB_QMN 7 130 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8 131 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9 132 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10 133 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11 134 #define QLA82XX_HW_PX_MAP_CRB_QMS 12 135 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13 136 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14 137 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15 138 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16 139 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17 140 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18 141 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19 142 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20 143 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2 144 #define QLA82XX_HW_PX_MAP_CRB_PGND 21 145 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22 146 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23 147 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24 148 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25 149 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26 150 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27 151 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28 152 #define QLA82XX_HW_PX_MAP_CRB_SN 29 153 #define QLA82XX_HW_PX_MAP_CRB_EG 31 154 #define QLA82XX_HW_PX_MAP_CRB_PH2 32 155 #define QLA82XX_HW_PX_MAP_CRB_PS2 33 156 #define QLA82XX_HW_PX_MAP_CRB_CAM 34 157 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35 158 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36 159 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37 160 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38 161 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39 162 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40 163 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42 164 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43 165 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44 166 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45 167 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46 168 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47 169 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48 170 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49 171 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50 172 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51 173 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52 174 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53 175 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54 176 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55 177 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56 178 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57 179 #define QLA82XX_HW_PX_MAP_CRB_SMB 58 180 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59 181 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60 182 #define QLA82XX_HW_PX_MAP_CRB_LPC 61 183 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62 184 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63 185 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4 186 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30 187 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41 188 189 /* This field defines CRB adr [31:20] of the agents */ 190 /* */ 191 192 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 193 QLA82XX_HW_MN_CRB_AGT_ADR) 194 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 195 QLA82XX_HW_PH_CRB_AGT_ADR) 196 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 197 QLA82XX_HW_MS_CRB_AGT_ADR) 198 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 199 QLA82XX_HW_PS_CRB_AGT_ADR) 200 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 201 QLA82XX_HW_SS_CRB_AGT_ADR) 202 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 203 QLA82XX_HW_RPMX3_CRB_AGT_ADR) 204 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 205 QLA82XX_HW_QMS_CRB_AGT_ADR) 206 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 207 QLA82XX_HW_SQGS0_CRB_AGT_ADR) 208 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 209 QLA82XX_HW_SQGS1_CRB_AGT_ADR) 210 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 211 QLA82XX_HW_SQGS2_CRB_AGT_ADR) 212 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 213 QLA82XX_HW_SQGS3_CRB_AGT_ADR) 214 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 215 QLA82XX_HW_C2C0_CRB_AGT_ADR) 216 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 217 QLA82XX_HW_C2C1_CRB_AGT_ADR) 218 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 219 QLA82XX_HW_RPMX2_CRB_AGT_ADR) 220 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 221 QLA82XX_HW_RPMX4_CRB_AGT_ADR) 222 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 223 QLA82XX_HW_RPMX7_CRB_AGT_ADR) 224 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 225 QLA82XX_HW_RPMX9_CRB_AGT_ADR) 226 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 227 QLA82XX_HW_SMB_CRB_AGT_ADR) 228 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 229 QLA82XX_HW_NIU_CRB_AGT_ADR) 230 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 231 QLA82XX_HW_I2C0_CRB_AGT_ADR) 232 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 233 QLA82XX_HW_I2C1_CRB_AGT_ADR) 234 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 235 QLA82XX_HW_SRE_CRB_AGT_ADR) 236 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 237 QLA82XX_HW_EG_CRB_AGT_ADR) 238 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 239 QLA82XX_HW_RPMX0_CRB_AGT_ADR) 240 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 241 QLA82XX_HW_QM_CRB_AGT_ADR) 242 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 243 QLA82XX_HW_SQG0_CRB_AGT_ADR) 244 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 245 QLA82XX_HW_SQG1_CRB_AGT_ADR) 246 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 247 QLA82XX_HW_SQG2_CRB_AGT_ADR) 248 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 249 QLA82XX_HW_SQG3_CRB_AGT_ADR) 250 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 251 QLA82XX_HW_RPMX1_CRB_AGT_ADR) 252 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 253 QLA82XX_HW_RPMX5_CRB_AGT_ADR) 254 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 255 QLA82XX_HW_RPMX6_CRB_AGT_ADR) 256 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 257 QLA82XX_HW_RPMX8_CRB_AGT_ADR) 258 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 259 QLA82XX_HW_CAS0_CRB_AGT_ADR) 260 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 261 QLA82XX_HW_CAS1_CRB_AGT_ADR) 262 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 263 QLA82XX_HW_CAS2_CRB_AGT_ADR) 264 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 265 QLA82XX_HW_CAS3_CRB_AGT_ADR) 266 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 267 QLA82XX_HW_PEGNI_CRB_AGT_ADR) 268 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 269 QLA82XX_HW_PEGND_CRB_AGT_ADR) 270 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 271 QLA82XX_HW_PEGN0_CRB_AGT_ADR) 272 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 273 QLA82XX_HW_PEGN1_CRB_AGT_ADR) 274 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 275 QLA82XX_HW_PEGN2_CRB_AGT_ADR) 276 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 277 QLA82XX_HW_PEGN3_CRB_AGT_ADR) 278 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 279 QLA82XX_HW_PEGN4_CRB_AGT_ADR) 280 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 281 QLA82XX_HW_PEGNC_CRB_AGT_ADR) 282 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 283 QLA82XX_HW_PEGR0_CRB_AGT_ADR) 284 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 285 QLA82XX_HW_PEGR1_CRB_AGT_ADR) 286 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 287 QLA82XX_HW_PEGR2_CRB_AGT_ADR) 288 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 289 QLA82XX_HW_PEGR3_CRB_AGT_ADR) 290 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 291 QLA82XX_HW_PEGSI_CRB_AGT_ADR) 292 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 293 QLA82XX_HW_PEGSD_CRB_AGT_ADR) 294 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 295 QLA82XX_HW_PEGS0_CRB_AGT_ADR) 296 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 297 QLA82XX_HW_PEGS1_CRB_AGT_ADR) 298 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 299 QLA82XX_HW_PEGS2_CRB_AGT_ADR) 300 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 301 QLA82XX_HW_PEGS3_CRB_AGT_ADR) 302 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 303 QLA82XX_HW_PEGSC_CRB_AGT_ADR) 304 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 305 QLA82XX_HW_NCM_CRB_AGT_ADR) 306 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 307 QLA82XX_HW_TMR_CRB_AGT_ADR) 308 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 309 QLA82XX_HW_XDMA_CRB_AGT_ADR) 310 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 311 QLA82XX_HW_SN_CRB_AGT_ADR) 312 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 313 QLA82XX_HW_I2Q_CRB_AGT_ADR) 314 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 315 QLA82XX_HW_ROMUSB_CRB_AGT_ADR) 316 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 317 QLA82XX_HW_OCM0_CRB_AGT_ADR) 318 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 319 QLA82XX_HW_OCM1_CRB_AGT_ADR) 320 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 321 QLA82XX_HW_LPC_CRB_AGT_ADR) 322 323 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000) 324 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 325 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 326 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 327 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 328 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 329 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 330 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 331 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 332 333 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000) 334 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 335 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 336 337 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 338 #define QLA82XX_PCI_CRB_WINDOW(A) \ 339 (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE) 340 #define QLA82XX_CRB_C2C_0 \ 341 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0) 342 #define QLA82XX_CRB_C2C_1 \ 343 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1) 344 #define QLA82XX_CRB_C2C_2 \ 345 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2) 346 #define QLA82XX_CRB_CAM \ 347 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM) 348 #define QLA82XX_CRB_CASPER \ 349 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS) 350 #define QLA82XX_CRB_CASPER_0 \ 351 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0) 352 #define QLA82XX_CRB_CASPER_1 \ 353 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1) 354 #define QLA82XX_CRB_CASPER_2 \ 355 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2) 356 #define QLA82XX_CRB_DDR_MD \ 357 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS) 358 #define QLA82XX_CRB_DDR_NET \ 359 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN) 360 #define QLA82XX_CRB_EPG \ 361 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG) 362 #define QLA82XX_CRB_I2Q \ 363 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q) 364 #define QLA82XX_CRB_NIU \ 365 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU) 366 367 #define QLA82XX_CRB_PCIX_HOST \ 368 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH) 369 #define QLA82XX_CRB_PCIX_HOST2 \ 370 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2) 371 #define QLA82XX_CRB_PCIX_MD \ 372 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS) 373 #define QLA82XX_CRB_PCIE \ 374 QLA82XX_CRB_PCIX_MD 375 376 /* window 1 pcie slot */ 377 #define QLA82XX_CRB_PCIE2 \ 378 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2) 379 #define QLA82XX_CRB_PEG_MD_0 \ 380 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0) 381 #define QLA82XX_CRB_PEG_MD_1 \ 382 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1) 383 #define QLA82XX_CRB_PEG_MD_2 \ 384 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2) 385 #define QLA82XX_CRB_PEG_MD_3 \ 386 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 387 #define QLA82XX_CRB_PEG_MD_3 \ 388 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 389 #define QLA82XX_CRB_PEG_MD_D \ 390 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD) 391 #define QLA82XX_CRB_PEG_MD_I \ 392 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI) 393 #define QLA82XX_CRB_PEG_NET_0 \ 394 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0) 395 #define QLA82XX_CRB_PEG_NET_1 \ 396 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1) 397 #define QLA82XX_CRB_PEG_NET_2 \ 398 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2) 399 #define QLA82XX_CRB_PEG_NET_3 \ 400 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3) 401 #define QLA82XX_CRB_PEG_NET_4 \ 402 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4) 403 #define QLA82XX_CRB_PEG_NET_D \ 404 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND) 405 #define QLA82XX_CRB_PEG_NET_I \ 406 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI) 407 #define QLA82XX_CRB_PQM_MD \ 408 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS) 409 #define QLA82XX_CRB_PQM_NET \ 410 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN) 411 #define QLA82XX_CRB_QDR_MD \ 412 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS) 413 #define QLA82XX_CRB_QDR_NET \ 414 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN) 415 #define QLA82XX_CRB_ROMUSB \ 416 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB) 417 #define QLA82XX_CRB_RPMX_0 \ 418 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0) 419 #define QLA82XX_CRB_RPMX_1 \ 420 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1) 421 #define QLA82XX_CRB_RPMX_2 \ 422 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2) 423 #define QLA82XX_CRB_RPMX_3 \ 424 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3) 425 #define QLA82XX_CRB_RPMX_4 \ 426 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4) 427 #define QLA82XX_CRB_RPMX_5 \ 428 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5) 429 #define QLA82XX_CRB_RPMX_6 \ 430 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6) 431 #define QLA82XX_CRB_RPMX_7 \ 432 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7) 433 #define QLA82XX_CRB_SQM_MD_0 \ 434 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0) 435 #define QLA82XX_CRB_SQM_MD_1 \ 436 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1) 437 #define QLA82XX_CRB_SQM_MD_2 \ 438 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2) 439 #define QLA82XX_CRB_SQM_MD_3 \ 440 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3) 441 #define QLA82XX_CRB_SQM_NET_0 \ 442 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0) 443 #define QLA82XX_CRB_SQM_NET_1 \ 444 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1) 445 #define QLA82XX_CRB_SQM_NET_2 \ 446 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2) 447 #define QLA82XX_CRB_SQM_NET_3 \ 448 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3) 449 #define QLA82XX_CRB_SRE \ 450 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE) 451 #define QLA82XX_CRB_TIMER \ 452 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR) 453 #define QLA82XX_CRB_XDMA \ 454 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA) 455 #define QLA82XX_CRB_I2C0 \ 456 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0) 457 #define QLA82XX_CRB_I2C1 \ 458 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1) 459 #define QLA82XX_CRB_OCM0 \ 460 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0) 461 #define QLA82XX_CRB_SMB \ 462 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB) 463 #define QLA82XX_CRB_MAX \ 464 QLA82XX_PCI_CRB_WINDOW(64) 465 466 /* 467 * ====================== BASE ADDRESSES ON-CHIP ====================== 468 * Base addresses of major components on-chip. 469 * ====================== BASE ADDRESSES ON-CHIP ====================== 470 */ 471 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) 472 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 473 474 /* Imbus address bit used to indicate a host address. This bit is 475 * eliminated by the pcie bar and bar select before presentation 476 * over pcie. */ 477 /* host memory via IMBUS */ 478 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) 479 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) 480 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 481 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) 482 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) 483 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) 484 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) 485 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) 486 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 487 488 #define QLA82XX_PCI_CRBSPACE 0x06000000UL 489 #define QLA82XX_PCI_DIRECT_CRB 0x04400000UL 490 #define QLA82XX_PCI_CAMQM 0x04800000UL 491 #define QLA82XX_PCI_CAMQM_MAX 0x04ffffffUL 492 #define QLA82XX_PCI_DDR_NET 0x00000000UL 493 #define QLA82XX_PCI_QDR_NET 0x04000000UL 494 #define QLA82XX_PCI_QDR_NET_MAX 0x043fffffUL 495 496 /* 497 * Register offsets for MN 498 */ 499 #define MIU_CONTROL (0x000) 500 #define MIU_TAG (0x004) 501 #define MIU_TEST_AGT_CTRL (0x090) 502 #define MIU_TEST_AGT_ADDR_LO (0x094) 503 #define MIU_TEST_AGT_ADDR_HI (0x098) 504 #define MIU_TEST_AGT_WRDATA_LO (0x0a0) 505 #define MIU_TEST_AGT_WRDATA_HI (0x0a4) 506 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 507 #define MIU_TEST_AGT_RDDATA_LO (0x0a8) 508 #define MIU_TEST_AGT_RDDATA_HI (0x0ac) 509 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 510 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 511 #define MIU_TEST_AGT_UPPER_ADDR(off) (0) 512 513 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 514 #define MIU_TA_CTL_START 1 515 #define MIU_TA_CTL_ENABLE 2 516 #define MIU_TA_CTL_WRITE 4 517 #define MIU_TA_CTL_BUSY 8 518 519 /*CAM RAM */ 520 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000) 521 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) 522 523 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24)) 524 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8)) 525 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac)) 526 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0)) 527 528 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8)) 529 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc)) 530 531 #define HALT_STATUS_UNRECOVERABLE 0x80000000 532 #define HALT_STATUS_RECOVERABLE 0x40000000 533 534 /* Driver Coexistence Defines */ 535 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138)) 536 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140)) 537 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144)) 538 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148)) 539 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 540 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) 541 542 /* Every driver should use these Device State */ 543 #define QLA8XXX_DEV_COLD 1 544 #define QLA8XXX_DEV_INITIALIZING 2 545 #define QLA8XXX_DEV_READY 3 546 #define QLA8XXX_DEV_NEED_RESET 4 547 #define QLA8XXX_DEV_NEED_QUIESCENT 5 548 #define QLA8XXX_DEV_FAILED 6 549 #define QLA8XXX_DEV_QUIESCENT 7 550 #define MAX_STATES 8 /* Increment if new state added */ 551 #define QLA8XXX_BAD_VALUE 0xbad0bad0 552 553 #define QLA82XX_IDC_VERSION 1 554 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30 555 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10 556 557 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100)) 558 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124)) 559 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150)) 560 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154)) 561 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158)) 562 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) 563 564 #define PCIE_SETUP_FUNCTION (0x12040) 565 #define PCIE_SETUP_FUNCTION2 (0x12048) 566 567 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) 568 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) 569 570 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 571 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 572 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */ 573 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */ 574 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 575 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ 576 577 /* Different drive state */ 578 #define QLA82XX_DRVST_NOT_RDY 0 579 #define QLA82XX_DRVST_RST_RDY 1 580 #define QLA82XX_DRVST_QSNT_RDY 2 581 582 /* Different drive active state */ 583 #define QLA82XX_DRV_NOT_ACTIVE 0 584 #define QLA82XX_DRV_ACTIVE 1 585 586 /* 587 * The PCI VendorID and DeviceID for our board. 588 */ 589 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021 590 #define PCI_DEVICE_ID_QLOGIC_ISP8044 0x8044 591 592 #define QLA82XX_MSIX_TBL_SPACE 8192 593 #define QLA82XX_PCI_REG_MSIX_TBL 0x44 594 #define QLA82XX_PCI_MSIX_CONTROL 0x40 595 596 struct crb_128M_2M_sub_block_map { 597 unsigned valid; 598 unsigned start_128M; 599 unsigned end_128M; 600 unsigned start_2M; 601 }; 602 603 struct crb_128M_2M_block_map { 604 struct crb_128M_2M_sub_block_map sub_block[16]; 605 }; 606 607 struct crb_addr_pair { 608 long addr; 609 long data; 610 }; 611 612 #define ADDR_ERROR ((unsigned long) 0xffffffff) 613 #define MAX_CTL_CHECK 1000 614 615 /*************************************************************************** 616 * PCI related defines. 617 **************************************************************************/ 618 619 /* 620 * Interrupt related defines. 621 */ 622 #define PCIX_TARGET_STATUS (0x10118) 623 #define PCIX_TARGET_STATUS_F1 (0x10160) 624 #define PCIX_TARGET_STATUS_F2 (0x10164) 625 #define PCIX_TARGET_STATUS_F3 (0x10168) 626 #define PCIX_TARGET_STATUS_F4 (0x10360) 627 #define PCIX_TARGET_STATUS_F5 (0x10364) 628 #define PCIX_TARGET_STATUS_F6 (0x10368) 629 #define PCIX_TARGET_STATUS_F7 (0x1036c) 630 631 #define PCIX_TARGET_MASK (0x10128) 632 #define PCIX_TARGET_MASK_F1 (0x10170) 633 #define PCIX_TARGET_MASK_F2 (0x10174) 634 #define PCIX_TARGET_MASK_F3 (0x10178) 635 #define PCIX_TARGET_MASK_F4 (0x10370) 636 #define PCIX_TARGET_MASK_F5 (0x10374) 637 #define PCIX_TARGET_MASK_F6 (0x10378) 638 #define PCIX_TARGET_MASK_F7 (0x1037c) 639 640 /* 641 * Message Signaled Interrupts 642 */ 643 #define PCIX_MSI_F0 (0x13000) 644 #define PCIX_MSI_F1 (0x13004) 645 #define PCIX_MSI_F2 (0x13008) 646 #define PCIX_MSI_F3 (0x1300c) 647 #define PCIX_MSI_F4 (0x13010) 648 #define PCIX_MSI_F5 (0x13014) 649 #define PCIX_MSI_F6 (0x13018) 650 #define PCIX_MSI_F7 (0x1301c) 651 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4)) 652 #define PCIX_INT_VECTOR (0x10100) 653 #define PCIX_INT_MASK (0x10104) 654 655 /* 656 * Interrupt state machine and other bits. 657 */ 658 #define PCIE_MISCCFG_RC (0x1206c) 659 660 #define ISR_INT_TARGET_STATUS \ 661 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS)) 662 #define ISR_INT_TARGET_STATUS_F1 \ 663 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 664 #define ISR_INT_TARGET_STATUS_F2 \ 665 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 666 #define ISR_INT_TARGET_STATUS_F3 \ 667 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 668 #define ISR_INT_TARGET_STATUS_F4 \ 669 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 670 #define ISR_INT_TARGET_STATUS_F5 \ 671 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 672 #define ISR_INT_TARGET_STATUS_F6 \ 673 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 674 #define ISR_INT_TARGET_STATUS_F7 \ 675 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 676 677 #define ISR_INT_TARGET_MASK \ 678 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK)) 679 #define ISR_INT_TARGET_MASK_F1 \ 680 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 681 #define ISR_INT_TARGET_MASK_F2 \ 682 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 683 #define ISR_INT_TARGET_MASK_F3 \ 684 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 685 #define ISR_INT_TARGET_MASK_F4 \ 686 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 687 #define ISR_INT_TARGET_MASK_F5 \ 688 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 689 #define ISR_INT_TARGET_MASK_F6 \ 690 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 691 #define ISR_INT_TARGET_MASK_F7 \ 692 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 693 694 #define ISR_INT_VECTOR \ 695 (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR)) 696 #define ISR_INT_MASK \ 697 (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK)) 698 #define ISR_INT_STATE_REG \ 699 (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC)) 700 701 #define ISR_MSI_INT_TRIGGER(FUNC) \ 702 (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 703 704 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 705 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 706 707 /* 708 * PCI Interrupt Vector Values. 709 */ 710 #define PCIX_INT_VECTOR_BIT_F0 0x0080 711 #define PCIX_INT_VECTOR_BIT_F1 0x0100 712 #define PCIX_INT_VECTOR_BIT_F2 0x0200 713 #define PCIX_INT_VECTOR_BIT_F3 0x0400 714 #define PCIX_INT_VECTOR_BIT_F4 0x0800 715 #define PCIX_INT_VECTOR_BIT_F5 0x1000 716 #define PCIX_INT_VECTOR_BIT_F6 0x2000 717 #define PCIX_INT_VECTOR_BIT_F7 0x4000 718 719 struct qla82xx_legacy_intr_set { 720 uint32_t int_vec_bit; 721 uint32_t tgt_status_reg; 722 uint32_t tgt_mask_reg; 723 uint32_t pci_int_reg; 724 }; 725 726 #define QLA82XX_LEGACY_INTR_CONFIG \ 727 { \ 728 { \ 729 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 730 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 731 .tgt_mask_reg = ISR_INT_TARGET_MASK, \ 732 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ 733 \ 734 { \ 735 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 736 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 737 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ 738 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ 739 \ 740 { \ 741 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 742 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 743 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ 744 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ 745 \ 746 { \ 747 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 748 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 749 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ 750 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ 751 \ 752 { \ 753 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 754 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 755 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ 756 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ 757 \ 758 { \ 759 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 760 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 761 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ 762 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ 763 \ 764 { \ 765 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 766 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 767 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ 768 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ 769 \ 770 { \ 771 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 772 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 773 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ 774 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ 775 } 776 777 #define BRDCFG_START 0x4000 778 #define BOOTLD_START 0x10000 779 #define IMAGE_START 0x100000 780 #define FLASH_ADDR_START 0x43000 781 782 /* Magic number to let user know flash is programmed */ 783 #define QLA82XX_BDINFO_MAGIC 0x12345678 784 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128) 785 #define FW_SIZE_OFFSET (0x3e840c) 786 #define QLA82XX_FW_MIN_SIZE 0x3fffff 787 788 /* UNIFIED ROMIMAGE START */ 789 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000 790 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0 791 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6 792 #define QLA82XX_URI_DIR_SECT_FW 0x7 793 794 /* Offsets */ 795 #define QLA82XX_URI_CHIP_REV_OFF 10 796 #define QLA82XX_URI_FLAGS_OFF 11 797 #define QLA82XX_URI_BIOS_VERSION_OFF 12 798 #define QLA82XX_URI_BOOTLD_IDX_OFF 27 799 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29 800 801 struct qla82xx_uri_table_desc{ 802 __le32 findex; 803 __le32 num_entries; 804 __le32 entry_size; 805 __le32 reserved[5]; 806 }; 807 808 struct qla82xx_uri_data_desc{ 809 __le32 findex; 810 __le32 size; 811 __le32 reserved[5]; 812 }; 813 814 /* UNIFIED ROMIMAGE END */ 815 816 #define QLA82XX_UNIFIED_ROMIMAGE 3 817 #define QLA82XX_FLASH_ROMIMAGE 4 818 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff 819 820 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0) 821 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4) 822 823 /* Request and response queue size */ 824 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */ 825 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/ 826 827 /* 828 * ISP 8021 I/O Register Set structure definitions. 829 */ 830 struct device_reg_82xx { 831 __le32 req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */ 832 __le32 rsp_q_in[64]; /* Response Queue In-Pointer. */ 833 __le32 rsp_q_out[64]; /* Response Queue Out-Pointer. */ 834 835 __le16 mailbox_in[32]; /* Mailbox In registers */ 836 __le16 unused_1[32]; 837 __le32 hint; /* Host interrupt register */ 838 #define HINT_MBX_INT_PENDING BIT_0 839 __le16 unused_2[62]; 840 __le16 mailbox_out[32]; /* Mailbox Out registers */ 841 __le32 unused_3[48]; 842 843 __le32 host_status; /* host status */ 844 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 845 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 846 __le32 host_int; /* Interrupt status. */ 847 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */ 848 }; 849 850 struct fcp_cmnd { 851 struct scsi_lun lun; 852 uint8_t crn; 853 uint8_t task_attribute; 854 uint8_t task_management; 855 uint8_t additional_cdb_len; 856 uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */ 857 }; 858 859 struct dsd_dma { 860 struct list_head list; 861 dma_addr_t dsd_list_dma; 862 void *dsd_addr; 863 }; 864 865 #define QLA_DSDS_PER_IOCB 37 866 #define QLA_DSD_SIZE 12 867 struct ct6_dsd { 868 uint16_t fcp_cmnd_len; 869 dma_addr_t fcp_cmnd_dma; 870 struct fcp_cmnd *fcp_cmnd; 871 int dsd_use_cnt; 872 struct list_head dsd_list; 873 }; 874 875 #define MBC_TOGGLE_INTERRUPT 0x10 876 #define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */ 877 #define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */ 878 879 /* Flash offset */ 880 #define FLT_REG_BOOTLOAD_82XX 0x72 881 #define FLT_REG_BOOT_CODE_82XX 0x78 882 #define FLT_REG_FW_82XX 0x74 883 #define FLT_REG_GOLD_FW_82XX 0x75 884 #define FLT_REG_VPD_8XXX 0x81 885 886 #define FA_VPD_SIZE_82XX 0x400 887 888 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 889 890 /****************************************************************************** 891 * 892 * Definitions specific to M25P flash 893 * 894 ******************************************************************************* 895 * Instructions 896 */ 897 #define M25P_INSTR_WREN 0x06 898 #define M25P_INSTR_WRDI 0x04 899 #define M25P_INSTR_RDID 0x9f 900 #define M25P_INSTR_RDSR 0x05 901 #define M25P_INSTR_WRSR 0x01 902 #define M25P_INSTR_READ 0x03 903 #define M25P_INSTR_FAST_READ 0x0b 904 #define M25P_INSTR_PP 0x02 905 #define M25P_INSTR_SE 0xd8 906 #define M25P_INSTR_BE 0xc7 907 #define M25P_INSTR_DP 0xb9 908 #define M25P_INSTR_RES 0xab 909 910 /* Minidump related */ 911 912 /* 913 * Version of the template 914 * 4 Bytes 915 * X.Major.Minor.RELEASE 916 */ 917 #define QLA82XX_MINIDUMP_VERSION 0x10101 918 919 /* 920 * Entry Type Defines 921 */ 922 #define QLA82XX_RDNOP 0 923 #define QLA82XX_RDCRB 1 924 #define QLA82XX_RDMUX 2 925 #define QLA82XX_QUEUE 3 926 #define QLA82XX_BOARD 4 927 #define QLA82XX_RDSRE 5 928 #define QLA82XX_RDOCM 6 929 #define QLA82XX_CACHE 10 930 #define QLA82XX_L1DAT 11 931 #define QLA82XX_L1INS 12 932 #define QLA82XX_L2DTG 21 933 #define QLA82XX_L2ITG 22 934 #define QLA82XX_L2DAT 23 935 #define QLA82XX_L2INS 24 936 #define QLA82XX_RDROM 71 937 #define QLA82XX_RDMEM 72 938 #define QLA82XX_CNTRL 98 939 #define QLA82XX_TLHDR 99 940 #define QLA82XX_RDEND 255 941 #define QLA8044_POLLRD 35 942 #define QLA8044_RDMUX2 36 943 #define QLA8044_L1DTG 8 944 #define QLA8044_L1ITG 9 945 #define QLA8044_POLLRDMWR 37 946 947 /* 948 * Opcodes for Control Entries. 949 * These Flags are bit fields. 950 */ 951 #define QLA82XX_DBG_OPCODE_WR 0x01 952 #define QLA82XX_DBG_OPCODE_RW 0x02 953 #define QLA82XX_DBG_OPCODE_AND 0x04 954 #define QLA82XX_DBG_OPCODE_OR 0x08 955 #define QLA82XX_DBG_OPCODE_POLL 0x10 956 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20 957 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40 958 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80 959 960 /* 961 * Template Header and Entry Header definitions start here. 962 */ 963 964 /* 965 * Template Header 966 * Parts of the template header can be modified by the driver. 967 * These include the saved_state_array, capture_debug_level, driver_timestamp 968 */ 969 970 #define QLA82XX_DBG_STATE_ARRAY_LEN 16 971 #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8 972 #define QLA82XX_DBG_RSVD_ARRAY_LEN 8 973 974 /* 975 * Driver Flags 976 */ 977 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */ 978 #define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */ 979 980 struct qla82xx_md_template_hdr { 981 uint32_t entry_type; 982 uint32_t first_entry_offset; 983 uint32_t size_of_template; 984 uint32_t capture_debug_level; 985 986 uint32_t num_of_entries; 987 uint32_t version; 988 uint32_t driver_timestamp; 989 uint32_t template_checksum; 990 991 uint32_t driver_capture_mask; 992 uint32_t driver_info[3]; 993 994 uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN]; 995 uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN]; 996 997 /* markers_array used to capture some special locations on board */ 998 uint32_t markers_array[QLA82XX_DBG_RSVD_ARRAY_LEN]; 999 uint32_t num_of_free_entries; /* For internal use */ 1000 uint32_t free_entry_offset; /* For internal use */ 1001 uint32_t total_table_size; /* For internal use */ 1002 uint32_t bkup_table_offset; /* For internal use */ 1003 } __packed; 1004 1005 /* 1006 * Entry Header: Common to All Entry Types 1007 */ 1008 1009 /* 1010 * Driver Code is for driver to write some info about the entry. 1011 * Currently not used. 1012 */ 1013 typedef struct qla82xx_md_entry_hdr { 1014 uint32_t entry_type; 1015 uint32_t entry_size; 1016 uint32_t entry_capture_size; 1017 struct { 1018 uint8_t entry_capture_mask; 1019 uint8_t entry_code; 1020 uint8_t driver_code; 1021 uint8_t driver_flags; 1022 } d_ctrl; 1023 } __packed qla82xx_md_entry_hdr_t; 1024 1025 /* 1026 * Read CRB entry header 1027 */ 1028 struct qla82xx_md_entry_crb { 1029 qla82xx_md_entry_hdr_t h; 1030 uint32_t addr; 1031 struct { 1032 uint8_t addr_stride; 1033 uint8_t state_index_a; 1034 uint16_t poll_timeout; 1035 } crb_strd; 1036 1037 uint32_t data_size; 1038 uint32_t op_count; 1039 1040 struct { 1041 uint8_t opcode; 1042 uint8_t state_index_v; 1043 uint8_t shl; 1044 uint8_t shr; 1045 } crb_ctrl; 1046 1047 uint32_t value_1; 1048 uint32_t value_2; 1049 uint32_t value_3; 1050 } __packed; 1051 1052 /* 1053 * Cache entry header 1054 */ 1055 struct qla82xx_md_entry_cache { 1056 qla82xx_md_entry_hdr_t h; 1057 1058 uint32_t tag_reg_addr; 1059 struct { 1060 uint16_t tag_value_stride; 1061 uint16_t init_tag_value; 1062 } addr_ctrl; 1063 1064 uint32_t data_size; 1065 uint32_t op_count; 1066 1067 uint32_t control_addr; 1068 struct { 1069 uint16_t write_value; 1070 uint8_t poll_mask; 1071 uint8_t poll_wait; 1072 } cache_ctrl; 1073 1074 uint32_t read_addr; 1075 struct { 1076 uint8_t read_addr_stride; 1077 uint8_t read_addr_cnt; 1078 uint16_t rsvd_1; 1079 } read_ctrl; 1080 } __packed; 1081 1082 /* 1083 * Read OCM 1084 */ 1085 struct qla82xx_md_entry_rdocm { 1086 qla82xx_md_entry_hdr_t h; 1087 1088 uint32_t rsvd_0; 1089 uint32_t rsvd_1; 1090 uint32_t data_size; 1091 uint32_t op_count; 1092 1093 uint32_t rsvd_2; 1094 uint32_t rsvd_3; 1095 uint32_t read_addr; 1096 uint32_t read_addr_stride; 1097 uint32_t read_addr_cntrl; 1098 } __packed; 1099 1100 /* 1101 * Read Memory 1102 */ 1103 struct qla82xx_md_entry_rdmem { 1104 qla82xx_md_entry_hdr_t h; 1105 uint32_t rsvd[6]; 1106 uint32_t read_addr; 1107 uint32_t read_data_size; 1108 } __packed; 1109 1110 /* 1111 * Read ROM 1112 */ 1113 struct qla82xx_md_entry_rdrom { 1114 qla82xx_md_entry_hdr_t h; 1115 uint32_t rsvd[6]; 1116 uint32_t read_addr; 1117 uint32_t read_data_size; 1118 } __packed; 1119 1120 struct qla82xx_md_entry_mux { 1121 qla82xx_md_entry_hdr_t h; 1122 1123 uint32_t select_addr; 1124 uint32_t rsvd_0; 1125 uint32_t data_size; 1126 uint32_t op_count; 1127 1128 uint32_t select_value; 1129 uint32_t select_value_stride; 1130 uint32_t read_addr; 1131 uint32_t rsvd_1; 1132 } __packed; 1133 1134 struct qla82xx_md_entry_queue { 1135 qla82xx_md_entry_hdr_t h; 1136 1137 uint32_t select_addr; 1138 struct { 1139 uint16_t queue_id_stride; 1140 uint16_t rsvd_0; 1141 } q_strd; 1142 1143 uint32_t data_size; 1144 uint32_t op_count; 1145 uint32_t rsvd_1; 1146 uint32_t rsvd_2; 1147 1148 uint32_t read_addr; 1149 struct { 1150 uint8_t read_addr_stride; 1151 uint8_t read_addr_cnt; 1152 uint16_t rsvd_3; 1153 } rd_strd; 1154 } __packed; 1155 1156 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129 1157 #define RQST_TMPLT_SIZE 0x0 1158 #define RQST_TMPLT 0x1 1159 #define MD_DIRECT_ROM_WINDOW 0x42110030 1160 #define MD_DIRECT_ROM_READ_BASE 0x42150000 1161 #define MD_MIU_TEST_AGT_CTRL 0x41000090 1162 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 1163 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 1164 1165 extern const int MD_MIU_TEST_AGT_RDDATA[4]; 1166 1167 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1 1168 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8 1169 1170 #define qla82xx_get_temp_val(x) ((x) >> 16) 1171 #define qla82xx_get_temp_state(x) ((x) & 0xffff) 1172 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state)) 1173 1174 /* 1175 * Temperature control. 1176 */ 1177 enum { 1178 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */ 1179 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */ 1180 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */ 1181 }; 1182 1183 #define LEG_INTR_PTR_OFFSET 0x38C0 1184 #define LEG_INTR_TRIG_OFFSET 0x38C4 1185 #define LEG_INTR_MASK_OFFSET 0x38C8 1186 #endif 1187