1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_NX_H 8 #define __QLA_NX_H 9 10 /* 11 * Following are the states of the Phantom. Phantom will set them and 12 * Host will read to check if the fields are correct. 13 */ 14 #define PHAN_INITIALIZE_FAILED 0xffff 15 #define PHAN_INITIALIZE_COMPLETE 0xff01 16 17 /* Host writes the following to notify that it has done the init-handshake */ 18 #define PHAN_INITIALIZE_ACK 0xf00f 19 #define PHAN_PEG_RCV_INITIALIZED 0xff01 20 21 /*CRB_RELATED*/ 22 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200) 23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X)) 24 25 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50) 26 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c) 27 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54) 28 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc) 29 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555 30 31 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05 32 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E 33 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03 34 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01 35 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06 36 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07 37 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08 38 39 /* Hub 0 */ 40 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15 41 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25 42 43 /* Hub 1 */ 44 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73 45 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00 46 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b 47 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01 48 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02 49 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03 50 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04 51 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58 52 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59 53 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a 54 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a 55 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c 56 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f 57 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12 58 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18 59 60 /* Hub 2 */ 61 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31 62 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19 63 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29 64 65 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10 66 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20 67 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22 68 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21 69 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66 70 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60 71 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61 72 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62 73 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63 74 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09 75 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d 76 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e 77 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11 78 79 /* Hub 3 */ 80 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A 81 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50 82 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51 83 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08 84 85 /* Hub 4 */ 86 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40 87 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41 88 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42 89 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43 90 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44 91 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45 92 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46 93 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47 94 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48 95 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49 96 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a 97 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b 98 99 /* Hub 5 */ 100 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40 101 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41 102 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42 103 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43 104 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44 105 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45 106 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46 107 108 /* Hub 6 */ 109 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46 110 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47 111 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48 112 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49 113 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16 114 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17 115 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05 116 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06 117 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07 118 119 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 120 /* */ 121 #define QLA82XX_HW_PX_MAP_CRB_PH 0 122 #define QLA82XX_HW_PX_MAP_CRB_PS 1 123 #define QLA82XX_HW_PX_MAP_CRB_MN 2 124 #define QLA82XX_HW_PX_MAP_CRB_MS 3 125 #define QLA82XX_HW_PX_MAP_CRB_SRE 5 126 #define QLA82XX_HW_PX_MAP_CRB_NIU 6 127 #define QLA82XX_HW_PX_MAP_CRB_QMN 7 128 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8 129 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9 130 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10 131 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11 132 #define QLA82XX_HW_PX_MAP_CRB_QMS 12 133 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13 134 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14 135 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15 136 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16 137 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17 138 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18 139 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19 140 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20 141 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2 142 #define QLA82XX_HW_PX_MAP_CRB_PGND 21 143 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22 144 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23 145 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24 146 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25 147 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26 148 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27 149 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28 150 #define QLA82XX_HW_PX_MAP_CRB_SN 29 151 #define QLA82XX_HW_PX_MAP_CRB_EG 31 152 #define QLA82XX_HW_PX_MAP_CRB_PH2 32 153 #define QLA82XX_HW_PX_MAP_CRB_PS2 33 154 #define QLA82XX_HW_PX_MAP_CRB_CAM 34 155 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35 156 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36 157 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37 158 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38 159 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39 160 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40 161 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42 162 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43 163 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44 164 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45 165 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46 166 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47 167 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48 168 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49 169 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50 170 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51 171 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52 172 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53 173 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54 174 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55 175 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56 176 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57 177 #define QLA82XX_HW_PX_MAP_CRB_SMB 58 178 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59 179 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60 180 #define QLA82XX_HW_PX_MAP_CRB_LPC 61 181 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62 182 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63 183 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4 184 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30 185 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41 186 187 /* This field defines CRB adr [31:20] of the agents */ 188 /* */ 189 190 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 191 QLA82XX_HW_MN_CRB_AGT_ADR) 192 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 193 QLA82XX_HW_PH_CRB_AGT_ADR) 194 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 195 QLA82XX_HW_MS_CRB_AGT_ADR) 196 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 197 QLA82XX_HW_PS_CRB_AGT_ADR) 198 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 199 QLA82XX_HW_SS_CRB_AGT_ADR) 200 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 201 QLA82XX_HW_RPMX3_CRB_AGT_ADR) 202 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 203 QLA82XX_HW_QMS_CRB_AGT_ADR) 204 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 205 QLA82XX_HW_SQGS0_CRB_AGT_ADR) 206 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 207 QLA82XX_HW_SQGS1_CRB_AGT_ADR) 208 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 209 QLA82XX_HW_SQGS2_CRB_AGT_ADR) 210 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 211 QLA82XX_HW_SQGS3_CRB_AGT_ADR) 212 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 213 QLA82XX_HW_C2C0_CRB_AGT_ADR) 214 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 215 QLA82XX_HW_C2C1_CRB_AGT_ADR) 216 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 217 QLA82XX_HW_RPMX2_CRB_AGT_ADR) 218 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 219 QLA82XX_HW_RPMX4_CRB_AGT_ADR) 220 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 221 QLA82XX_HW_RPMX7_CRB_AGT_ADR) 222 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 223 QLA82XX_HW_RPMX9_CRB_AGT_ADR) 224 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 225 QLA82XX_HW_SMB_CRB_AGT_ADR) 226 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 227 QLA82XX_HW_NIU_CRB_AGT_ADR) 228 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 229 QLA82XX_HW_I2C0_CRB_AGT_ADR) 230 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 231 QLA82XX_HW_I2C1_CRB_AGT_ADR) 232 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 233 QLA82XX_HW_SRE_CRB_AGT_ADR) 234 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 235 QLA82XX_HW_EG_CRB_AGT_ADR) 236 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 237 QLA82XX_HW_RPMX0_CRB_AGT_ADR) 238 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 239 QLA82XX_HW_QM_CRB_AGT_ADR) 240 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 241 QLA82XX_HW_SQG0_CRB_AGT_ADR) 242 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 243 QLA82XX_HW_SQG1_CRB_AGT_ADR) 244 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 245 QLA82XX_HW_SQG2_CRB_AGT_ADR) 246 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 247 QLA82XX_HW_SQG3_CRB_AGT_ADR) 248 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 249 QLA82XX_HW_RPMX1_CRB_AGT_ADR) 250 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 251 QLA82XX_HW_RPMX5_CRB_AGT_ADR) 252 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 253 QLA82XX_HW_RPMX6_CRB_AGT_ADR) 254 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 255 QLA82XX_HW_RPMX8_CRB_AGT_ADR) 256 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 257 QLA82XX_HW_CAS0_CRB_AGT_ADR) 258 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 259 QLA82XX_HW_CAS1_CRB_AGT_ADR) 260 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 261 QLA82XX_HW_CAS2_CRB_AGT_ADR) 262 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 263 QLA82XX_HW_CAS3_CRB_AGT_ADR) 264 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 265 QLA82XX_HW_PEGNI_CRB_AGT_ADR) 266 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 267 QLA82XX_HW_PEGND_CRB_AGT_ADR) 268 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 269 QLA82XX_HW_PEGN0_CRB_AGT_ADR) 270 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 271 QLA82XX_HW_PEGN1_CRB_AGT_ADR) 272 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 273 QLA82XX_HW_PEGN2_CRB_AGT_ADR) 274 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 275 QLA82XX_HW_PEGN3_CRB_AGT_ADR) 276 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 277 QLA82XX_HW_PEGN4_CRB_AGT_ADR) 278 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 279 QLA82XX_HW_PEGNC_CRB_AGT_ADR) 280 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 281 QLA82XX_HW_PEGR0_CRB_AGT_ADR) 282 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 283 QLA82XX_HW_PEGR1_CRB_AGT_ADR) 284 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 285 QLA82XX_HW_PEGR2_CRB_AGT_ADR) 286 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 287 QLA82XX_HW_PEGR3_CRB_AGT_ADR) 288 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 289 QLA82XX_HW_PEGSI_CRB_AGT_ADR) 290 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 291 QLA82XX_HW_PEGSD_CRB_AGT_ADR) 292 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 293 QLA82XX_HW_PEGS0_CRB_AGT_ADR) 294 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 295 QLA82XX_HW_PEGS1_CRB_AGT_ADR) 296 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 297 QLA82XX_HW_PEGS2_CRB_AGT_ADR) 298 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 299 QLA82XX_HW_PEGS3_CRB_AGT_ADR) 300 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 301 QLA82XX_HW_PEGSC_CRB_AGT_ADR) 302 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 303 QLA82XX_HW_NCM_CRB_AGT_ADR) 304 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 305 QLA82XX_HW_TMR_CRB_AGT_ADR) 306 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 307 QLA82XX_HW_XDMA_CRB_AGT_ADR) 308 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 309 QLA82XX_HW_SN_CRB_AGT_ADR) 310 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 311 QLA82XX_HW_I2Q_CRB_AGT_ADR) 312 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 313 QLA82XX_HW_ROMUSB_CRB_AGT_ADR) 314 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 315 QLA82XX_HW_OCM0_CRB_AGT_ADR) 316 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 317 QLA82XX_HW_OCM1_CRB_AGT_ADR) 318 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 319 QLA82XX_HW_LPC_CRB_AGT_ADR) 320 321 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000) 322 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 323 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 324 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 325 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 326 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 327 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 328 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 329 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 330 331 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000) 332 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 333 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 334 335 /* Lock IDs for ROM lock */ 336 #define ROM_LOCK_DRIVER 0x0d417340 337 338 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 339 #define QLA82XX_PCI_CRB_WINDOW(A) \ 340 (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE) 341 #define QLA82XX_CRB_C2C_0 \ 342 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0) 343 #define QLA82XX_CRB_C2C_1 \ 344 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1) 345 #define QLA82XX_CRB_C2C_2 \ 346 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2) 347 #define QLA82XX_CRB_CAM \ 348 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM) 349 #define QLA82XX_CRB_CASPER \ 350 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS) 351 #define QLA82XX_CRB_CASPER_0 \ 352 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0) 353 #define QLA82XX_CRB_CASPER_1 \ 354 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1) 355 #define QLA82XX_CRB_CASPER_2 \ 356 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2) 357 #define QLA82XX_CRB_DDR_MD \ 358 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS) 359 #define QLA82XX_CRB_DDR_NET \ 360 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN) 361 #define QLA82XX_CRB_EPG \ 362 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG) 363 #define QLA82XX_CRB_I2Q \ 364 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q) 365 #define QLA82XX_CRB_NIU \ 366 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU) 367 368 #define QLA82XX_CRB_PCIX_HOST \ 369 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH) 370 #define QLA82XX_CRB_PCIX_HOST2 \ 371 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2) 372 #define QLA82XX_CRB_PCIX_MD \ 373 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS) 374 #define QLA82XX_CRB_PCIE \ 375 QLA82XX_CRB_PCIX_MD 376 377 /* window 1 pcie slot */ 378 #define QLA82XX_CRB_PCIE2 \ 379 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2) 380 #define QLA82XX_CRB_PEG_MD_0 \ 381 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0) 382 #define QLA82XX_CRB_PEG_MD_1 \ 383 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1) 384 #define QLA82XX_CRB_PEG_MD_2 \ 385 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2) 386 #define QLA82XX_CRB_PEG_MD_3 \ 387 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 388 #define QLA82XX_CRB_PEG_MD_3 \ 389 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 390 #define QLA82XX_CRB_PEG_MD_D \ 391 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD) 392 #define QLA82XX_CRB_PEG_MD_I \ 393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI) 394 #define QLA82XX_CRB_PEG_NET_0 \ 395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0) 396 #define QLA82XX_CRB_PEG_NET_1 \ 397 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1) 398 #define QLA82XX_CRB_PEG_NET_2 \ 399 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2) 400 #define QLA82XX_CRB_PEG_NET_3 \ 401 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3) 402 #define QLA82XX_CRB_PEG_NET_4 \ 403 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4) 404 #define QLA82XX_CRB_PEG_NET_D \ 405 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND) 406 #define QLA82XX_CRB_PEG_NET_I \ 407 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI) 408 #define QLA82XX_CRB_PQM_MD \ 409 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS) 410 #define QLA82XX_CRB_PQM_NET \ 411 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN) 412 #define QLA82XX_CRB_QDR_MD \ 413 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS) 414 #define QLA82XX_CRB_QDR_NET \ 415 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN) 416 #define QLA82XX_CRB_ROMUSB \ 417 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB) 418 #define QLA82XX_CRB_RPMX_0 \ 419 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0) 420 #define QLA82XX_CRB_RPMX_1 \ 421 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1) 422 #define QLA82XX_CRB_RPMX_2 \ 423 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2) 424 #define QLA82XX_CRB_RPMX_3 \ 425 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3) 426 #define QLA82XX_CRB_RPMX_4 \ 427 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4) 428 #define QLA82XX_CRB_RPMX_5 \ 429 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5) 430 #define QLA82XX_CRB_RPMX_6 \ 431 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6) 432 #define QLA82XX_CRB_RPMX_7 \ 433 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7) 434 #define QLA82XX_CRB_SQM_MD_0 \ 435 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0) 436 #define QLA82XX_CRB_SQM_MD_1 \ 437 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1) 438 #define QLA82XX_CRB_SQM_MD_2 \ 439 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2) 440 #define QLA82XX_CRB_SQM_MD_3 \ 441 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3) 442 #define QLA82XX_CRB_SQM_NET_0 \ 443 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0) 444 #define QLA82XX_CRB_SQM_NET_1 \ 445 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1) 446 #define QLA82XX_CRB_SQM_NET_2 \ 447 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2) 448 #define QLA82XX_CRB_SQM_NET_3 \ 449 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3) 450 #define QLA82XX_CRB_SRE \ 451 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE) 452 #define QLA82XX_CRB_TIMER \ 453 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR) 454 #define QLA82XX_CRB_XDMA \ 455 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA) 456 #define QLA82XX_CRB_I2C0 \ 457 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0) 458 #define QLA82XX_CRB_I2C1 \ 459 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1) 460 #define QLA82XX_CRB_OCM0 \ 461 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0) 462 #define QLA82XX_CRB_SMB \ 463 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB) 464 #define QLA82XX_CRB_MAX \ 465 QLA82XX_PCI_CRB_WINDOW(64) 466 467 /* 468 * ====================== BASE ADDRESSES ON-CHIP ====================== 469 * Base addresses of major components on-chip. 470 * ====================== BASE ADDRESSES ON-CHIP ====================== 471 */ 472 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) 473 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 474 475 /* Imbus address bit used to indicate a host address. This bit is 476 * eliminated by the pcie bar and bar select before presentation 477 * over pcie. */ 478 /* host memory via IMBUS */ 479 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) 480 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) 481 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 482 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) 483 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) 484 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) 485 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) 486 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) 487 488 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 489 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 490 491 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000 492 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000 493 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000 494 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff 495 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000 496 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000 497 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff 498 499 /* 500 * Register offsets for MN 501 */ 502 #define MIU_CONTROL (0x000) 503 #define MIU_TAG (0x004) 504 #define MIU_TEST_AGT_CTRL (0x090) 505 #define MIU_TEST_AGT_ADDR_LO (0x094) 506 #define MIU_TEST_AGT_ADDR_HI (0x098) 507 #define MIU_TEST_AGT_WRDATA_LO (0x0a0) 508 #define MIU_TEST_AGT_WRDATA_HI (0x0a4) 509 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 510 #define MIU_TEST_AGT_RDDATA_LO (0x0a8) 511 #define MIU_TEST_AGT_RDDATA_HI (0x0ac) 512 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 513 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 514 #define MIU_TEST_AGT_UPPER_ADDR(off) (0) 515 516 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 517 #define MIU_TA_CTL_START 1 518 #define MIU_TA_CTL_ENABLE 2 519 #define MIU_TA_CTL_WRITE 4 520 #define MIU_TA_CTL_BUSY 8 521 522 /*CAM RAM */ 523 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000) 524 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) 525 526 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24)) 527 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8)) 528 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac)) 529 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0)) 530 531 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8)) 532 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc)) 533 534 #define HALT_STATUS_UNRECOVERABLE 0x80000000 535 #define HALT_STATUS_RECOVERABLE 0x40000000 536 537 /* Driver Coexistence Defines */ 538 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138)) 539 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140)) 540 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144)) 541 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148)) 542 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 543 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) 544 545 /* Every driver should use these Device State */ 546 #define QLA82XX_DEV_COLD 1 547 #define QLA82XX_DEV_INITIALIZING 2 548 #define QLA82XX_DEV_READY 3 549 #define QLA82XX_DEV_NEED_RESET 4 550 #define QLA82XX_DEV_NEED_QUIESCENT 5 551 #define QLA82XX_DEV_FAILED 6 552 #define QLA82XX_DEV_QUIESCENT 7 553 #define MAX_STATES 8 /* Increment if new state added */ 554 555 #define QLA82XX_IDC_VERSION 1 556 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30 557 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10 558 559 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100)) 560 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124)) 561 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150)) 562 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154)) 563 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158)) 564 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) 565 566 #define PCIE_CHICKEN3 (0x120c8) 567 #define PCIE_SETUP_FUNCTION (0x12040) 568 #define PCIE_SETUP_FUNCTION2 (0x12048) 569 570 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) 571 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) 572 573 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 574 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 575 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */ 576 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */ 577 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 578 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ 579 580 /* Different drive state */ 581 #define QLA82XX_DRVST_NOT_RDY 0 582 #define QLA82XX_DRVST_RST_RDY 1 583 #define QLA82XX_DRVST_QSNT_RDY 2 584 585 /* Different drive active state */ 586 #define QLA82XX_DRV_NOT_ACTIVE 0 587 #define QLA82XX_DRV_ACTIVE 1 588 589 /* 590 * The PCI VendorID and DeviceID for our board. 591 */ 592 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021 593 594 #define QLA82XX_MSIX_TBL_SPACE 8192 595 #define QLA82XX_PCI_REG_MSIX_TBL 0x44 596 #define QLA82XX_PCI_MSIX_CONTROL 0x40 597 598 struct crb_128M_2M_sub_block_map { 599 unsigned valid; 600 unsigned start_128M; 601 unsigned end_128M; 602 unsigned start_2M; 603 }; 604 605 struct crb_128M_2M_block_map { 606 struct crb_128M_2M_sub_block_map sub_block[16]; 607 }; 608 609 struct crb_addr_pair { 610 long addr; 611 long data; 612 }; 613 614 #define ADDR_ERROR ((unsigned long) 0xffffffff) 615 #define MAX_CTL_CHECK 1000 616 617 /*************************************************************************** 618 * PCI related defines. 619 **************************************************************************/ 620 621 /* 622 * Interrupt related defines. 623 */ 624 #define PCIX_TARGET_STATUS (0x10118) 625 #define PCIX_TARGET_STATUS_F1 (0x10160) 626 #define PCIX_TARGET_STATUS_F2 (0x10164) 627 #define PCIX_TARGET_STATUS_F3 (0x10168) 628 #define PCIX_TARGET_STATUS_F4 (0x10360) 629 #define PCIX_TARGET_STATUS_F5 (0x10364) 630 #define PCIX_TARGET_STATUS_F6 (0x10368) 631 #define PCIX_TARGET_STATUS_F7 (0x1036c) 632 633 #define PCIX_TARGET_MASK (0x10128) 634 #define PCIX_TARGET_MASK_F1 (0x10170) 635 #define PCIX_TARGET_MASK_F2 (0x10174) 636 #define PCIX_TARGET_MASK_F3 (0x10178) 637 #define PCIX_TARGET_MASK_F4 (0x10370) 638 #define PCIX_TARGET_MASK_F5 (0x10374) 639 #define PCIX_TARGET_MASK_F6 (0x10378) 640 #define PCIX_TARGET_MASK_F7 (0x1037c) 641 642 /* 643 * Message Signaled Interrupts 644 */ 645 #define PCIX_MSI_F0 (0x13000) 646 #define PCIX_MSI_F1 (0x13004) 647 #define PCIX_MSI_F2 (0x13008) 648 #define PCIX_MSI_F3 (0x1300c) 649 #define PCIX_MSI_F4 (0x13010) 650 #define PCIX_MSI_F5 (0x13014) 651 #define PCIX_MSI_F6 (0x13018) 652 #define PCIX_MSI_F7 (0x1301c) 653 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4)) 654 #define PCIX_INT_VECTOR (0x10100) 655 #define PCIX_INT_MASK (0x10104) 656 657 /* 658 * Interrupt state machine and other bits. 659 */ 660 #define PCIE_MISCCFG_RC (0x1206c) 661 662 #define ISR_INT_TARGET_STATUS \ 663 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS)) 664 #define ISR_INT_TARGET_STATUS_F1 \ 665 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 666 #define ISR_INT_TARGET_STATUS_F2 \ 667 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 668 #define ISR_INT_TARGET_STATUS_F3 \ 669 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 670 #define ISR_INT_TARGET_STATUS_F4 \ 671 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 672 #define ISR_INT_TARGET_STATUS_F5 \ 673 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 674 #define ISR_INT_TARGET_STATUS_F6 \ 675 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 676 #define ISR_INT_TARGET_STATUS_F7 \ 677 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 678 679 #define ISR_INT_TARGET_MASK \ 680 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK)) 681 #define ISR_INT_TARGET_MASK_F1 \ 682 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 683 #define ISR_INT_TARGET_MASK_F2 \ 684 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 685 #define ISR_INT_TARGET_MASK_F3 \ 686 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 687 #define ISR_INT_TARGET_MASK_F4 \ 688 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 689 #define ISR_INT_TARGET_MASK_F5 \ 690 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 691 #define ISR_INT_TARGET_MASK_F6 \ 692 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 693 #define ISR_INT_TARGET_MASK_F7 \ 694 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 695 696 #define ISR_INT_VECTOR \ 697 (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR)) 698 #define ISR_INT_MASK \ 699 (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK)) 700 #define ISR_INT_STATE_REG \ 701 (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC)) 702 703 #define ISR_MSI_INT_TRIGGER(FUNC) \ 704 (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 705 706 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 707 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 708 709 /* 710 * PCI Interrupt Vector Values. 711 */ 712 #define PCIX_INT_VECTOR_BIT_F0 0x0080 713 #define PCIX_INT_VECTOR_BIT_F1 0x0100 714 #define PCIX_INT_VECTOR_BIT_F2 0x0200 715 #define PCIX_INT_VECTOR_BIT_F3 0x0400 716 #define PCIX_INT_VECTOR_BIT_F4 0x0800 717 #define PCIX_INT_VECTOR_BIT_F5 0x1000 718 #define PCIX_INT_VECTOR_BIT_F6 0x2000 719 #define PCIX_INT_VECTOR_BIT_F7 0x4000 720 721 struct qla82xx_legacy_intr_set { 722 uint32_t int_vec_bit; 723 uint32_t tgt_status_reg; 724 uint32_t tgt_mask_reg; 725 uint32_t pci_int_reg; 726 }; 727 728 #define QLA82XX_LEGACY_INTR_CONFIG \ 729 { \ 730 { \ 731 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 732 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 733 .tgt_mask_reg = ISR_INT_TARGET_MASK, \ 734 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ 735 \ 736 { \ 737 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 738 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 739 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ 740 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ 741 \ 742 { \ 743 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 744 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 745 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ 746 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ 747 \ 748 { \ 749 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 750 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 751 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ 752 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ 753 \ 754 { \ 755 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 756 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 757 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ 758 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ 759 \ 760 { \ 761 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 762 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 763 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ 764 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ 765 \ 766 { \ 767 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 768 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 769 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ 770 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ 771 \ 772 { \ 773 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 774 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 775 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ 776 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ 777 } 778 779 #define BRDCFG_START 0x4000 780 #define BOOTLD_START 0x10000 781 #define IMAGE_START 0x100000 782 #define FLASH_ADDR_START 0x43000 783 784 /* Magic number to let user know flash is programmed */ 785 #define QLA82XX_BDINFO_MAGIC 0x12345678 786 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128) 787 #define FW_SIZE_OFFSET (0x3e840c) 788 #define QLA82XX_FW_MIN_SIZE 0x3fffff 789 790 /* UNIFIED ROMIMAGE START */ 791 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000 792 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0 793 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6 794 #define QLA82XX_URI_DIR_SECT_FW 0x7 795 796 /* Offsets */ 797 #define QLA82XX_URI_CHIP_REV_OFF 10 798 #define QLA82XX_URI_FLAGS_OFF 11 799 #define QLA82XX_URI_BIOS_VERSION_OFF 12 800 #define QLA82XX_URI_BOOTLD_IDX_OFF 27 801 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29 802 803 struct qla82xx_uri_table_desc{ 804 uint32_t findex; 805 uint32_t num_entries; 806 uint32_t entry_size; 807 uint32_t reserved[5]; 808 }; 809 810 struct qla82xx_uri_data_desc{ 811 uint32_t findex; 812 uint32_t size; 813 uint32_t reserved[5]; 814 }; 815 816 /* UNIFIED ROMIMAGE END */ 817 818 #define QLA82XX_UNIFIED_ROMIMAGE 3 819 #define QLA82XX_FLASH_ROMIMAGE 4 820 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff 821 822 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0) 823 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4) 824 825 #ifndef readq 826 static inline u64 readq(void __iomem *addr) 827 { 828 return readl(addr) | (((u64) readl(addr + 4)) << 32LL); 829 } 830 #endif 831 832 #ifndef writeq 833 static inline void writeq(u64 val, void __iomem *addr) 834 { 835 writel(((u32) (val)), (addr)); 836 writel(((u32) (val >> 32)), (addr + 4)); 837 } 838 #endif 839 840 /* Request and response queue size */ 841 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */ 842 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/ 843 844 /* 845 * ISP 8021 I/O Register Set structure definitions. 846 */ 847 struct device_reg_82xx { 848 uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */ 849 uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */ 850 uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */ 851 852 uint16_t mailbox_in[32]; /* Mail box In registers */ 853 uint16_t unused_1[32]; 854 uint32_t hint; /* Host interrupt register */ 855 #define HINT_MBX_INT_PENDING BIT_0 856 uint16_t unused_2[62]; 857 uint16_t mailbox_out[32]; /* Mail box Out registers */ 858 uint32_t unused_3[48]; 859 860 uint32_t host_status; /* host status */ 861 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 862 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 863 uint32_t host_int; /* Interrupt status. */ 864 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */ 865 }; 866 867 struct fcp_cmnd { 868 struct scsi_lun lun; 869 uint8_t crn; 870 uint8_t task_attribute; 871 uint8_t task_management; 872 uint8_t additional_cdb_len; 873 uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */ 874 }; 875 876 struct dsd_dma { 877 struct list_head list; 878 dma_addr_t dsd_list_dma; 879 void *dsd_addr; 880 }; 881 882 #define QLA_DSDS_PER_IOCB 37 883 #define QLA_DSD_SIZE 12 884 struct ct6_dsd { 885 uint16_t fcp_cmnd_len; 886 dma_addr_t fcp_cmnd_dma; 887 struct fcp_cmnd *fcp_cmnd; 888 int dsd_use_cnt; 889 struct list_head dsd_list; 890 }; 891 892 #define MBC_TOGGLE_INTERRUPT 0x10 893 894 /* Flash offset */ 895 #define FLT_REG_BOOTLOAD_82XX 0x72 896 #define FLT_REG_BOOT_CODE_82XX 0x78 897 #define FLT_REG_FW_82XX 0x74 898 #define FLT_REG_GOLD_FW_82XX 0x75 899 #define FLT_REG_VPD_82XX 0x81 900 901 #define FA_VPD_SIZE_82XX 0x400 902 903 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 904 905 /****************************************************************************** 906 * 907 * Definitions specific to M25P flash 908 * 909 ******************************************************************************* 910 * Instructions 911 */ 912 #define M25P_INSTR_WREN 0x06 913 #define M25P_INSTR_WRDI 0x04 914 #define M25P_INSTR_RDID 0x9f 915 #define M25P_INSTR_RDSR 0x05 916 #define M25P_INSTR_WRSR 0x01 917 #define M25P_INSTR_READ 0x03 918 #define M25P_INSTR_FAST_READ 0x0b 919 #define M25P_INSTR_PP 0x02 920 #define M25P_INSTR_SE 0xd8 921 #define M25P_INSTR_BE 0xc7 922 #define M25P_INSTR_DP 0xb9 923 #define M25P_INSTR_RES 0xab 924 925 #endif 926