1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 static void qla82xx_crb_addr_transform_setup(void) 46 { 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103 } 104 105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260 }; 261 262 /* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265 static unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330 }; 331 332 /* Device states */ 333 static char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342 }; 343 344 char *qdev_state(uint32_t dev_state) 345 { 346 return q_dev_state[dev_state]; 347 } 348 349 /* 350 * In: 'off_in' is offset from CRB space in 128M pci map 351 * Out: 'off_out' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 356 void __iomem **off_out) 357 { 358 u32 win_read; 359 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 360 361 ha->crb_win = CRB_HI(off_in); 362 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 368 if (win_read != ha->crb_win) { 369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 "%s: Written crbwin (0x%x) " 371 "!= Read crbwin (0x%x), off=0x%lx.\n", 372 __func__, ha->crb_win, win_read, off_in); 373 } 374 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375 } 376 377 static inline unsigned long 378 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379 { 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381 /* See if we are currently pointing to the region we want to use next */ 382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383 /* No need to change window. PCIX and PCIEregs are in both 384 * regs are in both windows. 385 */ 386 return off; 387 } 388 389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390 /* We are in first CRB window */ 391 if (ha->curr_window != 0) 392 WARN_ON(1); 393 return off; 394 } 395 396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397 /* We are in second CRB window */ 398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399 400 if (ha->curr_window != 1) 401 return off; 402 403 /* We are in the QM or direct access 404 * register region - do nothing 405 */ 406 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407 (off < QLA82XX_PCI_CAMQM_MAX)) 408 return off; 409 } 410 /* strange address given */ 411 ql_dbg(ql_dbg_p3p, vha, 0xb001, 412 "%s: Warning: unm_nic_pci_set_crbwindow " 413 "called with an unknown address(%llx).\n", 414 QLA2XXX_DRIVER_NAME, off); 415 return off; 416 } 417 418 static int 419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 420 void __iomem **off_out) 421 { 422 struct crb_128M_2M_sub_block_map *m; 423 424 if (off_in >= QLA82XX_CRB_MAX) 425 return -1; 426 427 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 428 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 430 return 0; 431 } 432 433 if (off_in < QLA82XX_PCI_CRBSPACE) 434 return -1; 435 436 off_in -= QLA82XX_PCI_CRBSPACE; 437 438 /* Try direct map */ 439 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 440 441 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 442 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 443 return 0; 444 } 445 /* Not in direct map, use crb window */ 446 *off_out = (void __iomem *)off_in; 447 return 1; 448 } 449 450 #define CRB_WIN_LOCK_TIMEOUT 100000000 451 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 452 { 453 int done = 0, timeout = 0; 454 455 while (!done) { 456 /* acquire semaphore3 from PCI HW block */ 457 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 458 if (done == 1) 459 break; 460 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 461 return -1; 462 timeout++; 463 } 464 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 465 return 0; 466 } 467 468 int 469 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 470 { 471 void __iomem *off; 472 unsigned long flags = 0; 473 int rv; 474 475 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 476 477 BUG_ON(rv == -1); 478 479 if (rv == 1) { 480 #ifndef __CHECKER__ 481 write_lock_irqsave(&ha->hw_lock, flags); 482 #endif 483 qla82xx_crb_win_lock(ha); 484 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 485 } 486 487 writel(data, (void __iomem *)off); 488 489 if (rv == 1) { 490 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 491 #ifndef __CHECKER__ 492 write_unlock_irqrestore(&ha->hw_lock, flags); 493 #endif 494 } 495 return 0; 496 } 497 498 int 499 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 500 { 501 void __iomem *off; 502 unsigned long flags = 0; 503 int rv; 504 u32 data; 505 506 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 507 508 BUG_ON(rv == -1); 509 510 if (rv == 1) { 511 #ifndef __CHECKER__ 512 write_lock_irqsave(&ha->hw_lock, flags); 513 #endif 514 qla82xx_crb_win_lock(ha); 515 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 516 } 517 data = RD_REG_DWORD(off); 518 519 if (rv == 1) { 520 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 521 #ifndef __CHECKER__ 522 write_unlock_irqrestore(&ha->hw_lock, flags); 523 #endif 524 } 525 return data; 526 } 527 528 #define IDC_LOCK_TIMEOUT 100000000 529 int qla82xx_idc_lock(struct qla_hw_data *ha) 530 { 531 int i; 532 int done = 0, timeout = 0; 533 534 while (!done) { 535 /* acquire semaphore5 from PCI HW block */ 536 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 537 if (done == 1) 538 break; 539 if (timeout >= IDC_LOCK_TIMEOUT) 540 return -1; 541 542 timeout++; 543 544 /* Yield CPU */ 545 if (!in_interrupt()) 546 schedule(); 547 else { 548 for (i = 0; i < 20; i++) 549 cpu_relax(); 550 } 551 } 552 553 return 0; 554 } 555 556 void qla82xx_idc_unlock(struct qla_hw_data *ha) 557 { 558 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 559 } 560 561 /* 562 * check memory access boundary. 563 * used by test agent. support ddr access only for now 564 */ 565 static unsigned long 566 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 567 unsigned long long addr, int size) 568 { 569 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 570 QLA82XX_ADDR_DDR_NET_MAX) || 571 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 572 QLA82XX_ADDR_DDR_NET_MAX) || 573 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 574 return 0; 575 else 576 return 1; 577 } 578 579 static int qla82xx_pci_set_window_warning_count; 580 581 static unsigned long 582 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 583 { 584 int window; 585 u32 win_read; 586 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 587 588 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 589 QLA82XX_ADDR_DDR_NET_MAX)) { 590 /* DDR network side */ 591 window = MN_WIN(addr); 592 ha->ddr_mn_window = window; 593 qla82xx_wr_32(ha, 594 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 595 win_read = qla82xx_rd_32(ha, 596 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 597 if ((win_read << 17) != window) { 598 ql_dbg(ql_dbg_p3p, vha, 0xb003, 599 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 600 __func__, window, win_read); 601 } 602 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 603 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 604 QLA82XX_ADDR_OCM0_MAX)) { 605 unsigned int temp1; 606 if ((addr & 0x00ff800) == 0xff800) { 607 ql_log(ql_log_warn, vha, 0xb004, 608 "%s: QM access not handled.\n", __func__); 609 addr = -1UL; 610 } 611 window = OCM_WIN(addr); 612 ha->ddr_mn_window = window; 613 qla82xx_wr_32(ha, 614 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 615 win_read = qla82xx_rd_32(ha, 616 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 617 temp1 = ((window & 0x1FF) << 7) | 618 ((window & 0x0FFFE0000) >> 17); 619 if (win_read != temp1) { 620 ql_log(ql_log_warn, vha, 0xb005, 621 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 622 __func__, temp1, win_read); 623 } 624 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 625 626 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 627 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 628 /* QDR network side */ 629 window = MS_WIN(addr); 630 ha->qdr_sn_window = window; 631 qla82xx_wr_32(ha, 632 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 633 win_read = qla82xx_rd_32(ha, 634 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 635 if (win_read != window) { 636 ql_log(ql_log_warn, vha, 0xb006, 637 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 638 __func__, window, win_read); 639 } 640 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 641 } else { 642 /* 643 * peg gdb frequently accesses memory that doesn't exist, 644 * this limits the chit chat so debugging isn't slowed down. 645 */ 646 if ((qla82xx_pci_set_window_warning_count++ < 8) || 647 (qla82xx_pci_set_window_warning_count%64 == 0)) { 648 ql_log(ql_log_warn, vha, 0xb007, 649 "%s: Warning:%s Unknown address range!.\n", 650 __func__, QLA2XXX_DRIVER_NAME); 651 } 652 addr = -1UL; 653 } 654 return addr; 655 } 656 657 /* check if address is in the same windows as the previous access */ 658 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 659 unsigned long long addr) 660 { 661 int window; 662 unsigned long long qdr_max; 663 664 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 665 666 /* DDR network side */ 667 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 668 QLA82XX_ADDR_DDR_NET_MAX)) 669 BUG(); 670 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 671 QLA82XX_ADDR_OCM0_MAX)) 672 return 1; 673 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 674 QLA82XX_ADDR_OCM1_MAX)) 675 return 1; 676 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 677 /* QDR network side */ 678 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 679 if (ha->qdr_sn_window == window) 680 return 1; 681 } 682 return 0; 683 } 684 685 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 686 u64 off, void *data, int size) 687 { 688 unsigned long flags; 689 void __iomem *addr = NULL; 690 int ret = 0; 691 u64 start; 692 uint8_t __iomem *mem_ptr = NULL; 693 unsigned long mem_base; 694 unsigned long mem_page; 695 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 696 697 write_lock_irqsave(&ha->hw_lock, flags); 698 699 /* 700 * If attempting to access unknown address or straddle hw windows, 701 * do not access. 702 */ 703 start = qla82xx_pci_set_window(ha, off); 704 if ((start == -1UL) || 705 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 706 write_unlock_irqrestore(&ha->hw_lock, flags); 707 ql_log(ql_log_fatal, vha, 0xb008, 708 "%s out of bound pci memory " 709 "access, offset is 0x%llx.\n", 710 QLA2XXX_DRIVER_NAME, off); 711 return -1; 712 } 713 714 write_unlock_irqrestore(&ha->hw_lock, flags); 715 mem_base = pci_resource_start(ha->pdev, 0); 716 mem_page = start & PAGE_MASK; 717 /* Map two pages whenever user tries to access addresses in two 718 * consecutive pages. 719 */ 720 if (mem_page != ((start + size - 1) & PAGE_MASK)) 721 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 722 else 723 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 724 if (mem_ptr == NULL) { 725 *(u8 *)data = 0; 726 return -1; 727 } 728 addr = mem_ptr; 729 addr += start & (PAGE_SIZE - 1); 730 write_lock_irqsave(&ha->hw_lock, flags); 731 732 switch (size) { 733 case 1: 734 *(u8 *)data = readb(addr); 735 break; 736 case 2: 737 *(u16 *)data = readw(addr); 738 break; 739 case 4: 740 *(u32 *)data = readl(addr); 741 break; 742 case 8: 743 *(u64 *)data = readq(addr); 744 break; 745 default: 746 ret = -1; 747 break; 748 } 749 write_unlock_irqrestore(&ha->hw_lock, flags); 750 751 if (mem_ptr) 752 iounmap(mem_ptr); 753 return ret; 754 } 755 756 static int 757 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 758 u64 off, void *data, int size) 759 { 760 unsigned long flags; 761 void __iomem *addr = NULL; 762 int ret = 0; 763 u64 start; 764 uint8_t __iomem *mem_ptr = NULL; 765 unsigned long mem_base; 766 unsigned long mem_page; 767 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 768 769 write_lock_irqsave(&ha->hw_lock, flags); 770 771 /* 772 * If attempting to access unknown address or straddle hw windows, 773 * do not access. 774 */ 775 start = qla82xx_pci_set_window(ha, off); 776 if ((start == -1UL) || 777 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 778 write_unlock_irqrestore(&ha->hw_lock, flags); 779 ql_log(ql_log_fatal, vha, 0xb009, 780 "%s out of bount memory " 781 "access, offset is 0x%llx.\n", 782 QLA2XXX_DRIVER_NAME, off); 783 return -1; 784 } 785 786 write_unlock_irqrestore(&ha->hw_lock, flags); 787 mem_base = pci_resource_start(ha->pdev, 0); 788 mem_page = start & PAGE_MASK; 789 /* Map two pages whenever user tries to access addresses in two 790 * consecutive pages. 791 */ 792 if (mem_page != ((start + size - 1) & PAGE_MASK)) 793 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 794 else 795 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 796 if (mem_ptr == NULL) 797 return -1; 798 799 addr = mem_ptr; 800 addr += start & (PAGE_SIZE - 1); 801 write_lock_irqsave(&ha->hw_lock, flags); 802 803 switch (size) { 804 case 1: 805 writeb(*(u8 *)data, addr); 806 break; 807 case 2: 808 writew(*(u16 *)data, addr); 809 break; 810 case 4: 811 writel(*(u32 *)data, addr); 812 break; 813 case 8: 814 writeq(*(u64 *)data, addr); 815 break; 816 default: 817 ret = -1; 818 break; 819 } 820 write_unlock_irqrestore(&ha->hw_lock, flags); 821 if (mem_ptr) 822 iounmap(mem_ptr); 823 return ret; 824 } 825 826 #define MTU_FUDGE_FACTOR 100 827 static unsigned long 828 qla82xx_decode_crb_addr(unsigned long addr) 829 { 830 int i; 831 unsigned long base_addr, offset, pci_base; 832 833 if (!qla82xx_crb_table_initialized) 834 qla82xx_crb_addr_transform_setup(); 835 836 pci_base = ADDR_ERROR; 837 base_addr = addr & 0xfff00000; 838 offset = addr & 0x000fffff; 839 840 for (i = 0; i < MAX_CRB_XFORM; i++) { 841 if (crb_addr_xform[i] == base_addr) { 842 pci_base = i << 20; 843 break; 844 } 845 } 846 if (pci_base == ADDR_ERROR) 847 return pci_base; 848 return pci_base + offset; 849 } 850 851 static long rom_max_timeout = 100; 852 static long qla82xx_rom_lock_timeout = 100; 853 854 static int 855 qla82xx_rom_lock(struct qla_hw_data *ha) 856 { 857 int done = 0, timeout = 0; 858 uint32_t lock_owner = 0; 859 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 860 861 while (!done) { 862 /* acquire semaphore2 from PCI HW block */ 863 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 864 if (done == 1) 865 break; 866 if (timeout >= qla82xx_rom_lock_timeout) { 867 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 868 ql_dbg(ql_dbg_p3p, vha, 0xb157, 869 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 870 __func__, ha->portnum, lock_owner); 871 return -1; 872 } 873 timeout++; 874 } 875 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 876 return 0; 877 } 878 879 static void 880 qla82xx_rom_unlock(struct qla_hw_data *ha) 881 { 882 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 883 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 884 } 885 886 static int 887 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 888 { 889 long timeout = 0; 890 long done = 0 ; 891 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 892 893 while (done == 0) { 894 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 895 done &= 4; 896 timeout++; 897 if (timeout >= rom_max_timeout) { 898 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 899 "%s: Timeout reached waiting for rom busy.\n", 900 QLA2XXX_DRIVER_NAME); 901 return -1; 902 } 903 } 904 return 0; 905 } 906 907 static int 908 qla82xx_wait_rom_done(struct qla_hw_data *ha) 909 { 910 long timeout = 0; 911 long done = 0 ; 912 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 913 914 while (done == 0) { 915 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 916 done &= 2; 917 timeout++; 918 if (timeout >= rom_max_timeout) { 919 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 920 "%s: Timeout reached waiting for rom done.\n", 921 QLA2XXX_DRIVER_NAME); 922 return -1; 923 } 924 } 925 return 0; 926 } 927 928 static int 929 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 930 { 931 uint32_t off_value, rval = 0; 932 933 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 934 935 /* Read back value to make sure write has gone through */ 936 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 937 off_value = (off & 0x0000FFFF); 938 939 if (flag) 940 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 941 data); 942 else 943 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M + 944 ha->nx_pcibase); 945 946 return rval; 947 } 948 949 static int 950 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 951 { 952 /* Dword reads to flash. */ 953 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 954 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 955 (addr & 0x0000FFFF), 0, 0); 956 957 return 0; 958 } 959 960 static int 961 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 962 { 963 int ret, loops = 0; 964 uint32_t lock_owner = 0; 965 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 966 967 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 968 udelay(100); 969 schedule(); 970 loops++; 971 } 972 if (loops >= 50000) { 973 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 974 ql_log(ql_log_fatal, vha, 0x00b9, 975 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 976 lock_owner); 977 return -1; 978 } 979 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 980 qla82xx_rom_unlock(ha); 981 return ret; 982 } 983 984 static int 985 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 986 { 987 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 989 qla82xx_wait_rom_busy(ha); 990 if (qla82xx_wait_rom_done(ha)) { 991 ql_log(ql_log_warn, vha, 0xb00c, 992 "Error waiting for rom done.\n"); 993 return -1; 994 } 995 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 996 return 0; 997 } 998 999 static int 1000 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 1001 { 1002 long timeout = 0; 1003 uint32_t done = 1 ; 1004 uint32_t val; 1005 int ret = 0; 1006 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1007 1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1009 while ((done != 0) && (ret == 0)) { 1010 ret = qla82xx_read_status_reg(ha, &val); 1011 done = val & 1; 1012 timeout++; 1013 udelay(10); 1014 cond_resched(); 1015 if (timeout >= 50000) { 1016 ql_log(ql_log_warn, vha, 0xb00d, 1017 "Timeout reached waiting for write finish.\n"); 1018 return -1; 1019 } 1020 } 1021 return ret; 1022 } 1023 1024 static int 1025 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1026 { 1027 uint32_t val; 1028 qla82xx_wait_rom_busy(ha); 1029 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1030 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1031 qla82xx_wait_rom_busy(ha); 1032 if (qla82xx_wait_rom_done(ha)) 1033 return -1; 1034 if (qla82xx_read_status_reg(ha, &val) != 0) 1035 return -1; 1036 if ((val & 2) != 2) 1037 return -1; 1038 return 0; 1039 } 1040 1041 static int 1042 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1043 { 1044 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1045 if (qla82xx_flash_set_write_enable(ha)) 1046 return -1; 1047 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1048 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1049 if (qla82xx_wait_rom_done(ha)) { 1050 ql_log(ql_log_warn, vha, 0xb00e, 1051 "Error waiting for rom done.\n"); 1052 return -1; 1053 } 1054 return qla82xx_flash_wait_write_finish(ha); 1055 } 1056 1057 static int 1058 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1059 { 1060 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1061 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1062 if (qla82xx_wait_rom_done(ha)) { 1063 ql_log(ql_log_warn, vha, 0xb00f, 1064 "Error waiting for rom done.\n"); 1065 return -1; 1066 } 1067 return 0; 1068 } 1069 1070 static int 1071 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1072 { 1073 int loops = 0; 1074 uint32_t lock_owner = 0; 1075 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1076 1077 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1078 udelay(100); 1079 cond_resched(); 1080 loops++; 1081 } 1082 if (loops >= 50000) { 1083 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1084 ql_log(ql_log_warn, vha, 0xb010, 1085 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1086 return -1; 1087 } 1088 return 0; 1089 } 1090 1091 static int 1092 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1093 uint32_t data) 1094 { 1095 int ret = 0; 1096 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1097 1098 ret = ql82xx_rom_lock_d(ha); 1099 if (ret < 0) { 1100 ql_log(ql_log_warn, vha, 0xb011, 1101 "ROM lock failed.\n"); 1102 return ret; 1103 } 1104 1105 if (qla82xx_flash_set_write_enable(ha)) 1106 goto done_write; 1107 1108 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1109 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1110 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1111 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1112 qla82xx_wait_rom_busy(ha); 1113 if (qla82xx_wait_rom_done(ha)) { 1114 ql_log(ql_log_warn, vha, 0xb012, 1115 "Error waiting for rom done.\n"); 1116 ret = -1; 1117 goto done_write; 1118 } 1119 1120 ret = qla82xx_flash_wait_write_finish(ha); 1121 1122 done_write: 1123 qla82xx_rom_unlock(ha); 1124 return ret; 1125 } 1126 1127 /* This routine does CRB initialize sequence 1128 * to put the ISP into operational state 1129 */ 1130 static int 1131 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1132 { 1133 int addr, val; 1134 int i ; 1135 struct crb_addr_pair *buf; 1136 unsigned long off; 1137 unsigned offset, n; 1138 struct qla_hw_data *ha = vha->hw; 1139 1140 struct crb_addr_pair { 1141 long addr; 1142 long data; 1143 }; 1144 1145 /* Halt all the individual PEGs and other blocks of the ISP */ 1146 qla82xx_rom_lock(ha); 1147 1148 /* disable all I2Q */ 1149 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1153 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1154 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1155 1156 /* disable all niu interrupts */ 1157 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1158 /* disable xge rx/tx */ 1159 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1160 /* disable xg1 rx/tx */ 1161 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1162 /* disable sideband mac */ 1163 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1164 /* disable ap0 mac */ 1165 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1166 /* disable ap1 mac */ 1167 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1168 1169 /* halt sre */ 1170 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1171 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1172 1173 /* halt epg */ 1174 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1175 1176 /* halt timers */ 1177 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1178 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1179 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1180 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1181 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1182 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1183 1184 /* halt pegs */ 1185 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1186 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1187 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1188 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1189 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1190 msleep(20); 1191 1192 /* big hammer */ 1193 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1194 /* don't reset CAM block on reset */ 1195 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1196 else 1197 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1198 qla82xx_rom_unlock(ha); 1199 1200 /* Read the signature value from the flash. 1201 * Offset 0: Contain signature (0xcafecafe) 1202 * Offset 4: Offset and number of addr/value pairs 1203 * that present in CRB initialize sequence 1204 */ 1205 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1206 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1207 ql_log(ql_log_fatal, vha, 0x006e, 1208 "Error Reading crb_init area: n: %08x.\n", n); 1209 return -1; 1210 } 1211 1212 /* Offset in flash = lower 16 bits 1213 * Number of entries = upper 16 bits 1214 */ 1215 offset = n & 0xffffU; 1216 n = (n >> 16) & 0xffffU; 1217 1218 /* number of addr/value pair should not exceed 1024 entries */ 1219 if (n >= 1024) { 1220 ql_log(ql_log_fatal, vha, 0x0071, 1221 "Card flash not initialized:n=0x%x.\n", n); 1222 return -1; 1223 } 1224 1225 ql_log(ql_log_info, vha, 0x0072, 1226 "%d CRB init values found in ROM.\n", n); 1227 1228 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1229 if (buf == NULL) { 1230 ql_log(ql_log_fatal, vha, 0x010c, 1231 "Unable to allocate memory.\n"); 1232 return -ENOMEM; 1233 } 1234 1235 for (i = 0; i < n; i++) { 1236 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1237 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1238 kfree(buf); 1239 return -1; 1240 } 1241 1242 buf[i].addr = addr; 1243 buf[i].data = val; 1244 } 1245 1246 for (i = 0; i < n; i++) { 1247 /* Translate internal CRB initialization 1248 * address to PCI bus address 1249 */ 1250 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1251 QLA82XX_PCI_CRBSPACE; 1252 /* Not all CRB addr/value pair to be written, 1253 * some of them are skipped 1254 */ 1255 1256 /* skipping cold reboot MAGIC */ 1257 if (off == QLA82XX_CAM_RAM(0x1fc)) 1258 continue; 1259 1260 /* do not reset PCI */ 1261 if (off == (ROMUSB_GLB + 0xbc)) 1262 continue; 1263 1264 /* skip core clock, so that firmware can increase the clock */ 1265 if (off == (ROMUSB_GLB + 0xc8)) 1266 continue; 1267 1268 /* skip the function enable register */ 1269 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1270 continue; 1271 1272 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1273 continue; 1274 1275 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1276 continue; 1277 1278 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1279 continue; 1280 1281 if (off == ADDR_ERROR) { 1282 ql_log(ql_log_fatal, vha, 0x0116, 1283 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1284 continue; 1285 } 1286 1287 qla82xx_wr_32(ha, off, buf[i].data); 1288 1289 /* ISP requires much bigger delay to settle down, 1290 * else crb_window returns 0xffffffff 1291 */ 1292 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1293 msleep(1000); 1294 1295 /* ISP requires millisec delay between 1296 * successive CRB register updation 1297 */ 1298 msleep(1); 1299 } 1300 1301 kfree(buf); 1302 1303 /* Resetting the data and instruction cache */ 1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1305 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1306 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1307 1308 /* Clear all protocol processing engines */ 1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1311 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1312 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1313 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1314 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1316 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1317 return 0; 1318 } 1319 1320 static int 1321 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1322 u64 off, void *data, int size) 1323 { 1324 int i, j, ret = 0, loop, sz[2], off0; 1325 int scale, shift_amount, startword; 1326 uint32_t temp; 1327 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1328 1329 /* 1330 * If not MN, go check for MS or invalid. 1331 */ 1332 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1333 mem_crb = QLA82XX_CRB_QDR_NET; 1334 else { 1335 mem_crb = QLA82XX_CRB_DDR_NET; 1336 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1337 return qla82xx_pci_mem_write_direct(ha, 1338 off, data, size); 1339 } 1340 1341 off0 = off & 0x7; 1342 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1343 sz[1] = size - sz[0]; 1344 1345 off8 = off & 0xfffffff0; 1346 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1347 shift_amount = 4; 1348 scale = 2; 1349 startword = (off & 0xf)/8; 1350 1351 for (i = 0; i < loop; i++) { 1352 if (qla82xx_pci_mem_read_2M(ha, off8 + 1353 (i << shift_amount), &word[i * scale], 8)) 1354 return -1; 1355 } 1356 1357 switch (size) { 1358 case 1: 1359 tmpw = *((uint8_t *)data); 1360 break; 1361 case 2: 1362 tmpw = *((uint16_t *)data); 1363 break; 1364 case 4: 1365 tmpw = *((uint32_t *)data); 1366 break; 1367 case 8: 1368 default: 1369 tmpw = *((uint64_t *)data); 1370 break; 1371 } 1372 1373 if (sz[0] == 8) { 1374 word[startword] = tmpw; 1375 } else { 1376 word[startword] &= 1377 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1378 word[startword] |= tmpw << (off0 * 8); 1379 } 1380 if (sz[1] != 0) { 1381 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1382 word[startword+1] |= tmpw >> (sz[0] * 8); 1383 } 1384 1385 for (i = 0; i < loop; i++) { 1386 temp = off8 + (i << shift_amount); 1387 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1388 temp = 0; 1389 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1390 temp = word[i * scale] & 0xffffffff; 1391 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1392 temp = (word[i * scale] >> 32) & 0xffffffff; 1393 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1394 temp = word[i*scale + 1] & 0xffffffff; 1395 qla82xx_wr_32(ha, mem_crb + 1396 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1397 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1398 qla82xx_wr_32(ha, mem_crb + 1399 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1400 1401 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1402 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1403 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1404 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1405 1406 for (j = 0; j < MAX_CTL_CHECK; j++) { 1407 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1408 if ((temp & MIU_TA_CTL_BUSY) == 0) 1409 break; 1410 } 1411 1412 if (j >= MAX_CTL_CHECK) { 1413 if (printk_ratelimit()) 1414 dev_err(&ha->pdev->dev, 1415 "failed to write through agent.\n"); 1416 ret = -1; 1417 break; 1418 } 1419 } 1420 1421 return ret; 1422 } 1423 1424 static int 1425 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1426 { 1427 int i; 1428 long size = 0; 1429 long flashaddr = ha->flt_region_bootload << 2; 1430 long memaddr = BOOTLD_START; 1431 u64 data; 1432 u32 high, low; 1433 size = (IMAGE_START - BOOTLD_START) / 8; 1434 1435 for (i = 0; i < size; i++) { 1436 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1437 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1438 return -1; 1439 } 1440 data = ((u64)high << 32) | low ; 1441 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1442 flashaddr += 8; 1443 memaddr += 8; 1444 1445 if (i % 0x1000 == 0) 1446 msleep(1); 1447 } 1448 udelay(100); 1449 read_lock(&ha->hw_lock); 1450 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1451 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1452 read_unlock(&ha->hw_lock); 1453 return 0; 1454 } 1455 1456 int 1457 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1458 u64 off, void *data, int size) 1459 { 1460 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1461 int shift_amount; 1462 uint32_t temp; 1463 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1464 1465 /* 1466 * If not MN, go check for MS or invalid. 1467 */ 1468 1469 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1470 mem_crb = QLA82XX_CRB_QDR_NET; 1471 else { 1472 mem_crb = QLA82XX_CRB_DDR_NET; 1473 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1474 return qla82xx_pci_mem_read_direct(ha, 1475 off, data, size); 1476 } 1477 1478 off8 = off & 0xfffffff0; 1479 off0[0] = off & 0xf; 1480 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1481 shift_amount = 4; 1482 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1483 off0[1] = 0; 1484 sz[1] = size - sz[0]; 1485 1486 for (i = 0; i < loop; i++) { 1487 temp = off8 + (i << shift_amount); 1488 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1489 temp = 0; 1490 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1491 temp = MIU_TA_CTL_ENABLE; 1492 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1493 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1494 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1495 1496 for (j = 0; j < MAX_CTL_CHECK; j++) { 1497 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1498 if ((temp & MIU_TA_CTL_BUSY) == 0) 1499 break; 1500 } 1501 1502 if (j >= MAX_CTL_CHECK) { 1503 if (printk_ratelimit()) 1504 dev_err(&ha->pdev->dev, 1505 "failed to read through agent.\n"); 1506 break; 1507 } 1508 1509 start = off0[i] >> 2; 1510 end = (off0[i] + sz[i] - 1) >> 2; 1511 for (k = start; k <= end; k++) { 1512 temp = qla82xx_rd_32(ha, 1513 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1514 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1515 } 1516 } 1517 1518 if (j >= MAX_CTL_CHECK) 1519 return -1; 1520 1521 if ((off0[0] & 7) == 0) { 1522 val = word[0]; 1523 } else { 1524 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1525 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1526 } 1527 1528 switch (size) { 1529 case 1: 1530 *(uint8_t *)data = val; 1531 break; 1532 case 2: 1533 *(uint16_t *)data = val; 1534 break; 1535 case 4: 1536 *(uint32_t *)data = val; 1537 break; 1538 case 8: 1539 *(uint64_t *)data = val; 1540 break; 1541 } 1542 return 0; 1543 } 1544 1545 1546 static struct qla82xx_uri_table_desc * 1547 qla82xx_get_table_desc(const u8 *unirom, int section) 1548 { 1549 uint32_t i; 1550 struct qla82xx_uri_table_desc *directory = 1551 (struct qla82xx_uri_table_desc *)&unirom[0]; 1552 __le32 offset; 1553 __le32 tab_type; 1554 __le32 entries = cpu_to_le32(directory->num_entries); 1555 1556 for (i = 0; i < entries; i++) { 1557 offset = cpu_to_le32(directory->findex) + 1558 (i * cpu_to_le32(directory->entry_size)); 1559 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1560 1561 if (tab_type == section) 1562 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1563 } 1564 1565 return NULL; 1566 } 1567 1568 static struct qla82xx_uri_data_desc * 1569 qla82xx_get_data_desc(struct qla_hw_data *ha, 1570 u32 section, u32 idx_offset) 1571 { 1572 const u8 *unirom = ha->hablob->fw->data; 1573 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1574 struct qla82xx_uri_table_desc *tab_desc = NULL; 1575 __le32 offset; 1576 1577 tab_desc = qla82xx_get_table_desc(unirom, section); 1578 if (!tab_desc) 1579 return NULL; 1580 1581 offset = cpu_to_le32(tab_desc->findex) + 1582 (cpu_to_le32(tab_desc->entry_size) * idx); 1583 1584 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1585 } 1586 1587 static u8 * 1588 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1589 { 1590 u32 offset = BOOTLD_START; 1591 struct qla82xx_uri_data_desc *uri_desc = NULL; 1592 1593 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1594 uri_desc = qla82xx_get_data_desc(ha, 1595 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1596 if (uri_desc) 1597 offset = cpu_to_le32(uri_desc->findex); 1598 } 1599 1600 return (u8 *)&ha->hablob->fw->data[offset]; 1601 } 1602 1603 static __le32 1604 qla82xx_get_fw_size(struct qla_hw_data *ha) 1605 { 1606 struct qla82xx_uri_data_desc *uri_desc = NULL; 1607 1608 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1609 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1610 QLA82XX_URI_FIRMWARE_IDX_OFF); 1611 if (uri_desc) 1612 return cpu_to_le32(uri_desc->size); 1613 } 1614 1615 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1616 } 1617 1618 static u8 * 1619 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1620 { 1621 u32 offset = IMAGE_START; 1622 struct qla82xx_uri_data_desc *uri_desc = NULL; 1623 1624 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1625 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1626 QLA82XX_URI_FIRMWARE_IDX_OFF); 1627 if (uri_desc) 1628 offset = cpu_to_le32(uri_desc->findex); 1629 } 1630 1631 return (u8 *)&ha->hablob->fw->data[offset]; 1632 } 1633 1634 /* PCI related functions */ 1635 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1636 { 1637 unsigned long val = 0; 1638 u32 control; 1639 1640 switch (region) { 1641 case 0: 1642 val = 0; 1643 break; 1644 case 1: 1645 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1646 val = control + QLA82XX_MSIX_TBL_SPACE; 1647 break; 1648 } 1649 return val; 1650 } 1651 1652 1653 int 1654 qla82xx_iospace_config(struct qla_hw_data *ha) 1655 { 1656 uint32_t len = 0; 1657 1658 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1660 "Failed to reserver selected regions.\n"); 1661 goto iospace_error_exit; 1662 } 1663 1664 /* Use MMIO operations for all accesses. */ 1665 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1666 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1667 "Region #0 not an MMIO resource, aborting.\n"); 1668 goto iospace_error_exit; 1669 } 1670 1671 len = pci_resource_len(ha->pdev, 0); 1672 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1673 if (!ha->nx_pcibase) { 1674 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1675 "Cannot remap pcibase MMIO, aborting.\n"); 1676 goto iospace_error_exit; 1677 } 1678 1679 /* Mapping of IO base pointer */ 1680 if (IS_QLA8044(ha)) { 1681 ha->iobase = ha->nx_pcibase; 1682 } else if (IS_QLA82XX(ha)) { 1683 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1684 } 1685 1686 if (!ql2xdbwr) { 1687 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1688 (ha->pdev->devfn << 12)), 4); 1689 if (!ha->nxdb_wr_ptr) { 1690 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1691 "Cannot remap MMIO, aborting.\n"); 1692 goto iospace_error_exit; 1693 } 1694 1695 /* Mapping of IO base pointer, 1696 * door bell read and write pointer 1697 */ 1698 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1699 (ha->pdev->devfn * 8); 1700 } else { 1701 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1702 QLA82XX_CAMRAM_DB1 : 1703 QLA82XX_CAMRAM_DB2); 1704 } 1705 1706 ha->max_req_queues = ha->max_rsp_queues = 1; 1707 ha->msix_count = ha->max_rsp_queues + 1; 1708 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1709 "nx_pci_base=%p iobase=%p " 1710 "max_req_queues=%d msix_count=%d.\n", 1711 ha->nx_pcibase, ha->iobase, 1712 ha->max_req_queues, ha->msix_count); 1713 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1714 "nx_pci_base=%p iobase=%p " 1715 "max_req_queues=%d msix_count=%d.\n", 1716 ha->nx_pcibase, ha->iobase, 1717 ha->max_req_queues, ha->msix_count); 1718 return 0; 1719 1720 iospace_error_exit: 1721 return -ENOMEM; 1722 } 1723 1724 /* GS related functions */ 1725 1726 /* Initialization related functions */ 1727 1728 /** 1729 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1730 * @ha: HA context 1731 * 1732 * Returns 0 on success. 1733 */ 1734 int 1735 qla82xx_pci_config(scsi_qla_host_t *vha) 1736 { 1737 struct qla_hw_data *ha = vha->hw; 1738 int ret; 1739 1740 pci_set_master(ha->pdev); 1741 ret = pci_set_mwi(ha->pdev); 1742 ha->chip_revision = ha->pdev->revision; 1743 ql_dbg(ql_dbg_init, vha, 0x0043, 1744 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1745 ha->chip_revision, ret); 1746 return 0; 1747 } 1748 1749 /** 1750 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1751 * @ha: HA context 1752 * 1753 * Returns 0 on success. 1754 */ 1755 void 1756 qla82xx_reset_chip(scsi_qla_host_t *vha) 1757 { 1758 struct qla_hw_data *ha = vha->hw; 1759 ha->isp_ops->disable_intrs(ha); 1760 } 1761 1762 void qla82xx_config_rings(struct scsi_qla_host *vha) 1763 { 1764 struct qla_hw_data *ha = vha->hw; 1765 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1766 struct init_cb_81xx *icb; 1767 struct req_que *req = ha->req_q_map[0]; 1768 struct rsp_que *rsp = ha->rsp_q_map[0]; 1769 1770 /* Setup ring parameters in initialization control block. */ 1771 icb = (struct init_cb_81xx *)ha->init_cb; 1772 icb->request_q_outpointer = cpu_to_le16(0); 1773 icb->response_q_inpointer = cpu_to_le16(0); 1774 icb->request_q_length = cpu_to_le16(req->length); 1775 icb->response_q_length = cpu_to_le16(rsp->length); 1776 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1777 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1778 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1779 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1780 1781 WRT_REG_DWORD(®->req_q_out[0], 0); 1782 WRT_REG_DWORD(®->rsp_q_in[0], 0); 1783 WRT_REG_DWORD(®->rsp_q_out[0], 0); 1784 } 1785 1786 static int 1787 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1788 { 1789 u64 *ptr64; 1790 u32 i, flashaddr, size; 1791 __le64 data; 1792 1793 size = (IMAGE_START - BOOTLD_START) / 8; 1794 1795 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1796 flashaddr = BOOTLD_START; 1797 1798 for (i = 0; i < size; i++) { 1799 data = cpu_to_le64(ptr64[i]); 1800 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1801 return -EIO; 1802 flashaddr += 8; 1803 } 1804 1805 flashaddr = FLASH_ADDR_START; 1806 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1807 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1808 1809 for (i = 0; i < size; i++) { 1810 data = cpu_to_le64(ptr64[i]); 1811 1812 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1813 return -EIO; 1814 flashaddr += 8; 1815 } 1816 udelay(100); 1817 1818 /* Write a magic value to CAMRAM register 1819 * at a specified offset to indicate 1820 * that all data is written and 1821 * ready for firmware to initialize. 1822 */ 1823 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1824 1825 read_lock(&ha->hw_lock); 1826 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1827 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1828 read_unlock(&ha->hw_lock); 1829 return 0; 1830 } 1831 1832 static int 1833 qla82xx_set_product_offset(struct qla_hw_data *ha) 1834 { 1835 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1836 const uint8_t *unirom = ha->hablob->fw->data; 1837 uint32_t i; 1838 __le32 entries; 1839 __le32 flags, file_chiprev, offset; 1840 uint8_t chiprev = ha->chip_revision; 1841 /* Hardcoding mn_present flag for P3P */ 1842 int mn_present = 0; 1843 uint32_t flagbit; 1844 1845 ptab_desc = qla82xx_get_table_desc(unirom, 1846 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1847 if (!ptab_desc) 1848 return -1; 1849 1850 entries = cpu_to_le32(ptab_desc->num_entries); 1851 1852 for (i = 0; i < entries; i++) { 1853 offset = cpu_to_le32(ptab_desc->findex) + 1854 (i * cpu_to_le32(ptab_desc->entry_size)); 1855 flags = cpu_to_le32(*((int *)&unirom[offset] + 1856 QLA82XX_URI_FLAGS_OFF)); 1857 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1858 QLA82XX_URI_CHIP_REV_OFF)); 1859 1860 flagbit = mn_present ? 1 : 2; 1861 1862 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1863 ha->file_prd_off = offset; 1864 return 0; 1865 } 1866 } 1867 return -1; 1868 } 1869 1870 static int 1871 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1872 { 1873 __le32 val; 1874 uint32_t min_size; 1875 struct qla_hw_data *ha = vha->hw; 1876 const struct firmware *fw = ha->hablob->fw; 1877 1878 ha->fw_type = fw_type; 1879 1880 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1881 if (qla82xx_set_product_offset(ha)) 1882 return -EINVAL; 1883 1884 min_size = QLA82XX_URI_FW_MIN_SIZE; 1885 } else { 1886 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1887 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1888 return -EINVAL; 1889 1890 min_size = QLA82XX_FW_MIN_SIZE; 1891 } 1892 1893 if (fw->size < min_size) 1894 return -EINVAL; 1895 return 0; 1896 } 1897 1898 static int 1899 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1900 { 1901 u32 val = 0; 1902 int retries = 60; 1903 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1904 1905 do { 1906 read_lock(&ha->hw_lock); 1907 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1908 read_unlock(&ha->hw_lock); 1909 1910 switch (val) { 1911 case PHAN_INITIALIZE_COMPLETE: 1912 case PHAN_INITIALIZE_ACK: 1913 return QLA_SUCCESS; 1914 case PHAN_INITIALIZE_FAILED: 1915 break; 1916 default: 1917 break; 1918 } 1919 ql_log(ql_log_info, vha, 0x00a8, 1920 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1921 val, retries); 1922 1923 msleep(500); 1924 1925 } while (--retries); 1926 1927 ql_log(ql_log_fatal, vha, 0x00a9, 1928 "Cmd Peg initialization failed: 0x%x.\n", val); 1929 1930 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1931 read_lock(&ha->hw_lock); 1932 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1933 read_unlock(&ha->hw_lock); 1934 return QLA_FUNCTION_FAILED; 1935 } 1936 1937 static int 1938 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1939 { 1940 u32 val = 0; 1941 int retries = 60; 1942 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1943 1944 do { 1945 read_lock(&ha->hw_lock); 1946 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1947 read_unlock(&ha->hw_lock); 1948 1949 switch (val) { 1950 case PHAN_INITIALIZE_COMPLETE: 1951 case PHAN_INITIALIZE_ACK: 1952 return QLA_SUCCESS; 1953 case PHAN_INITIALIZE_FAILED: 1954 break; 1955 default: 1956 break; 1957 } 1958 ql_log(ql_log_info, vha, 0x00ab, 1959 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1960 val, retries); 1961 1962 msleep(500); 1963 1964 } while (--retries); 1965 1966 ql_log(ql_log_fatal, vha, 0x00ac, 1967 "Rcv Peg initializatin failed: 0x%x.\n", val); 1968 read_lock(&ha->hw_lock); 1969 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1970 read_unlock(&ha->hw_lock); 1971 return QLA_FUNCTION_FAILED; 1972 } 1973 1974 /* ISR related functions */ 1975 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1976 QLA82XX_LEGACY_INTR_CONFIG; 1977 1978 /* 1979 * qla82xx_mbx_completion() - Process mailbox command completions. 1980 * @ha: SCSI driver HA context 1981 * @mb0: Mailbox0 register 1982 */ 1983 void 1984 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1985 { 1986 uint16_t cnt; 1987 uint16_t __iomem *wptr; 1988 struct qla_hw_data *ha = vha->hw; 1989 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1990 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1991 1992 /* Load return mailbox registers. */ 1993 ha->flags.mbox_int = 1; 1994 ha->mailbox_out[0] = mb0; 1995 1996 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1997 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1998 wptr++; 1999 } 2000 2001 if (!ha->mcp) 2002 ql_dbg(ql_dbg_async, vha, 0x5053, 2003 "MBX pointer ERROR.\n"); 2004 } 2005 2006 /* 2007 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2008 * @irq: 2009 * @dev_id: SCSI driver HA context 2010 * @regs: 2011 * 2012 * Called by system whenever the host adapter generates an interrupt. 2013 * 2014 * Returns handled flag. 2015 */ 2016 irqreturn_t 2017 qla82xx_intr_handler(int irq, void *dev_id) 2018 { 2019 scsi_qla_host_t *vha; 2020 struct qla_hw_data *ha; 2021 struct rsp_que *rsp; 2022 struct device_reg_82xx __iomem *reg; 2023 int status = 0, status1 = 0; 2024 unsigned long flags; 2025 unsigned long iter; 2026 uint32_t stat = 0; 2027 uint16_t mb[4]; 2028 2029 rsp = (struct rsp_que *) dev_id; 2030 if (!rsp) { 2031 ql_log(ql_log_info, NULL, 0xb053, 2032 "%s: NULL response queue pointer.\n", __func__); 2033 return IRQ_NONE; 2034 } 2035 ha = rsp->hw; 2036 2037 if (!ha->flags.msi_enabled) { 2038 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2039 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2040 return IRQ_NONE; 2041 2042 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2043 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2044 return IRQ_NONE; 2045 } 2046 2047 /* clear the interrupt */ 2048 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2049 2050 /* read twice to ensure write is flushed */ 2051 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2052 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2053 2054 reg = &ha->iobase->isp82; 2055 2056 spin_lock_irqsave(&ha->hardware_lock, flags); 2057 vha = pci_get_drvdata(ha->pdev); 2058 for (iter = 1; iter--; ) { 2059 2060 if (RD_REG_DWORD(®->host_int)) { 2061 stat = RD_REG_DWORD(®->host_status); 2062 2063 switch (stat & 0xff) { 2064 case 0x1: 2065 case 0x2: 2066 case 0x10: 2067 case 0x11: 2068 qla82xx_mbx_completion(vha, MSW(stat)); 2069 status |= MBX_INTERRUPT; 2070 break; 2071 case 0x12: 2072 mb[0] = MSW(stat); 2073 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2074 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2075 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2076 qla2x00_async_event(vha, rsp, mb); 2077 break; 2078 case 0x13: 2079 qla24xx_process_response_queue(vha, rsp); 2080 break; 2081 default: 2082 ql_dbg(ql_dbg_async, vha, 0x5054, 2083 "Unrecognized interrupt type (%d).\n", 2084 stat & 0xff); 2085 break; 2086 } 2087 } 2088 WRT_REG_DWORD(®->host_int, 0); 2089 } 2090 2091 qla2x00_handle_mbx_completion(ha, status); 2092 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2093 2094 if (!ha->flags.msi_enabled) 2095 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2096 2097 return IRQ_HANDLED; 2098 } 2099 2100 irqreturn_t 2101 qla82xx_msix_default(int irq, void *dev_id) 2102 { 2103 scsi_qla_host_t *vha; 2104 struct qla_hw_data *ha; 2105 struct rsp_que *rsp; 2106 struct device_reg_82xx __iomem *reg; 2107 int status = 0; 2108 unsigned long flags; 2109 uint32_t stat = 0; 2110 uint32_t host_int = 0; 2111 uint16_t mb[4]; 2112 2113 rsp = (struct rsp_que *) dev_id; 2114 if (!rsp) { 2115 printk(KERN_INFO 2116 "%s(): NULL response queue pointer.\n", __func__); 2117 return IRQ_NONE; 2118 } 2119 ha = rsp->hw; 2120 2121 reg = &ha->iobase->isp82; 2122 2123 spin_lock_irqsave(&ha->hardware_lock, flags); 2124 vha = pci_get_drvdata(ha->pdev); 2125 do { 2126 host_int = RD_REG_DWORD(®->host_int); 2127 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2128 break; 2129 if (host_int) { 2130 stat = RD_REG_DWORD(®->host_status); 2131 2132 switch (stat & 0xff) { 2133 case 0x1: 2134 case 0x2: 2135 case 0x10: 2136 case 0x11: 2137 qla82xx_mbx_completion(vha, MSW(stat)); 2138 status |= MBX_INTERRUPT; 2139 break; 2140 case 0x12: 2141 mb[0] = MSW(stat); 2142 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2143 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2144 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2145 qla2x00_async_event(vha, rsp, mb); 2146 break; 2147 case 0x13: 2148 qla24xx_process_response_queue(vha, rsp); 2149 break; 2150 default: 2151 ql_dbg(ql_dbg_async, vha, 0x5041, 2152 "Unrecognized interrupt type (%d).\n", 2153 stat & 0xff); 2154 break; 2155 } 2156 } 2157 WRT_REG_DWORD(®->host_int, 0); 2158 } while (0); 2159 2160 qla2x00_handle_mbx_completion(ha, status); 2161 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2162 2163 return IRQ_HANDLED; 2164 } 2165 2166 irqreturn_t 2167 qla82xx_msix_rsp_q(int irq, void *dev_id) 2168 { 2169 scsi_qla_host_t *vha; 2170 struct qla_hw_data *ha; 2171 struct rsp_que *rsp; 2172 struct device_reg_82xx __iomem *reg; 2173 unsigned long flags; 2174 uint32_t host_int = 0; 2175 2176 rsp = (struct rsp_que *) dev_id; 2177 if (!rsp) { 2178 printk(KERN_INFO 2179 "%s(): NULL response queue pointer.\n", __func__); 2180 return IRQ_NONE; 2181 } 2182 2183 ha = rsp->hw; 2184 reg = &ha->iobase->isp82; 2185 spin_lock_irqsave(&ha->hardware_lock, flags); 2186 vha = pci_get_drvdata(ha->pdev); 2187 host_int = RD_REG_DWORD(®->host_int); 2188 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2189 goto out; 2190 qla24xx_process_response_queue(vha, rsp); 2191 WRT_REG_DWORD(®->host_int, 0); 2192 out: 2193 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2194 return IRQ_HANDLED; 2195 } 2196 2197 void 2198 qla82xx_poll(int irq, void *dev_id) 2199 { 2200 scsi_qla_host_t *vha; 2201 struct qla_hw_data *ha; 2202 struct rsp_que *rsp; 2203 struct device_reg_82xx __iomem *reg; 2204 int status = 0; 2205 uint32_t stat; 2206 uint32_t host_int = 0; 2207 uint16_t mb[4]; 2208 unsigned long flags; 2209 2210 rsp = (struct rsp_que *) dev_id; 2211 if (!rsp) { 2212 printk(KERN_INFO 2213 "%s(): NULL response queue pointer.\n", __func__); 2214 return; 2215 } 2216 ha = rsp->hw; 2217 2218 reg = &ha->iobase->isp82; 2219 spin_lock_irqsave(&ha->hardware_lock, flags); 2220 vha = pci_get_drvdata(ha->pdev); 2221 2222 host_int = RD_REG_DWORD(®->host_int); 2223 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2224 goto out; 2225 if (host_int) { 2226 stat = RD_REG_DWORD(®->host_status); 2227 switch (stat & 0xff) { 2228 case 0x1: 2229 case 0x2: 2230 case 0x10: 2231 case 0x11: 2232 qla82xx_mbx_completion(vha, MSW(stat)); 2233 status |= MBX_INTERRUPT; 2234 break; 2235 case 0x12: 2236 mb[0] = MSW(stat); 2237 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2238 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2239 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2240 qla2x00_async_event(vha, rsp, mb); 2241 break; 2242 case 0x13: 2243 qla24xx_process_response_queue(vha, rsp); 2244 break; 2245 default: 2246 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2247 "Unrecognized interrupt type (%d).\n", 2248 stat * 0xff); 2249 break; 2250 } 2251 WRT_REG_DWORD(®->host_int, 0); 2252 } 2253 out: 2254 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2255 } 2256 2257 void 2258 qla82xx_enable_intrs(struct qla_hw_data *ha) 2259 { 2260 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2261 qla82xx_mbx_intr_enable(vha); 2262 spin_lock_irq(&ha->hardware_lock); 2263 if (IS_QLA8044(ha)) 2264 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2265 else 2266 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2267 spin_unlock_irq(&ha->hardware_lock); 2268 ha->interrupts_on = 1; 2269 } 2270 2271 void 2272 qla82xx_disable_intrs(struct qla_hw_data *ha) 2273 { 2274 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2275 qla82xx_mbx_intr_disable(vha); 2276 spin_lock_irq(&ha->hardware_lock); 2277 if (IS_QLA8044(ha)) 2278 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2279 else 2280 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2281 spin_unlock_irq(&ha->hardware_lock); 2282 ha->interrupts_on = 0; 2283 } 2284 2285 void qla82xx_init_flags(struct qla_hw_data *ha) 2286 { 2287 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2288 2289 /* ISP 8021 initializations */ 2290 rwlock_init(&ha->hw_lock); 2291 ha->qdr_sn_window = -1; 2292 ha->ddr_mn_window = -1; 2293 ha->curr_window = 255; 2294 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2295 nx_legacy_intr = &legacy_intr[ha->portnum]; 2296 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2297 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2298 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2299 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2300 } 2301 2302 static inline void 2303 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2304 { 2305 int idc_ver; 2306 uint32_t drv_active; 2307 struct qla_hw_data *ha = vha->hw; 2308 2309 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2310 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2311 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2312 QLA82XX_IDC_VERSION); 2313 ql_log(ql_log_info, vha, 0xb082, 2314 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2315 } else { 2316 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2317 if (idc_ver != QLA82XX_IDC_VERSION) 2318 ql_log(ql_log_info, vha, 0xb083, 2319 "qla2xxx driver IDC version %d is not compatible " 2320 "with IDC version %d of the other drivers\n", 2321 QLA82XX_IDC_VERSION, idc_ver); 2322 } 2323 } 2324 2325 inline void 2326 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2327 { 2328 uint32_t drv_active; 2329 struct qla_hw_data *ha = vha->hw; 2330 2331 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2332 2333 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2334 if (drv_active == 0xffffffff) { 2335 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2336 QLA82XX_DRV_NOT_ACTIVE); 2337 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2338 } 2339 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2340 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2341 } 2342 2343 inline void 2344 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2345 { 2346 uint32_t drv_active; 2347 2348 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2349 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2350 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2351 } 2352 2353 static inline int 2354 qla82xx_need_reset(struct qla_hw_data *ha) 2355 { 2356 uint32_t drv_state; 2357 int rval; 2358 2359 if (ha->flags.nic_core_reset_owner) 2360 return 1; 2361 else { 2362 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2363 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2364 return rval; 2365 } 2366 } 2367 2368 static inline void 2369 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2370 { 2371 uint32_t drv_state; 2372 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2373 2374 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2375 2376 /* If reset value is all FF's, initialize DRV_STATE */ 2377 if (drv_state == 0xffffffff) { 2378 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2379 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2380 } 2381 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2382 ql_dbg(ql_dbg_init, vha, 0x00bb, 2383 "drv_state = 0x%08x.\n", drv_state); 2384 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2385 } 2386 2387 static inline void 2388 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2389 { 2390 uint32_t drv_state; 2391 2392 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2393 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2394 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2395 } 2396 2397 static inline void 2398 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2399 { 2400 uint32_t qsnt_state; 2401 2402 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2403 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2404 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2405 } 2406 2407 void 2408 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2409 { 2410 struct qla_hw_data *ha = vha->hw; 2411 uint32_t qsnt_state; 2412 2413 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2414 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2415 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2416 } 2417 2418 static int 2419 qla82xx_load_fw(scsi_qla_host_t *vha) 2420 { 2421 int rst; 2422 struct fw_blob *blob; 2423 struct qla_hw_data *ha = vha->hw; 2424 2425 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2426 ql_log(ql_log_fatal, vha, 0x009f, 2427 "Error during CRB initialization.\n"); 2428 return QLA_FUNCTION_FAILED; 2429 } 2430 udelay(500); 2431 2432 /* Bring QM and CAMRAM out of reset */ 2433 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2434 rst &= ~((1 << 28) | (1 << 24)); 2435 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2436 2437 /* 2438 * FW Load priority: 2439 * 1) Operational firmware residing in flash. 2440 * 2) Firmware via request-firmware interface (.bin file). 2441 */ 2442 if (ql2xfwloadbin == 2) 2443 goto try_blob_fw; 2444 2445 ql_log(ql_log_info, vha, 0x00a0, 2446 "Attempting to load firmware from flash.\n"); 2447 2448 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2449 ql_log(ql_log_info, vha, 0x00a1, 2450 "Firmware loaded successfully from flash.\n"); 2451 return QLA_SUCCESS; 2452 } else { 2453 ql_log(ql_log_warn, vha, 0x0108, 2454 "Firmware load from flash failed.\n"); 2455 } 2456 2457 try_blob_fw: 2458 ql_log(ql_log_info, vha, 0x00a2, 2459 "Attempting to load firmware from blob.\n"); 2460 2461 /* Load firmware blob. */ 2462 blob = ha->hablob = qla2x00_request_firmware(vha); 2463 if (!blob) { 2464 ql_log(ql_log_fatal, vha, 0x00a3, 2465 "Firmware image not present.\n"); 2466 goto fw_load_failed; 2467 } 2468 2469 /* Validating firmware blob */ 2470 if (qla82xx_validate_firmware_blob(vha, 2471 QLA82XX_FLASH_ROMIMAGE)) { 2472 /* Fallback to URI format */ 2473 if (qla82xx_validate_firmware_blob(vha, 2474 QLA82XX_UNIFIED_ROMIMAGE)) { 2475 ql_log(ql_log_fatal, vha, 0x00a4, 2476 "No valid firmware image found.\n"); 2477 return QLA_FUNCTION_FAILED; 2478 } 2479 } 2480 2481 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2482 ql_log(ql_log_info, vha, 0x00a5, 2483 "Firmware loaded successfully from binary blob.\n"); 2484 return QLA_SUCCESS; 2485 } 2486 2487 ql_log(ql_log_fatal, vha, 0x00a6, 2488 "Firmware load failed for binary blob.\n"); 2489 blob->fw = NULL; 2490 blob = NULL; 2491 2492 fw_load_failed: 2493 return QLA_FUNCTION_FAILED; 2494 } 2495 2496 int 2497 qla82xx_start_firmware(scsi_qla_host_t *vha) 2498 { 2499 uint16_t lnk; 2500 struct qla_hw_data *ha = vha->hw; 2501 2502 /* scrub dma mask expansion register */ 2503 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2504 2505 /* Put both the PEG CMD and RCV PEG to default state 2506 * of 0 before resetting the hardware 2507 */ 2508 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2509 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2510 2511 /* Overwrite stale initialization register values */ 2512 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2513 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2514 2515 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2516 ql_log(ql_log_fatal, vha, 0x00a7, 2517 "Error trying to start fw.\n"); 2518 return QLA_FUNCTION_FAILED; 2519 } 2520 2521 /* Handshake with the card before we register the devices. */ 2522 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2523 ql_log(ql_log_fatal, vha, 0x00aa, 2524 "Error during card handshake.\n"); 2525 return QLA_FUNCTION_FAILED; 2526 } 2527 2528 /* Negotiated Link width */ 2529 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2530 ha->link_width = (lnk >> 4) & 0x3f; 2531 2532 /* Synchronize with Receive peg */ 2533 return qla82xx_check_rcvpeg_state(ha); 2534 } 2535 2536 static uint32_t * 2537 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2538 uint32_t length) 2539 { 2540 uint32_t i; 2541 uint32_t val; 2542 struct qla_hw_data *ha = vha->hw; 2543 2544 /* Dword reads to flash. */ 2545 for (i = 0; i < length/4; i++, faddr += 4) { 2546 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2547 ql_log(ql_log_warn, vha, 0x0106, 2548 "Do ROM fast read failed.\n"); 2549 goto done_read; 2550 } 2551 dwptr[i] = cpu_to_le32(val); 2552 } 2553 done_read: 2554 return dwptr; 2555 } 2556 2557 static int 2558 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2559 { 2560 int ret; 2561 uint32_t val; 2562 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2563 2564 ret = ql82xx_rom_lock_d(ha); 2565 if (ret < 0) { 2566 ql_log(ql_log_warn, vha, 0xb014, 2567 "ROM Lock failed.\n"); 2568 return ret; 2569 } 2570 2571 ret = qla82xx_read_status_reg(ha, &val); 2572 if (ret < 0) 2573 goto done_unprotect; 2574 2575 val &= ~(BLOCK_PROTECT_BITS << 2); 2576 ret = qla82xx_write_status_reg(ha, val); 2577 if (ret < 0) { 2578 val |= (BLOCK_PROTECT_BITS << 2); 2579 qla82xx_write_status_reg(ha, val); 2580 } 2581 2582 if (qla82xx_write_disable_flash(ha) != 0) 2583 ql_log(ql_log_warn, vha, 0xb015, 2584 "Write disable failed.\n"); 2585 2586 done_unprotect: 2587 qla82xx_rom_unlock(ha); 2588 return ret; 2589 } 2590 2591 static int 2592 qla82xx_protect_flash(struct qla_hw_data *ha) 2593 { 2594 int ret; 2595 uint32_t val; 2596 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2597 2598 ret = ql82xx_rom_lock_d(ha); 2599 if (ret < 0) { 2600 ql_log(ql_log_warn, vha, 0xb016, 2601 "ROM Lock failed.\n"); 2602 return ret; 2603 } 2604 2605 ret = qla82xx_read_status_reg(ha, &val); 2606 if (ret < 0) 2607 goto done_protect; 2608 2609 val |= (BLOCK_PROTECT_BITS << 2); 2610 /* LOCK all sectors */ 2611 ret = qla82xx_write_status_reg(ha, val); 2612 if (ret < 0) 2613 ql_log(ql_log_warn, vha, 0xb017, 2614 "Write status register failed.\n"); 2615 2616 if (qla82xx_write_disable_flash(ha) != 0) 2617 ql_log(ql_log_warn, vha, 0xb018, 2618 "Write disable failed.\n"); 2619 done_protect: 2620 qla82xx_rom_unlock(ha); 2621 return ret; 2622 } 2623 2624 static int 2625 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2626 { 2627 int ret = 0; 2628 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2629 2630 ret = ql82xx_rom_lock_d(ha); 2631 if (ret < 0) { 2632 ql_log(ql_log_warn, vha, 0xb019, 2633 "ROM Lock failed.\n"); 2634 return ret; 2635 } 2636 2637 qla82xx_flash_set_write_enable(ha); 2638 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2639 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2640 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2641 2642 if (qla82xx_wait_rom_done(ha)) { 2643 ql_log(ql_log_warn, vha, 0xb01a, 2644 "Error waiting for rom done.\n"); 2645 ret = -1; 2646 goto done; 2647 } 2648 ret = qla82xx_flash_wait_write_finish(ha); 2649 done: 2650 qla82xx_rom_unlock(ha); 2651 return ret; 2652 } 2653 2654 /* 2655 * Address and length are byte address 2656 */ 2657 uint8_t * 2658 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2659 uint32_t offset, uint32_t length) 2660 { 2661 scsi_block_requests(vha->host); 2662 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2663 scsi_unblock_requests(vha->host); 2664 return buf; 2665 } 2666 2667 static int 2668 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2669 uint32_t faddr, uint32_t dwords) 2670 { 2671 int ret; 2672 uint32_t liter; 2673 uint32_t rest_addr; 2674 dma_addr_t optrom_dma; 2675 void *optrom = NULL; 2676 int page_mode = 0; 2677 struct qla_hw_data *ha = vha->hw; 2678 2679 ret = -1; 2680 2681 /* Prepare burst-capable write on supported ISPs. */ 2682 if (page_mode && !(faddr & 0xfff) && 2683 dwords > OPTROM_BURST_DWORDS) { 2684 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2685 &optrom_dma, GFP_KERNEL); 2686 if (!optrom) { 2687 ql_log(ql_log_warn, vha, 0xb01b, 2688 "Unable to allocate memory " 2689 "for optrom burst write (%x KB).\n", 2690 OPTROM_BURST_SIZE / 1024); 2691 } 2692 } 2693 2694 rest_addr = ha->fdt_block_size - 1; 2695 2696 ret = qla82xx_unprotect_flash(ha); 2697 if (ret) { 2698 ql_log(ql_log_warn, vha, 0xb01c, 2699 "Unable to unprotect flash for update.\n"); 2700 goto write_done; 2701 } 2702 2703 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2704 /* Are we at the beginning of a sector? */ 2705 if ((faddr & rest_addr) == 0) { 2706 2707 ret = qla82xx_erase_sector(ha, faddr); 2708 if (ret) { 2709 ql_log(ql_log_warn, vha, 0xb01d, 2710 "Unable to erase sector: address=%x.\n", 2711 faddr); 2712 break; 2713 } 2714 } 2715 2716 /* Go with burst-write. */ 2717 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2718 /* Copy data to DMA'ble buffer. */ 2719 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2720 2721 ret = qla2x00_load_ram(vha, optrom_dma, 2722 (ha->flash_data_off | faddr), 2723 OPTROM_BURST_DWORDS); 2724 if (ret != QLA_SUCCESS) { 2725 ql_log(ql_log_warn, vha, 0xb01e, 2726 "Unable to burst-write optrom segment " 2727 "(%x/%x/%llx).\n", ret, 2728 (ha->flash_data_off | faddr), 2729 (unsigned long long)optrom_dma); 2730 ql_log(ql_log_warn, vha, 0xb01f, 2731 "Reverting to slow-write.\n"); 2732 2733 dma_free_coherent(&ha->pdev->dev, 2734 OPTROM_BURST_SIZE, optrom, optrom_dma); 2735 optrom = NULL; 2736 } else { 2737 liter += OPTROM_BURST_DWORDS - 1; 2738 faddr += OPTROM_BURST_DWORDS - 1; 2739 dwptr += OPTROM_BURST_DWORDS - 1; 2740 continue; 2741 } 2742 } 2743 2744 ret = qla82xx_write_flash_dword(ha, faddr, 2745 cpu_to_le32(*dwptr)); 2746 if (ret) { 2747 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2748 "Unable to program flash address=%x data=%x.\n", 2749 faddr, *dwptr); 2750 break; 2751 } 2752 } 2753 2754 ret = qla82xx_protect_flash(ha); 2755 if (ret) 2756 ql_log(ql_log_warn, vha, 0xb021, 2757 "Unable to protect flash after update.\n"); 2758 write_done: 2759 if (optrom) 2760 dma_free_coherent(&ha->pdev->dev, 2761 OPTROM_BURST_SIZE, optrom, optrom_dma); 2762 return ret; 2763 } 2764 2765 int 2766 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2767 uint32_t offset, uint32_t length) 2768 { 2769 int rval; 2770 2771 /* Suspend HBA. */ 2772 scsi_block_requests(vha->host); 2773 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2774 length >> 2); 2775 scsi_unblock_requests(vha->host); 2776 2777 /* Convert return ISP82xx to generic */ 2778 if (rval) 2779 rval = QLA_FUNCTION_FAILED; 2780 else 2781 rval = QLA_SUCCESS; 2782 return rval; 2783 } 2784 2785 void 2786 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2787 { 2788 struct qla_hw_data *ha = vha->hw; 2789 struct req_que *req = ha->req_q_map[0]; 2790 uint32_t dbval; 2791 2792 /* Adjust ring index. */ 2793 req->ring_index++; 2794 if (req->ring_index == req->length) { 2795 req->ring_index = 0; 2796 req->ring_ptr = req->ring; 2797 } else 2798 req->ring_ptr++; 2799 2800 dbval = 0x04 | (ha->portnum << 5); 2801 2802 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2803 if (ql2xdbwr) 2804 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2805 else { 2806 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2807 wmb(); 2808 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2809 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2810 wmb(); 2811 } 2812 } 2813 } 2814 2815 static void 2816 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2817 { 2818 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2819 uint32_t lock_owner = 0; 2820 2821 if (qla82xx_rom_lock(ha)) { 2822 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2823 /* Someone else is holding the lock. */ 2824 ql_log(ql_log_info, vha, 0xb022, 2825 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2826 } 2827 /* 2828 * Either we got the lock, or someone 2829 * else died while holding it. 2830 * In either case, unlock. 2831 */ 2832 qla82xx_rom_unlock(ha); 2833 } 2834 2835 /* 2836 * qla82xx_device_bootstrap 2837 * Initialize device, set DEV_READY, start fw 2838 * 2839 * Note: 2840 * IDC lock must be held upon entry 2841 * 2842 * Return: 2843 * Success : 0 2844 * Failed : 1 2845 */ 2846 static int 2847 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2848 { 2849 int rval = QLA_SUCCESS; 2850 int i; 2851 uint32_t old_count, count; 2852 struct qla_hw_data *ha = vha->hw; 2853 int need_reset = 0; 2854 2855 need_reset = qla82xx_need_reset(ha); 2856 2857 if (need_reset) { 2858 /* We are trying to perform a recovery here. */ 2859 if (ha->flags.isp82xx_fw_hung) 2860 qla82xx_rom_lock_recovery(ha); 2861 } else { 2862 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2863 for (i = 0; i < 10; i++) { 2864 msleep(200); 2865 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2866 if (count != old_count) { 2867 rval = QLA_SUCCESS; 2868 goto dev_ready; 2869 } 2870 } 2871 qla82xx_rom_lock_recovery(ha); 2872 } 2873 2874 /* set to DEV_INITIALIZING */ 2875 ql_log(ql_log_info, vha, 0x009e, 2876 "HW State: INITIALIZING.\n"); 2877 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2878 2879 qla82xx_idc_unlock(ha); 2880 rval = qla82xx_start_firmware(vha); 2881 qla82xx_idc_lock(ha); 2882 2883 if (rval != QLA_SUCCESS) { 2884 ql_log(ql_log_fatal, vha, 0x00ad, 2885 "HW State: FAILED.\n"); 2886 qla82xx_clear_drv_active(ha); 2887 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2888 return rval; 2889 } 2890 2891 dev_ready: 2892 ql_log(ql_log_info, vha, 0x00ae, 2893 "HW State: READY.\n"); 2894 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2895 2896 return QLA_SUCCESS; 2897 } 2898 2899 /* 2900 * qla82xx_need_qsnt_handler 2901 * Code to start quiescence sequence 2902 * 2903 * Note: 2904 * IDC lock must be held upon entry 2905 * 2906 * Return: void 2907 */ 2908 2909 static void 2910 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2911 { 2912 struct qla_hw_data *ha = vha->hw; 2913 uint32_t dev_state, drv_state, drv_active; 2914 unsigned long reset_timeout; 2915 2916 if (vha->flags.online) { 2917 /*Block any further I/O and wait for pending cmnds to complete*/ 2918 qla2x00_quiesce_io(vha); 2919 } 2920 2921 /* Set the quiescence ready bit */ 2922 qla82xx_set_qsnt_ready(ha); 2923 2924 /*wait for 30 secs for other functions to ack */ 2925 reset_timeout = jiffies + (30 * HZ); 2926 2927 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2928 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2929 /* Its 2 that is written when qsnt is acked, moving one bit */ 2930 drv_active = drv_active << 0x01; 2931 2932 while (drv_state != drv_active) { 2933 2934 if (time_after_eq(jiffies, reset_timeout)) { 2935 /* quiescence timeout, other functions didn't ack 2936 * changing the state to DEV_READY 2937 */ 2938 ql_log(ql_log_info, vha, 0xb023, 2939 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2940 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2941 drv_active, drv_state); 2942 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2943 QLA8XXX_DEV_READY); 2944 ql_log(ql_log_info, vha, 0xb025, 2945 "HW State: DEV_READY.\n"); 2946 qla82xx_idc_unlock(ha); 2947 qla2x00_perform_loop_resync(vha); 2948 qla82xx_idc_lock(ha); 2949 2950 qla82xx_clear_qsnt_ready(vha); 2951 return; 2952 } 2953 2954 qla82xx_idc_unlock(ha); 2955 msleep(1000); 2956 qla82xx_idc_lock(ha); 2957 2958 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2959 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2960 drv_active = drv_active << 0x01; 2961 } 2962 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2963 /* everyone acked so set the state to DEV_QUIESCENCE */ 2964 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2965 ql_log(ql_log_info, vha, 0xb026, 2966 "HW State: DEV_QUIESCENT.\n"); 2967 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2968 } 2969 } 2970 2971 /* 2972 * qla82xx_wait_for_state_change 2973 * Wait for device state to change from given current state 2974 * 2975 * Note: 2976 * IDC lock must not be held upon entry 2977 * 2978 * Return: 2979 * Changed device state. 2980 */ 2981 uint32_t 2982 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2983 { 2984 struct qla_hw_data *ha = vha->hw; 2985 uint32_t dev_state; 2986 2987 do { 2988 msleep(1000); 2989 qla82xx_idc_lock(ha); 2990 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2991 qla82xx_idc_unlock(ha); 2992 } while (dev_state == curr_state); 2993 2994 return dev_state; 2995 } 2996 2997 void 2998 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2999 { 3000 struct qla_hw_data *ha = vha->hw; 3001 3002 /* Disable the board */ 3003 ql_log(ql_log_fatal, vha, 0x00b8, 3004 "Disabling the board.\n"); 3005 3006 if (IS_QLA82XX(ha)) { 3007 qla82xx_clear_drv_active(ha); 3008 qla82xx_idc_unlock(ha); 3009 } else if (IS_QLA8044(ha)) { 3010 qla8044_clear_drv_active(ha); 3011 qla8044_idc_unlock(ha); 3012 } 3013 3014 /* Set DEV_FAILED flag to disable timer */ 3015 vha->device_flags |= DFLG_DEV_FAILED; 3016 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3017 qla2x00_mark_all_devices_lost(vha, 0); 3018 vha->flags.online = 0; 3019 vha->flags.init_done = 0; 3020 } 3021 3022 /* 3023 * qla82xx_need_reset_handler 3024 * Code to start reset sequence 3025 * 3026 * Note: 3027 * IDC lock must be held upon entry 3028 * 3029 * Return: 3030 * Success : 0 3031 * Failed : 1 3032 */ 3033 static void 3034 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3035 { 3036 uint32_t dev_state, drv_state, drv_active; 3037 uint32_t active_mask = 0; 3038 unsigned long reset_timeout; 3039 struct qla_hw_data *ha = vha->hw; 3040 struct req_que *req = ha->req_q_map[0]; 3041 3042 if (vha->flags.online) { 3043 qla82xx_idc_unlock(ha); 3044 qla2x00_abort_isp_cleanup(vha); 3045 ha->isp_ops->get_flash_version(vha, req->ring); 3046 ha->isp_ops->nvram_config(vha); 3047 qla82xx_idc_lock(ha); 3048 } 3049 3050 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3051 if (!ha->flags.nic_core_reset_owner) { 3052 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3053 "reset_acknowledged by 0x%x\n", ha->portnum); 3054 qla82xx_set_rst_ready(ha); 3055 } else { 3056 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3057 drv_active &= active_mask; 3058 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3059 "active_mask: 0x%08x\n", active_mask); 3060 } 3061 3062 /* wait for 10 seconds for reset ack from all functions */ 3063 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3064 3065 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3066 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3067 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3068 3069 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3070 "drv_state: 0x%08x, drv_active: 0x%08x, " 3071 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3072 drv_state, drv_active, dev_state, active_mask); 3073 3074 while (drv_state != drv_active && 3075 dev_state != QLA8XXX_DEV_INITIALIZING) { 3076 if (time_after_eq(jiffies, reset_timeout)) { 3077 ql_log(ql_log_warn, vha, 0x00b5, 3078 "Reset timeout.\n"); 3079 break; 3080 } 3081 qla82xx_idc_unlock(ha); 3082 msleep(1000); 3083 qla82xx_idc_lock(ha); 3084 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3085 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3086 if (ha->flags.nic_core_reset_owner) 3087 drv_active &= active_mask; 3088 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3089 } 3090 3091 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3092 "drv_state: 0x%08x, drv_active: 0x%08x, " 3093 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3094 drv_state, drv_active, dev_state, active_mask); 3095 3096 ql_log(ql_log_info, vha, 0x00b6, 3097 "Device state is 0x%x = %s.\n", 3098 dev_state, 3099 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3100 3101 /* Force to DEV_COLD unless someone else is starting a reset */ 3102 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3103 dev_state != QLA8XXX_DEV_COLD) { 3104 ql_log(ql_log_info, vha, 0x00b7, 3105 "HW State: COLD/RE-INIT.\n"); 3106 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3107 qla82xx_set_rst_ready(ha); 3108 if (ql2xmdenable) { 3109 if (qla82xx_md_collect(vha)) 3110 ql_log(ql_log_warn, vha, 0xb02c, 3111 "Minidump not collected.\n"); 3112 } else 3113 ql_log(ql_log_warn, vha, 0xb04f, 3114 "Minidump disabled.\n"); 3115 } 3116 } 3117 3118 int 3119 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3120 { 3121 struct qla_hw_data *ha = vha->hw; 3122 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3123 int rval = QLA_SUCCESS; 3124 3125 fw_major_version = ha->fw_major_version; 3126 fw_minor_version = ha->fw_minor_version; 3127 fw_subminor_version = ha->fw_subminor_version; 3128 3129 rval = qla2x00_get_fw_version(vha); 3130 if (rval != QLA_SUCCESS) 3131 return rval; 3132 3133 if (ql2xmdenable) { 3134 if (!ha->fw_dumped) { 3135 if ((fw_major_version != ha->fw_major_version || 3136 fw_minor_version != ha->fw_minor_version || 3137 fw_subminor_version != ha->fw_subminor_version) || 3138 (ha->prev_minidump_failed)) { 3139 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3140 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3141 fw_major_version, fw_minor_version, 3142 fw_subminor_version, 3143 ha->fw_major_version, 3144 ha->fw_minor_version, 3145 ha->fw_subminor_version, 3146 ha->prev_minidump_failed); 3147 /* Release MiniDump resources */ 3148 qla82xx_md_free(vha); 3149 /* ALlocate MiniDump resources */ 3150 qla82xx_md_prep(vha); 3151 } 3152 } else 3153 ql_log(ql_log_info, vha, 0xb02e, 3154 "Firmware dump available to retrieve\n"); 3155 } 3156 return rval; 3157 } 3158 3159 3160 static int 3161 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3162 { 3163 uint32_t fw_heartbeat_counter; 3164 int status = 0; 3165 3166 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3167 QLA82XX_PEG_ALIVE_COUNTER); 3168 /* all 0xff, assume AER/EEH in progress, ignore */ 3169 if (fw_heartbeat_counter == 0xffffffff) { 3170 ql_dbg(ql_dbg_timer, vha, 0x6003, 3171 "FW heartbeat counter is 0xffffffff, " 3172 "returning status=%d.\n", status); 3173 return status; 3174 } 3175 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3176 vha->seconds_since_last_heartbeat++; 3177 /* FW not alive after 2 seconds */ 3178 if (vha->seconds_since_last_heartbeat == 2) { 3179 vha->seconds_since_last_heartbeat = 0; 3180 status = 1; 3181 } 3182 } else 3183 vha->seconds_since_last_heartbeat = 0; 3184 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3185 if (status) 3186 ql_dbg(ql_dbg_timer, vha, 0x6004, 3187 "Returning status=%d.\n", status); 3188 return status; 3189 } 3190 3191 /* 3192 * qla82xx_device_state_handler 3193 * Main state handler 3194 * 3195 * Note: 3196 * IDC lock must be held upon entry 3197 * 3198 * Return: 3199 * Success : 0 3200 * Failed : 1 3201 */ 3202 int 3203 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3204 { 3205 uint32_t dev_state; 3206 uint32_t old_dev_state; 3207 int rval = QLA_SUCCESS; 3208 unsigned long dev_init_timeout; 3209 struct qla_hw_data *ha = vha->hw; 3210 int loopcount = 0; 3211 3212 qla82xx_idc_lock(ha); 3213 if (!vha->flags.init_done) { 3214 qla82xx_set_drv_active(vha); 3215 qla82xx_set_idc_version(vha); 3216 } 3217 3218 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3219 old_dev_state = dev_state; 3220 ql_log(ql_log_info, vha, 0x009b, 3221 "Device state is 0x%x = %s.\n", 3222 dev_state, 3223 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3224 3225 /* wait for 30 seconds for device to go ready */ 3226 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3227 3228 while (1) { 3229 3230 if (time_after_eq(jiffies, dev_init_timeout)) { 3231 ql_log(ql_log_fatal, vha, 0x009c, 3232 "Device init failed.\n"); 3233 rval = QLA_FUNCTION_FAILED; 3234 break; 3235 } 3236 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3237 if (old_dev_state != dev_state) { 3238 loopcount = 0; 3239 old_dev_state = dev_state; 3240 } 3241 if (loopcount < 5) { 3242 ql_log(ql_log_info, vha, 0x009d, 3243 "Device state is 0x%x = %s.\n", 3244 dev_state, 3245 dev_state < MAX_STATES ? qdev_state(dev_state) : 3246 "Unknown"); 3247 } 3248 3249 switch (dev_state) { 3250 case QLA8XXX_DEV_READY: 3251 ha->flags.nic_core_reset_owner = 0; 3252 goto rel_lock; 3253 case QLA8XXX_DEV_COLD: 3254 rval = qla82xx_device_bootstrap(vha); 3255 break; 3256 case QLA8XXX_DEV_INITIALIZING: 3257 qla82xx_idc_unlock(ha); 3258 msleep(1000); 3259 qla82xx_idc_lock(ha); 3260 break; 3261 case QLA8XXX_DEV_NEED_RESET: 3262 if (!ql2xdontresethba) 3263 qla82xx_need_reset_handler(vha); 3264 else { 3265 qla82xx_idc_unlock(ha); 3266 msleep(1000); 3267 qla82xx_idc_lock(ha); 3268 } 3269 dev_init_timeout = jiffies + 3270 (ha->fcoe_dev_init_timeout * HZ); 3271 break; 3272 case QLA8XXX_DEV_NEED_QUIESCENT: 3273 qla82xx_need_qsnt_handler(vha); 3274 /* Reset timeout value after quiescence handler */ 3275 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3276 * HZ); 3277 break; 3278 case QLA8XXX_DEV_QUIESCENT: 3279 /* Owner will exit and other will wait for the state 3280 * to get changed 3281 */ 3282 if (ha->flags.quiesce_owner) 3283 goto rel_lock; 3284 3285 qla82xx_idc_unlock(ha); 3286 msleep(1000); 3287 qla82xx_idc_lock(ha); 3288 3289 /* Reset timeout value after quiescence handler */ 3290 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3291 * HZ); 3292 break; 3293 case QLA8XXX_DEV_FAILED: 3294 qla8xxx_dev_failed_handler(vha); 3295 rval = QLA_FUNCTION_FAILED; 3296 goto exit; 3297 default: 3298 qla82xx_idc_unlock(ha); 3299 msleep(1000); 3300 qla82xx_idc_lock(ha); 3301 } 3302 loopcount++; 3303 } 3304 rel_lock: 3305 qla82xx_idc_unlock(ha); 3306 exit: 3307 return rval; 3308 } 3309 3310 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3311 { 3312 uint32_t temp, temp_state, temp_val; 3313 struct qla_hw_data *ha = vha->hw; 3314 3315 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3316 temp_state = qla82xx_get_temp_state(temp); 3317 temp_val = qla82xx_get_temp_val(temp); 3318 3319 if (temp_state == QLA82XX_TEMP_PANIC) { 3320 ql_log(ql_log_warn, vha, 0x600e, 3321 "Device temperature %d degrees C exceeds " 3322 " maximum allowed. Hardware has been shut down.\n", 3323 temp_val); 3324 return 1; 3325 } else if (temp_state == QLA82XX_TEMP_WARN) { 3326 ql_log(ql_log_warn, vha, 0x600f, 3327 "Device temperature %d degrees C exceeds " 3328 "operating range. Immediate action needed.\n", 3329 temp_val); 3330 } 3331 return 0; 3332 } 3333 3334 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3335 { 3336 uint32_t temp; 3337 3338 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3339 return qla82xx_get_temp_val(temp); 3340 } 3341 3342 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3343 { 3344 struct qla_hw_data *ha = vha->hw; 3345 3346 if (ha->flags.mbox_busy) { 3347 ha->flags.mbox_int = 1; 3348 ha->flags.mbox_busy = 0; 3349 ql_log(ql_log_warn, vha, 0x6010, 3350 "Doing premature completion of mbx command.\n"); 3351 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3352 complete(&ha->mbx_intr_comp); 3353 } 3354 } 3355 3356 void qla82xx_watchdog(scsi_qla_host_t *vha) 3357 { 3358 uint32_t dev_state, halt_status; 3359 struct qla_hw_data *ha = vha->hw; 3360 3361 /* don't poll if reset is going on */ 3362 if (!ha->flags.nic_core_reset_hdlr_active) { 3363 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3364 if (qla82xx_check_temp(vha)) { 3365 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3366 ha->flags.isp82xx_fw_hung = 1; 3367 qla82xx_clear_pending_mbx(vha); 3368 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3369 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3370 ql_log(ql_log_warn, vha, 0x6001, 3371 "Adapter reset needed.\n"); 3372 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3373 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3374 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3375 ql_log(ql_log_warn, vha, 0x6002, 3376 "Quiescent needed.\n"); 3377 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3378 } else if (dev_state == QLA8XXX_DEV_FAILED && 3379 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3380 vha->flags.online == 1) { 3381 ql_log(ql_log_warn, vha, 0xb055, 3382 "Adapter state is failed. Offlining.\n"); 3383 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3384 ha->flags.isp82xx_fw_hung = 1; 3385 qla82xx_clear_pending_mbx(vha); 3386 } else { 3387 if (qla82xx_check_fw_alive(vha)) { 3388 ql_dbg(ql_dbg_timer, vha, 0x6011, 3389 "disabling pause transmit on port 0 & 1.\n"); 3390 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3391 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3392 halt_status = qla82xx_rd_32(ha, 3393 QLA82XX_PEG_HALT_STATUS1); 3394 ql_log(ql_log_info, vha, 0x6005, 3395 "dumping hw/fw registers:.\n " 3396 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3397 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3398 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3399 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3400 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3401 qla82xx_rd_32(ha, 3402 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3403 qla82xx_rd_32(ha, 3404 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3405 qla82xx_rd_32(ha, 3406 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3407 qla82xx_rd_32(ha, 3408 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3409 qla82xx_rd_32(ha, 3410 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3411 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3412 ql_log(ql_log_warn, vha, 0xb052, 3413 "Firmware aborted with " 3414 "error code 0x00006700. Device is " 3415 "being reset.\n"); 3416 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3417 set_bit(ISP_UNRECOVERABLE, 3418 &vha->dpc_flags); 3419 } else { 3420 ql_log(ql_log_info, vha, 0x6006, 3421 "Detect abort needed.\n"); 3422 set_bit(ISP_ABORT_NEEDED, 3423 &vha->dpc_flags); 3424 } 3425 ha->flags.isp82xx_fw_hung = 1; 3426 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3427 qla82xx_clear_pending_mbx(vha); 3428 } 3429 } 3430 } 3431 } 3432 3433 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3434 { 3435 int rval = -1; 3436 struct qla_hw_data *ha = vha->hw; 3437 3438 if (IS_QLA82XX(ha)) 3439 rval = qla82xx_device_state_handler(vha); 3440 else if (IS_QLA8044(ha)) { 3441 qla8044_idc_lock(ha); 3442 /* Decide the reset ownership */ 3443 qla83xx_reset_ownership(vha); 3444 qla8044_idc_unlock(ha); 3445 rval = qla8044_device_state_handler(vha); 3446 } 3447 return rval; 3448 } 3449 3450 void 3451 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3452 { 3453 struct qla_hw_data *ha = vha->hw; 3454 uint32_t dev_state = 0; 3455 3456 if (IS_QLA82XX(ha)) 3457 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3458 else if (IS_QLA8044(ha)) 3459 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3460 3461 if (dev_state == QLA8XXX_DEV_READY) { 3462 ql_log(ql_log_info, vha, 0xb02f, 3463 "HW State: NEED RESET\n"); 3464 if (IS_QLA82XX(ha)) { 3465 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3466 QLA8XXX_DEV_NEED_RESET); 3467 ha->flags.nic_core_reset_owner = 1; 3468 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3469 "reset_owner is 0x%x\n", ha->portnum); 3470 } else if (IS_QLA8044(ha)) 3471 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3472 QLA8XXX_DEV_NEED_RESET); 3473 } else 3474 ql_log(ql_log_info, vha, 0xb031, 3475 "Device state is 0x%x = %s.\n", 3476 dev_state, 3477 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3478 } 3479 3480 /* 3481 * qla82xx_abort_isp 3482 * Resets ISP and aborts all outstanding commands. 3483 * 3484 * Input: 3485 * ha = adapter block pointer. 3486 * 3487 * Returns: 3488 * 0 = success 3489 */ 3490 int 3491 qla82xx_abort_isp(scsi_qla_host_t *vha) 3492 { 3493 int rval = -1; 3494 struct qla_hw_data *ha = vha->hw; 3495 3496 if (vha->device_flags & DFLG_DEV_FAILED) { 3497 ql_log(ql_log_warn, vha, 0x8024, 3498 "Device in failed state, exiting.\n"); 3499 return QLA_SUCCESS; 3500 } 3501 ha->flags.nic_core_reset_hdlr_active = 1; 3502 3503 qla82xx_idc_lock(ha); 3504 qla82xx_set_reset_owner(vha); 3505 qla82xx_idc_unlock(ha); 3506 3507 if (IS_QLA82XX(ha)) 3508 rval = qla82xx_device_state_handler(vha); 3509 else if (IS_QLA8044(ha)) { 3510 qla8044_idc_lock(ha); 3511 /* Decide the reset ownership */ 3512 qla83xx_reset_ownership(vha); 3513 qla8044_idc_unlock(ha); 3514 rval = qla8044_device_state_handler(vha); 3515 } 3516 3517 qla82xx_idc_lock(ha); 3518 qla82xx_clear_rst_ready(ha); 3519 qla82xx_idc_unlock(ha); 3520 3521 if (rval == QLA_SUCCESS) { 3522 ha->flags.isp82xx_fw_hung = 0; 3523 ha->flags.nic_core_reset_hdlr_active = 0; 3524 qla82xx_restart_isp(vha); 3525 } 3526 3527 if (rval) { 3528 vha->flags.online = 1; 3529 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3530 if (ha->isp_abort_cnt == 0) { 3531 ql_log(ql_log_warn, vha, 0x8027, 3532 "ISP error recover failed - board " 3533 "disabled.\n"); 3534 /* 3535 * The next call disables the board 3536 * completely. 3537 */ 3538 ha->isp_ops->reset_adapter(vha); 3539 vha->flags.online = 0; 3540 clear_bit(ISP_ABORT_RETRY, 3541 &vha->dpc_flags); 3542 rval = QLA_SUCCESS; 3543 } else { /* schedule another ISP abort */ 3544 ha->isp_abort_cnt--; 3545 ql_log(ql_log_warn, vha, 0x8036, 3546 "ISP abort - retry remaining %d.\n", 3547 ha->isp_abort_cnt); 3548 rval = QLA_FUNCTION_FAILED; 3549 } 3550 } else { 3551 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3552 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3553 "ISP error recovery - retrying (%d) more times.\n", 3554 ha->isp_abort_cnt); 3555 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3556 rval = QLA_FUNCTION_FAILED; 3557 } 3558 } 3559 return rval; 3560 } 3561 3562 /* 3563 * qla82xx_fcoe_ctx_reset 3564 * Perform a quick reset and aborts all outstanding commands. 3565 * This will only perform an FCoE context reset and avoids a full blown 3566 * chip reset. 3567 * 3568 * Input: 3569 * ha = adapter block pointer. 3570 * is_reset_path = flag for identifying the reset path. 3571 * 3572 * Returns: 3573 * 0 = success 3574 */ 3575 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3576 { 3577 int rval = QLA_FUNCTION_FAILED; 3578 3579 if (vha->flags.online) { 3580 /* Abort all outstanding commands, so as to be requeued later */ 3581 qla2x00_abort_isp_cleanup(vha); 3582 } 3583 3584 /* Stop currently executing firmware. 3585 * This will destroy existing FCoE context at the F/W end. 3586 */ 3587 qla2x00_try_to_stop_firmware(vha); 3588 3589 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3590 rval = qla82xx_restart_isp(vha); 3591 3592 return rval; 3593 } 3594 3595 /* 3596 * qla2x00_wait_for_fcoe_ctx_reset 3597 * Wait till the FCoE context is reset. 3598 * 3599 * Note: 3600 * Does context switching here. 3601 * Release SPIN_LOCK (if any) before calling this routine. 3602 * 3603 * Return: 3604 * Success (fcoe_ctx reset is done) : 0 3605 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3606 */ 3607 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3608 { 3609 int status = QLA_FUNCTION_FAILED; 3610 unsigned long wait_reset; 3611 3612 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3613 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3614 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3615 && time_before(jiffies, wait_reset)) { 3616 3617 set_current_state(TASK_UNINTERRUPTIBLE); 3618 schedule_timeout(HZ); 3619 3620 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3621 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3622 status = QLA_SUCCESS; 3623 break; 3624 } 3625 } 3626 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3627 "%s: status=%d.\n", __func__, status); 3628 3629 return status; 3630 } 3631 3632 void 3633 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3634 { 3635 int i, fw_state = 0; 3636 unsigned long flags; 3637 struct qla_hw_data *ha = vha->hw; 3638 3639 /* Check if 82XX firmware is alive or not 3640 * We may have arrived here from NEED_RESET 3641 * detection only 3642 */ 3643 if (!ha->flags.isp82xx_fw_hung) { 3644 for (i = 0; i < 2; i++) { 3645 msleep(1000); 3646 if (IS_QLA82XX(ha)) 3647 fw_state = qla82xx_check_fw_alive(vha); 3648 else if (IS_QLA8044(ha)) 3649 fw_state = qla8044_check_fw_alive(vha); 3650 if (fw_state) { 3651 ha->flags.isp82xx_fw_hung = 1; 3652 qla82xx_clear_pending_mbx(vha); 3653 break; 3654 } 3655 } 3656 } 3657 ql_dbg(ql_dbg_init, vha, 0x00b0, 3658 "Entered %s fw_hung=%d.\n", 3659 __func__, ha->flags.isp82xx_fw_hung); 3660 3661 /* Abort all commands gracefully if fw NOT hung */ 3662 if (!ha->flags.isp82xx_fw_hung) { 3663 int cnt, que; 3664 srb_t *sp; 3665 struct req_que *req; 3666 3667 spin_lock_irqsave(&ha->hardware_lock, flags); 3668 for (que = 0; que < ha->max_req_queues; que++) { 3669 req = ha->req_q_map[que]; 3670 if (!req) 3671 continue; 3672 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3673 sp = req->outstanding_cmds[cnt]; 3674 if (sp) { 3675 if ((!sp->u.scmd.ctx || 3676 (sp->flags & 3677 SRB_FCP_CMND_DMA_VALID)) && 3678 !ha->flags.isp82xx_fw_hung) { 3679 spin_unlock_irqrestore( 3680 &ha->hardware_lock, flags); 3681 if (ha->isp_ops->abort_command(sp)) { 3682 ql_log(ql_log_info, vha, 3683 0x00b1, 3684 "mbx abort failed.\n"); 3685 } else { 3686 ql_log(ql_log_info, vha, 3687 0x00b2, 3688 "mbx abort success.\n"); 3689 } 3690 spin_lock_irqsave(&ha->hardware_lock, flags); 3691 } 3692 } 3693 } 3694 } 3695 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3696 3697 /* Wait for pending cmds (physical and virtual) to complete */ 3698 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3699 WAIT_HOST) == QLA_SUCCESS) { 3700 ql_dbg(ql_dbg_init, vha, 0x00b3, 3701 "Done wait for " 3702 "pending commands.\n"); 3703 } 3704 } 3705 } 3706 3707 /* Minidump related functions */ 3708 static int 3709 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3710 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3711 { 3712 struct qla_hw_data *ha = vha->hw; 3713 struct qla82xx_md_entry_crb *crb_entry; 3714 uint32_t read_value, opcode, poll_time; 3715 uint32_t addr, index, crb_addr; 3716 unsigned long wtime; 3717 struct qla82xx_md_template_hdr *tmplt_hdr; 3718 uint32_t rval = QLA_SUCCESS; 3719 int i; 3720 3721 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3722 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3723 crb_addr = crb_entry->addr; 3724 3725 for (i = 0; i < crb_entry->op_count; i++) { 3726 opcode = crb_entry->crb_ctrl.opcode; 3727 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3728 qla82xx_md_rw_32(ha, crb_addr, 3729 crb_entry->value_1, 1); 3730 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3731 } 3732 3733 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3734 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3735 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3736 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3737 } 3738 3739 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3740 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3741 read_value &= crb_entry->value_2; 3742 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3743 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3744 read_value |= crb_entry->value_3; 3745 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3746 } 3747 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3748 } 3749 3750 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3751 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3752 read_value |= crb_entry->value_3; 3753 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3754 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3755 } 3756 3757 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3758 poll_time = crb_entry->crb_strd.poll_timeout; 3759 wtime = jiffies + poll_time; 3760 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3761 3762 do { 3763 if ((read_value & crb_entry->value_2) 3764 == crb_entry->value_1) 3765 break; 3766 else if (time_after_eq(jiffies, wtime)) { 3767 /* capturing dump failed */ 3768 rval = QLA_FUNCTION_FAILED; 3769 break; 3770 } else 3771 read_value = qla82xx_md_rw_32(ha, 3772 crb_addr, 0, 0); 3773 } while (1); 3774 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3775 } 3776 3777 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3778 if (crb_entry->crb_strd.state_index_a) { 3779 index = crb_entry->crb_strd.state_index_a; 3780 addr = tmplt_hdr->saved_state_array[index]; 3781 } else 3782 addr = crb_addr; 3783 3784 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3785 index = crb_entry->crb_ctrl.state_index_v; 3786 tmplt_hdr->saved_state_array[index] = read_value; 3787 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3788 } 3789 3790 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3791 if (crb_entry->crb_strd.state_index_a) { 3792 index = crb_entry->crb_strd.state_index_a; 3793 addr = tmplt_hdr->saved_state_array[index]; 3794 } else 3795 addr = crb_addr; 3796 3797 if (crb_entry->crb_ctrl.state_index_v) { 3798 index = crb_entry->crb_ctrl.state_index_v; 3799 read_value = 3800 tmplt_hdr->saved_state_array[index]; 3801 } else 3802 read_value = crb_entry->value_1; 3803 3804 qla82xx_md_rw_32(ha, addr, read_value, 1); 3805 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3806 } 3807 3808 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3809 index = crb_entry->crb_ctrl.state_index_v; 3810 read_value = tmplt_hdr->saved_state_array[index]; 3811 read_value <<= crb_entry->crb_ctrl.shl; 3812 read_value >>= crb_entry->crb_ctrl.shr; 3813 if (crb_entry->value_2) 3814 read_value &= crb_entry->value_2; 3815 read_value |= crb_entry->value_3; 3816 read_value += crb_entry->value_1; 3817 tmplt_hdr->saved_state_array[index] = read_value; 3818 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3819 } 3820 crb_addr += crb_entry->crb_strd.addr_stride; 3821 } 3822 return rval; 3823 } 3824 3825 static void 3826 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3827 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3828 { 3829 struct qla_hw_data *ha = vha->hw; 3830 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3831 struct qla82xx_md_entry_rdocm *ocm_hdr; 3832 uint32_t *data_ptr = *d_ptr; 3833 3834 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3835 r_addr = ocm_hdr->read_addr; 3836 r_stride = ocm_hdr->read_addr_stride; 3837 loop_cnt = ocm_hdr->op_count; 3838 3839 for (i = 0; i < loop_cnt; i++) { 3840 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase); 3841 *data_ptr++ = cpu_to_le32(r_value); 3842 r_addr += r_stride; 3843 } 3844 *d_ptr = data_ptr; 3845 } 3846 3847 static void 3848 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3849 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3850 { 3851 struct qla_hw_data *ha = vha->hw; 3852 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3853 struct qla82xx_md_entry_mux *mux_hdr; 3854 uint32_t *data_ptr = *d_ptr; 3855 3856 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3857 r_addr = mux_hdr->read_addr; 3858 s_addr = mux_hdr->select_addr; 3859 s_stride = mux_hdr->select_value_stride; 3860 s_value = mux_hdr->select_value; 3861 loop_cnt = mux_hdr->op_count; 3862 3863 for (i = 0; i < loop_cnt; i++) { 3864 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3865 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3866 *data_ptr++ = cpu_to_le32(s_value); 3867 *data_ptr++ = cpu_to_le32(r_value); 3868 s_value += s_stride; 3869 } 3870 *d_ptr = data_ptr; 3871 } 3872 3873 static void 3874 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3875 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3876 { 3877 struct qla_hw_data *ha = vha->hw; 3878 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3879 struct qla82xx_md_entry_crb *crb_hdr; 3880 uint32_t *data_ptr = *d_ptr; 3881 3882 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3883 r_addr = crb_hdr->addr; 3884 r_stride = crb_hdr->crb_strd.addr_stride; 3885 loop_cnt = crb_hdr->op_count; 3886 3887 for (i = 0; i < loop_cnt; i++) { 3888 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3889 *data_ptr++ = cpu_to_le32(r_addr); 3890 *data_ptr++ = cpu_to_le32(r_value); 3891 r_addr += r_stride; 3892 } 3893 *d_ptr = data_ptr; 3894 } 3895 3896 static int 3897 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3898 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3899 { 3900 struct qla_hw_data *ha = vha->hw; 3901 uint32_t addr, r_addr, c_addr, t_r_addr; 3902 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3903 unsigned long p_wait, w_time, p_mask; 3904 uint32_t c_value_w, c_value_r; 3905 struct qla82xx_md_entry_cache *cache_hdr; 3906 int rval = QLA_FUNCTION_FAILED; 3907 uint32_t *data_ptr = *d_ptr; 3908 3909 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3910 loop_count = cache_hdr->op_count; 3911 r_addr = cache_hdr->read_addr; 3912 c_addr = cache_hdr->control_addr; 3913 c_value_w = cache_hdr->cache_ctrl.write_value; 3914 3915 t_r_addr = cache_hdr->tag_reg_addr; 3916 t_value = cache_hdr->addr_ctrl.init_tag_value; 3917 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3918 p_wait = cache_hdr->cache_ctrl.poll_wait; 3919 p_mask = cache_hdr->cache_ctrl.poll_mask; 3920 3921 for (i = 0; i < loop_count; i++) { 3922 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3923 if (c_value_w) 3924 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3925 3926 if (p_mask) { 3927 w_time = jiffies + p_wait; 3928 do { 3929 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3930 if ((c_value_r & p_mask) == 0) 3931 break; 3932 else if (time_after_eq(jiffies, w_time)) { 3933 /* capturing dump failed */ 3934 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3935 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3936 "w_time: 0x%lx\n", 3937 c_value_r, p_mask, w_time); 3938 return rval; 3939 } 3940 } while (1); 3941 } 3942 3943 addr = r_addr; 3944 for (k = 0; k < r_cnt; k++) { 3945 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3946 *data_ptr++ = cpu_to_le32(r_value); 3947 addr += cache_hdr->read_ctrl.read_addr_stride; 3948 } 3949 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3950 } 3951 *d_ptr = data_ptr; 3952 return QLA_SUCCESS; 3953 } 3954 3955 static void 3956 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3957 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3958 { 3959 struct qla_hw_data *ha = vha->hw; 3960 uint32_t addr, r_addr, c_addr, t_r_addr; 3961 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3962 uint32_t c_value_w; 3963 struct qla82xx_md_entry_cache *cache_hdr; 3964 uint32_t *data_ptr = *d_ptr; 3965 3966 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3967 loop_count = cache_hdr->op_count; 3968 r_addr = cache_hdr->read_addr; 3969 c_addr = cache_hdr->control_addr; 3970 c_value_w = cache_hdr->cache_ctrl.write_value; 3971 3972 t_r_addr = cache_hdr->tag_reg_addr; 3973 t_value = cache_hdr->addr_ctrl.init_tag_value; 3974 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3975 3976 for (i = 0; i < loop_count; i++) { 3977 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3978 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3979 addr = r_addr; 3980 for (k = 0; k < r_cnt; k++) { 3981 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3982 *data_ptr++ = cpu_to_le32(r_value); 3983 addr += cache_hdr->read_ctrl.read_addr_stride; 3984 } 3985 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3986 } 3987 *d_ptr = data_ptr; 3988 } 3989 3990 static void 3991 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3992 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3993 { 3994 struct qla_hw_data *ha = vha->hw; 3995 uint32_t s_addr, r_addr; 3996 uint32_t r_stride, r_value, r_cnt, qid = 0; 3997 uint32_t i, k, loop_cnt; 3998 struct qla82xx_md_entry_queue *q_hdr; 3999 uint32_t *data_ptr = *d_ptr; 4000 4001 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 4002 s_addr = q_hdr->select_addr; 4003 r_cnt = q_hdr->rd_strd.read_addr_cnt; 4004 r_stride = q_hdr->rd_strd.read_addr_stride; 4005 loop_cnt = q_hdr->op_count; 4006 4007 for (i = 0; i < loop_cnt; i++) { 4008 qla82xx_md_rw_32(ha, s_addr, qid, 1); 4009 r_addr = q_hdr->read_addr; 4010 for (k = 0; k < r_cnt; k++) { 4011 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4012 *data_ptr++ = cpu_to_le32(r_value); 4013 r_addr += r_stride; 4014 } 4015 qid += q_hdr->q_strd.queue_id_stride; 4016 } 4017 *d_ptr = data_ptr; 4018 } 4019 4020 static void 4021 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 4022 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4023 { 4024 struct qla_hw_data *ha = vha->hw; 4025 uint32_t r_addr, r_value; 4026 uint32_t i, loop_cnt; 4027 struct qla82xx_md_entry_rdrom *rom_hdr; 4028 uint32_t *data_ptr = *d_ptr; 4029 4030 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4031 r_addr = rom_hdr->read_addr; 4032 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4033 4034 for (i = 0; i < loop_cnt; i++) { 4035 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4036 (r_addr & 0xFFFF0000), 1); 4037 r_value = qla82xx_md_rw_32(ha, 4038 MD_DIRECT_ROM_READ_BASE + 4039 (r_addr & 0x0000FFFF), 0, 0); 4040 *data_ptr++ = cpu_to_le32(r_value); 4041 r_addr += sizeof(uint32_t); 4042 } 4043 *d_ptr = data_ptr; 4044 } 4045 4046 static int 4047 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4048 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4049 { 4050 struct qla_hw_data *ha = vha->hw; 4051 uint32_t r_addr, r_value, r_data; 4052 uint32_t i, j, loop_cnt; 4053 struct qla82xx_md_entry_rdmem *m_hdr; 4054 unsigned long flags; 4055 int rval = QLA_FUNCTION_FAILED; 4056 uint32_t *data_ptr = *d_ptr; 4057 4058 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4059 r_addr = m_hdr->read_addr; 4060 loop_cnt = m_hdr->read_data_size/16; 4061 4062 if (r_addr & 0xf) { 4063 ql_log(ql_log_warn, vha, 0xb033, 4064 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4065 return rval; 4066 } 4067 4068 if (m_hdr->read_data_size % 16) { 4069 ql_log(ql_log_warn, vha, 0xb034, 4070 "Read data[0x%x] not multiple of 16 bytes\n", 4071 m_hdr->read_data_size); 4072 return rval; 4073 } 4074 4075 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4076 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4077 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4078 4079 write_lock_irqsave(&ha->hw_lock, flags); 4080 for (i = 0; i < loop_cnt; i++) { 4081 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4082 r_value = 0; 4083 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4084 r_value = MIU_TA_CTL_ENABLE; 4085 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4086 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4087 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4088 4089 for (j = 0; j < MAX_CTL_CHECK; j++) { 4090 r_value = qla82xx_md_rw_32(ha, 4091 MD_MIU_TEST_AGT_CTRL, 0, 0); 4092 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4093 break; 4094 } 4095 4096 if (j >= MAX_CTL_CHECK) { 4097 printk_ratelimited(KERN_ERR 4098 "failed to read through agent\n"); 4099 write_unlock_irqrestore(&ha->hw_lock, flags); 4100 return rval; 4101 } 4102 4103 for (j = 0; j < 4; j++) { 4104 r_data = qla82xx_md_rw_32(ha, 4105 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4106 *data_ptr++ = cpu_to_le32(r_data); 4107 } 4108 r_addr += 16; 4109 } 4110 write_unlock_irqrestore(&ha->hw_lock, flags); 4111 *d_ptr = data_ptr; 4112 return QLA_SUCCESS; 4113 } 4114 4115 int 4116 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4117 { 4118 struct qla_hw_data *ha = vha->hw; 4119 uint64_t chksum = 0; 4120 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4121 int count = ha->md_template_size/sizeof(uint32_t); 4122 4123 while (count-- > 0) 4124 chksum += *d_ptr++; 4125 while (chksum >> 32) 4126 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4127 return ~chksum; 4128 } 4129 4130 static void 4131 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4132 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4133 { 4134 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4135 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4136 "Skipping entry[%d]: " 4137 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4138 index, entry_hdr->entry_type, 4139 entry_hdr->d_ctrl.entry_capture_mask); 4140 } 4141 4142 int 4143 qla82xx_md_collect(scsi_qla_host_t *vha) 4144 { 4145 struct qla_hw_data *ha = vha->hw; 4146 int no_entry_hdr = 0; 4147 qla82xx_md_entry_hdr_t *entry_hdr; 4148 struct qla82xx_md_template_hdr *tmplt_hdr; 4149 uint32_t *data_ptr; 4150 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4151 int i = 0, rval = QLA_FUNCTION_FAILED; 4152 4153 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4154 data_ptr = (uint32_t *)ha->md_dump; 4155 4156 if (ha->fw_dumped) { 4157 ql_log(ql_log_warn, vha, 0xb037, 4158 "Firmware has been previously dumped (%p) " 4159 "-- ignoring request.\n", ha->fw_dump); 4160 goto md_failed; 4161 } 4162 4163 ha->fw_dumped = 0; 4164 4165 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4166 ql_log(ql_log_warn, vha, 0xb038, 4167 "Memory not allocated for minidump capture\n"); 4168 goto md_failed; 4169 } 4170 4171 if (ha->flags.isp82xx_no_md_cap) { 4172 ql_log(ql_log_warn, vha, 0xb054, 4173 "Forced reset from application, " 4174 "ignore minidump capture\n"); 4175 ha->flags.isp82xx_no_md_cap = 0; 4176 goto md_failed; 4177 } 4178 4179 if (qla82xx_validate_template_chksum(vha)) { 4180 ql_log(ql_log_info, vha, 0xb039, 4181 "Template checksum validation error\n"); 4182 goto md_failed; 4183 } 4184 4185 no_entry_hdr = tmplt_hdr->num_of_entries; 4186 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4187 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4188 4189 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4190 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4191 4192 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4193 4194 /* Validate whether required debug level is set */ 4195 if ((f_capture_mask & 0x3) != 0x3) { 4196 ql_log(ql_log_warn, vha, 0xb03c, 4197 "Minimum required capture mask[0x%x] level not set\n", 4198 f_capture_mask); 4199 goto md_failed; 4200 } 4201 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4202 4203 tmplt_hdr->driver_info[0] = vha->host_no; 4204 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4205 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4206 QLA_DRIVER_BETA_VER; 4207 4208 total_data_size = ha->md_dump_size; 4209 4210 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4211 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4212 4213 /* Check whether template obtained is valid */ 4214 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4215 ql_log(ql_log_warn, vha, 0xb04e, 4216 "Bad template header entry type: 0x%x obtained\n", 4217 tmplt_hdr->entry_type); 4218 goto md_failed; 4219 } 4220 4221 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4222 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4223 4224 /* Walk through the entry headers */ 4225 for (i = 0; i < no_entry_hdr; i++) { 4226 4227 if (data_collected > total_data_size) { 4228 ql_log(ql_log_warn, vha, 0xb03e, 4229 "More MiniDump data collected: [0x%x]\n", 4230 data_collected); 4231 goto md_failed; 4232 } 4233 4234 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4235 ql2xmdcapmask)) { 4236 entry_hdr->d_ctrl.driver_flags |= 4237 QLA82XX_DBG_SKIPPED_FLAG; 4238 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4239 "Skipping entry[%d]: " 4240 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4241 i, entry_hdr->entry_type, 4242 entry_hdr->d_ctrl.entry_capture_mask); 4243 goto skip_nxt_entry; 4244 } 4245 4246 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4247 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4248 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4249 __func__, i, data_ptr, entry_hdr, 4250 entry_hdr->entry_type, 4251 entry_hdr->d_ctrl.entry_capture_mask); 4252 4253 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4254 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4255 data_collected, (ha->md_dump_size - data_collected)); 4256 4257 /* Decode the entry type and take 4258 * required action to capture debug data */ 4259 switch (entry_hdr->entry_type) { 4260 case QLA82XX_RDEND: 4261 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4262 break; 4263 case QLA82XX_CNTRL: 4264 rval = qla82xx_minidump_process_control(vha, 4265 entry_hdr, &data_ptr); 4266 if (rval != QLA_SUCCESS) { 4267 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4268 goto md_failed; 4269 } 4270 break; 4271 case QLA82XX_RDCRB: 4272 qla82xx_minidump_process_rdcrb(vha, 4273 entry_hdr, &data_ptr); 4274 break; 4275 case QLA82XX_RDMEM: 4276 rval = qla82xx_minidump_process_rdmem(vha, 4277 entry_hdr, &data_ptr); 4278 if (rval != QLA_SUCCESS) { 4279 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4280 goto md_failed; 4281 } 4282 break; 4283 case QLA82XX_BOARD: 4284 case QLA82XX_RDROM: 4285 qla82xx_minidump_process_rdrom(vha, 4286 entry_hdr, &data_ptr); 4287 break; 4288 case QLA82XX_L2DTG: 4289 case QLA82XX_L2ITG: 4290 case QLA82XX_L2DAT: 4291 case QLA82XX_L2INS: 4292 rval = qla82xx_minidump_process_l2tag(vha, 4293 entry_hdr, &data_ptr); 4294 if (rval != QLA_SUCCESS) { 4295 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4296 goto md_failed; 4297 } 4298 break; 4299 case QLA82XX_L1DAT: 4300 case QLA82XX_L1INS: 4301 qla82xx_minidump_process_l1cache(vha, 4302 entry_hdr, &data_ptr); 4303 break; 4304 case QLA82XX_RDOCM: 4305 qla82xx_minidump_process_rdocm(vha, 4306 entry_hdr, &data_ptr); 4307 break; 4308 case QLA82XX_RDMUX: 4309 qla82xx_minidump_process_rdmux(vha, 4310 entry_hdr, &data_ptr); 4311 break; 4312 case QLA82XX_QUEUE: 4313 qla82xx_minidump_process_queue(vha, 4314 entry_hdr, &data_ptr); 4315 break; 4316 case QLA82XX_RDNOP: 4317 default: 4318 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4319 break; 4320 } 4321 4322 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4323 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4324 4325 data_collected = (uint8_t *)data_ptr - 4326 (uint8_t *)ha->md_dump; 4327 skip_nxt_entry: 4328 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4329 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4330 } 4331 4332 if (data_collected != total_data_size) { 4333 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4334 "MiniDump data mismatch: Data collected: [0x%x]," 4335 "total_data_size:[0x%x]\n", 4336 data_collected, total_data_size); 4337 goto md_failed; 4338 } 4339 4340 ql_log(ql_log_info, vha, 0xb044, 4341 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4342 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4343 ha->fw_dumped = 1; 4344 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4345 4346 md_failed: 4347 return rval; 4348 } 4349 4350 int 4351 qla82xx_md_alloc(scsi_qla_host_t *vha) 4352 { 4353 struct qla_hw_data *ha = vha->hw; 4354 int i, k; 4355 struct qla82xx_md_template_hdr *tmplt_hdr; 4356 4357 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4358 4359 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4360 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4361 ql_log(ql_log_info, vha, 0xb045, 4362 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4363 ql2xmdcapmask); 4364 } 4365 4366 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4367 if (i & ql2xmdcapmask) 4368 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4369 } 4370 4371 if (ha->md_dump) { 4372 ql_log(ql_log_warn, vha, 0xb046, 4373 "Firmware dump previously allocated.\n"); 4374 return 1; 4375 } 4376 4377 ha->md_dump = vmalloc(ha->md_dump_size); 4378 if (ha->md_dump == NULL) { 4379 ql_log(ql_log_warn, vha, 0xb047, 4380 "Unable to allocate memory for Minidump size " 4381 "(0x%x).\n", ha->md_dump_size); 4382 return 1; 4383 } 4384 return 0; 4385 } 4386 4387 void 4388 qla82xx_md_free(scsi_qla_host_t *vha) 4389 { 4390 struct qla_hw_data *ha = vha->hw; 4391 4392 /* Release the template header allocated */ 4393 if (ha->md_tmplt_hdr) { 4394 ql_log(ql_log_info, vha, 0xb048, 4395 "Free MiniDump template: %p, size (%d KB)\n", 4396 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4397 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4398 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4399 ha->md_tmplt_hdr = NULL; 4400 } 4401 4402 /* Release the template data buffer allocated */ 4403 if (ha->md_dump) { 4404 ql_log(ql_log_info, vha, 0xb049, 4405 "Free MiniDump memory: %p, size (%d KB)\n", 4406 ha->md_dump, ha->md_dump_size / 1024); 4407 vfree(ha->md_dump); 4408 ha->md_dump_size = 0; 4409 ha->md_dump = NULL; 4410 } 4411 } 4412 4413 void 4414 qla82xx_md_prep(scsi_qla_host_t *vha) 4415 { 4416 struct qla_hw_data *ha = vha->hw; 4417 int rval; 4418 4419 /* Get Minidump template size */ 4420 rval = qla82xx_md_get_template_size(vha); 4421 if (rval == QLA_SUCCESS) { 4422 ql_log(ql_log_info, vha, 0xb04a, 4423 "MiniDump Template size obtained (%d KB)\n", 4424 ha->md_template_size / 1024); 4425 4426 /* Get Minidump template */ 4427 if (IS_QLA8044(ha)) 4428 rval = qla8044_md_get_template(vha); 4429 else 4430 rval = qla82xx_md_get_template(vha); 4431 4432 if (rval == QLA_SUCCESS) { 4433 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4434 "MiniDump Template obtained\n"); 4435 4436 /* Allocate memory for minidump */ 4437 rval = qla82xx_md_alloc(vha); 4438 if (rval == QLA_SUCCESS) 4439 ql_log(ql_log_info, vha, 0xb04c, 4440 "MiniDump memory allocated (%d KB)\n", 4441 ha->md_dump_size / 1024); 4442 else { 4443 ql_log(ql_log_info, vha, 0xb04d, 4444 "Free MiniDump template: %p, size: (%d KB)\n", 4445 ha->md_tmplt_hdr, 4446 ha->md_template_size / 1024); 4447 dma_free_coherent(&ha->pdev->dev, 4448 ha->md_template_size, 4449 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4450 ha->md_tmplt_hdr = NULL; 4451 } 4452 4453 } 4454 } 4455 } 4456 4457 int 4458 qla82xx_beacon_on(struct scsi_qla_host *vha) 4459 { 4460 4461 int rval; 4462 struct qla_hw_data *ha = vha->hw; 4463 qla82xx_idc_lock(ha); 4464 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4465 4466 if (rval) { 4467 ql_log(ql_log_warn, vha, 0xb050, 4468 "mbx set led config failed in %s\n", __func__); 4469 goto exit; 4470 } 4471 ha->beacon_blink_led = 1; 4472 exit: 4473 qla82xx_idc_unlock(ha); 4474 return rval; 4475 } 4476 4477 int 4478 qla82xx_beacon_off(struct scsi_qla_host *vha) 4479 { 4480 4481 int rval; 4482 struct qla_hw_data *ha = vha->hw; 4483 qla82xx_idc_lock(ha); 4484 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4485 4486 if (rval) { 4487 ql_log(ql_log_warn, vha, 0xb051, 4488 "mbx set led config failed in %s\n", __func__); 4489 goto exit; 4490 } 4491 ha->beacon_blink_led = 0; 4492 exit: 4493 qla82xx_idc_unlock(ha); 4494 return rval; 4495 } 4496 4497 void 4498 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4499 { 4500 struct qla_hw_data *ha = vha->hw; 4501 4502 if (!ha->allow_cna_fw_dump) 4503 return; 4504 4505 scsi_block_requests(vha->host); 4506 ha->flags.isp82xx_no_md_cap = 1; 4507 qla82xx_idc_lock(ha); 4508 qla82xx_set_reset_owner(vha); 4509 qla82xx_idc_unlock(ha); 4510 qla2x00_wait_for_chip_reset(vha); 4511 scsi_unblock_requests(vha->host); 4512 } 4513