1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 static void qla82xx_crb_addr_transform_setup(void) 46 { 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103 } 104 105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260 }; 261 262 /* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265 static unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330 }; 331 332 /* Device states */ 333 static char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342 }; 343 344 char *qdev_state(uint32_t dev_state) 345 { 346 return q_dev_state[dev_state]; 347 } 348 349 /* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356 { 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void __iomem *) 368 (CRB_WINDOW_2M + ha->nx_pcibase)); 369 if (win_read != ha->crb_win) { 370 ql_dbg(ql_dbg_p3p, vha, 0xb000, 371 "%s: Written crbwin (0x%x) " 372 "!= Read crbwin (0x%x), off=0x%lx.\n", 373 __func__, ha->crb_win, win_read, *off); 374 } 375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376 } 377 378 static inline unsigned long 379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380 { 381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382 /* See if we are currently pointing to the region we want to use next */ 383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384 /* No need to change window. PCIX and PCIEregs are in both 385 * regs are in both windows. 386 */ 387 return off; 388 } 389 390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391 /* We are in first CRB window */ 392 if (ha->curr_window != 0) 393 WARN_ON(1); 394 return off; 395 } 396 397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398 /* We are in second CRB window */ 399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400 401 if (ha->curr_window != 1) 402 return off; 403 404 /* We are in the QM or direct access 405 * register region - do nothing 406 */ 407 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408 (off < QLA82XX_PCI_CAMQM_MAX)) 409 return off; 410 } 411 /* strange address given */ 412 ql_dbg(ql_dbg_p3p, vha, 0xb001, 413 "%s: Warning: unm_nic_pci_set_crbwindow " 414 "called with an unknown address(%llx).\n", 415 QLA2XXX_DRIVER_NAME, off); 416 return off; 417 } 418 419 static int 420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 421 { 422 struct crb_128M_2M_sub_block_map *m; 423 424 if (*off >= QLA82XX_CRB_MAX) 425 return -1; 426 427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 428 *off = (*off - QLA82XX_PCI_CAMQM) + 429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 430 return 0; 431 } 432 433 if (*off < QLA82XX_PCI_CRBSPACE) 434 return -1; 435 436 *off -= QLA82XX_PCI_CRBSPACE; 437 438 /* Try direct map */ 439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 440 441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 443 return 0; 444 } 445 /* Not in direct map, use crb window */ 446 return 1; 447 } 448 449 #define CRB_WIN_LOCK_TIMEOUT 100000000 450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 451 { 452 int done = 0, timeout = 0; 453 454 while (!done) { 455 /* acquire semaphore3 from PCI HW block */ 456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 457 if (done == 1) 458 break; 459 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 460 return -1; 461 timeout++; 462 } 463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 464 return 0; 465 } 466 467 int 468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469 { 470 unsigned long flags = 0; 471 int rv; 472 473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474 475 BUG_ON(rv == -1); 476 477 if (rv == 1) { 478 write_lock_irqsave(&ha->hw_lock, flags); 479 qla82xx_crb_win_lock(ha); 480 qla82xx_pci_set_crbwindow_2M(ha, &off); 481 } 482 483 writel(data, (void __iomem *)off); 484 485 if (rv == 1) { 486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487 write_unlock_irqrestore(&ha->hw_lock, flags); 488 } 489 return 0; 490 } 491 492 int 493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494 { 495 unsigned long flags = 0; 496 int rv; 497 u32 data; 498 499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500 501 BUG_ON(rv == -1); 502 503 if (rv == 1) { 504 write_lock_irqsave(&ha->hw_lock, flags); 505 qla82xx_crb_win_lock(ha); 506 qla82xx_pci_set_crbwindow_2M(ha, &off); 507 } 508 data = RD_REG_DWORD((void __iomem *)off); 509 510 if (rv == 1) { 511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512 write_unlock_irqrestore(&ha->hw_lock, flags); 513 } 514 return data; 515 } 516 517 #define IDC_LOCK_TIMEOUT 100000000 518 int qla82xx_idc_lock(struct qla_hw_data *ha) 519 { 520 int i; 521 int done = 0, timeout = 0; 522 523 while (!done) { 524 /* acquire semaphore5 from PCI HW block */ 525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526 if (done == 1) 527 break; 528 if (timeout >= IDC_LOCK_TIMEOUT) 529 return -1; 530 531 timeout++; 532 533 /* Yield CPU */ 534 if (!in_interrupt()) 535 schedule(); 536 else { 537 for (i = 0; i < 20; i++) 538 cpu_relax(); 539 } 540 } 541 542 return 0; 543 } 544 545 void qla82xx_idc_unlock(struct qla_hw_data *ha) 546 { 547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548 } 549 550 /* PCI Windowing for DDR regions. */ 551 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 552 (((addr) <= (high)) && ((addr) >= (low))) 553 /* 554 * check memory access boundary. 555 * used by test agent. support ddr access only for now 556 */ 557 static unsigned long 558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 559 unsigned long long addr, int size) 560 { 561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 562 QLA82XX_ADDR_DDR_NET_MAX) || 563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 564 QLA82XX_ADDR_DDR_NET_MAX) || 565 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 566 return 0; 567 else 568 return 1; 569 } 570 571 static int qla82xx_pci_set_window_warning_count; 572 573 static unsigned long 574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 575 { 576 int window; 577 u32 win_read; 578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 579 580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 581 QLA82XX_ADDR_DDR_NET_MAX)) { 582 /* DDR network side */ 583 window = MN_WIN(addr); 584 ha->ddr_mn_window = window; 585 qla82xx_wr_32(ha, 586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 587 win_read = qla82xx_rd_32(ha, 588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 589 if ((win_read << 17) != window) { 590 ql_dbg(ql_dbg_p3p, vha, 0xb003, 591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 592 __func__, window, win_read); 593 } 594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 596 QLA82XX_ADDR_OCM0_MAX)) { 597 unsigned int temp1; 598 if ((addr & 0x00ff800) == 0xff800) { 599 ql_log(ql_log_warn, vha, 0xb004, 600 "%s: QM access not handled.\n", __func__); 601 addr = -1UL; 602 } 603 window = OCM_WIN(addr); 604 ha->ddr_mn_window = window; 605 qla82xx_wr_32(ha, 606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 607 win_read = qla82xx_rd_32(ha, 608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 609 temp1 = ((window & 0x1FF) << 7) | 610 ((window & 0x0FFFE0000) >> 17); 611 if (win_read != temp1) { 612 ql_log(ql_log_warn, vha, 0xb005, 613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 614 __func__, temp1, win_read); 615 } 616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 617 618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 619 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 620 /* QDR network side */ 621 window = MS_WIN(addr); 622 ha->qdr_sn_window = window; 623 qla82xx_wr_32(ha, 624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 625 win_read = qla82xx_rd_32(ha, 626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 627 if (win_read != window) { 628 ql_log(ql_log_warn, vha, 0xb006, 629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 630 __func__, window, win_read); 631 } 632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 633 } else { 634 /* 635 * peg gdb frequently accesses memory that doesn't exist, 636 * this limits the chit chat so debugging isn't slowed down. 637 */ 638 if ((qla82xx_pci_set_window_warning_count++ < 8) || 639 (qla82xx_pci_set_window_warning_count%64 == 0)) { 640 ql_log(ql_log_warn, vha, 0xb007, 641 "%s: Warning:%s Unknown address range!.\n", 642 __func__, QLA2XXX_DRIVER_NAME); 643 } 644 addr = -1UL; 645 } 646 return addr; 647 } 648 649 /* check if address is in the same windows as the previous access */ 650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 651 unsigned long long addr) 652 { 653 int window; 654 unsigned long long qdr_max; 655 656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 657 658 /* DDR network side */ 659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 660 QLA82XX_ADDR_DDR_NET_MAX)) 661 BUG(); 662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 663 QLA82XX_ADDR_OCM0_MAX)) 664 return 1; 665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 666 QLA82XX_ADDR_OCM1_MAX)) 667 return 1; 668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 669 /* QDR network side */ 670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 671 if (ha->qdr_sn_window == window) 672 return 1; 673 } 674 return 0; 675 } 676 677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 678 u64 off, void *data, int size) 679 { 680 unsigned long flags; 681 void __iomem *addr = NULL; 682 int ret = 0; 683 u64 start; 684 uint8_t __iomem *mem_ptr = NULL; 685 unsigned long mem_base; 686 unsigned long mem_page; 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 688 689 write_lock_irqsave(&ha->hw_lock, flags); 690 691 /* 692 * If attempting to access unknown address or straddle hw windows, 693 * do not access. 694 */ 695 start = qla82xx_pci_set_window(ha, off); 696 if ((start == -1UL) || 697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 698 write_unlock_irqrestore(&ha->hw_lock, flags); 699 ql_log(ql_log_fatal, vha, 0xb008, 700 "%s out of bound pci memory " 701 "access, offset is 0x%llx.\n", 702 QLA2XXX_DRIVER_NAME, off); 703 return -1; 704 } 705 706 write_unlock_irqrestore(&ha->hw_lock, flags); 707 mem_base = pci_resource_start(ha->pdev, 0); 708 mem_page = start & PAGE_MASK; 709 /* Map two pages whenever user tries to access addresses in two 710 * consecutive pages. 711 */ 712 if (mem_page != ((start + size - 1) & PAGE_MASK)) 713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 714 else 715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 716 if (mem_ptr == NULL) { 717 *(u8 *)data = 0; 718 return -1; 719 } 720 addr = mem_ptr; 721 addr += start & (PAGE_SIZE - 1); 722 write_lock_irqsave(&ha->hw_lock, flags); 723 724 switch (size) { 725 case 1: 726 *(u8 *)data = readb(addr); 727 break; 728 case 2: 729 *(u16 *)data = readw(addr); 730 break; 731 case 4: 732 *(u32 *)data = readl(addr); 733 break; 734 case 8: 735 *(u64 *)data = readq(addr); 736 break; 737 default: 738 ret = -1; 739 break; 740 } 741 write_unlock_irqrestore(&ha->hw_lock, flags); 742 743 if (mem_ptr) 744 iounmap(mem_ptr); 745 return ret; 746 } 747 748 static int 749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 750 u64 off, void *data, int size) 751 { 752 unsigned long flags; 753 void __iomem *addr = NULL; 754 int ret = 0; 755 u64 start; 756 uint8_t __iomem *mem_ptr = NULL; 757 unsigned long mem_base; 758 unsigned long mem_page; 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 760 761 write_lock_irqsave(&ha->hw_lock, flags); 762 763 /* 764 * If attempting to access unknown address or straddle hw windows, 765 * do not access. 766 */ 767 start = qla82xx_pci_set_window(ha, off); 768 if ((start == -1UL) || 769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 770 write_unlock_irqrestore(&ha->hw_lock, flags); 771 ql_log(ql_log_fatal, vha, 0xb009, 772 "%s out of bount memory " 773 "access, offset is 0x%llx.\n", 774 QLA2XXX_DRIVER_NAME, off); 775 return -1; 776 } 777 778 write_unlock_irqrestore(&ha->hw_lock, flags); 779 mem_base = pci_resource_start(ha->pdev, 0); 780 mem_page = start & PAGE_MASK; 781 /* Map two pages whenever user tries to access addresses in two 782 * consecutive pages. 783 */ 784 if (mem_page != ((start + size - 1) & PAGE_MASK)) 785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 786 else 787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 788 if (mem_ptr == NULL) 789 return -1; 790 791 addr = mem_ptr; 792 addr += start & (PAGE_SIZE - 1); 793 write_lock_irqsave(&ha->hw_lock, flags); 794 795 switch (size) { 796 case 1: 797 writeb(*(u8 *)data, addr); 798 break; 799 case 2: 800 writew(*(u16 *)data, addr); 801 break; 802 case 4: 803 writel(*(u32 *)data, addr); 804 break; 805 case 8: 806 writeq(*(u64 *)data, addr); 807 break; 808 default: 809 ret = -1; 810 break; 811 } 812 write_unlock_irqrestore(&ha->hw_lock, flags); 813 if (mem_ptr) 814 iounmap(mem_ptr); 815 return ret; 816 } 817 818 #define MTU_FUDGE_FACTOR 100 819 static unsigned long 820 qla82xx_decode_crb_addr(unsigned long addr) 821 { 822 int i; 823 unsigned long base_addr, offset, pci_base; 824 825 if (!qla82xx_crb_table_initialized) 826 qla82xx_crb_addr_transform_setup(); 827 828 pci_base = ADDR_ERROR; 829 base_addr = addr & 0xfff00000; 830 offset = addr & 0x000fffff; 831 832 for (i = 0; i < MAX_CRB_XFORM; i++) { 833 if (crb_addr_xform[i] == base_addr) { 834 pci_base = i << 20; 835 break; 836 } 837 } 838 if (pci_base == ADDR_ERROR) 839 return pci_base; 840 return pci_base + offset; 841 } 842 843 static long rom_max_timeout = 100; 844 static long qla82xx_rom_lock_timeout = 100; 845 846 static int 847 qla82xx_rom_lock(struct qla_hw_data *ha) 848 { 849 int done = 0, timeout = 0; 850 uint32_t lock_owner = 0; 851 852 while (!done) { 853 /* acquire semaphore2 from PCI HW block */ 854 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 855 if (done == 1) 856 break; 857 if (timeout >= qla82xx_rom_lock_timeout) { 858 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 859 return -1; 860 } 861 timeout++; 862 } 863 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 864 return 0; 865 } 866 867 static void 868 qla82xx_rom_unlock(struct qla_hw_data *ha) 869 { 870 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 871 } 872 873 static int 874 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 875 { 876 long timeout = 0; 877 long done = 0 ; 878 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 879 880 while (done == 0) { 881 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 882 done &= 4; 883 timeout++; 884 if (timeout >= rom_max_timeout) { 885 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 886 "%s: Timeout reached waiting for rom busy.\n", 887 QLA2XXX_DRIVER_NAME); 888 return -1; 889 } 890 } 891 return 0; 892 } 893 894 static int 895 qla82xx_wait_rom_done(struct qla_hw_data *ha) 896 { 897 long timeout = 0; 898 long done = 0 ; 899 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 900 901 while (done == 0) { 902 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 903 done &= 2; 904 timeout++; 905 if (timeout >= rom_max_timeout) { 906 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 907 "%s: Timeout reached waiting for rom done.\n", 908 QLA2XXX_DRIVER_NAME); 909 return -1; 910 } 911 } 912 return 0; 913 } 914 915 static int 916 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 917 { 918 uint32_t off_value, rval = 0; 919 920 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 921 (off & 0xFFFF0000)); 922 923 /* Read back value to make sure write has gone through */ 924 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 925 off_value = (off & 0x0000FFFF); 926 927 if (flag) 928 WRT_REG_DWORD((void __iomem *) 929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 930 data); 931 else 932 rval = RD_REG_DWORD((void __iomem *) 933 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 934 935 return rval; 936 } 937 938 static int 939 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 940 { 941 /* Dword reads to flash. */ 942 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 943 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 944 (addr & 0x0000FFFF), 0, 0); 945 946 return 0; 947 } 948 949 static int 950 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 951 { 952 int ret, loops = 0; 953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 954 955 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 956 udelay(100); 957 schedule(); 958 loops++; 959 } 960 if (loops >= 50000) { 961 ql_log(ql_log_fatal, vha, 0x00b9, 962 "Failed to acquire SEM2 lock.\n"); 963 return -1; 964 } 965 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 966 qla82xx_rom_unlock(ha); 967 return ret; 968 } 969 970 static int 971 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 972 { 973 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 974 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 975 qla82xx_wait_rom_busy(ha); 976 if (qla82xx_wait_rom_done(ha)) { 977 ql_log(ql_log_warn, vha, 0xb00c, 978 "Error waiting for rom done.\n"); 979 return -1; 980 } 981 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 982 return 0; 983 } 984 985 static int 986 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 987 { 988 long timeout = 0; 989 uint32_t done = 1 ; 990 uint32_t val; 991 int ret = 0; 992 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 993 994 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 995 while ((done != 0) && (ret == 0)) { 996 ret = qla82xx_read_status_reg(ha, &val); 997 done = val & 1; 998 timeout++; 999 udelay(10); 1000 cond_resched(); 1001 if (timeout >= 50000) { 1002 ql_log(ql_log_warn, vha, 0xb00d, 1003 "Timeout reached waiting for write finish.\n"); 1004 return -1; 1005 } 1006 } 1007 return ret; 1008 } 1009 1010 static int 1011 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1012 { 1013 uint32_t val; 1014 qla82xx_wait_rom_busy(ha); 1015 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1016 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1017 qla82xx_wait_rom_busy(ha); 1018 if (qla82xx_wait_rom_done(ha)) 1019 return -1; 1020 if (qla82xx_read_status_reg(ha, &val) != 0) 1021 return -1; 1022 if ((val & 2) != 2) 1023 return -1; 1024 return 0; 1025 } 1026 1027 static int 1028 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1029 { 1030 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1031 if (qla82xx_flash_set_write_enable(ha)) 1032 return -1; 1033 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1034 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1035 if (qla82xx_wait_rom_done(ha)) { 1036 ql_log(ql_log_warn, vha, 0xb00e, 1037 "Error waiting for rom done.\n"); 1038 return -1; 1039 } 1040 return qla82xx_flash_wait_write_finish(ha); 1041 } 1042 1043 static int 1044 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1045 { 1046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1047 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1048 if (qla82xx_wait_rom_done(ha)) { 1049 ql_log(ql_log_warn, vha, 0xb00f, 1050 "Error waiting for rom done.\n"); 1051 return -1; 1052 } 1053 return 0; 1054 } 1055 1056 static int 1057 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1058 { 1059 int loops = 0; 1060 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1061 1062 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1063 udelay(100); 1064 cond_resched(); 1065 loops++; 1066 } 1067 if (loops >= 50000) { 1068 ql_log(ql_log_warn, vha, 0xb010, 1069 "ROM lock failed.\n"); 1070 return -1; 1071 } 1072 return 0; 1073 } 1074 1075 static int 1076 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1077 uint32_t data) 1078 { 1079 int ret = 0; 1080 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1081 1082 ret = ql82xx_rom_lock_d(ha); 1083 if (ret < 0) { 1084 ql_log(ql_log_warn, vha, 0xb011, 1085 "ROM lock failed.\n"); 1086 return ret; 1087 } 1088 1089 if (qla82xx_flash_set_write_enable(ha)) 1090 goto done_write; 1091 1092 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1093 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1094 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1095 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1096 qla82xx_wait_rom_busy(ha); 1097 if (qla82xx_wait_rom_done(ha)) { 1098 ql_log(ql_log_warn, vha, 0xb012, 1099 "Error waiting for rom done.\n"); 1100 ret = -1; 1101 goto done_write; 1102 } 1103 1104 ret = qla82xx_flash_wait_write_finish(ha); 1105 1106 done_write: 1107 qla82xx_rom_unlock(ha); 1108 return ret; 1109 } 1110 1111 /* This routine does CRB initialize sequence 1112 * to put the ISP into operational state 1113 */ 1114 static int 1115 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1116 { 1117 int addr, val; 1118 int i ; 1119 struct crb_addr_pair *buf; 1120 unsigned long off; 1121 unsigned offset, n; 1122 struct qla_hw_data *ha = vha->hw; 1123 1124 struct crb_addr_pair { 1125 long addr; 1126 long data; 1127 }; 1128 1129 /* Halt all the individual PEGs and other blocks of the ISP */ 1130 qla82xx_rom_lock(ha); 1131 1132 /* disable all I2Q */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1134 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1135 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1136 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1137 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1138 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1139 1140 /* disable all niu interrupts */ 1141 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1142 /* disable xge rx/tx */ 1143 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1144 /* disable xg1 rx/tx */ 1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1146 /* disable sideband mac */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1148 /* disable ap0 mac */ 1149 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1150 /* disable ap1 mac */ 1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1152 1153 /* halt sre */ 1154 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1155 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1156 1157 /* halt epg */ 1158 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1159 1160 /* halt timers */ 1161 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1162 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1163 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1164 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1165 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1166 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1167 1168 /* halt pegs */ 1169 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1170 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1171 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1172 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1173 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1174 msleep(20); 1175 1176 /* big hammer */ 1177 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1178 /* don't reset CAM block on reset */ 1179 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1180 else 1181 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1182 qla82xx_rom_unlock(ha); 1183 1184 /* Read the signature value from the flash. 1185 * Offset 0: Contain signature (0xcafecafe) 1186 * Offset 4: Offset and number of addr/value pairs 1187 * that present in CRB initialize sequence 1188 */ 1189 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1190 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1191 ql_log(ql_log_fatal, vha, 0x006e, 1192 "Error Reading crb_init area: n: %08x.\n", n); 1193 return -1; 1194 } 1195 1196 /* Offset in flash = lower 16 bits 1197 * Number of entries = upper 16 bits 1198 */ 1199 offset = n & 0xffffU; 1200 n = (n >> 16) & 0xffffU; 1201 1202 /* number of addr/value pair should not exceed 1024 entries */ 1203 if (n >= 1024) { 1204 ql_log(ql_log_fatal, vha, 0x0071, 1205 "Card flash not initialized:n=0x%x.\n", n); 1206 return -1; 1207 } 1208 1209 ql_log(ql_log_info, vha, 0x0072, 1210 "%d CRB init values found in ROM.\n", n); 1211 1212 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1213 if (buf == NULL) { 1214 ql_log(ql_log_fatal, vha, 0x010c, 1215 "Unable to allocate memory.\n"); 1216 return -1; 1217 } 1218 1219 for (i = 0; i < n; i++) { 1220 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1221 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1222 kfree(buf); 1223 return -1; 1224 } 1225 1226 buf[i].addr = addr; 1227 buf[i].data = val; 1228 } 1229 1230 for (i = 0; i < n; i++) { 1231 /* Translate internal CRB initialization 1232 * address to PCI bus address 1233 */ 1234 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1235 QLA82XX_PCI_CRBSPACE; 1236 /* Not all CRB addr/value pair to be written, 1237 * some of them are skipped 1238 */ 1239 1240 /* skipping cold reboot MAGIC */ 1241 if (off == QLA82XX_CAM_RAM(0x1fc)) 1242 continue; 1243 1244 /* do not reset PCI */ 1245 if (off == (ROMUSB_GLB + 0xbc)) 1246 continue; 1247 1248 /* skip core clock, so that firmware can increase the clock */ 1249 if (off == (ROMUSB_GLB + 0xc8)) 1250 continue; 1251 1252 /* skip the function enable register */ 1253 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1254 continue; 1255 1256 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1257 continue; 1258 1259 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1260 continue; 1261 1262 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1263 continue; 1264 1265 if (off == ADDR_ERROR) { 1266 ql_log(ql_log_fatal, vha, 0x0116, 1267 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1268 continue; 1269 } 1270 1271 qla82xx_wr_32(ha, off, buf[i].data); 1272 1273 /* ISP requires much bigger delay to settle down, 1274 * else crb_window returns 0xffffffff 1275 */ 1276 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1277 msleep(1000); 1278 1279 /* ISP requires millisec delay between 1280 * successive CRB register updation 1281 */ 1282 msleep(1); 1283 } 1284 1285 kfree(buf); 1286 1287 /* Resetting the data and instruction cache */ 1288 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1290 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1291 1292 /* Clear all protocol processing engines */ 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1301 return 0; 1302 } 1303 1304 static int 1305 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1306 u64 off, void *data, int size) 1307 { 1308 int i, j, ret = 0, loop, sz[2], off0; 1309 int scale, shift_amount, startword; 1310 uint32_t temp; 1311 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1312 1313 /* 1314 * If not MN, go check for MS or invalid. 1315 */ 1316 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1317 mem_crb = QLA82XX_CRB_QDR_NET; 1318 else { 1319 mem_crb = QLA82XX_CRB_DDR_NET; 1320 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1321 return qla82xx_pci_mem_write_direct(ha, 1322 off, data, size); 1323 } 1324 1325 off0 = off & 0x7; 1326 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1327 sz[1] = size - sz[0]; 1328 1329 off8 = off & 0xfffffff0; 1330 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1331 shift_amount = 4; 1332 scale = 2; 1333 startword = (off & 0xf)/8; 1334 1335 for (i = 0; i < loop; i++) { 1336 if (qla82xx_pci_mem_read_2M(ha, off8 + 1337 (i << shift_amount), &word[i * scale], 8)) 1338 return -1; 1339 } 1340 1341 switch (size) { 1342 case 1: 1343 tmpw = *((uint8_t *)data); 1344 break; 1345 case 2: 1346 tmpw = *((uint16_t *)data); 1347 break; 1348 case 4: 1349 tmpw = *((uint32_t *)data); 1350 break; 1351 case 8: 1352 default: 1353 tmpw = *((uint64_t *)data); 1354 break; 1355 } 1356 1357 if (sz[0] == 8) { 1358 word[startword] = tmpw; 1359 } else { 1360 word[startword] &= 1361 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1362 word[startword] |= tmpw << (off0 * 8); 1363 } 1364 if (sz[1] != 0) { 1365 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1366 word[startword+1] |= tmpw >> (sz[0] * 8); 1367 } 1368 1369 for (i = 0; i < loop; i++) { 1370 temp = off8 + (i << shift_amount); 1371 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1372 temp = 0; 1373 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1374 temp = word[i * scale] & 0xffffffff; 1375 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1376 temp = (word[i * scale] >> 32) & 0xffffffff; 1377 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1378 temp = word[i*scale + 1] & 0xffffffff; 1379 qla82xx_wr_32(ha, mem_crb + 1380 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1381 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1382 qla82xx_wr_32(ha, mem_crb + 1383 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1384 1385 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1386 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1387 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1388 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1389 1390 for (j = 0; j < MAX_CTL_CHECK; j++) { 1391 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1392 if ((temp & MIU_TA_CTL_BUSY) == 0) 1393 break; 1394 } 1395 1396 if (j >= MAX_CTL_CHECK) { 1397 if (printk_ratelimit()) 1398 dev_err(&ha->pdev->dev, 1399 "failed to write through agent.\n"); 1400 ret = -1; 1401 break; 1402 } 1403 } 1404 1405 return ret; 1406 } 1407 1408 static int 1409 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1410 { 1411 int i; 1412 long size = 0; 1413 long flashaddr = ha->flt_region_bootload << 2; 1414 long memaddr = BOOTLD_START; 1415 u64 data; 1416 u32 high, low; 1417 size = (IMAGE_START - BOOTLD_START) / 8; 1418 1419 for (i = 0; i < size; i++) { 1420 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1421 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1422 return -1; 1423 } 1424 data = ((u64)high << 32) | low ; 1425 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1426 flashaddr += 8; 1427 memaddr += 8; 1428 1429 if (i % 0x1000 == 0) 1430 msleep(1); 1431 } 1432 udelay(100); 1433 read_lock(&ha->hw_lock); 1434 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1435 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1436 read_unlock(&ha->hw_lock); 1437 return 0; 1438 } 1439 1440 int 1441 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1442 u64 off, void *data, int size) 1443 { 1444 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1445 int shift_amount; 1446 uint32_t temp; 1447 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1448 1449 /* 1450 * If not MN, go check for MS or invalid. 1451 */ 1452 1453 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1454 mem_crb = QLA82XX_CRB_QDR_NET; 1455 else { 1456 mem_crb = QLA82XX_CRB_DDR_NET; 1457 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1458 return qla82xx_pci_mem_read_direct(ha, 1459 off, data, size); 1460 } 1461 1462 off8 = off & 0xfffffff0; 1463 off0[0] = off & 0xf; 1464 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1465 shift_amount = 4; 1466 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1467 off0[1] = 0; 1468 sz[1] = size - sz[0]; 1469 1470 for (i = 0; i < loop; i++) { 1471 temp = off8 + (i << shift_amount); 1472 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1473 temp = 0; 1474 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1475 temp = MIU_TA_CTL_ENABLE; 1476 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1477 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1478 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1479 1480 for (j = 0; j < MAX_CTL_CHECK; j++) { 1481 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1482 if ((temp & MIU_TA_CTL_BUSY) == 0) 1483 break; 1484 } 1485 1486 if (j >= MAX_CTL_CHECK) { 1487 if (printk_ratelimit()) 1488 dev_err(&ha->pdev->dev, 1489 "failed to read through agent.\n"); 1490 break; 1491 } 1492 1493 start = off0[i] >> 2; 1494 end = (off0[i] + sz[i] - 1) >> 2; 1495 for (k = start; k <= end; k++) { 1496 temp = qla82xx_rd_32(ha, 1497 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1498 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1499 } 1500 } 1501 1502 if (j >= MAX_CTL_CHECK) 1503 return -1; 1504 1505 if ((off0[0] & 7) == 0) { 1506 val = word[0]; 1507 } else { 1508 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1509 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1510 } 1511 1512 switch (size) { 1513 case 1: 1514 *(uint8_t *)data = val; 1515 break; 1516 case 2: 1517 *(uint16_t *)data = val; 1518 break; 1519 case 4: 1520 *(uint32_t *)data = val; 1521 break; 1522 case 8: 1523 *(uint64_t *)data = val; 1524 break; 1525 } 1526 return 0; 1527 } 1528 1529 1530 static struct qla82xx_uri_table_desc * 1531 qla82xx_get_table_desc(const u8 *unirom, int section) 1532 { 1533 uint32_t i; 1534 struct qla82xx_uri_table_desc *directory = 1535 (struct qla82xx_uri_table_desc *)&unirom[0]; 1536 __le32 offset; 1537 __le32 tab_type; 1538 __le32 entries = cpu_to_le32(directory->num_entries); 1539 1540 for (i = 0; i < entries; i++) { 1541 offset = cpu_to_le32(directory->findex) + 1542 (i * cpu_to_le32(directory->entry_size)); 1543 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1544 1545 if (tab_type == section) 1546 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1547 } 1548 1549 return NULL; 1550 } 1551 1552 static struct qla82xx_uri_data_desc * 1553 qla82xx_get_data_desc(struct qla_hw_data *ha, 1554 u32 section, u32 idx_offset) 1555 { 1556 const u8 *unirom = ha->hablob->fw->data; 1557 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1558 struct qla82xx_uri_table_desc *tab_desc = NULL; 1559 __le32 offset; 1560 1561 tab_desc = qla82xx_get_table_desc(unirom, section); 1562 if (!tab_desc) 1563 return NULL; 1564 1565 offset = cpu_to_le32(tab_desc->findex) + 1566 (cpu_to_le32(tab_desc->entry_size) * idx); 1567 1568 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1569 } 1570 1571 static u8 * 1572 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1573 { 1574 u32 offset = BOOTLD_START; 1575 struct qla82xx_uri_data_desc *uri_desc = NULL; 1576 1577 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1578 uri_desc = qla82xx_get_data_desc(ha, 1579 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1580 if (uri_desc) 1581 offset = cpu_to_le32(uri_desc->findex); 1582 } 1583 1584 return (u8 *)&ha->hablob->fw->data[offset]; 1585 } 1586 1587 static __le32 1588 qla82xx_get_fw_size(struct qla_hw_data *ha) 1589 { 1590 struct qla82xx_uri_data_desc *uri_desc = NULL; 1591 1592 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1593 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1594 QLA82XX_URI_FIRMWARE_IDX_OFF); 1595 if (uri_desc) 1596 return cpu_to_le32(uri_desc->size); 1597 } 1598 1599 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1600 } 1601 1602 static u8 * 1603 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1604 { 1605 u32 offset = IMAGE_START; 1606 struct qla82xx_uri_data_desc *uri_desc = NULL; 1607 1608 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1609 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1610 QLA82XX_URI_FIRMWARE_IDX_OFF); 1611 if (uri_desc) 1612 offset = cpu_to_le32(uri_desc->findex); 1613 } 1614 1615 return (u8 *)&ha->hablob->fw->data[offset]; 1616 } 1617 1618 /* PCI related functions */ 1619 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1620 { 1621 unsigned long val = 0; 1622 u32 control; 1623 1624 switch (region) { 1625 case 0: 1626 val = 0; 1627 break; 1628 case 1: 1629 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1630 val = control + QLA82XX_MSIX_TBL_SPACE; 1631 break; 1632 } 1633 return val; 1634 } 1635 1636 1637 int 1638 qla82xx_iospace_config(struct qla_hw_data *ha) 1639 { 1640 uint32_t len = 0; 1641 1642 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1643 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1644 "Failed to reserver selected regions.\n"); 1645 goto iospace_error_exit; 1646 } 1647 1648 /* Use MMIO operations for all accesses. */ 1649 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1650 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1651 "Region #0 not an MMIO resource, aborting.\n"); 1652 goto iospace_error_exit; 1653 } 1654 1655 len = pci_resource_len(ha->pdev, 0); 1656 ha->nx_pcibase = 1657 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1658 if (!ha->nx_pcibase) { 1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1660 "Cannot remap pcibase MMIO, aborting.\n"); 1661 goto iospace_error_exit; 1662 } 1663 1664 /* Mapping of IO base pointer */ 1665 if (IS_QLA8044(ha)) { 1666 ha->iobase = 1667 (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase); 1668 } else if (IS_QLA82XX(ha)) { 1669 ha->iobase = 1670 (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1671 0xbc000 + (ha->pdev->devfn << 11)); 1672 } 1673 1674 if (!ql2xdbwr) { 1675 ha->nxdb_wr_ptr = 1676 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1677 (ha->pdev->devfn << 12)), 4); 1678 if (!ha->nxdb_wr_ptr) { 1679 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1680 "Cannot remap MMIO, aborting.\n"); 1681 goto iospace_error_exit; 1682 } 1683 1684 /* Mapping of IO base pointer, 1685 * door bell read and write pointer 1686 */ 1687 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1688 (ha->pdev->devfn * 8); 1689 } else { 1690 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1691 QLA82XX_CAMRAM_DB1 : 1692 QLA82XX_CAMRAM_DB2); 1693 } 1694 1695 ha->max_req_queues = ha->max_rsp_queues = 1; 1696 ha->msix_count = ha->max_rsp_queues + 1; 1697 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1698 "nx_pci_base=%p iobase=%p " 1699 "max_req_queues=%d msix_count=%d.\n", 1700 (void *)ha->nx_pcibase, ha->iobase, 1701 ha->max_req_queues, ha->msix_count); 1702 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1703 "nx_pci_base=%p iobase=%p " 1704 "max_req_queues=%d msix_count=%d.\n", 1705 (void *)ha->nx_pcibase, ha->iobase, 1706 ha->max_req_queues, ha->msix_count); 1707 return 0; 1708 1709 iospace_error_exit: 1710 return -ENOMEM; 1711 } 1712 1713 /* GS related functions */ 1714 1715 /* Initialization related functions */ 1716 1717 /** 1718 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1719 * @ha: HA context 1720 * 1721 * Returns 0 on success. 1722 */ 1723 int 1724 qla82xx_pci_config(scsi_qla_host_t *vha) 1725 { 1726 struct qla_hw_data *ha = vha->hw; 1727 int ret; 1728 1729 pci_set_master(ha->pdev); 1730 ret = pci_set_mwi(ha->pdev); 1731 ha->chip_revision = ha->pdev->revision; 1732 ql_dbg(ql_dbg_init, vha, 0x0043, 1733 "Chip revision:%d.\n", 1734 ha->chip_revision); 1735 return 0; 1736 } 1737 1738 /** 1739 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1740 * @ha: HA context 1741 * 1742 * Returns 0 on success. 1743 */ 1744 void 1745 qla82xx_reset_chip(scsi_qla_host_t *vha) 1746 { 1747 struct qla_hw_data *ha = vha->hw; 1748 ha->isp_ops->disable_intrs(ha); 1749 } 1750 1751 void qla82xx_config_rings(struct scsi_qla_host *vha) 1752 { 1753 struct qla_hw_data *ha = vha->hw; 1754 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1755 struct init_cb_81xx *icb; 1756 struct req_que *req = ha->req_q_map[0]; 1757 struct rsp_que *rsp = ha->rsp_q_map[0]; 1758 1759 /* Setup ring parameters in initialization control block. */ 1760 icb = (struct init_cb_81xx *)ha->init_cb; 1761 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1762 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1763 icb->request_q_length = cpu_to_le16(req->length); 1764 icb->response_q_length = cpu_to_le16(rsp->length); 1765 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1766 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1767 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1768 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1769 1770 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1771 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1772 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1773 } 1774 1775 static int 1776 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1777 { 1778 u64 *ptr64; 1779 u32 i, flashaddr, size; 1780 __le64 data; 1781 1782 size = (IMAGE_START - BOOTLD_START) / 8; 1783 1784 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1785 flashaddr = BOOTLD_START; 1786 1787 for (i = 0; i < size; i++) { 1788 data = cpu_to_le64(ptr64[i]); 1789 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1790 return -EIO; 1791 flashaddr += 8; 1792 } 1793 1794 flashaddr = FLASH_ADDR_START; 1795 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1796 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1797 1798 for (i = 0; i < size; i++) { 1799 data = cpu_to_le64(ptr64[i]); 1800 1801 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1802 return -EIO; 1803 flashaddr += 8; 1804 } 1805 udelay(100); 1806 1807 /* Write a magic value to CAMRAM register 1808 * at a specified offset to indicate 1809 * that all data is written and 1810 * ready for firmware to initialize. 1811 */ 1812 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1813 1814 read_lock(&ha->hw_lock); 1815 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1816 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1817 read_unlock(&ha->hw_lock); 1818 return 0; 1819 } 1820 1821 static int 1822 qla82xx_set_product_offset(struct qla_hw_data *ha) 1823 { 1824 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1825 const uint8_t *unirom = ha->hablob->fw->data; 1826 uint32_t i; 1827 __le32 entries; 1828 __le32 flags, file_chiprev, offset; 1829 uint8_t chiprev = ha->chip_revision; 1830 /* Hardcoding mn_present flag for P3P */ 1831 int mn_present = 0; 1832 uint32_t flagbit; 1833 1834 ptab_desc = qla82xx_get_table_desc(unirom, 1835 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1836 if (!ptab_desc) 1837 return -1; 1838 1839 entries = cpu_to_le32(ptab_desc->num_entries); 1840 1841 for (i = 0; i < entries; i++) { 1842 offset = cpu_to_le32(ptab_desc->findex) + 1843 (i * cpu_to_le32(ptab_desc->entry_size)); 1844 flags = cpu_to_le32(*((int *)&unirom[offset] + 1845 QLA82XX_URI_FLAGS_OFF)); 1846 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1847 QLA82XX_URI_CHIP_REV_OFF)); 1848 1849 flagbit = mn_present ? 1 : 2; 1850 1851 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1852 ha->file_prd_off = offset; 1853 return 0; 1854 } 1855 } 1856 return -1; 1857 } 1858 1859 static int 1860 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1861 { 1862 __le32 val; 1863 uint32_t min_size; 1864 struct qla_hw_data *ha = vha->hw; 1865 const struct firmware *fw = ha->hablob->fw; 1866 1867 ha->fw_type = fw_type; 1868 1869 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1870 if (qla82xx_set_product_offset(ha)) 1871 return -EINVAL; 1872 1873 min_size = QLA82XX_URI_FW_MIN_SIZE; 1874 } else { 1875 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1876 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1877 return -EINVAL; 1878 1879 min_size = QLA82XX_FW_MIN_SIZE; 1880 } 1881 1882 if (fw->size < min_size) 1883 return -EINVAL; 1884 return 0; 1885 } 1886 1887 static int 1888 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1889 { 1890 u32 val = 0; 1891 int retries = 60; 1892 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1893 1894 do { 1895 read_lock(&ha->hw_lock); 1896 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1897 read_unlock(&ha->hw_lock); 1898 1899 switch (val) { 1900 case PHAN_INITIALIZE_COMPLETE: 1901 case PHAN_INITIALIZE_ACK: 1902 return QLA_SUCCESS; 1903 case PHAN_INITIALIZE_FAILED: 1904 break; 1905 default: 1906 break; 1907 } 1908 ql_log(ql_log_info, vha, 0x00a8, 1909 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1910 val, retries); 1911 1912 msleep(500); 1913 1914 } while (--retries); 1915 1916 ql_log(ql_log_fatal, vha, 0x00a9, 1917 "Cmd Peg initialization failed: 0x%x.\n", val); 1918 1919 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1920 read_lock(&ha->hw_lock); 1921 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1922 read_unlock(&ha->hw_lock); 1923 return QLA_FUNCTION_FAILED; 1924 } 1925 1926 static int 1927 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1928 { 1929 u32 val = 0; 1930 int retries = 60; 1931 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1932 1933 do { 1934 read_lock(&ha->hw_lock); 1935 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1936 read_unlock(&ha->hw_lock); 1937 1938 switch (val) { 1939 case PHAN_INITIALIZE_COMPLETE: 1940 case PHAN_INITIALIZE_ACK: 1941 return QLA_SUCCESS; 1942 case PHAN_INITIALIZE_FAILED: 1943 break; 1944 default: 1945 break; 1946 } 1947 ql_log(ql_log_info, vha, 0x00ab, 1948 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1949 val, retries); 1950 1951 msleep(500); 1952 1953 } while (--retries); 1954 1955 ql_log(ql_log_fatal, vha, 0x00ac, 1956 "Rcv Peg initializatin failed: 0x%x.\n", val); 1957 read_lock(&ha->hw_lock); 1958 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1959 read_unlock(&ha->hw_lock); 1960 return QLA_FUNCTION_FAILED; 1961 } 1962 1963 /* ISR related functions */ 1964 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1965 QLA82XX_LEGACY_INTR_CONFIG; 1966 1967 /* 1968 * qla82xx_mbx_completion() - Process mailbox command completions. 1969 * @ha: SCSI driver HA context 1970 * @mb0: Mailbox0 register 1971 */ 1972 void 1973 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1974 { 1975 uint16_t cnt; 1976 uint16_t __iomem *wptr; 1977 struct qla_hw_data *ha = vha->hw; 1978 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1979 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1980 1981 /* Load return mailbox registers. */ 1982 ha->flags.mbox_int = 1; 1983 ha->mailbox_out[0] = mb0; 1984 1985 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1986 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1987 wptr++; 1988 } 1989 1990 if (!ha->mcp) 1991 ql_dbg(ql_dbg_async, vha, 0x5053, 1992 "MBX pointer ERROR.\n"); 1993 } 1994 1995 /* 1996 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1997 * @irq: 1998 * @dev_id: SCSI driver HA context 1999 * @regs: 2000 * 2001 * Called by system whenever the host adapter generates an interrupt. 2002 * 2003 * Returns handled flag. 2004 */ 2005 irqreturn_t 2006 qla82xx_intr_handler(int irq, void *dev_id) 2007 { 2008 scsi_qla_host_t *vha; 2009 struct qla_hw_data *ha; 2010 struct rsp_que *rsp; 2011 struct device_reg_82xx __iomem *reg; 2012 int status = 0, status1 = 0; 2013 unsigned long flags; 2014 unsigned long iter; 2015 uint32_t stat = 0; 2016 uint16_t mb[4]; 2017 2018 rsp = (struct rsp_que *) dev_id; 2019 if (!rsp) { 2020 ql_log(ql_log_info, NULL, 0xb053, 2021 "%s: NULL response queue pointer.\n", __func__); 2022 return IRQ_NONE; 2023 } 2024 ha = rsp->hw; 2025 2026 if (!ha->flags.msi_enabled) { 2027 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2028 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2029 return IRQ_NONE; 2030 2031 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2032 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2033 return IRQ_NONE; 2034 } 2035 2036 /* clear the interrupt */ 2037 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2038 2039 /* read twice to ensure write is flushed */ 2040 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2041 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2042 2043 reg = &ha->iobase->isp82; 2044 2045 spin_lock_irqsave(&ha->hardware_lock, flags); 2046 vha = pci_get_drvdata(ha->pdev); 2047 for (iter = 1; iter--; ) { 2048 2049 if (RD_REG_DWORD(®->host_int)) { 2050 stat = RD_REG_DWORD(®->host_status); 2051 2052 switch (stat & 0xff) { 2053 case 0x1: 2054 case 0x2: 2055 case 0x10: 2056 case 0x11: 2057 qla82xx_mbx_completion(vha, MSW(stat)); 2058 status |= MBX_INTERRUPT; 2059 break; 2060 case 0x12: 2061 mb[0] = MSW(stat); 2062 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2063 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2064 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2065 qla2x00_async_event(vha, rsp, mb); 2066 break; 2067 case 0x13: 2068 qla24xx_process_response_queue(vha, rsp); 2069 break; 2070 default: 2071 ql_dbg(ql_dbg_async, vha, 0x5054, 2072 "Unrecognized interrupt type (%d).\n", 2073 stat & 0xff); 2074 break; 2075 } 2076 } 2077 WRT_REG_DWORD(®->host_int, 0); 2078 } 2079 2080 qla2x00_handle_mbx_completion(ha, status); 2081 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2082 2083 if (!ha->flags.msi_enabled) 2084 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2085 2086 return IRQ_HANDLED; 2087 } 2088 2089 irqreturn_t 2090 qla82xx_msix_default(int irq, void *dev_id) 2091 { 2092 scsi_qla_host_t *vha; 2093 struct qla_hw_data *ha; 2094 struct rsp_que *rsp; 2095 struct device_reg_82xx __iomem *reg; 2096 int status = 0; 2097 unsigned long flags; 2098 uint32_t stat = 0; 2099 uint16_t mb[4]; 2100 2101 rsp = (struct rsp_que *) dev_id; 2102 if (!rsp) { 2103 printk(KERN_INFO 2104 "%s(): NULL response queue pointer.\n", __func__); 2105 return IRQ_NONE; 2106 } 2107 ha = rsp->hw; 2108 2109 reg = &ha->iobase->isp82; 2110 2111 spin_lock_irqsave(&ha->hardware_lock, flags); 2112 vha = pci_get_drvdata(ha->pdev); 2113 do { 2114 if (RD_REG_DWORD(®->host_int)) { 2115 stat = RD_REG_DWORD(®->host_status); 2116 2117 switch (stat & 0xff) { 2118 case 0x1: 2119 case 0x2: 2120 case 0x10: 2121 case 0x11: 2122 qla82xx_mbx_completion(vha, MSW(stat)); 2123 status |= MBX_INTERRUPT; 2124 break; 2125 case 0x12: 2126 mb[0] = MSW(stat); 2127 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2128 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2129 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2130 qla2x00_async_event(vha, rsp, mb); 2131 break; 2132 case 0x13: 2133 qla24xx_process_response_queue(vha, rsp); 2134 break; 2135 default: 2136 ql_dbg(ql_dbg_async, vha, 0x5041, 2137 "Unrecognized interrupt type (%d).\n", 2138 stat & 0xff); 2139 break; 2140 } 2141 } 2142 WRT_REG_DWORD(®->host_int, 0); 2143 } while (0); 2144 2145 qla2x00_handle_mbx_completion(ha, status); 2146 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2147 2148 return IRQ_HANDLED; 2149 } 2150 2151 irqreturn_t 2152 qla82xx_msix_rsp_q(int irq, void *dev_id) 2153 { 2154 scsi_qla_host_t *vha; 2155 struct qla_hw_data *ha; 2156 struct rsp_que *rsp; 2157 struct device_reg_82xx __iomem *reg; 2158 unsigned long flags; 2159 2160 rsp = (struct rsp_que *) dev_id; 2161 if (!rsp) { 2162 printk(KERN_INFO 2163 "%s(): NULL response queue pointer.\n", __func__); 2164 return IRQ_NONE; 2165 } 2166 2167 ha = rsp->hw; 2168 reg = &ha->iobase->isp82; 2169 spin_lock_irqsave(&ha->hardware_lock, flags); 2170 vha = pci_get_drvdata(ha->pdev); 2171 qla24xx_process_response_queue(vha, rsp); 2172 WRT_REG_DWORD(®->host_int, 0); 2173 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2174 return IRQ_HANDLED; 2175 } 2176 2177 void 2178 qla82xx_poll(int irq, void *dev_id) 2179 { 2180 scsi_qla_host_t *vha; 2181 struct qla_hw_data *ha; 2182 struct rsp_que *rsp; 2183 struct device_reg_82xx __iomem *reg; 2184 int status = 0; 2185 uint32_t stat; 2186 uint16_t mb[4]; 2187 unsigned long flags; 2188 2189 rsp = (struct rsp_que *) dev_id; 2190 if (!rsp) { 2191 printk(KERN_INFO 2192 "%s(): NULL response queue pointer.\n", __func__); 2193 return; 2194 } 2195 ha = rsp->hw; 2196 2197 reg = &ha->iobase->isp82; 2198 spin_lock_irqsave(&ha->hardware_lock, flags); 2199 vha = pci_get_drvdata(ha->pdev); 2200 2201 if (RD_REG_DWORD(®->host_int)) { 2202 stat = RD_REG_DWORD(®->host_status); 2203 switch (stat & 0xff) { 2204 case 0x1: 2205 case 0x2: 2206 case 0x10: 2207 case 0x11: 2208 qla82xx_mbx_completion(vha, MSW(stat)); 2209 status |= MBX_INTERRUPT; 2210 break; 2211 case 0x12: 2212 mb[0] = MSW(stat); 2213 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2214 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2215 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2216 qla2x00_async_event(vha, rsp, mb); 2217 break; 2218 case 0x13: 2219 qla24xx_process_response_queue(vha, rsp); 2220 break; 2221 default: 2222 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2223 "Unrecognized interrupt type (%d).\n", 2224 stat * 0xff); 2225 break; 2226 } 2227 } 2228 WRT_REG_DWORD(®->host_int, 0); 2229 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2230 } 2231 2232 void 2233 qla82xx_enable_intrs(struct qla_hw_data *ha) 2234 { 2235 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2236 qla82xx_mbx_intr_enable(vha); 2237 spin_lock_irq(&ha->hardware_lock); 2238 if (IS_QLA8044(ha)) 2239 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2240 else 2241 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2242 spin_unlock_irq(&ha->hardware_lock); 2243 ha->interrupts_on = 1; 2244 } 2245 2246 void 2247 qla82xx_disable_intrs(struct qla_hw_data *ha) 2248 { 2249 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2250 qla82xx_mbx_intr_disable(vha); 2251 spin_lock_irq(&ha->hardware_lock); 2252 if (IS_QLA8044(ha)) 2253 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2254 else 2255 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2256 spin_unlock_irq(&ha->hardware_lock); 2257 ha->interrupts_on = 0; 2258 } 2259 2260 void qla82xx_init_flags(struct qla_hw_data *ha) 2261 { 2262 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2263 2264 /* ISP 8021 initializations */ 2265 rwlock_init(&ha->hw_lock); 2266 ha->qdr_sn_window = -1; 2267 ha->ddr_mn_window = -1; 2268 ha->curr_window = 255; 2269 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2270 nx_legacy_intr = &legacy_intr[ha->portnum]; 2271 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2272 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2273 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2274 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2275 } 2276 2277 inline void 2278 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2279 { 2280 int idc_ver; 2281 uint32_t drv_active; 2282 struct qla_hw_data *ha = vha->hw; 2283 2284 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2285 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2286 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2287 QLA82XX_IDC_VERSION); 2288 ql_log(ql_log_info, vha, 0xb082, 2289 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2290 } else { 2291 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2292 if (idc_ver != QLA82XX_IDC_VERSION) 2293 ql_log(ql_log_info, vha, 0xb083, 2294 "qla2xxx driver IDC version %d is not compatible " 2295 "with IDC version %d of the other drivers\n", 2296 QLA82XX_IDC_VERSION, idc_ver); 2297 } 2298 } 2299 2300 inline void 2301 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2302 { 2303 uint32_t drv_active; 2304 struct qla_hw_data *ha = vha->hw; 2305 2306 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2307 2308 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2309 if (drv_active == 0xffffffff) { 2310 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2311 QLA82XX_DRV_NOT_ACTIVE); 2312 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2313 } 2314 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2315 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2316 } 2317 2318 inline void 2319 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2320 { 2321 uint32_t drv_active; 2322 2323 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2324 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2325 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2326 } 2327 2328 static inline int 2329 qla82xx_need_reset(struct qla_hw_data *ha) 2330 { 2331 uint32_t drv_state; 2332 int rval; 2333 2334 if (ha->flags.nic_core_reset_owner) 2335 return 1; 2336 else { 2337 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2338 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2339 return rval; 2340 } 2341 } 2342 2343 static inline void 2344 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2345 { 2346 uint32_t drv_state; 2347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2348 2349 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2350 2351 /* If reset value is all FF's, initialize DRV_STATE */ 2352 if (drv_state == 0xffffffff) { 2353 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2354 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2355 } 2356 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2357 ql_dbg(ql_dbg_init, vha, 0x00bb, 2358 "drv_state = 0x%08x.\n", drv_state); 2359 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2360 } 2361 2362 static inline void 2363 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2364 { 2365 uint32_t drv_state; 2366 2367 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2368 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2369 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2370 } 2371 2372 static inline void 2373 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2374 { 2375 uint32_t qsnt_state; 2376 2377 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2378 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2379 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2380 } 2381 2382 void 2383 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2384 { 2385 struct qla_hw_data *ha = vha->hw; 2386 uint32_t qsnt_state; 2387 2388 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2389 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2390 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2391 } 2392 2393 static int 2394 qla82xx_load_fw(scsi_qla_host_t *vha) 2395 { 2396 int rst; 2397 struct fw_blob *blob; 2398 struct qla_hw_data *ha = vha->hw; 2399 2400 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2401 ql_log(ql_log_fatal, vha, 0x009f, 2402 "Error during CRB initialization.\n"); 2403 return QLA_FUNCTION_FAILED; 2404 } 2405 udelay(500); 2406 2407 /* Bring QM and CAMRAM out of reset */ 2408 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2409 rst &= ~((1 << 28) | (1 << 24)); 2410 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2411 2412 /* 2413 * FW Load priority: 2414 * 1) Operational firmware residing in flash. 2415 * 2) Firmware via request-firmware interface (.bin file). 2416 */ 2417 if (ql2xfwloadbin == 2) 2418 goto try_blob_fw; 2419 2420 ql_log(ql_log_info, vha, 0x00a0, 2421 "Attempting to load firmware from flash.\n"); 2422 2423 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2424 ql_log(ql_log_info, vha, 0x00a1, 2425 "Firmware loaded successfully from flash.\n"); 2426 return QLA_SUCCESS; 2427 } else { 2428 ql_log(ql_log_warn, vha, 0x0108, 2429 "Firmware load from flash failed.\n"); 2430 } 2431 2432 try_blob_fw: 2433 ql_log(ql_log_info, vha, 0x00a2, 2434 "Attempting to load firmware from blob.\n"); 2435 2436 /* Load firmware blob. */ 2437 blob = ha->hablob = qla2x00_request_firmware(vha); 2438 if (!blob) { 2439 ql_log(ql_log_fatal, vha, 0x00a3, 2440 "Firmware image not present.\n"); 2441 goto fw_load_failed; 2442 } 2443 2444 /* Validating firmware blob */ 2445 if (qla82xx_validate_firmware_blob(vha, 2446 QLA82XX_FLASH_ROMIMAGE)) { 2447 /* Fallback to URI format */ 2448 if (qla82xx_validate_firmware_blob(vha, 2449 QLA82XX_UNIFIED_ROMIMAGE)) { 2450 ql_log(ql_log_fatal, vha, 0x00a4, 2451 "No valid firmware image found.\n"); 2452 return QLA_FUNCTION_FAILED; 2453 } 2454 } 2455 2456 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2457 ql_log(ql_log_info, vha, 0x00a5, 2458 "Firmware loaded successfully from binary blob.\n"); 2459 return QLA_SUCCESS; 2460 } else { 2461 ql_log(ql_log_fatal, vha, 0x00a6, 2462 "Firmware load failed for binary blob.\n"); 2463 blob->fw = NULL; 2464 blob = NULL; 2465 goto fw_load_failed; 2466 } 2467 return QLA_SUCCESS; 2468 2469 fw_load_failed: 2470 return QLA_FUNCTION_FAILED; 2471 } 2472 2473 int 2474 qla82xx_start_firmware(scsi_qla_host_t *vha) 2475 { 2476 uint16_t lnk; 2477 struct qla_hw_data *ha = vha->hw; 2478 2479 /* scrub dma mask expansion register */ 2480 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2481 2482 /* Put both the PEG CMD and RCV PEG to default state 2483 * of 0 before resetting the hardware 2484 */ 2485 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2486 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2487 2488 /* Overwrite stale initialization register values */ 2489 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2490 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2491 2492 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2493 ql_log(ql_log_fatal, vha, 0x00a7, 2494 "Error trying to start fw.\n"); 2495 return QLA_FUNCTION_FAILED; 2496 } 2497 2498 /* Handshake with the card before we register the devices. */ 2499 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2500 ql_log(ql_log_fatal, vha, 0x00aa, 2501 "Error during card handshake.\n"); 2502 return QLA_FUNCTION_FAILED; 2503 } 2504 2505 /* Negotiated Link width */ 2506 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2507 ha->link_width = (lnk >> 4) & 0x3f; 2508 2509 /* Synchronize with Receive peg */ 2510 return qla82xx_check_rcvpeg_state(ha); 2511 } 2512 2513 static uint32_t * 2514 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2515 uint32_t length) 2516 { 2517 uint32_t i; 2518 uint32_t val; 2519 struct qla_hw_data *ha = vha->hw; 2520 2521 /* Dword reads to flash. */ 2522 for (i = 0; i < length/4; i++, faddr += 4) { 2523 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2524 ql_log(ql_log_warn, vha, 0x0106, 2525 "Do ROM fast read failed.\n"); 2526 goto done_read; 2527 } 2528 dwptr[i] = __constant_cpu_to_le32(val); 2529 } 2530 done_read: 2531 return dwptr; 2532 } 2533 2534 static int 2535 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2536 { 2537 int ret; 2538 uint32_t val; 2539 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2540 2541 ret = ql82xx_rom_lock_d(ha); 2542 if (ret < 0) { 2543 ql_log(ql_log_warn, vha, 0xb014, 2544 "ROM Lock failed.\n"); 2545 return ret; 2546 } 2547 2548 ret = qla82xx_read_status_reg(ha, &val); 2549 if (ret < 0) 2550 goto done_unprotect; 2551 2552 val &= ~(BLOCK_PROTECT_BITS << 2); 2553 ret = qla82xx_write_status_reg(ha, val); 2554 if (ret < 0) { 2555 val |= (BLOCK_PROTECT_BITS << 2); 2556 qla82xx_write_status_reg(ha, val); 2557 } 2558 2559 if (qla82xx_write_disable_flash(ha) != 0) 2560 ql_log(ql_log_warn, vha, 0xb015, 2561 "Write disable failed.\n"); 2562 2563 done_unprotect: 2564 qla82xx_rom_unlock(ha); 2565 return ret; 2566 } 2567 2568 static int 2569 qla82xx_protect_flash(struct qla_hw_data *ha) 2570 { 2571 int ret; 2572 uint32_t val; 2573 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2574 2575 ret = ql82xx_rom_lock_d(ha); 2576 if (ret < 0) { 2577 ql_log(ql_log_warn, vha, 0xb016, 2578 "ROM Lock failed.\n"); 2579 return ret; 2580 } 2581 2582 ret = qla82xx_read_status_reg(ha, &val); 2583 if (ret < 0) 2584 goto done_protect; 2585 2586 val |= (BLOCK_PROTECT_BITS << 2); 2587 /* LOCK all sectors */ 2588 ret = qla82xx_write_status_reg(ha, val); 2589 if (ret < 0) 2590 ql_log(ql_log_warn, vha, 0xb017, 2591 "Write status register failed.\n"); 2592 2593 if (qla82xx_write_disable_flash(ha) != 0) 2594 ql_log(ql_log_warn, vha, 0xb018, 2595 "Write disable failed.\n"); 2596 done_protect: 2597 qla82xx_rom_unlock(ha); 2598 return ret; 2599 } 2600 2601 static int 2602 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2603 { 2604 int ret = 0; 2605 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2606 2607 ret = ql82xx_rom_lock_d(ha); 2608 if (ret < 0) { 2609 ql_log(ql_log_warn, vha, 0xb019, 2610 "ROM Lock failed.\n"); 2611 return ret; 2612 } 2613 2614 qla82xx_flash_set_write_enable(ha); 2615 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2616 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2617 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2618 2619 if (qla82xx_wait_rom_done(ha)) { 2620 ql_log(ql_log_warn, vha, 0xb01a, 2621 "Error waiting for rom done.\n"); 2622 ret = -1; 2623 goto done; 2624 } 2625 ret = qla82xx_flash_wait_write_finish(ha); 2626 done: 2627 qla82xx_rom_unlock(ha); 2628 return ret; 2629 } 2630 2631 /* 2632 * Address and length are byte address 2633 */ 2634 uint8_t * 2635 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2636 uint32_t offset, uint32_t length) 2637 { 2638 scsi_block_requests(vha->host); 2639 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2640 scsi_unblock_requests(vha->host); 2641 return buf; 2642 } 2643 2644 static int 2645 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2646 uint32_t faddr, uint32_t dwords) 2647 { 2648 int ret; 2649 uint32_t liter; 2650 uint32_t sec_mask, rest_addr; 2651 dma_addr_t optrom_dma; 2652 void *optrom = NULL; 2653 int page_mode = 0; 2654 struct qla_hw_data *ha = vha->hw; 2655 2656 ret = -1; 2657 2658 /* Prepare burst-capable write on supported ISPs. */ 2659 if (page_mode && !(faddr & 0xfff) && 2660 dwords > OPTROM_BURST_DWORDS) { 2661 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2662 &optrom_dma, GFP_KERNEL); 2663 if (!optrom) { 2664 ql_log(ql_log_warn, vha, 0xb01b, 2665 "Unable to allocate memory " 2666 "for optrom burst write (%x KB).\n", 2667 OPTROM_BURST_SIZE / 1024); 2668 } 2669 } 2670 2671 rest_addr = ha->fdt_block_size - 1; 2672 sec_mask = ~rest_addr; 2673 2674 ret = qla82xx_unprotect_flash(ha); 2675 if (ret) { 2676 ql_log(ql_log_warn, vha, 0xb01c, 2677 "Unable to unprotect flash for update.\n"); 2678 goto write_done; 2679 } 2680 2681 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2682 /* Are we at the beginning of a sector? */ 2683 if ((faddr & rest_addr) == 0) { 2684 2685 ret = qla82xx_erase_sector(ha, faddr); 2686 if (ret) { 2687 ql_log(ql_log_warn, vha, 0xb01d, 2688 "Unable to erase sector: address=%x.\n", 2689 faddr); 2690 break; 2691 } 2692 } 2693 2694 /* Go with burst-write. */ 2695 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2696 /* Copy data to DMA'ble buffer. */ 2697 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2698 2699 ret = qla2x00_load_ram(vha, optrom_dma, 2700 (ha->flash_data_off | faddr), 2701 OPTROM_BURST_DWORDS); 2702 if (ret != QLA_SUCCESS) { 2703 ql_log(ql_log_warn, vha, 0xb01e, 2704 "Unable to burst-write optrom segment " 2705 "(%x/%x/%llx).\n", ret, 2706 (ha->flash_data_off | faddr), 2707 (unsigned long long)optrom_dma); 2708 ql_log(ql_log_warn, vha, 0xb01f, 2709 "Reverting to slow-write.\n"); 2710 2711 dma_free_coherent(&ha->pdev->dev, 2712 OPTROM_BURST_SIZE, optrom, optrom_dma); 2713 optrom = NULL; 2714 } else { 2715 liter += OPTROM_BURST_DWORDS - 1; 2716 faddr += OPTROM_BURST_DWORDS - 1; 2717 dwptr += OPTROM_BURST_DWORDS - 1; 2718 continue; 2719 } 2720 } 2721 2722 ret = qla82xx_write_flash_dword(ha, faddr, 2723 cpu_to_le32(*dwptr)); 2724 if (ret) { 2725 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2726 "Unable to program flash address=%x data=%x.\n", 2727 faddr, *dwptr); 2728 break; 2729 } 2730 } 2731 2732 ret = qla82xx_protect_flash(ha); 2733 if (ret) 2734 ql_log(ql_log_warn, vha, 0xb021, 2735 "Unable to protect flash after update.\n"); 2736 write_done: 2737 if (optrom) 2738 dma_free_coherent(&ha->pdev->dev, 2739 OPTROM_BURST_SIZE, optrom, optrom_dma); 2740 return ret; 2741 } 2742 2743 int 2744 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2745 uint32_t offset, uint32_t length) 2746 { 2747 int rval; 2748 2749 /* Suspend HBA. */ 2750 scsi_block_requests(vha->host); 2751 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2752 length >> 2); 2753 scsi_unblock_requests(vha->host); 2754 2755 /* Convert return ISP82xx to generic */ 2756 if (rval) 2757 rval = QLA_FUNCTION_FAILED; 2758 else 2759 rval = QLA_SUCCESS; 2760 return rval; 2761 } 2762 2763 void 2764 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2765 { 2766 struct qla_hw_data *ha = vha->hw; 2767 struct req_que *req = ha->req_q_map[0]; 2768 struct device_reg_82xx __iomem *reg; 2769 uint32_t dbval; 2770 2771 /* Adjust ring index. */ 2772 req->ring_index++; 2773 if (req->ring_index == req->length) { 2774 req->ring_index = 0; 2775 req->ring_ptr = req->ring; 2776 } else 2777 req->ring_ptr++; 2778 2779 reg = &ha->iobase->isp82; 2780 dbval = 0x04 | (ha->portnum << 5); 2781 2782 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2783 if (ql2xdbwr) 2784 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2785 else { 2786 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2787 wmb(); 2788 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 2789 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2790 dbval); 2791 wmb(); 2792 } 2793 } 2794 } 2795 2796 static void 2797 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2798 { 2799 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2800 2801 if (qla82xx_rom_lock(ha)) 2802 /* Someone else is holding the lock. */ 2803 ql_log(ql_log_info, vha, 0xb022, 2804 "Resetting rom_lock.\n"); 2805 2806 /* 2807 * Either we got the lock, or someone 2808 * else died while holding it. 2809 * In either case, unlock. 2810 */ 2811 qla82xx_rom_unlock(ha); 2812 } 2813 2814 /* 2815 * qla82xx_device_bootstrap 2816 * Initialize device, set DEV_READY, start fw 2817 * 2818 * Note: 2819 * IDC lock must be held upon entry 2820 * 2821 * Return: 2822 * Success : 0 2823 * Failed : 1 2824 */ 2825 static int 2826 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2827 { 2828 int rval = QLA_SUCCESS; 2829 int i, timeout; 2830 uint32_t old_count, count; 2831 struct qla_hw_data *ha = vha->hw; 2832 int need_reset = 0, peg_stuck = 1; 2833 2834 need_reset = qla82xx_need_reset(ha); 2835 2836 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2837 2838 for (i = 0; i < 10; i++) { 2839 timeout = msleep_interruptible(200); 2840 if (timeout) { 2841 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2842 QLA8XXX_DEV_FAILED); 2843 return QLA_FUNCTION_FAILED; 2844 } 2845 2846 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2847 if (count != old_count) 2848 peg_stuck = 0; 2849 } 2850 2851 if (need_reset) { 2852 /* We are trying to perform a recovery here. */ 2853 if (peg_stuck) 2854 qla82xx_rom_lock_recovery(ha); 2855 goto dev_initialize; 2856 } else { 2857 /* Start of day for this ha context. */ 2858 if (peg_stuck) { 2859 /* Either we are the first or recovery in progress. */ 2860 qla82xx_rom_lock_recovery(ha); 2861 goto dev_initialize; 2862 } else 2863 /* Firmware already running. */ 2864 goto dev_ready; 2865 } 2866 2867 return rval; 2868 2869 dev_initialize: 2870 /* set to DEV_INITIALIZING */ 2871 ql_log(ql_log_info, vha, 0x009e, 2872 "HW State: INITIALIZING.\n"); 2873 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2874 2875 qla82xx_idc_unlock(ha); 2876 rval = qla82xx_start_firmware(vha); 2877 qla82xx_idc_lock(ha); 2878 2879 if (rval != QLA_SUCCESS) { 2880 ql_log(ql_log_fatal, vha, 0x00ad, 2881 "HW State: FAILED.\n"); 2882 qla82xx_clear_drv_active(ha); 2883 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2884 return rval; 2885 } 2886 2887 dev_ready: 2888 ql_log(ql_log_info, vha, 0x00ae, 2889 "HW State: READY.\n"); 2890 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2891 2892 return QLA_SUCCESS; 2893 } 2894 2895 /* 2896 * qla82xx_need_qsnt_handler 2897 * Code to start quiescence sequence 2898 * 2899 * Note: 2900 * IDC lock must be held upon entry 2901 * 2902 * Return: void 2903 */ 2904 2905 static void 2906 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2907 { 2908 struct qla_hw_data *ha = vha->hw; 2909 uint32_t dev_state, drv_state, drv_active; 2910 unsigned long reset_timeout; 2911 2912 if (vha->flags.online) { 2913 /*Block any further I/O and wait for pending cmnds to complete*/ 2914 qla2x00_quiesce_io(vha); 2915 } 2916 2917 /* Set the quiescence ready bit */ 2918 qla82xx_set_qsnt_ready(ha); 2919 2920 /*wait for 30 secs for other functions to ack */ 2921 reset_timeout = jiffies + (30 * HZ); 2922 2923 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2924 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2925 /* Its 2 that is written when qsnt is acked, moving one bit */ 2926 drv_active = drv_active << 0x01; 2927 2928 while (drv_state != drv_active) { 2929 2930 if (time_after_eq(jiffies, reset_timeout)) { 2931 /* quiescence timeout, other functions didn't ack 2932 * changing the state to DEV_READY 2933 */ 2934 ql_log(ql_log_info, vha, 0xb023, 2935 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2936 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2937 drv_active, drv_state); 2938 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2939 QLA8XXX_DEV_READY); 2940 ql_log(ql_log_info, vha, 0xb025, 2941 "HW State: DEV_READY.\n"); 2942 qla82xx_idc_unlock(ha); 2943 qla2x00_perform_loop_resync(vha); 2944 qla82xx_idc_lock(ha); 2945 2946 qla82xx_clear_qsnt_ready(vha); 2947 return; 2948 } 2949 2950 qla82xx_idc_unlock(ha); 2951 msleep(1000); 2952 qla82xx_idc_lock(ha); 2953 2954 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2955 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2956 drv_active = drv_active << 0x01; 2957 } 2958 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2959 /* everyone acked so set the state to DEV_QUIESCENCE */ 2960 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2961 ql_log(ql_log_info, vha, 0xb026, 2962 "HW State: DEV_QUIESCENT.\n"); 2963 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2964 } 2965 } 2966 2967 /* 2968 * qla82xx_wait_for_state_change 2969 * Wait for device state to change from given current state 2970 * 2971 * Note: 2972 * IDC lock must not be held upon entry 2973 * 2974 * Return: 2975 * Changed device state. 2976 */ 2977 uint32_t 2978 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2979 { 2980 struct qla_hw_data *ha = vha->hw; 2981 uint32_t dev_state; 2982 2983 do { 2984 msleep(1000); 2985 qla82xx_idc_lock(ha); 2986 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2987 qla82xx_idc_unlock(ha); 2988 } while (dev_state == curr_state); 2989 2990 return dev_state; 2991 } 2992 2993 void 2994 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2995 { 2996 struct qla_hw_data *ha = vha->hw; 2997 2998 /* Disable the board */ 2999 ql_log(ql_log_fatal, vha, 0x00b8, 3000 "Disabling the board.\n"); 3001 3002 if (IS_QLA82XX(ha)) { 3003 qla82xx_clear_drv_active(ha); 3004 qla82xx_idc_unlock(ha); 3005 } else if (IS_QLA8044(ha)) { 3006 qla8044_clear_drv_active(vha); 3007 qla8044_idc_unlock(ha); 3008 } 3009 3010 /* Set DEV_FAILED flag to disable timer */ 3011 vha->device_flags |= DFLG_DEV_FAILED; 3012 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3013 qla2x00_mark_all_devices_lost(vha, 0); 3014 vha->flags.online = 0; 3015 vha->flags.init_done = 0; 3016 } 3017 3018 /* 3019 * qla82xx_need_reset_handler 3020 * Code to start reset sequence 3021 * 3022 * Note: 3023 * IDC lock must be held upon entry 3024 * 3025 * Return: 3026 * Success : 0 3027 * Failed : 1 3028 */ 3029 static void 3030 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3031 { 3032 uint32_t dev_state, drv_state, drv_active; 3033 uint32_t active_mask = 0; 3034 unsigned long reset_timeout; 3035 struct qla_hw_data *ha = vha->hw; 3036 struct req_que *req = ha->req_q_map[0]; 3037 3038 if (vha->flags.online) { 3039 qla82xx_idc_unlock(ha); 3040 qla2x00_abort_isp_cleanup(vha); 3041 ha->isp_ops->get_flash_version(vha, req->ring); 3042 ha->isp_ops->nvram_config(vha); 3043 qla82xx_idc_lock(ha); 3044 } 3045 3046 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3047 if (!ha->flags.nic_core_reset_owner) { 3048 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3049 "reset_acknowledged by 0x%x\n", ha->portnum); 3050 qla82xx_set_rst_ready(ha); 3051 } else { 3052 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3053 drv_active &= active_mask; 3054 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3055 "active_mask: 0x%08x\n", active_mask); 3056 } 3057 3058 /* wait for 10 seconds for reset ack from all functions */ 3059 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3060 3061 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3062 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3063 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3064 3065 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3066 "drv_state: 0x%08x, drv_active: 0x%08x, " 3067 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3068 drv_state, drv_active, dev_state, active_mask); 3069 3070 while (drv_state != drv_active && 3071 dev_state != QLA8XXX_DEV_INITIALIZING) { 3072 if (time_after_eq(jiffies, reset_timeout)) { 3073 ql_log(ql_log_warn, vha, 0x00b5, 3074 "Reset timeout.\n"); 3075 break; 3076 } 3077 qla82xx_idc_unlock(ha); 3078 msleep(1000); 3079 qla82xx_idc_lock(ha); 3080 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3081 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3082 if (ha->flags.nic_core_reset_owner) 3083 drv_active &= active_mask; 3084 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3085 } 3086 3087 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3088 "drv_state: 0x%08x, drv_active: 0x%08x, " 3089 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3090 drv_state, drv_active, dev_state, active_mask); 3091 3092 ql_log(ql_log_info, vha, 0x00b6, 3093 "Device state is 0x%x = %s.\n", 3094 dev_state, 3095 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3096 3097 /* Force to DEV_COLD unless someone else is starting a reset */ 3098 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3099 dev_state != QLA8XXX_DEV_COLD) { 3100 ql_log(ql_log_info, vha, 0x00b7, 3101 "HW State: COLD/RE-INIT.\n"); 3102 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3103 qla82xx_set_rst_ready(ha); 3104 if (ql2xmdenable) { 3105 if (qla82xx_md_collect(vha)) 3106 ql_log(ql_log_warn, vha, 0xb02c, 3107 "Minidump not collected.\n"); 3108 } else 3109 ql_log(ql_log_warn, vha, 0xb04f, 3110 "Minidump disabled.\n"); 3111 } 3112 } 3113 3114 int 3115 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3116 { 3117 struct qla_hw_data *ha = vha->hw; 3118 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3119 int rval = QLA_SUCCESS; 3120 3121 fw_major_version = ha->fw_major_version; 3122 fw_minor_version = ha->fw_minor_version; 3123 fw_subminor_version = ha->fw_subminor_version; 3124 3125 rval = qla2x00_get_fw_version(vha); 3126 if (rval != QLA_SUCCESS) 3127 return rval; 3128 3129 if (ql2xmdenable) { 3130 if (!ha->fw_dumped) { 3131 if (fw_major_version != ha->fw_major_version || 3132 fw_minor_version != ha->fw_minor_version || 3133 fw_subminor_version != ha->fw_subminor_version) { 3134 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3135 "Firmware version differs " 3136 "Previous version: %d:%d:%d - " 3137 "New version: %d:%d:%d\n", 3138 fw_major_version, fw_minor_version, 3139 fw_subminor_version, 3140 ha->fw_major_version, 3141 ha->fw_minor_version, 3142 ha->fw_subminor_version); 3143 /* Release MiniDump resources */ 3144 qla82xx_md_free(vha); 3145 /* ALlocate MiniDump resources */ 3146 qla82xx_md_prep(vha); 3147 } 3148 } else 3149 ql_log(ql_log_info, vha, 0xb02e, 3150 "Firmware dump available to retrieve\n"); 3151 } 3152 return rval; 3153 } 3154 3155 3156 static int 3157 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3158 { 3159 uint32_t fw_heartbeat_counter; 3160 int status = 0; 3161 3162 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3163 QLA82XX_PEG_ALIVE_COUNTER); 3164 /* all 0xff, assume AER/EEH in progress, ignore */ 3165 if (fw_heartbeat_counter == 0xffffffff) { 3166 ql_dbg(ql_dbg_timer, vha, 0x6003, 3167 "FW heartbeat counter is 0xffffffff, " 3168 "returning status=%d.\n", status); 3169 return status; 3170 } 3171 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3172 vha->seconds_since_last_heartbeat++; 3173 /* FW not alive after 2 seconds */ 3174 if (vha->seconds_since_last_heartbeat == 2) { 3175 vha->seconds_since_last_heartbeat = 0; 3176 status = 1; 3177 } 3178 } else 3179 vha->seconds_since_last_heartbeat = 0; 3180 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3181 if (status) 3182 ql_dbg(ql_dbg_timer, vha, 0x6004, 3183 "Returning status=%d.\n", status); 3184 return status; 3185 } 3186 3187 /* 3188 * qla82xx_device_state_handler 3189 * Main state handler 3190 * 3191 * Note: 3192 * IDC lock must be held upon entry 3193 * 3194 * Return: 3195 * Success : 0 3196 * Failed : 1 3197 */ 3198 int 3199 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3200 { 3201 uint32_t dev_state; 3202 uint32_t old_dev_state; 3203 int rval = QLA_SUCCESS; 3204 unsigned long dev_init_timeout; 3205 struct qla_hw_data *ha = vha->hw; 3206 int loopcount = 0; 3207 3208 qla82xx_idc_lock(ha); 3209 if (!vha->flags.init_done) { 3210 qla82xx_set_drv_active(vha); 3211 qla82xx_set_idc_version(vha); 3212 } 3213 3214 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3215 old_dev_state = dev_state; 3216 ql_log(ql_log_info, vha, 0x009b, 3217 "Device state is 0x%x = %s.\n", 3218 dev_state, 3219 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3220 3221 /* wait for 30 seconds for device to go ready */ 3222 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3223 3224 while (1) { 3225 3226 if (time_after_eq(jiffies, dev_init_timeout)) { 3227 ql_log(ql_log_fatal, vha, 0x009c, 3228 "Device init failed.\n"); 3229 rval = QLA_FUNCTION_FAILED; 3230 break; 3231 } 3232 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3233 if (old_dev_state != dev_state) { 3234 loopcount = 0; 3235 old_dev_state = dev_state; 3236 } 3237 if (loopcount < 5) { 3238 ql_log(ql_log_info, vha, 0x009d, 3239 "Device state is 0x%x = %s.\n", 3240 dev_state, 3241 dev_state < MAX_STATES ? qdev_state(dev_state) : 3242 "Unknown"); 3243 } 3244 3245 switch (dev_state) { 3246 case QLA8XXX_DEV_READY: 3247 ha->flags.nic_core_reset_owner = 0; 3248 goto rel_lock; 3249 case QLA8XXX_DEV_COLD: 3250 rval = qla82xx_device_bootstrap(vha); 3251 break; 3252 case QLA8XXX_DEV_INITIALIZING: 3253 qla82xx_idc_unlock(ha); 3254 msleep(1000); 3255 qla82xx_idc_lock(ha); 3256 break; 3257 case QLA8XXX_DEV_NEED_RESET: 3258 if (!ql2xdontresethba) 3259 qla82xx_need_reset_handler(vha); 3260 else { 3261 qla82xx_idc_unlock(ha); 3262 msleep(1000); 3263 qla82xx_idc_lock(ha); 3264 } 3265 dev_init_timeout = jiffies + 3266 (ha->fcoe_dev_init_timeout * HZ); 3267 break; 3268 case QLA8XXX_DEV_NEED_QUIESCENT: 3269 qla82xx_need_qsnt_handler(vha); 3270 /* Reset timeout value after quiescence handler */ 3271 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3272 * HZ); 3273 break; 3274 case QLA8XXX_DEV_QUIESCENT: 3275 /* Owner will exit and other will wait for the state 3276 * to get changed 3277 */ 3278 if (ha->flags.quiesce_owner) 3279 goto rel_lock; 3280 3281 qla82xx_idc_unlock(ha); 3282 msleep(1000); 3283 qla82xx_idc_lock(ha); 3284 3285 /* Reset timeout value after quiescence handler */ 3286 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3287 * HZ); 3288 break; 3289 case QLA8XXX_DEV_FAILED: 3290 qla8xxx_dev_failed_handler(vha); 3291 rval = QLA_FUNCTION_FAILED; 3292 goto exit; 3293 default: 3294 qla82xx_idc_unlock(ha); 3295 msleep(1000); 3296 qla82xx_idc_lock(ha); 3297 } 3298 loopcount++; 3299 } 3300 rel_lock: 3301 qla82xx_idc_unlock(ha); 3302 exit: 3303 return rval; 3304 } 3305 3306 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3307 { 3308 uint32_t temp, temp_state, temp_val; 3309 struct qla_hw_data *ha = vha->hw; 3310 3311 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3312 temp_state = qla82xx_get_temp_state(temp); 3313 temp_val = qla82xx_get_temp_val(temp); 3314 3315 if (temp_state == QLA82XX_TEMP_PANIC) { 3316 ql_log(ql_log_warn, vha, 0x600e, 3317 "Device temperature %d degrees C exceeds " 3318 " maximum allowed. Hardware has been shut down.\n", 3319 temp_val); 3320 return 1; 3321 } else if (temp_state == QLA82XX_TEMP_WARN) { 3322 ql_log(ql_log_warn, vha, 0x600f, 3323 "Device temperature %d degrees C exceeds " 3324 "operating range. Immediate action needed.\n", 3325 temp_val); 3326 } 3327 return 0; 3328 } 3329 3330 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3331 { 3332 uint32_t temp; 3333 3334 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3335 return qla82xx_get_temp_val(temp); 3336 } 3337 3338 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3339 { 3340 struct qla_hw_data *ha = vha->hw; 3341 3342 if (ha->flags.mbox_busy) { 3343 ha->flags.mbox_int = 1; 3344 ha->flags.mbox_busy = 0; 3345 ql_log(ql_log_warn, vha, 0x6010, 3346 "Doing premature completion of mbx command.\n"); 3347 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3348 complete(&ha->mbx_intr_comp); 3349 } 3350 } 3351 3352 void qla82xx_watchdog(scsi_qla_host_t *vha) 3353 { 3354 uint32_t dev_state, halt_status; 3355 struct qla_hw_data *ha = vha->hw; 3356 3357 /* don't poll if reset is going on */ 3358 if (!ha->flags.nic_core_reset_hdlr_active) { 3359 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3360 if (qla82xx_check_temp(vha)) { 3361 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3362 ha->flags.isp82xx_fw_hung = 1; 3363 qla82xx_clear_pending_mbx(vha); 3364 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3365 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3366 ql_log(ql_log_warn, vha, 0x6001, 3367 "Adapter reset needed.\n"); 3368 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3369 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3370 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3371 ql_log(ql_log_warn, vha, 0x6002, 3372 "Quiescent needed.\n"); 3373 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3374 } else if (dev_state == QLA8XXX_DEV_FAILED && 3375 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3376 vha->flags.online == 1) { 3377 ql_log(ql_log_warn, vha, 0xb055, 3378 "Adapter state is failed. Offlining.\n"); 3379 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3380 ha->flags.isp82xx_fw_hung = 1; 3381 qla82xx_clear_pending_mbx(vha); 3382 } else { 3383 if (qla82xx_check_fw_alive(vha)) { 3384 ql_dbg(ql_dbg_timer, vha, 0x6011, 3385 "disabling pause transmit on port 0 & 1.\n"); 3386 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3387 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3388 halt_status = qla82xx_rd_32(ha, 3389 QLA82XX_PEG_HALT_STATUS1); 3390 ql_log(ql_log_info, vha, 0x6005, 3391 "dumping hw/fw registers:.\n " 3392 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3393 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3394 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3395 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3396 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3397 qla82xx_rd_32(ha, 3398 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3399 qla82xx_rd_32(ha, 3400 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3401 qla82xx_rd_32(ha, 3402 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3403 qla82xx_rd_32(ha, 3404 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3405 qla82xx_rd_32(ha, 3406 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3407 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3408 ql_log(ql_log_warn, vha, 0xb052, 3409 "Firmware aborted with " 3410 "error code 0x00006700. Device is " 3411 "being reset.\n"); 3412 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3413 set_bit(ISP_UNRECOVERABLE, 3414 &vha->dpc_flags); 3415 } else { 3416 ql_log(ql_log_info, vha, 0x6006, 3417 "Detect abort needed.\n"); 3418 set_bit(ISP_ABORT_NEEDED, 3419 &vha->dpc_flags); 3420 } 3421 ha->flags.isp82xx_fw_hung = 1; 3422 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3423 qla82xx_clear_pending_mbx(vha); 3424 } 3425 } 3426 } 3427 } 3428 3429 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3430 { 3431 int rval = -1; 3432 struct qla_hw_data *ha = vha->hw; 3433 3434 if (IS_QLA82XX(ha)) 3435 rval = qla82xx_device_state_handler(vha); 3436 else if (IS_QLA8044(ha)) { 3437 qla8044_idc_lock(ha); 3438 /* Decide the reset ownership */ 3439 qla83xx_reset_ownership(vha); 3440 qla8044_idc_unlock(ha); 3441 rval = qla8044_device_state_handler(vha); 3442 } 3443 return rval; 3444 } 3445 3446 void 3447 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3448 { 3449 struct qla_hw_data *ha = vha->hw; 3450 uint32_t dev_state = 0; 3451 3452 if (IS_QLA82XX(ha)) 3453 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3454 else if (IS_QLA8044(ha)) 3455 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3456 3457 if (dev_state == QLA8XXX_DEV_READY) { 3458 ql_log(ql_log_info, vha, 0xb02f, 3459 "HW State: NEED RESET\n"); 3460 if (IS_QLA82XX(ha)) { 3461 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3462 QLA8XXX_DEV_NEED_RESET); 3463 ha->flags.nic_core_reset_owner = 1; 3464 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3465 "reset_owner is 0x%x\n", ha->portnum); 3466 } else if (IS_QLA8044(ha)) 3467 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3468 QLA8XXX_DEV_NEED_RESET); 3469 } else 3470 ql_log(ql_log_info, vha, 0xb031, 3471 "Device state is 0x%x = %s.\n", 3472 dev_state, 3473 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3474 } 3475 3476 /* 3477 * qla82xx_abort_isp 3478 * Resets ISP and aborts all outstanding commands. 3479 * 3480 * Input: 3481 * ha = adapter block pointer. 3482 * 3483 * Returns: 3484 * 0 = success 3485 */ 3486 int 3487 qla82xx_abort_isp(scsi_qla_host_t *vha) 3488 { 3489 int rval = -1; 3490 struct qla_hw_data *ha = vha->hw; 3491 3492 if (vha->device_flags & DFLG_DEV_FAILED) { 3493 ql_log(ql_log_warn, vha, 0x8024, 3494 "Device in failed state, exiting.\n"); 3495 return QLA_SUCCESS; 3496 } 3497 ha->flags.nic_core_reset_hdlr_active = 1; 3498 3499 qla82xx_idc_lock(ha); 3500 qla82xx_set_reset_owner(vha); 3501 qla82xx_idc_unlock(ha); 3502 3503 if (IS_QLA82XX(ha)) 3504 rval = qla82xx_device_state_handler(vha); 3505 else if (IS_QLA8044(ha)) { 3506 qla8044_idc_lock(ha); 3507 /* Decide the reset ownership */ 3508 qla83xx_reset_ownership(vha); 3509 qla8044_idc_unlock(ha); 3510 rval = qla8044_device_state_handler(vha); 3511 } 3512 3513 qla82xx_idc_lock(ha); 3514 qla82xx_clear_rst_ready(ha); 3515 qla82xx_idc_unlock(ha); 3516 3517 if (rval == QLA_SUCCESS) { 3518 ha->flags.isp82xx_fw_hung = 0; 3519 ha->flags.nic_core_reset_hdlr_active = 0; 3520 qla82xx_restart_isp(vha); 3521 } 3522 3523 if (rval) { 3524 vha->flags.online = 1; 3525 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3526 if (ha->isp_abort_cnt == 0) { 3527 ql_log(ql_log_warn, vha, 0x8027, 3528 "ISP error recover failed - board " 3529 "disabled.\n"); 3530 /* 3531 * The next call disables the board 3532 * completely. 3533 */ 3534 ha->isp_ops->reset_adapter(vha); 3535 vha->flags.online = 0; 3536 clear_bit(ISP_ABORT_RETRY, 3537 &vha->dpc_flags); 3538 rval = QLA_SUCCESS; 3539 } else { /* schedule another ISP abort */ 3540 ha->isp_abort_cnt--; 3541 ql_log(ql_log_warn, vha, 0x8036, 3542 "ISP abort - retry remaining %d.\n", 3543 ha->isp_abort_cnt); 3544 rval = QLA_FUNCTION_FAILED; 3545 } 3546 } else { 3547 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3548 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3549 "ISP error recovery - retrying (%d) more times.\n", 3550 ha->isp_abort_cnt); 3551 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3552 rval = QLA_FUNCTION_FAILED; 3553 } 3554 } 3555 return rval; 3556 } 3557 3558 /* 3559 * qla82xx_fcoe_ctx_reset 3560 * Perform a quick reset and aborts all outstanding commands. 3561 * This will only perform an FCoE context reset and avoids a full blown 3562 * chip reset. 3563 * 3564 * Input: 3565 * ha = adapter block pointer. 3566 * is_reset_path = flag for identifying the reset path. 3567 * 3568 * Returns: 3569 * 0 = success 3570 */ 3571 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3572 { 3573 int rval = QLA_FUNCTION_FAILED; 3574 3575 if (vha->flags.online) { 3576 /* Abort all outstanding commands, so as to be requeued later */ 3577 qla2x00_abort_isp_cleanup(vha); 3578 } 3579 3580 /* Stop currently executing firmware. 3581 * This will destroy existing FCoE context at the F/W end. 3582 */ 3583 qla2x00_try_to_stop_firmware(vha); 3584 3585 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3586 rval = qla82xx_restart_isp(vha); 3587 3588 return rval; 3589 } 3590 3591 /* 3592 * qla2x00_wait_for_fcoe_ctx_reset 3593 * Wait till the FCoE context is reset. 3594 * 3595 * Note: 3596 * Does context switching here. 3597 * Release SPIN_LOCK (if any) before calling this routine. 3598 * 3599 * Return: 3600 * Success (fcoe_ctx reset is done) : 0 3601 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3602 */ 3603 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3604 { 3605 int status = QLA_FUNCTION_FAILED; 3606 unsigned long wait_reset; 3607 3608 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3609 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3610 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3611 && time_before(jiffies, wait_reset)) { 3612 3613 set_current_state(TASK_UNINTERRUPTIBLE); 3614 schedule_timeout(HZ); 3615 3616 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3617 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3618 status = QLA_SUCCESS; 3619 break; 3620 } 3621 } 3622 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3623 "%s: status=%d.\n", __func__, status); 3624 3625 return status; 3626 } 3627 3628 void 3629 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3630 { 3631 int i, fw_state = 0; 3632 unsigned long flags; 3633 struct qla_hw_data *ha = vha->hw; 3634 3635 /* Check if 82XX firmware is alive or not 3636 * We may have arrived here from NEED_RESET 3637 * detection only 3638 */ 3639 if (!ha->flags.isp82xx_fw_hung) { 3640 for (i = 0; i < 2; i++) { 3641 msleep(1000); 3642 if (IS_QLA82XX(ha)) 3643 fw_state = qla82xx_check_fw_alive(vha); 3644 else if (IS_QLA8044(ha)) 3645 fw_state = qla8044_check_fw_alive(vha); 3646 if (fw_state) { 3647 ha->flags.isp82xx_fw_hung = 1; 3648 qla82xx_clear_pending_mbx(vha); 3649 break; 3650 } 3651 } 3652 } 3653 ql_dbg(ql_dbg_init, vha, 0x00b0, 3654 "Entered %s fw_hung=%d.\n", 3655 __func__, ha->flags.isp82xx_fw_hung); 3656 3657 /* Abort all commands gracefully if fw NOT hung */ 3658 if (!ha->flags.isp82xx_fw_hung) { 3659 int cnt, que; 3660 srb_t *sp; 3661 struct req_que *req; 3662 3663 spin_lock_irqsave(&ha->hardware_lock, flags); 3664 for (que = 0; que < ha->max_req_queues; que++) { 3665 req = ha->req_q_map[que]; 3666 if (!req) 3667 continue; 3668 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3669 sp = req->outstanding_cmds[cnt]; 3670 if (sp) { 3671 if (!sp->u.scmd.ctx || 3672 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3673 spin_unlock_irqrestore( 3674 &ha->hardware_lock, flags); 3675 if (ha->isp_ops->abort_command(sp)) { 3676 ql_log(ql_log_info, vha, 3677 0x00b1, 3678 "mbx abort failed.\n"); 3679 } else { 3680 ql_log(ql_log_info, vha, 3681 0x00b2, 3682 "mbx abort success.\n"); 3683 } 3684 spin_lock_irqsave(&ha->hardware_lock, flags); 3685 } 3686 } 3687 } 3688 } 3689 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3690 3691 /* Wait for pending cmds (physical and virtual) to complete */ 3692 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3693 WAIT_HOST) == QLA_SUCCESS) { 3694 ql_dbg(ql_dbg_init, vha, 0x00b3, 3695 "Done wait for " 3696 "pending commands.\n"); 3697 } 3698 } 3699 } 3700 3701 /* Minidump related functions */ 3702 static int 3703 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3704 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3705 { 3706 struct qla_hw_data *ha = vha->hw; 3707 struct qla82xx_md_entry_crb *crb_entry; 3708 uint32_t read_value, opcode, poll_time; 3709 uint32_t addr, index, crb_addr; 3710 unsigned long wtime; 3711 struct qla82xx_md_template_hdr *tmplt_hdr; 3712 uint32_t rval = QLA_SUCCESS; 3713 int i; 3714 3715 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3716 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3717 crb_addr = crb_entry->addr; 3718 3719 for (i = 0; i < crb_entry->op_count; i++) { 3720 opcode = crb_entry->crb_ctrl.opcode; 3721 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3722 qla82xx_md_rw_32(ha, crb_addr, 3723 crb_entry->value_1, 1); 3724 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3725 } 3726 3727 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3728 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3729 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3730 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3731 } 3732 3733 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3734 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3735 read_value &= crb_entry->value_2; 3736 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3737 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3738 read_value |= crb_entry->value_3; 3739 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3740 } 3741 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3742 } 3743 3744 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3745 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3746 read_value |= crb_entry->value_3; 3747 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3748 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3749 } 3750 3751 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3752 poll_time = crb_entry->crb_strd.poll_timeout; 3753 wtime = jiffies + poll_time; 3754 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3755 3756 do { 3757 if ((read_value & crb_entry->value_2) 3758 == crb_entry->value_1) 3759 break; 3760 else if (time_after_eq(jiffies, wtime)) { 3761 /* capturing dump failed */ 3762 rval = QLA_FUNCTION_FAILED; 3763 break; 3764 } else 3765 read_value = qla82xx_md_rw_32(ha, 3766 crb_addr, 0, 0); 3767 } while (1); 3768 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3769 } 3770 3771 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3772 if (crb_entry->crb_strd.state_index_a) { 3773 index = crb_entry->crb_strd.state_index_a; 3774 addr = tmplt_hdr->saved_state_array[index]; 3775 } else 3776 addr = crb_addr; 3777 3778 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3779 index = crb_entry->crb_ctrl.state_index_v; 3780 tmplt_hdr->saved_state_array[index] = read_value; 3781 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3782 } 3783 3784 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3785 if (crb_entry->crb_strd.state_index_a) { 3786 index = crb_entry->crb_strd.state_index_a; 3787 addr = tmplt_hdr->saved_state_array[index]; 3788 } else 3789 addr = crb_addr; 3790 3791 if (crb_entry->crb_ctrl.state_index_v) { 3792 index = crb_entry->crb_ctrl.state_index_v; 3793 read_value = 3794 tmplt_hdr->saved_state_array[index]; 3795 } else 3796 read_value = crb_entry->value_1; 3797 3798 qla82xx_md_rw_32(ha, addr, read_value, 1); 3799 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3800 } 3801 3802 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3803 index = crb_entry->crb_ctrl.state_index_v; 3804 read_value = tmplt_hdr->saved_state_array[index]; 3805 read_value <<= crb_entry->crb_ctrl.shl; 3806 read_value >>= crb_entry->crb_ctrl.shr; 3807 if (crb_entry->value_2) 3808 read_value &= crb_entry->value_2; 3809 read_value |= crb_entry->value_3; 3810 read_value += crb_entry->value_1; 3811 tmplt_hdr->saved_state_array[index] = read_value; 3812 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3813 } 3814 crb_addr += crb_entry->crb_strd.addr_stride; 3815 } 3816 return rval; 3817 } 3818 3819 static void 3820 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3821 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3822 { 3823 struct qla_hw_data *ha = vha->hw; 3824 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3825 struct qla82xx_md_entry_rdocm *ocm_hdr; 3826 uint32_t *data_ptr = *d_ptr; 3827 3828 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3829 r_addr = ocm_hdr->read_addr; 3830 r_stride = ocm_hdr->read_addr_stride; 3831 loop_cnt = ocm_hdr->op_count; 3832 3833 for (i = 0; i < loop_cnt; i++) { 3834 r_value = RD_REG_DWORD((void __iomem *) 3835 (r_addr + ha->nx_pcibase)); 3836 *data_ptr++ = cpu_to_le32(r_value); 3837 r_addr += r_stride; 3838 } 3839 *d_ptr = data_ptr; 3840 } 3841 3842 static void 3843 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3844 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3845 { 3846 struct qla_hw_data *ha = vha->hw; 3847 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3848 struct qla82xx_md_entry_mux *mux_hdr; 3849 uint32_t *data_ptr = *d_ptr; 3850 3851 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3852 r_addr = mux_hdr->read_addr; 3853 s_addr = mux_hdr->select_addr; 3854 s_stride = mux_hdr->select_value_stride; 3855 s_value = mux_hdr->select_value; 3856 loop_cnt = mux_hdr->op_count; 3857 3858 for (i = 0; i < loop_cnt; i++) { 3859 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3860 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3861 *data_ptr++ = cpu_to_le32(s_value); 3862 *data_ptr++ = cpu_to_le32(r_value); 3863 s_value += s_stride; 3864 } 3865 *d_ptr = data_ptr; 3866 } 3867 3868 static void 3869 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3870 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3871 { 3872 struct qla_hw_data *ha = vha->hw; 3873 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3874 struct qla82xx_md_entry_crb *crb_hdr; 3875 uint32_t *data_ptr = *d_ptr; 3876 3877 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3878 r_addr = crb_hdr->addr; 3879 r_stride = crb_hdr->crb_strd.addr_stride; 3880 loop_cnt = crb_hdr->op_count; 3881 3882 for (i = 0; i < loop_cnt; i++) { 3883 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3884 *data_ptr++ = cpu_to_le32(r_addr); 3885 *data_ptr++ = cpu_to_le32(r_value); 3886 r_addr += r_stride; 3887 } 3888 *d_ptr = data_ptr; 3889 } 3890 3891 static int 3892 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3893 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3894 { 3895 struct qla_hw_data *ha = vha->hw; 3896 uint32_t addr, r_addr, c_addr, t_r_addr; 3897 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3898 unsigned long p_wait, w_time, p_mask; 3899 uint32_t c_value_w, c_value_r; 3900 struct qla82xx_md_entry_cache *cache_hdr; 3901 int rval = QLA_FUNCTION_FAILED; 3902 uint32_t *data_ptr = *d_ptr; 3903 3904 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3905 loop_count = cache_hdr->op_count; 3906 r_addr = cache_hdr->read_addr; 3907 c_addr = cache_hdr->control_addr; 3908 c_value_w = cache_hdr->cache_ctrl.write_value; 3909 3910 t_r_addr = cache_hdr->tag_reg_addr; 3911 t_value = cache_hdr->addr_ctrl.init_tag_value; 3912 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3913 p_wait = cache_hdr->cache_ctrl.poll_wait; 3914 p_mask = cache_hdr->cache_ctrl.poll_mask; 3915 3916 for (i = 0; i < loop_count; i++) { 3917 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3918 if (c_value_w) 3919 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3920 3921 if (p_mask) { 3922 w_time = jiffies + p_wait; 3923 do { 3924 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3925 if ((c_value_r & p_mask) == 0) 3926 break; 3927 else if (time_after_eq(jiffies, w_time)) { 3928 /* capturing dump failed */ 3929 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3930 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3931 "w_time: 0x%lx\n", 3932 c_value_r, p_mask, w_time); 3933 return rval; 3934 } 3935 } while (1); 3936 } 3937 3938 addr = r_addr; 3939 for (k = 0; k < r_cnt; k++) { 3940 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3941 *data_ptr++ = cpu_to_le32(r_value); 3942 addr += cache_hdr->read_ctrl.read_addr_stride; 3943 } 3944 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3945 } 3946 *d_ptr = data_ptr; 3947 return QLA_SUCCESS; 3948 } 3949 3950 static void 3951 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3952 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3953 { 3954 struct qla_hw_data *ha = vha->hw; 3955 uint32_t addr, r_addr, c_addr, t_r_addr; 3956 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3957 uint32_t c_value_w; 3958 struct qla82xx_md_entry_cache *cache_hdr; 3959 uint32_t *data_ptr = *d_ptr; 3960 3961 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3962 loop_count = cache_hdr->op_count; 3963 r_addr = cache_hdr->read_addr; 3964 c_addr = cache_hdr->control_addr; 3965 c_value_w = cache_hdr->cache_ctrl.write_value; 3966 3967 t_r_addr = cache_hdr->tag_reg_addr; 3968 t_value = cache_hdr->addr_ctrl.init_tag_value; 3969 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3970 3971 for (i = 0; i < loop_count; i++) { 3972 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3973 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3974 addr = r_addr; 3975 for (k = 0; k < r_cnt; k++) { 3976 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3977 *data_ptr++ = cpu_to_le32(r_value); 3978 addr += cache_hdr->read_ctrl.read_addr_stride; 3979 } 3980 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3981 } 3982 *d_ptr = data_ptr; 3983 } 3984 3985 static void 3986 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3987 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3988 { 3989 struct qla_hw_data *ha = vha->hw; 3990 uint32_t s_addr, r_addr; 3991 uint32_t r_stride, r_value, r_cnt, qid = 0; 3992 uint32_t i, k, loop_cnt; 3993 struct qla82xx_md_entry_queue *q_hdr; 3994 uint32_t *data_ptr = *d_ptr; 3995 3996 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3997 s_addr = q_hdr->select_addr; 3998 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3999 r_stride = q_hdr->rd_strd.read_addr_stride; 4000 loop_cnt = q_hdr->op_count; 4001 4002 for (i = 0; i < loop_cnt; i++) { 4003 qla82xx_md_rw_32(ha, s_addr, qid, 1); 4004 r_addr = q_hdr->read_addr; 4005 for (k = 0; k < r_cnt; k++) { 4006 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4007 *data_ptr++ = cpu_to_le32(r_value); 4008 r_addr += r_stride; 4009 } 4010 qid += q_hdr->q_strd.queue_id_stride; 4011 } 4012 *d_ptr = data_ptr; 4013 } 4014 4015 static void 4016 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 4017 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4018 { 4019 struct qla_hw_data *ha = vha->hw; 4020 uint32_t r_addr, r_value; 4021 uint32_t i, loop_cnt; 4022 struct qla82xx_md_entry_rdrom *rom_hdr; 4023 uint32_t *data_ptr = *d_ptr; 4024 4025 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4026 r_addr = rom_hdr->read_addr; 4027 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4028 4029 for (i = 0; i < loop_cnt; i++) { 4030 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4031 (r_addr & 0xFFFF0000), 1); 4032 r_value = qla82xx_md_rw_32(ha, 4033 MD_DIRECT_ROM_READ_BASE + 4034 (r_addr & 0x0000FFFF), 0, 0); 4035 *data_ptr++ = cpu_to_le32(r_value); 4036 r_addr += sizeof(uint32_t); 4037 } 4038 *d_ptr = data_ptr; 4039 } 4040 4041 static int 4042 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4043 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4044 { 4045 struct qla_hw_data *ha = vha->hw; 4046 uint32_t r_addr, r_value, r_data; 4047 uint32_t i, j, loop_cnt; 4048 struct qla82xx_md_entry_rdmem *m_hdr; 4049 unsigned long flags; 4050 int rval = QLA_FUNCTION_FAILED; 4051 uint32_t *data_ptr = *d_ptr; 4052 4053 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4054 r_addr = m_hdr->read_addr; 4055 loop_cnt = m_hdr->read_data_size/16; 4056 4057 if (r_addr & 0xf) { 4058 ql_log(ql_log_warn, vha, 0xb033, 4059 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4060 return rval; 4061 } 4062 4063 if (m_hdr->read_data_size % 16) { 4064 ql_log(ql_log_warn, vha, 0xb034, 4065 "Read data[0x%x] not multiple of 16 bytes\n", 4066 m_hdr->read_data_size); 4067 return rval; 4068 } 4069 4070 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4071 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4072 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4073 4074 write_lock_irqsave(&ha->hw_lock, flags); 4075 for (i = 0; i < loop_cnt; i++) { 4076 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4077 r_value = 0; 4078 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4079 r_value = MIU_TA_CTL_ENABLE; 4080 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4081 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4082 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4083 4084 for (j = 0; j < MAX_CTL_CHECK; j++) { 4085 r_value = qla82xx_md_rw_32(ha, 4086 MD_MIU_TEST_AGT_CTRL, 0, 0); 4087 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4088 break; 4089 } 4090 4091 if (j >= MAX_CTL_CHECK) { 4092 printk_ratelimited(KERN_ERR 4093 "failed to read through agent\n"); 4094 write_unlock_irqrestore(&ha->hw_lock, flags); 4095 return rval; 4096 } 4097 4098 for (j = 0; j < 4; j++) { 4099 r_data = qla82xx_md_rw_32(ha, 4100 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4101 *data_ptr++ = cpu_to_le32(r_data); 4102 } 4103 r_addr += 16; 4104 } 4105 write_unlock_irqrestore(&ha->hw_lock, flags); 4106 *d_ptr = data_ptr; 4107 return QLA_SUCCESS; 4108 } 4109 4110 int 4111 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4112 { 4113 struct qla_hw_data *ha = vha->hw; 4114 uint64_t chksum = 0; 4115 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4116 int count = ha->md_template_size/sizeof(uint32_t); 4117 4118 while (count-- > 0) 4119 chksum += *d_ptr++; 4120 while (chksum >> 32) 4121 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4122 return ~chksum; 4123 } 4124 4125 static void 4126 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4127 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4128 { 4129 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4130 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4131 "Skipping entry[%d]: " 4132 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4133 index, entry_hdr->entry_type, 4134 entry_hdr->d_ctrl.entry_capture_mask); 4135 } 4136 4137 int 4138 qla82xx_md_collect(scsi_qla_host_t *vha) 4139 { 4140 struct qla_hw_data *ha = vha->hw; 4141 int no_entry_hdr = 0; 4142 qla82xx_md_entry_hdr_t *entry_hdr; 4143 struct qla82xx_md_template_hdr *tmplt_hdr; 4144 uint32_t *data_ptr; 4145 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4146 int i = 0, rval = QLA_FUNCTION_FAILED; 4147 4148 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4149 data_ptr = (uint32_t *)ha->md_dump; 4150 4151 if (ha->fw_dumped) { 4152 ql_log(ql_log_warn, vha, 0xb037, 4153 "Firmware has been previously dumped (%p) " 4154 "-- ignoring request.\n", ha->fw_dump); 4155 goto md_failed; 4156 } 4157 4158 ha->fw_dumped = 0; 4159 4160 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4161 ql_log(ql_log_warn, vha, 0xb038, 4162 "Memory not allocated for minidump capture\n"); 4163 goto md_failed; 4164 } 4165 4166 if (ha->flags.isp82xx_no_md_cap) { 4167 ql_log(ql_log_warn, vha, 0xb054, 4168 "Forced reset from application, " 4169 "ignore minidump capture\n"); 4170 ha->flags.isp82xx_no_md_cap = 0; 4171 goto md_failed; 4172 } 4173 4174 if (qla82xx_validate_template_chksum(vha)) { 4175 ql_log(ql_log_info, vha, 0xb039, 4176 "Template checksum validation error\n"); 4177 goto md_failed; 4178 } 4179 4180 no_entry_hdr = tmplt_hdr->num_of_entries; 4181 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4182 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4183 4184 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4185 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4186 4187 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4188 4189 /* Validate whether required debug level is set */ 4190 if ((f_capture_mask & 0x3) != 0x3) { 4191 ql_log(ql_log_warn, vha, 0xb03c, 4192 "Minimum required capture mask[0x%x] level not set\n", 4193 f_capture_mask); 4194 goto md_failed; 4195 } 4196 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4197 4198 tmplt_hdr->driver_info[0] = vha->host_no; 4199 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4200 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4201 QLA_DRIVER_BETA_VER; 4202 4203 total_data_size = ha->md_dump_size; 4204 4205 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4206 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4207 4208 /* Check whether template obtained is valid */ 4209 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4210 ql_log(ql_log_warn, vha, 0xb04e, 4211 "Bad template header entry type: 0x%x obtained\n", 4212 tmplt_hdr->entry_type); 4213 goto md_failed; 4214 } 4215 4216 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4217 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4218 4219 /* Walk through the entry headers */ 4220 for (i = 0; i < no_entry_hdr; i++) { 4221 4222 if (data_collected > total_data_size) { 4223 ql_log(ql_log_warn, vha, 0xb03e, 4224 "More MiniDump data collected: [0x%x]\n", 4225 data_collected); 4226 goto md_failed; 4227 } 4228 4229 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4230 ql2xmdcapmask)) { 4231 entry_hdr->d_ctrl.driver_flags |= 4232 QLA82XX_DBG_SKIPPED_FLAG; 4233 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4234 "Skipping entry[%d]: " 4235 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4236 i, entry_hdr->entry_type, 4237 entry_hdr->d_ctrl.entry_capture_mask); 4238 goto skip_nxt_entry; 4239 } 4240 4241 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4242 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4243 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4244 __func__, i, data_ptr, entry_hdr, 4245 entry_hdr->entry_type, 4246 entry_hdr->d_ctrl.entry_capture_mask); 4247 4248 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4249 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4250 data_collected, (ha->md_dump_size - data_collected)); 4251 4252 /* Decode the entry type and take 4253 * required action to capture debug data */ 4254 switch (entry_hdr->entry_type) { 4255 case QLA82XX_RDEND: 4256 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4257 break; 4258 case QLA82XX_CNTRL: 4259 rval = qla82xx_minidump_process_control(vha, 4260 entry_hdr, &data_ptr); 4261 if (rval != QLA_SUCCESS) { 4262 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4263 goto md_failed; 4264 } 4265 break; 4266 case QLA82XX_RDCRB: 4267 qla82xx_minidump_process_rdcrb(vha, 4268 entry_hdr, &data_ptr); 4269 break; 4270 case QLA82XX_RDMEM: 4271 rval = qla82xx_minidump_process_rdmem(vha, 4272 entry_hdr, &data_ptr); 4273 if (rval != QLA_SUCCESS) { 4274 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4275 goto md_failed; 4276 } 4277 break; 4278 case QLA82XX_BOARD: 4279 case QLA82XX_RDROM: 4280 qla82xx_minidump_process_rdrom(vha, 4281 entry_hdr, &data_ptr); 4282 break; 4283 case QLA82XX_L2DTG: 4284 case QLA82XX_L2ITG: 4285 case QLA82XX_L2DAT: 4286 case QLA82XX_L2INS: 4287 rval = qla82xx_minidump_process_l2tag(vha, 4288 entry_hdr, &data_ptr); 4289 if (rval != QLA_SUCCESS) { 4290 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4291 goto md_failed; 4292 } 4293 break; 4294 case QLA82XX_L1DAT: 4295 case QLA82XX_L1INS: 4296 qla82xx_minidump_process_l1cache(vha, 4297 entry_hdr, &data_ptr); 4298 break; 4299 case QLA82XX_RDOCM: 4300 qla82xx_minidump_process_rdocm(vha, 4301 entry_hdr, &data_ptr); 4302 break; 4303 case QLA82XX_RDMUX: 4304 qla82xx_minidump_process_rdmux(vha, 4305 entry_hdr, &data_ptr); 4306 break; 4307 case QLA82XX_QUEUE: 4308 qla82xx_minidump_process_queue(vha, 4309 entry_hdr, &data_ptr); 4310 break; 4311 case QLA82XX_RDNOP: 4312 default: 4313 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4314 break; 4315 } 4316 4317 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4318 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4319 4320 data_collected = (uint8_t *)data_ptr - 4321 (uint8_t *)ha->md_dump; 4322 skip_nxt_entry: 4323 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4324 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4325 } 4326 4327 if (data_collected != total_data_size) { 4328 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4329 "MiniDump data mismatch: Data collected: [0x%x]," 4330 "total_data_size:[0x%x]\n", 4331 data_collected, total_data_size); 4332 goto md_failed; 4333 } 4334 4335 ql_log(ql_log_info, vha, 0xb044, 4336 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4337 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4338 ha->fw_dumped = 1; 4339 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4340 4341 md_failed: 4342 return rval; 4343 } 4344 4345 int 4346 qla82xx_md_alloc(scsi_qla_host_t *vha) 4347 { 4348 struct qla_hw_data *ha = vha->hw; 4349 int i, k; 4350 struct qla82xx_md_template_hdr *tmplt_hdr; 4351 4352 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4353 4354 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4355 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4356 ql_log(ql_log_info, vha, 0xb045, 4357 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4358 ql2xmdcapmask); 4359 } 4360 4361 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4362 if (i & ql2xmdcapmask) 4363 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4364 } 4365 4366 if (ha->md_dump) { 4367 ql_log(ql_log_warn, vha, 0xb046, 4368 "Firmware dump previously allocated.\n"); 4369 return 1; 4370 } 4371 4372 ha->md_dump = vmalloc(ha->md_dump_size); 4373 if (ha->md_dump == NULL) { 4374 ql_log(ql_log_warn, vha, 0xb047, 4375 "Unable to allocate memory for Minidump size " 4376 "(0x%x).\n", ha->md_dump_size); 4377 return 1; 4378 } 4379 return 0; 4380 } 4381 4382 void 4383 qla82xx_md_free(scsi_qla_host_t *vha) 4384 { 4385 struct qla_hw_data *ha = vha->hw; 4386 4387 /* Release the template header allocated */ 4388 if (ha->md_tmplt_hdr) { 4389 ql_log(ql_log_info, vha, 0xb048, 4390 "Free MiniDump template: %p, size (%d KB)\n", 4391 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4392 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4393 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4394 ha->md_tmplt_hdr = NULL; 4395 } 4396 4397 /* Release the template data buffer allocated */ 4398 if (ha->md_dump) { 4399 ql_log(ql_log_info, vha, 0xb049, 4400 "Free MiniDump memory: %p, size (%d KB)\n", 4401 ha->md_dump, ha->md_dump_size / 1024); 4402 vfree(ha->md_dump); 4403 ha->md_dump_size = 0; 4404 ha->md_dump = NULL; 4405 } 4406 } 4407 4408 void 4409 qla82xx_md_prep(scsi_qla_host_t *vha) 4410 { 4411 struct qla_hw_data *ha = vha->hw; 4412 int rval; 4413 4414 /* Get Minidump template size */ 4415 rval = qla82xx_md_get_template_size(vha); 4416 if (rval == QLA_SUCCESS) { 4417 ql_log(ql_log_info, vha, 0xb04a, 4418 "MiniDump Template size obtained (%d KB)\n", 4419 ha->md_template_size / 1024); 4420 4421 /* Get Minidump template */ 4422 if (IS_QLA8044(ha)) 4423 rval = qla8044_md_get_template(vha); 4424 else 4425 rval = qla82xx_md_get_template(vha); 4426 4427 if (rval == QLA_SUCCESS) { 4428 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4429 "MiniDump Template obtained\n"); 4430 4431 /* Allocate memory for minidump */ 4432 rval = qla82xx_md_alloc(vha); 4433 if (rval == QLA_SUCCESS) 4434 ql_log(ql_log_info, vha, 0xb04c, 4435 "MiniDump memory allocated (%d KB)\n", 4436 ha->md_dump_size / 1024); 4437 else { 4438 ql_log(ql_log_info, vha, 0xb04d, 4439 "Free MiniDump template: %p, size: (%d KB)\n", 4440 ha->md_tmplt_hdr, 4441 ha->md_template_size / 1024); 4442 dma_free_coherent(&ha->pdev->dev, 4443 ha->md_template_size, 4444 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4445 ha->md_tmplt_hdr = NULL; 4446 } 4447 4448 } 4449 } 4450 } 4451 4452 int 4453 qla82xx_beacon_on(struct scsi_qla_host *vha) 4454 { 4455 4456 int rval; 4457 struct qla_hw_data *ha = vha->hw; 4458 qla82xx_idc_lock(ha); 4459 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4460 4461 if (rval) { 4462 ql_log(ql_log_warn, vha, 0xb050, 4463 "mbx set led config failed in %s\n", __func__); 4464 goto exit; 4465 } 4466 ha->beacon_blink_led = 1; 4467 exit: 4468 qla82xx_idc_unlock(ha); 4469 return rval; 4470 } 4471 4472 int 4473 qla82xx_beacon_off(struct scsi_qla_host *vha) 4474 { 4475 4476 int rval; 4477 struct qla_hw_data *ha = vha->hw; 4478 qla82xx_idc_lock(ha); 4479 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4480 4481 if (rval) { 4482 ql_log(ql_log_warn, vha, 0xb051, 4483 "mbx set led config failed in %s\n", __func__); 4484 goto exit; 4485 } 4486 ha->beacon_blink_led = 0; 4487 exit: 4488 qla82xx_idc_unlock(ha); 4489 return rval; 4490 } 4491