1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/io-64-nonatomic-lo-hi.h> 10 #include <linux/pci.h> 11 #include <linux/ratelimit.h> 12 #include <linux/vmalloc.h> 13 #include <scsi/scsi_tcq.h> 14 15 #define MASK(n) ((1ULL<<(n))-1) 16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 17 ((addr >> 25) & 0x3ff)) 18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 19 ((addr >> 25) & 0x3ff)) 20 #define MS_WIN(addr) (addr & 0x0ffc0000) 21 #define QLA82XX_PCI_MN_2M (0) 22 #define QLA82XX_PCI_MS_2M (0x80000) 23 #define QLA82XX_PCI_OCM0_2M (0xc0000) 24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 26 #define BLOCK_PROTECT_BITS 0x0F 27 28 /* CRB window related */ 29 #define CRB_BLK(off) ((off >> 20) & 0x3f) 30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 31 #define CRB_WINDOW_2M (0x130060) 32 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 34 ((off) & 0xf0000)) 35 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 36 #define CRB_INDIRECT_2M (0x1e0000UL) 37 38 #define MAX_CRB_XFORM 60 39 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 40 static int qla82xx_crb_table_initialized; 41 42 #define qla82xx_crb_addr_transform(name) \ 43 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 44 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 45 46 const int MD_MIU_TEST_AGT_RDDATA[] = { 47 0x410000A8, 0x410000AC, 48 0x410000B8, 0x410000BC 49 }; 50 51 static void qla82xx_crb_addr_transform_setup(void) 52 { 53 qla82xx_crb_addr_transform(XDMA); 54 qla82xx_crb_addr_transform(TIMR); 55 qla82xx_crb_addr_transform(SRE); 56 qla82xx_crb_addr_transform(SQN3); 57 qla82xx_crb_addr_transform(SQN2); 58 qla82xx_crb_addr_transform(SQN1); 59 qla82xx_crb_addr_transform(SQN0); 60 qla82xx_crb_addr_transform(SQS3); 61 qla82xx_crb_addr_transform(SQS2); 62 qla82xx_crb_addr_transform(SQS1); 63 qla82xx_crb_addr_transform(SQS0); 64 qla82xx_crb_addr_transform(RPMX7); 65 qla82xx_crb_addr_transform(RPMX6); 66 qla82xx_crb_addr_transform(RPMX5); 67 qla82xx_crb_addr_transform(RPMX4); 68 qla82xx_crb_addr_transform(RPMX3); 69 qla82xx_crb_addr_transform(RPMX2); 70 qla82xx_crb_addr_transform(RPMX1); 71 qla82xx_crb_addr_transform(RPMX0); 72 qla82xx_crb_addr_transform(ROMUSB); 73 qla82xx_crb_addr_transform(SN); 74 qla82xx_crb_addr_transform(QMN); 75 qla82xx_crb_addr_transform(QMS); 76 qla82xx_crb_addr_transform(PGNI); 77 qla82xx_crb_addr_transform(PGND); 78 qla82xx_crb_addr_transform(PGN3); 79 qla82xx_crb_addr_transform(PGN2); 80 qla82xx_crb_addr_transform(PGN1); 81 qla82xx_crb_addr_transform(PGN0); 82 qla82xx_crb_addr_transform(PGSI); 83 qla82xx_crb_addr_transform(PGSD); 84 qla82xx_crb_addr_transform(PGS3); 85 qla82xx_crb_addr_transform(PGS2); 86 qla82xx_crb_addr_transform(PGS1); 87 qla82xx_crb_addr_transform(PGS0); 88 qla82xx_crb_addr_transform(PS); 89 qla82xx_crb_addr_transform(PH); 90 qla82xx_crb_addr_transform(NIU); 91 qla82xx_crb_addr_transform(I2Q); 92 qla82xx_crb_addr_transform(EG); 93 qla82xx_crb_addr_transform(MN); 94 qla82xx_crb_addr_transform(MS); 95 qla82xx_crb_addr_transform(CAS2); 96 qla82xx_crb_addr_transform(CAS1); 97 qla82xx_crb_addr_transform(CAS0); 98 qla82xx_crb_addr_transform(CAM); 99 qla82xx_crb_addr_transform(C2C1); 100 qla82xx_crb_addr_transform(C2C0); 101 qla82xx_crb_addr_transform(SMB); 102 qla82xx_crb_addr_transform(OCM0); 103 /* 104 * Used only in P3 just define it for P2 also. 105 */ 106 qla82xx_crb_addr_transform(I2C0); 107 108 qla82xx_crb_table_initialized = 1; 109 } 110 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 112 {{{0, 0, 0, 0} } }, 113 {{{1, 0x0100000, 0x0102000, 0x120000}, 114 {1, 0x0110000, 0x0120000, 0x130000}, 115 {1, 0x0120000, 0x0122000, 0x124000}, 116 {1, 0x0130000, 0x0132000, 0x126000}, 117 {1, 0x0140000, 0x0142000, 0x128000}, 118 {1, 0x0150000, 0x0152000, 0x12a000}, 119 {1, 0x0160000, 0x0170000, 0x110000}, 120 {1, 0x0170000, 0x0172000, 0x12e000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {1, 0x01e0000, 0x01e0800, 0x122000}, 128 {0, 0x0000000, 0x0000000, 0x000000} } } , 129 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 130 {{{0, 0, 0, 0} } }, 131 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 132 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 133 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 134 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 135 {{{1, 0x0800000, 0x0802000, 0x170000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 151 {{{1, 0x0900000, 0x0902000, 0x174000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 167 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 183 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {0, 0x0000000, 0x0000000, 0x000000}, 198 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 199 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 200 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 201 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 202 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 203 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 204 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 205 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 206 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 207 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 208 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 209 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 210 {{{0, 0, 0, 0} } }, 211 {{{0, 0, 0, 0} } }, 212 {{{0, 0, 0, 0} } }, 213 {{{0, 0, 0, 0} } }, 214 {{{0, 0, 0, 0} } }, 215 {{{0, 0, 0, 0} } }, 216 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 217 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 218 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 219 {{{0} } }, 220 {{{1, 0x2100000, 0x2102000, 0x120000}, 221 {1, 0x2110000, 0x2120000, 0x130000}, 222 {1, 0x2120000, 0x2122000, 0x124000}, 223 {1, 0x2130000, 0x2132000, 0x126000}, 224 {1, 0x2140000, 0x2142000, 0x128000}, 225 {1, 0x2150000, 0x2152000, 0x12a000}, 226 {1, 0x2160000, 0x2170000, 0x110000}, 227 {1, 0x2170000, 0x2172000, 0x12e000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000}, 235 {0, 0x0000000, 0x0000000, 0x000000} } }, 236 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 237 {{{0} } }, 238 {{{0} } }, 239 {{{0} } }, 240 {{{0} } }, 241 {{{0} } }, 242 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 243 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 244 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 245 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 246 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 247 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 248 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 249 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 250 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 251 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 252 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 253 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 254 {{{0} } }, 255 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 256 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 257 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 258 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 259 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 260 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 261 {{{0} } }, 262 {{{0} } }, 263 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 264 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 265 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 266 }; 267 268 /* 269 * top 12 bits of crb internal address (hub, agent) 270 */ 271 static unsigned qla82xx_crb_hub_agt[64] = { 272 0, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 276 0, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 299 0, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 301 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 302 0, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 304 0, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 307 0, 308 0, 309 0, 310 0, 311 0, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 313 0, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 324 0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 329 0, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 333 0, 334 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 335 0, 336 }; 337 338 /* Device states */ 339 static char *q_dev_state[] = { 340 "Unknown", 341 "Cold", 342 "Initializing", 343 "Ready", 344 "Need Reset", 345 "Need Quiescent", 346 "Failed", 347 "Quiescent", 348 }; 349 350 char *qdev_state(uint32_t dev_state) 351 { 352 return q_dev_state[dev_state]; 353 } 354 355 /* 356 * In: 'off_in' is offset from CRB space in 128M pci map 357 * Out: 'off_out' is 2M pci map addr 358 * side effect: lock crb window 359 */ 360 static void 361 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 362 void __iomem **off_out) 363 { 364 u32 win_read; 365 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 366 367 ha->crb_win = CRB_HI(off_in); 368 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 369 370 /* Read back value to make sure write has gone through before trying 371 * to use it. 372 */ 373 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 374 if (win_read != ha->crb_win) { 375 ql_dbg(ql_dbg_p3p, vha, 0xb000, 376 "%s: Written crbwin (0x%x) " 377 "!= Read crbwin (0x%x), off=0x%lx.\n", 378 __func__, ha->crb_win, win_read, off_in); 379 } 380 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 381 } 382 383 static int 384 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 385 void __iomem **off_out) 386 { 387 struct crb_128M_2M_sub_block_map *m; 388 389 if (off_in >= QLA82XX_CRB_MAX) 390 return -1; 391 392 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 393 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 394 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 395 return 0; 396 } 397 398 if (off_in < QLA82XX_PCI_CRBSPACE) 399 return -1; 400 401 off_in -= QLA82XX_PCI_CRBSPACE; 402 403 /* Try direct map */ 404 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 405 406 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 407 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 408 return 0; 409 } 410 /* Not in direct map, use crb window */ 411 *off_out = (void __iomem *)off_in; 412 return 1; 413 } 414 415 #define CRB_WIN_LOCK_TIMEOUT 100000000 416 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 417 { 418 int done = 0, timeout = 0; 419 420 while (!done) { 421 /* acquire semaphore3 from PCI HW block */ 422 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 423 if (done == 1) 424 break; 425 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 426 return -1; 427 timeout++; 428 } 429 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 430 return 0; 431 } 432 433 int 434 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 435 { 436 void __iomem *off; 437 unsigned long flags = 0; 438 int rv; 439 440 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 441 442 BUG_ON(rv == -1); 443 444 if (rv == 1) { 445 #ifndef __CHECKER__ 446 write_lock_irqsave(&ha->hw_lock, flags); 447 #endif 448 qla82xx_crb_win_lock(ha); 449 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 450 } 451 452 writel(data, (void __iomem *)off); 453 454 if (rv == 1) { 455 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 456 #ifndef __CHECKER__ 457 write_unlock_irqrestore(&ha->hw_lock, flags); 458 #endif 459 } 460 return 0; 461 } 462 463 int 464 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 465 { 466 void __iomem *off; 467 unsigned long flags = 0; 468 int rv; 469 u32 data; 470 471 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 472 473 BUG_ON(rv == -1); 474 475 if (rv == 1) { 476 #ifndef __CHECKER__ 477 write_lock_irqsave(&ha->hw_lock, flags); 478 #endif 479 qla82xx_crb_win_lock(ha); 480 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 481 } 482 data = rd_reg_dword(off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 #ifndef __CHECKER__ 487 write_unlock_irqrestore(&ha->hw_lock, flags); 488 #endif 489 } 490 return data; 491 } 492 493 #define IDC_LOCK_TIMEOUT 100000000 494 int qla82xx_idc_lock(struct qla_hw_data *ha) 495 { 496 int i; 497 int done = 0, timeout = 0; 498 499 while (!done) { 500 /* acquire semaphore5 from PCI HW block */ 501 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 502 if (done == 1) 503 break; 504 if (timeout >= IDC_LOCK_TIMEOUT) 505 return -1; 506 507 timeout++; 508 509 /* Yield CPU */ 510 if (!in_interrupt()) 511 schedule(); 512 else { 513 for (i = 0; i < 20; i++) 514 cpu_relax(); 515 } 516 } 517 518 return 0; 519 } 520 521 void qla82xx_idc_unlock(struct qla_hw_data *ha) 522 { 523 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 524 } 525 526 /* 527 * check memory access boundary. 528 * used by test agent. support ddr access only for now 529 */ 530 static unsigned long 531 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 532 unsigned long long addr, int size) 533 { 534 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 535 QLA82XX_ADDR_DDR_NET_MAX) || 536 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 537 QLA82XX_ADDR_DDR_NET_MAX) || 538 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 539 return 0; 540 else 541 return 1; 542 } 543 544 static int qla82xx_pci_set_window_warning_count; 545 546 static unsigned long 547 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 548 { 549 int window; 550 u32 win_read; 551 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 552 553 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 554 QLA82XX_ADDR_DDR_NET_MAX)) { 555 /* DDR network side */ 556 window = MN_WIN(addr); 557 ha->ddr_mn_window = window; 558 qla82xx_wr_32(ha, 559 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 560 win_read = qla82xx_rd_32(ha, 561 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 562 if ((win_read << 17) != window) { 563 ql_dbg(ql_dbg_p3p, vha, 0xb003, 564 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 565 __func__, window, win_read); 566 } 567 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 568 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 569 QLA82XX_ADDR_OCM0_MAX)) { 570 unsigned int temp1; 571 572 if ((addr & 0x00ff800) == 0xff800) { 573 ql_log(ql_log_warn, vha, 0xb004, 574 "%s: QM access not handled.\n", __func__); 575 addr = -1UL; 576 } 577 window = OCM_WIN(addr); 578 ha->ddr_mn_window = window; 579 qla82xx_wr_32(ha, 580 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 581 win_read = qla82xx_rd_32(ha, 582 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 583 temp1 = ((window & 0x1FF) << 7) | 584 ((window & 0x0FFFE0000) >> 17); 585 if (win_read != temp1) { 586 ql_log(ql_log_warn, vha, 0xb005, 587 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 588 __func__, temp1, win_read); 589 } 590 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 591 592 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 593 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 594 /* QDR network side */ 595 window = MS_WIN(addr); 596 ha->qdr_sn_window = window; 597 qla82xx_wr_32(ha, 598 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 599 win_read = qla82xx_rd_32(ha, 600 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 601 if (win_read != window) { 602 ql_log(ql_log_warn, vha, 0xb006, 603 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 604 __func__, window, win_read); 605 } 606 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 607 } else { 608 /* 609 * peg gdb frequently accesses memory that doesn't exist, 610 * this limits the chit chat so debugging isn't slowed down. 611 */ 612 if ((qla82xx_pci_set_window_warning_count++ < 8) || 613 (qla82xx_pci_set_window_warning_count%64 == 0)) { 614 ql_log(ql_log_warn, vha, 0xb007, 615 "%s: Warning:%s Unknown address range!.\n", 616 __func__, QLA2XXX_DRIVER_NAME); 617 } 618 addr = -1UL; 619 } 620 return addr; 621 } 622 623 /* check if address is in the same windows as the previous access */ 624 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 625 unsigned long long addr) 626 { 627 int window; 628 unsigned long long qdr_max; 629 630 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 631 632 /* DDR network side */ 633 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 634 QLA82XX_ADDR_DDR_NET_MAX)) 635 BUG(); 636 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 637 QLA82XX_ADDR_OCM0_MAX)) 638 return 1; 639 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 640 QLA82XX_ADDR_OCM1_MAX)) 641 return 1; 642 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 643 /* QDR network side */ 644 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 645 if (ha->qdr_sn_window == window) 646 return 1; 647 } 648 return 0; 649 } 650 651 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 652 u64 off, void *data, int size) 653 { 654 unsigned long flags; 655 void __iomem *addr = NULL; 656 int ret = 0; 657 u64 start; 658 uint8_t __iomem *mem_ptr = NULL; 659 unsigned long mem_base; 660 unsigned long mem_page; 661 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 662 663 write_lock_irqsave(&ha->hw_lock, flags); 664 665 /* 666 * If attempting to access unknown address or straddle hw windows, 667 * do not access. 668 */ 669 start = qla82xx_pci_set_window(ha, off); 670 if ((start == -1UL) || 671 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 672 write_unlock_irqrestore(&ha->hw_lock, flags); 673 ql_log(ql_log_fatal, vha, 0xb008, 674 "%s out of bound pci memory " 675 "access, offset is 0x%llx.\n", 676 QLA2XXX_DRIVER_NAME, off); 677 return -1; 678 } 679 680 write_unlock_irqrestore(&ha->hw_lock, flags); 681 mem_base = pci_resource_start(ha->pdev, 0); 682 mem_page = start & PAGE_MASK; 683 /* Map two pages whenever user tries to access addresses in two 684 * consecutive pages. 685 */ 686 if (mem_page != ((start + size - 1) & PAGE_MASK)) 687 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 688 else 689 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 690 if (mem_ptr == NULL) { 691 *(u8 *)data = 0; 692 return -1; 693 } 694 addr = mem_ptr; 695 addr += start & (PAGE_SIZE - 1); 696 write_lock_irqsave(&ha->hw_lock, flags); 697 698 switch (size) { 699 case 1: 700 *(u8 *)data = readb(addr); 701 break; 702 case 2: 703 *(u16 *)data = readw(addr); 704 break; 705 case 4: 706 *(u32 *)data = readl(addr); 707 break; 708 case 8: 709 *(u64 *)data = readq(addr); 710 break; 711 default: 712 ret = -1; 713 break; 714 } 715 write_unlock_irqrestore(&ha->hw_lock, flags); 716 717 if (mem_ptr) 718 iounmap(mem_ptr); 719 return ret; 720 } 721 722 static int 723 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 724 u64 off, void *data, int size) 725 { 726 unsigned long flags; 727 void __iomem *addr = NULL; 728 int ret = 0; 729 u64 start; 730 uint8_t __iomem *mem_ptr = NULL; 731 unsigned long mem_base; 732 unsigned long mem_page; 733 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 734 735 write_lock_irqsave(&ha->hw_lock, flags); 736 737 /* 738 * If attempting to access unknown address or straddle hw windows, 739 * do not access. 740 */ 741 start = qla82xx_pci_set_window(ha, off); 742 if ((start == -1UL) || 743 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 744 write_unlock_irqrestore(&ha->hw_lock, flags); 745 ql_log(ql_log_fatal, vha, 0xb009, 746 "%s out of bound memory " 747 "access, offset is 0x%llx.\n", 748 QLA2XXX_DRIVER_NAME, off); 749 return -1; 750 } 751 752 write_unlock_irqrestore(&ha->hw_lock, flags); 753 mem_base = pci_resource_start(ha->pdev, 0); 754 mem_page = start & PAGE_MASK; 755 /* Map two pages whenever user tries to access addresses in two 756 * consecutive pages. 757 */ 758 if (mem_page != ((start + size - 1) & PAGE_MASK)) 759 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 760 else 761 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 762 if (mem_ptr == NULL) 763 return -1; 764 765 addr = mem_ptr; 766 addr += start & (PAGE_SIZE - 1); 767 write_lock_irqsave(&ha->hw_lock, flags); 768 769 switch (size) { 770 case 1: 771 writeb(*(u8 *)data, addr); 772 break; 773 case 2: 774 writew(*(u16 *)data, addr); 775 break; 776 case 4: 777 writel(*(u32 *)data, addr); 778 break; 779 case 8: 780 writeq(*(u64 *)data, addr); 781 break; 782 default: 783 ret = -1; 784 break; 785 } 786 write_unlock_irqrestore(&ha->hw_lock, flags); 787 if (mem_ptr) 788 iounmap(mem_ptr); 789 return ret; 790 } 791 792 #define MTU_FUDGE_FACTOR 100 793 static unsigned long 794 qla82xx_decode_crb_addr(unsigned long addr) 795 { 796 int i; 797 unsigned long base_addr, offset, pci_base; 798 799 if (!qla82xx_crb_table_initialized) 800 qla82xx_crb_addr_transform_setup(); 801 802 pci_base = ADDR_ERROR; 803 base_addr = addr & 0xfff00000; 804 offset = addr & 0x000fffff; 805 806 for (i = 0; i < MAX_CRB_XFORM; i++) { 807 if (crb_addr_xform[i] == base_addr) { 808 pci_base = i << 20; 809 break; 810 } 811 } 812 if (pci_base == ADDR_ERROR) 813 return pci_base; 814 return pci_base + offset; 815 } 816 817 static long rom_max_timeout = 100; 818 static long qla82xx_rom_lock_timeout = 100; 819 820 static int 821 qla82xx_rom_lock(struct qla_hw_data *ha) 822 { 823 int done = 0, timeout = 0; 824 uint32_t lock_owner = 0; 825 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 826 827 while (!done) { 828 /* acquire semaphore2 from PCI HW block */ 829 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 830 if (done == 1) 831 break; 832 if (timeout >= qla82xx_rom_lock_timeout) { 833 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 834 ql_dbg(ql_dbg_p3p, vha, 0xb157, 835 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 836 __func__, ha->portnum, lock_owner); 837 return -1; 838 } 839 timeout++; 840 } 841 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 842 return 0; 843 } 844 845 static void 846 qla82xx_rom_unlock(struct qla_hw_data *ha) 847 { 848 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 849 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 850 } 851 852 static int 853 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 854 { 855 long timeout = 0; 856 long done = 0 ; 857 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 858 859 while (done == 0) { 860 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 861 done &= 4; 862 timeout++; 863 if (timeout >= rom_max_timeout) { 864 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 865 "%s: Timeout reached waiting for rom busy.\n", 866 QLA2XXX_DRIVER_NAME); 867 return -1; 868 } 869 } 870 return 0; 871 } 872 873 static int 874 qla82xx_wait_rom_done(struct qla_hw_data *ha) 875 { 876 long timeout = 0; 877 long done = 0 ; 878 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 879 880 while (done == 0) { 881 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 882 done &= 2; 883 timeout++; 884 if (timeout >= rom_max_timeout) { 885 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 886 "%s: Timeout reached waiting for rom done.\n", 887 QLA2XXX_DRIVER_NAME); 888 return -1; 889 } 890 } 891 return 0; 892 } 893 894 static int 895 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 896 { 897 uint32_t off_value, rval = 0; 898 899 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 900 901 /* Read back value to make sure write has gone through */ 902 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 903 off_value = (off & 0x0000FFFF); 904 905 if (flag) 906 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 907 data); 908 else 909 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + 910 ha->nx_pcibase); 911 912 return rval; 913 } 914 915 static int 916 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 917 { 918 /* Dword reads to flash. */ 919 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 920 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 921 (addr & 0x0000FFFF), 0, 0); 922 923 return 0; 924 } 925 926 static int 927 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 928 { 929 int ret, loops = 0; 930 uint32_t lock_owner = 0; 931 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 932 933 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 934 udelay(100); 935 schedule(); 936 loops++; 937 } 938 if (loops >= 50000) { 939 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 940 ql_log(ql_log_fatal, vha, 0x00b9, 941 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 942 lock_owner); 943 return -1; 944 } 945 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 946 qla82xx_rom_unlock(ha); 947 return ret; 948 } 949 950 static int 951 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 952 { 953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 954 955 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 956 qla82xx_wait_rom_busy(ha); 957 if (qla82xx_wait_rom_done(ha)) { 958 ql_log(ql_log_warn, vha, 0xb00c, 959 "Error waiting for rom done.\n"); 960 return -1; 961 } 962 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 963 return 0; 964 } 965 966 static int 967 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 968 { 969 long timeout = 0; 970 uint32_t done = 1 ; 971 uint32_t val; 972 int ret = 0; 973 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 974 975 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 976 while ((done != 0) && (ret == 0)) { 977 ret = qla82xx_read_status_reg(ha, &val); 978 done = val & 1; 979 timeout++; 980 udelay(10); 981 cond_resched(); 982 if (timeout >= 50000) { 983 ql_log(ql_log_warn, vha, 0xb00d, 984 "Timeout reached waiting for write finish.\n"); 985 return -1; 986 } 987 } 988 return ret; 989 } 990 991 static int 992 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 993 { 994 uint32_t val; 995 996 qla82xx_wait_rom_busy(ha); 997 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 998 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 999 qla82xx_wait_rom_busy(ha); 1000 if (qla82xx_wait_rom_done(ha)) 1001 return -1; 1002 if (qla82xx_read_status_reg(ha, &val) != 0) 1003 return -1; 1004 if ((val & 2) != 2) 1005 return -1; 1006 return 0; 1007 } 1008 1009 static int 1010 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1011 { 1012 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1013 1014 if (qla82xx_flash_set_write_enable(ha)) 1015 return -1; 1016 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1017 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1018 if (qla82xx_wait_rom_done(ha)) { 1019 ql_log(ql_log_warn, vha, 0xb00e, 1020 "Error waiting for rom done.\n"); 1021 return -1; 1022 } 1023 return qla82xx_flash_wait_write_finish(ha); 1024 } 1025 1026 static int 1027 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1028 { 1029 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1030 1031 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1032 if (qla82xx_wait_rom_done(ha)) { 1033 ql_log(ql_log_warn, vha, 0xb00f, 1034 "Error waiting for rom done.\n"); 1035 return -1; 1036 } 1037 return 0; 1038 } 1039 1040 static int 1041 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1042 { 1043 int loops = 0; 1044 uint32_t lock_owner = 0; 1045 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1046 1047 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1048 udelay(100); 1049 cond_resched(); 1050 loops++; 1051 } 1052 if (loops >= 50000) { 1053 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1054 ql_log(ql_log_warn, vha, 0xb010, 1055 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1056 return -1; 1057 } 1058 return 0; 1059 } 1060 1061 static int 1062 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063 uint32_t data) 1064 { 1065 int ret = 0; 1066 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067 1068 ret = ql82xx_rom_lock_d(ha); 1069 if (ret < 0) { 1070 ql_log(ql_log_warn, vha, 0xb011, 1071 "ROM lock failed.\n"); 1072 return ret; 1073 } 1074 1075 if (qla82xx_flash_set_write_enable(ha)) 1076 goto done_write; 1077 1078 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082 qla82xx_wait_rom_busy(ha); 1083 if (qla82xx_wait_rom_done(ha)) { 1084 ql_log(ql_log_warn, vha, 0xb012, 1085 "Error waiting for rom done.\n"); 1086 ret = -1; 1087 goto done_write; 1088 } 1089 1090 ret = qla82xx_flash_wait_write_finish(ha); 1091 1092 done_write: 1093 qla82xx_rom_unlock(ha); 1094 return ret; 1095 } 1096 1097 /* This routine does CRB initialize sequence 1098 * to put the ISP into operational state 1099 */ 1100 static int 1101 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102 { 1103 int addr, val; 1104 int i ; 1105 struct crb_addr_pair *buf; 1106 unsigned long off; 1107 unsigned offset, n; 1108 struct qla_hw_data *ha = vha->hw; 1109 1110 struct crb_addr_pair { 1111 long addr; 1112 long data; 1113 }; 1114 1115 /* Halt all the individual PEGs and other blocks of the ISP */ 1116 qla82xx_rom_lock(ha); 1117 1118 /* disable all I2Q */ 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1120 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1121 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1122 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1123 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1124 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1125 1126 /* disable all niu interrupts */ 1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128 /* disable xge rx/tx */ 1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130 /* disable xg1 rx/tx */ 1131 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1132 /* disable sideband mac */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1134 /* disable ap0 mac */ 1135 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1136 /* disable ap1 mac */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138 1139 /* halt sre */ 1140 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142 1143 /* halt epg */ 1144 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145 1146 /* halt timers */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153 1154 /* halt pegs */ 1155 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1160 msleep(20); 1161 1162 /* big hammer */ 1163 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164 /* don't reset CAM block on reset */ 1165 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166 else 1167 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168 qla82xx_rom_unlock(ha); 1169 1170 /* Read the signature value from the flash. 1171 * Offset 0: Contain signature (0xcafecafe) 1172 * Offset 4: Offset and number of addr/value pairs 1173 * that present in CRB initialize sequence 1174 */ 1175 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1176 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1177 ql_log(ql_log_fatal, vha, 0x006e, 1178 "Error Reading crb_init area: n: %08x.\n", n); 1179 return -1; 1180 } 1181 1182 /* Offset in flash = lower 16 bits 1183 * Number of entries = upper 16 bits 1184 */ 1185 offset = n & 0xffffU; 1186 n = (n >> 16) & 0xffffU; 1187 1188 /* number of addr/value pair should not exceed 1024 entries */ 1189 if (n >= 1024) { 1190 ql_log(ql_log_fatal, vha, 0x0071, 1191 "Card flash not initialized:n=0x%x.\n", n); 1192 return -1; 1193 } 1194 1195 ql_log(ql_log_info, vha, 0x0072, 1196 "%d CRB init values found in ROM.\n", n); 1197 1198 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1199 if (buf == NULL) { 1200 ql_log(ql_log_fatal, vha, 0x010c, 1201 "Unable to allocate memory.\n"); 1202 return -ENOMEM; 1203 } 1204 1205 for (i = 0; i < n; i++) { 1206 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1207 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1208 kfree(buf); 1209 return -1; 1210 } 1211 1212 buf[i].addr = addr; 1213 buf[i].data = val; 1214 } 1215 1216 for (i = 0; i < n; i++) { 1217 /* Translate internal CRB initialization 1218 * address to PCI bus address 1219 */ 1220 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1221 QLA82XX_PCI_CRBSPACE; 1222 /* Not all CRB addr/value pair to be written, 1223 * some of them are skipped 1224 */ 1225 1226 /* skipping cold reboot MAGIC */ 1227 if (off == QLA82XX_CAM_RAM(0x1fc)) 1228 continue; 1229 1230 /* do not reset PCI */ 1231 if (off == (ROMUSB_GLB + 0xbc)) 1232 continue; 1233 1234 /* skip core clock, so that firmware can increase the clock */ 1235 if (off == (ROMUSB_GLB + 0xc8)) 1236 continue; 1237 1238 /* skip the function enable register */ 1239 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1240 continue; 1241 1242 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1243 continue; 1244 1245 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1246 continue; 1247 1248 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1249 continue; 1250 1251 if (off == ADDR_ERROR) { 1252 ql_log(ql_log_fatal, vha, 0x0116, 1253 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1254 continue; 1255 } 1256 1257 qla82xx_wr_32(ha, off, buf[i].data); 1258 1259 /* ISP requires much bigger delay to settle down, 1260 * else crb_window returns 0xffffffff 1261 */ 1262 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1263 msleep(1000); 1264 1265 /* ISP requires millisec delay between 1266 * successive CRB register updation 1267 */ 1268 msleep(1); 1269 } 1270 1271 kfree(buf); 1272 1273 /* Resetting the data and instruction cache */ 1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1277 1278 /* Clear all protocol processing engines */ 1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1280 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1281 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1282 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1283 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1284 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1285 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1286 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1287 return 0; 1288 } 1289 1290 static int 1291 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1292 u64 off, void *data, int size) 1293 { 1294 int i, j, ret = 0, loop, sz[2], off0; 1295 int scale, shift_amount, startword; 1296 uint32_t temp; 1297 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1298 1299 /* 1300 * If not MN, go check for MS or invalid. 1301 */ 1302 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1303 mem_crb = QLA82XX_CRB_QDR_NET; 1304 else { 1305 mem_crb = QLA82XX_CRB_DDR_NET; 1306 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1307 return qla82xx_pci_mem_write_direct(ha, 1308 off, data, size); 1309 } 1310 1311 off0 = off & 0x7; 1312 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1313 sz[1] = size - sz[0]; 1314 1315 off8 = off & 0xfffffff0; 1316 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1317 shift_amount = 4; 1318 scale = 2; 1319 startword = (off & 0xf)/8; 1320 1321 for (i = 0; i < loop; i++) { 1322 if (qla82xx_pci_mem_read_2M(ha, off8 + 1323 (i << shift_amount), &word[i * scale], 8)) 1324 return -1; 1325 } 1326 1327 switch (size) { 1328 case 1: 1329 tmpw = *((uint8_t *)data); 1330 break; 1331 case 2: 1332 tmpw = *((uint16_t *)data); 1333 break; 1334 case 4: 1335 tmpw = *((uint32_t *)data); 1336 break; 1337 case 8: 1338 default: 1339 tmpw = *((uint64_t *)data); 1340 break; 1341 } 1342 1343 if (sz[0] == 8) { 1344 word[startword] = tmpw; 1345 } else { 1346 word[startword] &= 1347 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1348 word[startword] |= tmpw << (off0 * 8); 1349 } 1350 if (sz[1] != 0) { 1351 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1352 word[startword+1] |= tmpw >> (sz[0] * 8); 1353 } 1354 1355 for (i = 0; i < loop; i++) { 1356 temp = off8 + (i << shift_amount); 1357 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1358 temp = 0; 1359 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1360 temp = word[i * scale] & 0xffffffff; 1361 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1362 temp = (word[i * scale] >> 32) & 0xffffffff; 1363 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1364 temp = word[i*scale + 1] & 0xffffffff; 1365 qla82xx_wr_32(ha, mem_crb + 1366 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1367 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1368 qla82xx_wr_32(ha, mem_crb + 1369 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1370 1371 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1372 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1373 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1374 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1375 1376 for (j = 0; j < MAX_CTL_CHECK; j++) { 1377 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1378 if ((temp & MIU_TA_CTL_BUSY) == 0) 1379 break; 1380 } 1381 1382 if (j >= MAX_CTL_CHECK) { 1383 if (printk_ratelimit()) 1384 dev_err(&ha->pdev->dev, 1385 "failed to write through agent.\n"); 1386 ret = -1; 1387 break; 1388 } 1389 } 1390 1391 return ret; 1392 } 1393 1394 static int 1395 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1396 { 1397 int i; 1398 long size = 0; 1399 long flashaddr = ha->flt_region_bootload << 2; 1400 long memaddr = BOOTLD_START; 1401 u64 data; 1402 u32 high, low; 1403 1404 size = (IMAGE_START - BOOTLD_START) / 8; 1405 1406 for (i = 0; i < size; i++) { 1407 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1408 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1409 return -1; 1410 } 1411 data = ((u64)high << 32) | low ; 1412 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1413 flashaddr += 8; 1414 memaddr += 8; 1415 1416 if (i % 0x1000 == 0) 1417 msleep(1); 1418 } 1419 udelay(100); 1420 read_lock(&ha->hw_lock); 1421 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1422 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1423 read_unlock(&ha->hw_lock); 1424 return 0; 1425 } 1426 1427 int 1428 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1429 u64 off, void *data, int size) 1430 { 1431 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1432 int shift_amount; 1433 uint32_t temp; 1434 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1435 1436 /* 1437 * If not MN, go check for MS or invalid. 1438 */ 1439 1440 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1441 mem_crb = QLA82XX_CRB_QDR_NET; 1442 else { 1443 mem_crb = QLA82XX_CRB_DDR_NET; 1444 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1445 return qla82xx_pci_mem_read_direct(ha, 1446 off, data, size); 1447 } 1448 1449 off8 = off & 0xfffffff0; 1450 off0[0] = off & 0xf; 1451 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1452 shift_amount = 4; 1453 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1454 off0[1] = 0; 1455 sz[1] = size - sz[0]; 1456 1457 for (i = 0; i < loop; i++) { 1458 temp = off8 + (i << shift_amount); 1459 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1460 temp = 0; 1461 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1462 temp = MIU_TA_CTL_ENABLE; 1463 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1464 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1465 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1466 1467 for (j = 0; j < MAX_CTL_CHECK; j++) { 1468 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1469 if ((temp & MIU_TA_CTL_BUSY) == 0) 1470 break; 1471 } 1472 1473 if (j >= MAX_CTL_CHECK) { 1474 if (printk_ratelimit()) 1475 dev_err(&ha->pdev->dev, 1476 "failed to read through agent.\n"); 1477 break; 1478 } 1479 1480 start = off0[i] >> 2; 1481 end = (off0[i] + sz[i] - 1) >> 2; 1482 for (k = start; k <= end; k++) { 1483 temp = qla82xx_rd_32(ha, 1484 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1485 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1486 } 1487 } 1488 1489 if (j >= MAX_CTL_CHECK) 1490 return -1; 1491 1492 if ((off0[0] & 7) == 0) { 1493 val = word[0]; 1494 } else { 1495 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1496 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1497 } 1498 1499 switch (size) { 1500 case 1: 1501 *(uint8_t *)data = val; 1502 break; 1503 case 2: 1504 *(uint16_t *)data = val; 1505 break; 1506 case 4: 1507 *(uint32_t *)data = val; 1508 break; 1509 case 8: 1510 *(uint64_t *)data = val; 1511 break; 1512 } 1513 return 0; 1514 } 1515 1516 1517 static struct qla82xx_uri_table_desc * 1518 qla82xx_get_table_desc(const u8 *unirom, int section) 1519 { 1520 uint32_t i; 1521 struct qla82xx_uri_table_desc *directory = 1522 (struct qla82xx_uri_table_desc *)&unirom[0]; 1523 uint32_t offset; 1524 uint32_t tab_type; 1525 uint32_t entries = le32_to_cpu(directory->num_entries); 1526 1527 for (i = 0; i < entries; i++) { 1528 offset = le32_to_cpu(directory->findex) + 1529 (i * le32_to_cpu(directory->entry_size)); 1530 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8); 1531 1532 if (tab_type == section) 1533 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1534 } 1535 1536 return NULL; 1537 } 1538 1539 static struct qla82xx_uri_data_desc * 1540 qla82xx_get_data_desc(struct qla_hw_data *ha, 1541 u32 section, u32 idx_offset) 1542 { 1543 const u8 *unirom = ha->hablob->fw->data; 1544 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] + 1545 idx_offset); 1546 struct qla82xx_uri_table_desc *tab_desc = NULL; 1547 uint32_t offset; 1548 1549 tab_desc = qla82xx_get_table_desc(unirom, section); 1550 if (!tab_desc) 1551 return NULL; 1552 1553 offset = le32_to_cpu(tab_desc->findex) + 1554 (le32_to_cpu(tab_desc->entry_size) * idx); 1555 1556 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1557 } 1558 1559 static u8 * 1560 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1561 { 1562 u32 offset = BOOTLD_START; 1563 struct qla82xx_uri_data_desc *uri_desc = NULL; 1564 1565 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1566 uri_desc = qla82xx_get_data_desc(ha, 1567 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1568 if (uri_desc) 1569 offset = le32_to_cpu(uri_desc->findex); 1570 } 1571 1572 return (u8 *)&ha->hablob->fw->data[offset]; 1573 } 1574 1575 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha) 1576 { 1577 struct qla82xx_uri_data_desc *uri_desc = NULL; 1578 1579 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1580 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1581 QLA82XX_URI_FIRMWARE_IDX_OFF); 1582 if (uri_desc) 1583 return le32_to_cpu(uri_desc->size); 1584 } 1585 1586 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1587 } 1588 1589 static u8 * 1590 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1591 { 1592 u32 offset = IMAGE_START; 1593 struct qla82xx_uri_data_desc *uri_desc = NULL; 1594 1595 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1596 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1597 QLA82XX_URI_FIRMWARE_IDX_OFF); 1598 if (uri_desc) 1599 offset = le32_to_cpu(uri_desc->findex); 1600 } 1601 1602 return (u8 *)&ha->hablob->fw->data[offset]; 1603 } 1604 1605 /* PCI related functions */ 1606 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1607 { 1608 unsigned long val = 0; 1609 u32 control; 1610 1611 switch (region) { 1612 case 0: 1613 val = 0; 1614 break; 1615 case 1: 1616 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1617 val = control + QLA82XX_MSIX_TBL_SPACE; 1618 break; 1619 } 1620 return val; 1621 } 1622 1623 1624 int 1625 qla82xx_iospace_config(struct qla_hw_data *ha) 1626 { 1627 uint32_t len = 0; 1628 1629 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1631 "Failed to reserver selected regions.\n"); 1632 goto iospace_error_exit; 1633 } 1634 1635 /* Use MMIO operations for all accesses. */ 1636 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1637 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1638 "Region #0 not an MMIO resource, aborting.\n"); 1639 goto iospace_error_exit; 1640 } 1641 1642 len = pci_resource_len(ha->pdev, 0); 1643 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1644 if (!ha->nx_pcibase) { 1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1646 "Cannot remap pcibase MMIO, aborting.\n"); 1647 goto iospace_error_exit; 1648 } 1649 1650 /* Mapping of IO base pointer */ 1651 if (IS_QLA8044(ha)) { 1652 ha->iobase = ha->nx_pcibase; 1653 } else if (IS_QLA82XX(ha)) { 1654 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1655 } 1656 1657 if (!ql2xdbwr) { 1658 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1659 (ha->pdev->devfn << 12)), 4); 1660 if (!ha->nxdb_wr_ptr) { 1661 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1662 "Cannot remap MMIO, aborting.\n"); 1663 goto iospace_error_exit; 1664 } 1665 1666 /* Mapping of IO base pointer, 1667 * door bell read and write pointer 1668 */ 1669 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1670 (ha->pdev->devfn * 8); 1671 } else { 1672 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1673 QLA82XX_CAMRAM_DB1 : 1674 QLA82XX_CAMRAM_DB2); 1675 } 1676 1677 ha->max_req_queues = ha->max_rsp_queues = 1; 1678 ha->msix_count = ha->max_rsp_queues + 1; 1679 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1680 "nx_pci_base=%p iobase=%p " 1681 "max_req_queues=%d msix_count=%d.\n", 1682 ha->nx_pcibase, ha->iobase, 1683 ha->max_req_queues, ha->msix_count); 1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1685 "nx_pci_base=%p iobase=%p " 1686 "max_req_queues=%d msix_count=%d.\n", 1687 ha->nx_pcibase, ha->iobase, 1688 ha->max_req_queues, ha->msix_count); 1689 return 0; 1690 1691 iospace_error_exit: 1692 return -ENOMEM; 1693 } 1694 1695 /* GS related functions */ 1696 1697 /* Initialization related functions */ 1698 1699 /** 1700 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1701 * @vha: HA context 1702 * 1703 * Returns 0 on success. 1704 */ 1705 int 1706 qla82xx_pci_config(scsi_qla_host_t *vha) 1707 { 1708 struct qla_hw_data *ha = vha->hw; 1709 int ret; 1710 1711 pci_set_master(ha->pdev); 1712 ret = pci_set_mwi(ha->pdev); 1713 ha->chip_revision = ha->pdev->revision; 1714 ql_dbg(ql_dbg_init, vha, 0x0043, 1715 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1716 ha->chip_revision, ret); 1717 return 0; 1718 } 1719 1720 /** 1721 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1722 * @vha: HA context 1723 * 1724 * Returns 0 on success. 1725 */ 1726 int 1727 qla82xx_reset_chip(scsi_qla_host_t *vha) 1728 { 1729 struct qla_hw_data *ha = vha->hw; 1730 1731 ha->isp_ops->disable_intrs(ha); 1732 1733 return QLA_SUCCESS; 1734 } 1735 1736 void qla82xx_config_rings(struct scsi_qla_host *vha) 1737 { 1738 struct qla_hw_data *ha = vha->hw; 1739 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1740 struct init_cb_81xx *icb; 1741 struct req_que *req = ha->req_q_map[0]; 1742 struct rsp_que *rsp = ha->rsp_q_map[0]; 1743 1744 /* Setup ring parameters in initialization control block. */ 1745 icb = (struct init_cb_81xx *)ha->init_cb; 1746 icb->request_q_outpointer = cpu_to_le16(0); 1747 icb->response_q_inpointer = cpu_to_le16(0); 1748 icb->request_q_length = cpu_to_le16(req->length); 1749 icb->response_q_length = cpu_to_le16(rsp->length); 1750 put_unaligned_le64(req->dma, &icb->request_q_address); 1751 put_unaligned_le64(rsp->dma, &icb->response_q_address); 1752 1753 wrt_reg_dword(®->req_q_out[0], 0); 1754 wrt_reg_dword(®->rsp_q_in[0], 0); 1755 wrt_reg_dword(®->rsp_q_out[0], 0); 1756 } 1757 1758 static int 1759 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1760 { 1761 u64 *ptr64; 1762 u32 i, flashaddr, size; 1763 __le64 data; 1764 1765 size = (IMAGE_START - BOOTLD_START) / 8; 1766 1767 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1768 flashaddr = BOOTLD_START; 1769 1770 for (i = 0; i < size; i++) { 1771 data = cpu_to_le64(ptr64[i]); 1772 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1773 return -EIO; 1774 flashaddr += 8; 1775 } 1776 1777 flashaddr = FLASH_ADDR_START; 1778 size = qla82xx_get_fw_size(ha) / 8; 1779 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1780 1781 for (i = 0; i < size; i++) { 1782 data = cpu_to_le64(ptr64[i]); 1783 1784 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1785 return -EIO; 1786 flashaddr += 8; 1787 } 1788 udelay(100); 1789 1790 /* Write a magic value to CAMRAM register 1791 * at a specified offset to indicate 1792 * that all data is written and 1793 * ready for firmware to initialize. 1794 */ 1795 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1796 1797 read_lock(&ha->hw_lock); 1798 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1799 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1800 read_unlock(&ha->hw_lock); 1801 return 0; 1802 } 1803 1804 static int 1805 qla82xx_set_product_offset(struct qla_hw_data *ha) 1806 { 1807 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1808 const uint8_t *unirom = ha->hablob->fw->data; 1809 uint32_t i; 1810 uint32_t entries; 1811 uint32_t flags, file_chiprev, offset; 1812 uint8_t chiprev = ha->chip_revision; 1813 /* Hardcoding mn_present flag for P3P */ 1814 int mn_present = 0; 1815 uint32_t flagbit; 1816 1817 ptab_desc = qla82xx_get_table_desc(unirom, 1818 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1819 if (!ptab_desc) 1820 return -1; 1821 1822 entries = le32_to_cpu(ptab_desc->num_entries); 1823 1824 for (i = 0; i < entries; i++) { 1825 offset = le32_to_cpu(ptab_desc->findex) + 1826 (i * le32_to_cpu(ptab_desc->entry_size)); 1827 flags = le32_to_cpu(*((__le32 *)&unirom[offset] + 1828 QLA82XX_URI_FLAGS_OFF)); 1829 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] + 1830 QLA82XX_URI_CHIP_REV_OFF)); 1831 1832 flagbit = mn_present ? 1 : 2; 1833 1834 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1835 ha->file_prd_off = offset; 1836 return 0; 1837 } 1838 } 1839 return -1; 1840 } 1841 1842 static int 1843 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1844 { 1845 uint32_t val; 1846 uint32_t min_size; 1847 struct qla_hw_data *ha = vha->hw; 1848 const struct firmware *fw = ha->hablob->fw; 1849 1850 ha->fw_type = fw_type; 1851 1852 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1853 if (qla82xx_set_product_offset(ha)) 1854 return -EINVAL; 1855 1856 min_size = QLA82XX_URI_FW_MIN_SIZE; 1857 } else { 1858 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1859 if (val != QLA82XX_BDINFO_MAGIC) 1860 return -EINVAL; 1861 1862 min_size = QLA82XX_FW_MIN_SIZE; 1863 } 1864 1865 if (fw->size < min_size) 1866 return -EINVAL; 1867 return 0; 1868 } 1869 1870 static int 1871 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1872 { 1873 u32 val = 0; 1874 int retries = 60; 1875 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1876 1877 do { 1878 read_lock(&ha->hw_lock); 1879 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1880 read_unlock(&ha->hw_lock); 1881 1882 switch (val) { 1883 case PHAN_INITIALIZE_COMPLETE: 1884 case PHAN_INITIALIZE_ACK: 1885 return QLA_SUCCESS; 1886 case PHAN_INITIALIZE_FAILED: 1887 break; 1888 default: 1889 break; 1890 } 1891 ql_log(ql_log_info, vha, 0x00a8, 1892 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1893 val, retries); 1894 1895 msleep(500); 1896 1897 } while (--retries); 1898 1899 ql_log(ql_log_fatal, vha, 0x00a9, 1900 "Cmd Peg initialization failed: 0x%x.\n", val); 1901 1902 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1903 read_lock(&ha->hw_lock); 1904 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1905 read_unlock(&ha->hw_lock); 1906 return QLA_FUNCTION_FAILED; 1907 } 1908 1909 static int 1910 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1911 { 1912 u32 val = 0; 1913 int retries = 60; 1914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1915 1916 do { 1917 read_lock(&ha->hw_lock); 1918 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1919 read_unlock(&ha->hw_lock); 1920 1921 switch (val) { 1922 case PHAN_INITIALIZE_COMPLETE: 1923 case PHAN_INITIALIZE_ACK: 1924 return QLA_SUCCESS; 1925 case PHAN_INITIALIZE_FAILED: 1926 break; 1927 default: 1928 break; 1929 } 1930 ql_log(ql_log_info, vha, 0x00ab, 1931 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1932 val, retries); 1933 1934 msleep(500); 1935 1936 } while (--retries); 1937 1938 ql_log(ql_log_fatal, vha, 0x00ac, 1939 "Rcv Peg initialization failed: 0x%x.\n", val); 1940 read_lock(&ha->hw_lock); 1941 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1942 read_unlock(&ha->hw_lock); 1943 return QLA_FUNCTION_FAILED; 1944 } 1945 1946 /* ISR related functions */ 1947 static struct qla82xx_legacy_intr_set legacy_intr[] = 1948 QLA82XX_LEGACY_INTR_CONFIG; 1949 1950 /* 1951 * qla82xx_mbx_completion() - Process mailbox command completions. 1952 * @ha: SCSI driver HA context 1953 * @mb0: Mailbox0 register 1954 */ 1955 void 1956 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1957 { 1958 uint16_t cnt; 1959 __le16 __iomem *wptr; 1960 struct qla_hw_data *ha = vha->hw; 1961 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1962 1963 wptr = ®->mailbox_out[1]; 1964 1965 /* Load return mailbox registers. */ 1966 ha->flags.mbox_int = 1; 1967 ha->mailbox_out[0] = mb0; 1968 1969 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1970 ha->mailbox_out[cnt] = rd_reg_word(wptr); 1971 wptr++; 1972 } 1973 1974 if (!ha->mcp) 1975 ql_dbg(ql_dbg_async, vha, 0x5053, 1976 "MBX pointer ERROR.\n"); 1977 } 1978 1979 /** 1980 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1981 * @irq: interrupt number 1982 * @dev_id: SCSI driver HA context 1983 * 1984 * Called by system whenever the host adapter generates an interrupt. 1985 * 1986 * Returns handled flag. 1987 */ 1988 irqreturn_t 1989 qla82xx_intr_handler(int irq, void *dev_id) 1990 { 1991 scsi_qla_host_t *vha; 1992 struct qla_hw_data *ha; 1993 struct rsp_que *rsp; 1994 struct device_reg_82xx __iomem *reg; 1995 int status = 0, status1 = 0; 1996 unsigned long flags; 1997 unsigned long iter; 1998 uint32_t stat = 0; 1999 uint16_t mb[8]; 2000 2001 rsp = (struct rsp_que *) dev_id; 2002 if (!rsp) { 2003 ql_log(ql_log_info, NULL, 0xb053, 2004 "%s: NULL response queue pointer.\n", __func__); 2005 return IRQ_NONE; 2006 } 2007 ha = rsp->hw; 2008 2009 if (!ha->flags.msi_enabled) { 2010 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2011 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2012 return IRQ_NONE; 2013 2014 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2015 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2016 return IRQ_NONE; 2017 } 2018 2019 /* clear the interrupt */ 2020 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2021 2022 /* read twice to ensure write is flushed */ 2023 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2024 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2025 2026 reg = &ha->iobase->isp82; 2027 2028 spin_lock_irqsave(&ha->hardware_lock, flags); 2029 vha = pci_get_drvdata(ha->pdev); 2030 for (iter = 1; iter--; ) { 2031 2032 if (rd_reg_dword(®->host_int)) { 2033 stat = rd_reg_dword(®->host_status); 2034 2035 switch (stat & 0xff) { 2036 case 0x1: 2037 case 0x2: 2038 case 0x10: 2039 case 0x11: 2040 qla82xx_mbx_completion(vha, MSW(stat)); 2041 status |= MBX_INTERRUPT; 2042 break; 2043 case 0x12: 2044 mb[0] = MSW(stat); 2045 mb[1] = rd_reg_word(®->mailbox_out[1]); 2046 mb[2] = rd_reg_word(®->mailbox_out[2]); 2047 mb[3] = rd_reg_word(®->mailbox_out[3]); 2048 qla2x00_async_event(vha, rsp, mb); 2049 break; 2050 case 0x13: 2051 qla24xx_process_response_queue(vha, rsp); 2052 break; 2053 default: 2054 ql_dbg(ql_dbg_async, vha, 0x5054, 2055 "Unrecognized interrupt type (%d).\n", 2056 stat & 0xff); 2057 break; 2058 } 2059 } 2060 wrt_reg_dword(®->host_int, 0); 2061 } 2062 2063 qla2x00_handle_mbx_completion(ha, status); 2064 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2065 2066 if (!ha->flags.msi_enabled) 2067 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2068 2069 return IRQ_HANDLED; 2070 } 2071 2072 irqreturn_t 2073 qla82xx_msix_default(int irq, void *dev_id) 2074 { 2075 scsi_qla_host_t *vha; 2076 struct qla_hw_data *ha; 2077 struct rsp_que *rsp; 2078 struct device_reg_82xx __iomem *reg; 2079 int status = 0; 2080 unsigned long flags; 2081 uint32_t stat = 0; 2082 uint32_t host_int = 0; 2083 uint16_t mb[8]; 2084 2085 rsp = (struct rsp_que *) dev_id; 2086 if (!rsp) { 2087 printk(KERN_INFO 2088 "%s(): NULL response queue pointer.\n", __func__); 2089 return IRQ_NONE; 2090 } 2091 ha = rsp->hw; 2092 2093 reg = &ha->iobase->isp82; 2094 2095 spin_lock_irqsave(&ha->hardware_lock, flags); 2096 vha = pci_get_drvdata(ha->pdev); 2097 do { 2098 host_int = rd_reg_dword(®->host_int); 2099 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2100 break; 2101 if (host_int) { 2102 stat = rd_reg_dword(®->host_status); 2103 2104 switch (stat & 0xff) { 2105 case 0x1: 2106 case 0x2: 2107 case 0x10: 2108 case 0x11: 2109 qla82xx_mbx_completion(vha, MSW(stat)); 2110 status |= MBX_INTERRUPT; 2111 break; 2112 case 0x12: 2113 mb[0] = MSW(stat); 2114 mb[1] = rd_reg_word(®->mailbox_out[1]); 2115 mb[2] = rd_reg_word(®->mailbox_out[2]); 2116 mb[3] = rd_reg_word(®->mailbox_out[3]); 2117 qla2x00_async_event(vha, rsp, mb); 2118 break; 2119 case 0x13: 2120 qla24xx_process_response_queue(vha, rsp); 2121 break; 2122 default: 2123 ql_dbg(ql_dbg_async, vha, 0x5041, 2124 "Unrecognized interrupt type (%d).\n", 2125 stat & 0xff); 2126 break; 2127 } 2128 } 2129 wrt_reg_dword(®->host_int, 0); 2130 } while (0); 2131 2132 qla2x00_handle_mbx_completion(ha, status); 2133 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2134 2135 return IRQ_HANDLED; 2136 } 2137 2138 irqreturn_t 2139 qla82xx_msix_rsp_q(int irq, void *dev_id) 2140 { 2141 scsi_qla_host_t *vha; 2142 struct qla_hw_data *ha; 2143 struct rsp_que *rsp; 2144 struct device_reg_82xx __iomem *reg; 2145 unsigned long flags; 2146 uint32_t host_int = 0; 2147 2148 rsp = (struct rsp_que *) dev_id; 2149 if (!rsp) { 2150 printk(KERN_INFO 2151 "%s(): NULL response queue pointer.\n", __func__); 2152 return IRQ_NONE; 2153 } 2154 2155 ha = rsp->hw; 2156 reg = &ha->iobase->isp82; 2157 spin_lock_irqsave(&ha->hardware_lock, flags); 2158 vha = pci_get_drvdata(ha->pdev); 2159 host_int = rd_reg_dword(®->host_int); 2160 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2161 goto out; 2162 qla24xx_process_response_queue(vha, rsp); 2163 wrt_reg_dword(®->host_int, 0); 2164 out: 2165 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2166 return IRQ_HANDLED; 2167 } 2168 2169 void 2170 qla82xx_poll(int irq, void *dev_id) 2171 { 2172 scsi_qla_host_t *vha; 2173 struct qla_hw_data *ha; 2174 struct rsp_que *rsp; 2175 struct device_reg_82xx __iomem *reg; 2176 int status = 0; 2177 uint32_t stat; 2178 uint32_t host_int = 0; 2179 uint16_t mb[8]; 2180 unsigned long flags; 2181 2182 rsp = (struct rsp_que *) dev_id; 2183 if (!rsp) { 2184 printk(KERN_INFO 2185 "%s(): NULL response queue pointer.\n", __func__); 2186 return; 2187 } 2188 ha = rsp->hw; 2189 2190 reg = &ha->iobase->isp82; 2191 spin_lock_irqsave(&ha->hardware_lock, flags); 2192 vha = pci_get_drvdata(ha->pdev); 2193 2194 host_int = rd_reg_dword(®->host_int); 2195 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2196 goto out; 2197 if (host_int) { 2198 stat = rd_reg_dword(®->host_status); 2199 switch (stat & 0xff) { 2200 case 0x1: 2201 case 0x2: 2202 case 0x10: 2203 case 0x11: 2204 qla82xx_mbx_completion(vha, MSW(stat)); 2205 status |= MBX_INTERRUPT; 2206 break; 2207 case 0x12: 2208 mb[0] = MSW(stat); 2209 mb[1] = rd_reg_word(®->mailbox_out[1]); 2210 mb[2] = rd_reg_word(®->mailbox_out[2]); 2211 mb[3] = rd_reg_word(®->mailbox_out[3]); 2212 qla2x00_async_event(vha, rsp, mb); 2213 break; 2214 case 0x13: 2215 qla24xx_process_response_queue(vha, rsp); 2216 break; 2217 default: 2218 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2219 "Unrecognized interrupt type (%d).\n", 2220 stat * 0xff); 2221 break; 2222 } 2223 wrt_reg_dword(®->host_int, 0); 2224 } 2225 out: 2226 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2227 } 2228 2229 void 2230 qla82xx_enable_intrs(struct qla_hw_data *ha) 2231 { 2232 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2233 2234 qla82xx_mbx_intr_enable(vha); 2235 spin_lock_irq(&ha->hardware_lock); 2236 if (IS_QLA8044(ha)) 2237 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2238 else 2239 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2240 spin_unlock_irq(&ha->hardware_lock); 2241 ha->interrupts_on = 1; 2242 } 2243 2244 void 2245 qla82xx_disable_intrs(struct qla_hw_data *ha) 2246 { 2247 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2248 2249 if (ha->interrupts_on) 2250 qla82xx_mbx_intr_disable(vha); 2251 2252 spin_lock_irq(&ha->hardware_lock); 2253 if (IS_QLA8044(ha)) 2254 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2255 else 2256 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2257 spin_unlock_irq(&ha->hardware_lock); 2258 ha->interrupts_on = 0; 2259 } 2260 2261 void qla82xx_init_flags(struct qla_hw_data *ha) 2262 { 2263 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2264 2265 /* ISP 8021 initializations */ 2266 rwlock_init(&ha->hw_lock); 2267 ha->qdr_sn_window = -1; 2268 ha->ddr_mn_window = -1; 2269 ha->curr_window = 255; 2270 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2271 nx_legacy_intr = &legacy_intr[ha->portnum]; 2272 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2273 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2274 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2275 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2276 } 2277 2278 static inline void 2279 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2280 { 2281 int idc_ver; 2282 uint32_t drv_active; 2283 struct qla_hw_data *ha = vha->hw; 2284 2285 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2286 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2287 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2288 QLA82XX_IDC_VERSION); 2289 ql_log(ql_log_info, vha, 0xb082, 2290 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2291 } else { 2292 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2293 if (idc_ver != QLA82XX_IDC_VERSION) 2294 ql_log(ql_log_info, vha, 0xb083, 2295 "qla2xxx driver IDC version %d is not compatible " 2296 "with IDC version %d of the other drivers\n", 2297 QLA82XX_IDC_VERSION, idc_ver); 2298 } 2299 } 2300 2301 inline void 2302 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2303 { 2304 uint32_t drv_active; 2305 struct qla_hw_data *ha = vha->hw; 2306 2307 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2308 2309 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2310 if (drv_active == 0xffffffff) { 2311 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2312 QLA82XX_DRV_NOT_ACTIVE); 2313 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2314 } 2315 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2316 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2317 } 2318 2319 inline void 2320 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2321 { 2322 uint32_t drv_active; 2323 2324 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2325 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2326 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2327 } 2328 2329 static inline int 2330 qla82xx_need_reset(struct qla_hw_data *ha) 2331 { 2332 uint32_t drv_state; 2333 int rval; 2334 2335 if (ha->flags.nic_core_reset_owner) 2336 return 1; 2337 else { 2338 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2339 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2340 return rval; 2341 } 2342 } 2343 2344 static inline void 2345 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2346 { 2347 uint32_t drv_state; 2348 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2349 2350 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2351 2352 /* If reset value is all FF's, initialize DRV_STATE */ 2353 if (drv_state == 0xffffffff) { 2354 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2355 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2356 } 2357 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2358 ql_dbg(ql_dbg_init, vha, 0x00bb, 2359 "drv_state = 0x%08x.\n", drv_state); 2360 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2361 } 2362 2363 static inline void 2364 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2365 { 2366 uint32_t drv_state; 2367 2368 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2369 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2370 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2371 } 2372 2373 static inline void 2374 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2375 { 2376 uint32_t qsnt_state; 2377 2378 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2379 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2380 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2381 } 2382 2383 void 2384 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2385 { 2386 struct qla_hw_data *ha = vha->hw; 2387 uint32_t qsnt_state; 2388 2389 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2390 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2391 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2392 } 2393 2394 static int 2395 qla82xx_load_fw(scsi_qla_host_t *vha) 2396 { 2397 int rst; 2398 struct fw_blob *blob; 2399 struct qla_hw_data *ha = vha->hw; 2400 2401 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2402 ql_log(ql_log_fatal, vha, 0x009f, 2403 "Error during CRB initialization.\n"); 2404 return QLA_FUNCTION_FAILED; 2405 } 2406 udelay(500); 2407 2408 /* Bring QM and CAMRAM out of reset */ 2409 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2410 rst &= ~((1 << 28) | (1 << 24)); 2411 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2412 2413 /* 2414 * FW Load priority: 2415 * 1) Operational firmware residing in flash. 2416 * 2) Firmware via request-firmware interface (.bin file). 2417 */ 2418 if (ql2xfwloadbin == 2) 2419 goto try_blob_fw; 2420 2421 ql_log(ql_log_info, vha, 0x00a0, 2422 "Attempting to load firmware from flash.\n"); 2423 2424 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2425 ql_log(ql_log_info, vha, 0x00a1, 2426 "Firmware loaded successfully from flash.\n"); 2427 return QLA_SUCCESS; 2428 } else { 2429 ql_log(ql_log_warn, vha, 0x0108, 2430 "Firmware load from flash failed.\n"); 2431 } 2432 2433 try_blob_fw: 2434 ql_log(ql_log_info, vha, 0x00a2, 2435 "Attempting to load firmware from blob.\n"); 2436 2437 /* Load firmware blob. */ 2438 blob = ha->hablob = qla2x00_request_firmware(vha); 2439 if (!blob) { 2440 ql_log(ql_log_fatal, vha, 0x00a3, 2441 "Firmware image not present.\n"); 2442 goto fw_load_failed; 2443 } 2444 2445 /* Validating firmware blob */ 2446 if (qla82xx_validate_firmware_blob(vha, 2447 QLA82XX_FLASH_ROMIMAGE)) { 2448 /* Fallback to URI format */ 2449 if (qla82xx_validate_firmware_blob(vha, 2450 QLA82XX_UNIFIED_ROMIMAGE)) { 2451 ql_log(ql_log_fatal, vha, 0x00a4, 2452 "No valid firmware image found.\n"); 2453 return QLA_FUNCTION_FAILED; 2454 } 2455 } 2456 2457 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2458 ql_log(ql_log_info, vha, 0x00a5, 2459 "Firmware loaded successfully from binary blob.\n"); 2460 return QLA_SUCCESS; 2461 } 2462 2463 ql_log(ql_log_fatal, vha, 0x00a6, 2464 "Firmware load failed for binary blob.\n"); 2465 blob->fw = NULL; 2466 blob = NULL; 2467 2468 fw_load_failed: 2469 return QLA_FUNCTION_FAILED; 2470 } 2471 2472 int 2473 qla82xx_start_firmware(scsi_qla_host_t *vha) 2474 { 2475 uint16_t lnk; 2476 struct qla_hw_data *ha = vha->hw; 2477 2478 /* scrub dma mask expansion register */ 2479 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2480 2481 /* Put both the PEG CMD and RCV PEG to default state 2482 * of 0 before resetting the hardware 2483 */ 2484 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2485 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2486 2487 /* Overwrite stale initialization register values */ 2488 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2489 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2490 2491 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2492 ql_log(ql_log_fatal, vha, 0x00a7, 2493 "Error trying to start fw.\n"); 2494 return QLA_FUNCTION_FAILED; 2495 } 2496 2497 /* Handshake with the card before we register the devices. */ 2498 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2499 ql_log(ql_log_fatal, vha, 0x00aa, 2500 "Error during card handshake.\n"); 2501 return QLA_FUNCTION_FAILED; 2502 } 2503 2504 /* Negotiated Link width */ 2505 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2506 ha->link_width = (lnk >> 4) & 0x3f; 2507 2508 /* Synchronize with Receive peg */ 2509 return qla82xx_check_rcvpeg_state(ha); 2510 } 2511 2512 static __le32 * 2513 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 2514 uint32_t length) 2515 { 2516 uint32_t i; 2517 uint32_t val; 2518 struct qla_hw_data *ha = vha->hw; 2519 2520 /* Dword reads to flash. */ 2521 for (i = 0; i < length/4; i++, faddr += 4) { 2522 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2523 ql_log(ql_log_warn, vha, 0x0106, 2524 "Do ROM fast read failed.\n"); 2525 goto done_read; 2526 } 2527 dwptr[i] = cpu_to_le32(val); 2528 } 2529 done_read: 2530 return dwptr; 2531 } 2532 2533 static int 2534 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2535 { 2536 int ret; 2537 uint32_t val; 2538 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2539 2540 ret = ql82xx_rom_lock_d(ha); 2541 if (ret < 0) { 2542 ql_log(ql_log_warn, vha, 0xb014, 2543 "ROM Lock failed.\n"); 2544 return ret; 2545 } 2546 2547 ret = qla82xx_read_status_reg(ha, &val); 2548 if (ret < 0) 2549 goto done_unprotect; 2550 2551 val &= ~(BLOCK_PROTECT_BITS << 2); 2552 ret = qla82xx_write_status_reg(ha, val); 2553 if (ret < 0) { 2554 val |= (BLOCK_PROTECT_BITS << 2); 2555 qla82xx_write_status_reg(ha, val); 2556 } 2557 2558 if (qla82xx_write_disable_flash(ha) != 0) 2559 ql_log(ql_log_warn, vha, 0xb015, 2560 "Write disable failed.\n"); 2561 2562 done_unprotect: 2563 qla82xx_rom_unlock(ha); 2564 return ret; 2565 } 2566 2567 static int 2568 qla82xx_protect_flash(struct qla_hw_data *ha) 2569 { 2570 int ret; 2571 uint32_t val; 2572 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2573 2574 ret = ql82xx_rom_lock_d(ha); 2575 if (ret < 0) { 2576 ql_log(ql_log_warn, vha, 0xb016, 2577 "ROM Lock failed.\n"); 2578 return ret; 2579 } 2580 2581 ret = qla82xx_read_status_reg(ha, &val); 2582 if (ret < 0) 2583 goto done_protect; 2584 2585 val |= (BLOCK_PROTECT_BITS << 2); 2586 /* LOCK all sectors */ 2587 ret = qla82xx_write_status_reg(ha, val); 2588 if (ret < 0) 2589 ql_log(ql_log_warn, vha, 0xb017, 2590 "Write status register failed.\n"); 2591 2592 if (qla82xx_write_disable_flash(ha) != 0) 2593 ql_log(ql_log_warn, vha, 0xb018, 2594 "Write disable failed.\n"); 2595 done_protect: 2596 qla82xx_rom_unlock(ha); 2597 return ret; 2598 } 2599 2600 static int 2601 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2602 { 2603 int ret = 0; 2604 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2605 2606 ret = ql82xx_rom_lock_d(ha); 2607 if (ret < 0) { 2608 ql_log(ql_log_warn, vha, 0xb019, 2609 "ROM Lock failed.\n"); 2610 return ret; 2611 } 2612 2613 qla82xx_flash_set_write_enable(ha); 2614 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2615 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2616 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2617 2618 if (qla82xx_wait_rom_done(ha)) { 2619 ql_log(ql_log_warn, vha, 0xb01a, 2620 "Error waiting for rom done.\n"); 2621 ret = -1; 2622 goto done; 2623 } 2624 ret = qla82xx_flash_wait_write_finish(ha); 2625 done: 2626 qla82xx_rom_unlock(ha); 2627 return ret; 2628 } 2629 2630 /* 2631 * Address and length are byte address 2632 */ 2633 void * 2634 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2635 uint32_t offset, uint32_t length) 2636 { 2637 scsi_block_requests(vha->host); 2638 qla82xx_read_flash_data(vha, buf, offset, length); 2639 scsi_unblock_requests(vha->host); 2640 return buf; 2641 } 2642 2643 static int 2644 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr, 2645 uint32_t faddr, uint32_t dwords) 2646 { 2647 int ret; 2648 uint32_t liter; 2649 uint32_t rest_addr; 2650 dma_addr_t optrom_dma; 2651 void *optrom = NULL; 2652 int page_mode = 0; 2653 struct qla_hw_data *ha = vha->hw; 2654 2655 ret = -1; 2656 2657 /* Prepare burst-capable write on supported ISPs. */ 2658 if (page_mode && !(faddr & 0xfff) && 2659 dwords > OPTROM_BURST_DWORDS) { 2660 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2661 &optrom_dma, GFP_KERNEL); 2662 if (!optrom) { 2663 ql_log(ql_log_warn, vha, 0xb01b, 2664 "Unable to allocate memory " 2665 "for optrom burst write (%x KB).\n", 2666 OPTROM_BURST_SIZE / 1024); 2667 } 2668 } 2669 2670 rest_addr = ha->fdt_block_size - 1; 2671 2672 ret = qla82xx_unprotect_flash(ha); 2673 if (ret) { 2674 ql_log(ql_log_warn, vha, 0xb01c, 2675 "Unable to unprotect flash for update.\n"); 2676 goto write_done; 2677 } 2678 2679 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2680 /* Are we at the beginning of a sector? */ 2681 if ((faddr & rest_addr) == 0) { 2682 2683 ret = qla82xx_erase_sector(ha, faddr); 2684 if (ret) { 2685 ql_log(ql_log_warn, vha, 0xb01d, 2686 "Unable to erase sector: address=%x.\n", 2687 faddr); 2688 break; 2689 } 2690 } 2691 2692 /* Go with burst-write. */ 2693 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2694 /* Copy data to DMA'ble buffer. */ 2695 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2696 2697 ret = qla2x00_load_ram(vha, optrom_dma, 2698 (ha->flash_data_off | faddr), 2699 OPTROM_BURST_DWORDS); 2700 if (ret != QLA_SUCCESS) { 2701 ql_log(ql_log_warn, vha, 0xb01e, 2702 "Unable to burst-write optrom segment " 2703 "(%x/%x/%llx).\n", ret, 2704 (ha->flash_data_off | faddr), 2705 (unsigned long long)optrom_dma); 2706 ql_log(ql_log_warn, vha, 0xb01f, 2707 "Reverting to slow-write.\n"); 2708 2709 dma_free_coherent(&ha->pdev->dev, 2710 OPTROM_BURST_SIZE, optrom, optrom_dma); 2711 optrom = NULL; 2712 } else { 2713 liter += OPTROM_BURST_DWORDS - 1; 2714 faddr += OPTROM_BURST_DWORDS - 1; 2715 dwptr += OPTROM_BURST_DWORDS - 1; 2716 continue; 2717 } 2718 } 2719 2720 ret = qla82xx_write_flash_dword(ha, faddr, 2721 le32_to_cpu(*dwptr)); 2722 if (ret) { 2723 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2724 "Unable to program flash address=%x data=%x.\n", 2725 faddr, *dwptr); 2726 break; 2727 } 2728 } 2729 2730 ret = qla82xx_protect_flash(ha); 2731 if (ret) 2732 ql_log(ql_log_warn, vha, 0xb021, 2733 "Unable to protect flash after update.\n"); 2734 write_done: 2735 if (optrom) 2736 dma_free_coherent(&ha->pdev->dev, 2737 OPTROM_BURST_SIZE, optrom, optrom_dma); 2738 return ret; 2739 } 2740 2741 int 2742 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2743 uint32_t offset, uint32_t length) 2744 { 2745 int rval; 2746 2747 /* Suspend HBA. */ 2748 scsi_block_requests(vha->host); 2749 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2750 scsi_unblock_requests(vha->host); 2751 2752 /* Convert return ISP82xx to generic */ 2753 if (rval) 2754 rval = QLA_FUNCTION_FAILED; 2755 else 2756 rval = QLA_SUCCESS; 2757 return rval; 2758 } 2759 2760 void 2761 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2762 { 2763 struct qla_hw_data *ha = vha->hw; 2764 struct req_que *req = ha->req_q_map[0]; 2765 uint32_t dbval; 2766 2767 /* Adjust ring index. */ 2768 req->ring_index++; 2769 if (req->ring_index == req->length) { 2770 req->ring_index = 0; 2771 req->ring_ptr = req->ring; 2772 } else 2773 req->ring_ptr++; 2774 2775 dbval = 0x04 | (ha->portnum << 5); 2776 2777 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2778 if (ql2xdbwr) 2779 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2780 else { 2781 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2782 wmb(); 2783 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { 2784 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2785 wmb(); 2786 } 2787 } 2788 } 2789 2790 static void 2791 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2792 { 2793 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2794 uint32_t lock_owner = 0; 2795 2796 if (qla82xx_rom_lock(ha)) { 2797 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2798 /* Someone else is holding the lock. */ 2799 ql_log(ql_log_info, vha, 0xb022, 2800 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2801 } 2802 /* 2803 * Either we got the lock, or someone 2804 * else died while holding it. 2805 * In either case, unlock. 2806 */ 2807 qla82xx_rom_unlock(ha); 2808 } 2809 2810 /* 2811 * qla82xx_device_bootstrap 2812 * Initialize device, set DEV_READY, start fw 2813 * 2814 * Note: 2815 * IDC lock must be held upon entry 2816 * 2817 * Return: 2818 * Success : 0 2819 * Failed : 1 2820 */ 2821 static int 2822 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2823 { 2824 int rval = QLA_SUCCESS; 2825 int i; 2826 uint32_t old_count, count; 2827 struct qla_hw_data *ha = vha->hw; 2828 int need_reset = 0; 2829 2830 need_reset = qla82xx_need_reset(ha); 2831 2832 if (need_reset) { 2833 /* We are trying to perform a recovery here. */ 2834 if (ha->flags.isp82xx_fw_hung) 2835 qla82xx_rom_lock_recovery(ha); 2836 } else { 2837 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2838 for (i = 0; i < 10; i++) { 2839 msleep(200); 2840 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2841 if (count != old_count) { 2842 rval = QLA_SUCCESS; 2843 goto dev_ready; 2844 } 2845 } 2846 qla82xx_rom_lock_recovery(ha); 2847 } 2848 2849 /* set to DEV_INITIALIZING */ 2850 ql_log(ql_log_info, vha, 0x009e, 2851 "HW State: INITIALIZING.\n"); 2852 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2853 2854 qla82xx_idc_unlock(ha); 2855 rval = qla82xx_start_firmware(vha); 2856 qla82xx_idc_lock(ha); 2857 2858 if (rval != QLA_SUCCESS) { 2859 ql_log(ql_log_fatal, vha, 0x00ad, 2860 "HW State: FAILED.\n"); 2861 qla82xx_clear_drv_active(ha); 2862 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2863 return rval; 2864 } 2865 2866 dev_ready: 2867 ql_log(ql_log_info, vha, 0x00ae, 2868 "HW State: READY.\n"); 2869 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2870 2871 return QLA_SUCCESS; 2872 } 2873 2874 /* 2875 * qla82xx_need_qsnt_handler 2876 * Code to start quiescence sequence 2877 * 2878 * Note: 2879 * IDC lock must be held upon entry 2880 * 2881 * Return: void 2882 */ 2883 2884 static void 2885 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2886 { 2887 struct qla_hw_data *ha = vha->hw; 2888 uint32_t dev_state, drv_state, drv_active; 2889 unsigned long reset_timeout; 2890 2891 if (vha->flags.online) { 2892 /*Block any further I/O and wait for pending cmnds to complete*/ 2893 qla2x00_quiesce_io(vha); 2894 } 2895 2896 /* Set the quiescence ready bit */ 2897 qla82xx_set_qsnt_ready(ha); 2898 2899 /*wait for 30 secs for other functions to ack */ 2900 reset_timeout = jiffies + (30 * HZ); 2901 2902 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2903 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2904 /* Its 2 that is written when qsnt is acked, moving one bit */ 2905 drv_active = drv_active << 0x01; 2906 2907 while (drv_state != drv_active) { 2908 2909 if (time_after_eq(jiffies, reset_timeout)) { 2910 /* quiescence timeout, other functions didn't ack 2911 * changing the state to DEV_READY 2912 */ 2913 ql_log(ql_log_info, vha, 0xb023, 2914 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2915 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2916 drv_active, drv_state); 2917 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2918 QLA8XXX_DEV_READY); 2919 ql_log(ql_log_info, vha, 0xb025, 2920 "HW State: DEV_READY.\n"); 2921 qla82xx_idc_unlock(ha); 2922 qla2x00_perform_loop_resync(vha); 2923 qla82xx_idc_lock(ha); 2924 2925 qla82xx_clear_qsnt_ready(vha); 2926 return; 2927 } 2928 2929 qla82xx_idc_unlock(ha); 2930 msleep(1000); 2931 qla82xx_idc_lock(ha); 2932 2933 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2934 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2935 drv_active = drv_active << 0x01; 2936 } 2937 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2938 /* everyone acked so set the state to DEV_QUIESCENCE */ 2939 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2940 ql_log(ql_log_info, vha, 0xb026, 2941 "HW State: DEV_QUIESCENT.\n"); 2942 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2943 } 2944 } 2945 2946 /* 2947 * qla82xx_wait_for_state_change 2948 * Wait for device state to change from given current state 2949 * 2950 * Note: 2951 * IDC lock must not be held upon entry 2952 * 2953 * Return: 2954 * Changed device state. 2955 */ 2956 uint32_t 2957 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2958 { 2959 struct qla_hw_data *ha = vha->hw; 2960 uint32_t dev_state; 2961 2962 do { 2963 msleep(1000); 2964 qla82xx_idc_lock(ha); 2965 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2966 qla82xx_idc_unlock(ha); 2967 } while (dev_state == curr_state); 2968 2969 return dev_state; 2970 } 2971 2972 void 2973 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2974 { 2975 struct qla_hw_data *ha = vha->hw; 2976 2977 /* Disable the board */ 2978 ql_log(ql_log_fatal, vha, 0x00b8, 2979 "Disabling the board.\n"); 2980 2981 if (IS_QLA82XX(ha)) { 2982 qla82xx_clear_drv_active(ha); 2983 qla82xx_idc_unlock(ha); 2984 } else if (IS_QLA8044(ha)) { 2985 qla8044_clear_drv_active(ha); 2986 qla8044_idc_unlock(ha); 2987 } 2988 2989 /* Set DEV_FAILED flag to disable timer */ 2990 vha->device_flags |= DFLG_DEV_FAILED; 2991 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2992 qla2x00_mark_all_devices_lost(vha); 2993 vha->flags.online = 0; 2994 vha->flags.init_done = 0; 2995 } 2996 2997 /* 2998 * qla82xx_need_reset_handler 2999 * Code to start reset sequence 3000 * 3001 * Note: 3002 * IDC lock must be held upon entry 3003 * 3004 * Return: 3005 * Success : 0 3006 * Failed : 1 3007 */ 3008 static void 3009 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3010 { 3011 uint32_t dev_state, drv_state, drv_active; 3012 uint32_t active_mask = 0; 3013 unsigned long reset_timeout; 3014 struct qla_hw_data *ha = vha->hw; 3015 struct req_que *req = ha->req_q_map[0]; 3016 3017 if (vha->flags.online) { 3018 qla82xx_idc_unlock(ha); 3019 qla2x00_abort_isp_cleanup(vha); 3020 ha->isp_ops->get_flash_version(vha, req->ring); 3021 ha->isp_ops->nvram_config(vha); 3022 qla82xx_idc_lock(ha); 3023 } 3024 3025 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3026 if (!ha->flags.nic_core_reset_owner) { 3027 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3028 "reset_acknowledged by 0x%x\n", ha->portnum); 3029 qla82xx_set_rst_ready(ha); 3030 } else { 3031 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3032 drv_active &= active_mask; 3033 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3034 "active_mask: 0x%08x\n", active_mask); 3035 } 3036 3037 /* wait for 10 seconds for reset ack from all functions */ 3038 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3039 3040 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3041 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3042 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3043 3044 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3045 "drv_state: 0x%08x, drv_active: 0x%08x, " 3046 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3047 drv_state, drv_active, dev_state, active_mask); 3048 3049 while (drv_state != drv_active && 3050 dev_state != QLA8XXX_DEV_INITIALIZING) { 3051 if (time_after_eq(jiffies, reset_timeout)) { 3052 ql_log(ql_log_warn, vha, 0x00b5, 3053 "Reset timeout.\n"); 3054 break; 3055 } 3056 qla82xx_idc_unlock(ha); 3057 msleep(1000); 3058 qla82xx_idc_lock(ha); 3059 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3060 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3061 if (ha->flags.nic_core_reset_owner) 3062 drv_active &= active_mask; 3063 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3064 } 3065 3066 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3067 "drv_state: 0x%08x, drv_active: 0x%08x, " 3068 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3069 drv_state, drv_active, dev_state, active_mask); 3070 3071 ql_log(ql_log_info, vha, 0x00b6, 3072 "Device state is 0x%x = %s.\n", 3073 dev_state, 3074 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3075 3076 /* Force to DEV_COLD unless someone else is starting a reset */ 3077 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3078 dev_state != QLA8XXX_DEV_COLD) { 3079 ql_log(ql_log_info, vha, 0x00b7, 3080 "HW State: COLD/RE-INIT.\n"); 3081 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3082 qla82xx_set_rst_ready(ha); 3083 if (ql2xmdenable) { 3084 if (qla82xx_md_collect(vha)) 3085 ql_log(ql_log_warn, vha, 0xb02c, 3086 "Minidump not collected.\n"); 3087 } else 3088 ql_log(ql_log_warn, vha, 0xb04f, 3089 "Minidump disabled.\n"); 3090 } 3091 } 3092 3093 int 3094 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3095 { 3096 struct qla_hw_data *ha = vha->hw; 3097 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3098 int rval = QLA_SUCCESS; 3099 3100 fw_major_version = ha->fw_major_version; 3101 fw_minor_version = ha->fw_minor_version; 3102 fw_subminor_version = ha->fw_subminor_version; 3103 3104 rval = qla2x00_get_fw_version(vha); 3105 if (rval != QLA_SUCCESS) 3106 return rval; 3107 3108 if (ql2xmdenable) { 3109 if (!ha->fw_dumped) { 3110 if ((fw_major_version != ha->fw_major_version || 3111 fw_minor_version != ha->fw_minor_version || 3112 fw_subminor_version != ha->fw_subminor_version) || 3113 (ha->prev_minidump_failed)) { 3114 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3115 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3116 fw_major_version, fw_minor_version, 3117 fw_subminor_version, 3118 ha->fw_major_version, 3119 ha->fw_minor_version, 3120 ha->fw_subminor_version, 3121 ha->prev_minidump_failed); 3122 /* Release MiniDump resources */ 3123 qla82xx_md_free(vha); 3124 /* ALlocate MiniDump resources */ 3125 qla82xx_md_prep(vha); 3126 } 3127 } else 3128 ql_log(ql_log_info, vha, 0xb02e, 3129 "Firmware dump available to retrieve\n"); 3130 } 3131 return rval; 3132 } 3133 3134 3135 static int 3136 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3137 { 3138 uint32_t fw_heartbeat_counter; 3139 int status = 0; 3140 3141 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3142 QLA82XX_PEG_ALIVE_COUNTER); 3143 /* all 0xff, assume AER/EEH in progress, ignore */ 3144 if (fw_heartbeat_counter == 0xffffffff) { 3145 ql_dbg(ql_dbg_timer, vha, 0x6003, 3146 "FW heartbeat counter is 0xffffffff, " 3147 "returning status=%d.\n", status); 3148 return status; 3149 } 3150 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3151 vha->seconds_since_last_heartbeat++; 3152 /* FW not alive after 2 seconds */ 3153 if (vha->seconds_since_last_heartbeat == 2) { 3154 vha->seconds_since_last_heartbeat = 0; 3155 status = 1; 3156 } 3157 } else 3158 vha->seconds_since_last_heartbeat = 0; 3159 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3160 if (status) 3161 ql_dbg(ql_dbg_timer, vha, 0x6004, 3162 "Returning status=%d.\n", status); 3163 return status; 3164 } 3165 3166 /* 3167 * qla82xx_device_state_handler 3168 * Main state handler 3169 * 3170 * Note: 3171 * IDC lock must be held upon entry 3172 * 3173 * Return: 3174 * Success : 0 3175 * Failed : 1 3176 */ 3177 int 3178 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3179 { 3180 uint32_t dev_state; 3181 uint32_t old_dev_state; 3182 int rval = QLA_SUCCESS; 3183 unsigned long dev_init_timeout; 3184 struct qla_hw_data *ha = vha->hw; 3185 int loopcount = 0; 3186 3187 qla82xx_idc_lock(ha); 3188 if (!vha->flags.init_done) { 3189 qla82xx_set_drv_active(vha); 3190 qla82xx_set_idc_version(vha); 3191 } 3192 3193 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3194 old_dev_state = dev_state; 3195 ql_log(ql_log_info, vha, 0x009b, 3196 "Device state is 0x%x = %s.\n", 3197 dev_state, 3198 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3199 3200 /* wait for 30 seconds for device to go ready */ 3201 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3202 3203 while (1) { 3204 3205 if (time_after_eq(jiffies, dev_init_timeout)) { 3206 ql_log(ql_log_fatal, vha, 0x009c, 3207 "Device init failed.\n"); 3208 rval = QLA_FUNCTION_FAILED; 3209 break; 3210 } 3211 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3212 if (old_dev_state != dev_state) { 3213 loopcount = 0; 3214 old_dev_state = dev_state; 3215 } 3216 if (loopcount < 5) { 3217 ql_log(ql_log_info, vha, 0x009d, 3218 "Device state is 0x%x = %s.\n", 3219 dev_state, 3220 dev_state < MAX_STATES ? qdev_state(dev_state) : 3221 "Unknown"); 3222 } 3223 3224 switch (dev_state) { 3225 case QLA8XXX_DEV_READY: 3226 ha->flags.nic_core_reset_owner = 0; 3227 goto rel_lock; 3228 case QLA8XXX_DEV_COLD: 3229 rval = qla82xx_device_bootstrap(vha); 3230 break; 3231 case QLA8XXX_DEV_INITIALIZING: 3232 qla82xx_idc_unlock(ha); 3233 msleep(1000); 3234 qla82xx_idc_lock(ha); 3235 break; 3236 case QLA8XXX_DEV_NEED_RESET: 3237 if (!ql2xdontresethba) 3238 qla82xx_need_reset_handler(vha); 3239 else { 3240 qla82xx_idc_unlock(ha); 3241 msleep(1000); 3242 qla82xx_idc_lock(ha); 3243 } 3244 dev_init_timeout = jiffies + 3245 (ha->fcoe_dev_init_timeout * HZ); 3246 break; 3247 case QLA8XXX_DEV_NEED_QUIESCENT: 3248 qla82xx_need_qsnt_handler(vha); 3249 /* Reset timeout value after quiescence handler */ 3250 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3251 * HZ); 3252 break; 3253 case QLA8XXX_DEV_QUIESCENT: 3254 /* Owner will exit and other will wait for the state 3255 * to get changed 3256 */ 3257 if (ha->flags.quiesce_owner) 3258 goto rel_lock; 3259 3260 qla82xx_idc_unlock(ha); 3261 msleep(1000); 3262 qla82xx_idc_lock(ha); 3263 3264 /* Reset timeout value after quiescence handler */ 3265 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3266 * HZ); 3267 break; 3268 case QLA8XXX_DEV_FAILED: 3269 qla8xxx_dev_failed_handler(vha); 3270 rval = QLA_FUNCTION_FAILED; 3271 goto exit; 3272 default: 3273 qla82xx_idc_unlock(ha); 3274 msleep(1000); 3275 qla82xx_idc_lock(ha); 3276 } 3277 loopcount++; 3278 } 3279 rel_lock: 3280 qla82xx_idc_unlock(ha); 3281 exit: 3282 return rval; 3283 } 3284 3285 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3286 { 3287 uint32_t temp, temp_state, temp_val; 3288 struct qla_hw_data *ha = vha->hw; 3289 3290 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3291 temp_state = qla82xx_get_temp_state(temp); 3292 temp_val = qla82xx_get_temp_val(temp); 3293 3294 if (temp_state == QLA82XX_TEMP_PANIC) { 3295 ql_log(ql_log_warn, vha, 0x600e, 3296 "Device temperature %d degrees C exceeds " 3297 " maximum allowed. Hardware has been shut down.\n", 3298 temp_val); 3299 return 1; 3300 } else if (temp_state == QLA82XX_TEMP_WARN) { 3301 ql_log(ql_log_warn, vha, 0x600f, 3302 "Device temperature %d degrees C exceeds " 3303 "operating range. Immediate action needed.\n", 3304 temp_val); 3305 } 3306 return 0; 3307 } 3308 3309 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3310 { 3311 uint32_t temp; 3312 3313 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3314 return qla82xx_get_temp_val(temp); 3315 } 3316 3317 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3318 { 3319 struct qla_hw_data *ha = vha->hw; 3320 3321 if (ha->flags.mbox_busy) { 3322 ha->flags.mbox_int = 1; 3323 ha->flags.mbox_busy = 0; 3324 ql_log(ql_log_warn, vha, 0x6010, 3325 "Doing premature completion of mbx command.\n"); 3326 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3327 complete(&ha->mbx_intr_comp); 3328 } 3329 } 3330 3331 void qla82xx_watchdog(scsi_qla_host_t *vha) 3332 { 3333 uint32_t dev_state, halt_status; 3334 struct qla_hw_data *ha = vha->hw; 3335 3336 /* don't poll if reset is going on */ 3337 if (!ha->flags.nic_core_reset_hdlr_active) { 3338 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3339 if (qla82xx_check_temp(vha)) { 3340 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3341 ha->flags.isp82xx_fw_hung = 1; 3342 qla82xx_clear_pending_mbx(vha); 3343 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3344 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3345 ql_log(ql_log_warn, vha, 0x6001, 3346 "Adapter reset needed.\n"); 3347 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3348 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3349 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3350 ql_log(ql_log_warn, vha, 0x6002, 3351 "Quiescent needed.\n"); 3352 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3353 } else if (dev_state == QLA8XXX_DEV_FAILED && 3354 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3355 vha->flags.online == 1) { 3356 ql_log(ql_log_warn, vha, 0xb055, 3357 "Adapter state is failed. Offlining.\n"); 3358 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3359 ha->flags.isp82xx_fw_hung = 1; 3360 qla82xx_clear_pending_mbx(vha); 3361 } else { 3362 if (qla82xx_check_fw_alive(vha)) { 3363 ql_dbg(ql_dbg_timer, vha, 0x6011, 3364 "disabling pause transmit on port 0 & 1.\n"); 3365 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3366 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3367 halt_status = qla82xx_rd_32(ha, 3368 QLA82XX_PEG_HALT_STATUS1); 3369 ql_log(ql_log_info, vha, 0x6005, 3370 "dumping hw/fw registers:.\n " 3371 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3372 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3373 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3374 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3375 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3376 qla82xx_rd_32(ha, 3377 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3378 qla82xx_rd_32(ha, 3379 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3380 qla82xx_rd_32(ha, 3381 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3382 qla82xx_rd_32(ha, 3383 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3384 qla82xx_rd_32(ha, 3385 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3386 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3387 ql_log(ql_log_warn, vha, 0xb052, 3388 "Firmware aborted with " 3389 "error code 0x00006700. Device is " 3390 "being reset.\n"); 3391 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3392 set_bit(ISP_UNRECOVERABLE, 3393 &vha->dpc_flags); 3394 } else { 3395 ql_log(ql_log_info, vha, 0x6006, 3396 "Detect abort needed.\n"); 3397 set_bit(ISP_ABORT_NEEDED, 3398 &vha->dpc_flags); 3399 } 3400 ha->flags.isp82xx_fw_hung = 1; 3401 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3402 qla82xx_clear_pending_mbx(vha); 3403 } 3404 } 3405 } 3406 } 3407 3408 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3409 { 3410 int rval = -1; 3411 struct qla_hw_data *ha = vha->hw; 3412 3413 if (IS_QLA82XX(ha)) 3414 rval = qla82xx_device_state_handler(vha); 3415 else if (IS_QLA8044(ha)) { 3416 qla8044_idc_lock(ha); 3417 /* Decide the reset ownership */ 3418 qla83xx_reset_ownership(vha); 3419 qla8044_idc_unlock(ha); 3420 rval = qla8044_device_state_handler(vha); 3421 } 3422 return rval; 3423 } 3424 3425 void 3426 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3427 { 3428 struct qla_hw_data *ha = vha->hw; 3429 uint32_t dev_state = 0; 3430 3431 if (IS_QLA82XX(ha)) 3432 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3433 else if (IS_QLA8044(ha)) 3434 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3435 3436 if (dev_state == QLA8XXX_DEV_READY) { 3437 ql_log(ql_log_info, vha, 0xb02f, 3438 "HW State: NEED RESET\n"); 3439 if (IS_QLA82XX(ha)) { 3440 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3441 QLA8XXX_DEV_NEED_RESET); 3442 ha->flags.nic_core_reset_owner = 1; 3443 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3444 "reset_owner is 0x%x\n", ha->portnum); 3445 } else if (IS_QLA8044(ha)) 3446 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3447 QLA8XXX_DEV_NEED_RESET); 3448 } else 3449 ql_log(ql_log_info, vha, 0xb031, 3450 "Device state is 0x%x = %s.\n", 3451 dev_state, 3452 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3453 } 3454 3455 /* 3456 * qla82xx_abort_isp 3457 * Resets ISP and aborts all outstanding commands. 3458 * 3459 * Input: 3460 * ha = adapter block pointer. 3461 * 3462 * Returns: 3463 * 0 = success 3464 */ 3465 int 3466 qla82xx_abort_isp(scsi_qla_host_t *vha) 3467 { 3468 int rval = -1; 3469 struct qla_hw_data *ha = vha->hw; 3470 3471 if (vha->device_flags & DFLG_DEV_FAILED) { 3472 ql_log(ql_log_warn, vha, 0x8024, 3473 "Device in failed state, exiting.\n"); 3474 return QLA_SUCCESS; 3475 } 3476 ha->flags.nic_core_reset_hdlr_active = 1; 3477 3478 qla82xx_idc_lock(ha); 3479 qla82xx_set_reset_owner(vha); 3480 qla82xx_idc_unlock(ha); 3481 3482 if (IS_QLA82XX(ha)) 3483 rval = qla82xx_device_state_handler(vha); 3484 else if (IS_QLA8044(ha)) { 3485 qla8044_idc_lock(ha); 3486 /* Decide the reset ownership */ 3487 qla83xx_reset_ownership(vha); 3488 qla8044_idc_unlock(ha); 3489 rval = qla8044_device_state_handler(vha); 3490 } 3491 3492 qla82xx_idc_lock(ha); 3493 qla82xx_clear_rst_ready(ha); 3494 qla82xx_idc_unlock(ha); 3495 3496 if (rval == QLA_SUCCESS) { 3497 ha->flags.isp82xx_fw_hung = 0; 3498 ha->flags.nic_core_reset_hdlr_active = 0; 3499 qla82xx_restart_isp(vha); 3500 } 3501 3502 if (rval) { 3503 vha->flags.online = 1; 3504 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3505 if (ha->isp_abort_cnt == 0) { 3506 ql_log(ql_log_warn, vha, 0x8027, 3507 "ISP error recover failed - board " 3508 "disabled.\n"); 3509 /* 3510 * The next call disables the board 3511 * completely. 3512 */ 3513 ha->isp_ops->reset_adapter(vha); 3514 vha->flags.online = 0; 3515 clear_bit(ISP_ABORT_RETRY, 3516 &vha->dpc_flags); 3517 rval = QLA_SUCCESS; 3518 } else { /* schedule another ISP abort */ 3519 ha->isp_abort_cnt--; 3520 ql_log(ql_log_warn, vha, 0x8036, 3521 "ISP abort - retry remaining %d.\n", 3522 ha->isp_abort_cnt); 3523 rval = QLA_FUNCTION_FAILED; 3524 } 3525 } else { 3526 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3527 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3528 "ISP error recovery - retrying (%d) more times.\n", 3529 ha->isp_abort_cnt); 3530 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3531 rval = QLA_FUNCTION_FAILED; 3532 } 3533 } 3534 return rval; 3535 } 3536 3537 /* 3538 * qla82xx_fcoe_ctx_reset 3539 * Perform a quick reset and aborts all outstanding commands. 3540 * This will only perform an FCoE context reset and avoids a full blown 3541 * chip reset. 3542 * 3543 * Input: 3544 * ha = adapter block pointer. 3545 * is_reset_path = flag for identifying the reset path. 3546 * 3547 * Returns: 3548 * 0 = success 3549 */ 3550 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3551 { 3552 int rval = QLA_FUNCTION_FAILED; 3553 3554 if (vha->flags.online) { 3555 /* Abort all outstanding commands, so as to be requeued later */ 3556 qla2x00_abort_isp_cleanup(vha); 3557 } 3558 3559 /* Stop currently executing firmware. 3560 * This will destroy existing FCoE context at the F/W end. 3561 */ 3562 qla2x00_try_to_stop_firmware(vha); 3563 3564 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3565 rval = qla82xx_restart_isp(vha); 3566 3567 return rval; 3568 } 3569 3570 /* 3571 * qla2x00_wait_for_fcoe_ctx_reset 3572 * Wait till the FCoE context is reset. 3573 * 3574 * Note: 3575 * Does context switching here. 3576 * Release SPIN_LOCK (if any) before calling this routine. 3577 * 3578 * Return: 3579 * Success (fcoe_ctx reset is done) : 0 3580 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3581 */ 3582 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3583 { 3584 int status = QLA_FUNCTION_FAILED; 3585 unsigned long wait_reset; 3586 3587 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3588 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3589 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3590 && time_before(jiffies, wait_reset)) { 3591 3592 set_current_state(TASK_UNINTERRUPTIBLE); 3593 schedule_timeout(HZ); 3594 3595 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3596 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3597 status = QLA_SUCCESS; 3598 break; 3599 } 3600 } 3601 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3602 "%s: status=%d.\n", __func__, status); 3603 3604 return status; 3605 } 3606 3607 void 3608 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3609 { 3610 int i, fw_state = 0; 3611 unsigned long flags; 3612 struct qla_hw_data *ha = vha->hw; 3613 3614 /* Check if 82XX firmware is alive or not 3615 * We may have arrived here from NEED_RESET 3616 * detection only 3617 */ 3618 if (!ha->flags.isp82xx_fw_hung) { 3619 for (i = 0; i < 2; i++) { 3620 msleep(1000); 3621 if (IS_QLA82XX(ha)) 3622 fw_state = qla82xx_check_fw_alive(vha); 3623 else if (IS_QLA8044(ha)) 3624 fw_state = qla8044_check_fw_alive(vha); 3625 if (fw_state) { 3626 ha->flags.isp82xx_fw_hung = 1; 3627 qla82xx_clear_pending_mbx(vha); 3628 break; 3629 } 3630 } 3631 } 3632 ql_dbg(ql_dbg_init, vha, 0x00b0, 3633 "Entered %s fw_hung=%d.\n", 3634 __func__, ha->flags.isp82xx_fw_hung); 3635 3636 /* Abort all commands gracefully if fw NOT hung */ 3637 if (!ha->flags.isp82xx_fw_hung) { 3638 int cnt, que; 3639 srb_t *sp; 3640 struct req_que *req; 3641 3642 spin_lock_irqsave(&ha->hardware_lock, flags); 3643 for (que = 0; que < ha->max_req_queues; que++) { 3644 req = ha->req_q_map[que]; 3645 if (!req) 3646 continue; 3647 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3648 sp = req->outstanding_cmds[cnt]; 3649 if (sp) { 3650 if ((!sp->u.scmd.crc_ctx || 3651 (sp->flags & 3652 SRB_FCP_CMND_DMA_VALID)) && 3653 !ha->flags.isp82xx_fw_hung) { 3654 spin_unlock_irqrestore( 3655 &ha->hardware_lock, flags); 3656 if (ha->isp_ops->abort_command(sp)) { 3657 ql_log(ql_log_info, vha, 3658 0x00b1, 3659 "mbx abort failed.\n"); 3660 } else { 3661 ql_log(ql_log_info, vha, 3662 0x00b2, 3663 "mbx abort success.\n"); 3664 } 3665 spin_lock_irqsave(&ha->hardware_lock, flags); 3666 } 3667 } 3668 } 3669 } 3670 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3671 3672 /* Wait for pending cmds (physical and virtual) to complete */ 3673 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3674 WAIT_HOST) == QLA_SUCCESS) { 3675 ql_dbg(ql_dbg_init, vha, 0x00b3, 3676 "Done wait for " 3677 "pending commands.\n"); 3678 } else { 3679 WARN_ON_ONCE(true); 3680 } 3681 } 3682 } 3683 3684 /* Minidump related functions */ 3685 static int 3686 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3687 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3688 { 3689 struct qla_hw_data *ha = vha->hw; 3690 struct qla82xx_md_entry_crb *crb_entry; 3691 uint32_t read_value, opcode, poll_time; 3692 uint32_t addr, index, crb_addr; 3693 unsigned long wtime; 3694 struct qla82xx_md_template_hdr *tmplt_hdr; 3695 uint32_t rval = QLA_SUCCESS; 3696 int i; 3697 3698 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3699 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3700 crb_addr = crb_entry->addr; 3701 3702 for (i = 0; i < crb_entry->op_count; i++) { 3703 opcode = crb_entry->crb_ctrl.opcode; 3704 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3705 qla82xx_md_rw_32(ha, crb_addr, 3706 crb_entry->value_1, 1); 3707 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3708 } 3709 3710 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3711 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3712 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3713 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3714 } 3715 3716 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3717 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3718 read_value &= crb_entry->value_2; 3719 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3720 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3721 read_value |= crb_entry->value_3; 3722 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3723 } 3724 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3725 } 3726 3727 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3728 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3729 read_value |= crb_entry->value_3; 3730 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3731 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3732 } 3733 3734 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3735 poll_time = crb_entry->crb_strd.poll_timeout; 3736 wtime = jiffies + poll_time; 3737 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3738 3739 do { 3740 if ((read_value & crb_entry->value_2) 3741 == crb_entry->value_1) 3742 break; 3743 else if (time_after_eq(jiffies, wtime)) { 3744 /* capturing dump failed */ 3745 rval = QLA_FUNCTION_FAILED; 3746 break; 3747 } else 3748 read_value = qla82xx_md_rw_32(ha, 3749 crb_addr, 0, 0); 3750 } while (1); 3751 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3752 } 3753 3754 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3755 if (crb_entry->crb_strd.state_index_a) { 3756 index = crb_entry->crb_strd.state_index_a; 3757 addr = tmplt_hdr->saved_state_array[index]; 3758 } else 3759 addr = crb_addr; 3760 3761 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3762 index = crb_entry->crb_ctrl.state_index_v; 3763 tmplt_hdr->saved_state_array[index] = read_value; 3764 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3765 } 3766 3767 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3768 if (crb_entry->crb_strd.state_index_a) { 3769 index = crb_entry->crb_strd.state_index_a; 3770 addr = tmplt_hdr->saved_state_array[index]; 3771 } else 3772 addr = crb_addr; 3773 3774 if (crb_entry->crb_ctrl.state_index_v) { 3775 index = crb_entry->crb_ctrl.state_index_v; 3776 read_value = 3777 tmplt_hdr->saved_state_array[index]; 3778 } else 3779 read_value = crb_entry->value_1; 3780 3781 qla82xx_md_rw_32(ha, addr, read_value, 1); 3782 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3783 } 3784 3785 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3786 index = crb_entry->crb_ctrl.state_index_v; 3787 read_value = tmplt_hdr->saved_state_array[index]; 3788 read_value <<= crb_entry->crb_ctrl.shl; 3789 read_value >>= crb_entry->crb_ctrl.shr; 3790 if (crb_entry->value_2) 3791 read_value &= crb_entry->value_2; 3792 read_value |= crb_entry->value_3; 3793 read_value += crb_entry->value_1; 3794 tmplt_hdr->saved_state_array[index] = read_value; 3795 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3796 } 3797 crb_addr += crb_entry->crb_strd.addr_stride; 3798 } 3799 return rval; 3800 } 3801 3802 static void 3803 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3804 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3805 { 3806 struct qla_hw_data *ha = vha->hw; 3807 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3808 struct qla82xx_md_entry_rdocm *ocm_hdr; 3809 __le32 *data_ptr = *d_ptr; 3810 3811 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3812 r_addr = ocm_hdr->read_addr; 3813 r_stride = ocm_hdr->read_addr_stride; 3814 loop_cnt = ocm_hdr->op_count; 3815 3816 for (i = 0; i < loop_cnt; i++) { 3817 r_value = rd_reg_dword(r_addr + ha->nx_pcibase); 3818 *data_ptr++ = cpu_to_le32(r_value); 3819 r_addr += r_stride; 3820 } 3821 *d_ptr = data_ptr; 3822 } 3823 3824 static void 3825 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3826 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3827 { 3828 struct qla_hw_data *ha = vha->hw; 3829 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3830 struct qla82xx_md_entry_mux *mux_hdr; 3831 __le32 *data_ptr = *d_ptr; 3832 3833 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3834 r_addr = mux_hdr->read_addr; 3835 s_addr = mux_hdr->select_addr; 3836 s_stride = mux_hdr->select_value_stride; 3837 s_value = mux_hdr->select_value; 3838 loop_cnt = mux_hdr->op_count; 3839 3840 for (i = 0; i < loop_cnt; i++) { 3841 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3842 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3843 *data_ptr++ = cpu_to_le32(s_value); 3844 *data_ptr++ = cpu_to_le32(r_value); 3845 s_value += s_stride; 3846 } 3847 *d_ptr = data_ptr; 3848 } 3849 3850 static void 3851 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3852 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3853 { 3854 struct qla_hw_data *ha = vha->hw; 3855 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3856 struct qla82xx_md_entry_crb *crb_hdr; 3857 __le32 *data_ptr = *d_ptr; 3858 3859 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3860 r_addr = crb_hdr->addr; 3861 r_stride = crb_hdr->crb_strd.addr_stride; 3862 loop_cnt = crb_hdr->op_count; 3863 3864 for (i = 0; i < loop_cnt; i++) { 3865 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3866 *data_ptr++ = cpu_to_le32(r_addr); 3867 *data_ptr++ = cpu_to_le32(r_value); 3868 r_addr += r_stride; 3869 } 3870 *d_ptr = data_ptr; 3871 } 3872 3873 static int 3874 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3875 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3876 { 3877 struct qla_hw_data *ha = vha->hw; 3878 uint32_t addr, r_addr, c_addr, t_r_addr; 3879 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3880 unsigned long p_wait, w_time, p_mask; 3881 uint32_t c_value_w, c_value_r; 3882 struct qla82xx_md_entry_cache *cache_hdr; 3883 int rval = QLA_FUNCTION_FAILED; 3884 __le32 *data_ptr = *d_ptr; 3885 3886 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3887 loop_count = cache_hdr->op_count; 3888 r_addr = cache_hdr->read_addr; 3889 c_addr = cache_hdr->control_addr; 3890 c_value_w = cache_hdr->cache_ctrl.write_value; 3891 3892 t_r_addr = cache_hdr->tag_reg_addr; 3893 t_value = cache_hdr->addr_ctrl.init_tag_value; 3894 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3895 p_wait = cache_hdr->cache_ctrl.poll_wait; 3896 p_mask = cache_hdr->cache_ctrl.poll_mask; 3897 3898 for (i = 0; i < loop_count; i++) { 3899 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3900 if (c_value_w) 3901 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3902 3903 if (p_mask) { 3904 w_time = jiffies + p_wait; 3905 do { 3906 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3907 if ((c_value_r & p_mask) == 0) 3908 break; 3909 else if (time_after_eq(jiffies, w_time)) { 3910 /* capturing dump failed */ 3911 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3912 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3913 "w_time: 0x%lx\n", 3914 c_value_r, p_mask, w_time); 3915 return rval; 3916 } 3917 } while (1); 3918 } 3919 3920 addr = r_addr; 3921 for (k = 0; k < r_cnt; k++) { 3922 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3923 *data_ptr++ = cpu_to_le32(r_value); 3924 addr += cache_hdr->read_ctrl.read_addr_stride; 3925 } 3926 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3927 } 3928 *d_ptr = data_ptr; 3929 return QLA_SUCCESS; 3930 } 3931 3932 static void 3933 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3934 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3935 { 3936 struct qla_hw_data *ha = vha->hw; 3937 uint32_t addr, r_addr, c_addr, t_r_addr; 3938 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3939 uint32_t c_value_w; 3940 struct qla82xx_md_entry_cache *cache_hdr; 3941 __le32 *data_ptr = *d_ptr; 3942 3943 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3944 loop_count = cache_hdr->op_count; 3945 r_addr = cache_hdr->read_addr; 3946 c_addr = cache_hdr->control_addr; 3947 c_value_w = cache_hdr->cache_ctrl.write_value; 3948 3949 t_r_addr = cache_hdr->tag_reg_addr; 3950 t_value = cache_hdr->addr_ctrl.init_tag_value; 3951 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3952 3953 for (i = 0; i < loop_count; i++) { 3954 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3955 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3956 addr = r_addr; 3957 for (k = 0; k < r_cnt; k++) { 3958 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3959 *data_ptr++ = cpu_to_le32(r_value); 3960 addr += cache_hdr->read_ctrl.read_addr_stride; 3961 } 3962 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3963 } 3964 *d_ptr = data_ptr; 3965 } 3966 3967 static void 3968 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3969 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3970 { 3971 struct qla_hw_data *ha = vha->hw; 3972 uint32_t s_addr, r_addr; 3973 uint32_t r_stride, r_value, r_cnt, qid = 0; 3974 uint32_t i, k, loop_cnt; 3975 struct qla82xx_md_entry_queue *q_hdr; 3976 __le32 *data_ptr = *d_ptr; 3977 3978 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3979 s_addr = q_hdr->select_addr; 3980 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3981 r_stride = q_hdr->rd_strd.read_addr_stride; 3982 loop_cnt = q_hdr->op_count; 3983 3984 for (i = 0; i < loop_cnt; i++) { 3985 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3986 r_addr = q_hdr->read_addr; 3987 for (k = 0; k < r_cnt; k++) { 3988 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3989 *data_ptr++ = cpu_to_le32(r_value); 3990 r_addr += r_stride; 3991 } 3992 qid += q_hdr->q_strd.queue_id_stride; 3993 } 3994 *d_ptr = data_ptr; 3995 } 3996 3997 static void 3998 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3999 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 4000 { 4001 struct qla_hw_data *ha = vha->hw; 4002 uint32_t r_addr, r_value; 4003 uint32_t i, loop_cnt; 4004 struct qla82xx_md_entry_rdrom *rom_hdr; 4005 __le32 *data_ptr = *d_ptr; 4006 4007 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4008 r_addr = rom_hdr->read_addr; 4009 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4010 4011 for (i = 0; i < loop_cnt; i++) { 4012 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4013 (r_addr & 0xFFFF0000), 1); 4014 r_value = qla82xx_md_rw_32(ha, 4015 MD_DIRECT_ROM_READ_BASE + 4016 (r_addr & 0x0000FFFF), 0, 0); 4017 *data_ptr++ = cpu_to_le32(r_value); 4018 r_addr += sizeof(uint32_t); 4019 } 4020 *d_ptr = data_ptr; 4021 } 4022 4023 static int 4024 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4025 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 4026 { 4027 struct qla_hw_data *ha = vha->hw; 4028 uint32_t r_addr, r_value, r_data; 4029 uint32_t i, j, loop_cnt; 4030 struct qla82xx_md_entry_rdmem *m_hdr; 4031 unsigned long flags; 4032 int rval = QLA_FUNCTION_FAILED; 4033 __le32 *data_ptr = *d_ptr; 4034 4035 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4036 r_addr = m_hdr->read_addr; 4037 loop_cnt = m_hdr->read_data_size/16; 4038 4039 if (r_addr & 0xf) { 4040 ql_log(ql_log_warn, vha, 0xb033, 4041 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4042 return rval; 4043 } 4044 4045 if (m_hdr->read_data_size % 16) { 4046 ql_log(ql_log_warn, vha, 0xb034, 4047 "Read data[0x%x] not multiple of 16 bytes\n", 4048 m_hdr->read_data_size); 4049 return rval; 4050 } 4051 4052 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4053 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4054 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4055 4056 write_lock_irqsave(&ha->hw_lock, flags); 4057 for (i = 0; i < loop_cnt; i++) { 4058 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4059 r_value = 0; 4060 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4061 r_value = MIU_TA_CTL_ENABLE; 4062 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4063 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4064 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4065 4066 for (j = 0; j < MAX_CTL_CHECK; j++) { 4067 r_value = qla82xx_md_rw_32(ha, 4068 MD_MIU_TEST_AGT_CTRL, 0, 0); 4069 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4070 break; 4071 } 4072 4073 if (j >= MAX_CTL_CHECK) { 4074 printk_ratelimited(KERN_ERR 4075 "failed to read through agent\n"); 4076 write_unlock_irqrestore(&ha->hw_lock, flags); 4077 return rval; 4078 } 4079 4080 for (j = 0; j < 4; j++) { 4081 r_data = qla82xx_md_rw_32(ha, 4082 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4083 *data_ptr++ = cpu_to_le32(r_data); 4084 } 4085 r_addr += 16; 4086 } 4087 write_unlock_irqrestore(&ha->hw_lock, flags); 4088 *d_ptr = data_ptr; 4089 return QLA_SUCCESS; 4090 } 4091 4092 int 4093 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4094 { 4095 struct qla_hw_data *ha = vha->hw; 4096 uint64_t chksum = 0; 4097 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4098 int count = ha->md_template_size/sizeof(uint32_t); 4099 4100 while (count-- > 0) 4101 chksum += *d_ptr++; 4102 while (chksum >> 32) 4103 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4104 return ~chksum; 4105 } 4106 4107 static void 4108 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4109 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4110 { 4111 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4112 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4113 "Skipping entry[%d]: " 4114 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4115 index, entry_hdr->entry_type, 4116 entry_hdr->d_ctrl.entry_capture_mask); 4117 } 4118 4119 int 4120 qla82xx_md_collect(scsi_qla_host_t *vha) 4121 { 4122 struct qla_hw_data *ha = vha->hw; 4123 int no_entry_hdr = 0; 4124 qla82xx_md_entry_hdr_t *entry_hdr; 4125 struct qla82xx_md_template_hdr *tmplt_hdr; 4126 __le32 *data_ptr; 4127 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4128 int i = 0, rval = QLA_FUNCTION_FAILED; 4129 4130 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4131 data_ptr = ha->md_dump; 4132 4133 if (ha->fw_dumped) { 4134 ql_log(ql_log_warn, vha, 0xb037, 4135 "Firmware has been previously dumped (%p) " 4136 "-- ignoring request.\n", ha->fw_dump); 4137 goto md_failed; 4138 } 4139 4140 ha->fw_dumped = false; 4141 4142 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4143 ql_log(ql_log_warn, vha, 0xb038, 4144 "Memory not allocated for minidump capture\n"); 4145 goto md_failed; 4146 } 4147 4148 if (ha->flags.isp82xx_no_md_cap) { 4149 ql_log(ql_log_warn, vha, 0xb054, 4150 "Forced reset from application, " 4151 "ignore minidump capture\n"); 4152 ha->flags.isp82xx_no_md_cap = 0; 4153 goto md_failed; 4154 } 4155 4156 if (qla82xx_validate_template_chksum(vha)) { 4157 ql_log(ql_log_info, vha, 0xb039, 4158 "Template checksum validation error\n"); 4159 goto md_failed; 4160 } 4161 4162 no_entry_hdr = tmplt_hdr->num_of_entries; 4163 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4164 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4165 4166 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4167 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4168 4169 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4170 4171 /* Validate whether required debug level is set */ 4172 if ((f_capture_mask & 0x3) != 0x3) { 4173 ql_log(ql_log_warn, vha, 0xb03c, 4174 "Minimum required capture mask[0x%x] level not set\n", 4175 f_capture_mask); 4176 goto md_failed; 4177 } 4178 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4179 4180 tmplt_hdr->driver_info[0] = vha->host_no; 4181 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4182 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4183 QLA_DRIVER_BETA_VER; 4184 4185 total_data_size = ha->md_dump_size; 4186 4187 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4188 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4189 4190 /* Check whether template obtained is valid */ 4191 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4192 ql_log(ql_log_warn, vha, 0xb04e, 4193 "Bad template header entry type: 0x%x obtained\n", 4194 tmplt_hdr->entry_type); 4195 goto md_failed; 4196 } 4197 4198 entry_hdr = (qla82xx_md_entry_hdr_t *) 4199 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4200 4201 /* Walk through the entry headers */ 4202 for (i = 0; i < no_entry_hdr; i++) { 4203 4204 if (data_collected > total_data_size) { 4205 ql_log(ql_log_warn, vha, 0xb03e, 4206 "More MiniDump data collected: [0x%x]\n", 4207 data_collected); 4208 goto md_failed; 4209 } 4210 4211 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4212 ql2xmdcapmask)) { 4213 entry_hdr->d_ctrl.driver_flags |= 4214 QLA82XX_DBG_SKIPPED_FLAG; 4215 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4216 "Skipping entry[%d]: " 4217 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4218 i, entry_hdr->entry_type, 4219 entry_hdr->d_ctrl.entry_capture_mask); 4220 goto skip_nxt_entry; 4221 } 4222 4223 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4224 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4225 "entry_type: 0x%x, capture_mask: 0x%x\n", 4226 __func__, i, data_ptr, entry_hdr, 4227 entry_hdr->entry_type, 4228 entry_hdr->d_ctrl.entry_capture_mask); 4229 4230 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4231 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4232 data_collected, (ha->md_dump_size - data_collected)); 4233 4234 /* Decode the entry type and take 4235 * required action to capture debug data */ 4236 switch (entry_hdr->entry_type) { 4237 case QLA82XX_RDEND: 4238 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4239 break; 4240 case QLA82XX_CNTRL: 4241 rval = qla82xx_minidump_process_control(vha, 4242 entry_hdr, &data_ptr); 4243 if (rval != QLA_SUCCESS) { 4244 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4245 goto md_failed; 4246 } 4247 break; 4248 case QLA82XX_RDCRB: 4249 qla82xx_minidump_process_rdcrb(vha, 4250 entry_hdr, &data_ptr); 4251 break; 4252 case QLA82XX_RDMEM: 4253 rval = qla82xx_minidump_process_rdmem(vha, 4254 entry_hdr, &data_ptr); 4255 if (rval != QLA_SUCCESS) { 4256 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4257 goto md_failed; 4258 } 4259 break; 4260 case QLA82XX_BOARD: 4261 case QLA82XX_RDROM: 4262 qla82xx_minidump_process_rdrom(vha, 4263 entry_hdr, &data_ptr); 4264 break; 4265 case QLA82XX_L2DTG: 4266 case QLA82XX_L2ITG: 4267 case QLA82XX_L2DAT: 4268 case QLA82XX_L2INS: 4269 rval = qla82xx_minidump_process_l2tag(vha, 4270 entry_hdr, &data_ptr); 4271 if (rval != QLA_SUCCESS) { 4272 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4273 goto md_failed; 4274 } 4275 break; 4276 case QLA82XX_L1DAT: 4277 case QLA82XX_L1INS: 4278 qla82xx_minidump_process_l1cache(vha, 4279 entry_hdr, &data_ptr); 4280 break; 4281 case QLA82XX_RDOCM: 4282 qla82xx_minidump_process_rdocm(vha, 4283 entry_hdr, &data_ptr); 4284 break; 4285 case QLA82XX_RDMUX: 4286 qla82xx_minidump_process_rdmux(vha, 4287 entry_hdr, &data_ptr); 4288 break; 4289 case QLA82XX_QUEUE: 4290 qla82xx_minidump_process_queue(vha, 4291 entry_hdr, &data_ptr); 4292 break; 4293 case QLA82XX_RDNOP: 4294 default: 4295 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4296 break; 4297 } 4298 4299 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4300 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4301 4302 data_collected = (uint8_t *)data_ptr - 4303 (uint8_t *)ha->md_dump; 4304 skip_nxt_entry: 4305 entry_hdr = (qla82xx_md_entry_hdr_t *) 4306 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4307 } 4308 4309 if (data_collected != total_data_size) { 4310 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4311 "MiniDump data mismatch: Data collected: [0x%x]," 4312 "total_data_size:[0x%x]\n", 4313 data_collected, total_data_size); 4314 goto md_failed; 4315 } 4316 4317 ql_log(ql_log_info, vha, 0xb044, 4318 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4319 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4320 ha->fw_dumped = true; 4321 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4322 4323 md_failed: 4324 return rval; 4325 } 4326 4327 int 4328 qla82xx_md_alloc(scsi_qla_host_t *vha) 4329 { 4330 struct qla_hw_data *ha = vha->hw; 4331 int i, k; 4332 struct qla82xx_md_template_hdr *tmplt_hdr; 4333 4334 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4335 4336 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4337 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4338 ql_log(ql_log_info, vha, 0xb045, 4339 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4340 ql2xmdcapmask); 4341 } 4342 4343 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4344 if (i & ql2xmdcapmask) 4345 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4346 } 4347 4348 if (ha->md_dump) { 4349 ql_log(ql_log_warn, vha, 0xb046, 4350 "Firmware dump previously allocated.\n"); 4351 return 1; 4352 } 4353 4354 ha->md_dump = vmalloc(ha->md_dump_size); 4355 if (ha->md_dump == NULL) { 4356 ql_log(ql_log_warn, vha, 0xb047, 4357 "Unable to allocate memory for Minidump size " 4358 "(0x%x).\n", ha->md_dump_size); 4359 return 1; 4360 } 4361 return 0; 4362 } 4363 4364 void 4365 qla82xx_md_free(scsi_qla_host_t *vha) 4366 { 4367 struct qla_hw_data *ha = vha->hw; 4368 4369 /* Release the template header allocated */ 4370 if (ha->md_tmplt_hdr) { 4371 ql_log(ql_log_info, vha, 0xb048, 4372 "Free MiniDump template: %p, size (%d KB)\n", 4373 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4374 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4375 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4376 ha->md_tmplt_hdr = NULL; 4377 } 4378 4379 /* Release the template data buffer allocated */ 4380 if (ha->md_dump) { 4381 ql_log(ql_log_info, vha, 0xb049, 4382 "Free MiniDump memory: %p, size (%d KB)\n", 4383 ha->md_dump, ha->md_dump_size / 1024); 4384 vfree(ha->md_dump); 4385 ha->md_dump_size = 0; 4386 ha->md_dump = NULL; 4387 } 4388 } 4389 4390 void 4391 qla82xx_md_prep(scsi_qla_host_t *vha) 4392 { 4393 struct qla_hw_data *ha = vha->hw; 4394 int rval; 4395 4396 /* Get Minidump template size */ 4397 rval = qla82xx_md_get_template_size(vha); 4398 if (rval == QLA_SUCCESS) { 4399 ql_log(ql_log_info, vha, 0xb04a, 4400 "MiniDump Template size obtained (%d KB)\n", 4401 ha->md_template_size / 1024); 4402 4403 /* Get Minidump template */ 4404 if (IS_QLA8044(ha)) 4405 rval = qla8044_md_get_template(vha); 4406 else 4407 rval = qla82xx_md_get_template(vha); 4408 4409 if (rval == QLA_SUCCESS) { 4410 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4411 "MiniDump Template obtained\n"); 4412 4413 /* Allocate memory for minidump */ 4414 rval = qla82xx_md_alloc(vha); 4415 if (rval == QLA_SUCCESS) 4416 ql_log(ql_log_info, vha, 0xb04c, 4417 "MiniDump memory allocated (%d KB)\n", 4418 ha->md_dump_size / 1024); 4419 else { 4420 ql_log(ql_log_info, vha, 0xb04d, 4421 "Free MiniDump template: %p, size: (%d KB)\n", 4422 ha->md_tmplt_hdr, 4423 ha->md_template_size / 1024); 4424 dma_free_coherent(&ha->pdev->dev, 4425 ha->md_template_size, 4426 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4427 ha->md_tmplt_hdr = NULL; 4428 } 4429 4430 } 4431 } 4432 } 4433 4434 int 4435 qla82xx_beacon_on(struct scsi_qla_host *vha) 4436 { 4437 4438 int rval; 4439 struct qla_hw_data *ha = vha->hw; 4440 4441 qla82xx_idc_lock(ha); 4442 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4443 4444 if (rval) { 4445 ql_log(ql_log_warn, vha, 0xb050, 4446 "mbx set led config failed in %s\n", __func__); 4447 goto exit; 4448 } 4449 ha->beacon_blink_led = 1; 4450 exit: 4451 qla82xx_idc_unlock(ha); 4452 return rval; 4453 } 4454 4455 int 4456 qla82xx_beacon_off(struct scsi_qla_host *vha) 4457 { 4458 4459 int rval; 4460 struct qla_hw_data *ha = vha->hw; 4461 4462 qla82xx_idc_lock(ha); 4463 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4464 4465 if (rval) { 4466 ql_log(ql_log_warn, vha, 0xb051, 4467 "mbx set led config failed in %s\n", __func__); 4468 goto exit; 4469 } 4470 ha->beacon_blink_led = 0; 4471 exit: 4472 qla82xx_idc_unlock(ha); 4473 return rval; 4474 } 4475 4476 void 4477 qla82xx_fw_dump(scsi_qla_host_t *vha) 4478 { 4479 struct qla_hw_data *ha = vha->hw; 4480 4481 if (!ha->allow_cna_fw_dump) 4482 return; 4483 4484 scsi_block_requests(vha->host); 4485 ha->flags.isp82xx_no_md_cap = 1; 4486 qla82xx_idc_lock(ha); 4487 qla82xx_set_reset_owner(vha); 4488 qla82xx_idc_unlock(ha); 4489 qla2x00_wait_for_chip_reset(vha); 4490 scsi_unblock_requests(vha->host); 4491 } 4492