1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 const int MD_MIU_TEST_AGT_RDDATA[] = { 46 0x410000A8, 0x410000AC, 47 0x410000B8, 0x410000BC 48 }; 49 50 static void qla82xx_crb_addr_transform_setup(void) 51 { 52 qla82xx_crb_addr_transform(XDMA); 53 qla82xx_crb_addr_transform(TIMR); 54 qla82xx_crb_addr_transform(SRE); 55 qla82xx_crb_addr_transform(SQN3); 56 qla82xx_crb_addr_transform(SQN2); 57 qla82xx_crb_addr_transform(SQN1); 58 qla82xx_crb_addr_transform(SQN0); 59 qla82xx_crb_addr_transform(SQS3); 60 qla82xx_crb_addr_transform(SQS2); 61 qla82xx_crb_addr_transform(SQS1); 62 qla82xx_crb_addr_transform(SQS0); 63 qla82xx_crb_addr_transform(RPMX7); 64 qla82xx_crb_addr_transform(RPMX6); 65 qla82xx_crb_addr_transform(RPMX5); 66 qla82xx_crb_addr_transform(RPMX4); 67 qla82xx_crb_addr_transform(RPMX3); 68 qla82xx_crb_addr_transform(RPMX2); 69 qla82xx_crb_addr_transform(RPMX1); 70 qla82xx_crb_addr_transform(RPMX0); 71 qla82xx_crb_addr_transform(ROMUSB); 72 qla82xx_crb_addr_transform(SN); 73 qla82xx_crb_addr_transform(QMN); 74 qla82xx_crb_addr_transform(QMS); 75 qla82xx_crb_addr_transform(PGNI); 76 qla82xx_crb_addr_transform(PGND); 77 qla82xx_crb_addr_transform(PGN3); 78 qla82xx_crb_addr_transform(PGN2); 79 qla82xx_crb_addr_transform(PGN1); 80 qla82xx_crb_addr_transform(PGN0); 81 qla82xx_crb_addr_transform(PGSI); 82 qla82xx_crb_addr_transform(PGSD); 83 qla82xx_crb_addr_transform(PGS3); 84 qla82xx_crb_addr_transform(PGS2); 85 qla82xx_crb_addr_transform(PGS1); 86 qla82xx_crb_addr_transform(PGS0); 87 qla82xx_crb_addr_transform(PS); 88 qla82xx_crb_addr_transform(PH); 89 qla82xx_crb_addr_transform(NIU); 90 qla82xx_crb_addr_transform(I2Q); 91 qla82xx_crb_addr_transform(EG); 92 qla82xx_crb_addr_transform(MN); 93 qla82xx_crb_addr_transform(MS); 94 qla82xx_crb_addr_transform(CAS2); 95 qla82xx_crb_addr_transform(CAS1); 96 qla82xx_crb_addr_transform(CAS0); 97 qla82xx_crb_addr_transform(CAM); 98 qla82xx_crb_addr_transform(C2C1); 99 qla82xx_crb_addr_transform(C2C0); 100 qla82xx_crb_addr_transform(SMB); 101 qla82xx_crb_addr_transform(OCM0); 102 /* 103 * Used only in P3 just define it for P2 also. 104 */ 105 qla82xx_crb_addr_transform(I2C0); 106 107 qla82xx_crb_table_initialized = 1; 108 } 109 110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 111 {{{0, 0, 0, 0} } }, 112 {{{1, 0x0100000, 0x0102000, 0x120000}, 113 {1, 0x0110000, 0x0120000, 0x130000}, 114 {1, 0x0120000, 0x0122000, 0x124000}, 115 {1, 0x0130000, 0x0132000, 0x126000}, 116 {1, 0x0140000, 0x0142000, 0x128000}, 117 {1, 0x0150000, 0x0152000, 0x12a000}, 118 {1, 0x0160000, 0x0170000, 0x110000}, 119 {1, 0x0170000, 0x0172000, 0x12e000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {1, 0x01e0000, 0x01e0800, 0x122000}, 127 {0, 0x0000000, 0x0000000, 0x000000} } } , 128 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 129 {{{0, 0, 0, 0} } }, 130 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 131 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 134 {{{1, 0x0800000, 0x0802000, 0x170000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 150 {{{1, 0x0900000, 0x0902000, 0x174000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 166 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 182 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 203 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 204 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 205 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 206 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 207 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 208 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{0, 0, 0, 0} } }, 211 {{{0, 0, 0, 0} } }, 212 {{{0, 0, 0, 0} } }, 213 {{{0, 0, 0, 0} } }, 214 {{{0, 0, 0, 0} } }, 215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 218 {{{0} } }, 219 {{{1, 0x2100000, 0x2102000, 0x120000}, 220 {1, 0x2110000, 0x2120000, 0x130000}, 221 {1, 0x2120000, 0x2122000, 0x124000}, 222 {1, 0x2130000, 0x2132000, 0x126000}, 223 {1, 0x2140000, 0x2142000, 0x128000}, 224 {1, 0x2150000, 0x2152000, 0x12a000}, 225 {1, 0x2160000, 0x2170000, 0x110000}, 226 {1, 0x2170000, 0x2172000, 0x12e000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000} } }, 235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 236 {{{0} } }, 237 {{{0} } }, 238 {{{0} } }, 239 {{{0} } }, 240 {{{0} } }, 241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 242 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 253 {{{0} } }, 254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 260 {{{0} } }, 261 {{{0} } }, 262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 265 }; 266 267 /* 268 * top 12 bits of crb internal address (hub, agent) 269 */ 270 static unsigned qla82xx_crb_hub_agt[64] = { 271 0, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 275 0, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 301 0, 302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 303 0, 304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 306 0, 307 0, 308 0, 309 0, 310 0, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 312 0, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 328 0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 332 0, 333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 334 0, 335 }; 336 337 /* Device states */ 338 static char *q_dev_state[] = { 339 "Unknown", 340 "Cold", 341 "Initializing", 342 "Ready", 343 "Need Reset", 344 "Need Quiescent", 345 "Failed", 346 "Quiescent", 347 }; 348 349 char *qdev_state(uint32_t dev_state) 350 { 351 return q_dev_state[dev_state]; 352 } 353 354 /* 355 * In: 'off_in' is offset from CRB space in 128M pci map 356 * Out: 'off_out' is 2M pci map addr 357 * side effect: lock crb window 358 */ 359 static void 360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 361 void __iomem **off_out) 362 { 363 u32 win_read; 364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 365 366 ha->crb_win = CRB_HI(off_in); 367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 368 369 /* Read back value to make sure write has gone through before trying 370 * to use it. 371 */ 372 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 373 if (win_read != ha->crb_win) { 374 ql_dbg(ql_dbg_p3p, vha, 0xb000, 375 "%s: Written crbwin (0x%x) " 376 "!= Read crbwin (0x%x), off=0x%lx.\n", 377 __func__, ha->crb_win, win_read, off_in); 378 } 379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 380 } 381 382 static inline unsigned long 383 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 384 { 385 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 386 /* See if we are currently pointing to the region we want to use next */ 387 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 388 /* No need to change window. PCIX and PCIEregs are in both 389 * regs are in both windows. 390 */ 391 return off; 392 } 393 394 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 395 /* We are in first CRB window */ 396 if (ha->curr_window != 0) 397 WARN_ON(1); 398 return off; 399 } 400 401 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 402 /* We are in second CRB window */ 403 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 404 405 if (ha->curr_window != 1) 406 return off; 407 408 /* We are in the QM or direct access 409 * register region - do nothing 410 */ 411 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 412 (off < QLA82XX_PCI_CAMQM_MAX)) 413 return off; 414 } 415 /* strange address given */ 416 ql_dbg(ql_dbg_p3p, vha, 0xb001, 417 "%s: Warning: unm_nic_pci_set_crbwindow " 418 "called with an unknown address(%llx).\n", 419 QLA2XXX_DRIVER_NAME, off); 420 return off; 421 } 422 423 static int 424 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 425 void __iomem **off_out) 426 { 427 struct crb_128M_2M_sub_block_map *m; 428 429 if (off_in >= QLA82XX_CRB_MAX) 430 return -1; 431 432 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 433 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 434 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 435 return 0; 436 } 437 438 if (off_in < QLA82XX_PCI_CRBSPACE) 439 return -1; 440 441 off_in -= QLA82XX_PCI_CRBSPACE; 442 443 /* Try direct map */ 444 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 445 446 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 447 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 448 return 0; 449 } 450 /* Not in direct map, use crb window */ 451 *off_out = (void __iomem *)off_in; 452 return 1; 453 } 454 455 #define CRB_WIN_LOCK_TIMEOUT 100000000 456 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 457 { 458 int done = 0, timeout = 0; 459 460 while (!done) { 461 /* acquire semaphore3 from PCI HW block */ 462 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 463 if (done == 1) 464 break; 465 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 466 return -1; 467 timeout++; 468 } 469 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 470 return 0; 471 } 472 473 int 474 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 475 { 476 void __iomem *off; 477 unsigned long flags = 0; 478 int rv; 479 480 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 481 482 BUG_ON(rv == -1); 483 484 if (rv == 1) { 485 #ifndef __CHECKER__ 486 write_lock_irqsave(&ha->hw_lock, flags); 487 #endif 488 qla82xx_crb_win_lock(ha); 489 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 490 } 491 492 writel(data, (void __iomem *)off); 493 494 if (rv == 1) { 495 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 496 #ifndef __CHECKER__ 497 write_unlock_irqrestore(&ha->hw_lock, flags); 498 #endif 499 } 500 return 0; 501 } 502 503 int 504 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 505 { 506 void __iomem *off; 507 unsigned long flags = 0; 508 int rv; 509 u32 data; 510 511 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 512 513 BUG_ON(rv == -1); 514 515 if (rv == 1) { 516 #ifndef __CHECKER__ 517 write_lock_irqsave(&ha->hw_lock, flags); 518 #endif 519 qla82xx_crb_win_lock(ha); 520 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 521 } 522 data = RD_REG_DWORD(off); 523 524 if (rv == 1) { 525 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 526 #ifndef __CHECKER__ 527 write_unlock_irqrestore(&ha->hw_lock, flags); 528 #endif 529 } 530 return data; 531 } 532 533 #define IDC_LOCK_TIMEOUT 100000000 534 int qla82xx_idc_lock(struct qla_hw_data *ha) 535 { 536 int i; 537 int done = 0, timeout = 0; 538 539 while (!done) { 540 /* acquire semaphore5 from PCI HW block */ 541 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 542 if (done == 1) 543 break; 544 if (timeout >= IDC_LOCK_TIMEOUT) 545 return -1; 546 547 timeout++; 548 549 /* Yield CPU */ 550 if (!in_interrupt()) 551 schedule(); 552 else { 553 for (i = 0; i < 20; i++) 554 cpu_relax(); 555 } 556 } 557 558 return 0; 559 } 560 561 void qla82xx_idc_unlock(struct qla_hw_data *ha) 562 { 563 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 564 } 565 566 /* 567 * check memory access boundary. 568 * used by test agent. support ddr access only for now 569 */ 570 static unsigned long 571 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 572 unsigned long long addr, int size) 573 { 574 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 575 QLA82XX_ADDR_DDR_NET_MAX) || 576 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 577 QLA82XX_ADDR_DDR_NET_MAX) || 578 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 579 return 0; 580 else 581 return 1; 582 } 583 584 static int qla82xx_pci_set_window_warning_count; 585 586 static unsigned long 587 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 588 { 589 int window; 590 u32 win_read; 591 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 592 593 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 594 QLA82XX_ADDR_DDR_NET_MAX)) { 595 /* DDR network side */ 596 window = MN_WIN(addr); 597 ha->ddr_mn_window = window; 598 qla82xx_wr_32(ha, 599 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 600 win_read = qla82xx_rd_32(ha, 601 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 602 if ((win_read << 17) != window) { 603 ql_dbg(ql_dbg_p3p, vha, 0xb003, 604 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 605 __func__, window, win_read); 606 } 607 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 608 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 609 QLA82XX_ADDR_OCM0_MAX)) { 610 unsigned int temp1; 611 if ((addr & 0x00ff800) == 0xff800) { 612 ql_log(ql_log_warn, vha, 0xb004, 613 "%s: QM access not handled.\n", __func__); 614 addr = -1UL; 615 } 616 window = OCM_WIN(addr); 617 ha->ddr_mn_window = window; 618 qla82xx_wr_32(ha, 619 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 620 win_read = qla82xx_rd_32(ha, 621 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 622 temp1 = ((window & 0x1FF) << 7) | 623 ((window & 0x0FFFE0000) >> 17); 624 if (win_read != temp1) { 625 ql_log(ql_log_warn, vha, 0xb005, 626 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 627 __func__, temp1, win_read); 628 } 629 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 630 631 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 632 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 633 /* QDR network side */ 634 window = MS_WIN(addr); 635 ha->qdr_sn_window = window; 636 qla82xx_wr_32(ha, 637 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 638 win_read = qla82xx_rd_32(ha, 639 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 640 if (win_read != window) { 641 ql_log(ql_log_warn, vha, 0xb006, 642 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 643 __func__, window, win_read); 644 } 645 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 646 } else { 647 /* 648 * peg gdb frequently accesses memory that doesn't exist, 649 * this limits the chit chat so debugging isn't slowed down. 650 */ 651 if ((qla82xx_pci_set_window_warning_count++ < 8) || 652 (qla82xx_pci_set_window_warning_count%64 == 0)) { 653 ql_log(ql_log_warn, vha, 0xb007, 654 "%s: Warning:%s Unknown address range!.\n", 655 __func__, QLA2XXX_DRIVER_NAME); 656 } 657 addr = -1UL; 658 } 659 return addr; 660 } 661 662 /* check if address is in the same windows as the previous access */ 663 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 664 unsigned long long addr) 665 { 666 int window; 667 unsigned long long qdr_max; 668 669 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 670 671 /* DDR network side */ 672 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 673 QLA82XX_ADDR_DDR_NET_MAX)) 674 BUG(); 675 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 676 QLA82XX_ADDR_OCM0_MAX)) 677 return 1; 678 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 679 QLA82XX_ADDR_OCM1_MAX)) 680 return 1; 681 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 682 /* QDR network side */ 683 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 684 if (ha->qdr_sn_window == window) 685 return 1; 686 } 687 return 0; 688 } 689 690 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 691 u64 off, void *data, int size) 692 { 693 unsigned long flags; 694 void __iomem *addr = NULL; 695 int ret = 0; 696 u64 start; 697 uint8_t __iomem *mem_ptr = NULL; 698 unsigned long mem_base; 699 unsigned long mem_page; 700 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 701 702 write_lock_irqsave(&ha->hw_lock, flags); 703 704 /* 705 * If attempting to access unknown address or straddle hw windows, 706 * do not access. 707 */ 708 start = qla82xx_pci_set_window(ha, off); 709 if ((start == -1UL) || 710 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 711 write_unlock_irqrestore(&ha->hw_lock, flags); 712 ql_log(ql_log_fatal, vha, 0xb008, 713 "%s out of bound pci memory " 714 "access, offset is 0x%llx.\n", 715 QLA2XXX_DRIVER_NAME, off); 716 return -1; 717 } 718 719 write_unlock_irqrestore(&ha->hw_lock, flags); 720 mem_base = pci_resource_start(ha->pdev, 0); 721 mem_page = start & PAGE_MASK; 722 /* Map two pages whenever user tries to access addresses in two 723 * consecutive pages. 724 */ 725 if (mem_page != ((start + size - 1) & PAGE_MASK)) 726 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 727 else 728 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 729 if (mem_ptr == NULL) { 730 *(u8 *)data = 0; 731 return -1; 732 } 733 addr = mem_ptr; 734 addr += start & (PAGE_SIZE - 1); 735 write_lock_irqsave(&ha->hw_lock, flags); 736 737 switch (size) { 738 case 1: 739 *(u8 *)data = readb(addr); 740 break; 741 case 2: 742 *(u16 *)data = readw(addr); 743 break; 744 case 4: 745 *(u32 *)data = readl(addr); 746 break; 747 case 8: 748 *(u64 *)data = readq(addr); 749 break; 750 default: 751 ret = -1; 752 break; 753 } 754 write_unlock_irqrestore(&ha->hw_lock, flags); 755 756 if (mem_ptr) 757 iounmap(mem_ptr); 758 return ret; 759 } 760 761 static int 762 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 763 u64 off, void *data, int size) 764 { 765 unsigned long flags; 766 void __iomem *addr = NULL; 767 int ret = 0; 768 u64 start; 769 uint8_t __iomem *mem_ptr = NULL; 770 unsigned long mem_base; 771 unsigned long mem_page; 772 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 773 774 write_lock_irqsave(&ha->hw_lock, flags); 775 776 /* 777 * If attempting to access unknown address or straddle hw windows, 778 * do not access. 779 */ 780 start = qla82xx_pci_set_window(ha, off); 781 if ((start == -1UL) || 782 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 783 write_unlock_irqrestore(&ha->hw_lock, flags); 784 ql_log(ql_log_fatal, vha, 0xb009, 785 "%s out of bound memory " 786 "access, offset is 0x%llx.\n", 787 QLA2XXX_DRIVER_NAME, off); 788 return -1; 789 } 790 791 write_unlock_irqrestore(&ha->hw_lock, flags); 792 mem_base = pci_resource_start(ha->pdev, 0); 793 mem_page = start & PAGE_MASK; 794 /* Map two pages whenever user tries to access addresses in two 795 * consecutive pages. 796 */ 797 if (mem_page != ((start + size - 1) & PAGE_MASK)) 798 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 799 else 800 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 801 if (mem_ptr == NULL) 802 return -1; 803 804 addr = mem_ptr; 805 addr += start & (PAGE_SIZE - 1); 806 write_lock_irqsave(&ha->hw_lock, flags); 807 808 switch (size) { 809 case 1: 810 writeb(*(u8 *)data, addr); 811 break; 812 case 2: 813 writew(*(u16 *)data, addr); 814 break; 815 case 4: 816 writel(*(u32 *)data, addr); 817 break; 818 case 8: 819 writeq(*(u64 *)data, addr); 820 break; 821 default: 822 ret = -1; 823 break; 824 } 825 write_unlock_irqrestore(&ha->hw_lock, flags); 826 if (mem_ptr) 827 iounmap(mem_ptr); 828 return ret; 829 } 830 831 #define MTU_FUDGE_FACTOR 100 832 static unsigned long 833 qla82xx_decode_crb_addr(unsigned long addr) 834 { 835 int i; 836 unsigned long base_addr, offset, pci_base; 837 838 if (!qla82xx_crb_table_initialized) 839 qla82xx_crb_addr_transform_setup(); 840 841 pci_base = ADDR_ERROR; 842 base_addr = addr & 0xfff00000; 843 offset = addr & 0x000fffff; 844 845 for (i = 0; i < MAX_CRB_XFORM; i++) { 846 if (crb_addr_xform[i] == base_addr) { 847 pci_base = i << 20; 848 break; 849 } 850 } 851 if (pci_base == ADDR_ERROR) 852 return pci_base; 853 return pci_base + offset; 854 } 855 856 static long rom_max_timeout = 100; 857 static long qla82xx_rom_lock_timeout = 100; 858 859 static int 860 qla82xx_rom_lock(struct qla_hw_data *ha) 861 { 862 int done = 0, timeout = 0; 863 uint32_t lock_owner = 0; 864 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 865 866 while (!done) { 867 /* acquire semaphore2 from PCI HW block */ 868 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 869 if (done == 1) 870 break; 871 if (timeout >= qla82xx_rom_lock_timeout) { 872 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 873 ql_dbg(ql_dbg_p3p, vha, 0xb157, 874 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 875 __func__, ha->portnum, lock_owner); 876 return -1; 877 } 878 timeout++; 879 } 880 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 881 return 0; 882 } 883 884 static void 885 qla82xx_rom_unlock(struct qla_hw_data *ha) 886 { 887 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 888 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 889 } 890 891 static int 892 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 893 { 894 long timeout = 0; 895 long done = 0 ; 896 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 897 898 while (done == 0) { 899 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 900 done &= 4; 901 timeout++; 902 if (timeout >= rom_max_timeout) { 903 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 904 "%s: Timeout reached waiting for rom busy.\n", 905 QLA2XXX_DRIVER_NAME); 906 return -1; 907 } 908 } 909 return 0; 910 } 911 912 static int 913 qla82xx_wait_rom_done(struct qla_hw_data *ha) 914 { 915 long timeout = 0; 916 long done = 0 ; 917 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 918 919 while (done == 0) { 920 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 921 done &= 2; 922 timeout++; 923 if (timeout >= rom_max_timeout) { 924 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 925 "%s: Timeout reached waiting for rom done.\n", 926 QLA2XXX_DRIVER_NAME); 927 return -1; 928 } 929 } 930 return 0; 931 } 932 933 static int 934 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 935 { 936 uint32_t off_value, rval = 0; 937 938 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 939 940 /* Read back value to make sure write has gone through */ 941 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 942 off_value = (off & 0x0000FFFF); 943 944 if (flag) 945 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 946 data); 947 else 948 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M + 949 ha->nx_pcibase); 950 951 return rval; 952 } 953 954 static int 955 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 956 { 957 /* Dword reads to flash. */ 958 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 959 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 960 (addr & 0x0000FFFF), 0, 0); 961 962 return 0; 963 } 964 965 static int 966 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 967 { 968 int ret, loops = 0; 969 uint32_t lock_owner = 0; 970 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 971 972 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 973 udelay(100); 974 schedule(); 975 loops++; 976 } 977 if (loops >= 50000) { 978 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 979 ql_log(ql_log_fatal, vha, 0x00b9, 980 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 981 lock_owner); 982 return -1; 983 } 984 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 985 qla82xx_rom_unlock(ha); 986 return ret; 987 } 988 989 static int 990 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 991 { 992 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 993 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 994 qla82xx_wait_rom_busy(ha); 995 if (qla82xx_wait_rom_done(ha)) { 996 ql_log(ql_log_warn, vha, 0xb00c, 997 "Error waiting for rom done.\n"); 998 return -1; 999 } 1000 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1001 return 0; 1002 } 1003 1004 static int 1005 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 1006 { 1007 long timeout = 0; 1008 uint32_t done = 1 ; 1009 uint32_t val; 1010 int ret = 0; 1011 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1012 1013 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1014 while ((done != 0) && (ret == 0)) { 1015 ret = qla82xx_read_status_reg(ha, &val); 1016 done = val & 1; 1017 timeout++; 1018 udelay(10); 1019 cond_resched(); 1020 if (timeout >= 50000) { 1021 ql_log(ql_log_warn, vha, 0xb00d, 1022 "Timeout reached waiting for write finish.\n"); 1023 return -1; 1024 } 1025 } 1026 return ret; 1027 } 1028 1029 static int 1030 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1031 { 1032 uint32_t val; 1033 qla82xx_wait_rom_busy(ha); 1034 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1035 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1036 qla82xx_wait_rom_busy(ha); 1037 if (qla82xx_wait_rom_done(ha)) 1038 return -1; 1039 if (qla82xx_read_status_reg(ha, &val) != 0) 1040 return -1; 1041 if ((val & 2) != 2) 1042 return -1; 1043 return 0; 1044 } 1045 1046 static int 1047 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1048 { 1049 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1050 if (qla82xx_flash_set_write_enable(ha)) 1051 return -1; 1052 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1053 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1054 if (qla82xx_wait_rom_done(ha)) { 1055 ql_log(ql_log_warn, vha, 0xb00e, 1056 "Error waiting for rom done.\n"); 1057 return -1; 1058 } 1059 return qla82xx_flash_wait_write_finish(ha); 1060 } 1061 1062 static int 1063 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1064 { 1065 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1066 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1067 if (qla82xx_wait_rom_done(ha)) { 1068 ql_log(ql_log_warn, vha, 0xb00f, 1069 "Error waiting for rom done.\n"); 1070 return -1; 1071 } 1072 return 0; 1073 } 1074 1075 static int 1076 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1077 { 1078 int loops = 0; 1079 uint32_t lock_owner = 0; 1080 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1081 1082 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1083 udelay(100); 1084 cond_resched(); 1085 loops++; 1086 } 1087 if (loops >= 50000) { 1088 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1089 ql_log(ql_log_warn, vha, 0xb010, 1090 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1091 return -1; 1092 } 1093 return 0; 1094 } 1095 1096 static int 1097 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1098 uint32_t data) 1099 { 1100 int ret = 0; 1101 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1102 1103 ret = ql82xx_rom_lock_d(ha); 1104 if (ret < 0) { 1105 ql_log(ql_log_warn, vha, 0xb011, 1106 "ROM lock failed.\n"); 1107 return ret; 1108 } 1109 1110 if (qla82xx_flash_set_write_enable(ha)) 1111 goto done_write; 1112 1113 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1114 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1115 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1116 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1117 qla82xx_wait_rom_busy(ha); 1118 if (qla82xx_wait_rom_done(ha)) { 1119 ql_log(ql_log_warn, vha, 0xb012, 1120 "Error waiting for rom done.\n"); 1121 ret = -1; 1122 goto done_write; 1123 } 1124 1125 ret = qla82xx_flash_wait_write_finish(ha); 1126 1127 done_write: 1128 qla82xx_rom_unlock(ha); 1129 return ret; 1130 } 1131 1132 /* This routine does CRB initialize sequence 1133 * to put the ISP into operational state 1134 */ 1135 static int 1136 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1137 { 1138 int addr, val; 1139 int i ; 1140 struct crb_addr_pair *buf; 1141 unsigned long off; 1142 unsigned offset, n; 1143 struct qla_hw_data *ha = vha->hw; 1144 1145 struct crb_addr_pair { 1146 long addr; 1147 long data; 1148 }; 1149 1150 /* Halt all the individual PEGs and other blocks of the ISP */ 1151 qla82xx_rom_lock(ha); 1152 1153 /* disable all I2Q */ 1154 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1155 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1156 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1157 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1160 1161 /* disable all niu interrupts */ 1162 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1163 /* disable xge rx/tx */ 1164 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1165 /* disable xg1 rx/tx */ 1166 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1167 /* disable sideband mac */ 1168 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1169 /* disable ap0 mac */ 1170 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1171 /* disable ap1 mac */ 1172 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1173 1174 /* halt sre */ 1175 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1176 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1177 1178 /* halt epg */ 1179 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1180 1181 /* halt timers */ 1182 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1183 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1184 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1185 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1186 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1187 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1188 1189 /* halt pegs */ 1190 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1191 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1192 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1193 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1194 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1195 msleep(20); 1196 1197 /* big hammer */ 1198 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1199 /* don't reset CAM block on reset */ 1200 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1201 else 1202 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1203 qla82xx_rom_unlock(ha); 1204 1205 /* Read the signature value from the flash. 1206 * Offset 0: Contain signature (0xcafecafe) 1207 * Offset 4: Offset and number of addr/value pairs 1208 * that present in CRB initialize sequence 1209 */ 1210 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1211 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1212 ql_log(ql_log_fatal, vha, 0x006e, 1213 "Error Reading crb_init area: n: %08x.\n", n); 1214 return -1; 1215 } 1216 1217 /* Offset in flash = lower 16 bits 1218 * Number of entries = upper 16 bits 1219 */ 1220 offset = n & 0xffffU; 1221 n = (n >> 16) & 0xffffU; 1222 1223 /* number of addr/value pair should not exceed 1024 entries */ 1224 if (n >= 1024) { 1225 ql_log(ql_log_fatal, vha, 0x0071, 1226 "Card flash not initialized:n=0x%x.\n", n); 1227 return -1; 1228 } 1229 1230 ql_log(ql_log_info, vha, 0x0072, 1231 "%d CRB init values found in ROM.\n", n); 1232 1233 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1234 if (buf == NULL) { 1235 ql_log(ql_log_fatal, vha, 0x010c, 1236 "Unable to allocate memory.\n"); 1237 return -ENOMEM; 1238 } 1239 1240 for (i = 0; i < n; i++) { 1241 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1242 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1243 kfree(buf); 1244 return -1; 1245 } 1246 1247 buf[i].addr = addr; 1248 buf[i].data = val; 1249 } 1250 1251 for (i = 0; i < n; i++) { 1252 /* Translate internal CRB initialization 1253 * address to PCI bus address 1254 */ 1255 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1256 QLA82XX_PCI_CRBSPACE; 1257 /* Not all CRB addr/value pair to be written, 1258 * some of them are skipped 1259 */ 1260 1261 /* skipping cold reboot MAGIC */ 1262 if (off == QLA82XX_CAM_RAM(0x1fc)) 1263 continue; 1264 1265 /* do not reset PCI */ 1266 if (off == (ROMUSB_GLB + 0xbc)) 1267 continue; 1268 1269 /* skip core clock, so that firmware can increase the clock */ 1270 if (off == (ROMUSB_GLB + 0xc8)) 1271 continue; 1272 1273 /* skip the function enable register */ 1274 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1275 continue; 1276 1277 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1278 continue; 1279 1280 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1281 continue; 1282 1283 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1284 continue; 1285 1286 if (off == ADDR_ERROR) { 1287 ql_log(ql_log_fatal, vha, 0x0116, 1288 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1289 continue; 1290 } 1291 1292 qla82xx_wr_32(ha, off, buf[i].data); 1293 1294 /* ISP requires much bigger delay to settle down, 1295 * else crb_window returns 0xffffffff 1296 */ 1297 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1298 msleep(1000); 1299 1300 /* ISP requires millisec delay between 1301 * successive CRB register updation 1302 */ 1303 msleep(1); 1304 } 1305 1306 kfree(buf); 1307 1308 /* Resetting the data and instruction cache */ 1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1311 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1312 1313 /* Clear all protocol processing engines */ 1314 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1316 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1317 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1318 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1319 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1320 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1321 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1322 return 0; 1323 } 1324 1325 static int 1326 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1327 u64 off, void *data, int size) 1328 { 1329 int i, j, ret = 0, loop, sz[2], off0; 1330 int scale, shift_amount, startword; 1331 uint32_t temp; 1332 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1333 1334 /* 1335 * If not MN, go check for MS or invalid. 1336 */ 1337 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1338 mem_crb = QLA82XX_CRB_QDR_NET; 1339 else { 1340 mem_crb = QLA82XX_CRB_DDR_NET; 1341 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1342 return qla82xx_pci_mem_write_direct(ha, 1343 off, data, size); 1344 } 1345 1346 off0 = off & 0x7; 1347 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1348 sz[1] = size - sz[0]; 1349 1350 off8 = off & 0xfffffff0; 1351 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1352 shift_amount = 4; 1353 scale = 2; 1354 startword = (off & 0xf)/8; 1355 1356 for (i = 0; i < loop; i++) { 1357 if (qla82xx_pci_mem_read_2M(ha, off8 + 1358 (i << shift_amount), &word[i * scale], 8)) 1359 return -1; 1360 } 1361 1362 switch (size) { 1363 case 1: 1364 tmpw = *((uint8_t *)data); 1365 break; 1366 case 2: 1367 tmpw = *((uint16_t *)data); 1368 break; 1369 case 4: 1370 tmpw = *((uint32_t *)data); 1371 break; 1372 case 8: 1373 default: 1374 tmpw = *((uint64_t *)data); 1375 break; 1376 } 1377 1378 if (sz[0] == 8) { 1379 word[startword] = tmpw; 1380 } else { 1381 word[startword] &= 1382 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1383 word[startword] |= tmpw << (off0 * 8); 1384 } 1385 if (sz[1] != 0) { 1386 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1387 word[startword+1] |= tmpw >> (sz[0] * 8); 1388 } 1389 1390 for (i = 0; i < loop; i++) { 1391 temp = off8 + (i << shift_amount); 1392 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1393 temp = 0; 1394 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1395 temp = word[i * scale] & 0xffffffff; 1396 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1397 temp = (word[i * scale] >> 32) & 0xffffffff; 1398 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1399 temp = word[i*scale + 1] & 0xffffffff; 1400 qla82xx_wr_32(ha, mem_crb + 1401 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1402 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1403 qla82xx_wr_32(ha, mem_crb + 1404 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1405 1406 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1407 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1408 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1409 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1410 1411 for (j = 0; j < MAX_CTL_CHECK; j++) { 1412 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1413 if ((temp & MIU_TA_CTL_BUSY) == 0) 1414 break; 1415 } 1416 1417 if (j >= MAX_CTL_CHECK) { 1418 if (printk_ratelimit()) 1419 dev_err(&ha->pdev->dev, 1420 "failed to write through agent.\n"); 1421 ret = -1; 1422 break; 1423 } 1424 } 1425 1426 return ret; 1427 } 1428 1429 static int 1430 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1431 { 1432 int i; 1433 long size = 0; 1434 long flashaddr = ha->flt_region_bootload << 2; 1435 long memaddr = BOOTLD_START; 1436 u64 data; 1437 u32 high, low; 1438 size = (IMAGE_START - BOOTLD_START) / 8; 1439 1440 for (i = 0; i < size; i++) { 1441 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1442 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1443 return -1; 1444 } 1445 data = ((u64)high << 32) | low ; 1446 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1447 flashaddr += 8; 1448 memaddr += 8; 1449 1450 if (i % 0x1000 == 0) 1451 msleep(1); 1452 } 1453 udelay(100); 1454 read_lock(&ha->hw_lock); 1455 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1456 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1457 read_unlock(&ha->hw_lock); 1458 return 0; 1459 } 1460 1461 int 1462 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1463 u64 off, void *data, int size) 1464 { 1465 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1466 int shift_amount; 1467 uint32_t temp; 1468 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1469 1470 /* 1471 * If not MN, go check for MS or invalid. 1472 */ 1473 1474 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1475 mem_crb = QLA82XX_CRB_QDR_NET; 1476 else { 1477 mem_crb = QLA82XX_CRB_DDR_NET; 1478 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1479 return qla82xx_pci_mem_read_direct(ha, 1480 off, data, size); 1481 } 1482 1483 off8 = off & 0xfffffff0; 1484 off0[0] = off & 0xf; 1485 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1486 shift_amount = 4; 1487 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1488 off0[1] = 0; 1489 sz[1] = size - sz[0]; 1490 1491 for (i = 0; i < loop; i++) { 1492 temp = off8 + (i << shift_amount); 1493 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1494 temp = 0; 1495 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1496 temp = MIU_TA_CTL_ENABLE; 1497 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1498 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1499 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1500 1501 for (j = 0; j < MAX_CTL_CHECK; j++) { 1502 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1503 if ((temp & MIU_TA_CTL_BUSY) == 0) 1504 break; 1505 } 1506 1507 if (j >= MAX_CTL_CHECK) { 1508 if (printk_ratelimit()) 1509 dev_err(&ha->pdev->dev, 1510 "failed to read through agent.\n"); 1511 break; 1512 } 1513 1514 start = off0[i] >> 2; 1515 end = (off0[i] + sz[i] - 1) >> 2; 1516 for (k = start; k <= end; k++) { 1517 temp = qla82xx_rd_32(ha, 1518 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1519 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1520 } 1521 } 1522 1523 if (j >= MAX_CTL_CHECK) 1524 return -1; 1525 1526 if ((off0[0] & 7) == 0) { 1527 val = word[0]; 1528 } else { 1529 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1530 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1531 } 1532 1533 switch (size) { 1534 case 1: 1535 *(uint8_t *)data = val; 1536 break; 1537 case 2: 1538 *(uint16_t *)data = val; 1539 break; 1540 case 4: 1541 *(uint32_t *)data = val; 1542 break; 1543 case 8: 1544 *(uint64_t *)data = val; 1545 break; 1546 } 1547 return 0; 1548 } 1549 1550 1551 static struct qla82xx_uri_table_desc * 1552 qla82xx_get_table_desc(const u8 *unirom, int section) 1553 { 1554 uint32_t i; 1555 struct qla82xx_uri_table_desc *directory = 1556 (struct qla82xx_uri_table_desc *)&unirom[0]; 1557 __le32 offset; 1558 __le32 tab_type; 1559 __le32 entries = cpu_to_le32(directory->num_entries); 1560 1561 for (i = 0; i < entries; i++) { 1562 offset = cpu_to_le32(directory->findex) + 1563 (i * cpu_to_le32(directory->entry_size)); 1564 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1565 1566 if (tab_type == section) 1567 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1568 } 1569 1570 return NULL; 1571 } 1572 1573 static struct qla82xx_uri_data_desc * 1574 qla82xx_get_data_desc(struct qla_hw_data *ha, 1575 u32 section, u32 idx_offset) 1576 { 1577 const u8 *unirom = ha->hablob->fw->data; 1578 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1579 struct qla82xx_uri_table_desc *tab_desc = NULL; 1580 __le32 offset; 1581 1582 tab_desc = qla82xx_get_table_desc(unirom, section); 1583 if (!tab_desc) 1584 return NULL; 1585 1586 offset = cpu_to_le32(tab_desc->findex) + 1587 (cpu_to_le32(tab_desc->entry_size) * idx); 1588 1589 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1590 } 1591 1592 static u8 * 1593 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1594 { 1595 u32 offset = BOOTLD_START; 1596 struct qla82xx_uri_data_desc *uri_desc = NULL; 1597 1598 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1599 uri_desc = qla82xx_get_data_desc(ha, 1600 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1601 if (uri_desc) 1602 offset = cpu_to_le32(uri_desc->findex); 1603 } 1604 1605 return (u8 *)&ha->hablob->fw->data[offset]; 1606 } 1607 1608 static __le32 1609 qla82xx_get_fw_size(struct qla_hw_data *ha) 1610 { 1611 struct qla82xx_uri_data_desc *uri_desc = NULL; 1612 1613 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1614 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1615 QLA82XX_URI_FIRMWARE_IDX_OFF); 1616 if (uri_desc) 1617 return cpu_to_le32(uri_desc->size); 1618 } 1619 1620 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1621 } 1622 1623 static u8 * 1624 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1625 { 1626 u32 offset = IMAGE_START; 1627 struct qla82xx_uri_data_desc *uri_desc = NULL; 1628 1629 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1630 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1631 QLA82XX_URI_FIRMWARE_IDX_OFF); 1632 if (uri_desc) 1633 offset = cpu_to_le32(uri_desc->findex); 1634 } 1635 1636 return (u8 *)&ha->hablob->fw->data[offset]; 1637 } 1638 1639 /* PCI related functions */ 1640 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1641 { 1642 unsigned long val = 0; 1643 u32 control; 1644 1645 switch (region) { 1646 case 0: 1647 val = 0; 1648 break; 1649 case 1: 1650 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1651 val = control + QLA82XX_MSIX_TBL_SPACE; 1652 break; 1653 } 1654 return val; 1655 } 1656 1657 1658 int 1659 qla82xx_iospace_config(struct qla_hw_data *ha) 1660 { 1661 uint32_t len = 0; 1662 1663 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1664 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1665 "Failed to reserver selected regions.\n"); 1666 goto iospace_error_exit; 1667 } 1668 1669 /* Use MMIO operations for all accesses. */ 1670 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1671 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1672 "Region #0 not an MMIO resource, aborting.\n"); 1673 goto iospace_error_exit; 1674 } 1675 1676 len = pci_resource_len(ha->pdev, 0); 1677 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1678 if (!ha->nx_pcibase) { 1679 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1680 "Cannot remap pcibase MMIO, aborting.\n"); 1681 goto iospace_error_exit; 1682 } 1683 1684 /* Mapping of IO base pointer */ 1685 if (IS_QLA8044(ha)) { 1686 ha->iobase = ha->nx_pcibase; 1687 } else if (IS_QLA82XX(ha)) { 1688 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1689 } 1690 1691 if (!ql2xdbwr) { 1692 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1693 (ha->pdev->devfn << 12)), 4); 1694 if (!ha->nxdb_wr_ptr) { 1695 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1696 "Cannot remap MMIO, aborting.\n"); 1697 goto iospace_error_exit; 1698 } 1699 1700 /* Mapping of IO base pointer, 1701 * door bell read and write pointer 1702 */ 1703 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1704 (ha->pdev->devfn * 8); 1705 } else { 1706 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1707 QLA82XX_CAMRAM_DB1 : 1708 QLA82XX_CAMRAM_DB2); 1709 } 1710 1711 ha->max_req_queues = ha->max_rsp_queues = 1; 1712 ha->msix_count = ha->max_rsp_queues + 1; 1713 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1714 "nx_pci_base=%p iobase=%p " 1715 "max_req_queues=%d msix_count=%d.\n", 1716 ha->nx_pcibase, ha->iobase, 1717 ha->max_req_queues, ha->msix_count); 1718 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1719 "nx_pci_base=%p iobase=%p " 1720 "max_req_queues=%d msix_count=%d.\n", 1721 ha->nx_pcibase, ha->iobase, 1722 ha->max_req_queues, ha->msix_count); 1723 return 0; 1724 1725 iospace_error_exit: 1726 return -ENOMEM; 1727 } 1728 1729 /* GS related functions */ 1730 1731 /* Initialization related functions */ 1732 1733 /** 1734 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1735 * @vha: HA context 1736 * 1737 * Returns 0 on success. 1738 */ 1739 int 1740 qla82xx_pci_config(scsi_qla_host_t *vha) 1741 { 1742 struct qla_hw_data *ha = vha->hw; 1743 int ret; 1744 1745 pci_set_master(ha->pdev); 1746 ret = pci_set_mwi(ha->pdev); 1747 ha->chip_revision = ha->pdev->revision; 1748 ql_dbg(ql_dbg_init, vha, 0x0043, 1749 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1750 ha->chip_revision, ret); 1751 return 0; 1752 } 1753 1754 /** 1755 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1756 * @vha: HA context 1757 * 1758 * Returns 0 on success. 1759 */ 1760 void 1761 qla82xx_reset_chip(scsi_qla_host_t *vha) 1762 { 1763 struct qla_hw_data *ha = vha->hw; 1764 ha->isp_ops->disable_intrs(ha); 1765 } 1766 1767 void qla82xx_config_rings(struct scsi_qla_host *vha) 1768 { 1769 struct qla_hw_data *ha = vha->hw; 1770 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1771 struct init_cb_81xx *icb; 1772 struct req_que *req = ha->req_q_map[0]; 1773 struct rsp_que *rsp = ha->rsp_q_map[0]; 1774 1775 /* Setup ring parameters in initialization control block. */ 1776 icb = (struct init_cb_81xx *)ha->init_cb; 1777 icb->request_q_outpointer = cpu_to_le16(0); 1778 icb->response_q_inpointer = cpu_to_le16(0); 1779 icb->request_q_length = cpu_to_le16(req->length); 1780 icb->response_q_length = cpu_to_le16(rsp->length); 1781 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1782 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1783 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1784 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1785 1786 WRT_REG_DWORD(®->req_q_out[0], 0); 1787 WRT_REG_DWORD(®->rsp_q_in[0], 0); 1788 WRT_REG_DWORD(®->rsp_q_out[0], 0); 1789 } 1790 1791 static int 1792 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1793 { 1794 u64 *ptr64; 1795 u32 i, flashaddr, size; 1796 __le64 data; 1797 1798 size = (IMAGE_START - BOOTLD_START) / 8; 1799 1800 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1801 flashaddr = BOOTLD_START; 1802 1803 for (i = 0; i < size; i++) { 1804 data = cpu_to_le64(ptr64[i]); 1805 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1806 return -EIO; 1807 flashaddr += 8; 1808 } 1809 1810 flashaddr = FLASH_ADDR_START; 1811 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1812 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1813 1814 for (i = 0; i < size; i++) { 1815 data = cpu_to_le64(ptr64[i]); 1816 1817 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1818 return -EIO; 1819 flashaddr += 8; 1820 } 1821 udelay(100); 1822 1823 /* Write a magic value to CAMRAM register 1824 * at a specified offset to indicate 1825 * that all data is written and 1826 * ready for firmware to initialize. 1827 */ 1828 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1829 1830 read_lock(&ha->hw_lock); 1831 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1832 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1833 read_unlock(&ha->hw_lock); 1834 return 0; 1835 } 1836 1837 static int 1838 qla82xx_set_product_offset(struct qla_hw_data *ha) 1839 { 1840 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1841 const uint8_t *unirom = ha->hablob->fw->data; 1842 uint32_t i; 1843 __le32 entries; 1844 __le32 flags, file_chiprev, offset; 1845 uint8_t chiprev = ha->chip_revision; 1846 /* Hardcoding mn_present flag for P3P */ 1847 int mn_present = 0; 1848 uint32_t flagbit; 1849 1850 ptab_desc = qla82xx_get_table_desc(unirom, 1851 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1852 if (!ptab_desc) 1853 return -1; 1854 1855 entries = cpu_to_le32(ptab_desc->num_entries); 1856 1857 for (i = 0; i < entries; i++) { 1858 offset = cpu_to_le32(ptab_desc->findex) + 1859 (i * cpu_to_le32(ptab_desc->entry_size)); 1860 flags = cpu_to_le32(*((int *)&unirom[offset] + 1861 QLA82XX_URI_FLAGS_OFF)); 1862 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1863 QLA82XX_URI_CHIP_REV_OFF)); 1864 1865 flagbit = mn_present ? 1 : 2; 1866 1867 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1868 ha->file_prd_off = offset; 1869 return 0; 1870 } 1871 } 1872 return -1; 1873 } 1874 1875 static int 1876 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1877 { 1878 __le32 val; 1879 uint32_t min_size; 1880 struct qla_hw_data *ha = vha->hw; 1881 const struct firmware *fw = ha->hablob->fw; 1882 1883 ha->fw_type = fw_type; 1884 1885 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1886 if (qla82xx_set_product_offset(ha)) 1887 return -EINVAL; 1888 1889 min_size = QLA82XX_URI_FW_MIN_SIZE; 1890 } else { 1891 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1892 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1893 return -EINVAL; 1894 1895 min_size = QLA82XX_FW_MIN_SIZE; 1896 } 1897 1898 if (fw->size < min_size) 1899 return -EINVAL; 1900 return 0; 1901 } 1902 1903 static int 1904 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1905 { 1906 u32 val = 0; 1907 int retries = 60; 1908 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1909 1910 do { 1911 read_lock(&ha->hw_lock); 1912 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1913 read_unlock(&ha->hw_lock); 1914 1915 switch (val) { 1916 case PHAN_INITIALIZE_COMPLETE: 1917 case PHAN_INITIALIZE_ACK: 1918 return QLA_SUCCESS; 1919 case PHAN_INITIALIZE_FAILED: 1920 break; 1921 default: 1922 break; 1923 } 1924 ql_log(ql_log_info, vha, 0x00a8, 1925 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1926 val, retries); 1927 1928 msleep(500); 1929 1930 } while (--retries); 1931 1932 ql_log(ql_log_fatal, vha, 0x00a9, 1933 "Cmd Peg initialization failed: 0x%x.\n", val); 1934 1935 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1936 read_lock(&ha->hw_lock); 1937 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1938 read_unlock(&ha->hw_lock); 1939 return QLA_FUNCTION_FAILED; 1940 } 1941 1942 static int 1943 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1944 { 1945 u32 val = 0; 1946 int retries = 60; 1947 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1948 1949 do { 1950 read_lock(&ha->hw_lock); 1951 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1952 read_unlock(&ha->hw_lock); 1953 1954 switch (val) { 1955 case PHAN_INITIALIZE_COMPLETE: 1956 case PHAN_INITIALIZE_ACK: 1957 return QLA_SUCCESS; 1958 case PHAN_INITIALIZE_FAILED: 1959 break; 1960 default: 1961 break; 1962 } 1963 ql_log(ql_log_info, vha, 0x00ab, 1964 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1965 val, retries); 1966 1967 msleep(500); 1968 1969 } while (--retries); 1970 1971 ql_log(ql_log_fatal, vha, 0x00ac, 1972 "Rcv Peg initializatin failed: 0x%x.\n", val); 1973 read_lock(&ha->hw_lock); 1974 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1975 read_unlock(&ha->hw_lock); 1976 return QLA_FUNCTION_FAILED; 1977 } 1978 1979 /* ISR related functions */ 1980 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1981 QLA82XX_LEGACY_INTR_CONFIG; 1982 1983 /* 1984 * qla82xx_mbx_completion() - Process mailbox command completions. 1985 * @ha: SCSI driver HA context 1986 * @mb0: Mailbox0 register 1987 */ 1988 void 1989 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1990 { 1991 uint16_t cnt; 1992 uint16_t __iomem *wptr; 1993 struct qla_hw_data *ha = vha->hw; 1994 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1995 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1996 1997 /* Load return mailbox registers. */ 1998 ha->flags.mbox_int = 1; 1999 ha->mailbox_out[0] = mb0; 2000 2001 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2002 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2003 wptr++; 2004 } 2005 2006 if (!ha->mcp) 2007 ql_dbg(ql_dbg_async, vha, 0x5053, 2008 "MBX pointer ERROR.\n"); 2009 } 2010 2011 /** 2012 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2013 * @irq: 2014 * @dev_id: SCSI driver HA context 2015 * 2016 * Called by system whenever the host adapter generates an interrupt. 2017 * 2018 * Returns handled flag. 2019 */ 2020 irqreturn_t 2021 qla82xx_intr_handler(int irq, void *dev_id) 2022 { 2023 scsi_qla_host_t *vha; 2024 struct qla_hw_data *ha; 2025 struct rsp_que *rsp; 2026 struct device_reg_82xx __iomem *reg; 2027 int status = 0, status1 = 0; 2028 unsigned long flags; 2029 unsigned long iter; 2030 uint32_t stat = 0; 2031 uint16_t mb[4]; 2032 2033 rsp = (struct rsp_que *) dev_id; 2034 if (!rsp) { 2035 ql_log(ql_log_info, NULL, 0xb053, 2036 "%s: NULL response queue pointer.\n", __func__); 2037 return IRQ_NONE; 2038 } 2039 ha = rsp->hw; 2040 2041 if (!ha->flags.msi_enabled) { 2042 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2043 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2044 return IRQ_NONE; 2045 2046 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2047 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2048 return IRQ_NONE; 2049 } 2050 2051 /* clear the interrupt */ 2052 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2053 2054 /* read twice to ensure write is flushed */ 2055 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2056 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2057 2058 reg = &ha->iobase->isp82; 2059 2060 spin_lock_irqsave(&ha->hardware_lock, flags); 2061 vha = pci_get_drvdata(ha->pdev); 2062 for (iter = 1; iter--; ) { 2063 2064 if (RD_REG_DWORD(®->host_int)) { 2065 stat = RD_REG_DWORD(®->host_status); 2066 2067 switch (stat & 0xff) { 2068 case 0x1: 2069 case 0x2: 2070 case 0x10: 2071 case 0x11: 2072 qla82xx_mbx_completion(vha, MSW(stat)); 2073 status |= MBX_INTERRUPT; 2074 break; 2075 case 0x12: 2076 mb[0] = MSW(stat); 2077 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2078 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2079 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2080 qla2x00_async_event(vha, rsp, mb); 2081 break; 2082 case 0x13: 2083 qla24xx_process_response_queue(vha, rsp); 2084 break; 2085 default: 2086 ql_dbg(ql_dbg_async, vha, 0x5054, 2087 "Unrecognized interrupt type (%d).\n", 2088 stat & 0xff); 2089 break; 2090 } 2091 } 2092 WRT_REG_DWORD(®->host_int, 0); 2093 } 2094 2095 qla2x00_handle_mbx_completion(ha, status); 2096 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2097 2098 if (!ha->flags.msi_enabled) 2099 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2100 2101 return IRQ_HANDLED; 2102 } 2103 2104 irqreturn_t 2105 qla82xx_msix_default(int irq, void *dev_id) 2106 { 2107 scsi_qla_host_t *vha; 2108 struct qla_hw_data *ha; 2109 struct rsp_que *rsp; 2110 struct device_reg_82xx __iomem *reg; 2111 int status = 0; 2112 unsigned long flags; 2113 uint32_t stat = 0; 2114 uint32_t host_int = 0; 2115 uint16_t mb[4]; 2116 2117 rsp = (struct rsp_que *) dev_id; 2118 if (!rsp) { 2119 printk(KERN_INFO 2120 "%s(): NULL response queue pointer.\n", __func__); 2121 return IRQ_NONE; 2122 } 2123 ha = rsp->hw; 2124 2125 reg = &ha->iobase->isp82; 2126 2127 spin_lock_irqsave(&ha->hardware_lock, flags); 2128 vha = pci_get_drvdata(ha->pdev); 2129 do { 2130 host_int = RD_REG_DWORD(®->host_int); 2131 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2132 break; 2133 if (host_int) { 2134 stat = RD_REG_DWORD(®->host_status); 2135 2136 switch (stat & 0xff) { 2137 case 0x1: 2138 case 0x2: 2139 case 0x10: 2140 case 0x11: 2141 qla82xx_mbx_completion(vha, MSW(stat)); 2142 status |= MBX_INTERRUPT; 2143 break; 2144 case 0x12: 2145 mb[0] = MSW(stat); 2146 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2147 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2148 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2149 qla2x00_async_event(vha, rsp, mb); 2150 break; 2151 case 0x13: 2152 qla24xx_process_response_queue(vha, rsp); 2153 break; 2154 default: 2155 ql_dbg(ql_dbg_async, vha, 0x5041, 2156 "Unrecognized interrupt type (%d).\n", 2157 stat & 0xff); 2158 break; 2159 } 2160 } 2161 WRT_REG_DWORD(®->host_int, 0); 2162 } while (0); 2163 2164 qla2x00_handle_mbx_completion(ha, status); 2165 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2166 2167 return IRQ_HANDLED; 2168 } 2169 2170 irqreturn_t 2171 qla82xx_msix_rsp_q(int irq, void *dev_id) 2172 { 2173 scsi_qla_host_t *vha; 2174 struct qla_hw_data *ha; 2175 struct rsp_que *rsp; 2176 struct device_reg_82xx __iomem *reg; 2177 unsigned long flags; 2178 uint32_t host_int = 0; 2179 2180 rsp = (struct rsp_que *) dev_id; 2181 if (!rsp) { 2182 printk(KERN_INFO 2183 "%s(): NULL response queue pointer.\n", __func__); 2184 return IRQ_NONE; 2185 } 2186 2187 ha = rsp->hw; 2188 reg = &ha->iobase->isp82; 2189 spin_lock_irqsave(&ha->hardware_lock, flags); 2190 vha = pci_get_drvdata(ha->pdev); 2191 host_int = RD_REG_DWORD(®->host_int); 2192 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2193 goto out; 2194 qla24xx_process_response_queue(vha, rsp); 2195 WRT_REG_DWORD(®->host_int, 0); 2196 out: 2197 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2198 return IRQ_HANDLED; 2199 } 2200 2201 void 2202 qla82xx_poll(int irq, void *dev_id) 2203 { 2204 scsi_qla_host_t *vha; 2205 struct qla_hw_data *ha; 2206 struct rsp_que *rsp; 2207 struct device_reg_82xx __iomem *reg; 2208 int status = 0; 2209 uint32_t stat; 2210 uint32_t host_int = 0; 2211 uint16_t mb[4]; 2212 unsigned long flags; 2213 2214 rsp = (struct rsp_que *) dev_id; 2215 if (!rsp) { 2216 printk(KERN_INFO 2217 "%s(): NULL response queue pointer.\n", __func__); 2218 return; 2219 } 2220 ha = rsp->hw; 2221 2222 reg = &ha->iobase->isp82; 2223 spin_lock_irqsave(&ha->hardware_lock, flags); 2224 vha = pci_get_drvdata(ha->pdev); 2225 2226 host_int = RD_REG_DWORD(®->host_int); 2227 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2228 goto out; 2229 if (host_int) { 2230 stat = RD_REG_DWORD(®->host_status); 2231 switch (stat & 0xff) { 2232 case 0x1: 2233 case 0x2: 2234 case 0x10: 2235 case 0x11: 2236 qla82xx_mbx_completion(vha, MSW(stat)); 2237 status |= MBX_INTERRUPT; 2238 break; 2239 case 0x12: 2240 mb[0] = MSW(stat); 2241 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2242 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2243 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2244 qla2x00_async_event(vha, rsp, mb); 2245 break; 2246 case 0x13: 2247 qla24xx_process_response_queue(vha, rsp); 2248 break; 2249 default: 2250 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2251 "Unrecognized interrupt type (%d).\n", 2252 stat * 0xff); 2253 break; 2254 } 2255 WRT_REG_DWORD(®->host_int, 0); 2256 } 2257 out: 2258 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2259 } 2260 2261 void 2262 qla82xx_enable_intrs(struct qla_hw_data *ha) 2263 { 2264 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2265 qla82xx_mbx_intr_enable(vha); 2266 spin_lock_irq(&ha->hardware_lock); 2267 if (IS_QLA8044(ha)) 2268 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2269 else 2270 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2271 spin_unlock_irq(&ha->hardware_lock); 2272 ha->interrupts_on = 1; 2273 } 2274 2275 void 2276 qla82xx_disable_intrs(struct qla_hw_data *ha) 2277 { 2278 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2279 qla82xx_mbx_intr_disable(vha); 2280 spin_lock_irq(&ha->hardware_lock); 2281 if (IS_QLA8044(ha)) 2282 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2283 else 2284 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2285 spin_unlock_irq(&ha->hardware_lock); 2286 ha->interrupts_on = 0; 2287 } 2288 2289 void qla82xx_init_flags(struct qla_hw_data *ha) 2290 { 2291 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2292 2293 /* ISP 8021 initializations */ 2294 rwlock_init(&ha->hw_lock); 2295 ha->qdr_sn_window = -1; 2296 ha->ddr_mn_window = -1; 2297 ha->curr_window = 255; 2298 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2299 nx_legacy_intr = &legacy_intr[ha->portnum]; 2300 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2301 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2302 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2303 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2304 } 2305 2306 static inline void 2307 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2308 { 2309 int idc_ver; 2310 uint32_t drv_active; 2311 struct qla_hw_data *ha = vha->hw; 2312 2313 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2314 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2315 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2316 QLA82XX_IDC_VERSION); 2317 ql_log(ql_log_info, vha, 0xb082, 2318 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2319 } else { 2320 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2321 if (idc_ver != QLA82XX_IDC_VERSION) 2322 ql_log(ql_log_info, vha, 0xb083, 2323 "qla2xxx driver IDC version %d is not compatible " 2324 "with IDC version %d of the other drivers\n", 2325 QLA82XX_IDC_VERSION, idc_ver); 2326 } 2327 } 2328 2329 inline void 2330 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2331 { 2332 uint32_t drv_active; 2333 struct qla_hw_data *ha = vha->hw; 2334 2335 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2336 2337 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2338 if (drv_active == 0xffffffff) { 2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2340 QLA82XX_DRV_NOT_ACTIVE); 2341 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2342 } 2343 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2344 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2345 } 2346 2347 inline void 2348 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2349 { 2350 uint32_t drv_active; 2351 2352 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2353 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2354 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2355 } 2356 2357 static inline int 2358 qla82xx_need_reset(struct qla_hw_data *ha) 2359 { 2360 uint32_t drv_state; 2361 int rval; 2362 2363 if (ha->flags.nic_core_reset_owner) 2364 return 1; 2365 else { 2366 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2367 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2368 return rval; 2369 } 2370 } 2371 2372 static inline void 2373 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2374 { 2375 uint32_t drv_state; 2376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2377 2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2379 2380 /* If reset value is all FF's, initialize DRV_STATE */ 2381 if (drv_state == 0xffffffff) { 2382 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2383 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2384 } 2385 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2386 ql_dbg(ql_dbg_init, vha, 0x00bb, 2387 "drv_state = 0x%08x.\n", drv_state); 2388 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2389 } 2390 2391 static inline void 2392 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2393 { 2394 uint32_t drv_state; 2395 2396 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2397 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2398 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2399 } 2400 2401 static inline void 2402 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2403 { 2404 uint32_t qsnt_state; 2405 2406 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2407 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2408 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2409 } 2410 2411 void 2412 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2413 { 2414 struct qla_hw_data *ha = vha->hw; 2415 uint32_t qsnt_state; 2416 2417 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2418 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2419 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2420 } 2421 2422 static int 2423 qla82xx_load_fw(scsi_qla_host_t *vha) 2424 { 2425 int rst; 2426 struct fw_blob *blob; 2427 struct qla_hw_data *ha = vha->hw; 2428 2429 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2430 ql_log(ql_log_fatal, vha, 0x009f, 2431 "Error during CRB initialization.\n"); 2432 return QLA_FUNCTION_FAILED; 2433 } 2434 udelay(500); 2435 2436 /* Bring QM and CAMRAM out of reset */ 2437 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2438 rst &= ~((1 << 28) | (1 << 24)); 2439 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2440 2441 /* 2442 * FW Load priority: 2443 * 1) Operational firmware residing in flash. 2444 * 2) Firmware via request-firmware interface (.bin file). 2445 */ 2446 if (ql2xfwloadbin == 2) 2447 goto try_blob_fw; 2448 2449 ql_log(ql_log_info, vha, 0x00a0, 2450 "Attempting to load firmware from flash.\n"); 2451 2452 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2453 ql_log(ql_log_info, vha, 0x00a1, 2454 "Firmware loaded successfully from flash.\n"); 2455 return QLA_SUCCESS; 2456 } else { 2457 ql_log(ql_log_warn, vha, 0x0108, 2458 "Firmware load from flash failed.\n"); 2459 } 2460 2461 try_blob_fw: 2462 ql_log(ql_log_info, vha, 0x00a2, 2463 "Attempting to load firmware from blob.\n"); 2464 2465 /* Load firmware blob. */ 2466 blob = ha->hablob = qla2x00_request_firmware(vha); 2467 if (!blob) { 2468 ql_log(ql_log_fatal, vha, 0x00a3, 2469 "Firmware image not present.\n"); 2470 goto fw_load_failed; 2471 } 2472 2473 /* Validating firmware blob */ 2474 if (qla82xx_validate_firmware_blob(vha, 2475 QLA82XX_FLASH_ROMIMAGE)) { 2476 /* Fallback to URI format */ 2477 if (qla82xx_validate_firmware_blob(vha, 2478 QLA82XX_UNIFIED_ROMIMAGE)) { 2479 ql_log(ql_log_fatal, vha, 0x00a4, 2480 "No valid firmware image found.\n"); 2481 return QLA_FUNCTION_FAILED; 2482 } 2483 } 2484 2485 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2486 ql_log(ql_log_info, vha, 0x00a5, 2487 "Firmware loaded successfully from binary blob.\n"); 2488 return QLA_SUCCESS; 2489 } 2490 2491 ql_log(ql_log_fatal, vha, 0x00a6, 2492 "Firmware load failed for binary blob.\n"); 2493 blob->fw = NULL; 2494 blob = NULL; 2495 2496 fw_load_failed: 2497 return QLA_FUNCTION_FAILED; 2498 } 2499 2500 int 2501 qla82xx_start_firmware(scsi_qla_host_t *vha) 2502 { 2503 uint16_t lnk; 2504 struct qla_hw_data *ha = vha->hw; 2505 2506 /* scrub dma mask expansion register */ 2507 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2508 2509 /* Put both the PEG CMD and RCV PEG to default state 2510 * of 0 before resetting the hardware 2511 */ 2512 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2513 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2514 2515 /* Overwrite stale initialization register values */ 2516 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2517 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2518 2519 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2520 ql_log(ql_log_fatal, vha, 0x00a7, 2521 "Error trying to start fw.\n"); 2522 return QLA_FUNCTION_FAILED; 2523 } 2524 2525 /* Handshake with the card before we register the devices. */ 2526 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2527 ql_log(ql_log_fatal, vha, 0x00aa, 2528 "Error during card handshake.\n"); 2529 return QLA_FUNCTION_FAILED; 2530 } 2531 2532 /* Negotiated Link width */ 2533 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2534 ha->link_width = (lnk >> 4) & 0x3f; 2535 2536 /* Synchronize with Receive peg */ 2537 return qla82xx_check_rcvpeg_state(ha); 2538 } 2539 2540 static uint32_t * 2541 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2542 uint32_t length) 2543 { 2544 uint32_t i; 2545 uint32_t val; 2546 struct qla_hw_data *ha = vha->hw; 2547 2548 /* Dword reads to flash. */ 2549 for (i = 0; i < length/4; i++, faddr += 4) { 2550 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2551 ql_log(ql_log_warn, vha, 0x0106, 2552 "Do ROM fast read failed.\n"); 2553 goto done_read; 2554 } 2555 dwptr[i] = cpu_to_le32(val); 2556 } 2557 done_read: 2558 return dwptr; 2559 } 2560 2561 static int 2562 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2563 { 2564 int ret; 2565 uint32_t val; 2566 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2567 2568 ret = ql82xx_rom_lock_d(ha); 2569 if (ret < 0) { 2570 ql_log(ql_log_warn, vha, 0xb014, 2571 "ROM Lock failed.\n"); 2572 return ret; 2573 } 2574 2575 ret = qla82xx_read_status_reg(ha, &val); 2576 if (ret < 0) 2577 goto done_unprotect; 2578 2579 val &= ~(BLOCK_PROTECT_BITS << 2); 2580 ret = qla82xx_write_status_reg(ha, val); 2581 if (ret < 0) { 2582 val |= (BLOCK_PROTECT_BITS << 2); 2583 qla82xx_write_status_reg(ha, val); 2584 } 2585 2586 if (qla82xx_write_disable_flash(ha) != 0) 2587 ql_log(ql_log_warn, vha, 0xb015, 2588 "Write disable failed.\n"); 2589 2590 done_unprotect: 2591 qla82xx_rom_unlock(ha); 2592 return ret; 2593 } 2594 2595 static int 2596 qla82xx_protect_flash(struct qla_hw_data *ha) 2597 { 2598 int ret; 2599 uint32_t val; 2600 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2601 2602 ret = ql82xx_rom_lock_d(ha); 2603 if (ret < 0) { 2604 ql_log(ql_log_warn, vha, 0xb016, 2605 "ROM Lock failed.\n"); 2606 return ret; 2607 } 2608 2609 ret = qla82xx_read_status_reg(ha, &val); 2610 if (ret < 0) 2611 goto done_protect; 2612 2613 val |= (BLOCK_PROTECT_BITS << 2); 2614 /* LOCK all sectors */ 2615 ret = qla82xx_write_status_reg(ha, val); 2616 if (ret < 0) 2617 ql_log(ql_log_warn, vha, 0xb017, 2618 "Write status register failed.\n"); 2619 2620 if (qla82xx_write_disable_flash(ha) != 0) 2621 ql_log(ql_log_warn, vha, 0xb018, 2622 "Write disable failed.\n"); 2623 done_protect: 2624 qla82xx_rom_unlock(ha); 2625 return ret; 2626 } 2627 2628 static int 2629 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2630 { 2631 int ret = 0; 2632 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2633 2634 ret = ql82xx_rom_lock_d(ha); 2635 if (ret < 0) { 2636 ql_log(ql_log_warn, vha, 0xb019, 2637 "ROM Lock failed.\n"); 2638 return ret; 2639 } 2640 2641 qla82xx_flash_set_write_enable(ha); 2642 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2643 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2644 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2645 2646 if (qla82xx_wait_rom_done(ha)) { 2647 ql_log(ql_log_warn, vha, 0xb01a, 2648 "Error waiting for rom done.\n"); 2649 ret = -1; 2650 goto done; 2651 } 2652 ret = qla82xx_flash_wait_write_finish(ha); 2653 done: 2654 qla82xx_rom_unlock(ha); 2655 return ret; 2656 } 2657 2658 /* 2659 * Address and length are byte address 2660 */ 2661 uint8_t * 2662 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2663 uint32_t offset, uint32_t length) 2664 { 2665 scsi_block_requests(vha->host); 2666 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2667 scsi_unblock_requests(vha->host); 2668 return buf; 2669 } 2670 2671 static int 2672 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2673 uint32_t faddr, uint32_t dwords) 2674 { 2675 int ret; 2676 uint32_t liter; 2677 uint32_t rest_addr; 2678 dma_addr_t optrom_dma; 2679 void *optrom = NULL; 2680 int page_mode = 0; 2681 struct qla_hw_data *ha = vha->hw; 2682 2683 ret = -1; 2684 2685 /* Prepare burst-capable write on supported ISPs. */ 2686 if (page_mode && !(faddr & 0xfff) && 2687 dwords > OPTROM_BURST_DWORDS) { 2688 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2689 &optrom_dma, GFP_KERNEL); 2690 if (!optrom) { 2691 ql_log(ql_log_warn, vha, 0xb01b, 2692 "Unable to allocate memory " 2693 "for optrom burst write (%x KB).\n", 2694 OPTROM_BURST_SIZE / 1024); 2695 } 2696 } 2697 2698 rest_addr = ha->fdt_block_size - 1; 2699 2700 ret = qla82xx_unprotect_flash(ha); 2701 if (ret) { 2702 ql_log(ql_log_warn, vha, 0xb01c, 2703 "Unable to unprotect flash for update.\n"); 2704 goto write_done; 2705 } 2706 2707 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2708 /* Are we at the beginning of a sector? */ 2709 if ((faddr & rest_addr) == 0) { 2710 2711 ret = qla82xx_erase_sector(ha, faddr); 2712 if (ret) { 2713 ql_log(ql_log_warn, vha, 0xb01d, 2714 "Unable to erase sector: address=%x.\n", 2715 faddr); 2716 break; 2717 } 2718 } 2719 2720 /* Go with burst-write. */ 2721 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2722 /* Copy data to DMA'ble buffer. */ 2723 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2724 2725 ret = qla2x00_load_ram(vha, optrom_dma, 2726 (ha->flash_data_off | faddr), 2727 OPTROM_BURST_DWORDS); 2728 if (ret != QLA_SUCCESS) { 2729 ql_log(ql_log_warn, vha, 0xb01e, 2730 "Unable to burst-write optrom segment " 2731 "(%x/%x/%llx).\n", ret, 2732 (ha->flash_data_off | faddr), 2733 (unsigned long long)optrom_dma); 2734 ql_log(ql_log_warn, vha, 0xb01f, 2735 "Reverting to slow-write.\n"); 2736 2737 dma_free_coherent(&ha->pdev->dev, 2738 OPTROM_BURST_SIZE, optrom, optrom_dma); 2739 optrom = NULL; 2740 } else { 2741 liter += OPTROM_BURST_DWORDS - 1; 2742 faddr += OPTROM_BURST_DWORDS - 1; 2743 dwptr += OPTROM_BURST_DWORDS - 1; 2744 continue; 2745 } 2746 } 2747 2748 ret = qla82xx_write_flash_dword(ha, faddr, 2749 cpu_to_le32(*dwptr)); 2750 if (ret) { 2751 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2752 "Unable to program flash address=%x data=%x.\n", 2753 faddr, *dwptr); 2754 break; 2755 } 2756 } 2757 2758 ret = qla82xx_protect_flash(ha); 2759 if (ret) 2760 ql_log(ql_log_warn, vha, 0xb021, 2761 "Unable to protect flash after update.\n"); 2762 write_done: 2763 if (optrom) 2764 dma_free_coherent(&ha->pdev->dev, 2765 OPTROM_BURST_SIZE, optrom, optrom_dma); 2766 return ret; 2767 } 2768 2769 int 2770 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2771 uint32_t offset, uint32_t length) 2772 { 2773 int rval; 2774 2775 /* Suspend HBA. */ 2776 scsi_block_requests(vha->host); 2777 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2778 length >> 2); 2779 scsi_unblock_requests(vha->host); 2780 2781 /* Convert return ISP82xx to generic */ 2782 if (rval) 2783 rval = QLA_FUNCTION_FAILED; 2784 else 2785 rval = QLA_SUCCESS; 2786 return rval; 2787 } 2788 2789 void 2790 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2791 { 2792 struct qla_hw_data *ha = vha->hw; 2793 struct req_que *req = ha->req_q_map[0]; 2794 uint32_t dbval; 2795 2796 /* Adjust ring index. */ 2797 req->ring_index++; 2798 if (req->ring_index == req->length) { 2799 req->ring_index = 0; 2800 req->ring_ptr = req->ring; 2801 } else 2802 req->ring_ptr++; 2803 2804 dbval = 0x04 | (ha->portnum << 5); 2805 2806 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2807 if (ql2xdbwr) 2808 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2809 else { 2810 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2811 wmb(); 2812 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2813 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2814 wmb(); 2815 } 2816 } 2817 } 2818 2819 static void 2820 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2821 { 2822 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2823 uint32_t lock_owner = 0; 2824 2825 if (qla82xx_rom_lock(ha)) { 2826 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2827 /* Someone else is holding the lock. */ 2828 ql_log(ql_log_info, vha, 0xb022, 2829 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2830 } 2831 /* 2832 * Either we got the lock, or someone 2833 * else died while holding it. 2834 * In either case, unlock. 2835 */ 2836 qla82xx_rom_unlock(ha); 2837 } 2838 2839 /* 2840 * qla82xx_device_bootstrap 2841 * Initialize device, set DEV_READY, start fw 2842 * 2843 * Note: 2844 * IDC lock must be held upon entry 2845 * 2846 * Return: 2847 * Success : 0 2848 * Failed : 1 2849 */ 2850 static int 2851 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2852 { 2853 int rval = QLA_SUCCESS; 2854 int i; 2855 uint32_t old_count, count; 2856 struct qla_hw_data *ha = vha->hw; 2857 int need_reset = 0; 2858 2859 need_reset = qla82xx_need_reset(ha); 2860 2861 if (need_reset) { 2862 /* We are trying to perform a recovery here. */ 2863 if (ha->flags.isp82xx_fw_hung) 2864 qla82xx_rom_lock_recovery(ha); 2865 } else { 2866 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2867 for (i = 0; i < 10; i++) { 2868 msleep(200); 2869 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2870 if (count != old_count) { 2871 rval = QLA_SUCCESS; 2872 goto dev_ready; 2873 } 2874 } 2875 qla82xx_rom_lock_recovery(ha); 2876 } 2877 2878 /* set to DEV_INITIALIZING */ 2879 ql_log(ql_log_info, vha, 0x009e, 2880 "HW State: INITIALIZING.\n"); 2881 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2882 2883 qla82xx_idc_unlock(ha); 2884 rval = qla82xx_start_firmware(vha); 2885 qla82xx_idc_lock(ha); 2886 2887 if (rval != QLA_SUCCESS) { 2888 ql_log(ql_log_fatal, vha, 0x00ad, 2889 "HW State: FAILED.\n"); 2890 qla82xx_clear_drv_active(ha); 2891 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2892 return rval; 2893 } 2894 2895 dev_ready: 2896 ql_log(ql_log_info, vha, 0x00ae, 2897 "HW State: READY.\n"); 2898 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2899 2900 return QLA_SUCCESS; 2901 } 2902 2903 /* 2904 * qla82xx_need_qsnt_handler 2905 * Code to start quiescence sequence 2906 * 2907 * Note: 2908 * IDC lock must be held upon entry 2909 * 2910 * Return: void 2911 */ 2912 2913 static void 2914 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2915 { 2916 struct qla_hw_data *ha = vha->hw; 2917 uint32_t dev_state, drv_state, drv_active; 2918 unsigned long reset_timeout; 2919 2920 if (vha->flags.online) { 2921 /*Block any further I/O and wait for pending cmnds to complete*/ 2922 qla2x00_quiesce_io(vha); 2923 } 2924 2925 /* Set the quiescence ready bit */ 2926 qla82xx_set_qsnt_ready(ha); 2927 2928 /*wait for 30 secs for other functions to ack */ 2929 reset_timeout = jiffies + (30 * HZ); 2930 2931 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2932 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2933 /* Its 2 that is written when qsnt is acked, moving one bit */ 2934 drv_active = drv_active << 0x01; 2935 2936 while (drv_state != drv_active) { 2937 2938 if (time_after_eq(jiffies, reset_timeout)) { 2939 /* quiescence timeout, other functions didn't ack 2940 * changing the state to DEV_READY 2941 */ 2942 ql_log(ql_log_info, vha, 0xb023, 2943 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2944 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2945 drv_active, drv_state); 2946 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2947 QLA8XXX_DEV_READY); 2948 ql_log(ql_log_info, vha, 0xb025, 2949 "HW State: DEV_READY.\n"); 2950 qla82xx_idc_unlock(ha); 2951 qla2x00_perform_loop_resync(vha); 2952 qla82xx_idc_lock(ha); 2953 2954 qla82xx_clear_qsnt_ready(vha); 2955 return; 2956 } 2957 2958 qla82xx_idc_unlock(ha); 2959 msleep(1000); 2960 qla82xx_idc_lock(ha); 2961 2962 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2963 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2964 drv_active = drv_active << 0x01; 2965 } 2966 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2967 /* everyone acked so set the state to DEV_QUIESCENCE */ 2968 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2969 ql_log(ql_log_info, vha, 0xb026, 2970 "HW State: DEV_QUIESCENT.\n"); 2971 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2972 } 2973 } 2974 2975 /* 2976 * qla82xx_wait_for_state_change 2977 * Wait for device state to change from given current state 2978 * 2979 * Note: 2980 * IDC lock must not be held upon entry 2981 * 2982 * Return: 2983 * Changed device state. 2984 */ 2985 uint32_t 2986 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2987 { 2988 struct qla_hw_data *ha = vha->hw; 2989 uint32_t dev_state; 2990 2991 do { 2992 msleep(1000); 2993 qla82xx_idc_lock(ha); 2994 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2995 qla82xx_idc_unlock(ha); 2996 } while (dev_state == curr_state); 2997 2998 return dev_state; 2999 } 3000 3001 void 3002 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3003 { 3004 struct qla_hw_data *ha = vha->hw; 3005 3006 /* Disable the board */ 3007 ql_log(ql_log_fatal, vha, 0x00b8, 3008 "Disabling the board.\n"); 3009 3010 if (IS_QLA82XX(ha)) { 3011 qla82xx_clear_drv_active(ha); 3012 qla82xx_idc_unlock(ha); 3013 } else if (IS_QLA8044(ha)) { 3014 qla8044_clear_drv_active(ha); 3015 qla8044_idc_unlock(ha); 3016 } 3017 3018 /* Set DEV_FAILED flag to disable timer */ 3019 vha->device_flags |= DFLG_DEV_FAILED; 3020 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3021 qla2x00_mark_all_devices_lost(vha, 0); 3022 vha->flags.online = 0; 3023 vha->flags.init_done = 0; 3024 } 3025 3026 /* 3027 * qla82xx_need_reset_handler 3028 * Code to start reset sequence 3029 * 3030 * Note: 3031 * IDC lock must be held upon entry 3032 * 3033 * Return: 3034 * Success : 0 3035 * Failed : 1 3036 */ 3037 static void 3038 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3039 { 3040 uint32_t dev_state, drv_state, drv_active; 3041 uint32_t active_mask = 0; 3042 unsigned long reset_timeout; 3043 struct qla_hw_data *ha = vha->hw; 3044 struct req_que *req = ha->req_q_map[0]; 3045 3046 if (vha->flags.online) { 3047 qla82xx_idc_unlock(ha); 3048 qla2x00_abort_isp_cleanup(vha); 3049 ha->isp_ops->get_flash_version(vha, req->ring); 3050 ha->isp_ops->nvram_config(vha); 3051 qla82xx_idc_lock(ha); 3052 } 3053 3054 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3055 if (!ha->flags.nic_core_reset_owner) { 3056 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3057 "reset_acknowledged by 0x%x\n", ha->portnum); 3058 qla82xx_set_rst_ready(ha); 3059 } else { 3060 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3061 drv_active &= active_mask; 3062 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3063 "active_mask: 0x%08x\n", active_mask); 3064 } 3065 3066 /* wait for 10 seconds for reset ack from all functions */ 3067 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3068 3069 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3070 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3071 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3072 3073 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3074 "drv_state: 0x%08x, drv_active: 0x%08x, " 3075 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3076 drv_state, drv_active, dev_state, active_mask); 3077 3078 while (drv_state != drv_active && 3079 dev_state != QLA8XXX_DEV_INITIALIZING) { 3080 if (time_after_eq(jiffies, reset_timeout)) { 3081 ql_log(ql_log_warn, vha, 0x00b5, 3082 "Reset timeout.\n"); 3083 break; 3084 } 3085 qla82xx_idc_unlock(ha); 3086 msleep(1000); 3087 qla82xx_idc_lock(ha); 3088 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3089 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3090 if (ha->flags.nic_core_reset_owner) 3091 drv_active &= active_mask; 3092 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3093 } 3094 3095 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3096 "drv_state: 0x%08x, drv_active: 0x%08x, " 3097 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3098 drv_state, drv_active, dev_state, active_mask); 3099 3100 ql_log(ql_log_info, vha, 0x00b6, 3101 "Device state is 0x%x = %s.\n", 3102 dev_state, 3103 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3104 3105 /* Force to DEV_COLD unless someone else is starting a reset */ 3106 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3107 dev_state != QLA8XXX_DEV_COLD) { 3108 ql_log(ql_log_info, vha, 0x00b7, 3109 "HW State: COLD/RE-INIT.\n"); 3110 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3111 qla82xx_set_rst_ready(ha); 3112 if (ql2xmdenable) { 3113 if (qla82xx_md_collect(vha)) 3114 ql_log(ql_log_warn, vha, 0xb02c, 3115 "Minidump not collected.\n"); 3116 } else 3117 ql_log(ql_log_warn, vha, 0xb04f, 3118 "Minidump disabled.\n"); 3119 } 3120 } 3121 3122 int 3123 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3124 { 3125 struct qla_hw_data *ha = vha->hw; 3126 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3127 int rval = QLA_SUCCESS; 3128 3129 fw_major_version = ha->fw_major_version; 3130 fw_minor_version = ha->fw_minor_version; 3131 fw_subminor_version = ha->fw_subminor_version; 3132 3133 rval = qla2x00_get_fw_version(vha); 3134 if (rval != QLA_SUCCESS) 3135 return rval; 3136 3137 if (ql2xmdenable) { 3138 if (!ha->fw_dumped) { 3139 if ((fw_major_version != ha->fw_major_version || 3140 fw_minor_version != ha->fw_minor_version || 3141 fw_subminor_version != ha->fw_subminor_version) || 3142 (ha->prev_minidump_failed)) { 3143 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3144 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3145 fw_major_version, fw_minor_version, 3146 fw_subminor_version, 3147 ha->fw_major_version, 3148 ha->fw_minor_version, 3149 ha->fw_subminor_version, 3150 ha->prev_minidump_failed); 3151 /* Release MiniDump resources */ 3152 qla82xx_md_free(vha); 3153 /* ALlocate MiniDump resources */ 3154 qla82xx_md_prep(vha); 3155 } 3156 } else 3157 ql_log(ql_log_info, vha, 0xb02e, 3158 "Firmware dump available to retrieve\n"); 3159 } 3160 return rval; 3161 } 3162 3163 3164 static int 3165 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3166 { 3167 uint32_t fw_heartbeat_counter; 3168 int status = 0; 3169 3170 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3171 QLA82XX_PEG_ALIVE_COUNTER); 3172 /* all 0xff, assume AER/EEH in progress, ignore */ 3173 if (fw_heartbeat_counter == 0xffffffff) { 3174 ql_dbg(ql_dbg_timer, vha, 0x6003, 3175 "FW heartbeat counter is 0xffffffff, " 3176 "returning status=%d.\n", status); 3177 return status; 3178 } 3179 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3180 vha->seconds_since_last_heartbeat++; 3181 /* FW not alive after 2 seconds */ 3182 if (vha->seconds_since_last_heartbeat == 2) { 3183 vha->seconds_since_last_heartbeat = 0; 3184 status = 1; 3185 } 3186 } else 3187 vha->seconds_since_last_heartbeat = 0; 3188 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3189 if (status) 3190 ql_dbg(ql_dbg_timer, vha, 0x6004, 3191 "Returning status=%d.\n", status); 3192 return status; 3193 } 3194 3195 /* 3196 * qla82xx_device_state_handler 3197 * Main state handler 3198 * 3199 * Note: 3200 * IDC lock must be held upon entry 3201 * 3202 * Return: 3203 * Success : 0 3204 * Failed : 1 3205 */ 3206 int 3207 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3208 { 3209 uint32_t dev_state; 3210 uint32_t old_dev_state; 3211 int rval = QLA_SUCCESS; 3212 unsigned long dev_init_timeout; 3213 struct qla_hw_data *ha = vha->hw; 3214 int loopcount = 0; 3215 3216 qla82xx_idc_lock(ha); 3217 if (!vha->flags.init_done) { 3218 qla82xx_set_drv_active(vha); 3219 qla82xx_set_idc_version(vha); 3220 } 3221 3222 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3223 old_dev_state = dev_state; 3224 ql_log(ql_log_info, vha, 0x009b, 3225 "Device state is 0x%x = %s.\n", 3226 dev_state, 3227 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3228 3229 /* wait for 30 seconds for device to go ready */ 3230 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3231 3232 while (1) { 3233 3234 if (time_after_eq(jiffies, dev_init_timeout)) { 3235 ql_log(ql_log_fatal, vha, 0x009c, 3236 "Device init failed.\n"); 3237 rval = QLA_FUNCTION_FAILED; 3238 break; 3239 } 3240 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3241 if (old_dev_state != dev_state) { 3242 loopcount = 0; 3243 old_dev_state = dev_state; 3244 } 3245 if (loopcount < 5) { 3246 ql_log(ql_log_info, vha, 0x009d, 3247 "Device state is 0x%x = %s.\n", 3248 dev_state, 3249 dev_state < MAX_STATES ? qdev_state(dev_state) : 3250 "Unknown"); 3251 } 3252 3253 switch (dev_state) { 3254 case QLA8XXX_DEV_READY: 3255 ha->flags.nic_core_reset_owner = 0; 3256 goto rel_lock; 3257 case QLA8XXX_DEV_COLD: 3258 rval = qla82xx_device_bootstrap(vha); 3259 break; 3260 case QLA8XXX_DEV_INITIALIZING: 3261 qla82xx_idc_unlock(ha); 3262 msleep(1000); 3263 qla82xx_idc_lock(ha); 3264 break; 3265 case QLA8XXX_DEV_NEED_RESET: 3266 if (!ql2xdontresethba) 3267 qla82xx_need_reset_handler(vha); 3268 else { 3269 qla82xx_idc_unlock(ha); 3270 msleep(1000); 3271 qla82xx_idc_lock(ha); 3272 } 3273 dev_init_timeout = jiffies + 3274 (ha->fcoe_dev_init_timeout * HZ); 3275 break; 3276 case QLA8XXX_DEV_NEED_QUIESCENT: 3277 qla82xx_need_qsnt_handler(vha); 3278 /* Reset timeout value after quiescence handler */ 3279 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3280 * HZ); 3281 break; 3282 case QLA8XXX_DEV_QUIESCENT: 3283 /* Owner will exit and other will wait for the state 3284 * to get changed 3285 */ 3286 if (ha->flags.quiesce_owner) 3287 goto rel_lock; 3288 3289 qla82xx_idc_unlock(ha); 3290 msleep(1000); 3291 qla82xx_idc_lock(ha); 3292 3293 /* Reset timeout value after quiescence handler */ 3294 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3295 * HZ); 3296 break; 3297 case QLA8XXX_DEV_FAILED: 3298 qla8xxx_dev_failed_handler(vha); 3299 rval = QLA_FUNCTION_FAILED; 3300 goto exit; 3301 default: 3302 qla82xx_idc_unlock(ha); 3303 msleep(1000); 3304 qla82xx_idc_lock(ha); 3305 } 3306 loopcount++; 3307 } 3308 rel_lock: 3309 qla82xx_idc_unlock(ha); 3310 exit: 3311 return rval; 3312 } 3313 3314 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3315 { 3316 uint32_t temp, temp_state, temp_val; 3317 struct qla_hw_data *ha = vha->hw; 3318 3319 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3320 temp_state = qla82xx_get_temp_state(temp); 3321 temp_val = qla82xx_get_temp_val(temp); 3322 3323 if (temp_state == QLA82XX_TEMP_PANIC) { 3324 ql_log(ql_log_warn, vha, 0x600e, 3325 "Device temperature %d degrees C exceeds " 3326 " maximum allowed. Hardware has been shut down.\n", 3327 temp_val); 3328 return 1; 3329 } else if (temp_state == QLA82XX_TEMP_WARN) { 3330 ql_log(ql_log_warn, vha, 0x600f, 3331 "Device temperature %d degrees C exceeds " 3332 "operating range. Immediate action needed.\n", 3333 temp_val); 3334 } 3335 return 0; 3336 } 3337 3338 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3339 { 3340 uint32_t temp; 3341 3342 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3343 return qla82xx_get_temp_val(temp); 3344 } 3345 3346 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3347 { 3348 struct qla_hw_data *ha = vha->hw; 3349 3350 if (ha->flags.mbox_busy) { 3351 ha->flags.mbox_int = 1; 3352 ha->flags.mbox_busy = 0; 3353 ql_log(ql_log_warn, vha, 0x6010, 3354 "Doing premature completion of mbx command.\n"); 3355 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3356 complete(&ha->mbx_intr_comp); 3357 } 3358 } 3359 3360 void qla82xx_watchdog(scsi_qla_host_t *vha) 3361 { 3362 uint32_t dev_state, halt_status; 3363 struct qla_hw_data *ha = vha->hw; 3364 3365 /* don't poll if reset is going on */ 3366 if (!ha->flags.nic_core_reset_hdlr_active) { 3367 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3368 if (qla82xx_check_temp(vha)) { 3369 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3370 ha->flags.isp82xx_fw_hung = 1; 3371 qla82xx_clear_pending_mbx(vha); 3372 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3373 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3374 ql_log(ql_log_warn, vha, 0x6001, 3375 "Adapter reset needed.\n"); 3376 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3377 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3378 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3379 ql_log(ql_log_warn, vha, 0x6002, 3380 "Quiescent needed.\n"); 3381 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3382 } else if (dev_state == QLA8XXX_DEV_FAILED && 3383 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3384 vha->flags.online == 1) { 3385 ql_log(ql_log_warn, vha, 0xb055, 3386 "Adapter state is failed. Offlining.\n"); 3387 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3388 ha->flags.isp82xx_fw_hung = 1; 3389 qla82xx_clear_pending_mbx(vha); 3390 } else { 3391 if (qla82xx_check_fw_alive(vha)) { 3392 ql_dbg(ql_dbg_timer, vha, 0x6011, 3393 "disabling pause transmit on port 0 & 1.\n"); 3394 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3395 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3396 halt_status = qla82xx_rd_32(ha, 3397 QLA82XX_PEG_HALT_STATUS1); 3398 ql_log(ql_log_info, vha, 0x6005, 3399 "dumping hw/fw registers:.\n " 3400 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3401 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3402 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3403 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3404 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3405 qla82xx_rd_32(ha, 3406 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3407 qla82xx_rd_32(ha, 3408 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3409 qla82xx_rd_32(ha, 3410 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3411 qla82xx_rd_32(ha, 3412 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3413 qla82xx_rd_32(ha, 3414 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3415 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3416 ql_log(ql_log_warn, vha, 0xb052, 3417 "Firmware aborted with " 3418 "error code 0x00006700. Device is " 3419 "being reset.\n"); 3420 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3421 set_bit(ISP_UNRECOVERABLE, 3422 &vha->dpc_flags); 3423 } else { 3424 ql_log(ql_log_info, vha, 0x6006, 3425 "Detect abort needed.\n"); 3426 set_bit(ISP_ABORT_NEEDED, 3427 &vha->dpc_flags); 3428 } 3429 ha->flags.isp82xx_fw_hung = 1; 3430 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3431 qla82xx_clear_pending_mbx(vha); 3432 } 3433 } 3434 } 3435 } 3436 3437 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3438 { 3439 int rval = -1; 3440 struct qla_hw_data *ha = vha->hw; 3441 3442 if (IS_QLA82XX(ha)) 3443 rval = qla82xx_device_state_handler(vha); 3444 else if (IS_QLA8044(ha)) { 3445 qla8044_idc_lock(ha); 3446 /* Decide the reset ownership */ 3447 qla83xx_reset_ownership(vha); 3448 qla8044_idc_unlock(ha); 3449 rval = qla8044_device_state_handler(vha); 3450 } 3451 return rval; 3452 } 3453 3454 void 3455 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3456 { 3457 struct qla_hw_data *ha = vha->hw; 3458 uint32_t dev_state = 0; 3459 3460 if (IS_QLA82XX(ha)) 3461 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3462 else if (IS_QLA8044(ha)) 3463 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3464 3465 if (dev_state == QLA8XXX_DEV_READY) { 3466 ql_log(ql_log_info, vha, 0xb02f, 3467 "HW State: NEED RESET\n"); 3468 if (IS_QLA82XX(ha)) { 3469 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3470 QLA8XXX_DEV_NEED_RESET); 3471 ha->flags.nic_core_reset_owner = 1; 3472 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3473 "reset_owner is 0x%x\n", ha->portnum); 3474 } else if (IS_QLA8044(ha)) 3475 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3476 QLA8XXX_DEV_NEED_RESET); 3477 } else 3478 ql_log(ql_log_info, vha, 0xb031, 3479 "Device state is 0x%x = %s.\n", 3480 dev_state, 3481 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3482 } 3483 3484 /* 3485 * qla82xx_abort_isp 3486 * Resets ISP and aborts all outstanding commands. 3487 * 3488 * Input: 3489 * ha = adapter block pointer. 3490 * 3491 * Returns: 3492 * 0 = success 3493 */ 3494 int 3495 qla82xx_abort_isp(scsi_qla_host_t *vha) 3496 { 3497 int rval = -1; 3498 struct qla_hw_data *ha = vha->hw; 3499 3500 if (vha->device_flags & DFLG_DEV_FAILED) { 3501 ql_log(ql_log_warn, vha, 0x8024, 3502 "Device in failed state, exiting.\n"); 3503 return QLA_SUCCESS; 3504 } 3505 ha->flags.nic_core_reset_hdlr_active = 1; 3506 3507 qla82xx_idc_lock(ha); 3508 qla82xx_set_reset_owner(vha); 3509 qla82xx_idc_unlock(ha); 3510 3511 if (IS_QLA82XX(ha)) 3512 rval = qla82xx_device_state_handler(vha); 3513 else if (IS_QLA8044(ha)) { 3514 qla8044_idc_lock(ha); 3515 /* Decide the reset ownership */ 3516 qla83xx_reset_ownership(vha); 3517 qla8044_idc_unlock(ha); 3518 rval = qla8044_device_state_handler(vha); 3519 } 3520 3521 qla82xx_idc_lock(ha); 3522 qla82xx_clear_rst_ready(ha); 3523 qla82xx_idc_unlock(ha); 3524 3525 if (rval == QLA_SUCCESS) { 3526 ha->flags.isp82xx_fw_hung = 0; 3527 ha->flags.nic_core_reset_hdlr_active = 0; 3528 qla82xx_restart_isp(vha); 3529 } 3530 3531 if (rval) { 3532 vha->flags.online = 1; 3533 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3534 if (ha->isp_abort_cnt == 0) { 3535 ql_log(ql_log_warn, vha, 0x8027, 3536 "ISP error recover failed - board " 3537 "disabled.\n"); 3538 /* 3539 * The next call disables the board 3540 * completely. 3541 */ 3542 ha->isp_ops->reset_adapter(vha); 3543 vha->flags.online = 0; 3544 clear_bit(ISP_ABORT_RETRY, 3545 &vha->dpc_flags); 3546 rval = QLA_SUCCESS; 3547 } else { /* schedule another ISP abort */ 3548 ha->isp_abort_cnt--; 3549 ql_log(ql_log_warn, vha, 0x8036, 3550 "ISP abort - retry remaining %d.\n", 3551 ha->isp_abort_cnt); 3552 rval = QLA_FUNCTION_FAILED; 3553 } 3554 } else { 3555 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3556 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3557 "ISP error recovery - retrying (%d) more times.\n", 3558 ha->isp_abort_cnt); 3559 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3560 rval = QLA_FUNCTION_FAILED; 3561 } 3562 } 3563 return rval; 3564 } 3565 3566 /* 3567 * qla82xx_fcoe_ctx_reset 3568 * Perform a quick reset and aborts all outstanding commands. 3569 * This will only perform an FCoE context reset and avoids a full blown 3570 * chip reset. 3571 * 3572 * Input: 3573 * ha = adapter block pointer. 3574 * is_reset_path = flag for identifying the reset path. 3575 * 3576 * Returns: 3577 * 0 = success 3578 */ 3579 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3580 { 3581 int rval = QLA_FUNCTION_FAILED; 3582 3583 if (vha->flags.online) { 3584 /* Abort all outstanding commands, so as to be requeued later */ 3585 qla2x00_abort_isp_cleanup(vha); 3586 } 3587 3588 /* Stop currently executing firmware. 3589 * This will destroy existing FCoE context at the F/W end. 3590 */ 3591 qla2x00_try_to_stop_firmware(vha); 3592 3593 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3594 rval = qla82xx_restart_isp(vha); 3595 3596 return rval; 3597 } 3598 3599 /* 3600 * qla2x00_wait_for_fcoe_ctx_reset 3601 * Wait till the FCoE context is reset. 3602 * 3603 * Note: 3604 * Does context switching here. 3605 * Release SPIN_LOCK (if any) before calling this routine. 3606 * 3607 * Return: 3608 * Success (fcoe_ctx reset is done) : 0 3609 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3610 */ 3611 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3612 { 3613 int status = QLA_FUNCTION_FAILED; 3614 unsigned long wait_reset; 3615 3616 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3617 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3618 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3619 && time_before(jiffies, wait_reset)) { 3620 3621 set_current_state(TASK_UNINTERRUPTIBLE); 3622 schedule_timeout(HZ); 3623 3624 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3625 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3626 status = QLA_SUCCESS; 3627 break; 3628 } 3629 } 3630 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3631 "%s: status=%d.\n", __func__, status); 3632 3633 return status; 3634 } 3635 3636 void 3637 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3638 { 3639 int i, fw_state = 0; 3640 unsigned long flags; 3641 struct qla_hw_data *ha = vha->hw; 3642 3643 /* Check if 82XX firmware is alive or not 3644 * We may have arrived here from NEED_RESET 3645 * detection only 3646 */ 3647 if (!ha->flags.isp82xx_fw_hung) { 3648 for (i = 0; i < 2; i++) { 3649 msleep(1000); 3650 if (IS_QLA82XX(ha)) 3651 fw_state = qla82xx_check_fw_alive(vha); 3652 else if (IS_QLA8044(ha)) 3653 fw_state = qla8044_check_fw_alive(vha); 3654 if (fw_state) { 3655 ha->flags.isp82xx_fw_hung = 1; 3656 qla82xx_clear_pending_mbx(vha); 3657 break; 3658 } 3659 } 3660 } 3661 ql_dbg(ql_dbg_init, vha, 0x00b0, 3662 "Entered %s fw_hung=%d.\n", 3663 __func__, ha->flags.isp82xx_fw_hung); 3664 3665 /* Abort all commands gracefully if fw NOT hung */ 3666 if (!ha->flags.isp82xx_fw_hung) { 3667 int cnt, que; 3668 srb_t *sp; 3669 struct req_que *req; 3670 3671 spin_lock_irqsave(&ha->hardware_lock, flags); 3672 for (que = 0; que < ha->max_req_queues; que++) { 3673 req = ha->req_q_map[que]; 3674 if (!req) 3675 continue; 3676 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3677 sp = req->outstanding_cmds[cnt]; 3678 if (sp) { 3679 if ((!sp->u.scmd.ctx || 3680 (sp->flags & 3681 SRB_FCP_CMND_DMA_VALID)) && 3682 !ha->flags.isp82xx_fw_hung) { 3683 spin_unlock_irqrestore( 3684 &ha->hardware_lock, flags); 3685 if (ha->isp_ops->abort_command(sp)) { 3686 ql_log(ql_log_info, vha, 3687 0x00b1, 3688 "mbx abort failed.\n"); 3689 } else { 3690 ql_log(ql_log_info, vha, 3691 0x00b2, 3692 "mbx abort success.\n"); 3693 } 3694 spin_lock_irqsave(&ha->hardware_lock, flags); 3695 } 3696 } 3697 } 3698 } 3699 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3700 3701 /* Wait for pending cmds (physical and virtual) to complete */ 3702 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3703 WAIT_HOST) == QLA_SUCCESS) { 3704 ql_dbg(ql_dbg_init, vha, 0x00b3, 3705 "Done wait for " 3706 "pending commands.\n"); 3707 } 3708 } 3709 } 3710 3711 /* Minidump related functions */ 3712 static int 3713 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3714 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3715 { 3716 struct qla_hw_data *ha = vha->hw; 3717 struct qla82xx_md_entry_crb *crb_entry; 3718 uint32_t read_value, opcode, poll_time; 3719 uint32_t addr, index, crb_addr; 3720 unsigned long wtime; 3721 struct qla82xx_md_template_hdr *tmplt_hdr; 3722 uint32_t rval = QLA_SUCCESS; 3723 int i; 3724 3725 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3726 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3727 crb_addr = crb_entry->addr; 3728 3729 for (i = 0; i < crb_entry->op_count; i++) { 3730 opcode = crb_entry->crb_ctrl.opcode; 3731 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3732 qla82xx_md_rw_32(ha, crb_addr, 3733 crb_entry->value_1, 1); 3734 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3735 } 3736 3737 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3738 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3739 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3740 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3741 } 3742 3743 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3744 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3745 read_value &= crb_entry->value_2; 3746 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3747 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3748 read_value |= crb_entry->value_3; 3749 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3750 } 3751 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3752 } 3753 3754 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3755 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3756 read_value |= crb_entry->value_3; 3757 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3758 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3759 } 3760 3761 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3762 poll_time = crb_entry->crb_strd.poll_timeout; 3763 wtime = jiffies + poll_time; 3764 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3765 3766 do { 3767 if ((read_value & crb_entry->value_2) 3768 == crb_entry->value_1) 3769 break; 3770 else if (time_after_eq(jiffies, wtime)) { 3771 /* capturing dump failed */ 3772 rval = QLA_FUNCTION_FAILED; 3773 break; 3774 } else 3775 read_value = qla82xx_md_rw_32(ha, 3776 crb_addr, 0, 0); 3777 } while (1); 3778 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3779 } 3780 3781 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3782 if (crb_entry->crb_strd.state_index_a) { 3783 index = crb_entry->crb_strd.state_index_a; 3784 addr = tmplt_hdr->saved_state_array[index]; 3785 } else 3786 addr = crb_addr; 3787 3788 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3789 index = crb_entry->crb_ctrl.state_index_v; 3790 tmplt_hdr->saved_state_array[index] = read_value; 3791 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3792 } 3793 3794 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3795 if (crb_entry->crb_strd.state_index_a) { 3796 index = crb_entry->crb_strd.state_index_a; 3797 addr = tmplt_hdr->saved_state_array[index]; 3798 } else 3799 addr = crb_addr; 3800 3801 if (crb_entry->crb_ctrl.state_index_v) { 3802 index = crb_entry->crb_ctrl.state_index_v; 3803 read_value = 3804 tmplt_hdr->saved_state_array[index]; 3805 } else 3806 read_value = crb_entry->value_1; 3807 3808 qla82xx_md_rw_32(ha, addr, read_value, 1); 3809 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3810 } 3811 3812 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3813 index = crb_entry->crb_ctrl.state_index_v; 3814 read_value = tmplt_hdr->saved_state_array[index]; 3815 read_value <<= crb_entry->crb_ctrl.shl; 3816 read_value >>= crb_entry->crb_ctrl.shr; 3817 if (crb_entry->value_2) 3818 read_value &= crb_entry->value_2; 3819 read_value |= crb_entry->value_3; 3820 read_value += crb_entry->value_1; 3821 tmplt_hdr->saved_state_array[index] = read_value; 3822 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3823 } 3824 crb_addr += crb_entry->crb_strd.addr_stride; 3825 } 3826 return rval; 3827 } 3828 3829 static void 3830 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3831 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3832 { 3833 struct qla_hw_data *ha = vha->hw; 3834 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3835 struct qla82xx_md_entry_rdocm *ocm_hdr; 3836 uint32_t *data_ptr = *d_ptr; 3837 3838 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3839 r_addr = ocm_hdr->read_addr; 3840 r_stride = ocm_hdr->read_addr_stride; 3841 loop_cnt = ocm_hdr->op_count; 3842 3843 for (i = 0; i < loop_cnt; i++) { 3844 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase); 3845 *data_ptr++ = cpu_to_le32(r_value); 3846 r_addr += r_stride; 3847 } 3848 *d_ptr = data_ptr; 3849 } 3850 3851 static void 3852 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3853 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3854 { 3855 struct qla_hw_data *ha = vha->hw; 3856 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3857 struct qla82xx_md_entry_mux *mux_hdr; 3858 uint32_t *data_ptr = *d_ptr; 3859 3860 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3861 r_addr = mux_hdr->read_addr; 3862 s_addr = mux_hdr->select_addr; 3863 s_stride = mux_hdr->select_value_stride; 3864 s_value = mux_hdr->select_value; 3865 loop_cnt = mux_hdr->op_count; 3866 3867 for (i = 0; i < loop_cnt; i++) { 3868 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3869 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3870 *data_ptr++ = cpu_to_le32(s_value); 3871 *data_ptr++ = cpu_to_le32(r_value); 3872 s_value += s_stride; 3873 } 3874 *d_ptr = data_ptr; 3875 } 3876 3877 static void 3878 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3879 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3880 { 3881 struct qla_hw_data *ha = vha->hw; 3882 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3883 struct qla82xx_md_entry_crb *crb_hdr; 3884 uint32_t *data_ptr = *d_ptr; 3885 3886 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3887 r_addr = crb_hdr->addr; 3888 r_stride = crb_hdr->crb_strd.addr_stride; 3889 loop_cnt = crb_hdr->op_count; 3890 3891 for (i = 0; i < loop_cnt; i++) { 3892 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3893 *data_ptr++ = cpu_to_le32(r_addr); 3894 *data_ptr++ = cpu_to_le32(r_value); 3895 r_addr += r_stride; 3896 } 3897 *d_ptr = data_ptr; 3898 } 3899 3900 static int 3901 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3902 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3903 { 3904 struct qla_hw_data *ha = vha->hw; 3905 uint32_t addr, r_addr, c_addr, t_r_addr; 3906 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3907 unsigned long p_wait, w_time, p_mask; 3908 uint32_t c_value_w, c_value_r; 3909 struct qla82xx_md_entry_cache *cache_hdr; 3910 int rval = QLA_FUNCTION_FAILED; 3911 uint32_t *data_ptr = *d_ptr; 3912 3913 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3914 loop_count = cache_hdr->op_count; 3915 r_addr = cache_hdr->read_addr; 3916 c_addr = cache_hdr->control_addr; 3917 c_value_w = cache_hdr->cache_ctrl.write_value; 3918 3919 t_r_addr = cache_hdr->tag_reg_addr; 3920 t_value = cache_hdr->addr_ctrl.init_tag_value; 3921 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3922 p_wait = cache_hdr->cache_ctrl.poll_wait; 3923 p_mask = cache_hdr->cache_ctrl.poll_mask; 3924 3925 for (i = 0; i < loop_count; i++) { 3926 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3927 if (c_value_w) 3928 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3929 3930 if (p_mask) { 3931 w_time = jiffies + p_wait; 3932 do { 3933 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3934 if ((c_value_r & p_mask) == 0) 3935 break; 3936 else if (time_after_eq(jiffies, w_time)) { 3937 /* capturing dump failed */ 3938 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3939 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3940 "w_time: 0x%lx\n", 3941 c_value_r, p_mask, w_time); 3942 return rval; 3943 } 3944 } while (1); 3945 } 3946 3947 addr = r_addr; 3948 for (k = 0; k < r_cnt; k++) { 3949 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3950 *data_ptr++ = cpu_to_le32(r_value); 3951 addr += cache_hdr->read_ctrl.read_addr_stride; 3952 } 3953 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3954 } 3955 *d_ptr = data_ptr; 3956 return QLA_SUCCESS; 3957 } 3958 3959 static void 3960 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3961 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3962 { 3963 struct qla_hw_data *ha = vha->hw; 3964 uint32_t addr, r_addr, c_addr, t_r_addr; 3965 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3966 uint32_t c_value_w; 3967 struct qla82xx_md_entry_cache *cache_hdr; 3968 uint32_t *data_ptr = *d_ptr; 3969 3970 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3971 loop_count = cache_hdr->op_count; 3972 r_addr = cache_hdr->read_addr; 3973 c_addr = cache_hdr->control_addr; 3974 c_value_w = cache_hdr->cache_ctrl.write_value; 3975 3976 t_r_addr = cache_hdr->tag_reg_addr; 3977 t_value = cache_hdr->addr_ctrl.init_tag_value; 3978 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3979 3980 for (i = 0; i < loop_count; i++) { 3981 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3982 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3983 addr = r_addr; 3984 for (k = 0; k < r_cnt; k++) { 3985 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3986 *data_ptr++ = cpu_to_le32(r_value); 3987 addr += cache_hdr->read_ctrl.read_addr_stride; 3988 } 3989 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3990 } 3991 *d_ptr = data_ptr; 3992 } 3993 3994 static void 3995 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3996 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3997 { 3998 struct qla_hw_data *ha = vha->hw; 3999 uint32_t s_addr, r_addr; 4000 uint32_t r_stride, r_value, r_cnt, qid = 0; 4001 uint32_t i, k, loop_cnt; 4002 struct qla82xx_md_entry_queue *q_hdr; 4003 uint32_t *data_ptr = *d_ptr; 4004 4005 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 4006 s_addr = q_hdr->select_addr; 4007 r_cnt = q_hdr->rd_strd.read_addr_cnt; 4008 r_stride = q_hdr->rd_strd.read_addr_stride; 4009 loop_cnt = q_hdr->op_count; 4010 4011 for (i = 0; i < loop_cnt; i++) { 4012 qla82xx_md_rw_32(ha, s_addr, qid, 1); 4013 r_addr = q_hdr->read_addr; 4014 for (k = 0; k < r_cnt; k++) { 4015 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4016 *data_ptr++ = cpu_to_le32(r_value); 4017 r_addr += r_stride; 4018 } 4019 qid += q_hdr->q_strd.queue_id_stride; 4020 } 4021 *d_ptr = data_ptr; 4022 } 4023 4024 static void 4025 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 4026 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4027 { 4028 struct qla_hw_data *ha = vha->hw; 4029 uint32_t r_addr, r_value; 4030 uint32_t i, loop_cnt; 4031 struct qla82xx_md_entry_rdrom *rom_hdr; 4032 uint32_t *data_ptr = *d_ptr; 4033 4034 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4035 r_addr = rom_hdr->read_addr; 4036 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4037 4038 for (i = 0; i < loop_cnt; i++) { 4039 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4040 (r_addr & 0xFFFF0000), 1); 4041 r_value = qla82xx_md_rw_32(ha, 4042 MD_DIRECT_ROM_READ_BASE + 4043 (r_addr & 0x0000FFFF), 0, 0); 4044 *data_ptr++ = cpu_to_le32(r_value); 4045 r_addr += sizeof(uint32_t); 4046 } 4047 *d_ptr = data_ptr; 4048 } 4049 4050 static int 4051 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4052 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4053 { 4054 struct qla_hw_data *ha = vha->hw; 4055 uint32_t r_addr, r_value, r_data; 4056 uint32_t i, j, loop_cnt; 4057 struct qla82xx_md_entry_rdmem *m_hdr; 4058 unsigned long flags; 4059 int rval = QLA_FUNCTION_FAILED; 4060 uint32_t *data_ptr = *d_ptr; 4061 4062 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4063 r_addr = m_hdr->read_addr; 4064 loop_cnt = m_hdr->read_data_size/16; 4065 4066 if (r_addr & 0xf) { 4067 ql_log(ql_log_warn, vha, 0xb033, 4068 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4069 return rval; 4070 } 4071 4072 if (m_hdr->read_data_size % 16) { 4073 ql_log(ql_log_warn, vha, 0xb034, 4074 "Read data[0x%x] not multiple of 16 bytes\n", 4075 m_hdr->read_data_size); 4076 return rval; 4077 } 4078 4079 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4080 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4081 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4082 4083 write_lock_irqsave(&ha->hw_lock, flags); 4084 for (i = 0; i < loop_cnt; i++) { 4085 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4086 r_value = 0; 4087 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4088 r_value = MIU_TA_CTL_ENABLE; 4089 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4090 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4091 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4092 4093 for (j = 0; j < MAX_CTL_CHECK; j++) { 4094 r_value = qla82xx_md_rw_32(ha, 4095 MD_MIU_TEST_AGT_CTRL, 0, 0); 4096 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4097 break; 4098 } 4099 4100 if (j >= MAX_CTL_CHECK) { 4101 printk_ratelimited(KERN_ERR 4102 "failed to read through agent\n"); 4103 write_unlock_irqrestore(&ha->hw_lock, flags); 4104 return rval; 4105 } 4106 4107 for (j = 0; j < 4; j++) { 4108 r_data = qla82xx_md_rw_32(ha, 4109 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4110 *data_ptr++ = cpu_to_le32(r_data); 4111 } 4112 r_addr += 16; 4113 } 4114 write_unlock_irqrestore(&ha->hw_lock, flags); 4115 *d_ptr = data_ptr; 4116 return QLA_SUCCESS; 4117 } 4118 4119 int 4120 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4121 { 4122 struct qla_hw_data *ha = vha->hw; 4123 uint64_t chksum = 0; 4124 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4125 int count = ha->md_template_size/sizeof(uint32_t); 4126 4127 while (count-- > 0) 4128 chksum += *d_ptr++; 4129 while (chksum >> 32) 4130 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4131 return ~chksum; 4132 } 4133 4134 static void 4135 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4136 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4137 { 4138 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4139 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4140 "Skipping entry[%d]: " 4141 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4142 index, entry_hdr->entry_type, 4143 entry_hdr->d_ctrl.entry_capture_mask); 4144 } 4145 4146 int 4147 qla82xx_md_collect(scsi_qla_host_t *vha) 4148 { 4149 struct qla_hw_data *ha = vha->hw; 4150 int no_entry_hdr = 0; 4151 qla82xx_md_entry_hdr_t *entry_hdr; 4152 struct qla82xx_md_template_hdr *tmplt_hdr; 4153 uint32_t *data_ptr; 4154 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4155 int i = 0, rval = QLA_FUNCTION_FAILED; 4156 4157 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4158 data_ptr = (uint32_t *)ha->md_dump; 4159 4160 if (ha->fw_dumped) { 4161 ql_log(ql_log_warn, vha, 0xb037, 4162 "Firmware has been previously dumped (%p) " 4163 "-- ignoring request.\n", ha->fw_dump); 4164 goto md_failed; 4165 } 4166 4167 ha->fw_dumped = 0; 4168 4169 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4170 ql_log(ql_log_warn, vha, 0xb038, 4171 "Memory not allocated for minidump capture\n"); 4172 goto md_failed; 4173 } 4174 4175 if (ha->flags.isp82xx_no_md_cap) { 4176 ql_log(ql_log_warn, vha, 0xb054, 4177 "Forced reset from application, " 4178 "ignore minidump capture\n"); 4179 ha->flags.isp82xx_no_md_cap = 0; 4180 goto md_failed; 4181 } 4182 4183 if (qla82xx_validate_template_chksum(vha)) { 4184 ql_log(ql_log_info, vha, 0xb039, 4185 "Template checksum validation error\n"); 4186 goto md_failed; 4187 } 4188 4189 no_entry_hdr = tmplt_hdr->num_of_entries; 4190 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4191 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4192 4193 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4194 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4195 4196 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4197 4198 /* Validate whether required debug level is set */ 4199 if ((f_capture_mask & 0x3) != 0x3) { 4200 ql_log(ql_log_warn, vha, 0xb03c, 4201 "Minimum required capture mask[0x%x] level not set\n", 4202 f_capture_mask); 4203 goto md_failed; 4204 } 4205 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4206 4207 tmplt_hdr->driver_info[0] = vha->host_no; 4208 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4209 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4210 QLA_DRIVER_BETA_VER; 4211 4212 total_data_size = ha->md_dump_size; 4213 4214 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4215 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4216 4217 /* Check whether template obtained is valid */ 4218 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4219 ql_log(ql_log_warn, vha, 0xb04e, 4220 "Bad template header entry type: 0x%x obtained\n", 4221 tmplt_hdr->entry_type); 4222 goto md_failed; 4223 } 4224 4225 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4226 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4227 4228 /* Walk through the entry headers */ 4229 for (i = 0; i < no_entry_hdr; i++) { 4230 4231 if (data_collected > total_data_size) { 4232 ql_log(ql_log_warn, vha, 0xb03e, 4233 "More MiniDump data collected: [0x%x]\n", 4234 data_collected); 4235 goto md_failed; 4236 } 4237 4238 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4239 ql2xmdcapmask)) { 4240 entry_hdr->d_ctrl.driver_flags |= 4241 QLA82XX_DBG_SKIPPED_FLAG; 4242 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4243 "Skipping entry[%d]: " 4244 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4245 i, entry_hdr->entry_type, 4246 entry_hdr->d_ctrl.entry_capture_mask); 4247 goto skip_nxt_entry; 4248 } 4249 4250 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4251 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4252 "entry_type: 0x%x, capture_mask: 0x%x\n", 4253 __func__, i, data_ptr, entry_hdr, 4254 entry_hdr->entry_type, 4255 entry_hdr->d_ctrl.entry_capture_mask); 4256 4257 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4258 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4259 data_collected, (ha->md_dump_size - data_collected)); 4260 4261 /* Decode the entry type and take 4262 * required action to capture debug data */ 4263 switch (entry_hdr->entry_type) { 4264 case QLA82XX_RDEND: 4265 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4266 break; 4267 case QLA82XX_CNTRL: 4268 rval = qla82xx_minidump_process_control(vha, 4269 entry_hdr, &data_ptr); 4270 if (rval != QLA_SUCCESS) { 4271 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4272 goto md_failed; 4273 } 4274 break; 4275 case QLA82XX_RDCRB: 4276 qla82xx_minidump_process_rdcrb(vha, 4277 entry_hdr, &data_ptr); 4278 break; 4279 case QLA82XX_RDMEM: 4280 rval = qla82xx_minidump_process_rdmem(vha, 4281 entry_hdr, &data_ptr); 4282 if (rval != QLA_SUCCESS) { 4283 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4284 goto md_failed; 4285 } 4286 break; 4287 case QLA82XX_BOARD: 4288 case QLA82XX_RDROM: 4289 qla82xx_minidump_process_rdrom(vha, 4290 entry_hdr, &data_ptr); 4291 break; 4292 case QLA82XX_L2DTG: 4293 case QLA82XX_L2ITG: 4294 case QLA82XX_L2DAT: 4295 case QLA82XX_L2INS: 4296 rval = qla82xx_minidump_process_l2tag(vha, 4297 entry_hdr, &data_ptr); 4298 if (rval != QLA_SUCCESS) { 4299 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4300 goto md_failed; 4301 } 4302 break; 4303 case QLA82XX_L1DAT: 4304 case QLA82XX_L1INS: 4305 qla82xx_minidump_process_l1cache(vha, 4306 entry_hdr, &data_ptr); 4307 break; 4308 case QLA82XX_RDOCM: 4309 qla82xx_minidump_process_rdocm(vha, 4310 entry_hdr, &data_ptr); 4311 break; 4312 case QLA82XX_RDMUX: 4313 qla82xx_minidump_process_rdmux(vha, 4314 entry_hdr, &data_ptr); 4315 break; 4316 case QLA82XX_QUEUE: 4317 qla82xx_minidump_process_queue(vha, 4318 entry_hdr, &data_ptr); 4319 break; 4320 case QLA82XX_RDNOP: 4321 default: 4322 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4323 break; 4324 } 4325 4326 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4327 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4328 4329 data_collected = (uint8_t *)data_ptr - 4330 (uint8_t *)ha->md_dump; 4331 skip_nxt_entry: 4332 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4333 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4334 } 4335 4336 if (data_collected != total_data_size) { 4337 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4338 "MiniDump data mismatch: Data collected: [0x%x]," 4339 "total_data_size:[0x%x]\n", 4340 data_collected, total_data_size); 4341 goto md_failed; 4342 } 4343 4344 ql_log(ql_log_info, vha, 0xb044, 4345 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4346 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4347 ha->fw_dumped = 1; 4348 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4349 4350 md_failed: 4351 return rval; 4352 } 4353 4354 int 4355 qla82xx_md_alloc(scsi_qla_host_t *vha) 4356 { 4357 struct qla_hw_data *ha = vha->hw; 4358 int i, k; 4359 struct qla82xx_md_template_hdr *tmplt_hdr; 4360 4361 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4362 4363 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4364 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4365 ql_log(ql_log_info, vha, 0xb045, 4366 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4367 ql2xmdcapmask); 4368 } 4369 4370 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4371 if (i & ql2xmdcapmask) 4372 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4373 } 4374 4375 if (ha->md_dump) { 4376 ql_log(ql_log_warn, vha, 0xb046, 4377 "Firmware dump previously allocated.\n"); 4378 return 1; 4379 } 4380 4381 ha->md_dump = vmalloc(ha->md_dump_size); 4382 if (ha->md_dump == NULL) { 4383 ql_log(ql_log_warn, vha, 0xb047, 4384 "Unable to allocate memory for Minidump size " 4385 "(0x%x).\n", ha->md_dump_size); 4386 return 1; 4387 } 4388 return 0; 4389 } 4390 4391 void 4392 qla82xx_md_free(scsi_qla_host_t *vha) 4393 { 4394 struct qla_hw_data *ha = vha->hw; 4395 4396 /* Release the template header allocated */ 4397 if (ha->md_tmplt_hdr) { 4398 ql_log(ql_log_info, vha, 0xb048, 4399 "Free MiniDump template: %p, size (%d KB)\n", 4400 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4401 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4402 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4403 ha->md_tmplt_hdr = NULL; 4404 } 4405 4406 /* Release the template data buffer allocated */ 4407 if (ha->md_dump) { 4408 ql_log(ql_log_info, vha, 0xb049, 4409 "Free MiniDump memory: %p, size (%d KB)\n", 4410 ha->md_dump, ha->md_dump_size / 1024); 4411 vfree(ha->md_dump); 4412 ha->md_dump_size = 0; 4413 ha->md_dump = NULL; 4414 } 4415 } 4416 4417 void 4418 qla82xx_md_prep(scsi_qla_host_t *vha) 4419 { 4420 struct qla_hw_data *ha = vha->hw; 4421 int rval; 4422 4423 /* Get Minidump template size */ 4424 rval = qla82xx_md_get_template_size(vha); 4425 if (rval == QLA_SUCCESS) { 4426 ql_log(ql_log_info, vha, 0xb04a, 4427 "MiniDump Template size obtained (%d KB)\n", 4428 ha->md_template_size / 1024); 4429 4430 /* Get Minidump template */ 4431 if (IS_QLA8044(ha)) 4432 rval = qla8044_md_get_template(vha); 4433 else 4434 rval = qla82xx_md_get_template(vha); 4435 4436 if (rval == QLA_SUCCESS) { 4437 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4438 "MiniDump Template obtained\n"); 4439 4440 /* Allocate memory for minidump */ 4441 rval = qla82xx_md_alloc(vha); 4442 if (rval == QLA_SUCCESS) 4443 ql_log(ql_log_info, vha, 0xb04c, 4444 "MiniDump memory allocated (%d KB)\n", 4445 ha->md_dump_size / 1024); 4446 else { 4447 ql_log(ql_log_info, vha, 0xb04d, 4448 "Free MiniDump template: %p, size: (%d KB)\n", 4449 ha->md_tmplt_hdr, 4450 ha->md_template_size / 1024); 4451 dma_free_coherent(&ha->pdev->dev, 4452 ha->md_template_size, 4453 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4454 ha->md_tmplt_hdr = NULL; 4455 } 4456 4457 } 4458 } 4459 } 4460 4461 int 4462 qla82xx_beacon_on(struct scsi_qla_host *vha) 4463 { 4464 4465 int rval; 4466 struct qla_hw_data *ha = vha->hw; 4467 qla82xx_idc_lock(ha); 4468 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4469 4470 if (rval) { 4471 ql_log(ql_log_warn, vha, 0xb050, 4472 "mbx set led config failed in %s\n", __func__); 4473 goto exit; 4474 } 4475 ha->beacon_blink_led = 1; 4476 exit: 4477 qla82xx_idc_unlock(ha); 4478 return rval; 4479 } 4480 4481 int 4482 qla82xx_beacon_off(struct scsi_qla_host *vha) 4483 { 4484 4485 int rval; 4486 struct qla_hw_data *ha = vha->hw; 4487 qla82xx_idc_lock(ha); 4488 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4489 4490 if (rval) { 4491 ql_log(ql_log_warn, vha, 0xb051, 4492 "mbx set led config failed in %s\n", __func__); 4493 goto exit; 4494 } 4495 ha->beacon_blink_led = 0; 4496 exit: 4497 qla82xx_idc_unlock(ha); 4498 return rval; 4499 } 4500 4501 void 4502 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4503 { 4504 struct qla_hw_data *ha = vha->hw; 4505 4506 if (!ha->allow_cna_fw_dump) 4507 return; 4508 4509 scsi_block_requests(vha->host); 4510 ha->flags.isp82xx_no_md_cap = 1; 4511 qla82xx_idc_lock(ha); 4512 qla82xx_set_reset_owner(vha); 4513 qla82xx_idc_unlock(ha); 4514 qla2x00_wait_for_chip_reset(vha); 4515 scsi_unblock_requests(vha->host); 4516 } 4517