1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 static void qla82xx_crb_addr_transform_setup(void) 46 { 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103 } 104 105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260 }; 261 262 /* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265 static unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330 }; 331 332 /* Device states */ 333 static char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342 }; 343 344 char *qdev_state(uint32_t dev_state) 345 { 346 return q_dev_state[dev_state]; 347 } 348 349 /* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356 { 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void __iomem *) 368 (CRB_WINDOW_2M + ha->nx_pcibase)); 369 if (win_read != ha->crb_win) { 370 ql_dbg(ql_dbg_p3p, vha, 0xb000, 371 "%s: Written crbwin (0x%x) " 372 "!= Read crbwin (0x%x), off=0x%lx.\n", 373 __func__, ha->crb_win, win_read, *off); 374 } 375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376 } 377 378 static inline unsigned long 379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380 { 381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382 /* See if we are currently pointing to the region we want to use next */ 383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384 /* No need to change window. PCIX and PCIEregs are in both 385 * regs are in both windows. 386 */ 387 return off; 388 } 389 390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391 /* We are in first CRB window */ 392 if (ha->curr_window != 0) 393 WARN_ON(1); 394 return off; 395 } 396 397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398 /* We are in second CRB window */ 399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400 401 if (ha->curr_window != 1) 402 return off; 403 404 /* We are in the QM or direct access 405 * register region - do nothing 406 */ 407 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408 (off < QLA82XX_PCI_CAMQM_MAX)) 409 return off; 410 } 411 /* strange address given */ 412 ql_dbg(ql_dbg_p3p, vha, 0xb001, 413 "%s: Warning: unm_nic_pci_set_crbwindow " 414 "called with an unknown address(%llx).\n", 415 QLA2XXX_DRIVER_NAME, off); 416 return off; 417 } 418 419 static int 420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 421 { 422 struct crb_128M_2M_sub_block_map *m; 423 424 if (*off >= QLA82XX_CRB_MAX) 425 return -1; 426 427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 428 *off = (*off - QLA82XX_PCI_CAMQM) + 429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 430 return 0; 431 } 432 433 if (*off < QLA82XX_PCI_CRBSPACE) 434 return -1; 435 436 *off -= QLA82XX_PCI_CRBSPACE; 437 438 /* Try direct map */ 439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 440 441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 443 return 0; 444 } 445 /* Not in direct map, use crb window */ 446 return 1; 447 } 448 449 #define CRB_WIN_LOCK_TIMEOUT 100000000 450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 451 { 452 int done = 0, timeout = 0; 453 454 while (!done) { 455 /* acquire semaphore3 from PCI HW block */ 456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 457 if (done == 1) 458 break; 459 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 460 return -1; 461 timeout++; 462 } 463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 464 return 0; 465 } 466 467 int 468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469 { 470 unsigned long flags = 0; 471 int rv; 472 473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474 475 BUG_ON(rv == -1); 476 477 if (rv == 1) { 478 write_lock_irqsave(&ha->hw_lock, flags); 479 qla82xx_crb_win_lock(ha); 480 qla82xx_pci_set_crbwindow_2M(ha, &off); 481 } 482 483 writel(data, (void __iomem *)off); 484 485 if (rv == 1) { 486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487 write_unlock_irqrestore(&ha->hw_lock, flags); 488 } 489 return 0; 490 } 491 492 int 493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494 { 495 unsigned long flags = 0; 496 int rv; 497 u32 data; 498 499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500 501 BUG_ON(rv == -1); 502 503 if (rv == 1) { 504 write_lock_irqsave(&ha->hw_lock, flags); 505 qla82xx_crb_win_lock(ha); 506 qla82xx_pci_set_crbwindow_2M(ha, &off); 507 } 508 data = RD_REG_DWORD((void __iomem *)off); 509 510 if (rv == 1) { 511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512 write_unlock_irqrestore(&ha->hw_lock, flags); 513 } 514 return data; 515 } 516 517 #define IDC_LOCK_TIMEOUT 100000000 518 int qla82xx_idc_lock(struct qla_hw_data *ha) 519 { 520 int i; 521 int done = 0, timeout = 0; 522 523 while (!done) { 524 /* acquire semaphore5 from PCI HW block */ 525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526 if (done == 1) 527 break; 528 if (timeout >= IDC_LOCK_TIMEOUT) 529 return -1; 530 531 timeout++; 532 533 /* Yield CPU */ 534 if (!in_interrupt()) 535 schedule(); 536 else { 537 for (i = 0; i < 20; i++) 538 cpu_relax(); 539 } 540 } 541 542 return 0; 543 } 544 545 void qla82xx_idc_unlock(struct qla_hw_data *ha) 546 { 547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548 } 549 550 /* PCI Windowing for DDR regions. */ 551 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 552 (((addr) <= (high)) && ((addr) >= (low))) 553 /* 554 * check memory access boundary. 555 * used by test agent. support ddr access only for now 556 */ 557 static unsigned long 558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 559 unsigned long long addr, int size) 560 { 561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 562 QLA82XX_ADDR_DDR_NET_MAX) || 563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 564 QLA82XX_ADDR_DDR_NET_MAX) || 565 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 566 return 0; 567 else 568 return 1; 569 } 570 571 static int qla82xx_pci_set_window_warning_count; 572 573 static unsigned long 574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 575 { 576 int window; 577 u32 win_read; 578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 579 580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 581 QLA82XX_ADDR_DDR_NET_MAX)) { 582 /* DDR network side */ 583 window = MN_WIN(addr); 584 ha->ddr_mn_window = window; 585 qla82xx_wr_32(ha, 586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 587 win_read = qla82xx_rd_32(ha, 588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 589 if ((win_read << 17) != window) { 590 ql_dbg(ql_dbg_p3p, vha, 0xb003, 591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 592 __func__, window, win_read); 593 } 594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 596 QLA82XX_ADDR_OCM0_MAX)) { 597 unsigned int temp1; 598 if ((addr & 0x00ff800) == 0xff800) { 599 ql_log(ql_log_warn, vha, 0xb004, 600 "%s: QM access not handled.\n", __func__); 601 addr = -1UL; 602 } 603 window = OCM_WIN(addr); 604 ha->ddr_mn_window = window; 605 qla82xx_wr_32(ha, 606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 607 win_read = qla82xx_rd_32(ha, 608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 609 temp1 = ((window & 0x1FF) << 7) | 610 ((window & 0x0FFFE0000) >> 17); 611 if (win_read != temp1) { 612 ql_log(ql_log_warn, vha, 0xb005, 613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 614 __func__, temp1, win_read); 615 } 616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 617 618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 619 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 620 /* QDR network side */ 621 window = MS_WIN(addr); 622 ha->qdr_sn_window = window; 623 qla82xx_wr_32(ha, 624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 625 win_read = qla82xx_rd_32(ha, 626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 627 if (win_read != window) { 628 ql_log(ql_log_warn, vha, 0xb006, 629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 630 __func__, window, win_read); 631 } 632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 633 } else { 634 /* 635 * peg gdb frequently accesses memory that doesn't exist, 636 * this limits the chit chat so debugging isn't slowed down. 637 */ 638 if ((qla82xx_pci_set_window_warning_count++ < 8) || 639 (qla82xx_pci_set_window_warning_count%64 == 0)) { 640 ql_log(ql_log_warn, vha, 0xb007, 641 "%s: Warning:%s Unknown address range!.\n", 642 __func__, QLA2XXX_DRIVER_NAME); 643 } 644 addr = -1UL; 645 } 646 return addr; 647 } 648 649 /* check if address is in the same windows as the previous access */ 650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 651 unsigned long long addr) 652 { 653 int window; 654 unsigned long long qdr_max; 655 656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 657 658 /* DDR network side */ 659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 660 QLA82XX_ADDR_DDR_NET_MAX)) 661 BUG(); 662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 663 QLA82XX_ADDR_OCM0_MAX)) 664 return 1; 665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 666 QLA82XX_ADDR_OCM1_MAX)) 667 return 1; 668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 669 /* QDR network side */ 670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 671 if (ha->qdr_sn_window == window) 672 return 1; 673 } 674 return 0; 675 } 676 677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 678 u64 off, void *data, int size) 679 { 680 unsigned long flags; 681 void __iomem *addr = NULL; 682 int ret = 0; 683 u64 start; 684 uint8_t __iomem *mem_ptr = NULL; 685 unsigned long mem_base; 686 unsigned long mem_page; 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 688 689 write_lock_irqsave(&ha->hw_lock, flags); 690 691 /* 692 * If attempting to access unknown address or straddle hw windows, 693 * do not access. 694 */ 695 start = qla82xx_pci_set_window(ha, off); 696 if ((start == -1UL) || 697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 698 write_unlock_irqrestore(&ha->hw_lock, flags); 699 ql_log(ql_log_fatal, vha, 0xb008, 700 "%s out of bound pci memory " 701 "access, offset is 0x%llx.\n", 702 QLA2XXX_DRIVER_NAME, off); 703 return -1; 704 } 705 706 write_unlock_irqrestore(&ha->hw_lock, flags); 707 mem_base = pci_resource_start(ha->pdev, 0); 708 mem_page = start & PAGE_MASK; 709 /* Map two pages whenever user tries to access addresses in two 710 * consecutive pages. 711 */ 712 if (mem_page != ((start + size - 1) & PAGE_MASK)) 713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 714 else 715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 716 if (mem_ptr == NULL) { 717 *(u8 *)data = 0; 718 return -1; 719 } 720 addr = mem_ptr; 721 addr += start & (PAGE_SIZE - 1); 722 write_lock_irqsave(&ha->hw_lock, flags); 723 724 switch (size) { 725 case 1: 726 *(u8 *)data = readb(addr); 727 break; 728 case 2: 729 *(u16 *)data = readw(addr); 730 break; 731 case 4: 732 *(u32 *)data = readl(addr); 733 break; 734 case 8: 735 *(u64 *)data = readq(addr); 736 break; 737 default: 738 ret = -1; 739 break; 740 } 741 write_unlock_irqrestore(&ha->hw_lock, flags); 742 743 if (mem_ptr) 744 iounmap(mem_ptr); 745 return ret; 746 } 747 748 static int 749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 750 u64 off, void *data, int size) 751 { 752 unsigned long flags; 753 void __iomem *addr = NULL; 754 int ret = 0; 755 u64 start; 756 uint8_t __iomem *mem_ptr = NULL; 757 unsigned long mem_base; 758 unsigned long mem_page; 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 760 761 write_lock_irqsave(&ha->hw_lock, flags); 762 763 /* 764 * If attempting to access unknown address or straddle hw windows, 765 * do not access. 766 */ 767 start = qla82xx_pci_set_window(ha, off); 768 if ((start == -1UL) || 769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 770 write_unlock_irqrestore(&ha->hw_lock, flags); 771 ql_log(ql_log_fatal, vha, 0xb009, 772 "%s out of bount memory " 773 "access, offset is 0x%llx.\n", 774 QLA2XXX_DRIVER_NAME, off); 775 return -1; 776 } 777 778 write_unlock_irqrestore(&ha->hw_lock, flags); 779 mem_base = pci_resource_start(ha->pdev, 0); 780 mem_page = start & PAGE_MASK; 781 /* Map two pages whenever user tries to access addresses in two 782 * consecutive pages. 783 */ 784 if (mem_page != ((start + size - 1) & PAGE_MASK)) 785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 786 else 787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 788 if (mem_ptr == NULL) 789 return -1; 790 791 addr = mem_ptr; 792 addr += start & (PAGE_SIZE - 1); 793 write_lock_irqsave(&ha->hw_lock, flags); 794 795 switch (size) { 796 case 1: 797 writeb(*(u8 *)data, addr); 798 break; 799 case 2: 800 writew(*(u16 *)data, addr); 801 break; 802 case 4: 803 writel(*(u32 *)data, addr); 804 break; 805 case 8: 806 writeq(*(u64 *)data, addr); 807 break; 808 default: 809 ret = -1; 810 break; 811 } 812 write_unlock_irqrestore(&ha->hw_lock, flags); 813 if (mem_ptr) 814 iounmap(mem_ptr); 815 return ret; 816 } 817 818 #define MTU_FUDGE_FACTOR 100 819 static unsigned long 820 qla82xx_decode_crb_addr(unsigned long addr) 821 { 822 int i; 823 unsigned long base_addr, offset, pci_base; 824 825 if (!qla82xx_crb_table_initialized) 826 qla82xx_crb_addr_transform_setup(); 827 828 pci_base = ADDR_ERROR; 829 base_addr = addr & 0xfff00000; 830 offset = addr & 0x000fffff; 831 832 for (i = 0; i < MAX_CRB_XFORM; i++) { 833 if (crb_addr_xform[i] == base_addr) { 834 pci_base = i << 20; 835 break; 836 } 837 } 838 if (pci_base == ADDR_ERROR) 839 return pci_base; 840 return pci_base + offset; 841 } 842 843 static long rom_max_timeout = 100; 844 static long qla82xx_rom_lock_timeout = 100; 845 846 static int 847 qla82xx_rom_lock(struct qla_hw_data *ha) 848 { 849 int done = 0, timeout = 0; 850 uint32_t lock_owner = 0; 851 852 while (!done) { 853 /* acquire semaphore2 from PCI HW block */ 854 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 855 if (done == 1) 856 break; 857 if (timeout >= qla82xx_rom_lock_timeout) { 858 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 859 return -1; 860 } 861 timeout++; 862 } 863 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 864 return 0; 865 } 866 867 static void 868 qla82xx_rom_unlock(struct qla_hw_data *ha) 869 { 870 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 871 } 872 873 static int 874 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 875 { 876 long timeout = 0; 877 long done = 0 ; 878 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 879 880 while (done == 0) { 881 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 882 done &= 4; 883 timeout++; 884 if (timeout >= rom_max_timeout) { 885 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 886 "%s: Timeout reached waiting for rom busy.\n", 887 QLA2XXX_DRIVER_NAME); 888 return -1; 889 } 890 } 891 return 0; 892 } 893 894 static int 895 qla82xx_wait_rom_done(struct qla_hw_data *ha) 896 { 897 long timeout = 0; 898 long done = 0 ; 899 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 900 901 while (done == 0) { 902 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 903 done &= 2; 904 timeout++; 905 if (timeout >= rom_max_timeout) { 906 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 907 "%s: Timeout reached waiting for rom done.\n", 908 QLA2XXX_DRIVER_NAME); 909 return -1; 910 } 911 } 912 return 0; 913 } 914 915 static int 916 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 917 { 918 uint32_t off_value, rval = 0; 919 920 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 921 (off & 0xFFFF0000)); 922 923 /* Read back value to make sure write has gone through */ 924 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 925 off_value = (off & 0x0000FFFF); 926 927 if (flag) 928 WRT_REG_DWORD((void __iomem *) 929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 930 data); 931 else 932 rval = RD_REG_DWORD((void __iomem *) 933 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 934 935 return rval; 936 } 937 938 static int 939 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 940 { 941 /* Dword reads to flash. */ 942 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 943 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 944 (addr & 0x0000FFFF), 0, 0); 945 946 return 0; 947 } 948 949 static int 950 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 951 { 952 int ret, loops = 0; 953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 954 955 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 956 udelay(100); 957 schedule(); 958 loops++; 959 } 960 if (loops >= 50000) { 961 ql_log(ql_log_fatal, vha, 0x00b9, 962 "Failed to acquire SEM2 lock.\n"); 963 return -1; 964 } 965 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 966 qla82xx_rom_unlock(ha); 967 return ret; 968 } 969 970 static int 971 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 972 { 973 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 974 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 975 qla82xx_wait_rom_busy(ha); 976 if (qla82xx_wait_rom_done(ha)) { 977 ql_log(ql_log_warn, vha, 0xb00c, 978 "Error waiting for rom done.\n"); 979 return -1; 980 } 981 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 982 return 0; 983 } 984 985 static int 986 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 987 { 988 long timeout = 0; 989 uint32_t done = 1 ; 990 uint32_t val; 991 int ret = 0; 992 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 993 994 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 995 while ((done != 0) && (ret == 0)) { 996 ret = qla82xx_read_status_reg(ha, &val); 997 done = val & 1; 998 timeout++; 999 udelay(10); 1000 cond_resched(); 1001 if (timeout >= 50000) { 1002 ql_log(ql_log_warn, vha, 0xb00d, 1003 "Timeout reached waiting for write finish.\n"); 1004 return -1; 1005 } 1006 } 1007 return ret; 1008 } 1009 1010 static int 1011 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1012 { 1013 uint32_t val; 1014 qla82xx_wait_rom_busy(ha); 1015 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1016 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1017 qla82xx_wait_rom_busy(ha); 1018 if (qla82xx_wait_rom_done(ha)) 1019 return -1; 1020 if (qla82xx_read_status_reg(ha, &val) != 0) 1021 return -1; 1022 if ((val & 2) != 2) 1023 return -1; 1024 return 0; 1025 } 1026 1027 static int 1028 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1029 { 1030 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1031 if (qla82xx_flash_set_write_enable(ha)) 1032 return -1; 1033 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1034 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1035 if (qla82xx_wait_rom_done(ha)) { 1036 ql_log(ql_log_warn, vha, 0xb00e, 1037 "Error waiting for rom done.\n"); 1038 return -1; 1039 } 1040 return qla82xx_flash_wait_write_finish(ha); 1041 } 1042 1043 static int 1044 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1045 { 1046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1047 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1048 if (qla82xx_wait_rom_done(ha)) { 1049 ql_log(ql_log_warn, vha, 0xb00f, 1050 "Error waiting for rom done.\n"); 1051 return -1; 1052 } 1053 return 0; 1054 } 1055 1056 static int 1057 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1058 { 1059 int loops = 0; 1060 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1061 1062 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1063 udelay(100); 1064 cond_resched(); 1065 loops++; 1066 } 1067 if (loops >= 50000) { 1068 ql_log(ql_log_warn, vha, 0xb010, 1069 "ROM lock failed.\n"); 1070 return -1; 1071 } 1072 return 0; 1073 } 1074 1075 static int 1076 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1077 uint32_t data) 1078 { 1079 int ret = 0; 1080 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1081 1082 ret = ql82xx_rom_lock_d(ha); 1083 if (ret < 0) { 1084 ql_log(ql_log_warn, vha, 0xb011, 1085 "ROM lock failed.\n"); 1086 return ret; 1087 } 1088 1089 if (qla82xx_flash_set_write_enable(ha)) 1090 goto done_write; 1091 1092 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1093 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1094 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1095 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1096 qla82xx_wait_rom_busy(ha); 1097 if (qla82xx_wait_rom_done(ha)) { 1098 ql_log(ql_log_warn, vha, 0xb012, 1099 "Error waiting for rom done.\n"); 1100 ret = -1; 1101 goto done_write; 1102 } 1103 1104 ret = qla82xx_flash_wait_write_finish(ha); 1105 1106 done_write: 1107 qla82xx_rom_unlock(ha); 1108 return ret; 1109 } 1110 1111 /* This routine does CRB initialize sequence 1112 * to put the ISP into operational state 1113 */ 1114 static int 1115 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1116 { 1117 int addr, val; 1118 int i ; 1119 struct crb_addr_pair *buf; 1120 unsigned long off; 1121 unsigned offset, n; 1122 struct qla_hw_data *ha = vha->hw; 1123 1124 struct crb_addr_pair { 1125 long addr; 1126 long data; 1127 }; 1128 1129 /* Halt all the individual PEGs and other blocks of the ISP */ 1130 qla82xx_rom_lock(ha); 1131 1132 /* disable all I2Q */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1134 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1135 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1136 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1137 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1138 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1139 1140 /* disable all niu interrupts */ 1141 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1142 /* disable xge rx/tx */ 1143 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1144 /* disable xg1 rx/tx */ 1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1146 /* disable sideband mac */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1148 /* disable ap0 mac */ 1149 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1150 /* disable ap1 mac */ 1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1152 1153 /* halt sre */ 1154 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1155 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1156 1157 /* halt epg */ 1158 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1159 1160 /* halt timers */ 1161 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1162 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1163 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1164 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1165 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1166 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1167 1168 /* halt pegs */ 1169 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1170 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1171 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1172 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1173 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1174 msleep(20); 1175 1176 /* big hammer */ 1177 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1178 /* don't reset CAM block on reset */ 1179 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1180 else 1181 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1182 qla82xx_rom_unlock(ha); 1183 1184 /* Read the signature value from the flash. 1185 * Offset 0: Contain signature (0xcafecafe) 1186 * Offset 4: Offset and number of addr/value pairs 1187 * that present in CRB initialize sequence 1188 */ 1189 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1190 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1191 ql_log(ql_log_fatal, vha, 0x006e, 1192 "Error Reading crb_init area: n: %08x.\n", n); 1193 return -1; 1194 } 1195 1196 /* Offset in flash = lower 16 bits 1197 * Number of entries = upper 16 bits 1198 */ 1199 offset = n & 0xffffU; 1200 n = (n >> 16) & 0xffffU; 1201 1202 /* number of addr/value pair should not exceed 1024 entries */ 1203 if (n >= 1024) { 1204 ql_log(ql_log_fatal, vha, 0x0071, 1205 "Card flash not initialized:n=0x%x.\n", n); 1206 return -1; 1207 } 1208 1209 ql_log(ql_log_info, vha, 0x0072, 1210 "%d CRB init values found in ROM.\n", n); 1211 1212 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1213 if (buf == NULL) { 1214 ql_log(ql_log_fatal, vha, 0x010c, 1215 "Unable to allocate memory.\n"); 1216 return -1; 1217 } 1218 1219 for (i = 0; i < n; i++) { 1220 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1221 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1222 kfree(buf); 1223 return -1; 1224 } 1225 1226 buf[i].addr = addr; 1227 buf[i].data = val; 1228 } 1229 1230 for (i = 0; i < n; i++) { 1231 /* Translate internal CRB initialization 1232 * address to PCI bus address 1233 */ 1234 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1235 QLA82XX_PCI_CRBSPACE; 1236 /* Not all CRB addr/value pair to be written, 1237 * some of them are skipped 1238 */ 1239 1240 /* skipping cold reboot MAGIC */ 1241 if (off == QLA82XX_CAM_RAM(0x1fc)) 1242 continue; 1243 1244 /* do not reset PCI */ 1245 if (off == (ROMUSB_GLB + 0xbc)) 1246 continue; 1247 1248 /* skip core clock, so that firmware can increase the clock */ 1249 if (off == (ROMUSB_GLB + 0xc8)) 1250 continue; 1251 1252 /* skip the function enable register */ 1253 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1254 continue; 1255 1256 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1257 continue; 1258 1259 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1260 continue; 1261 1262 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1263 continue; 1264 1265 if (off == ADDR_ERROR) { 1266 ql_log(ql_log_fatal, vha, 0x0116, 1267 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1268 continue; 1269 } 1270 1271 qla82xx_wr_32(ha, off, buf[i].data); 1272 1273 /* ISP requires much bigger delay to settle down, 1274 * else crb_window returns 0xffffffff 1275 */ 1276 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1277 msleep(1000); 1278 1279 /* ISP requires millisec delay between 1280 * successive CRB register updation 1281 */ 1282 msleep(1); 1283 } 1284 1285 kfree(buf); 1286 1287 /* Resetting the data and instruction cache */ 1288 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1290 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1291 1292 /* Clear all protocol processing engines */ 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1301 return 0; 1302 } 1303 1304 static int 1305 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1306 u64 off, void *data, int size) 1307 { 1308 int i, j, ret = 0, loop, sz[2], off0; 1309 int scale, shift_amount, startword; 1310 uint32_t temp; 1311 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1312 1313 /* 1314 * If not MN, go check for MS or invalid. 1315 */ 1316 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1317 mem_crb = QLA82XX_CRB_QDR_NET; 1318 else { 1319 mem_crb = QLA82XX_CRB_DDR_NET; 1320 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1321 return qla82xx_pci_mem_write_direct(ha, 1322 off, data, size); 1323 } 1324 1325 off0 = off & 0x7; 1326 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1327 sz[1] = size - sz[0]; 1328 1329 off8 = off & 0xfffffff0; 1330 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1331 shift_amount = 4; 1332 scale = 2; 1333 startword = (off & 0xf)/8; 1334 1335 for (i = 0; i < loop; i++) { 1336 if (qla82xx_pci_mem_read_2M(ha, off8 + 1337 (i << shift_amount), &word[i * scale], 8)) 1338 return -1; 1339 } 1340 1341 switch (size) { 1342 case 1: 1343 tmpw = *((uint8_t *)data); 1344 break; 1345 case 2: 1346 tmpw = *((uint16_t *)data); 1347 break; 1348 case 4: 1349 tmpw = *((uint32_t *)data); 1350 break; 1351 case 8: 1352 default: 1353 tmpw = *((uint64_t *)data); 1354 break; 1355 } 1356 1357 if (sz[0] == 8) { 1358 word[startword] = tmpw; 1359 } else { 1360 word[startword] &= 1361 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1362 word[startword] |= tmpw << (off0 * 8); 1363 } 1364 if (sz[1] != 0) { 1365 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1366 word[startword+1] |= tmpw >> (sz[0] * 8); 1367 } 1368 1369 for (i = 0; i < loop; i++) { 1370 temp = off8 + (i << shift_amount); 1371 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1372 temp = 0; 1373 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1374 temp = word[i * scale] & 0xffffffff; 1375 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1376 temp = (word[i * scale] >> 32) & 0xffffffff; 1377 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1378 temp = word[i*scale + 1] & 0xffffffff; 1379 qla82xx_wr_32(ha, mem_crb + 1380 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1381 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1382 qla82xx_wr_32(ha, mem_crb + 1383 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1384 1385 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1386 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1387 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1388 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1389 1390 for (j = 0; j < MAX_CTL_CHECK; j++) { 1391 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1392 if ((temp & MIU_TA_CTL_BUSY) == 0) 1393 break; 1394 } 1395 1396 if (j >= MAX_CTL_CHECK) { 1397 if (printk_ratelimit()) 1398 dev_err(&ha->pdev->dev, 1399 "failed to write through agent.\n"); 1400 ret = -1; 1401 break; 1402 } 1403 } 1404 1405 return ret; 1406 } 1407 1408 static int 1409 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1410 { 1411 int i; 1412 long size = 0; 1413 long flashaddr = ha->flt_region_bootload << 2; 1414 long memaddr = BOOTLD_START; 1415 u64 data; 1416 u32 high, low; 1417 size = (IMAGE_START - BOOTLD_START) / 8; 1418 1419 for (i = 0; i < size; i++) { 1420 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1421 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1422 return -1; 1423 } 1424 data = ((u64)high << 32) | low ; 1425 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1426 flashaddr += 8; 1427 memaddr += 8; 1428 1429 if (i % 0x1000 == 0) 1430 msleep(1); 1431 } 1432 udelay(100); 1433 read_lock(&ha->hw_lock); 1434 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1435 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1436 read_unlock(&ha->hw_lock); 1437 return 0; 1438 } 1439 1440 int 1441 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1442 u64 off, void *data, int size) 1443 { 1444 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1445 int shift_amount; 1446 uint32_t temp; 1447 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1448 1449 /* 1450 * If not MN, go check for MS or invalid. 1451 */ 1452 1453 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1454 mem_crb = QLA82XX_CRB_QDR_NET; 1455 else { 1456 mem_crb = QLA82XX_CRB_DDR_NET; 1457 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1458 return qla82xx_pci_mem_read_direct(ha, 1459 off, data, size); 1460 } 1461 1462 off8 = off & 0xfffffff0; 1463 off0[0] = off & 0xf; 1464 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1465 shift_amount = 4; 1466 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1467 off0[1] = 0; 1468 sz[1] = size - sz[0]; 1469 1470 for (i = 0; i < loop; i++) { 1471 temp = off8 + (i << shift_amount); 1472 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1473 temp = 0; 1474 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1475 temp = MIU_TA_CTL_ENABLE; 1476 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1477 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1478 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1479 1480 for (j = 0; j < MAX_CTL_CHECK; j++) { 1481 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1482 if ((temp & MIU_TA_CTL_BUSY) == 0) 1483 break; 1484 } 1485 1486 if (j >= MAX_CTL_CHECK) { 1487 if (printk_ratelimit()) 1488 dev_err(&ha->pdev->dev, 1489 "failed to read through agent.\n"); 1490 break; 1491 } 1492 1493 start = off0[i] >> 2; 1494 end = (off0[i] + sz[i] - 1) >> 2; 1495 for (k = start; k <= end; k++) { 1496 temp = qla82xx_rd_32(ha, 1497 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1498 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1499 } 1500 } 1501 1502 if (j >= MAX_CTL_CHECK) 1503 return -1; 1504 1505 if ((off0[0] & 7) == 0) { 1506 val = word[0]; 1507 } else { 1508 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1509 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1510 } 1511 1512 switch (size) { 1513 case 1: 1514 *(uint8_t *)data = val; 1515 break; 1516 case 2: 1517 *(uint16_t *)data = val; 1518 break; 1519 case 4: 1520 *(uint32_t *)data = val; 1521 break; 1522 case 8: 1523 *(uint64_t *)data = val; 1524 break; 1525 } 1526 return 0; 1527 } 1528 1529 1530 static struct qla82xx_uri_table_desc * 1531 qla82xx_get_table_desc(const u8 *unirom, int section) 1532 { 1533 uint32_t i; 1534 struct qla82xx_uri_table_desc *directory = 1535 (struct qla82xx_uri_table_desc *)&unirom[0]; 1536 __le32 offset; 1537 __le32 tab_type; 1538 __le32 entries = cpu_to_le32(directory->num_entries); 1539 1540 for (i = 0; i < entries; i++) { 1541 offset = cpu_to_le32(directory->findex) + 1542 (i * cpu_to_le32(directory->entry_size)); 1543 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1544 1545 if (tab_type == section) 1546 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1547 } 1548 1549 return NULL; 1550 } 1551 1552 static struct qla82xx_uri_data_desc * 1553 qla82xx_get_data_desc(struct qla_hw_data *ha, 1554 u32 section, u32 idx_offset) 1555 { 1556 const u8 *unirom = ha->hablob->fw->data; 1557 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1558 struct qla82xx_uri_table_desc *tab_desc = NULL; 1559 __le32 offset; 1560 1561 tab_desc = qla82xx_get_table_desc(unirom, section); 1562 if (!tab_desc) 1563 return NULL; 1564 1565 offset = cpu_to_le32(tab_desc->findex) + 1566 (cpu_to_le32(tab_desc->entry_size) * idx); 1567 1568 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1569 } 1570 1571 static u8 * 1572 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1573 { 1574 u32 offset = BOOTLD_START; 1575 struct qla82xx_uri_data_desc *uri_desc = NULL; 1576 1577 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1578 uri_desc = qla82xx_get_data_desc(ha, 1579 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1580 if (uri_desc) 1581 offset = cpu_to_le32(uri_desc->findex); 1582 } 1583 1584 return (u8 *)&ha->hablob->fw->data[offset]; 1585 } 1586 1587 static __le32 1588 qla82xx_get_fw_size(struct qla_hw_data *ha) 1589 { 1590 struct qla82xx_uri_data_desc *uri_desc = NULL; 1591 1592 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1593 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1594 QLA82XX_URI_FIRMWARE_IDX_OFF); 1595 if (uri_desc) 1596 return cpu_to_le32(uri_desc->size); 1597 } 1598 1599 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1600 } 1601 1602 static u8 * 1603 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1604 { 1605 u32 offset = IMAGE_START; 1606 struct qla82xx_uri_data_desc *uri_desc = NULL; 1607 1608 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1609 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1610 QLA82XX_URI_FIRMWARE_IDX_OFF); 1611 if (uri_desc) 1612 offset = cpu_to_le32(uri_desc->findex); 1613 } 1614 1615 return (u8 *)&ha->hablob->fw->data[offset]; 1616 } 1617 1618 /* PCI related functions */ 1619 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1620 { 1621 unsigned long val = 0; 1622 u32 control; 1623 1624 switch (region) { 1625 case 0: 1626 val = 0; 1627 break; 1628 case 1: 1629 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1630 val = control + QLA82XX_MSIX_TBL_SPACE; 1631 break; 1632 } 1633 return val; 1634 } 1635 1636 1637 int 1638 qla82xx_iospace_config(struct qla_hw_data *ha) 1639 { 1640 uint32_t len = 0; 1641 1642 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1643 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1644 "Failed to reserver selected regions.\n"); 1645 goto iospace_error_exit; 1646 } 1647 1648 /* Use MMIO operations for all accesses. */ 1649 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1650 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1651 "Region #0 not an MMIO resource, aborting.\n"); 1652 goto iospace_error_exit; 1653 } 1654 1655 len = pci_resource_len(ha->pdev, 0); 1656 ha->nx_pcibase = 1657 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1658 if (!ha->nx_pcibase) { 1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1660 "Cannot remap pcibase MMIO, aborting.\n"); 1661 goto iospace_error_exit; 1662 } 1663 1664 /* Mapping of IO base pointer */ 1665 if (IS_QLA8044(ha)) { 1666 ha->iobase = 1667 (device_reg_t *)((uint8_t *)ha->nx_pcibase); 1668 } else if (IS_QLA82XX(ha)) { 1669 ha->iobase = 1670 (device_reg_t *)((uint8_t *)ha->nx_pcibase + 1671 0xbc000 + (ha->pdev->devfn << 11)); 1672 } 1673 1674 if (!ql2xdbwr) { 1675 ha->nxdb_wr_ptr = 1676 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1677 (ha->pdev->devfn << 12)), 4); 1678 if (!ha->nxdb_wr_ptr) { 1679 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1680 "Cannot remap MMIO, aborting.\n"); 1681 goto iospace_error_exit; 1682 } 1683 1684 /* Mapping of IO base pointer, 1685 * door bell read and write pointer 1686 */ 1687 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1688 (ha->pdev->devfn * 8); 1689 } else { 1690 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1691 QLA82XX_CAMRAM_DB1 : 1692 QLA82XX_CAMRAM_DB2); 1693 } 1694 1695 ha->max_req_queues = ha->max_rsp_queues = 1; 1696 ha->msix_count = ha->max_rsp_queues + 1; 1697 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1698 "nx_pci_base=%p iobase=%p " 1699 "max_req_queues=%d msix_count=%d.\n", 1700 (void *)ha->nx_pcibase, ha->iobase, 1701 ha->max_req_queues, ha->msix_count); 1702 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1703 "nx_pci_base=%p iobase=%p " 1704 "max_req_queues=%d msix_count=%d.\n", 1705 (void *)ha->nx_pcibase, ha->iobase, 1706 ha->max_req_queues, ha->msix_count); 1707 return 0; 1708 1709 iospace_error_exit: 1710 return -ENOMEM; 1711 } 1712 1713 /* GS related functions */ 1714 1715 /* Initialization related functions */ 1716 1717 /** 1718 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1719 * @ha: HA context 1720 * 1721 * Returns 0 on success. 1722 */ 1723 int 1724 qla82xx_pci_config(scsi_qla_host_t *vha) 1725 { 1726 struct qla_hw_data *ha = vha->hw; 1727 int ret; 1728 1729 pci_set_master(ha->pdev); 1730 ret = pci_set_mwi(ha->pdev); 1731 ha->chip_revision = ha->pdev->revision; 1732 ql_dbg(ql_dbg_init, vha, 0x0043, 1733 "Chip revision:%d.\n", 1734 ha->chip_revision); 1735 return 0; 1736 } 1737 1738 /** 1739 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1740 * @ha: HA context 1741 * 1742 * Returns 0 on success. 1743 */ 1744 void 1745 qla82xx_reset_chip(scsi_qla_host_t *vha) 1746 { 1747 struct qla_hw_data *ha = vha->hw; 1748 ha->isp_ops->disable_intrs(ha); 1749 } 1750 1751 void qla82xx_config_rings(struct scsi_qla_host *vha) 1752 { 1753 struct qla_hw_data *ha = vha->hw; 1754 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1755 struct init_cb_81xx *icb; 1756 struct req_que *req = ha->req_q_map[0]; 1757 struct rsp_que *rsp = ha->rsp_q_map[0]; 1758 1759 /* Setup ring parameters in initialization control block. */ 1760 icb = (struct init_cb_81xx *)ha->init_cb; 1761 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1762 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1763 icb->request_q_length = cpu_to_le16(req->length); 1764 icb->response_q_length = cpu_to_le16(rsp->length); 1765 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1766 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1767 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1768 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1769 1770 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1771 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1772 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1773 } 1774 1775 static int 1776 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1777 { 1778 u64 *ptr64; 1779 u32 i, flashaddr, size; 1780 __le64 data; 1781 1782 size = (IMAGE_START - BOOTLD_START) / 8; 1783 1784 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1785 flashaddr = BOOTLD_START; 1786 1787 for (i = 0; i < size; i++) { 1788 data = cpu_to_le64(ptr64[i]); 1789 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1790 return -EIO; 1791 flashaddr += 8; 1792 } 1793 1794 flashaddr = FLASH_ADDR_START; 1795 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1796 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1797 1798 for (i = 0; i < size; i++) { 1799 data = cpu_to_le64(ptr64[i]); 1800 1801 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1802 return -EIO; 1803 flashaddr += 8; 1804 } 1805 udelay(100); 1806 1807 /* Write a magic value to CAMRAM register 1808 * at a specified offset to indicate 1809 * that all data is written and 1810 * ready for firmware to initialize. 1811 */ 1812 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1813 1814 read_lock(&ha->hw_lock); 1815 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1816 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1817 read_unlock(&ha->hw_lock); 1818 return 0; 1819 } 1820 1821 static int 1822 qla82xx_set_product_offset(struct qla_hw_data *ha) 1823 { 1824 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1825 const uint8_t *unirom = ha->hablob->fw->data; 1826 uint32_t i; 1827 __le32 entries; 1828 __le32 flags, file_chiprev, offset; 1829 uint8_t chiprev = ha->chip_revision; 1830 /* Hardcoding mn_present flag for P3P */ 1831 int mn_present = 0; 1832 uint32_t flagbit; 1833 1834 ptab_desc = qla82xx_get_table_desc(unirom, 1835 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1836 if (!ptab_desc) 1837 return -1; 1838 1839 entries = cpu_to_le32(ptab_desc->num_entries); 1840 1841 for (i = 0; i < entries; i++) { 1842 offset = cpu_to_le32(ptab_desc->findex) + 1843 (i * cpu_to_le32(ptab_desc->entry_size)); 1844 flags = cpu_to_le32(*((int *)&unirom[offset] + 1845 QLA82XX_URI_FLAGS_OFF)); 1846 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1847 QLA82XX_URI_CHIP_REV_OFF)); 1848 1849 flagbit = mn_present ? 1 : 2; 1850 1851 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1852 ha->file_prd_off = offset; 1853 return 0; 1854 } 1855 } 1856 return -1; 1857 } 1858 1859 static int 1860 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1861 { 1862 __le32 val; 1863 uint32_t min_size; 1864 struct qla_hw_data *ha = vha->hw; 1865 const struct firmware *fw = ha->hablob->fw; 1866 1867 ha->fw_type = fw_type; 1868 1869 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1870 if (qla82xx_set_product_offset(ha)) 1871 return -EINVAL; 1872 1873 min_size = QLA82XX_URI_FW_MIN_SIZE; 1874 } else { 1875 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1876 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1877 return -EINVAL; 1878 1879 min_size = QLA82XX_FW_MIN_SIZE; 1880 } 1881 1882 if (fw->size < min_size) 1883 return -EINVAL; 1884 return 0; 1885 } 1886 1887 static int 1888 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1889 { 1890 u32 val = 0; 1891 int retries = 60; 1892 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1893 1894 do { 1895 read_lock(&ha->hw_lock); 1896 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1897 read_unlock(&ha->hw_lock); 1898 1899 switch (val) { 1900 case PHAN_INITIALIZE_COMPLETE: 1901 case PHAN_INITIALIZE_ACK: 1902 return QLA_SUCCESS; 1903 case PHAN_INITIALIZE_FAILED: 1904 break; 1905 default: 1906 break; 1907 } 1908 ql_log(ql_log_info, vha, 0x00a8, 1909 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1910 val, retries); 1911 1912 msleep(500); 1913 1914 } while (--retries); 1915 1916 ql_log(ql_log_fatal, vha, 0x00a9, 1917 "Cmd Peg initialization failed: 0x%x.\n", val); 1918 1919 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1920 read_lock(&ha->hw_lock); 1921 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1922 read_unlock(&ha->hw_lock); 1923 return QLA_FUNCTION_FAILED; 1924 } 1925 1926 static int 1927 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1928 { 1929 u32 val = 0; 1930 int retries = 60; 1931 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1932 1933 do { 1934 read_lock(&ha->hw_lock); 1935 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1936 read_unlock(&ha->hw_lock); 1937 1938 switch (val) { 1939 case PHAN_INITIALIZE_COMPLETE: 1940 case PHAN_INITIALIZE_ACK: 1941 return QLA_SUCCESS; 1942 case PHAN_INITIALIZE_FAILED: 1943 break; 1944 default: 1945 break; 1946 } 1947 ql_log(ql_log_info, vha, 0x00ab, 1948 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1949 val, retries); 1950 1951 msleep(500); 1952 1953 } while (--retries); 1954 1955 ql_log(ql_log_fatal, vha, 0x00ac, 1956 "Rcv Peg initializatin failed: 0x%x.\n", val); 1957 read_lock(&ha->hw_lock); 1958 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1959 read_unlock(&ha->hw_lock); 1960 return QLA_FUNCTION_FAILED; 1961 } 1962 1963 /* ISR related functions */ 1964 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1965 QLA82XX_LEGACY_INTR_CONFIG; 1966 1967 /* 1968 * qla82xx_mbx_completion() - Process mailbox command completions. 1969 * @ha: SCSI driver HA context 1970 * @mb0: Mailbox0 register 1971 */ 1972 void 1973 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1974 { 1975 uint16_t cnt; 1976 uint16_t __iomem *wptr; 1977 struct qla_hw_data *ha = vha->hw; 1978 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1979 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1980 1981 /* Load return mailbox registers. */ 1982 ha->flags.mbox_int = 1; 1983 ha->mailbox_out[0] = mb0; 1984 1985 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1986 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1987 wptr++; 1988 } 1989 1990 if (!ha->mcp) 1991 ql_dbg(ql_dbg_async, vha, 0x5053, 1992 "MBX pointer ERROR.\n"); 1993 } 1994 1995 /* 1996 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1997 * @irq: 1998 * @dev_id: SCSI driver HA context 1999 * @regs: 2000 * 2001 * Called by system whenever the host adapter generates an interrupt. 2002 * 2003 * Returns handled flag. 2004 */ 2005 irqreturn_t 2006 qla82xx_intr_handler(int irq, void *dev_id) 2007 { 2008 scsi_qla_host_t *vha; 2009 struct qla_hw_data *ha; 2010 struct rsp_que *rsp; 2011 struct device_reg_82xx __iomem *reg; 2012 int status = 0, status1 = 0; 2013 unsigned long flags; 2014 unsigned long iter; 2015 uint32_t stat = 0; 2016 uint16_t mb[4]; 2017 2018 rsp = (struct rsp_que *) dev_id; 2019 if (!rsp) { 2020 ql_log(ql_log_info, NULL, 0xb053, 2021 "%s: NULL response queue pointer.\n", __func__); 2022 return IRQ_NONE; 2023 } 2024 ha = rsp->hw; 2025 2026 if (!ha->flags.msi_enabled) { 2027 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2028 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2029 return IRQ_NONE; 2030 2031 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2032 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2033 return IRQ_NONE; 2034 } 2035 2036 /* clear the interrupt */ 2037 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2038 2039 /* read twice to ensure write is flushed */ 2040 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2041 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2042 2043 reg = &ha->iobase->isp82; 2044 2045 spin_lock_irqsave(&ha->hardware_lock, flags); 2046 vha = pci_get_drvdata(ha->pdev); 2047 for (iter = 1; iter--; ) { 2048 2049 if (RD_REG_DWORD(®->host_int)) { 2050 stat = RD_REG_DWORD(®->host_status); 2051 2052 switch (stat & 0xff) { 2053 case 0x1: 2054 case 0x2: 2055 case 0x10: 2056 case 0x11: 2057 qla82xx_mbx_completion(vha, MSW(stat)); 2058 status |= MBX_INTERRUPT; 2059 break; 2060 case 0x12: 2061 mb[0] = MSW(stat); 2062 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2063 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2064 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2065 qla2x00_async_event(vha, rsp, mb); 2066 break; 2067 case 0x13: 2068 qla24xx_process_response_queue(vha, rsp); 2069 break; 2070 default: 2071 ql_dbg(ql_dbg_async, vha, 0x5054, 2072 "Unrecognized interrupt type (%d).\n", 2073 stat & 0xff); 2074 break; 2075 } 2076 } 2077 WRT_REG_DWORD(®->host_int, 0); 2078 } 2079 2080 qla2x00_handle_mbx_completion(ha, status); 2081 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2082 2083 if (!ha->flags.msi_enabled) 2084 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2085 2086 return IRQ_HANDLED; 2087 } 2088 2089 irqreturn_t 2090 qla82xx_msix_default(int irq, void *dev_id) 2091 { 2092 scsi_qla_host_t *vha; 2093 struct qla_hw_data *ha; 2094 struct rsp_que *rsp; 2095 struct device_reg_82xx __iomem *reg; 2096 int status = 0; 2097 unsigned long flags; 2098 uint32_t stat = 0; 2099 uint32_t host_int = 0; 2100 uint16_t mb[4]; 2101 2102 rsp = (struct rsp_que *) dev_id; 2103 if (!rsp) { 2104 printk(KERN_INFO 2105 "%s(): NULL response queue pointer.\n", __func__); 2106 return IRQ_NONE; 2107 } 2108 ha = rsp->hw; 2109 2110 reg = &ha->iobase->isp82; 2111 2112 spin_lock_irqsave(&ha->hardware_lock, flags); 2113 vha = pci_get_drvdata(ha->pdev); 2114 do { 2115 host_int = RD_REG_DWORD(®->host_int); 2116 if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2117 break; 2118 if (host_int) { 2119 stat = RD_REG_DWORD(®->host_status); 2120 2121 switch (stat & 0xff) { 2122 case 0x1: 2123 case 0x2: 2124 case 0x10: 2125 case 0x11: 2126 qla82xx_mbx_completion(vha, MSW(stat)); 2127 status |= MBX_INTERRUPT; 2128 break; 2129 case 0x12: 2130 mb[0] = MSW(stat); 2131 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2132 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2133 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2134 qla2x00_async_event(vha, rsp, mb); 2135 break; 2136 case 0x13: 2137 qla24xx_process_response_queue(vha, rsp); 2138 break; 2139 default: 2140 ql_dbg(ql_dbg_async, vha, 0x5041, 2141 "Unrecognized interrupt type (%d).\n", 2142 stat & 0xff); 2143 break; 2144 } 2145 } 2146 WRT_REG_DWORD(®->host_int, 0); 2147 } while (0); 2148 2149 qla2x00_handle_mbx_completion(ha, status); 2150 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2151 2152 return IRQ_HANDLED; 2153 } 2154 2155 irqreturn_t 2156 qla82xx_msix_rsp_q(int irq, void *dev_id) 2157 { 2158 scsi_qla_host_t *vha; 2159 struct qla_hw_data *ha; 2160 struct rsp_que *rsp; 2161 struct device_reg_82xx __iomem *reg; 2162 unsigned long flags; 2163 uint32_t host_int = 0; 2164 2165 rsp = (struct rsp_que *) dev_id; 2166 if (!rsp) { 2167 printk(KERN_INFO 2168 "%s(): NULL response queue pointer.\n", __func__); 2169 return IRQ_NONE; 2170 } 2171 2172 ha = rsp->hw; 2173 reg = &ha->iobase->isp82; 2174 spin_lock_irqsave(&ha->hardware_lock, flags); 2175 vha = pci_get_drvdata(ha->pdev); 2176 host_int = RD_REG_DWORD(®->host_int); 2177 if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2178 goto out; 2179 qla24xx_process_response_queue(vha, rsp); 2180 WRT_REG_DWORD(®->host_int, 0); 2181 out: 2182 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2183 return IRQ_HANDLED; 2184 } 2185 2186 void 2187 qla82xx_poll(int irq, void *dev_id) 2188 { 2189 scsi_qla_host_t *vha; 2190 struct qla_hw_data *ha; 2191 struct rsp_que *rsp; 2192 struct device_reg_82xx __iomem *reg; 2193 int status = 0; 2194 uint32_t stat; 2195 uint32_t host_int = 0; 2196 uint16_t mb[4]; 2197 unsigned long flags; 2198 2199 rsp = (struct rsp_que *) dev_id; 2200 if (!rsp) { 2201 printk(KERN_INFO 2202 "%s(): NULL response queue pointer.\n", __func__); 2203 return; 2204 } 2205 ha = rsp->hw; 2206 2207 reg = &ha->iobase->isp82; 2208 spin_lock_irqsave(&ha->hardware_lock, flags); 2209 vha = pci_get_drvdata(ha->pdev); 2210 2211 host_int = RD_REG_DWORD(®->host_int); 2212 if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2213 goto out; 2214 if (host_int) { 2215 stat = RD_REG_DWORD(®->host_status); 2216 switch (stat & 0xff) { 2217 case 0x1: 2218 case 0x2: 2219 case 0x10: 2220 case 0x11: 2221 qla82xx_mbx_completion(vha, MSW(stat)); 2222 status |= MBX_INTERRUPT; 2223 break; 2224 case 0x12: 2225 mb[0] = MSW(stat); 2226 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2227 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2228 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2229 qla2x00_async_event(vha, rsp, mb); 2230 break; 2231 case 0x13: 2232 qla24xx_process_response_queue(vha, rsp); 2233 break; 2234 default: 2235 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2236 "Unrecognized interrupt type (%d).\n", 2237 stat * 0xff); 2238 break; 2239 } 2240 WRT_REG_DWORD(®->host_int, 0); 2241 } 2242 out: 2243 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2244 } 2245 2246 void 2247 qla82xx_enable_intrs(struct qla_hw_data *ha) 2248 { 2249 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2250 qla82xx_mbx_intr_enable(vha); 2251 spin_lock_irq(&ha->hardware_lock); 2252 if (IS_QLA8044(ha)) 2253 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2254 else 2255 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2256 spin_unlock_irq(&ha->hardware_lock); 2257 ha->interrupts_on = 1; 2258 } 2259 2260 void 2261 qla82xx_disable_intrs(struct qla_hw_data *ha) 2262 { 2263 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2264 qla82xx_mbx_intr_disable(vha); 2265 spin_lock_irq(&ha->hardware_lock); 2266 if (IS_QLA8044(ha)) 2267 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2268 else 2269 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2270 spin_unlock_irq(&ha->hardware_lock); 2271 ha->interrupts_on = 0; 2272 } 2273 2274 void qla82xx_init_flags(struct qla_hw_data *ha) 2275 { 2276 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2277 2278 /* ISP 8021 initializations */ 2279 rwlock_init(&ha->hw_lock); 2280 ha->qdr_sn_window = -1; 2281 ha->ddr_mn_window = -1; 2282 ha->curr_window = 255; 2283 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2284 nx_legacy_intr = &legacy_intr[ha->portnum]; 2285 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2286 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2287 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2288 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2289 } 2290 2291 inline void 2292 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2293 { 2294 int idc_ver; 2295 uint32_t drv_active; 2296 struct qla_hw_data *ha = vha->hw; 2297 2298 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2299 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2300 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2301 QLA82XX_IDC_VERSION); 2302 ql_log(ql_log_info, vha, 0xb082, 2303 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2304 } else { 2305 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2306 if (idc_ver != QLA82XX_IDC_VERSION) 2307 ql_log(ql_log_info, vha, 0xb083, 2308 "qla2xxx driver IDC version %d is not compatible " 2309 "with IDC version %d of the other drivers\n", 2310 QLA82XX_IDC_VERSION, idc_ver); 2311 } 2312 } 2313 2314 inline void 2315 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2316 { 2317 uint32_t drv_active; 2318 struct qla_hw_data *ha = vha->hw; 2319 2320 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2321 2322 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2323 if (drv_active == 0xffffffff) { 2324 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2325 QLA82XX_DRV_NOT_ACTIVE); 2326 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2327 } 2328 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2329 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2330 } 2331 2332 inline void 2333 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2334 { 2335 uint32_t drv_active; 2336 2337 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2338 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2340 } 2341 2342 static inline int 2343 qla82xx_need_reset(struct qla_hw_data *ha) 2344 { 2345 uint32_t drv_state; 2346 int rval; 2347 2348 if (ha->flags.nic_core_reset_owner) 2349 return 1; 2350 else { 2351 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2352 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2353 return rval; 2354 } 2355 } 2356 2357 static inline void 2358 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2359 { 2360 uint32_t drv_state; 2361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2362 2363 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2364 2365 /* If reset value is all FF's, initialize DRV_STATE */ 2366 if (drv_state == 0xffffffff) { 2367 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2368 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2369 } 2370 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2371 ql_dbg(ql_dbg_init, vha, 0x00bb, 2372 "drv_state = 0x%08x.\n", drv_state); 2373 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2374 } 2375 2376 static inline void 2377 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2378 { 2379 uint32_t drv_state; 2380 2381 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2384 } 2385 2386 static inline void 2387 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2388 { 2389 uint32_t qsnt_state; 2390 2391 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2392 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2394 } 2395 2396 void 2397 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2398 { 2399 struct qla_hw_data *ha = vha->hw; 2400 uint32_t qsnt_state; 2401 2402 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2403 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2404 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2405 } 2406 2407 static int 2408 qla82xx_load_fw(scsi_qla_host_t *vha) 2409 { 2410 int rst; 2411 struct fw_blob *blob; 2412 struct qla_hw_data *ha = vha->hw; 2413 2414 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2415 ql_log(ql_log_fatal, vha, 0x009f, 2416 "Error during CRB initialization.\n"); 2417 return QLA_FUNCTION_FAILED; 2418 } 2419 udelay(500); 2420 2421 /* Bring QM and CAMRAM out of reset */ 2422 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2423 rst &= ~((1 << 28) | (1 << 24)); 2424 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2425 2426 /* 2427 * FW Load priority: 2428 * 1) Operational firmware residing in flash. 2429 * 2) Firmware via request-firmware interface (.bin file). 2430 */ 2431 if (ql2xfwloadbin == 2) 2432 goto try_blob_fw; 2433 2434 ql_log(ql_log_info, vha, 0x00a0, 2435 "Attempting to load firmware from flash.\n"); 2436 2437 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2438 ql_log(ql_log_info, vha, 0x00a1, 2439 "Firmware loaded successfully from flash.\n"); 2440 return QLA_SUCCESS; 2441 } else { 2442 ql_log(ql_log_warn, vha, 0x0108, 2443 "Firmware load from flash failed.\n"); 2444 } 2445 2446 try_blob_fw: 2447 ql_log(ql_log_info, vha, 0x00a2, 2448 "Attempting to load firmware from blob.\n"); 2449 2450 /* Load firmware blob. */ 2451 blob = ha->hablob = qla2x00_request_firmware(vha); 2452 if (!blob) { 2453 ql_log(ql_log_fatal, vha, 0x00a3, 2454 "Firmware image not present.\n"); 2455 goto fw_load_failed; 2456 } 2457 2458 /* Validating firmware blob */ 2459 if (qla82xx_validate_firmware_blob(vha, 2460 QLA82XX_FLASH_ROMIMAGE)) { 2461 /* Fallback to URI format */ 2462 if (qla82xx_validate_firmware_blob(vha, 2463 QLA82XX_UNIFIED_ROMIMAGE)) { 2464 ql_log(ql_log_fatal, vha, 0x00a4, 2465 "No valid firmware image found.\n"); 2466 return QLA_FUNCTION_FAILED; 2467 } 2468 } 2469 2470 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2471 ql_log(ql_log_info, vha, 0x00a5, 2472 "Firmware loaded successfully from binary blob.\n"); 2473 return QLA_SUCCESS; 2474 } else { 2475 ql_log(ql_log_fatal, vha, 0x00a6, 2476 "Firmware load failed for binary blob.\n"); 2477 blob->fw = NULL; 2478 blob = NULL; 2479 goto fw_load_failed; 2480 } 2481 return QLA_SUCCESS; 2482 2483 fw_load_failed: 2484 return QLA_FUNCTION_FAILED; 2485 } 2486 2487 int 2488 qla82xx_start_firmware(scsi_qla_host_t *vha) 2489 { 2490 uint16_t lnk; 2491 struct qla_hw_data *ha = vha->hw; 2492 2493 /* scrub dma mask expansion register */ 2494 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2495 2496 /* Put both the PEG CMD and RCV PEG to default state 2497 * of 0 before resetting the hardware 2498 */ 2499 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2500 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2501 2502 /* Overwrite stale initialization register values */ 2503 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2504 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2505 2506 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2507 ql_log(ql_log_fatal, vha, 0x00a7, 2508 "Error trying to start fw.\n"); 2509 return QLA_FUNCTION_FAILED; 2510 } 2511 2512 /* Handshake with the card before we register the devices. */ 2513 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2514 ql_log(ql_log_fatal, vha, 0x00aa, 2515 "Error during card handshake.\n"); 2516 return QLA_FUNCTION_FAILED; 2517 } 2518 2519 /* Negotiated Link width */ 2520 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2521 ha->link_width = (lnk >> 4) & 0x3f; 2522 2523 /* Synchronize with Receive peg */ 2524 return qla82xx_check_rcvpeg_state(ha); 2525 } 2526 2527 static uint32_t * 2528 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2529 uint32_t length) 2530 { 2531 uint32_t i; 2532 uint32_t val; 2533 struct qla_hw_data *ha = vha->hw; 2534 2535 /* Dword reads to flash. */ 2536 for (i = 0; i < length/4; i++, faddr += 4) { 2537 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2538 ql_log(ql_log_warn, vha, 0x0106, 2539 "Do ROM fast read failed.\n"); 2540 goto done_read; 2541 } 2542 dwptr[i] = __constant_cpu_to_le32(val); 2543 } 2544 done_read: 2545 return dwptr; 2546 } 2547 2548 static int 2549 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2550 { 2551 int ret; 2552 uint32_t val; 2553 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2554 2555 ret = ql82xx_rom_lock_d(ha); 2556 if (ret < 0) { 2557 ql_log(ql_log_warn, vha, 0xb014, 2558 "ROM Lock failed.\n"); 2559 return ret; 2560 } 2561 2562 ret = qla82xx_read_status_reg(ha, &val); 2563 if (ret < 0) 2564 goto done_unprotect; 2565 2566 val &= ~(BLOCK_PROTECT_BITS << 2); 2567 ret = qla82xx_write_status_reg(ha, val); 2568 if (ret < 0) { 2569 val |= (BLOCK_PROTECT_BITS << 2); 2570 qla82xx_write_status_reg(ha, val); 2571 } 2572 2573 if (qla82xx_write_disable_flash(ha) != 0) 2574 ql_log(ql_log_warn, vha, 0xb015, 2575 "Write disable failed.\n"); 2576 2577 done_unprotect: 2578 qla82xx_rom_unlock(ha); 2579 return ret; 2580 } 2581 2582 static int 2583 qla82xx_protect_flash(struct qla_hw_data *ha) 2584 { 2585 int ret; 2586 uint32_t val; 2587 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2588 2589 ret = ql82xx_rom_lock_d(ha); 2590 if (ret < 0) { 2591 ql_log(ql_log_warn, vha, 0xb016, 2592 "ROM Lock failed.\n"); 2593 return ret; 2594 } 2595 2596 ret = qla82xx_read_status_reg(ha, &val); 2597 if (ret < 0) 2598 goto done_protect; 2599 2600 val |= (BLOCK_PROTECT_BITS << 2); 2601 /* LOCK all sectors */ 2602 ret = qla82xx_write_status_reg(ha, val); 2603 if (ret < 0) 2604 ql_log(ql_log_warn, vha, 0xb017, 2605 "Write status register failed.\n"); 2606 2607 if (qla82xx_write_disable_flash(ha) != 0) 2608 ql_log(ql_log_warn, vha, 0xb018, 2609 "Write disable failed.\n"); 2610 done_protect: 2611 qla82xx_rom_unlock(ha); 2612 return ret; 2613 } 2614 2615 static int 2616 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2617 { 2618 int ret = 0; 2619 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2620 2621 ret = ql82xx_rom_lock_d(ha); 2622 if (ret < 0) { 2623 ql_log(ql_log_warn, vha, 0xb019, 2624 "ROM Lock failed.\n"); 2625 return ret; 2626 } 2627 2628 qla82xx_flash_set_write_enable(ha); 2629 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2630 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2631 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2632 2633 if (qla82xx_wait_rom_done(ha)) { 2634 ql_log(ql_log_warn, vha, 0xb01a, 2635 "Error waiting for rom done.\n"); 2636 ret = -1; 2637 goto done; 2638 } 2639 ret = qla82xx_flash_wait_write_finish(ha); 2640 done: 2641 qla82xx_rom_unlock(ha); 2642 return ret; 2643 } 2644 2645 /* 2646 * Address and length are byte address 2647 */ 2648 uint8_t * 2649 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2650 uint32_t offset, uint32_t length) 2651 { 2652 scsi_block_requests(vha->host); 2653 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2654 scsi_unblock_requests(vha->host); 2655 return buf; 2656 } 2657 2658 static int 2659 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2660 uint32_t faddr, uint32_t dwords) 2661 { 2662 int ret; 2663 uint32_t liter; 2664 uint32_t sec_mask, rest_addr; 2665 dma_addr_t optrom_dma; 2666 void *optrom = NULL; 2667 int page_mode = 0; 2668 struct qla_hw_data *ha = vha->hw; 2669 2670 ret = -1; 2671 2672 /* Prepare burst-capable write on supported ISPs. */ 2673 if (page_mode && !(faddr & 0xfff) && 2674 dwords > OPTROM_BURST_DWORDS) { 2675 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2676 &optrom_dma, GFP_KERNEL); 2677 if (!optrom) { 2678 ql_log(ql_log_warn, vha, 0xb01b, 2679 "Unable to allocate memory " 2680 "for optrom burst write (%x KB).\n", 2681 OPTROM_BURST_SIZE / 1024); 2682 } 2683 } 2684 2685 rest_addr = ha->fdt_block_size - 1; 2686 sec_mask = ~rest_addr; 2687 2688 ret = qla82xx_unprotect_flash(ha); 2689 if (ret) { 2690 ql_log(ql_log_warn, vha, 0xb01c, 2691 "Unable to unprotect flash for update.\n"); 2692 goto write_done; 2693 } 2694 2695 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2696 /* Are we at the beginning of a sector? */ 2697 if ((faddr & rest_addr) == 0) { 2698 2699 ret = qla82xx_erase_sector(ha, faddr); 2700 if (ret) { 2701 ql_log(ql_log_warn, vha, 0xb01d, 2702 "Unable to erase sector: address=%x.\n", 2703 faddr); 2704 break; 2705 } 2706 } 2707 2708 /* Go with burst-write. */ 2709 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2710 /* Copy data to DMA'ble buffer. */ 2711 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2712 2713 ret = qla2x00_load_ram(vha, optrom_dma, 2714 (ha->flash_data_off | faddr), 2715 OPTROM_BURST_DWORDS); 2716 if (ret != QLA_SUCCESS) { 2717 ql_log(ql_log_warn, vha, 0xb01e, 2718 "Unable to burst-write optrom segment " 2719 "(%x/%x/%llx).\n", ret, 2720 (ha->flash_data_off | faddr), 2721 (unsigned long long)optrom_dma); 2722 ql_log(ql_log_warn, vha, 0xb01f, 2723 "Reverting to slow-write.\n"); 2724 2725 dma_free_coherent(&ha->pdev->dev, 2726 OPTROM_BURST_SIZE, optrom, optrom_dma); 2727 optrom = NULL; 2728 } else { 2729 liter += OPTROM_BURST_DWORDS - 1; 2730 faddr += OPTROM_BURST_DWORDS - 1; 2731 dwptr += OPTROM_BURST_DWORDS - 1; 2732 continue; 2733 } 2734 } 2735 2736 ret = qla82xx_write_flash_dword(ha, faddr, 2737 cpu_to_le32(*dwptr)); 2738 if (ret) { 2739 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2740 "Unable to program flash address=%x data=%x.\n", 2741 faddr, *dwptr); 2742 break; 2743 } 2744 } 2745 2746 ret = qla82xx_protect_flash(ha); 2747 if (ret) 2748 ql_log(ql_log_warn, vha, 0xb021, 2749 "Unable to protect flash after update.\n"); 2750 write_done: 2751 if (optrom) 2752 dma_free_coherent(&ha->pdev->dev, 2753 OPTROM_BURST_SIZE, optrom, optrom_dma); 2754 return ret; 2755 } 2756 2757 int 2758 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2759 uint32_t offset, uint32_t length) 2760 { 2761 int rval; 2762 2763 /* Suspend HBA. */ 2764 scsi_block_requests(vha->host); 2765 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2766 length >> 2); 2767 scsi_unblock_requests(vha->host); 2768 2769 /* Convert return ISP82xx to generic */ 2770 if (rval) 2771 rval = QLA_FUNCTION_FAILED; 2772 else 2773 rval = QLA_SUCCESS; 2774 return rval; 2775 } 2776 2777 void 2778 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2779 { 2780 struct qla_hw_data *ha = vha->hw; 2781 struct req_que *req = ha->req_q_map[0]; 2782 struct device_reg_82xx __iomem *reg; 2783 uint32_t dbval; 2784 2785 /* Adjust ring index. */ 2786 req->ring_index++; 2787 if (req->ring_index == req->length) { 2788 req->ring_index = 0; 2789 req->ring_ptr = req->ring; 2790 } else 2791 req->ring_ptr++; 2792 2793 reg = &ha->iobase->isp82; 2794 dbval = 0x04 | (ha->portnum << 5); 2795 2796 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2797 if (ql2xdbwr) 2798 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2799 else { 2800 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2801 wmb(); 2802 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 2803 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2804 dbval); 2805 wmb(); 2806 } 2807 } 2808 } 2809 2810 static void 2811 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2812 { 2813 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2814 2815 if (qla82xx_rom_lock(ha)) 2816 /* Someone else is holding the lock. */ 2817 ql_log(ql_log_info, vha, 0xb022, 2818 "Resetting rom_lock.\n"); 2819 2820 /* 2821 * Either we got the lock, or someone 2822 * else died while holding it. 2823 * In either case, unlock. 2824 */ 2825 qla82xx_rom_unlock(ha); 2826 } 2827 2828 /* 2829 * qla82xx_device_bootstrap 2830 * Initialize device, set DEV_READY, start fw 2831 * 2832 * Note: 2833 * IDC lock must be held upon entry 2834 * 2835 * Return: 2836 * Success : 0 2837 * Failed : 1 2838 */ 2839 static int 2840 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2841 { 2842 int rval = QLA_SUCCESS; 2843 int i, timeout; 2844 uint32_t old_count, count; 2845 struct qla_hw_data *ha = vha->hw; 2846 int need_reset = 0, peg_stuck = 1; 2847 2848 need_reset = qla82xx_need_reset(ha); 2849 2850 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2851 2852 for (i = 0; i < 10; i++) { 2853 timeout = msleep_interruptible(200); 2854 if (timeout) { 2855 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2856 QLA8XXX_DEV_FAILED); 2857 return QLA_FUNCTION_FAILED; 2858 } 2859 2860 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2861 if (count != old_count) 2862 peg_stuck = 0; 2863 } 2864 2865 if (need_reset) { 2866 /* We are trying to perform a recovery here. */ 2867 if (peg_stuck) 2868 qla82xx_rom_lock_recovery(ha); 2869 goto dev_initialize; 2870 } else { 2871 /* Start of day for this ha context. */ 2872 if (peg_stuck) { 2873 /* Either we are the first or recovery in progress. */ 2874 qla82xx_rom_lock_recovery(ha); 2875 goto dev_initialize; 2876 } else 2877 /* Firmware already running. */ 2878 goto dev_ready; 2879 } 2880 2881 return rval; 2882 2883 dev_initialize: 2884 /* set to DEV_INITIALIZING */ 2885 ql_log(ql_log_info, vha, 0x009e, 2886 "HW State: INITIALIZING.\n"); 2887 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2888 2889 qla82xx_idc_unlock(ha); 2890 rval = qla82xx_start_firmware(vha); 2891 qla82xx_idc_lock(ha); 2892 2893 if (rval != QLA_SUCCESS) { 2894 ql_log(ql_log_fatal, vha, 0x00ad, 2895 "HW State: FAILED.\n"); 2896 qla82xx_clear_drv_active(ha); 2897 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2898 return rval; 2899 } 2900 2901 dev_ready: 2902 ql_log(ql_log_info, vha, 0x00ae, 2903 "HW State: READY.\n"); 2904 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2905 2906 return QLA_SUCCESS; 2907 } 2908 2909 /* 2910 * qla82xx_need_qsnt_handler 2911 * Code to start quiescence sequence 2912 * 2913 * Note: 2914 * IDC lock must be held upon entry 2915 * 2916 * Return: void 2917 */ 2918 2919 static void 2920 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2921 { 2922 struct qla_hw_data *ha = vha->hw; 2923 uint32_t dev_state, drv_state, drv_active; 2924 unsigned long reset_timeout; 2925 2926 if (vha->flags.online) { 2927 /*Block any further I/O and wait for pending cmnds to complete*/ 2928 qla2x00_quiesce_io(vha); 2929 } 2930 2931 /* Set the quiescence ready bit */ 2932 qla82xx_set_qsnt_ready(ha); 2933 2934 /*wait for 30 secs for other functions to ack */ 2935 reset_timeout = jiffies + (30 * HZ); 2936 2937 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2938 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2939 /* Its 2 that is written when qsnt is acked, moving one bit */ 2940 drv_active = drv_active << 0x01; 2941 2942 while (drv_state != drv_active) { 2943 2944 if (time_after_eq(jiffies, reset_timeout)) { 2945 /* quiescence timeout, other functions didn't ack 2946 * changing the state to DEV_READY 2947 */ 2948 ql_log(ql_log_info, vha, 0xb023, 2949 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2950 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2951 drv_active, drv_state); 2952 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2953 QLA8XXX_DEV_READY); 2954 ql_log(ql_log_info, vha, 0xb025, 2955 "HW State: DEV_READY.\n"); 2956 qla82xx_idc_unlock(ha); 2957 qla2x00_perform_loop_resync(vha); 2958 qla82xx_idc_lock(ha); 2959 2960 qla82xx_clear_qsnt_ready(vha); 2961 return; 2962 } 2963 2964 qla82xx_idc_unlock(ha); 2965 msleep(1000); 2966 qla82xx_idc_lock(ha); 2967 2968 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2969 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2970 drv_active = drv_active << 0x01; 2971 } 2972 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2973 /* everyone acked so set the state to DEV_QUIESCENCE */ 2974 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2975 ql_log(ql_log_info, vha, 0xb026, 2976 "HW State: DEV_QUIESCENT.\n"); 2977 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2978 } 2979 } 2980 2981 /* 2982 * qla82xx_wait_for_state_change 2983 * Wait for device state to change from given current state 2984 * 2985 * Note: 2986 * IDC lock must not be held upon entry 2987 * 2988 * Return: 2989 * Changed device state. 2990 */ 2991 uint32_t 2992 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2993 { 2994 struct qla_hw_data *ha = vha->hw; 2995 uint32_t dev_state; 2996 2997 do { 2998 msleep(1000); 2999 qla82xx_idc_lock(ha); 3000 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3001 qla82xx_idc_unlock(ha); 3002 } while (dev_state == curr_state); 3003 3004 return dev_state; 3005 } 3006 3007 void 3008 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3009 { 3010 struct qla_hw_data *ha = vha->hw; 3011 3012 /* Disable the board */ 3013 ql_log(ql_log_fatal, vha, 0x00b8, 3014 "Disabling the board.\n"); 3015 3016 if (IS_QLA82XX(ha)) { 3017 qla82xx_clear_drv_active(ha); 3018 qla82xx_idc_unlock(ha); 3019 } else if (IS_QLA8044(ha)) { 3020 qla8044_clear_drv_active(ha); 3021 qla8044_idc_unlock(ha); 3022 } 3023 3024 /* Set DEV_FAILED flag to disable timer */ 3025 vha->device_flags |= DFLG_DEV_FAILED; 3026 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3027 qla2x00_mark_all_devices_lost(vha, 0); 3028 vha->flags.online = 0; 3029 vha->flags.init_done = 0; 3030 } 3031 3032 /* 3033 * qla82xx_need_reset_handler 3034 * Code to start reset sequence 3035 * 3036 * Note: 3037 * IDC lock must be held upon entry 3038 * 3039 * Return: 3040 * Success : 0 3041 * Failed : 1 3042 */ 3043 static void 3044 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3045 { 3046 uint32_t dev_state, drv_state, drv_active; 3047 uint32_t active_mask = 0; 3048 unsigned long reset_timeout; 3049 struct qla_hw_data *ha = vha->hw; 3050 struct req_que *req = ha->req_q_map[0]; 3051 3052 if (vha->flags.online) { 3053 qla82xx_idc_unlock(ha); 3054 qla2x00_abort_isp_cleanup(vha); 3055 ha->isp_ops->get_flash_version(vha, req->ring); 3056 ha->isp_ops->nvram_config(vha); 3057 qla82xx_idc_lock(ha); 3058 } 3059 3060 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3061 if (!ha->flags.nic_core_reset_owner) { 3062 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3063 "reset_acknowledged by 0x%x\n", ha->portnum); 3064 qla82xx_set_rst_ready(ha); 3065 } else { 3066 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3067 drv_active &= active_mask; 3068 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3069 "active_mask: 0x%08x\n", active_mask); 3070 } 3071 3072 /* wait for 10 seconds for reset ack from all functions */ 3073 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3074 3075 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3076 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3077 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3078 3079 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3080 "drv_state: 0x%08x, drv_active: 0x%08x, " 3081 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3082 drv_state, drv_active, dev_state, active_mask); 3083 3084 while (drv_state != drv_active && 3085 dev_state != QLA8XXX_DEV_INITIALIZING) { 3086 if (time_after_eq(jiffies, reset_timeout)) { 3087 ql_log(ql_log_warn, vha, 0x00b5, 3088 "Reset timeout.\n"); 3089 break; 3090 } 3091 qla82xx_idc_unlock(ha); 3092 msleep(1000); 3093 qla82xx_idc_lock(ha); 3094 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3095 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3096 if (ha->flags.nic_core_reset_owner) 3097 drv_active &= active_mask; 3098 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3099 } 3100 3101 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3102 "drv_state: 0x%08x, drv_active: 0x%08x, " 3103 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3104 drv_state, drv_active, dev_state, active_mask); 3105 3106 ql_log(ql_log_info, vha, 0x00b6, 3107 "Device state is 0x%x = %s.\n", 3108 dev_state, 3109 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3110 3111 /* Force to DEV_COLD unless someone else is starting a reset */ 3112 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3113 dev_state != QLA8XXX_DEV_COLD) { 3114 ql_log(ql_log_info, vha, 0x00b7, 3115 "HW State: COLD/RE-INIT.\n"); 3116 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3117 qla82xx_set_rst_ready(ha); 3118 if (ql2xmdenable) { 3119 if (qla82xx_md_collect(vha)) 3120 ql_log(ql_log_warn, vha, 0xb02c, 3121 "Minidump not collected.\n"); 3122 } else 3123 ql_log(ql_log_warn, vha, 0xb04f, 3124 "Minidump disabled.\n"); 3125 } 3126 } 3127 3128 int 3129 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3130 { 3131 struct qla_hw_data *ha = vha->hw; 3132 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3133 int rval = QLA_SUCCESS; 3134 3135 fw_major_version = ha->fw_major_version; 3136 fw_minor_version = ha->fw_minor_version; 3137 fw_subminor_version = ha->fw_subminor_version; 3138 3139 rval = qla2x00_get_fw_version(vha); 3140 if (rval != QLA_SUCCESS) 3141 return rval; 3142 3143 if (ql2xmdenable) { 3144 if (!ha->fw_dumped) { 3145 if (fw_major_version != ha->fw_major_version || 3146 fw_minor_version != ha->fw_minor_version || 3147 fw_subminor_version != ha->fw_subminor_version) { 3148 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3149 "Firmware version differs " 3150 "Previous version: %d:%d:%d - " 3151 "New version: %d:%d:%d\n", 3152 fw_major_version, fw_minor_version, 3153 fw_subminor_version, 3154 ha->fw_major_version, 3155 ha->fw_minor_version, 3156 ha->fw_subminor_version); 3157 /* Release MiniDump resources */ 3158 qla82xx_md_free(vha); 3159 /* ALlocate MiniDump resources */ 3160 qla82xx_md_prep(vha); 3161 } 3162 } else 3163 ql_log(ql_log_info, vha, 0xb02e, 3164 "Firmware dump available to retrieve\n"); 3165 } 3166 return rval; 3167 } 3168 3169 3170 static int 3171 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3172 { 3173 uint32_t fw_heartbeat_counter; 3174 int status = 0; 3175 3176 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3177 QLA82XX_PEG_ALIVE_COUNTER); 3178 /* all 0xff, assume AER/EEH in progress, ignore */ 3179 if (fw_heartbeat_counter == 0xffffffff) { 3180 ql_dbg(ql_dbg_timer, vha, 0x6003, 3181 "FW heartbeat counter is 0xffffffff, " 3182 "returning status=%d.\n", status); 3183 return status; 3184 } 3185 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3186 vha->seconds_since_last_heartbeat++; 3187 /* FW not alive after 2 seconds */ 3188 if (vha->seconds_since_last_heartbeat == 2) { 3189 vha->seconds_since_last_heartbeat = 0; 3190 status = 1; 3191 } 3192 } else 3193 vha->seconds_since_last_heartbeat = 0; 3194 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3195 if (status) 3196 ql_dbg(ql_dbg_timer, vha, 0x6004, 3197 "Returning status=%d.\n", status); 3198 return status; 3199 } 3200 3201 /* 3202 * qla82xx_device_state_handler 3203 * Main state handler 3204 * 3205 * Note: 3206 * IDC lock must be held upon entry 3207 * 3208 * Return: 3209 * Success : 0 3210 * Failed : 1 3211 */ 3212 int 3213 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3214 { 3215 uint32_t dev_state; 3216 uint32_t old_dev_state; 3217 int rval = QLA_SUCCESS; 3218 unsigned long dev_init_timeout; 3219 struct qla_hw_data *ha = vha->hw; 3220 int loopcount = 0; 3221 3222 qla82xx_idc_lock(ha); 3223 if (!vha->flags.init_done) { 3224 qla82xx_set_drv_active(vha); 3225 qla82xx_set_idc_version(vha); 3226 } 3227 3228 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3229 old_dev_state = dev_state; 3230 ql_log(ql_log_info, vha, 0x009b, 3231 "Device state is 0x%x = %s.\n", 3232 dev_state, 3233 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3234 3235 /* wait for 30 seconds for device to go ready */ 3236 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3237 3238 while (1) { 3239 3240 if (time_after_eq(jiffies, dev_init_timeout)) { 3241 ql_log(ql_log_fatal, vha, 0x009c, 3242 "Device init failed.\n"); 3243 rval = QLA_FUNCTION_FAILED; 3244 break; 3245 } 3246 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3247 if (old_dev_state != dev_state) { 3248 loopcount = 0; 3249 old_dev_state = dev_state; 3250 } 3251 if (loopcount < 5) { 3252 ql_log(ql_log_info, vha, 0x009d, 3253 "Device state is 0x%x = %s.\n", 3254 dev_state, 3255 dev_state < MAX_STATES ? qdev_state(dev_state) : 3256 "Unknown"); 3257 } 3258 3259 switch (dev_state) { 3260 case QLA8XXX_DEV_READY: 3261 ha->flags.nic_core_reset_owner = 0; 3262 goto rel_lock; 3263 case QLA8XXX_DEV_COLD: 3264 rval = qla82xx_device_bootstrap(vha); 3265 break; 3266 case QLA8XXX_DEV_INITIALIZING: 3267 qla82xx_idc_unlock(ha); 3268 msleep(1000); 3269 qla82xx_idc_lock(ha); 3270 break; 3271 case QLA8XXX_DEV_NEED_RESET: 3272 if (!ql2xdontresethba) 3273 qla82xx_need_reset_handler(vha); 3274 else { 3275 qla82xx_idc_unlock(ha); 3276 msleep(1000); 3277 qla82xx_idc_lock(ha); 3278 } 3279 dev_init_timeout = jiffies + 3280 (ha->fcoe_dev_init_timeout * HZ); 3281 break; 3282 case QLA8XXX_DEV_NEED_QUIESCENT: 3283 qla82xx_need_qsnt_handler(vha); 3284 /* Reset timeout value after quiescence handler */ 3285 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3286 * HZ); 3287 break; 3288 case QLA8XXX_DEV_QUIESCENT: 3289 /* Owner will exit and other will wait for the state 3290 * to get changed 3291 */ 3292 if (ha->flags.quiesce_owner) 3293 goto rel_lock; 3294 3295 qla82xx_idc_unlock(ha); 3296 msleep(1000); 3297 qla82xx_idc_lock(ha); 3298 3299 /* Reset timeout value after quiescence handler */ 3300 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3301 * HZ); 3302 break; 3303 case QLA8XXX_DEV_FAILED: 3304 qla8xxx_dev_failed_handler(vha); 3305 rval = QLA_FUNCTION_FAILED; 3306 goto exit; 3307 default: 3308 qla82xx_idc_unlock(ha); 3309 msleep(1000); 3310 qla82xx_idc_lock(ha); 3311 } 3312 loopcount++; 3313 } 3314 rel_lock: 3315 qla82xx_idc_unlock(ha); 3316 exit: 3317 return rval; 3318 } 3319 3320 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3321 { 3322 uint32_t temp, temp_state, temp_val; 3323 struct qla_hw_data *ha = vha->hw; 3324 3325 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3326 temp_state = qla82xx_get_temp_state(temp); 3327 temp_val = qla82xx_get_temp_val(temp); 3328 3329 if (temp_state == QLA82XX_TEMP_PANIC) { 3330 ql_log(ql_log_warn, vha, 0x600e, 3331 "Device temperature %d degrees C exceeds " 3332 " maximum allowed. Hardware has been shut down.\n", 3333 temp_val); 3334 return 1; 3335 } else if (temp_state == QLA82XX_TEMP_WARN) { 3336 ql_log(ql_log_warn, vha, 0x600f, 3337 "Device temperature %d degrees C exceeds " 3338 "operating range. Immediate action needed.\n", 3339 temp_val); 3340 } 3341 return 0; 3342 } 3343 3344 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3345 { 3346 uint32_t temp; 3347 3348 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3349 return qla82xx_get_temp_val(temp); 3350 } 3351 3352 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3353 { 3354 struct qla_hw_data *ha = vha->hw; 3355 3356 if (ha->flags.mbox_busy) { 3357 ha->flags.mbox_int = 1; 3358 ha->flags.mbox_busy = 0; 3359 ql_log(ql_log_warn, vha, 0x6010, 3360 "Doing premature completion of mbx command.\n"); 3361 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3362 complete(&ha->mbx_intr_comp); 3363 } 3364 } 3365 3366 void qla82xx_watchdog(scsi_qla_host_t *vha) 3367 { 3368 uint32_t dev_state, halt_status; 3369 struct qla_hw_data *ha = vha->hw; 3370 3371 /* don't poll if reset is going on */ 3372 if (!ha->flags.nic_core_reset_hdlr_active) { 3373 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3374 if (qla82xx_check_temp(vha)) { 3375 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3376 ha->flags.isp82xx_fw_hung = 1; 3377 qla82xx_clear_pending_mbx(vha); 3378 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3379 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3380 ql_log(ql_log_warn, vha, 0x6001, 3381 "Adapter reset needed.\n"); 3382 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3383 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3384 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3385 ql_log(ql_log_warn, vha, 0x6002, 3386 "Quiescent needed.\n"); 3387 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3388 } else if (dev_state == QLA8XXX_DEV_FAILED && 3389 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3390 vha->flags.online == 1) { 3391 ql_log(ql_log_warn, vha, 0xb055, 3392 "Adapter state is failed. Offlining.\n"); 3393 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3394 ha->flags.isp82xx_fw_hung = 1; 3395 qla82xx_clear_pending_mbx(vha); 3396 } else { 3397 if (qla82xx_check_fw_alive(vha)) { 3398 ql_dbg(ql_dbg_timer, vha, 0x6011, 3399 "disabling pause transmit on port 0 & 1.\n"); 3400 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3401 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3402 halt_status = qla82xx_rd_32(ha, 3403 QLA82XX_PEG_HALT_STATUS1); 3404 ql_log(ql_log_info, vha, 0x6005, 3405 "dumping hw/fw registers:.\n " 3406 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3407 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3408 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3409 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3410 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3411 qla82xx_rd_32(ha, 3412 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3413 qla82xx_rd_32(ha, 3414 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3415 qla82xx_rd_32(ha, 3416 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3417 qla82xx_rd_32(ha, 3418 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3419 qla82xx_rd_32(ha, 3420 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3421 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3422 ql_log(ql_log_warn, vha, 0xb052, 3423 "Firmware aborted with " 3424 "error code 0x00006700. Device is " 3425 "being reset.\n"); 3426 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3427 set_bit(ISP_UNRECOVERABLE, 3428 &vha->dpc_flags); 3429 } else { 3430 ql_log(ql_log_info, vha, 0x6006, 3431 "Detect abort needed.\n"); 3432 set_bit(ISP_ABORT_NEEDED, 3433 &vha->dpc_flags); 3434 } 3435 ha->flags.isp82xx_fw_hung = 1; 3436 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3437 qla82xx_clear_pending_mbx(vha); 3438 } 3439 } 3440 } 3441 } 3442 3443 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3444 { 3445 int rval = -1; 3446 struct qla_hw_data *ha = vha->hw; 3447 3448 if (IS_QLA82XX(ha)) 3449 rval = qla82xx_device_state_handler(vha); 3450 else if (IS_QLA8044(ha)) { 3451 qla8044_idc_lock(ha); 3452 /* Decide the reset ownership */ 3453 qla83xx_reset_ownership(vha); 3454 qla8044_idc_unlock(ha); 3455 rval = qla8044_device_state_handler(vha); 3456 } 3457 return rval; 3458 } 3459 3460 void 3461 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3462 { 3463 struct qla_hw_data *ha = vha->hw; 3464 uint32_t dev_state = 0; 3465 3466 if (IS_QLA82XX(ha)) 3467 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3468 else if (IS_QLA8044(ha)) 3469 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3470 3471 if (dev_state == QLA8XXX_DEV_READY) { 3472 ql_log(ql_log_info, vha, 0xb02f, 3473 "HW State: NEED RESET\n"); 3474 if (IS_QLA82XX(ha)) { 3475 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3476 QLA8XXX_DEV_NEED_RESET); 3477 ha->flags.nic_core_reset_owner = 1; 3478 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3479 "reset_owner is 0x%x\n", ha->portnum); 3480 } else if (IS_QLA8044(ha)) 3481 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3482 QLA8XXX_DEV_NEED_RESET); 3483 } else 3484 ql_log(ql_log_info, vha, 0xb031, 3485 "Device state is 0x%x = %s.\n", 3486 dev_state, 3487 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3488 } 3489 3490 /* 3491 * qla82xx_abort_isp 3492 * Resets ISP and aborts all outstanding commands. 3493 * 3494 * Input: 3495 * ha = adapter block pointer. 3496 * 3497 * Returns: 3498 * 0 = success 3499 */ 3500 int 3501 qla82xx_abort_isp(scsi_qla_host_t *vha) 3502 { 3503 int rval = -1; 3504 struct qla_hw_data *ha = vha->hw; 3505 3506 if (vha->device_flags & DFLG_DEV_FAILED) { 3507 ql_log(ql_log_warn, vha, 0x8024, 3508 "Device in failed state, exiting.\n"); 3509 return QLA_SUCCESS; 3510 } 3511 ha->flags.nic_core_reset_hdlr_active = 1; 3512 3513 qla82xx_idc_lock(ha); 3514 qla82xx_set_reset_owner(vha); 3515 qla82xx_idc_unlock(ha); 3516 3517 if (IS_QLA82XX(ha)) 3518 rval = qla82xx_device_state_handler(vha); 3519 else if (IS_QLA8044(ha)) { 3520 qla8044_idc_lock(ha); 3521 /* Decide the reset ownership */ 3522 qla83xx_reset_ownership(vha); 3523 qla8044_idc_unlock(ha); 3524 rval = qla8044_device_state_handler(vha); 3525 } 3526 3527 qla82xx_idc_lock(ha); 3528 qla82xx_clear_rst_ready(ha); 3529 qla82xx_idc_unlock(ha); 3530 3531 if (rval == QLA_SUCCESS) { 3532 ha->flags.isp82xx_fw_hung = 0; 3533 ha->flags.nic_core_reset_hdlr_active = 0; 3534 qla82xx_restart_isp(vha); 3535 } 3536 3537 if (rval) { 3538 vha->flags.online = 1; 3539 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3540 if (ha->isp_abort_cnt == 0) { 3541 ql_log(ql_log_warn, vha, 0x8027, 3542 "ISP error recover failed - board " 3543 "disabled.\n"); 3544 /* 3545 * The next call disables the board 3546 * completely. 3547 */ 3548 ha->isp_ops->reset_adapter(vha); 3549 vha->flags.online = 0; 3550 clear_bit(ISP_ABORT_RETRY, 3551 &vha->dpc_flags); 3552 rval = QLA_SUCCESS; 3553 } else { /* schedule another ISP abort */ 3554 ha->isp_abort_cnt--; 3555 ql_log(ql_log_warn, vha, 0x8036, 3556 "ISP abort - retry remaining %d.\n", 3557 ha->isp_abort_cnt); 3558 rval = QLA_FUNCTION_FAILED; 3559 } 3560 } else { 3561 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3562 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3563 "ISP error recovery - retrying (%d) more times.\n", 3564 ha->isp_abort_cnt); 3565 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3566 rval = QLA_FUNCTION_FAILED; 3567 } 3568 } 3569 return rval; 3570 } 3571 3572 /* 3573 * qla82xx_fcoe_ctx_reset 3574 * Perform a quick reset and aborts all outstanding commands. 3575 * This will only perform an FCoE context reset and avoids a full blown 3576 * chip reset. 3577 * 3578 * Input: 3579 * ha = adapter block pointer. 3580 * is_reset_path = flag for identifying the reset path. 3581 * 3582 * Returns: 3583 * 0 = success 3584 */ 3585 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3586 { 3587 int rval = QLA_FUNCTION_FAILED; 3588 3589 if (vha->flags.online) { 3590 /* Abort all outstanding commands, so as to be requeued later */ 3591 qla2x00_abort_isp_cleanup(vha); 3592 } 3593 3594 /* Stop currently executing firmware. 3595 * This will destroy existing FCoE context at the F/W end. 3596 */ 3597 qla2x00_try_to_stop_firmware(vha); 3598 3599 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3600 rval = qla82xx_restart_isp(vha); 3601 3602 return rval; 3603 } 3604 3605 /* 3606 * qla2x00_wait_for_fcoe_ctx_reset 3607 * Wait till the FCoE context is reset. 3608 * 3609 * Note: 3610 * Does context switching here. 3611 * Release SPIN_LOCK (if any) before calling this routine. 3612 * 3613 * Return: 3614 * Success (fcoe_ctx reset is done) : 0 3615 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3616 */ 3617 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3618 { 3619 int status = QLA_FUNCTION_FAILED; 3620 unsigned long wait_reset; 3621 3622 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3623 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3624 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3625 && time_before(jiffies, wait_reset)) { 3626 3627 set_current_state(TASK_UNINTERRUPTIBLE); 3628 schedule_timeout(HZ); 3629 3630 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3631 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3632 status = QLA_SUCCESS; 3633 break; 3634 } 3635 } 3636 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3637 "%s: status=%d.\n", __func__, status); 3638 3639 return status; 3640 } 3641 3642 void 3643 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3644 { 3645 int i, fw_state = 0; 3646 unsigned long flags; 3647 struct qla_hw_data *ha = vha->hw; 3648 3649 /* Check if 82XX firmware is alive or not 3650 * We may have arrived here from NEED_RESET 3651 * detection only 3652 */ 3653 if (!ha->flags.isp82xx_fw_hung) { 3654 for (i = 0; i < 2; i++) { 3655 msleep(1000); 3656 if (IS_QLA82XX(ha)) 3657 fw_state = qla82xx_check_fw_alive(vha); 3658 else if (IS_QLA8044(ha)) 3659 fw_state = qla8044_check_fw_alive(vha); 3660 if (fw_state) { 3661 ha->flags.isp82xx_fw_hung = 1; 3662 qla82xx_clear_pending_mbx(vha); 3663 break; 3664 } 3665 } 3666 } 3667 ql_dbg(ql_dbg_init, vha, 0x00b0, 3668 "Entered %s fw_hung=%d.\n", 3669 __func__, ha->flags.isp82xx_fw_hung); 3670 3671 /* Abort all commands gracefully if fw NOT hung */ 3672 if (!ha->flags.isp82xx_fw_hung) { 3673 int cnt, que; 3674 srb_t *sp; 3675 struct req_que *req; 3676 3677 spin_lock_irqsave(&ha->hardware_lock, flags); 3678 for (que = 0; que < ha->max_req_queues; que++) { 3679 req = ha->req_q_map[que]; 3680 if (!req) 3681 continue; 3682 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3683 sp = req->outstanding_cmds[cnt]; 3684 if (sp) { 3685 if (!sp->u.scmd.ctx || 3686 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3687 spin_unlock_irqrestore( 3688 &ha->hardware_lock, flags); 3689 if (ha->isp_ops->abort_command(sp)) { 3690 ql_log(ql_log_info, vha, 3691 0x00b1, 3692 "mbx abort failed.\n"); 3693 } else { 3694 ql_log(ql_log_info, vha, 3695 0x00b2, 3696 "mbx abort success.\n"); 3697 } 3698 spin_lock_irqsave(&ha->hardware_lock, flags); 3699 } 3700 } 3701 } 3702 } 3703 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3704 3705 /* Wait for pending cmds (physical and virtual) to complete */ 3706 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3707 WAIT_HOST) == QLA_SUCCESS) { 3708 ql_dbg(ql_dbg_init, vha, 0x00b3, 3709 "Done wait for " 3710 "pending commands.\n"); 3711 } 3712 } 3713 } 3714 3715 /* Minidump related functions */ 3716 static int 3717 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3718 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3719 { 3720 struct qla_hw_data *ha = vha->hw; 3721 struct qla82xx_md_entry_crb *crb_entry; 3722 uint32_t read_value, opcode, poll_time; 3723 uint32_t addr, index, crb_addr; 3724 unsigned long wtime; 3725 struct qla82xx_md_template_hdr *tmplt_hdr; 3726 uint32_t rval = QLA_SUCCESS; 3727 int i; 3728 3729 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3730 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3731 crb_addr = crb_entry->addr; 3732 3733 for (i = 0; i < crb_entry->op_count; i++) { 3734 opcode = crb_entry->crb_ctrl.opcode; 3735 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3736 qla82xx_md_rw_32(ha, crb_addr, 3737 crb_entry->value_1, 1); 3738 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3739 } 3740 3741 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3742 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3743 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3744 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3745 } 3746 3747 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3748 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3749 read_value &= crb_entry->value_2; 3750 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3751 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3752 read_value |= crb_entry->value_3; 3753 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3754 } 3755 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3756 } 3757 3758 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3759 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3760 read_value |= crb_entry->value_3; 3761 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3762 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3763 } 3764 3765 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3766 poll_time = crb_entry->crb_strd.poll_timeout; 3767 wtime = jiffies + poll_time; 3768 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3769 3770 do { 3771 if ((read_value & crb_entry->value_2) 3772 == crb_entry->value_1) 3773 break; 3774 else if (time_after_eq(jiffies, wtime)) { 3775 /* capturing dump failed */ 3776 rval = QLA_FUNCTION_FAILED; 3777 break; 3778 } else 3779 read_value = qla82xx_md_rw_32(ha, 3780 crb_addr, 0, 0); 3781 } while (1); 3782 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3783 } 3784 3785 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3786 if (crb_entry->crb_strd.state_index_a) { 3787 index = crb_entry->crb_strd.state_index_a; 3788 addr = tmplt_hdr->saved_state_array[index]; 3789 } else 3790 addr = crb_addr; 3791 3792 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3793 index = crb_entry->crb_ctrl.state_index_v; 3794 tmplt_hdr->saved_state_array[index] = read_value; 3795 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3796 } 3797 3798 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3799 if (crb_entry->crb_strd.state_index_a) { 3800 index = crb_entry->crb_strd.state_index_a; 3801 addr = tmplt_hdr->saved_state_array[index]; 3802 } else 3803 addr = crb_addr; 3804 3805 if (crb_entry->crb_ctrl.state_index_v) { 3806 index = crb_entry->crb_ctrl.state_index_v; 3807 read_value = 3808 tmplt_hdr->saved_state_array[index]; 3809 } else 3810 read_value = crb_entry->value_1; 3811 3812 qla82xx_md_rw_32(ha, addr, read_value, 1); 3813 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3814 } 3815 3816 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3817 index = crb_entry->crb_ctrl.state_index_v; 3818 read_value = tmplt_hdr->saved_state_array[index]; 3819 read_value <<= crb_entry->crb_ctrl.shl; 3820 read_value >>= crb_entry->crb_ctrl.shr; 3821 if (crb_entry->value_2) 3822 read_value &= crb_entry->value_2; 3823 read_value |= crb_entry->value_3; 3824 read_value += crb_entry->value_1; 3825 tmplt_hdr->saved_state_array[index] = read_value; 3826 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3827 } 3828 crb_addr += crb_entry->crb_strd.addr_stride; 3829 } 3830 return rval; 3831 } 3832 3833 static void 3834 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3835 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3836 { 3837 struct qla_hw_data *ha = vha->hw; 3838 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3839 struct qla82xx_md_entry_rdocm *ocm_hdr; 3840 uint32_t *data_ptr = *d_ptr; 3841 3842 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3843 r_addr = ocm_hdr->read_addr; 3844 r_stride = ocm_hdr->read_addr_stride; 3845 loop_cnt = ocm_hdr->op_count; 3846 3847 for (i = 0; i < loop_cnt; i++) { 3848 r_value = RD_REG_DWORD((void __iomem *) 3849 (r_addr + ha->nx_pcibase)); 3850 *data_ptr++ = cpu_to_le32(r_value); 3851 r_addr += r_stride; 3852 } 3853 *d_ptr = data_ptr; 3854 } 3855 3856 static void 3857 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3858 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3859 { 3860 struct qla_hw_data *ha = vha->hw; 3861 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3862 struct qla82xx_md_entry_mux *mux_hdr; 3863 uint32_t *data_ptr = *d_ptr; 3864 3865 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3866 r_addr = mux_hdr->read_addr; 3867 s_addr = mux_hdr->select_addr; 3868 s_stride = mux_hdr->select_value_stride; 3869 s_value = mux_hdr->select_value; 3870 loop_cnt = mux_hdr->op_count; 3871 3872 for (i = 0; i < loop_cnt; i++) { 3873 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3874 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3875 *data_ptr++ = cpu_to_le32(s_value); 3876 *data_ptr++ = cpu_to_le32(r_value); 3877 s_value += s_stride; 3878 } 3879 *d_ptr = data_ptr; 3880 } 3881 3882 static void 3883 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3884 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3885 { 3886 struct qla_hw_data *ha = vha->hw; 3887 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3888 struct qla82xx_md_entry_crb *crb_hdr; 3889 uint32_t *data_ptr = *d_ptr; 3890 3891 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3892 r_addr = crb_hdr->addr; 3893 r_stride = crb_hdr->crb_strd.addr_stride; 3894 loop_cnt = crb_hdr->op_count; 3895 3896 for (i = 0; i < loop_cnt; i++) { 3897 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3898 *data_ptr++ = cpu_to_le32(r_addr); 3899 *data_ptr++ = cpu_to_le32(r_value); 3900 r_addr += r_stride; 3901 } 3902 *d_ptr = data_ptr; 3903 } 3904 3905 static int 3906 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3907 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3908 { 3909 struct qla_hw_data *ha = vha->hw; 3910 uint32_t addr, r_addr, c_addr, t_r_addr; 3911 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3912 unsigned long p_wait, w_time, p_mask; 3913 uint32_t c_value_w, c_value_r; 3914 struct qla82xx_md_entry_cache *cache_hdr; 3915 int rval = QLA_FUNCTION_FAILED; 3916 uint32_t *data_ptr = *d_ptr; 3917 3918 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3919 loop_count = cache_hdr->op_count; 3920 r_addr = cache_hdr->read_addr; 3921 c_addr = cache_hdr->control_addr; 3922 c_value_w = cache_hdr->cache_ctrl.write_value; 3923 3924 t_r_addr = cache_hdr->tag_reg_addr; 3925 t_value = cache_hdr->addr_ctrl.init_tag_value; 3926 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3927 p_wait = cache_hdr->cache_ctrl.poll_wait; 3928 p_mask = cache_hdr->cache_ctrl.poll_mask; 3929 3930 for (i = 0; i < loop_count; i++) { 3931 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3932 if (c_value_w) 3933 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3934 3935 if (p_mask) { 3936 w_time = jiffies + p_wait; 3937 do { 3938 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3939 if ((c_value_r & p_mask) == 0) 3940 break; 3941 else if (time_after_eq(jiffies, w_time)) { 3942 /* capturing dump failed */ 3943 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3944 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3945 "w_time: 0x%lx\n", 3946 c_value_r, p_mask, w_time); 3947 return rval; 3948 } 3949 } while (1); 3950 } 3951 3952 addr = r_addr; 3953 for (k = 0; k < r_cnt; k++) { 3954 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3955 *data_ptr++ = cpu_to_le32(r_value); 3956 addr += cache_hdr->read_ctrl.read_addr_stride; 3957 } 3958 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3959 } 3960 *d_ptr = data_ptr; 3961 return QLA_SUCCESS; 3962 } 3963 3964 static void 3965 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3966 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3967 { 3968 struct qla_hw_data *ha = vha->hw; 3969 uint32_t addr, r_addr, c_addr, t_r_addr; 3970 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3971 uint32_t c_value_w; 3972 struct qla82xx_md_entry_cache *cache_hdr; 3973 uint32_t *data_ptr = *d_ptr; 3974 3975 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3976 loop_count = cache_hdr->op_count; 3977 r_addr = cache_hdr->read_addr; 3978 c_addr = cache_hdr->control_addr; 3979 c_value_w = cache_hdr->cache_ctrl.write_value; 3980 3981 t_r_addr = cache_hdr->tag_reg_addr; 3982 t_value = cache_hdr->addr_ctrl.init_tag_value; 3983 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3984 3985 for (i = 0; i < loop_count; i++) { 3986 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3987 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3988 addr = r_addr; 3989 for (k = 0; k < r_cnt; k++) { 3990 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3991 *data_ptr++ = cpu_to_le32(r_value); 3992 addr += cache_hdr->read_ctrl.read_addr_stride; 3993 } 3994 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3995 } 3996 *d_ptr = data_ptr; 3997 } 3998 3999 static void 4000 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 4001 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4002 { 4003 struct qla_hw_data *ha = vha->hw; 4004 uint32_t s_addr, r_addr; 4005 uint32_t r_stride, r_value, r_cnt, qid = 0; 4006 uint32_t i, k, loop_cnt; 4007 struct qla82xx_md_entry_queue *q_hdr; 4008 uint32_t *data_ptr = *d_ptr; 4009 4010 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 4011 s_addr = q_hdr->select_addr; 4012 r_cnt = q_hdr->rd_strd.read_addr_cnt; 4013 r_stride = q_hdr->rd_strd.read_addr_stride; 4014 loop_cnt = q_hdr->op_count; 4015 4016 for (i = 0; i < loop_cnt; i++) { 4017 qla82xx_md_rw_32(ha, s_addr, qid, 1); 4018 r_addr = q_hdr->read_addr; 4019 for (k = 0; k < r_cnt; k++) { 4020 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4021 *data_ptr++ = cpu_to_le32(r_value); 4022 r_addr += r_stride; 4023 } 4024 qid += q_hdr->q_strd.queue_id_stride; 4025 } 4026 *d_ptr = data_ptr; 4027 } 4028 4029 static void 4030 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 4031 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4032 { 4033 struct qla_hw_data *ha = vha->hw; 4034 uint32_t r_addr, r_value; 4035 uint32_t i, loop_cnt; 4036 struct qla82xx_md_entry_rdrom *rom_hdr; 4037 uint32_t *data_ptr = *d_ptr; 4038 4039 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4040 r_addr = rom_hdr->read_addr; 4041 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4042 4043 for (i = 0; i < loop_cnt; i++) { 4044 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4045 (r_addr & 0xFFFF0000), 1); 4046 r_value = qla82xx_md_rw_32(ha, 4047 MD_DIRECT_ROM_READ_BASE + 4048 (r_addr & 0x0000FFFF), 0, 0); 4049 *data_ptr++ = cpu_to_le32(r_value); 4050 r_addr += sizeof(uint32_t); 4051 } 4052 *d_ptr = data_ptr; 4053 } 4054 4055 static int 4056 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4057 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4058 { 4059 struct qla_hw_data *ha = vha->hw; 4060 uint32_t r_addr, r_value, r_data; 4061 uint32_t i, j, loop_cnt; 4062 struct qla82xx_md_entry_rdmem *m_hdr; 4063 unsigned long flags; 4064 int rval = QLA_FUNCTION_FAILED; 4065 uint32_t *data_ptr = *d_ptr; 4066 4067 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4068 r_addr = m_hdr->read_addr; 4069 loop_cnt = m_hdr->read_data_size/16; 4070 4071 if (r_addr & 0xf) { 4072 ql_log(ql_log_warn, vha, 0xb033, 4073 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4074 return rval; 4075 } 4076 4077 if (m_hdr->read_data_size % 16) { 4078 ql_log(ql_log_warn, vha, 0xb034, 4079 "Read data[0x%x] not multiple of 16 bytes\n", 4080 m_hdr->read_data_size); 4081 return rval; 4082 } 4083 4084 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4085 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4086 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4087 4088 write_lock_irqsave(&ha->hw_lock, flags); 4089 for (i = 0; i < loop_cnt; i++) { 4090 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4091 r_value = 0; 4092 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4093 r_value = MIU_TA_CTL_ENABLE; 4094 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4095 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4096 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4097 4098 for (j = 0; j < MAX_CTL_CHECK; j++) { 4099 r_value = qla82xx_md_rw_32(ha, 4100 MD_MIU_TEST_AGT_CTRL, 0, 0); 4101 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4102 break; 4103 } 4104 4105 if (j >= MAX_CTL_CHECK) { 4106 printk_ratelimited(KERN_ERR 4107 "failed to read through agent\n"); 4108 write_unlock_irqrestore(&ha->hw_lock, flags); 4109 return rval; 4110 } 4111 4112 for (j = 0; j < 4; j++) { 4113 r_data = qla82xx_md_rw_32(ha, 4114 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4115 *data_ptr++ = cpu_to_le32(r_data); 4116 } 4117 r_addr += 16; 4118 } 4119 write_unlock_irqrestore(&ha->hw_lock, flags); 4120 *d_ptr = data_ptr; 4121 return QLA_SUCCESS; 4122 } 4123 4124 int 4125 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4126 { 4127 struct qla_hw_data *ha = vha->hw; 4128 uint64_t chksum = 0; 4129 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4130 int count = ha->md_template_size/sizeof(uint32_t); 4131 4132 while (count-- > 0) 4133 chksum += *d_ptr++; 4134 while (chksum >> 32) 4135 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4136 return ~chksum; 4137 } 4138 4139 static void 4140 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4141 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4142 { 4143 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4144 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4145 "Skipping entry[%d]: " 4146 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4147 index, entry_hdr->entry_type, 4148 entry_hdr->d_ctrl.entry_capture_mask); 4149 } 4150 4151 int 4152 qla82xx_md_collect(scsi_qla_host_t *vha) 4153 { 4154 struct qla_hw_data *ha = vha->hw; 4155 int no_entry_hdr = 0; 4156 qla82xx_md_entry_hdr_t *entry_hdr; 4157 struct qla82xx_md_template_hdr *tmplt_hdr; 4158 uint32_t *data_ptr; 4159 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4160 int i = 0, rval = QLA_FUNCTION_FAILED; 4161 4162 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4163 data_ptr = (uint32_t *)ha->md_dump; 4164 4165 if (ha->fw_dumped) { 4166 ql_log(ql_log_warn, vha, 0xb037, 4167 "Firmware has been previously dumped (%p) " 4168 "-- ignoring request.\n", ha->fw_dump); 4169 goto md_failed; 4170 } 4171 4172 ha->fw_dumped = 0; 4173 4174 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4175 ql_log(ql_log_warn, vha, 0xb038, 4176 "Memory not allocated for minidump capture\n"); 4177 goto md_failed; 4178 } 4179 4180 if (ha->flags.isp82xx_no_md_cap) { 4181 ql_log(ql_log_warn, vha, 0xb054, 4182 "Forced reset from application, " 4183 "ignore minidump capture\n"); 4184 ha->flags.isp82xx_no_md_cap = 0; 4185 goto md_failed; 4186 } 4187 4188 if (qla82xx_validate_template_chksum(vha)) { 4189 ql_log(ql_log_info, vha, 0xb039, 4190 "Template checksum validation error\n"); 4191 goto md_failed; 4192 } 4193 4194 no_entry_hdr = tmplt_hdr->num_of_entries; 4195 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4196 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4197 4198 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4199 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4200 4201 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4202 4203 /* Validate whether required debug level is set */ 4204 if ((f_capture_mask & 0x3) != 0x3) { 4205 ql_log(ql_log_warn, vha, 0xb03c, 4206 "Minimum required capture mask[0x%x] level not set\n", 4207 f_capture_mask); 4208 goto md_failed; 4209 } 4210 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4211 4212 tmplt_hdr->driver_info[0] = vha->host_no; 4213 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4214 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4215 QLA_DRIVER_BETA_VER; 4216 4217 total_data_size = ha->md_dump_size; 4218 4219 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4220 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4221 4222 /* Check whether template obtained is valid */ 4223 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4224 ql_log(ql_log_warn, vha, 0xb04e, 4225 "Bad template header entry type: 0x%x obtained\n", 4226 tmplt_hdr->entry_type); 4227 goto md_failed; 4228 } 4229 4230 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4231 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4232 4233 /* Walk through the entry headers */ 4234 for (i = 0; i < no_entry_hdr; i++) { 4235 4236 if (data_collected > total_data_size) { 4237 ql_log(ql_log_warn, vha, 0xb03e, 4238 "More MiniDump data collected: [0x%x]\n", 4239 data_collected); 4240 goto md_failed; 4241 } 4242 4243 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4244 ql2xmdcapmask)) { 4245 entry_hdr->d_ctrl.driver_flags |= 4246 QLA82XX_DBG_SKIPPED_FLAG; 4247 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4248 "Skipping entry[%d]: " 4249 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4250 i, entry_hdr->entry_type, 4251 entry_hdr->d_ctrl.entry_capture_mask); 4252 goto skip_nxt_entry; 4253 } 4254 4255 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4256 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4257 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4258 __func__, i, data_ptr, entry_hdr, 4259 entry_hdr->entry_type, 4260 entry_hdr->d_ctrl.entry_capture_mask); 4261 4262 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4263 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4264 data_collected, (ha->md_dump_size - data_collected)); 4265 4266 /* Decode the entry type and take 4267 * required action to capture debug data */ 4268 switch (entry_hdr->entry_type) { 4269 case QLA82XX_RDEND: 4270 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4271 break; 4272 case QLA82XX_CNTRL: 4273 rval = qla82xx_minidump_process_control(vha, 4274 entry_hdr, &data_ptr); 4275 if (rval != QLA_SUCCESS) { 4276 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4277 goto md_failed; 4278 } 4279 break; 4280 case QLA82XX_RDCRB: 4281 qla82xx_minidump_process_rdcrb(vha, 4282 entry_hdr, &data_ptr); 4283 break; 4284 case QLA82XX_RDMEM: 4285 rval = qla82xx_minidump_process_rdmem(vha, 4286 entry_hdr, &data_ptr); 4287 if (rval != QLA_SUCCESS) { 4288 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4289 goto md_failed; 4290 } 4291 break; 4292 case QLA82XX_BOARD: 4293 case QLA82XX_RDROM: 4294 qla82xx_minidump_process_rdrom(vha, 4295 entry_hdr, &data_ptr); 4296 break; 4297 case QLA82XX_L2DTG: 4298 case QLA82XX_L2ITG: 4299 case QLA82XX_L2DAT: 4300 case QLA82XX_L2INS: 4301 rval = qla82xx_minidump_process_l2tag(vha, 4302 entry_hdr, &data_ptr); 4303 if (rval != QLA_SUCCESS) { 4304 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4305 goto md_failed; 4306 } 4307 break; 4308 case QLA82XX_L1DAT: 4309 case QLA82XX_L1INS: 4310 qla82xx_minidump_process_l1cache(vha, 4311 entry_hdr, &data_ptr); 4312 break; 4313 case QLA82XX_RDOCM: 4314 qla82xx_minidump_process_rdocm(vha, 4315 entry_hdr, &data_ptr); 4316 break; 4317 case QLA82XX_RDMUX: 4318 qla82xx_minidump_process_rdmux(vha, 4319 entry_hdr, &data_ptr); 4320 break; 4321 case QLA82XX_QUEUE: 4322 qla82xx_minidump_process_queue(vha, 4323 entry_hdr, &data_ptr); 4324 break; 4325 case QLA82XX_RDNOP: 4326 default: 4327 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4328 break; 4329 } 4330 4331 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4332 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4333 4334 data_collected = (uint8_t *)data_ptr - 4335 (uint8_t *)ha->md_dump; 4336 skip_nxt_entry: 4337 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4338 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4339 } 4340 4341 if (data_collected != total_data_size) { 4342 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4343 "MiniDump data mismatch: Data collected: [0x%x]," 4344 "total_data_size:[0x%x]\n", 4345 data_collected, total_data_size); 4346 goto md_failed; 4347 } 4348 4349 ql_log(ql_log_info, vha, 0xb044, 4350 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4351 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4352 ha->fw_dumped = 1; 4353 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4354 4355 md_failed: 4356 return rval; 4357 } 4358 4359 int 4360 qla82xx_md_alloc(scsi_qla_host_t *vha) 4361 { 4362 struct qla_hw_data *ha = vha->hw; 4363 int i, k; 4364 struct qla82xx_md_template_hdr *tmplt_hdr; 4365 4366 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4367 4368 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4369 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4370 ql_log(ql_log_info, vha, 0xb045, 4371 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4372 ql2xmdcapmask); 4373 } 4374 4375 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4376 if (i & ql2xmdcapmask) 4377 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4378 } 4379 4380 if (ha->md_dump) { 4381 ql_log(ql_log_warn, vha, 0xb046, 4382 "Firmware dump previously allocated.\n"); 4383 return 1; 4384 } 4385 4386 ha->md_dump = vmalloc(ha->md_dump_size); 4387 if (ha->md_dump == NULL) { 4388 ql_log(ql_log_warn, vha, 0xb047, 4389 "Unable to allocate memory for Minidump size " 4390 "(0x%x).\n", ha->md_dump_size); 4391 return 1; 4392 } 4393 return 0; 4394 } 4395 4396 void 4397 qla82xx_md_free(scsi_qla_host_t *vha) 4398 { 4399 struct qla_hw_data *ha = vha->hw; 4400 4401 /* Release the template header allocated */ 4402 if (ha->md_tmplt_hdr) { 4403 ql_log(ql_log_info, vha, 0xb048, 4404 "Free MiniDump template: %p, size (%d KB)\n", 4405 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4406 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4407 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4408 ha->md_tmplt_hdr = NULL; 4409 } 4410 4411 /* Release the template data buffer allocated */ 4412 if (ha->md_dump) { 4413 ql_log(ql_log_info, vha, 0xb049, 4414 "Free MiniDump memory: %p, size (%d KB)\n", 4415 ha->md_dump, ha->md_dump_size / 1024); 4416 vfree(ha->md_dump); 4417 ha->md_dump_size = 0; 4418 ha->md_dump = NULL; 4419 } 4420 } 4421 4422 void 4423 qla82xx_md_prep(scsi_qla_host_t *vha) 4424 { 4425 struct qla_hw_data *ha = vha->hw; 4426 int rval; 4427 4428 /* Get Minidump template size */ 4429 rval = qla82xx_md_get_template_size(vha); 4430 if (rval == QLA_SUCCESS) { 4431 ql_log(ql_log_info, vha, 0xb04a, 4432 "MiniDump Template size obtained (%d KB)\n", 4433 ha->md_template_size / 1024); 4434 4435 /* Get Minidump template */ 4436 if (IS_QLA8044(ha)) 4437 rval = qla8044_md_get_template(vha); 4438 else 4439 rval = qla82xx_md_get_template(vha); 4440 4441 if (rval == QLA_SUCCESS) { 4442 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4443 "MiniDump Template obtained\n"); 4444 4445 /* Allocate memory for minidump */ 4446 rval = qla82xx_md_alloc(vha); 4447 if (rval == QLA_SUCCESS) 4448 ql_log(ql_log_info, vha, 0xb04c, 4449 "MiniDump memory allocated (%d KB)\n", 4450 ha->md_dump_size / 1024); 4451 else { 4452 ql_log(ql_log_info, vha, 0xb04d, 4453 "Free MiniDump template: %p, size: (%d KB)\n", 4454 ha->md_tmplt_hdr, 4455 ha->md_template_size / 1024); 4456 dma_free_coherent(&ha->pdev->dev, 4457 ha->md_template_size, 4458 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4459 ha->md_tmplt_hdr = NULL; 4460 } 4461 4462 } 4463 } 4464 } 4465 4466 int 4467 qla82xx_beacon_on(struct scsi_qla_host *vha) 4468 { 4469 4470 int rval; 4471 struct qla_hw_data *ha = vha->hw; 4472 qla82xx_idc_lock(ha); 4473 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4474 4475 if (rval) { 4476 ql_log(ql_log_warn, vha, 0xb050, 4477 "mbx set led config failed in %s\n", __func__); 4478 goto exit; 4479 } 4480 ha->beacon_blink_led = 1; 4481 exit: 4482 qla82xx_idc_unlock(ha); 4483 return rval; 4484 } 4485 4486 int 4487 qla82xx_beacon_off(struct scsi_qla_host *vha) 4488 { 4489 4490 int rval; 4491 struct qla_hw_data *ha = vha->hw; 4492 qla82xx_idc_lock(ha); 4493 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4494 4495 if (rval) { 4496 ql_log(ql_log_warn, vha, 0xb051, 4497 "mbx set led config failed in %s\n", __func__); 4498 goto exit; 4499 } 4500 ha->beacon_blink_led = 0; 4501 exit: 4502 qla82xx_idc_unlock(ha); 4503 return rval; 4504 } 4505 4506 void 4507 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4508 { 4509 struct qla_hw_data *ha = vha->hw; 4510 4511 if (!ha->allow_cna_fw_dump) 4512 return; 4513 4514 scsi_block_requests(vha->host); 4515 ha->flags.isp82xx_no_md_cap = 1; 4516 qla82xx_idc_lock(ha); 4517 qla82xx_set_reset_owner(vha); 4518 qla82xx_idc_unlock(ha); 4519 qla2x00_wait_for_chip_reset(vha); 4520 scsi_unblock_requests(vha->host); 4521 } 4522