1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include <linux/delay.h> 8 #include <linux/io-64-nonatomic-lo-hi.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 const int MD_MIU_TEST_AGT_RDDATA[] = { 46 0x410000A8, 0x410000AC, 47 0x410000B8, 0x410000BC 48 }; 49 50 static void qla82xx_crb_addr_transform_setup(void) 51 { 52 qla82xx_crb_addr_transform(XDMA); 53 qla82xx_crb_addr_transform(TIMR); 54 qla82xx_crb_addr_transform(SRE); 55 qla82xx_crb_addr_transform(SQN3); 56 qla82xx_crb_addr_transform(SQN2); 57 qla82xx_crb_addr_transform(SQN1); 58 qla82xx_crb_addr_transform(SQN0); 59 qla82xx_crb_addr_transform(SQS3); 60 qla82xx_crb_addr_transform(SQS2); 61 qla82xx_crb_addr_transform(SQS1); 62 qla82xx_crb_addr_transform(SQS0); 63 qla82xx_crb_addr_transform(RPMX7); 64 qla82xx_crb_addr_transform(RPMX6); 65 qla82xx_crb_addr_transform(RPMX5); 66 qla82xx_crb_addr_transform(RPMX4); 67 qla82xx_crb_addr_transform(RPMX3); 68 qla82xx_crb_addr_transform(RPMX2); 69 qla82xx_crb_addr_transform(RPMX1); 70 qla82xx_crb_addr_transform(RPMX0); 71 qla82xx_crb_addr_transform(ROMUSB); 72 qla82xx_crb_addr_transform(SN); 73 qla82xx_crb_addr_transform(QMN); 74 qla82xx_crb_addr_transform(QMS); 75 qla82xx_crb_addr_transform(PGNI); 76 qla82xx_crb_addr_transform(PGND); 77 qla82xx_crb_addr_transform(PGN3); 78 qla82xx_crb_addr_transform(PGN2); 79 qla82xx_crb_addr_transform(PGN1); 80 qla82xx_crb_addr_transform(PGN0); 81 qla82xx_crb_addr_transform(PGSI); 82 qla82xx_crb_addr_transform(PGSD); 83 qla82xx_crb_addr_transform(PGS3); 84 qla82xx_crb_addr_transform(PGS2); 85 qla82xx_crb_addr_transform(PGS1); 86 qla82xx_crb_addr_transform(PGS0); 87 qla82xx_crb_addr_transform(PS); 88 qla82xx_crb_addr_transform(PH); 89 qla82xx_crb_addr_transform(NIU); 90 qla82xx_crb_addr_transform(I2Q); 91 qla82xx_crb_addr_transform(EG); 92 qla82xx_crb_addr_transform(MN); 93 qla82xx_crb_addr_transform(MS); 94 qla82xx_crb_addr_transform(CAS2); 95 qla82xx_crb_addr_transform(CAS1); 96 qla82xx_crb_addr_transform(CAS0); 97 qla82xx_crb_addr_transform(CAM); 98 qla82xx_crb_addr_transform(C2C1); 99 qla82xx_crb_addr_transform(C2C0); 100 qla82xx_crb_addr_transform(SMB); 101 qla82xx_crb_addr_transform(OCM0); 102 /* 103 * Used only in P3 just define it for P2 also. 104 */ 105 qla82xx_crb_addr_transform(I2C0); 106 107 qla82xx_crb_table_initialized = 1; 108 } 109 110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 111 {{{0, 0, 0, 0} } }, 112 {{{1, 0x0100000, 0x0102000, 0x120000}, 113 {1, 0x0110000, 0x0120000, 0x130000}, 114 {1, 0x0120000, 0x0122000, 0x124000}, 115 {1, 0x0130000, 0x0132000, 0x126000}, 116 {1, 0x0140000, 0x0142000, 0x128000}, 117 {1, 0x0150000, 0x0152000, 0x12a000}, 118 {1, 0x0160000, 0x0170000, 0x110000}, 119 {1, 0x0170000, 0x0172000, 0x12e000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {1, 0x01e0000, 0x01e0800, 0x122000}, 127 {0, 0x0000000, 0x0000000, 0x000000} } } , 128 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 129 {{{0, 0, 0, 0} } }, 130 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 131 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 134 {{{1, 0x0800000, 0x0802000, 0x170000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 150 {{{1, 0x0900000, 0x0902000, 0x174000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 166 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 182 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 203 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 204 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 205 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 206 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 207 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 208 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{0, 0, 0, 0} } }, 211 {{{0, 0, 0, 0} } }, 212 {{{0, 0, 0, 0} } }, 213 {{{0, 0, 0, 0} } }, 214 {{{0, 0, 0, 0} } }, 215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 218 {{{0} } }, 219 {{{1, 0x2100000, 0x2102000, 0x120000}, 220 {1, 0x2110000, 0x2120000, 0x130000}, 221 {1, 0x2120000, 0x2122000, 0x124000}, 222 {1, 0x2130000, 0x2132000, 0x126000}, 223 {1, 0x2140000, 0x2142000, 0x128000}, 224 {1, 0x2150000, 0x2152000, 0x12a000}, 225 {1, 0x2160000, 0x2170000, 0x110000}, 226 {1, 0x2170000, 0x2172000, 0x12e000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000} } }, 235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 236 {{{0} } }, 237 {{{0} } }, 238 {{{0} } }, 239 {{{0} } }, 240 {{{0} } }, 241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 242 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 253 {{{0} } }, 254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 260 {{{0} } }, 261 {{{0} } }, 262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 265 }; 266 267 /* 268 * top 12 bits of crb internal address (hub, agent) 269 */ 270 static unsigned qla82xx_crb_hub_agt[64] = { 271 0, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 275 0, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 301 0, 302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 303 0, 304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 306 0, 307 0, 308 0, 309 0, 310 0, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 312 0, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 328 0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 332 0, 333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 334 0, 335 }; 336 337 /* Device states */ 338 static char *q_dev_state[] = { 339 "Unknown", 340 "Cold", 341 "Initializing", 342 "Ready", 343 "Need Reset", 344 "Need Quiescent", 345 "Failed", 346 "Quiescent", 347 }; 348 349 char *qdev_state(uint32_t dev_state) 350 { 351 return q_dev_state[dev_state]; 352 } 353 354 /* 355 * In: 'off_in' is offset from CRB space in 128M pci map 356 * Out: 'off_out' is 2M pci map addr 357 * side effect: lock crb window 358 */ 359 static void 360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 361 void __iomem **off_out) 362 { 363 u32 win_read; 364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 365 366 ha->crb_win = CRB_HI(off_in); 367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 368 369 /* Read back value to make sure write has gone through before trying 370 * to use it. 371 */ 372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 373 if (win_read != ha->crb_win) { 374 ql_dbg(ql_dbg_p3p, vha, 0xb000, 375 "%s: Written crbwin (0x%x) " 376 "!= Read crbwin (0x%x), off=0x%lx.\n", 377 __func__, ha->crb_win, win_read, off_in); 378 } 379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 380 } 381 382 static int 383 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 384 void __iomem **off_out) 385 { 386 struct crb_128M_2M_sub_block_map *m; 387 388 if (off_in >= QLA82XX_CRB_MAX) 389 return -1; 390 391 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 392 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 393 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 394 return 0; 395 } 396 397 if (off_in < QLA82XX_PCI_CRBSPACE) 398 return -1; 399 400 off_in -= QLA82XX_PCI_CRBSPACE; 401 402 /* Try direct map */ 403 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 404 405 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 406 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 407 return 0; 408 } 409 /* Not in direct map, use crb window */ 410 *off_out = (void __iomem *)off_in; 411 return 1; 412 } 413 414 #define CRB_WIN_LOCK_TIMEOUT 100000000 415 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 416 { 417 int done = 0, timeout = 0; 418 419 while (!done) { 420 /* acquire semaphore3 from PCI HW block */ 421 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 422 if (done == 1) 423 break; 424 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 425 return -1; 426 timeout++; 427 } 428 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 429 return 0; 430 } 431 432 int 433 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 434 { 435 void __iomem *off; 436 unsigned long flags = 0; 437 int rv; 438 439 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 440 441 BUG_ON(rv == -1); 442 443 if (rv == 1) { 444 #ifndef __CHECKER__ 445 write_lock_irqsave(&ha->hw_lock, flags); 446 #endif 447 qla82xx_crb_win_lock(ha); 448 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 449 } 450 451 writel(data, (void __iomem *)off); 452 453 if (rv == 1) { 454 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 455 #ifndef __CHECKER__ 456 write_unlock_irqrestore(&ha->hw_lock, flags); 457 #endif 458 } 459 return 0; 460 } 461 462 int 463 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 464 { 465 void __iomem *off; 466 unsigned long flags = 0; 467 int rv; 468 u32 data; 469 470 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 471 472 BUG_ON(rv == -1); 473 474 if (rv == 1) { 475 #ifndef __CHECKER__ 476 write_lock_irqsave(&ha->hw_lock, flags); 477 #endif 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 480 } 481 data = rd_reg_dword(off); 482 483 if (rv == 1) { 484 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 485 #ifndef __CHECKER__ 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 #endif 488 } 489 return data; 490 } 491 492 #define IDC_LOCK_TIMEOUT 100000000 493 int qla82xx_idc_lock(struct qla_hw_data *ha) 494 { 495 int i; 496 int done = 0, timeout = 0; 497 498 while (!done) { 499 /* acquire semaphore5 from PCI HW block */ 500 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 501 if (done == 1) 502 break; 503 if (timeout >= IDC_LOCK_TIMEOUT) 504 return -1; 505 506 timeout++; 507 508 /* Yield CPU */ 509 if (!in_interrupt()) 510 schedule(); 511 else { 512 for (i = 0; i < 20; i++) 513 cpu_relax(); 514 } 515 } 516 517 return 0; 518 } 519 520 void qla82xx_idc_unlock(struct qla_hw_data *ha) 521 { 522 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 523 } 524 525 /* 526 * check memory access boundary. 527 * used by test agent. support ddr access only for now 528 */ 529 static unsigned long 530 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 531 unsigned long long addr, int size) 532 { 533 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 534 QLA82XX_ADDR_DDR_NET_MAX) || 535 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 536 QLA82XX_ADDR_DDR_NET_MAX) || 537 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 538 return 0; 539 else 540 return 1; 541 } 542 543 static int qla82xx_pci_set_window_warning_count; 544 545 static unsigned long 546 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 547 { 548 int window; 549 u32 win_read; 550 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 551 552 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 553 QLA82XX_ADDR_DDR_NET_MAX)) { 554 /* DDR network side */ 555 window = MN_WIN(addr); 556 ha->ddr_mn_window = window; 557 qla82xx_wr_32(ha, 558 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 559 win_read = qla82xx_rd_32(ha, 560 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 561 if ((win_read << 17) != window) { 562 ql_dbg(ql_dbg_p3p, vha, 0xb003, 563 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 564 __func__, window, win_read); 565 } 566 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 567 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 568 QLA82XX_ADDR_OCM0_MAX)) { 569 unsigned int temp1; 570 571 if ((addr & 0x00ff800) == 0xff800) { 572 ql_log(ql_log_warn, vha, 0xb004, 573 "%s: QM access not handled.\n", __func__); 574 addr = -1UL; 575 } 576 window = OCM_WIN(addr); 577 ha->ddr_mn_window = window; 578 qla82xx_wr_32(ha, 579 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 580 win_read = qla82xx_rd_32(ha, 581 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 582 temp1 = ((window & 0x1FF) << 7) | 583 ((window & 0x0FFFE0000) >> 17); 584 if (win_read != temp1) { 585 ql_log(ql_log_warn, vha, 0xb005, 586 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 587 __func__, temp1, win_read); 588 } 589 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 590 591 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 592 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 593 /* QDR network side */ 594 window = MS_WIN(addr); 595 ha->qdr_sn_window = window; 596 qla82xx_wr_32(ha, 597 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 598 win_read = qla82xx_rd_32(ha, 599 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 600 if (win_read != window) { 601 ql_log(ql_log_warn, vha, 0xb006, 602 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 603 __func__, window, win_read); 604 } 605 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 606 } else { 607 /* 608 * peg gdb frequently accesses memory that doesn't exist, 609 * this limits the chit chat so debugging isn't slowed down. 610 */ 611 if ((qla82xx_pci_set_window_warning_count++ < 8) || 612 (qla82xx_pci_set_window_warning_count%64 == 0)) { 613 ql_log(ql_log_warn, vha, 0xb007, 614 "%s: Warning:%s Unknown address range!.\n", 615 __func__, QLA2XXX_DRIVER_NAME); 616 } 617 addr = -1UL; 618 } 619 return addr; 620 } 621 622 /* check if address is in the same windows as the previous access */ 623 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 624 unsigned long long addr) 625 { 626 int window; 627 unsigned long long qdr_max; 628 629 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 630 631 /* DDR network side */ 632 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 633 QLA82XX_ADDR_DDR_NET_MAX)) 634 BUG(); 635 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 636 QLA82XX_ADDR_OCM0_MAX)) 637 return 1; 638 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 639 QLA82XX_ADDR_OCM1_MAX)) 640 return 1; 641 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 642 /* QDR network side */ 643 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 644 if (ha->qdr_sn_window == window) 645 return 1; 646 } 647 return 0; 648 } 649 650 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 651 u64 off, void *data, int size) 652 { 653 unsigned long flags; 654 void __iomem *addr = NULL; 655 int ret = 0; 656 u64 start; 657 uint8_t __iomem *mem_ptr = NULL; 658 unsigned long mem_base; 659 unsigned long mem_page; 660 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 661 662 write_lock_irqsave(&ha->hw_lock, flags); 663 664 /* 665 * If attempting to access unknown address or straddle hw windows, 666 * do not access. 667 */ 668 start = qla82xx_pci_set_window(ha, off); 669 if ((start == -1UL) || 670 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 671 write_unlock_irqrestore(&ha->hw_lock, flags); 672 ql_log(ql_log_fatal, vha, 0xb008, 673 "%s out of bound pci memory " 674 "access, offset is 0x%llx.\n", 675 QLA2XXX_DRIVER_NAME, off); 676 return -1; 677 } 678 679 write_unlock_irqrestore(&ha->hw_lock, flags); 680 mem_base = pci_resource_start(ha->pdev, 0); 681 mem_page = start & PAGE_MASK; 682 /* Map two pages whenever user tries to access addresses in two 683 * consecutive pages. 684 */ 685 if (mem_page != ((start + size - 1) & PAGE_MASK)) 686 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 687 else 688 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 689 if (mem_ptr == NULL) { 690 *(u8 *)data = 0; 691 return -1; 692 } 693 addr = mem_ptr; 694 addr += start & (PAGE_SIZE - 1); 695 write_lock_irqsave(&ha->hw_lock, flags); 696 697 switch (size) { 698 case 1: 699 *(u8 *)data = readb(addr); 700 break; 701 case 2: 702 *(u16 *)data = readw(addr); 703 break; 704 case 4: 705 *(u32 *)data = readl(addr); 706 break; 707 case 8: 708 *(u64 *)data = readq(addr); 709 break; 710 default: 711 ret = -1; 712 break; 713 } 714 write_unlock_irqrestore(&ha->hw_lock, flags); 715 716 if (mem_ptr) 717 iounmap(mem_ptr); 718 return ret; 719 } 720 721 static int 722 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 723 u64 off, void *data, int size) 724 { 725 unsigned long flags; 726 void __iomem *addr = NULL; 727 int ret = 0; 728 u64 start; 729 uint8_t __iomem *mem_ptr = NULL; 730 unsigned long mem_base; 731 unsigned long mem_page; 732 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 733 734 write_lock_irqsave(&ha->hw_lock, flags); 735 736 /* 737 * If attempting to access unknown address or straddle hw windows, 738 * do not access. 739 */ 740 start = qla82xx_pci_set_window(ha, off); 741 if ((start == -1UL) || 742 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 743 write_unlock_irqrestore(&ha->hw_lock, flags); 744 ql_log(ql_log_fatal, vha, 0xb009, 745 "%s out of bound memory " 746 "access, offset is 0x%llx.\n", 747 QLA2XXX_DRIVER_NAME, off); 748 return -1; 749 } 750 751 write_unlock_irqrestore(&ha->hw_lock, flags); 752 mem_base = pci_resource_start(ha->pdev, 0); 753 mem_page = start & PAGE_MASK; 754 /* Map two pages whenever user tries to access addresses in two 755 * consecutive pages. 756 */ 757 if (mem_page != ((start + size - 1) & PAGE_MASK)) 758 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 759 else 760 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 761 if (mem_ptr == NULL) 762 return -1; 763 764 addr = mem_ptr; 765 addr += start & (PAGE_SIZE - 1); 766 write_lock_irqsave(&ha->hw_lock, flags); 767 768 switch (size) { 769 case 1: 770 writeb(*(u8 *)data, addr); 771 break; 772 case 2: 773 writew(*(u16 *)data, addr); 774 break; 775 case 4: 776 writel(*(u32 *)data, addr); 777 break; 778 case 8: 779 writeq(*(u64 *)data, addr); 780 break; 781 default: 782 ret = -1; 783 break; 784 } 785 write_unlock_irqrestore(&ha->hw_lock, flags); 786 if (mem_ptr) 787 iounmap(mem_ptr); 788 return ret; 789 } 790 791 #define MTU_FUDGE_FACTOR 100 792 static unsigned long 793 qla82xx_decode_crb_addr(unsigned long addr) 794 { 795 int i; 796 unsigned long base_addr, offset, pci_base; 797 798 if (!qla82xx_crb_table_initialized) 799 qla82xx_crb_addr_transform_setup(); 800 801 pci_base = ADDR_ERROR; 802 base_addr = addr & 0xfff00000; 803 offset = addr & 0x000fffff; 804 805 for (i = 0; i < MAX_CRB_XFORM; i++) { 806 if (crb_addr_xform[i] == base_addr) { 807 pci_base = i << 20; 808 break; 809 } 810 } 811 if (pci_base == ADDR_ERROR) 812 return pci_base; 813 return pci_base + offset; 814 } 815 816 static long rom_max_timeout = 100; 817 static long qla82xx_rom_lock_timeout = 100; 818 819 static int 820 qla82xx_rom_lock(struct qla_hw_data *ha) 821 { 822 int done = 0, timeout = 0; 823 uint32_t lock_owner = 0; 824 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 825 826 while (!done) { 827 /* acquire semaphore2 from PCI HW block */ 828 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 829 if (done == 1) 830 break; 831 if (timeout >= qla82xx_rom_lock_timeout) { 832 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 833 ql_dbg(ql_dbg_p3p, vha, 0xb157, 834 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 835 __func__, ha->portnum, lock_owner); 836 return -1; 837 } 838 timeout++; 839 } 840 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 841 return 0; 842 } 843 844 static void 845 qla82xx_rom_unlock(struct qla_hw_data *ha) 846 { 847 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 848 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 849 } 850 851 static int 852 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 853 { 854 long timeout = 0; 855 long done = 0 ; 856 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 857 858 while (done == 0) { 859 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 860 done &= 4; 861 timeout++; 862 if (timeout >= rom_max_timeout) { 863 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 864 "%s: Timeout reached waiting for rom busy.\n", 865 QLA2XXX_DRIVER_NAME); 866 return -1; 867 } 868 } 869 return 0; 870 } 871 872 static int 873 qla82xx_wait_rom_done(struct qla_hw_data *ha) 874 { 875 long timeout = 0; 876 long done = 0 ; 877 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 878 879 while (done == 0) { 880 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 881 done &= 2; 882 timeout++; 883 if (timeout >= rom_max_timeout) { 884 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 885 "%s: Timeout reached waiting for rom done.\n", 886 QLA2XXX_DRIVER_NAME); 887 return -1; 888 } 889 } 890 return 0; 891 } 892 893 static int 894 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 895 { 896 uint32_t off_value, rval = 0; 897 898 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 899 900 /* Read back value to make sure write has gone through */ 901 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 902 off_value = (off & 0x0000FFFF); 903 904 if (flag) 905 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 906 data); 907 else 908 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + 909 ha->nx_pcibase); 910 911 return rval; 912 } 913 914 static int 915 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 916 { 917 /* Dword reads to flash. */ 918 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 919 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 920 (addr & 0x0000FFFF), 0, 0); 921 922 return 0; 923 } 924 925 static int 926 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 927 { 928 int ret, loops = 0; 929 uint32_t lock_owner = 0; 930 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 931 932 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 933 udelay(100); 934 schedule(); 935 loops++; 936 } 937 if (loops >= 50000) { 938 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 939 ql_log(ql_log_fatal, vha, 0x00b9, 940 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 941 lock_owner); 942 return -1; 943 } 944 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 945 qla82xx_rom_unlock(ha); 946 return ret; 947 } 948 949 static int 950 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 951 { 952 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 953 954 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 955 qla82xx_wait_rom_busy(ha); 956 if (qla82xx_wait_rom_done(ha)) { 957 ql_log(ql_log_warn, vha, 0xb00c, 958 "Error waiting for rom done.\n"); 959 return -1; 960 } 961 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 962 return 0; 963 } 964 965 static int 966 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 967 { 968 uint32_t val; 969 int i, ret; 970 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 971 972 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 973 for (i = 0; i < 50000; i++) { 974 ret = qla82xx_read_status_reg(ha, &val); 975 if (ret < 0 || (val & 1) == 0) 976 return ret; 977 udelay(10); 978 cond_resched(); 979 } 980 ql_log(ql_log_warn, vha, 0xb00d, 981 "Timeout reached waiting for write finish.\n"); 982 return -1; 983 } 984 985 static int 986 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 987 { 988 uint32_t val; 989 990 qla82xx_wait_rom_busy(ha); 991 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 992 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 993 qla82xx_wait_rom_busy(ha); 994 if (qla82xx_wait_rom_done(ha)) 995 return -1; 996 if (qla82xx_read_status_reg(ha, &val) != 0) 997 return -1; 998 if ((val & 2) != 2) 999 return -1; 1000 return 0; 1001 } 1002 1003 static int 1004 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1005 { 1006 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1007 1008 if (qla82xx_flash_set_write_enable(ha)) 1009 return -1; 1010 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1011 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1012 if (qla82xx_wait_rom_done(ha)) { 1013 ql_log(ql_log_warn, vha, 0xb00e, 1014 "Error waiting for rom done.\n"); 1015 return -1; 1016 } 1017 return qla82xx_flash_wait_write_finish(ha); 1018 } 1019 1020 static int 1021 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1022 { 1023 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1024 1025 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1026 if (qla82xx_wait_rom_done(ha)) { 1027 ql_log(ql_log_warn, vha, 0xb00f, 1028 "Error waiting for rom done.\n"); 1029 return -1; 1030 } 1031 return 0; 1032 } 1033 1034 static int 1035 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1036 { 1037 int loops = 0; 1038 uint32_t lock_owner = 0; 1039 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1040 1041 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1042 udelay(100); 1043 cond_resched(); 1044 loops++; 1045 } 1046 if (loops >= 50000) { 1047 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1048 ql_log(ql_log_warn, vha, 0xb010, 1049 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1050 return -1; 1051 } 1052 return 0; 1053 } 1054 1055 static int 1056 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1057 uint32_t data) 1058 { 1059 int ret = 0; 1060 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1061 1062 ret = ql82xx_rom_lock_d(ha); 1063 if (ret < 0) { 1064 ql_log(ql_log_warn, vha, 0xb011, 1065 "ROM lock failed.\n"); 1066 return ret; 1067 } 1068 1069 ret = qla82xx_flash_set_write_enable(ha); 1070 if (ret < 0) 1071 goto done_write; 1072 1073 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1074 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1075 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1076 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1077 qla82xx_wait_rom_busy(ha); 1078 if (qla82xx_wait_rom_done(ha)) { 1079 ql_log(ql_log_warn, vha, 0xb012, 1080 "Error waiting for rom done.\n"); 1081 ret = -1; 1082 goto done_write; 1083 } 1084 1085 ret = qla82xx_flash_wait_write_finish(ha); 1086 1087 done_write: 1088 qla82xx_rom_unlock(ha); 1089 return ret; 1090 } 1091 1092 /* This routine does CRB initialize sequence 1093 * to put the ISP into operational state 1094 */ 1095 static int 1096 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1097 { 1098 int addr, val; 1099 int i ; 1100 struct crb_addr_pair *buf; 1101 unsigned long off; 1102 unsigned offset, n; 1103 struct qla_hw_data *ha = vha->hw; 1104 1105 struct crb_addr_pair { 1106 long addr; 1107 long data; 1108 }; 1109 1110 /* Halt all the individual PEGs and other blocks of the ISP */ 1111 qla82xx_rom_lock(ha); 1112 1113 /* disable all I2Q */ 1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1116 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1117 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1118 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1120 1121 /* disable all niu interrupts */ 1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1123 /* disable xge rx/tx */ 1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1125 /* disable xg1 rx/tx */ 1126 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1127 /* disable sideband mac */ 1128 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1129 /* disable ap0 mac */ 1130 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1131 /* disable ap1 mac */ 1132 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1133 1134 /* halt sre */ 1135 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1136 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1137 1138 /* halt epg */ 1139 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1140 1141 /* halt timers */ 1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1144 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1145 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1146 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1148 1149 /* halt pegs */ 1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1153 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1154 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1155 msleep(20); 1156 1157 /* big hammer */ 1158 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1159 /* don't reset CAM block on reset */ 1160 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1161 else 1162 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1163 qla82xx_rom_unlock(ha); 1164 1165 /* Read the signature value from the flash. 1166 * Offset 0: Contain signature (0xcafecafe) 1167 * Offset 4: Offset and number of addr/value pairs 1168 * that present in CRB initialize sequence 1169 */ 1170 n = 0; 1171 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1172 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1173 ql_log(ql_log_fatal, vha, 0x006e, 1174 "Error Reading crb_init area: n: %08x.\n", n); 1175 return -1; 1176 } 1177 1178 /* Offset in flash = lower 16 bits 1179 * Number of entries = upper 16 bits 1180 */ 1181 offset = n & 0xffffU; 1182 n = (n >> 16) & 0xffffU; 1183 1184 /* number of addr/value pair should not exceed 1024 entries */ 1185 if (n >= 1024) { 1186 ql_log(ql_log_fatal, vha, 0x0071, 1187 "Card flash not initialized:n=0x%x.\n", n); 1188 return -1; 1189 } 1190 1191 ql_log(ql_log_info, vha, 0x0072, 1192 "%d CRB init values found in ROM.\n", n); 1193 1194 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1195 if (buf == NULL) { 1196 ql_log(ql_log_fatal, vha, 0x010c, 1197 "Unable to allocate memory.\n"); 1198 return -ENOMEM; 1199 } 1200 1201 for (i = 0; i < n; i++) { 1202 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1203 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1204 kfree(buf); 1205 return -1; 1206 } 1207 1208 buf[i].addr = addr; 1209 buf[i].data = val; 1210 } 1211 1212 for (i = 0; i < n; i++) { 1213 /* Translate internal CRB initialization 1214 * address to PCI bus address 1215 */ 1216 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1217 QLA82XX_PCI_CRBSPACE; 1218 /* Not all CRB addr/value pair to be written, 1219 * some of them are skipped 1220 */ 1221 1222 /* skipping cold reboot MAGIC */ 1223 if (off == QLA82XX_CAM_RAM(0x1fc)) 1224 continue; 1225 1226 /* do not reset PCI */ 1227 if (off == (ROMUSB_GLB + 0xbc)) 1228 continue; 1229 1230 /* skip core clock, so that firmware can increase the clock */ 1231 if (off == (ROMUSB_GLB + 0xc8)) 1232 continue; 1233 1234 /* skip the function enable register */ 1235 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1236 continue; 1237 1238 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1239 continue; 1240 1241 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1242 continue; 1243 1244 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1245 continue; 1246 1247 if (off == ADDR_ERROR) { 1248 ql_log(ql_log_fatal, vha, 0x0116, 1249 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1250 continue; 1251 } 1252 1253 qla82xx_wr_32(ha, off, buf[i].data); 1254 1255 /* ISP requires much bigger delay to settle down, 1256 * else crb_window returns 0xffffffff 1257 */ 1258 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1259 msleep(1000); 1260 1261 /* ISP requires millisec delay between 1262 * successive CRB register updation 1263 */ 1264 msleep(1); 1265 } 1266 1267 kfree(buf); 1268 1269 /* Resetting the data and instruction cache */ 1270 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1273 1274 /* Clear all protocol processing engines */ 1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1280 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1281 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1282 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1283 return 0; 1284 } 1285 1286 static int 1287 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1288 u64 off, void *data, int size) 1289 { 1290 int i, j, ret = 0, loop, sz[2], off0; 1291 int scale, shift_amount, startword; 1292 uint32_t temp; 1293 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1294 1295 /* 1296 * If not MN, go check for MS or invalid. 1297 */ 1298 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1299 mem_crb = QLA82XX_CRB_QDR_NET; 1300 else { 1301 mem_crb = QLA82XX_CRB_DDR_NET; 1302 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1303 return qla82xx_pci_mem_write_direct(ha, 1304 off, data, size); 1305 } 1306 1307 off0 = off & 0x7; 1308 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1309 sz[1] = size - sz[0]; 1310 1311 off8 = off & 0xfffffff0; 1312 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1313 shift_amount = 4; 1314 scale = 2; 1315 startword = (off & 0xf)/8; 1316 1317 for (i = 0; i < loop; i++) { 1318 if (qla82xx_pci_mem_read_2M(ha, off8 + 1319 (i << shift_amount), &word[i * scale], 8)) 1320 return -1; 1321 } 1322 1323 switch (size) { 1324 case 1: 1325 tmpw = *((uint8_t *)data); 1326 break; 1327 case 2: 1328 tmpw = *((uint16_t *)data); 1329 break; 1330 case 4: 1331 tmpw = *((uint32_t *)data); 1332 break; 1333 case 8: 1334 default: 1335 tmpw = *((uint64_t *)data); 1336 break; 1337 } 1338 1339 if (sz[0] == 8) { 1340 word[startword] = tmpw; 1341 } else { 1342 word[startword] &= 1343 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1344 word[startword] |= tmpw << (off0 * 8); 1345 } 1346 if (sz[1] != 0) { 1347 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1348 word[startword+1] |= tmpw >> (sz[0] * 8); 1349 } 1350 1351 for (i = 0; i < loop; i++) { 1352 temp = off8 + (i << shift_amount); 1353 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1354 temp = 0; 1355 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1356 temp = word[i * scale] & 0xffffffff; 1357 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1358 temp = (word[i * scale] >> 32) & 0xffffffff; 1359 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1360 temp = word[i*scale + 1] & 0xffffffff; 1361 qla82xx_wr_32(ha, mem_crb + 1362 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1363 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1364 qla82xx_wr_32(ha, mem_crb + 1365 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1366 1367 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1368 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1369 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1370 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1371 1372 for (j = 0; j < MAX_CTL_CHECK; j++) { 1373 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1374 if ((temp & MIU_TA_CTL_BUSY) == 0) 1375 break; 1376 } 1377 1378 if (j >= MAX_CTL_CHECK) { 1379 if (printk_ratelimit()) 1380 dev_err(&ha->pdev->dev, 1381 "failed to write through agent.\n"); 1382 ret = -1; 1383 break; 1384 } 1385 } 1386 1387 return ret; 1388 } 1389 1390 static int 1391 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1392 { 1393 int i; 1394 long size = 0; 1395 long flashaddr = ha->flt_region_bootload << 2; 1396 long memaddr = BOOTLD_START; 1397 u64 data; 1398 u32 high, low; 1399 1400 size = (IMAGE_START - BOOTLD_START) / 8; 1401 1402 for (i = 0; i < size; i++) { 1403 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1404 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1405 return -1; 1406 } 1407 data = ((u64)high << 32) | low ; 1408 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1409 flashaddr += 8; 1410 memaddr += 8; 1411 1412 if (i % 0x1000 == 0) 1413 msleep(1); 1414 } 1415 udelay(100); 1416 read_lock(&ha->hw_lock); 1417 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1418 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1419 read_unlock(&ha->hw_lock); 1420 return 0; 1421 } 1422 1423 int 1424 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1425 u64 off, void *data, int size) 1426 { 1427 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1428 int shift_amount; 1429 uint32_t temp; 1430 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1431 1432 /* 1433 * If not MN, go check for MS or invalid. 1434 */ 1435 1436 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1437 mem_crb = QLA82XX_CRB_QDR_NET; 1438 else { 1439 mem_crb = QLA82XX_CRB_DDR_NET; 1440 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1441 return qla82xx_pci_mem_read_direct(ha, 1442 off, data, size); 1443 } 1444 1445 off8 = off & 0xfffffff0; 1446 off0[0] = off & 0xf; 1447 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1448 shift_amount = 4; 1449 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1450 off0[1] = 0; 1451 sz[1] = size - sz[0]; 1452 1453 for (i = 0; i < loop; i++) { 1454 temp = off8 + (i << shift_amount); 1455 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1456 temp = 0; 1457 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1458 temp = MIU_TA_CTL_ENABLE; 1459 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1460 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1461 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1462 1463 for (j = 0; j < MAX_CTL_CHECK; j++) { 1464 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1465 if ((temp & MIU_TA_CTL_BUSY) == 0) 1466 break; 1467 } 1468 1469 if (j >= MAX_CTL_CHECK) { 1470 if (printk_ratelimit()) 1471 dev_err(&ha->pdev->dev, 1472 "failed to read through agent.\n"); 1473 break; 1474 } 1475 1476 start = off0[i] >> 2; 1477 end = (off0[i] + sz[i] - 1) >> 2; 1478 for (k = start; k <= end; k++) { 1479 temp = qla82xx_rd_32(ha, 1480 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1481 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1482 } 1483 } 1484 1485 if (j >= MAX_CTL_CHECK) 1486 return -1; 1487 1488 if ((off0[0] & 7) == 0) { 1489 val = word[0]; 1490 } else { 1491 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1492 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1493 } 1494 1495 switch (size) { 1496 case 1: 1497 *(uint8_t *)data = val; 1498 break; 1499 case 2: 1500 *(uint16_t *)data = val; 1501 break; 1502 case 4: 1503 *(uint32_t *)data = val; 1504 break; 1505 case 8: 1506 *(uint64_t *)data = val; 1507 break; 1508 } 1509 return 0; 1510 } 1511 1512 1513 static struct qla82xx_uri_table_desc * 1514 qla82xx_get_table_desc(const u8 *unirom, int section) 1515 { 1516 uint32_t i; 1517 struct qla82xx_uri_table_desc *directory = 1518 (struct qla82xx_uri_table_desc *)&unirom[0]; 1519 uint32_t offset; 1520 uint32_t tab_type; 1521 uint32_t entries = le32_to_cpu(directory->num_entries); 1522 1523 for (i = 0; i < entries; i++) { 1524 offset = le32_to_cpu(directory->findex) + 1525 (i * le32_to_cpu(directory->entry_size)); 1526 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8); 1527 1528 if (tab_type == section) 1529 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1530 } 1531 1532 return NULL; 1533 } 1534 1535 static struct qla82xx_uri_data_desc * 1536 qla82xx_get_data_desc(struct qla_hw_data *ha, 1537 u32 section, u32 idx_offset) 1538 { 1539 const u8 *unirom = ha->hablob->fw->data; 1540 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] + 1541 idx_offset); 1542 struct qla82xx_uri_table_desc *tab_desc = NULL; 1543 uint32_t offset; 1544 1545 tab_desc = qla82xx_get_table_desc(unirom, section); 1546 if (!tab_desc) 1547 return NULL; 1548 1549 offset = le32_to_cpu(tab_desc->findex) + 1550 (le32_to_cpu(tab_desc->entry_size) * idx); 1551 1552 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1553 } 1554 1555 static u8 * 1556 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1557 { 1558 u32 offset = BOOTLD_START; 1559 struct qla82xx_uri_data_desc *uri_desc = NULL; 1560 1561 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1562 uri_desc = qla82xx_get_data_desc(ha, 1563 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1564 if (uri_desc) 1565 offset = le32_to_cpu(uri_desc->findex); 1566 } 1567 1568 return (u8 *)&ha->hablob->fw->data[offset]; 1569 } 1570 1571 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha) 1572 { 1573 struct qla82xx_uri_data_desc *uri_desc = NULL; 1574 1575 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1576 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1577 QLA82XX_URI_FIRMWARE_IDX_OFF); 1578 if (uri_desc) 1579 return le32_to_cpu(uri_desc->size); 1580 } 1581 1582 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1583 } 1584 1585 static u8 * 1586 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1587 { 1588 u32 offset = IMAGE_START; 1589 struct qla82xx_uri_data_desc *uri_desc = NULL; 1590 1591 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1592 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1593 QLA82XX_URI_FIRMWARE_IDX_OFF); 1594 if (uri_desc) 1595 offset = le32_to_cpu(uri_desc->findex); 1596 } 1597 1598 return (u8 *)&ha->hablob->fw->data[offset]; 1599 } 1600 1601 /* PCI related functions */ 1602 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1603 { 1604 unsigned long val = 0; 1605 u32 control; 1606 1607 switch (region) { 1608 case 0: 1609 val = 0; 1610 break; 1611 case 1: 1612 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1613 val = control + QLA82XX_MSIX_TBL_SPACE; 1614 break; 1615 } 1616 return val; 1617 } 1618 1619 1620 int 1621 qla82xx_iospace_config(struct qla_hw_data *ha) 1622 { 1623 uint32_t len = 0; 1624 1625 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1626 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1627 "Failed to reserver selected regions.\n"); 1628 goto iospace_error_exit; 1629 } 1630 1631 /* Use MMIO operations for all accesses. */ 1632 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1633 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1634 "Region #0 not an MMIO resource, aborting.\n"); 1635 goto iospace_error_exit; 1636 } 1637 1638 len = pci_resource_len(ha->pdev, 0); 1639 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1640 if (!ha->nx_pcibase) { 1641 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1642 "Cannot remap pcibase MMIO, aborting.\n"); 1643 goto iospace_error_exit; 1644 } 1645 1646 /* Mapping of IO base pointer */ 1647 if (IS_QLA8044(ha)) { 1648 ha->iobase = ha->nx_pcibase; 1649 } else if (IS_QLA82XX(ha)) { 1650 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1651 } 1652 1653 if (!ql2xdbwr) { 1654 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1655 (ha->pdev->devfn << 12)), 4); 1656 if (!ha->nxdb_wr_ptr) { 1657 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1658 "Cannot remap MMIO, aborting.\n"); 1659 goto iospace_error_exit; 1660 } 1661 1662 /* Mapping of IO base pointer, 1663 * door bell read and write pointer 1664 */ 1665 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1666 (ha->pdev->devfn * 8); 1667 } else { 1668 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1669 QLA82XX_CAMRAM_DB1 : 1670 QLA82XX_CAMRAM_DB2); 1671 } 1672 1673 ha->max_req_queues = ha->max_rsp_queues = 1; 1674 ha->msix_count = ha->max_rsp_queues + 1; 1675 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1676 "nx_pci_base=%p iobase=%p " 1677 "max_req_queues=%d msix_count=%d.\n", 1678 ha->nx_pcibase, ha->iobase, 1679 ha->max_req_queues, ha->msix_count); 1680 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1681 "nx_pci_base=%p iobase=%p " 1682 "max_req_queues=%d msix_count=%d.\n", 1683 ha->nx_pcibase, ha->iobase, 1684 ha->max_req_queues, ha->msix_count); 1685 return 0; 1686 1687 iospace_error_exit: 1688 return -ENOMEM; 1689 } 1690 1691 /* GS related functions */ 1692 1693 /* Initialization related functions */ 1694 1695 /** 1696 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1697 * @vha: HA context 1698 * 1699 * Returns 0 on success. 1700 */ 1701 int 1702 qla82xx_pci_config(scsi_qla_host_t *vha) 1703 { 1704 struct qla_hw_data *ha = vha->hw; 1705 int ret; 1706 1707 pci_set_master(ha->pdev); 1708 ret = pci_set_mwi(ha->pdev); 1709 ha->chip_revision = ha->pdev->revision; 1710 ql_dbg(ql_dbg_init, vha, 0x0043, 1711 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1712 ha->chip_revision, ret); 1713 return 0; 1714 } 1715 1716 /** 1717 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1718 * @vha: HA context 1719 * 1720 * Returns 0 on success. 1721 */ 1722 int 1723 qla82xx_reset_chip(scsi_qla_host_t *vha) 1724 { 1725 struct qla_hw_data *ha = vha->hw; 1726 1727 ha->isp_ops->disable_intrs(ha); 1728 1729 return QLA_SUCCESS; 1730 } 1731 1732 void qla82xx_config_rings(struct scsi_qla_host *vha) 1733 { 1734 struct qla_hw_data *ha = vha->hw; 1735 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1736 struct init_cb_81xx *icb; 1737 struct req_que *req = ha->req_q_map[0]; 1738 struct rsp_que *rsp = ha->rsp_q_map[0]; 1739 1740 /* Setup ring parameters in initialization control block. */ 1741 icb = (struct init_cb_81xx *)ha->init_cb; 1742 icb->request_q_outpointer = cpu_to_le16(0); 1743 icb->response_q_inpointer = cpu_to_le16(0); 1744 icb->request_q_length = cpu_to_le16(req->length); 1745 icb->response_q_length = cpu_to_le16(rsp->length); 1746 put_unaligned_le64(req->dma, &icb->request_q_address); 1747 put_unaligned_le64(rsp->dma, &icb->response_q_address); 1748 1749 wrt_reg_dword(®->req_q_out[0], 0); 1750 wrt_reg_dword(®->rsp_q_in[0], 0); 1751 wrt_reg_dword(®->rsp_q_out[0], 0); 1752 } 1753 1754 static int 1755 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1756 { 1757 u64 *ptr64; 1758 u32 i, flashaddr, size; 1759 __le64 data; 1760 1761 size = (IMAGE_START - BOOTLD_START) / 8; 1762 1763 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1764 flashaddr = BOOTLD_START; 1765 1766 for (i = 0; i < size; i++) { 1767 data = cpu_to_le64(ptr64[i]); 1768 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1769 return -EIO; 1770 flashaddr += 8; 1771 } 1772 1773 flashaddr = FLASH_ADDR_START; 1774 size = qla82xx_get_fw_size(ha) / 8; 1775 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1776 1777 for (i = 0; i < size; i++) { 1778 data = cpu_to_le64(ptr64[i]); 1779 1780 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1781 return -EIO; 1782 flashaddr += 8; 1783 } 1784 udelay(100); 1785 1786 /* Write a magic value to CAMRAM register 1787 * at a specified offset to indicate 1788 * that all data is written and 1789 * ready for firmware to initialize. 1790 */ 1791 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1792 1793 read_lock(&ha->hw_lock); 1794 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1795 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1796 read_unlock(&ha->hw_lock); 1797 return 0; 1798 } 1799 1800 static int 1801 qla82xx_set_product_offset(struct qla_hw_data *ha) 1802 { 1803 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1804 const uint8_t *unirom = ha->hablob->fw->data; 1805 uint32_t i; 1806 uint32_t entries; 1807 uint32_t flags, file_chiprev, offset; 1808 uint8_t chiprev = ha->chip_revision; 1809 /* Hardcoding mn_present flag for P3P */ 1810 int mn_present = 0; 1811 uint32_t flagbit; 1812 1813 ptab_desc = qla82xx_get_table_desc(unirom, 1814 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1815 if (!ptab_desc) 1816 return -1; 1817 1818 entries = le32_to_cpu(ptab_desc->num_entries); 1819 1820 for (i = 0; i < entries; i++) { 1821 offset = le32_to_cpu(ptab_desc->findex) + 1822 (i * le32_to_cpu(ptab_desc->entry_size)); 1823 flags = le32_to_cpu(*((__le32 *)&unirom[offset] + 1824 QLA82XX_URI_FLAGS_OFF)); 1825 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] + 1826 QLA82XX_URI_CHIP_REV_OFF)); 1827 1828 flagbit = mn_present ? 1 : 2; 1829 1830 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1831 ha->file_prd_off = offset; 1832 return 0; 1833 } 1834 } 1835 return -1; 1836 } 1837 1838 static int 1839 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1840 { 1841 uint32_t val; 1842 uint32_t min_size; 1843 struct qla_hw_data *ha = vha->hw; 1844 const struct firmware *fw = ha->hablob->fw; 1845 1846 ha->fw_type = fw_type; 1847 1848 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1849 if (qla82xx_set_product_offset(ha)) 1850 return -EINVAL; 1851 1852 min_size = QLA82XX_URI_FW_MIN_SIZE; 1853 } else { 1854 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1855 if (val != QLA82XX_BDINFO_MAGIC) 1856 return -EINVAL; 1857 1858 min_size = QLA82XX_FW_MIN_SIZE; 1859 } 1860 1861 if (fw->size < min_size) 1862 return -EINVAL; 1863 return 0; 1864 } 1865 1866 static int 1867 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1868 { 1869 u32 val = 0; 1870 int retries = 60; 1871 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1872 1873 do { 1874 read_lock(&ha->hw_lock); 1875 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1876 read_unlock(&ha->hw_lock); 1877 1878 switch (val) { 1879 case PHAN_INITIALIZE_COMPLETE: 1880 case PHAN_INITIALIZE_ACK: 1881 return QLA_SUCCESS; 1882 case PHAN_INITIALIZE_FAILED: 1883 break; 1884 default: 1885 break; 1886 } 1887 ql_log(ql_log_info, vha, 0x00a8, 1888 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1889 val, retries); 1890 1891 msleep(500); 1892 1893 } while (--retries); 1894 1895 ql_log(ql_log_fatal, vha, 0x00a9, 1896 "Cmd Peg initialization failed: 0x%x.\n", val); 1897 1898 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1899 read_lock(&ha->hw_lock); 1900 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1901 read_unlock(&ha->hw_lock); 1902 return QLA_FUNCTION_FAILED; 1903 } 1904 1905 static int 1906 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1907 { 1908 u32 val = 0; 1909 int retries = 60; 1910 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1911 1912 do { 1913 read_lock(&ha->hw_lock); 1914 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1915 read_unlock(&ha->hw_lock); 1916 1917 switch (val) { 1918 case PHAN_INITIALIZE_COMPLETE: 1919 case PHAN_INITIALIZE_ACK: 1920 return QLA_SUCCESS; 1921 case PHAN_INITIALIZE_FAILED: 1922 break; 1923 default: 1924 break; 1925 } 1926 ql_log(ql_log_info, vha, 0x00ab, 1927 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1928 val, retries); 1929 1930 msleep(500); 1931 1932 } while (--retries); 1933 1934 ql_log(ql_log_fatal, vha, 0x00ac, 1935 "Rcv Peg initialization failed: 0x%x.\n", val); 1936 read_lock(&ha->hw_lock); 1937 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1938 read_unlock(&ha->hw_lock); 1939 return QLA_FUNCTION_FAILED; 1940 } 1941 1942 /* ISR related functions */ 1943 static struct qla82xx_legacy_intr_set legacy_intr[] = 1944 QLA82XX_LEGACY_INTR_CONFIG; 1945 1946 /* 1947 * qla82xx_mbx_completion() - Process mailbox command completions. 1948 * @ha: SCSI driver HA context 1949 * @mb0: Mailbox0 register 1950 */ 1951 void 1952 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1953 { 1954 uint16_t cnt; 1955 __le16 __iomem *wptr; 1956 struct qla_hw_data *ha = vha->hw; 1957 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1958 1959 wptr = ®->mailbox_out[1]; 1960 1961 /* Load return mailbox registers. */ 1962 ha->flags.mbox_int = 1; 1963 ha->mailbox_out[0] = mb0; 1964 1965 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1966 ha->mailbox_out[cnt] = rd_reg_word(wptr); 1967 wptr++; 1968 } 1969 1970 if (!ha->mcp) 1971 ql_dbg(ql_dbg_async, vha, 0x5053, 1972 "MBX pointer ERROR.\n"); 1973 } 1974 1975 /** 1976 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1977 * @irq: interrupt number 1978 * @dev_id: SCSI driver HA context 1979 * 1980 * Called by system whenever the host adapter generates an interrupt. 1981 * 1982 * Returns handled flag. 1983 */ 1984 irqreturn_t 1985 qla82xx_intr_handler(int irq, void *dev_id) 1986 { 1987 scsi_qla_host_t *vha; 1988 struct qla_hw_data *ha; 1989 struct rsp_que *rsp; 1990 struct device_reg_82xx __iomem *reg; 1991 int status = 0, status1 = 0; 1992 unsigned long flags; 1993 unsigned long iter; 1994 uint32_t stat = 0; 1995 uint16_t mb[8]; 1996 1997 rsp = (struct rsp_que *) dev_id; 1998 if (!rsp) { 1999 ql_log(ql_log_info, NULL, 0xb053, 2000 "%s: NULL response queue pointer.\n", __func__); 2001 return IRQ_NONE; 2002 } 2003 ha = rsp->hw; 2004 2005 if (!ha->flags.msi_enabled) { 2006 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2007 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2008 return IRQ_NONE; 2009 2010 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2011 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2012 return IRQ_NONE; 2013 } 2014 2015 /* clear the interrupt */ 2016 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2017 2018 /* read twice to ensure write is flushed */ 2019 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2020 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2021 2022 reg = &ha->iobase->isp82; 2023 2024 spin_lock_irqsave(&ha->hardware_lock, flags); 2025 vha = pci_get_drvdata(ha->pdev); 2026 for (iter = 1; iter--; ) { 2027 2028 if (rd_reg_dword(®->host_int)) { 2029 stat = rd_reg_dword(®->host_status); 2030 2031 switch (stat & 0xff) { 2032 case 0x1: 2033 case 0x2: 2034 case 0x10: 2035 case 0x11: 2036 qla82xx_mbx_completion(vha, MSW(stat)); 2037 status |= MBX_INTERRUPT; 2038 break; 2039 case 0x12: 2040 mb[0] = MSW(stat); 2041 mb[1] = rd_reg_word(®->mailbox_out[1]); 2042 mb[2] = rd_reg_word(®->mailbox_out[2]); 2043 mb[3] = rd_reg_word(®->mailbox_out[3]); 2044 qla2x00_async_event(vha, rsp, mb); 2045 break; 2046 case 0x13: 2047 qla24xx_process_response_queue(vha, rsp); 2048 break; 2049 default: 2050 ql_dbg(ql_dbg_async, vha, 0x5054, 2051 "Unrecognized interrupt type (%d).\n", 2052 stat & 0xff); 2053 break; 2054 } 2055 } 2056 wrt_reg_dword(®->host_int, 0); 2057 } 2058 2059 qla2x00_handle_mbx_completion(ha, status); 2060 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2061 2062 if (!ha->flags.msi_enabled) 2063 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2064 2065 return IRQ_HANDLED; 2066 } 2067 2068 irqreturn_t 2069 qla82xx_msix_default(int irq, void *dev_id) 2070 { 2071 scsi_qla_host_t *vha; 2072 struct qla_hw_data *ha; 2073 struct rsp_que *rsp; 2074 struct device_reg_82xx __iomem *reg; 2075 int status = 0; 2076 unsigned long flags; 2077 uint32_t stat = 0; 2078 uint32_t host_int = 0; 2079 uint16_t mb[8]; 2080 2081 rsp = (struct rsp_que *) dev_id; 2082 if (!rsp) { 2083 printk(KERN_INFO 2084 "%s(): NULL response queue pointer.\n", __func__); 2085 return IRQ_NONE; 2086 } 2087 ha = rsp->hw; 2088 2089 reg = &ha->iobase->isp82; 2090 2091 spin_lock_irqsave(&ha->hardware_lock, flags); 2092 vha = pci_get_drvdata(ha->pdev); 2093 do { 2094 host_int = rd_reg_dword(®->host_int); 2095 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2096 break; 2097 if (host_int) { 2098 stat = rd_reg_dword(®->host_status); 2099 2100 switch (stat & 0xff) { 2101 case 0x1: 2102 case 0x2: 2103 case 0x10: 2104 case 0x11: 2105 qla82xx_mbx_completion(vha, MSW(stat)); 2106 status |= MBX_INTERRUPT; 2107 break; 2108 case 0x12: 2109 mb[0] = MSW(stat); 2110 mb[1] = rd_reg_word(®->mailbox_out[1]); 2111 mb[2] = rd_reg_word(®->mailbox_out[2]); 2112 mb[3] = rd_reg_word(®->mailbox_out[3]); 2113 qla2x00_async_event(vha, rsp, mb); 2114 break; 2115 case 0x13: 2116 qla24xx_process_response_queue(vha, rsp); 2117 break; 2118 default: 2119 ql_dbg(ql_dbg_async, vha, 0x5041, 2120 "Unrecognized interrupt type (%d).\n", 2121 stat & 0xff); 2122 break; 2123 } 2124 } 2125 wrt_reg_dword(®->host_int, 0); 2126 } while (0); 2127 2128 qla2x00_handle_mbx_completion(ha, status); 2129 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2130 2131 return IRQ_HANDLED; 2132 } 2133 2134 irqreturn_t 2135 qla82xx_msix_rsp_q(int irq, void *dev_id) 2136 { 2137 scsi_qla_host_t *vha; 2138 struct qla_hw_data *ha; 2139 struct rsp_que *rsp; 2140 struct device_reg_82xx __iomem *reg; 2141 unsigned long flags; 2142 uint32_t host_int = 0; 2143 2144 rsp = (struct rsp_que *) dev_id; 2145 if (!rsp) { 2146 printk(KERN_INFO 2147 "%s(): NULL response queue pointer.\n", __func__); 2148 return IRQ_NONE; 2149 } 2150 2151 ha = rsp->hw; 2152 reg = &ha->iobase->isp82; 2153 spin_lock_irqsave(&ha->hardware_lock, flags); 2154 vha = pci_get_drvdata(ha->pdev); 2155 host_int = rd_reg_dword(®->host_int); 2156 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2157 goto out; 2158 qla24xx_process_response_queue(vha, rsp); 2159 wrt_reg_dword(®->host_int, 0); 2160 out: 2161 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2162 return IRQ_HANDLED; 2163 } 2164 2165 void 2166 qla82xx_poll(int irq, void *dev_id) 2167 { 2168 scsi_qla_host_t *vha; 2169 struct qla_hw_data *ha; 2170 struct rsp_que *rsp; 2171 struct device_reg_82xx __iomem *reg; 2172 int status = 0; 2173 uint32_t stat; 2174 uint32_t host_int = 0; 2175 uint16_t mb[8]; 2176 unsigned long flags; 2177 2178 rsp = (struct rsp_que *) dev_id; 2179 if (!rsp) { 2180 printk(KERN_INFO 2181 "%s(): NULL response queue pointer.\n", __func__); 2182 return; 2183 } 2184 ha = rsp->hw; 2185 2186 reg = &ha->iobase->isp82; 2187 spin_lock_irqsave(&ha->hardware_lock, flags); 2188 vha = pci_get_drvdata(ha->pdev); 2189 2190 host_int = rd_reg_dword(®->host_int); 2191 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2192 goto out; 2193 if (host_int) { 2194 stat = rd_reg_dword(®->host_status); 2195 switch (stat & 0xff) { 2196 case 0x1: 2197 case 0x2: 2198 case 0x10: 2199 case 0x11: 2200 qla82xx_mbx_completion(vha, MSW(stat)); 2201 status |= MBX_INTERRUPT; 2202 break; 2203 case 0x12: 2204 mb[0] = MSW(stat); 2205 mb[1] = rd_reg_word(®->mailbox_out[1]); 2206 mb[2] = rd_reg_word(®->mailbox_out[2]); 2207 mb[3] = rd_reg_word(®->mailbox_out[3]); 2208 qla2x00_async_event(vha, rsp, mb); 2209 break; 2210 case 0x13: 2211 qla24xx_process_response_queue(vha, rsp); 2212 break; 2213 default: 2214 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2215 "Unrecognized interrupt type (%d).\n", 2216 stat * 0xff); 2217 break; 2218 } 2219 wrt_reg_dword(®->host_int, 0); 2220 } 2221 out: 2222 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2223 } 2224 2225 void 2226 qla82xx_enable_intrs(struct qla_hw_data *ha) 2227 { 2228 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2229 2230 qla82xx_mbx_intr_enable(vha); 2231 spin_lock_irq(&ha->hardware_lock); 2232 if (IS_QLA8044(ha)) 2233 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2234 else 2235 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2236 spin_unlock_irq(&ha->hardware_lock); 2237 ha->interrupts_on = 1; 2238 } 2239 2240 void 2241 qla82xx_disable_intrs(struct qla_hw_data *ha) 2242 { 2243 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2244 2245 if (ha->interrupts_on) 2246 qla82xx_mbx_intr_disable(vha); 2247 2248 spin_lock_irq(&ha->hardware_lock); 2249 if (IS_QLA8044(ha)) 2250 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2251 else 2252 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2253 spin_unlock_irq(&ha->hardware_lock); 2254 ha->interrupts_on = 0; 2255 } 2256 2257 void qla82xx_init_flags(struct qla_hw_data *ha) 2258 { 2259 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2260 2261 /* ISP 8021 initializations */ 2262 rwlock_init(&ha->hw_lock); 2263 ha->qdr_sn_window = -1; 2264 ha->ddr_mn_window = -1; 2265 ha->curr_window = 255; 2266 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2267 nx_legacy_intr = &legacy_intr[ha->portnum]; 2268 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2269 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2270 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2271 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2272 } 2273 2274 static inline void 2275 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2276 { 2277 int idc_ver; 2278 uint32_t drv_active; 2279 struct qla_hw_data *ha = vha->hw; 2280 2281 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2282 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2283 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2284 QLA82XX_IDC_VERSION); 2285 ql_log(ql_log_info, vha, 0xb082, 2286 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2287 } else { 2288 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2289 if (idc_ver != QLA82XX_IDC_VERSION) 2290 ql_log(ql_log_info, vha, 0xb083, 2291 "qla2xxx driver IDC version %d is not compatible " 2292 "with IDC version %d of the other drivers\n", 2293 QLA82XX_IDC_VERSION, idc_ver); 2294 } 2295 } 2296 2297 inline void 2298 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2299 { 2300 uint32_t drv_active; 2301 struct qla_hw_data *ha = vha->hw; 2302 2303 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2304 2305 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2306 if (drv_active == 0xffffffff) { 2307 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2308 QLA82XX_DRV_NOT_ACTIVE); 2309 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2310 } 2311 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2312 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2313 } 2314 2315 inline void 2316 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2317 { 2318 uint32_t drv_active; 2319 2320 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2321 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2322 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2323 } 2324 2325 static inline int 2326 qla82xx_need_reset(struct qla_hw_data *ha) 2327 { 2328 uint32_t drv_state; 2329 int rval; 2330 2331 if (ha->flags.nic_core_reset_owner) 2332 return 1; 2333 else { 2334 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2335 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2336 return rval; 2337 } 2338 } 2339 2340 static inline void 2341 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2342 { 2343 uint32_t drv_state; 2344 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2345 2346 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2347 2348 /* If reset value is all FF's, initialize DRV_STATE */ 2349 if (drv_state == 0xffffffff) { 2350 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2351 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2352 } 2353 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2354 ql_dbg(ql_dbg_init, vha, 0x00bb, 2355 "drv_state = 0x%08x.\n", drv_state); 2356 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2357 } 2358 2359 static inline void 2360 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2361 { 2362 uint32_t drv_state; 2363 2364 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2365 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2366 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2367 } 2368 2369 static inline void 2370 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2371 { 2372 uint32_t qsnt_state; 2373 2374 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2375 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2376 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2377 } 2378 2379 void 2380 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2381 { 2382 struct qla_hw_data *ha = vha->hw; 2383 uint32_t qsnt_state; 2384 2385 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2386 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2387 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2388 } 2389 2390 static int 2391 qla82xx_load_fw(scsi_qla_host_t *vha) 2392 { 2393 int rst; 2394 struct fw_blob *blob; 2395 struct qla_hw_data *ha = vha->hw; 2396 2397 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2398 ql_log(ql_log_fatal, vha, 0x009f, 2399 "Error during CRB initialization.\n"); 2400 return QLA_FUNCTION_FAILED; 2401 } 2402 udelay(500); 2403 2404 /* Bring QM and CAMRAM out of reset */ 2405 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2406 rst &= ~((1 << 28) | (1 << 24)); 2407 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2408 2409 /* 2410 * FW Load priority: 2411 * 1) Operational firmware residing in flash. 2412 * 2) Firmware via request-firmware interface (.bin file). 2413 */ 2414 if (ql2xfwloadbin == 2) 2415 goto try_blob_fw; 2416 2417 ql_log(ql_log_info, vha, 0x00a0, 2418 "Attempting to load firmware from flash.\n"); 2419 2420 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2421 ql_log(ql_log_info, vha, 0x00a1, 2422 "Firmware loaded successfully from flash.\n"); 2423 return QLA_SUCCESS; 2424 } else { 2425 ql_log(ql_log_warn, vha, 0x0108, 2426 "Firmware load from flash failed.\n"); 2427 } 2428 2429 try_blob_fw: 2430 ql_log(ql_log_info, vha, 0x00a2, 2431 "Attempting to load firmware from blob.\n"); 2432 2433 /* Load firmware blob. */ 2434 blob = ha->hablob = qla2x00_request_firmware(vha); 2435 if (!blob) { 2436 ql_log(ql_log_fatal, vha, 0x00a3, 2437 "Firmware image not present.\n"); 2438 goto fw_load_failed; 2439 } 2440 2441 /* Validating firmware blob */ 2442 if (qla82xx_validate_firmware_blob(vha, 2443 QLA82XX_FLASH_ROMIMAGE)) { 2444 /* Fallback to URI format */ 2445 if (qla82xx_validate_firmware_blob(vha, 2446 QLA82XX_UNIFIED_ROMIMAGE)) { 2447 ql_log(ql_log_fatal, vha, 0x00a4, 2448 "No valid firmware image found.\n"); 2449 return QLA_FUNCTION_FAILED; 2450 } 2451 } 2452 2453 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2454 ql_log(ql_log_info, vha, 0x00a5, 2455 "Firmware loaded successfully from binary blob.\n"); 2456 return QLA_SUCCESS; 2457 } 2458 2459 ql_log(ql_log_fatal, vha, 0x00a6, 2460 "Firmware load failed for binary blob.\n"); 2461 blob->fw = NULL; 2462 blob = NULL; 2463 2464 fw_load_failed: 2465 return QLA_FUNCTION_FAILED; 2466 } 2467 2468 int 2469 qla82xx_start_firmware(scsi_qla_host_t *vha) 2470 { 2471 uint16_t lnk; 2472 struct qla_hw_data *ha = vha->hw; 2473 2474 /* scrub dma mask expansion register */ 2475 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2476 2477 /* Put both the PEG CMD and RCV PEG to default state 2478 * of 0 before resetting the hardware 2479 */ 2480 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2481 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2482 2483 /* Overwrite stale initialization register values */ 2484 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2485 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2486 2487 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2488 ql_log(ql_log_fatal, vha, 0x00a7, 2489 "Error trying to start fw.\n"); 2490 return QLA_FUNCTION_FAILED; 2491 } 2492 2493 /* Handshake with the card before we register the devices. */ 2494 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2495 ql_log(ql_log_fatal, vha, 0x00aa, 2496 "Error during card handshake.\n"); 2497 return QLA_FUNCTION_FAILED; 2498 } 2499 2500 /* Negotiated Link width */ 2501 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2502 ha->link_width = (lnk >> 4) & 0x3f; 2503 2504 /* Synchronize with Receive peg */ 2505 return qla82xx_check_rcvpeg_state(ha); 2506 } 2507 2508 static __le32 * 2509 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 2510 uint32_t length) 2511 { 2512 uint32_t i; 2513 uint32_t val; 2514 struct qla_hw_data *ha = vha->hw; 2515 2516 /* Dword reads to flash. */ 2517 for (i = 0; i < length/4; i++, faddr += 4) { 2518 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2519 ql_log(ql_log_warn, vha, 0x0106, 2520 "Do ROM fast read failed.\n"); 2521 goto done_read; 2522 } 2523 dwptr[i] = cpu_to_le32(val); 2524 } 2525 done_read: 2526 return dwptr; 2527 } 2528 2529 static int 2530 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2531 { 2532 int ret; 2533 uint32_t val; 2534 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2535 2536 ret = ql82xx_rom_lock_d(ha); 2537 if (ret < 0) { 2538 ql_log(ql_log_warn, vha, 0xb014, 2539 "ROM Lock failed.\n"); 2540 return ret; 2541 } 2542 2543 ret = qla82xx_read_status_reg(ha, &val); 2544 if (ret < 0) 2545 goto done_unprotect; 2546 2547 val &= ~(BLOCK_PROTECT_BITS << 2); 2548 ret = qla82xx_write_status_reg(ha, val); 2549 if (ret < 0) { 2550 val |= (BLOCK_PROTECT_BITS << 2); 2551 qla82xx_write_status_reg(ha, val); 2552 } 2553 2554 if (qla82xx_write_disable_flash(ha) != 0) 2555 ql_log(ql_log_warn, vha, 0xb015, 2556 "Write disable failed.\n"); 2557 2558 done_unprotect: 2559 qla82xx_rom_unlock(ha); 2560 return ret; 2561 } 2562 2563 static int 2564 qla82xx_protect_flash(struct qla_hw_data *ha) 2565 { 2566 int ret; 2567 uint32_t val; 2568 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2569 2570 ret = ql82xx_rom_lock_d(ha); 2571 if (ret < 0) { 2572 ql_log(ql_log_warn, vha, 0xb016, 2573 "ROM Lock failed.\n"); 2574 return ret; 2575 } 2576 2577 ret = qla82xx_read_status_reg(ha, &val); 2578 if (ret < 0) 2579 goto done_protect; 2580 2581 val |= (BLOCK_PROTECT_BITS << 2); 2582 /* LOCK all sectors */ 2583 ret = qla82xx_write_status_reg(ha, val); 2584 if (ret < 0) 2585 ql_log(ql_log_warn, vha, 0xb017, 2586 "Write status register failed.\n"); 2587 2588 if (qla82xx_write_disable_flash(ha) != 0) 2589 ql_log(ql_log_warn, vha, 0xb018, 2590 "Write disable failed.\n"); 2591 done_protect: 2592 qla82xx_rom_unlock(ha); 2593 return ret; 2594 } 2595 2596 static int 2597 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2598 { 2599 int ret = 0; 2600 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2601 2602 ret = ql82xx_rom_lock_d(ha); 2603 if (ret < 0) { 2604 ql_log(ql_log_warn, vha, 0xb019, 2605 "ROM Lock failed.\n"); 2606 return ret; 2607 } 2608 2609 qla82xx_flash_set_write_enable(ha); 2610 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2611 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2612 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2613 2614 if (qla82xx_wait_rom_done(ha)) { 2615 ql_log(ql_log_warn, vha, 0xb01a, 2616 "Error waiting for rom done.\n"); 2617 ret = -1; 2618 goto done; 2619 } 2620 ret = qla82xx_flash_wait_write_finish(ha); 2621 done: 2622 qla82xx_rom_unlock(ha); 2623 return ret; 2624 } 2625 2626 /* 2627 * Address and length are byte address 2628 */ 2629 void * 2630 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2631 uint32_t offset, uint32_t length) 2632 { 2633 scsi_block_requests(vha->host); 2634 qla82xx_read_flash_data(vha, buf, offset, length); 2635 scsi_unblock_requests(vha->host); 2636 return buf; 2637 } 2638 2639 static int 2640 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr, 2641 uint32_t faddr, uint32_t dwords) 2642 { 2643 int ret; 2644 uint32_t liter; 2645 uint32_t rest_addr; 2646 dma_addr_t optrom_dma; 2647 void *optrom = NULL; 2648 int page_mode = 0; 2649 struct qla_hw_data *ha = vha->hw; 2650 2651 ret = -1; 2652 2653 /* Prepare burst-capable write on supported ISPs. */ 2654 if (page_mode && !(faddr & 0xfff) && 2655 dwords > OPTROM_BURST_DWORDS) { 2656 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2657 &optrom_dma, GFP_KERNEL); 2658 if (!optrom) { 2659 ql_log(ql_log_warn, vha, 0xb01b, 2660 "Unable to allocate memory " 2661 "for optrom burst write (%x KB).\n", 2662 OPTROM_BURST_SIZE / 1024); 2663 } 2664 } 2665 2666 rest_addr = ha->fdt_block_size - 1; 2667 2668 ret = qla82xx_unprotect_flash(ha); 2669 if (ret) { 2670 ql_log(ql_log_warn, vha, 0xb01c, 2671 "Unable to unprotect flash for update.\n"); 2672 goto write_done; 2673 } 2674 2675 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2676 /* Are we at the beginning of a sector? */ 2677 if ((faddr & rest_addr) == 0) { 2678 2679 ret = qla82xx_erase_sector(ha, faddr); 2680 if (ret) { 2681 ql_log(ql_log_warn, vha, 0xb01d, 2682 "Unable to erase sector: address=%x.\n", 2683 faddr); 2684 break; 2685 } 2686 } 2687 2688 /* Go with burst-write. */ 2689 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2690 /* Copy data to DMA'ble buffer. */ 2691 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2692 2693 ret = qla2x00_load_ram(vha, optrom_dma, 2694 (ha->flash_data_off | faddr), 2695 OPTROM_BURST_DWORDS); 2696 if (ret != QLA_SUCCESS) { 2697 ql_log(ql_log_warn, vha, 0xb01e, 2698 "Unable to burst-write optrom segment " 2699 "(%x/%x/%llx).\n", ret, 2700 (ha->flash_data_off | faddr), 2701 (unsigned long long)optrom_dma); 2702 ql_log(ql_log_warn, vha, 0xb01f, 2703 "Reverting to slow-write.\n"); 2704 2705 dma_free_coherent(&ha->pdev->dev, 2706 OPTROM_BURST_SIZE, optrom, optrom_dma); 2707 optrom = NULL; 2708 } else { 2709 liter += OPTROM_BURST_DWORDS - 1; 2710 faddr += OPTROM_BURST_DWORDS - 1; 2711 dwptr += OPTROM_BURST_DWORDS - 1; 2712 continue; 2713 } 2714 } 2715 2716 ret = qla82xx_write_flash_dword(ha, faddr, 2717 le32_to_cpu(*dwptr)); 2718 if (ret) { 2719 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2720 "Unable to program flash address=%x data=%x.\n", 2721 faddr, *dwptr); 2722 break; 2723 } 2724 } 2725 2726 ret = qla82xx_protect_flash(ha); 2727 if (ret) 2728 ql_log(ql_log_warn, vha, 0xb021, 2729 "Unable to protect flash after update.\n"); 2730 write_done: 2731 if (optrom) 2732 dma_free_coherent(&ha->pdev->dev, 2733 OPTROM_BURST_SIZE, optrom, optrom_dma); 2734 return ret; 2735 } 2736 2737 int 2738 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2739 uint32_t offset, uint32_t length) 2740 { 2741 int rval; 2742 2743 /* Suspend HBA. */ 2744 scsi_block_requests(vha->host); 2745 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2746 scsi_unblock_requests(vha->host); 2747 2748 /* Convert return ISP82xx to generic */ 2749 if (rval) 2750 rval = QLA_FUNCTION_FAILED; 2751 else 2752 rval = QLA_SUCCESS; 2753 return rval; 2754 } 2755 2756 void 2757 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2758 { 2759 struct qla_hw_data *ha = vha->hw; 2760 struct req_que *req = ha->req_q_map[0]; 2761 uint32_t dbval; 2762 2763 /* Adjust ring index. */ 2764 req->ring_index++; 2765 if (req->ring_index == req->length) { 2766 req->ring_index = 0; 2767 req->ring_ptr = req->ring; 2768 } else 2769 req->ring_ptr++; 2770 2771 dbval = 0x04 | (ha->portnum << 5); 2772 2773 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2774 if (ql2xdbwr) 2775 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2776 else { 2777 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2778 wmb(); 2779 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { 2780 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2781 wmb(); 2782 } 2783 } 2784 } 2785 2786 static void 2787 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2788 { 2789 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2790 uint32_t lock_owner = 0; 2791 2792 if (qla82xx_rom_lock(ha)) { 2793 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2794 /* Someone else is holding the lock. */ 2795 ql_log(ql_log_info, vha, 0xb022, 2796 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2797 } 2798 /* 2799 * Either we got the lock, or someone 2800 * else died while holding it. 2801 * In either case, unlock. 2802 */ 2803 qla82xx_rom_unlock(ha); 2804 } 2805 2806 /* 2807 * qla82xx_device_bootstrap 2808 * Initialize device, set DEV_READY, start fw 2809 * 2810 * Note: 2811 * IDC lock must be held upon entry 2812 * 2813 * Return: 2814 * Success : 0 2815 * Failed : 1 2816 */ 2817 static int 2818 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2819 { 2820 int rval = QLA_SUCCESS; 2821 int i; 2822 uint32_t old_count, count; 2823 struct qla_hw_data *ha = vha->hw; 2824 int need_reset = 0; 2825 2826 need_reset = qla82xx_need_reset(ha); 2827 2828 if (need_reset) { 2829 /* We are trying to perform a recovery here. */ 2830 if (ha->flags.isp82xx_fw_hung) 2831 qla82xx_rom_lock_recovery(ha); 2832 } else { 2833 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2834 for (i = 0; i < 10; i++) { 2835 msleep(200); 2836 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2837 if (count != old_count) { 2838 rval = QLA_SUCCESS; 2839 goto dev_ready; 2840 } 2841 } 2842 qla82xx_rom_lock_recovery(ha); 2843 } 2844 2845 /* set to DEV_INITIALIZING */ 2846 ql_log(ql_log_info, vha, 0x009e, 2847 "HW State: INITIALIZING.\n"); 2848 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2849 2850 qla82xx_idc_unlock(ha); 2851 rval = qla82xx_start_firmware(vha); 2852 qla82xx_idc_lock(ha); 2853 2854 if (rval != QLA_SUCCESS) { 2855 ql_log(ql_log_fatal, vha, 0x00ad, 2856 "HW State: FAILED.\n"); 2857 qla82xx_clear_drv_active(ha); 2858 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2859 return rval; 2860 } 2861 2862 dev_ready: 2863 ql_log(ql_log_info, vha, 0x00ae, 2864 "HW State: READY.\n"); 2865 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2866 2867 return QLA_SUCCESS; 2868 } 2869 2870 /* 2871 * qla82xx_need_qsnt_handler 2872 * Code to start quiescence sequence 2873 * 2874 * Note: 2875 * IDC lock must be held upon entry 2876 * 2877 * Return: void 2878 */ 2879 2880 static void 2881 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2882 { 2883 struct qla_hw_data *ha = vha->hw; 2884 uint32_t dev_state, drv_state, drv_active; 2885 unsigned long reset_timeout; 2886 2887 if (vha->flags.online) { 2888 /*Block any further I/O and wait for pending cmnds to complete*/ 2889 qla2x00_quiesce_io(vha); 2890 } 2891 2892 /* Set the quiescence ready bit */ 2893 qla82xx_set_qsnt_ready(ha); 2894 2895 /*wait for 30 secs for other functions to ack */ 2896 reset_timeout = jiffies + (30 * HZ); 2897 2898 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2899 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2900 /* Its 2 that is written when qsnt is acked, moving one bit */ 2901 drv_active = drv_active << 0x01; 2902 2903 while (drv_state != drv_active) { 2904 2905 if (time_after_eq(jiffies, reset_timeout)) { 2906 /* quiescence timeout, other functions didn't ack 2907 * changing the state to DEV_READY 2908 */ 2909 ql_log(ql_log_info, vha, 0xb023, 2910 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2911 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2912 drv_active, drv_state); 2913 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2914 QLA8XXX_DEV_READY); 2915 ql_log(ql_log_info, vha, 0xb025, 2916 "HW State: DEV_READY.\n"); 2917 qla82xx_idc_unlock(ha); 2918 qla2x00_perform_loop_resync(vha); 2919 qla82xx_idc_lock(ha); 2920 2921 qla82xx_clear_qsnt_ready(vha); 2922 return; 2923 } 2924 2925 qla82xx_idc_unlock(ha); 2926 msleep(1000); 2927 qla82xx_idc_lock(ha); 2928 2929 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2930 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2931 drv_active = drv_active << 0x01; 2932 } 2933 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2934 /* everyone acked so set the state to DEV_QUIESCENCE */ 2935 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2936 ql_log(ql_log_info, vha, 0xb026, 2937 "HW State: DEV_QUIESCENT.\n"); 2938 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2939 } 2940 } 2941 2942 /* 2943 * qla82xx_wait_for_state_change 2944 * Wait for device state to change from given current state 2945 * 2946 * Note: 2947 * IDC lock must not be held upon entry 2948 * 2949 * Return: 2950 * Changed device state. 2951 */ 2952 uint32_t 2953 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2954 { 2955 struct qla_hw_data *ha = vha->hw; 2956 uint32_t dev_state; 2957 2958 do { 2959 msleep(1000); 2960 qla82xx_idc_lock(ha); 2961 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2962 qla82xx_idc_unlock(ha); 2963 } while (dev_state == curr_state); 2964 2965 return dev_state; 2966 } 2967 2968 void 2969 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2970 { 2971 struct qla_hw_data *ha = vha->hw; 2972 2973 /* Disable the board */ 2974 ql_log(ql_log_fatal, vha, 0x00b8, 2975 "Disabling the board.\n"); 2976 2977 if (IS_QLA82XX(ha)) { 2978 qla82xx_clear_drv_active(ha); 2979 qla82xx_idc_unlock(ha); 2980 } else if (IS_QLA8044(ha)) { 2981 qla8044_clear_drv_active(ha); 2982 qla8044_idc_unlock(ha); 2983 } 2984 2985 /* Set DEV_FAILED flag to disable timer */ 2986 vha->device_flags |= DFLG_DEV_FAILED; 2987 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2988 qla2x00_mark_all_devices_lost(vha); 2989 vha->flags.online = 0; 2990 vha->flags.init_done = 0; 2991 } 2992 2993 /* 2994 * qla82xx_need_reset_handler 2995 * Code to start reset sequence 2996 * 2997 * Note: 2998 * IDC lock must be held upon entry 2999 * 3000 * Return: 3001 * Success : 0 3002 * Failed : 1 3003 */ 3004 static void 3005 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3006 { 3007 uint32_t dev_state, drv_state, drv_active; 3008 uint32_t active_mask = 0; 3009 unsigned long reset_timeout; 3010 struct qla_hw_data *ha = vha->hw; 3011 struct req_que *req = ha->req_q_map[0]; 3012 3013 if (vha->flags.online) { 3014 qla82xx_idc_unlock(ha); 3015 qla2x00_abort_isp_cleanup(vha); 3016 ha->isp_ops->get_flash_version(vha, req->ring); 3017 ha->isp_ops->nvram_config(vha); 3018 qla82xx_idc_lock(ha); 3019 } 3020 3021 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3022 if (!ha->flags.nic_core_reset_owner) { 3023 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3024 "reset_acknowledged by 0x%x\n", ha->portnum); 3025 qla82xx_set_rst_ready(ha); 3026 } else { 3027 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3028 drv_active &= active_mask; 3029 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3030 "active_mask: 0x%08x\n", active_mask); 3031 } 3032 3033 /* wait for 10 seconds for reset ack from all functions */ 3034 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3035 3036 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3037 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3038 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3039 3040 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3041 "drv_state: 0x%08x, drv_active: 0x%08x, " 3042 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3043 drv_state, drv_active, dev_state, active_mask); 3044 3045 while (drv_state != drv_active && 3046 dev_state != QLA8XXX_DEV_INITIALIZING) { 3047 if (time_after_eq(jiffies, reset_timeout)) { 3048 ql_log(ql_log_warn, vha, 0x00b5, 3049 "Reset timeout.\n"); 3050 break; 3051 } 3052 qla82xx_idc_unlock(ha); 3053 msleep(1000); 3054 qla82xx_idc_lock(ha); 3055 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3056 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3057 if (ha->flags.nic_core_reset_owner) 3058 drv_active &= active_mask; 3059 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3060 } 3061 3062 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3063 "drv_state: 0x%08x, drv_active: 0x%08x, " 3064 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3065 drv_state, drv_active, dev_state, active_mask); 3066 3067 ql_log(ql_log_info, vha, 0x00b6, 3068 "Device state is 0x%x = %s.\n", 3069 dev_state, 3070 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3071 3072 /* Force to DEV_COLD unless someone else is starting a reset */ 3073 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3074 dev_state != QLA8XXX_DEV_COLD) { 3075 ql_log(ql_log_info, vha, 0x00b7, 3076 "HW State: COLD/RE-INIT.\n"); 3077 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3078 qla82xx_set_rst_ready(ha); 3079 if (ql2xmdenable) { 3080 if (qla82xx_md_collect(vha)) 3081 ql_log(ql_log_warn, vha, 0xb02c, 3082 "Minidump not collected.\n"); 3083 } else 3084 ql_log(ql_log_warn, vha, 0xb04f, 3085 "Minidump disabled.\n"); 3086 } 3087 } 3088 3089 int 3090 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3091 { 3092 struct qla_hw_data *ha = vha->hw; 3093 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3094 int rval = QLA_SUCCESS; 3095 3096 fw_major_version = ha->fw_major_version; 3097 fw_minor_version = ha->fw_minor_version; 3098 fw_subminor_version = ha->fw_subminor_version; 3099 3100 rval = qla2x00_get_fw_version(vha); 3101 if (rval != QLA_SUCCESS) 3102 return rval; 3103 3104 if (ql2xmdenable) { 3105 if (!ha->fw_dumped) { 3106 if ((fw_major_version != ha->fw_major_version || 3107 fw_minor_version != ha->fw_minor_version || 3108 fw_subminor_version != ha->fw_subminor_version) || 3109 (ha->prev_minidump_failed)) { 3110 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3111 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3112 fw_major_version, fw_minor_version, 3113 fw_subminor_version, 3114 ha->fw_major_version, 3115 ha->fw_minor_version, 3116 ha->fw_subminor_version, 3117 ha->prev_minidump_failed); 3118 /* Release MiniDump resources */ 3119 qla82xx_md_free(vha); 3120 /* ALlocate MiniDump resources */ 3121 qla82xx_md_prep(vha); 3122 } 3123 } else 3124 ql_log(ql_log_info, vha, 0xb02e, 3125 "Firmware dump available to retrieve\n"); 3126 } 3127 return rval; 3128 } 3129 3130 3131 static int 3132 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3133 { 3134 uint32_t fw_heartbeat_counter; 3135 int status = 0; 3136 3137 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3138 QLA82XX_PEG_ALIVE_COUNTER); 3139 /* all 0xff, assume AER/EEH in progress, ignore */ 3140 if (fw_heartbeat_counter == 0xffffffff) { 3141 ql_dbg(ql_dbg_timer, vha, 0x6003, 3142 "FW heartbeat counter is 0xffffffff, " 3143 "returning status=%d.\n", status); 3144 return status; 3145 } 3146 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3147 vha->seconds_since_last_heartbeat++; 3148 /* FW not alive after 2 seconds */ 3149 if (vha->seconds_since_last_heartbeat == 2) { 3150 vha->seconds_since_last_heartbeat = 0; 3151 status = 1; 3152 } 3153 } else 3154 vha->seconds_since_last_heartbeat = 0; 3155 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3156 if (status) 3157 ql_dbg(ql_dbg_timer, vha, 0x6004, 3158 "Returning status=%d.\n", status); 3159 return status; 3160 } 3161 3162 /* 3163 * qla82xx_device_state_handler 3164 * Main state handler 3165 * 3166 * Note: 3167 * IDC lock must be held upon entry 3168 * 3169 * Return: 3170 * Success : 0 3171 * Failed : 1 3172 */ 3173 int 3174 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3175 { 3176 uint32_t dev_state; 3177 uint32_t old_dev_state; 3178 int rval = QLA_SUCCESS; 3179 unsigned long dev_init_timeout; 3180 struct qla_hw_data *ha = vha->hw; 3181 int loopcount = 0; 3182 3183 qla82xx_idc_lock(ha); 3184 if (!vha->flags.init_done) { 3185 qla82xx_set_drv_active(vha); 3186 qla82xx_set_idc_version(vha); 3187 } 3188 3189 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3190 old_dev_state = dev_state; 3191 ql_log(ql_log_info, vha, 0x009b, 3192 "Device state is 0x%x = %s.\n", 3193 dev_state, 3194 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3195 3196 /* wait for 30 seconds for device to go ready */ 3197 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3198 3199 while (1) { 3200 3201 if (time_after_eq(jiffies, dev_init_timeout)) { 3202 ql_log(ql_log_fatal, vha, 0x009c, 3203 "Device init failed.\n"); 3204 rval = QLA_FUNCTION_FAILED; 3205 break; 3206 } 3207 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3208 if (old_dev_state != dev_state) { 3209 loopcount = 0; 3210 old_dev_state = dev_state; 3211 } 3212 if (loopcount < 5) { 3213 ql_log(ql_log_info, vha, 0x009d, 3214 "Device state is 0x%x = %s.\n", 3215 dev_state, 3216 dev_state < MAX_STATES ? qdev_state(dev_state) : 3217 "Unknown"); 3218 } 3219 3220 switch (dev_state) { 3221 case QLA8XXX_DEV_READY: 3222 ha->flags.nic_core_reset_owner = 0; 3223 goto rel_lock; 3224 case QLA8XXX_DEV_COLD: 3225 rval = qla82xx_device_bootstrap(vha); 3226 break; 3227 case QLA8XXX_DEV_INITIALIZING: 3228 qla82xx_idc_unlock(ha); 3229 msleep(1000); 3230 qla82xx_idc_lock(ha); 3231 break; 3232 case QLA8XXX_DEV_NEED_RESET: 3233 if (!ql2xdontresethba) 3234 qla82xx_need_reset_handler(vha); 3235 else { 3236 qla82xx_idc_unlock(ha); 3237 msleep(1000); 3238 qla82xx_idc_lock(ha); 3239 } 3240 dev_init_timeout = jiffies + 3241 (ha->fcoe_dev_init_timeout * HZ); 3242 break; 3243 case QLA8XXX_DEV_NEED_QUIESCENT: 3244 qla82xx_need_qsnt_handler(vha); 3245 /* Reset timeout value after quiescence handler */ 3246 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3247 * HZ); 3248 break; 3249 case QLA8XXX_DEV_QUIESCENT: 3250 /* Owner will exit and other will wait for the state 3251 * to get changed 3252 */ 3253 if (ha->flags.quiesce_owner) 3254 goto rel_lock; 3255 3256 qla82xx_idc_unlock(ha); 3257 msleep(1000); 3258 qla82xx_idc_lock(ha); 3259 3260 /* Reset timeout value after quiescence handler */ 3261 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3262 * HZ); 3263 break; 3264 case QLA8XXX_DEV_FAILED: 3265 qla8xxx_dev_failed_handler(vha); 3266 rval = QLA_FUNCTION_FAILED; 3267 goto exit; 3268 default: 3269 qla82xx_idc_unlock(ha); 3270 msleep(1000); 3271 qla82xx_idc_lock(ha); 3272 } 3273 loopcount++; 3274 } 3275 rel_lock: 3276 qla82xx_idc_unlock(ha); 3277 exit: 3278 return rval; 3279 } 3280 3281 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3282 { 3283 uint32_t temp, temp_state, temp_val; 3284 struct qla_hw_data *ha = vha->hw; 3285 3286 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3287 temp_state = qla82xx_get_temp_state(temp); 3288 temp_val = qla82xx_get_temp_val(temp); 3289 3290 if (temp_state == QLA82XX_TEMP_PANIC) { 3291 ql_log(ql_log_warn, vha, 0x600e, 3292 "Device temperature %d degrees C exceeds " 3293 " maximum allowed. Hardware has been shut down.\n", 3294 temp_val); 3295 return 1; 3296 } else if (temp_state == QLA82XX_TEMP_WARN) { 3297 ql_log(ql_log_warn, vha, 0x600f, 3298 "Device temperature %d degrees C exceeds " 3299 "operating range. Immediate action needed.\n", 3300 temp_val); 3301 } 3302 return 0; 3303 } 3304 3305 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3306 { 3307 uint32_t temp; 3308 3309 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3310 return qla82xx_get_temp_val(temp); 3311 } 3312 3313 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3314 { 3315 struct qla_hw_data *ha = vha->hw; 3316 3317 if (ha->flags.mbox_busy) { 3318 ha->flags.mbox_int = 1; 3319 ha->flags.mbox_busy = 0; 3320 ql_log(ql_log_warn, vha, 0x6010, 3321 "Doing premature completion of mbx command.\n"); 3322 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3323 complete(&ha->mbx_intr_comp); 3324 } 3325 } 3326 3327 void qla82xx_watchdog(scsi_qla_host_t *vha) 3328 { 3329 uint32_t dev_state, halt_status; 3330 struct qla_hw_data *ha = vha->hw; 3331 3332 /* don't poll if reset is going on */ 3333 if (!ha->flags.nic_core_reset_hdlr_active) { 3334 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3335 if (qla82xx_check_temp(vha)) { 3336 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3337 ha->flags.isp82xx_fw_hung = 1; 3338 qla82xx_clear_pending_mbx(vha); 3339 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3340 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3341 ql_log(ql_log_warn, vha, 0x6001, 3342 "Adapter reset needed.\n"); 3343 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3344 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3345 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3346 ql_log(ql_log_warn, vha, 0x6002, 3347 "Quiescent needed.\n"); 3348 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3349 } else if (dev_state == QLA8XXX_DEV_FAILED && 3350 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3351 vha->flags.online == 1) { 3352 ql_log(ql_log_warn, vha, 0xb055, 3353 "Adapter state is failed. Offlining.\n"); 3354 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3355 ha->flags.isp82xx_fw_hung = 1; 3356 qla82xx_clear_pending_mbx(vha); 3357 } else { 3358 if (qla82xx_check_fw_alive(vha)) { 3359 ql_dbg(ql_dbg_timer, vha, 0x6011, 3360 "disabling pause transmit on port 0 & 1.\n"); 3361 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3362 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3363 halt_status = qla82xx_rd_32(ha, 3364 QLA82XX_PEG_HALT_STATUS1); 3365 ql_log(ql_log_info, vha, 0x6005, 3366 "dumping hw/fw registers:.\n " 3367 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3368 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3369 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3370 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3371 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3372 qla82xx_rd_32(ha, 3373 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3374 qla82xx_rd_32(ha, 3375 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3376 qla82xx_rd_32(ha, 3377 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3378 qla82xx_rd_32(ha, 3379 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3380 qla82xx_rd_32(ha, 3381 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3382 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3383 ql_log(ql_log_warn, vha, 0xb052, 3384 "Firmware aborted with " 3385 "error code 0x00006700. Device is " 3386 "being reset.\n"); 3387 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3388 set_bit(ISP_UNRECOVERABLE, 3389 &vha->dpc_flags); 3390 } else { 3391 ql_log(ql_log_info, vha, 0x6006, 3392 "Detect abort needed.\n"); 3393 set_bit(ISP_ABORT_NEEDED, 3394 &vha->dpc_flags); 3395 } 3396 ha->flags.isp82xx_fw_hung = 1; 3397 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3398 qla82xx_clear_pending_mbx(vha); 3399 } 3400 } 3401 } 3402 } 3403 3404 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3405 { 3406 int rval = -1; 3407 struct qla_hw_data *ha = vha->hw; 3408 3409 if (IS_QLA82XX(ha)) 3410 rval = qla82xx_device_state_handler(vha); 3411 else if (IS_QLA8044(ha)) { 3412 qla8044_idc_lock(ha); 3413 /* Decide the reset ownership */ 3414 qla83xx_reset_ownership(vha); 3415 qla8044_idc_unlock(ha); 3416 rval = qla8044_device_state_handler(vha); 3417 } 3418 return rval; 3419 } 3420 3421 void 3422 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3423 { 3424 struct qla_hw_data *ha = vha->hw; 3425 uint32_t dev_state = 0; 3426 3427 if (IS_QLA82XX(ha)) 3428 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3429 else if (IS_QLA8044(ha)) 3430 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3431 3432 if (dev_state == QLA8XXX_DEV_READY) { 3433 ql_log(ql_log_info, vha, 0xb02f, 3434 "HW State: NEED RESET\n"); 3435 if (IS_QLA82XX(ha)) { 3436 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3437 QLA8XXX_DEV_NEED_RESET); 3438 ha->flags.nic_core_reset_owner = 1; 3439 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3440 "reset_owner is 0x%x\n", ha->portnum); 3441 } else if (IS_QLA8044(ha)) 3442 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3443 QLA8XXX_DEV_NEED_RESET); 3444 } else 3445 ql_log(ql_log_info, vha, 0xb031, 3446 "Device state is 0x%x = %s.\n", 3447 dev_state, 3448 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3449 } 3450 3451 /* 3452 * qla82xx_abort_isp 3453 * Resets ISP and aborts all outstanding commands. 3454 * 3455 * Input: 3456 * ha = adapter block pointer. 3457 * 3458 * Returns: 3459 * 0 = success 3460 */ 3461 int 3462 qla82xx_abort_isp(scsi_qla_host_t *vha) 3463 { 3464 int rval = -1; 3465 struct qla_hw_data *ha = vha->hw; 3466 3467 if (vha->device_flags & DFLG_DEV_FAILED) { 3468 ql_log(ql_log_warn, vha, 0x8024, 3469 "Device in failed state, exiting.\n"); 3470 return QLA_SUCCESS; 3471 } 3472 ha->flags.nic_core_reset_hdlr_active = 1; 3473 3474 qla82xx_idc_lock(ha); 3475 qla82xx_set_reset_owner(vha); 3476 qla82xx_idc_unlock(ha); 3477 3478 if (IS_QLA82XX(ha)) 3479 rval = qla82xx_device_state_handler(vha); 3480 else if (IS_QLA8044(ha)) { 3481 qla8044_idc_lock(ha); 3482 /* Decide the reset ownership */ 3483 qla83xx_reset_ownership(vha); 3484 qla8044_idc_unlock(ha); 3485 rval = qla8044_device_state_handler(vha); 3486 } 3487 3488 qla82xx_idc_lock(ha); 3489 qla82xx_clear_rst_ready(ha); 3490 qla82xx_idc_unlock(ha); 3491 3492 if (rval == QLA_SUCCESS) { 3493 ha->flags.isp82xx_fw_hung = 0; 3494 ha->flags.nic_core_reset_hdlr_active = 0; 3495 qla82xx_restart_isp(vha); 3496 } 3497 3498 if (rval) { 3499 vha->flags.online = 1; 3500 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3501 if (ha->isp_abort_cnt == 0) { 3502 ql_log(ql_log_warn, vha, 0x8027, 3503 "ISP error recover failed - board " 3504 "disabled.\n"); 3505 /* 3506 * The next call disables the board 3507 * completely. 3508 */ 3509 ha->isp_ops->reset_adapter(vha); 3510 vha->flags.online = 0; 3511 clear_bit(ISP_ABORT_RETRY, 3512 &vha->dpc_flags); 3513 rval = QLA_SUCCESS; 3514 } else { /* schedule another ISP abort */ 3515 ha->isp_abort_cnt--; 3516 ql_log(ql_log_warn, vha, 0x8036, 3517 "ISP abort - retry remaining %d.\n", 3518 ha->isp_abort_cnt); 3519 rval = QLA_FUNCTION_FAILED; 3520 } 3521 } else { 3522 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3523 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3524 "ISP error recovery - retrying (%d) more times.\n", 3525 ha->isp_abort_cnt); 3526 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3527 rval = QLA_FUNCTION_FAILED; 3528 } 3529 } 3530 return rval; 3531 } 3532 3533 /* 3534 * qla82xx_fcoe_ctx_reset 3535 * Perform a quick reset and aborts all outstanding commands. 3536 * This will only perform an FCoE context reset and avoids a full blown 3537 * chip reset. 3538 * 3539 * Input: 3540 * ha = adapter block pointer. 3541 * is_reset_path = flag for identifying the reset path. 3542 * 3543 * Returns: 3544 * 0 = success 3545 */ 3546 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3547 { 3548 int rval = QLA_FUNCTION_FAILED; 3549 3550 if (vha->flags.online) { 3551 /* Abort all outstanding commands, so as to be requeued later */ 3552 qla2x00_abort_isp_cleanup(vha); 3553 } 3554 3555 /* Stop currently executing firmware. 3556 * This will destroy existing FCoE context at the F/W end. 3557 */ 3558 qla2x00_try_to_stop_firmware(vha); 3559 3560 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3561 rval = qla82xx_restart_isp(vha); 3562 3563 return rval; 3564 } 3565 3566 /* 3567 * qla2x00_wait_for_fcoe_ctx_reset 3568 * Wait till the FCoE context is reset. 3569 * 3570 * Note: 3571 * Does context switching here. 3572 * Release SPIN_LOCK (if any) before calling this routine. 3573 * 3574 * Return: 3575 * Success (fcoe_ctx reset is done) : 0 3576 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3577 */ 3578 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3579 { 3580 int status = QLA_FUNCTION_FAILED; 3581 unsigned long wait_reset; 3582 3583 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3584 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3585 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3586 && time_before(jiffies, wait_reset)) { 3587 3588 set_current_state(TASK_UNINTERRUPTIBLE); 3589 schedule_timeout(HZ); 3590 3591 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3592 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3593 status = QLA_SUCCESS; 3594 break; 3595 } 3596 } 3597 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3598 "%s: status=%d.\n", __func__, status); 3599 3600 return status; 3601 } 3602 3603 void 3604 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3605 { 3606 int i, fw_state = 0; 3607 unsigned long flags; 3608 struct qla_hw_data *ha = vha->hw; 3609 3610 /* Check if 82XX firmware is alive or not 3611 * We may have arrived here from NEED_RESET 3612 * detection only 3613 */ 3614 if (!ha->flags.isp82xx_fw_hung) { 3615 for (i = 0; i < 2; i++) { 3616 msleep(1000); 3617 if (IS_QLA82XX(ha)) 3618 fw_state = qla82xx_check_fw_alive(vha); 3619 else if (IS_QLA8044(ha)) 3620 fw_state = qla8044_check_fw_alive(vha); 3621 if (fw_state) { 3622 ha->flags.isp82xx_fw_hung = 1; 3623 qla82xx_clear_pending_mbx(vha); 3624 break; 3625 } 3626 } 3627 } 3628 ql_dbg(ql_dbg_init, vha, 0x00b0, 3629 "Entered %s fw_hung=%d.\n", 3630 __func__, ha->flags.isp82xx_fw_hung); 3631 3632 /* Abort all commands gracefully if fw NOT hung */ 3633 if (!ha->flags.isp82xx_fw_hung) { 3634 int cnt, que; 3635 srb_t *sp; 3636 struct req_que *req; 3637 3638 spin_lock_irqsave(&ha->hardware_lock, flags); 3639 for (que = 0; que < ha->max_req_queues; que++) { 3640 req = ha->req_q_map[que]; 3641 if (!req) 3642 continue; 3643 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3644 sp = req->outstanding_cmds[cnt]; 3645 if (sp) { 3646 if ((!sp->u.scmd.crc_ctx || 3647 (sp->flags & 3648 SRB_FCP_CMND_DMA_VALID)) && 3649 !ha->flags.isp82xx_fw_hung) { 3650 spin_unlock_irqrestore( 3651 &ha->hardware_lock, flags); 3652 if (ha->isp_ops->abort_command(sp)) { 3653 ql_log(ql_log_info, vha, 3654 0x00b1, 3655 "mbx abort failed.\n"); 3656 } else { 3657 ql_log(ql_log_info, vha, 3658 0x00b2, 3659 "mbx abort success.\n"); 3660 } 3661 spin_lock_irqsave(&ha->hardware_lock, flags); 3662 } 3663 } 3664 } 3665 } 3666 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3667 3668 /* Wait for pending cmds (physical and virtual) to complete */ 3669 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3670 WAIT_HOST) == QLA_SUCCESS) { 3671 ql_dbg(ql_dbg_init, vha, 0x00b3, 3672 "Done wait for " 3673 "pending commands.\n"); 3674 } else { 3675 WARN_ON_ONCE(true); 3676 } 3677 } 3678 } 3679 3680 /* Minidump related functions */ 3681 static int 3682 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3683 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3684 { 3685 struct qla_hw_data *ha = vha->hw; 3686 struct qla82xx_md_entry_crb *crb_entry; 3687 uint32_t read_value, opcode, poll_time; 3688 uint32_t addr, index, crb_addr; 3689 unsigned long wtime; 3690 struct qla82xx_md_template_hdr *tmplt_hdr; 3691 uint32_t rval = QLA_SUCCESS; 3692 int i; 3693 3694 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3695 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3696 crb_addr = crb_entry->addr; 3697 3698 for (i = 0; i < crb_entry->op_count; i++) { 3699 opcode = crb_entry->crb_ctrl.opcode; 3700 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3701 qla82xx_md_rw_32(ha, crb_addr, 3702 crb_entry->value_1, 1); 3703 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3704 } 3705 3706 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3707 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3708 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3709 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3710 } 3711 3712 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3713 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3714 read_value &= crb_entry->value_2; 3715 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3716 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3717 read_value |= crb_entry->value_3; 3718 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3719 } 3720 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3721 } 3722 3723 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3724 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3725 read_value |= crb_entry->value_3; 3726 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3727 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3728 } 3729 3730 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3731 poll_time = crb_entry->crb_strd.poll_timeout; 3732 wtime = jiffies + poll_time; 3733 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3734 3735 do { 3736 if ((read_value & crb_entry->value_2) 3737 == crb_entry->value_1) 3738 break; 3739 else if (time_after_eq(jiffies, wtime)) { 3740 /* capturing dump failed */ 3741 rval = QLA_FUNCTION_FAILED; 3742 break; 3743 } else 3744 read_value = qla82xx_md_rw_32(ha, 3745 crb_addr, 0, 0); 3746 } while (1); 3747 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3748 } 3749 3750 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3751 if (crb_entry->crb_strd.state_index_a) { 3752 index = crb_entry->crb_strd.state_index_a; 3753 addr = tmplt_hdr->saved_state_array[index]; 3754 } else 3755 addr = crb_addr; 3756 3757 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3758 index = crb_entry->crb_ctrl.state_index_v; 3759 tmplt_hdr->saved_state_array[index] = read_value; 3760 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3761 } 3762 3763 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3764 if (crb_entry->crb_strd.state_index_a) { 3765 index = crb_entry->crb_strd.state_index_a; 3766 addr = tmplt_hdr->saved_state_array[index]; 3767 } else 3768 addr = crb_addr; 3769 3770 if (crb_entry->crb_ctrl.state_index_v) { 3771 index = crb_entry->crb_ctrl.state_index_v; 3772 read_value = 3773 tmplt_hdr->saved_state_array[index]; 3774 } else 3775 read_value = crb_entry->value_1; 3776 3777 qla82xx_md_rw_32(ha, addr, read_value, 1); 3778 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3779 } 3780 3781 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3782 index = crb_entry->crb_ctrl.state_index_v; 3783 read_value = tmplt_hdr->saved_state_array[index]; 3784 read_value <<= crb_entry->crb_ctrl.shl; 3785 read_value >>= crb_entry->crb_ctrl.shr; 3786 if (crb_entry->value_2) 3787 read_value &= crb_entry->value_2; 3788 read_value |= crb_entry->value_3; 3789 read_value += crb_entry->value_1; 3790 tmplt_hdr->saved_state_array[index] = read_value; 3791 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3792 } 3793 crb_addr += crb_entry->crb_strd.addr_stride; 3794 } 3795 return rval; 3796 } 3797 3798 static void 3799 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3800 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3801 { 3802 struct qla_hw_data *ha = vha->hw; 3803 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3804 struct qla82xx_md_entry_rdocm *ocm_hdr; 3805 __le32 *data_ptr = *d_ptr; 3806 3807 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3808 r_addr = ocm_hdr->read_addr; 3809 r_stride = ocm_hdr->read_addr_stride; 3810 loop_cnt = ocm_hdr->op_count; 3811 3812 for (i = 0; i < loop_cnt; i++) { 3813 r_value = rd_reg_dword(r_addr + ha->nx_pcibase); 3814 *data_ptr++ = cpu_to_le32(r_value); 3815 r_addr += r_stride; 3816 } 3817 *d_ptr = data_ptr; 3818 } 3819 3820 static void 3821 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3822 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3823 { 3824 struct qla_hw_data *ha = vha->hw; 3825 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3826 struct qla82xx_md_entry_mux *mux_hdr; 3827 __le32 *data_ptr = *d_ptr; 3828 3829 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3830 r_addr = mux_hdr->read_addr; 3831 s_addr = mux_hdr->select_addr; 3832 s_stride = mux_hdr->select_value_stride; 3833 s_value = mux_hdr->select_value; 3834 loop_cnt = mux_hdr->op_count; 3835 3836 for (i = 0; i < loop_cnt; i++) { 3837 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3838 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3839 *data_ptr++ = cpu_to_le32(s_value); 3840 *data_ptr++ = cpu_to_le32(r_value); 3841 s_value += s_stride; 3842 } 3843 *d_ptr = data_ptr; 3844 } 3845 3846 static void 3847 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3848 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3849 { 3850 struct qla_hw_data *ha = vha->hw; 3851 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3852 struct qla82xx_md_entry_crb *crb_hdr; 3853 __le32 *data_ptr = *d_ptr; 3854 3855 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3856 r_addr = crb_hdr->addr; 3857 r_stride = crb_hdr->crb_strd.addr_stride; 3858 loop_cnt = crb_hdr->op_count; 3859 3860 for (i = 0; i < loop_cnt; i++) { 3861 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3862 *data_ptr++ = cpu_to_le32(r_addr); 3863 *data_ptr++ = cpu_to_le32(r_value); 3864 r_addr += r_stride; 3865 } 3866 *d_ptr = data_ptr; 3867 } 3868 3869 static int 3870 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3871 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3872 { 3873 struct qla_hw_data *ha = vha->hw; 3874 uint32_t addr, r_addr, c_addr, t_r_addr; 3875 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3876 unsigned long p_wait, w_time, p_mask; 3877 uint32_t c_value_w, c_value_r; 3878 struct qla82xx_md_entry_cache *cache_hdr; 3879 int rval = QLA_FUNCTION_FAILED; 3880 __le32 *data_ptr = *d_ptr; 3881 3882 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3883 loop_count = cache_hdr->op_count; 3884 r_addr = cache_hdr->read_addr; 3885 c_addr = cache_hdr->control_addr; 3886 c_value_w = cache_hdr->cache_ctrl.write_value; 3887 3888 t_r_addr = cache_hdr->tag_reg_addr; 3889 t_value = cache_hdr->addr_ctrl.init_tag_value; 3890 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3891 p_wait = cache_hdr->cache_ctrl.poll_wait; 3892 p_mask = cache_hdr->cache_ctrl.poll_mask; 3893 3894 for (i = 0; i < loop_count; i++) { 3895 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3896 if (c_value_w) 3897 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3898 3899 if (p_mask) { 3900 w_time = jiffies + p_wait; 3901 do { 3902 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3903 if ((c_value_r & p_mask) == 0) 3904 break; 3905 else if (time_after_eq(jiffies, w_time)) { 3906 /* capturing dump failed */ 3907 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3908 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3909 "w_time: 0x%lx\n", 3910 c_value_r, p_mask, w_time); 3911 return rval; 3912 } 3913 } while (1); 3914 } 3915 3916 addr = r_addr; 3917 for (k = 0; k < r_cnt; k++) { 3918 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3919 *data_ptr++ = cpu_to_le32(r_value); 3920 addr += cache_hdr->read_ctrl.read_addr_stride; 3921 } 3922 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3923 } 3924 *d_ptr = data_ptr; 3925 return QLA_SUCCESS; 3926 } 3927 3928 static void 3929 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3930 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3931 { 3932 struct qla_hw_data *ha = vha->hw; 3933 uint32_t addr, r_addr, c_addr, t_r_addr; 3934 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3935 uint32_t c_value_w; 3936 struct qla82xx_md_entry_cache *cache_hdr; 3937 __le32 *data_ptr = *d_ptr; 3938 3939 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3940 loop_count = cache_hdr->op_count; 3941 r_addr = cache_hdr->read_addr; 3942 c_addr = cache_hdr->control_addr; 3943 c_value_w = cache_hdr->cache_ctrl.write_value; 3944 3945 t_r_addr = cache_hdr->tag_reg_addr; 3946 t_value = cache_hdr->addr_ctrl.init_tag_value; 3947 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3948 3949 for (i = 0; i < loop_count; i++) { 3950 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3951 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3952 addr = r_addr; 3953 for (k = 0; k < r_cnt; k++) { 3954 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3955 *data_ptr++ = cpu_to_le32(r_value); 3956 addr += cache_hdr->read_ctrl.read_addr_stride; 3957 } 3958 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3959 } 3960 *d_ptr = data_ptr; 3961 } 3962 3963 static void 3964 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3965 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3966 { 3967 struct qla_hw_data *ha = vha->hw; 3968 uint32_t s_addr, r_addr; 3969 uint32_t r_stride, r_value, r_cnt, qid = 0; 3970 uint32_t i, k, loop_cnt; 3971 struct qla82xx_md_entry_queue *q_hdr; 3972 __le32 *data_ptr = *d_ptr; 3973 3974 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3975 s_addr = q_hdr->select_addr; 3976 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3977 r_stride = q_hdr->rd_strd.read_addr_stride; 3978 loop_cnt = q_hdr->op_count; 3979 3980 for (i = 0; i < loop_cnt; i++) { 3981 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3982 r_addr = q_hdr->read_addr; 3983 for (k = 0; k < r_cnt; k++) { 3984 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3985 *data_ptr++ = cpu_to_le32(r_value); 3986 r_addr += r_stride; 3987 } 3988 qid += q_hdr->q_strd.queue_id_stride; 3989 } 3990 *d_ptr = data_ptr; 3991 } 3992 3993 static void 3994 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3995 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3996 { 3997 struct qla_hw_data *ha = vha->hw; 3998 uint32_t r_addr, r_value; 3999 uint32_t i, loop_cnt; 4000 struct qla82xx_md_entry_rdrom *rom_hdr; 4001 __le32 *data_ptr = *d_ptr; 4002 4003 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4004 r_addr = rom_hdr->read_addr; 4005 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4006 4007 for (i = 0; i < loop_cnt; i++) { 4008 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4009 (r_addr & 0xFFFF0000), 1); 4010 r_value = qla82xx_md_rw_32(ha, 4011 MD_DIRECT_ROM_READ_BASE + 4012 (r_addr & 0x0000FFFF), 0, 0); 4013 *data_ptr++ = cpu_to_le32(r_value); 4014 r_addr += sizeof(uint32_t); 4015 } 4016 *d_ptr = data_ptr; 4017 } 4018 4019 static int 4020 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4021 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 4022 { 4023 struct qla_hw_data *ha = vha->hw; 4024 uint32_t r_addr, r_value, r_data; 4025 uint32_t i, j, loop_cnt; 4026 struct qla82xx_md_entry_rdmem *m_hdr; 4027 unsigned long flags; 4028 int rval = QLA_FUNCTION_FAILED; 4029 __le32 *data_ptr = *d_ptr; 4030 4031 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4032 r_addr = m_hdr->read_addr; 4033 loop_cnt = m_hdr->read_data_size/16; 4034 4035 if (r_addr & 0xf) { 4036 ql_log(ql_log_warn, vha, 0xb033, 4037 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4038 return rval; 4039 } 4040 4041 if (m_hdr->read_data_size % 16) { 4042 ql_log(ql_log_warn, vha, 0xb034, 4043 "Read data[0x%x] not multiple of 16 bytes\n", 4044 m_hdr->read_data_size); 4045 return rval; 4046 } 4047 4048 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4049 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4050 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4051 4052 write_lock_irqsave(&ha->hw_lock, flags); 4053 for (i = 0; i < loop_cnt; i++) { 4054 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4055 r_value = 0; 4056 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4057 r_value = MIU_TA_CTL_ENABLE; 4058 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4059 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4060 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4061 4062 for (j = 0; j < MAX_CTL_CHECK; j++) { 4063 r_value = qla82xx_md_rw_32(ha, 4064 MD_MIU_TEST_AGT_CTRL, 0, 0); 4065 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4066 break; 4067 } 4068 4069 if (j >= MAX_CTL_CHECK) { 4070 printk_ratelimited(KERN_ERR 4071 "failed to read through agent\n"); 4072 write_unlock_irqrestore(&ha->hw_lock, flags); 4073 return rval; 4074 } 4075 4076 for (j = 0; j < 4; j++) { 4077 r_data = qla82xx_md_rw_32(ha, 4078 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4079 *data_ptr++ = cpu_to_le32(r_data); 4080 } 4081 r_addr += 16; 4082 } 4083 write_unlock_irqrestore(&ha->hw_lock, flags); 4084 *d_ptr = data_ptr; 4085 return QLA_SUCCESS; 4086 } 4087 4088 int 4089 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4090 { 4091 struct qla_hw_data *ha = vha->hw; 4092 uint64_t chksum = 0; 4093 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4094 int count = ha->md_template_size/sizeof(uint32_t); 4095 4096 while (count-- > 0) 4097 chksum += *d_ptr++; 4098 while (chksum >> 32) 4099 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4100 return ~chksum; 4101 } 4102 4103 static void 4104 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4105 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4106 { 4107 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4108 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4109 "Skipping entry[%d]: " 4110 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4111 index, entry_hdr->entry_type, 4112 entry_hdr->d_ctrl.entry_capture_mask); 4113 } 4114 4115 int 4116 qla82xx_md_collect(scsi_qla_host_t *vha) 4117 { 4118 struct qla_hw_data *ha = vha->hw; 4119 int no_entry_hdr = 0; 4120 qla82xx_md_entry_hdr_t *entry_hdr; 4121 struct qla82xx_md_template_hdr *tmplt_hdr; 4122 __le32 *data_ptr; 4123 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4124 int i = 0, rval = QLA_FUNCTION_FAILED; 4125 4126 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4127 data_ptr = ha->md_dump; 4128 4129 if (ha->fw_dumped) { 4130 ql_log(ql_log_warn, vha, 0xb037, 4131 "Firmware has been previously dumped (%p) " 4132 "-- ignoring request.\n", ha->fw_dump); 4133 goto md_failed; 4134 } 4135 4136 ha->fw_dumped = false; 4137 4138 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4139 ql_log(ql_log_warn, vha, 0xb038, 4140 "Memory not allocated for minidump capture\n"); 4141 goto md_failed; 4142 } 4143 4144 if (ha->flags.isp82xx_no_md_cap) { 4145 ql_log(ql_log_warn, vha, 0xb054, 4146 "Forced reset from application, " 4147 "ignore minidump capture\n"); 4148 ha->flags.isp82xx_no_md_cap = 0; 4149 goto md_failed; 4150 } 4151 4152 if (qla82xx_validate_template_chksum(vha)) { 4153 ql_log(ql_log_info, vha, 0xb039, 4154 "Template checksum validation error\n"); 4155 goto md_failed; 4156 } 4157 4158 no_entry_hdr = tmplt_hdr->num_of_entries; 4159 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4160 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4161 4162 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4163 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4164 4165 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4166 4167 /* Validate whether required debug level is set */ 4168 if ((f_capture_mask & 0x3) != 0x3) { 4169 ql_log(ql_log_warn, vha, 0xb03c, 4170 "Minimum required capture mask[0x%x] level not set\n", 4171 f_capture_mask); 4172 goto md_failed; 4173 } 4174 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4175 4176 tmplt_hdr->driver_info[0] = vha->host_no; 4177 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4178 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4179 QLA_DRIVER_BETA_VER; 4180 4181 total_data_size = ha->md_dump_size; 4182 4183 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4184 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4185 4186 /* Check whether template obtained is valid */ 4187 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4188 ql_log(ql_log_warn, vha, 0xb04e, 4189 "Bad template header entry type: 0x%x obtained\n", 4190 tmplt_hdr->entry_type); 4191 goto md_failed; 4192 } 4193 4194 entry_hdr = (qla82xx_md_entry_hdr_t *) 4195 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4196 4197 /* Walk through the entry headers */ 4198 for (i = 0; i < no_entry_hdr; i++) { 4199 4200 if (data_collected > total_data_size) { 4201 ql_log(ql_log_warn, vha, 0xb03e, 4202 "More MiniDump data collected: [0x%x]\n", 4203 data_collected); 4204 goto md_failed; 4205 } 4206 4207 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4208 ql2xmdcapmask)) { 4209 entry_hdr->d_ctrl.driver_flags |= 4210 QLA82XX_DBG_SKIPPED_FLAG; 4211 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4212 "Skipping entry[%d]: " 4213 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4214 i, entry_hdr->entry_type, 4215 entry_hdr->d_ctrl.entry_capture_mask); 4216 goto skip_nxt_entry; 4217 } 4218 4219 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4220 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4221 "entry_type: 0x%x, capture_mask: 0x%x\n", 4222 __func__, i, data_ptr, entry_hdr, 4223 entry_hdr->entry_type, 4224 entry_hdr->d_ctrl.entry_capture_mask); 4225 4226 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4227 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4228 data_collected, (ha->md_dump_size - data_collected)); 4229 4230 /* Decode the entry type and take 4231 * required action to capture debug data */ 4232 switch (entry_hdr->entry_type) { 4233 case QLA82XX_RDEND: 4234 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4235 break; 4236 case QLA82XX_CNTRL: 4237 rval = qla82xx_minidump_process_control(vha, 4238 entry_hdr, &data_ptr); 4239 if (rval != QLA_SUCCESS) { 4240 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4241 goto md_failed; 4242 } 4243 break; 4244 case QLA82XX_RDCRB: 4245 qla82xx_minidump_process_rdcrb(vha, 4246 entry_hdr, &data_ptr); 4247 break; 4248 case QLA82XX_RDMEM: 4249 rval = qla82xx_minidump_process_rdmem(vha, 4250 entry_hdr, &data_ptr); 4251 if (rval != QLA_SUCCESS) { 4252 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4253 goto md_failed; 4254 } 4255 break; 4256 case QLA82XX_BOARD: 4257 case QLA82XX_RDROM: 4258 qla82xx_minidump_process_rdrom(vha, 4259 entry_hdr, &data_ptr); 4260 break; 4261 case QLA82XX_L2DTG: 4262 case QLA82XX_L2ITG: 4263 case QLA82XX_L2DAT: 4264 case QLA82XX_L2INS: 4265 rval = qla82xx_minidump_process_l2tag(vha, 4266 entry_hdr, &data_ptr); 4267 if (rval != QLA_SUCCESS) { 4268 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4269 goto md_failed; 4270 } 4271 break; 4272 case QLA82XX_L1DAT: 4273 case QLA82XX_L1INS: 4274 qla82xx_minidump_process_l1cache(vha, 4275 entry_hdr, &data_ptr); 4276 break; 4277 case QLA82XX_RDOCM: 4278 qla82xx_minidump_process_rdocm(vha, 4279 entry_hdr, &data_ptr); 4280 break; 4281 case QLA82XX_RDMUX: 4282 qla82xx_minidump_process_rdmux(vha, 4283 entry_hdr, &data_ptr); 4284 break; 4285 case QLA82XX_QUEUE: 4286 qla82xx_minidump_process_queue(vha, 4287 entry_hdr, &data_ptr); 4288 break; 4289 case QLA82XX_RDNOP: 4290 default: 4291 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4292 break; 4293 } 4294 4295 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4296 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4297 4298 data_collected = (uint8_t *)data_ptr - 4299 (uint8_t *)ha->md_dump; 4300 skip_nxt_entry: 4301 entry_hdr = (qla82xx_md_entry_hdr_t *) 4302 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4303 } 4304 4305 if (data_collected != total_data_size) { 4306 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4307 "MiniDump data mismatch: Data collected: [0x%x]," 4308 "total_data_size:[0x%x]\n", 4309 data_collected, total_data_size); 4310 goto md_failed; 4311 } 4312 4313 ql_log(ql_log_info, vha, 0xb044, 4314 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4315 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4316 ha->fw_dumped = true; 4317 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4318 4319 md_failed: 4320 return rval; 4321 } 4322 4323 int 4324 qla82xx_md_alloc(scsi_qla_host_t *vha) 4325 { 4326 struct qla_hw_data *ha = vha->hw; 4327 int i, k; 4328 struct qla82xx_md_template_hdr *tmplt_hdr; 4329 4330 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4331 4332 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4333 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4334 ql_log(ql_log_info, vha, 0xb045, 4335 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4336 ql2xmdcapmask); 4337 } 4338 4339 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4340 if (i & ql2xmdcapmask) 4341 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4342 } 4343 4344 if (ha->md_dump) { 4345 ql_log(ql_log_warn, vha, 0xb046, 4346 "Firmware dump previously allocated.\n"); 4347 return 1; 4348 } 4349 4350 ha->md_dump = vmalloc(ha->md_dump_size); 4351 if (ha->md_dump == NULL) { 4352 ql_log(ql_log_warn, vha, 0xb047, 4353 "Unable to allocate memory for Minidump size " 4354 "(0x%x).\n", ha->md_dump_size); 4355 return 1; 4356 } 4357 return 0; 4358 } 4359 4360 void 4361 qla82xx_md_free(scsi_qla_host_t *vha) 4362 { 4363 struct qla_hw_data *ha = vha->hw; 4364 4365 /* Release the template header allocated */ 4366 if (ha->md_tmplt_hdr) { 4367 ql_log(ql_log_info, vha, 0xb048, 4368 "Free MiniDump template: %p, size (%d KB)\n", 4369 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4370 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4371 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4372 ha->md_tmplt_hdr = NULL; 4373 } 4374 4375 /* Release the template data buffer allocated */ 4376 if (ha->md_dump) { 4377 ql_log(ql_log_info, vha, 0xb049, 4378 "Free MiniDump memory: %p, size (%d KB)\n", 4379 ha->md_dump, ha->md_dump_size / 1024); 4380 vfree(ha->md_dump); 4381 ha->md_dump_size = 0; 4382 ha->md_dump = NULL; 4383 } 4384 } 4385 4386 void 4387 qla82xx_md_prep(scsi_qla_host_t *vha) 4388 { 4389 struct qla_hw_data *ha = vha->hw; 4390 int rval; 4391 4392 /* Get Minidump template size */ 4393 rval = qla82xx_md_get_template_size(vha); 4394 if (rval == QLA_SUCCESS) { 4395 ql_log(ql_log_info, vha, 0xb04a, 4396 "MiniDump Template size obtained (%d KB)\n", 4397 ha->md_template_size / 1024); 4398 4399 /* Get Minidump template */ 4400 if (IS_QLA8044(ha)) 4401 rval = qla8044_md_get_template(vha); 4402 else 4403 rval = qla82xx_md_get_template(vha); 4404 4405 if (rval == QLA_SUCCESS) { 4406 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4407 "MiniDump Template obtained\n"); 4408 4409 /* Allocate memory for minidump */ 4410 rval = qla82xx_md_alloc(vha); 4411 if (rval == QLA_SUCCESS) 4412 ql_log(ql_log_info, vha, 0xb04c, 4413 "MiniDump memory allocated (%d KB)\n", 4414 ha->md_dump_size / 1024); 4415 else { 4416 ql_log(ql_log_info, vha, 0xb04d, 4417 "Free MiniDump template: %p, size: (%d KB)\n", 4418 ha->md_tmplt_hdr, 4419 ha->md_template_size / 1024); 4420 dma_free_coherent(&ha->pdev->dev, 4421 ha->md_template_size, 4422 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4423 ha->md_tmplt_hdr = NULL; 4424 } 4425 4426 } 4427 } 4428 } 4429 4430 int 4431 qla82xx_beacon_on(struct scsi_qla_host *vha) 4432 { 4433 4434 int rval; 4435 struct qla_hw_data *ha = vha->hw; 4436 4437 qla82xx_idc_lock(ha); 4438 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4439 4440 if (rval) { 4441 ql_log(ql_log_warn, vha, 0xb050, 4442 "mbx set led config failed in %s\n", __func__); 4443 goto exit; 4444 } 4445 ha->beacon_blink_led = 1; 4446 exit: 4447 qla82xx_idc_unlock(ha); 4448 return rval; 4449 } 4450 4451 int 4452 qla82xx_beacon_off(struct scsi_qla_host *vha) 4453 { 4454 4455 int rval; 4456 struct qla_hw_data *ha = vha->hw; 4457 4458 qla82xx_idc_lock(ha); 4459 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4460 4461 if (rval) { 4462 ql_log(ql_log_warn, vha, 0xb051, 4463 "mbx set led config failed in %s\n", __func__); 4464 goto exit; 4465 } 4466 ha->beacon_blink_led = 0; 4467 exit: 4468 qla82xx_idc_unlock(ha); 4469 return rval; 4470 } 4471 4472 void 4473 qla82xx_fw_dump(scsi_qla_host_t *vha) 4474 { 4475 struct qla_hw_data *ha = vha->hw; 4476 4477 if (!ha->allow_cna_fw_dump) 4478 return; 4479 4480 scsi_block_requests(vha->host); 4481 ha->flags.isp82xx_no_md_cap = 1; 4482 qla82xx_idc_lock(ha); 4483 qla82xx_set_reset_owner(vha); 4484 qla82xx_idc_unlock(ha); 4485 qla2x00_wait_for_chip_reset(vha); 4486 scsi_unblock_requests(vha->host); 4487 } 4488