1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include <linux/delay.h> 8 #include <linux/io-64-nonatomic-lo-hi.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include <linux/vmalloc.h> 12 #include <scsi/scsi_tcq.h> 13 14 #define MASK(n) ((1ULL<<(n))-1) 15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 #define BLOCK_PROTECT_BITS 0x0F 26 27 /* CRB window related */ 28 #define CRB_BLK(off) ((off >> 20) & 0x3f) 29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30 #define CRB_WINDOW_2M (0x130060) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35 #define CRB_INDIRECT_2M (0x1e0000UL) 36 37 #define MAX_CRB_XFORM 60 38 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39 static int qla82xx_crb_table_initialized; 40 41 #define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45 const int MD_MIU_TEST_AGT_RDDATA[] = { 46 0x410000A8, 0x410000AC, 47 0x410000B8, 0x410000BC 48 }; 49 50 static void qla82xx_crb_addr_transform_setup(void) 51 { 52 qla82xx_crb_addr_transform(XDMA); 53 qla82xx_crb_addr_transform(TIMR); 54 qla82xx_crb_addr_transform(SRE); 55 qla82xx_crb_addr_transform(SQN3); 56 qla82xx_crb_addr_transform(SQN2); 57 qla82xx_crb_addr_transform(SQN1); 58 qla82xx_crb_addr_transform(SQN0); 59 qla82xx_crb_addr_transform(SQS3); 60 qla82xx_crb_addr_transform(SQS2); 61 qla82xx_crb_addr_transform(SQS1); 62 qla82xx_crb_addr_transform(SQS0); 63 qla82xx_crb_addr_transform(RPMX7); 64 qla82xx_crb_addr_transform(RPMX6); 65 qla82xx_crb_addr_transform(RPMX5); 66 qla82xx_crb_addr_transform(RPMX4); 67 qla82xx_crb_addr_transform(RPMX3); 68 qla82xx_crb_addr_transform(RPMX2); 69 qla82xx_crb_addr_transform(RPMX1); 70 qla82xx_crb_addr_transform(RPMX0); 71 qla82xx_crb_addr_transform(ROMUSB); 72 qla82xx_crb_addr_transform(SN); 73 qla82xx_crb_addr_transform(QMN); 74 qla82xx_crb_addr_transform(QMS); 75 qla82xx_crb_addr_transform(PGNI); 76 qla82xx_crb_addr_transform(PGND); 77 qla82xx_crb_addr_transform(PGN3); 78 qla82xx_crb_addr_transform(PGN2); 79 qla82xx_crb_addr_transform(PGN1); 80 qla82xx_crb_addr_transform(PGN0); 81 qla82xx_crb_addr_transform(PGSI); 82 qla82xx_crb_addr_transform(PGSD); 83 qla82xx_crb_addr_transform(PGS3); 84 qla82xx_crb_addr_transform(PGS2); 85 qla82xx_crb_addr_transform(PGS1); 86 qla82xx_crb_addr_transform(PGS0); 87 qla82xx_crb_addr_transform(PS); 88 qla82xx_crb_addr_transform(PH); 89 qla82xx_crb_addr_transform(NIU); 90 qla82xx_crb_addr_transform(I2Q); 91 qla82xx_crb_addr_transform(EG); 92 qla82xx_crb_addr_transform(MN); 93 qla82xx_crb_addr_transform(MS); 94 qla82xx_crb_addr_transform(CAS2); 95 qla82xx_crb_addr_transform(CAS1); 96 qla82xx_crb_addr_transform(CAS0); 97 qla82xx_crb_addr_transform(CAM); 98 qla82xx_crb_addr_transform(C2C1); 99 qla82xx_crb_addr_transform(C2C0); 100 qla82xx_crb_addr_transform(SMB); 101 qla82xx_crb_addr_transform(OCM0); 102 /* 103 * Used only in P3 just define it for P2 also. 104 */ 105 qla82xx_crb_addr_transform(I2C0); 106 107 qla82xx_crb_table_initialized = 1; 108 } 109 110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 111 {{{0, 0, 0, 0} } }, 112 {{{1, 0x0100000, 0x0102000, 0x120000}, 113 {1, 0x0110000, 0x0120000, 0x130000}, 114 {1, 0x0120000, 0x0122000, 0x124000}, 115 {1, 0x0130000, 0x0132000, 0x126000}, 116 {1, 0x0140000, 0x0142000, 0x128000}, 117 {1, 0x0150000, 0x0152000, 0x12a000}, 118 {1, 0x0160000, 0x0170000, 0x110000}, 119 {1, 0x0170000, 0x0172000, 0x12e000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {1, 0x01e0000, 0x01e0800, 0x122000}, 127 {0, 0x0000000, 0x0000000, 0x000000} } } , 128 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 129 {{{0, 0, 0, 0} } }, 130 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 131 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 134 {{{1, 0x0800000, 0x0802000, 0x170000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 150 {{{1, 0x0900000, 0x0902000, 0x174000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 166 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 182 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 203 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 204 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 205 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 206 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 207 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 208 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{0, 0, 0, 0} } }, 211 {{{0, 0, 0, 0} } }, 212 {{{0, 0, 0, 0} } }, 213 {{{0, 0, 0, 0} } }, 214 {{{0, 0, 0, 0} } }, 215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 218 {{{0} } }, 219 {{{1, 0x2100000, 0x2102000, 0x120000}, 220 {1, 0x2110000, 0x2120000, 0x130000}, 221 {1, 0x2120000, 0x2122000, 0x124000}, 222 {1, 0x2130000, 0x2132000, 0x126000}, 223 {1, 0x2140000, 0x2142000, 0x128000}, 224 {1, 0x2150000, 0x2152000, 0x12a000}, 225 {1, 0x2160000, 0x2170000, 0x110000}, 226 {1, 0x2170000, 0x2172000, 0x12e000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000} } }, 235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 236 {{{0} } }, 237 {{{0} } }, 238 {{{0} } }, 239 {{{0} } }, 240 {{{0} } }, 241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 242 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 253 {{{0} } }, 254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 260 {{{0} } }, 261 {{{0} } }, 262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 265 }; 266 267 /* 268 * top 12 bits of crb internal address (hub, agent) 269 */ 270 static unsigned qla82xx_crb_hub_agt[64] = { 271 0, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 275 0, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 301 0, 302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 303 0, 304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 306 0, 307 0, 308 0, 309 0, 310 0, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 312 0, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 328 0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 332 0, 333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 334 0, 335 }; 336 337 /* Device states */ 338 static char *q_dev_state[] = { 339 "Unknown", 340 "Cold", 341 "Initializing", 342 "Ready", 343 "Need Reset", 344 "Need Quiescent", 345 "Failed", 346 "Quiescent", 347 }; 348 349 char *qdev_state(uint32_t dev_state) 350 { 351 return q_dev_state[dev_state]; 352 } 353 354 /* 355 * In: 'off_in' is offset from CRB space in 128M pci map 356 * Out: 'off_out' is 2M pci map addr 357 * side effect: lock crb window 358 */ 359 static void 360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 361 void __iomem **off_out) 362 { 363 u32 win_read; 364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 365 366 ha->crb_win = CRB_HI(off_in); 367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 368 369 /* Read back value to make sure write has gone through before trying 370 * to use it. 371 */ 372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 373 if (win_read != ha->crb_win) { 374 ql_dbg(ql_dbg_p3p, vha, 0xb000, 375 "%s: Written crbwin (0x%x) " 376 "!= Read crbwin (0x%x), off=0x%lx.\n", 377 __func__, ha->crb_win, win_read, off_in); 378 } 379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 380 } 381 382 static int 383 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 384 void __iomem **off_out) 385 { 386 struct crb_128M_2M_sub_block_map *m; 387 388 if (off_in >= QLA82XX_CRB_MAX) 389 return -1; 390 391 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 392 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 393 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 394 return 0; 395 } 396 397 if (off_in < QLA82XX_PCI_CRBSPACE) 398 return -1; 399 400 off_in -= QLA82XX_PCI_CRBSPACE; 401 402 /* Try direct map */ 403 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 404 405 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 406 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 407 return 0; 408 } 409 /* Not in direct map, use crb window */ 410 *off_out = (void __iomem *)off_in; 411 return 1; 412 } 413 414 #define CRB_WIN_LOCK_TIMEOUT 100000000 415 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 416 { 417 int done = 0, timeout = 0; 418 419 while (!done) { 420 /* acquire semaphore3 from PCI HW block */ 421 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 422 if (done == 1) 423 break; 424 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 425 return -1; 426 timeout++; 427 } 428 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 429 return 0; 430 } 431 432 int 433 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 434 { 435 void __iomem *off; 436 unsigned long flags = 0; 437 int rv; 438 439 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 440 441 BUG_ON(rv == -1); 442 443 if (rv == 1) { 444 #ifndef __CHECKER__ 445 write_lock_irqsave(&ha->hw_lock, flags); 446 #endif 447 qla82xx_crb_win_lock(ha); 448 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 449 } 450 451 writel(data, (void __iomem *)off); 452 453 if (rv == 1) { 454 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 455 #ifndef __CHECKER__ 456 write_unlock_irqrestore(&ha->hw_lock, flags); 457 #endif 458 } 459 return 0; 460 } 461 462 int 463 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 464 { 465 void __iomem *off; 466 unsigned long flags = 0; 467 int rv; 468 u32 data; 469 470 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 471 472 BUG_ON(rv == -1); 473 474 if (rv == 1) { 475 #ifndef __CHECKER__ 476 write_lock_irqsave(&ha->hw_lock, flags); 477 #endif 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 480 } 481 data = rd_reg_dword(off); 482 483 if (rv == 1) { 484 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 485 #ifndef __CHECKER__ 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 #endif 488 } 489 return data; 490 } 491 492 /* 493 * Context: task, might sleep 494 */ 495 int qla82xx_idc_lock(struct qla_hw_data *ha) 496 { 497 const int delay_ms = 100, timeout_ms = 2000; 498 int done, total = 0; 499 500 might_sleep(); 501 502 while (true) { 503 /* acquire semaphore5 from PCI HW block */ 504 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 505 if (done == 1) 506 break; 507 if (WARN_ON_ONCE(total >= timeout_ms)) 508 return -1; 509 510 total += delay_ms; 511 msleep(delay_ms); 512 } 513 514 return 0; 515 } 516 517 void qla82xx_idc_unlock(struct qla_hw_data *ha) 518 { 519 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 520 } 521 522 /* 523 * check memory access boundary. 524 * used by test agent. support ddr access only for now 525 */ 526 static unsigned long 527 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 528 unsigned long long addr, int size) 529 { 530 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 531 QLA82XX_ADDR_DDR_NET_MAX) || 532 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 533 QLA82XX_ADDR_DDR_NET_MAX) || 534 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 535 return 0; 536 else 537 return 1; 538 } 539 540 static int qla82xx_pci_set_window_warning_count; 541 542 static unsigned long 543 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 544 { 545 int window; 546 u32 win_read; 547 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 548 549 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 550 QLA82XX_ADDR_DDR_NET_MAX)) { 551 /* DDR network side */ 552 window = MN_WIN(addr); 553 ha->ddr_mn_window = window; 554 qla82xx_wr_32(ha, 555 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 556 win_read = qla82xx_rd_32(ha, 557 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 558 if ((win_read << 17) != window) { 559 ql_dbg(ql_dbg_p3p, vha, 0xb003, 560 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 561 __func__, window, win_read); 562 } 563 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 564 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 565 QLA82XX_ADDR_OCM0_MAX)) { 566 unsigned int temp1; 567 568 if ((addr & 0x00ff800) == 0xff800) { 569 ql_log(ql_log_warn, vha, 0xb004, 570 "%s: QM access not handled.\n", __func__); 571 addr = -1UL; 572 } 573 window = OCM_WIN(addr); 574 ha->ddr_mn_window = window; 575 qla82xx_wr_32(ha, 576 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 577 win_read = qla82xx_rd_32(ha, 578 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 579 temp1 = ((window & 0x1FF) << 7) | 580 ((window & 0x0FFFE0000) >> 17); 581 if (win_read != temp1) { 582 ql_log(ql_log_warn, vha, 0xb005, 583 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 584 __func__, temp1, win_read); 585 } 586 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 587 588 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 589 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 590 /* QDR network side */ 591 window = MS_WIN(addr); 592 ha->qdr_sn_window = window; 593 qla82xx_wr_32(ha, 594 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 595 win_read = qla82xx_rd_32(ha, 596 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 597 if (win_read != window) { 598 ql_log(ql_log_warn, vha, 0xb006, 599 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 600 __func__, window, win_read); 601 } 602 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 603 } else { 604 /* 605 * peg gdb frequently accesses memory that doesn't exist, 606 * this limits the chit chat so debugging isn't slowed down. 607 */ 608 if ((qla82xx_pci_set_window_warning_count++ < 8) || 609 (qla82xx_pci_set_window_warning_count%64 == 0)) { 610 ql_log(ql_log_warn, vha, 0xb007, 611 "%s: Warning:%s Unknown address range!.\n", 612 __func__, QLA2XXX_DRIVER_NAME); 613 } 614 addr = -1UL; 615 } 616 return addr; 617 } 618 619 /* check if address is in the same windows as the previous access */ 620 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 621 unsigned long long addr) 622 { 623 int window; 624 unsigned long long qdr_max; 625 626 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 627 628 /* DDR network side */ 629 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 630 QLA82XX_ADDR_DDR_NET_MAX)) 631 BUG(); 632 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 633 QLA82XX_ADDR_OCM0_MAX)) 634 return 1; 635 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 636 QLA82XX_ADDR_OCM1_MAX)) 637 return 1; 638 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 639 /* QDR network side */ 640 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 641 if (ha->qdr_sn_window == window) 642 return 1; 643 } 644 return 0; 645 } 646 647 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 648 u64 off, void *data, int size) 649 { 650 unsigned long flags; 651 void __iomem *addr = NULL; 652 int ret = 0; 653 u64 start; 654 uint8_t __iomem *mem_ptr = NULL; 655 unsigned long mem_base; 656 unsigned long mem_page; 657 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 658 659 write_lock_irqsave(&ha->hw_lock, flags); 660 661 /* 662 * If attempting to access unknown address or straddle hw windows, 663 * do not access. 664 */ 665 start = qla82xx_pci_set_window(ha, off); 666 if ((start == -1UL) || 667 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 668 write_unlock_irqrestore(&ha->hw_lock, flags); 669 ql_log(ql_log_fatal, vha, 0xb008, 670 "%s out of bound pci memory " 671 "access, offset is 0x%llx.\n", 672 QLA2XXX_DRIVER_NAME, off); 673 return -1; 674 } 675 676 write_unlock_irqrestore(&ha->hw_lock, flags); 677 mem_base = pci_resource_start(ha->pdev, 0); 678 mem_page = start & PAGE_MASK; 679 /* Map two pages whenever user tries to access addresses in two 680 * consecutive pages. 681 */ 682 if (mem_page != ((start + size - 1) & PAGE_MASK)) 683 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 684 else 685 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 686 if (mem_ptr == NULL) { 687 *(u8 *)data = 0; 688 return -1; 689 } 690 addr = mem_ptr; 691 addr += start & (PAGE_SIZE - 1); 692 write_lock_irqsave(&ha->hw_lock, flags); 693 694 switch (size) { 695 case 1: 696 *(u8 *)data = readb(addr); 697 break; 698 case 2: 699 *(u16 *)data = readw(addr); 700 break; 701 case 4: 702 *(u32 *)data = readl(addr); 703 break; 704 case 8: 705 *(u64 *)data = readq(addr); 706 break; 707 default: 708 ret = -1; 709 break; 710 } 711 write_unlock_irqrestore(&ha->hw_lock, flags); 712 713 if (mem_ptr) 714 iounmap(mem_ptr); 715 return ret; 716 } 717 718 static int 719 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 720 u64 off, void *data, int size) 721 { 722 unsigned long flags; 723 void __iomem *addr = NULL; 724 int ret = 0; 725 u64 start; 726 uint8_t __iomem *mem_ptr = NULL; 727 unsigned long mem_base; 728 unsigned long mem_page; 729 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 730 731 write_lock_irqsave(&ha->hw_lock, flags); 732 733 /* 734 * If attempting to access unknown address or straddle hw windows, 735 * do not access. 736 */ 737 start = qla82xx_pci_set_window(ha, off); 738 if ((start == -1UL) || 739 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 740 write_unlock_irqrestore(&ha->hw_lock, flags); 741 ql_log(ql_log_fatal, vha, 0xb009, 742 "%s out of bound memory " 743 "access, offset is 0x%llx.\n", 744 QLA2XXX_DRIVER_NAME, off); 745 return -1; 746 } 747 748 write_unlock_irqrestore(&ha->hw_lock, flags); 749 mem_base = pci_resource_start(ha->pdev, 0); 750 mem_page = start & PAGE_MASK; 751 /* Map two pages whenever user tries to access addresses in two 752 * consecutive pages. 753 */ 754 if (mem_page != ((start + size - 1) & PAGE_MASK)) 755 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 756 else 757 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 758 if (mem_ptr == NULL) 759 return -1; 760 761 addr = mem_ptr; 762 addr += start & (PAGE_SIZE - 1); 763 write_lock_irqsave(&ha->hw_lock, flags); 764 765 switch (size) { 766 case 1: 767 writeb(*(u8 *)data, addr); 768 break; 769 case 2: 770 writew(*(u16 *)data, addr); 771 break; 772 case 4: 773 writel(*(u32 *)data, addr); 774 break; 775 case 8: 776 writeq(*(u64 *)data, addr); 777 break; 778 default: 779 ret = -1; 780 break; 781 } 782 write_unlock_irqrestore(&ha->hw_lock, flags); 783 if (mem_ptr) 784 iounmap(mem_ptr); 785 return ret; 786 } 787 788 #define MTU_FUDGE_FACTOR 100 789 static unsigned long 790 qla82xx_decode_crb_addr(unsigned long addr) 791 { 792 int i; 793 unsigned long base_addr, offset, pci_base; 794 795 if (!qla82xx_crb_table_initialized) 796 qla82xx_crb_addr_transform_setup(); 797 798 pci_base = ADDR_ERROR; 799 base_addr = addr & 0xfff00000; 800 offset = addr & 0x000fffff; 801 802 for (i = 0; i < MAX_CRB_XFORM; i++) { 803 if (crb_addr_xform[i] == base_addr) { 804 pci_base = i << 20; 805 break; 806 } 807 } 808 if (pci_base == ADDR_ERROR) 809 return pci_base; 810 return pci_base + offset; 811 } 812 813 static long rom_max_timeout = 100; 814 static long qla82xx_rom_lock_timeout = 100; 815 816 static int 817 qla82xx_rom_lock(struct qla_hw_data *ha) 818 { 819 int done = 0, timeout = 0; 820 uint32_t lock_owner = 0; 821 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 822 823 while (!done) { 824 /* acquire semaphore2 from PCI HW block */ 825 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 826 if (done == 1) 827 break; 828 if (timeout >= qla82xx_rom_lock_timeout) { 829 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 830 ql_dbg(ql_dbg_p3p, vha, 0xb157, 831 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 832 __func__, ha->portnum, lock_owner); 833 return -1; 834 } 835 timeout++; 836 } 837 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 838 return 0; 839 } 840 841 static void 842 qla82xx_rom_unlock(struct qla_hw_data *ha) 843 { 844 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 845 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 846 } 847 848 static int 849 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 850 { 851 long timeout = 0; 852 long done = 0 ; 853 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 854 855 while (done == 0) { 856 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 857 done &= 4; 858 timeout++; 859 if (timeout >= rom_max_timeout) { 860 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 861 "%s: Timeout reached waiting for rom busy.\n", 862 QLA2XXX_DRIVER_NAME); 863 return -1; 864 } 865 } 866 return 0; 867 } 868 869 static int 870 qla82xx_wait_rom_done(struct qla_hw_data *ha) 871 { 872 long timeout = 0; 873 long done = 0 ; 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875 876 while (done == 0) { 877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 2; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 882 "%s: Timeout reached waiting for rom done.\n", 883 QLA2XXX_DRIVER_NAME); 884 return -1; 885 } 886 } 887 return 0; 888 } 889 890 static int 891 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 892 { 893 uint32_t off_value, rval = 0; 894 895 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 896 897 /* Read back value to make sure write has gone through */ 898 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 899 off_value = (off & 0x0000FFFF); 900 901 if (flag) 902 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 903 data); 904 else 905 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + 906 ha->nx_pcibase); 907 908 return rval; 909 } 910 911 static int 912 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913 { 914 /* Dword reads to flash. */ 915 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 916 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 917 (addr & 0x0000FFFF), 0, 0); 918 919 return 0; 920 } 921 922 static int 923 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 924 { 925 int ret, loops = 0; 926 uint32_t lock_owner = 0; 927 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 928 929 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 930 udelay(100); 931 schedule(); 932 loops++; 933 } 934 if (loops >= 50000) { 935 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 936 ql_log(ql_log_fatal, vha, 0x00b9, 937 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 938 lock_owner); 939 return -1; 940 } 941 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 942 qla82xx_rom_unlock(ha); 943 return ret; 944 } 945 946 static int 947 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 948 { 949 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 950 951 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 952 qla82xx_wait_rom_busy(ha); 953 if (qla82xx_wait_rom_done(ha)) { 954 ql_log(ql_log_warn, vha, 0xb00c, 955 "Error waiting for rom done.\n"); 956 return -1; 957 } 958 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 959 return 0; 960 } 961 962 static int 963 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 964 { 965 uint32_t val = 0; 966 int i, ret; 967 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 968 969 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 970 for (i = 0; i < 50000; i++) { 971 ret = qla82xx_read_status_reg(ha, &val); 972 if (ret < 0 || (val & 1) == 0) 973 return ret; 974 udelay(10); 975 cond_resched(); 976 } 977 ql_log(ql_log_warn, vha, 0xb00d, 978 "Timeout reached waiting for write finish.\n"); 979 return -1; 980 } 981 982 static int 983 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 984 { 985 uint32_t val; 986 987 qla82xx_wait_rom_busy(ha); 988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 989 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 990 qla82xx_wait_rom_busy(ha); 991 if (qla82xx_wait_rom_done(ha)) 992 return -1; 993 if (qla82xx_read_status_reg(ha, &val) != 0) 994 return -1; 995 if ((val & 2) != 2) 996 return -1; 997 return 0; 998 } 999 1000 static int 1001 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1002 { 1003 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1004 1005 if (qla82xx_flash_set_write_enable(ha)) 1006 return -1; 1007 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1009 if (qla82xx_wait_rom_done(ha)) { 1010 ql_log(ql_log_warn, vha, 0xb00e, 1011 "Error waiting for rom done.\n"); 1012 return -1; 1013 } 1014 return qla82xx_flash_wait_write_finish(ha); 1015 } 1016 1017 static int 1018 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1019 { 1020 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1021 1022 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1023 if (qla82xx_wait_rom_done(ha)) { 1024 ql_log(ql_log_warn, vha, 0xb00f, 1025 "Error waiting for rom done.\n"); 1026 return -1; 1027 } 1028 return 0; 1029 } 1030 1031 static int 1032 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1033 { 1034 int loops = 0; 1035 uint32_t lock_owner = 0; 1036 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1037 1038 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1039 udelay(100); 1040 cond_resched(); 1041 loops++; 1042 } 1043 if (loops >= 50000) { 1044 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1045 ql_log(ql_log_warn, vha, 0xb010, 1046 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1047 return -1; 1048 } 1049 return 0; 1050 } 1051 1052 static int 1053 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1054 uint32_t data) 1055 { 1056 int ret = 0; 1057 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1058 1059 ret = ql82xx_rom_lock_d(ha); 1060 if (ret < 0) { 1061 ql_log(ql_log_warn, vha, 0xb011, 1062 "ROM lock failed.\n"); 1063 return ret; 1064 } 1065 1066 if (qla82xx_flash_set_write_enable(ha)) 1067 goto done_write; 1068 1069 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1070 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1071 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1072 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1073 qla82xx_wait_rom_busy(ha); 1074 if (qla82xx_wait_rom_done(ha)) { 1075 ql_log(ql_log_warn, vha, 0xb012, 1076 "Error waiting for rom done.\n"); 1077 ret = -1; 1078 goto done_write; 1079 } 1080 1081 ret = qla82xx_flash_wait_write_finish(ha); 1082 1083 done_write: 1084 qla82xx_rom_unlock(ha); 1085 return ret; 1086 } 1087 1088 /* This routine does CRB initialize sequence 1089 * to put the ISP into operational state 1090 */ 1091 static int 1092 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1093 { 1094 int addr, val; 1095 int i ; 1096 struct crb_addr_pair *buf; 1097 unsigned long off; 1098 unsigned offset, n; 1099 struct qla_hw_data *ha = vha->hw; 1100 1101 struct crb_addr_pair { 1102 long addr; 1103 long data; 1104 }; 1105 1106 /* Halt all the individual PEGs and other blocks of the ISP */ 1107 qla82xx_rom_lock(ha); 1108 1109 /* disable all I2Q */ 1110 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1111 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1112 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1113 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1116 1117 /* disable all niu interrupts */ 1118 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1119 /* disable xge rx/tx */ 1120 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1121 /* disable xg1 rx/tx */ 1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1123 /* disable sideband mac */ 1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1125 /* disable ap0 mac */ 1126 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1127 /* disable ap1 mac */ 1128 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1129 1130 /* halt sre */ 1131 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1132 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1133 1134 /* halt epg */ 1135 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1136 1137 /* halt timers */ 1138 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1139 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1140 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1144 1145 /* halt pegs */ 1146 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1147 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1148 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1149 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1151 msleep(20); 1152 1153 /* big hammer */ 1154 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1155 /* don't reset CAM block on reset */ 1156 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1157 else 1158 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1159 qla82xx_rom_unlock(ha); 1160 1161 /* Read the signature value from the flash. 1162 * Offset 0: Contain signature (0xcafecafe) 1163 * Offset 4: Offset and number of addr/value pairs 1164 * that present in CRB initialize sequence 1165 */ 1166 n = 0; 1167 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1168 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1169 ql_log(ql_log_fatal, vha, 0x006e, 1170 "Error Reading crb_init area: n: %08x.\n", n); 1171 return -1; 1172 } 1173 1174 /* Offset in flash = lower 16 bits 1175 * Number of entries = upper 16 bits 1176 */ 1177 offset = n & 0xffffU; 1178 n = (n >> 16) & 0xffffU; 1179 1180 /* number of addr/value pair should not exceed 1024 entries */ 1181 if (n >= 1024) { 1182 ql_log(ql_log_fatal, vha, 0x0071, 1183 "Card flash not initialized:n=0x%x.\n", n); 1184 return -1; 1185 } 1186 1187 ql_log(ql_log_info, vha, 0x0072, 1188 "%d CRB init values found in ROM.\n", n); 1189 1190 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1191 if (buf == NULL) { 1192 ql_log(ql_log_fatal, vha, 0x010c, 1193 "Unable to allocate memory.\n"); 1194 return -ENOMEM; 1195 } 1196 1197 for (i = 0; i < n; i++) { 1198 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1199 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1200 kfree(buf); 1201 return -1; 1202 } 1203 1204 buf[i].addr = addr; 1205 buf[i].data = val; 1206 } 1207 1208 for (i = 0; i < n; i++) { 1209 /* Translate internal CRB initialization 1210 * address to PCI bus address 1211 */ 1212 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1213 QLA82XX_PCI_CRBSPACE; 1214 /* Not all CRB addr/value pair to be written, 1215 * some of them are skipped 1216 */ 1217 1218 /* skipping cold reboot MAGIC */ 1219 if (off == QLA82XX_CAM_RAM(0x1fc)) 1220 continue; 1221 1222 /* do not reset PCI */ 1223 if (off == (ROMUSB_GLB + 0xbc)) 1224 continue; 1225 1226 /* skip core clock, so that firmware can increase the clock */ 1227 if (off == (ROMUSB_GLB + 0xc8)) 1228 continue; 1229 1230 /* skip the function enable register */ 1231 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1232 continue; 1233 1234 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1235 continue; 1236 1237 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1238 continue; 1239 1240 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1241 continue; 1242 1243 if (off == ADDR_ERROR) { 1244 ql_log(ql_log_fatal, vha, 0x0116, 1245 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1246 continue; 1247 } 1248 1249 qla82xx_wr_32(ha, off, buf[i].data); 1250 1251 /* ISP requires much bigger delay to settle down, 1252 * else crb_window returns 0xffffffff 1253 */ 1254 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1255 msleep(1000); 1256 1257 /* ISP requires millisec delay between 1258 * successive CRB register updation 1259 */ 1260 msleep(1); 1261 } 1262 1263 kfree(buf); 1264 1265 /* Resetting the data and instruction cache */ 1266 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1267 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1268 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1269 1270 /* Clear all protocol processing engines */ 1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1273 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1279 return 0; 1280 } 1281 1282 static int 1283 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1284 u64 off, void *data, int size) 1285 { 1286 int i, j, ret = 0, loop, sz[2], off0; 1287 int scale, shift_amount, startword; 1288 uint32_t temp; 1289 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1290 1291 /* 1292 * If not MN, go check for MS or invalid. 1293 */ 1294 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1295 mem_crb = QLA82XX_CRB_QDR_NET; 1296 else { 1297 mem_crb = QLA82XX_CRB_DDR_NET; 1298 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1299 return qla82xx_pci_mem_write_direct(ha, 1300 off, data, size); 1301 } 1302 1303 off0 = off & 0x7; 1304 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1305 sz[1] = size - sz[0]; 1306 1307 off8 = off & 0xfffffff0; 1308 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1309 shift_amount = 4; 1310 scale = 2; 1311 startword = (off & 0xf)/8; 1312 1313 for (i = 0; i < loop; i++) { 1314 if (qla82xx_pci_mem_read_2M(ha, off8 + 1315 (i << shift_amount), &word[i * scale], 8)) 1316 return -1; 1317 } 1318 1319 switch (size) { 1320 case 1: 1321 tmpw = *((uint8_t *)data); 1322 break; 1323 case 2: 1324 tmpw = *((uint16_t *)data); 1325 break; 1326 case 4: 1327 tmpw = *((uint32_t *)data); 1328 break; 1329 case 8: 1330 default: 1331 tmpw = *((uint64_t *)data); 1332 break; 1333 } 1334 1335 if (sz[0] == 8) { 1336 word[startword] = tmpw; 1337 } else { 1338 word[startword] &= 1339 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1340 word[startword] |= tmpw << (off0 * 8); 1341 } 1342 if (sz[1] != 0) { 1343 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1344 word[startword+1] |= tmpw >> (sz[0] * 8); 1345 } 1346 1347 for (i = 0; i < loop; i++) { 1348 temp = off8 + (i << shift_amount); 1349 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1350 temp = 0; 1351 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1352 temp = word[i * scale] & 0xffffffff; 1353 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1354 temp = (word[i * scale] >> 32) & 0xffffffff; 1355 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1356 temp = word[i*scale + 1] & 0xffffffff; 1357 qla82xx_wr_32(ha, mem_crb + 1358 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1359 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1360 qla82xx_wr_32(ha, mem_crb + 1361 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1362 1363 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1364 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1365 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1366 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1367 1368 for (j = 0; j < MAX_CTL_CHECK; j++) { 1369 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1370 if ((temp & MIU_TA_CTL_BUSY) == 0) 1371 break; 1372 } 1373 1374 if (j >= MAX_CTL_CHECK) { 1375 if (printk_ratelimit()) 1376 dev_err(&ha->pdev->dev, 1377 "failed to write through agent.\n"); 1378 ret = -1; 1379 break; 1380 } 1381 } 1382 1383 return ret; 1384 } 1385 1386 static int 1387 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1388 { 1389 int i; 1390 long size = 0; 1391 long flashaddr = ha->flt_region_bootload << 2; 1392 long memaddr = BOOTLD_START; 1393 u64 data; 1394 u32 high, low; 1395 1396 size = (IMAGE_START - BOOTLD_START) / 8; 1397 1398 for (i = 0; i < size; i++) { 1399 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1400 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1401 return -1; 1402 } 1403 data = ((u64)high << 32) | low ; 1404 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1405 flashaddr += 8; 1406 memaddr += 8; 1407 1408 if (i % 0x1000 == 0) 1409 msleep(1); 1410 } 1411 udelay(100); 1412 read_lock(&ha->hw_lock); 1413 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1414 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1415 read_unlock(&ha->hw_lock); 1416 return 0; 1417 } 1418 1419 int 1420 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1421 u64 off, void *data, int size) 1422 { 1423 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1424 int shift_amount; 1425 uint32_t temp; 1426 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1427 1428 /* 1429 * If not MN, go check for MS or invalid. 1430 */ 1431 1432 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1433 mem_crb = QLA82XX_CRB_QDR_NET; 1434 else { 1435 mem_crb = QLA82XX_CRB_DDR_NET; 1436 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1437 return qla82xx_pci_mem_read_direct(ha, 1438 off, data, size); 1439 } 1440 1441 off8 = off & 0xfffffff0; 1442 off0[0] = off & 0xf; 1443 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1444 shift_amount = 4; 1445 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1446 off0[1] = 0; 1447 sz[1] = size - sz[0]; 1448 1449 for (i = 0; i < loop; i++) { 1450 temp = off8 + (i << shift_amount); 1451 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1452 temp = 0; 1453 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1454 temp = MIU_TA_CTL_ENABLE; 1455 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1456 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1457 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1458 1459 for (j = 0; j < MAX_CTL_CHECK; j++) { 1460 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1461 if ((temp & MIU_TA_CTL_BUSY) == 0) 1462 break; 1463 } 1464 1465 if (j >= MAX_CTL_CHECK) { 1466 if (printk_ratelimit()) 1467 dev_err(&ha->pdev->dev, 1468 "failed to read through agent.\n"); 1469 break; 1470 } 1471 1472 start = off0[i] >> 2; 1473 end = (off0[i] + sz[i] - 1) >> 2; 1474 for (k = start; k <= end; k++) { 1475 temp = qla82xx_rd_32(ha, 1476 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1477 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1478 } 1479 } 1480 1481 if (j >= MAX_CTL_CHECK) 1482 return -1; 1483 1484 if ((off0[0] & 7) == 0) { 1485 val = word[0]; 1486 } else { 1487 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1488 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1489 } 1490 1491 switch (size) { 1492 case 1: 1493 *(uint8_t *)data = val; 1494 break; 1495 case 2: 1496 *(uint16_t *)data = val; 1497 break; 1498 case 4: 1499 *(uint32_t *)data = val; 1500 break; 1501 case 8: 1502 *(uint64_t *)data = val; 1503 break; 1504 } 1505 return 0; 1506 } 1507 1508 1509 static struct qla82xx_uri_table_desc * 1510 qla82xx_get_table_desc(const u8 *unirom, int section) 1511 { 1512 uint32_t i; 1513 struct qla82xx_uri_table_desc *directory = 1514 (struct qla82xx_uri_table_desc *)&unirom[0]; 1515 uint32_t offset; 1516 uint32_t tab_type; 1517 uint32_t entries = le32_to_cpu(directory->num_entries); 1518 1519 for (i = 0; i < entries; i++) { 1520 offset = le32_to_cpu(directory->findex) + 1521 (i * le32_to_cpu(directory->entry_size)); 1522 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8); 1523 1524 if (tab_type == section) 1525 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1526 } 1527 1528 return NULL; 1529 } 1530 1531 static struct qla82xx_uri_data_desc * 1532 qla82xx_get_data_desc(struct qla_hw_data *ha, 1533 u32 section, u32 idx_offset) 1534 { 1535 const u8 *unirom = ha->hablob->fw->data; 1536 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] + 1537 idx_offset); 1538 struct qla82xx_uri_table_desc *tab_desc = NULL; 1539 uint32_t offset; 1540 1541 tab_desc = qla82xx_get_table_desc(unirom, section); 1542 if (!tab_desc) 1543 return NULL; 1544 1545 offset = le32_to_cpu(tab_desc->findex) + 1546 (le32_to_cpu(tab_desc->entry_size) * idx); 1547 1548 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1549 } 1550 1551 static u8 * 1552 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1553 { 1554 u32 offset = BOOTLD_START; 1555 struct qla82xx_uri_data_desc *uri_desc = NULL; 1556 1557 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1558 uri_desc = qla82xx_get_data_desc(ha, 1559 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1560 if (uri_desc) 1561 offset = le32_to_cpu(uri_desc->findex); 1562 } 1563 1564 return (u8 *)&ha->hablob->fw->data[offset]; 1565 } 1566 1567 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha) 1568 { 1569 struct qla82xx_uri_data_desc *uri_desc = NULL; 1570 1571 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1572 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1573 QLA82XX_URI_FIRMWARE_IDX_OFF); 1574 if (uri_desc) 1575 return le32_to_cpu(uri_desc->size); 1576 } 1577 1578 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1579 } 1580 1581 static u8 * 1582 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1583 { 1584 u32 offset = IMAGE_START; 1585 struct qla82xx_uri_data_desc *uri_desc = NULL; 1586 1587 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1588 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1589 QLA82XX_URI_FIRMWARE_IDX_OFF); 1590 if (uri_desc) 1591 offset = le32_to_cpu(uri_desc->findex); 1592 } 1593 1594 return (u8 *)&ha->hablob->fw->data[offset]; 1595 } 1596 1597 /* PCI related functions */ 1598 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1599 { 1600 unsigned long val = 0; 1601 u32 control; 1602 1603 switch (region) { 1604 case 0: 1605 val = 0; 1606 break; 1607 case 1: 1608 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1609 val = control + QLA82XX_MSIX_TBL_SPACE; 1610 break; 1611 } 1612 return val; 1613 } 1614 1615 1616 int 1617 qla82xx_iospace_config(struct qla_hw_data *ha) 1618 { 1619 uint32_t len = 0; 1620 1621 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1623 "Failed to reserver selected regions.\n"); 1624 goto iospace_error_exit; 1625 } 1626 1627 /* Use MMIO operations for all accesses. */ 1628 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1629 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1630 "Region #0 not an MMIO resource, aborting.\n"); 1631 goto iospace_error_exit; 1632 } 1633 1634 len = pci_resource_len(ha->pdev, 0); 1635 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1636 if (!ha->nx_pcibase) { 1637 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1638 "Cannot remap pcibase MMIO, aborting.\n"); 1639 goto iospace_error_exit; 1640 } 1641 1642 /* Mapping of IO base pointer */ 1643 if (IS_QLA8044(ha)) { 1644 ha->iobase = ha->nx_pcibase; 1645 } else if (IS_QLA82XX(ha)) { 1646 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1647 } 1648 1649 if (!ql2xdbwr) { 1650 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1651 (ha->pdev->devfn << 12)), 4); 1652 if (!ha->nxdb_wr_ptr) { 1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1654 "Cannot remap MMIO, aborting.\n"); 1655 goto iospace_error_exit; 1656 } 1657 1658 /* Mapping of IO base pointer, 1659 * door bell read and write pointer 1660 */ 1661 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1662 (ha->pdev->devfn * 8); 1663 } else { 1664 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1665 QLA82XX_CAMRAM_DB1 : 1666 QLA82XX_CAMRAM_DB2); 1667 } 1668 1669 ha->max_req_queues = ha->max_rsp_queues = 1; 1670 ha->msix_count = ha->max_rsp_queues + 1; 1671 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1672 "nx_pci_base=%p iobase=%p " 1673 "max_req_queues=%d msix_count=%d.\n", 1674 ha->nx_pcibase, ha->iobase, 1675 ha->max_req_queues, ha->msix_count); 1676 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1677 "nx_pci_base=%p iobase=%p " 1678 "max_req_queues=%d msix_count=%d.\n", 1679 ha->nx_pcibase, ha->iobase, 1680 ha->max_req_queues, ha->msix_count); 1681 return 0; 1682 1683 iospace_error_exit: 1684 return -ENOMEM; 1685 } 1686 1687 /* GS related functions */ 1688 1689 /* Initialization related functions */ 1690 1691 /** 1692 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1693 * @vha: HA context 1694 * 1695 * Returns 0 on success. 1696 */ 1697 int 1698 qla82xx_pci_config(scsi_qla_host_t *vha) 1699 { 1700 struct qla_hw_data *ha = vha->hw; 1701 int ret; 1702 1703 pci_set_master(ha->pdev); 1704 ret = pci_set_mwi(ha->pdev); 1705 ha->chip_revision = ha->pdev->revision; 1706 ql_dbg(ql_dbg_init, vha, 0x0043, 1707 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1708 ha->chip_revision, ret); 1709 return 0; 1710 } 1711 1712 /** 1713 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1714 * @vha: HA context 1715 * 1716 * Returns 0 on success. 1717 */ 1718 int 1719 qla82xx_reset_chip(scsi_qla_host_t *vha) 1720 { 1721 struct qla_hw_data *ha = vha->hw; 1722 1723 ha->isp_ops->disable_intrs(ha); 1724 1725 return QLA_SUCCESS; 1726 } 1727 1728 void qla82xx_config_rings(struct scsi_qla_host *vha) 1729 { 1730 struct qla_hw_data *ha = vha->hw; 1731 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1732 struct init_cb_81xx *icb; 1733 struct req_que *req = ha->req_q_map[0]; 1734 struct rsp_que *rsp = ha->rsp_q_map[0]; 1735 1736 /* Setup ring parameters in initialization control block. */ 1737 icb = (struct init_cb_81xx *)ha->init_cb; 1738 icb->request_q_outpointer = cpu_to_le16(0); 1739 icb->response_q_inpointer = cpu_to_le16(0); 1740 icb->request_q_length = cpu_to_le16(req->length); 1741 icb->response_q_length = cpu_to_le16(rsp->length); 1742 put_unaligned_le64(req->dma, &icb->request_q_address); 1743 put_unaligned_le64(rsp->dma, &icb->response_q_address); 1744 1745 wrt_reg_dword(®->req_q_out[0], 0); 1746 wrt_reg_dword(®->rsp_q_in[0], 0); 1747 wrt_reg_dword(®->rsp_q_out[0], 0); 1748 } 1749 1750 static int 1751 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1752 { 1753 u64 *ptr64; 1754 u32 i, flashaddr, size; 1755 __le64 data; 1756 1757 size = (IMAGE_START - BOOTLD_START) / 8; 1758 1759 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1760 flashaddr = BOOTLD_START; 1761 1762 for (i = 0; i < size; i++) { 1763 data = cpu_to_le64(ptr64[i]); 1764 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1765 return -EIO; 1766 flashaddr += 8; 1767 } 1768 1769 flashaddr = FLASH_ADDR_START; 1770 size = qla82xx_get_fw_size(ha) / 8; 1771 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1772 1773 for (i = 0; i < size; i++) { 1774 data = cpu_to_le64(ptr64[i]); 1775 1776 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1777 return -EIO; 1778 flashaddr += 8; 1779 } 1780 udelay(100); 1781 1782 /* Write a magic value to CAMRAM register 1783 * at a specified offset to indicate 1784 * that all data is written and 1785 * ready for firmware to initialize. 1786 */ 1787 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1788 1789 read_lock(&ha->hw_lock); 1790 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1791 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1792 read_unlock(&ha->hw_lock); 1793 return 0; 1794 } 1795 1796 static int 1797 qla82xx_set_product_offset(struct qla_hw_data *ha) 1798 { 1799 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1800 const uint8_t *unirom = ha->hablob->fw->data; 1801 uint32_t i; 1802 uint32_t entries; 1803 uint32_t flags, file_chiprev, offset; 1804 uint8_t chiprev = ha->chip_revision; 1805 /* Hardcoding mn_present flag for P3P */ 1806 int mn_present = 0; 1807 uint32_t flagbit; 1808 1809 ptab_desc = qla82xx_get_table_desc(unirom, 1810 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1811 if (!ptab_desc) 1812 return -1; 1813 1814 entries = le32_to_cpu(ptab_desc->num_entries); 1815 1816 for (i = 0; i < entries; i++) { 1817 offset = le32_to_cpu(ptab_desc->findex) + 1818 (i * le32_to_cpu(ptab_desc->entry_size)); 1819 flags = le32_to_cpu(*((__le32 *)&unirom[offset] + 1820 QLA82XX_URI_FLAGS_OFF)); 1821 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] + 1822 QLA82XX_URI_CHIP_REV_OFF)); 1823 1824 flagbit = mn_present ? 1 : 2; 1825 1826 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1827 ha->file_prd_off = offset; 1828 return 0; 1829 } 1830 } 1831 return -1; 1832 } 1833 1834 static int 1835 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1836 { 1837 uint32_t val; 1838 uint32_t min_size; 1839 struct qla_hw_data *ha = vha->hw; 1840 const struct firmware *fw = ha->hablob->fw; 1841 1842 ha->fw_type = fw_type; 1843 1844 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1845 if (qla82xx_set_product_offset(ha)) 1846 return -EINVAL; 1847 1848 min_size = QLA82XX_URI_FW_MIN_SIZE; 1849 } else { 1850 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1851 if (val != QLA82XX_BDINFO_MAGIC) 1852 return -EINVAL; 1853 1854 min_size = QLA82XX_FW_MIN_SIZE; 1855 } 1856 1857 if (fw->size < min_size) 1858 return -EINVAL; 1859 return 0; 1860 } 1861 1862 static int 1863 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1864 { 1865 u32 val = 0; 1866 int retries = 60; 1867 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1868 1869 do { 1870 read_lock(&ha->hw_lock); 1871 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1872 read_unlock(&ha->hw_lock); 1873 1874 switch (val) { 1875 case PHAN_INITIALIZE_COMPLETE: 1876 case PHAN_INITIALIZE_ACK: 1877 return QLA_SUCCESS; 1878 case PHAN_INITIALIZE_FAILED: 1879 break; 1880 default: 1881 break; 1882 } 1883 ql_log(ql_log_info, vha, 0x00a8, 1884 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1885 val, retries); 1886 1887 msleep(500); 1888 1889 } while (--retries); 1890 1891 ql_log(ql_log_fatal, vha, 0x00a9, 1892 "Cmd Peg initialization failed: 0x%x.\n", val); 1893 1894 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1895 read_lock(&ha->hw_lock); 1896 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1897 read_unlock(&ha->hw_lock); 1898 return QLA_FUNCTION_FAILED; 1899 } 1900 1901 static int 1902 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1903 { 1904 u32 val = 0; 1905 int retries = 60; 1906 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1907 1908 do { 1909 read_lock(&ha->hw_lock); 1910 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1911 read_unlock(&ha->hw_lock); 1912 1913 switch (val) { 1914 case PHAN_INITIALIZE_COMPLETE: 1915 case PHAN_INITIALIZE_ACK: 1916 return QLA_SUCCESS; 1917 case PHAN_INITIALIZE_FAILED: 1918 break; 1919 default: 1920 break; 1921 } 1922 ql_log(ql_log_info, vha, 0x00ab, 1923 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1924 val, retries); 1925 1926 msleep(500); 1927 1928 } while (--retries); 1929 1930 ql_log(ql_log_fatal, vha, 0x00ac, 1931 "Rcv Peg initialization failed: 0x%x.\n", val); 1932 read_lock(&ha->hw_lock); 1933 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1934 read_unlock(&ha->hw_lock); 1935 return QLA_FUNCTION_FAILED; 1936 } 1937 1938 /* ISR related functions */ 1939 static struct qla82xx_legacy_intr_set legacy_intr[] = 1940 QLA82XX_LEGACY_INTR_CONFIG; 1941 1942 /* 1943 * qla82xx_mbx_completion() - Process mailbox command completions. 1944 * @ha: SCSI driver HA context 1945 * @mb0: Mailbox0 register 1946 */ 1947 void 1948 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1949 { 1950 uint16_t cnt; 1951 __le16 __iomem *wptr; 1952 struct qla_hw_data *ha = vha->hw; 1953 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1954 1955 wptr = ®->mailbox_out[1]; 1956 1957 /* Load return mailbox registers. */ 1958 ha->flags.mbox_int = 1; 1959 ha->mailbox_out[0] = mb0; 1960 1961 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1962 ha->mailbox_out[cnt] = rd_reg_word(wptr); 1963 wptr++; 1964 } 1965 1966 if (!ha->mcp) 1967 ql_dbg(ql_dbg_async, vha, 0x5053, 1968 "MBX pointer ERROR.\n"); 1969 } 1970 1971 /** 1972 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1973 * @irq: interrupt number 1974 * @dev_id: SCSI driver HA context 1975 * 1976 * Called by system whenever the host adapter generates an interrupt. 1977 * 1978 * Returns handled flag. 1979 */ 1980 irqreturn_t 1981 qla82xx_intr_handler(int irq, void *dev_id) 1982 { 1983 scsi_qla_host_t *vha; 1984 struct qla_hw_data *ha; 1985 struct rsp_que *rsp; 1986 struct device_reg_82xx __iomem *reg; 1987 int status = 0, status1 = 0; 1988 unsigned long flags; 1989 unsigned long iter; 1990 uint32_t stat = 0; 1991 uint16_t mb[8]; 1992 1993 rsp = (struct rsp_que *) dev_id; 1994 if (!rsp) { 1995 ql_log(ql_log_info, NULL, 0xb053, 1996 "%s: NULL response queue pointer.\n", __func__); 1997 return IRQ_NONE; 1998 } 1999 ha = rsp->hw; 2000 2001 if (!ha->flags.msi_enabled) { 2002 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2003 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2004 return IRQ_NONE; 2005 2006 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2007 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2008 return IRQ_NONE; 2009 } 2010 2011 /* clear the interrupt */ 2012 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2013 2014 /* read twice to ensure write is flushed */ 2015 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2016 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2017 2018 reg = &ha->iobase->isp82; 2019 2020 spin_lock_irqsave(&ha->hardware_lock, flags); 2021 vha = pci_get_drvdata(ha->pdev); 2022 for (iter = 1; iter--; ) { 2023 2024 if (rd_reg_dword(®->host_int)) { 2025 stat = rd_reg_dword(®->host_status); 2026 2027 switch (stat & 0xff) { 2028 case 0x1: 2029 case 0x2: 2030 case 0x10: 2031 case 0x11: 2032 qla82xx_mbx_completion(vha, MSW(stat)); 2033 status |= MBX_INTERRUPT; 2034 break; 2035 case 0x12: 2036 mb[0] = MSW(stat); 2037 mb[1] = rd_reg_word(®->mailbox_out[1]); 2038 mb[2] = rd_reg_word(®->mailbox_out[2]); 2039 mb[3] = rd_reg_word(®->mailbox_out[3]); 2040 qla2x00_async_event(vha, rsp, mb); 2041 break; 2042 case 0x13: 2043 qla24xx_process_response_queue(vha, rsp); 2044 break; 2045 default: 2046 ql_dbg(ql_dbg_async, vha, 0x5054, 2047 "Unrecognized interrupt type (%d).\n", 2048 stat & 0xff); 2049 break; 2050 } 2051 } 2052 wrt_reg_dword(®->host_int, 0); 2053 } 2054 2055 qla2x00_handle_mbx_completion(ha, status); 2056 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2057 2058 if (!ha->flags.msi_enabled) 2059 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2060 2061 return IRQ_HANDLED; 2062 } 2063 2064 irqreturn_t 2065 qla82xx_msix_default(int irq, void *dev_id) 2066 { 2067 scsi_qla_host_t *vha; 2068 struct qla_hw_data *ha; 2069 struct rsp_que *rsp; 2070 struct device_reg_82xx __iomem *reg; 2071 int status = 0; 2072 unsigned long flags; 2073 uint32_t stat = 0; 2074 uint32_t host_int = 0; 2075 uint16_t mb[8]; 2076 2077 rsp = (struct rsp_que *) dev_id; 2078 if (!rsp) { 2079 printk(KERN_INFO 2080 "%s(): NULL response queue pointer.\n", __func__); 2081 return IRQ_NONE; 2082 } 2083 ha = rsp->hw; 2084 2085 reg = &ha->iobase->isp82; 2086 2087 spin_lock_irqsave(&ha->hardware_lock, flags); 2088 vha = pci_get_drvdata(ha->pdev); 2089 do { 2090 host_int = rd_reg_dword(®->host_int); 2091 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2092 break; 2093 if (host_int) { 2094 stat = rd_reg_dword(®->host_status); 2095 2096 switch (stat & 0xff) { 2097 case 0x1: 2098 case 0x2: 2099 case 0x10: 2100 case 0x11: 2101 qla82xx_mbx_completion(vha, MSW(stat)); 2102 status |= MBX_INTERRUPT; 2103 break; 2104 case 0x12: 2105 mb[0] = MSW(stat); 2106 mb[1] = rd_reg_word(®->mailbox_out[1]); 2107 mb[2] = rd_reg_word(®->mailbox_out[2]); 2108 mb[3] = rd_reg_word(®->mailbox_out[3]); 2109 qla2x00_async_event(vha, rsp, mb); 2110 break; 2111 case 0x13: 2112 qla24xx_process_response_queue(vha, rsp); 2113 break; 2114 default: 2115 ql_dbg(ql_dbg_async, vha, 0x5041, 2116 "Unrecognized interrupt type (%d).\n", 2117 stat & 0xff); 2118 break; 2119 } 2120 } 2121 wrt_reg_dword(®->host_int, 0); 2122 } while (0); 2123 2124 qla2x00_handle_mbx_completion(ha, status); 2125 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2126 2127 return IRQ_HANDLED; 2128 } 2129 2130 irqreturn_t 2131 qla82xx_msix_rsp_q(int irq, void *dev_id) 2132 { 2133 scsi_qla_host_t *vha; 2134 struct qla_hw_data *ha; 2135 struct rsp_que *rsp; 2136 struct device_reg_82xx __iomem *reg; 2137 unsigned long flags; 2138 uint32_t host_int = 0; 2139 2140 rsp = (struct rsp_que *) dev_id; 2141 if (!rsp) { 2142 printk(KERN_INFO 2143 "%s(): NULL response queue pointer.\n", __func__); 2144 return IRQ_NONE; 2145 } 2146 2147 ha = rsp->hw; 2148 reg = &ha->iobase->isp82; 2149 spin_lock_irqsave(&ha->hardware_lock, flags); 2150 vha = pci_get_drvdata(ha->pdev); 2151 host_int = rd_reg_dword(®->host_int); 2152 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2153 goto out; 2154 qla24xx_process_response_queue(vha, rsp); 2155 wrt_reg_dword(®->host_int, 0); 2156 out: 2157 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2158 return IRQ_HANDLED; 2159 } 2160 2161 void 2162 qla82xx_poll(int irq, void *dev_id) 2163 { 2164 scsi_qla_host_t *vha; 2165 struct qla_hw_data *ha; 2166 struct rsp_que *rsp; 2167 struct device_reg_82xx __iomem *reg; 2168 int status = 0; 2169 uint32_t stat; 2170 uint32_t host_int = 0; 2171 uint16_t mb[8]; 2172 unsigned long flags; 2173 2174 rsp = (struct rsp_que *) dev_id; 2175 if (!rsp) { 2176 printk(KERN_INFO 2177 "%s(): NULL response queue pointer.\n", __func__); 2178 return; 2179 } 2180 ha = rsp->hw; 2181 2182 reg = &ha->iobase->isp82; 2183 spin_lock_irqsave(&ha->hardware_lock, flags); 2184 vha = pci_get_drvdata(ha->pdev); 2185 2186 host_int = rd_reg_dword(®->host_int); 2187 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2188 goto out; 2189 if (host_int) { 2190 stat = rd_reg_dword(®->host_status); 2191 switch (stat & 0xff) { 2192 case 0x1: 2193 case 0x2: 2194 case 0x10: 2195 case 0x11: 2196 qla82xx_mbx_completion(vha, MSW(stat)); 2197 status |= MBX_INTERRUPT; 2198 break; 2199 case 0x12: 2200 mb[0] = MSW(stat); 2201 mb[1] = rd_reg_word(®->mailbox_out[1]); 2202 mb[2] = rd_reg_word(®->mailbox_out[2]); 2203 mb[3] = rd_reg_word(®->mailbox_out[3]); 2204 qla2x00_async_event(vha, rsp, mb); 2205 break; 2206 case 0x13: 2207 qla24xx_process_response_queue(vha, rsp); 2208 break; 2209 default: 2210 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2211 "Unrecognized interrupt type (%d).\n", 2212 stat * 0xff); 2213 break; 2214 } 2215 wrt_reg_dword(®->host_int, 0); 2216 } 2217 out: 2218 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2219 } 2220 2221 void 2222 qla82xx_enable_intrs(struct qla_hw_data *ha) 2223 { 2224 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2225 2226 qla82xx_mbx_intr_enable(vha); 2227 spin_lock_irq(&ha->hardware_lock); 2228 if (IS_QLA8044(ha)) 2229 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2230 else 2231 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2232 spin_unlock_irq(&ha->hardware_lock); 2233 ha->interrupts_on = 1; 2234 } 2235 2236 void 2237 qla82xx_disable_intrs(struct qla_hw_data *ha) 2238 { 2239 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2240 2241 if (ha->interrupts_on) 2242 qla82xx_mbx_intr_disable(vha); 2243 2244 spin_lock_irq(&ha->hardware_lock); 2245 if (IS_QLA8044(ha)) 2246 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2247 else 2248 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2249 spin_unlock_irq(&ha->hardware_lock); 2250 ha->interrupts_on = 0; 2251 } 2252 2253 void qla82xx_init_flags(struct qla_hw_data *ha) 2254 { 2255 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2256 2257 /* ISP 8021 initializations */ 2258 rwlock_init(&ha->hw_lock); 2259 ha->qdr_sn_window = -1; 2260 ha->ddr_mn_window = -1; 2261 ha->curr_window = 255; 2262 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2263 nx_legacy_intr = &legacy_intr[ha->portnum]; 2264 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2265 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2266 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2267 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2268 } 2269 2270 static inline void 2271 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2272 { 2273 int idc_ver; 2274 uint32_t drv_active; 2275 struct qla_hw_data *ha = vha->hw; 2276 2277 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2278 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2279 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2280 QLA82XX_IDC_VERSION); 2281 ql_log(ql_log_info, vha, 0xb082, 2282 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2283 } else { 2284 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2285 if (idc_ver != QLA82XX_IDC_VERSION) 2286 ql_log(ql_log_info, vha, 0xb083, 2287 "qla2xxx driver IDC version %d is not compatible " 2288 "with IDC version %d of the other drivers\n", 2289 QLA82XX_IDC_VERSION, idc_ver); 2290 } 2291 } 2292 2293 inline void 2294 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2295 { 2296 uint32_t drv_active; 2297 struct qla_hw_data *ha = vha->hw; 2298 2299 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2300 2301 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2302 if (drv_active == 0xffffffff) { 2303 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2304 QLA82XX_DRV_NOT_ACTIVE); 2305 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2306 } 2307 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2308 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2309 } 2310 2311 inline void 2312 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2313 { 2314 uint32_t drv_active; 2315 2316 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2317 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2318 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2319 } 2320 2321 static inline int 2322 qla82xx_need_reset(struct qla_hw_data *ha) 2323 { 2324 uint32_t drv_state; 2325 int rval; 2326 2327 if (ha->flags.nic_core_reset_owner) 2328 return 1; 2329 else { 2330 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2331 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2332 return rval; 2333 } 2334 } 2335 2336 static inline void 2337 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2338 { 2339 uint32_t drv_state; 2340 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2341 2342 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2343 2344 /* If reset value is all FF's, initialize DRV_STATE */ 2345 if (drv_state == 0xffffffff) { 2346 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2347 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2348 } 2349 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2350 ql_dbg(ql_dbg_init, vha, 0x00bb, 2351 "drv_state = 0x%08x.\n", drv_state); 2352 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2353 } 2354 2355 static inline void 2356 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2357 { 2358 uint32_t drv_state; 2359 2360 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2361 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2362 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2363 } 2364 2365 static inline void 2366 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2367 { 2368 uint32_t qsnt_state; 2369 2370 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2371 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2372 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2373 } 2374 2375 void 2376 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2377 { 2378 struct qla_hw_data *ha = vha->hw; 2379 uint32_t qsnt_state; 2380 2381 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2384 } 2385 2386 static int 2387 qla82xx_load_fw(scsi_qla_host_t *vha) 2388 { 2389 int rst; 2390 struct fw_blob *blob; 2391 struct qla_hw_data *ha = vha->hw; 2392 2393 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2394 ql_log(ql_log_fatal, vha, 0x009f, 2395 "Error during CRB initialization.\n"); 2396 return QLA_FUNCTION_FAILED; 2397 } 2398 udelay(500); 2399 2400 /* Bring QM and CAMRAM out of reset */ 2401 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2402 rst &= ~((1 << 28) | (1 << 24)); 2403 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2404 2405 /* 2406 * FW Load priority: 2407 * 1) Operational firmware residing in flash. 2408 * 2) Firmware via request-firmware interface (.bin file). 2409 */ 2410 if (ql2xfwloadbin == 2) 2411 goto try_blob_fw; 2412 2413 ql_log(ql_log_info, vha, 0x00a0, 2414 "Attempting to load firmware from flash.\n"); 2415 2416 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2417 ql_log(ql_log_info, vha, 0x00a1, 2418 "Firmware loaded successfully from flash.\n"); 2419 return QLA_SUCCESS; 2420 } else { 2421 ql_log(ql_log_warn, vha, 0x0108, 2422 "Firmware load from flash failed.\n"); 2423 } 2424 2425 try_blob_fw: 2426 ql_log(ql_log_info, vha, 0x00a2, 2427 "Attempting to load firmware from blob.\n"); 2428 2429 /* Load firmware blob. */ 2430 blob = ha->hablob = qla2x00_request_firmware(vha); 2431 if (!blob) { 2432 ql_log(ql_log_fatal, vha, 0x00a3, 2433 "Firmware image not present.\n"); 2434 goto fw_load_failed; 2435 } 2436 2437 /* Validating firmware blob */ 2438 if (qla82xx_validate_firmware_blob(vha, 2439 QLA82XX_FLASH_ROMIMAGE)) { 2440 /* Fallback to URI format */ 2441 if (qla82xx_validate_firmware_blob(vha, 2442 QLA82XX_UNIFIED_ROMIMAGE)) { 2443 ql_log(ql_log_fatal, vha, 0x00a4, 2444 "No valid firmware image found.\n"); 2445 return QLA_FUNCTION_FAILED; 2446 } 2447 } 2448 2449 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2450 ql_log(ql_log_info, vha, 0x00a5, 2451 "Firmware loaded successfully from binary blob.\n"); 2452 return QLA_SUCCESS; 2453 } 2454 2455 ql_log(ql_log_fatal, vha, 0x00a6, 2456 "Firmware load failed for binary blob.\n"); 2457 blob->fw = NULL; 2458 blob = NULL; 2459 2460 fw_load_failed: 2461 return QLA_FUNCTION_FAILED; 2462 } 2463 2464 int 2465 qla82xx_start_firmware(scsi_qla_host_t *vha) 2466 { 2467 uint16_t lnk; 2468 struct qla_hw_data *ha = vha->hw; 2469 2470 /* scrub dma mask expansion register */ 2471 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2472 2473 /* Put both the PEG CMD and RCV PEG to default state 2474 * of 0 before resetting the hardware 2475 */ 2476 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2477 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2478 2479 /* Overwrite stale initialization register values */ 2480 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2481 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2482 2483 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2484 ql_log(ql_log_fatal, vha, 0x00a7, 2485 "Error trying to start fw.\n"); 2486 return QLA_FUNCTION_FAILED; 2487 } 2488 2489 /* Handshake with the card before we register the devices. */ 2490 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2491 ql_log(ql_log_fatal, vha, 0x00aa, 2492 "Error during card handshake.\n"); 2493 return QLA_FUNCTION_FAILED; 2494 } 2495 2496 /* Negotiated Link width */ 2497 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2498 ha->link_width = (lnk >> 4) & 0x3f; 2499 2500 /* Synchronize with Receive peg */ 2501 return qla82xx_check_rcvpeg_state(ha); 2502 } 2503 2504 static __le32 * 2505 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 2506 uint32_t length) 2507 { 2508 uint32_t i; 2509 uint32_t val; 2510 struct qla_hw_data *ha = vha->hw; 2511 2512 /* Dword reads to flash. */ 2513 for (i = 0; i < length/4; i++, faddr += 4) { 2514 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2515 ql_log(ql_log_warn, vha, 0x0106, 2516 "Do ROM fast read failed.\n"); 2517 goto done_read; 2518 } 2519 dwptr[i] = cpu_to_le32(val); 2520 } 2521 done_read: 2522 return dwptr; 2523 } 2524 2525 static int 2526 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2527 { 2528 int ret; 2529 uint32_t val; 2530 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2531 2532 ret = ql82xx_rom_lock_d(ha); 2533 if (ret < 0) { 2534 ql_log(ql_log_warn, vha, 0xb014, 2535 "ROM Lock failed.\n"); 2536 return ret; 2537 } 2538 2539 ret = qla82xx_read_status_reg(ha, &val); 2540 if (ret < 0) 2541 goto done_unprotect; 2542 2543 val &= ~(BLOCK_PROTECT_BITS << 2); 2544 ret = qla82xx_write_status_reg(ha, val); 2545 if (ret < 0) { 2546 val |= (BLOCK_PROTECT_BITS << 2); 2547 qla82xx_write_status_reg(ha, val); 2548 } 2549 2550 if (qla82xx_write_disable_flash(ha) != 0) 2551 ql_log(ql_log_warn, vha, 0xb015, 2552 "Write disable failed.\n"); 2553 2554 done_unprotect: 2555 qla82xx_rom_unlock(ha); 2556 return ret; 2557 } 2558 2559 static int 2560 qla82xx_protect_flash(struct qla_hw_data *ha) 2561 { 2562 int ret; 2563 uint32_t val; 2564 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2565 2566 ret = ql82xx_rom_lock_d(ha); 2567 if (ret < 0) { 2568 ql_log(ql_log_warn, vha, 0xb016, 2569 "ROM Lock failed.\n"); 2570 return ret; 2571 } 2572 2573 ret = qla82xx_read_status_reg(ha, &val); 2574 if (ret < 0) 2575 goto done_protect; 2576 2577 val |= (BLOCK_PROTECT_BITS << 2); 2578 /* LOCK all sectors */ 2579 ret = qla82xx_write_status_reg(ha, val); 2580 if (ret < 0) 2581 ql_log(ql_log_warn, vha, 0xb017, 2582 "Write status register failed.\n"); 2583 2584 if (qla82xx_write_disable_flash(ha) != 0) 2585 ql_log(ql_log_warn, vha, 0xb018, 2586 "Write disable failed.\n"); 2587 done_protect: 2588 qla82xx_rom_unlock(ha); 2589 return ret; 2590 } 2591 2592 static int 2593 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2594 { 2595 int ret = 0; 2596 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2597 2598 ret = ql82xx_rom_lock_d(ha); 2599 if (ret < 0) { 2600 ql_log(ql_log_warn, vha, 0xb019, 2601 "ROM Lock failed.\n"); 2602 return ret; 2603 } 2604 2605 qla82xx_flash_set_write_enable(ha); 2606 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2607 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2608 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2609 2610 if (qla82xx_wait_rom_done(ha)) { 2611 ql_log(ql_log_warn, vha, 0xb01a, 2612 "Error waiting for rom done.\n"); 2613 ret = -1; 2614 goto done; 2615 } 2616 ret = qla82xx_flash_wait_write_finish(ha); 2617 done: 2618 qla82xx_rom_unlock(ha); 2619 return ret; 2620 } 2621 2622 /* 2623 * Address and length are byte address 2624 */ 2625 void * 2626 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2627 uint32_t offset, uint32_t length) 2628 { 2629 scsi_block_requests(vha->host); 2630 qla82xx_read_flash_data(vha, buf, offset, length); 2631 scsi_unblock_requests(vha->host); 2632 return buf; 2633 } 2634 2635 static int 2636 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr, 2637 uint32_t faddr, uint32_t dwords) 2638 { 2639 int ret; 2640 uint32_t liter; 2641 uint32_t rest_addr; 2642 dma_addr_t optrom_dma; 2643 void *optrom = NULL; 2644 int page_mode = 0; 2645 struct qla_hw_data *ha = vha->hw; 2646 2647 ret = -1; 2648 2649 /* Prepare burst-capable write on supported ISPs. */ 2650 if (page_mode && !(faddr & 0xfff) && 2651 dwords > OPTROM_BURST_DWORDS) { 2652 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2653 &optrom_dma, GFP_KERNEL); 2654 if (!optrom) { 2655 ql_log(ql_log_warn, vha, 0xb01b, 2656 "Unable to allocate memory " 2657 "for optrom burst write (%x KB).\n", 2658 OPTROM_BURST_SIZE / 1024); 2659 } 2660 } 2661 2662 rest_addr = ha->fdt_block_size - 1; 2663 2664 ret = qla82xx_unprotect_flash(ha); 2665 if (ret) { 2666 ql_log(ql_log_warn, vha, 0xb01c, 2667 "Unable to unprotect flash for update.\n"); 2668 goto write_done; 2669 } 2670 2671 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2672 /* Are we at the beginning of a sector? */ 2673 if ((faddr & rest_addr) == 0) { 2674 2675 ret = qla82xx_erase_sector(ha, faddr); 2676 if (ret) { 2677 ql_log(ql_log_warn, vha, 0xb01d, 2678 "Unable to erase sector: address=%x.\n", 2679 faddr); 2680 break; 2681 } 2682 } 2683 2684 /* Go with burst-write. */ 2685 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2686 /* Copy data to DMA'ble buffer. */ 2687 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2688 2689 ret = qla2x00_load_ram(vha, optrom_dma, 2690 (ha->flash_data_off | faddr), 2691 OPTROM_BURST_DWORDS); 2692 if (ret != QLA_SUCCESS) { 2693 ql_log(ql_log_warn, vha, 0xb01e, 2694 "Unable to burst-write optrom segment " 2695 "(%x/%x/%llx).\n", ret, 2696 (ha->flash_data_off | faddr), 2697 (unsigned long long)optrom_dma); 2698 ql_log(ql_log_warn, vha, 0xb01f, 2699 "Reverting to slow-write.\n"); 2700 2701 dma_free_coherent(&ha->pdev->dev, 2702 OPTROM_BURST_SIZE, optrom, optrom_dma); 2703 optrom = NULL; 2704 } else { 2705 liter += OPTROM_BURST_DWORDS - 1; 2706 faddr += OPTROM_BURST_DWORDS - 1; 2707 dwptr += OPTROM_BURST_DWORDS - 1; 2708 continue; 2709 } 2710 } 2711 2712 ret = qla82xx_write_flash_dword(ha, faddr, 2713 le32_to_cpu(*dwptr)); 2714 if (ret) { 2715 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2716 "Unable to program flash address=%x data=%x.\n", 2717 faddr, *dwptr); 2718 break; 2719 } 2720 } 2721 2722 ret = qla82xx_protect_flash(ha); 2723 if (ret) 2724 ql_log(ql_log_warn, vha, 0xb021, 2725 "Unable to protect flash after update.\n"); 2726 write_done: 2727 if (optrom) 2728 dma_free_coherent(&ha->pdev->dev, 2729 OPTROM_BURST_SIZE, optrom, optrom_dma); 2730 return ret; 2731 } 2732 2733 int 2734 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2735 uint32_t offset, uint32_t length) 2736 { 2737 int rval; 2738 2739 /* Suspend HBA. */ 2740 scsi_block_requests(vha->host); 2741 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2742 scsi_unblock_requests(vha->host); 2743 2744 /* Convert return ISP82xx to generic */ 2745 if (rval) 2746 rval = QLA_FUNCTION_FAILED; 2747 else 2748 rval = QLA_SUCCESS; 2749 return rval; 2750 } 2751 2752 void 2753 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2754 { 2755 struct qla_hw_data *ha = vha->hw; 2756 struct req_que *req = ha->req_q_map[0]; 2757 uint32_t dbval; 2758 2759 /* Adjust ring index. */ 2760 req->ring_index++; 2761 if (req->ring_index == req->length) { 2762 req->ring_index = 0; 2763 req->ring_ptr = req->ring; 2764 } else 2765 req->ring_ptr++; 2766 2767 dbval = 0x04 | (ha->portnum << 5); 2768 2769 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2770 if (ql2xdbwr) 2771 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2772 else { 2773 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2774 wmb(); 2775 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { 2776 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2777 wmb(); 2778 } 2779 } 2780 } 2781 2782 static void 2783 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2784 { 2785 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2786 uint32_t lock_owner = 0; 2787 2788 if (qla82xx_rom_lock(ha)) { 2789 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2790 /* Someone else is holding the lock. */ 2791 ql_log(ql_log_info, vha, 0xb022, 2792 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2793 } 2794 /* 2795 * Either we got the lock, or someone 2796 * else died while holding it. 2797 * In either case, unlock. 2798 */ 2799 qla82xx_rom_unlock(ha); 2800 } 2801 2802 /* 2803 * qla82xx_device_bootstrap 2804 * Initialize device, set DEV_READY, start fw 2805 * 2806 * Note: 2807 * IDC lock must be held upon entry 2808 * 2809 * Return: 2810 * Success : 0 2811 * Failed : 1 2812 */ 2813 static int 2814 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2815 { 2816 int rval = QLA_SUCCESS; 2817 int i; 2818 uint32_t old_count, count; 2819 struct qla_hw_data *ha = vha->hw; 2820 int need_reset = 0; 2821 2822 need_reset = qla82xx_need_reset(ha); 2823 2824 if (need_reset) { 2825 /* We are trying to perform a recovery here. */ 2826 if (ha->flags.isp82xx_fw_hung) 2827 qla82xx_rom_lock_recovery(ha); 2828 } else { 2829 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2830 for (i = 0; i < 10; i++) { 2831 msleep(200); 2832 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2833 if (count != old_count) { 2834 rval = QLA_SUCCESS; 2835 goto dev_ready; 2836 } 2837 } 2838 qla82xx_rom_lock_recovery(ha); 2839 } 2840 2841 /* set to DEV_INITIALIZING */ 2842 ql_log(ql_log_info, vha, 0x009e, 2843 "HW State: INITIALIZING.\n"); 2844 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2845 2846 qla82xx_idc_unlock(ha); 2847 rval = qla82xx_start_firmware(vha); 2848 qla82xx_idc_lock(ha); 2849 2850 if (rval != QLA_SUCCESS) { 2851 ql_log(ql_log_fatal, vha, 0x00ad, 2852 "HW State: FAILED.\n"); 2853 qla82xx_clear_drv_active(ha); 2854 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2855 return rval; 2856 } 2857 2858 dev_ready: 2859 ql_log(ql_log_info, vha, 0x00ae, 2860 "HW State: READY.\n"); 2861 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2862 2863 return QLA_SUCCESS; 2864 } 2865 2866 /* 2867 * qla82xx_need_qsnt_handler 2868 * Code to start quiescence sequence 2869 * 2870 * Note: 2871 * IDC lock must be held upon entry 2872 * 2873 * Return: void 2874 */ 2875 2876 static void 2877 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2878 { 2879 struct qla_hw_data *ha = vha->hw; 2880 uint32_t dev_state, drv_state, drv_active; 2881 unsigned long reset_timeout; 2882 2883 if (vha->flags.online) { 2884 /*Block any further I/O and wait for pending cmnds to complete*/ 2885 qla2x00_quiesce_io(vha); 2886 } 2887 2888 /* Set the quiescence ready bit */ 2889 qla82xx_set_qsnt_ready(ha); 2890 2891 /*wait for 30 secs for other functions to ack */ 2892 reset_timeout = jiffies + (30 * HZ); 2893 2894 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2895 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2896 /* Its 2 that is written when qsnt is acked, moving one bit */ 2897 drv_active = drv_active << 0x01; 2898 2899 while (drv_state != drv_active) { 2900 2901 if (time_after_eq(jiffies, reset_timeout)) { 2902 /* quiescence timeout, other functions didn't ack 2903 * changing the state to DEV_READY 2904 */ 2905 ql_log(ql_log_info, vha, 0xb023, 2906 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2907 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2908 drv_active, drv_state); 2909 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2910 QLA8XXX_DEV_READY); 2911 ql_log(ql_log_info, vha, 0xb025, 2912 "HW State: DEV_READY.\n"); 2913 qla82xx_idc_unlock(ha); 2914 qla2x00_perform_loop_resync(vha); 2915 qla82xx_idc_lock(ha); 2916 2917 qla82xx_clear_qsnt_ready(vha); 2918 return; 2919 } 2920 2921 qla82xx_idc_unlock(ha); 2922 msleep(1000); 2923 qla82xx_idc_lock(ha); 2924 2925 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2926 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2927 drv_active = drv_active << 0x01; 2928 } 2929 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2930 /* everyone acked so set the state to DEV_QUIESCENCE */ 2931 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2932 ql_log(ql_log_info, vha, 0xb026, 2933 "HW State: DEV_QUIESCENT.\n"); 2934 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2935 } 2936 } 2937 2938 /* 2939 * qla82xx_wait_for_state_change 2940 * Wait for device state to change from given current state 2941 * 2942 * Note: 2943 * IDC lock must not be held upon entry 2944 * 2945 * Return: 2946 * Changed device state. 2947 */ 2948 uint32_t 2949 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2950 { 2951 struct qla_hw_data *ha = vha->hw; 2952 uint32_t dev_state; 2953 2954 do { 2955 msleep(1000); 2956 qla82xx_idc_lock(ha); 2957 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2958 qla82xx_idc_unlock(ha); 2959 } while (dev_state == curr_state); 2960 2961 return dev_state; 2962 } 2963 2964 void 2965 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2966 { 2967 struct qla_hw_data *ha = vha->hw; 2968 2969 /* Disable the board */ 2970 ql_log(ql_log_fatal, vha, 0x00b8, 2971 "Disabling the board.\n"); 2972 2973 if (IS_QLA82XX(ha)) { 2974 qla82xx_clear_drv_active(ha); 2975 qla82xx_idc_unlock(ha); 2976 } else if (IS_QLA8044(ha)) { 2977 qla8044_clear_drv_active(ha); 2978 qla8044_idc_unlock(ha); 2979 } 2980 2981 /* Set DEV_FAILED flag to disable timer */ 2982 vha->device_flags |= DFLG_DEV_FAILED; 2983 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2984 qla2x00_mark_all_devices_lost(vha); 2985 vha->flags.online = 0; 2986 vha->flags.init_done = 0; 2987 } 2988 2989 /* 2990 * qla82xx_need_reset_handler 2991 * Code to start reset sequence 2992 * 2993 * Note: 2994 * IDC lock must be held upon entry 2995 * 2996 * Return: 2997 * Success : 0 2998 * Failed : 1 2999 */ 3000 static void 3001 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3002 { 3003 uint32_t dev_state, drv_state, drv_active; 3004 uint32_t active_mask = 0; 3005 unsigned long reset_timeout; 3006 struct qla_hw_data *ha = vha->hw; 3007 struct req_que *req = ha->req_q_map[0]; 3008 3009 if (vha->flags.online) { 3010 qla82xx_idc_unlock(ha); 3011 qla2x00_abort_isp_cleanup(vha); 3012 ha->isp_ops->get_flash_version(vha, req->ring); 3013 ha->isp_ops->nvram_config(vha); 3014 qla82xx_idc_lock(ha); 3015 } 3016 3017 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3018 if (!ha->flags.nic_core_reset_owner) { 3019 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3020 "reset_acknowledged by 0x%x\n", ha->portnum); 3021 qla82xx_set_rst_ready(ha); 3022 } else { 3023 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3024 drv_active &= active_mask; 3025 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3026 "active_mask: 0x%08x\n", active_mask); 3027 } 3028 3029 /* wait for 10 seconds for reset ack from all functions */ 3030 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3031 3032 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3033 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3034 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3035 3036 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3037 "drv_state: 0x%08x, drv_active: 0x%08x, " 3038 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3039 drv_state, drv_active, dev_state, active_mask); 3040 3041 while (drv_state != drv_active && 3042 dev_state != QLA8XXX_DEV_INITIALIZING) { 3043 if (time_after_eq(jiffies, reset_timeout)) { 3044 ql_log(ql_log_warn, vha, 0x00b5, 3045 "Reset timeout.\n"); 3046 break; 3047 } 3048 qla82xx_idc_unlock(ha); 3049 msleep(1000); 3050 qla82xx_idc_lock(ha); 3051 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3052 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3053 if (ha->flags.nic_core_reset_owner) 3054 drv_active &= active_mask; 3055 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3056 } 3057 3058 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3059 "drv_state: 0x%08x, drv_active: 0x%08x, " 3060 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3061 drv_state, drv_active, dev_state, active_mask); 3062 3063 ql_log(ql_log_info, vha, 0x00b6, 3064 "Device state is 0x%x = %s.\n", 3065 dev_state, 3066 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3067 3068 /* Force to DEV_COLD unless someone else is starting a reset */ 3069 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3070 dev_state != QLA8XXX_DEV_COLD) { 3071 ql_log(ql_log_info, vha, 0x00b7, 3072 "HW State: COLD/RE-INIT.\n"); 3073 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3074 qla82xx_set_rst_ready(ha); 3075 if (ql2xmdenable) { 3076 if (qla82xx_md_collect(vha)) 3077 ql_log(ql_log_warn, vha, 0xb02c, 3078 "Minidump not collected.\n"); 3079 } else 3080 ql_log(ql_log_warn, vha, 0xb04f, 3081 "Minidump disabled.\n"); 3082 } 3083 } 3084 3085 int 3086 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3087 { 3088 struct qla_hw_data *ha = vha->hw; 3089 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3090 int rval = QLA_SUCCESS; 3091 3092 fw_major_version = ha->fw_major_version; 3093 fw_minor_version = ha->fw_minor_version; 3094 fw_subminor_version = ha->fw_subminor_version; 3095 3096 rval = qla2x00_get_fw_version(vha); 3097 if (rval != QLA_SUCCESS) 3098 return rval; 3099 3100 if (ql2xmdenable) { 3101 if (!ha->fw_dumped) { 3102 if ((fw_major_version != ha->fw_major_version || 3103 fw_minor_version != ha->fw_minor_version || 3104 fw_subminor_version != ha->fw_subminor_version) || 3105 (ha->prev_minidump_failed)) { 3106 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3107 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3108 fw_major_version, fw_minor_version, 3109 fw_subminor_version, 3110 ha->fw_major_version, 3111 ha->fw_minor_version, 3112 ha->fw_subminor_version, 3113 ha->prev_minidump_failed); 3114 /* Release MiniDump resources */ 3115 qla82xx_md_free(vha); 3116 /* ALlocate MiniDump resources */ 3117 qla82xx_md_prep(vha); 3118 } 3119 } else 3120 ql_log(ql_log_info, vha, 0xb02e, 3121 "Firmware dump available to retrieve\n"); 3122 } 3123 return rval; 3124 } 3125 3126 3127 static int 3128 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3129 { 3130 uint32_t fw_heartbeat_counter; 3131 int status = 0; 3132 3133 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3134 QLA82XX_PEG_ALIVE_COUNTER); 3135 /* all 0xff, assume AER/EEH in progress, ignore */ 3136 if (fw_heartbeat_counter == 0xffffffff) { 3137 ql_dbg(ql_dbg_timer, vha, 0x6003, 3138 "FW heartbeat counter is 0xffffffff, " 3139 "returning status=%d.\n", status); 3140 return status; 3141 } 3142 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3143 vha->seconds_since_last_heartbeat++; 3144 /* FW not alive after 2 seconds */ 3145 if (vha->seconds_since_last_heartbeat == 2) { 3146 vha->seconds_since_last_heartbeat = 0; 3147 status = 1; 3148 } 3149 } else 3150 vha->seconds_since_last_heartbeat = 0; 3151 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3152 if (status) 3153 ql_dbg(ql_dbg_timer, vha, 0x6004, 3154 "Returning status=%d.\n", status); 3155 return status; 3156 } 3157 3158 /* 3159 * qla82xx_device_state_handler 3160 * Main state handler 3161 * 3162 * Note: 3163 * IDC lock must be held upon entry 3164 * 3165 * Return: 3166 * Success : 0 3167 * Failed : 1 3168 */ 3169 int 3170 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3171 { 3172 uint32_t dev_state; 3173 uint32_t old_dev_state; 3174 int rval = QLA_SUCCESS; 3175 unsigned long dev_init_timeout; 3176 struct qla_hw_data *ha = vha->hw; 3177 int loopcount = 0; 3178 3179 qla82xx_idc_lock(ha); 3180 if (!vha->flags.init_done) { 3181 qla82xx_set_drv_active(vha); 3182 qla82xx_set_idc_version(vha); 3183 } 3184 3185 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3186 old_dev_state = dev_state; 3187 ql_log(ql_log_info, vha, 0x009b, 3188 "Device state is 0x%x = %s.\n", 3189 dev_state, 3190 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3191 3192 /* wait for 30 seconds for device to go ready */ 3193 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3194 3195 while (1) { 3196 3197 if (time_after_eq(jiffies, dev_init_timeout)) { 3198 ql_log(ql_log_fatal, vha, 0x009c, 3199 "Device init failed.\n"); 3200 rval = QLA_FUNCTION_FAILED; 3201 break; 3202 } 3203 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3204 if (old_dev_state != dev_state) { 3205 loopcount = 0; 3206 old_dev_state = dev_state; 3207 } 3208 if (loopcount < 5) { 3209 ql_log(ql_log_info, vha, 0x009d, 3210 "Device state is 0x%x = %s.\n", 3211 dev_state, 3212 dev_state < MAX_STATES ? qdev_state(dev_state) : 3213 "Unknown"); 3214 } 3215 3216 switch (dev_state) { 3217 case QLA8XXX_DEV_READY: 3218 ha->flags.nic_core_reset_owner = 0; 3219 goto rel_lock; 3220 case QLA8XXX_DEV_COLD: 3221 rval = qla82xx_device_bootstrap(vha); 3222 break; 3223 case QLA8XXX_DEV_INITIALIZING: 3224 qla82xx_idc_unlock(ha); 3225 msleep(1000); 3226 qla82xx_idc_lock(ha); 3227 break; 3228 case QLA8XXX_DEV_NEED_RESET: 3229 if (!ql2xdontresethba) 3230 qla82xx_need_reset_handler(vha); 3231 else { 3232 qla82xx_idc_unlock(ha); 3233 msleep(1000); 3234 qla82xx_idc_lock(ha); 3235 } 3236 dev_init_timeout = jiffies + 3237 (ha->fcoe_dev_init_timeout * HZ); 3238 break; 3239 case QLA8XXX_DEV_NEED_QUIESCENT: 3240 qla82xx_need_qsnt_handler(vha); 3241 /* Reset timeout value after quiescence handler */ 3242 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3243 * HZ); 3244 break; 3245 case QLA8XXX_DEV_QUIESCENT: 3246 /* Owner will exit and other will wait for the state 3247 * to get changed 3248 */ 3249 if (ha->flags.quiesce_owner) 3250 goto rel_lock; 3251 3252 qla82xx_idc_unlock(ha); 3253 msleep(1000); 3254 qla82xx_idc_lock(ha); 3255 3256 /* Reset timeout value after quiescence handler */ 3257 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3258 * HZ); 3259 break; 3260 case QLA8XXX_DEV_FAILED: 3261 qla8xxx_dev_failed_handler(vha); 3262 rval = QLA_FUNCTION_FAILED; 3263 goto exit; 3264 default: 3265 qla82xx_idc_unlock(ha); 3266 msleep(1000); 3267 qla82xx_idc_lock(ha); 3268 } 3269 loopcount++; 3270 } 3271 rel_lock: 3272 qla82xx_idc_unlock(ha); 3273 exit: 3274 return rval; 3275 } 3276 3277 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3278 { 3279 uint32_t temp, temp_state, temp_val; 3280 struct qla_hw_data *ha = vha->hw; 3281 3282 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3283 temp_state = qla82xx_get_temp_state(temp); 3284 temp_val = qla82xx_get_temp_val(temp); 3285 3286 if (temp_state == QLA82XX_TEMP_PANIC) { 3287 ql_log(ql_log_warn, vha, 0x600e, 3288 "Device temperature %d degrees C exceeds " 3289 " maximum allowed. Hardware has been shut down.\n", 3290 temp_val); 3291 return 1; 3292 } else if (temp_state == QLA82XX_TEMP_WARN) { 3293 ql_log(ql_log_warn, vha, 0x600f, 3294 "Device temperature %d degrees C exceeds " 3295 "operating range. Immediate action needed.\n", 3296 temp_val); 3297 } 3298 return 0; 3299 } 3300 3301 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3302 { 3303 uint32_t temp; 3304 3305 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3306 return qla82xx_get_temp_val(temp); 3307 } 3308 3309 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3310 { 3311 struct qla_hw_data *ha = vha->hw; 3312 3313 if (ha->flags.mbox_busy) { 3314 ha->flags.mbox_int = 1; 3315 ha->flags.mbox_busy = 0; 3316 ql_log(ql_log_warn, vha, 0x6010, 3317 "Doing premature completion of mbx command.\n"); 3318 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3319 complete(&ha->mbx_intr_comp); 3320 } 3321 } 3322 3323 void qla82xx_watchdog(scsi_qla_host_t *vha) 3324 { 3325 uint32_t dev_state, halt_status; 3326 struct qla_hw_data *ha = vha->hw; 3327 3328 /* don't poll if reset is going on */ 3329 if (!ha->flags.nic_core_reset_hdlr_active) { 3330 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3331 if (qla82xx_check_temp(vha)) { 3332 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3333 ha->flags.isp82xx_fw_hung = 1; 3334 qla82xx_clear_pending_mbx(vha); 3335 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3336 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3337 ql_log(ql_log_warn, vha, 0x6001, 3338 "Adapter reset needed.\n"); 3339 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3340 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3341 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3342 ql_log(ql_log_warn, vha, 0x6002, 3343 "Quiescent needed.\n"); 3344 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3345 } else if (dev_state == QLA8XXX_DEV_FAILED && 3346 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3347 vha->flags.online == 1) { 3348 ql_log(ql_log_warn, vha, 0xb055, 3349 "Adapter state is failed. Offlining.\n"); 3350 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3351 ha->flags.isp82xx_fw_hung = 1; 3352 qla82xx_clear_pending_mbx(vha); 3353 } else { 3354 if (qla82xx_check_fw_alive(vha)) { 3355 ql_dbg(ql_dbg_timer, vha, 0x6011, 3356 "disabling pause transmit on port 0 & 1.\n"); 3357 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3358 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3359 halt_status = qla82xx_rd_32(ha, 3360 QLA82XX_PEG_HALT_STATUS1); 3361 ql_log(ql_log_info, vha, 0x6005, 3362 "dumping hw/fw registers:.\n " 3363 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3364 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3365 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3366 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3367 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3368 qla82xx_rd_32(ha, 3369 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3370 qla82xx_rd_32(ha, 3371 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3372 qla82xx_rd_32(ha, 3373 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3374 qla82xx_rd_32(ha, 3375 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3376 qla82xx_rd_32(ha, 3377 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3378 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3379 ql_log(ql_log_warn, vha, 0xb052, 3380 "Firmware aborted with " 3381 "error code 0x00006700. Device is " 3382 "being reset.\n"); 3383 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3384 set_bit(ISP_UNRECOVERABLE, 3385 &vha->dpc_flags); 3386 } else { 3387 ql_log(ql_log_info, vha, 0x6006, 3388 "Detect abort needed.\n"); 3389 set_bit(ISP_ABORT_NEEDED, 3390 &vha->dpc_flags); 3391 } 3392 ha->flags.isp82xx_fw_hung = 1; 3393 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3394 qla82xx_clear_pending_mbx(vha); 3395 } 3396 } 3397 } 3398 } 3399 3400 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3401 { 3402 int rval = -1; 3403 struct qla_hw_data *ha = vha->hw; 3404 3405 if (IS_QLA82XX(ha)) 3406 rval = qla82xx_device_state_handler(vha); 3407 else if (IS_QLA8044(ha)) { 3408 qla8044_idc_lock(ha); 3409 /* Decide the reset ownership */ 3410 qla83xx_reset_ownership(vha); 3411 qla8044_idc_unlock(ha); 3412 rval = qla8044_device_state_handler(vha); 3413 } 3414 return rval; 3415 } 3416 3417 void 3418 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3419 { 3420 struct qla_hw_data *ha = vha->hw; 3421 uint32_t dev_state = 0; 3422 3423 if (IS_QLA82XX(ha)) 3424 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3425 else if (IS_QLA8044(ha)) 3426 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3427 3428 if (dev_state == QLA8XXX_DEV_READY) { 3429 ql_log(ql_log_info, vha, 0xb02f, 3430 "HW State: NEED RESET\n"); 3431 if (IS_QLA82XX(ha)) { 3432 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3433 QLA8XXX_DEV_NEED_RESET); 3434 ha->flags.nic_core_reset_owner = 1; 3435 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3436 "reset_owner is 0x%x\n", ha->portnum); 3437 } else if (IS_QLA8044(ha)) 3438 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3439 QLA8XXX_DEV_NEED_RESET); 3440 } else 3441 ql_log(ql_log_info, vha, 0xb031, 3442 "Device state is 0x%x = %s.\n", 3443 dev_state, 3444 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3445 } 3446 3447 /* 3448 * qla82xx_abort_isp 3449 * Resets ISP and aborts all outstanding commands. 3450 * 3451 * Input: 3452 * ha = adapter block pointer. 3453 * 3454 * Returns: 3455 * 0 = success 3456 */ 3457 int 3458 qla82xx_abort_isp(scsi_qla_host_t *vha) 3459 { 3460 int rval = -1; 3461 struct qla_hw_data *ha = vha->hw; 3462 3463 if (vha->device_flags & DFLG_DEV_FAILED) { 3464 ql_log(ql_log_warn, vha, 0x8024, 3465 "Device in failed state, exiting.\n"); 3466 return QLA_SUCCESS; 3467 } 3468 ha->flags.nic_core_reset_hdlr_active = 1; 3469 3470 qla82xx_idc_lock(ha); 3471 qla82xx_set_reset_owner(vha); 3472 qla82xx_idc_unlock(ha); 3473 3474 if (IS_QLA82XX(ha)) 3475 rval = qla82xx_device_state_handler(vha); 3476 else if (IS_QLA8044(ha)) { 3477 qla8044_idc_lock(ha); 3478 /* Decide the reset ownership */ 3479 qla83xx_reset_ownership(vha); 3480 qla8044_idc_unlock(ha); 3481 rval = qla8044_device_state_handler(vha); 3482 } 3483 3484 qla82xx_idc_lock(ha); 3485 qla82xx_clear_rst_ready(ha); 3486 qla82xx_idc_unlock(ha); 3487 3488 if (rval == QLA_SUCCESS) { 3489 ha->flags.isp82xx_fw_hung = 0; 3490 ha->flags.nic_core_reset_hdlr_active = 0; 3491 qla82xx_restart_isp(vha); 3492 } 3493 3494 if (rval) { 3495 vha->flags.online = 1; 3496 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3497 if (ha->isp_abort_cnt == 0) { 3498 ql_log(ql_log_warn, vha, 0x8027, 3499 "ISP error recover failed - board " 3500 "disabled.\n"); 3501 /* 3502 * The next call disables the board 3503 * completely. 3504 */ 3505 ha->isp_ops->reset_adapter(vha); 3506 vha->flags.online = 0; 3507 clear_bit(ISP_ABORT_RETRY, 3508 &vha->dpc_flags); 3509 rval = QLA_SUCCESS; 3510 } else { /* schedule another ISP abort */ 3511 ha->isp_abort_cnt--; 3512 ql_log(ql_log_warn, vha, 0x8036, 3513 "ISP abort - retry remaining %d.\n", 3514 ha->isp_abort_cnt); 3515 rval = QLA_FUNCTION_FAILED; 3516 } 3517 } else { 3518 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3519 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3520 "ISP error recovery - retrying (%d) more times.\n", 3521 ha->isp_abort_cnt); 3522 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3523 rval = QLA_FUNCTION_FAILED; 3524 } 3525 } 3526 return rval; 3527 } 3528 3529 /* 3530 * qla82xx_fcoe_ctx_reset 3531 * Perform a quick reset and aborts all outstanding commands. 3532 * This will only perform an FCoE context reset and avoids a full blown 3533 * chip reset. 3534 * 3535 * Input: 3536 * ha = adapter block pointer. 3537 * is_reset_path = flag for identifying the reset path. 3538 * 3539 * Returns: 3540 * 0 = success 3541 */ 3542 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3543 { 3544 int rval = QLA_FUNCTION_FAILED; 3545 3546 if (vha->flags.online) { 3547 /* Abort all outstanding commands, so as to be requeued later */ 3548 qla2x00_abort_isp_cleanup(vha); 3549 } 3550 3551 /* Stop currently executing firmware. 3552 * This will destroy existing FCoE context at the F/W end. 3553 */ 3554 qla2x00_try_to_stop_firmware(vha); 3555 3556 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3557 rval = qla82xx_restart_isp(vha); 3558 3559 return rval; 3560 } 3561 3562 /* 3563 * qla2x00_wait_for_fcoe_ctx_reset 3564 * Wait till the FCoE context is reset. 3565 * 3566 * Note: 3567 * Does context switching here. 3568 * Release SPIN_LOCK (if any) before calling this routine. 3569 * 3570 * Return: 3571 * Success (fcoe_ctx reset is done) : 0 3572 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3573 */ 3574 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3575 { 3576 int status = QLA_FUNCTION_FAILED; 3577 unsigned long wait_reset; 3578 3579 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3580 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3581 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3582 && time_before(jiffies, wait_reset)) { 3583 3584 set_current_state(TASK_UNINTERRUPTIBLE); 3585 schedule_timeout(HZ); 3586 3587 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3588 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3589 status = QLA_SUCCESS; 3590 break; 3591 } 3592 } 3593 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3594 "%s: status=%d.\n", __func__, status); 3595 3596 return status; 3597 } 3598 3599 void 3600 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3601 { 3602 int i, fw_state = 0; 3603 unsigned long flags; 3604 struct qla_hw_data *ha = vha->hw; 3605 3606 /* Check if 82XX firmware is alive or not 3607 * We may have arrived here from NEED_RESET 3608 * detection only 3609 */ 3610 if (!ha->flags.isp82xx_fw_hung) { 3611 for (i = 0; i < 2; i++) { 3612 msleep(1000); 3613 if (IS_QLA82XX(ha)) 3614 fw_state = qla82xx_check_fw_alive(vha); 3615 else if (IS_QLA8044(ha)) 3616 fw_state = qla8044_check_fw_alive(vha); 3617 if (fw_state) { 3618 ha->flags.isp82xx_fw_hung = 1; 3619 qla82xx_clear_pending_mbx(vha); 3620 break; 3621 } 3622 } 3623 } 3624 ql_dbg(ql_dbg_init, vha, 0x00b0, 3625 "Entered %s fw_hung=%d.\n", 3626 __func__, ha->flags.isp82xx_fw_hung); 3627 3628 /* Abort all commands gracefully if fw NOT hung */ 3629 if (!ha->flags.isp82xx_fw_hung) { 3630 int cnt, que; 3631 srb_t *sp; 3632 struct req_que *req; 3633 3634 spin_lock_irqsave(&ha->hardware_lock, flags); 3635 for (que = 0; que < ha->max_req_queues; que++) { 3636 req = ha->req_q_map[que]; 3637 if (!req) 3638 continue; 3639 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3640 sp = req->outstanding_cmds[cnt]; 3641 if (sp) { 3642 if ((!sp->u.scmd.crc_ctx || 3643 (sp->flags & 3644 SRB_FCP_CMND_DMA_VALID)) && 3645 !ha->flags.isp82xx_fw_hung) { 3646 spin_unlock_irqrestore( 3647 &ha->hardware_lock, flags); 3648 if (ha->isp_ops->abort_command(sp)) { 3649 ql_log(ql_log_info, vha, 3650 0x00b1, 3651 "mbx abort failed.\n"); 3652 } else { 3653 ql_log(ql_log_info, vha, 3654 0x00b2, 3655 "mbx abort success.\n"); 3656 } 3657 spin_lock_irqsave(&ha->hardware_lock, flags); 3658 } 3659 } 3660 } 3661 } 3662 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3663 3664 /* Wait for pending cmds (physical and virtual) to complete */ 3665 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3666 WAIT_HOST) == QLA_SUCCESS) { 3667 ql_dbg(ql_dbg_init, vha, 0x00b3, 3668 "Done wait for " 3669 "pending commands.\n"); 3670 } else { 3671 WARN_ON_ONCE(true); 3672 } 3673 } 3674 } 3675 3676 /* Minidump related functions */ 3677 static int 3678 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3679 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3680 { 3681 struct qla_hw_data *ha = vha->hw; 3682 struct qla82xx_md_entry_crb *crb_entry; 3683 uint32_t read_value, opcode, poll_time; 3684 uint32_t addr, index, crb_addr; 3685 unsigned long wtime; 3686 struct qla82xx_md_template_hdr *tmplt_hdr; 3687 uint32_t rval = QLA_SUCCESS; 3688 int i; 3689 3690 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3691 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3692 crb_addr = crb_entry->addr; 3693 3694 for (i = 0; i < crb_entry->op_count; i++) { 3695 opcode = crb_entry->crb_ctrl.opcode; 3696 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3697 qla82xx_md_rw_32(ha, crb_addr, 3698 crb_entry->value_1, 1); 3699 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3700 } 3701 3702 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3703 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3704 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3705 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3706 } 3707 3708 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3709 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3710 read_value &= crb_entry->value_2; 3711 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3712 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3713 read_value |= crb_entry->value_3; 3714 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3715 } 3716 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3717 } 3718 3719 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3720 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3721 read_value |= crb_entry->value_3; 3722 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3723 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3724 } 3725 3726 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3727 poll_time = crb_entry->crb_strd.poll_timeout; 3728 wtime = jiffies + poll_time; 3729 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3730 3731 do { 3732 if ((read_value & crb_entry->value_2) 3733 == crb_entry->value_1) 3734 break; 3735 else if (time_after_eq(jiffies, wtime)) { 3736 /* capturing dump failed */ 3737 rval = QLA_FUNCTION_FAILED; 3738 break; 3739 } else 3740 read_value = qla82xx_md_rw_32(ha, 3741 crb_addr, 0, 0); 3742 } while (1); 3743 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3744 } 3745 3746 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3747 if (crb_entry->crb_strd.state_index_a) { 3748 index = crb_entry->crb_strd.state_index_a; 3749 addr = tmplt_hdr->saved_state_array[index]; 3750 } else 3751 addr = crb_addr; 3752 3753 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3754 index = crb_entry->crb_ctrl.state_index_v; 3755 tmplt_hdr->saved_state_array[index] = read_value; 3756 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3757 } 3758 3759 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3760 if (crb_entry->crb_strd.state_index_a) { 3761 index = crb_entry->crb_strd.state_index_a; 3762 addr = tmplt_hdr->saved_state_array[index]; 3763 } else 3764 addr = crb_addr; 3765 3766 if (crb_entry->crb_ctrl.state_index_v) { 3767 index = crb_entry->crb_ctrl.state_index_v; 3768 read_value = 3769 tmplt_hdr->saved_state_array[index]; 3770 } else 3771 read_value = crb_entry->value_1; 3772 3773 qla82xx_md_rw_32(ha, addr, read_value, 1); 3774 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3775 } 3776 3777 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3778 index = crb_entry->crb_ctrl.state_index_v; 3779 read_value = tmplt_hdr->saved_state_array[index]; 3780 read_value <<= crb_entry->crb_ctrl.shl; 3781 read_value >>= crb_entry->crb_ctrl.shr; 3782 if (crb_entry->value_2) 3783 read_value &= crb_entry->value_2; 3784 read_value |= crb_entry->value_3; 3785 read_value += crb_entry->value_1; 3786 tmplt_hdr->saved_state_array[index] = read_value; 3787 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3788 } 3789 crb_addr += crb_entry->crb_strd.addr_stride; 3790 } 3791 return rval; 3792 } 3793 3794 static void 3795 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3796 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3797 { 3798 struct qla_hw_data *ha = vha->hw; 3799 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3800 struct qla82xx_md_entry_rdocm *ocm_hdr; 3801 __le32 *data_ptr = *d_ptr; 3802 3803 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3804 r_addr = ocm_hdr->read_addr; 3805 r_stride = ocm_hdr->read_addr_stride; 3806 loop_cnt = ocm_hdr->op_count; 3807 3808 for (i = 0; i < loop_cnt; i++) { 3809 r_value = rd_reg_dword(r_addr + ha->nx_pcibase); 3810 *data_ptr++ = cpu_to_le32(r_value); 3811 r_addr += r_stride; 3812 } 3813 *d_ptr = data_ptr; 3814 } 3815 3816 static void 3817 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3818 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3819 { 3820 struct qla_hw_data *ha = vha->hw; 3821 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3822 struct qla82xx_md_entry_mux *mux_hdr; 3823 __le32 *data_ptr = *d_ptr; 3824 3825 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3826 r_addr = mux_hdr->read_addr; 3827 s_addr = mux_hdr->select_addr; 3828 s_stride = mux_hdr->select_value_stride; 3829 s_value = mux_hdr->select_value; 3830 loop_cnt = mux_hdr->op_count; 3831 3832 for (i = 0; i < loop_cnt; i++) { 3833 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3834 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3835 *data_ptr++ = cpu_to_le32(s_value); 3836 *data_ptr++ = cpu_to_le32(r_value); 3837 s_value += s_stride; 3838 } 3839 *d_ptr = data_ptr; 3840 } 3841 3842 static void 3843 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3844 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3845 { 3846 struct qla_hw_data *ha = vha->hw; 3847 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3848 struct qla82xx_md_entry_crb *crb_hdr; 3849 __le32 *data_ptr = *d_ptr; 3850 3851 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3852 r_addr = crb_hdr->addr; 3853 r_stride = crb_hdr->crb_strd.addr_stride; 3854 loop_cnt = crb_hdr->op_count; 3855 3856 for (i = 0; i < loop_cnt; i++) { 3857 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3858 *data_ptr++ = cpu_to_le32(r_addr); 3859 *data_ptr++ = cpu_to_le32(r_value); 3860 r_addr += r_stride; 3861 } 3862 *d_ptr = data_ptr; 3863 } 3864 3865 static int 3866 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3867 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3868 { 3869 struct qla_hw_data *ha = vha->hw; 3870 uint32_t addr, r_addr, c_addr, t_r_addr; 3871 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3872 unsigned long p_wait, w_time, p_mask; 3873 uint32_t c_value_w, c_value_r; 3874 struct qla82xx_md_entry_cache *cache_hdr; 3875 int rval = QLA_FUNCTION_FAILED; 3876 __le32 *data_ptr = *d_ptr; 3877 3878 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3879 loop_count = cache_hdr->op_count; 3880 r_addr = cache_hdr->read_addr; 3881 c_addr = cache_hdr->control_addr; 3882 c_value_w = cache_hdr->cache_ctrl.write_value; 3883 3884 t_r_addr = cache_hdr->tag_reg_addr; 3885 t_value = cache_hdr->addr_ctrl.init_tag_value; 3886 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3887 p_wait = cache_hdr->cache_ctrl.poll_wait; 3888 p_mask = cache_hdr->cache_ctrl.poll_mask; 3889 3890 for (i = 0; i < loop_count; i++) { 3891 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3892 if (c_value_w) 3893 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3894 3895 if (p_mask) { 3896 w_time = jiffies + p_wait; 3897 do { 3898 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3899 if ((c_value_r & p_mask) == 0) 3900 break; 3901 else if (time_after_eq(jiffies, w_time)) { 3902 /* capturing dump failed */ 3903 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3904 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3905 "w_time: 0x%lx\n", 3906 c_value_r, p_mask, w_time); 3907 return rval; 3908 } 3909 } while (1); 3910 } 3911 3912 addr = r_addr; 3913 for (k = 0; k < r_cnt; k++) { 3914 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3915 *data_ptr++ = cpu_to_le32(r_value); 3916 addr += cache_hdr->read_ctrl.read_addr_stride; 3917 } 3918 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3919 } 3920 *d_ptr = data_ptr; 3921 return QLA_SUCCESS; 3922 } 3923 3924 static void 3925 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3926 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3927 { 3928 struct qla_hw_data *ha = vha->hw; 3929 uint32_t addr, r_addr, c_addr, t_r_addr; 3930 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3931 uint32_t c_value_w; 3932 struct qla82xx_md_entry_cache *cache_hdr; 3933 __le32 *data_ptr = *d_ptr; 3934 3935 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3936 loop_count = cache_hdr->op_count; 3937 r_addr = cache_hdr->read_addr; 3938 c_addr = cache_hdr->control_addr; 3939 c_value_w = cache_hdr->cache_ctrl.write_value; 3940 3941 t_r_addr = cache_hdr->tag_reg_addr; 3942 t_value = cache_hdr->addr_ctrl.init_tag_value; 3943 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3944 3945 for (i = 0; i < loop_count; i++) { 3946 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3947 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3948 addr = r_addr; 3949 for (k = 0; k < r_cnt; k++) { 3950 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3951 *data_ptr++ = cpu_to_le32(r_value); 3952 addr += cache_hdr->read_ctrl.read_addr_stride; 3953 } 3954 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3955 } 3956 *d_ptr = data_ptr; 3957 } 3958 3959 static void 3960 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3961 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3962 { 3963 struct qla_hw_data *ha = vha->hw; 3964 uint32_t s_addr, r_addr; 3965 uint32_t r_stride, r_value, r_cnt, qid = 0; 3966 uint32_t i, k, loop_cnt; 3967 struct qla82xx_md_entry_queue *q_hdr; 3968 __le32 *data_ptr = *d_ptr; 3969 3970 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3971 s_addr = q_hdr->select_addr; 3972 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3973 r_stride = q_hdr->rd_strd.read_addr_stride; 3974 loop_cnt = q_hdr->op_count; 3975 3976 for (i = 0; i < loop_cnt; i++) { 3977 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3978 r_addr = q_hdr->read_addr; 3979 for (k = 0; k < r_cnt; k++) { 3980 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3981 *data_ptr++ = cpu_to_le32(r_value); 3982 r_addr += r_stride; 3983 } 3984 qid += q_hdr->q_strd.queue_id_stride; 3985 } 3986 *d_ptr = data_ptr; 3987 } 3988 3989 static void 3990 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3991 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3992 { 3993 struct qla_hw_data *ha = vha->hw; 3994 uint32_t r_addr, r_value; 3995 uint32_t i, loop_cnt; 3996 struct qla82xx_md_entry_rdrom *rom_hdr; 3997 __le32 *data_ptr = *d_ptr; 3998 3999 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4000 r_addr = rom_hdr->read_addr; 4001 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4002 4003 for (i = 0; i < loop_cnt; i++) { 4004 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4005 (r_addr & 0xFFFF0000), 1); 4006 r_value = qla82xx_md_rw_32(ha, 4007 MD_DIRECT_ROM_READ_BASE + 4008 (r_addr & 0x0000FFFF), 0, 0); 4009 *data_ptr++ = cpu_to_le32(r_value); 4010 r_addr += sizeof(uint32_t); 4011 } 4012 *d_ptr = data_ptr; 4013 } 4014 4015 static int 4016 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4017 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 4018 { 4019 struct qla_hw_data *ha = vha->hw; 4020 uint32_t r_addr, r_value, r_data; 4021 uint32_t i, j, loop_cnt; 4022 struct qla82xx_md_entry_rdmem *m_hdr; 4023 unsigned long flags; 4024 int rval = QLA_FUNCTION_FAILED; 4025 __le32 *data_ptr = *d_ptr; 4026 4027 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4028 r_addr = m_hdr->read_addr; 4029 loop_cnt = m_hdr->read_data_size/16; 4030 4031 if (r_addr & 0xf) { 4032 ql_log(ql_log_warn, vha, 0xb033, 4033 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4034 return rval; 4035 } 4036 4037 if (m_hdr->read_data_size % 16) { 4038 ql_log(ql_log_warn, vha, 0xb034, 4039 "Read data[0x%x] not multiple of 16 bytes\n", 4040 m_hdr->read_data_size); 4041 return rval; 4042 } 4043 4044 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4045 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4046 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4047 4048 write_lock_irqsave(&ha->hw_lock, flags); 4049 for (i = 0; i < loop_cnt; i++) { 4050 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4051 r_value = 0; 4052 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4053 r_value = MIU_TA_CTL_ENABLE; 4054 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4055 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4056 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4057 4058 for (j = 0; j < MAX_CTL_CHECK; j++) { 4059 r_value = qla82xx_md_rw_32(ha, 4060 MD_MIU_TEST_AGT_CTRL, 0, 0); 4061 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4062 break; 4063 } 4064 4065 if (j >= MAX_CTL_CHECK) { 4066 printk_ratelimited(KERN_ERR 4067 "failed to read through agent\n"); 4068 write_unlock_irqrestore(&ha->hw_lock, flags); 4069 return rval; 4070 } 4071 4072 for (j = 0; j < 4; j++) { 4073 r_data = qla82xx_md_rw_32(ha, 4074 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4075 *data_ptr++ = cpu_to_le32(r_data); 4076 } 4077 r_addr += 16; 4078 } 4079 write_unlock_irqrestore(&ha->hw_lock, flags); 4080 *d_ptr = data_ptr; 4081 return QLA_SUCCESS; 4082 } 4083 4084 int 4085 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4086 { 4087 struct qla_hw_data *ha = vha->hw; 4088 uint64_t chksum = 0; 4089 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4090 int count = ha->md_template_size/sizeof(uint32_t); 4091 4092 while (count-- > 0) 4093 chksum += *d_ptr++; 4094 while (chksum >> 32) 4095 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4096 return ~chksum; 4097 } 4098 4099 static void 4100 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4101 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4102 { 4103 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4104 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4105 "Skipping entry[%d]: " 4106 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4107 index, entry_hdr->entry_type, 4108 entry_hdr->d_ctrl.entry_capture_mask); 4109 } 4110 4111 int 4112 qla82xx_md_collect(scsi_qla_host_t *vha) 4113 { 4114 struct qla_hw_data *ha = vha->hw; 4115 int no_entry_hdr = 0; 4116 qla82xx_md_entry_hdr_t *entry_hdr; 4117 struct qla82xx_md_template_hdr *tmplt_hdr; 4118 __le32 *data_ptr; 4119 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4120 int i = 0, rval = QLA_FUNCTION_FAILED; 4121 4122 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4123 data_ptr = ha->md_dump; 4124 4125 if (ha->fw_dumped) { 4126 ql_log(ql_log_warn, vha, 0xb037, 4127 "Firmware has been previously dumped (%p) " 4128 "-- ignoring request.\n", ha->fw_dump); 4129 goto md_failed; 4130 } 4131 4132 ha->fw_dumped = false; 4133 4134 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4135 ql_log(ql_log_warn, vha, 0xb038, 4136 "Memory not allocated for minidump capture\n"); 4137 goto md_failed; 4138 } 4139 4140 if (ha->flags.isp82xx_no_md_cap) { 4141 ql_log(ql_log_warn, vha, 0xb054, 4142 "Forced reset from application, " 4143 "ignore minidump capture\n"); 4144 ha->flags.isp82xx_no_md_cap = 0; 4145 goto md_failed; 4146 } 4147 4148 if (qla82xx_validate_template_chksum(vha)) { 4149 ql_log(ql_log_info, vha, 0xb039, 4150 "Template checksum validation error\n"); 4151 goto md_failed; 4152 } 4153 4154 no_entry_hdr = tmplt_hdr->num_of_entries; 4155 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4156 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4157 4158 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4159 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4160 4161 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4162 4163 /* Validate whether required debug level is set */ 4164 if ((f_capture_mask & 0x3) != 0x3) { 4165 ql_log(ql_log_warn, vha, 0xb03c, 4166 "Minimum required capture mask[0x%x] level not set\n", 4167 f_capture_mask); 4168 goto md_failed; 4169 } 4170 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4171 4172 tmplt_hdr->driver_info[0] = vha->host_no; 4173 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4174 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4175 QLA_DRIVER_BETA_VER; 4176 4177 total_data_size = ha->md_dump_size; 4178 4179 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4180 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4181 4182 /* Check whether template obtained is valid */ 4183 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4184 ql_log(ql_log_warn, vha, 0xb04e, 4185 "Bad template header entry type: 0x%x obtained\n", 4186 tmplt_hdr->entry_type); 4187 goto md_failed; 4188 } 4189 4190 entry_hdr = (qla82xx_md_entry_hdr_t *) 4191 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4192 4193 /* Walk through the entry headers */ 4194 for (i = 0; i < no_entry_hdr; i++) { 4195 4196 if (data_collected > total_data_size) { 4197 ql_log(ql_log_warn, vha, 0xb03e, 4198 "More MiniDump data collected: [0x%x]\n", 4199 data_collected); 4200 goto md_failed; 4201 } 4202 4203 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4204 ql2xmdcapmask)) { 4205 entry_hdr->d_ctrl.driver_flags |= 4206 QLA82XX_DBG_SKIPPED_FLAG; 4207 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4208 "Skipping entry[%d]: " 4209 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4210 i, entry_hdr->entry_type, 4211 entry_hdr->d_ctrl.entry_capture_mask); 4212 goto skip_nxt_entry; 4213 } 4214 4215 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4216 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4217 "entry_type: 0x%x, capture_mask: 0x%x\n", 4218 __func__, i, data_ptr, entry_hdr, 4219 entry_hdr->entry_type, 4220 entry_hdr->d_ctrl.entry_capture_mask); 4221 4222 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4223 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4224 data_collected, (ha->md_dump_size - data_collected)); 4225 4226 /* Decode the entry type and take 4227 * required action to capture debug data */ 4228 switch (entry_hdr->entry_type) { 4229 case QLA82XX_RDEND: 4230 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4231 break; 4232 case QLA82XX_CNTRL: 4233 rval = qla82xx_minidump_process_control(vha, 4234 entry_hdr, &data_ptr); 4235 if (rval != QLA_SUCCESS) { 4236 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4237 goto md_failed; 4238 } 4239 break; 4240 case QLA82XX_RDCRB: 4241 qla82xx_minidump_process_rdcrb(vha, 4242 entry_hdr, &data_ptr); 4243 break; 4244 case QLA82XX_RDMEM: 4245 rval = qla82xx_minidump_process_rdmem(vha, 4246 entry_hdr, &data_ptr); 4247 if (rval != QLA_SUCCESS) { 4248 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4249 goto md_failed; 4250 } 4251 break; 4252 case QLA82XX_BOARD: 4253 case QLA82XX_RDROM: 4254 qla82xx_minidump_process_rdrom(vha, 4255 entry_hdr, &data_ptr); 4256 break; 4257 case QLA82XX_L2DTG: 4258 case QLA82XX_L2ITG: 4259 case QLA82XX_L2DAT: 4260 case QLA82XX_L2INS: 4261 rval = qla82xx_minidump_process_l2tag(vha, 4262 entry_hdr, &data_ptr); 4263 if (rval != QLA_SUCCESS) { 4264 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4265 goto md_failed; 4266 } 4267 break; 4268 case QLA82XX_L1DAT: 4269 case QLA82XX_L1INS: 4270 qla82xx_minidump_process_l1cache(vha, 4271 entry_hdr, &data_ptr); 4272 break; 4273 case QLA82XX_RDOCM: 4274 qla82xx_minidump_process_rdocm(vha, 4275 entry_hdr, &data_ptr); 4276 break; 4277 case QLA82XX_RDMUX: 4278 qla82xx_minidump_process_rdmux(vha, 4279 entry_hdr, &data_ptr); 4280 break; 4281 case QLA82XX_QUEUE: 4282 qla82xx_minidump_process_queue(vha, 4283 entry_hdr, &data_ptr); 4284 break; 4285 case QLA82XX_RDNOP: 4286 default: 4287 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4288 break; 4289 } 4290 4291 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4292 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4293 4294 data_collected = (uint8_t *)data_ptr - 4295 (uint8_t *)ha->md_dump; 4296 skip_nxt_entry: 4297 entry_hdr = (qla82xx_md_entry_hdr_t *) 4298 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4299 } 4300 4301 if (data_collected != total_data_size) { 4302 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4303 "MiniDump data mismatch: Data collected: [0x%x]," 4304 "total_data_size:[0x%x]\n", 4305 data_collected, total_data_size); 4306 goto md_failed; 4307 } 4308 4309 ql_log(ql_log_info, vha, 0xb044, 4310 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4311 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4312 ha->fw_dumped = true; 4313 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4314 4315 md_failed: 4316 return rval; 4317 } 4318 4319 int 4320 qla82xx_md_alloc(scsi_qla_host_t *vha) 4321 { 4322 struct qla_hw_data *ha = vha->hw; 4323 int i, k; 4324 struct qla82xx_md_template_hdr *tmplt_hdr; 4325 4326 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4327 4328 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4329 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4330 ql_log(ql_log_info, vha, 0xb045, 4331 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4332 ql2xmdcapmask); 4333 } 4334 4335 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4336 if (i & ql2xmdcapmask) 4337 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4338 } 4339 4340 if (ha->md_dump) { 4341 ql_log(ql_log_warn, vha, 0xb046, 4342 "Firmware dump previously allocated.\n"); 4343 return 1; 4344 } 4345 4346 ha->md_dump = vmalloc(ha->md_dump_size); 4347 if (ha->md_dump == NULL) { 4348 ql_log(ql_log_warn, vha, 0xb047, 4349 "Unable to allocate memory for Minidump size " 4350 "(0x%x).\n", ha->md_dump_size); 4351 return 1; 4352 } 4353 return 0; 4354 } 4355 4356 void 4357 qla82xx_md_free(scsi_qla_host_t *vha) 4358 { 4359 struct qla_hw_data *ha = vha->hw; 4360 4361 /* Release the template header allocated */ 4362 if (ha->md_tmplt_hdr) { 4363 ql_log(ql_log_info, vha, 0xb048, 4364 "Free MiniDump template: %p, size (%d KB)\n", 4365 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4366 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4367 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4368 ha->md_tmplt_hdr = NULL; 4369 } 4370 4371 /* Release the template data buffer allocated */ 4372 if (ha->md_dump) { 4373 ql_log(ql_log_info, vha, 0xb049, 4374 "Free MiniDump memory: %p, size (%d KB)\n", 4375 ha->md_dump, ha->md_dump_size / 1024); 4376 vfree(ha->md_dump); 4377 ha->md_dump_size = 0; 4378 ha->md_dump = NULL; 4379 } 4380 } 4381 4382 void 4383 qla82xx_md_prep(scsi_qla_host_t *vha) 4384 { 4385 struct qla_hw_data *ha = vha->hw; 4386 int rval; 4387 4388 /* Get Minidump template size */ 4389 rval = qla82xx_md_get_template_size(vha); 4390 if (rval == QLA_SUCCESS) { 4391 ql_log(ql_log_info, vha, 0xb04a, 4392 "MiniDump Template size obtained (%d KB)\n", 4393 ha->md_template_size / 1024); 4394 4395 /* Get Minidump template */ 4396 if (IS_QLA8044(ha)) 4397 rval = qla8044_md_get_template(vha); 4398 else 4399 rval = qla82xx_md_get_template(vha); 4400 4401 if (rval == QLA_SUCCESS) { 4402 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4403 "MiniDump Template obtained\n"); 4404 4405 /* Allocate memory for minidump */ 4406 rval = qla82xx_md_alloc(vha); 4407 if (rval == QLA_SUCCESS) 4408 ql_log(ql_log_info, vha, 0xb04c, 4409 "MiniDump memory allocated (%d KB)\n", 4410 ha->md_dump_size / 1024); 4411 else { 4412 ql_log(ql_log_info, vha, 0xb04d, 4413 "Free MiniDump template: %p, size: (%d KB)\n", 4414 ha->md_tmplt_hdr, 4415 ha->md_template_size / 1024); 4416 dma_free_coherent(&ha->pdev->dev, 4417 ha->md_template_size, 4418 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4419 ha->md_tmplt_hdr = NULL; 4420 } 4421 4422 } 4423 } 4424 } 4425 4426 int 4427 qla82xx_beacon_on(struct scsi_qla_host *vha) 4428 { 4429 4430 int rval; 4431 struct qla_hw_data *ha = vha->hw; 4432 4433 qla82xx_idc_lock(ha); 4434 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4435 4436 if (rval) { 4437 ql_log(ql_log_warn, vha, 0xb050, 4438 "mbx set led config failed in %s\n", __func__); 4439 goto exit; 4440 } 4441 ha->beacon_blink_led = 1; 4442 exit: 4443 qla82xx_idc_unlock(ha); 4444 return rval; 4445 } 4446 4447 int 4448 qla82xx_beacon_off(struct scsi_qla_host *vha) 4449 { 4450 4451 int rval; 4452 struct qla_hw_data *ha = vha->hw; 4453 4454 qla82xx_idc_lock(ha); 4455 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4456 4457 if (rval) { 4458 ql_log(ql_log_warn, vha, 0xb051, 4459 "mbx set led config failed in %s\n", __func__); 4460 goto exit; 4461 } 4462 ha->beacon_blink_led = 0; 4463 exit: 4464 qla82xx_idc_unlock(ha); 4465 return rval; 4466 } 4467 4468 void 4469 qla82xx_fw_dump(scsi_qla_host_t *vha) 4470 { 4471 struct qla_hw_data *ha = vha->hw; 4472 4473 if (!ha->allow_cna_fw_dump) 4474 return; 4475 4476 scsi_block_requests(vha->host); 4477 ha->flags.isp82xx_no_md_cap = 1; 4478 qla82xx_idc_lock(ha); 4479 qla82xx_set_reset_owner(vha); 4480 qla82xx_idc_unlock(ha); 4481 qla2x00_wait_for_chip_reset(vha); 4482 scsi_unblock_requests(vha->host); 4483 } 4484