1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/io-64-nonatomic-lo-hi.h> 10 #include <linux/pci.h> 11 #include <linux/ratelimit.h> 12 #include <linux/vmalloc.h> 13 #include <scsi/scsi_tcq.h> 14 15 #define MASK(n) ((1ULL<<(n))-1) 16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 17 ((addr >> 25) & 0x3ff)) 18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 19 ((addr >> 25) & 0x3ff)) 20 #define MS_WIN(addr) (addr & 0x0ffc0000) 21 #define QLA82XX_PCI_MN_2M (0) 22 #define QLA82XX_PCI_MS_2M (0x80000) 23 #define QLA82XX_PCI_OCM0_2M (0xc0000) 24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 26 #define BLOCK_PROTECT_BITS 0x0F 27 28 /* CRB window related */ 29 #define CRB_BLK(off) ((off >> 20) & 0x3f) 30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 31 #define CRB_WINDOW_2M (0x130060) 32 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 34 ((off) & 0xf0000)) 35 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 36 #define CRB_INDIRECT_2M (0x1e0000UL) 37 38 #define MAX_CRB_XFORM 60 39 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 40 static int qla82xx_crb_table_initialized; 41 42 #define qla82xx_crb_addr_transform(name) \ 43 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 44 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 45 46 const int MD_MIU_TEST_AGT_RDDATA[] = { 47 0x410000A8, 0x410000AC, 48 0x410000B8, 0x410000BC 49 }; 50 51 static void qla82xx_crb_addr_transform_setup(void) 52 { 53 qla82xx_crb_addr_transform(XDMA); 54 qla82xx_crb_addr_transform(TIMR); 55 qla82xx_crb_addr_transform(SRE); 56 qla82xx_crb_addr_transform(SQN3); 57 qla82xx_crb_addr_transform(SQN2); 58 qla82xx_crb_addr_transform(SQN1); 59 qla82xx_crb_addr_transform(SQN0); 60 qla82xx_crb_addr_transform(SQS3); 61 qla82xx_crb_addr_transform(SQS2); 62 qla82xx_crb_addr_transform(SQS1); 63 qla82xx_crb_addr_transform(SQS0); 64 qla82xx_crb_addr_transform(RPMX7); 65 qla82xx_crb_addr_transform(RPMX6); 66 qla82xx_crb_addr_transform(RPMX5); 67 qla82xx_crb_addr_transform(RPMX4); 68 qla82xx_crb_addr_transform(RPMX3); 69 qla82xx_crb_addr_transform(RPMX2); 70 qla82xx_crb_addr_transform(RPMX1); 71 qla82xx_crb_addr_transform(RPMX0); 72 qla82xx_crb_addr_transform(ROMUSB); 73 qla82xx_crb_addr_transform(SN); 74 qla82xx_crb_addr_transform(QMN); 75 qla82xx_crb_addr_transform(QMS); 76 qla82xx_crb_addr_transform(PGNI); 77 qla82xx_crb_addr_transform(PGND); 78 qla82xx_crb_addr_transform(PGN3); 79 qla82xx_crb_addr_transform(PGN2); 80 qla82xx_crb_addr_transform(PGN1); 81 qla82xx_crb_addr_transform(PGN0); 82 qla82xx_crb_addr_transform(PGSI); 83 qla82xx_crb_addr_transform(PGSD); 84 qla82xx_crb_addr_transform(PGS3); 85 qla82xx_crb_addr_transform(PGS2); 86 qla82xx_crb_addr_transform(PGS1); 87 qla82xx_crb_addr_transform(PGS0); 88 qla82xx_crb_addr_transform(PS); 89 qla82xx_crb_addr_transform(PH); 90 qla82xx_crb_addr_transform(NIU); 91 qla82xx_crb_addr_transform(I2Q); 92 qla82xx_crb_addr_transform(EG); 93 qla82xx_crb_addr_transform(MN); 94 qla82xx_crb_addr_transform(MS); 95 qla82xx_crb_addr_transform(CAS2); 96 qla82xx_crb_addr_transform(CAS1); 97 qla82xx_crb_addr_transform(CAS0); 98 qla82xx_crb_addr_transform(CAM); 99 qla82xx_crb_addr_transform(C2C1); 100 qla82xx_crb_addr_transform(C2C0); 101 qla82xx_crb_addr_transform(SMB); 102 qla82xx_crb_addr_transform(OCM0); 103 /* 104 * Used only in P3 just define it for P2 also. 105 */ 106 qla82xx_crb_addr_transform(I2C0); 107 108 qla82xx_crb_table_initialized = 1; 109 } 110 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 112 {{{0, 0, 0, 0} } }, 113 {{{1, 0x0100000, 0x0102000, 0x120000}, 114 {1, 0x0110000, 0x0120000, 0x130000}, 115 {1, 0x0120000, 0x0122000, 0x124000}, 116 {1, 0x0130000, 0x0132000, 0x126000}, 117 {1, 0x0140000, 0x0142000, 0x128000}, 118 {1, 0x0150000, 0x0152000, 0x12a000}, 119 {1, 0x0160000, 0x0170000, 0x110000}, 120 {1, 0x0170000, 0x0172000, 0x12e000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {1, 0x01e0000, 0x01e0800, 0x122000}, 128 {0, 0x0000000, 0x0000000, 0x000000} } } , 129 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 130 {{{0, 0, 0, 0} } }, 131 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 132 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 133 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 134 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 135 {{{1, 0x0800000, 0x0802000, 0x170000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 151 {{{1, 0x0900000, 0x0902000, 0x174000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 167 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 183 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {0, 0x0000000, 0x0000000, 0x000000}, 198 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 199 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 200 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 201 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 202 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 203 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 204 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 205 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 206 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 207 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 208 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 209 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 210 {{{0, 0, 0, 0} } }, 211 {{{0, 0, 0, 0} } }, 212 {{{0, 0, 0, 0} } }, 213 {{{0, 0, 0, 0} } }, 214 {{{0, 0, 0, 0} } }, 215 {{{0, 0, 0, 0} } }, 216 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 217 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 218 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 219 {{{0} } }, 220 {{{1, 0x2100000, 0x2102000, 0x120000}, 221 {1, 0x2110000, 0x2120000, 0x130000}, 222 {1, 0x2120000, 0x2122000, 0x124000}, 223 {1, 0x2130000, 0x2132000, 0x126000}, 224 {1, 0x2140000, 0x2142000, 0x128000}, 225 {1, 0x2150000, 0x2152000, 0x12a000}, 226 {1, 0x2160000, 0x2170000, 0x110000}, 227 {1, 0x2170000, 0x2172000, 0x12e000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000}, 235 {0, 0x0000000, 0x0000000, 0x000000} } }, 236 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 237 {{{0} } }, 238 {{{0} } }, 239 {{{0} } }, 240 {{{0} } }, 241 {{{0} } }, 242 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 243 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 244 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 245 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 246 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 247 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 248 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 249 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 250 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 251 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 252 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 253 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 254 {{{0} } }, 255 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 256 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 257 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 258 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 259 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 260 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 261 {{{0} } }, 262 {{{0} } }, 263 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 264 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 265 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 266 }; 267 268 /* 269 * top 12 bits of crb internal address (hub, agent) 270 */ 271 static unsigned qla82xx_crb_hub_agt[64] = { 272 0, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 276 0, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 299 0, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 301 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 302 0, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 304 0, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 307 0, 308 0, 309 0, 310 0, 311 0, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 313 0, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 324 0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 329 0, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 333 0, 334 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 335 0, 336 }; 337 338 /* Device states */ 339 static char *q_dev_state[] = { 340 "Unknown", 341 "Cold", 342 "Initializing", 343 "Ready", 344 "Need Reset", 345 "Need Quiescent", 346 "Failed", 347 "Quiescent", 348 }; 349 350 char *qdev_state(uint32_t dev_state) 351 { 352 return q_dev_state[dev_state]; 353 } 354 355 /* 356 * In: 'off_in' is offset from CRB space in 128M pci map 357 * Out: 'off_out' is 2M pci map addr 358 * side effect: lock crb window 359 */ 360 static void 361 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 362 void __iomem **off_out) 363 { 364 u32 win_read; 365 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 366 367 ha->crb_win = CRB_HI(off_in); 368 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 369 370 /* Read back value to make sure write has gone through before trying 371 * to use it. 372 */ 373 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 374 if (win_read != ha->crb_win) { 375 ql_dbg(ql_dbg_p3p, vha, 0xb000, 376 "%s: Written crbwin (0x%x) " 377 "!= Read crbwin (0x%x), off=0x%lx.\n", 378 __func__, ha->crb_win, win_read, off_in); 379 } 380 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 381 } 382 383 static int 384 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 385 void __iomem **off_out) 386 { 387 struct crb_128M_2M_sub_block_map *m; 388 389 if (off_in >= QLA82XX_CRB_MAX) 390 return -1; 391 392 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 393 *off_out = (off_in - QLA82XX_PCI_CAMQM) + 394 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 395 return 0; 396 } 397 398 if (off_in < QLA82XX_PCI_CRBSPACE) 399 return -1; 400 401 off_in -= QLA82XX_PCI_CRBSPACE; 402 403 /* Try direct map */ 404 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 405 406 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 407 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 408 return 0; 409 } 410 /* Not in direct map, use crb window */ 411 *off_out = (void __iomem *)off_in; 412 return 1; 413 } 414 415 #define CRB_WIN_LOCK_TIMEOUT 100000000 416 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 417 { 418 int done = 0, timeout = 0; 419 420 while (!done) { 421 /* acquire semaphore3 from PCI HW block */ 422 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 423 if (done == 1) 424 break; 425 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 426 return -1; 427 timeout++; 428 } 429 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 430 return 0; 431 } 432 433 int 434 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 435 { 436 void __iomem *off; 437 unsigned long flags = 0; 438 int rv; 439 440 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 441 442 BUG_ON(rv == -1); 443 444 if (rv == 1) { 445 #ifndef __CHECKER__ 446 write_lock_irqsave(&ha->hw_lock, flags); 447 #endif 448 qla82xx_crb_win_lock(ha); 449 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 450 } 451 452 writel(data, (void __iomem *)off); 453 454 if (rv == 1) { 455 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 456 #ifndef __CHECKER__ 457 write_unlock_irqrestore(&ha->hw_lock, flags); 458 #endif 459 } 460 return 0; 461 } 462 463 int 464 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 465 { 466 void __iomem *off; 467 unsigned long flags = 0; 468 int rv; 469 u32 data; 470 471 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 472 473 BUG_ON(rv == -1); 474 475 if (rv == 1) { 476 #ifndef __CHECKER__ 477 write_lock_irqsave(&ha->hw_lock, flags); 478 #endif 479 qla82xx_crb_win_lock(ha); 480 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 481 } 482 data = rd_reg_dword(off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 #ifndef __CHECKER__ 487 write_unlock_irqrestore(&ha->hw_lock, flags); 488 #endif 489 } 490 return data; 491 } 492 493 #define IDC_LOCK_TIMEOUT 100000000 494 int qla82xx_idc_lock(struct qla_hw_data *ha) 495 { 496 int i; 497 int done = 0, timeout = 0; 498 499 while (!done) { 500 /* acquire semaphore5 from PCI HW block */ 501 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 502 if (done == 1) 503 break; 504 if (timeout >= IDC_LOCK_TIMEOUT) 505 return -1; 506 507 timeout++; 508 509 /* Yield CPU */ 510 if (!in_interrupt()) 511 schedule(); 512 else { 513 for (i = 0; i < 20; i++) 514 cpu_relax(); 515 } 516 } 517 518 return 0; 519 } 520 521 void qla82xx_idc_unlock(struct qla_hw_data *ha) 522 { 523 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 524 } 525 526 /* 527 * check memory access boundary. 528 * used by test agent. support ddr access only for now 529 */ 530 static unsigned long 531 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 532 unsigned long long addr, int size) 533 { 534 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 535 QLA82XX_ADDR_DDR_NET_MAX) || 536 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 537 QLA82XX_ADDR_DDR_NET_MAX) || 538 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 539 return 0; 540 else 541 return 1; 542 } 543 544 static int qla82xx_pci_set_window_warning_count; 545 546 static unsigned long 547 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 548 { 549 int window; 550 u32 win_read; 551 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 552 553 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 554 QLA82XX_ADDR_DDR_NET_MAX)) { 555 /* DDR network side */ 556 window = MN_WIN(addr); 557 ha->ddr_mn_window = window; 558 qla82xx_wr_32(ha, 559 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 560 win_read = qla82xx_rd_32(ha, 561 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 562 if ((win_read << 17) != window) { 563 ql_dbg(ql_dbg_p3p, vha, 0xb003, 564 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 565 __func__, window, win_read); 566 } 567 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 568 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 569 QLA82XX_ADDR_OCM0_MAX)) { 570 unsigned int temp1; 571 572 if ((addr & 0x00ff800) == 0xff800) { 573 ql_log(ql_log_warn, vha, 0xb004, 574 "%s: QM access not handled.\n", __func__); 575 addr = -1UL; 576 } 577 window = OCM_WIN(addr); 578 ha->ddr_mn_window = window; 579 qla82xx_wr_32(ha, 580 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 581 win_read = qla82xx_rd_32(ha, 582 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 583 temp1 = ((window & 0x1FF) << 7) | 584 ((window & 0x0FFFE0000) >> 17); 585 if (win_read != temp1) { 586 ql_log(ql_log_warn, vha, 0xb005, 587 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 588 __func__, temp1, win_read); 589 } 590 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 591 592 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 593 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 594 /* QDR network side */ 595 window = MS_WIN(addr); 596 ha->qdr_sn_window = window; 597 qla82xx_wr_32(ha, 598 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 599 win_read = qla82xx_rd_32(ha, 600 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 601 if (win_read != window) { 602 ql_log(ql_log_warn, vha, 0xb006, 603 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 604 __func__, window, win_read); 605 } 606 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 607 } else { 608 /* 609 * peg gdb frequently accesses memory that doesn't exist, 610 * this limits the chit chat so debugging isn't slowed down. 611 */ 612 if ((qla82xx_pci_set_window_warning_count++ < 8) || 613 (qla82xx_pci_set_window_warning_count%64 == 0)) { 614 ql_log(ql_log_warn, vha, 0xb007, 615 "%s: Warning:%s Unknown address range!.\n", 616 __func__, QLA2XXX_DRIVER_NAME); 617 } 618 addr = -1UL; 619 } 620 return addr; 621 } 622 623 /* check if address is in the same windows as the previous access */ 624 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 625 unsigned long long addr) 626 { 627 int window; 628 unsigned long long qdr_max; 629 630 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 631 632 /* DDR network side */ 633 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 634 QLA82XX_ADDR_DDR_NET_MAX)) 635 BUG(); 636 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 637 QLA82XX_ADDR_OCM0_MAX)) 638 return 1; 639 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 640 QLA82XX_ADDR_OCM1_MAX)) 641 return 1; 642 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 643 /* QDR network side */ 644 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 645 if (ha->qdr_sn_window == window) 646 return 1; 647 } 648 return 0; 649 } 650 651 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 652 u64 off, void *data, int size) 653 { 654 unsigned long flags; 655 void __iomem *addr = NULL; 656 int ret = 0; 657 u64 start; 658 uint8_t __iomem *mem_ptr = NULL; 659 unsigned long mem_base; 660 unsigned long mem_page; 661 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 662 663 write_lock_irqsave(&ha->hw_lock, flags); 664 665 /* 666 * If attempting to access unknown address or straddle hw windows, 667 * do not access. 668 */ 669 start = qla82xx_pci_set_window(ha, off); 670 if ((start == -1UL) || 671 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 672 write_unlock_irqrestore(&ha->hw_lock, flags); 673 ql_log(ql_log_fatal, vha, 0xb008, 674 "%s out of bound pci memory " 675 "access, offset is 0x%llx.\n", 676 QLA2XXX_DRIVER_NAME, off); 677 return -1; 678 } 679 680 write_unlock_irqrestore(&ha->hw_lock, flags); 681 mem_base = pci_resource_start(ha->pdev, 0); 682 mem_page = start & PAGE_MASK; 683 /* Map two pages whenever user tries to access addresses in two 684 * consecutive pages. 685 */ 686 if (mem_page != ((start + size - 1) & PAGE_MASK)) 687 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 688 else 689 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 690 if (mem_ptr == NULL) { 691 *(u8 *)data = 0; 692 return -1; 693 } 694 addr = mem_ptr; 695 addr += start & (PAGE_SIZE - 1); 696 write_lock_irqsave(&ha->hw_lock, flags); 697 698 switch (size) { 699 case 1: 700 *(u8 *)data = readb(addr); 701 break; 702 case 2: 703 *(u16 *)data = readw(addr); 704 break; 705 case 4: 706 *(u32 *)data = readl(addr); 707 break; 708 case 8: 709 *(u64 *)data = readq(addr); 710 break; 711 default: 712 ret = -1; 713 break; 714 } 715 write_unlock_irqrestore(&ha->hw_lock, flags); 716 717 if (mem_ptr) 718 iounmap(mem_ptr); 719 return ret; 720 } 721 722 static int 723 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 724 u64 off, void *data, int size) 725 { 726 unsigned long flags; 727 void __iomem *addr = NULL; 728 int ret = 0; 729 u64 start; 730 uint8_t __iomem *mem_ptr = NULL; 731 unsigned long mem_base; 732 unsigned long mem_page; 733 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 734 735 write_lock_irqsave(&ha->hw_lock, flags); 736 737 /* 738 * If attempting to access unknown address or straddle hw windows, 739 * do not access. 740 */ 741 start = qla82xx_pci_set_window(ha, off); 742 if ((start == -1UL) || 743 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 744 write_unlock_irqrestore(&ha->hw_lock, flags); 745 ql_log(ql_log_fatal, vha, 0xb009, 746 "%s out of bound memory " 747 "access, offset is 0x%llx.\n", 748 QLA2XXX_DRIVER_NAME, off); 749 return -1; 750 } 751 752 write_unlock_irqrestore(&ha->hw_lock, flags); 753 mem_base = pci_resource_start(ha->pdev, 0); 754 mem_page = start & PAGE_MASK; 755 /* Map two pages whenever user tries to access addresses in two 756 * consecutive pages. 757 */ 758 if (mem_page != ((start + size - 1) & PAGE_MASK)) 759 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 760 else 761 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 762 if (mem_ptr == NULL) 763 return -1; 764 765 addr = mem_ptr; 766 addr += start & (PAGE_SIZE - 1); 767 write_lock_irqsave(&ha->hw_lock, flags); 768 769 switch (size) { 770 case 1: 771 writeb(*(u8 *)data, addr); 772 break; 773 case 2: 774 writew(*(u16 *)data, addr); 775 break; 776 case 4: 777 writel(*(u32 *)data, addr); 778 break; 779 case 8: 780 writeq(*(u64 *)data, addr); 781 break; 782 default: 783 ret = -1; 784 break; 785 } 786 write_unlock_irqrestore(&ha->hw_lock, flags); 787 if (mem_ptr) 788 iounmap(mem_ptr); 789 return ret; 790 } 791 792 #define MTU_FUDGE_FACTOR 100 793 static unsigned long 794 qla82xx_decode_crb_addr(unsigned long addr) 795 { 796 int i; 797 unsigned long base_addr, offset, pci_base; 798 799 if (!qla82xx_crb_table_initialized) 800 qla82xx_crb_addr_transform_setup(); 801 802 pci_base = ADDR_ERROR; 803 base_addr = addr & 0xfff00000; 804 offset = addr & 0x000fffff; 805 806 for (i = 0; i < MAX_CRB_XFORM; i++) { 807 if (crb_addr_xform[i] == base_addr) { 808 pci_base = i << 20; 809 break; 810 } 811 } 812 if (pci_base == ADDR_ERROR) 813 return pci_base; 814 return pci_base + offset; 815 } 816 817 static long rom_max_timeout = 100; 818 static long qla82xx_rom_lock_timeout = 100; 819 820 static int 821 qla82xx_rom_lock(struct qla_hw_data *ha) 822 { 823 int done = 0, timeout = 0; 824 uint32_t lock_owner = 0; 825 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 826 827 while (!done) { 828 /* acquire semaphore2 from PCI HW block */ 829 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 830 if (done == 1) 831 break; 832 if (timeout >= qla82xx_rom_lock_timeout) { 833 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 834 ql_dbg(ql_dbg_p3p, vha, 0xb157, 835 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 836 __func__, ha->portnum, lock_owner); 837 return -1; 838 } 839 timeout++; 840 } 841 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 842 return 0; 843 } 844 845 static void 846 qla82xx_rom_unlock(struct qla_hw_data *ha) 847 { 848 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 849 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 850 } 851 852 static int 853 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 854 { 855 long timeout = 0; 856 long done = 0 ; 857 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 858 859 while (done == 0) { 860 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 861 done &= 4; 862 timeout++; 863 if (timeout >= rom_max_timeout) { 864 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 865 "%s: Timeout reached waiting for rom busy.\n", 866 QLA2XXX_DRIVER_NAME); 867 return -1; 868 } 869 } 870 return 0; 871 } 872 873 static int 874 qla82xx_wait_rom_done(struct qla_hw_data *ha) 875 { 876 long timeout = 0; 877 long done = 0 ; 878 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 879 880 while (done == 0) { 881 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 882 done &= 2; 883 timeout++; 884 if (timeout >= rom_max_timeout) { 885 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 886 "%s: Timeout reached waiting for rom done.\n", 887 QLA2XXX_DRIVER_NAME); 888 return -1; 889 } 890 } 891 return 0; 892 } 893 894 static int 895 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 896 { 897 uint32_t off_value, rval = 0; 898 899 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 900 901 /* Read back value to make sure write has gone through */ 902 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 903 off_value = (off & 0x0000FFFF); 904 905 if (flag) 906 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 907 data); 908 else 909 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + 910 ha->nx_pcibase); 911 912 return rval; 913 } 914 915 static int 916 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 917 { 918 /* Dword reads to flash. */ 919 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 920 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 921 (addr & 0x0000FFFF), 0, 0); 922 923 return 0; 924 } 925 926 static int 927 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 928 { 929 int ret, loops = 0; 930 uint32_t lock_owner = 0; 931 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 932 933 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 934 udelay(100); 935 schedule(); 936 loops++; 937 } 938 if (loops >= 50000) { 939 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 940 ql_log(ql_log_fatal, vha, 0x00b9, 941 "Failed to acquire SEM2 lock, Lock Owner %u.\n", 942 lock_owner); 943 return -1; 944 } 945 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 946 qla82xx_rom_unlock(ha); 947 return ret; 948 } 949 950 static int 951 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 952 { 953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 954 955 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 956 qla82xx_wait_rom_busy(ha); 957 if (qla82xx_wait_rom_done(ha)) { 958 ql_log(ql_log_warn, vha, 0xb00c, 959 "Error waiting for rom done.\n"); 960 return -1; 961 } 962 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 963 return 0; 964 } 965 966 static int 967 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 968 { 969 uint32_t val; 970 int i, ret; 971 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 972 973 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 974 for (i = 0; i < 50000; i++) { 975 ret = qla82xx_read_status_reg(ha, &val); 976 if (ret < 0 || (val & 1) == 0) 977 return ret; 978 udelay(10); 979 cond_resched(); 980 } 981 ql_log(ql_log_warn, vha, 0xb00d, 982 "Timeout reached waiting for write finish.\n"); 983 return -1; 984 } 985 986 static int 987 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 988 { 989 uint32_t val; 990 991 qla82xx_wait_rom_busy(ha); 992 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 993 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 994 qla82xx_wait_rom_busy(ha); 995 if (qla82xx_wait_rom_done(ha)) 996 return -1; 997 if (qla82xx_read_status_reg(ha, &val) != 0) 998 return -1; 999 if ((val & 2) != 2) 1000 return -1; 1001 return 0; 1002 } 1003 1004 static int 1005 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1006 { 1007 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1008 1009 if (qla82xx_flash_set_write_enable(ha)) 1010 return -1; 1011 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1012 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1013 if (qla82xx_wait_rom_done(ha)) { 1014 ql_log(ql_log_warn, vha, 0xb00e, 1015 "Error waiting for rom done.\n"); 1016 return -1; 1017 } 1018 return qla82xx_flash_wait_write_finish(ha); 1019 } 1020 1021 static int 1022 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1023 { 1024 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1025 1026 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1027 if (qla82xx_wait_rom_done(ha)) { 1028 ql_log(ql_log_warn, vha, 0xb00f, 1029 "Error waiting for rom done.\n"); 1030 return -1; 1031 } 1032 return 0; 1033 } 1034 1035 static int 1036 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1037 { 1038 int loops = 0; 1039 uint32_t lock_owner = 0; 1040 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1041 1042 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1043 udelay(100); 1044 cond_resched(); 1045 loops++; 1046 } 1047 if (loops >= 50000) { 1048 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 1049 ql_log(ql_log_warn, vha, 0xb010, 1050 "ROM lock failed, Lock Owner %u.\n", lock_owner); 1051 return -1; 1052 } 1053 return 0; 1054 } 1055 1056 static int 1057 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1058 uint32_t data) 1059 { 1060 int ret = 0; 1061 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1062 1063 ret = ql82xx_rom_lock_d(ha); 1064 if (ret < 0) { 1065 ql_log(ql_log_warn, vha, 0xb011, 1066 "ROM lock failed.\n"); 1067 return ret; 1068 } 1069 1070 if (qla82xx_flash_set_write_enable(ha)) 1071 goto done_write; 1072 1073 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1074 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1075 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1076 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1077 qla82xx_wait_rom_busy(ha); 1078 if (qla82xx_wait_rom_done(ha)) { 1079 ql_log(ql_log_warn, vha, 0xb012, 1080 "Error waiting for rom done.\n"); 1081 ret = -1; 1082 goto done_write; 1083 } 1084 1085 ret = qla82xx_flash_wait_write_finish(ha); 1086 1087 done_write: 1088 qla82xx_rom_unlock(ha); 1089 return ret; 1090 } 1091 1092 /* This routine does CRB initialize sequence 1093 * to put the ISP into operational state 1094 */ 1095 static int 1096 qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1097 { 1098 int addr, val; 1099 int i ; 1100 struct crb_addr_pair *buf; 1101 unsigned long off; 1102 unsigned offset, n; 1103 struct qla_hw_data *ha = vha->hw; 1104 1105 struct crb_addr_pair { 1106 long addr; 1107 long data; 1108 }; 1109 1110 /* Halt all the individual PEGs and other blocks of the ISP */ 1111 qla82xx_rom_lock(ha); 1112 1113 /* disable all I2Q */ 1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1116 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1117 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1118 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1120 1121 /* disable all niu interrupts */ 1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1123 /* disable xge rx/tx */ 1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1125 /* disable xg1 rx/tx */ 1126 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1127 /* disable sideband mac */ 1128 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1129 /* disable ap0 mac */ 1130 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1131 /* disable ap1 mac */ 1132 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1133 1134 /* halt sre */ 1135 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1136 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1137 1138 /* halt epg */ 1139 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1140 1141 /* halt timers */ 1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1144 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1145 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1146 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1148 1149 /* halt pegs */ 1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1153 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1154 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1155 msleep(20); 1156 1157 /* big hammer */ 1158 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1159 /* don't reset CAM block on reset */ 1160 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1161 else 1162 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1163 qla82xx_rom_unlock(ha); 1164 1165 /* Read the signature value from the flash. 1166 * Offset 0: Contain signature (0xcafecafe) 1167 * Offset 4: Offset and number of addr/value pairs 1168 * that present in CRB initialize sequence 1169 */ 1170 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1171 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1172 ql_log(ql_log_fatal, vha, 0x006e, 1173 "Error Reading crb_init area: n: %08x.\n", n); 1174 return -1; 1175 } 1176 1177 /* Offset in flash = lower 16 bits 1178 * Number of entries = upper 16 bits 1179 */ 1180 offset = n & 0xffffU; 1181 n = (n >> 16) & 0xffffU; 1182 1183 /* number of addr/value pair should not exceed 1024 entries */ 1184 if (n >= 1024) { 1185 ql_log(ql_log_fatal, vha, 0x0071, 1186 "Card flash not initialized:n=0x%x.\n", n); 1187 return -1; 1188 } 1189 1190 ql_log(ql_log_info, vha, 0x0072, 1191 "%d CRB init values found in ROM.\n", n); 1192 1193 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1194 if (buf == NULL) { 1195 ql_log(ql_log_fatal, vha, 0x010c, 1196 "Unable to allocate memory.\n"); 1197 return -ENOMEM; 1198 } 1199 1200 for (i = 0; i < n; i++) { 1201 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1202 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1203 kfree(buf); 1204 return -1; 1205 } 1206 1207 buf[i].addr = addr; 1208 buf[i].data = val; 1209 } 1210 1211 for (i = 0; i < n; i++) { 1212 /* Translate internal CRB initialization 1213 * address to PCI bus address 1214 */ 1215 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1216 QLA82XX_PCI_CRBSPACE; 1217 /* Not all CRB addr/value pair to be written, 1218 * some of them are skipped 1219 */ 1220 1221 /* skipping cold reboot MAGIC */ 1222 if (off == QLA82XX_CAM_RAM(0x1fc)) 1223 continue; 1224 1225 /* do not reset PCI */ 1226 if (off == (ROMUSB_GLB + 0xbc)) 1227 continue; 1228 1229 /* skip core clock, so that firmware can increase the clock */ 1230 if (off == (ROMUSB_GLB + 0xc8)) 1231 continue; 1232 1233 /* skip the function enable register */ 1234 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1235 continue; 1236 1237 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1238 continue; 1239 1240 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1241 continue; 1242 1243 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1244 continue; 1245 1246 if (off == ADDR_ERROR) { 1247 ql_log(ql_log_fatal, vha, 0x0116, 1248 "Unknown addr: 0x%08lx.\n", buf[i].addr); 1249 continue; 1250 } 1251 1252 qla82xx_wr_32(ha, off, buf[i].data); 1253 1254 /* ISP requires much bigger delay to settle down, 1255 * else crb_window returns 0xffffffff 1256 */ 1257 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1258 msleep(1000); 1259 1260 /* ISP requires millisec delay between 1261 * successive CRB register updation 1262 */ 1263 msleep(1); 1264 } 1265 1266 kfree(buf); 1267 1268 /* Resetting the data and instruction cache */ 1269 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1270 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1272 1273 /* Clear all protocol processing engines */ 1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1280 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1281 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1282 return 0; 1283 } 1284 1285 static int 1286 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1287 u64 off, void *data, int size) 1288 { 1289 int i, j, ret = 0, loop, sz[2], off0; 1290 int scale, shift_amount, startword; 1291 uint32_t temp; 1292 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1293 1294 /* 1295 * If not MN, go check for MS or invalid. 1296 */ 1297 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1298 mem_crb = QLA82XX_CRB_QDR_NET; 1299 else { 1300 mem_crb = QLA82XX_CRB_DDR_NET; 1301 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1302 return qla82xx_pci_mem_write_direct(ha, 1303 off, data, size); 1304 } 1305 1306 off0 = off & 0x7; 1307 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1308 sz[1] = size - sz[0]; 1309 1310 off8 = off & 0xfffffff0; 1311 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1312 shift_amount = 4; 1313 scale = 2; 1314 startword = (off & 0xf)/8; 1315 1316 for (i = 0; i < loop; i++) { 1317 if (qla82xx_pci_mem_read_2M(ha, off8 + 1318 (i << shift_amount), &word[i * scale], 8)) 1319 return -1; 1320 } 1321 1322 switch (size) { 1323 case 1: 1324 tmpw = *((uint8_t *)data); 1325 break; 1326 case 2: 1327 tmpw = *((uint16_t *)data); 1328 break; 1329 case 4: 1330 tmpw = *((uint32_t *)data); 1331 break; 1332 case 8: 1333 default: 1334 tmpw = *((uint64_t *)data); 1335 break; 1336 } 1337 1338 if (sz[0] == 8) { 1339 word[startword] = tmpw; 1340 } else { 1341 word[startword] &= 1342 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1343 word[startword] |= tmpw << (off0 * 8); 1344 } 1345 if (sz[1] != 0) { 1346 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1347 word[startword+1] |= tmpw >> (sz[0] * 8); 1348 } 1349 1350 for (i = 0; i < loop; i++) { 1351 temp = off8 + (i << shift_amount); 1352 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1353 temp = 0; 1354 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1355 temp = word[i * scale] & 0xffffffff; 1356 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1357 temp = (word[i * scale] >> 32) & 0xffffffff; 1358 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1359 temp = word[i*scale + 1] & 0xffffffff; 1360 qla82xx_wr_32(ha, mem_crb + 1361 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1362 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1363 qla82xx_wr_32(ha, mem_crb + 1364 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1365 1366 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1367 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1368 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1369 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1370 1371 for (j = 0; j < MAX_CTL_CHECK; j++) { 1372 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1373 if ((temp & MIU_TA_CTL_BUSY) == 0) 1374 break; 1375 } 1376 1377 if (j >= MAX_CTL_CHECK) { 1378 if (printk_ratelimit()) 1379 dev_err(&ha->pdev->dev, 1380 "failed to write through agent.\n"); 1381 ret = -1; 1382 break; 1383 } 1384 } 1385 1386 return ret; 1387 } 1388 1389 static int 1390 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1391 { 1392 int i; 1393 long size = 0; 1394 long flashaddr = ha->flt_region_bootload << 2; 1395 long memaddr = BOOTLD_START; 1396 u64 data; 1397 u32 high, low; 1398 1399 size = (IMAGE_START - BOOTLD_START) / 8; 1400 1401 for (i = 0; i < size; i++) { 1402 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1403 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1404 return -1; 1405 } 1406 data = ((u64)high << 32) | low ; 1407 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1408 flashaddr += 8; 1409 memaddr += 8; 1410 1411 if (i % 0x1000 == 0) 1412 msleep(1); 1413 } 1414 udelay(100); 1415 read_lock(&ha->hw_lock); 1416 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1417 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1418 read_unlock(&ha->hw_lock); 1419 return 0; 1420 } 1421 1422 int 1423 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1424 u64 off, void *data, int size) 1425 { 1426 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1427 int shift_amount; 1428 uint32_t temp; 1429 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1430 1431 /* 1432 * If not MN, go check for MS or invalid. 1433 */ 1434 1435 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1436 mem_crb = QLA82XX_CRB_QDR_NET; 1437 else { 1438 mem_crb = QLA82XX_CRB_DDR_NET; 1439 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1440 return qla82xx_pci_mem_read_direct(ha, 1441 off, data, size); 1442 } 1443 1444 off8 = off & 0xfffffff0; 1445 off0[0] = off & 0xf; 1446 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1447 shift_amount = 4; 1448 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1449 off0[1] = 0; 1450 sz[1] = size - sz[0]; 1451 1452 for (i = 0; i < loop; i++) { 1453 temp = off8 + (i << shift_amount); 1454 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1455 temp = 0; 1456 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1457 temp = MIU_TA_CTL_ENABLE; 1458 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1459 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1460 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1461 1462 for (j = 0; j < MAX_CTL_CHECK; j++) { 1463 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1464 if ((temp & MIU_TA_CTL_BUSY) == 0) 1465 break; 1466 } 1467 1468 if (j >= MAX_CTL_CHECK) { 1469 if (printk_ratelimit()) 1470 dev_err(&ha->pdev->dev, 1471 "failed to read through agent.\n"); 1472 break; 1473 } 1474 1475 start = off0[i] >> 2; 1476 end = (off0[i] + sz[i] - 1) >> 2; 1477 for (k = start; k <= end; k++) { 1478 temp = qla82xx_rd_32(ha, 1479 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1480 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1481 } 1482 } 1483 1484 if (j >= MAX_CTL_CHECK) 1485 return -1; 1486 1487 if ((off0[0] & 7) == 0) { 1488 val = word[0]; 1489 } else { 1490 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1491 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1492 } 1493 1494 switch (size) { 1495 case 1: 1496 *(uint8_t *)data = val; 1497 break; 1498 case 2: 1499 *(uint16_t *)data = val; 1500 break; 1501 case 4: 1502 *(uint32_t *)data = val; 1503 break; 1504 case 8: 1505 *(uint64_t *)data = val; 1506 break; 1507 } 1508 return 0; 1509 } 1510 1511 1512 static struct qla82xx_uri_table_desc * 1513 qla82xx_get_table_desc(const u8 *unirom, int section) 1514 { 1515 uint32_t i; 1516 struct qla82xx_uri_table_desc *directory = 1517 (struct qla82xx_uri_table_desc *)&unirom[0]; 1518 uint32_t offset; 1519 uint32_t tab_type; 1520 uint32_t entries = le32_to_cpu(directory->num_entries); 1521 1522 for (i = 0; i < entries; i++) { 1523 offset = le32_to_cpu(directory->findex) + 1524 (i * le32_to_cpu(directory->entry_size)); 1525 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8); 1526 1527 if (tab_type == section) 1528 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1529 } 1530 1531 return NULL; 1532 } 1533 1534 static struct qla82xx_uri_data_desc * 1535 qla82xx_get_data_desc(struct qla_hw_data *ha, 1536 u32 section, u32 idx_offset) 1537 { 1538 const u8 *unirom = ha->hablob->fw->data; 1539 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] + 1540 idx_offset); 1541 struct qla82xx_uri_table_desc *tab_desc = NULL; 1542 uint32_t offset; 1543 1544 tab_desc = qla82xx_get_table_desc(unirom, section); 1545 if (!tab_desc) 1546 return NULL; 1547 1548 offset = le32_to_cpu(tab_desc->findex) + 1549 (le32_to_cpu(tab_desc->entry_size) * idx); 1550 1551 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1552 } 1553 1554 static u8 * 1555 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1556 { 1557 u32 offset = BOOTLD_START; 1558 struct qla82xx_uri_data_desc *uri_desc = NULL; 1559 1560 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1561 uri_desc = qla82xx_get_data_desc(ha, 1562 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1563 if (uri_desc) 1564 offset = le32_to_cpu(uri_desc->findex); 1565 } 1566 1567 return (u8 *)&ha->hablob->fw->data[offset]; 1568 } 1569 1570 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha) 1571 { 1572 struct qla82xx_uri_data_desc *uri_desc = NULL; 1573 1574 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1575 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1576 QLA82XX_URI_FIRMWARE_IDX_OFF); 1577 if (uri_desc) 1578 return le32_to_cpu(uri_desc->size); 1579 } 1580 1581 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1582 } 1583 1584 static u8 * 1585 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1586 { 1587 u32 offset = IMAGE_START; 1588 struct qla82xx_uri_data_desc *uri_desc = NULL; 1589 1590 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1591 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1592 QLA82XX_URI_FIRMWARE_IDX_OFF); 1593 if (uri_desc) 1594 offset = le32_to_cpu(uri_desc->findex); 1595 } 1596 1597 return (u8 *)&ha->hablob->fw->data[offset]; 1598 } 1599 1600 /* PCI related functions */ 1601 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1602 { 1603 unsigned long val = 0; 1604 u32 control; 1605 1606 switch (region) { 1607 case 0: 1608 val = 0; 1609 break; 1610 case 1: 1611 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1612 val = control + QLA82XX_MSIX_TBL_SPACE; 1613 break; 1614 } 1615 return val; 1616 } 1617 1618 1619 int 1620 qla82xx_iospace_config(struct qla_hw_data *ha) 1621 { 1622 uint32_t len = 0; 1623 1624 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1625 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1626 "Failed to reserver selected regions.\n"); 1627 goto iospace_error_exit; 1628 } 1629 1630 /* Use MMIO operations for all accesses. */ 1631 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1632 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1633 "Region #0 not an MMIO resource, aborting.\n"); 1634 goto iospace_error_exit; 1635 } 1636 1637 len = pci_resource_len(ha->pdev, 0); 1638 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1639 if (!ha->nx_pcibase) { 1640 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1641 "Cannot remap pcibase MMIO, aborting.\n"); 1642 goto iospace_error_exit; 1643 } 1644 1645 /* Mapping of IO base pointer */ 1646 if (IS_QLA8044(ha)) { 1647 ha->iobase = ha->nx_pcibase; 1648 } else if (IS_QLA82XX(ha)) { 1649 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 1650 } 1651 1652 if (!ql2xdbwr) { 1653 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1654 (ha->pdev->devfn << 12)), 4); 1655 if (!ha->nxdb_wr_ptr) { 1656 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1657 "Cannot remap MMIO, aborting.\n"); 1658 goto iospace_error_exit; 1659 } 1660 1661 /* Mapping of IO base pointer, 1662 * door bell read and write pointer 1663 */ 1664 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1665 (ha->pdev->devfn * 8); 1666 } else { 1667 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1668 QLA82XX_CAMRAM_DB1 : 1669 QLA82XX_CAMRAM_DB2); 1670 } 1671 1672 ha->max_req_queues = ha->max_rsp_queues = 1; 1673 ha->msix_count = ha->max_rsp_queues + 1; 1674 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1675 "nx_pci_base=%p iobase=%p " 1676 "max_req_queues=%d msix_count=%d.\n", 1677 ha->nx_pcibase, ha->iobase, 1678 ha->max_req_queues, ha->msix_count); 1679 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1680 "nx_pci_base=%p iobase=%p " 1681 "max_req_queues=%d msix_count=%d.\n", 1682 ha->nx_pcibase, ha->iobase, 1683 ha->max_req_queues, ha->msix_count); 1684 return 0; 1685 1686 iospace_error_exit: 1687 return -ENOMEM; 1688 } 1689 1690 /* GS related functions */ 1691 1692 /* Initialization related functions */ 1693 1694 /** 1695 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1696 * @vha: HA context 1697 * 1698 * Returns 0 on success. 1699 */ 1700 int 1701 qla82xx_pci_config(scsi_qla_host_t *vha) 1702 { 1703 struct qla_hw_data *ha = vha->hw; 1704 int ret; 1705 1706 pci_set_master(ha->pdev); 1707 ret = pci_set_mwi(ha->pdev); 1708 ha->chip_revision = ha->pdev->revision; 1709 ql_dbg(ql_dbg_init, vha, 0x0043, 1710 "Chip revision:%d; pci_set_mwi() returned %d.\n", 1711 ha->chip_revision, ret); 1712 return 0; 1713 } 1714 1715 /** 1716 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1717 * @vha: HA context 1718 * 1719 * Returns 0 on success. 1720 */ 1721 int 1722 qla82xx_reset_chip(scsi_qla_host_t *vha) 1723 { 1724 struct qla_hw_data *ha = vha->hw; 1725 1726 ha->isp_ops->disable_intrs(ha); 1727 1728 return QLA_SUCCESS; 1729 } 1730 1731 void qla82xx_config_rings(struct scsi_qla_host *vha) 1732 { 1733 struct qla_hw_data *ha = vha->hw; 1734 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1735 struct init_cb_81xx *icb; 1736 struct req_que *req = ha->req_q_map[0]; 1737 struct rsp_que *rsp = ha->rsp_q_map[0]; 1738 1739 /* Setup ring parameters in initialization control block. */ 1740 icb = (struct init_cb_81xx *)ha->init_cb; 1741 icb->request_q_outpointer = cpu_to_le16(0); 1742 icb->response_q_inpointer = cpu_to_le16(0); 1743 icb->request_q_length = cpu_to_le16(req->length); 1744 icb->response_q_length = cpu_to_le16(rsp->length); 1745 put_unaligned_le64(req->dma, &icb->request_q_address); 1746 put_unaligned_le64(rsp->dma, &icb->response_q_address); 1747 1748 wrt_reg_dword(®->req_q_out[0], 0); 1749 wrt_reg_dword(®->rsp_q_in[0], 0); 1750 wrt_reg_dword(®->rsp_q_out[0], 0); 1751 } 1752 1753 static int 1754 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1755 { 1756 u64 *ptr64; 1757 u32 i, flashaddr, size; 1758 __le64 data; 1759 1760 size = (IMAGE_START - BOOTLD_START) / 8; 1761 1762 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1763 flashaddr = BOOTLD_START; 1764 1765 for (i = 0; i < size; i++) { 1766 data = cpu_to_le64(ptr64[i]); 1767 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1768 return -EIO; 1769 flashaddr += 8; 1770 } 1771 1772 flashaddr = FLASH_ADDR_START; 1773 size = qla82xx_get_fw_size(ha) / 8; 1774 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1775 1776 for (i = 0; i < size; i++) { 1777 data = cpu_to_le64(ptr64[i]); 1778 1779 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1780 return -EIO; 1781 flashaddr += 8; 1782 } 1783 udelay(100); 1784 1785 /* Write a magic value to CAMRAM register 1786 * at a specified offset to indicate 1787 * that all data is written and 1788 * ready for firmware to initialize. 1789 */ 1790 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1791 1792 read_lock(&ha->hw_lock); 1793 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1794 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1795 read_unlock(&ha->hw_lock); 1796 return 0; 1797 } 1798 1799 static int 1800 qla82xx_set_product_offset(struct qla_hw_data *ha) 1801 { 1802 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1803 const uint8_t *unirom = ha->hablob->fw->data; 1804 uint32_t i; 1805 uint32_t entries; 1806 uint32_t flags, file_chiprev, offset; 1807 uint8_t chiprev = ha->chip_revision; 1808 /* Hardcoding mn_present flag for P3P */ 1809 int mn_present = 0; 1810 uint32_t flagbit; 1811 1812 ptab_desc = qla82xx_get_table_desc(unirom, 1813 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1814 if (!ptab_desc) 1815 return -1; 1816 1817 entries = le32_to_cpu(ptab_desc->num_entries); 1818 1819 for (i = 0; i < entries; i++) { 1820 offset = le32_to_cpu(ptab_desc->findex) + 1821 (i * le32_to_cpu(ptab_desc->entry_size)); 1822 flags = le32_to_cpu(*((__le32 *)&unirom[offset] + 1823 QLA82XX_URI_FLAGS_OFF)); 1824 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] + 1825 QLA82XX_URI_CHIP_REV_OFF)); 1826 1827 flagbit = mn_present ? 1 : 2; 1828 1829 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1830 ha->file_prd_off = offset; 1831 return 0; 1832 } 1833 } 1834 return -1; 1835 } 1836 1837 static int 1838 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1839 { 1840 uint32_t val; 1841 uint32_t min_size; 1842 struct qla_hw_data *ha = vha->hw; 1843 const struct firmware *fw = ha->hablob->fw; 1844 1845 ha->fw_type = fw_type; 1846 1847 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1848 if (qla82xx_set_product_offset(ha)) 1849 return -EINVAL; 1850 1851 min_size = QLA82XX_URI_FW_MIN_SIZE; 1852 } else { 1853 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1854 if (val != QLA82XX_BDINFO_MAGIC) 1855 return -EINVAL; 1856 1857 min_size = QLA82XX_FW_MIN_SIZE; 1858 } 1859 1860 if (fw->size < min_size) 1861 return -EINVAL; 1862 return 0; 1863 } 1864 1865 static int 1866 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1867 { 1868 u32 val = 0; 1869 int retries = 60; 1870 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1871 1872 do { 1873 read_lock(&ha->hw_lock); 1874 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1875 read_unlock(&ha->hw_lock); 1876 1877 switch (val) { 1878 case PHAN_INITIALIZE_COMPLETE: 1879 case PHAN_INITIALIZE_ACK: 1880 return QLA_SUCCESS; 1881 case PHAN_INITIALIZE_FAILED: 1882 break; 1883 default: 1884 break; 1885 } 1886 ql_log(ql_log_info, vha, 0x00a8, 1887 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1888 val, retries); 1889 1890 msleep(500); 1891 1892 } while (--retries); 1893 1894 ql_log(ql_log_fatal, vha, 0x00a9, 1895 "Cmd Peg initialization failed: 0x%x.\n", val); 1896 1897 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1898 read_lock(&ha->hw_lock); 1899 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1900 read_unlock(&ha->hw_lock); 1901 return QLA_FUNCTION_FAILED; 1902 } 1903 1904 static int 1905 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1906 { 1907 u32 val = 0; 1908 int retries = 60; 1909 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1910 1911 do { 1912 read_lock(&ha->hw_lock); 1913 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1914 read_unlock(&ha->hw_lock); 1915 1916 switch (val) { 1917 case PHAN_INITIALIZE_COMPLETE: 1918 case PHAN_INITIALIZE_ACK: 1919 return QLA_SUCCESS; 1920 case PHAN_INITIALIZE_FAILED: 1921 break; 1922 default: 1923 break; 1924 } 1925 ql_log(ql_log_info, vha, 0x00ab, 1926 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1927 val, retries); 1928 1929 msleep(500); 1930 1931 } while (--retries); 1932 1933 ql_log(ql_log_fatal, vha, 0x00ac, 1934 "Rcv Peg initialization failed: 0x%x.\n", val); 1935 read_lock(&ha->hw_lock); 1936 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1937 read_unlock(&ha->hw_lock); 1938 return QLA_FUNCTION_FAILED; 1939 } 1940 1941 /* ISR related functions */ 1942 static struct qla82xx_legacy_intr_set legacy_intr[] = 1943 QLA82XX_LEGACY_INTR_CONFIG; 1944 1945 /* 1946 * qla82xx_mbx_completion() - Process mailbox command completions. 1947 * @ha: SCSI driver HA context 1948 * @mb0: Mailbox0 register 1949 */ 1950 void 1951 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1952 { 1953 uint16_t cnt; 1954 __le16 __iomem *wptr; 1955 struct qla_hw_data *ha = vha->hw; 1956 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1957 1958 wptr = ®->mailbox_out[1]; 1959 1960 /* Load return mailbox registers. */ 1961 ha->flags.mbox_int = 1; 1962 ha->mailbox_out[0] = mb0; 1963 1964 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1965 ha->mailbox_out[cnt] = rd_reg_word(wptr); 1966 wptr++; 1967 } 1968 1969 if (!ha->mcp) 1970 ql_dbg(ql_dbg_async, vha, 0x5053, 1971 "MBX pointer ERROR.\n"); 1972 } 1973 1974 /** 1975 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1976 * @irq: interrupt number 1977 * @dev_id: SCSI driver HA context 1978 * 1979 * Called by system whenever the host adapter generates an interrupt. 1980 * 1981 * Returns handled flag. 1982 */ 1983 irqreturn_t 1984 qla82xx_intr_handler(int irq, void *dev_id) 1985 { 1986 scsi_qla_host_t *vha; 1987 struct qla_hw_data *ha; 1988 struct rsp_que *rsp; 1989 struct device_reg_82xx __iomem *reg; 1990 int status = 0, status1 = 0; 1991 unsigned long flags; 1992 unsigned long iter; 1993 uint32_t stat = 0; 1994 uint16_t mb[8]; 1995 1996 rsp = (struct rsp_que *) dev_id; 1997 if (!rsp) { 1998 ql_log(ql_log_info, NULL, 0xb053, 1999 "%s: NULL response queue pointer.\n", __func__); 2000 return IRQ_NONE; 2001 } 2002 ha = rsp->hw; 2003 2004 if (!ha->flags.msi_enabled) { 2005 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2006 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2007 return IRQ_NONE; 2008 2009 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2010 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2011 return IRQ_NONE; 2012 } 2013 2014 /* clear the interrupt */ 2015 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2016 2017 /* read twice to ensure write is flushed */ 2018 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2019 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2020 2021 reg = &ha->iobase->isp82; 2022 2023 spin_lock_irqsave(&ha->hardware_lock, flags); 2024 vha = pci_get_drvdata(ha->pdev); 2025 for (iter = 1; iter--; ) { 2026 2027 if (rd_reg_dword(®->host_int)) { 2028 stat = rd_reg_dword(®->host_status); 2029 2030 switch (stat & 0xff) { 2031 case 0x1: 2032 case 0x2: 2033 case 0x10: 2034 case 0x11: 2035 qla82xx_mbx_completion(vha, MSW(stat)); 2036 status |= MBX_INTERRUPT; 2037 break; 2038 case 0x12: 2039 mb[0] = MSW(stat); 2040 mb[1] = rd_reg_word(®->mailbox_out[1]); 2041 mb[2] = rd_reg_word(®->mailbox_out[2]); 2042 mb[3] = rd_reg_word(®->mailbox_out[3]); 2043 qla2x00_async_event(vha, rsp, mb); 2044 break; 2045 case 0x13: 2046 qla24xx_process_response_queue(vha, rsp); 2047 break; 2048 default: 2049 ql_dbg(ql_dbg_async, vha, 0x5054, 2050 "Unrecognized interrupt type (%d).\n", 2051 stat & 0xff); 2052 break; 2053 } 2054 } 2055 wrt_reg_dword(®->host_int, 0); 2056 } 2057 2058 qla2x00_handle_mbx_completion(ha, status); 2059 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2060 2061 if (!ha->flags.msi_enabled) 2062 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2063 2064 return IRQ_HANDLED; 2065 } 2066 2067 irqreturn_t 2068 qla82xx_msix_default(int irq, void *dev_id) 2069 { 2070 scsi_qla_host_t *vha; 2071 struct qla_hw_data *ha; 2072 struct rsp_que *rsp; 2073 struct device_reg_82xx __iomem *reg; 2074 int status = 0; 2075 unsigned long flags; 2076 uint32_t stat = 0; 2077 uint32_t host_int = 0; 2078 uint16_t mb[8]; 2079 2080 rsp = (struct rsp_que *) dev_id; 2081 if (!rsp) { 2082 printk(KERN_INFO 2083 "%s(): NULL response queue pointer.\n", __func__); 2084 return IRQ_NONE; 2085 } 2086 ha = rsp->hw; 2087 2088 reg = &ha->iobase->isp82; 2089 2090 spin_lock_irqsave(&ha->hardware_lock, flags); 2091 vha = pci_get_drvdata(ha->pdev); 2092 do { 2093 host_int = rd_reg_dword(®->host_int); 2094 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2095 break; 2096 if (host_int) { 2097 stat = rd_reg_dword(®->host_status); 2098 2099 switch (stat & 0xff) { 2100 case 0x1: 2101 case 0x2: 2102 case 0x10: 2103 case 0x11: 2104 qla82xx_mbx_completion(vha, MSW(stat)); 2105 status |= MBX_INTERRUPT; 2106 break; 2107 case 0x12: 2108 mb[0] = MSW(stat); 2109 mb[1] = rd_reg_word(®->mailbox_out[1]); 2110 mb[2] = rd_reg_word(®->mailbox_out[2]); 2111 mb[3] = rd_reg_word(®->mailbox_out[3]); 2112 qla2x00_async_event(vha, rsp, mb); 2113 break; 2114 case 0x13: 2115 qla24xx_process_response_queue(vha, rsp); 2116 break; 2117 default: 2118 ql_dbg(ql_dbg_async, vha, 0x5041, 2119 "Unrecognized interrupt type (%d).\n", 2120 stat & 0xff); 2121 break; 2122 } 2123 } 2124 wrt_reg_dword(®->host_int, 0); 2125 } while (0); 2126 2127 qla2x00_handle_mbx_completion(ha, status); 2128 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2129 2130 return IRQ_HANDLED; 2131 } 2132 2133 irqreturn_t 2134 qla82xx_msix_rsp_q(int irq, void *dev_id) 2135 { 2136 scsi_qla_host_t *vha; 2137 struct qla_hw_data *ha; 2138 struct rsp_que *rsp; 2139 struct device_reg_82xx __iomem *reg; 2140 unsigned long flags; 2141 uint32_t host_int = 0; 2142 2143 rsp = (struct rsp_que *) dev_id; 2144 if (!rsp) { 2145 printk(KERN_INFO 2146 "%s(): NULL response queue pointer.\n", __func__); 2147 return IRQ_NONE; 2148 } 2149 2150 ha = rsp->hw; 2151 reg = &ha->iobase->isp82; 2152 spin_lock_irqsave(&ha->hardware_lock, flags); 2153 vha = pci_get_drvdata(ha->pdev); 2154 host_int = rd_reg_dword(®->host_int); 2155 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2156 goto out; 2157 qla24xx_process_response_queue(vha, rsp); 2158 wrt_reg_dword(®->host_int, 0); 2159 out: 2160 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2161 return IRQ_HANDLED; 2162 } 2163 2164 void 2165 qla82xx_poll(int irq, void *dev_id) 2166 { 2167 scsi_qla_host_t *vha; 2168 struct qla_hw_data *ha; 2169 struct rsp_que *rsp; 2170 struct device_reg_82xx __iomem *reg; 2171 int status = 0; 2172 uint32_t stat; 2173 uint32_t host_int = 0; 2174 uint16_t mb[8]; 2175 unsigned long flags; 2176 2177 rsp = (struct rsp_que *) dev_id; 2178 if (!rsp) { 2179 printk(KERN_INFO 2180 "%s(): NULL response queue pointer.\n", __func__); 2181 return; 2182 } 2183 ha = rsp->hw; 2184 2185 reg = &ha->iobase->isp82; 2186 spin_lock_irqsave(&ha->hardware_lock, flags); 2187 vha = pci_get_drvdata(ha->pdev); 2188 2189 host_int = rd_reg_dword(®->host_int); 2190 if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2191 goto out; 2192 if (host_int) { 2193 stat = rd_reg_dword(®->host_status); 2194 switch (stat & 0xff) { 2195 case 0x1: 2196 case 0x2: 2197 case 0x10: 2198 case 0x11: 2199 qla82xx_mbx_completion(vha, MSW(stat)); 2200 status |= MBX_INTERRUPT; 2201 break; 2202 case 0x12: 2203 mb[0] = MSW(stat); 2204 mb[1] = rd_reg_word(®->mailbox_out[1]); 2205 mb[2] = rd_reg_word(®->mailbox_out[2]); 2206 mb[3] = rd_reg_word(®->mailbox_out[3]); 2207 qla2x00_async_event(vha, rsp, mb); 2208 break; 2209 case 0x13: 2210 qla24xx_process_response_queue(vha, rsp); 2211 break; 2212 default: 2213 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2214 "Unrecognized interrupt type (%d).\n", 2215 stat * 0xff); 2216 break; 2217 } 2218 wrt_reg_dword(®->host_int, 0); 2219 } 2220 out: 2221 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2222 } 2223 2224 void 2225 qla82xx_enable_intrs(struct qla_hw_data *ha) 2226 { 2227 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2228 2229 qla82xx_mbx_intr_enable(vha); 2230 spin_lock_irq(&ha->hardware_lock); 2231 if (IS_QLA8044(ha)) 2232 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 2233 else 2234 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2235 spin_unlock_irq(&ha->hardware_lock); 2236 ha->interrupts_on = 1; 2237 } 2238 2239 void 2240 qla82xx_disable_intrs(struct qla_hw_data *ha) 2241 { 2242 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2243 2244 if (ha->interrupts_on) 2245 qla82xx_mbx_intr_disable(vha); 2246 2247 spin_lock_irq(&ha->hardware_lock); 2248 if (IS_QLA8044(ha)) 2249 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 2250 else 2251 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2252 spin_unlock_irq(&ha->hardware_lock); 2253 ha->interrupts_on = 0; 2254 } 2255 2256 void qla82xx_init_flags(struct qla_hw_data *ha) 2257 { 2258 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2259 2260 /* ISP 8021 initializations */ 2261 rwlock_init(&ha->hw_lock); 2262 ha->qdr_sn_window = -1; 2263 ha->ddr_mn_window = -1; 2264 ha->curr_window = 255; 2265 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2266 nx_legacy_intr = &legacy_intr[ha->portnum]; 2267 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2268 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2269 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2270 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2271 } 2272 2273 static inline void 2274 qla82xx_set_idc_version(scsi_qla_host_t *vha) 2275 { 2276 int idc_ver; 2277 uint32_t drv_active; 2278 struct qla_hw_data *ha = vha->hw; 2279 2280 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2281 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 2282 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 2283 QLA82XX_IDC_VERSION); 2284 ql_log(ql_log_info, vha, 0xb082, 2285 "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 2286 } else { 2287 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 2288 if (idc_ver != QLA82XX_IDC_VERSION) 2289 ql_log(ql_log_info, vha, 0xb083, 2290 "qla2xxx driver IDC version %d is not compatible " 2291 "with IDC version %d of the other drivers\n", 2292 QLA82XX_IDC_VERSION, idc_ver); 2293 } 2294 } 2295 2296 inline void 2297 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2298 { 2299 uint32_t drv_active; 2300 struct qla_hw_data *ha = vha->hw; 2301 2302 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2303 2304 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2305 if (drv_active == 0xffffffff) { 2306 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2307 QLA82XX_DRV_NOT_ACTIVE); 2308 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2309 } 2310 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2311 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2312 } 2313 2314 inline void 2315 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2316 { 2317 uint32_t drv_active; 2318 2319 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2320 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2321 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2322 } 2323 2324 static inline int 2325 qla82xx_need_reset(struct qla_hw_data *ha) 2326 { 2327 uint32_t drv_state; 2328 int rval; 2329 2330 if (ha->flags.nic_core_reset_owner) 2331 return 1; 2332 else { 2333 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2334 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2335 return rval; 2336 } 2337 } 2338 2339 static inline void 2340 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2341 { 2342 uint32_t drv_state; 2343 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2344 2345 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2346 2347 /* If reset value is all FF's, initialize DRV_STATE */ 2348 if (drv_state == 0xffffffff) { 2349 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2350 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2351 } 2352 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2353 ql_dbg(ql_dbg_init, vha, 0x00bb, 2354 "drv_state = 0x%08x.\n", drv_state); 2355 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2356 } 2357 2358 static inline void 2359 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2360 { 2361 uint32_t drv_state; 2362 2363 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2364 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2365 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2366 } 2367 2368 static inline void 2369 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2370 { 2371 uint32_t qsnt_state; 2372 2373 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2374 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2375 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2376 } 2377 2378 void 2379 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2380 { 2381 struct qla_hw_data *ha = vha->hw; 2382 uint32_t qsnt_state; 2383 2384 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2385 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2386 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2387 } 2388 2389 static int 2390 qla82xx_load_fw(scsi_qla_host_t *vha) 2391 { 2392 int rst; 2393 struct fw_blob *blob; 2394 struct qla_hw_data *ha = vha->hw; 2395 2396 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2397 ql_log(ql_log_fatal, vha, 0x009f, 2398 "Error during CRB initialization.\n"); 2399 return QLA_FUNCTION_FAILED; 2400 } 2401 udelay(500); 2402 2403 /* Bring QM and CAMRAM out of reset */ 2404 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2405 rst &= ~((1 << 28) | (1 << 24)); 2406 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2407 2408 /* 2409 * FW Load priority: 2410 * 1) Operational firmware residing in flash. 2411 * 2) Firmware via request-firmware interface (.bin file). 2412 */ 2413 if (ql2xfwloadbin == 2) 2414 goto try_blob_fw; 2415 2416 ql_log(ql_log_info, vha, 0x00a0, 2417 "Attempting to load firmware from flash.\n"); 2418 2419 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2420 ql_log(ql_log_info, vha, 0x00a1, 2421 "Firmware loaded successfully from flash.\n"); 2422 return QLA_SUCCESS; 2423 } else { 2424 ql_log(ql_log_warn, vha, 0x0108, 2425 "Firmware load from flash failed.\n"); 2426 } 2427 2428 try_blob_fw: 2429 ql_log(ql_log_info, vha, 0x00a2, 2430 "Attempting to load firmware from blob.\n"); 2431 2432 /* Load firmware blob. */ 2433 blob = ha->hablob = qla2x00_request_firmware(vha); 2434 if (!blob) { 2435 ql_log(ql_log_fatal, vha, 0x00a3, 2436 "Firmware image not present.\n"); 2437 goto fw_load_failed; 2438 } 2439 2440 /* Validating firmware blob */ 2441 if (qla82xx_validate_firmware_blob(vha, 2442 QLA82XX_FLASH_ROMIMAGE)) { 2443 /* Fallback to URI format */ 2444 if (qla82xx_validate_firmware_blob(vha, 2445 QLA82XX_UNIFIED_ROMIMAGE)) { 2446 ql_log(ql_log_fatal, vha, 0x00a4, 2447 "No valid firmware image found.\n"); 2448 return QLA_FUNCTION_FAILED; 2449 } 2450 } 2451 2452 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2453 ql_log(ql_log_info, vha, 0x00a5, 2454 "Firmware loaded successfully from binary blob.\n"); 2455 return QLA_SUCCESS; 2456 } 2457 2458 ql_log(ql_log_fatal, vha, 0x00a6, 2459 "Firmware load failed for binary blob.\n"); 2460 blob->fw = NULL; 2461 blob = NULL; 2462 2463 fw_load_failed: 2464 return QLA_FUNCTION_FAILED; 2465 } 2466 2467 int 2468 qla82xx_start_firmware(scsi_qla_host_t *vha) 2469 { 2470 uint16_t lnk; 2471 struct qla_hw_data *ha = vha->hw; 2472 2473 /* scrub dma mask expansion register */ 2474 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2475 2476 /* Put both the PEG CMD and RCV PEG to default state 2477 * of 0 before resetting the hardware 2478 */ 2479 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2480 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2481 2482 /* Overwrite stale initialization register values */ 2483 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2484 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2485 2486 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2487 ql_log(ql_log_fatal, vha, 0x00a7, 2488 "Error trying to start fw.\n"); 2489 return QLA_FUNCTION_FAILED; 2490 } 2491 2492 /* Handshake with the card before we register the devices. */ 2493 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2494 ql_log(ql_log_fatal, vha, 0x00aa, 2495 "Error during card handshake.\n"); 2496 return QLA_FUNCTION_FAILED; 2497 } 2498 2499 /* Negotiated Link width */ 2500 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2501 ha->link_width = (lnk >> 4) & 0x3f; 2502 2503 /* Synchronize with Receive peg */ 2504 return qla82xx_check_rcvpeg_state(ha); 2505 } 2506 2507 static __le32 * 2508 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 2509 uint32_t length) 2510 { 2511 uint32_t i; 2512 uint32_t val; 2513 struct qla_hw_data *ha = vha->hw; 2514 2515 /* Dword reads to flash. */ 2516 for (i = 0; i < length/4; i++, faddr += 4) { 2517 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2518 ql_log(ql_log_warn, vha, 0x0106, 2519 "Do ROM fast read failed.\n"); 2520 goto done_read; 2521 } 2522 dwptr[i] = cpu_to_le32(val); 2523 } 2524 done_read: 2525 return dwptr; 2526 } 2527 2528 static int 2529 qla82xx_unprotect_flash(struct qla_hw_data *ha) 2530 { 2531 int ret; 2532 uint32_t val; 2533 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2534 2535 ret = ql82xx_rom_lock_d(ha); 2536 if (ret < 0) { 2537 ql_log(ql_log_warn, vha, 0xb014, 2538 "ROM Lock failed.\n"); 2539 return ret; 2540 } 2541 2542 ret = qla82xx_read_status_reg(ha, &val); 2543 if (ret < 0) 2544 goto done_unprotect; 2545 2546 val &= ~(BLOCK_PROTECT_BITS << 2); 2547 ret = qla82xx_write_status_reg(ha, val); 2548 if (ret < 0) { 2549 val |= (BLOCK_PROTECT_BITS << 2); 2550 qla82xx_write_status_reg(ha, val); 2551 } 2552 2553 if (qla82xx_write_disable_flash(ha) != 0) 2554 ql_log(ql_log_warn, vha, 0xb015, 2555 "Write disable failed.\n"); 2556 2557 done_unprotect: 2558 qla82xx_rom_unlock(ha); 2559 return ret; 2560 } 2561 2562 static int 2563 qla82xx_protect_flash(struct qla_hw_data *ha) 2564 { 2565 int ret; 2566 uint32_t val; 2567 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2568 2569 ret = ql82xx_rom_lock_d(ha); 2570 if (ret < 0) { 2571 ql_log(ql_log_warn, vha, 0xb016, 2572 "ROM Lock failed.\n"); 2573 return ret; 2574 } 2575 2576 ret = qla82xx_read_status_reg(ha, &val); 2577 if (ret < 0) 2578 goto done_protect; 2579 2580 val |= (BLOCK_PROTECT_BITS << 2); 2581 /* LOCK all sectors */ 2582 ret = qla82xx_write_status_reg(ha, val); 2583 if (ret < 0) 2584 ql_log(ql_log_warn, vha, 0xb017, 2585 "Write status register failed.\n"); 2586 2587 if (qla82xx_write_disable_flash(ha) != 0) 2588 ql_log(ql_log_warn, vha, 0xb018, 2589 "Write disable failed.\n"); 2590 done_protect: 2591 qla82xx_rom_unlock(ha); 2592 return ret; 2593 } 2594 2595 static int 2596 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2597 { 2598 int ret = 0; 2599 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2600 2601 ret = ql82xx_rom_lock_d(ha); 2602 if (ret < 0) { 2603 ql_log(ql_log_warn, vha, 0xb019, 2604 "ROM Lock failed.\n"); 2605 return ret; 2606 } 2607 2608 qla82xx_flash_set_write_enable(ha); 2609 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2610 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2611 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2612 2613 if (qla82xx_wait_rom_done(ha)) { 2614 ql_log(ql_log_warn, vha, 0xb01a, 2615 "Error waiting for rom done.\n"); 2616 ret = -1; 2617 goto done; 2618 } 2619 ret = qla82xx_flash_wait_write_finish(ha); 2620 done: 2621 qla82xx_rom_unlock(ha); 2622 return ret; 2623 } 2624 2625 /* 2626 * Address and length are byte address 2627 */ 2628 void * 2629 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2630 uint32_t offset, uint32_t length) 2631 { 2632 scsi_block_requests(vha->host); 2633 qla82xx_read_flash_data(vha, buf, offset, length); 2634 scsi_unblock_requests(vha->host); 2635 return buf; 2636 } 2637 2638 static int 2639 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr, 2640 uint32_t faddr, uint32_t dwords) 2641 { 2642 int ret; 2643 uint32_t liter; 2644 uint32_t rest_addr; 2645 dma_addr_t optrom_dma; 2646 void *optrom = NULL; 2647 int page_mode = 0; 2648 struct qla_hw_data *ha = vha->hw; 2649 2650 ret = -1; 2651 2652 /* Prepare burst-capable write on supported ISPs. */ 2653 if (page_mode && !(faddr & 0xfff) && 2654 dwords > OPTROM_BURST_DWORDS) { 2655 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2656 &optrom_dma, GFP_KERNEL); 2657 if (!optrom) { 2658 ql_log(ql_log_warn, vha, 0xb01b, 2659 "Unable to allocate memory " 2660 "for optrom burst write (%x KB).\n", 2661 OPTROM_BURST_SIZE / 1024); 2662 } 2663 } 2664 2665 rest_addr = ha->fdt_block_size - 1; 2666 2667 ret = qla82xx_unprotect_flash(ha); 2668 if (ret) { 2669 ql_log(ql_log_warn, vha, 0xb01c, 2670 "Unable to unprotect flash for update.\n"); 2671 goto write_done; 2672 } 2673 2674 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2675 /* Are we at the beginning of a sector? */ 2676 if ((faddr & rest_addr) == 0) { 2677 2678 ret = qla82xx_erase_sector(ha, faddr); 2679 if (ret) { 2680 ql_log(ql_log_warn, vha, 0xb01d, 2681 "Unable to erase sector: address=%x.\n", 2682 faddr); 2683 break; 2684 } 2685 } 2686 2687 /* Go with burst-write. */ 2688 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2689 /* Copy data to DMA'ble buffer. */ 2690 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2691 2692 ret = qla2x00_load_ram(vha, optrom_dma, 2693 (ha->flash_data_off | faddr), 2694 OPTROM_BURST_DWORDS); 2695 if (ret != QLA_SUCCESS) { 2696 ql_log(ql_log_warn, vha, 0xb01e, 2697 "Unable to burst-write optrom segment " 2698 "(%x/%x/%llx).\n", ret, 2699 (ha->flash_data_off | faddr), 2700 (unsigned long long)optrom_dma); 2701 ql_log(ql_log_warn, vha, 0xb01f, 2702 "Reverting to slow-write.\n"); 2703 2704 dma_free_coherent(&ha->pdev->dev, 2705 OPTROM_BURST_SIZE, optrom, optrom_dma); 2706 optrom = NULL; 2707 } else { 2708 liter += OPTROM_BURST_DWORDS - 1; 2709 faddr += OPTROM_BURST_DWORDS - 1; 2710 dwptr += OPTROM_BURST_DWORDS - 1; 2711 continue; 2712 } 2713 } 2714 2715 ret = qla82xx_write_flash_dword(ha, faddr, 2716 le32_to_cpu(*dwptr)); 2717 if (ret) { 2718 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2719 "Unable to program flash address=%x data=%x.\n", 2720 faddr, *dwptr); 2721 break; 2722 } 2723 } 2724 2725 ret = qla82xx_protect_flash(ha); 2726 if (ret) 2727 ql_log(ql_log_warn, vha, 0xb021, 2728 "Unable to protect flash after update.\n"); 2729 write_done: 2730 if (optrom) 2731 dma_free_coherent(&ha->pdev->dev, 2732 OPTROM_BURST_SIZE, optrom, optrom_dma); 2733 return ret; 2734 } 2735 2736 int 2737 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2738 uint32_t offset, uint32_t length) 2739 { 2740 int rval; 2741 2742 /* Suspend HBA. */ 2743 scsi_block_requests(vha->host); 2744 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2745 scsi_unblock_requests(vha->host); 2746 2747 /* Convert return ISP82xx to generic */ 2748 if (rval) 2749 rval = QLA_FUNCTION_FAILED; 2750 else 2751 rval = QLA_SUCCESS; 2752 return rval; 2753 } 2754 2755 void 2756 qla82xx_start_iocbs(scsi_qla_host_t *vha) 2757 { 2758 struct qla_hw_data *ha = vha->hw; 2759 struct req_que *req = ha->req_q_map[0]; 2760 uint32_t dbval; 2761 2762 /* Adjust ring index. */ 2763 req->ring_index++; 2764 if (req->ring_index == req->length) { 2765 req->ring_index = 0; 2766 req->ring_ptr = req->ring; 2767 } else 2768 req->ring_ptr++; 2769 2770 dbval = 0x04 | (ha->portnum << 5); 2771 2772 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2773 if (ql2xdbwr) 2774 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 2775 else { 2776 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2777 wmb(); 2778 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { 2779 wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2780 wmb(); 2781 } 2782 } 2783 } 2784 2785 static void 2786 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2787 { 2788 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2789 uint32_t lock_owner = 0; 2790 2791 if (qla82xx_rom_lock(ha)) { 2792 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2793 /* Someone else is holding the lock. */ 2794 ql_log(ql_log_info, vha, 0xb022, 2795 "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 2796 } 2797 /* 2798 * Either we got the lock, or someone 2799 * else died while holding it. 2800 * In either case, unlock. 2801 */ 2802 qla82xx_rom_unlock(ha); 2803 } 2804 2805 /* 2806 * qla82xx_device_bootstrap 2807 * Initialize device, set DEV_READY, start fw 2808 * 2809 * Note: 2810 * IDC lock must be held upon entry 2811 * 2812 * Return: 2813 * Success : 0 2814 * Failed : 1 2815 */ 2816 static int 2817 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2818 { 2819 int rval = QLA_SUCCESS; 2820 int i; 2821 uint32_t old_count, count; 2822 struct qla_hw_data *ha = vha->hw; 2823 int need_reset = 0; 2824 2825 need_reset = qla82xx_need_reset(ha); 2826 2827 if (need_reset) { 2828 /* We are trying to perform a recovery here. */ 2829 if (ha->flags.isp82xx_fw_hung) 2830 qla82xx_rom_lock_recovery(ha); 2831 } else { 2832 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2833 for (i = 0; i < 10; i++) { 2834 msleep(200); 2835 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2836 if (count != old_count) { 2837 rval = QLA_SUCCESS; 2838 goto dev_ready; 2839 } 2840 } 2841 qla82xx_rom_lock_recovery(ha); 2842 } 2843 2844 /* set to DEV_INITIALIZING */ 2845 ql_log(ql_log_info, vha, 0x009e, 2846 "HW State: INITIALIZING.\n"); 2847 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2848 2849 qla82xx_idc_unlock(ha); 2850 rval = qla82xx_start_firmware(vha); 2851 qla82xx_idc_lock(ha); 2852 2853 if (rval != QLA_SUCCESS) { 2854 ql_log(ql_log_fatal, vha, 0x00ad, 2855 "HW State: FAILED.\n"); 2856 qla82xx_clear_drv_active(ha); 2857 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2858 return rval; 2859 } 2860 2861 dev_ready: 2862 ql_log(ql_log_info, vha, 0x00ae, 2863 "HW State: READY.\n"); 2864 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2865 2866 return QLA_SUCCESS; 2867 } 2868 2869 /* 2870 * qla82xx_need_qsnt_handler 2871 * Code to start quiescence sequence 2872 * 2873 * Note: 2874 * IDC lock must be held upon entry 2875 * 2876 * Return: void 2877 */ 2878 2879 static void 2880 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2881 { 2882 struct qla_hw_data *ha = vha->hw; 2883 uint32_t dev_state, drv_state, drv_active; 2884 unsigned long reset_timeout; 2885 2886 if (vha->flags.online) { 2887 /*Block any further I/O and wait for pending cmnds to complete*/ 2888 qla2x00_quiesce_io(vha); 2889 } 2890 2891 /* Set the quiescence ready bit */ 2892 qla82xx_set_qsnt_ready(ha); 2893 2894 /*wait for 30 secs for other functions to ack */ 2895 reset_timeout = jiffies + (30 * HZ); 2896 2897 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2898 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2899 /* Its 2 that is written when qsnt is acked, moving one bit */ 2900 drv_active = drv_active << 0x01; 2901 2902 while (drv_state != drv_active) { 2903 2904 if (time_after_eq(jiffies, reset_timeout)) { 2905 /* quiescence timeout, other functions didn't ack 2906 * changing the state to DEV_READY 2907 */ 2908 ql_log(ql_log_info, vha, 0xb023, 2909 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 2910 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 2911 drv_active, drv_state); 2912 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2913 QLA8XXX_DEV_READY); 2914 ql_log(ql_log_info, vha, 0xb025, 2915 "HW State: DEV_READY.\n"); 2916 qla82xx_idc_unlock(ha); 2917 qla2x00_perform_loop_resync(vha); 2918 qla82xx_idc_lock(ha); 2919 2920 qla82xx_clear_qsnt_ready(vha); 2921 return; 2922 } 2923 2924 qla82xx_idc_unlock(ha); 2925 msleep(1000); 2926 qla82xx_idc_lock(ha); 2927 2928 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2929 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2930 drv_active = drv_active << 0x01; 2931 } 2932 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2933 /* everyone acked so set the state to DEV_QUIESCENCE */ 2934 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 2935 ql_log(ql_log_info, vha, 0xb026, 2936 "HW State: DEV_QUIESCENT.\n"); 2937 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2938 } 2939 } 2940 2941 /* 2942 * qla82xx_wait_for_state_change 2943 * Wait for device state to change from given current state 2944 * 2945 * Note: 2946 * IDC lock must not be held upon entry 2947 * 2948 * Return: 2949 * Changed device state. 2950 */ 2951 uint32_t 2952 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2953 { 2954 struct qla_hw_data *ha = vha->hw; 2955 uint32_t dev_state; 2956 2957 do { 2958 msleep(1000); 2959 qla82xx_idc_lock(ha); 2960 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2961 qla82xx_idc_unlock(ha); 2962 } while (dev_state == curr_state); 2963 2964 return dev_state; 2965 } 2966 2967 void 2968 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2969 { 2970 struct qla_hw_data *ha = vha->hw; 2971 2972 /* Disable the board */ 2973 ql_log(ql_log_fatal, vha, 0x00b8, 2974 "Disabling the board.\n"); 2975 2976 if (IS_QLA82XX(ha)) { 2977 qla82xx_clear_drv_active(ha); 2978 qla82xx_idc_unlock(ha); 2979 } else if (IS_QLA8044(ha)) { 2980 qla8044_clear_drv_active(ha); 2981 qla8044_idc_unlock(ha); 2982 } 2983 2984 /* Set DEV_FAILED flag to disable timer */ 2985 vha->device_flags |= DFLG_DEV_FAILED; 2986 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 2987 qla2x00_mark_all_devices_lost(vha); 2988 vha->flags.online = 0; 2989 vha->flags.init_done = 0; 2990 } 2991 2992 /* 2993 * qla82xx_need_reset_handler 2994 * Code to start reset sequence 2995 * 2996 * Note: 2997 * IDC lock must be held upon entry 2998 * 2999 * Return: 3000 * Success : 0 3001 * Failed : 1 3002 */ 3003 static void 3004 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3005 { 3006 uint32_t dev_state, drv_state, drv_active; 3007 uint32_t active_mask = 0; 3008 unsigned long reset_timeout; 3009 struct qla_hw_data *ha = vha->hw; 3010 struct req_que *req = ha->req_q_map[0]; 3011 3012 if (vha->flags.online) { 3013 qla82xx_idc_unlock(ha); 3014 qla2x00_abort_isp_cleanup(vha); 3015 ha->isp_ops->get_flash_version(vha, req->ring); 3016 ha->isp_ops->nvram_config(vha); 3017 qla82xx_idc_lock(ha); 3018 } 3019 3020 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3021 if (!ha->flags.nic_core_reset_owner) { 3022 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3023 "reset_acknowledged by 0x%x\n", ha->portnum); 3024 qla82xx_set_rst_ready(ha); 3025 } else { 3026 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3027 drv_active &= active_mask; 3028 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3029 "active_mask: 0x%08x\n", active_mask); 3030 } 3031 3032 /* wait for 10 seconds for reset ack from all functions */ 3033 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3034 3035 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3036 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3037 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3038 3039 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3040 "drv_state: 0x%08x, drv_active: 0x%08x, " 3041 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3042 drv_state, drv_active, dev_state, active_mask); 3043 3044 while (drv_state != drv_active && 3045 dev_state != QLA8XXX_DEV_INITIALIZING) { 3046 if (time_after_eq(jiffies, reset_timeout)) { 3047 ql_log(ql_log_warn, vha, 0x00b5, 3048 "Reset timeout.\n"); 3049 break; 3050 } 3051 qla82xx_idc_unlock(ha); 3052 msleep(1000); 3053 qla82xx_idc_lock(ha); 3054 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3055 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3056 if (ha->flags.nic_core_reset_owner) 3057 drv_active &= active_mask; 3058 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3059 } 3060 3061 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3062 "drv_state: 0x%08x, drv_active: 0x%08x, " 3063 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3064 drv_state, drv_active, dev_state, active_mask); 3065 3066 ql_log(ql_log_info, vha, 0x00b6, 3067 "Device state is 0x%x = %s.\n", 3068 dev_state, 3069 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3070 3071 /* Force to DEV_COLD unless someone else is starting a reset */ 3072 if (dev_state != QLA8XXX_DEV_INITIALIZING && 3073 dev_state != QLA8XXX_DEV_COLD) { 3074 ql_log(ql_log_info, vha, 0x00b7, 3075 "HW State: COLD/RE-INIT.\n"); 3076 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3077 qla82xx_set_rst_ready(ha); 3078 if (ql2xmdenable) { 3079 if (qla82xx_md_collect(vha)) 3080 ql_log(ql_log_warn, vha, 0xb02c, 3081 "Minidump not collected.\n"); 3082 } else 3083 ql_log(ql_log_warn, vha, 0xb04f, 3084 "Minidump disabled.\n"); 3085 } 3086 } 3087 3088 int 3089 qla82xx_check_md_needed(scsi_qla_host_t *vha) 3090 { 3091 struct qla_hw_data *ha = vha->hw; 3092 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3093 int rval = QLA_SUCCESS; 3094 3095 fw_major_version = ha->fw_major_version; 3096 fw_minor_version = ha->fw_minor_version; 3097 fw_subminor_version = ha->fw_subminor_version; 3098 3099 rval = qla2x00_get_fw_version(vha); 3100 if (rval != QLA_SUCCESS) 3101 return rval; 3102 3103 if (ql2xmdenable) { 3104 if (!ha->fw_dumped) { 3105 if ((fw_major_version != ha->fw_major_version || 3106 fw_minor_version != ha->fw_minor_version || 3107 fw_subminor_version != ha->fw_subminor_version) || 3108 (ha->prev_minidump_failed)) { 3109 ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3110 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 3111 fw_major_version, fw_minor_version, 3112 fw_subminor_version, 3113 ha->fw_major_version, 3114 ha->fw_minor_version, 3115 ha->fw_subminor_version, 3116 ha->prev_minidump_failed); 3117 /* Release MiniDump resources */ 3118 qla82xx_md_free(vha); 3119 /* ALlocate MiniDump resources */ 3120 qla82xx_md_prep(vha); 3121 } 3122 } else 3123 ql_log(ql_log_info, vha, 0xb02e, 3124 "Firmware dump available to retrieve\n"); 3125 } 3126 return rval; 3127 } 3128 3129 3130 static int 3131 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3132 { 3133 uint32_t fw_heartbeat_counter; 3134 int status = 0; 3135 3136 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3137 QLA82XX_PEG_ALIVE_COUNTER); 3138 /* all 0xff, assume AER/EEH in progress, ignore */ 3139 if (fw_heartbeat_counter == 0xffffffff) { 3140 ql_dbg(ql_dbg_timer, vha, 0x6003, 3141 "FW heartbeat counter is 0xffffffff, " 3142 "returning status=%d.\n", status); 3143 return status; 3144 } 3145 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3146 vha->seconds_since_last_heartbeat++; 3147 /* FW not alive after 2 seconds */ 3148 if (vha->seconds_since_last_heartbeat == 2) { 3149 vha->seconds_since_last_heartbeat = 0; 3150 status = 1; 3151 } 3152 } else 3153 vha->seconds_since_last_heartbeat = 0; 3154 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3155 if (status) 3156 ql_dbg(ql_dbg_timer, vha, 0x6004, 3157 "Returning status=%d.\n", status); 3158 return status; 3159 } 3160 3161 /* 3162 * qla82xx_device_state_handler 3163 * Main state handler 3164 * 3165 * Note: 3166 * IDC lock must be held upon entry 3167 * 3168 * Return: 3169 * Success : 0 3170 * Failed : 1 3171 */ 3172 int 3173 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3174 { 3175 uint32_t dev_state; 3176 uint32_t old_dev_state; 3177 int rval = QLA_SUCCESS; 3178 unsigned long dev_init_timeout; 3179 struct qla_hw_data *ha = vha->hw; 3180 int loopcount = 0; 3181 3182 qla82xx_idc_lock(ha); 3183 if (!vha->flags.init_done) { 3184 qla82xx_set_drv_active(vha); 3185 qla82xx_set_idc_version(vha); 3186 } 3187 3188 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3189 old_dev_state = dev_state; 3190 ql_log(ql_log_info, vha, 0x009b, 3191 "Device state is 0x%x = %s.\n", 3192 dev_state, 3193 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3194 3195 /* wait for 30 seconds for device to go ready */ 3196 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3197 3198 while (1) { 3199 3200 if (time_after_eq(jiffies, dev_init_timeout)) { 3201 ql_log(ql_log_fatal, vha, 0x009c, 3202 "Device init failed.\n"); 3203 rval = QLA_FUNCTION_FAILED; 3204 break; 3205 } 3206 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3207 if (old_dev_state != dev_state) { 3208 loopcount = 0; 3209 old_dev_state = dev_state; 3210 } 3211 if (loopcount < 5) { 3212 ql_log(ql_log_info, vha, 0x009d, 3213 "Device state is 0x%x = %s.\n", 3214 dev_state, 3215 dev_state < MAX_STATES ? qdev_state(dev_state) : 3216 "Unknown"); 3217 } 3218 3219 switch (dev_state) { 3220 case QLA8XXX_DEV_READY: 3221 ha->flags.nic_core_reset_owner = 0; 3222 goto rel_lock; 3223 case QLA8XXX_DEV_COLD: 3224 rval = qla82xx_device_bootstrap(vha); 3225 break; 3226 case QLA8XXX_DEV_INITIALIZING: 3227 qla82xx_idc_unlock(ha); 3228 msleep(1000); 3229 qla82xx_idc_lock(ha); 3230 break; 3231 case QLA8XXX_DEV_NEED_RESET: 3232 if (!ql2xdontresethba) 3233 qla82xx_need_reset_handler(vha); 3234 else { 3235 qla82xx_idc_unlock(ha); 3236 msleep(1000); 3237 qla82xx_idc_lock(ha); 3238 } 3239 dev_init_timeout = jiffies + 3240 (ha->fcoe_dev_init_timeout * HZ); 3241 break; 3242 case QLA8XXX_DEV_NEED_QUIESCENT: 3243 qla82xx_need_qsnt_handler(vha); 3244 /* Reset timeout value after quiescence handler */ 3245 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3246 * HZ); 3247 break; 3248 case QLA8XXX_DEV_QUIESCENT: 3249 /* Owner will exit and other will wait for the state 3250 * to get changed 3251 */ 3252 if (ha->flags.quiesce_owner) 3253 goto rel_lock; 3254 3255 qla82xx_idc_unlock(ha); 3256 msleep(1000); 3257 qla82xx_idc_lock(ha); 3258 3259 /* Reset timeout value after quiescence handler */ 3260 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3261 * HZ); 3262 break; 3263 case QLA8XXX_DEV_FAILED: 3264 qla8xxx_dev_failed_handler(vha); 3265 rval = QLA_FUNCTION_FAILED; 3266 goto exit; 3267 default: 3268 qla82xx_idc_unlock(ha); 3269 msleep(1000); 3270 qla82xx_idc_lock(ha); 3271 } 3272 loopcount++; 3273 } 3274 rel_lock: 3275 qla82xx_idc_unlock(ha); 3276 exit: 3277 return rval; 3278 } 3279 3280 static int qla82xx_check_temp(scsi_qla_host_t *vha) 3281 { 3282 uint32_t temp, temp_state, temp_val; 3283 struct qla_hw_data *ha = vha->hw; 3284 3285 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 3286 temp_state = qla82xx_get_temp_state(temp); 3287 temp_val = qla82xx_get_temp_val(temp); 3288 3289 if (temp_state == QLA82XX_TEMP_PANIC) { 3290 ql_log(ql_log_warn, vha, 0x600e, 3291 "Device temperature %d degrees C exceeds " 3292 " maximum allowed. Hardware has been shut down.\n", 3293 temp_val); 3294 return 1; 3295 } else if (temp_state == QLA82XX_TEMP_WARN) { 3296 ql_log(ql_log_warn, vha, 0x600f, 3297 "Device temperature %d degrees C exceeds " 3298 "operating range. Immediate action needed.\n", 3299 temp_val); 3300 } 3301 return 0; 3302 } 3303 3304 int qla82xx_read_temperature(scsi_qla_host_t *vha) 3305 { 3306 uint32_t temp; 3307 3308 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 3309 return qla82xx_get_temp_val(temp); 3310 } 3311 3312 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3313 { 3314 struct qla_hw_data *ha = vha->hw; 3315 3316 if (ha->flags.mbox_busy) { 3317 ha->flags.mbox_int = 1; 3318 ha->flags.mbox_busy = 0; 3319 ql_log(ql_log_warn, vha, 0x6010, 3320 "Doing premature completion of mbx command.\n"); 3321 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3322 complete(&ha->mbx_intr_comp); 3323 } 3324 } 3325 3326 void qla82xx_watchdog(scsi_qla_host_t *vha) 3327 { 3328 uint32_t dev_state, halt_status; 3329 struct qla_hw_data *ha = vha->hw; 3330 3331 /* don't poll if reset is going on */ 3332 if (!ha->flags.nic_core_reset_hdlr_active) { 3333 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3334 if (qla82xx_check_temp(vha)) { 3335 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3336 ha->flags.isp82xx_fw_hung = 1; 3337 qla82xx_clear_pending_mbx(vha); 3338 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 3339 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3340 ql_log(ql_log_warn, vha, 0x6001, 3341 "Adapter reset needed.\n"); 3342 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3343 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3344 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3345 ql_log(ql_log_warn, vha, 0x6002, 3346 "Quiescent needed.\n"); 3347 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3348 } else if (dev_state == QLA8XXX_DEV_FAILED && 3349 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 3350 vha->flags.online == 1) { 3351 ql_log(ql_log_warn, vha, 0xb055, 3352 "Adapter state is failed. Offlining.\n"); 3353 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3354 ha->flags.isp82xx_fw_hung = 1; 3355 qla82xx_clear_pending_mbx(vha); 3356 } else { 3357 if (qla82xx_check_fw_alive(vha)) { 3358 ql_dbg(ql_dbg_timer, vha, 0x6011, 3359 "disabling pause transmit on port 0 & 1.\n"); 3360 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3361 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3362 halt_status = qla82xx_rd_32(ha, 3363 QLA82XX_PEG_HALT_STATUS1); 3364 ql_log(ql_log_info, vha, 0x6005, 3365 "dumping hw/fw registers:.\n " 3366 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3367 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3368 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3369 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3370 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3371 qla82xx_rd_32(ha, 3372 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3373 qla82xx_rd_32(ha, 3374 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3375 qla82xx_rd_32(ha, 3376 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3377 qla82xx_rd_32(ha, 3378 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3379 qla82xx_rd_32(ha, 3380 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3381 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3382 ql_log(ql_log_warn, vha, 0xb052, 3383 "Firmware aborted with " 3384 "error code 0x00006700. Device is " 3385 "being reset.\n"); 3386 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3387 set_bit(ISP_UNRECOVERABLE, 3388 &vha->dpc_flags); 3389 } else { 3390 ql_log(ql_log_info, vha, 0x6006, 3391 "Detect abort needed.\n"); 3392 set_bit(ISP_ABORT_NEEDED, 3393 &vha->dpc_flags); 3394 } 3395 ha->flags.isp82xx_fw_hung = 1; 3396 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3397 qla82xx_clear_pending_mbx(vha); 3398 } 3399 } 3400 } 3401 } 3402 3403 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3404 { 3405 int rval = -1; 3406 struct qla_hw_data *ha = vha->hw; 3407 3408 if (IS_QLA82XX(ha)) 3409 rval = qla82xx_device_state_handler(vha); 3410 else if (IS_QLA8044(ha)) { 3411 qla8044_idc_lock(ha); 3412 /* Decide the reset ownership */ 3413 qla83xx_reset_ownership(vha); 3414 qla8044_idc_unlock(ha); 3415 rval = qla8044_device_state_handler(vha); 3416 } 3417 return rval; 3418 } 3419 3420 void 3421 qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3422 { 3423 struct qla_hw_data *ha = vha->hw; 3424 uint32_t dev_state = 0; 3425 3426 if (IS_QLA82XX(ha)) 3427 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3428 else if (IS_QLA8044(ha)) 3429 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 3430 3431 if (dev_state == QLA8XXX_DEV_READY) { 3432 ql_log(ql_log_info, vha, 0xb02f, 3433 "HW State: NEED RESET\n"); 3434 if (IS_QLA82XX(ha)) { 3435 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3436 QLA8XXX_DEV_NEED_RESET); 3437 ha->flags.nic_core_reset_owner = 1; 3438 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3439 "reset_owner is 0x%x\n", ha->portnum); 3440 } else if (IS_QLA8044(ha)) 3441 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 3442 QLA8XXX_DEV_NEED_RESET); 3443 } else 3444 ql_log(ql_log_info, vha, 0xb031, 3445 "Device state is 0x%x = %s.\n", 3446 dev_state, 3447 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3448 } 3449 3450 /* 3451 * qla82xx_abort_isp 3452 * Resets ISP and aborts all outstanding commands. 3453 * 3454 * Input: 3455 * ha = adapter block pointer. 3456 * 3457 * Returns: 3458 * 0 = success 3459 */ 3460 int 3461 qla82xx_abort_isp(scsi_qla_host_t *vha) 3462 { 3463 int rval = -1; 3464 struct qla_hw_data *ha = vha->hw; 3465 3466 if (vha->device_flags & DFLG_DEV_FAILED) { 3467 ql_log(ql_log_warn, vha, 0x8024, 3468 "Device in failed state, exiting.\n"); 3469 return QLA_SUCCESS; 3470 } 3471 ha->flags.nic_core_reset_hdlr_active = 1; 3472 3473 qla82xx_idc_lock(ha); 3474 qla82xx_set_reset_owner(vha); 3475 qla82xx_idc_unlock(ha); 3476 3477 if (IS_QLA82XX(ha)) 3478 rval = qla82xx_device_state_handler(vha); 3479 else if (IS_QLA8044(ha)) { 3480 qla8044_idc_lock(ha); 3481 /* Decide the reset ownership */ 3482 qla83xx_reset_ownership(vha); 3483 qla8044_idc_unlock(ha); 3484 rval = qla8044_device_state_handler(vha); 3485 } 3486 3487 qla82xx_idc_lock(ha); 3488 qla82xx_clear_rst_ready(ha); 3489 qla82xx_idc_unlock(ha); 3490 3491 if (rval == QLA_SUCCESS) { 3492 ha->flags.isp82xx_fw_hung = 0; 3493 ha->flags.nic_core_reset_hdlr_active = 0; 3494 qla82xx_restart_isp(vha); 3495 } 3496 3497 if (rval) { 3498 vha->flags.online = 1; 3499 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3500 if (ha->isp_abort_cnt == 0) { 3501 ql_log(ql_log_warn, vha, 0x8027, 3502 "ISP error recover failed - board " 3503 "disabled.\n"); 3504 /* 3505 * The next call disables the board 3506 * completely. 3507 */ 3508 ha->isp_ops->reset_adapter(vha); 3509 vha->flags.online = 0; 3510 clear_bit(ISP_ABORT_RETRY, 3511 &vha->dpc_flags); 3512 rval = QLA_SUCCESS; 3513 } else { /* schedule another ISP abort */ 3514 ha->isp_abort_cnt--; 3515 ql_log(ql_log_warn, vha, 0x8036, 3516 "ISP abort - retry remaining %d.\n", 3517 ha->isp_abort_cnt); 3518 rval = QLA_FUNCTION_FAILED; 3519 } 3520 } else { 3521 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3522 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3523 "ISP error recovery - retrying (%d) more times.\n", 3524 ha->isp_abort_cnt); 3525 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3526 rval = QLA_FUNCTION_FAILED; 3527 } 3528 } 3529 return rval; 3530 } 3531 3532 /* 3533 * qla82xx_fcoe_ctx_reset 3534 * Perform a quick reset and aborts all outstanding commands. 3535 * This will only perform an FCoE context reset and avoids a full blown 3536 * chip reset. 3537 * 3538 * Input: 3539 * ha = adapter block pointer. 3540 * is_reset_path = flag for identifying the reset path. 3541 * 3542 * Returns: 3543 * 0 = success 3544 */ 3545 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3546 { 3547 int rval = QLA_FUNCTION_FAILED; 3548 3549 if (vha->flags.online) { 3550 /* Abort all outstanding commands, so as to be requeued later */ 3551 qla2x00_abort_isp_cleanup(vha); 3552 } 3553 3554 /* Stop currently executing firmware. 3555 * This will destroy existing FCoE context at the F/W end. 3556 */ 3557 qla2x00_try_to_stop_firmware(vha); 3558 3559 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3560 rval = qla82xx_restart_isp(vha); 3561 3562 return rval; 3563 } 3564 3565 /* 3566 * qla2x00_wait_for_fcoe_ctx_reset 3567 * Wait till the FCoE context is reset. 3568 * 3569 * Note: 3570 * Does context switching here. 3571 * Release SPIN_LOCK (if any) before calling this routine. 3572 * 3573 * Return: 3574 * Success (fcoe_ctx reset is done) : 0 3575 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3576 */ 3577 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3578 { 3579 int status = QLA_FUNCTION_FAILED; 3580 unsigned long wait_reset; 3581 3582 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3583 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3584 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3585 && time_before(jiffies, wait_reset)) { 3586 3587 set_current_state(TASK_UNINTERRUPTIBLE); 3588 schedule_timeout(HZ); 3589 3590 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3591 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3592 status = QLA_SUCCESS; 3593 break; 3594 } 3595 } 3596 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3597 "%s: status=%d.\n", __func__, status); 3598 3599 return status; 3600 } 3601 3602 void 3603 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3604 { 3605 int i, fw_state = 0; 3606 unsigned long flags; 3607 struct qla_hw_data *ha = vha->hw; 3608 3609 /* Check if 82XX firmware is alive or not 3610 * We may have arrived here from NEED_RESET 3611 * detection only 3612 */ 3613 if (!ha->flags.isp82xx_fw_hung) { 3614 for (i = 0; i < 2; i++) { 3615 msleep(1000); 3616 if (IS_QLA82XX(ha)) 3617 fw_state = qla82xx_check_fw_alive(vha); 3618 else if (IS_QLA8044(ha)) 3619 fw_state = qla8044_check_fw_alive(vha); 3620 if (fw_state) { 3621 ha->flags.isp82xx_fw_hung = 1; 3622 qla82xx_clear_pending_mbx(vha); 3623 break; 3624 } 3625 } 3626 } 3627 ql_dbg(ql_dbg_init, vha, 0x00b0, 3628 "Entered %s fw_hung=%d.\n", 3629 __func__, ha->flags.isp82xx_fw_hung); 3630 3631 /* Abort all commands gracefully if fw NOT hung */ 3632 if (!ha->flags.isp82xx_fw_hung) { 3633 int cnt, que; 3634 srb_t *sp; 3635 struct req_que *req; 3636 3637 spin_lock_irqsave(&ha->hardware_lock, flags); 3638 for (que = 0; que < ha->max_req_queues; que++) { 3639 req = ha->req_q_map[que]; 3640 if (!req) 3641 continue; 3642 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 3643 sp = req->outstanding_cmds[cnt]; 3644 if (sp) { 3645 if ((!sp->u.scmd.crc_ctx || 3646 (sp->flags & 3647 SRB_FCP_CMND_DMA_VALID)) && 3648 !ha->flags.isp82xx_fw_hung) { 3649 spin_unlock_irqrestore( 3650 &ha->hardware_lock, flags); 3651 if (ha->isp_ops->abort_command(sp)) { 3652 ql_log(ql_log_info, vha, 3653 0x00b1, 3654 "mbx abort failed.\n"); 3655 } else { 3656 ql_log(ql_log_info, vha, 3657 0x00b2, 3658 "mbx abort success.\n"); 3659 } 3660 spin_lock_irqsave(&ha->hardware_lock, flags); 3661 } 3662 } 3663 } 3664 } 3665 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3666 3667 /* Wait for pending cmds (physical and virtual) to complete */ 3668 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3669 WAIT_HOST) == QLA_SUCCESS) { 3670 ql_dbg(ql_dbg_init, vha, 0x00b3, 3671 "Done wait for " 3672 "pending commands.\n"); 3673 } else { 3674 WARN_ON_ONCE(true); 3675 } 3676 } 3677 } 3678 3679 /* Minidump related functions */ 3680 static int 3681 qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3682 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3683 { 3684 struct qla_hw_data *ha = vha->hw; 3685 struct qla82xx_md_entry_crb *crb_entry; 3686 uint32_t read_value, opcode, poll_time; 3687 uint32_t addr, index, crb_addr; 3688 unsigned long wtime; 3689 struct qla82xx_md_template_hdr *tmplt_hdr; 3690 uint32_t rval = QLA_SUCCESS; 3691 int i; 3692 3693 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3694 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3695 crb_addr = crb_entry->addr; 3696 3697 for (i = 0; i < crb_entry->op_count; i++) { 3698 opcode = crb_entry->crb_ctrl.opcode; 3699 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3700 qla82xx_md_rw_32(ha, crb_addr, 3701 crb_entry->value_1, 1); 3702 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3703 } 3704 3705 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3706 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3707 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3708 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3709 } 3710 3711 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3712 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3713 read_value &= crb_entry->value_2; 3714 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3715 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3716 read_value |= crb_entry->value_3; 3717 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3718 } 3719 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3720 } 3721 3722 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3723 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3724 read_value |= crb_entry->value_3; 3725 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3726 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3727 } 3728 3729 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3730 poll_time = crb_entry->crb_strd.poll_timeout; 3731 wtime = jiffies + poll_time; 3732 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3733 3734 do { 3735 if ((read_value & crb_entry->value_2) 3736 == crb_entry->value_1) 3737 break; 3738 else if (time_after_eq(jiffies, wtime)) { 3739 /* capturing dump failed */ 3740 rval = QLA_FUNCTION_FAILED; 3741 break; 3742 } else 3743 read_value = qla82xx_md_rw_32(ha, 3744 crb_addr, 0, 0); 3745 } while (1); 3746 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3747 } 3748 3749 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3750 if (crb_entry->crb_strd.state_index_a) { 3751 index = crb_entry->crb_strd.state_index_a; 3752 addr = tmplt_hdr->saved_state_array[index]; 3753 } else 3754 addr = crb_addr; 3755 3756 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3757 index = crb_entry->crb_ctrl.state_index_v; 3758 tmplt_hdr->saved_state_array[index] = read_value; 3759 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3760 } 3761 3762 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3763 if (crb_entry->crb_strd.state_index_a) { 3764 index = crb_entry->crb_strd.state_index_a; 3765 addr = tmplt_hdr->saved_state_array[index]; 3766 } else 3767 addr = crb_addr; 3768 3769 if (crb_entry->crb_ctrl.state_index_v) { 3770 index = crb_entry->crb_ctrl.state_index_v; 3771 read_value = 3772 tmplt_hdr->saved_state_array[index]; 3773 } else 3774 read_value = crb_entry->value_1; 3775 3776 qla82xx_md_rw_32(ha, addr, read_value, 1); 3777 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3778 } 3779 3780 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3781 index = crb_entry->crb_ctrl.state_index_v; 3782 read_value = tmplt_hdr->saved_state_array[index]; 3783 read_value <<= crb_entry->crb_ctrl.shl; 3784 read_value >>= crb_entry->crb_ctrl.shr; 3785 if (crb_entry->value_2) 3786 read_value &= crb_entry->value_2; 3787 read_value |= crb_entry->value_3; 3788 read_value += crb_entry->value_1; 3789 tmplt_hdr->saved_state_array[index] = read_value; 3790 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3791 } 3792 crb_addr += crb_entry->crb_strd.addr_stride; 3793 } 3794 return rval; 3795 } 3796 3797 static void 3798 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3799 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3800 { 3801 struct qla_hw_data *ha = vha->hw; 3802 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3803 struct qla82xx_md_entry_rdocm *ocm_hdr; 3804 __le32 *data_ptr = *d_ptr; 3805 3806 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3807 r_addr = ocm_hdr->read_addr; 3808 r_stride = ocm_hdr->read_addr_stride; 3809 loop_cnt = ocm_hdr->op_count; 3810 3811 for (i = 0; i < loop_cnt; i++) { 3812 r_value = rd_reg_dword(r_addr + ha->nx_pcibase); 3813 *data_ptr++ = cpu_to_le32(r_value); 3814 r_addr += r_stride; 3815 } 3816 *d_ptr = data_ptr; 3817 } 3818 3819 static void 3820 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3821 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3822 { 3823 struct qla_hw_data *ha = vha->hw; 3824 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3825 struct qla82xx_md_entry_mux *mux_hdr; 3826 __le32 *data_ptr = *d_ptr; 3827 3828 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3829 r_addr = mux_hdr->read_addr; 3830 s_addr = mux_hdr->select_addr; 3831 s_stride = mux_hdr->select_value_stride; 3832 s_value = mux_hdr->select_value; 3833 loop_cnt = mux_hdr->op_count; 3834 3835 for (i = 0; i < loop_cnt; i++) { 3836 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3837 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3838 *data_ptr++ = cpu_to_le32(s_value); 3839 *data_ptr++ = cpu_to_le32(r_value); 3840 s_value += s_stride; 3841 } 3842 *d_ptr = data_ptr; 3843 } 3844 3845 static void 3846 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3847 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3848 { 3849 struct qla_hw_data *ha = vha->hw; 3850 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3851 struct qla82xx_md_entry_crb *crb_hdr; 3852 __le32 *data_ptr = *d_ptr; 3853 3854 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3855 r_addr = crb_hdr->addr; 3856 r_stride = crb_hdr->crb_strd.addr_stride; 3857 loop_cnt = crb_hdr->op_count; 3858 3859 for (i = 0; i < loop_cnt; i++) { 3860 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3861 *data_ptr++ = cpu_to_le32(r_addr); 3862 *data_ptr++ = cpu_to_le32(r_value); 3863 r_addr += r_stride; 3864 } 3865 *d_ptr = data_ptr; 3866 } 3867 3868 static int 3869 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3870 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3871 { 3872 struct qla_hw_data *ha = vha->hw; 3873 uint32_t addr, r_addr, c_addr, t_r_addr; 3874 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3875 unsigned long p_wait, w_time, p_mask; 3876 uint32_t c_value_w, c_value_r; 3877 struct qla82xx_md_entry_cache *cache_hdr; 3878 int rval = QLA_FUNCTION_FAILED; 3879 __le32 *data_ptr = *d_ptr; 3880 3881 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3882 loop_count = cache_hdr->op_count; 3883 r_addr = cache_hdr->read_addr; 3884 c_addr = cache_hdr->control_addr; 3885 c_value_w = cache_hdr->cache_ctrl.write_value; 3886 3887 t_r_addr = cache_hdr->tag_reg_addr; 3888 t_value = cache_hdr->addr_ctrl.init_tag_value; 3889 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3890 p_wait = cache_hdr->cache_ctrl.poll_wait; 3891 p_mask = cache_hdr->cache_ctrl.poll_mask; 3892 3893 for (i = 0; i < loop_count; i++) { 3894 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3895 if (c_value_w) 3896 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3897 3898 if (p_mask) { 3899 w_time = jiffies + p_wait; 3900 do { 3901 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3902 if ((c_value_r & p_mask) == 0) 3903 break; 3904 else if (time_after_eq(jiffies, w_time)) { 3905 /* capturing dump failed */ 3906 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3907 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3908 "w_time: 0x%lx\n", 3909 c_value_r, p_mask, w_time); 3910 return rval; 3911 } 3912 } while (1); 3913 } 3914 3915 addr = r_addr; 3916 for (k = 0; k < r_cnt; k++) { 3917 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3918 *data_ptr++ = cpu_to_le32(r_value); 3919 addr += cache_hdr->read_ctrl.read_addr_stride; 3920 } 3921 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3922 } 3923 *d_ptr = data_ptr; 3924 return QLA_SUCCESS; 3925 } 3926 3927 static void 3928 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3929 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3930 { 3931 struct qla_hw_data *ha = vha->hw; 3932 uint32_t addr, r_addr, c_addr, t_r_addr; 3933 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3934 uint32_t c_value_w; 3935 struct qla82xx_md_entry_cache *cache_hdr; 3936 __le32 *data_ptr = *d_ptr; 3937 3938 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3939 loop_count = cache_hdr->op_count; 3940 r_addr = cache_hdr->read_addr; 3941 c_addr = cache_hdr->control_addr; 3942 c_value_w = cache_hdr->cache_ctrl.write_value; 3943 3944 t_r_addr = cache_hdr->tag_reg_addr; 3945 t_value = cache_hdr->addr_ctrl.init_tag_value; 3946 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3947 3948 for (i = 0; i < loop_count; i++) { 3949 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3950 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3951 addr = r_addr; 3952 for (k = 0; k < r_cnt; k++) { 3953 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3954 *data_ptr++ = cpu_to_le32(r_value); 3955 addr += cache_hdr->read_ctrl.read_addr_stride; 3956 } 3957 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3958 } 3959 *d_ptr = data_ptr; 3960 } 3961 3962 static void 3963 qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3964 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3965 { 3966 struct qla_hw_data *ha = vha->hw; 3967 uint32_t s_addr, r_addr; 3968 uint32_t r_stride, r_value, r_cnt, qid = 0; 3969 uint32_t i, k, loop_cnt; 3970 struct qla82xx_md_entry_queue *q_hdr; 3971 __le32 *data_ptr = *d_ptr; 3972 3973 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3974 s_addr = q_hdr->select_addr; 3975 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3976 r_stride = q_hdr->rd_strd.read_addr_stride; 3977 loop_cnt = q_hdr->op_count; 3978 3979 for (i = 0; i < loop_cnt; i++) { 3980 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3981 r_addr = q_hdr->read_addr; 3982 for (k = 0; k < r_cnt; k++) { 3983 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3984 *data_ptr++ = cpu_to_le32(r_value); 3985 r_addr += r_stride; 3986 } 3987 qid += q_hdr->q_strd.queue_id_stride; 3988 } 3989 *d_ptr = data_ptr; 3990 } 3991 3992 static void 3993 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3994 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 3995 { 3996 struct qla_hw_data *ha = vha->hw; 3997 uint32_t r_addr, r_value; 3998 uint32_t i, loop_cnt; 3999 struct qla82xx_md_entry_rdrom *rom_hdr; 4000 __le32 *data_ptr = *d_ptr; 4001 4002 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4003 r_addr = rom_hdr->read_addr; 4004 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4005 4006 for (i = 0; i < loop_cnt; i++) { 4007 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4008 (r_addr & 0xFFFF0000), 1); 4009 r_value = qla82xx_md_rw_32(ha, 4010 MD_DIRECT_ROM_READ_BASE + 4011 (r_addr & 0x0000FFFF), 0, 0); 4012 *data_ptr++ = cpu_to_le32(r_value); 4013 r_addr += sizeof(uint32_t); 4014 } 4015 *d_ptr = data_ptr; 4016 } 4017 4018 static int 4019 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4020 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 4021 { 4022 struct qla_hw_data *ha = vha->hw; 4023 uint32_t r_addr, r_value, r_data; 4024 uint32_t i, j, loop_cnt; 4025 struct qla82xx_md_entry_rdmem *m_hdr; 4026 unsigned long flags; 4027 int rval = QLA_FUNCTION_FAILED; 4028 __le32 *data_ptr = *d_ptr; 4029 4030 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4031 r_addr = m_hdr->read_addr; 4032 loop_cnt = m_hdr->read_data_size/16; 4033 4034 if (r_addr & 0xf) { 4035 ql_log(ql_log_warn, vha, 0xb033, 4036 "Read addr 0x%x not 16 bytes aligned\n", r_addr); 4037 return rval; 4038 } 4039 4040 if (m_hdr->read_data_size % 16) { 4041 ql_log(ql_log_warn, vha, 0xb034, 4042 "Read data[0x%x] not multiple of 16 bytes\n", 4043 m_hdr->read_data_size); 4044 return rval; 4045 } 4046 4047 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4048 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4049 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4050 4051 write_lock_irqsave(&ha->hw_lock, flags); 4052 for (i = 0; i < loop_cnt; i++) { 4053 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4054 r_value = 0; 4055 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4056 r_value = MIU_TA_CTL_ENABLE; 4057 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4058 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4059 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4060 4061 for (j = 0; j < MAX_CTL_CHECK; j++) { 4062 r_value = qla82xx_md_rw_32(ha, 4063 MD_MIU_TEST_AGT_CTRL, 0, 0); 4064 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4065 break; 4066 } 4067 4068 if (j >= MAX_CTL_CHECK) { 4069 printk_ratelimited(KERN_ERR 4070 "failed to read through agent\n"); 4071 write_unlock_irqrestore(&ha->hw_lock, flags); 4072 return rval; 4073 } 4074 4075 for (j = 0; j < 4; j++) { 4076 r_data = qla82xx_md_rw_32(ha, 4077 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4078 *data_ptr++ = cpu_to_le32(r_data); 4079 } 4080 r_addr += 16; 4081 } 4082 write_unlock_irqrestore(&ha->hw_lock, flags); 4083 *d_ptr = data_ptr; 4084 return QLA_SUCCESS; 4085 } 4086 4087 int 4088 qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4089 { 4090 struct qla_hw_data *ha = vha->hw; 4091 uint64_t chksum = 0; 4092 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4093 int count = ha->md_template_size/sizeof(uint32_t); 4094 4095 while (count-- > 0) 4096 chksum += *d_ptr++; 4097 while (chksum >> 32) 4098 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4099 return ~chksum; 4100 } 4101 4102 static void 4103 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4104 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4105 { 4106 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4107 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4108 "Skipping entry[%d]: " 4109 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4110 index, entry_hdr->entry_type, 4111 entry_hdr->d_ctrl.entry_capture_mask); 4112 } 4113 4114 int 4115 qla82xx_md_collect(scsi_qla_host_t *vha) 4116 { 4117 struct qla_hw_data *ha = vha->hw; 4118 int no_entry_hdr = 0; 4119 qla82xx_md_entry_hdr_t *entry_hdr; 4120 struct qla82xx_md_template_hdr *tmplt_hdr; 4121 __le32 *data_ptr; 4122 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4123 int i = 0, rval = QLA_FUNCTION_FAILED; 4124 4125 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4126 data_ptr = ha->md_dump; 4127 4128 if (ha->fw_dumped) { 4129 ql_log(ql_log_warn, vha, 0xb037, 4130 "Firmware has been previously dumped (%p) " 4131 "-- ignoring request.\n", ha->fw_dump); 4132 goto md_failed; 4133 } 4134 4135 ha->fw_dumped = false; 4136 4137 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4138 ql_log(ql_log_warn, vha, 0xb038, 4139 "Memory not allocated for minidump capture\n"); 4140 goto md_failed; 4141 } 4142 4143 if (ha->flags.isp82xx_no_md_cap) { 4144 ql_log(ql_log_warn, vha, 0xb054, 4145 "Forced reset from application, " 4146 "ignore minidump capture\n"); 4147 ha->flags.isp82xx_no_md_cap = 0; 4148 goto md_failed; 4149 } 4150 4151 if (qla82xx_validate_template_chksum(vha)) { 4152 ql_log(ql_log_info, vha, 0xb039, 4153 "Template checksum validation error\n"); 4154 goto md_failed; 4155 } 4156 4157 no_entry_hdr = tmplt_hdr->num_of_entries; 4158 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4159 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4160 4161 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4162 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4163 4164 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4165 4166 /* Validate whether required debug level is set */ 4167 if ((f_capture_mask & 0x3) != 0x3) { 4168 ql_log(ql_log_warn, vha, 0xb03c, 4169 "Minimum required capture mask[0x%x] level not set\n", 4170 f_capture_mask); 4171 goto md_failed; 4172 } 4173 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4174 4175 tmplt_hdr->driver_info[0] = vha->host_no; 4176 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4177 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4178 QLA_DRIVER_BETA_VER; 4179 4180 total_data_size = ha->md_dump_size; 4181 4182 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4183 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4184 4185 /* Check whether template obtained is valid */ 4186 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4187 ql_log(ql_log_warn, vha, 0xb04e, 4188 "Bad template header entry type: 0x%x obtained\n", 4189 tmplt_hdr->entry_type); 4190 goto md_failed; 4191 } 4192 4193 entry_hdr = (qla82xx_md_entry_hdr_t *) 4194 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4195 4196 /* Walk through the entry headers */ 4197 for (i = 0; i < no_entry_hdr; i++) { 4198 4199 if (data_collected > total_data_size) { 4200 ql_log(ql_log_warn, vha, 0xb03e, 4201 "More MiniDump data collected: [0x%x]\n", 4202 data_collected); 4203 goto md_failed; 4204 } 4205 4206 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4207 ql2xmdcapmask)) { 4208 entry_hdr->d_ctrl.driver_flags |= 4209 QLA82XX_DBG_SKIPPED_FLAG; 4210 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4211 "Skipping entry[%d]: " 4212 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4213 i, entry_hdr->entry_type, 4214 entry_hdr->d_ctrl.entry_capture_mask); 4215 goto skip_nxt_entry; 4216 } 4217 4218 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4219 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4220 "entry_type: 0x%x, capture_mask: 0x%x\n", 4221 __func__, i, data_ptr, entry_hdr, 4222 entry_hdr->entry_type, 4223 entry_hdr->d_ctrl.entry_capture_mask); 4224 4225 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4226 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4227 data_collected, (ha->md_dump_size - data_collected)); 4228 4229 /* Decode the entry type and take 4230 * required action to capture debug data */ 4231 switch (entry_hdr->entry_type) { 4232 case QLA82XX_RDEND: 4233 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4234 break; 4235 case QLA82XX_CNTRL: 4236 rval = qla82xx_minidump_process_control(vha, 4237 entry_hdr, &data_ptr); 4238 if (rval != QLA_SUCCESS) { 4239 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4240 goto md_failed; 4241 } 4242 break; 4243 case QLA82XX_RDCRB: 4244 qla82xx_minidump_process_rdcrb(vha, 4245 entry_hdr, &data_ptr); 4246 break; 4247 case QLA82XX_RDMEM: 4248 rval = qla82xx_minidump_process_rdmem(vha, 4249 entry_hdr, &data_ptr); 4250 if (rval != QLA_SUCCESS) { 4251 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4252 goto md_failed; 4253 } 4254 break; 4255 case QLA82XX_BOARD: 4256 case QLA82XX_RDROM: 4257 qla82xx_minidump_process_rdrom(vha, 4258 entry_hdr, &data_ptr); 4259 break; 4260 case QLA82XX_L2DTG: 4261 case QLA82XX_L2ITG: 4262 case QLA82XX_L2DAT: 4263 case QLA82XX_L2INS: 4264 rval = qla82xx_minidump_process_l2tag(vha, 4265 entry_hdr, &data_ptr); 4266 if (rval != QLA_SUCCESS) { 4267 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4268 goto md_failed; 4269 } 4270 break; 4271 case QLA82XX_L1DAT: 4272 case QLA82XX_L1INS: 4273 qla82xx_minidump_process_l1cache(vha, 4274 entry_hdr, &data_ptr); 4275 break; 4276 case QLA82XX_RDOCM: 4277 qla82xx_minidump_process_rdocm(vha, 4278 entry_hdr, &data_ptr); 4279 break; 4280 case QLA82XX_RDMUX: 4281 qla82xx_minidump_process_rdmux(vha, 4282 entry_hdr, &data_ptr); 4283 break; 4284 case QLA82XX_QUEUE: 4285 qla82xx_minidump_process_queue(vha, 4286 entry_hdr, &data_ptr); 4287 break; 4288 case QLA82XX_RDNOP: 4289 default: 4290 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4291 break; 4292 } 4293 4294 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4295 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4296 4297 data_collected = (uint8_t *)data_ptr - 4298 (uint8_t *)ha->md_dump; 4299 skip_nxt_entry: 4300 entry_hdr = (qla82xx_md_entry_hdr_t *) 4301 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4302 } 4303 4304 if (data_collected != total_data_size) { 4305 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4306 "MiniDump data mismatch: Data collected: [0x%x]," 4307 "total_data_size:[0x%x]\n", 4308 data_collected, total_data_size); 4309 goto md_failed; 4310 } 4311 4312 ql_log(ql_log_info, vha, 0xb044, 4313 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4314 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4315 ha->fw_dumped = true; 4316 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4317 4318 md_failed: 4319 return rval; 4320 } 4321 4322 int 4323 qla82xx_md_alloc(scsi_qla_host_t *vha) 4324 { 4325 struct qla_hw_data *ha = vha->hw; 4326 int i, k; 4327 struct qla82xx_md_template_hdr *tmplt_hdr; 4328 4329 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4330 4331 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4332 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4333 ql_log(ql_log_info, vha, 0xb045, 4334 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4335 ql2xmdcapmask); 4336 } 4337 4338 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4339 if (i & ql2xmdcapmask) 4340 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4341 } 4342 4343 if (ha->md_dump) { 4344 ql_log(ql_log_warn, vha, 0xb046, 4345 "Firmware dump previously allocated.\n"); 4346 return 1; 4347 } 4348 4349 ha->md_dump = vmalloc(ha->md_dump_size); 4350 if (ha->md_dump == NULL) { 4351 ql_log(ql_log_warn, vha, 0xb047, 4352 "Unable to allocate memory for Minidump size " 4353 "(0x%x).\n", ha->md_dump_size); 4354 return 1; 4355 } 4356 return 0; 4357 } 4358 4359 void 4360 qla82xx_md_free(scsi_qla_host_t *vha) 4361 { 4362 struct qla_hw_data *ha = vha->hw; 4363 4364 /* Release the template header allocated */ 4365 if (ha->md_tmplt_hdr) { 4366 ql_log(ql_log_info, vha, 0xb048, 4367 "Free MiniDump template: %p, size (%d KB)\n", 4368 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4369 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4370 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4371 ha->md_tmplt_hdr = NULL; 4372 } 4373 4374 /* Release the template data buffer allocated */ 4375 if (ha->md_dump) { 4376 ql_log(ql_log_info, vha, 0xb049, 4377 "Free MiniDump memory: %p, size (%d KB)\n", 4378 ha->md_dump, ha->md_dump_size / 1024); 4379 vfree(ha->md_dump); 4380 ha->md_dump_size = 0; 4381 ha->md_dump = NULL; 4382 } 4383 } 4384 4385 void 4386 qla82xx_md_prep(scsi_qla_host_t *vha) 4387 { 4388 struct qla_hw_data *ha = vha->hw; 4389 int rval; 4390 4391 /* Get Minidump template size */ 4392 rval = qla82xx_md_get_template_size(vha); 4393 if (rval == QLA_SUCCESS) { 4394 ql_log(ql_log_info, vha, 0xb04a, 4395 "MiniDump Template size obtained (%d KB)\n", 4396 ha->md_template_size / 1024); 4397 4398 /* Get Minidump template */ 4399 if (IS_QLA8044(ha)) 4400 rval = qla8044_md_get_template(vha); 4401 else 4402 rval = qla82xx_md_get_template(vha); 4403 4404 if (rval == QLA_SUCCESS) { 4405 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4406 "MiniDump Template obtained\n"); 4407 4408 /* Allocate memory for minidump */ 4409 rval = qla82xx_md_alloc(vha); 4410 if (rval == QLA_SUCCESS) 4411 ql_log(ql_log_info, vha, 0xb04c, 4412 "MiniDump memory allocated (%d KB)\n", 4413 ha->md_dump_size / 1024); 4414 else { 4415 ql_log(ql_log_info, vha, 0xb04d, 4416 "Free MiniDump template: %p, size: (%d KB)\n", 4417 ha->md_tmplt_hdr, 4418 ha->md_template_size / 1024); 4419 dma_free_coherent(&ha->pdev->dev, 4420 ha->md_template_size, 4421 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4422 ha->md_tmplt_hdr = NULL; 4423 } 4424 4425 } 4426 } 4427 } 4428 4429 int 4430 qla82xx_beacon_on(struct scsi_qla_host *vha) 4431 { 4432 4433 int rval; 4434 struct qla_hw_data *ha = vha->hw; 4435 4436 qla82xx_idc_lock(ha); 4437 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4438 4439 if (rval) { 4440 ql_log(ql_log_warn, vha, 0xb050, 4441 "mbx set led config failed in %s\n", __func__); 4442 goto exit; 4443 } 4444 ha->beacon_blink_led = 1; 4445 exit: 4446 qla82xx_idc_unlock(ha); 4447 return rval; 4448 } 4449 4450 int 4451 qla82xx_beacon_off(struct scsi_qla_host *vha) 4452 { 4453 4454 int rval; 4455 struct qla_hw_data *ha = vha->hw; 4456 4457 qla82xx_idc_lock(ha); 4458 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4459 4460 if (rval) { 4461 ql_log(ql_log_warn, vha, 0xb051, 4462 "mbx set led config failed in %s\n", __func__); 4463 goto exit; 4464 } 4465 ha->beacon_blink_led = 0; 4466 exit: 4467 qla82xx_idc_unlock(ha); 4468 return rval; 4469 } 4470 4471 void 4472 qla82xx_fw_dump(scsi_qla_host_t *vha) 4473 { 4474 struct qla_hw_data *ha = vha->hw; 4475 4476 if (!ha->allow_cna_fw_dump) 4477 return; 4478 4479 scsi_block_requests(vha->host); 4480 ha->flags.isp82xx_no_md_cap = 1; 4481 qla82xx_idc_lock(ha); 4482 qla82xx_set_reset_owner(vha); 4483 qla82xx_idc_unlock(ha); 4484 qla2x00_wait_for_chip_reset(vha); 4485 scsi_unblock_requests(vha->host); 4486 } 4487