1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/pci.h> 10 11 #define MASK(n) ((1ULL<<(n))-1) 12 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 13 ((addr >> 25) & 0x3ff)) 14 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 15 ((addr >> 25) & 0x3ff)) 16 #define MS_WIN(addr) (addr & 0x0ffc0000) 17 #define QLA82XX_PCI_MN_2M (0) 18 #define QLA82XX_PCI_MS_2M (0x80000) 19 #define QLA82XX_PCI_OCM0_2M (0xc0000) 20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 22 #define BLOCK_PROTECT_BITS 0x0F 23 24 /* CRB window related */ 25 #define CRB_BLK(off) ((off >> 20) & 0x3f) 26 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 27 #define CRB_WINDOW_2M (0x130060) 28 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 29 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 30 ((off) & 0xf0000)) 31 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 32 #define CRB_INDIRECT_2M (0x1e0000UL) 33 34 #define MAX_CRB_XFORM 60 35 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 36 int qla82xx_crb_table_initialized; 37 38 #define qla82xx_crb_addr_transform(name) \ 39 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 40 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 41 42 static void qla82xx_crb_addr_transform_setup(void) 43 { 44 qla82xx_crb_addr_transform(XDMA); 45 qla82xx_crb_addr_transform(TIMR); 46 qla82xx_crb_addr_transform(SRE); 47 qla82xx_crb_addr_transform(SQN3); 48 qla82xx_crb_addr_transform(SQN2); 49 qla82xx_crb_addr_transform(SQN1); 50 qla82xx_crb_addr_transform(SQN0); 51 qla82xx_crb_addr_transform(SQS3); 52 qla82xx_crb_addr_transform(SQS2); 53 qla82xx_crb_addr_transform(SQS1); 54 qla82xx_crb_addr_transform(SQS0); 55 qla82xx_crb_addr_transform(RPMX7); 56 qla82xx_crb_addr_transform(RPMX6); 57 qla82xx_crb_addr_transform(RPMX5); 58 qla82xx_crb_addr_transform(RPMX4); 59 qla82xx_crb_addr_transform(RPMX3); 60 qla82xx_crb_addr_transform(RPMX2); 61 qla82xx_crb_addr_transform(RPMX1); 62 qla82xx_crb_addr_transform(RPMX0); 63 qla82xx_crb_addr_transform(ROMUSB); 64 qla82xx_crb_addr_transform(SN); 65 qla82xx_crb_addr_transform(QMN); 66 qla82xx_crb_addr_transform(QMS); 67 qla82xx_crb_addr_transform(PGNI); 68 qla82xx_crb_addr_transform(PGND); 69 qla82xx_crb_addr_transform(PGN3); 70 qla82xx_crb_addr_transform(PGN2); 71 qla82xx_crb_addr_transform(PGN1); 72 qla82xx_crb_addr_transform(PGN0); 73 qla82xx_crb_addr_transform(PGSI); 74 qla82xx_crb_addr_transform(PGSD); 75 qla82xx_crb_addr_transform(PGS3); 76 qla82xx_crb_addr_transform(PGS2); 77 qla82xx_crb_addr_transform(PGS1); 78 qla82xx_crb_addr_transform(PGS0); 79 qla82xx_crb_addr_transform(PS); 80 qla82xx_crb_addr_transform(PH); 81 qla82xx_crb_addr_transform(NIU); 82 qla82xx_crb_addr_transform(I2Q); 83 qla82xx_crb_addr_transform(EG); 84 qla82xx_crb_addr_transform(MN); 85 qla82xx_crb_addr_transform(MS); 86 qla82xx_crb_addr_transform(CAS2); 87 qla82xx_crb_addr_transform(CAS1); 88 qla82xx_crb_addr_transform(CAS0); 89 qla82xx_crb_addr_transform(CAM); 90 qla82xx_crb_addr_transform(C2C1); 91 qla82xx_crb_addr_transform(C2C0); 92 qla82xx_crb_addr_transform(SMB); 93 qla82xx_crb_addr_transform(OCM0); 94 /* 95 * Used only in P3 just define it for P2 also. 96 */ 97 qla82xx_crb_addr_transform(I2C0); 98 99 qla82xx_crb_table_initialized = 1; 100 } 101 102 struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 103 {{{0, 0, 0, 0} } }, 104 {{{1, 0x0100000, 0x0102000, 0x120000}, 105 {1, 0x0110000, 0x0120000, 0x130000}, 106 {1, 0x0120000, 0x0122000, 0x124000}, 107 {1, 0x0130000, 0x0132000, 0x126000}, 108 {1, 0x0140000, 0x0142000, 0x128000}, 109 {1, 0x0150000, 0x0152000, 0x12a000}, 110 {1, 0x0160000, 0x0170000, 0x110000}, 111 {1, 0x0170000, 0x0172000, 0x12e000}, 112 {0, 0x0000000, 0x0000000, 0x000000}, 113 {0, 0x0000000, 0x0000000, 0x000000}, 114 {0, 0x0000000, 0x0000000, 0x000000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {1, 0x01e0000, 0x01e0800, 0x122000}, 119 {0, 0x0000000, 0x0000000, 0x000000} } } , 120 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 121 {{{0, 0, 0, 0} } }, 122 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 123 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 124 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 125 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 126 {{{1, 0x0800000, 0x0802000, 0x170000}, 127 {0, 0x0000000, 0x0000000, 0x000000}, 128 {0, 0x0000000, 0x0000000, 0x000000}, 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 142 {{{1, 0x0900000, 0x0902000, 0x174000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 158 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 174 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 190 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 191 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 192 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 193 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 194 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 195 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 196 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 197 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 198 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 199 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 200 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 201 {{{0, 0, 0, 0} } }, 202 {{{0, 0, 0, 0} } }, 203 {{{0, 0, 0, 0} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 208 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 209 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 210 {{{0} } }, 211 {{{1, 0x2100000, 0x2102000, 0x120000}, 212 {1, 0x2110000, 0x2120000, 0x130000}, 213 {1, 0x2120000, 0x2122000, 0x124000}, 214 {1, 0x2130000, 0x2132000, 0x126000}, 215 {1, 0x2140000, 0x2142000, 0x128000}, 216 {1, 0x2150000, 0x2152000, 0x12a000}, 217 {1, 0x2160000, 0x2170000, 0x110000}, 218 {1, 0x2170000, 0x2172000, 0x12e000}, 219 {0, 0x0000000, 0x0000000, 0x000000}, 220 {0, 0x0000000, 0x0000000, 0x000000}, 221 {0, 0x0000000, 0x0000000, 0x000000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000} } }, 227 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 228 {{{0} } }, 229 {{{0} } }, 230 {{{0} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 234 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 235 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 236 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 237 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 238 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 239 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 240 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 241 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 242 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 243 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 244 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 245 {{{0} } }, 246 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 247 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 248 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 249 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 250 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 251 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 252 {{{0} } }, 253 {{{0} } }, 254 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 255 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 256 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 257 }; 258 259 /* 260 * top 12 bits of crb internal address (hub, agent) 261 */ 262 unsigned qla82xx_crb_hub_agt[64] = { 263 0, 264 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 265 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 266 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 267 0, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 270 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 290 0, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 295 0, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 298 0, 299 0, 300 0, 301 0, 302 0, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 304 0, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 307 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 315 0, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 320 0, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 324 0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 326 0, 327 }; 328 329 /* Device states */ 330 char *qdev_state[] = { 331 "Unknown", 332 "Cold", 333 "Initializing", 334 "Ready", 335 "Need Reset", 336 "Need Quiescent", 337 "Failed", 338 "Quiescent", 339 }; 340 341 /* 342 * In: 'off' is offset from CRB space in 128M pci map 343 * Out: 'off' is 2M pci map addr 344 * side effect: lock crb window 345 */ 346 static void 347 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 348 { 349 u32 win_read; 350 351 ha->crb_win = CRB_HI(*off); 352 writel(ha->crb_win, 353 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 354 355 /* Read back value to make sure write has gone through before trying 356 * to use it. 357 */ 358 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 359 if (win_read != ha->crb_win) { 360 DEBUG2(qla_printk(KERN_INFO, ha, 361 "%s: Written crbwin (0x%x) != Read crbwin (0x%x), " 362 "off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 363 } 364 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 365 } 366 367 static inline unsigned long 368 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 369 { 370 /* See if we are currently pointing to the region we want to use next */ 371 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 372 /* No need to change window. PCIX and PCIEregs are in both 373 * regs are in both windows. 374 */ 375 return off; 376 } 377 378 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 379 /* We are in first CRB window */ 380 if (ha->curr_window != 0) 381 WARN_ON(1); 382 return off; 383 } 384 385 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 386 /* We are in second CRB window */ 387 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 388 389 if (ha->curr_window != 1) 390 return off; 391 392 /* We are in the QM or direct access 393 * register region - do nothing 394 */ 395 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 396 (off < QLA82XX_PCI_CAMQM_MAX)) 397 return off; 398 } 399 /* strange address given */ 400 qla_printk(KERN_WARNING, ha, 401 "%s: Warning: unm_nic_pci_set_crbwindow called with" 402 " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off); 403 return off; 404 } 405 406 int 407 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 408 { 409 unsigned long flags = 0; 410 int rv; 411 412 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 413 414 BUG_ON(rv == -1); 415 416 if (rv == 1) { 417 write_lock_irqsave(&ha->hw_lock, flags); 418 qla82xx_crb_win_lock(ha); 419 qla82xx_pci_set_crbwindow_2M(ha, &off); 420 } 421 422 writel(data, (void __iomem *)off); 423 424 if (rv == 1) { 425 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 426 write_unlock_irqrestore(&ha->hw_lock, flags); 427 } 428 return 0; 429 } 430 431 int 432 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 433 { 434 unsigned long flags = 0; 435 int rv; 436 u32 data; 437 438 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 439 440 BUG_ON(rv == -1); 441 442 if (rv == 1) { 443 write_lock_irqsave(&ha->hw_lock, flags); 444 qla82xx_crb_win_lock(ha); 445 qla82xx_pci_set_crbwindow_2M(ha, &off); 446 } 447 data = RD_REG_DWORD((void __iomem *)off); 448 449 if (rv == 1) { 450 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 451 write_unlock_irqrestore(&ha->hw_lock, flags); 452 } 453 return data; 454 } 455 456 #define CRB_WIN_LOCK_TIMEOUT 100000000 457 int qla82xx_crb_win_lock(struct qla_hw_data *ha) 458 { 459 int done = 0, timeout = 0; 460 461 while (!done) { 462 /* acquire semaphore3 from PCI HW block */ 463 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 464 if (done == 1) 465 break; 466 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 467 return -1; 468 timeout++; 469 } 470 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 471 return 0; 472 } 473 474 #define IDC_LOCK_TIMEOUT 100000000 475 int qla82xx_idc_lock(struct qla_hw_data *ha) 476 { 477 int i; 478 int done = 0, timeout = 0; 479 480 while (!done) { 481 /* acquire semaphore5 from PCI HW block */ 482 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 483 if (done == 1) 484 break; 485 if (timeout >= IDC_LOCK_TIMEOUT) 486 return -1; 487 488 timeout++; 489 490 /* Yield CPU */ 491 if (!in_interrupt()) 492 schedule(); 493 else { 494 for (i = 0; i < 20; i++) 495 cpu_relax(); 496 } 497 } 498 499 return 0; 500 } 501 502 void qla82xx_idc_unlock(struct qla_hw_data *ha) 503 { 504 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 505 } 506 507 int 508 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 509 { 510 struct crb_128M_2M_sub_block_map *m; 511 512 if (*off >= QLA82XX_CRB_MAX) 513 return -1; 514 515 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 516 *off = (*off - QLA82XX_PCI_CAMQM) + 517 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 518 return 0; 519 } 520 521 if (*off < QLA82XX_PCI_CRBSPACE) 522 return -1; 523 524 *off -= QLA82XX_PCI_CRBSPACE; 525 526 /* Try direct map */ 527 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 528 529 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 530 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 531 return 0; 532 } 533 /* Not in direct map, use crb window */ 534 return 1; 535 } 536 537 /* PCI Windowing for DDR regions. */ 538 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 539 (((addr) <= (high)) && ((addr) >= (low))) 540 /* 541 * check memory access boundary. 542 * used by test agent. support ddr access only for now 543 */ 544 static unsigned long 545 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 546 unsigned long long addr, int size) 547 { 548 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 549 QLA82XX_ADDR_DDR_NET_MAX) || 550 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 551 QLA82XX_ADDR_DDR_NET_MAX) || 552 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 553 return 0; 554 else 555 return 1; 556 } 557 558 int qla82xx_pci_set_window_warning_count; 559 560 unsigned long 561 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 562 { 563 int window; 564 u32 win_read; 565 566 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 567 QLA82XX_ADDR_DDR_NET_MAX)) { 568 /* DDR network side */ 569 window = MN_WIN(addr); 570 ha->ddr_mn_window = window; 571 qla82xx_wr_32(ha, 572 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 573 win_read = qla82xx_rd_32(ha, 574 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 575 if ((win_read << 17) != window) { 576 qla_printk(KERN_WARNING, ha, 577 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 578 __func__, window, win_read); 579 } 580 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 581 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 582 QLA82XX_ADDR_OCM0_MAX)) { 583 unsigned int temp1; 584 if ((addr & 0x00ff800) == 0xff800) { 585 qla_printk(KERN_WARNING, ha, 586 "%s: QM access not handled.\n", __func__); 587 addr = -1UL; 588 } 589 window = OCM_WIN(addr); 590 ha->ddr_mn_window = window; 591 qla82xx_wr_32(ha, 592 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 593 win_read = qla82xx_rd_32(ha, 594 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 595 temp1 = ((window & 0x1FF) << 7) | 596 ((window & 0x0FFFE0000) >> 17); 597 if (win_read != temp1) { 598 qla_printk(KERN_WARNING, ha, 599 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n", 600 __func__, temp1, win_read); 601 } 602 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 603 604 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 605 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 606 /* QDR network side */ 607 window = MS_WIN(addr); 608 ha->qdr_sn_window = window; 609 qla82xx_wr_32(ha, 610 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 611 win_read = qla82xx_rd_32(ha, 612 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 613 if (win_read != window) { 614 qla_printk(KERN_WARNING, ha, 615 "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n", 616 __func__, window, win_read); 617 } 618 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 619 } else { 620 /* 621 * peg gdb frequently accesses memory that doesn't exist, 622 * this limits the chit chat so debugging isn't slowed down. 623 */ 624 if ((qla82xx_pci_set_window_warning_count++ < 8) || 625 (qla82xx_pci_set_window_warning_count%64 == 0)) { 626 qla_printk(KERN_WARNING, ha, 627 "%s: Warning:%s Unknown address range!\n", __func__, 628 QLA2XXX_DRIVER_NAME); 629 } 630 addr = -1UL; 631 } 632 return addr; 633 } 634 635 /* check if address is in the same windows as the previous access */ 636 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 637 unsigned long long addr) 638 { 639 int window; 640 unsigned long long qdr_max; 641 642 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 643 644 /* DDR network side */ 645 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 646 QLA82XX_ADDR_DDR_NET_MAX)) 647 BUG(); 648 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 649 QLA82XX_ADDR_OCM0_MAX)) 650 return 1; 651 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 652 QLA82XX_ADDR_OCM1_MAX)) 653 return 1; 654 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 655 /* QDR network side */ 656 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 657 if (ha->qdr_sn_window == window) 658 return 1; 659 } 660 return 0; 661 } 662 663 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 664 u64 off, void *data, int size) 665 { 666 unsigned long flags; 667 void *addr = NULL; 668 int ret = 0; 669 u64 start; 670 uint8_t *mem_ptr = NULL; 671 unsigned long mem_base; 672 unsigned long mem_page; 673 674 write_lock_irqsave(&ha->hw_lock, flags); 675 676 /* 677 * If attempting to access unknown address or straddle hw windows, 678 * do not access. 679 */ 680 start = qla82xx_pci_set_window(ha, off); 681 if ((start == -1UL) || 682 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 683 write_unlock_irqrestore(&ha->hw_lock, flags); 684 qla_printk(KERN_ERR, ha, 685 "%s out of bound pci memory access. " 686 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 687 return -1; 688 } 689 690 write_unlock_irqrestore(&ha->hw_lock, flags); 691 mem_base = pci_resource_start(ha->pdev, 0); 692 mem_page = start & PAGE_MASK; 693 /* Map two pages whenever user tries to access addresses in two 694 * consecutive pages. 695 */ 696 if (mem_page != ((start + size - 1) & PAGE_MASK)) 697 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 698 else 699 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 700 if (mem_ptr == 0UL) { 701 *(u8 *)data = 0; 702 return -1; 703 } 704 addr = mem_ptr; 705 addr += start & (PAGE_SIZE - 1); 706 write_lock_irqsave(&ha->hw_lock, flags); 707 708 switch (size) { 709 case 1: 710 *(u8 *)data = readb(addr); 711 break; 712 case 2: 713 *(u16 *)data = readw(addr); 714 break; 715 case 4: 716 *(u32 *)data = readl(addr); 717 break; 718 case 8: 719 *(u64 *)data = readq(addr); 720 break; 721 default: 722 ret = -1; 723 break; 724 } 725 write_unlock_irqrestore(&ha->hw_lock, flags); 726 727 if (mem_ptr) 728 iounmap(mem_ptr); 729 return ret; 730 } 731 732 static int 733 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 734 u64 off, void *data, int size) 735 { 736 unsigned long flags; 737 void *addr = NULL; 738 int ret = 0; 739 u64 start; 740 uint8_t *mem_ptr = NULL; 741 unsigned long mem_base; 742 unsigned long mem_page; 743 744 write_lock_irqsave(&ha->hw_lock, flags); 745 746 /* 747 * If attempting to access unknown address or straddle hw windows, 748 * do not access. 749 */ 750 start = qla82xx_pci_set_window(ha, off); 751 if ((start == -1UL) || 752 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 753 write_unlock_irqrestore(&ha->hw_lock, flags); 754 qla_printk(KERN_ERR, ha, 755 "%s out of bound pci memory access. " 756 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 757 return -1; 758 } 759 760 write_unlock_irqrestore(&ha->hw_lock, flags); 761 mem_base = pci_resource_start(ha->pdev, 0); 762 mem_page = start & PAGE_MASK; 763 /* Map two pages whenever user tries to access addresses in two 764 * consecutive pages. 765 */ 766 if (mem_page != ((start + size - 1) & PAGE_MASK)) 767 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 768 else 769 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 770 if (mem_ptr == 0UL) 771 return -1; 772 773 addr = mem_ptr; 774 addr += start & (PAGE_SIZE - 1); 775 write_lock_irqsave(&ha->hw_lock, flags); 776 777 switch (size) { 778 case 1: 779 writeb(*(u8 *)data, addr); 780 break; 781 case 2: 782 writew(*(u16 *)data, addr); 783 break; 784 case 4: 785 writel(*(u32 *)data, addr); 786 break; 787 case 8: 788 writeq(*(u64 *)data, addr); 789 break; 790 default: 791 ret = -1; 792 break; 793 } 794 write_unlock_irqrestore(&ha->hw_lock, flags); 795 if (mem_ptr) 796 iounmap(mem_ptr); 797 return ret; 798 } 799 800 int 801 qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size) 802 { 803 int i, j, ret = 0, loop, sz[2], off0; 804 u32 temp; 805 u64 off8, mem_crb, tmpw, word[2] = {0, 0}; 806 #define MAX_CTL_CHECK 1000 807 /* 808 * If not MN, go check for MS or invalid. 809 */ 810 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) { 811 mem_crb = QLA82XX_CRB_QDR_NET; 812 } else { 813 mem_crb = QLA82XX_CRB_DDR_NET; 814 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 815 return qla82xx_pci_mem_write_direct(ha, off, 816 data, size); 817 } 818 819 off8 = off & 0xfffffff8; 820 off0 = off & 0x7; 821 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 822 sz[1] = size - sz[0]; 823 loop = ((off0 + size - 1) >> 3) + 1; 824 825 if ((size != 8) || (off0 != 0)) { 826 for (i = 0; i < loop; i++) { 827 if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8)) 828 return -1; 829 } 830 } 831 832 switch (size) { 833 case 1: 834 tmpw = *((u8 *)data); 835 break; 836 case 2: 837 tmpw = *((u16 *)data); 838 break; 839 case 4: 840 tmpw = *((u32 *)data); 841 break; 842 case 8: 843 default: 844 tmpw = *((u64 *)data); 845 break; 846 } 847 848 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 849 word[0] |= tmpw << (off0 * 8); 850 851 if (loop == 2) { 852 word[1] &= ~(~0ULL << (sz[1] * 8)); 853 word[1] |= tmpw >> (sz[0] * 8); 854 } 855 856 for (i = 0; i < loop; i++) { 857 temp = off8 + (i << 3); 858 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 859 temp = 0; 860 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 861 temp = word[i] & 0xffffffff; 862 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 863 temp = (word[i] >> 32) & 0xffffffff; 864 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 865 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 866 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 867 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 868 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 869 870 for (j = 0; j < MAX_CTL_CHECK; j++) { 871 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 872 if ((temp & MIU_TA_CTL_BUSY) == 0) 873 break; 874 } 875 876 if (j >= MAX_CTL_CHECK) { 877 qla_printk(KERN_WARNING, ha, 878 "%s: Fail to write through agent\n", 879 QLA2XXX_DRIVER_NAME); 880 ret = -1; 881 break; 882 } 883 } 884 return ret; 885 } 886 887 int 888 qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size) 889 { 890 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 891 u32 temp; 892 u64 off8, val, mem_crb, word[2] = {0, 0}; 893 #define MAX_CTL_CHECK 1000 894 895 /* 896 * If not MN, go check for MS or invalid. 897 */ 898 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 899 mem_crb = QLA82XX_CRB_QDR_NET; 900 else { 901 mem_crb = QLA82XX_CRB_DDR_NET; 902 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 903 return qla82xx_pci_mem_read_direct(ha, off, 904 data, size); 905 } 906 907 off8 = off & 0xfffffff8; 908 off0[0] = off & 0x7; 909 off0[1] = 0; 910 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); 911 sz[1] = size - sz[0]; 912 loop = ((off0[0] + size - 1) >> 3) + 1; 913 914 for (i = 0; i < loop; i++) { 915 temp = off8 + (i << 3); 916 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 917 temp = 0; 918 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 919 temp = MIU_TA_CTL_ENABLE; 920 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 921 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 922 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 923 924 for (j = 0; j < MAX_CTL_CHECK; j++) { 925 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 926 if ((temp & MIU_TA_CTL_BUSY) == 0) 927 break; 928 } 929 930 if (j >= MAX_CTL_CHECK) { 931 qla_printk(KERN_INFO, ha, 932 "%s: Fail to read through agent\n", 933 QLA2XXX_DRIVER_NAME); 934 break; 935 } 936 937 start = off0[i] >> 2; 938 end = (off0[i] + sz[i] - 1) >> 2; 939 for (k = start; k <= end; k++) { 940 temp = qla82xx_rd_32(ha, 941 mem_crb + MIU_TEST_AGT_RDDATA(k)); 942 word[i] |= ((u64)temp << (32 * k)); 943 } 944 } 945 946 if (j >= MAX_CTL_CHECK) 947 return -1; 948 949 if (sz[0] == 8) { 950 val = word[0]; 951 } else { 952 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 953 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 954 } 955 956 switch (size) { 957 case 1: 958 *(u8 *)data = val; 959 break; 960 case 2: 961 *(u16 *)data = val; 962 break; 963 case 4: 964 *(u32 *)data = val; 965 break; 966 case 8: 967 *(u64 *)data = val; 968 break; 969 } 970 return 0; 971 } 972 973 #define MTU_FUDGE_FACTOR 100 974 unsigned long qla82xx_decode_crb_addr(unsigned long addr) 975 { 976 int i; 977 unsigned long base_addr, offset, pci_base; 978 979 if (!qla82xx_crb_table_initialized) 980 qla82xx_crb_addr_transform_setup(); 981 982 pci_base = ADDR_ERROR; 983 base_addr = addr & 0xfff00000; 984 offset = addr & 0x000fffff; 985 986 for (i = 0; i < MAX_CRB_XFORM; i++) { 987 if (crb_addr_xform[i] == base_addr) { 988 pci_base = i << 20; 989 break; 990 } 991 } 992 if (pci_base == ADDR_ERROR) 993 return pci_base; 994 return pci_base + offset; 995 } 996 997 static long rom_max_timeout = 100; 998 static long qla82xx_rom_lock_timeout = 100; 999 1000 int 1001 qla82xx_rom_lock(struct qla_hw_data *ha) 1002 { 1003 int done = 0, timeout = 0; 1004 1005 while (!done) { 1006 /* acquire semaphore2 from PCI HW block */ 1007 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 1008 if (done == 1) 1009 break; 1010 if (timeout >= qla82xx_rom_lock_timeout) 1011 return -1; 1012 timeout++; 1013 } 1014 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 1015 return 0; 1016 } 1017 1018 int 1019 qla82xx_wait_rom_busy(struct qla_hw_data *ha) 1020 { 1021 long timeout = 0; 1022 long done = 0 ; 1023 1024 while (done == 0) { 1025 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 1026 done &= 4; 1027 timeout++; 1028 if (timeout >= rom_max_timeout) { 1029 DEBUG(qla_printk(KERN_INFO, ha, 1030 "%s: Timeout reached waiting for rom busy", 1031 QLA2XXX_DRIVER_NAME)); 1032 return -1; 1033 } 1034 } 1035 return 0; 1036 } 1037 1038 int 1039 qla82xx_wait_rom_done(struct qla_hw_data *ha) 1040 { 1041 long timeout = 0; 1042 long done = 0 ; 1043 1044 while (done == 0) { 1045 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 1046 done &= 2; 1047 timeout++; 1048 if (timeout >= rom_max_timeout) { 1049 DEBUG(qla_printk(KERN_INFO, ha, 1050 "%s: Timeout reached waiting for rom done", 1051 QLA2XXX_DRIVER_NAME)); 1052 return -1; 1053 } 1054 } 1055 return 0; 1056 } 1057 1058 int 1059 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 1060 { 1061 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 1062 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 1063 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1064 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 1065 qla82xx_wait_rom_busy(ha); 1066 if (qla82xx_wait_rom_done(ha)) { 1067 qla_printk(KERN_WARNING, ha, 1068 "%s: Error waiting for rom done\n", 1069 QLA2XXX_DRIVER_NAME); 1070 return -1; 1071 } 1072 /* Reset abyte_cnt and dummy_byte_cnt */ 1073 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 1074 udelay(10); 1075 cond_resched(); 1076 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1077 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1078 return 0; 1079 } 1080 1081 int 1082 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 1083 { 1084 int ret, loops = 0; 1085 1086 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1087 udelay(100); 1088 schedule(); 1089 loops++; 1090 } 1091 if (loops >= 50000) { 1092 qla_printk(KERN_INFO, ha, 1093 "%s: qla82xx_rom_lock failed\n", 1094 QLA2XXX_DRIVER_NAME); 1095 return -1; 1096 } 1097 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 1098 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1099 return ret; 1100 } 1101 1102 int 1103 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 1104 { 1105 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 1106 qla82xx_wait_rom_busy(ha); 1107 if (qla82xx_wait_rom_done(ha)) { 1108 qla_printk(KERN_WARNING, ha, 1109 "Error waiting for rom done\n"); 1110 return -1; 1111 } 1112 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1113 return 0; 1114 } 1115 1116 int 1117 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 1118 { 1119 long timeout = 0; 1120 uint32_t done = 1 ; 1121 uint32_t val; 1122 int ret = 0; 1123 1124 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1125 while ((done != 0) && (ret == 0)) { 1126 ret = qla82xx_read_status_reg(ha, &val); 1127 done = val & 1; 1128 timeout++; 1129 udelay(10); 1130 cond_resched(); 1131 if (timeout >= 50000) { 1132 qla_printk(KERN_WARNING, ha, 1133 "Timeout reached waiting for write finish"); 1134 return -1; 1135 } 1136 } 1137 return ret; 1138 } 1139 1140 int 1141 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1142 { 1143 uint32_t val; 1144 qla82xx_wait_rom_busy(ha); 1145 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1146 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1147 qla82xx_wait_rom_busy(ha); 1148 if (qla82xx_wait_rom_done(ha)) 1149 return -1; 1150 if (qla82xx_read_status_reg(ha, &val) != 0) 1151 return -1; 1152 if ((val & 2) != 2) 1153 return -1; 1154 return 0; 1155 } 1156 1157 int 1158 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1159 { 1160 if (qla82xx_flash_set_write_enable(ha)) 1161 return -1; 1162 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1163 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1164 if (qla82xx_wait_rom_done(ha)) { 1165 qla_printk(KERN_WARNING, ha, 1166 "Error waiting for rom done\n"); 1167 return -1; 1168 } 1169 return qla82xx_flash_wait_write_finish(ha); 1170 } 1171 1172 int 1173 qla82xx_write_disable_flash(struct qla_hw_data *ha) 1174 { 1175 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1176 if (qla82xx_wait_rom_done(ha)) { 1177 qla_printk(KERN_WARNING, ha, 1178 "Error waiting for rom done\n"); 1179 return -1; 1180 } 1181 return 0; 1182 } 1183 1184 int 1185 ql82xx_rom_lock_d(struct qla_hw_data *ha) 1186 { 1187 int loops = 0; 1188 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1189 udelay(100); 1190 cond_resched(); 1191 loops++; 1192 } 1193 if (loops >= 50000) { 1194 qla_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1195 return -1; 1196 } 1197 return 0;; 1198 } 1199 1200 int 1201 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1202 uint32_t data) 1203 { 1204 int ret = 0; 1205 1206 ret = ql82xx_rom_lock_d(ha); 1207 if (ret < 0) { 1208 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 1209 return ret; 1210 } 1211 1212 if (qla82xx_flash_set_write_enable(ha)) 1213 goto done_write; 1214 1215 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1216 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1217 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1218 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1219 qla82xx_wait_rom_busy(ha); 1220 if (qla82xx_wait_rom_done(ha)) { 1221 qla_printk(KERN_WARNING, ha, 1222 "Error waiting for rom done\n"); 1223 ret = -1; 1224 goto done_write; 1225 } 1226 1227 ret = qla82xx_flash_wait_write_finish(ha); 1228 1229 done_write: 1230 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1231 return ret; 1232 } 1233 1234 /* This routine does CRB initialize sequence 1235 * to put the ISP into operational state 1236 */ 1237 int qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1238 { 1239 int addr, val; 1240 int i ; 1241 struct crb_addr_pair *buf; 1242 unsigned long off; 1243 unsigned offset, n; 1244 struct qla_hw_data *ha = vha->hw; 1245 1246 struct crb_addr_pair { 1247 long addr; 1248 long data; 1249 }; 1250 1251 /* Halt all the indiviual PEGs and other blocks of the ISP */ 1252 qla82xx_rom_lock(ha); 1253 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1254 /* don't reset CAM block on reset */ 1255 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1256 else 1257 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1258 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1259 1260 /* Read the signature value from the flash. 1261 * Offset 0: Contain signature (0xcafecafe) 1262 * Offset 4: Offset and number of addr/value pairs 1263 * that present in CRB initialize sequence 1264 */ 1265 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1266 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1267 qla_printk(KERN_WARNING, ha, 1268 "[ERROR] Reading crb_init area: n: %08x\n", n); 1269 return -1; 1270 } 1271 1272 /* Offset in flash = lower 16 bits 1273 * Number of enteries = upper 16 bits 1274 */ 1275 offset = n & 0xffffU; 1276 n = (n >> 16) & 0xffffU; 1277 1278 /* number of addr/value pair should not exceed 1024 enteries */ 1279 if (n >= 1024) { 1280 qla_printk(KERN_WARNING, ha, 1281 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1282 QLA2XXX_DRIVER_NAME, __func__, n); 1283 return -1; 1284 } 1285 1286 qla_printk(KERN_INFO, ha, 1287 "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n); 1288 1289 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1290 if (buf == NULL) { 1291 qla_printk(KERN_WARNING, ha, 1292 "%s: [ERROR] Unable to malloc memory.\n", 1293 QLA2XXX_DRIVER_NAME); 1294 return -1; 1295 } 1296 1297 for (i = 0; i < n; i++) { 1298 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1299 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1300 kfree(buf); 1301 return -1; 1302 } 1303 1304 buf[i].addr = addr; 1305 buf[i].data = val; 1306 } 1307 1308 for (i = 0; i < n; i++) { 1309 /* Translate internal CRB initialization 1310 * address to PCI bus address 1311 */ 1312 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1313 QLA82XX_PCI_CRBSPACE; 1314 /* Not all CRB addr/value pair to be written, 1315 * some of them are skipped 1316 */ 1317 1318 /* skipping cold reboot MAGIC */ 1319 if (off == QLA82XX_CAM_RAM(0x1fc)) 1320 continue; 1321 1322 /* do not reset PCI */ 1323 if (off == (ROMUSB_GLB + 0xbc)) 1324 continue; 1325 1326 /* skip core clock, so that firmware can increase the clock */ 1327 if (off == (ROMUSB_GLB + 0xc8)) 1328 continue; 1329 1330 /* skip the function enable register */ 1331 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1332 continue; 1333 1334 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1335 continue; 1336 1337 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1338 continue; 1339 1340 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1341 continue; 1342 1343 if (off == ADDR_ERROR) { 1344 qla_printk(KERN_WARNING, ha, 1345 "%s: [ERROR] Unknown addr: 0x%08lx\n", 1346 QLA2XXX_DRIVER_NAME, buf[i].addr); 1347 continue; 1348 } 1349 1350 if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) { 1351 if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) 1352 buf[i].data = 0x1020; 1353 } 1354 1355 qla82xx_wr_32(ha, off, buf[i].data); 1356 1357 /* ISP requires much bigger delay to settle down, 1358 * else crb_window returns 0xffffffff 1359 */ 1360 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1361 msleep(1000); 1362 1363 /* ISP requires millisec delay between 1364 * successive CRB register updation 1365 */ 1366 msleep(1); 1367 } 1368 1369 kfree(buf); 1370 1371 /* Resetting the data and instruction cache */ 1372 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1373 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1374 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1375 1376 /* Clear all protocol processing engines */ 1377 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1378 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1379 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1380 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1381 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1382 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1383 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1384 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1385 return 0; 1386 } 1387 1388 int qla82xx_check_for_bad_spd(struct qla_hw_data *ha) 1389 { 1390 u32 val = 0; 1391 val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS); 1392 val &= QLA82XX_BOOT_LOADER_MN_ISSUE; 1393 if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) { 1394 qla_printk(KERN_INFO, ha, 1395 "Memory DIMM SPD not programmed. " 1396 " Assumed valid.\n"); 1397 return 1; 1398 } else if (val) { 1399 qla_printk(KERN_INFO, ha, 1400 "Memory DIMM type incorrect.Info:%08X.\n", val); 1401 return 2; 1402 } 1403 return 0; 1404 } 1405 1406 int 1407 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1408 { 1409 int i; 1410 long size = 0; 1411 long flashaddr = ha->flt_region_bootload << 2; 1412 long memaddr = BOOTLD_START; 1413 u64 data; 1414 u32 high, low; 1415 size = (IMAGE_START - BOOTLD_START) / 8; 1416 1417 for (i = 0; i < size; i++) { 1418 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1419 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1420 return -1; 1421 } 1422 data = ((u64)high << 32) | low ; 1423 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1424 flashaddr += 8; 1425 memaddr += 8; 1426 1427 if (i % 0x1000 == 0) 1428 msleep(1); 1429 } 1430 udelay(100); 1431 read_lock(&ha->hw_lock); 1432 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1433 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1435 } else { 1436 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); 1437 } 1438 read_unlock(&ha->hw_lock); 1439 return 0; 1440 } 1441 1442 int 1443 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1444 u64 off, void *data, int size) 1445 { 1446 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1447 int shift_amount; 1448 uint32_t temp; 1449 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1450 1451 /* 1452 * If not MN, go check for MS or invalid. 1453 */ 1454 1455 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1456 mem_crb = QLA82XX_CRB_QDR_NET; 1457 else { 1458 mem_crb = QLA82XX_CRB_DDR_NET; 1459 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1460 return qla82xx_pci_mem_read_direct(ha, 1461 off, data, size); 1462 } 1463 1464 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1465 off8 = off & 0xfffffff0; 1466 off0[0] = off & 0xf; 1467 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1468 shift_amount = 4; 1469 } else { 1470 off8 = off & 0xfffffff8; 1471 off0[0] = off & 0x7; 1472 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); 1473 shift_amount = 4; 1474 } 1475 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1476 off0[1] = 0; 1477 sz[1] = size - sz[0]; 1478 1479 /* 1480 * don't lock here - write_wx gets the lock if each time 1481 * write_lock_irqsave(&adapter->adapter_lock, flags); 1482 * netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1483 */ 1484 1485 for (i = 0; i < loop; i++) { 1486 temp = off8 + (i << shift_amount); 1487 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1488 temp = 0; 1489 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1490 temp = MIU_TA_CTL_ENABLE; 1491 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1492 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1493 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1494 1495 for (j = 0; j < MAX_CTL_CHECK; j++) { 1496 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1497 if ((temp & MIU_TA_CTL_BUSY) == 0) 1498 break; 1499 } 1500 1501 if (j >= MAX_CTL_CHECK) { 1502 if (printk_ratelimit()) 1503 dev_err(&ha->pdev->dev, 1504 "failed to read through agent\n"); 1505 break; 1506 } 1507 1508 start = off0[i] >> 2; 1509 end = (off0[i] + sz[i] - 1) >> 2; 1510 for (k = start; k <= end; k++) { 1511 temp = qla82xx_rd_32(ha, 1512 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1513 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1514 } 1515 } 1516 1517 /* 1518 * netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1519 * write_unlock_irqrestore(&adapter->adapter_lock, flags); 1520 */ 1521 1522 if (j >= MAX_CTL_CHECK) 1523 return -1; 1524 1525 if ((off0[0] & 7) == 0) { 1526 val = word[0]; 1527 } else { 1528 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1529 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1530 } 1531 1532 switch (size) { 1533 case 1: 1534 *(uint8_t *)data = val; 1535 break; 1536 case 2: 1537 *(uint16_t *)data = val; 1538 break; 1539 case 4: 1540 *(uint32_t *)data = val; 1541 break; 1542 case 8: 1543 *(uint64_t *)data = val; 1544 break; 1545 } 1546 return 0; 1547 } 1548 1549 int 1550 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1551 u64 off, void *data, int size) 1552 { 1553 int i, j, ret = 0, loop, sz[2], off0; 1554 int scale, shift_amount, p3p, startword; 1555 uint32_t temp; 1556 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1557 1558 /* 1559 * If not MN, go check for MS or invalid. 1560 */ 1561 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1562 mem_crb = QLA82XX_CRB_QDR_NET; 1563 else { 1564 mem_crb = QLA82XX_CRB_DDR_NET; 1565 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1566 return qla82xx_pci_mem_write_direct(ha, 1567 off, data, size); 1568 } 1569 1570 off0 = off & 0x7; 1571 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1572 sz[1] = size - sz[0]; 1573 1574 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1575 off8 = off & 0xfffffff0; 1576 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1577 shift_amount = 4; 1578 scale = 2; 1579 p3p = 1; 1580 startword = (off & 0xf)/8; 1581 } else { 1582 off8 = off & 0xfffffff8; 1583 loop = ((off0 + size - 1) >> 3) + 1; 1584 shift_amount = 3; 1585 scale = 1; 1586 p3p = 0; 1587 startword = 0; 1588 } 1589 1590 if (p3p || (size != 8) || (off0 != 0)) { 1591 for (i = 0; i < loop; i++) { 1592 if (qla82xx_pci_mem_read_2M(ha, off8 + 1593 (i << shift_amount), &word[i * scale], 8)) 1594 return -1; 1595 } 1596 } 1597 1598 switch (size) { 1599 case 1: 1600 tmpw = *((uint8_t *)data); 1601 break; 1602 case 2: 1603 tmpw = *((uint16_t *)data); 1604 break; 1605 case 4: 1606 tmpw = *((uint32_t *)data); 1607 break; 1608 case 8: 1609 default: 1610 tmpw = *((uint64_t *)data); 1611 break; 1612 } 1613 1614 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1615 if (sz[0] == 8) { 1616 word[startword] = tmpw; 1617 } else { 1618 word[startword] &= 1619 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1620 word[startword] |= tmpw << (off0 * 8); 1621 } 1622 if (sz[1] != 0) { 1623 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1624 word[startword+1] |= tmpw >> (sz[0] * 8); 1625 } 1626 } else { 1627 word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1628 word[startword] |= tmpw << (off0 * 8); 1629 1630 if (loop == 2) { 1631 word[1] &= ~(~0ULL << (sz[1] * 8)); 1632 word[1] |= tmpw >> (sz[0] * 8); 1633 } 1634 } 1635 1636 /* 1637 * don't lock here - write_wx gets the lock if each time 1638 * write_lock_irqsave(&adapter->adapter_lock, flags); 1639 * netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1640 */ 1641 for (i = 0; i < loop; i++) { 1642 temp = off8 + (i << shift_amount); 1643 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1644 temp = 0; 1645 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1646 temp = word[i * scale] & 0xffffffff; 1647 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1648 temp = (word[i * scale] >> 32) & 0xffffffff; 1649 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1650 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1651 temp = word[i*scale + 1] & 0xffffffff; 1652 qla82xx_wr_32(ha, mem_crb + 1653 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1654 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1655 qla82xx_wr_32(ha, mem_crb + 1656 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1657 } 1658 1659 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1660 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1661 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1662 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1663 1664 for (j = 0; j < MAX_CTL_CHECK; j++) { 1665 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1666 if ((temp & MIU_TA_CTL_BUSY) == 0) 1667 break; 1668 } 1669 1670 if (j >= MAX_CTL_CHECK) { 1671 if (printk_ratelimit()) 1672 dev_err(&ha->pdev->dev, 1673 "failed to write through agent\n"); 1674 ret = -1; 1675 break; 1676 } 1677 } 1678 1679 return ret; 1680 } 1681 1682 static struct qla82xx_uri_table_desc * 1683 qla82xx_get_table_desc(const u8 *unirom, int section) 1684 { 1685 uint32_t i; 1686 struct qla82xx_uri_table_desc *directory = 1687 (struct qla82xx_uri_table_desc *)&unirom[0]; 1688 __le32 offset; 1689 __le32 tab_type; 1690 __le32 entries = cpu_to_le32(directory->num_entries); 1691 1692 for (i = 0; i < entries; i++) { 1693 offset = cpu_to_le32(directory->findex) + 1694 (i * cpu_to_le32(directory->entry_size)); 1695 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1696 1697 if (tab_type == section) 1698 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1699 } 1700 1701 return NULL; 1702 } 1703 1704 static struct qla82xx_uri_data_desc * 1705 qla82xx_get_data_desc(struct qla_hw_data *ha, 1706 u32 section, u32 idx_offset) 1707 { 1708 const u8 *unirom = ha->hablob->fw->data; 1709 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1710 struct qla82xx_uri_table_desc *tab_desc = NULL; 1711 __le32 offset; 1712 1713 tab_desc = qla82xx_get_table_desc(unirom, section); 1714 if (!tab_desc) 1715 return NULL; 1716 1717 offset = cpu_to_le32(tab_desc->findex) + 1718 (cpu_to_le32(tab_desc->entry_size) * idx); 1719 1720 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1721 } 1722 1723 static u8 * 1724 qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1725 { 1726 u32 offset = BOOTLD_START; 1727 struct qla82xx_uri_data_desc *uri_desc = NULL; 1728 1729 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1730 uri_desc = qla82xx_get_data_desc(ha, 1731 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1732 if (uri_desc) 1733 offset = cpu_to_le32(uri_desc->findex); 1734 } 1735 1736 return (u8 *)&ha->hablob->fw->data[offset]; 1737 } 1738 1739 static __le32 1740 qla82xx_get_fw_size(struct qla_hw_data *ha) 1741 { 1742 struct qla82xx_uri_data_desc *uri_desc = NULL; 1743 1744 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1745 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1746 QLA82XX_URI_FIRMWARE_IDX_OFF); 1747 if (uri_desc) 1748 return cpu_to_le32(uri_desc->size); 1749 } 1750 1751 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1752 } 1753 1754 static u8 * 1755 qla82xx_get_fw_offs(struct qla_hw_data *ha) 1756 { 1757 u32 offset = IMAGE_START; 1758 struct qla82xx_uri_data_desc *uri_desc = NULL; 1759 1760 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1761 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1762 QLA82XX_URI_FIRMWARE_IDX_OFF); 1763 if (uri_desc) 1764 offset = cpu_to_le32(uri_desc->findex); 1765 } 1766 1767 return (u8 *)&ha->hablob->fw->data[offset]; 1768 } 1769 1770 /* PCI related functions */ 1771 char * 1772 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1773 { 1774 int pcie_reg; 1775 struct qla_hw_data *ha = vha->hw; 1776 char lwstr[6]; 1777 uint16_t lnk; 1778 1779 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1780 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1781 ha->link_width = (lnk >> 4) & 0x3f; 1782 1783 strcpy(str, "PCIe ("); 1784 strcat(str, "2.5Gb/s "); 1785 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1786 strcat(str, lwstr); 1787 return str; 1788 } 1789 1790 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1791 { 1792 unsigned long val = 0; 1793 u32 control; 1794 1795 switch (region) { 1796 case 0: 1797 val = 0; 1798 break; 1799 case 1: 1800 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1801 val = control + QLA82XX_MSIX_TBL_SPACE; 1802 break; 1803 } 1804 return val; 1805 } 1806 1807 int qla82xx_pci_region_len(struct pci_dev *pdev, int region) 1808 { 1809 unsigned long val = 0; 1810 u32 control; 1811 switch (region) { 1812 case 0: 1813 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1814 val = control; 1815 break; 1816 case 1: 1817 val = pci_resource_len(pdev, 0) - 1818 qla82xx_pci_region_offset(pdev, 1); 1819 break; 1820 } 1821 return val; 1822 } 1823 1824 int 1825 qla82xx_iospace_config(struct qla_hw_data *ha) 1826 { 1827 uint32_t len = 0; 1828 1829 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1830 qla_printk(KERN_WARNING, ha, 1831 "Failed to reserve selected regions (%s)\n", 1832 pci_name(ha->pdev)); 1833 goto iospace_error_exit; 1834 } 1835 1836 /* Use MMIO operations for all accesses. */ 1837 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1838 qla_printk(KERN_ERR, ha, 1839 "region #0 not an MMIO resource (%s), aborting\n", 1840 pci_name(ha->pdev)); 1841 goto iospace_error_exit; 1842 } 1843 1844 len = pci_resource_len(ha->pdev, 0); 1845 ha->nx_pcibase = 1846 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1847 if (!ha->nx_pcibase) { 1848 qla_printk(KERN_ERR, ha, 1849 "cannot remap pcibase MMIO (%s), aborting\n", 1850 pci_name(ha->pdev)); 1851 pci_release_regions(ha->pdev); 1852 goto iospace_error_exit; 1853 } 1854 1855 /* Mapping of IO base pointer */ 1856 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1857 0xbc000 + (ha->pdev->devfn << 11)); 1858 1859 if (!ql2xdbwr) { 1860 ha->nxdb_wr_ptr = 1861 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1862 (ha->pdev->devfn << 12)), 4); 1863 if (!ha->nxdb_wr_ptr) { 1864 qla_printk(KERN_ERR, ha, 1865 "cannot remap MMIO (%s), aborting\n", 1866 pci_name(ha->pdev)); 1867 pci_release_regions(ha->pdev); 1868 goto iospace_error_exit; 1869 } 1870 1871 /* Mapping of IO base pointer, 1872 * door bell read and write pointer 1873 */ 1874 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1875 (ha->pdev->devfn * 8); 1876 } else { 1877 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1878 QLA82XX_CAMRAM_DB1 : 1879 QLA82XX_CAMRAM_DB2); 1880 } 1881 1882 ha->max_req_queues = ha->max_rsp_queues = 1; 1883 ha->msix_count = ha->max_rsp_queues + 1; 1884 return 0; 1885 1886 iospace_error_exit: 1887 return -ENOMEM; 1888 } 1889 1890 /* GS related functions */ 1891 1892 /* Initialization related functions */ 1893 1894 /** 1895 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1896 * @ha: HA context 1897 * 1898 * Returns 0 on success. 1899 */ 1900 int 1901 qla82xx_pci_config(scsi_qla_host_t *vha) 1902 { 1903 struct qla_hw_data *ha = vha->hw; 1904 int ret; 1905 1906 pci_set_master(ha->pdev); 1907 ret = pci_set_mwi(ha->pdev); 1908 ha->chip_revision = ha->pdev->revision; 1909 return 0; 1910 } 1911 1912 /** 1913 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1914 * @ha: HA context 1915 * 1916 * Returns 0 on success. 1917 */ 1918 void 1919 qla82xx_reset_chip(scsi_qla_host_t *vha) 1920 { 1921 struct qla_hw_data *ha = vha->hw; 1922 ha->isp_ops->disable_intrs(ha); 1923 } 1924 1925 void qla82xx_config_rings(struct scsi_qla_host *vha) 1926 { 1927 struct qla_hw_data *ha = vha->hw; 1928 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1929 struct init_cb_81xx *icb; 1930 struct req_que *req = ha->req_q_map[0]; 1931 struct rsp_que *rsp = ha->rsp_q_map[0]; 1932 1933 /* Setup ring parameters in initialization control block. */ 1934 icb = (struct init_cb_81xx *)ha->init_cb; 1935 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1936 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1937 icb->request_q_length = cpu_to_le16(req->length); 1938 icb->response_q_length = cpu_to_le16(rsp->length); 1939 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1940 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1941 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1942 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1943 1944 icb->version = 1; 1945 icb->frame_payload_size = 2112; 1946 icb->execution_throttle = 8; 1947 icb->exchange_count = 128; 1948 icb->login_retry_count = 8; 1949 1950 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1951 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1952 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1953 } 1954 1955 void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1956 { 1957 struct qla_hw_data *ha = vha->hw; 1958 vha->flags.online = 0; 1959 qla2x00_try_to_stop_firmware(vha); 1960 ha->isp_ops->disable_intrs(ha); 1961 } 1962 1963 int qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1964 { 1965 u64 *ptr64; 1966 u32 i, flashaddr, size; 1967 __le64 data; 1968 1969 size = (IMAGE_START - BOOTLD_START) / 8; 1970 1971 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1972 flashaddr = BOOTLD_START; 1973 1974 for (i = 0; i < size; i++) { 1975 data = cpu_to_le64(ptr64[i]); 1976 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1977 return -EIO; 1978 flashaddr += 8; 1979 } 1980 1981 flashaddr = FLASH_ADDR_START; 1982 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1983 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1984 1985 for (i = 0; i < size; i++) { 1986 data = cpu_to_le64(ptr64[i]); 1987 1988 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1989 return -EIO; 1990 flashaddr += 8; 1991 } 1992 udelay(100); 1993 1994 /* Write a magic value to CAMRAM register 1995 * at a specified offset to indicate 1996 * that all data is written and 1997 * ready for firmware to initialize. 1998 */ 1999 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 2000 2001 read_lock(&ha->hw_lock); 2002 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 2003 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 2004 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 2005 } else 2006 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); 2007 read_unlock(&ha->hw_lock); 2008 return 0; 2009 } 2010 2011 static int 2012 qla82xx_set_product_offset(struct qla_hw_data *ha) 2013 { 2014 struct qla82xx_uri_table_desc *ptab_desc = NULL; 2015 const uint8_t *unirom = ha->hablob->fw->data; 2016 uint32_t i; 2017 __le32 entries; 2018 __le32 flags, file_chiprev, offset; 2019 uint8_t chiprev = ha->chip_revision; 2020 /* Hardcoding mn_present flag for P3P */ 2021 int mn_present = 0; 2022 uint32_t flagbit; 2023 2024 ptab_desc = qla82xx_get_table_desc(unirom, 2025 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 2026 if (!ptab_desc) 2027 return -1; 2028 2029 entries = cpu_to_le32(ptab_desc->num_entries); 2030 2031 for (i = 0; i < entries; i++) { 2032 offset = cpu_to_le32(ptab_desc->findex) + 2033 (i * cpu_to_le32(ptab_desc->entry_size)); 2034 flags = cpu_to_le32(*((int *)&unirom[offset] + 2035 QLA82XX_URI_FLAGS_OFF)); 2036 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 2037 QLA82XX_URI_CHIP_REV_OFF)); 2038 2039 flagbit = mn_present ? 1 : 2; 2040 2041 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 2042 ha->file_prd_off = offset; 2043 return 0; 2044 } 2045 } 2046 return -1; 2047 } 2048 2049 int 2050 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 2051 { 2052 __le32 val; 2053 uint32_t min_size; 2054 struct qla_hw_data *ha = vha->hw; 2055 const struct firmware *fw = ha->hablob->fw; 2056 2057 ha->fw_type = fw_type; 2058 2059 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 2060 if (qla82xx_set_product_offset(ha)) 2061 return -EINVAL; 2062 2063 min_size = QLA82XX_URI_FW_MIN_SIZE; 2064 } else { 2065 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 2066 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 2067 return -EINVAL; 2068 2069 min_size = QLA82XX_FW_MIN_SIZE; 2070 } 2071 2072 if (fw->size < min_size) 2073 return -EINVAL; 2074 return 0; 2075 } 2076 2077 int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 2078 { 2079 u32 val = 0; 2080 int retries = 60; 2081 2082 do { 2083 read_lock(&ha->hw_lock); 2084 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 2085 read_unlock(&ha->hw_lock); 2086 2087 switch (val) { 2088 case PHAN_INITIALIZE_COMPLETE: 2089 case PHAN_INITIALIZE_ACK: 2090 return QLA_SUCCESS; 2091 case PHAN_INITIALIZE_FAILED: 2092 break; 2093 default: 2094 break; 2095 } 2096 qla_printk(KERN_WARNING, ha, 2097 "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n", 2098 val, retries); 2099 2100 msleep(500); 2101 2102 } while (--retries); 2103 2104 qla_printk(KERN_INFO, ha, 2105 "Cmd Peg initialization failed: 0x%x.\n", val); 2106 2107 qla82xx_check_for_bad_spd(ha); 2108 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 2109 read_lock(&ha->hw_lock); 2110 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 2111 read_unlock(&ha->hw_lock); 2112 return QLA_FUNCTION_FAILED; 2113 } 2114 2115 int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 2116 { 2117 u32 val = 0; 2118 int retries = 60; 2119 2120 do { 2121 read_lock(&ha->hw_lock); 2122 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 2123 read_unlock(&ha->hw_lock); 2124 2125 switch (val) { 2126 case PHAN_INITIALIZE_COMPLETE: 2127 case PHAN_INITIALIZE_ACK: 2128 return QLA_SUCCESS; 2129 case PHAN_INITIALIZE_FAILED: 2130 break; 2131 default: 2132 break; 2133 } 2134 2135 qla_printk(KERN_WARNING, ha, 2136 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n", 2137 val, retries); 2138 2139 msleep(500); 2140 2141 } while (--retries); 2142 2143 qla_printk(KERN_INFO, ha, 2144 "Rcv Peg initialization failed: 0x%x.\n", val); 2145 read_lock(&ha->hw_lock); 2146 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 2147 read_unlock(&ha->hw_lock); 2148 return QLA_FUNCTION_FAILED; 2149 } 2150 2151 /* ISR related functions */ 2152 uint32_t qla82xx_isr_int_target_mask_enable[8] = { 2153 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 2154 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 2155 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 2156 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 2157 }; 2158 2159 uint32_t qla82xx_isr_int_target_status[8] = { 2160 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 2161 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 2162 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 2163 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 2164 }; 2165 2166 static struct qla82xx_legacy_intr_set legacy_intr[] = \ 2167 QLA82XX_LEGACY_INTR_CONFIG; 2168 2169 /* 2170 * qla82xx_mbx_completion() - Process mailbox command completions. 2171 * @ha: SCSI driver HA context 2172 * @mb0: Mailbox0 register 2173 */ 2174 void 2175 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2176 { 2177 uint16_t cnt; 2178 uint16_t __iomem *wptr; 2179 struct qla_hw_data *ha = vha->hw; 2180 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2181 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2182 2183 /* Load return mailbox registers. */ 2184 ha->flags.mbox_int = 1; 2185 ha->mailbox_out[0] = mb0; 2186 2187 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2188 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2189 wptr++; 2190 } 2191 2192 if (ha->mcp) { 2193 DEBUG3_11(printk(KERN_INFO "%s(%ld): " 2194 "Got mailbox completion. cmd=%x.\n", 2195 __func__, vha->host_no, ha->mcp->mb[0])); 2196 } else { 2197 qla_printk(KERN_INFO, ha, 2198 "%s(%ld): MBX pointer ERROR!\n", 2199 __func__, vha->host_no); 2200 } 2201 } 2202 2203 /* 2204 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2205 * @irq: 2206 * @dev_id: SCSI driver HA context 2207 * @regs: 2208 * 2209 * Called by system whenever the host adapter generates an interrupt. 2210 * 2211 * Returns handled flag. 2212 */ 2213 irqreturn_t 2214 qla82xx_intr_handler(int irq, void *dev_id) 2215 { 2216 scsi_qla_host_t *vha; 2217 struct qla_hw_data *ha; 2218 struct rsp_que *rsp; 2219 struct device_reg_82xx __iomem *reg; 2220 int status = 0, status1 = 0; 2221 unsigned long flags; 2222 unsigned long iter; 2223 uint32_t stat; 2224 uint16_t mb[4]; 2225 2226 rsp = (struct rsp_que *) dev_id; 2227 if (!rsp) { 2228 printk(KERN_INFO 2229 "%s(): NULL response queue pointer\n", __func__); 2230 return IRQ_NONE; 2231 } 2232 ha = rsp->hw; 2233 2234 if (!ha->flags.msi_enabled) { 2235 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2236 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2237 return IRQ_NONE; 2238 2239 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2240 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2241 return IRQ_NONE; 2242 } 2243 2244 /* clear the interrupt */ 2245 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2246 2247 /* read twice to ensure write is flushed */ 2248 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2249 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2250 2251 reg = &ha->iobase->isp82; 2252 2253 spin_lock_irqsave(&ha->hardware_lock, flags); 2254 vha = pci_get_drvdata(ha->pdev); 2255 for (iter = 1; iter--; ) { 2256 2257 if (RD_REG_DWORD(®->host_int)) { 2258 stat = RD_REG_DWORD(®->host_status); 2259 if ((stat & HSRX_RISC_INT) == 0) 2260 break; 2261 2262 switch (stat & 0xff) { 2263 case 0x1: 2264 case 0x2: 2265 case 0x10: 2266 case 0x11: 2267 qla82xx_mbx_completion(vha, MSW(stat)); 2268 status |= MBX_INTERRUPT; 2269 break; 2270 case 0x12: 2271 mb[0] = MSW(stat); 2272 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2273 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2274 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2275 qla2x00_async_event(vha, rsp, mb); 2276 break; 2277 case 0x13: 2278 qla24xx_process_response_queue(vha, rsp); 2279 break; 2280 default: 2281 DEBUG2(printk("scsi(%ld): " 2282 " Unrecognized interrupt type (%d).\n", 2283 vha->host_no, stat & 0xff)); 2284 break; 2285 } 2286 } 2287 WRT_REG_DWORD(®->host_int, 0); 2288 } 2289 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2290 if (!ha->flags.msi_enabled) 2291 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2292 2293 #ifdef QL_DEBUG_LEVEL_17 2294 if (!irq && ha->flags.eeh_busy) 2295 qla_printk(KERN_WARNING, ha, 2296 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2297 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2298 #endif 2299 2300 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2301 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2302 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2303 complete(&ha->mbx_intr_comp); 2304 } 2305 return IRQ_HANDLED; 2306 } 2307 2308 irqreturn_t 2309 qla82xx_msix_default(int irq, void *dev_id) 2310 { 2311 scsi_qla_host_t *vha; 2312 struct qla_hw_data *ha; 2313 struct rsp_que *rsp; 2314 struct device_reg_82xx __iomem *reg; 2315 int status = 0; 2316 unsigned long flags; 2317 uint32_t stat; 2318 uint16_t mb[4]; 2319 2320 rsp = (struct rsp_que *) dev_id; 2321 if (!rsp) { 2322 printk(KERN_INFO 2323 "%s(): NULL response queue pointer\n", __func__); 2324 return IRQ_NONE; 2325 } 2326 ha = rsp->hw; 2327 2328 reg = &ha->iobase->isp82; 2329 2330 spin_lock_irqsave(&ha->hardware_lock, flags); 2331 vha = pci_get_drvdata(ha->pdev); 2332 do { 2333 if (RD_REG_DWORD(®->host_int)) { 2334 stat = RD_REG_DWORD(®->host_status); 2335 if ((stat & HSRX_RISC_INT) == 0) 2336 break; 2337 2338 switch (stat & 0xff) { 2339 case 0x1: 2340 case 0x2: 2341 case 0x10: 2342 case 0x11: 2343 qla82xx_mbx_completion(vha, MSW(stat)); 2344 status |= MBX_INTERRUPT; 2345 break; 2346 case 0x12: 2347 mb[0] = MSW(stat); 2348 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2349 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2350 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2351 qla2x00_async_event(vha, rsp, mb); 2352 break; 2353 case 0x13: 2354 qla24xx_process_response_queue(vha, rsp); 2355 break; 2356 default: 2357 DEBUG2(printk("scsi(%ld): " 2358 " Unrecognized interrupt type (%d).\n", 2359 vha->host_no, stat & 0xff)); 2360 break; 2361 } 2362 } 2363 WRT_REG_DWORD(®->host_int, 0); 2364 } while (0); 2365 2366 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2367 2368 #ifdef QL_DEBUG_LEVEL_17 2369 if (!irq && ha->flags.eeh_busy) 2370 qla_printk(KERN_WARNING, ha, 2371 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2372 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2373 #endif 2374 2375 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2376 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2377 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2378 complete(&ha->mbx_intr_comp); 2379 } 2380 return IRQ_HANDLED; 2381 } 2382 2383 irqreturn_t 2384 qla82xx_msix_rsp_q(int irq, void *dev_id) 2385 { 2386 scsi_qla_host_t *vha; 2387 struct qla_hw_data *ha; 2388 struct rsp_que *rsp; 2389 struct device_reg_82xx __iomem *reg; 2390 2391 rsp = (struct rsp_que *) dev_id; 2392 if (!rsp) { 2393 printk(KERN_INFO 2394 "%s(): NULL response queue pointer\n", __func__); 2395 return IRQ_NONE; 2396 } 2397 2398 ha = rsp->hw; 2399 reg = &ha->iobase->isp82; 2400 spin_lock_irq(&ha->hardware_lock); 2401 vha = pci_get_drvdata(ha->pdev); 2402 qla24xx_process_response_queue(vha, rsp); 2403 WRT_REG_DWORD(®->host_int, 0); 2404 spin_unlock_irq(&ha->hardware_lock); 2405 return IRQ_HANDLED; 2406 } 2407 2408 void 2409 qla82xx_poll(int irq, void *dev_id) 2410 { 2411 scsi_qla_host_t *vha; 2412 struct qla_hw_data *ha; 2413 struct rsp_que *rsp; 2414 struct device_reg_82xx __iomem *reg; 2415 int status = 0; 2416 uint32_t stat; 2417 uint16_t mb[4]; 2418 unsigned long flags; 2419 2420 rsp = (struct rsp_que *) dev_id; 2421 if (!rsp) { 2422 printk(KERN_INFO 2423 "%s(): NULL response queue pointer\n", __func__); 2424 return; 2425 } 2426 ha = rsp->hw; 2427 2428 reg = &ha->iobase->isp82; 2429 spin_lock_irqsave(&ha->hardware_lock, flags); 2430 vha = pci_get_drvdata(ha->pdev); 2431 2432 if (RD_REG_DWORD(®->host_int)) { 2433 stat = RD_REG_DWORD(®->host_status); 2434 switch (stat & 0xff) { 2435 case 0x1: 2436 case 0x2: 2437 case 0x10: 2438 case 0x11: 2439 qla82xx_mbx_completion(vha, MSW(stat)); 2440 status |= MBX_INTERRUPT; 2441 break; 2442 case 0x12: 2443 mb[0] = MSW(stat); 2444 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2445 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2446 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2447 qla2x00_async_event(vha, rsp, mb); 2448 break; 2449 case 0x13: 2450 qla24xx_process_response_queue(vha, rsp); 2451 break; 2452 default: 2453 DEBUG2(printk("scsi(%ld): Unrecognized interrupt type " 2454 "(%d).\n", 2455 vha->host_no, stat & 0xff)); 2456 break; 2457 } 2458 } 2459 WRT_REG_DWORD(®->host_int, 0); 2460 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2461 } 2462 2463 void 2464 qla82xx_enable_intrs(struct qla_hw_data *ha) 2465 { 2466 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2467 qla82xx_mbx_intr_enable(vha); 2468 spin_lock_irq(&ha->hardware_lock); 2469 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2470 spin_unlock_irq(&ha->hardware_lock); 2471 ha->interrupts_on = 1; 2472 } 2473 2474 void 2475 qla82xx_disable_intrs(struct qla_hw_data *ha) 2476 { 2477 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2478 qla82xx_mbx_intr_disable(vha); 2479 spin_lock_irq(&ha->hardware_lock); 2480 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2481 spin_unlock_irq(&ha->hardware_lock); 2482 ha->interrupts_on = 0; 2483 } 2484 2485 void qla82xx_init_flags(struct qla_hw_data *ha) 2486 { 2487 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2488 2489 /* ISP 8021 initializations */ 2490 rwlock_init(&ha->hw_lock); 2491 ha->qdr_sn_window = -1; 2492 ha->ddr_mn_window = -1; 2493 ha->curr_window = 255; 2494 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2495 nx_legacy_intr = &legacy_intr[ha->portnum]; 2496 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2497 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2498 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2499 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2500 } 2501 2502 static inline void 2503 qla82xx_set_drv_active(scsi_qla_host_t *vha) 2504 { 2505 uint32_t drv_active; 2506 struct qla_hw_data *ha = vha->hw; 2507 2508 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2509 2510 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2511 if (drv_active == 0xffffffff) { 2512 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0); 2513 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2514 } 2515 drv_active |= (1 << (ha->portnum * 4)); 2516 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2517 } 2518 2519 inline void 2520 qla82xx_clear_drv_active(struct qla_hw_data *ha) 2521 { 2522 uint32_t drv_active; 2523 2524 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2525 drv_active &= ~(1 << (ha->portnum * 4)); 2526 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2527 } 2528 2529 static inline int 2530 qla82xx_need_reset(struct qla_hw_data *ha) 2531 { 2532 uint32_t drv_state; 2533 int rval; 2534 2535 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2536 rval = drv_state & (1 << (ha->portnum * 4)); 2537 return rval; 2538 } 2539 2540 static inline void 2541 qla82xx_set_rst_ready(struct qla_hw_data *ha) 2542 { 2543 uint32_t drv_state; 2544 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2545 2546 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2547 2548 /* If reset value is all FF's, initialize DRV_STATE */ 2549 if (drv_state == 0xffffffff) { 2550 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 2551 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2552 } 2553 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2554 qla_printk(KERN_INFO, ha, 2555 "%s(%ld):drv_state = 0x%x\n", 2556 __func__, vha->host_no, drv_state); 2557 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2558 } 2559 2560 static inline void 2561 qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2562 { 2563 uint32_t drv_state; 2564 2565 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2566 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2567 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2568 } 2569 2570 static inline void 2571 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2572 { 2573 uint32_t qsnt_state; 2574 2575 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2576 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2577 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2578 } 2579 2580 int qla82xx_load_fw(scsi_qla_host_t *vha) 2581 { 2582 int rst; 2583 struct fw_blob *blob; 2584 struct qla_hw_data *ha = vha->hw; 2585 2586 /* Put both the PEG CMD and RCV PEG to default state 2587 * of 0 before resetting the hardware 2588 */ 2589 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2590 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2591 2592 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2593 qla_printk(KERN_ERR, ha, 2594 "%s: Error during CRB Initialization\n", __func__); 2595 return QLA_FUNCTION_FAILED; 2596 } 2597 udelay(500); 2598 2599 /* Bring QM and CAMRAM out of reset */ 2600 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2601 rst &= ~((1 << 28) | (1 << 24)); 2602 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2603 2604 /* 2605 * FW Load priority: 2606 * 1) Operational firmware residing in flash. 2607 * 2) Firmware via request-firmware interface (.bin file). 2608 */ 2609 if (ql2xfwloadbin == 2) 2610 goto try_blob_fw; 2611 2612 qla_printk(KERN_INFO, ha, 2613 "Attempting to load firmware from flash\n"); 2614 2615 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2616 qla_printk(KERN_ERR, ha, 2617 "Firmware loaded successfully from flash\n"); 2618 return QLA_SUCCESS; 2619 } 2620 try_blob_fw: 2621 qla_printk(KERN_INFO, ha, 2622 "Attempting to load firmware from blob\n"); 2623 2624 /* Load firmware blob. */ 2625 blob = ha->hablob = qla2x00_request_firmware(vha); 2626 if (!blob) { 2627 qla_printk(KERN_ERR, ha, 2628 "Firmware image not present.\n"); 2629 goto fw_load_failed; 2630 } 2631 2632 /* Validating firmware blob */ 2633 if (qla82xx_validate_firmware_blob(vha, 2634 QLA82XX_FLASH_ROMIMAGE)) { 2635 /* Fallback to URI format */ 2636 if (qla82xx_validate_firmware_blob(vha, 2637 QLA82XX_UNIFIED_ROMIMAGE)) { 2638 qla_printk(KERN_ERR, ha, 2639 "No valid firmware image found!!!"); 2640 return QLA_FUNCTION_FAILED; 2641 } 2642 } 2643 2644 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2645 qla_printk(KERN_ERR, ha, 2646 "%s: Firmware loaded successfully " 2647 " from binary blob\n", __func__); 2648 return QLA_SUCCESS; 2649 } else { 2650 qla_printk(KERN_ERR, ha, 2651 "Firmware load failed from binary blob\n"); 2652 blob->fw = NULL; 2653 blob = NULL; 2654 goto fw_load_failed; 2655 } 2656 return QLA_SUCCESS; 2657 2658 fw_load_failed: 2659 return QLA_FUNCTION_FAILED; 2660 } 2661 2662 static int 2663 qla82xx_start_firmware(scsi_qla_host_t *vha) 2664 { 2665 int pcie_cap; 2666 uint16_t lnk; 2667 struct qla_hw_data *ha = vha->hw; 2668 2669 /* scrub dma mask expansion register */ 2670 qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 2671 2672 /* Overwrite stale initialization register values */ 2673 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2674 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2675 2676 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2677 qla_printk(KERN_INFO, ha, 2678 "%s: Error trying to start fw!\n", __func__); 2679 return QLA_FUNCTION_FAILED; 2680 } 2681 2682 /* Handshake with the card before we register the devices. */ 2683 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2684 qla_printk(KERN_INFO, ha, 2685 "%s: Error during card handshake!\n", __func__); 2686 return QLA_FUNCTION_FAILED; 2687 } 2688 2689 /* Negotiated Link width */ 2690 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2691 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2692 ha->link_width = (lnk >> 4) & 0x3f; 2693 2694 /* Synchronize with Receive peg */ 2695 return qla82xx_check_rcvpeg_state(ha); 2696 } 2697 2698 static inline int 2699 qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2700 uint16_t tot_dsds) 2701 { 2702 uint32_t *cur_dsd = NULL; 2703 scsi_qla_host_t *vha; 2704 struct qla_hw_data *ha; 2705 struct scsi_cmnd *cmd; 2706 struct scatterlist *cur_seg; 2707 uint32_t *dsd_seg; 2708 void *next_dsd; 2709 uint8_t avail_dsds; 2710 uint8_t first_iocb = 1; 2711 uint32_t dsd_list_len; 2712 struct dsd_dma *dsd_ptr; 2713 struct ct6_dsd *ctx; 2714 2715 cmd = sp->cmd; 2716 2717 /* Update entry type to indicate Command Type 3 IOCB */ 2718 *((uint32_t *)(&cmd_pkt->entry_type)) = 2719 __constant_cpu_to_le32(COMMAND_TYPE_6); 2720 2721 /* No data transfer */ 2722 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2723 cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2724 return 0; 2725 } 2726 2727 vha = sp->fcport->vha; 2728 ha = vha->hw; 2729 2730 /* Set transfer direction */ 2731 if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2732 cmd_pkt->control_flags = 2733 __constant_cpu_to_le16(CF_WRITE_DATA); 2734 ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2735 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2736 cmd_pkt->control_flags = 2737 __constant_cpu_to_le16(CF_READ_DATA); 2738 ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2739 } 2740 2741 cur_seg = scsi_sglist(cmd); 2742 ctx = sp->ctx; 2743 2744 while (tot_dsds) { 2745 avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2746 QLA_DSDS_PER_IOCB : tot_dsds; 2747 tot_dsds -= avail_dsds; 2748 dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2749 2750 dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2751 struct dsd_dma, list); 2752 next_dsd = dsd_ptr->dsd_addr; 2753 list_del(&dsd_ptr->list); 2754 ha->gbl_dsd_avail--; 2755 list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2756 ctx->dsd_use_cnt++; 2757 ha->gbl_dsd_inuse++; 2758 2759 if (first_iocb) { 2760 first_iocb = 0; 2761 dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2762 *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2763 *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2764 *dsd_seg++ = dsd_list_len; 2765 } else { 2766 *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2767 *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2768 *cur_dsd++ = dsd_list_len; 2769 } 2770 cur_dsd = (uint32_t *)next_dsd; 2771 while (avail_dsds) { 2772 dma_addr_t sle_dma; 2773 2774 sle_dma = sg_dma_address(cur_seg); 2775 *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2776 *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2777 *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2778 cur_seg++; 2779 avail_dsds--; 2780 } 2781 } 2782 2783 /* Null termination */ 2784 *cur_dsd++ = 0; 2785 *cur_dsd++ = 0; 2786 *cur_dsd++ = 0; 2787 cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2788 return 0; 2789 } 2790 2791 /* 2792 * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2793 * for Command Type 6. 2794 * 2795 * @dsds: number of data segment decriptors needed 2796 * 2797 * Returns the number of dsd list needed to store @dsds. 2798 */ 2799 inline uint16_t 2800 qla82xx_calc_dsd_lists(uint16_t dsds) 2801 { 2802 uint16_t dsd_lists = 0; 2803 2804 dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2805 if (dsds % QLA_DSDS_PER_IOCB) 2806 dsd_lists++; 2807 return dsd_lists; 2808 } 2809 2810 /* 2811 * qla82xx_start_scsi() - Send a SCSI command to the ISP 2812 * @sp: command to send to the ISP 2813 * 2814 * Returns non-zero if a failure occured, else zero. 2815 */ 2816 int 2817 qla82xx_start_scsi(srb_t *sp) 2818 { 2819 int ret, nseg; 2820 unsigned long flags; 2821 struct scsi_cmnd *cmd; 2822 uint32_t *clr_ptr; 2823 uint32_t index; 2824 uint32_t handle; 2825 uint16_t cnt; 2826 uint16_t req_cnt; 2827 uint16_t tot_dsds; 2828 struct device_reg_82xx __iomem *reg; 2829 uint32_t dbval; 2830 uint32_t *fcp_dl; 2831 uint8_t additional_cdb_len; 2832 struct ct6_dsd *ctx; 2833 struct scsi_qla_host *vha = sp->fcport->vha; 2834 struct qla_hw_data *ha = vha->hw; 2835 struct req_que *req = NULL; 2836 struct rsp_que *rsp = NULL; 2837 2838 /* Setup device pointers. */ 2839 ret = 0; 2840 reg = &ha->iobase->isp82; 2841 cmd = sp->cmd; 2842 req = vha->req; 2843 rsp = ha->rsp_q_map[0]; 2844 2845 /* So we know we haven't pci_map'ed anything yet */ 2846 tot_dsds = 0; 2847 2848 dbval = 0x04 | (ha->portnum << 5); 2849 2850 /* Send marker if required */ 2851 if (vha->marker_needed != 0) { 2852 if (qla2x00_marker(vha, req, 2853 rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) 2854 return QLA_FUNCTION_FAILED; 2855 vha->marker_needed = 0; 2856 } 2857 2858 /* Acquire ring specific lock */ 2859 spin_lock_irqsave(&ha->hardware_lock, flags); 2860 2861 /* Check for room in outstanding command list. */ 2862 handle = req->current_outstanding_cmd; 2863 for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2864 handle++; 2865 if (handle == MAX_OUTSTANDING_COMMANDS) 2866 handle = 1; 2867 if (!req->outstanding_cmds[handle]) 2868 break; 2869 } 2870 if (index == MAX_OUTSTANDING_COMMANDS) 2871 goto queuing_error; 2872 2873 /* Map the sg table so we have an accurate count of sg entries needed */ 2874 if (scsi_sg_count(cmd)) { 2875 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2876 scsi_sg_count(cmd), cmd->sc_data_direction); 2877 if (unlikely(!nseg)) 2878 goto queuing_error; 2879 } else 2880 nseg = 0; 2881 2882 tot_dsds = nseg; 2883 2884 if (tot_dsds > ql2xshiftctondsd) { 2885 struct cmd_type_6 *cmd_pkt; 2886 uint16_t more_dsd_lists = 0; 2887 struct dsd_dma *dsd_ptr; 2888 uint16_t i; 2889 2890 more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 2891 if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) 2892 goto queuing_error; 2893 2894 if (more_dsd_lists <= ha->gbl_dsd_avail) 2895 goto sufficient_dsds; 2896 else 2897 more_dsd_lists -= ha->gbl_dsd_avail; 2898 2899 for (i = 0; i < more_dsd_lists; i++) { 2900 dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 2901 if (!dsd_ptr) 2902 goto queuing_error; 2903 2904 dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2905 GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2906 if (!dsd_ptr->dsd_addr) { 2907 kfree(dsd_ptr); 2908 goto queuing_error; 2909 } 2910 list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2911 ha->gbl_dsd_avail++; 2912 } 2913 2914 sufficient_dsds: 2915 req_cnt = 1; 2916 2917 ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2918 if (!sp->ctx) { 2919 DEBUG(printk(KERN_INFO 2920 "%s(%ld): failed to allocate" 2921 " ctx.\n", __func__, vha->host_no)); 2922 goto queuing_error; 2923 } 2924 memset(ctx, 0, sizeof(struct ct6_dsd)); 2925 ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2926 GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2927 if (!ctx->fcp_cmnd) { 2928 DEBUG2_3(printk("%s(%ld): failed to allocate" 2929 " fcp_cmnd.\n", __func__, vha->host_no)); 2930 goto queuing_error_fcp_cmnd; 2931 } 2932 2933 /* Initialize the DSD list and dma handle */ 2934 INIT_LIST_HEAD(&ctx->dsd_list); 2935 ctx->dsd_use_cnt = 0; 2936 2937 if (cmd->cmd_len > 16) { 2938 additional_cdb_len = cmd->cmd_len - 16; 2939 if ((cmd->cmd_len % 4) != 0) { 2940 /* SCSI command bigger than 16 bytes must be 2941 * multiple of 4 2942 */ 2943 goto queuing_error_fcp_cmnd; 2944 } 2945 ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2946 } else { 2947 additional_cdb_len = 0; 2948 ctx->fcp_cmnd_len = 12 + 16 + 4; 2949 } 2950 2951 cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2952 cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2953 2954 /* Zero out remaining portion of packet. */ 2955 /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2956 clr_ptr = (uint32_t *)cmd_pkt + 2; 2957 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2958 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2959 2960 /* Set NPORT-ID and LUN number*/ 2961 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2962 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2963 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2964 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2965 cmd_pkt->vp_index = sp->fcport->vp_idx; 2966 2967 /* Build IOCB segments */ 2968 if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2969 goto queuing_error_fcp_cmnd; 2970 2971 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2972 2973 /* build FCP_CMND IU */ 2974 memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 2975 int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 2976 ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 2977 2978 if (cmd->sc_data_direction == DMA_TO_DEVICE) 2979 ctx->fcp_cmnd->additional_cdb_len |= 1; 2980 else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 2981 ctx->fcp_cmnd->additional_cdb_len |= 2; 2982 2983 memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2984 2985 fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2986 additional_cdb_len); 2987 *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2988 2989 cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2990 cmd_pkt->fcp_cmnd_dseg_address[0] = 2991 cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2992 cmd_pkt->fcp_cmnd_dseg_address[1] = 2993 cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2994 2995 sp->flags |= SRB_FCP_CMND_DMA_VALID; 2996 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2997 /* Set total data segment count. */ 2998 cmd_pkt->entry_count = (uint8_t)req_cnt; 2999 /* Specify response queue number where 3000 * completion should happen 3001 */ 3002 cmd_pkt->entry_status = (uint8_t) rsp->id; 3003 } else { 3004 struct cmd_type_7 *cmd_pkt; 3005 req_cnt = qla24xx_calc_iocbs(tot_dsds); 3006 if (req->cnt < (req_cnt + 2)) { 3007 cnt = (uint16_t)RD_REG_DWORD_RELAXED( 3008 ®->req_q_out[0]); 3009 if (req->ring_index < cnt) 3010 req->cnt = cnt - req->ring_index; 3011 else 3012 req->cnt = req->length - 3013 (req->ring_index - cnt); 3014 } 3015 if (req->cnt < (req_cnt + 2)) 3016 goto queuing_error; 3017 3018 cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 3019 cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 3020 3021 /* Zero out remaining portion of packet. */ 3022 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 3023 clr_ptr = (uint32_t *)cmd_pkt + 2; 3024 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 3025 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 3026 3027 /* Set NPORT-ID and LUN number*/ 3028 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 3029 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 3030 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 3031 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 3032 cmd_pkt->vp_index = sp->fcport->vp_idx; 3033 3034 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 3035 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 3036 sizeof(cmd_pkt->lun)); 3037 3038 /* Load SCSI command packet. */ 3039 memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 3040 host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 3041 3042 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 3043 3044 /* Build IOCB segments */ 3045 qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 3046 3047 /* Set total data segment count. */ 3048 cmd_pkt->entry_count = (uint8_t)req_cnt; 3049 /* Specify response queue number where 3050 * completion should happen. 3051 */ 3052 cmd_pkt->entry_status = (uint8_t) rsp->id; 3053 3054 } 3055 /* Build command packet. */ 3056 req->current_outstanding_cmd = handle; 3057 req->outstanding_cmds[handle] = sp; 3058 sp->handle = handle; 3059 sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 3060 req->cnt -= req_cnt; 3061 wmb(); 3062 3063 /* Adjust ring index. */ 3064 req->ring_index++; 3065 if (req->ring_index == req->length) { 3066 req->ring_index = 0; 3067 req->ring_ptr = req->ring; 3068 } else 3069 req->ring_ptr++; 3070 3071 sp->flags |= SRB_DMA_VALID; 3072 3073 /* Set chip new ring index. */ 3074 /* write, read and verify logic */ 3075 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 3076 if (ql2xdbwr) 3077 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 3078 else { 3079 WRT_REG_DWORD( 3080 (unsigned long __iomem *)ha->nxdb_wr_ptr, 3081 dbval); 3082 wmb(); 3083 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 3084 WRT_REG_DWORD( 3085 (unsigned long __iomem *)ha->nxdb_wr_ptr, 3086 dbval); 3087 wmb(); 3088 } 3089 } 3090 3091 /* Manage unprocessed RIO/ZIO commands in response queue. */ 3092 if (vha->flags.process_response_queue && 3093 rsp->ring_ptr->signature != RESPONSE_PROCESSED) 3094 qla24xx_process_response_queue(vha, rsp); 3095 3096 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3097 return QLA_SUCCESS; 3098 3099 queuing_error_fcp_cmnd: 3100 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 3101 queuing_error: 3102 if (tot_dsds) 3103 scsi_dma_unmap(cmd); 3104 3105 if (sp->ctx) { 3106 mempool_free(sp->ctx, ha->ctx_mempool); 3107 sp->ctx = NULL; 3108 } 3109 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3110 3111 return QLA_FUNCTION_FAILED; 3112 } 3113 3114 uint32_t * 3115 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 3116 uint32_t length) 3117 { 3118 uint32_t i; 3119 uint32_t val; 3120 struct qla_hw_data *ha = vha->hw; 3121 3122 /* Dword reads to flash. */ 3123 for (i = 0; i < length/4; i++, faddr += 4) { 3124 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 3125 qla_printk(KERN_WARNING, ha, 3126 "Do ROM fast read failed\n"); 3127 goto done_read; 3128 } 3129 dwptr[i] = __constant_cpu_to_le32(val); 3130 } 3131 done_read: 3132 return dwptr; 3133 } 3134 3135 int 3136 qla82xx_unprotect_flash(struct qla_hw_data *ha) 3137 { 3138 int ret; 3139 uint32_t val; 3140 3141 ret = ql82xx_rom_lock_d(ha); 3142 if (ret < 0) { 3143 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3144 return ret; 3145 } 3146 3147 ret = qla82xx_read_status_reg(ha, &val); 3148 if (ret < 0) 3149 goto done_unprotect; 3150 3151 val &= ~(BLOCK_PROTECT_BITS << 2); 3152 ret = qla82xx_write_status_reg(ha, val); 3153 if (ret < 0) { 3154 val |= (BLOCK_PROTECT_BITS << 2); 3155 qla82xx_write_status_reg(ha, val); 3156 } 3157 3158 if (qla82xx_write_disable_flash(ha) != 0) 3159 qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3160 3161 done_unprotect: 3162 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3163 return ret; 3164 } 3165 3166 int 3167 qla82xx_protect_flash(struct qla_hw_data *ha) 3168 { 3169 int ret; 3170 uint32_t val; 3171 3172 ret = ql82xx_rom_lock_d(ha); 3173 if (ret < 0) { 3174 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3175 return ret; 3176 } 3177 3178 ret = qla82xx_read_status_reg(ha, &val); 3179 if (ret < 0) 3180 goto done_protect; 3181 3182 val |= (BLOCK_PROTECT_BITS << 2); 3183 /* LOCK all sectors */ 3184 ret = qla82xx_write_status_reg(ha, val); 3185 if (ret < 0) 3186 qla_printk(KERN_WARNING, ha, "Write status register failed\n"); 3187 3188 if (qla82xx_write_disable_flash(ha) != 0) 3189 qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3190 done_protect: 3191 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3192 return ret; 3193 } 3194 3195 int 3196 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3197 { 3198 int ret = 0; 3199 3200 ret = ql82xx_rom_lock_d(ha); 3201 if (ret < 0) { 3202 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3203 return ret; 3204 } 3205 3206 qla82xx_flash_set_write_enable(ha); 3207 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3208 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3209 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3210 3211 if (qla82xx_wait_rom_done(ha)) { 3212 qla_printk(KERN_WARNING, ha, 3213 "Error waiting for rom done\n"); 3214 ret = -1; 3215 goto done; 3216 } 3217 ret = qla82xx_flash_wait_write_finish(ha); 3218 done: 3219 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3220 return ret; 3221 } 3222 3223 /* 3224 * Address and length are byte address 3225 */ 3226 uint8_t * 3227 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3228 uint32_t offset, uint32_t length) 3229 { 3230 scsi_block_requests(vha->host); 3231 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3232 scsi_unblock_requests(vha->host); 3233 return buf; 3234 } 3235 3236 static int 3237 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3238 uint32_t faddr, uint32_t dwords) 3239 { 3240 int ret; 3241 uint32_t liter; 3242 uint32_t sec_mask, rest_addr; 3243 dma_addr_t optrom_dma; 3244 void *optrom = NULL; 3245 int page_mode = 0; 3246 struct qla_hw_data *ha = vha->hw; 3247 3248 ret = -1; 3249 3250 /* Prepare burst-capable write on supported ISPs. */ 3251 if (page_mode && !(faddr & 0xfff) && 3252 dwords > OPTROM_BURST_DWORDS) { 3253 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3254 &optrom_dma, GFP_KERNEL); 3255 if (!optrom) { 3256 qla_printk(KERN_DEBUG, ha, 3257 "Unable to allocate memory for optrom " 3258 "burst write (%x KB).\n", 3259 OPTROM_BURST_SIZE / 1024); 3260 } 3261 } 3262 3263 rest_addr = ha->fdt_block_size - 1; 3264 sec_mask = ~rest_addr; 3265 3266 ret = qla82xx_unprotect_flash(ha); 3267 if (ret) { 3268 qla_printk(KERN_WARNING, ha, 3269 "Unable to unprotect flash for update.\n"); 3270 goto write_done; 3271 } 3272 3273 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3274 /* Are we at the beginning of a sector? */ 3275 if ((faddr & rest_addr) == 0) { 3276 3277 ret = qla82xx_erase_sector(ha, faddr); 3278 if (ret) { 3279 DEBUG9(qla_printk(KERN_ERR, ha, 3280 "Unable to erase sector: " 3281 "address=%x.\n", faddr)); 3282 break; 3283 } 3284 } 3285 3286 /* Go with burst-write. */ 3287 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3288 /* Copy data to DMA'ble buffer. */ 3289 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3290 3291 ret = qla2x00_load_ram(vha, optrom_dma, 3292 (ha->flash_data_off | faddr), 3293 OPTROM_BURST_DWORDS); 3294 if (ret != QLA_SUCCESS) { 3295 qla_printk(KERN_WARNING, ha, 3296 "Unable to burst-write optrom segment " 3297 "(%x/%x/%llx).\n", ret, 3298 (ha->flash_data_off | faddr), 3299 (unsigned long long)optrom_dma); 3300 qla_printk(KERN_WARNING, ha, 3301 "Reverting to slow-write.\n"); 3302 3303 dma_free_coherent(&ha->pdev->dev, 3304 OPTROM_BURST_SIZE, optrom, optrom_dma); 3305 optrom = NULL; 3306 } else { 3307 liter += OPTROM_BURST_DWORDS - 1; 3308 faddr += OPTROM_BURST_DWORDS - 1; 3309 dwptr += OPTROM_BURST_DWORDS - 1; 3310 continue; 3311 } 3312 } 3313 3314 ret = qla82xx_write_flash_dword(ha, faddr, 3315 cpu_to_le32(*dwptr)); 3316 if (ret) { 3317 DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program" 3318 "flash address=%x data=%x.\n", __func__, 3319 ha->host_no, faddr, *dwptr)); 3320 break; 3321 } 3322 } 3323 3324 ret = qla82xx_protect_flash(ha); 3325 if (ret) 3326 qla_printk(KERN_WARNING, ha, 3327 "Unable to protect flash after update.\n"); 3328 write_done: 3329 if (optrom) 3330 dma_free_coherent(&ha->pdev->dev, 3331 OPTROM_BURST_SIZE, optrom, optrom_dma); 3332 return ret; 3333 } 3334 3335 int 3336 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3337 uint32_t offset, uint32_t length) 3338 { 3339 int rval; 3340 3341 /* Suspend HBA. */ 3342 scsi_block_requests(vha->host); 3343 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3344 length >> 2); 3345 scsi_unblock_requests(vha->host); 3346 3347 /* Convert return ISP82xx to generic */ 3348 if (rval) 3349 rval = QLA_FUNCTION_FAILED; 3350 else 3351 rval = QLA_SUCCESS; 3352 return rval; 3353 } 3354 3355 void 3356 qla82xx_start_iocbs(srb_t *sp) 3357 { 3358 struct qla_hw_data *ha = sp->fcport->vha->hw; 3359 struct req_que *req = ha->req_q_map[0]; 3360 struct device_reg_82xx __iomem *reg; 3361 uint32_t dbval; 3362 3363 /* Adjust ring index. */ 3364 req->ring_index++; 3365 if (req->ring_index == req->length) { 3366 req->ring_index = 0; 3367 req->ring_ptr = req->ring; 3368 } else 3369 req->ring_ptr++; 3370 3371 reg = &ha->iobase->isp82; 3372 dbval = 0x04 | (ha->portnum << 5); 3373 3374 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 3375 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3376 wmb(); 3377 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 3378 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3379 wmb(); 3380 } 3381 } 3382 3383 /* 3384 * qla82xx_device_bootstrap 3385 * Initialize device, set DEV_READY, start fw 3386 * 3387 * Note: 3388 * IDC lock must be held upon entry 3389 * 3390 * Return: 3391 * Success : 0 3392 * Failed : 1 3393 */ 3394 static int 3395 qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3396 { 3397 int rval, i, timeout; 3398 uint32_t old_count, count; 3399 struct qla_hw_data *ha = vha->hw; 3400 3401 if (qla82xx_need_reset(ha)) 3402 goto dev_initialize; 3403 3404 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3405 3406 for (i = 0; i < 10; i++) { 3407 timeout = msleep_interruptible(200); 3408 if (timeout) { 3409 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3410 QLA82XX_DEV_FAILED); 3411 return QLA_FUNCTION_FAILED; 3412 } 3413 3414 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3415 if (count != old_count) 3416 goto dev_ready; 3417 } 3418 3419 dev_initialize: 3420 /* set to DEV_INITIALIZING */ 3421 qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 3422 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3423 3424 /* Driver that sets device state to initializating sets IDC version */ 3425 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3426 3427 qla82xx_idc_unlock(ha); 3428 rval = qla82xx_start_firmware(vha); 3429 qla82xx_idc_lock(ha); 3430 3431 if (rval != QLA_SUCCESS) { 3432 qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3433 qla82xx_clear_drv_active(ha); 3434 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3435 return rval; 3436 } 3437 3438 dev_ready: 3439 qla_printk(KERN_INFO, ha, "HW State: READY\n"); 3440 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3441 3442 return QLA_SUCCESS; 3443 } 3444 3445 static void 3446 qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3447 { 3448 struct qla_hw_data *ha = vha->hw; 3449 3450 /* Disable the board */ 3451 qla_printk(KERN_INFO, ha, "Disabling the board\n"); 3452 3453 qla82xx_idc_lock(ha); 3454 qla82xx_clear_drv_active(ha); 3455 qla82xx_idc_unlock(ha); 3456 3457 /* Set DEV_FAILED flag to disable timer */ 3458 vha->device_flags |= DFLG_DEV_FAILED; 3459 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3460 qla2x00_mark_all_devices_lost(vha, 0); 3461 vha->flags.online = 0; 3462 vha->flags.init_done = 0; 3463 } 3464 3465 /* 3466 * qla82xx_need_reset_handler 3467 * Code to start reset sequence 3468 * 3469 * Note: 3470 * IDC lock must be held upon entry 3471 * 3472 * Return: 3473 * Success : 0 3474 * Failed : 1 3475 */ 3476 static void 3477 qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3478 { 3479 uint32_t dev_state, drv_state, drv_active; 3480 unsigned long reset_timeout; 3481 struct qla_hw_data *ha = vha->hw; 3482 struct req_que *req = ha->req_q_map[0]; 3483 3484 if (vha->flags.online) { 3485 qla82xx_idc_unlock(ha); 3486 qla2x00_abort_isp_cleanup(vha); 3487 ha->isp_ops->get_flash_version(vha, req->ring); 3488 ha->isp_ops->nvram_config(vha); 3489 qla82xx_idc_lock(ha); 3490 } 3491 3492 qla82xx_set_rst_ready(ha); 3493 3494 /* wait for 10 seconds for reset ack from all functions */ 3495 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3496 3497 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3498 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3499 3500 while (drv_state != drv_active) { 3501 if (time_after_eq(jiffies, reset_timeout)) { 3502 qla_printk(KERN_INFO, ha, 3503 "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME); 3504 break; 3505 } 3506 qla82xx_idc_unlock(ha); 3507 msleep(1000); 3508 qla82xx_idc_lock(ha); 3509 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3510 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3511 } 3512 3513 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3514 qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 3515 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3516 3517 /* Force to DEV_COLD unless someone else is starting a reset */ 3518 if (dev_state != QLA82XX_DEV_INITIALIZING) { 3519 qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3520 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3521 } 3522 } 3523 3524 static void 3525 qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3526 { 3527 uint32_t fw_heartbeat_counter, halt_status; 3528 struct qla_hw_data *ha = vha->hw; 3529 3530 fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3531 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3532 vha->seconds_since_last_heartbeat++; 3533 /* FW not alive after 2 seconds */ 3534 if (vha->seconds_since_last_heartbeat == 2) { 3535 vha->seconds_since_last_heartbeat = 0; 3536 halt_status = qla82xx_rd_32(ha, 3537 QLA82XX_PEG_HALT_STATUS1); 3538 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3539 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3540 } else { 3541 qla_printk(KERN_INFO, ha, 3542 "scsi(%ld): %s - detect abort needed\n", 3543 vha->host_no, __func__); 3544 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3545 } 3546 qla2xxx_wake_dpc(vha); 3547 if (ha->flags.mbox_busy) { 3548 ha->flags.fw_hung = 1; 3549 ha->flags.mbox_int = 1; 3550 DEBUG2(qla_printk(KERN_ERR, ha, 3551 "Due to fw hung, doing premature " 3552 "completion of mbx command\n")); 3553 complete(&ha->mbx_intr_comp); 3554 } 3555 } 3556 } 3557 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3558 } 3559 3560 /* 3561 * qla82xx_device_state_handler 3562 * Main state handler 3563 * 3564 * Note: 3565 * IDC lock must be held upon entry 3566 * 3567 * Return: 3568 * Success : 0 3569 * Failed : 1 3570 */ 3571 int 3572 qla82xx_device_state_handler(scsi_qla_host_t *vha) 3573 { 3574 uint32_t dev_state; 3575 int rval = QLA_SUCCESS; 3576 unsigned long dev_init_timeout; 3577 struct qla_hw_data *ha = vha->hw; 3578 3579 qla82xx_idc_lock(ha); 3580 if (!vha->flags.init_done) 3581 qla82xx_set_drv_active(vha); 3582 3583 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3584 qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 3585 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3586 3587 /* wait for 30 seconds for device to go ready */ 3588 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3589 3590 while (1) { 3591 3592 if (time_after_eq(jiffies, dev_init_timeout)) { 3593 DEBUG(qla_printk(KERN_INFO, ha, 3594 "%s: device init failed!\n", 3595 QLA2XXX_DRIVER_NAME)); 3596 rval = QLA_FUNCTION_FAILED; 3597 break; 3598 } 3599 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3600 qla_printk(KERN_INFO, ha, 3601 "2:Device state is 0x%x = %s\n", dev_state, 3602 dev_state < MAX_STATES ? 3603 qdev_state[dev_state] : "Unknown"); 3604 3605 switch (dev_state) { 3606 case QLA82XX_DEV_READY: 3607 goto exit; 3608 case QLA82XX_DEV_COLD: 3609 rval = qla82xx_device_bootstrap(vha); 3610 goto exit; 3611 case QLA82XX_DEV_INITIALIZING: 3612 qla82xx_idc_unlock(ha); 3613 msleep(1000); 3614 qla82xx_idc_lock(ha); 3615 break; 3616 case QLA82XX_DEV_NEED_RESET: 3617 if (!ql2xdontresethba) 3618 qla82xx_need_reset_handler(vha); 3619 break; 3620 case QLA82XX_DEV_NEED_QUIESCENT: 3621 qla82xx_set_qsnt_ready(ha); 3622 case QLA82XX_DEV_QUIESCENT: 3623 qla82xx_idc_unlock(ha); 3624 msleep(1000); 3625 qla82xx_idc_lock(ha); 3626 break; 3627 case QLA82XX_DEV_FAILED: 3628 qla82xx_dev_failed_handler(vha); 3629 rval = QLA_FUNCTION_FAILED; 3630 goto exit; 3631 default: 3632 qla82xx_idc_unlock(ha); 3633 msleep(1000); 3634 qla82xx_idc_lock(ha); 3635 } 3636 } 3637 exit: 3638 qla82xx_idc_unlock(ha); 3639 return rval; 3640 } 3641 3642 void qla82xx_watchdog(scsi_qla_host_t *vha) 3643 { 3644 uint32_t dev_state; 3645 struct qla_hw_data *ha = vha->hw; 3646 3647 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3648 3649 /* don't poll if reset is going on */ 3650 if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 3651 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || 3652 test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) { 3653 if (dev_state == QLA82XX_DEV_NEED_RESET) { 3654 qla_printk(KERN_WARNING, ha, 3655 "%s(): Adapter reset needed!\n", __func__); 3656 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3657 qla2xxx_wake_dpc(vha); 3658 if (ha->flags.mbox_busy) { 3659 ha->flags.fw_hung = 1; 3660 ha->flags.mbox_int = 1; 3661 DEBUG2(qla_printk(KERN_ERR, ha, 3662 "Need reset, doing premature " 3663 "completion of mbx command\n")); 3664 complete(&ha->mbx_intr_comp); 3665 } 3666 } else { 3667 qla82xx_check_fw_alive(vha); 3668 } 3669 } 3670 } 3671 3672 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3673 { 3674 int rval; 3675 rval = qla82xx_device_state_handler(vha); 3676 return rval; 3677 } 3678 3679 /* 3680 * qla82xx_abort_isp 3681 * Resets ISP and aborts all outstanding commands. 3682 * 3683 * Input: 3684 * ha = adapter block pointer. 3685 * 3686 * Returns: 3687 * 0 = success 3688 */ 3689 int 3690 qla82xx_abort_isp(scsi_qla_host_t *vha) 3691 { 3692 int rval; 3693 struct qla_hw_data *ha = vha->hw; 3694 uint32_t dev_state; 3695 3696 if (vha->device_flags & DFLG_DEV_FAILED) { 3697 qla_printk(KERN_WARNING, ha, 3698 "%s(%ld): Device in failed state, " 3699 "Exiting.\n", __func__, vha->host_no); 3700 return QLA_SUCCESS; 3701 } 3702 3703 qla82xx_idc_lock(ha); 3704 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3705 if (dev_state == QLA82XX_DEV_READY) { 3706 qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3707 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3708 QLA82XX_DEV_NEED_RESET); 3709 } else 3710 qla_printk(KERN_INFO, ha, "HW State: %s\n", 3711 dev_state < MAX_STATES ? 3712 qdev_state[dev_state] : "Unknown"); 3713 qla82xx_idc_unlock(ha); 3714 3715 rval = qla82xx_device_state_handler(vha); 3716 3717 qla82xx_idc_lock(ha); 3718 qla82xx_clear_rst_ready(ha); 3719 qla82xx_idc_unlock(ha); 3720 3721 if (rval == QLA_SUCCESS) { 3722 ha->flags.fw_hung = 0; 3723 qla82xx_restart_isp(vha); 3724 } 3725 3726 if (rval) { 3727 vha->flags.online = 1; 3728 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3729 if (ha->isp_abort_cnt == 0) { 3730 qla_printk(KERN_WARNING, ha, 3731 "ISP error recovery failed - " 3732 "board disabled\n"); 3733 /* 3734 * The next call disables the board 3735 * completely. 3736 */ 3737 ha->isp_ops->reset_adapter(vha); 3738 vha->flags.online = 0; 3739 clear_bit(ISP_ABORT_RETRY, 3740 &vha->dpc_flags); 3741 rval = QLA_SUCCESS; 3742 } else { /* schedule another ISP abort */ 3743 ha->isp_abort_cnt--; 3744 DEBUG(qla_printk(KERN_INFO, ha, 3745 "qla%ld: ISP abort - retry remaining %d\n", 3746 vha->host_no, ha->isp_abort_cnt)); 3747 rval = QLA_FUNCTION_FAILED; 3748 } 3749 } else { 3750 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3751 DEBUG(qla_printk(KERN_INFO, ha, 3752 "(%ld): ISP error recovery - retrying (%d) " 3753 "more times\n", vha->host_no, ha->isp_abort_cnt)); 3754 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3755 rval = QLA_FUNCTION_FAILED; 3756 } 3757 } 3758 return rval; 3759 } 3760 3761 /* 3762 * qla82xx_fcoe_ctx_reset 3763 * Perform a quick reset and aborts all outstanding commands. 3764 * This will only perform an FCoE context reset and avoids a full blown 3765 * chip reset. 3766 * 3767 * Input: 3768 * ha = adapter block pointer. 3769 * is_reset_path = flag for identifying the reset path. 3770 * 3771 * Returns: 3772 * 0 = success 3773 */ 3774 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3775 { 3776 int rval = QLA_FUNCTION_FAILED; 3777 3778 if (vha->flags.online) { 3779 /* Abort all outstanding commands, so as to be requeued later */ 3780 qla2x00_abort_isp_cleanup(vha); 3781 } 3782 3783 /* Stop currently executing firmware. 3784 * This will destroy existing FCoE context at the F/W end. 3785 */ 3786 qla2x00_try_to_stop_firmware(vha); 3787 3788 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3789 rval = qla82xx_restart_isp(vha); 3790 3791 return rval; 3792 } 3793 3794 /* 3795 * qla2x00_wait_for_fcoe_ctx_reset 3796 * Wait till the FCoE context is reset. 3797 * 3798 * Note: 3799 * Does context switching here. 3800 * Release SPIN_LOCK (if any) before calling this routine. 3801 * 3802 * Return: 3803 * Success (fcoe_ctx reset is done) : 0 3804 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3805 */ 3806 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3807 { 3808 int status = QLA_FUNCTION_FAILED; 3809 unsigned long wait_reset; 3810 3811 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3812 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3813 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3814 && time_before(jiffies, wait_reset)) { 3815 3816 set_current_state(TASK_UNINTERRUPTIBLE); 3817 schedule_timeout(HZ); 3818 3819 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3820 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3821 status = QLA_SUCCESS; 3822 break; 3823 } 3824 } 3825 DEBUG2(printk(KERN_INFO 3826 "%s status=%d\n", __func__, status)); 3827 3828 return status; 3829 } 3830