1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 3a9083016SGiridhar Malavali * Copyright (c) 2003-2008 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 10a9083016SGiridhar Malavali 11a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 12a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 13a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 14a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 15a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 16a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 17a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 18a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 19a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 20a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 21a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 22a9083016SGiridhar Malavali 23a9083016SGiridhar Malavali /* CRB window related */ 24a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 25a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 26a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 27a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 28a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 29a9083016SGiridhar Malavali ((off) & 0xf0000)) 30a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 31a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 32a9083016SGiridhar Malavali 33a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 34a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 35a9083016SGiridhar Malavali int qla82xx_crb_table_initialized; 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 38a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 39a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 42a9083016SGiridhar Malavali { 43a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 44a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 45a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 46a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 93a9083016SGiridhar Malavali /* 94a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 95a9083016SGiridhar Malavali */ 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 97a9083016SGiridhar Malavali 98a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 99a9083016SGiridhar Malavali } 100a9083016SGiridhar Malavali 101a9083016SGiridhar Malavali struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 102a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 103a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 104a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 105a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 106a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 107a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 108a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 109a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 110a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 111a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 112a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 113a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 114a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 119a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 120a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 121a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 122a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 123a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 124a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 125a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 126a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 127a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 128a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 129a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 141a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 145a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 157a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 161a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 173a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 177a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 189a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 190a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 191a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 192a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 193a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 194a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 195a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 196a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 197a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 200a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 201a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 202a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 203a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 207a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 208a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 209a9083016SGiridhar Malavali {{{0} } }, 210a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 211a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 212a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 213a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 214a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 215a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 216a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 217a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 218a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 219a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 220a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 221a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 226a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 227a9083016SGiridhar Malavali {{{0} } }, 228a9083016SGiridhar Malavali {{{0} } }, 229a9083016SGiridhar Malavali {{{0} } }, 230a9083016SGiridhar Malavali {{{0} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 233a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 234a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 235a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 236a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 237a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 240a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 241a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 242a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 243a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 244a9083016SGiridhar Malavali {{{0} } }, 245a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 248a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 249a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 251a9083016SGiridhar Malavali {{{0} } }, 252a9083016SGiridhar Malavali {{{0} } }, 253a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 255a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 256a9083016SGiridhar Malavali }; 257a9083016SGiridhar Malavali 258a9083016SGiridhar Malavali /* 259a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 260a9083016SGiridhar Malavali */ 261a9083016SGiridhar Malavali unsigned qla82xx_crb_hub_agt[64] = { 262a9083016SGiridhar Malavali 0, 263a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 264a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 265a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 270a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 289a9083016SGiridhar Malavali 0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 292a9083016SGiridhar Malavali 0, 293a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 294a9083016SGiridhar Malavali 0, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 296a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 297a9083016SGiridhar Malavali 0, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali 0, 300a9083016SGiridhar Malavali 0, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 305a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 307a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 314a9083016SGiridhar Malavali 0, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 318a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 319a9083016SGiridhar Malavali 0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 325a9083016SGiridhar Malavali 0, 326a9083016SGiridhar Malavali }; 327a9083016SGiridhar Malavali 328f1af6208SGiridhar Malavali /* Device states */ 329f1af6208SGiridhar Malavali char *qdev_state[] = { 330f1af6208SGiridhar Malavali "Unknown", 331f1af6208SGiridhar Malavali "Cold", 332f1af6208SGiridhar Malavali "Initializing", 333f1af6208SGiridhar Malavali "Ready", 334f1af6208SGiridhar Malavali "Need Reset", 335f1af6208SGiridhar Malavali "Need Quiescent", 336f1af6208SGiridhar Malavali "Failed", 337f1af6208SGiridhar Malavali "Quiescent", 338f1af6208SGiridhar Malavali }; 339f1af6208SGiridhar Malavali 340a9083016SGiridhar Malavali /* 341a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 342a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 343a9083016SGiridhar Malavali * side effect: lock crb window 344a9083016SGiridhar Malavali */ 345a9083016SGiridhar Malavali static void 346a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 347a9083016SGiridhar Malavali { 348a9083016SGiridhar Malavali u32 win_read; 349a9083016SGiridhar Malavali 350a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 351a9083016SGiridhar Malavali writel(ha->crb_win, 352a9083016SGiridhar Malavali (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 353a9083016SGiridhar Malavali 354a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 355a9083016SGiridhar Malavali * to use it. 356a9083016SGiridhar Malavali */ 357a9083016SGiridhar Malavali win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 358a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 359a9083016SGiridhar Malavali DEBUG2(qla_printk(KERN_INFO, ha, 360a9083016SGiridhar Malavali "%s: Written crbwin (0x%x) != Read crbwin (0x%x), " 361a9083016SGiridhar Malavali "off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 362a9083016SGiridhar Malavali } 363a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 364a9083016SGiridhar Malavali } 365a9083016SGiridhar Malavali 366a9083016SGiridhar Malavali static inline unsigned long 367a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 368a9083016SGiridhar Malavali { 369a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 370a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 371a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 372a9083016SGiridhar Malavali * regs are in both windows. 373a9083016SGiridhar Malavali */ 374a9083016SGiridhar Malavali return off; 375a9083016SGiridhar Malavali } 376a9083016SGiridhar Malavali 377a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 378a9083016SGiridhar Malavali /* We are in first CRB window */ 379a9083016SGiridhar Malavali if (ha->curr_window != 0) 380a9083016SGiridhar Malavali WARN_ON(1); 381a9083016SGiridhar Malavali return off; 382a9083016SGiridhar Malavali } 383a9083016SGiridhar Malavali 384a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 385a9083016SGiridhar Malavali /* We are in second CRB window */ 386a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 387a9083016SGiridhar Malavali 388a9083016SGiridhar Malavali if (ha->curr_window != 1) 389a9083016SGiridhar Malavali return off; 390a9083016SGiridhar Malavali 391a9083016SGiridhar Malavali /* We are in the QM or direct access 392a9083016SGiridhar Malavali * register region - do nothing 393a9083016SGiridhar Malavali */ 394a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 395a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 396a9083016SGiridhar Malavali return off; 397a9083016SGiridhar Malavali } 398a9083016SGiridhar Malavali /* strange address given */ 399a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 400a9083016SGiridhar Malavali "%s: Warning: unm_nic_pci_set_crbwindow called with" 401a9083016SGiridhar Malavali " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off); 402a9083016SGiridhar Malavali return off; 403a9083016SGiridhar Malavali } 404a9083016SGiridhar Malavali 405a9083016SGiridhar Malavali int 406a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 407a9083016SGiridhar Malavali { 408a9083016SGiridhar Malavali unsigned long flags = 0; 409a9083016SGiridhar Malavali int rv; 410a9083016SGiridhar Malavali 411a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 412a9083016SGiridhar Malavali 413a9083016SGiridhar Malavali BUG_ON(rv == -1); 414a9083016SGiridhar Malavali 415a9083016SGiridhar Malavali if (rv == 1) { 416a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 417a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 418a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 419a9083016SGiridhar Malavali } 420a9083016SGiridhar Malavali 421a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 422a9083016SGiridhar Malavali 423a9083016SGiridhar Malavali if (rv == 1) { 424a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 425a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 426a9083016SGiridhar Malavali } 427a9083016SGiridhar Malavali return 0; 428a9083016SGiridhar Malavali } 429a9083016SGiridhar Malavali 430a9083016SGiridhar Malavali int 431a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 432a9083016SGiridhar Malavali { 433a9083016SGiridhar Malavali unsigned long flags = 0; 434a9083016SGiridhar Malavali int rv; 435a9083016SGiridhar Malavali u32 data; 436a9083016SGiridhar Malavali 437a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 438a9083016SGiridhar Malavali 439a9083016SGiridhar Malavali BUG_ON(rv == -1); 440a9083016SGiridhar Malavali 441a9083016SGiridhar Malavali if (rv == 1) { 442a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 443a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 444a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 445a9083016SGiridhar Malavali } 446a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 447a9083016SGiridhar Malavali 448a9083016SGiridhar Malavali if (rv == 1) { 449a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 450a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 451a9083016SGiridhar Malavali } 452a9083016SGiridhar Malavali return data; 453a9083016SGiridhar Malavali } 454a9083016SGiridhar Malavali 455a9083016SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 456a9083016SGiridhar Malavali int qla82xx_crb_win_lock(struct qla_hw_data *ha) 457a9083016SGiridhar Malavali { 458a9083016SGiridhar Malavali int done = 0, timeout = 0; 459a9083016SGiridhar Malavali 460a9083016SGiridhar Malavali while (!done) { 461a9083016SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 462a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 463a9083016SGiridhar Malavali if (done == 1) 464a9083016SGiridhar Malavali break; 465a9083016SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 466a9083016SGiridhar Malavali return -1; 467a9083016SGiridhar Malavali timeout++; 468a9083016SGiridhar Malavali } 469a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 470a9083016SGiridhar Malavali return 0; 471a9083016SGiridhar Malavali } 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 474a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 475a9083016SGiridhar Malavali { 476a9083016SGiridhar Malavali int i; 477a9083016SGiridhar Malavali int done = 0, timeout = 0; 478a9083016SGiridhar Malavali 479a9083016SGiridhar Malavali while (!done) { 480a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 481a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 482a9083016SGiridhar Malavali if (done == 1) 483a9083016SGiridhar Malavali break; 484a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 485a9083016SGiridhar Malavali return -1; 486a9083016SGiridhar Malavali 487a9083016SGiridhar Malavali timeout++; 488a9083016SGiridhar Malavali 489a9083016SGiridhar Malavali /* Yield CPU */ 490a9083016SGiridhar Malavali if (!in_interrupt()) 491a9083016SGiridhar Malavali schedule(); 492a9083016SGiridhar Malavali else { 493a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 494a9083016SGiridhar Malavali cpu_relax(); 495a9083016SGiridhar Malavali } 496a9083016SGiridhar Malavali } 497a9083016SGiridhar Malavali 498a9083016SGiridhar Malavali return 0; 499a9083016SGiridhar Malavali } 500a9083016SGiridhar Malavali 501a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 502a9083016SGiridhar Malavali { 503a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 504a9083016SGiridhar Malavali } 505a9083016SGiridhar Malavali 506a9083016SGiridhar Malavali int 507a9083016SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 508a9083016SGiridhar Malavali { 509a9083016SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 510a9083016SGiridhar Malavali 511a9083016SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 512a9083016SGiridhar Malavali return -1; 513a9083016SGiridhar Malavali 514a9083016SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 515a9083016SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 516a9083016SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 517a9083016SGiridhar Malavali return 0; 518a9083016SGiridhar Malavali } 519a9083016SGiridhar Malavali 520a9083016SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 521a9083016SGiridhar Malavali return -1; 522a9083016SGiridhar Malavali 523a9083016SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 524a9083016SGiridhar Malavali 525a9083016SGiridhar Malavali /* Try direct map */ 526a9083016SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 527a9083016SGiridhar Malavali 528a9083016SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 529a9083016SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 530a9083016SGiridhar Malavali return 0; 531a9083016SGiridhar Malavali } 532a9083016SGiridhar Malavali /* Not in direct map, use crb window */ 533a9083016SGiridhar Malavali return 1; 534a9083016SGiridhar Malavali } 535a9083016SGiridhar Malavali 536a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 537a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 538a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 539a9083016SGiridhar Malavali /* 540a9083016SGiridhar Malavali * check memory access boundary. 541a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 542a9083016SGiridhar Malavali */ 543a9083016SGiridhar Malavali static unsigned long 544a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 545a9083016SGiridhar Malavali unsigned long long addr, int size) 546a9083016SGiridhar Malavali { 547a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 548a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 549a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 550a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 551a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 552a9083016SGiridhar Malavali return 0; 553a9083016SGiridhar Malavali else 554a9083016SGiridhar Malavali return 1; 555a9083016SGiridhar Malavali } 556a9083016SGiridhar Malavali 557a9083016SGiridhar Malavali int qla82xx_pci_set_window_warning_count; 558a9083016SGiridhar Malavali 559a9083016SGiridhar Malavali unsigned long 560a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 561a9083016SGiridhar Malavali { 562a9083016SGiridhar Malavali int window; 563a9083016SGiridhar Malavali u32 win_read; 564a9083016SGiridhar Malavali 565a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 566a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 567a9083016SGiridhar Malavali /* DDR network side */ 568a9083016SGiridhar Malavali window = MN_WIN(addr); 569a9083016SGiridhar Malavali ha->ddr_mn_window = window; 570a9083016SGiridhar Malavali qla82xx_wr_32(ha, 571a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 572a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 573a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 574a9083016SGiridhar Malavali if ((win_read << 17) != window) { 575a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 576a9083016SGiridhar Malavali "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 577a9083016SGiridhar Malavali __func__, window, win_read); 578a9083016SGiridhar Malavali } 579a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 580a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 581a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 582a9083016SGiridhar Malavali unsigned int temp1; 583a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 584a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 585a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 586a9083016SGiridhar Malavali addr = -1UL; 587a9083016SGiridhar Malavali } 588a9083016SGiridhar Malavali window = OCM_WIN(addr); 589a9083016SGiridhar Malavali ha->ddr_mn_window = window; 590a9083016SGiridhar Malavali qla82xx_wr_32(ha, 591a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 592a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 593a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 594a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 595a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 596a9083016SGiridhar Malavali if (win_read != temp1) { 597a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 598a9083016SGiridhar Malavali "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n", 599a9083016SGiridhar Malavali __func__, temp1, win_read); 600a9083016SGiridhar Malavali } 601a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 602a9083016SGiridhar Malavali 603a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 604a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 605a9083016SGiridhar Malavali /* QDR network side */ 606a9083016SGiridhar Malavali window = MS_WIN(addr); 607a9083016SGiridhar Malavali ha->qdr_sn_window = window; 608a9083016SGiridhar Malavali qla82xx_wr_32(ha, 609a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 610a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 611a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 612a9083016SGiridhar Malavali if (win_read != window) { 613a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 614a9083016SGiridhar Malavali "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n", 615a9083016SGiridhar Malavali __func__, window, win_read); 616a9083016SGiridhar Malavali } 617a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 618a9083016SGiridhar Malavali } else { 619a9083016SGiridhar Malavali /* 620a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 621a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 622a9083016SGiridhar Malavali */ 623a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 624a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 625a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 626a9083016SGiridhar Malavali "%s: Warning:%s Unknown address range!\n", __func__, 627a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 628a9083016SGiridhar Malavali } 629a9083016SGiridhar Malavali addr = -1UL; 630a9083016SGiridhar Malavali } 631a9083016SGiridhar Malavali return addr; 632a9083016SGiridhar Malavali } 633a9083016SGiridhar Malavali 634a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 635a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 636a9083016SGiridhar Malavali unsigned long long addr) 637a9083016SGiridhar Malavali { 638a9083016SGiridhar Malavali int window; 639a9083016SGiridhar Malavali unsigned long long qdr_max; 640a9083016SGiridhar Malavali 641a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 642a9083016SGiridhar Malavali 643a9083016SGiridhar Malavali /* DDR network side */ 644a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 645a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 646a9083016SGiridhar Malavali BUG(); 647a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 648a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 649a9083016SGiridhar Malavali return 1; 650a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 651a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 652a9083016SGiridhar Malavali return 1; 653a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 654a9083016SGiridhar Malavali /* QDR network side */ 655a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 656a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 657a9083016SGiridhar Malavali return 1; 658a9083016SGiridhar Malavali } 659a9083016SGiridhar Malavali return 0; 660a9083016SGiridhar Malavali } 661a9083016SGiridhar Malavali 662a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 663a9083016SGiridhar Malavali u64 off, void *data, int size) 664a9083016SGiridhar Malavali { 665a9083016SGiridhar Malavali unsigned long flags; 666f1af6208SGiridhar Malavali void *addr = NULL; 667a9083016SGiridhar Malavali int ret = 0; 668a9083016SGiridhar Malavali u64 start; 669a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 670a9083016SGiridhar Malavali unsigned long mem_base; 671a9083016SGiridhar Malavali unsigned long mem_page; 672a9083016SGiridhar Malavali 673a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 674a9083016SGiridhar Malavali 675a9083016SGiridhar Malavali /* 676a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 677a9083016SGiridhar Malavali * do not access. 678a9083016SGiridhar Malavali */ 679a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 680a9083016SGiridhar Malavali if ((start == -1UL) || 681a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 682a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 683a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 684a9083016SGiridhar Malavali "%s out of bound pci memory access. " 685a9083016SGiridhar Malavali "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 686a9083016SGiridhar Malavali return -1; 687a9083016SGiridhar Malavali } 688a9083016SGiridhar Malavali 689a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 690a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 691a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 692a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 693a9083016SGiridhar Malavali * consecutive pages. 694a9083016SGiridhar Malavali */ 695a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 696a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 697a9083016SGiridhar Malavali else 698a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 699a9083016SGiridhar Malavali if (mem_ptr == 0UL) { 700a9083016SGiridhar Malavali *(u8 *)data = 0; 701a9083016SGiridhar Malavali return -1; 702a9083016SGiridhar Malavali } 703a9083016SGiridhar Malavali addr = mem_ptr; 704a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 705a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 706a9083016SGiridhar Malavali 707a9083016SGiridhar Malavali switch (size) { 708a9083016SGiridhar Malavali case 1: 709a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 710a9083016SGiridhar Malavali break; 711a9083016SGiridhar Malavali case 2: 712a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 713a9083016SGiridhar Malavali break; 714a9083016SGiridhar Malavali case 4: 715a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 716a9083016SGiridhar Malavali break; 717a9083016SGiridhar Malavali case 8: 718a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 719a9083016SGiridhar Malavali break; 720a9083016SGiridhar Malavali default: 721a9083016SGiridhar Malavali ret = -1; 722a9083016SGiridhar Malavali break; 723a9083016SGiridhar Malavali } 724a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 725a9083016SGiridhar Malavali 726a9083016SGiridhar Malavali if (mem_ptr) 727a9083016SGiridhar Malavali iounmap(mem_ptr); 728a9083016SGiridhar Malavali return ret; 729a9083016SGiridhar Malavali } 730a9083016SGiridhar Malavali 731a9083016SGiridhar Malavali static int 732a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 733a9083016SGiridhar Malavali u64 off, void *data, int size) 734a9083016SGiridhar Malavali { 735a9083016SGiridhar Malavali unsigned long flags; 736f1af6208SGiridhar Malavali void *addr = NULL; 737a9083016SGiridhar Malavali int ret = 0; 738a9083016SGiridhar Malavali u64 start; 739a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 740a9083016SGiridhar Malavali unsigned long mem_base; 741a9083016SGiridhar Malavali unsigned long mem_page; 742a9083016SGiridhar Malavali 743a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 744a9083016SGiridhar Malavali 745a9083016SGiridhar Malavali /* 746a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 747a9083016SGiridhar Malavali * do not access. 748a9083016SGiridhar Malavali */ 749a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 750a9083016SGiridhar Malavali if ((start == -1UL) || 751a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 752a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 753a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 754a9083016SGiridhar Malavali "%s out of bound pci memory access. " 755a9083016SGiridhar Malavali "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 756a9083016SGiridhar Malavali return -1; 757a9083016SGiridhar Malavali } 758a9083016SGiridhar Malavali 759a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 760a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 761a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 762a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 763a9083016SGiridhar Malavali * consecutive pages. 764a9083016SGiridhar Malavali */ 765a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 766a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 767a9083016SGiridhar Malavali else 768a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 769a9083016SGiridhar Malavali if (mem_ptr == 0UL) 770a9083016SGiridhar Malavali return -1; 771a9083016SGiridhar Malavali 772a9083016SGiridhar Malavali addr = mem_ptr; 773a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 774a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 775a9083016SGiridhar Malavali 776a9083016SGiridhar Malavali switch (size) { 777a9083016SGiridhar Malavali case 1: 778a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 779a9083016SGiridhar Malavali break; 780a9083016SGiridhar Malavali case 2: 781a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 782a9083016SGiridhar Malavali break; 783a9083016SGiridhar Malavali case 4: 784a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 785a9083016SGiridhar Malavali break; 786a9083016SGiridhar Malavali case 8: 787a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 788a9083016SGiridhar Malavali break; 789a9083016SGiridhar Malavali default: 790a9083016SGiridhar Malavali ret = -1; 791a9083016SGiridhar Malavali break; 792a9083016SGiridhar Malavali } 793a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 794a9083016SGiridhar Malavali if (mem_ptr) 795a9083016SGiridhar Malavali iounmap(mem_ptr); 796a9083016SGiridhar Malavali return ret; 797a9083016SGiridhar Malavali } 798a9083016SGiridhar Malavali 799a9083016SGiridhar Malavali int 800a9083016SGiridhar Malavali qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size) 801a9083016SGiridhar Malavali { 802a9083016SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 803a9083016SGiridhar Malavali u32 temp; 804a9083016SGiridhar Malavali u64 off8, mem_crb, tmpw, word[2] = {0, 0}; 805a9083016SGiridhar Malavali #define MAX_CTL_CHECK 1000 806a9083016SGiridhar Malavali /* 807a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 808a9083016SGiridhar Malavali */ 809a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) { 810a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 811a9083016SGiridhar Malavali } else { 812a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 813a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 814a9083016SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, off, 815a9083016SGiridhar Malavali data, size); 816a9083016SGiridhar Malavali } 817a9083016SGiridhar Malavali 818a9083016SGiridhar Malavali off8 = off & 0xfffffff8; 819a9083016SGiridhar Malavali off0 = off & 0x7; 820a9083016SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 821a9083016SGiridhar Malavali sz[1] = size - sz[0]; 822a9083016SGiridhar Malavali loop = ((off0 + size - 1) >> 3) + 1; 823a9083016SGiridhar Malavali 824a9083016SGiridhar Malavali if ((size != 8) || (off0 != 0)) { 825a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 826a9083016SGiridhar Malavali if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8)) 827a9083016SGiridhar Malavali return -1; 828a9083016SGiridhar Malavali } 829a9083016SGiridhar Malavali } 830a9083016SGiridhar Malavali 831a9083016SGiridhar Malavali switch (size) { 832a9083016SGiridhar Malavali case 1: 833a9083016SGiridhar Malavali tmpw = *((u8 *)data); 834a9083016SGiridhar Malavali break; 835a9083016SGiridhar Malavali case 2: 836a9083016SGiridhar Malavali tmpw = *((u16 *)data); 837a9083016SGiridhar Malavali break; 838a9083016SGiridhar Malavali case 4: 839a9083016SGiridhar Malavali tmpw = *((u32 *)data); 840a9083016SGiridhar Malavali break; 841a9083016SGiridhar Malavali case 8: 842a9083016SGiridhar Malavali default: 843a9083016SGiridhar Malavali tmpw = *((u64 *)data); 844a9083016SGiridhar Malavali break; 845a9083016SGiridhar Malavali } 846a9083016SGiridhar Malavali 847a9083016SGiridhar Malavali word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 848a9083016SGiridhar Malavali word[0] |= tmpw << (off0 * 8); 849a9083016SGiridhar Malavali 850a9083016SGiridhar Malavali if (loop == 2) { 851a9083016SGiridhar Malavali word[1] &= ~(~0ULL << (sz[1] * 8)); 852a9083016SGiridhar Malavali word[1] |= tmpw >> (sz[0] * 8); 853a9083016SGiridhar Malavali } 854a9083016SGiridhar Malavali 855a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 856a9083016SGiridhar Malavali temp = off8 + (i << 3); 857a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 858a9083016SGiridhar Malavali temp = 0; 859a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 860a9083016SGiridhar Malavali temp = word[i] & 0xffffffff; 861a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 862a9083016SGiridhar Malavali temp = (word[i] >> 32) & 0xffffffff; 863a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 864a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 865a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 866a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 867a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 868a9083016SGiridhar Malavali 869a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 870a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 871a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 872a9083016SGiridhar Malavali break; 873a9083016SGiridhar Malavali } 874a9083016SGiridhar Malavali 875a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 876a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 877a9083016SGiridhar Malavali "%s: Fail to write through agent\n", 878a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 879a9083016SGiridhar Malavali ret = -1; 880a9083016SGiridhar Malavali break; 881a9083016SGiridhar Malavali } 882a9083016SGiridhar Malavali } 883a9083016SGiridhar Malavali return ret; 884a9083016SGiridhar Malavali } 885a9083016SGiridhar Malavali 886a9083016SGiridhar Malavali int 887a9083016SGiridhar Malavali qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size) 888a9083016SGiridhar Malavali { 889a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 890a9083016SGiridhar Malavali u32 temp; 891a9083016SGiridhar Malavali u64 off8, val, mem_crb, word[2] = {0, 0}; 892a9083016SGiridhar Malavali #define MAX_CTL_CHECK 1000 893a9083016SGiridhar Malavali 894a9083016SGiridhar Malavali /* 895a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 896a9083016SGiridhar Malavali */ 897a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 898a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 899a9083016SGiridhar Malavali else { 900a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 901a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 902a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, off, 903a9083016SGiridhar Malavali data, size); 904a9083016SGiridhar Malavali } 905a9083016SGiridhar Malavali 906a9083016SGiridhar Malavali off8 = off & 0xfffffff8; 907a9083016SGiridhar Malavali off0[0] = off & 0x7; 908a9083016SGiridhar Malavali off0[1] = 0; 909a9083016SGiridhar Malavali sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); 910a9083016SGiridhar Malavali sz[1] = size - sz[0]; 911a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> 3) + 1; 912a9083016SGiridhar Malavali 913a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 914a9083016SGiridhar Malavali temp = off8 + (i << 3); 915a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 916a9083016SGiridhar Malavali temp = 0; 917a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 918a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 919a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 920a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 921a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 922a9083016SGiridhar Malavali 923a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 924a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 925a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 926a9083016SGiridhar Malavali break; 927a9083016SGiridhar Malavali } 928a9083016SGiridhar Malavali 929a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 930a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 931a9083016SGiridhar Malavali "%s: Fail to read through agent\n", 932a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 933a9083016SGiridhar Malavali break; 934a9083016SGiridhar Malavali } 935a9083016SGiridhar Malavali 936a9083016SGiridhar Malavali start = off0[i] >> 2; 937a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 938a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 939a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 940a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 941a9083016SGiridhar Malavali word[i] |= ((u64)temp << (32 * k)); 942a9083016SGiridhar Malavali } 943a9083016SGiridhar Malavali } 944a9083016SGiridhar Malavali 945a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 946a9083016SGiridhar Malavali return -1; 947a9083016SGiridhar Malavali 948a9083016SGiridhar Malavali if (sz[0] == 8) { 949a9083016SGiridhar Malavali val = word[0]; 950a9083016SGiridhar Malavali } else { 951a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 952a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 953a9083016SGiridhar Malavali } 954a9083016SGiridhar Malavali 955a9083016SGiridhar Malavali switch (size) { 956a9083016SGiridhar Malavali case 1: 957a9083016SGiridhar Malavali *(u8 *)data = val; 958a9083016SGiridhar Malavali break; 959a9083016SGiridhar Malavali case 2: 960a9083016SGiridhar Malavali *(u16 *)data = val; 961a9083016SGiridhar Malavali break; 962a9083016SGiridhar Malavali case 4: 963a9083016SGiridhar Malavali *(u32 *)data = val; 964a9083016SGiridhar Malavali break; 965a9083016SGiridhar Malavali case 8: 966a9083016SGiridhar Malavali *(u64 *)data = val; 967a9083016SGiridhar Malavali break; 968a9083016SGiridhar Malavali } 969a9083016SGiridhar Malavali return 0; 970a9083016SGiridhar Malavali } 971a9083016SGiridhar Malavali 972a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 973a9083016SGiridhar Malavali unsigned long qla82xx_decode_crb_addr(unsigned long addr) 974a9083016SGiridhar Malavali { 975a9083016SGiridhar Malavali int i; 976a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 977a9083016SGiridhar Malavali 978a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 979a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 980a9083016SGiridhar Malavali 981a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 982a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 983a9083016SGiridhar Malavali offset = addr & 0x000fffff; 984a9083016SGiridhar Malavali 985a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 986a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 987a9083016SGiridhar Malavali pci_base = i << 20; 988a9083016SGiridhar Malavali break; 989a9083016SGiridhar Malavali } 990a9083016SGiridhar Malavali } 991a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 992a9083016SGiridhar Malavali return pci_base; 993a9083016SGiridhar Malavali return pci_base + offset; 994a9083016SGiridhar Malavali } 995a9083016SGiridhar Malavali 996a9083016SGiridhar Malavali static long rom_max_timeout = 100; 997a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 998a9083016SGiridhar Malavali 999a9083016SGiridhar Malavali int 1000a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 1001a9083016SGiridhar Malavali { 1002a9083016SGiridhar Malavali int done = 0, timeout = 0; 1003a9083016SGiridhar Malavali 1004a9083016SGiridhar Malavali while (!done) { 1005a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 1006a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 1007a9083016SGiridhar Malavali if (done == 1) 1008a9083016SGiridhar Malavali break; 1009a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 1010a9083016SGiridhar Malavali return -1; 1011a9083016SGiridhar Malavali timeout++; 1012a9083016SGiridhar Malavali } 1013a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 1014a9083016SGiridhar Malavali return 0; 1015a9083016SGiridhar Malavali } 1016a9083016SGiridhar Malavali 1017a9083016SGiridhar Malavali int 1018a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 1019a9083016SGiridhar Malavali { 1020a9083016SGiridhar Malavali long timeout = 0; 1021a9083016SGiridhar Malavali long done = 0 ; 1022a9083016SGiridhar Malavali 1023a9083016SGiridhar Malavali while (done == 0) { 1024a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 1025a9083016SGiridhar Malavali done &= 4; 1026a9083016SGiridhar Malavali timeout++; 1027a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 1028a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 1029a9083016SGiridhar Malavali "%s: Timeout reached waiting for rom busy", 1030a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 1031a9083016SGiridhar Malavali return -1; 1032a9083016SGiridhar Malavali } 1033a9083016SGiridhar Malavali } 1034a9083016SGiridhar Malavali return 0; 1035a9083016SGiridhar Malavali } 1036a9083016SGiridhar Malavali 1037a9083016SGiridhar Malavali int 1038a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 1039a9083016SGiridhar Malavali { 1040a9083016SGiridhar Malavali long timeout = 0; 1041a9083016SGiridhar Malavali long done = 0 ; 1042a9083016SGiridhar Malavali 1043a9083016SGiridhar Malavali while (done == 0) { 1044a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 1045a9083016SGiridhar Malavali done &= 2; 1046a9083016SGiridhar Malavali timeout++; 1047a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 1048a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 1049a9083016SGiridhar Malavali "%s: Timeout reached waiting for rom done", 1050a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 1051a9083016SGiridhar Malavali return -1; 1052a9083016SGiridhar Malavali } 1053a9083016SGiridhar Malavali } 1054a9083016SGiridhar Malavali return 0; 1055a9083016SGiridhar Malavali } 1056a9083016SGiridhar Malavali 1057a9083016SGiridhar Malavali int 1058a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 1059a9083016SGiridhar Malavali { 1060a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 1061a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 1062a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1063a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 1064a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1065a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1066a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1067a9083016SGiridhar Malavali "%s: Error waiting for rom done\n", 1068a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 1069a9083016SGiridhar Malavali return -1; 1070a9083016SGiridhar Malavali } 1071a9083016SGiridhar Malavali /* Reset abyte_cnt and dummy_byte_cnt */ 1072a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 1073a9083016SGiridhar Malavali udelay(10); 1074a9083016SGiridhar Malavali cond_resched(); 1075a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1076a9083016SGiridhar Malavali *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1077a9083016SGiridhar Malavali return 0; 1078a9083016SGiridhar Malavali } 1079a9083016SGiridhar Malavali 1080a9083016SGiridhar Malavali int 1081a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 1082a9083016SGiridhar Malavali { 1083a9083016SGiridhar Malavali int ret, loops = 0; 1084a9083016SGiridhar Malavali 1085a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1086a9083016SGiridhar Malavali udelay(100); 1087a9083016SGiridhar Malavali schedule(); 1088a9083016SGiridhar Malavali loops++; 1089a9083016SGiridhar Malavali } 1090a9083016SGiridhar Malavali if (loops >= 50000) { 1091a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1092a9083016SGiridhar Malavali "%s: qla82xx_rom_lock failed\n", 1093a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 1094a9083016SGiridhar Malavali return -1; 1095a9083016SGiridhar Malavali } 1096a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 1097a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1098a9083016SGiridhar Malavali return ret; 1099a9083016SGiridhar Malavali } 1100a9083016SGiridhar Malavali 1101a9083016SGiridhar Malavali int 1102a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 1103a9083016SGiridhar Malavali { 1104a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 1105a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1106a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1107a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1108a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1109a9083016SGiridhar Malavali return -1; 1110a9083016SGiridhar Malavali } 1111a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1112a9083016SGiridhar Malavali return 0; 1113a9083016SGiridhar Malavali } 1114a9083016SGiridhar Malavali 1115a9083016SGiridhar Malavali int 1116a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 1117a9083016SGiridhar Malavali { 1118a9083016SGiridhar Malavali long timeout = 0; 1119a9083016SGiridhar Malavali uint32_t done = 1 ; 1120a9083016SGiridhar Malavali uint32_t val; 1121a9083016SGiridhar Malavali int ret = 0; 1122a9083016SGiridhar Malavali 1123a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1124a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 1125a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 1126a9083016SGiridhar Malavali done = val & 1; 1127a9083016SGiridhar Malavali timeout++; 1128a9083016SGiridhar Malavali udelay(10); 1129a9083016SGiridhar Malavali cond_resched(); 1130a9083016SGiridhar Malavali if (timeout >= 50000) { 1131a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1132a9083016SGiridhar Malavali "Timeout reached waiting for write finish"); 1133a9083016SGiridhar Malavali return -1; 1134a9083016SGiridhar Malavali } 1135a9083016SGiridhar Malavali } 1136a9083016SGiridhar Malavali return ret; 1137a9083016SGiridhar Malavali } 1138a9083016SGiridhar Malavali 1139a9083016SGiridhar Malavali int 1140a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1141a9083016SGiridhar Malavali { 1142a9083016SGiridhar Malavali uint32_t val; 1143a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1144a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1145a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1146a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1147a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1148a9083016SGiridhar Malavali return -1; 1149a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1150a9083016SGiridhar Malavali return -1; 1151a9083016SGiridhar Malavali if ((val & 2) != 2) 1152a9083016SGiridhar Malavali return -1; 1153a9083016SGiridhar Malavali return 0; 1154a9083016SGiridhar Malavali } 1155a9083016SGiridhar Malavali 1156a9083016SGiridhar Malavali int 1157a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1158a9083016SGiridhar Malavali { 1159a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1160a9083016SGiridhar Malavali return -1; 1161a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1162a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1163a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1164a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1165a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1166a9083016SGiridhar Malavali return -1; 1167a9083016SGiridhar Malavali } 1168a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1169a9083016SGiridhar Malavali } 1170a9083016SGiridhar Malavali 1171a9083016SGiridhar Malavali int 1172a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1173a9083016SGiridhar Malavali { 1174a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1175a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1176a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1177a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1178a9083016SGiridhar Malavali return -1; 1179a9083016SGiridhar Malavali } 1180a9083016SGiridhar Malavali return 0; 1181a9083016SGiridhar Malavali } 1182a9083016SGiridhar Malavali 1183a9083016SGiridhar Malavali int 1184a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1185a9083016SGiridhar Malavali { 1186a9083016SGiridhar Malavali int loops = 0; 1187a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1188a9083016SGiridhar Malavali udelay(100); 1189a9083016SGiridhar Malavali cond_resched(); 1190a9083016SGiridhar Malavali loops++; 1191a9083016SGiridhar Malavali } 1192a9083016SGiridhar Malavali if (loops >= 50000) { 1193a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1194a9083016SGiridhar Malavali return -1; 1195a9083016SGiridhar Malavali } 1196a9083016SGiridhar Malavali return 0;; 1197a9083016SGiridhar Malavali } 1198a9083016SGiridhar Malavali 1199a9083016SGiridhar Malavali int 1200a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1201a9083016SGiridhar Malavali uint32_t data) 1202a9083016SGiridhar Malavali { 1203a9083016SGiridhar Malavali int ret = 0; 1204a9083016SGiridhar Malavali 1205a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1206a9083016SGiridhar Malavali if (ret < 0) { 1207a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 1208a9083016SGiridhar Malavali return ret; 1209a9083016SGiridhar Malavali } 1210a9083016SGiridhar Malavali 1211a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1212a9083016SGiridhar Malavali goto done_write; 1213a9083016SGiridhar Malavali 1214a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1215a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1216a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1217a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1218a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1219a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1220a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1221a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1222a9083016SGiridhar Malavali ret = -1; 1223a9083016SGiridhar Malavali goto done_write; 1224a9083016SGiridhar Malavali } 1225a9083016SGiridhar Malavali 1226a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1227a9083016SGiridhar Malavali 1228a9083016SGiridhar Malavali done_write: 1229a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1230a9083016SGiridhar Malavali return ret; 1231a9083016SGiridhar Malavali } 1232a9083016SGiridhar Malavali 1233a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1234a9083016SGiridhar Malavali * to put the ISP into operational state 1235a9083016SGiridhar Malavali */ 1236a9083016SGiridhar Malavali int qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1237a9083016SGiridhar Malavali { 1238a9083016SGiridhar Malavali int addr, val; 1239a9083016SGiridhar Malavali int i ; 1240a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1241a9083016SGiridhar Malavali unsigned long off; 1242a9083016SGiridhar Malavali unsigned offset, n; 1243a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1244a9083016SGiridhar Malavali 1245a9083016SGiridhar Malavali struct crb_addr_pair { 1246a9083016SGiridhar Malavali long addr; 1247a9083016SGiridhar Malavali long data; 1248a9083016SGiridhar Malavali }; 1249a9083016SGiridhar Malavali 1250a9083016SGiridhar Malavali /* Halt all the indiviual PEGs and other blocks of the ISP */ 1251a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1252a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1253a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1254a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1255a9083016SGiridhar Malavali else 1256a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1257a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1258a9083016SGiridhar Malavali 1259a9083016SGiridhar Malavali /* Read the signature value from the flash. 1260a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1261a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1262a9083016SGiridhar Malavali * that present in CRB initialize sequence 1263a9083016SGiridhar Malavali */ 1264a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1265a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1266a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1267a9083016SGiridhar Malavali "[ERROR] Reading crb_init area: n: %08x\n", n); 1268a9083016SGiridhar Malavali return -1; 1269a9083016SGiridhar Malavali } 1270a9083016SGiridhar Malavali 1271a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 1272a9083016SGiridhar Malavali * Number of enteries = upper 16 bits 1273a9083016SGiridhar Malavali */ 1274a9083016SGiridhar Malavali offset = n & 0xffffU; 1275a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1276a9083016SGiridhar Malavali 1277a9083016SGiridhar Malavali /* number of addr/value pair should not exceed 1024 enteries */ 1278a9083016SGiridhar Malavali if (n >= 1024) { 1279a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1280a9083016SGiridhar Malavali "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1281a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME, __func__, n); 1282a9083016SGiridhar Malavali return -1; 1283a9083016SGiridhar Malavali } 1284a9083016SGiridhar Malavali 1285a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1286a9083016SGiridhar Malavali "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n); 1287a9083016SGiridhar Malavali 1288a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1289a9083016SGiridhar Malavali if (buf == NULL) { 1290a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1291a9083016SGiridhar Malavali "%s: [ERROR] Unable to malloc memory.\n", 1292a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 1293a9083016SGiridhar Malavali return -1; 1294a9083016SGiridhar Malavali } 1295a9083016SGiridhar Malavali 1296a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1297a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1298a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1299a9083016SGiridhar Malavali kfree(buf); 1300a9083016SGiridhar Malavali return -1; 1301a9083016SGiridhar Malavali } 1302a9083016SGiridhar Malavali 1303a9083016SGiridhar Malavali buf[i].addr = addr; 1304a9083016SGiridhar Malavali buf[i].data = val; 1305a9083016SGiridhar Malavali } 1306a9083016SGiridhar Malavali 1307a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1308a9083016SGiridhar Malavali /* Translate internal CRB initialization 1309a9083016SGiridhar Malavali * address to PCI bus address 1310a9083016SGiridhar Malavali */ 1311a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1312a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1313a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1314a9083016SGiridhar Malavali * some of them are skipped 1315a9083016SGiridhar Malavali */ 1316a9083016SGiridhar Malavali 1317a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1318a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1319a9083016SGiridhar Malavali continue; 1320a9083016SGiridhar Malavali 1321a9083016SGiridhar Malavali /* do not reset PCI */ 1322a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1323a9083016SGiridhar Malavali continue; 1324a9083016SGiridhar Malavali 1325a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1326a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1327a9083016SGiridhar Malavali continue; 1328a9083016SGiridhar Malavali 1329a9083016SGiridhar Malavali /* skip the function enable register */ 1330a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1331a9083016SGiridhar Malavali continue; 1332a9083016SGiridhar Malavali 1333a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1334a9083016SGiridhar Malavali continue; 1335a9083016SGiridhar Malavali 1336a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1337a9083016SGiridhar Malavali continue; 1338a9083016SGiridhar Malavali 1339a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1340a9083016SGiridhar Malavali continue; 1341a9083016SGiridhar Malavali 1342a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 1343a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1344a9083016SGiridhar Malavali "%s: [ERROR] Unknown addr: 0x%08lx\n", 1345a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME, buf[i].addr); 1346a9083016SGiridhar Malavali continue; 1347a9083016SGiridhar Malavali } 1348a9083016SGiridhar Malavali 1349a9083016SGiridhar Malavali if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) { 1350a9083016SGiridhar Malavali if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) 1351a9083016SGiridhar Malavali buf[i].data = 0x1020; 1352a9083016SGiridhar Malavali } 1353a9083016SGiridhar Malavali 1354a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1355a9083016SGiridhar Malavali 1356a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1357a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1358a9083016SGiridhar Malavali */ 1359a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1360a9083016SGiridhar Malavali msleep(1000); 1361a9083016SGiridhar Malavali 1362a9083016SGiridhar Malavali /* ISP requires millisec delay between 1363a9083016SGiridhar Malavali * successive CRB register updation 1364a9083016SGiridhar Malavali */ 1365a9083016SGiridhar Malavali msleep(1); 1366a9083016SGiridhar Malavali } 1367a9083016SGiridhar Malavali 1368a9083016SGiridhar Malavali kfree(buf); 1369a9083016SGiridhar Malavali 1370a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1371a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1372a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1373a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1374a9083016SGiridhar Malavali 1375a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1376a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1377a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1378a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1379a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1380a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1381a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1382a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1383a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1384a9083016SGiridhar Malavali return 0; 1385a9083016SGiridhar Malavali } 1386a9083016SGiridhar Malavali 1387a9083016SGiridhar Malavali int qla82xx_check_for_bad_spd(struct qla_hw_data *ha) 1388a9083016SGiridhar Malavali { 1389a9083016SGiridhar Malavali u32 val = 0; 1390a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS); 1391a9083016SGiridhar Malavali val &= QLA82XX_BOOT_LOADER_MN_ISSUE; 1392a9083016SGiridhar Malavali if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) { 1393a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1394a9083016SGiridhar Malavali "Memory DIMM SPD not programmed. " 1395a9083016SGiridhar Malavali " Assumed valid.\n"); 1396a9083016SGiridhar Malavali return 1; 1397a9083016SGiridhar Malavali } else if (val) { 1398a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1399a9083016SGiridhar Malavali "Memory DIMM type incorrect.Info:%08X.\n", val); 1400a9083016SGiridhar Malavali return 2; 1401a9083016SGiridhar Malavali } 1402a9083016SGiridhar Malavali return 0; 1403a9083016SGiridhar Malavali } 1404a9083016SGiridhar Malavali 1405a9083016SGiridhar Malavali int 1406a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1407a9083016SGiridhar Malavali { 1408a9083016SGiridhar Malavali int i; 1409a9083016SGiridhar Malavali long size = 0; 14109c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14119c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1412a9083016SGiridhar Malavali u64 data; 1413a9083016SGiridhar Malavali u32 high, low; 1414a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1415a9083016SGiridhar Malavali 1416a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1417a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1418a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1419a9083016SGiridhar Malavali return -1; 1420a9083016SGiridhar Malavali } 1421a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1422a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1423a9083016SGiridhar Malavali flashaddr += 8; 1424a9083016SGiridhar Malavali memaddr += 8; 1425a9083016SGiridhar Malavali 1426a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1427a9083016SGiridhar Malavali msleep(1); 1428a9083016SGiridhar Malavali } 1429a9083016SGiridhar Malavali udelay(100); 1430a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1431a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1432a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1433a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1434a9083016SGiridhar Malavali } else { 1435a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); 1436a9083016SGiridhar Malavali } 1437a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1438a9083016SGiridhar Malavali return 0; 1439a9083016SGiridhar Malavali } 1440a9083016SGiridhar Malavali 1441a9083016SGiridhar Malavali int 1442a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1443a9083016SGiridhar Malavali u64 off, void *data, int size) 1444a9083016SGiridhar Malavali { 1445a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1446a9083016SGiridhar Malavali int shift_amount; 1447a9083016SGiridhar Malavali uint32_t temp; 1448a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1449a9083016SGiridhar Malavali 1450a9083016SGiridhar Malavali /* 1451a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1452a9083016SGiridhar Malavali */ 1453a9083016SGiridhar Malavali 1454a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1455a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1456a9083016SGiridhar Malavali else { 1457a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1458a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1459a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1460a9083016SGiridhar Malavali off, data, size); 1461a9083016SGiridhar Malavali } 1462a9083016SGiridhar Malavali 1463a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1464a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1465a9083016SGiridhar Malavali off0[0] = off & 0xf; 1466a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1467a9083016SGiridhar Malavali shift_amount = 4; 1468a9083016SGiridhar Malavali } else { 1469a9083016SGiridhar Malavali off8 = off & 0xfffffff8; 1470a9083016SGiridhar Malavali off0[0] = off & 0x7; 1471a9083016SGiridhar Malavali sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); 1472a9083016SGiridhar Malavali shift_amount = 4; 1473a9083016SGiridhar Malavali } 1474a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1475a9083016SGiridhar Malavali off0[1] = 0; 1476a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1477a9083016SGiridhar Malavali 1478a9083016SGiridhar Malavali /* 1479a9083016SGiridhar Malavali * don't lock here - write_wx gets the lock if each time 1480a9083016SGiridhar Malavali * write_lock_irqsave(&adapter->adapter_lock, flags); 1481a9083016SGiridhar Malavali * netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1482a9083016SGiridhar Malavali */ 1483a9083016SGiridhar Malavali 1484a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1485a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1486a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1487a9083016SGiridhar Malavali temp = 0; 1488a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1489a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1490a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1491a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1492a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1493a9083016SGiridhar Malavali 1494a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1495a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1496a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1497a9083016SGiridhar Malavali break; 1498a9083016SGiridhar Malavali } 1499a9083016SGiridhar Malavali 1500a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1501a9083016SGiridhar Malavali if (printk_ratelimit()) 1502a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 1503a9083016SGiridhar Malavali "failed to read through agent\n"); 1504a9083016SGiridhar Malavali break; 1505a9083016SGiridhar Malavali } 1506a9083016SGiridhar Malavali 1507a9083016SGiridhar Malavali start = off0[i] >> 2; 1508a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1509a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1510a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1511a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1512a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1513a9083016SGiridhar Malavali } 1514a9083016SGiridhar Malavali } 1515a9083016SGiridhar Malavali 1516a9083016SGiridhar Malavali /* 1517a9083016SGiridhar Malavali * netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1518a9083016SGiridhar Malavali * write_unlock_irqrestore(&adapter->adapter_lock, flags); 1519a9083016SGiridhar Malavali */ 1520a9083016SGiridhar Malavali 1521a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1522a9083016SGiridhar Malavali return -1; 1523a9083016SGiridhar Malavali 1524a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1525a9083016SGiridhar Malavali val = word[0]; 1526a9083016SGiridhar Malavali } else { 1527a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1528a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1529a9083016SGiridhar Malavali } 1530a9083016SGiridhar Malavali 1531a9083016SGiridhar Malavali switch (size) { 1532a9083016SGiridhar Malavali case 1: 1533a9083016SGiridhar Malavali *(uint8_t *)data = val; 1534a9083016SGiridhar Malavali break; 1535a9083016SGiridhar Malavali case 2: 1536a9083016SGiridhar Malavali *(uint16_t *)data = val; 1537a9083016SGiridhar Malavali break; 1538a9083016SGiridhar Malavali case 4: 1539a9083016SGiridhar Malavali *(uint32_t *)data = val; 1540a9083016SGiridhar Malavali break; 1541a9083016SGiridhar Malavali case 8: 1542a9083016SGiridhar Malavali *(uint64_t *)data = val; 1543a9083016SGiridhar Malavali break; 1544a9083016SGiridhar Malavali } 1545a9083016SGiridhar Malavali return 0; 1546a9083016SGiridhar Malavali } 1547a9083016SGiridhar Malavali 1548a9083016SGiridhar Malavali int 1549a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1550a9083016SGiridhar Malavali u64 off, void *data, int size) 1551a9083016SGiridhar Malavali { 1552a9083016SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 1553a9083016SGiridhar Malavali int scale, shift_amount, p3p, startword; 1554a9083016SGiridhar Malavali uint32_t temp; 1555a9083016SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1556a9083016SGiridhar Malavali 1557a9083016SGiridhar Malavali /* 1558a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1559a9083016SGiridhar Malavali */ 1560a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1561a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1562a9083016SGiridhar Malavali else { 1563a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1564a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1565a9083016SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 1566a9083016SGiridhar Malavali off, data, size); 1567a9083016SGiridhar Malavali } 1568a9083016SGiridhar Malavali 1569a9083016SGiridhar Malavali off0 = off & 0x7; 1570a9083016SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1571a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1572a9083016SGiridhar Malavali 1573a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1574a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1575a9083016SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 1576a9083016SGiridhar Malavali shift_amount = 4; 1577a9083016SGiridhar Malavali scale = 2; 1578a9083016SGiridhar Malavali p3p = 1; 1579a9083016SGiridhar Malavali startword = (off & 0xf)/8; 1580a9083016SGiridhar Malavali } else { 1581a9083016SGiridhar Malavali off8 = off & 0xfffffff8; 1582a9083016SGiridhar Malavali loop = ((off0 + size - 1) >> 3) + 1; 1583a9083016SGiridhar Malavali shift_amount = 3; 1584a9083016SGiridhar Malavali scale = 1; 1585a9083016SGiridhar Malavali p3p = 0; 1586a9083016SGiridhar Malavali startword = 0; 1587a9083016SGiridhar Malavali } 1588a9083016SGiridhar Malavali 1589a9083016SGiridhar Malavali if (p3p || (size != 8) || (off0 != 0)) { 1590a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1591a9083016SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 1592a9083016SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 1593a9083016SGiridhar Malavali return -1; 1594a9083016SGiridhar Malavali } 1595a9083016SGiridhar Malavali } 1596a9083016SGiridhar Malavali 1597a9083016SGiridhar Malavali switch (size) { 1598a9083016SGiridhar Malavali case 1: 1599a9083016SGiridhar Malavali tmpw = *((uint8_t *)data); 1600a9083016SGiridhar Malavali break; 1601a9083016SGiridhar Malavali case 2: 1602a9083016SGiridhar Malavali tmpw = *((uint16_t *)data); 1603a9083016SGiridhar Malavali break; 1604a9083016SGiridhar Malavali case 4: 1605a9083016SGiridhar Malavali tmpw = *((uint32_t *)data); 1606a9083016SGiridhar Malavali break; 1607a9083016SGiridhar Malavali case 8: 1608a9083016SGiridhar Malavali default: 1609a9083016SGiridhar Malavali tmpw = *((uint64_t *)data); 1610a9083016SGiridhar Malavali break; 1611a9083016SGiridhar Malavali } 1612a9083016SGiridhar Malavali 1613a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1614a9083016SGiridhar Malavali if (sz[0] == 8) { 1615a9083016SGiridhar Malavali word[startword] = tmpw; 1616a9083016SGiridhar Malavali } else { 1617a9083016SGiridhar Malavali word[startword] &= 1618a9083016SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1619a9083016SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 1620a9083016SGiridhar Malavali } 1621a9083016SGiridhar Malavali if (sz[1] != 0) { 1622a9083016SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1623a9083016SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 1624a9083016SGiridhar Malavali } 1625a9083016SGiridhar Malavali } else { 1626a9083016SGiridhar Malavali word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1627a9083016SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 1628a9083016SGiridhar Malavali 1629a9083016SGiridhar Malavali if (loop == 2) { 1630a9083016SGiridhar Malavali word[1] &= ~(~0ULL << (sz[1] * 8)); 1631a9083016SGiridhar Malavali word[1] |= tmpw >> (sz[0] * 8); 1632a9083016SGiridhar Malavali } 1633a9083016SGiridhar Malavali } 1634a9083016SGiridhar Malavali 1635a9083016SGiridhar Malavali /* 1636a9083016SGiridhar Malavali * don't lock here - write_wx gets the lock if each time 1637a9083016SGiridhar Malavali * write_lock_irqsave(&adapter->adapter_lock, flags); 1638a9083016SGiridhar Malavali * netxen_nic_pci_change_crbwindow_128M(adapter, 0); 1639a9083016SGiridhar Malavali */ 1640a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1641a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1642a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1643a9083016SGiridhar Malavali temp = 0; 1644a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1645a9083016SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 1646a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1647a9083016SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 1648a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1649a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 1650a9083016SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 1651a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 1652a9083016SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1653a9083016SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1654a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 1655a9083016SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1656a9083016SGiridhar Malavali } 1657a9083016SGiridhar Malavali 1658a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1659a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1660a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1661a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1662a9083016SGiridhar Malavali 1663a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1664a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1665a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1666a9083016SGiridhar Malavali break; 1667a9083016SGiridhar Malavali } 1668a9083016SGiridhar Malavali 1669a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1670a9083016SGiridhar Malavali if (printk_ratelimit()) 1671a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 1672a9083016SGiridhar Malavali "failed to write through agent\n"); 1673a9083016SGiridhar Malavali ret = -1; 1674a9083016SGiridhar Malavali break; 1675a9083016SGiridhar Malavali } 1676a9083016SGiridhar Malavali } 1677a9083016SGiridhar Malavali 1678a9083016SGiridhar Malavali return ret; 1679a9083016SGiridhar Malavali } 1680a9083016SGiridhar Malavali 16819c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 16829c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 16839c2b2975SHarish Zunjarrao { 16849c2b2975SHarish Zunjarrao uint32_t i; 16859c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 16869c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 16879c2b2975SHarish Zunjarrao __le32 offset; 16889c2b2975SHarish Zunjarrao __le32 tab_type; 16899c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 16909c2b2975SHarish Zunjarrao 16919c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 16929c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 16939c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 16949c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 16959c2b2975SHarish Zunjarrao 16969c2b2975SHarish Zunjarrao if (tab_type == section) 16979c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 16989c2b2975SHarish Zunjarrao } 16999c2b2975SHarish Zunjarrao 17009c2b2975SHarish Zunjarrao return NULL; 17019c2b2975SHarish Zunjarrao } 17029c2b2975SHarish Zunjarrao 17039c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 17049c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 17059c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 17069c2b2975SHarish Zunjarrao { 17079c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 17089c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 17099c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 17109c2b2975SHarish Zunjarrao __le32 offset; 17119c2b2975SHarish Zunjarrao 17129c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 17139c2b2975SHarish Zunjarrao if (!tab_desc) 17149c2b2975SHarish Zunjarrao return NULL; 17159c2b2975SHarish Zunjarrao 17169c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 17179c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 17189c2b2975SHarish Zunjarrao 17199c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 17209c2b2975SHarish Zunjarrao } 17219c2b2975SHarish Zunjarrao 17229c2b2975SHarish Zunjarrao static u8 * 17239c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 17249c2b2975SHarish Zunjarrao { 17259c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 17269c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 17279c2b2975SHarish Zunjarrao 17289c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 17299c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 17309c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 17319c2b2975SHarish Zunjarrao if (uri_desc) 17329c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 17339c2b2975SHarish Zunjarrao } 17349c2b2975SHarish Zunjarrao 17359c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 17369c2b2975SHarish Zunjarrao } 17379c2b2975SHarish Zunjarrao 17389c2b2975SHarish Zunjarrao static __le32 17399c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 17409c2b2975SHarish Zunjarrao { 17419c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 17429c2b2975SHarish Zunjarrao 17439c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 17449c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 17459c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 17469c2b2975SHarish Zunjarrao if (uri_desc) 17479c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 17489c2b2975SHarish Zunjarrao } 17499c2b2975SHarish Zunjarrao 17509c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 17519c2b2975SHarish Zunjarrao } 17529c2b2975SHarish Zunjarrao 17539c2b2975SHarish Zunjarrao static u8 * 17549c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 17559c2b2975SHarish Zunjarrao { 17569c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 17579c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 17589c2b2975SHarish Zunjarrao 17599c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 17609c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 17619c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 17629c2b2975SHarish Zunjarrao if (uri_desc) 17639c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 17649c2b2975SHarish Zunjarrao } 17659c2b2975SHarish Zunjarrao 17669c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 17679c2b2975SHarish Zunjarrao } 17689c2b2975SHarish Zunjarrao 1769a9083016SGiridhar Malavali /* PCI related functions */ 1770a9083016SGiridhar Malavali char * 1771a9083016SGiridhar Malavali qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1772a9083016SGiridhar Malavali { 1773a9083016SGiridhar Malavali int pcie_reg; 1774a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1775a9083016SGiridhar Malavali char lwstr[6]; 1776a9083016SGiridhar Malavali uint16_t lnk; 1777a9083016SGiridhar Malavali 1778a9083016SGiridhar Malavali pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1779a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1780a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 1781a9083016SGiridhar Malavali 1782a9083016SGiridhar Malavali strcpy(str, "PCIe ("); 1783a9083016SGiridhar Malavali strcat(str, "2.5Gb/s "); 1784a9083016SGiridhar Malavali snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1785a9083016SGiridhar Malavali strcat(str, lwstr); 1786a9083016SGiridhar Malavali return str; 1787a9083016SGiridhar Malavali } 1788a9083016SGiridhar Malavali 1789a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1790a9083016SGiridhar Malavali { 1791a9083016SGiridhar Malavali unsigned long val = 0; 1792a9083016SGiridhar Malavali u32 control; 1793a9083016SGiridhar Malavali 1794a9083016SGiridhar Malavali switch (region) { 1795a9083016SGiridhar Malavali case 0: 1796a9083016SGiridhar Malavali val = 0; 1797a9083016SGiridhar Malavali break; 1798a9083016SGiridhar Malavali case 1: 1799a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1800a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1801a9083016SGiridhar Malavali break; 1802a9083016SGiridhar Malavali } 1803a9083016SGiridhar Malavali return val; 1804a9083016SGiridhar Malavali } 1805a9083016SGiridhar Malavali 1806a9083016SGiridhar Malavali int qla82xx_pci_region_len(struct pci_dev *pdev, int region) 1807a9083016SGiridhar Malavali { 1808a9083016SGiridhar Malavali unsigned long val = 0; 1809a9083016SGiridhar Malavali u32 control; 1810a9083016SGiridhar Malavali switch (region) { 1811a9083016SGiridhar Malavali case 0: 1812a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1813a9083016SGiridhar Malavali val = control; 1814a9083016SGiridhar Malavali break; 1815a9083016SGiridhar Malavali case 1: 1816a9083016SGiridhar Malavali val = pci_resource_len(pdev, 0) - 1817a9083016SGiridhar Malavali qla82xx_pci_region_offset(pdev, 1); 1818a9083016SGiridhar Malavali break; 1819a9083016SGiridhar Malavali } 1820a9083016SGiridhar Malavali return val; 1821a9083016SGiridhar Malavali } 1822a9083016SGiridhar Malavali 1823a9083016SGiridhar Malavali int 1824a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1825a9083016SGiridhar Malavali { 1826a9083016SGiridhar Malavali uint32_t len = 0; 1827a9083016SGiridhar Malavali 1828a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1829a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1830a9083016SGiridhar Malavali "Failed to reserve selected regions (%s)\n", 1831a9083016SGiridhar Malavali pci_name(ha->pdev)); 1832a9083016SGiridhar Malavali goto iospace_error_exit; 1833a9083016SGiridhar Malavali } 1834a9083016SGiridhar Malavali 1835a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1836a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1837a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1838a9083016SGiridhar Malavali "region #0 not an MMIO resource (%s), aborting\n", 1839a9083016SGiridhar Malavali pci_name(ha->pdev)); 1840a9083016SGiridhar Malavali goto iospace_error_exit; 1841a9083016SGiridhar Malavali } 1842a9083016SGiridhar Malavali 1843a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1844a9083016SGiridhar Malavali ha->nx_pcibase = 1845a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1846a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 1847a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1848a9083016SGiridhar Malavali "cannot remap pcibase MMIO (%s), aborting\n", 1849a9083016SGiridhar Malavali pci_name(ha->pdev)); 1850a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1851a9083016SGiridhar Malavali goto iospace_error_exit; 1852a9083016SGiridhar Malavali } 1853a9083016SGiridhar Malavali 1854a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1855a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1856a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1857a9083016SGiridhar Malavali 1858a9083016SGiridhar Malavali if (!ql2xdbwr) { 1859a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1860a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1861a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1862a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 1863a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1864a9083016SGiridhar Malavali "cannot remap MMIO (%s), aborting\n", 1865a9083016SGiridhar Malavali pci_name(ha->pdev)); 1866a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1867a9083016SGiridhar Malavali goto iospace_error_exit; 1868a9083016SGiridhar Malavali } 1869a9083016SGiridhar Malavali 1870a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1871a9083016SGiridhar Malavali * door bell read and write pointer 1872a9083016SGiridhar Malavali */ 1873a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1874a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1875a9083016SGiridhar Malavali } else { 1876a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1877a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1878a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1879a9083016SGiridhar Malavali } 1880a9083016SGiridhar Malavali 1881a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1882a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 1883a9083016SGiridhar Malavali return 0; 1884a9083016SGiridhar Malavali 1885a9083016SGiridhar Malavali iospace_error_exit: 1886a9083016SGiridhar Malavali return -ENOMEM; 1887a9083016SGiridhar Malavali } 1888a9083016SGiridhar Malavali 1889a9083016SGiridhar Malavali /* GS related functions */ 1890a9083016SGiridhar Malavali 1891a9083016SGiridhar Malavali /* Initialization related functions */ 1892a9083016SGiridhar Malavali 1893a9083016SGiridhar Malavali /** 1894a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1895a9083016SGiridhar Malavali * @ha: HA context 1896a9083016SGiridhar Malavali * 1897a9083016SGiridhar Malavali * Returns 0 on success. 1898a9083016SGiridhar Malavali */ 1899a9083016SGiridhar Malavali int 1900a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1901a9083016SGiridhar Malavali { 1902a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1903a9083016SGiridhar Malavali int ret; 1904a9083016SGiridhar Malavali 1905a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1906a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1907a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 1908a9083016SGiridhar Malavali return 0; 1909a9083016SGiridhar Malavali } 1910a9083016SGiridhar Malavali 1911a9083016SGiridhar Malavali /** 1912a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1913a9083016SGiridhar Malavali * @ha: HA context 1914a9083016SGiridhar Malavali * 1915a9083016SGiridhar Malavali * Returns 0 on success. 1916a9083016SGiridhar Malavali */ 1917a9083016SGiridhar Malavali void 1918a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1919a9083016SGiridhar Malavali { 1920a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1921a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1922a9083016SGiridhar Malavali } 1923a9083016SGiridhar Malavali 1924a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1925a9083016SGiridhar Malavali { 1926a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1927a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1928a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1929a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1930a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1931a9083016SGiridhar Malavali 1932a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1933a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1934a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1935a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1936a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1937a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1938a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1939a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1940a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1941a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1942a9083016SGiridhar Malavali 1943a9083016SGiridhar Malavali icb->version = 1; 1944a9083016SGiridhar Malavali icb->frame_payload_size = 2112; 1945a9083016SGiridhar Malavali icb->execution_throttle = 8; 1946a9083016SGiridhar Malavali icb->exchange_count = 128; 1947a9083016SGiridhar Malavali icb->login_retry_count = 8; 1948a9083016SGiridhar Malavali 1949a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1950a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1951a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1952a9083016SGiridhar Malavali } 1953a9083016SGiridhar Malavali 1954f1af6208SGiridhar Malavali void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1955f1af6208SGiridhar Malavali { 1956f1af6208SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1957f1af6208SGiridhar Malavali vha->flags.online = 0; 1958f1af6208SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 1959f1af6208SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1960f1af6208SGiridhar Malavali } 1961f1af6208SGiridhar Malavali 1962a9083016SGiridhar Malavali int qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1963a9083016SGiridhar Malavali { 1964a9083016SGiridhar Malavali u64 *ptr64; 1965a9083016SGiridhar Malavali u32 i, flashaddr, size; 1966a9083016SGiridhar Malavali __le64 data; 1967a9083016SGiridhar Malavali 1968a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1969a9083016SGiridhar Malavali 19709c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1971a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1972a9083016SGiridhar Malavali 1973a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1974a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 19759c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 19769c2b2975SHarish Zunjarrao return -EIO; 1977a9083016SGiridhar Malavali flashaddr += 8; 1978a9083016SGiridhar Malavali } 1979a9083016SGiridhar Malavali 1980a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 19819c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 19829c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1983a9083016SGiridhar Malavali 1984a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1985a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1986a9083016SGiridhar Malavali 1987a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1988a9083016SGiridhar Malavali return -EIO; 1989a9083016SGiridhar Malavali flashaddr += 8; 1990a9083016SGiridhar Malavali } 19919c2b2975SHarish Zunjarrao udelay(100); 1992a9083016SGiridhar Malavali 1993a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1994a9083016SGiridhar Malavali * at a specified offset to indicate 1995a9083016SGiridhar Malavali * that all data is written and 1996a9083016SGiridhar Malavali * ready for firmware to initialize. 1997a9083016SGiridhar Malavali */ 19989c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1999a9083016SGiridhar Malavali 20009c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 2001a9083016SGiridhar Malavali if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { 2002a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 2003a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 2004a9083016SGiridhar Malavali } else 2005a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); 20069c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 20079c2b2975SHarish Zunjarrao return 0; 20089c2b2975SHarish Zunjarrao } 20099c2b2975SHarish Zunjarrao 20109c2b2975SHarish Zunjarrao static int 20119c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 20129c2b2975SHarish Zunjarrao { 20139c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 20149c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 20159c2b2975SHarish Zunjarrao uint32_t i; 20169c2b2975SHarish Zunjarrao __le32 entries; 20179c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 20189c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 20199c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 20209c2b2975SHarish Zunjarrao int mn_present = 0; 20219c2b2975SHarish Zunjarrao uint32_t flagbit; 20229c2b2975SHarish Zunjarrao 20239c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 20249c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 20259c2b2975SHarish Zunjarrao if (!ptab_desc) 20269c2b2975SHarish Zunjarrao return -1; 20279c2b2975SHarish Zunjarrao 20289c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 20299c2b2975SHarish Zunjarrao 20309c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 20319c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 20329c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 20339c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 20349c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 20359c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 20369c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 20379c2b2975SHarish Zunjarrao 20389c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 20399c2b2975SHarish Zunjarrao 20409c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 20419c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 20429c2b2975SHarish Zunjarrao return 0; 20439c2b2975SHarish Zunjarrao } 20449c2b2975SHarish Zunjarrao } 20459c2b2975SHarish Zunjarrao return -1; 20469c2b2975SHarish Zunjarrao } 20479c2b2975SHarish Zunjarrao 20489c2b2975SHarish Zunjarrao int 20499c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 20509c2b2975SHarish Zunjarrao { 20519c2b2975SHarish Zunjarrao __le32 val; 20529c2b2975SHarish Zunjarrao uint32_t min_size; 20539c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 20549c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 20559c2b2975SHarish Zunjarrao 20569c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 20579c2b2975SHarish Zunjarrao 20589c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 20599c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 20609c2b2975SHarish Zunjarrao return -EINVAL; 20619c2b2975SHarish Zunjarrao 20629c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 20639c2b2975SHarish Zunjarrao } else { 20649c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 20659c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 20669c2b2975SHarish Zunjarrao return -EINVAL; 20679c2b2975SHarish Zunjarrao 20689c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 20699c2b2975SHarish Zunjarrao } 20709c2b2975SHarish Zunjarrao 20719c2b2975SHarish Zunjarrao if (fw->size < min_size) 20729c2b2975SHarish Zunjarrao return -EINVAL; 2073a9083016SGiridhar Malavali return 0; 2074a9083016SGiridhar Malavali } 2075a9083016SGiridhar Malavali 2076a9083016SGiridhar Malavali int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 2077a9083016SGiridhar Malavali { 2078a9083016SGiridhar Malavali u32 val = 0; 2079a9083016SGiridhar Malavali int retries = 60; 2080a9083016SGiridhar Malavali 2081a9083016SGiridhar Malavali do { 2082a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 2083a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 2084a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 2085a9083016SGiridhar Malavali 2086a9083016SGiridhar Malavali switch (val) { 2087a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 2088a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 2089a9083016SGiridhar Malavali return QLA_SUCCESS; 2090a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 2091a9083016SGiridhar Malavali break; 2092a9083016SGiridhar Malavali default: 2093a9083016SGiridhar Malavali break; 2094a9083016SGiridhar Malavali } 2095a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2096a9083016SGiridhar Malavali "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n", 2097a9083016SGiridhar Malavali val, retries); 2098a9083016SGiridhar Malavali 2099a9083016SGiridhar Malavali msleep(500); 2100a9083016SGiridhar Malavali 2101a9083016SGiridhar Malavali } while (--retries); 2102a9083016SGiridhar Malavali 2103a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2104a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 2105a9083016SGiridhar Malavali 2106a9083016SGiridhar Malavali qla82xx_check_for_bad_spd(ha); 2107a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 2108a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 2109a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 2110a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 2111a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2112a9083016SGiridhar Malavali } 2113a9083016SGiridhar Malavali 2114a9083016SGiridhar Malavali int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 2115a9083016SGiridhar Malavali { 2116a9083016SGiridhar Malavali u32 val = 0; 2117a9083016SGiridhar Malavali int retries = 60; 2118a9083016SGiridhar Malavali 2119a9083016SGiridhar Malavali do { 2120a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 2121a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 2122a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 2123a9083016SGiridhar Malavali 2124a9083016SGiridhar Malavali switch (val) { 2125a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 2126a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 2127a9083016SGiridhar Malavali return QLA_SUCCESS; 2128a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 2129a9083016SGiridhar Malavali break; 2130a9083016SGiridhar Malavali default: 2131a9083016SGiridhar Malavali break; 2132a9083016SGiridhar Malavali } 2133a9083016SGiridhar Malavali 2134a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2135a9083016SGiridhar Malavali "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n", 2136a9083016SGiridhar Malavali val, retries); 2137a9083016SGiridhar Malavali 2138a9083016SGiridhar Malavali msleep(500); 2139a9083016SGiridhar Malavali 2140a9083016SGiridhar Malavali } while (--retries); 2141a9083016SGiridhar Malavali 2142a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2143a9083016SGiridhar Malavali "Rcv Peg initialization failed: 0x%x.\n", val); 2144a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 2145a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 2146a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 2147a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2148a9083016SGiridhar Malavali } 2149a9083016SGiridhar Malavali 2150a9083016SGiridhar Malavali /* ISR related functions */ 2151a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_mask_enable[8] = { 2152a9083016SGiridhar Malavali ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 2153a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 2154a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 2155a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 2156a9083016SGiridhar Malavali }; 2157a9083016SGiridhar Malavali 2158a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_status[8] = { 2159a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 2160a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 2161a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 2162a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 2163a9083016SGiridhar Malavali }; 2164a9083016SGiridhar Malavali 2165a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 2166a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 2167a9083016SGiridhar Malavali 2168a9083016SGiridhar Malavali /* 2169a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 2170a9083016SGiridhar Malavali * @ha: SCSI driver HA context 2171a9083016SGiridhar Malavali * @mb0: Mailbox0 register 2172a9083016SGiridhar Malavali */ 2173a9083016SGiridhar Malavali void 2174a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2175a9083016SGiridhar Malavali { 2176a9083016SGiridhar Malavali uint16_t cnt; 2177a9083016SGiridhar Malavali uint16_t __iomem *wptr; 2178a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2179a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2180a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2181a9083016SGiridhar Malavali 2182a9083016SGiridhar Malavali /* Load return mailbox registers. */ 2183a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 2184a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 2185a9083016SGiridhar Malavali 2186a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2187a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2188a9083016SGiridhar Malavali wptr++; 2189a9083016SGiridhar Malavali } 2190a9083016SGiridhar Malavali 2191a9083016SGiridhar Malavali if (ha->mcp) { 2192a9083016SGiridhar Malavali DEBUG3_11(printk(KERN_INFO "%s(%ld): " 2193a9083016SGiridhar Malavali "Got mailbox completion. cmd=%x.\n", 2194a9083016SGiridhar Malavali __func__, vha->host_no, ha->mcp->mb[0])); 2195a9083016SGiridhar Malavali } else { 2196a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2197a9083016SGiridhar Malavali "%s(%ld): MBX pointer ERROR!\n", 2198a9083016SGiridhar Malavali __func__, vha->host_no); 2199a9083016SGiridhar Malavali } 2200a9083016SGiridhar Malavali } 2201a9083016SGiridhar Malavali 2202a9083016SGiridhar Malavali /* 2203a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2204a9083016SGiridhar Malavali * @irq: 2205a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2206a9083016SGiridhar Malavali * @regs: 2207a9083016SGiridhar Malavali * 2208a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2209a9083016SGiridhar Malavali * 2210a9083016SGiridhar Malavali * Returns handled flag. 2211a9083016SGiridhar Malavali */ 2212a9083016SGiridhar Malavali irqreturn_t 2213a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2214a9083016SGiridhar Malavali { 2215a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2216a9083016SGiridhar Malavali struct qla_hw_data *ha; 2217a9083016SGiridhar Malavali struct rsp_que *rsp; 2218a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2219a9083016SGiridhar Malavali int status = 0, status1 = 0; 2220a9083016SGiridhar Malavali unsigned long flags; 2221a9083016SGiridhar Malavali unsigned long iter; 2222a9083016SGiridhar Malavali uint32_t stat; 2223a9083016SGiridhar Malavali uint16_t mb[4]; 2224a9083016SGiridhar Malavali 2225a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2226a9083016SGiridhar Malavali if (!rsp) { 2227a9083016SGiridhar Malavali printk(KERN_INFO 2228a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2229a9083016SGiridhar Malavali return IRQ_NONE; 2230a9083016SGiridhar Malavali } 2231a9083016SGiridhar Malavali ha = rsp->hw; 2232a9083016SGiridhar Malavali 2233a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2234a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2235a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2236a9083016SGiridhar Malavali return IRQ_NONE; 2237a9083016SGiridhar Malavali 2238a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2239a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2240a9083016SGiridhar Malavali return IRQ_NONE; 2241a9083016SGiridhar Malavali } 2242a9083016SGiridhar Malavali 2243a9083016SGiridhar Malavali /* clear the interrupt */ 2244a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2245a9083016SGiridhar Malavali 2246a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2247a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2248a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2249a9083016SGiridhar Malavali 2250a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2251a9083016SGiridhar Malavali 2252a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2253a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2254a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2255a9083016SGiridhar Malavali 2256a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2257a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2258f1af6208SGiridhar Malavali if ((stat & HSRX_RISC_INT) == 0) 2259a9083016SGiridhar Malavali break; 2260a9083016SGiridhar Malavali 2261a9083016SGiridhar Malavali switch (stat & 0xff) { 2262a9083016SGiridhar Malavali case 0x1: 2263a9083016SGiridhar Malavali case 0x2: 2264a9083016SGiridhar Malavali case 0x10: 2265a9083016SGiridhar Malavali case 0x11: 2266a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2267a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2268a9083016SGiridhar Malavali break; 2269a9083016SGiridhar Malavali case 0x12: 2270a9083016SGiridhar Malavali mb[0] = MSW(stat); 2271a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2272a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2273a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2274a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2275a9083016SGiridhar Malavali break; 2276a9083016SGiridhar Malavali case 0x13: 2277a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2278a9083016SGiridhar Malavali break; 2279a9083016SGiridhar Malavali default: 2280a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): " 2281a9083016SGiridhar Malavali " Unrecognized interrupt type (%d).\n", 2282a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2283a9083016SGiridhar Malavali break; 2284a9083016SGiridhar Malavali } 2285a9083016SGiridhar Malavali } 2286a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2287a9083016SGiridhar Malavali } 2288a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2289a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2290a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2291a9083016SGiridhar Malavali 2292a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2293a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 2294a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2295a9083016SGiridhar Malavali "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2296a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2297a9083016SGiridhar Malavali #endif 2298a9083016SGiridhar Malavali 2299a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2300a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2301a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2302a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2303a9083016SGiridhar Malavali } 2304a9083016SGiridhar Malavali return IRQ_HANDLED; 2305a9083016SGiridhar Malavali } 2306a9083016SGiridhar Malavali 2307a9083016SGiridhar Malavali irqreturn_t 2308a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2309a9083016SGiridhar Malavali { 2310a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2311a9083016SGiridhar Malavali struct qla_hw_data *ha; 2312a9083016SGiridhar Malavali struct rsp_que *rsp; 2313a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2314a9083016SGiridhar Malavali int status = 0; 2315a9083016SGiridhar Malavali unsigned long flags; 2316a9083016SGiridhar Malavali uint32_t stat; 2317a9083016SGiridhar Malavali uint16_t mb[4]; 2318a9083016SGiridhar Malavali 2319a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2320a9083016SGiridhar Malavali if (!rsp) { 2321a9083016SGiridhar Malavali printk(KERN_INFO 2322a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2323a9083016SGiridhar Malavali return IRQ_NONE; 2324a9083016SGiridhar Malavali } 2325a9083016SGiridhar Malavali ha = rsp->hw; 2326a9083016SGiridhar Malavali 2327a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2328a9083016SGiridhar Malavali 2329a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2330a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2331a9083016SGiridhar Malavali do { 2332a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2333a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2334f1af6208SGiridhar Malavali if ((stat & HSRX_RISC_INT) == 0) 2335a9083016SGiridhar Malavali break; 2336a9083016SGiridhar Malavali 2337a9083016SGiridhar Malavali switch (stat & 0xff) { 2338a9083016SGiridhar Malavali case 0x1: 2339a9083016SGiridhar Malavali case 0x2: 2340a9083016SGiridhar Malavali case 0x10: 2341a9083016SGiridhar Malavali case 0x11: 2342a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2343a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2344a9083016SGiridhar Malavali break; 2345a9083016SGiridhar Malavali case 0x12: 2346a9083016SGiridhar Malavali mb[0] = MSW(stat); 2347a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2348a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2349a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2350a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2351a9083016SGiridhar Malavali break; 2352a9083016SGiridhar Malavali case 0x13: 2353a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2354a9083016SGiridhar Malavali break; 2355a9083016SGiridhar Malavali default: 2356a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): " 2357a9083016SGiridhar Malavali " Unrecognized interrupt type (%d).\n", 2358a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2359a9083016SGiridhar Malavali break; 2360a9083016SGiridhar Malavali } 2361a9083016SGiridhar Malavali } 2362a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2363a9083016SGiridhar Malavali } while (0); 2364a9083016SGiridhar Malavali 2365a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2366a9083016SGiridhar Malavali 2367a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2368a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 2369a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2370a9083016SGiridhar Malavali "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2371a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2372a9083016SGiridhar Malavali #endif 2373a9083016SGiridhar Malavali 2374a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2375a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2376a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2377a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2378a9083016SGiridhar Malavali } 2379a9083016SGiridhar Malavali return IRQ_HANDLED; 2380a9083016SGiridhar Malavali } 2381a9083016SGiridhar Malavali 2382a9083016SGiridhar Malavali irqreturn_t 2383a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2384a9083016SGiridhar Malavali { 2385a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2386a9083016SGiridhar Malavali struct qla_hw_data *ha; 2387a9083016SGiridhar Malavali struct rsp_que *rsp; 2388a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2389a9083016SGiridhar Malavali 2390a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2391a9083016SGiridhar Malavali if (!rsp) { 2392a9083016SGiridhar Malavali printk(KERN_INFO 2393a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2394a9083016SGiridhar Malavali return IRQ_NONE; 2395a9083016SGiridhar Malavali } 2396a9083016SGiridhar Malavali 2397a9083016SGiridhar Malavali ha = rsp->hw; 2398a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2399a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2400a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2401a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2402a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2403a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2404a9083016SGiridhar Malavali return IRQ_HANDLED; 2405a9083016SGiridhar Malavali } 2406a9083016SGiridhar Malavali 2407a9083016SGiridhar Malavali void 2408a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2409a9083016SGiridhar Malavali { 2410a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2411a9083016SGiridhar Malavali struct qla_hw_data *ha; 2412a9083016SGiridhar Malavali struct rsp_que *rsp; 2413a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2414a9083016SGiridhar Malavali int status = 0; 2415a9083016SGiridhar Malavali uint32_t stat; 2416a9083016SGiridhar Malavali uint16_t mb[4]; 2417a9083016SGiridhar Malavali unsigned long flags; 2418a9083016SGiridhar Malavali 2419a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2420a9083016SGiridhar Malavali if (!rsp) { 2421a9083016SGiridhar Malavali printk(KERN_INFO 2422a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2423a9083016SGiridhar Malavali return; 2424a9083016SGiridhar Malavali } 2425a9083016SGiridhar Malavali ha = rsp->hw; 2426a9083016SGiridhar Malavali 2427a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2428a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2429a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2430a9083016SGiridhar Malavali 2431a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2432a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2433a9083016SGiridhar Malavali switch (stat & 0xff) { 2434a9083016SGiridhar Malavali case 0x1: 2435a9083016SGiridhar Malavali case 0x2: 2436a9083016SGiridhar Malavali case 0x10: 2437a9083016SGiridhar Malavali case 0x11: 2438a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2439a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2440a9083016SGiridhar Malavali break; 2441a9083016SGiridhar Malavali case 0x12: 2442a9083016SGiridhar Malavali mb[0] = MSW(stat); 2443a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2444a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2445a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2446a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2447a9083016SGiridhar Malavali break; 2448a9083016SGiridhar Malavali case 0x13: 2449a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2450a9083016SGiridhar Malavali break; 2451a9083016SGiridhar Malavali default: 2452a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): Unrecognized interrupt type " 2453a9083016SGiridhar Malavali "(%d).\n", 2454a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2455a9083016SGiridhar Malavali break; 2456a9083016SGiridhar Malavali } 2457a9083016SGiridhar Malavali } 2458a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2459a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2460a9083016SGiridhar Malavali } 2461a9083016SGiridhar Malavali 2462a9083016SGiridhar Malavali void 2463a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2464a9083016SGiridhar Malavali { 2465a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2466a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2467a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2468a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2469a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2470a9083016SGiridhar Malavali ha->interrupts_on = 1; 2471a9083016SGiridhar Malavali } 2472a9083016SGiridhar Malavali 2473a9083016SGiridhar Malavali void 2474a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2475a9083016SGiridhar Malavali { 2476a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2477a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2478a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2479a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2480a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2481a9083016SGiridhar Malavali ha->interrupts_on = 0; 2482a9083016SGiridhar Malavali } 2483a9083016SGiridhar Malavali 2484a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2485a9083016SGiridhar Malavali { 2486a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2487a9083016SGiridhar Malavali 2488a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2489a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2490a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2491a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2492a9083016SGiridhar Malavali ha->curr_window = 255; 2493a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2494a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2495a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2496a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2497a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2498a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2499a9083016SGiridhar Malavali } 2500a9083016SGiridhar Malavali 2501a9083016SGiridhar Malavali static inline void 2502a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2503a9083016SGiridhar Malavali { 2504a9083016SGiridhar Malavali uint32_t drv_active; 2505a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2506a9083016SGiridhar Malavali 2507a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2508a9083016SGiridhar Malavali 2509a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2510a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 2511a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0); 2512a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2513a9083016SGiridhar Malavali } 2514a9083016SGiridhar Malavali drv_active |= (1 << (ha->portnum * 4)); 2515a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2516a9083016SGiridhar Malavali } 2517a9083016SGiridhar Malavali 2518a9083016SGiridhar Malavali inline void 2519a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2520a9083016SGiridhar Malavali { 2521a9083016SGiridhar Malavali uint32_t drv_active; 2522a9083016SGiridhar Malavali 2523a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2524a9083016SGiridhar Malavali drv_active &= ~(1 << (ha->portnum * 4)); 2525a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2526a9083016SGiridhar Malavali } 2527a9083016SGiridhar Malavali 2528a9083016SGiridhar Malavali static inline int 2529a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2530a9083016SGiridhar Malavali { 2531a9083016SGiridhar Malavali uint32_t drv_state; 2532a9083016SGiridhar Malavali int rval; 2533a9083016SGiridhar Malavali 2534a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2535a9083016SGiridhar Malavali rval = drv_state & (1 << (ha->portnum * 4)); 2536a9083016SGiridhar Malavali return rval; 2537a9083016SGiridhar Malavali } 2538a9083016SGiridhar Malavali 2539a9083016SGiridhar Malavali static inline void 2540a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2541a9083016SGiridhar Malavali { 2542a9083016SGiridhar Malavali uint32_t drv_state; 2543a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2544a9083016SGiridhar Malavali 2545a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2546a9083016SGiridhar Malavali 2547a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2548a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 2549a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 2550a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2551a9083016SGiridhar Malavali } 2552a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2553a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2554a9083016SGiridhar Malavali "%s(%ld):drv_state = 0x%x\n", 2555a9083016SGiridhar Malavali __func__, vha->host_no, drv_state); 2556a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2557a9083016SGiridhar Malavali } 2558a9083016SGiridhar Malavali 2559a9083016SGiridhar Malavali static inline void 2560a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2561a9083016SGiridhar Malavali { 2562a9083016SGiridhar Malavali uint32_t drv_state; 2563a9083016SGiridhar Malavali 2564a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2565a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2566a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2567a9083016SGiridhar Malavali } 2568a9083016SGiridhar Malavali 2569a9083016SGiridhar Malavali static inline void 2570a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2571a9083016SGiridhar Malavali { 2572a9083016SGiridhar Malavali uint32_t qsnt_state; 2573a9083016SGiridhar Malavali 2574a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2575a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2576a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2577a9083016SGiridhar Malavali } 2578a9083016SGiridhar Malavali 2579a9083016SGiridhar Malavali int qla82xx_load_fw(scsi_qla_host_t *vha) 2580a9083016SGiridhar Malavali { 2581a9083016SGiridhar Malavali int rst; 2582a9083016SGiridhar Malavali struct fw_blob *blob; 2583a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2584a9083016SGiridhar Malavali 2585a9083016SGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 2586a9083016SGiridhar Malavali * of 0 before resetting the hardware 2587a9083016SGiridhar Malavali */ 2588a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2589a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2590a9083016SGiridhar Malavali 2591a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2592a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2593a9083016SGiridhar Malavali "%s: Error during CRB Initialization\n", __func__); 2594a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2595a9083016SGiridhar Malavali } 2596a9083016SGiridhar Malavali udelay(500); 2597a9083016SGiridhar Malavali 2598a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2599a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2600a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2601a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2602a9083016SGiridhar Malavali 2603a9083016SGiridhar Malavali /* 2604a9083016SGiridhar Malavali * FW Load priority: 2605a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2606a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2607a9083016SGiridhar Malavali */ 2608a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2609a9083016SGiridhar Malavali goto try_blob_fw; 2610a9083016SGiridhar Malavali 2611a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2612a9083016SGiridhar Malavali "Attempting to load firmware from flash\n"); 2613a9083016SGiridhar Malavali 2614a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2615a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2616a9083016SGiridhar Malavali "Firmware loaded successfully from flash\n"); 2617a9083016SGiridhar Malavali return QLA_SUCCESS; 2618a9083016SGiridhar Malavali } 2619a9083016SGiridhar Malavali try_blob_fw: 2620a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2621a9083016SGiridhar Malavali "Attempting to load firmware from blob\n"); 2622a9083016SGiridhar Malavali 2623a9083016SGiridhar Malavali /* Load firmware blob. */ 2624a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2625a9083016SGiridhar Malavali if (!blob) { 2626a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2627a9083016SGiridhar Malavali "Firmware image not present.\n"); 2628a9083016SGiridhar Malavali goto fw_load_failed; 2629a9083016SGiridhar Malavali } 2630a9083016SGiridhar Malavali 26319c2b2975SHarish Zunjarrao /* Validating firmware blob */ 26329c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 26339c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 26349c2b2975SHarish Zunjarrao /* Fallback to URI format */ 26359c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 26369c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 26379c2b2975SHarish Zunjarrao qla_printk(KERN_ERR, ha, 26389c2b2975SHarish Zunjarrao "No valid firmware image found!!!"); 26399c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 26409c2b2975SHarish Zunjarrao } 26419c2b2975SHarish Zunjarrao } 26429c2b2975SHarish Zunjarrao 2643a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2644a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2645a9083016SGiridhar Malavali "%s: Firmware loaded successfully " 2646a9083016SGiridhar Malavali " from binary blob\n", __func__); 2647a9083016SGiridhar Malavali return QLA_SUCCESS; 2648a9083016SGiridhar Malavali } else { 2649a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2650a9083016SGiridhar Malavali "Firmware load failed from binary blob\n"); 2651a9083016SGiridhar Malavali blob->fw = NULL; 2652a9083016SGiridhar Malavali blob = NULL; 2653a9083016SGiridhar Malavali goto fw_load_failed; 2654a9083016SGiridhar Malavali } 2655a9083016SGiridhar Malavali return QLA_SUCCESS; 2656a9083016SGiridhar Malavali 2657a9083016SGiridhar Malavali fw_load_failed: 2658a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2659a9083016SGiridhar Malavali } 2660a9083016SGiridhar Malavali 2661a9083016SGiridhar Malavali static int 2662a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2663a9083016SGiridhar Malavali { 2664a9083016SGiridhar Malavali int pcie_cap; 2665a9083016SGiridhar Malavali uint16_t lnk; 2666a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2667a9083016SGiridhar Malavali 2668a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 2669a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 2670a9083016SGiridhar Malavali 2671a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2672a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2673a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2674a9083016SGiridhar Malavali 2675a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2676a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2677a9083016SGiridhar Malavali "%s: Error trying to start fw!\n", __func__); 2678a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2679a9083016SGiridhar Malavali } 2680a9083016SGiridhar Malavali 2681a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2682a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2683a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2684a9083016SGiridhar Malavali "%s: Error during card handshake!\n", __func__); 2685a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2686a9083016SGiridhar Malavali } 2687a9083016SGiridhar Malavali 2688a9083016SGiridhar Malavali /* Negotiated Link width */ 2689a9083016SGiridhar Malavali pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2690a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2691a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2692a9083016SGiridhar Malavali 2693a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2694a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2695a9083016SGiridhar Malavali } 2696a9083016SGiridhar Malavali 2697a9083016SGiridhar Malavali static inline int 2698a9083016SGiridhar Malavali qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2699a9083016SGiridhar Malavali uint16_t tot_dsds) 2700a9083016SGiridhar Malavali { 2701a9083016SGiridhar Malavali uint32_t *cur_dsd = NULL; 2702a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2703a9083016SGiridhar Malavali struct qla_hw_data *ha; 2704a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2705a9083016SGiridhar Malavali struct scatterlist *cur_seg; 2706a9083016SGiridhar Malavali uint32_t *dsd_seg; 2707a9083016SGiridhar Malavali void *next_dsd; 2708a9083016SGiridhar Malavali uint8_t avail_dsds; 2709a9083016SGiridhar Malavali uint8_t first_iocb = 1; 2710a9083016SGiridhar Malavali uint32_t dsd_list_len; 2711a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2712a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2713a9083016SGiridhar Malavali 2714a9083016SGiridhar Malavali cmd = sp->cmd; 2715a9083016SGiridhar Malavali 2716a9083016SGiridhar Malavali /* Update entry type to indicate Command Type 3 IOCB */ 2717a9083016SGiridhar Malavali *((uint32_t *)(&cmd_pkt->entry_type)) = 2718a9083016SGiridhar Malavali __constant_cpu_to_le32(COMMAND_TYPE_6); 2719a9083016SGiridhar Malavali 2720a9083016SGiridhar Malavali /* No data transfer */ 2721a9083016SGiridhar Malavali if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2722a9083016SGiridhar Malavali cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2723a9083016SGiridhar Malavali return 0; 2724a9083016SGiridhar Malavali } 2725a9083016SGiridhar Malavali 2726a9083016SGiridhar Malavali vha = sp->fcport->vha; 2727a9083016SGiridhar Malavali ha = vha->hw; 2728a9083016SGiridhar Malavali 2729a9083016SGiridhar Malavali /* Set transfer direction */ 2730a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2731a9083016SGiridhar Malavali cmd_pkt->control_flags = 2732a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_WRITE_DATA); 2733a9083016SGiridhar Malavali ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2734a9083016SGiridhar Malavali } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2735a9083016SGiridhar Malavali cmd_pkt->control_flags = 2736a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_READ_DATA); 2737a9083016SGiridhar Malavali ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2738a9083016SGiridhar Malavali } 2739a9083016SGiridhar Malavali 2740a9083016SGiridhar Malavali cur_seg = scsi_sglist(cmd); 2741a9083016SGiridhar Malavali ctx = sp->ctx; 2742a9083016SGiridhar Malavali 2743a9083016SGiridhar Malavali while (tot_dsds) { 2744a9083016SGiridhar Malavali avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2745a9083016SGiridhar Malavali QLA_DSDS_PER_IOCB : tot_dsds; 2746a9083016SGiridhar Malavali tot_dsds -= avail_dsds; 2747a9083016SGiridhar Malavali dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2748a9083016SGiridhar Malavali 2749a9083016SGiridhar Malavali dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2750a9083016SGiridhar Malavali struct dsd_dma, list); 2751a9083016SGiridhar Malavali next_dsd = dsd_ptr->dsd_addr; 2752a9083016SGiridhar Malavali list_del(&dsd_ptr->list); 2753a9083016SGiridhar Malavali ha->gbl_dsd_avail--; 2754a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2755a9083016SGiridhar Malavali ctx->dsd_use_cnt++; 2756a9083016SGiridhar Malavali ha->gbl_dsd_inuse++; 2757a9083016SGiridhar Malavali 2758a9083016SGiridhar Malavali if (first_iocb) { 2759a9083016SGiridhar Malavali first_iocb = 0; 2760a9083016SGiridhar Malavali dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2761a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2762a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2763a9083016SGiridhar Malavali *dsd_seg++ = dsd_list_len; 2764a9083016SGiridhar Malavali } else { 2765a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2766a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2767a9083016SGiridhar Malavali *cur_dsd++ = dsd_list_len; 2768a9083016SGiridhar Malavali } 2769a9083016SGiridhar Malavali cur_dsd = (uint32_t *)next_dsd; 2770a9083016SGiridhar Malavali while (avail_dsds) { 2771a9083016SGiridhar Malavali dma_addr_t sle_dma; 2772a9083016SGiridhar Malavali 2773a9083016SGiridhar Malavali sle_dma = sg_dma_address(cur_seg); 2774a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2775a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2776a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2777a9083016SGiridhar Malavali cur_seg++; 2778a9083016SGiridhar Malavali avail_dsds--; 2779a9083016SGiridhar Malavali } 2780a9083016SGiridhar Malavali } 2781a9083016SGiridhar Malavali 2782a9083016SGiridhar Malavali /* Null termination */ 2783a9083016SGiridhar Malavali *cur_dsd++ = 0; 2784a9083016SGiridhar Malavali *cur_dsd++ = 0; 2785a9083016SGiridhar Malavali *cur_dsd++ = 0; 2786a9083016SGiridhar Malavali cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2787a9083016SGiridhar Malavali return 0; 2788a9083016SGiridhar Malavali } 2789a9083016SGiridhar Malavali 2790a9083016SGiridhar Malavali /* 2791a9083016SGiridhar Malavali * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2792a9083016SGiridhar Malavali * for Command Type 6. 2793a9083016SGiridhar Malavali * 2794a9083016SGiridhar Malavali * @dsds: number of data segment decriptors needed 2795a9083016SGiridhar Malavali * 2796a9083016SGiridhar Malavali * Returns the number of dsd list needed to store @dsds. 2797a9083016SGiridhar Malavali */ 2798a9083016SGiridhar Malavali inline uint16_t 2799a9083016SGiridhar Malavali qla82xx_calc_dsd_lists(uint16_t dsds) 2800a9083016SGiridhar Malavali { 2801a9083016SGiridhar Malavali uint16_t dsd_lists = 0; 2802a9083016SGiridhar Malavali 2803a9083016SGiridhar Malavali dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2804a9083016SGiridhar Malavali if (dsds % QLA_DSDS_PER_IOCB) 2805a9083016SGiridhar Malavali dsd_lists++; 2806a9083016SGiridhar Malavali return dsd_lists; 2807a9083016SGiridhar Malavali } 2808a9083016SGiridhar Malavali 2809a9083016SGiridhar Malavali /* 2810a9083016SGiridhar Malavali * qla82xx_start_scsi() - Send a SCSI command to the ISP 2811a9083016SGiridhar Malavali * @sp: command to send to the ISP 2812a9083016SGiridhar Malavali * 2813a9083016SGiridhar Malavali * Returns non-zero if a failure occured, else zero. 2814a9083016SGiridhar Malavali */ 2815a9083016SGiridhar Malavali int 2816a9083016SGiridhar Malavali qla82xx_start_scsi(srb_t *sp) 2817a9083016SGiridhar Malavali { 2818a9083016SGiridhar Malavali int ret, nseg; 2819a9083016SGiridhar Malavali unsigned long flags; 2820a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2821a9083016SGiridhar Malavali uint32_t *clr_ptr; 2822a9083016SGiridhar Malavali uint32_t index; 2823a9083016SGiridhar Malavali uint32_t handle; 2824a9083016SGiridhar Malavali uint16_t cnt; 2825a9083016SGiridhar Malavali uint16_t req_cnt; 2826a9083016SGiridhar Malavali uint16_t tot_dsds; 2827a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2828a9083016SGiridhar Malavali uint32_t dbval; 2829a9083016SGiridhar Malavali uint32_t *fcp_dl; 2830a9083016SGiridhar Malavali uint8_t additional_cdb_len; 2831a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2832a9083016SGiridhar Malavali struct scsi_qla_host *vha = sp->fcport->vha; 2833a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2834a9083016SGiridhar Malavali struct req_que *req = NULL; 2835a9083016SGiridhar Malavali struct rsp_que *rsp = NULL; 2836a9083016SGiridhar Malavali 2837a9083016SGiridhar Malavali /* Setup device pointers. */ 2838a9083016SGiridhar Malavali ret = 0; 2839a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2840a9083016SGiridhar Malavali cmd = sp->cmd; 2841a9083016SGiridhar Malavali req = vha->req; 2842a9083016SGiridhar Malavali rsp = ha->rsp_q_map[0]; 2843a9083016SGiridhar Malavali 2844a9083016SGiridhar Malavali /* So we know we haven't pci_map'ed anything yet */ 2845a9083016SGiridhar Malavali tot_dsds = 0; 2846a9083016SGiridhar Malavali 2847a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2848a9083016SGiridhar Malavali 2849a9083016SGiridhar Malavali /* Send marker if required */ 2850a9083016SGiridhar Malavali if (vha->marker_needed != 0) { 2851a9083016SGiridhar Malavali if (qla2x00_marker(vha, req, 2852a9083016SGiridhar Malavali rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) 2853a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2854a9083016SGiridhar Malavali vha->marker_needed = 0; 2855a9083016SGiridhar Malavali } 2856a9083016SGiridhar Malavali 2857a9083016SGiridhar Malavali /* Acquire ring specific lock */ 2858a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2859a9083016SGiridhar Malavali 2860a9083016SGiridhar Malavali /* Check for room in outstanding command list. */ 2861a9083016SGiridhar Malavali handle = req->current_outstanding_cmd; 2862a9083016SGiridhar Malavali for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2863a9083016SGiridhar Malavali handle++; 2864a9083016SGiridhar Malavali if (handle == MAX_OUTSTANDING_COMMANDS) 2865a9083016SGiridhar Malavali handle = 1; 2866a9083016SGiridhar Malavali if (!req->outstanding_cmds[handle]) 2867a9083016SGiridhar Malavali break; 2868a9083016SGiridhar Malavali } 2869a9083016SGiridhar Malavali if (index == MAX_OUTSTANDING_COMMANDS) 2870a9083016SGiridhar Malavali goto queuing_error; 2871a9083016SGiridhar Malavali 2872a9083016SGiridhar Malavali /* Map the sg table so we have an accurate count of sg entries needed */ 2873a9083016SGiridhar Malavali if (scsi_sg_count(cmd)) { 2874a9083016SGiridhar Malavali nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2875a9083016SGiridhar Malavali scsi_sg_count(cmd), cmd->sc_data_direction); 2876a9083016SGiridhar Malavali if (unlikely(!nseg)) 2877a9083016SGiridhar Malavali goto queuing_error; 2878a9083016SGiridhar Malavali } else 2879a9083016SGiridhar Malavali nseg = 0; 2880a9083016SGiridhar Malavali 2881a9083016SGiridhar Malavali tot_dsds = nseg; 2882a9083016SGiridhar Malavali 2883a9083016SGiridhar Malavali if (tot_dsds > ql2xshiftctondsd) { 2884a9083016SGiridhar Malavali struct cmd_type_6 *cmd_pkt; 2885a9083016SGiridhar Malavali uint16_t more_dsd_lists = 0; 2886a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2887a9083016SGiridhar Malavali uint16_t i; 2888a9083016SGiridhar Malavali 2889a9083016SGiridhar Malavali more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 2890a9083016SGiridhar Malavali if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) 2891a9083016SGiridhar Malavali goto queuing_error; 2892a9083016SGiridhar Malavali 2893a9083016SGiridhar Malavali if (more_dsd_lists <= ha->gbl_dsd_avail) 2894a9083016SGiridhar Malavali goto sufficient_dsds; 2895a9083016SGiridhar Malavali else 2896a9083016SGiridhar Malavali more_dsd_lists -= ha->gbl_dsd_avail; 2897a9083016SGiridhar Malavali 2898a9083016SGiridhar Malavali for (i = 0; i < more_dsd_lists; i++) { 2899a9083016SGiridhar Malavali dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 2900a9083016SGiridhar Malavali if (!dsd_ptr) 2901a9083016SGiridhar Malavali goto queuing_error; 2902a9083016SGiridhar Malavali 2903a9083016SGiridhar Malavali dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2904a9083016SGiridhar Malavali GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2905a9083016SGiridhar Malavali if (!dsd_ptr->dsd_addr) { 2906a9083016SGiridhar Malavali kfree(dsd_ptr); 2907a9083016SGiridhar Malavali goto queuing_error; 2908a9083016SGiridhar Malavali } 2909a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2910a9083016SGiridhar Malavali ha->gbl_dsd_avail++; 2911a9083016SGiridhar Malavali } 2912a9083016SGiridhar Malavali 2913a9083016SGiridhar Malavali sufficient_dsds: 2914a9083016SGiridhar Malavali req_cnt = 1; 2915a9083016SGiridhar Malavali 2916a9083016SGiridhar Malavali ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2917a9083016SGiridhar Malavali if (!sp->ctx) { 2918a9083016SGiridhar Malavali DEBUG(printk(KERN_INFO 2919a9083016SGiridhar Malavali "%s(%ld): failed to allocate" 2920a9083016SGiridhar Malavali " ctx.\n", __func__, vha->host_no)); 2921a9083016SGiridhar Malavali goto queuing_error; 2922a9083016SGiridhar Malavali } 2923a9083016SGiridhar Malavali memset(ctx, 0, sizeof(struct ct6_dsd)); 2924a9083016SGiridhar Malavali ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2925a9083016SGiridhar Malavali GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2926a9083016SGiridhar Malavali if (!ctx->fcp_cmnd) { 2927a9083016SGiridhar Malavali DEBUG2_3(printk("%s(%ld): failed to allocate" 2928a9083016SGiridhar Malavali " fcp_cmnd.\n", __func__, vha->host_no)); 2929a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2930a9083016SGiridhar Malavali } 2931a9083016SGiridhar Malavali 2932a9083016SGiridhar Malavali /* Initialize the DSD list and dma handle */ 2933a9083016SGiridhar Malavali INIT_LIST_HEAD(&ctx->dsd_list); 2934a9083016SGiridhar Malavali ctx->dsd_use_cnt = 0; 2935a9083016SGiridhar Malavali 2936a9083016SGiridhar Malavali if (cmd->cmd_len > 16) { 2937a9083016SGiridhar Malavali additional_cdb_len = cmd->cmd_len - 16; 2938a9083016SGiridhar Malavali if ((cmd->cmd_len % 4) != 0) { 2939a9083016SGiridhar Malavali /* SCSI command bigger than 16 bytes must be 2940a9083016SGiridhar Malavali * multiple of 4 2941a9083016SGiridhar Malavali */ 2942a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2943a9083016SGiridhar Malavali } 2944a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2945a9083016SGiridhar Malavali } else { 2946a9083016SGiridhar Malavali additional_cdb_len = 0; 2947a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + 16 + 4; 2948a9083016SGiridhar Malavali } 2949a9083016SGiridhar Malavali 2950a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2951a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2952a9083016SGiridhar Malavali 2953a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2954a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2955a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2956a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2957a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2958a9083016SGiridhar Malavali 2959a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2960a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2961a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2962a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2963a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2964a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2965a9083016SGiridhar Malavali 2966a9083016SGiridhar Malavali /* Build IOCB segments */ 2967a9083016SGiridhar Malavali if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2968a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2969a9083016SGiridhar Malavali 2970a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2971a9083016SGiridhar Malavali 2972a9083016SGiridhar Malavali /* build FCP_CMND IU */ 2973a9083016SGiridhar Malavali memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 2974a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 2975a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 2976a9083016SGiridhar Malavali 2977a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) 2978a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 1; 2979a9083016SGiridhar Malavali else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 2980a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 2; 2981a9083016SGiridhar Malavali 2982a9083016SGiridhar Malavali memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2983a9083016SGiridhar Malavali 2984a9083016SGiridhar Malavali fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2985a9083016SGiridhar Malavali additional_cdb_len); 2986a9083016SGiridhar Malavali *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2987a9083016SGiridhar Malavali 2988a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2989a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[0] = 2990a9083016SGiridhar Malavali cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2991a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[1] = 2992a9083016SGiridhar Malavali cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2993a9083016SGiridhar Malavali 2994a9083016SGiridhar Malavali sp->flags |= SRB_FCP_CMND_DMA_VALID; 2995a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2996a9083016SGiridhar Malavali /* Set total data segment count. */ 2997a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2998a9083016SGiridhar Malavali /* Specify response queue number where 2999a9083016SGiridhar Malavali * completion should happen 3000a9083016SGiridhar Malavali */ 3001a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 3002a9083016SGiridhar Malavali } else { 3003a9083016SGiridhar Malavali struct cmd_type_7 *cmd_pkt; 3004a9083016SGiridhar Malavali req_cnt = qla24xx_calc_iocbs(tot_dsds); 3005a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 3006a9083016SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 3007a9083016SGiridhar Malavali ®->req_q_out[0]); 3008a9083016SGiridhar Malavali if (req->ring_index < cnt) 3009a9083016SGiridhar Malavali req->cnt = cnt - req->ring_index; 3010a9083016SGiridhar Malavali else 3011a9083016SGiridhar Malavali req->cnt = req->length - 3012a9083016SGiridhar Malavali (req->ring_index - cnt); 3013a9083016SGiridhar Malavali } 3014a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 3015a9083016SGiridhar Malavali goto queuing_error; 3016a9083016SGiridhar Malavali 3017a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 3018a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 3019a9083016SGiridhar Malavali 3020a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 3021a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 3022a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 3023a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 3024a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 3025a9083016SGiridhar Malavali 3026a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 3027a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 3028a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 3029a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 3030a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 3031a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 3032a9083016SGiridhar Malavali 3033a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 3034a9083016SGiridhar Malavali host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 3035a9083016SGiridhar Malavali sizeof(cmd_pkt->lun)); 3036a9083016SGiridhar Malavali 3037a9083016SGiridhar Malavali /* Load SCSI command packet. */ 3038a9083016SGiridhar Malavali memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 3039a9083016SGiridhar Malavali host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 3040a9083016SGiridhar Malavali 3041a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 3042a9083016SGiridhar Malavali 3043a9083016SGiridhar Malavali /* Build IOCB segments */ 3044a9083016SGiridhar Malavali qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 3045a9083016SGiridhar Malavali 3046a9083016SGiridhar Malavali /* Set total data segment count. */ 3047a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 3048a9083016SGiridhar Malavali /* Specify response queue number where 3049a9083016SGiridhar Malavali * completion should happen. 3050a9083016SGiridhar Malavali */ 3051a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 3052a9083016SGiridhar Malavali 3053a9083016SGiridhar Malavali } 3054a9083016SGiridhar Malavali /* Build command packet. */ 3055a9083016SGiridhar Malavali req->current_outstanding_cmd = handle; 3056a9083016SGiridhar Malavali req->outstanding_cmds[handle] = sp; 3057a9083016SGiridhar Malavali sp->handle = handle; 3058a9083016SGiridhar Malavali sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 3059a9083016SGiridhar Malavali req->cnt -= req_cnt; 3060a9083016SGiridhar Malavali wmb(); 3061a9083016SGiridhar Malavali 3062a9083016SGiridhar Malavali /* Adjust ring index. */ 3063a9083016SGiridhar Malavali req->ring_index++; 3064a9083016SGiridhar Malavali if (req->ring_index == req->length) { 3065a9083016SGiridhar Malavali req->ring_index = 0; 3066a9083016SGiridhar Malavali req->ring_ptr = req->ring; 3067a9083016SGiridhar Malavali } else 3068a9083016SGiridhar Malavali req->ring_ptr++; 3069a9083016SGiridhar Malavali 3070a9083016SGiridhar Malavali sp->flags |= SRB_DMA_VALID; 3071a9083016SGiridhar Malavali 3072a9083016SGiridhar Malavali /* Set chip new ring index. */ 3073a9083016SGiridhar Malavali /* write, read and verify logic */ 3074a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 3075a9083016SGiridhar Malavali if (ql2xdbwr) 3076a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 3077a9083016SGiridhar Malavali else { 3078a9083016SGiridhar Malavali WRT_REG_DWORD( 3079a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 3080a9083016SGiridhar Malavali dbval); 3081a9083016SGiridhar Malavali wmb(); 3082a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 3083a9083016SGiridhar Malavali WRT_REG_DWORD( 3084a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 3085a9083016SGiridhar Malavali dbval); 3086a9083016SGiridhar Malavali wmb(); 3087a9083016SGiridhar Malavali } 3088a9083016SGiridhar Malavali } 3089a9083016SGiridhar Malavali 3090a9083016SGiridhar Malavali /* Manage unprocessed RIO/ZIO commands in response queue. */ 3091a9083016SGiridhar Malavali if (vha->flags.process_response_queue && 3092a9083016SGiridhar Malavali rsp->ring_ptr->signature != RESPONSE_PROCESSED) 3093a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 3094a9083016SGiridhar Malavali 3095a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 3096a9083016SGiridhar Malavali return QLA_SUCCESS; 3097a9083016SGiridhar Malavali 3098a9083016SGiridhar Malavali queuing_error_fcp_cmnd: 3099a9083016SGiridhar Malavali dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 3100a9083016SGiridhar Malavali queuing_error: 3101a9083016SGiridhar Malavali if (tot_dsds) 3102a9083016SGiridhar Malavali scsi_dma_unmap(cmd); 3103a9083016SGiridhar Malavali 3104a9083016SGiridhar Malavali if (sp->ctx) { 3105a9083016SGiridhar Malavali mempool_free(sp->ctx, ha->ctx_mempool); 3106a9083016SGiridhar Malavali sp->ctx = NULL; 3107a9083016SGiridhar Malavali } 3108a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 3109a9083016SGiridhar Malavali 3110a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3111a9083016SGiridhar Malavali } 3112a9083016SGiridhar Malavali 3113a9083016SGiridhar Malavali uint32_t * 3114a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 3115a9083016SGiridhar Malavali uint32_t length) 3116a9083016SGiridhar Malavali { 3117a9083016SGiridhar Malavali uint32_t i; 3118a9083016SGiridhar Malavali uint32_t val; 3119a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3120a9083016SGiridhar Malavali 3121a9083016SGiridhar Malavali /* Dword reads to flash. */ 3122a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 3123a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 3124a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3125a9083016SGiridhar Malavali "Do ROM fast read failed\n"); 3126a9083016SGiridhar Malavali goto done_read; 3127a9083016SGiridhar Malavali } 3128a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 3129a9083016SGiridhar Malavali } 3130a9083016SGiridhar Malavali done_read: 3131a9083016SGiridhar Malavali return dwptr; 3132a9083016SGiridhar Malavali } 3133a9083016SGiridhar Malavali 3134a9083016SGiridhar Malavali int 3135a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 3136a9083016SGiridhar Malavali { 3137a9083016SGiridhar Malavali int ret; 3138a9083016SGiridhar Malavali uint32_t val; 3139a9083016SGiridhar Malavali 3140a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3141a9083016SGiridhar Malavali if (ret < 0) { 3142a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3143a9083016SGiridhar Malavali return ret; 3144a9083016SGiridhar Malavali } 3145a9083016SGiridhar Malavali 3146a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3147a9083016SGiridhar Malavali if (ret < 0) 3148a9083016SGiridhar Malavali goto done_unprotect; 3149a9083016SGiridhar Malavali 3150a9083016SGiridhar Malavali val &= ~(0x7 << 2); 3151a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3152a9083016SGiridhar Malavali if (ret < 0) { 3153a9083016SGiridhar Malavali val |= (0x7 << 2); 3154a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 3155a9083016SGiridhar Malavali } 3156a9083016SGiridhar Malavali 3157a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 3158a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3159a9083016SGiridhar Malavali 3160a9083016SGiridhar Malavali done_unprotect: 3161a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3162a9083016SGiridhar Malavali return ret; 3163a9083016SGiridhar Malavali } 3164a9083016SGiridhar Malavali 3165a9083016SGiridhar Malavali int 3166a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 3167a9083016SGiridhar Malavali { 3168a9083016SGiridhar Malavali int ret; 3169a9083016SGiridhar Malavali uint32_t val; 3170a9083016SGiridhar Malavali 3171a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3172a9083016SGiridhar Malavali if (ret < 0) { 3173a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3174a9083016SGiridhar Malavali return ret; 3175a9083016SGiridhar Malavali } 3176a9083016SGiridhar Malavali 3177a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3178a9083016SGiridhar Malavali if (ret < 0) 3179a9083016SGiridhar Malavali goto done_protect; 3180a9083016SGiridhar Malavali 3181a9083016SGiridhar Malavali val |= (0x7 << 2); 3182a9083016SGiridhar Malavali /* LOCK all sectors */ 3183a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3184a9083016SGiridhar Malavali if (ret < 0) 3185a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write status register failed\n"); 3186a9083016SGiridhar Malavali 3187a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 3188a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3189a9083016SGiridhar Malavali done_protect: 3190a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3191a9083016SGiridhar Malavali return ret; 3192a9083016SGiridhar Malavali } 3193a9083016SGiridhar Malavali 3194a9083016SGiridhar Malavali int 3195a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3196a9083016SGiridhar Malavali { 3197a9083016SGiridhar Malavali int ret = 0; 3198a9083016SGiridhar Malavali 3199a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3200a9083016SGiridhar Malavali if (ret < 0) { 3201a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3202a9083016SGiridhar Malavali return ret; 3203a9083016SGiridhar Malavali } 3204a9083016SGiridhar Malavali 3205a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 3206a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3207a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3208a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3209a9083016SGiridhar Malavali 3210a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 3211a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3212a9083016SGiridhar Malavali "Error waiting for rom done\n"); 3213a9083016SGiridhar Malavali ret = -1; 3214a9083016SGiridhar Malavali goto done; 3215a9083016SGiridhar Malavali } 3216a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 3217a9083016SGiridhar Malavali done: 3218a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3219a9083016SGiridhar Malavali return ret; 3220a9083016SGiridhar Malavali } 3221a9083016SGiridhar Malavali 3222a9083016SGiridhar Malavali /* 3223a9083016SGiridhar Malavali * Address and length are byte address 3224a9083016SGiridhar Malavali */ 3225a9083016SGiridhar Malavali uint8_t * 3226a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3227a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3228a9083016SGiridhar Malavali { 3229a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3230a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3231a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3232a9083016SGiridhar Malavali return buf; 3233a9083016SGiridhar Malavali } 3234a9083016SGiridhar Malavali 3235a9083016SGiridhar Malavali static int 3236a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3237a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 3238a9083016SGiridhar Malavali { 3239a9083016SGiridhar Malavali int ret; 3240a9083016SGiridhar Malavali uint32_t liter; 3241a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 3242a9083016SGiridhar Malavali dma_addr_t optrom_dma; 3243a9083016SGiridhar Malavali void *optrom = NULL; 3244a9083016SGiridhar Malavali int page_mode = 0; 3245a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3246a9083016SGiridhar Malavali 3247a9083016SGiridhar Malavali ret = -1; 3248a9083016SGiridhar Malavali 3249a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 3250a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 3251a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 3252a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3253a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 3254a9083016SGiridhar Malavali if (!optrom) { 3255a9083016SGiridhar Malavali qla_printk(KERN_DEBUG, ha, 3256a9083016SGiridhar Malavali "Unable to allocate memory for optrom " 3257a9083016SGiridhar Malavali "burst write (%x KB).\n", 3258a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 3259a9083016SGiridhar Malavali } 3260a9083016SGiridhar Malavali } 3261a9083016SGiridhar Malavali 3262a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 3263a9083016SGiridhar Malavali sec_mask = ~rest_addr; 3264a9083016SGiridhar Malavali 3265a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 3266a9083016SGiridhar Malavali if (ret) { 3267a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3268a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 3269a9083016SGiridhar Malavali goto write_done; 3270a9083016SGiridhar Malavali } 3271a9083016SGiridhar Malavali 3272a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3273a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 3274a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 3275a9083016SGiridhar Malavali 3276a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 3277a9083016SGiridhar Malavali if (ret) { 3278a9083016SGiridhar Malavali DEBUG9(qla_printk(KERN_ERR, ha, 3279a9083016SGiridhar Malavali "Unable to erase sector: " 3280a9083016SGiridhar Malavali "address=%x.\n", faddr)); 3281a9083016SGiridhar Malavali break; 3282a9083016SGiridhar Malavali } 3283a9083016SGiridhar Malavali } 3284a9083016SGiridhar Malavali 3285a9083016SGiridhar Malavali /* Go with burst-write. */ 3286a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3287a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 3288a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3289a9083016SGiridhar Malavali 3290a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 3291a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3292a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 3293a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 3294a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3295a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 3296a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 3297a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3298a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 3299a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3300a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 3301a9083016SGiridhar Malavali 3302a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3303a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3304a9083016SGiridhar Malavali optrom = NULL; 3305a9083016SGiridhar Malavali } else { 3306a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 3307a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 3308a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 3309a9083016SGiridhar Malavali continue; 3310a9083016SGiridhar Malavali } 3311a9083016SGiridhar Malavali } 3312a9083016SGiridhar Malavali 3313a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 3314a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 3315a9083016SGiridhar Malavali if (ret) { 3316a9083016SGiridhar Malavali DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program" 3317a9083016SGiridhar Malavali "flash address=%x data=%x.\n", __func__, 3318a9083016SGiridhar Malavali ha->host_no, faddr, *dwptr)); 3319a9083016SGiridhar Malavali break; 3320a9083016SGiridhar Malavali } 3321a9083016SGiridhar Malavali } 3322a9083016SGiridhar Malavali 3323a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 3324a9083016SGiridhar Malavali if (ret) 3325a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3326a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 3327a9083016SGiridhar Malavali write_done: 3328a9083016SGiridhar Malavali if (optrom) 3329a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3330a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3331a9083016SGiridhar Malavali return ret; 3332a9083016SGiridhar Malavali } 3333a9083016SGiridhar Malavali 3334a9083016SGiridhar Malavali int 3335a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3336a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3337a9083016SGiridhar Malavali { 3338a9083016SGiridhar Malavali int rval; 3339a9083016SGiridhar Malavali 3340a9083016SGiridhar Malavali /* Suspend HBA. */ 3341a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3342a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3343a9083016SGiridhar Malavali length >> 2); 3344a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3345a9083016SGiridhar Malavali 3346a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 3347a9083016SGiridhar Malavali if (rval) 3348a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3349a9083016SGiridhar Malavali else 3350a9083016SGiridhar Malavali rval = QLA_SUCCESS; 3351a9083016SGiridhar Malavali return rval; 3352a9083016SGiridhar Malavali } 3353a9083016SGiridhar Malavali 3354a9083016SGiridhar Malavali void 3355a9083016SGiridhar Malavali qla82xx_start_iocbs(srb_t *sp) 3356a9083016SGiridhar Malavali { 3357a9083016SGiridhar Malavali struct qla_hw_data *ha = sp->fcport->vha->hw; 3358a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3359a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 3360a9083016SGiridhar Malavali uint32_t dbval; 3361a9083016SGiridhar Malavali 3362a9083016SGiridhar Malavali /* Adjust ring index. */ 3363a9083016SGiridhar Malavali req->ring_index++; 3364a9083016SGiridhar Malavali if (req->ring_index == req->length) { 3365a9083016SGiridhar Malavali req->ring_index = 0; 3366a9083016SGiridhar Malavali req->ring_ptr = req->ring; 3367a9083016SGiridhar Malavali } else 3368a9083016SGiridhar Malavali req->ring_ptr++; 3369a9083016SGiridhar Malavali 3370a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 3371a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 3372a9083016SGiridhar Malavali 3373a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 3374a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3375a9083016SGiridhar Malavali wmb(); 3376a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 3377a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3378a9083016SGiridhar Malavali wmb(); 3379a9083016SGiridhar Malavali } 3380a9083016SGiridhar Malavali } 3381a9083016SGiridhar Malavali 3382a9083016SGiridhar Malavali /* 3383a9083016SGiridhar Malavali * qla82xx_device_bootstrap 3384a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 3385a9083016SGiridhar Malavali * 3386a9083016SGiridhar Malavali * Note: 3387a9083016SGiridhar Malavali * IDC lock must be held upon entry 3388a9083016SGiridhar Malavali * 3389a9083016SGiridhar Malavali * Return: 3390a9083016SGiridhar Malavali * Success : 0 3391a9083016SGiridhar Malavali * Failed : 1 3392a9083016SGiridhar Malavali */ 3393a9083016SGiridhar Malavali static int 3394a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3395a9083016SGiridhar Malavali { 3396a9083016SGiridhar Malavali int rval, i, timeout; 3397a9083016SGiridhar Malavali uint32_t old_count, count; 3398a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3399a9083016SGiridhar Malavali 3400a9083016SGiridhar Malavali if (qla82xx_need_reset(ha)) 3401a9083016SGiridhar Malavali goto dev_initialize; 3402a9083016SGiridhar Malavali 3403a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3404a9083016SGiridhar Malavali 3405a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 3406a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 3407a9083016SGiridhar Malavali if (timeout) { 3408a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3409a9083016SGiridhar Malavali QLA82XX_DEV_FAILED); 3410a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3411a9083016SGiridhar Malavali } 3412a9083016SGiridhar Malavali 3413a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3414a9083016SGiridhar Malavali if (count != old_count) 3415a9083016SGiridhar Malavali goto dev_ready; 3416a9083016SGiridhar Malavali } 3417a9083016SGiridhar Malavali 3418a9083016SGiridhar Malavali dev_initialize: 3419a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 3420a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 3421a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3422a9083016SGiridhar Malavali 3423a9083016SGiridhar Malavali /* Driver that sets device state to initializating sets IDC version */ 3424a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3425a9083016SGiridhar Malavali 3426a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3427a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 3428a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3429a9083016SGiridhar Malavali 3430a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 3431a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3432a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 3433a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3434a9083016SGiridhar Malavali return rval; 3435a9083016SGiridhar Malavali } 3436a9083016SGiridhar Malavali 3437a9083016SGiridhar Malavali dev_ready: 3438a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: READY\n"); 3439a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3440a9083016SGiridhar Malavali 3441a9083016SGiridhar Malavali return QLA_SUCCESS; 3442a9083016SGiridhar Malavali } 3443a9083016SGiridhar Malavali 3444a9083016SGiridhar Malavali static void 3445a9083016SGiridhar Malavali qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3446a9083016SGiridhar Malavali { 3447a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3448a9083016SGiridhar Malavali 3449a9083016SGiridhar Malavali /* Disable the board */ 3450a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "Disabling the board\n"); 3451a9083016SGiridhar Malavali 3452b963752fSGiridhar Malavali qla82xx_idc_lock(ha); 3453b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3454b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 3455b963752fSGiridhar Malavali 3456a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3457a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3458a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3459a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3460a9083016SGiridhar Malavali vha->flags.online = 0; 3461a9083016SGiridhar Malavali vha->flags.init_done = 0; 3462a9083016SGiridhar Malavali } 3463a9083016SGiridhar Malavali 3464a9083016SGiridhar Malavali /* 3465a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3466a9083016SGiridhar Malavali * Code to start reset sequence 3467a9083016SGiridhar Malavali * 3468a9083016SGiridhar Malavali * Note: 3469a9083016SGiridhar Malavali * IDC lock must be held upon entry 3470a9083016SGiridhar Malavali * 3471a9083016SGiridhar Malavali * Return: 3472a9083016SGiridhar Malavali * Success : 0 3473a9083016SGiridhar Malavali * Failed : 1 3474a9083016SGiridhar Malavali */ 3475a9083016SGiridhar Malavali static void 3476a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3477a9083016SGiridhar Malavali { 3478a9083016SGiridhar Malavali uint32_t dev_state, drv_state, drv_active; 3479a9083016SGiridhar Malavali unsigned long reset_timeout; 3480a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3481a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3482a9083016SGiridhar Malavali 3483a9083016SGiridhar Malavali if (vha->flags.online) { 3484a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3485a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3486a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3487a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3488a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3489a9083016SGiridhar Malavali } 3490a9083016SGiridhar Malavali 3491a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 3492a9083016SGiridhar Malavali 3493a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 3494a9083016SGiridhar Malavali reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3495a9083016SGiridhar Malavali 3496a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3497a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3498a9083016SGiridhar Malavali 3499a9083016SGiridhar Malavali while (drv_state != drv_active) { 3500a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 3501a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 3502a9083016SGiridhar Malavali "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME); 3503a9083016SGiridhar Malavali break; 3504a9083016SGiridhar Malavali } 3505a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3506a9083016SGiridhar Malavali msleep(1000); 3507a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3508a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3509a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3510a9083016SGiridhar Malavali } 3511a9083016SGiridhar Malavali 3512a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3513f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 3514f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3515f1af6208SGiridhar Malavali 3516a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 3517a9083016SGiridhar Malavali if (dev_state != QLA82XX_DEV_INITIALIZING) { 3518a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3519a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3520a9083016SGiridhar Malavali } 3521a9083016SGiridhar Malavali } 3522a9083016SGiridhar Malavali 3523a9083016SGiridhar Malavali static void 3524a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3525a9083016SGiridhar Malavali { 3526a9083016SGiridhar Malavali uint32_t fw_heartbeat_counter, halt_status; 3527a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3528a9083016SGiridhar Malavali 3529a9083016SGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3530a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3531a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3532a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3533a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3534a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 3535a9083016SGiridhar Malavali halt_status = qla82xx_rd_32(ha, 3536a9083016SGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 3537a9083016SGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3538a9083016SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 3539a9083016SGiridhar Malavali } else { 3540a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 3541a9083016SGiridhar Malavali "scsi(%ld): %s - detect abort needed\n", 3542a9083016SGiridhar Malavali vha->host_no, __func__); 3543a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3544a9083016SGiridhar Malavali } 3545a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3546cdbb0a4fSSantosh Vernekar if (ha->flags.mbox_busy) { 3547cdbb0a4fSSantosh Vernekar ha->flags.fw_hung = 1; 3548cdbb0a4fSSantosh Vernekar ha->flags.mbox_int = 1; 3549cdbb0a4fSSantosh Vernekar DEBUG2(qla_printk(KERN_ERR, ha, 3550cdbb0a4fSSantosh Vernekar "Due to fw hung, doing premature " 3551cdbb0a4fSSantosh Vernekar "completion of mbx command\n")); 3552cdbb0a4fSSantosh Vernekar complete(&ha->mbx_intr_comp); 3553cdbb0a4fSSantosh Vernekar } 3554a9083016SGiridhar Malavali } 3555a9083016SGiridhar Malavali } 3556a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 3557a9083016SGiridhar Malavali } 3558a9083016SGiridhar Malavali 3559a9083016SGiridhar Malavali /* 3560a9083016SGiridhar Malavali * qla82xx_device_state_handler 3561a9083016SGiridhar Malavali * Main state handler 3562a9083016SGiridhar Malavali * 3563a9083016SGiridhar Malavali * Note: 3564a9083016SGiridhar Malavali * IDC lock must be held upon entry 3565a9083016SGiridhar Malavali * 3566a9083016SGiridhar Malavali * Return: 3567a9083016SGiridhar Malavali * Success : 0 3568a9083016SGiridhar Malavali * Failed : 1 3569a9083016SGiridhar Malavali */ 3570a9083016SGiridhar Malavali int 3571a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3572a9083016SGiridhar Malavali { 3573a9083016SGiridhar Malavali uint32_t dev_state; 3574a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3575a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3576a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3577a9083016SGiridhar Malavali 3578a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3579a9083016SGiridhar Malavali if (!vha->flags.init_done) 3580a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 3581a9083016SGiridhar Malavali 3582a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3583f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 3584f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3585a9083016SGiridhar Malavali 3586a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 3587a9083016SGiridhar Malavali dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3588a9083016SGiridhar Malavali 3589a9083016SGiridhar Malavali while (1) { 3590a9083016SGiridhar Malavali 3591a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 3592a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3593a9083016SGiridhar Malavali "%s: device init failed!\n", 3594a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 3595a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3596a9083016SGiridhar Malavali break; 3597a9083016SGiridhar Malavali } 3598a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3599f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, 3600f1af6208SGiridhar Malavali "2:Device state is 0x%x = %s\n", dev_state, 3601f1af6208SGiridhar Malavali dev_state < MAX_STATES ? 3602f1af6208SGiridhar Malavali qdev_state[dev_state] : "Unknown"); 3603f1af6208SGiridhar Malavali 3604a9083016SGiridhar Malavali switch (dev_state) { 3605a9083016SGiridhar Malavali case QLA82XX_DEV_READY: 3606a9083016SGiridhar Malavali goto exit; 3607a9083016SGiridhar Malavali case QLA82XX_DEV_COLD: 3608a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 3609a9083016SGiridhar Malavali goto exit; 3610a9083016SGiridhar Malavali case QLA82XX_DEV_INITIALIZING: 3611a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3612a9083016SGiridhar Malavali msleep(1000); 3613a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3614a9083016SGiridhar Malavali break; 3615a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_RESET: 3616a9083016SGiridhar Malavali if (!ql2xdontresethba) 3617a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3618a9083016SGiridhar Malavali break; 3619a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_QUIESCENT: 3620a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(ha); 3621a9083016SGiridhar Malavali case QLA82XX_DEV_QUIESCENT: 3622a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3623a9083016SGiridhar Malavali msleep(1000); 3624a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3625a9083016SGiridhar Malavali break; 3626a9083016SGiridhar Malavali case QLA82XX_DEV_FAILED: 3627a9083016SGiridhar Malavali qla82xx_dev_failed_handler(vha); 3628a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3629a9083016SGiridhar Malavali goto exit; 3630a9083016SGiridhar Malavali default: 3631a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3632a9083016SGiridhar Malavali msleep(1000); 3633a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3634a9083016SGiridhar Malavali } 3635a9083016SGiridhar Malavali } 3636a9083016SGiridhar Malavali exit: 3637a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3638a9083016SGiridhar Malavali return rval; 3639a9083016SGiridhar Malavali } 3640a9083016SGiridhar Malavali 3641a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3642a9083016SGiridhar Malavali { 3643a9083016SGiridhar Malavali uint32_t dev_state; 3644a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3645a9083016SGiridhar Malavali 3646a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3647a9083016SGiridhar Malavali 3648a9083016SGiridhar Malavali /* don't poll if reset is going on */ 3649a9083016SGiridhar Malavali if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 3650a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || 3651a9083016SGiridhar Malavali test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) { 3652a9083016SGiridhar Malavali if (dev_state == QLA82XX_DEV_NEED_RESET) { 3653a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3654a9083016SGiridhar Malavali "%s(): Adapter reset needed!\n", __func__); 3655a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3656a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3657cdbb0a4fSSantosh Vernekar if (ha->flags.mbox_busy) { 3658cdbb0a4fSSantosh Vernekar ha->flags.fw_hung = 1; 3659cdbb0a4fSSantosh Vernekar ha->flags.mbox_int = 1; 3660cdbb0a4fSSantosh Vernekar DEBUG2(qla_printk(KERN_ERR, ha, 3661cdbb0a4fSSantosh Vernekar "Need reset, doing premature " 3662cdbb0a4fSSantosh Vernekar "completion of mbx command\n")); 3663cdbb0a4fSSantosh Vernekar complete(&ha->mbx_intr_comp); 3664cdbb0a4fSSantosh Vernekar } 3665a9083016SGiridhar Malavali } else { 3666a9083016SGiridhar Malavali qla82xx_check_fw_alive(vha); 3667a9083016SGiridhar Malavali } 3668a9083016SGiridhar Malavali } 3669a9083016SGiridhar Malavali } 3670a9083016SGiridhar Malavali 3671a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3672a9083016SGiridhar Malavali { 3673a9083016SGiridhar Malavali int rval; 3674a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3675a9083016SGiridhar Malavali return rval; 3676a9083016SGiridhar Malavali } 3677a9083016SGiridhar Malavali 3678a9083016SGiridhar Malavali /* 3679a9083016SGiridhar Malavali * qla82xx_abort_isp 3680a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3681a9083016SGiridhar Malavali * 3682a9083016SGiridhar Malavali * Input: 3683a9083016SGiridhar Malavali * ha = adapter block pointer. 3684a9083016SGiridhar Malavali * 3685a9083016SGiridhar Malavali * Returns: 3686a9083016SGiridhar Malavali * 0 = success 3687a9083016SGiridhar Malavali */ 3688a9083016SGiridhar Malavali int 3689a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3690a9083016SGiridhar Malavali { 3691a9083016SGiridhar Malavali int rval; 3692a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3693a9083016SGiridhar Malavali uint32_t dev_state; 3694a9083016SGiridhar Malavali 3695a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 3696a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3697a9083016SGiridhar Malavali "%s(%ld): Device in failed state, " 3698a9083016SGiridhar Malavali "Exiting.\n", __func__, vha->host_no); 3699a9083016SGiridhar Malavali return QLA_SUCCESS; 3700a9083016SGiridhar Malavali } 3701a9083016SGiridhar Malavali 3702a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3703a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3704f1af6208SGiridhar Malavali if (dev_state == QLA82XX_DEV_READY) { 3705a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3706a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3707a9083016SGiridhar Malavali QLA82XX_DEV_NEED_RESET); 3708a9083016SGiridhar Malavali } else 3709f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: %s\n", 3710f1af6208SGiridhar Malavali dev_state < MAX_STATES ? 3711f1af6208SGiridhar Malavali qdev_state[dev_state] : "Unknown"); 3712a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3713a9083016SGiridhar Malavali 3714a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3715a9083016SGiridhar Malavali 3716a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3717a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3718a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3719a9083016SGiridhar Malavali 3720cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 3721cdbb0a4fSSantosh Vernekar ha->flags.fw_hung = 0; 3722a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3723cdbb0a4fSSantosh Vernekar } 3724f1af6208SGiridhar Malavali 3725f1af6208SGiridhar Malavali if (rval) { 3726f1af6208SGiridhar Malavali vha->flags.online = 1; 3727f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3728f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 3729f1af6208SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3730f1af6208SGiridhar Malavali "ISP error recovery failed - " 3731f1af6208SGiridhar Malavali "board disabled\n"); 3732f1af6208SGiridhar Malavali /* 3733f1af6208SGiridhar Malavali * The next call disables the board 3734f1af6208SGiridhar Malavali * completely. 3735f1af6208SGiridhar Malavali */ 3736f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3737f1af6208SGiridhar Malavali vha->flags.online = 0; 3738f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3739f1af6208SGiridhar Malavali &vha->dpc_flags); 3740f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3741f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3742f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 3743f1af6208SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3744f1af6208SGiridhar Malavali "qla%ld: ISP abort - retry remaining %d\n", 3745f1af6208SGiridhar Malavali vha->host_no, ha->isp_abort_cnt)); 3746f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3747f1af6208SGiridhar Malavali } 3748f1af6208SGiridhar Malavali } else { 3749f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3750f1af6208SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3751f1af6208SGiridhar Malavali "(%ld): ISP error recovery - retrying (%d) " 3752f1af6208SGiridhar Malavali "more times\n", vha->host_no, ha->isp_abort_cnt)); 3753f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3754f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3755f1af6208SGiridhar Malavali } 3756f1af6208SGiridhar Malavali } 3757a9083016SGiridhar Malavali return rval; 3758a9083016SGiridhar Malavali } 3759a9083016SGiridhar Malavali 3760a9083016SGiridhar Malavali /* 3761a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3762a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3763a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3764a9083016SGiridhar Malavali * chip reset. 3765a9083016SGiridhar Malavali * 3766a9083016SGiridhar Malavali * Input: 3767a9083016SGiridhar Malavali * ha = adapter block pointer. 3768a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3769a9083016SGiridhar Malavali * 3770a9083016SGiridhar Malavali * Returns: 3771a9083016SGiridhar Malavali * 0 = success 3772a9083016SGiridhar Malavali */ 3773a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3774a9083016SGiridhar Malavali { 3775a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3776a9083016SGiridhar Malavali 3777a9083016SGiridhar Malavali if (vha->flags.online) { 3778a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3779a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3780a9083016SGiridhar Malavali } 3781a9083016SGiridhar Malavali 3782a9083016SGiridhar Malavali /* Stop currently executing firmware. 3783a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3784a9083016SGiridhar Malavali */ 3785a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3786a9083016SGiridhar Malavali 3787a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3788a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3789a9083016SGiridhar Malavali 3790a9083016SGiridhar Malavali return rval; 3791a9083016SGiridhar Malavali } 3792a9083016SGiridhar Malavali 3793a9083016SGiridhar Malavali /* 3794a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3795a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3796a9083016SGiridhar Malavali * 3797a9083016SGiridhar Malavali * Note: 3798a9083016SGiridhar Malavali * Does context switching here. 3799a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3800a9083016SGiridhar Malavali * 3801a9083016SGiridhar Malavali * Return: 3802a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3803a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3804a9083016SGiridhar Malavali */ 3805a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3806a9083016SGiridhar Malavali { 3807a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3808a9083016SGiridhar Malavali unsigned long wait_reset; 3809a9083016SGiridhar Malavali 3810a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3811a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3812a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3813a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3814a9083016SGiridhar Malavali 3815a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3816a9083016SGiridhar Malavali schedule_timeout(HZ); 3817a9083016SGiridhar Malavali 3818a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3819a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3820a9083016SGiridhar Malavali status = QLA_SUCCESS; 3821a9083016SGiridhar Malavali break; 3822a9083016SGiridhar Malavali } 3823a9083016SGiridhar Malavali } 3824a9083016SGiridhar Malavali DEBUG2(printk(KERN_INFO 3825a9083016SGiridhar Malavali "%s status=%d\n", __func__, status)); 3826a9083016SGiridhar Malavali 3827a9083016SGiridhar Malavali return status; 3828a9083016SGiridhar Malavali } 3829