1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 307e264b7SAndrew Vasquez * Copyright (c) 2003-2011 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39a9083016SGiridhar Malavali int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 45a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 46a9083016SGiridhar Malavali { 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 97a9083016SGiridhar Malavali /* 98a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 99a9083016SGiridhar Malavali */ 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 101a9083016SGiridhar Malavali 102a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 103a9083016SGiridhar Malavali } 104a9083016SGiridhar Malavali 105a9083016SGiridhar Malavali struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 107a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 108a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 109a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 110a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 111a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 112a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 113a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 114a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 123a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 125a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213a9083016SGiridhar Malavali {{{0} } }, 214a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 215a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 216a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 217a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 218a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 219a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 220a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 221a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 230a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{0} } }, 235a9083016SGiridhar Malavali {{{0} } }, 236a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248a9083016SGiridhar Malavali {{{0} } }, 249a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255a9083016SGiridhar Malavali {{{0} } }, 256a9083016SGiridhar Malavali {{{0} } }, 257a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260a9083016SGiridhar Malavali }; 261a9083016SGiridhar Malavali 262a9083016SGiridhar Malavali /* 263a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 264a9083016SGiridhar Malavali */ 265a9083016SGiridhar Malavali unsigned qla82xx_crb_hub_agt[64] = { 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270a9083016SGiridhar Malavali 0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293a9083016SGiridhar Malavali 0, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318a9083016SGiridhar Malavali 0, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali }; 331a9083016SGiridhar Malavali 332f1af6208SGiridhar Malavali /* Device states */ 33308de2844SGiridhar Malavali char *q_dev_state[] = { 334f1af6208SGiridhar Malavali "Unknown", 335f1af6208SGiridhar Malavali "Cold", 336f1af6208SGiridhar Malavali "Initializing", 337f1af6208SGiridhar Malavali "Ready", 338f1af6208SGiridhar Malavali "Need Reset", 339f1af6208SGiridhar Malavali "Need Quiescent", 340f1af6208SGiridhar Malavali "Failed", 341f1af6208SGiridhar Malavali "Quiescent", 342f1af6208SGiridhar Malavali }; 343f1af6208SGiridhar Malavali 34408de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 34508de2844SGiridhar Malavali { 34608de2844SGiridhar Malavali return q_dev_state[dev_state]; 34708de2844SGiridhar Malavali } 34808de2844SGiridhar Malavali 349a9083016SGiridhar Malavali /* 350a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 351a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 352a9083016SGiridhar Malavali * side effect: lock crb window 353a9083016SGiridhar Malavali */ 354a9083016SGiridhar Malavali static void 355a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356a9083016SGiridhar Malavali { 357a9083016SGiridhar Malavali u32 win_read; 3587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359a9083016SGiridhar Malavali 360a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 361a9083016SGiridhar Malavali writel(ha->crb_win, 362a9083016SGiridhar Malavali (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363a9083016SGiridhar Malavali 364a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 365a9083016SGiridhar Malavali * to use it. 366a9083016SGiridhar Malavali */ 367a9083016SGiridhar Malavali win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3697c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3707c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3717c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 3727c3df132SSaurav Kashyap ha->crb_win, win_read, *off); 373a9083016SGiridhar Malavali } 374a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375a9083016SGiridhar Malavali } 376a9083016SGiridhar Malavali 377a9083016SGiridhar Malavali static inline unsigned long 378a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379a9083016SGiridhar Malavali { 3807c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 382a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 384a9083016SGiridhar Malavali * regs are in both windows. 385a9083016SGiridhar Malavali */ 386a9083016SGiridhar Malavali return off; 387a9083016SGiridhar Malavali } 388a9083016SGiridhar Malavali 389a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390a9083016SGiridhar Malavali /* We are in first CRB window */ 391a9083016SGiridhar Malavali if (ha->curr_window != 0) 392a9083016SGiridhar Malavali WARN_ON(1); 393a9083016SGiridhar Malavali return off; 394a9083016SGiridhar Malavali } 395a9083016SGiridhar Malavali 396a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397a9083016SGiridhar Malavali /* We are in second CRB window */ 398a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399a9083016SGiridhar Malavali 400a9083016SGiridhar Malavali if (ha->curr_window != 1) 401a9083016SGiridhar Malavali return off; 402a9083016SGiridhar Malavali 403a9083016SGiridhar Malavali /* We are in the QM or direct access 404a9083016SGiridhar Malavali * register region - do nothing 405a9083016SGiridhar Malavali */ 406a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 408a9083016SGiridhar Malavali return off; 409a9083016SGiridhar Malavali } 410a9083016SGiridhar Malavali /* strange address given */ 4117c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 4127c3df132SSaurav Kashyap "%x: Warning: unm_nic_pci_set_crbwindow " 4137c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4147c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 415a9083016SGiridhar Malavali return off; 416a9083016SGiridhar Malavali } 417a9083016SGiridhar Malavali 41877e334d2SGiridhar Malavali static int 41977e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 42077e334d2SGiridhar Malavali { 42177e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42277e334d2SGiridhar Malavali 42377e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 42477e334d2SGiridhar Malavali return -1; 42577e334d2SGiridhar Malavali 42677e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42777e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42877e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 42977e334d2SGiridhar Malavali return 0; 43077e334d2SGiridhar Malavali } 43177e334d2SGiridhar Malavali 43277e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 43377e334d2SGiridhar Malavali return -1; 43477e334d2SGiridhar Malavali 43577e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 43677e334d2SGiridhar Malavali 43777e334d2SGiridhar Malavali /* Try direct map */ 43877e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 43977e334d2SGiridhar Malavali 44077e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 44177e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 44277e334d2SGiridhar Malavali return 0; 44377e334d2SGiridhar Malavali } 44477e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 44577e334d2SGiridhar Malavali return 1; 44677e334d2SGiridhar Malavali } 44777e334d2SGiridhar Malavali 44877e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 44977e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45077e334d2SGiridhar Malavali { 45177e334d2SGiridhar Malavali int done = 0, timeout = 0; 45277e334d2SGiridhar Malavali 45377e334d2SGiridhar Malavali while (!done) { 45477e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 45577e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 45677e334d2SGiridhar Malavali if (done == 1) 45777e334d2SGiridhar Malavali break; 45877e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 45977e334d2SGiridhar Malavali return -1; 46077e334d2SGiridhar Malavali timeout++; 46177e334d2SGiridhar Malavali } 46277e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 46377e334d2SGiridhar Malavali return 0; 46477e334d2SGiridhar Malavali } 46577e334d2SGiridhar Malavali 466a9083016SGiridhar Malavali int 467a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468a9083016SGiridhar Malavali { 469a9083016SGiridhar Malavali unsigned long flags = 0; 470a9083016SGiridhar Malavali int rv; 471a9083016SGiridhar Malavali 472a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473a9083016SGiridhar Malavali 474a9083016SGiridhar Malavali BUG_ON(rv == -1); 475a9083016SGiridhar Malavali 476a9083016SGiridhar Malavali if (rv == 1) { 477a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 478a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 479a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 480a9083016SGiridhar Malavali } 481a9083016SGiridhar Malavali 482a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 483a9083016SGiridhar Malavali 484a9083016SGiridhar Malavali if (rv == 1) { 485a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 487a9083016SGiridhar Malavali } 488a9083016SGiridhar Malavali return 0; 489a9083016SGiridhar Malavali } 490a9083016SGiridhar Malavali 491a9083016SGiridhar Malavali int 492a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493a9083016SGiridhar Malavali { 494a9083016SGiridhar Malavali unsigned long flags = 0; 495a9083016SGiridhar Malavali int rv; 496a9083016SGiridhar Malavali u32 data; 497a9083016SGiridhar Malavali 498a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499a9083016SGiridhar Malavali 500a9083016SGiridhar Malavali BUG_ON(rv == -1); 501a9083016SGiridhar Malavali 502a9083016SGiridhar Malavali if (rv == 1) { 503a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 504a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 505a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 506a9083016SGiridhar Malavali } 507a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 508a9083016SGiridhar Malavali 509a9083016SGiridhar Malavali if (rv == 1) { 510a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 512a9083016SGiridhar Malavali } 513a9083016SGiridhar Malavali return data; 514a9083016SGiridhar Malavali } 515a9083016SGiridhar Malavali 516a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 517a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 518a9083016SGiridhar Malavali { 519a9083016SGiridhar Malavali int i; 520a9083016SGiridhar Malavali int done = 0, timeout = 0; 521a9083016SGiridhar Malavali 522a9083016SGiridhar Malavali while (!done) { 523a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 524a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525a9083016SGiridhar Malavali if (done == 1) 526a9083016SGiridhar Malavali break; 527a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 528a9083016SGiridhar Malavali return -1; 529a9083016SGiridhar Malavali 530a9083016SGiridhar Malavali timeout++; 531a9083016SGiridhar Malavali 532a9083016SGiridhar Malavali /* Yield CPU */ 533a9083016SGiridhar Malavali if (!in_interrupt()) 534a9083016SGiridhar Malavali schedule(); 535a9083016SGiridhar Malavali else { 536a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 537a9083016SGiridhar Malavali cpu_relax(); 538a9083016SGiridhar Malavali } 539a9083016SGiridhar Malavali } 540a9083016SGiridhar Malavali 541a9083016SGiridhar Malavali return 0; 542a9083016SGiridhar Malavali } 543a9083016SGiridhar Malavali 544a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 545a9083016SGiridhar Malavali { 546a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547a9083016SGiridhar Malavali } 548a9083016SGiridhar Malavali 549a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 550a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 552a9083016SGiridhar Malavali /* 553a9083016SGiridhar Malavali * check memory access boundary. 554a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 555a9083016SGiridhar Malavali */ 556a9083016SGiridhar Malavali static unsigned long 557a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558a9083016SGiridhar Malavali unsigned long long addr, int size) 559a9083016SGiridhar Malavali { 560a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 562a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 564a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565a9083016SGiridhar Malavali return 0; 566a9083016SGiridhar Malavali else 567a9083016SGiridhar Malavali return 1; 568a9083016SGiridhar Malavali } 569a9083016SGiridhar Malavali 570a9083016SGiridhar Malavali int qla82xx_pci_set_window_warning_count; 571a9083016SGiridhar Malavali 57277e334d2SGiridhar Malavali static unsigned long 573a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574a9083016SGiridhar Malavali { 575a9083016SGiridhar Malavali int window; 576a9083016SGiridhar Malavali u32 win_read; 5777c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578a9083016SGiridhar Malavali 579a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 581a9083016SGiridhar Malavali /* DDR network side */ 582a9083016SGiridhar Malavali window = MN_WIN(addr); 583a9083016SGiridhar Malavali ha->ddr_mn_window = window; 584a9083016SGiridhar Malavali qla82xx_wr_32(ha, 585a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 587a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5897c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5907c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591a9083016SGiridhar Malavali __func__, window, win_read); 592a9083016SGiridhar Malavali } 593a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 596a9083016SGiridhar Malavali unsigned int temp1; 597a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 599a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 600a9083016SGiridhar Malavali addr = -1UL; 601a9083016SGiridhar Malavali } 602a9083016SGiridhar Malavali window = OCM_WIN(addr); 603a9083016SGiridhar Malavali ha->ddr_mn_window = window; 604a9083016SGiridhar Malavali qla82xx_wr_32(ha, 605a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 607a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 609a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 610a9083016SGiridhar Malavali if (win_read != temp1) { 6117c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6127c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613a9083016SGiridhar Malavali __func__, temp1, win_read); 614a9083016SGiridhar Malavali } 615a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616a9083016SGiridhar Malavali 617a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619a9083016SGiridhar Malavali /* QDR network side */ 620a9083016SGiridhar Malavali window = MS_WIN(addr); 621a9083016SGiridhar Malavali ha->qdr_sn_window = window; 622a9083016SGiridhar Malavali qla82xx_wr_32(ha, 623a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 625a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626a9083016SGiridhar Malavali if (win_read != window) { 6277c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6287c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629a9083016SGiridhar Malavali __func__, window, win_read); 630a9083016SGiridhar Malavali } 631a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632a9083016SGiridhar Malavali } else { 633a9083016SGiridhar Malavali /* 634a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 635a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 636a9083016SGiridhar Malavali */ 637a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 638a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6397c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6407c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6417c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 642a9083016SGiridhar Malavali } 643a9083016SGiridhar Malavali addr = -1UL; 644a9083016SGiridhar Malavali } 645a9083016SGiridhar Malavali return addr; 646a9083016SGiridhar Malavali } 647a9083016SGiridhar Malavali 648a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 649a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650a9083016SGiridhar Malavali unsigned long long addr) 651a9083016SGiridhar Malavali { 652a9083016SGiridhar Malavali int window; 653a9083016SGiridhar Malavali unsigned long long qdr_max; 654a9083016SGiridhar Malavali 655a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656a9083016SGiridhar Malavali 657a9083016SGiridhar Malavali /* DDR network side */ 658a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 660a9083016SGiridhar Malavali BUG(); 661a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 663a9083016SGiridhar Malavali return 1; 664a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 666a9083016SGiridhar Malavali return 1; 667a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668a9083016SGiridhar Malavali /* QDR network side */ 669a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 671a9083016SGiridhar Malavali return 1; 672a9083016SGiridhar Malavali } 673a9083016SGiridhar Malavali return 0; 674a9083016SGiridhar Malavali } 675a9083016SGiridhar Malavali 676a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677a9083016SGiridhar Malavali u64 off, void *data, int size) 678a9083016SGiridhar Malavali { 679a9083016SGiridhar Malavali unsigned long flags; 680f1af6208SGiridhar Malavali void *addr = NULL; 681a9083016SGiridhar Malavali int ret = 0; 682a9083016SGiridhar Malavali u64 start; 683a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 684a9083016SGiridhar Malavali unsigned long mem_base; 685a9083016SGiridhar Malavali unsigned long mem_page; 6867c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687a9083016SGiridhar Malavali 688a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 689a9083016SGiridhar Malavali 690a9083016SGiridhar Malavali /* 691a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 692a9083016SGiridhar Malavali * do not access. 693a9083016SGiridhar Malavali */ 694a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 695a9083016SGiridhar Malavali if ((start == -1UL) || 696a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6987c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 6997c3df132SSaurav Kashyap "%s out of bound pci memory " 7007c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7017c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 702a9083016SGiridhar Malavali return -1; 703a9083016SGiridhar Malavali } 704a9083016SGiridhar Malavali 705a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 706a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 707a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 708a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 709a9083016SGiridhar Malavali * consecutive pages. 710a9083016SGiridhar Malavali */ 711a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 712a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713a9083016SGiridhar Malavali else 714a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715a9083016SGiridhar Malavali if (mem_ptr == 0UL) { 716a9083016SGiridhar Malavali *(u8 *)data = 0; 717a9083016SGiridhar Malavali return -1; 718a9083016SGiridhar Malavali } 719a9083016SGiridhar Malavali addr = mem_ptr; 720a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 721a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 722a9083016SGiridhar Malavali 723a9083016SGiridhar Malavali switch (size) { 724a9083016SGiridhar Malavali case 1: 725a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 726a9083016SGiridhar Malavali break; 727a9083016SGiridhar Malavali case 2: 728a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 729a9083016SGiridhar Malavali break; 730a9083016SGiridhar Malavali case 4: 731a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 732a9083016SGiridhar Malavali break; 733a9083016SGiridhar Malavali case 8: 734a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 735a9083016SGiridhar Malavali break; 736a9083016SGiridhar Malavali default: 737a9083016SGiridhar Malavali ret = -1; 738a9083016SGiridhar Malavali break; 739a9083016SGiridhar Malavali } 740a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 741a9083016SGiridhar Malavali 742a9083016SGiridhar Malavali if (mem_ptr) 743a9083016SGiridhar Malavali iounmap(mem_ptr); 744a9083016SGiridhar Malavali return ret; 745a9083016SGiridhar Malavali } 746a9083016SGiridhar Malavali 747a9083016SGiridhar Malavali static int 748a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749a9083016SGiridhar Malavali u64 off, void *data, int size) 750a9083016SGiridhar Malavali { 751a9083016SGiridhar Malavali unsigned long flags; 752f1af6208SGiridhar Malavali void *addr = NULL; 753a9083016SGiridhar Malavali int ret = 0; 754a9083016SGiridhar Malavali u64 start; 755a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 756a9083016SGiridhar Malavali unsigned long mem_base; 757a9083016SGiridhar Malavali unsigned long mem_page; 7587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759a9083016SGiridhar Malavali 760a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 761a9083016SGiridhar Malavali 762a9083016SGiridhar Malavali /* 763a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 764a9083016SGiridhar Malavali * do not access. 765a9083016SGiridhar Malavali */ 766a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 767a9083016SGiridhar Malavali if ((start == -1UL) || 768a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7717c3df132SSaurav Kashyap "%s out of bount memory " 7727c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7737c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 774a9083016SGiridhar Malavali return -1; 775a9083016SGiridhar Malavali } 776a9083016SGiridhar Malavali 777a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 778a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 779a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 780a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 781a9083016SGiridhar Malavali * consecutive pages. 782a9083016SGiridhar Malavali */ 783a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 784a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785a9083016SGiridhar Malavali else 786a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787a9083016SGiridhar Malavali if (mem_ptr == 0UL) 788a9083016SGiridhar Malavali return -1; 789a9083016SGiridhar Malavali 790a9083016SGiridhar Malavali addr = mem_ptr; 791a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 792a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 793a9083016SGiridhar Malavali 794a9083016SGiridhar Malavali switch (size) { 795a9083016SGiridhar Malavali case 1: 796a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 797a9083016SGiridhar Malavali break; 798a9083016SGiridhar Malavali case 2: 799a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 800a9083016SGiridhar Malavali break; 801a9083016SGiridhar Malavali case 4: 802a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 803a9083016SGiridhar Malavali break; 804a9083016SGiridhar Malavali case 8: 805a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 806a9083016SGiridhar Malavali break; 807a9083016SGiridhar Malavali default: 808a9083016SGiridhar Malavali ret = -1; 809a9083016SGiridhar Malavali break; 810a9083016SGiridhar Malavali } 811a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 812a9083016SGiridhar Malavali if (mem_ptr) 813a9083016SGiridhar Malavali iounmap(mem_ptr); 814a9083016SGiridhar Malavali return ret; 815a9083016SGiridhar Malavali } 816a9083016SGiridhar Malavali 817a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81877e334d2SGiridhar Malavali static unsigned long 81977e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 820a9083016SGiridhar Malavali { 821a9083016SGiridhar Malavali int i; 822a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 823a9083016SGiridhar Malavali 824a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 825a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 826a9083016SGiridhar Malavali 827a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 828a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 829a9083016SGiridhar Malavali offset = addr & 0x000fffff; 830a9083016SGiridhar Malavali 831a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 832a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 833a9083016SGiridhar Malavali pci_base = i << 20; 834a9083016SGiridhar Malavali break; 835a9083016SGiridhar Malavali } 836a9083016SGiridhar Malavali } 837a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 838a9083016SGiridhar Malavali return pci_base; 839a9083016SGiridhar Malavali return pci_base + offset; 840a9083016SGiridhar Malavali } 841a9083016SGiridhar Malavali 842a9083016SGiridhar Malavali static long rom_max_timeout = 100; 843a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 844a9083016SGiridhar Malavali 84577e334d2SGiridhar Malavali static int 846a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 847a9083016SGiridhar Malavali { 848a9083016SGiridhar Malavali int done = 0, timeout = 0; 849a9083016SGiridhar Malavali 850a9083016SGiridhar Malavali while (!done) { 851a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 852a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853a9083016SGiridhar Malavali if (done == 1) 854a9083016SGiridhar Malavali break; 855a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 856a9083016SGiridhar Malavali return -1; 857a9083016SGiridhar Malavali timeout++; 858a9083016SGiridhar Malavali } 859a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860a9083016SGiridhar Malavali return 0; 861a9083016SGiridhar Malavali } 862a9083016SGiridhar Malavali 863d652e093SChad Dupuis static void 864d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 865d652e093SChad Dupuis { 866d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867d652e093SChad Dupuis } 868d652e093SChad Dupuis 86977e334d2SGiridhar Malavali static int 870a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871a9083016SGiridhar Malavali { 872a9083016SGiridhar Malavali long timeout = 0; 873a9083016SGiridhar Malavali long done = 0 ; 8747c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875a9083016SGiridhar Malavali 876a9083016SGiridhar Malavali while (done == 0) { 877a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878a9083016SGiridhar Malavali done &= 4; 879a9083016SGiridhar Malavali timeout++; 880a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8817c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8827c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8837c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 884a9083016SGiridhar Malavali return -1; 885a9083016SGiridhar Malavali } 886a9083016SGiridhar Malavali } 887a9083016SGiridhar Malavali return 0; 888a9083016SGiridhar Malavali } 889a9083016SGiridhar Malavali 89077e334d2SGiridhar Malavali static int 891a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 892a9083016SGiridhar Malavali { 893a9083016SGiridhar Malavali long timeout = 0; 894a9083016SGiridhar Malavali long done = 0 ; 8957c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896a9083016SGiridhar Malavali 897a9083016SGiridhar Malavali while (done == 0) { 898a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899a9083016SGiridhar Malavali done &= 2; 900a9083016SGiridhar Malavali timeout++; 901a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9027c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9037c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9047c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 905a9083016SGiridhar Malavali return -1; 906a9083016SGiridhar Malavali } 907a9083016SGiridhar Malavali } 908a9083016SGiridhar Malavali return 0; 909a9083016SGiridhar Malavali } 910a9083016SGiridhar Malavali 91177e334d2SGiridhar Malavali static int 912a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913a9083016SGiridhar Malavali { 9147c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 9157c3df132SSaurav Kashyap 916a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 917a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 918a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 919a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 920a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 921a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9227c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ba, 9237c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 924a9083016SGiridhar Malavali return -1; 925a9083016SGiridhar Malavali } 926a9083016SGiridhar Malavali /* Reset abyte_cnt and dummy_byte_cnt */ 927a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 928a9083016SGiridhar Malavali udelay(10); 929a9083016SGiridhar Malavali cond_resched(); 930a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 931a9083016SGiridhar Malavali *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 932a9083016SGiridhar Malavali return 0; 933a9083016SGiridhar Malavali } 934a9083016SGiridhar Malavali 93577e334d2SGiridhar Malavali static int 936a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937a9083016SGiridhar Malavali { 938a9083016SGiridhar Malavali int ret, loops = 0; 9397c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 940a9083016SGiridhar Malavali 941a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 942a9083016SGiridhar Malavali udelay(100); 943a9083016SGiridhar Malavali schedule(); 944a9083016SGiridhar Malavali loops++; 945a9083016SGiridhar Malavali } 946a9083016SGiridhar Malavali if (loops >= 50000) { 9477c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9487c3df132SSaurav Kashyap "Failed to aquire SEM2 lock.\n"); 949a9083016SGiridhar Malavali return -1; 950a9083016SGiridhar Malavali } 951a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 952d652e093SChad Dupuis qla82xx_rom_unlock(ha); 953a9083016SGiridhar Malavali return ret; 954a9083016SGiridhar Malavali } 955a9083016SGiridhar Malavali 95677e334d2SGiridhar Malavali static int 957a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 958a9083016SGiridhar Malavali { 9597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 960a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 961a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 962a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9647c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 965a9083016SGiridhar Malavali return -1; 966a9083016SGiridhar Malavali } 967a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 968a9083016SGiridhar Malavali return 0; 969a9083016SGiridhar Malavali } 970a9083016SGiridhar Malavali 97177e334d2SGiridhar Malavali static int 972a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 973a9083016SGiridhar Malavali { 974a9083016SGiridhar Malavali long timeout = 0; 975a9083016SGiridhar Malavali uint32_t done = 1 ; 976a9083016SGiridhar Malavali uint32_t val; 977a9083016SGiridhar Malavali int ret = 0; 9787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979a9083016SGiridhar Malavali 980a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 981a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 982a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 983a9083016SGiridhar Malavali done = val & 1; 984a9083016SGiridhar Malavali timeout++; 985a9083016SGiridhar Malavali udelay(10); 986a9083016SGiridhar Malavali cond_resched(); 987a9083016SGiridhar Malavali if (timeout >= 50000) { 9887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 9897c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 990a9083016SGiridhar Malavali return -1; 991a9083016SGiridhar Malavali } 992a9083016SGiridhar Malavali } 993a9083016SGiridhar Malavali return ret; 994a9083016SGiridhar Malavali } 995a9083016SGiridhar Malavali 99677e334d2SGiridhar Malavali static int 997a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 998a9083016SGiridhar Malavali { 999a9083016SGiridhar Malavali uint32_t val; 1000a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1001a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1002a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1003a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1004a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1005a9083016SGiridhar Malavali return -1; 1006a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1007a9083016SGiridhar Malavali return -1; 1008a9083016SGiridhar Malavali if ((val & 2) != 2) 1009a9083016SGiridhar Malavali return -1; 1010a9083016SGiridhar Malavali return 0; 1011a9083016SGiridhar Malavali } 1012a9083016SGiridhar Malavali 101377e334d2SGiridhar Malavali static int 1014a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1015a9083016SGiridhar Malavali { 10167c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1017a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1018a9083016SGiridhar Malavali return -1; 1019a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1020a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1021a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10227c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10237c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1024a9083016SGiridhar Malavali return -1; 1025a9083016SGiridhar Malavali } 1026a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1027a9083016SGiridhar Malavali } 1028a9083016SGiridhar Malavali 102977e334d2SGiridhar Malavali static int 1030a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1031a9083016SGiridhar Malavali { 10327c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1033a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1034a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10357c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10367c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1037a9083016SGiridhar Malavali return -1; 1038a9083016SGiridhar Malavali } 1039a9083016SGiridhar Malavali return 0; 1040a9083016SGiridhar Malavali } 1041a9083016SGiridhar Malavali 104277e334d2SGiridhar Malavali static int 1043a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1044a9083016SGiridhar Malavali { 1045a9083016SGiridhar Malavali int loops = 0; 10467c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10477c3df132SSaurav Kashyap 1048a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1049a9083016SGiridhar Malavali udelay(100); 1050a9083016SGiridhar Malavali cond_resched(); 1051a9083016SGiridhar Malavali loops++; 1052a9083016SGiridhar Malavali } 1053a9083016SGiridhar Malavali if (loops >= 50000) { 10547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10557c3df132SSaurav Kashyap "ROM lock failed.\n"); 1056a9083016SGiridhar Malavali return -1; 1057a9083016SGiridhar Malavali } 1058a9083016SGiridhar Malavali return 0;; 1059a9083016SGiridhar Malavali } 1060a9083016SGiridhar Malavali 106177e334d2SGiridhar Malavali static int 1062a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063a9083016SGiridhar Malavali uint32_t data) 1064a9083016SGiridhar Malavali { 1065a9083016SGiridhar Malavali int ret = 0; 10667c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067a9083016SGiridhar Malavali 1068a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1069a9083016SGiridhar Malavali if (ret < 0) { 10707c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10717c3df132SSaurav Kashyap "ROM lock failed.\n"); 1072a9083016SGiridhar Malavali return ret; 1073a9083016SGiridhar Malavali } 1074a9083016SGiridhar Malavali 1075a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1076a9083016SGiridhar Malavali goto done_write; 1077a9083016SGiridhar Malavali 1078a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1083a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10847c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 10857c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1086a9083016SGiridhar Malavali ret = -1; 1087a9083016SGiridhar Malavali goto done_write; 1088a9083016SGiridhar Malavali } 1089a9083016SGiridhar Malavali 1090a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1091a9083016SGiridhar Malavali 1092a9083016SGiridhar Malavali done_write: 1093d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1094a9083016SGiridhar Malavali return ret; 1095a9083016SGiridhar Malavali } 1096a9083016SGiridhar Malavali 1097a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1098a9083016SGiridhar Malavali * to put the ISP into operational state 1099a9083016SGiridhar Malavali */ 110077e334d2SGiridhar Malavali static int 110177e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102a9083016SGiridhar Malavali { 1103a9083016SGiridhar Malavali int addr, val; 1104a9083016SGiridhar Malavali int i ; 1105a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1106a9083016SGiridhar Malavali unsigned long off; 1107a9083016SGiridhar Malavali unsigned offset, n; 1108a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1109a9083016SGiridhar Malavali 1110a9083016SGiridhar Malavali struct crb_addr_pair { 1111a9083016SGiridhar Malavali long addr; 1112a9083016SGiridhar Malavali long data; 1113a9083016SGiridhar Malavali }; 1114a9083016SGiridhar Malavali 1115a9083016SGiridhar Malavali /* Halt all the indiviual PEGs and other blocks of the ISP */ 1116a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1117c9e8fd5cSMadhuranath Iyengar 111802be2215SGiridhar Malavali /* disable all I2Q */ 111902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 112002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 112102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 112202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 112302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 112402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 112502be2215SGiridhar Malavali 112602be2215SGiridhar Malavali /* disable all niu interrupts */ 1127c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1129c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1131c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 113202be2215SGiridhar Malavali /* disable sideband mac */ 113302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 113402be2215SGiridhar Malavali /* disable ap0 mac */ 113502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 113602be2215SGiridhar Malavali /* disable ap1 mac */ 113702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138c9e8fd5cSMadhuranath Iyengar 1139c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1140c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142c9e8fd5cSMadhuranath Iyengar 1143c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1144c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145c9e8fd5cSMadhuranath Iyengar 1146c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1147c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 115202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153c9e8fd5cSMadhuranath Iyengar 1154c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1155c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 116002be2215SGiridhar Malavali msleep(20); 1161c9e8fd5cSMadhuranath Iyengar 1162c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1163a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1165a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166a9083016SGiridhar Malavali else 1167a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168c9e8fd5cSMadhuranath Iyengar 1169c9e8fd5cSMadhuranath Iyengar /* reset ms */ 1170c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1171c9e8fd5cSMadhuranath Iyengar val |= (1 << 1); 1172c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1173c9e8fd5cSMadhuranath Iyengar msleep(20); 1174c9e8fd5cSMadhuranath Iyengar 1175c9e8fd5cSMadhuranath Iyengar /* unreset ms */ 1176c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1177c9e8fd5cSMadhuranath Iyengar val &= ~(1 << 1); 1178c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1179c9e8fd5cSMadhuranath Iyengar msleep(20); 1180c9e8fd5cSMadhuranath Iyengar 1181d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1182a9083016SGiridhar Malavali 1183a9083016SGiridhar Malavali /* Read the signature value from the flash. 1184a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1185a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1186a9083016SGiridhar Malavali * that present in CRB initialize sequence 1187a9083016SGiridhar Malavali */ 1188a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1189a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11907c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11917c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1192a9083016SGiridhar Malavali return -1; 1193a9083016SGiridhar Malavali } 1194a9083016SGiridhar Malavali 1195a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 1196a9083016SGiridhar Malavali * Number of enteries = upper 16 bits 1197a9083016SGiridhar Malavali */ 1198a9083016SGiridhar Malavali offset = n & 0xffffU; 1199a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1200a9083016SGiridhar Malavali 1201a9083016SGiridhar Malavali /* number of addr/value pair should not exceed 1024 enteries */ 1202a9083016SGiridhar Malavali if (n >= 1024) { 12037c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 12047c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1205a9083016SGiridhar Malavali return -1; 1206a9083016SGiridhar Malavali } 1207a9083016SGiridhar Malavali 12087c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12097c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1210a9083016SGiridhar Malavali 1211a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1212a9083016SGiridhar Malavali if (buf == NULL) { 12137c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12147c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1215a9083016SGiridhar Malavali return -1; 1216a9083016SGiridhar Malavali } 1217a9083016SGiridhar Malavali 1218a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1219a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1220a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1221a9083016SGiridhar Malavali kfree(buf); 1222a9083016SGiridhar Malavali return -1; 1223a9083016SGiridhar Malavali } 1224a9083016SGiridhar Malavali 1225a9083016SGiridhar Malavali buf[i].addr = addr; 1226a9083016SGiridhar Malavali buf[i].data = val; 1227a9083016SGiridhar Malavali } 1228a9083016SGiridhar Malavali 1229a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1230a9083016SGiridhar Malavali /* Translate internal CRB initialization 1231a9083016SGiridhar Malavali * address to PCI bus address 1232a9083016SGiridhar Malavali */ 1233a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1234a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1235a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1236a9083016SGiridhar Malavali * some of them are skipped 1237a9083016SGiridhar Malavali */ 1238a9083016SGiridhar Malavali 1239a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1240a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1241a9083016SGiridhar Malavali continue; 1242a9083016SGiridhar Malavali 1243a9083016SGiridhar Malavali /* do not reset PCI */ 1244a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1245a9083016SGiridhar Malavali continue; 1246a9083016SGiridhar Malavali 1247a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1248a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1249a9083016SGiridhar Malavali continue; 1250a9083016SGiridhar Malavali 1251a9083016SGiridhar Malavali /* skip the function enable register */ 1252a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1253a9083016SGiridhar Malavali continue; 1254a9083016SGiridhar Malavali 1255a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1256a9083016SGiridhar Malavali continue; 1257a9083016SGiridhar Malavali 1258a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1259a9083016SGiridhar Malavali continue; 1260a9083016SGiridhar Malavali 1261a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1262a9083016SGiridhar Malavali continue; 1263a9083016SGiridhar Malavali 1264a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12657c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 12667c3df132SSaurav Kashyap "Unknow addr: 0x%08lx.\n", buf[i].addr); 1267a9083016SGiridhar Malavali continue; 1268a9083016SGiridhar Malavali } 1269a9083016SGiridhar Malavali 1270a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1271a9083016SGiridhar Malavali 1272a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1273a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1274a9083016SGiridhar Malavali */ 1275a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1276a9083016SGiridhar Malavali msleep(1000); 1277a9083016SGiridhar Malavali 1278a9083016SGiridhar Malavali /* ISP requires millisec delay between 1279a9083016SGiridhar Malavali * successive CRB register updation 1280a9083016SGiridhar Malavali */ 1281a9083016SGiridhar Malavali msleep(1); 1282a9083016SGiridhar Malavali } 1283a9083016SGiridhar Malavali 1284a9083016SGiridhar Malavali kfree(buf); 1285a9083016SGiridhar Malavali 1286a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1287a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1288a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1289a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1290a9083016SGiridhar Malavali 1291a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1292a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1293a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1294a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1295a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1296a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1297a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1298a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1299a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1300a9083016SGiridhar Malavali return 0; 1301a9083016SGiridhar Malavali } 1302a9083016SGiridhar Malavali 130377e334d2SGiridhar Malavali static int 130477e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 130577e334d2SGiridhar Malavali u64 off, void *data, int size) 130677e334d2SGiridhar Malavali { 130777e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 130877e334d2SGiridhar Malavali int scale, shift_amount, startword; 130977e334d2SGiridhar Malavali uint32_t temp; 131077e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 131177e334d2SGiridhar Malavali 131277e334d2SGiridhar Malavali /* 131377e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 131477e334d2SGiridhar Malavali */ 131577e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 131677e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 131777e334d2SGiridhar Malavali else { 131877e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 131977e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 132077e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 132177e334d2SGiridhar Malavali off, data, size); 132277e334d2SGiridhar Malavali } 132377e334d2SGiridhar Malavali 132477e334d2SGiridhar Malavali off0 = off & 0x7; 132577e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 132677e334d2SGiridhar Malavali sz[1] = size - sz[0]; 132777e334d2SGiridhar Malavali 132877e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 132977e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 133077e334d2SGiridhar Malavali shift_amount = 4; 133177e334d2SGiridhar Malavali scale = 2; 133277e334d2SGiridhar Malavali startword = (off & 0xf)/8; 133377e334d2SGiridhar Malavali 133477e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 133577e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 133677e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 133777e334d2SGiridhar Malavali return -1; 133877e334d2SGiridhar Malavali } 133977e334d2SGiridhar Malavali 134077e334d2SGiridhar Malavali switch (size) { 134177e334d2SGiridhar Malavali case 1: 134277e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 134377e334d2SGiridhar Malavali break; 134477e334d2SGiridhar Malavali case 2: 134577e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 134677e334d2SGiridhar Malavali break; 134777e334d2SGiridhar Malavali case 4: 134877e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 134977e334d2SGiridhar Malavali break; 135077e334d2SGiridhar Malavali case 8: 135177e334d2SGiridhar Malavali default: 135277e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 135377e334d2SGiridhar Malavali break; 135477e334d2SGiridhar Malavali } 135577e334d2SGiridhar Malavali 135677e334d2SGiridhar Malavali if (sz[0] == 8) { 135777e334d2SGiridhar Malavali word[startword] = tmpw; 135877e334d2SGiridhar Malavali } else { 135977e334d2SGiridhar Malavali word[startword] &= 136077e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 136177e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 136277e334d2SGiridhar Malavali } 136377e334d2SGiridhar Malavali if (sz[1] != 0) { 136477e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 136577e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 136677e334d2SGiridhar Malavali } 136777e334d2SGiridhar Malavali 136877e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 136977e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 137077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 137177e334d2SGiridhar Malavali temp = 0; 137277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 137377e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 137477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 137577e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 137677e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 137777e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 137877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 137977e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 138077e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 138177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 138277e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 138377e334d2SGiridhar Malavali 138477e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 138577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 138677e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 138777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 138877e334d2SGiridhar Malavali 138977e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 139077e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 139177e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 139277e334d2SGiridhar Malavali break; 139377e334d2SGiridhar Malavali } 139477e334d2SGiridhar Malavali 139577e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 139677e334d2SGiridhar Malavali if (printk_ratelimit()) 139777e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 13987c3df132SSaurav Kashyap "failed to write through agent.\n"); 139977e334d2SGiridhar Malavali ret = -1; 140077e334d2SGiridhar Malavali break; 140177e334d2SGiridhar Malavali } 140277e334d2SGiridhar Malavali } 140377e334d2SGiridhar Malavali 140477e334d2SGiridhar Malavali return ret; 140577e334d2SGiridhar Malavali } 140677e334d2SGiridhar Malavali 140777e334d2SGiridhar Malavali static int 1408a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1409a9083016SGiridhar Malavali { 1410a9083016SGiridhar Malavali int i; 1411a9083016SGiridhar Malavali long size = 0; 14129c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14139c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1414a9083016SGiridhar Malavali u64 data; 1415a9083016SGiridhar Malavali u32 high, low; 1416a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1417a9083016SGiridhar Malavali 1418a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1419a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1420a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1421a9083016SGiridhar Malavali return -1; 1422a9083016SGiridhar Malavali } 1423a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1424a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1425a9083016SGiridhar Malavali flashaddr += 8; 1426a9083016SGiridhar Malavali memaddr += 8; 1427a9083016SGiridhar Malavali 1428a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1429a9083016SGiridhar Malavali msleep(1); 1430a9083016SGiridhar Malavali } 1431a9083016SGiridhar Malavali udelay(100); 1432a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1433a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1434a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1435a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1436a9083016SGiridhar Malavali return 0; 1437a9083016SGiridhar Malavali } 1438a9083016SGiridhar Malavali 1439a9083016SGiridhar Malavali int 1440a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1441a9083016SGiridhar Malavali u64 off, void *data, int size) 1442a9083016SGiridhar Malavali { 1443a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1444a9083016SGiridhar Malavali int shift_amount; 1445a9083016SGiridhar Malavali uint32_t temp; 1446a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1447a9083016SGiridhar Malavali 1448a9083016SGiridhar Malavali /* 1449a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1450a9083016SGiridhar Malavali */ 1451a9083016SGiridhar Malavali 1452a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1453a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1454a9083016SGiridhar Malavali else { 1455a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1456a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1457a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1458a9083016SGiridhar Malavali off, data, size); 1459a9083016SGiridhar Malavali } 1460a9083016SGiridhar Malavali 1461a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1462a9083016SGiridhar Malavali off0[0] = off & 0xf; 1463a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1464a9083016SGiridhar Malavali shift_amount = 4; 1465a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1466a9083016SGiridhar Malavali off0[1] = 0; 1467a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1468a9083016SGiridhar Malavali 1469a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1470a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1471a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1472a9083016SGiridhar Malavali temp = 0; 1473a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1474a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1475a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1476a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1477a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1478a9083016SGiridhar Malavali 1479a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1480a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1481a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1482a9083016SGiridhar Malavali break; 1483a9083016SGiridhar Malavali } 1484a9083016SGiridhar Malavali 1485a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1486a9083016SGiridhar Malavali if (printk_ratelimit()) 1487a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14887c3df132SSaurav Kashyap "failed to read through agent.\n"); 1489a9083016SGiridhar Malavali break; 1490a9083016SGiridhar Malavali } 1491a9083016SGiridhar Malavali 1492a9083016SGiridhar Malavali start = off0[i] >> 2; 1493a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1494a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1495a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1496a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1497a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1498a9083016SGiridhar Malavali } 1499a9083016SGiridhar Malavali } 1500a9083016SGiridhar Malavali 1501a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1502a9083016SGiridhar Malavali return -1; 1503a9083016SGiridhar Malavali 1504a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1505a9083016SGiridhar Malavali val = word[0]; 1506a9083016SGiridhar Malavali } else { 1507a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1508a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1509a9083016SGiridhar Malavali } 1510a9083016SGiridhar Malavali 1511a9083016SGiridhar Malavali switch (size) { 1512a9083016SGiridhar Malavali case 1: 1513a9083016SGiridhar Malavali *(uint8_t *)data = val; 1514a9083016SGiridhar Malavali break; 1515a9083016SGiridhar Malavali case 2: 1516a9083016SGiridhar Malavali *(uint16_t *)data = val; 1517a9083016SGiridhar Malavali break; 1518a9083016SGiridhar Malavali case 4: 1519a9083016SGiridhar Malavali *(uint32_t *)data = val; 1520a9083016SGiridhar Malavali break; 1521a9083016SGiridhar Malavali case 8: 1522a9083016SGiridhar Malavali *(uint64_t *)data = val; 1523a9083016SGiridhar Malavali break; 1524a9083016SGiridhar Malavali } 1525a9083016SGiridhar Malavali return 0; 1526a9083016SGiridhar Malavali } 1527a9083016SGiridhar Malavali 1528a9083016SGiridhar Malavali 15299c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15309c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15319c2b2975SHarish Zunjarrao { 15329c2b2975SHarish Zunjarrao uint32_t i; 15339c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15349c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15359c2b2975SHarish Zunjarrao __le32 offset; 15369c2b2975SHarish Zunjarrao __le32 tab_type; 15379c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15389c2b2975SHarish Zunjarrao 15399c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15409c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15419c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15429c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15439c2b2975SHarish Zunjarrao 15449c2b2975SHarish Zunjarrao if (tab_type == section) 15459c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15469c2b2975SHarish Zunjarrao } 15479c2b2975SHarish Zunjarrao 15489c2b2975SHarish Zunjarrao return NULL; 15499c2b2975SHarish Zunjarrao } 15509c2b2975SHarish Zunjarrao 15519c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15529c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15539c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15549c2b2975SHarish Zunjarrao { 15559c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15569c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15579c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15589c2b2975SHarish Zunjarrao __le32 offset; 15599c2b2975SHarish Zunjarrao 15609c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15619c2b2975SHarish Zunjarrao if (!tab_desc) 15629c2b2975SHarish Zunjarrao return NULL; 15639c2b2975SHarish Zunjarrao 15649c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15659c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15669c2b2975SHarish Zunjarrao 15679c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15689c2b2975SHarish Zunjarrao } 15699c2b2975SHarish Zunjarrao 15709c2b2975SHarish Zunjarrao static u8 * 15719c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15729c2b2975SHarish Zunjarrao { 15739c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15749c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15759c2b2975SHarish Zunjarrao 15769c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15779c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15789c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15799c2b2975SHarish Zunjarrao if (uri_desc) 15809c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15819c2b2975SHarish Zunjarrao } 15829c2b2975SHarish Zunjarrao 15839c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15849c2b2975SHarish Zunjarrao } 15859c2b2975SHarish Zunjarrao 15869c2b2975SHarish Zunjarrao static __le32 15879c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15889c2b2975SHarish Zunjarrao { 15899c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15909c2b2975SHarish Zunjarrao 15919c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15929c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15939c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15949c2b2975SHarish Zunjarrao if (uri_desc) 15959c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 15969c2b2975SHarish Zunjarrao } 15979c2b2975SHarish Zunjarrao 15989c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15999c2b2975SHarish Zunjarrao } 16009c2b2975SHarish Zunjarrao 16019c2b2975SHarish Zunjarrao static u8 * 16029c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 16039c2b2975SHarish Zunjarrao { 16049c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 16059c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16069c2b2975SHarish Zunjarrao 16079c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16089c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16099c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16109c2b2975SHarish Zunjarrao if (uri_desc) 16119c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16129c2b2975SHarish Zunjarrao } 16139c2b2975SHarish Zunjarrao 16149c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16159c2b2975SHarish Zunjarrao } 16169c2b2975SHarish Zunjarrao 1617a9083016SGiridhar Malavali /* PCI related functions */ 1618a9083016SGiridhar Malavali char * 1619a9083016SGiridhar Malavali qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1620a9083016SGiridhar Malavali { 1621a9083016SGiridhar Malavali int pcie_reg; 1622a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1623a9083016SGiridhar Malavali char lwstr[6]; 1624a9083016SGiridhar Malavali uint16_t lnk; 1625a9083016SGiridhar Malavali 1626a9083016SGiridhar Malavali pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1627a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1628a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 1629a9083016SGiridhar Malavali 1630a9083016SGiridhar Malavali strcpy(str, "PCIe ("); 1631a9083016SGiridhar Malavali strcat(str, "2.5Gb/s "); 1632a9083016SGiridhar Malavali snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1633a9083016SGiridhar Malavali strcat(str, lwstr); 1634a9083016SGiridhar Malavali return str; 1635a9083016SGiridhar Malavali } 1636a9083016SGiridhar Malavali 1637a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1638a9083016SGiridhar Malavali { 1639a9083016SGiridhar Malavali unsigned long val = 0; 1640a9083016SGiridhar Malavali u32 control; 1641a9083016SGiridhar Malavali 1642a9083016SGiridhar Malavali switch (region) { 1643a9083016SGiridhar Malavali case 0: 1644a9083016SGiridhar Malavali val = 0; 1645a9083016SGiridhar Malavali break; 1646a9083016SGiridhar Malavali case 1: 1647a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1648a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1649a9083016SGiridhar Malavali break; 1650a9083016SGiridhar Malavali } 1651a9083016SGiridhar Malavali return val; 1652a9083016SGiridhar Malavali } 1653a9083016SGiridhar Malavali 1654a9083016SGiridhar Malavali 1655a9083016SGiridhar Malavali int 1656a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1657a9083016SGiridhar Malavali { 1658a9083016SGiridhar Malavali uint32_t len = 0; 1659a9083016SGiridhar Malavali 1660a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16617c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16627c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1663a9083016SGiridhar Malavali goto iospace_error_exit; 1664a9083016SGiridhar Malavali } 1665a9083016SGiridhar Malavali 1666a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1667a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16687c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16697c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1670a9083016SGiridhar Malavali goto iospace_error_exit; 1671a9083016SGiridhar Malavali } 1672a9083016SGiridhar Malavali 1673a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1674a9083016SGiridhar Malavali ha->nx_pcibase = 1675a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1676a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16777c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16787c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1679a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1680a9083016SGiridhar Malavali goto iospace_error_exit; 1681a9083016SGiridhar Malavali } 1682a9083016SGiridhar Malavali 1683a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1684a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1685a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1686a9083016SGiridhar Malavali 1687a9083016SGiridhar Malavali if (!ql2xdbwr) { 1688a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1689a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1690a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1691a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16927c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16937c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1694a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1695a9083016SGiridhar Malavali goto iospace_error_exit; 1696a9083016SGiridhar Malavali } 1697a9083016SGiridhar Malavali 1698a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1699a9083016SGiridhar Malavali * door bell read and write pointer 1700a9083016SGiridhar Malavali */ 1701a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1702a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1703a9083016SGiridhar Malavali } else { 1704a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1705a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1706a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1707a9083016SGiridhar Malavali } 1708a9083016SGiridhar Malavali 1709a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1710a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 17117c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 17127c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17137c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17147c3df132SSaurav Kashyap ha->nx_pcibase, ha->iobase, 17157c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17167c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17177c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17187c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17197c3df132SSaurav Kashyap ha->nx_pcibase, ha->iobase, 17207c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1721a9083016SGiridhar Malavali return 0; 1722a9083016SGiridhar Malavali 1723a9083016SGiridhar Malavali iospace_error_exit: 1724a9083016SGiridhar Malavali return -ENOMEM; 1725a9083016SGiridhar Malavali } 1726a9083016SGiridhar Malavali 1727a9083016SGiridhar Malavali /* GS related functions */ 1728a9083016SGiridhar Malavali 1729a9083016SGiridhar Malavali /* Initialization related functions */ 1730a9083016SGiridhar Malavali 1731a9083016SGiridhar Malavali /** 1732a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1733a9083016SGiridhar Malavali * @ha: HA context 1734a9083016SGiridhar Malavali * 1735a9083016SGiridhar Malavali * Returns 0 on success. 1736a9083016SGiridhar Malavali */ 1737a9083016SGiridhar Malavali int 1738a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1739a9083016SGiridhar Malavali { 1740a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1741a9083016SGiridhar Malavali int ret; 1742a9083016SGiridhar Malavali 1743a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1744a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1745a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17467c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 17477c3df132SSaurav Kashyap "Chip revision:%ld.\n", 17487c3df132SSaurav Kashyap ha->chip_revision); 1749a9083016SGiridhar Malavali return 0; 1750a9083016SGiridhar Malavali } 1751a9083016SGiridhar Malavali 1752a9083016SGiridhar Malavali /** 1753a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1754a9083016SGiridhar Malavali * @ha: HA context 1755a9083016SGiridhar Malavali * 1756a9083016SGiridhar Malavali * Returns 0 on success. 1757a9083016SGiridhar Malavali */ 1758a9083016SGiridhar Malavali void 1759a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1760a9083016SGiridhar Malavali { 1761a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1762a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1763a9083016SGiridhar Malavali } 1764a9083016SGiridhar Malavali 1765a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1766a9083016SGiridhar Malavali { 1767a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1768a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1769a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1770a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1771a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1772a9083016SGiridhar Malavali 1773a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1774a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1775a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1776a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1777a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1778a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1779a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1780a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1781a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1782a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1783a9083016SGiridhar Malavali 1784a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1785a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1786a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1787a9083016SGiridhar Malavali } 1788a9083016SGiridhar Malavali 1789f1af6208SGiridhar Malavali void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1790f1af6208SGiridhar Malavali { 1791f1af6208SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1792f1af6208SGiridhar Malavali vha->flags.online = 0; 1793f1af6208SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 1794f1af6208SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1795f1af6208SGiridhar Malavali } 1796f1af6208SGiridhar Malavali 179777e334d2SGiridhar Malavali static int 179877e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1799a9083016SGiridhar Malavali { 1800a9083016SGiridhar Malavali u64 *ptr64; 1801a9083016SGiridhar Malavali u32 i, flashaddr, size; 1802a9083016SGiridhar Malavali __le64 data; 1803a9083016SGiridhar Malavali 1804a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1805a9083016SGiridhar Malavali 18069c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1807a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1808a9083016SGiridhar Malavali 1809a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1810a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 18119c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 18129c2b2975SHarish Zunjarrao return -EIO; 1813a9083016SGiridhar Malavali flashaddr += 8; 1814a9083016SGiridhar Malavali } 1815a9083016SGiridhar Malavali 1816a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18179c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18189c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1819a9083016SGiridhar Malavali 1820a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1821a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1822a9083016SGiridhar Malavali 1823a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1824a9083016SGiridhar Malavali return -EIO; 1825a9083016SGiridhar Malavali flashaddr += 8; 1826a9083016SGiridhar Malavali } 18279c2b2975SHarish Zunjarrao udelay(100); 1828a9083016SGiridhar Malavali 1829a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1830a9083016SGiridhar Malavali * at a specified offset to indicate 1831a9083016SGiridhar Malavali * that all data is written and 1832a9083016SGiridhar Malavali * ready for firmware to initialize. 1833a9083016SGiridhar Malavali */ 18349c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1835a9083016SGiridhar Malavali 18369c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1837a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1838a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18399c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18409c2b2975SHarish Zunjarrao return 0; 18419c2b2975SHarish Zunjarrao } 18429c2b2975SHarish Zunjarrao 18439c2b2975SHarish Zunjarrao static int 18449c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18459c2b2975SHarish Zunjarrao { 18469c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18479c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18489c2b2975SHarish Zunjarrao uint32_t i; 18499c2b2975SHarish Zunjarrao __le32 entries; 18509c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18519c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18529c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18539c2b2975SHarish Zunjarrao int mn_present = 0; 18549c2b2975SHarish Zunjarrao uint32_t flagbit; 18559c2b2975SHarish Zunjarrao 18569c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18579c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18589c2b2975SHarish Zunjarrao if (!ptab_desc) 18599c2b2975SHarish Zunjarrao return -1; 18609c2b2975SHarish Zunjarrao 18619c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18629c2b2975SHarish Zunjarrao 18639c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18649c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18659c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18669c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18679c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18689c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18699c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18709c2b2975SHarish Zunjarrao 18719c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18729c2b2975SHarish Zunjarrao 18739c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18749c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18759c2b2975SHarish Zunjarrao return 0; 18769c2b2975SHarish Zunjarrao } 18779c2b2975SHarish Zunjarrao } 18789c2b2975SHarish Zunjarrao return -1; 18799c2b2975SHarish Zunjarrao } 18809c2b2975SHarish Zunjarrao 18819c2b2975SHarish Zunjarrao int 18829c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18839c2b2975SHarish Zunjarrao { 18849c2b2975SHarish Zunjarrao __le32 val; 18859c2b2975SHarish Zunjarrao uint32_t min_size; 18869c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18879c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18889c2b2975SHarish Zunjarrao 18899c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18909c2b2975SHarish Zunjarrao 18919c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18929c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18939c2b2975SHarish Zunjarrao return -EINVAL; 18949c2b2975SHarish Zunjarrao 18959c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18969c2b2975SHarish Zunjarrao } else { 18979c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18989c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18999c2b2975SHarish Zunjarrao return -EINVAL; 19009c2b2975SHarish Zunjarrao 19019c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 19029c2b2975SHarish Zunjarrao } 19039c2b2975SHarish Zunjarrao 19049c2b2975SHarish Zunjarrao if (fw->size < min_size) 19059c2b2975SHarish Zunjarrao return -EINVAL; 1906a9083016SGiridhar Malavali return 0; 1907a9083016SGiridhar Malavali } 1908a9083016SGiridhar Malavali 190977e334d2SGiridhar Malavali static int 191077e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1911a9083016SGiridhar Malavali { 1912a9083016SGiridhar Malavali u32 val = 0; 1913a9083016SGiridhar Malavali int retries = 60; 19147c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1915a9083016SGiridhar Malavali 1916a9083016SGiridhar Malavali do { 1917a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1918a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1919a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1920a9083016SGiridhar Malavali 1921a9083016SGiridhar Malavali switch (val) { 1922a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1923a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1924a9083016SGiridhar Malavali return QLA_SUCCESS; 1925a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1926a9083016SGiridhar Malavali break; 1927a9083016SGiridhar Malavali default: 1928a9083016SGiridhar Malavali break; 1929a9083016SGiridhar Malavali } 19307c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19317c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1932a9083016SGiridhar Malavali val, retries); 1933a9083016SGiridhar Malavali 1934a9083016SGiridhar Malavali msleep(500); 1935a9083016SGiridhar Malavali 1936a9083016SGiridhar Malavali } while (--retries); 1937a9083016SGiridhar Malavali 19387c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1939a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1940a9083016SGiridhar Malavali 1941a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1942a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1943a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1944a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1945a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1946a9083016SGiridhar Malavali } 1947a9083016SGiridhar Malavali 194877e334d2SGiridhar Malavali static int 194977e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1950a9083016SGiridhar Malavali { 1951a9083016SGiridhar Malavali u32 val = 0; 1952a9083016SGiridhar Malavali int retries = 60; 19537c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1954a9083016SGiridhar Malavali 1955a9083016SGiridhar Malavali do { 1956a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1957a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1958a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1959a9083016SGiridhar Malavali 1960a9083016SGiridhar Malavali switch (val) { 1961a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1962a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1963a9083016SGiridhar Malavali return QLA_SUCCESS; 1964a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1965a9083016SGiridhar Malavali break; 1966a9083016SGiridhar Malavali default: 1967a9083016SGiridhar Malavali break; 1968a9083016SGiridhar Malavali } 19697c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19707c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1971a9083016SGiridhar Malavali val, retries); 1972a9083016SGiridhar Malavali 1973a9083016SGiridhar Malavali msleep(500); 1974a9083016SGiridhar Malavali 1975a9083016SGiridhar Malavali } while (--retries); 1976a9083016SGiridhar Malavali 19777c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19787c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1979a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1980a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1981a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1982a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1983a9083016SGiridhar Malavali } 1984a9083016SGiridhar Malavali 1985a9083016SGiridhar Malavali /* ISR related functions */ 1986a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1987a9083016SGiridhar Malavali ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1988a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1989a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1990a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1991a9083016SGiridhar Malavali }; 1992a9083016SGiridhar Malavali 1993a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_status[8] = { 1994a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1995a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1996a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1997a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1998a9083016SGiridhar Malavali }; 1999a9083016SGiridhar Malavali 2000a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 2001a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 2002a9083016SGiridhar Malavali 2003a9083016SGiridhar Malavali /* 2004a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 2005a9083016SGiridhar Malavali * @ha: SCSI driver HA context 2006a9083016SGiridhar Malavali * @mb0: Mailbox0 register 2007a9083016SGiridhar Malavali */ 200877e334d2SGiridhar Malavali static void 2009a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2010a9083016SGiridhar Malavali { 2011a9083016SGiridhar Malavali uint16_t cnt; 2012a9083016SGiridhar Malavali uint16_t __iomem *wptr; 2013a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2014a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2015a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2016a9083016SGiridhar Malavali 2017a9083016SGiridhar Malavali /* Load return mailbox registers. */ 2018a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 2019a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 2020a9083016SGiridhar Malavali 2021a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2022a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2023a9083016SGiridhar Malavali wptr++; 2024a9083016SGiridhar Malavali } 2025a9083016SGiridhar Malavali 2026a9083016SGiridhar Malavali if (ha->mcp) { 20277c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5052, 20287c3df132SSaurav Kashyap "Got mailbox completion. cmd=%x.\n", ha->mcp->mb[0]); 2029a9083016SGiridhar Malavali } else { 20307c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 20317c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 2032a9083016SGiridhar Malavali } 2033a9083016SGiridhar Malavali } 2034a9083016SGiridhar Malavali 2035a9083016SGiridhar Malavali /* 2036a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2037a9083016SGiridhar Malavali * @irq: 2038a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2039a9083016SGiridhar Malavali * @regs: 2040a9083016SGiridhar Malavali * 2041a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2042a9083016SGiridhar Malavali * 2043a9083016SGiridhar Malavali * Returns handled flag. 2044a9083016SGiridhar Malavali */ 2045a9083016SGiridhar Malavali irqreturn_t 2046a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2047a9083016SGiridhar Malavali { 2048a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2049a9083016SGiridhar Malavali struct qla_hw_data *ha; 2050a9083016SGiridhar Malavali struct rsp_que *rsp; 2051a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2052a9083016SGiridhar Malavali int status = 0, status1 = 0; 2053a9083016SGiridhar Malavali unsigned long flags; 2054a9083016SGiridhar Malavali unsigned long iter; 20557c3df132SSaurav Kashyap uint32_t stat = 0; 2056a9083016SGiridhar Malavali uint16_t mb[4]; 2057a9083016SGiridhar Malavali 2058a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2059a9083016SGiridhar Malavali if (!rsp) { 2060a9083016SGiridhar Malavali printk(KERN_INFO 20617c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2062a9083016SGiridhar Malavali return IRQ_NONE; 2063a9083016SGiridhar Malavali } 2064a9083016SGiridhar Malavali ha = rsp->hw; 2065a9083016SGiridhar Malavali 2066a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2067a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2068a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2069a9083016SGiridhar Malavali return IRQ_NONE; 2070a9083016SGiridhar Malavali 2071a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2072a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2073a9083016SGiridhar Malavali return IRQ_NONE; 2074a9083016SGiridhar Malavali } 2075a9083016SGiridhar Malavali 2076a9083016SGiridhar Malavali /* clear the interrupt */ 2077a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2078a9083016SGiridhar Malavali 2079a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2080a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2081a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2082a9083016SGiridhar Malavali 2083a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2084a9083016SGiridhar Malavali 2085a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2086a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2087a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2088a9083016SGiridhar Malavali 2089a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2090a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2091a9083016SGiridhar Malavali 2092a9083016SGiridhar Malavali switch (stat & 0xff) { 2093a9083016SGiridhar Malavali case 0x1: 2094a9083016SGiridhar Malavali case 0x2: 2095a9083016SGiridhar Malavali case 0x10: 2096a9083016SGiridhar Malavali case 0x11: 2097a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2098a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2099a9083016SGiridhar Malavali break; 2100a9083016SGiridhar Malavali case 0x12: 2101a9083016SGiridhar Malavali mb[0] = MSW(stat); 2102a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2103a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2104a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2105a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2106a9083016SGiridhar Malavali break; 2107a9083016SGiridhar Malavali case 0x13: 2108a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2109a9083016SGiridhar Malavali break; 2110a9083016SGiridhar Malavali default: 21117c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2112a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21137c3df132SSaurav Kashyap stat & 0xff); 2114a9083016SGiridhar Malavali break; 2115a9083016SGiridhar Malavali } 2116a9083016SGiridhar Malavali } 2117a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2118a9083016SGiridhar Malavali } 2119a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2120a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2121a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2122a9083016SGiridhar Malavali 2123a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2124a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21257c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x503d, 21267c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2127a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2128a9083016SGiridhar Malavali #endif 2129a9083016SGiridhar Malavali 2130a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2131a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2132a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2133a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2134a9083016SGiridhar Malavali } 2135a9083016SGiridhar Malavali return IRQ_HANDLED; 2136a9083016SGiridhar Malavali } 2137a9083016SGiridhar Malavali 2138a9083016SGiridhar Malavali irqreturn_t 2139a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2140a9083016SGiridhar Malavali { 2141a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2142a9083016SGiridhar Malavali struct qla_hw_data *ha; 2143a9083016SGiridhar Malavali struct rsp_que *rsp; 2144a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2145a9083016SGiridhar Malavali int status = 0; 2146a9083016SGiridhar Malavali unsigned long flags; 21477c3df132SSaurav Kashyap uint32_t stat = 0; 2148a9083016SGiridhar Malavali uint16_t mb[4]; 2149a9083016SGiridhar Malavali 2150a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2151a9083016SGiridhar Malavali if (!rsp) { 2152a9083016SGiridhar Malavali printk(KERN_INFO 21537c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2154a9083016SGiridhar Malavali return IRQ_NONE; 2155a9083016SGiridhar Malavali } 2156a9083016SGiridhar Malavali ha = rsp->hw; 2157a9083016SGiridhar Malavali 2158a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2159a9083016SGiridhar Malavali 2160a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2161a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2162a9083016SGiridhar Malavali do { 2163a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2164a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2165a9083016SGiridhar Malavali 2166a9083016SGiridhar Malavali switch (stat & 0xff) { 2167a9083016SGiridhar Malavali case 0x1: 2168a9083016SGiridhar Malavali case 0x2: 2169a9083016SGiridhar Malavali case 0x10: 2170a9083016SGiridhar Malavali case 0x11: 2171a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2172a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2173a9083016SGiridhar Malavali break; 2174a9083016SGiridhar Malavali case 0x12: 2175a9083016SGiridhar Malavali mb[0] = MSW(stat); 2176a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2177a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2178a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2179a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2180a9083016SGiridhar Malavali break; 2181a9083016SGiridhar Malavali case 0x13: 2182a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2183a9083016SGiridhar Malavali break; 2184a9083016SGiridhar Malavali default: 21857c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2186a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21877c3df132SSaurav Kashyap stat & 0xff); 2188a9083016SGiridhar Malavali break; 2189a9083016SGiridhar Malavali } 2190a9083016SGiridhar Malavali } 2191a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2192a9083016SGiridhar Malavali } while (0); 2193a9083016SGiridhar Malavali 2194a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2195a9083016SGiridhar Malavali 2196a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2197a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x5044, 21997c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2200a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2201a9083016SGiridhar Malavali #endif 2202a9083016SGiridhar Malavali 2203a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2204a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2205a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2206a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2207a9083016SGiridhar Malavali } 2208a9083016SGiridhar Malavali return IRQ_HANDLED; 2209a9083016SGiridhar Malavali } 2210a9083016SGiridhar Malavali 2211a9083016SGiridhar Malavali irqreturn_t 2212a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2213a9083016SGiridhar Malavali { 2214a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2215a9083016SGiridhar Malavali struct qla_hw_data *ha; 2216a9083016SGiridhar Malavali struct rsp_que *rsp; 2217a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 22183553d343SSaurav Kashyap unsigned long flags; 2219a9083016SGiridhar Malavali 2220a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2221a9083016SGiridhar Malavali if (!rsp) { 2222a9083016SGiridhar Malavali printk(KERN_INFO 22237c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2224a9083016SGiridhar Malavali return IRQ_NONE; 2225a9083016SGiridhar Malavali } 2226a9083016SGiridhar Malavali 2227a9083016SGiridhar Malavali ha = rsp->hw; 2228a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 22293553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2230a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2231a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2232a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 22333553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2234a9083016SGiridhar Malavali return IRQ_HANDLED; 2235a9083016SGiridhar Malavali } 2236a9083016SGiridhar Malavali 2237a9083016SGiridhar Malavali void 2238a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2239a9083016SGiridhar Malavali { 2240a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2241a9083016SGiridhar Malavali struct qla_hw_data *ha; 2242a9083016SGiridhar Malavali struct rsp_que *rsp; 2243a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2244a9083016SGiridhar Malavali int status = 0; 2245a9083016SGiridhar Malavali uint32_t stat; 2246a9083016SGiridhar Malavali uint16_t mb[4]; 2247a9083016SGiridhar Malavali unsigned long flags; 2248a9083016SGiridhar Malavali 2249a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2250a9083016SGiridhar Malavali if (!rsp) { 2251a9083016SGiridhar Malavali printk(KERN_INFO 22527c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2253a9083016SGiridhar Malavali return; 2254a9083016SGiridhar Malavali } 2255a9083016SGiridhar Malavali ha = rsp->hw; 2256a9083016SGiridhar Malavali 2257a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2258a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2259a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2260a9083016SGiridhar Malavali 2261a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2262a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2263a9083016SGiridhar Malavali switch (stat & 0xff) { 2264a9083016SGiridhar Malavali case 0x1: 2265a9083016SGiridhar Malavali case 0x2: 2266a9083016SGiridhar Malavali case 0x10: 2267a9083016SGiridhar Malavali case 0x11: 2268a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2269a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2270a9083016SGiridhar Malavali break; 2271a9083016SGiridhar Malavali case 0x12: 2272a9083016SGiridhar Malavali mb[0] = MSW(stat); 2273a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2274a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2275a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2276a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2277a9083016SGiridhar Malavali break; 2278a9083016SGiridhar Malavali case 0x13: 2279a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2280a9083016SGiridhar Malavali break; 2281a9083016SGiridhar Malavali default: 22827c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22837c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22847c3df132SSaurav Kashyap stat * 0xff); 2285a9083016SGiridhar Malavali break; 2286a9083016SGiridhar Malavali } 2287a9083016SGiridhar Malavali } 2288a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2289a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2290a9083016SGiridhar Malavali } 2291a9083016SGiridhar Malavali 2292a9083016SGiridhar Malavali void 2293a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2294a9083016SGiridhar Malavali { 2295a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2296a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2297a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2298a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2299a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2300a9083016SGiridhar Malavali ha->interrupts_on = 1; 2301a9083016SGiridhar Malavali } 2302a9083016SGiridhar Malavali 2303a9083016SGiridhar Malavali void 2304a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2305a9083016SGiridhar Malavali { 2306a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2307a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2308a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2309a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2310a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2311a9083016SGiridhar Malavali ha->interrupts_on = 0; 2312a9083016SGiridhar Malavali } 2313a9083016SGiridhar Malavali 2314a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2315a9083016SGiridhar Malavali { 2316a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2317a9083016SGiridhar Malavali 2318a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2319a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2320a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2321a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2322a9083016SGiridhar Malavali ha->curr_window = 255; 2323a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2324a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2325a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2326a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2327a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2328a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2329a9083016SGiridhar Malavali } 2330a9083016SGiridhar Malavali 2331a5b36321SLalit Chandivade inline void 2332a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2333a9083016SGiridhar Malavali { 2334a9083016SGiridhar Malavali uint32_t drv_active; 2335a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2336a9083016SGiridhar Malavali 2337a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2338a9083016SGiridhar Malavali 2339a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2340a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 234177e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 234277e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2343a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2344a9083016SGiridhar Malavali } 234577e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2346a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2347a9083016SGiridhar Malavali } 2348a9083016SGiridhar Malavali 2349a9083016SGiridhar Malavali inline void 2350a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2351a9083016SGiridhar Malavali { 2352a9083016SGiridhar Malavali uint32_t drv_active; 2353a9083016SGiridhar Malavali 2354a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 235577e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2356a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2357a9083016SGiridhar Malavali } 2358a9083016SGiridhar Malavali 2359a9083016SGiridhar Malavali static inline int 2360a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2361a9083016SGiridhar Malavali { 2362a9083016SGiridhar Malavali uint32_t drv_state; 2363a9083016SGiridhar Malavali int rval; 2364a9083016SGiridhar Malavali 236508de2844SGiridhar Malavali if (ha->flags.isp82xx_reset_owner) 236608de2844SGiridhar Malavali return 1; 236708de2844SGiridhar Malavali else { 2368a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 236977e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2370a9083016SGiridhar Malavali return rval; 2371a9083016SGiridhar Malavali } 237208de2844SGiridhar Malavali } 2373a9083016SGiridhar Malavali 2374a9083016SGiridhar Malavali static inline void 2375a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2376a9083016SGiridhar Malavali { 2377a9083016SGiridhar Malavali uint32_t drv_state; 2378a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2379a9083016SGiridhar Malavali 2380a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2381a9083016SGiridhar Malavali 2382a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2383a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 238477e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2385a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2386a9083016SGiridhar Malavali } 2387a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 238808de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 238908de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2390a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2391a9083016SGiridhar Malavali } 2392a9083016SGiridhar Malavali 2393a9083016SGiridhar Malavali static inline void 2394a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2395a9083016SGiridhar Malavali { 2396a9083016SGiridhar Malavali uint32_t drv_state; 2397a9083016SGiridhar Malavali 2398a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2399a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2400a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2401a9083016SGiridhar Malavali } 2402a9083016SGiridhar Malavali 2403a9083016SGiridhar Malavali static inline void 2404a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2405a9083016SGiridhar Malavali { 2406a9083016SGiridhar Malavali uint32_t qsnt_state; 2407a9083016SGiridhar Malavali 2408a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2409a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2410a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2411a9083016SGiridhar Malavali } 2412a9083016SGiridhar Malavali 2413579d12b5SSaurav Kashyap void 2414579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2415579d12b5SSaurav Kashyap { 2416579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2417579d12b5SSaurav Kashyap uint32_t qsnt_state; 2418579d12b5SSaurav Kashyap 2419579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2420579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2421579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2422579d12b5SSaurav Kashyap } 2423579d12b5SSaurav Kashyap 242477e334d2SGiridhar Malavali static int 242577e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2426a9083016SGiridhar Malavali { 2427a9083016SGiridhar Malavali int rst; 2428a9083016SGiridhar Malavali struct fw_blob *blob; 2429a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2430a9083016SGiridhar Malavali 2431a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24327c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24337c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2434a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2435a9083016SGiridhar Malavali } 2436a9083016SGiridhar Malavali udelay(500); 2437a9083016SGiridhar Malavali 2438a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2439a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2440a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2441a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2442a9083016SGiridhar Malavali 2443a9083016SGiridhar Malavali /* 2444a9083016SGiridhar Malavali * FW Load priority: 2445a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2446a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2447a9083016SGiridhar Malavali */ 2448a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2449a9083016SGiridhar Malavali goto try_blob_fw; 2450a9083016SGiridhar Malavali 24517c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24527c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2453a9083016SGiridhar Malavali 2454a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24557c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 24567c3df132SSaurav Kashyap "Firmware loaded successully from flash.\n"); 2457a9083016SGiridhar Malavali return QLA_SUCCESS; 2458875efad7SChad Dupuis } else { 24597c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24607c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2461a9083016SGiridhar Malavali } 2462875efad7SChad Dupuis 2463a9083016SGiridhar Malavali try_blob_fw: 24647c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24657c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2466a9083016SGiridhar Malavali 2467a9083016SGiridhar Malavali /* Load firmware blob. */ 2468a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2469a9083016SGiridhar Malavali if (!blob) { 24707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 24717c3df132SSaurav Kashyap "Firmware image not preset.\n"); 2472a9083016SGiridhar Malavali goto fw_load_failed; 2473a9083016SGiridhar Malavali } 2474a9083016SGiridhar Malavali 24759c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24769c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24779c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24789c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24799c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24809c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24817c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24827c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24839c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24849c2b2975SHarish Zunjarrao } 24859c2b2975SHarish Zunjarrao } 24869c2b2975SHarish Zunjarrao 2487a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24887c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24897c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2490a9083016SGiridhar Malavali return QLA_SUCCESS; 2491a9083016SGiridhar Malavali } else { 24927c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24937c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2494a9083016SGiridhar Malavali blob->fw = NULL; 2495a9083016SGiridhar Malavali blob = NULL; 2496a9083016SGiridhar Malavali goto fw_load_failed; 2497a9083016SGiridhar Malavali } 2498a9083016SGiridhar Malavali return QLA_SUCCESS; 2499a9083016SGiridhar Malavali 2500a9083016SGiridhar Malavali fw_load_failed: 2501a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2502a9083016SGiridhar Malavali } 2503a9083016SGiridhar Malavali 2504a5b36321SLalit Chandivade int 2505a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2506a9083016SGiridhar Malavali { 2507a9083016SGiridhar Malavali int pcie_cap; 2508a9083016SGiridhar Malavali uint16_t lnk; 2509a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2510a9083016SGiridhar Malavali 2511a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 251277e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2513a9083016SGiridhar Malavali 25143711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 25153711333dSGiridhar Malavali * of 0 before resetting the hardware 25163711333dSGiridhar Malavali */ 25173711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25183711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25193711333dSGiridhar Malavali 2520a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2521a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2522a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2523a9083016SGiridhar Malavali 2524a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25257c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25267c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2527a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2528a9083016SGiridhar Malavali } 2529a9083016SGiridhar Malavali 2530a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2531a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25327c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25337c3df132SSaurav Kashyap "Error during card handshake.\n"); 2534a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2535a9083016SGiridhar Malavali } 2536a9083016SGiridhar Malavali 2537a9083016SGiridhar Malavali /* Negotiated Link width */ 2538a9083016SGiridhar Malavali pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2539a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2540a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2541a9083016SGiridhar Malavali 2542a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2543a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2544a9083016SGiridhar Malavali } 2545a9083016SGiridhar Malavali 2546a9083016SGiridhar Malavali static inline int 2547a9083016SGiridhar Malavali qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2548a9083016SGiridhar Malavali uint16_t tot_dsds) 2549a9083016SGiridhar Malavali { 2550a9083016SGiridhar Malavali uint32_t *cur_dsd = NULL; 2551a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2552a9083016SGiridhar Malavali struct qla_hw_data *ha; 2553a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2554a9083016SGiridhar Malavali struct scatterlist *cur_seg; 2555a9083016SGiridhar Malavali uint32_t *dsd_seg; 2556a9083016SGiridhar Malavali void *next_dsd; 2557a9083016SGiridhar Malavali uint8_t avail_dsds; 2558a9083016SGiridhar Malavali uint8_t first_iocb = 1; 2559a9083016SGiridhar Malavali uint32_t dsd_list_len; 2560a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2561a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2562a9083016SGiridhar Malavali 2563a9083016SGiridhar Malavali cmd = sp->cmd; 2564a9083016SGiridhar Malavali 2565a9083016SGiridhar Malavali /* Update entry type to indicate Command Type 3 IOCB */ 2566a9083016SGiridhar Malavali *((uint32_t *)(&cmd_pkt->entry_type)) = 2567a9083016SGiridhar Malavali __constant_cpu_to_le32(COMMAND_TYPE_6); 2568a9083016SGiridhar Malavali 2569a9083016SGiridhar Malavali /* No data transfer */ 2570a9083016SGiridhar Malavali if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2571a9083016SGiridhar Malavali cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2572a9083016SGiridhar Malavali return 0; 2573a9083016SGiridhar Malavali } 2574a9083016SGiridhar Malavali 2575a9083016SGiridhar Malavali vha = sp->fcport->vha; 2576a9083016SGiridhar Malavali ha = vha->hw; 2577a9083016SGiridhar Malavali 2578a9083016SGiridhar Malavali /* Set transfer direction */ 2579a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2580a9083016SGiridhar Malavali cmd_pkt->control_flags = 2581a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_WRITE_DATA); 2582a9083016SGiridhar Malavali ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2583a9083016SGiridhar Malavali } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2584a9083016SGiridhar Malavali cmd_pkt->control_flags = 2585a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_READ_DATA); 2586a9083016SGiridhar Malavali ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2587a9083016SGiridhar Malavali } 2588a9083016SGiridhar Malavali 2589a9083016SGiridhar Malavali cur_seg = scsi_sglist(cmd); 2590a9083016SGiridhar Malavali ctx = sp->ctx; 2591a9083016SGiridhar Malavali 2592a9083016SGiridhar Malavali while (tot_dsds) { 2593a9083016SGiridhar Malavali avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2594a9083016SGiridhar Malavali QLA_DSDS_PER_IOCB : tot_dsds; 2595a9083016SGiridhar Malavali tot_dsds -= avail_dsds; 2596a9083016SGiridhar Malavali dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2597a9083016SGiridhar Malavali 2598a9083016SGiridhar Malavali dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2599a9083016SGiridhar Malavali struct dsd_dma, list); 2600a9083016SGiridhar Malavali next_dsd = dsd_ptr->dsd_addr; 2601a9083016SGiridhar Malavali list_del(&dsd_ptr->list); 2602a9083016SGiridhar Malavali ha->gbl_dsd_avail--; 2603a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2604a9083016SGiridhar Malavali ctx->dsd_use_cnt++; 2605a9083016SGiridhar Malavali ha->gbl_dsd_inuse++; 2606a9083016SGiridhar Malavali 2607a9083016SGiridhar Malavali if (first_iocb) { 2608a9083016SGiridhar Malavali first_iocb = 0; 2609a9083016SGiridhar Malavali dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2610a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2611a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 261263d92d3eSSaurav Kashyap cmd_pkt->fcp_data_dseg_len = cpu_to_le32(dsd_list_len); 2613a9083016SGiridhar Malavali } else { 2614a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2615a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2616fa96d927SAndrew Vasquez *cur_dsd++ = cpu_to_le32(dsd_list_len); 2617a9083016SGiridhar Malavali } 2618a9083016SGiridhar Malavali cur_dsd = (uint32_t *)next_dsd; 2619a9083016SGiridhar Malavali while (avail_dsds) { 2620a9083016SGiridhar Malavali dma_addr_t sle_dma; 2621a9083016SGiridhar Malavali 2622a9083016SGiridhar Malavali sle_dma = sg_dma_address(cur_seg); 2623a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2624a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2625a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2626aa5cbf8aSGiridhar Malavali cur_seg = sg_next(cur_seg); 2627a9083016SGiridhar Malavali avail_dsds--; 2628a9083016SGiridhar Malavali } 2629a9083016SGiridhar Malavali } 2630a9083016SGiridhar Malavali 2631a9083016SGiridhar Malavali /* Null termination */ 2632a9083016SGiridhar Malavali *cur_dsd++ = 0; 2633a9083016SGiridhar Malavali *cur_dsd++ = 0; 2634a9083016SGiridhar Malavali *cur_dsd++ = 0; 2635a9083016SGiridhar Malavali cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2636a9083016SGiridhar Malavali return 0; 2637a9083016SGiridhar Malavali } 2638a9083016SGiridhar Malavali 2639a9083016SGiridhar Malavali /* 2640a9083016SGiridhar Malavali * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2641a9083016SGiridhar Malavali * for Command Type 6. 2642a9083016SGiridhar Malavali * 2643a9083016SGiridhar Malavali * @dsds: number of data segment decriptors needed 2644a9083016SGiridhar Malavali * 2645a9083016SGiridhar Malavali * Returns the number of dsd list needed to store @dsds. 2646a9083016SGiridhar Malavali */ 2647a9083016SGiridhar Malavali inline uint16_t 2648a9083016SGiridhar Malavali qla82xx_calc_dsd_lists(uint16_t dsds) 2649a9083016SGiridhar Malavali { 2650a9083016SGiridhar Malavali uint16_t dsd_lists = 0; 2651a9083016SGiridhar Malavali 2652a9083016SGiridhar Malavali dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2653a9083016SGiridhar Malavali if (dsds % QLA_DSDS_PER_IOCB) 2654a9083016SGiridhar Malavali dsd_lists++; 2655a9083016SGiridhar Malavali return dsd_lists; 2656a9083016SGiridhar Malavali } 2657a9083016SGiridhar Malavali 2658a9083016SGiridhar Malavali /* 2659a9083016SGiridhar Malavali * qla82xx_start_scsi() - Send a SCSI command to the ISP 2660a9083016SGiridhar Malavali * @sp: command to send to the ISP 2661a9083016SGiridhar Malavali * 266225985edcSLucas De Marchi * Returns non-zero if a failure occurred, else zero. 2663a9083016SGiridhar Malavali */ 2664a9083016SGiridhar Malavali int 2665a9083016SGiridhar Malavali qla82xx_start_scsi(srb_t *sp) 2666a9083016SGiridhar Malavali { 2667a9083016SGiridhar Malavali int ret, nseg; 2668a9083016SGiridhar Malavali unsigned long flags; 2669a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2670a9083016SGiridhar Malavali uint32_t *clr_ptr; 2671a9083016SGiridhar Malavali uint32_t index; 2672a9083016SGiridhar Malavali uint32_t handle; 2673a9083016SGiridhar Malavali uint16_t cnt; 2674a9083016SGiridhar Malavali uint16_t req_cnt; 2675a9083016SGiridhar Malavali uint16_t tot_dsds; 2676a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2677a9083016SGiridhar Malavali uint32_t dbval; 2678a9083016SGiridhar Malavali uint32_t *fcp_dl; 2679a9083016SGiridhar Malavali uint8_t additional_cdb_len; 2680a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2681a9083016SGiridhar Malavali struct scsi_qla_host *vha = sp->fcport->vha; 2682a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2683a9083016SGiridhar Malavali struct req_que *req = NULL; 2684a9083016SGiridhar Malavali struct rsp_que *rsp = NULL; 2685ff2fc42eSAndrew Vasquez char tag[2]; 2686a9083016SGiridhar Malavali 2687a9083016SGiridhar Malavali /* Setup device pointers. */ 2688a9083016SGiridhar Malavali ret = 0; 2689a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2690a9083016SGiridhar Malavali cmd = sp->cmd; 2691a9083016SGiridhar Malavali req = vha->req; 2692a9083016SGiridhar Malavali rsp = ha->rsp_q_map[0]; 2693a9083016SGiridhar Malavali 2694a9083016SGiridhar Malavali /* So we know we haven't pci_map'ed anything yet */ 2695a9083016SGiridhar Malavali tot_dsds = 0; 2696a9083016SGiridhar Malavali 2697a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2698a9083016SGiridhar Malavali 2699a9083016SGiridhar Malavali /* Send marker if required */ 2700a9083016SGiridhar Malavali if (vha->marker_needed != 0) { 2701a9083016SGiridhar Malavali if (qla2x00_marker(vha, req, 27027c3df132SSaurav Kashyap rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) { 27037c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x300c, 27047c3df132SSaurav Kashyap "qla2x00_marker failed for cmd=%p.\n", cmd); 2705a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 27067c3df132SSaurav Kashyap } 2707a9083016SGiridhar Malavali vha->marker_needed = 0; 2708a9083016SGiridhar Malavali } 2709a9083016SGiridhar Malavali 2710a9083016SGiridhar Malavali /* Acquire ring specific lock */ 2711a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2712a9083016SGiridhar Malavali 2713a9083016SGiridhar Malavali /* Check for room in outstanding command list. */ 2714a9083016SGiridhar Malavali handle = req->current_outstanding_cmd; 2715a9083016SGiridhar Malavali for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2716a9083016SGiridhar Malavali handle++; 2717a9083016SGiridhar Malavali if (handle == MAX_OUTSTANDING_COMMANDS) 2718a9083016SGiridhar Malavali handle = 1; 2719a9083016SGiridhar Malavali if (!req->outstanding_cmds[handle]) 2720a9083016SGiridhar Malavali break; 2721a9083016SGiridhar Malavali } 2722a9083016SGiridhar Malavali if (index == MAX_OUTSTANDING_COMMANDS) 2723a9083016SGiridhar Malavali goto queuing_error; 2724a9083016SGiridhar Malavali 2725a9083016SGiridhar Malavali /* Map the sg table so we have an accurate count of sg entries needed */ 2726a9083016SGiridhar Malavali if (scsi_sg_count(cmd)) { 2727a9083016SGiridhar Malavali nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2728a9083016SGiridhar Malavali scsi_sg_count(cmd), cmd->sc_data_direction); 2729a9083016SGiridhar Malavali if (unlikely(!nseg)) 2730a9083016SGiridhar Malavali goto queuing_error; 2731a9083016SGiridhar Malavali } else 2732a9083016SGiridhar Malavali nseg = 0; 2733a9083016SGiridhar Malavali 2734a9083016SGiridhar Malavali tot_dsds = nseg; 2735a9083016SGiridhar Malavali 2736a9083016SGiridhar Malavali if (tot_dsds > ql2xshiftctondsd) { 2737a9083016SGiridhar Malavali struct cmd_type_6 *cmd_pkt; 2738a9083016SGiridhar Malavali uint16_t more_dsd_lists = 0; 2739a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2740a9083016SGiridhar Malavali uint16_t i; 2741a9083016SGiridhar Malavali 2742a9083016SGiridhar Malavali more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 27437c3df132SSaurav Kashyap if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) { 27447c3df132SSaurav Kashyap ql_dbg(ql_dbg_io, vha, 0x300d, 27457c3df132SSaurav Kashyap "Num of DSD list %d is than %d for cmd=%p.\n", 27467c3df132SSaurav Kashyap more_dsd_lists + ha->gbl_dsd_inuse, NUM_DSD_CHAIN, 27477c3df132SSaurav Kashyap cmd); 2748a9083016SGiridhar Malavali goto queuing_error; 27497c3df132SSaurav Kashyap } 2750a9083016SGiridhar Malavali 2751a9083016SGiridhar Malavali if (more_dsd_lists <= ha->gbl_dsd_avail) 2752a9083016SGiridhar Malavali goto sufficient_dsds; 2753a9083016SGiridhar Malavali else 2754a9083016SGiridhar Malavali more_dsd_lists -= ha->gbl_dsd_avail; 2755a9083016SGiridhar Malavali 2756a9083016SGiridhar Malavali for (i = 0; i < more_dsd_lists; i++) { 2757a9083016SGiridhar Malavali dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 27587c3df132SSaurav Kashyap if (!dsd_ptr) { 27597c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x300e, 27607c3df132SSaurav Kashyap "Failed to allocate memory for dsd_dma " 27617c3df132SSaurav Kashyap "for cmd=%p.\n", cmd); 2762a9083016SGiridhar Malavali goto queuing_error; 27637c3df132SSaurav Kashyap } 2764a9083016SGiridhar Malavali 2765a9083016SGiridhar Malavali dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2766a9083016SGiridhar Malavali GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2767a9083016SGiridhar Malavali if (!dsd_ptr->dsd_addr) { 2768a9083016SGiridhar Malavali kfree(dsd_ptr); 27697c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x300f, 27707c3df132SSaurav Kashyap "Failed to allocate memory for dsd_addr " 27717c3df132SSaurav Kashyap "for cmd=%p.\n", cmd); 2772a9083016SGiridhar Malavali goto queuing_error; 2773a9083016SGiridhar Malavali } 2774a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2775a9083016SGiridhar Malavali ha->gbl_dsd_avail++; 2776a9083016SGiridhar Malavali } 2777a9083016SGiridhar Malavali 2778a9083016SGiridhar Malavali sufficient_dsds: 2779a9083016SGiridhar Malavali req_cnt = 1; 2780a9083016SGiridhar Malavali 27811bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 27821bd58b89SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 27831bd58b89SGiridhar Malavali ®->req_q_out[0]); 27841bd58b89SGiridhar Malavali if (req->ring_index < cnt) 27851bd58b89SGiridhar Malavali req->cnt = cnt - req->ring_index; 27861bd58b89SGiridhar Malavali else 27871bd58b89SGiridhar Malavali req->cnt = req->length - 27881bd58b89SGiridhar Malavali (req->ring_index - cnt); 27891bd58b89SGiridhar Malavali } 27901bd58b89SGiridhar Malavali 27911bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 27921bd58b89SGiridhar Malavali goto queuing_error; 27931bd58b89SGiridhar Malavali 2794a9083016SGiridhar Malavali ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2795a9083016SGiridhar Malavali if (!sp->ctx) { 27967c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x3010, 27977c3df132SSaurav Kashyap "Failed to allocate ctx for cmd=%p.\n", cmd); 2798a9083016SGiridhar Malavali goto queuing_error; 2799a9083016SGiridhar Malavali } 2800a9083016SGiridhar Malavali memset(ctx, 0, sizeof(struct ct6_dsd)); 2801a9083016SGiridhar Malavali ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2802a9083016SGiridhar Malavali GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2803a9083016SGiridhar Malavali if (!ctx->fcp_cmnd) { 28047c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x3011, 28057c3df132SSaurav Kashyap "Failed to allocate fcp_cmnd for cmd=%p.\n", cmd); 2806a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2807a9083016SGiridhar Malavali } 2808a9083016SGiridhar Malavali 2809a9083016SGiridhar Malavali /* Initialize the DSD list and dma handle */ 2810a9083016SGiridhar Malavali INIT_LIST_HEAD(&ctx->dsd_list); 2811a9083016SGiridhar Malavali ctx->dsd_use_cnt = 0; 2812a9083016SGiridhar Malavali 2813a9083016SGiridhar Malavali if (cmd->cmd_len > 16) { 2814a9083016SGiridhar Malavali additional_cdb_len = cmd->cmd_len - 16; 2815a9083016SGiridhar Malavali if ((cmd->cmd_len % 4) != 0) { 2816a9083016SGiridhar Malavali /* SCSI command bigger than 16 bytes must be 2817a9083016SGiridhar Malavali * multiple of 4 2818a9083016SGiridhar Malavali */ 28197c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x3012, 28207c3df132SSaurav Kashyap "scsi cmd len %d not multiple of 4 " 28217c3df132SSaurav Kashyap "for cmd=%p.\n", cmd->cmd_len, cmd); 2822a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2823a9083016SGiridhar Malavali } 2824a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2825a9083016SGiridhar Malavali } else { 2826a9083016SGiridhar Malavali additional_cdb_len = 0; 2827a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + 16 + 4; 2828a9083016SGiridhar Malavali } 2829a9083016SGiridhar Malavali 2830a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2831a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2832a9083016SGiridhar Malavali 2833a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2834a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2835a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2836a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2837a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2838a9083016SGiridhar Malavali 2839a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2840a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2841a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2842a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2843a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2844a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2845a9083016SGiridhar Malavali 2846a9083016SGiridhar Malavali /* Build IOCB segments */ 2847a9083016SGiridhar Malavali if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2848a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2849a9083016SGiridhar Malavali 2850a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 285185727e1fSMike Hernandez host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun)); 2852a9083016SGiridhar Malavali 285351cc9a8eSSaurav Kashyap /* build FCP_CMND IU */ 285451cc9a8eSSaurav Kashyap memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 285551cc9a8eSSaurav Kashyap int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 285651cc9a8eSSaurav Kashyap ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 285751cc9a8eSSaurav Kashyap 285851cc9a8eSSaurav Kashyap if (cmd->sc_data_direction == DMA_TO_DEVICE) 285951cc9a8eSSaurav Kashyap ctx->fcp_cmnd->additional_cdb_len |= 1; 286051cc9a8eSSaurav Kashyap else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 286151cc9a8eSSaurav Kashyap ctx->fcp_cmnd->additional_cdb_len |= 2; 286251cc9a8eSSaurav Kashyap 2863ff2fc42eSAndrew Vasquez /* 2864ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2865ff2fc42eSAndrew Vasquez */ 2866ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2867ff2fc42eSAndrew Vasquez switch (tag[0]) { 2868ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2869ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2870ff2fc42eSAndrew Vasquez TSK_HEAD_OF_QUEUE; 2871ff2fc42eSAndrew Vasquez break; 2872ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2873ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2874ff2fc42eSAndrew Vasquez TSK_ORDERED; 2875ff2fc42eSAndrew Vasquez break; 2876ff2fc42eSAndrew Vasquez } 2877ff2fc42eSAndrew Vasquez } 2878ff2fc42eSAndrew Vasquez 2879a9083016SGiridhar Malavali memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2880a9083016SGiridhar Malavali 2881a9083016SGiridhar Malavali fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2882a9083016SGiridhar Malavali additional_cdb_len); 2883a9083016SGiridhar Malavali *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2884a9083016SGiridhar Malavali 2885a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2886a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[0] = 2887a9083016SGiridhar Malavali cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2888a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[1] = 2889a9083016SGiridhar Malavali cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2890a9083016SGiridhar Malavali 2891a9083016SGiridhar Malavali sp->flags |= SRB_FCP_CMND_DMA_VALID; 2892a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2893a9083016SGiridhar Malavali /* Set total data segment count. */ 2894a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2895a9083016SGiridhar Malavali /* Specify response queue number where 2896a9083016SGiridhar Malavali * completion should happen 2897a9083016SGiridhar Malavali */ 2898a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2899a9083016SGiridhar Malavali } else { 2900a9083016SGiridhar Malavali struct cmd_type_7 *cmd_pkt; 29017c3df132SSaurav Kashyap req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); 2902a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 2903a9083016SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 2904a9083016SGiridhar Malavali ®->req_q_out[0]); 2905a9083016SGiridhar Malavali if (req->ring_index < cnt) 2906a9083016SGiridhar Malavali req->cnt = cnt - req->ring_index; 2907a9083016SGiridhar Malavali else 2908a9083016SGiridhar Malavali req->cnt = req->length - 2909a9083016SGiridhar Malavali (req->ring_index - cnt); 2910a9083016SGiridhar Malavali } 2911a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 2912a9083016SGiridhar Malavali goto queuing_error; 2913a9083016SGiridhar Malavali 2914a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 2915a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2916a9083016SGiridhar Malavali 2917a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2918a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 2919a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2920a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2921a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2922a9083016SGiridhar Malavali 2923a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2924a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2925a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2926a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2927a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2928a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2929a9083016SGiridhar Malavali 2930a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2931a9083016SGiridhar Malavali host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 2932a9083016SGiridhar Malavali sizeof(cmd_pkt->lun)); 2933a9083016SGiridhar Malavali 2934ff2fc42eSAndrew Vasquez /* 2935ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2936ff2fc42eSAndrew Vasquez */ 2937ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2938ff2fc42eSAndrew Vasquez switch (tag[0]) { 2939ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2940ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_HEAD_OF_QUEUE; 2941ff2fc42eSAndrew Vasquez break; 2942ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2943ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_ORDERED; 2944ff2fc42eSAndrew Vasquez break; 2945ff2fc42eSAndrew Vasquez } 2946ff2fc42eSAndrew Vasquez } 2947ff2fc42eSAndrew Vasquez 2948a9083016SGiridhar Malavali /* Load SCSI command packet. */ 2949a9083016SGiridhar Malavali memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 2950a9083016SGiridhar Malavali host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 2951a9083016SGiridhar Malavali 2952a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2953a9083016SGiridhar Malavali 2954a9083016SGiridhar Malavali /* Build IOCB segments */ 2955a9083016SGiridhar Malavali qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 2956a9083016SGiridhar Malavali 2957a9083016SGiridhar Malavali /* Set total data segment count. */ 2958a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2959a9083016SGiridhar Malavali /* Specify response queue number where 2960a9083016SGiridhar Malavali * completion should happen. 2961a9083016SGiridhar Malavali */ 2962a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2963a9083016SGiridhar Malavali 2964a9083016SGiridhar Malavali } 2965a9083016SGiridhar Malavali /* Build command packet. */ 2966a9083016SGiridhar Malavali req->current_outstanding_cmd = handle; 2967a9083016SGiridhar Malavali req->outstanding_cmds[handle] = sp; 2968a9083016SGiridhar Malavali sp->handle = handle; 2969a9083016SGiridhar Malavali sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 2970a9083016SGiridhar Malavali req->cnt -= req_cnt; 2971a9083016SGiridhar Malavali wmb(); 2972a9083016SGiridhar Malavali 2973a9083016SGiridhar Malavali /* Adjust ring index. */ 2974a9083016SGiridhar Malavali req->ring_index++; 2975a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2976a9083016SGiridhar Malavali req->ring_index = 0; 2977a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2978a9083016SGiridhar Malavali } else 2979a9083016SGiridhar Malavali req->ring_ptr++; 2980a9083016SGiridhar Malavali 2981a9083016SGiridhar Malavali sp->flags |= SRB_DMA_VALID; 2982a9083016SGiridhar Malavali 2983a9083016SGiridhar Malavali /* Set chip new ring index. */ 2984a9083016SGiridhar Malavali /* write, read and verify logic */ 2985a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2986a9083016SGiridhar Malavali if (ql2xdbwr) 2987a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2988a9083016SGiridhar Malavali else { 2989a9083016SGiridhar Malavali WRT_REG_DWORD( 2990a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2991a9083016SGiridhar Malavali dbval); 2992a9083016SGiridhar Malavali wmb(); 2993a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2994a9083016SGiridhar Malavali WRT_REG_DWORD( 2995a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2996a9083016SGiridhar Malavali dbval); 2997a9083016SGiridhar Malavali wmb(); 2998a9083016SGiridhar Malavali } 2999a9083016SGiridhar Malavali } 3000a9083016SGiridhar Malavali 3001a9083016SGiridhar Malavali /* Manage unprocessed RIO/ZIO commands in response queue. */ 3002a9083016SGiridhar Malavali if (vha->flags.process_response_queue && 3003a9083016SGiridhar Malavali rsp->ring_ptr->signature != RESPONSE_PROCESSED) 3004a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 3005a9083016SGiridhar Malavali 3006a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 3007a9083016SGiridhar Malavali return QLA_SUCCESS; 3008a9083016SGiridhar Malavali 3009a9083016SGiridhar Malavali queuing_error_fcp_cmnd: 3010a9083016SGiridhar Malavali dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 3011a9083016SGiridhar Malavali queuing_error: 3012a9083016SGiridhar Malavali if (tot_dsds) 3013a9083016SGiridhar Malavali scsi_dma_unmap(cmd); 3014a9083016SGiridhar Malavali 3015a9083016SGiridhar Malavali if (sp->ctx) { 3016a9083016SGiridhar Malavali mempool_free(sp->ctx, ha->ctx_mempool); 3017a9083016SGiridhar Malavali sp->ctx = NULL; 3018a9083016SGiridhar Malavali } 3019a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 3020a9083016SGiridhar Malavali 3021a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3022a9083016SGiridhar Malavali } 3023a9083016SGiridhar Malavali 302477e334d2SGiridhar Malavali static uint32_t * 3025a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 3026a9083016SGiridhar Malavali uint32_t length) 3027a9083016SGiridhar Malavali { 3028a9083016SGiridhar Malavali uint32_t i; 3029a9083016SGiridhar Malavali uint32_t val; 3030a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3031a9083016SGiridhar Malavali 3032a9083016SGiridhar Malavali /* Dword reads to flash. */ 3033a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 3034a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 30357c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 30367c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 3037a9083016SGiridhar Malavali goto done_read; 3038a9083016SGiridhar Malavali } 3039a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 3040a9083016SGiridhar Malavali } 3041a9083016SGiridhar Malavali done_read: 3042a9083016SGiridhar Malavali return dwptr; 3043a9083016SGiridhar Malavali } 3044a9083016SGiridhar Malavali 304577e334d2SGiridhar Malavali static int 3046a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 3047a9083016SGiridhar Malavali { 3048a9083016SGiridhar Malavali int ret; 3049a9083016SGiridhar Malavali uint32_t val; 30507c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3051a9083016SGiridhar Malavali 3052a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3053a9083016SGiridhar Malavali if (ret < 0) { 30547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 30557c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3056a9083016SGiridhar Malavali return ret; 3057a9083016SGiridhar Malavali } 3058a9083016SGiridhar Malavali 3059a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3060a9083016SGiridhar Malavali if (ret < 0) 3061a9083016SGiridhar Malavali goto done_unprotect; 3062a9083016SGiridhar Malavali 30630547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 3064a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3065a9083016SGiridhar Malavali if (ret < 0) { 30660547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3067a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 3068a9083016SGiridhar Malavali } 3069a9083016SGiridhar Malavali 3070a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 30717c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 30727c3df132SSaurav Kashyap "Write disable failed.\n"); 3073a9083016SGiridhar Malavali 3074a9083016SGiridhar Malavali done_unprotect: 3075d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3076a9083016SGiridhar Malavali return ret; 3077a9083016SGiridhar Malavali } 3078a9083016SGiridhar Malavali 307977e334d2SGiridhar Malavali static int 3080a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 3081a9083016SGiridhar Malavali { 3082a9083016SGiridhar Malavali int ret; 3083a9083016SGiridhar Malavali uint32_t val; 30847c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3085a9083016SGiridhar Malavali 3086a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3087a9083016SGiridhar Malavali if (ret < 0) { 30887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 30897c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3090a9083016SGiridhar Malavali return ret; 3091a9083016SGiridhar Malavali } 3092a9083016SGiridhar Malavali 3093a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3094a9083016SGiridhar Malavali if (ret < 0) 3095a9083016SGiridhar Malavali goto done_protect; 3096a9083016SGiridhar Malavali 30970547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3098a9083016SGiridhar Malavali /* LOCK all sectors */ 3099a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3100a9083016SGiridhar Malavali if (ret < 0) 31017c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 31027c3df132SSaurav Kashyap "Write status register failed.\n"); 3103a9083016SGiridhar Malavali 3104a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 31057c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 31067c3df132SSaurav Kashyap "Write disable failed.\n"); 3107a9083016SGiridhar Malavali done_protect: 3108d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3109a9083016SGiridhar Malavali return ret; 3110a9083016SGiridhar Malavali } 3111a9083016SGiridhar Malavali 311277e334d2SGiridhar Malavali static int 3113a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3114a9083016SGiridhar Malavali { 3115a9083016SGiridhar Malavali int ret = 0; 31167c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3117a9083016SGiridhar Malavali 3118a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3119a9083016SGiridhar Malavali if (ret < 0) { 31207c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 31217c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3122a9083016SGiridhar Malavali return ret; 3123a9083016SGiridhar Malavali } 3124a9083016SGiridhar Malavali 3125a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 3126a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3127a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3128a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3129a9083016SGiridhar Malavali 3130a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 31317c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 31327c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 3133a9083016SGiridhar Malavali ret = -1; 3134a9083016SGiridhar Malavali goto done; 3135a9083016SGiridhar Malavali } 3136a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 3137a9083016SGiridhar Malavali done: 3138d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3139a9083016SGiridhar Malavali return ret; 3140a9083016SGiridhar Malavali } 3141a9083016SGiridhar Malavali 3142a9083016SGiridhar Malavali /* 3143a9083016SGiridhar Malavali * Address and length are byte address 3144a9083016SGiridhar Malavali */ 3145a9083016SGiridhar Malavali uint8_t * 3146a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3147a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3148a9083016SGiridhar Malavali { 3149a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3150a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3151a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3152a9083016SGiridhar Malavali return buf; 3153a9083016SGiridhar Malavali } 3154a9083016SGiridhar Malavali 3155a9083016SGiridhar Malavali static int 3156a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3157a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 3158a9083016SGiridhar Malavali { 3159a9083016SGiridhar Malavali int ret; 3160a9083016SGiridhar Malavali uint32_t liter; 3161a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 3162a9083016SGiridhar Malavali dma_addr_t optrom_dma; 3163a9083016SGiridhar Malavali void *optrom = NULL; 3164a9083016SGiridhar Malavali int page_mode = 0; 3165a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3166a9083016SGiridhar Malavali 3167a9083016SGiridhar Malavali ret = -1; 3168a9083016SGiridhar Malavali 3169a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 3170a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 3171a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 3172a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3173a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 3174a9083016SGiridhar Malavali if (!optrom) { 31757c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 31767c3df132SSaurav Kashyap "Unable to allocate memory " 31777c3df132SSaurav Kashyap "for optron burst write (%x KB).\n", 3178a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 3179a9083016SGiridhar Malavali } 3180a9083016SGiridhar Malavali } 3181a9083016SGiridhar Malavali 3182a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 3183a9083016SGiridhar Malavali sec_mask = ~rest_addr; 3184a9083016SGiridhar Malavali 3185a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 3186a9083016SGiridhar Malavali if (ret) { 31877c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 3188a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 3189a9083016SGiridhar Malavali goto write_done; 3190a9083016SGiridhar Malavali } 3191a9083016SGiridhar Malavali 3192a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3193a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 3194a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 3195a9083016SGiridhar Malavali 3196a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 3197a9083016SGiridhar Malavali if (ret) { 31987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 31997c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 32007c3df132SSaurav Kashyap faddr); 3201a9083016SGiridhar Malavali break; 3202a9083016SGiridhar Malavali } 3203a9083016SGiridhar Malavali } 3204a9083016SGiridhar Malavali 3205a9083016SGiridhar Malavali /* Go with burst-write. */ 3206a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3207a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 3208a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3209a9083016SGiridhar Malavali 3210a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 3211a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3212a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 3213a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 32147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 3215a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 3216a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 3217a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3218a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 32197c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 3220a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 3221a9083016SGiridhar Malavali 3222a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3223a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3224a9083016SGiridhar Malavali optrom = NULL; 3225a9083016SGiridhar Malavali } else { 3226a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 3227a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 3228a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 3229a9083016SGiridhar Malavali continue; 3230a9083016SGiridhar Malavali } 3231a9083016SGiridhar Malavali } 3232a9083016SGiridhar Malavali 3233a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 3234a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 3235a9083016SGiridhar Malavali if (ret) { 32367c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 32377c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 32387c3df132SSaurav Kashyap faddr, *dwptr); 3239a9083016SGiridhar Malavali break; 3240a9083016SGiridhar Malavali } 3241a9083016SGiridhar Malavali } 3242a9083016SGiridhar Malavali 3243a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 3244a9083016SGiridhar Malavali if (ret) 32457c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 3246a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 3247a9083016SGiridhar Malavali write_done: 3248a9083016SGiridhar Malavali if (optrom) 3249a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3250a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3251a9083016SGiridhar Malavali return ret; 3252a9083016SGiridhar Malavali } 3253a9083016SGiridhar Malavali 3254a9083016SGiridhar Malavali int 3255a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3256a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3257a9083016SGiridhar Malavali { 3258a9083016SGiridhar Malavali int rval; 3259a9083016SGiridhar Malavali 3260a9083016SGiridhar Malavali /* Suspend HBA. */ 3261a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3262a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3263a9083016SGiridhar Malavali length >> 2); 3264a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3265a9083016SGiridhar Malavali 3266a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 3267a9083016SGiridhar Malavali if (rval) 3268a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3269a9083016SGiridhar Malavali else 3270a9083016SGiridhar Malavali rval = QLA_SUCCESS; 3271a9083016SGiridhar Malavali return rval; 3272a9083016SGiridhar Malavali } 3273a9083016SGiridhar Malavali 3274a9083016SGiridhar Malavali void 3275a9083016SGiridhar Malavali qla82xx_start_iocbs(srb_t *sp) 3276a9083016SGiridhar Malavali { 3277a9083016SGiridhar Malavali struct qla_hw_data *ha = sp->fcport->vha->hw; 3278a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3279a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 3280a9083016SGiridhar Malavali uint32_t dbval; 3281a9083016SGiridhar Malavali 3282a9083016SGiridhar Malavali /* Adjust ring index. */ 3283a9083016SGiridhar Malavali req->ring_index++; 3284a9083016SGiridhar Malavali if (req->ring_index == req->length) { 3285a9083016SGiridhar Malavali req->ring_index = 0; 3286a9083016SGiridhar Malavali req->ring_ptr = req->ring; 3287a9083016SGiridhar Malavali } else 3288a9083016SGiridhar Malavali req->ring_ptr++; 3289a9083016SGiridhar Malavali 3290a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 3291a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 3292a9083016SGiridhar Malavali 3293a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 32946907869dSGiridhar Malavali if (ql2xdbwr) 32956907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 32966907869dSGiridhar Malavali else { 3297a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3298a9083016SGiridhar Malavali wmb(); 3299a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 33006907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 33016907869dSGiridhar Malavali dbval); 3302a9083016SGiridhar Malavali wmb(); 3303a9083016SGiridhar Malavali } 3304a9083016SGiridhar Malavali } 33056907869dSGiridhar Malavali } 3306a9083016SGiridhar Malavali 3307e6a4202aSShyam Sundar void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 3308e6a4202aSShyam Sundar { 33097c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 33107c3df132SSaurav Kashyap 3311e6a4202aSShyam Sundar if (qla82xx_rom_lock(ha)) 3312e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 33137c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 33147c3df132SSaurav Kashyap "Resetting rom_lock.\n"); 3315e6a4202aSShyam Sundar 3316e6a4202aSShyam Sundar /* 3317e6a4202aSShyam Sundar * Either we got the lock, or someone 3318e6a4202aSShyam Sundar * else died while holding it. 3319e6a4202aSShyam Sundar * In either case, unlock. 3320e6a4202aSShyam Sundar */ 3321d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3322e6a4202aSShyam Sundar } 3323e6a4202aSShyam Sundar 3324a9083016SGiridhar Malavali /* 3325a9083016SGiridhar Malavali * qla82xx_device_bootstrap 3326a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 3327a9083016SGiridhar Malavali * 3328a9083016SGiridhar Malavali * Note: 3329a9083016SGiridhar Malavali * IDC lock must be held upon entry 3330a9083016SGiridhar Malavali * 3331a9083016SGiridhar Malavali * Return: 3332a9083016SGiridhar Malavali * Success : 0 3333a9083016SGiridhar Malavali * Failed : 1 3334a9083016SGiridhar Malavali */ 3335a9083016SGiridhar Malavali static int 3336a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3337a9083016SGiridhar Malavali { 3338e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 3339e6a4202aSShyam Sundar int i, timeout; 3340a9083016SGiridhar Malavali uint32_t old_count, count; 3341a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3342e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 3343a9083016SGiridhar Malavali 3344e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 3345a9083016SGiridhar Malavali 3346a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3347a9083016SGiridhar Malavali 3348a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 3349a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 3350a9083016SGiridhar Malavali if (timeout) { 3351a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3352a9083016SGiridhar Malavali QLA82XX_DEV_FAILED); 3353a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3354a9083016SGiridhar Malavali } 3355a9083016SGiridhar Malavali 3356a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3357a9083016SGiridhar Malavali if (count != old_count) 3358e6a4202aSShyam Sundar peg_stuck = 0; 3359e6a4202aSShyam Sundar } 3360e6a4202aSShyam Sundar 3361e6a4202aSShyam Sundar if (need_reset) { 3362e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 3363e6a4202aSShyam Sundar if (peg_stuck) 3364e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3365e6a4202aSShyam Sundar goto dev_initialize; 3366e6a4202aSShyam Sundar } else { 3367e6a4202aSShyam Sundar /* Start of day for this ha context. */ 3368e6a4202aSShyam Sundar if (peg_stuck) { 3369e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 3370e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3371e6a4202aSShyam Sundar goto dev_initialize; 3372e6a4202aSShyam Sundar } else 3373e6a4202aSShyam Sundar /* Firmware already running. */ 3374a9083016SGiridhar Malavali goto dev_ready; 3375a9083016SGiridhar Malavali } 3376a9083016SGiridhar Malavali 3377e6a4202aSShyam Sundar return rval; 3378e6a4202aSShyam Sundar 3379a9083016SGiridhar Malavali dev_initialize: 3380a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 33817c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 33827c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 3383a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3384a9083016SGiridhar Malavali 3385a9083016SGiridhar Malavali /* Driver that sets device state to initializating sets IDC version */ 3386a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3387a9083016SGiridhar Malavali 3388a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3389a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 3390a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3391a9083016SGiridhar Malavali 3392a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 33937c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 33947c3df132SSaurav Kashyap "HW State: FAILED.\n"); 3395a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 3396a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3397a9083016SGiridhar Malavali return rval; 3398a9083016SGiridhar Malavali } 3399a9083016SGiridhar Malavali 3400a9083016SGiridhar Malavali dev_ready: 34017c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 34027c3df132SSaurav Kashyap "HW State: READY.\n"); 3403a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3404a9083016SGiridhar Malavali 3405a9083016SGiridhar Malavali return QLA_SUCCESS; 3406a9083016SGiridhar Malavali } 3407a9083016SGiridhar Malavali 3408579d12b5SSaurav Kashyap /* 3409579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 3410579d12b5SSaurav Kashyap * Code to start quiescence sequence 3411579d12b5SSaurav Kashyap * 3412579d12b5SSaurav Kashyap * Note: 3413579d12b5SSaurav Kashyap * IDC lock must be held upon entry 3414579d12b5SSaurav Kashyap * 3415579d12b5SSaurav Kashyap * Return: void 3416579d12b5SSaurav Kashyap */ 3417579d12b5SSaurav Kashyap 3418579d12b5SSaurav Kashyap static void 3419579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 3420579d12b5SSaurav Kashyap { 3421579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3422579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 3423579d12b5SSaurav Kashyap unsigned long reset_timeout; 3424579d12b5SSaurav Kashyap 3425579d12b5SSaurav Kashyap if (vha->flags.online) { 3426579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 3427579d12b5SSaurav Kashyap qla82xx_quiescent_state_cleanup(vha); 3428579d12b5SSaurav Kashyap } 3429579d12b5SSaurav Kashyap 3430579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 3431579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 3432579d12b5SSaurav Kashyap 3433579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 3434579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 3435579d12b5SSaurav Kashyap 3436579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3437579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3438579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 3439579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3440579d12b5SSaurav Kashyap 3441579d12b5SSaurav Kashyap while (drv_state != drv_active) { 3442579d12b5SSaurav Kashyap 3443579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 3444579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 3445579d12b5SSaurav Kashyap * changing the state to DEV_READY 3446579d12b5SSaurav Kashyap */ 34477c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 34487c3df132SSaurav Kashyap "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 34497c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb024, 34507c3df132SSaurav Kashyap "DRV_ACTIVE:%d DRV_STATE:%d.\n", 34517c3df132SSaurav Kashyap drv_active, drv_state); 3452579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3453579d12b5SSaurav Kashyap QLA82XX_DEV_READY); 34547c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 34557c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 3456579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3457579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 3458579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3459579d12b5SSaurav Kashyap 3460579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 3461579d12b5SSaurav Kashyap return; 3462579d12b5SSaurav Kashyap } 3463579d12b5SSaurav Kashyap 3464579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3465579d12b5SSaurav Kashyap msleep(1000); 3466579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3467579d12b5SSaurav Kashyap 3468579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3469579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3470579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3471579d12b5SSaurav Kashyap } 3472579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3473579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 3474579d12b5SSaurav Kashyap if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 34757c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 34767c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 3477579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 3478579d12b5SSaurav Kashyap } 3479579d12b5SSaurav Kashyap } 3480579d12b5SSaurav Kashyap 3481579d12b5SSaurav Kashyap /* 3482579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 3483579d12b5SSaurav Kashyap * Wait for device state to change from given current state 3484579d12b5SSaurav Kashyap * 3485579d12b5SSaurav Kashyap * Note: 3486579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 3487579d12b5SSaurav Kashyap * 3488579d12b5SSaurav Kashyap * Return: 3489579d12b5SSaurav Kashyap * Changed device state. 3490579d12b5SSaurav Kashyap */ 3491579d12b5SSaurav Kashyap uint32_t 3492579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3493579d12b5SSaurav Kashyap { 3494579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3495579d12b5SSaurav Kashyap uint32_t dev_state; 3496579d12b5SSaurav Kashyap 3497579d12b5SSaurav Kashyap do { 3498579d12b5SSaurav Kashyap msleep(1000); 3499579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3500579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3501579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3502579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3503579d12b5SSaurav Kashyap 3504579d12b5SSaurav Kashyap return dev_state; 3505579d12b5SSaurav Kashyap } 3506579d12b5SSaurav Kashyap 3507a9083016SGiridhar Malavali static void 3508a9083016SGiridhar Malavali qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3509a9083016SGiridhar Malavali { 3510a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3511a9083016SGiridhar Malavali 3512a9083016SGiridhar Malavali /* Disable the board */ 35137c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 35147c3df132SSaurav Kashyap "Disabling the board.\n"); 3515a9083016SGiridhar Malavali 3516b963752fSGiridhar Malavali qla82xx_idc_lock(ha); 3517b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3518b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 3519b963752fSGiridhar Malavali 3520a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3521a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3522a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3523a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3524a9083016SGiridhar Malavali vha->flags.online = 0; 3525a9083016SGiridhar Malavali vha->flags.init_done = 0; 3526a9083016SGiridhar Malavali } 3527a9083016SGiridhar Malavali 3528a9083016SGiridhar Malavali /* 3529a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3530a9083016SGiridhar Malavali * Code to start reset sequence 3531a9083016SGiridhar Malavali * 3532a9083016SGiridhar Malavali * Note: 3533a9083016SGiridhar Malavali * IDC lock must be held upon entry 3534a9083016SGiridhar Malavali * 3535a9083016SGiridhar Malavali * Return: 3536a9083016SGiridhar Malavali * Success : 0 3537a9083016SGiridhar Malavali * Failed : 1 3538a9083016SGiridhar Malavali */ 3539a9083016SGiridhar Malavali static void 3540a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3541a9083016SGiridhar Malavali { 3542e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3543e5fdae55SChad Dupuis uint32_t active_mask = 0; 3544a9083016SGiridhar Malavali unsigned long reset_timeout; 3545a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3546a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3547a9083016SGiridhar Malavali 3548a9083016SGiridhar Malavali if (vha->flags.online) { 3549a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3550a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3551a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3552a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3553a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3554a9083016SGiridhar Malavali } 3555a9083016SGiridhar Malavali 355608de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 355708de2844SGiridhar Malavali if (!ha->flags.isp82xx_reset_owner) { 355808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 355908de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3560a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 356108de2844SGiridhar Malavali } else { 356208de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 356308de2844SGiridhar Malavali drv_active &= active_mask; 356408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 356508de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 356608de2844SGiridhar Malavali } 3567a9083016SGiridhar Malavali 3568a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 3569a9083016SGiridhar Malavali reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3570a9083016SGiridhar Malavali 3571a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3572a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 357308de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3574a9083016SGiridhar Malavali 357508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 357608de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 357708de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 357808de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 357908de2844SGiridhar Malavali 358008de2844SGiridhar Malavali while (drv_state != drv_active && 358108de2844SGiridhar Malavali dev_state != QLA82XX_DEV_INITIALIZING) { 3582a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 35837c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 35847c3df132SSaurav Kashyap "Reset timeout.\n"); 3585a9083016SGiridhar Malavali break; 3586a9083016SGiridhar Malavali } 3587a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3588a9083016SGiridhar Malavali msleep(1000); 3589a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3590a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3591a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 359208de2844SGiridhar Malavali if (ha->flags.isp82xx_reset_owner) 359308de2844SGiridhar Malavali drv_active &= active_mask; 359408de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3595a9083016SGiridhar Malavali } 3596a9083016SGiridhar Malavali 359708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 359808de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 359908de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 360008de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 360108de2844SGiridhar Malavali 36027c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 36037c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 36047c3df132SSaurav Kashyap dev_state, 360508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3606f1af6208SGiridhar Malavali 3607a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 360808de2844SGiridhar Malavali if (dev_state != QLA82XX_DEV_INITIALIZING && 360908de2844SGiridhar Malavali dev_state != QLA82XX_DEV_COLD) { 36107c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 36117c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 3612a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 361308de2844SGiridhar Malavali if (ql2xmdenable) { 361408de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 361508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 361608de2844SGiridhar Malavali "Not able to collect minidump.\n"); 361708de2844SGiridhar Malavali } else 361808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 361908de2844SGiridhar Malavali "Minidump disabled.\n"); 3620a9083016SGiridhar Malavali } 3621a9083016SGiridhar Malavali } 3622a9083016SGiridhar Malavali 36233173167fSGiridhar Malavali int 362408de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 362508de2844SGiridhar Malavali { 362608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 362708de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 36283173167fSGiridhar Malavali int rval = QLA_SUCCESS; 362908de2844SGiridhar Malavali 36303173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 36313173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 36323173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 36333173167fSGiridhar Malavali 36343173167fSGiridhar Malavali rval = qla2x00_get_fw_version(vha, &ha->fw_major_version, 36353173167fSGiridhar Malavali &ha->fw_minor_version, &ha->fw_subminor_version, 36363173167fSGiridhar Malavali &ha->fw_attributes, &ha->fw_memory_size, 36373173167fSGiridhar Malavali ha->mpi_version, &ha->mpi_capabilities, 36383173167fSGiridhar Malavali ha->phy_version); 36393173167fSGiridhar Malavali 36403173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 36413173167fSGiridhar Malavali return rval; 36423173167fSGiridhar Malavali 36433173167fSGiridhar Malavali if (ql2xmdenable) { 364408de2844SGiridhar Malavali if (!ha->fw_dumped) { 364508de2844SGiridhar Malavali if (fw_major_version != ha->fw_major_version || 364608de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 364708de2844SGiridhar Malavali fw_subminor_version != ha->fw_subminor_version) { 36483173167fSGiridhar Malavali 364908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02d, 365008de2844SGiridhar Malavali "Firmware version differs " 365108de2844SGiridhar Malavali "Previous version: %d:%d:%d - " 365208de2844SGiridhar Malavali "New version: %d:%d:%d\n", 365308de2844SGiridhar Malavali ha->fw_major_version, 36543173167fSGiridhar Malavali ha->fw_minor_version, 36553173167fSGiridhar Malavali ha->fw_subminor_version, 365608de2844SGiridhar Malavali fw_major_version, fw_minor_version, 365708de2844SGiridhar Malavali fw_subminor_version); 365808de2844SGiridhar Malavali /* Release MiniDump resources */ 365908de2844SGiridhar Malavali qla82xx_md_free(vha); 366008de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 366108de2844SGiridhar Malavali qla82xx_md_prep(vha); 366208de2844SGiridhar Malavali } else 366308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 366408de2844SGiridhar Malavali "Firmware dump available to retrieve\n", 366508de2844SGiridhar Malavali vha->host_no); 366608de2844SGiridhar Malavali } 36673173167fSGiridhar Malavali } 36683173167fSGiridhar Malavali return rval; 36693173167fSGiridhar Malavali } 367008de2844SGiridhar Malavali 367108de2844SGiridhar Malavali 36727190575fSGiridhar Malavali int 3673a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3674a9083016SGiridhar Malavali { 36757190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 36767190575fSGiridhar Malavali int status = 0; 3677a9083016SGiridhar Malavali 36787190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 36797190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3680a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 36817c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 36827c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 36837c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 36847c3df132SSaurav Kashyap "returning status=%d.\n", status); 36857190575fSGiridhar Malavali return status; 36867c3df132SSaurav Kashyap } 3687a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3688a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3689a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3690a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3691a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 36927190575fSGiridhar Malavali status = 1; 3693a9083016SGiridhar Malavali } 3694efa786ccSLalit Chandivade } else 3695efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3696a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 36977c3df132SSaurav Kashyap if (status) 36987c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 36997c3df132SSaurav Kashyap "Returning status=%d.\n", status); 37007190575fSGiridhar Malavali return status; 3701a9083016SGiridhar Malavali } 3702a9083016SGiridhar Malavali 3703a9083016SGiridhar Malavali /* 3704a9083016SGiridhar Malavali * qla82xx_device_state_handler 3705a9083016SGiridhar Malavali * Main state handler 3706a9083016SGiridhar Malavali * 3707a9083016SGiridhar Malavali * Note: 3708a9083016SGiridhar Malavali * IDC lock must be held upon entry 3709a9083016SGiridhar Malavali * 3710a9083016SGiridhar Malavali * Return: 3711a9083016SGiridhar Malavali * Success : 0 3712a9083016SGiridhar Malavali * Failed : 1 3713a9083016SGiridhar Malavali */ 3714a9083016SGiridhar Malavali int 3715a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3716a9083016SGiridhar Malavali { 3717a9083016SGiridhar Malavali uint32_t dev_state; 371892dbf273SGiridhar Malavali uint32_t old_dev_state; 3719a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3720a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3721a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 372292dbf273SGiridhar Malavali int loopcount = 0; 3723a9083016SGiridhar Malavali 3724a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3725a9083016SGiridhar Malavali if (!vha->flags.init_done) 3726a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 3727a9083016SGiridhar Malavali 3728a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 372992dbf273SGiridhar Malavali old_dev_state = dev_state; 37307c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 37317c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 37327c3df132SSaurav Kashyap dev_state, 373308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3734a9083016SGiridhar Malavali 3735a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 3736a9083016SGiridhar Malavali dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3737a9083016SGiridhar Malavali 3738a9083016SGiridhar Malavali while (1) { 3739a9083016SGiridhar Malavali 3740a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 37417c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 37427c3df132SSaurav Kashyap "Device init failed.\n"); 3743a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3744a9083016SGiridhar Malavali break; 3745a9083016SGiridhar Malavali } 3746a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 374792dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 374892dbf273SGiridhar Malavali loopcount = 0; 374992dbf273SGiridhar Malavali old_dev_state = dev_state; 375092dbf273SGiridhar Malavali } 375192dbf273SGiridhar Malavali if (loopcount < 5) { 37527c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 37537c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 37547c3df132SSaurav Kashyap dev_state, 375508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 37567c3df132SSaurav Kashyap "Unknown"); 375792dbf273SGiridhar Malavali } 3758f1af6208SGiridhar Malavali 3759a9083016SGiridhar Malavali switch (dev_state) { 3760a9083016SGiridhar Malavali case QLA82XX_DEV_READY: 376108de2844SGiridhar Malavali qla82xx_check_md_needed(vha); 376208de2844SGiridhar Malavali ha->flags.isp82xx_reset_owner = 0; 3763a9083016SGiridhar Malavali goto exit; 3764a9083016SGiridhar Malavali case QLA82XX_DEV_COLD: 3765a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 376608de2844SGiridhar Malavali break; 3767a9083016SGiridhar Malavali case QLA82XX_DEV_INITIALIZING: 3768a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3769a9083016SGiridhar Malavali msleep(1000); 3770a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3771a9083016SGiridhar Malavali break; 3772a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_RESET: 3773ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3774a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3775c8582ad9SSaurav Kashyap else { 3776c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3777c8582ad9SSaurav Kashyap msleep(1000); 3778c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3779c8582ad9SSaurav Kashyap } 37800060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 37810060ddf8SGiridhar Malavali (ha->nx_dev_init_timeout * HZ); 3782a9083016SGiridhar Malavali break; 3783a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_QUIESCENT: 3784579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3785579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3786579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3787579d12b5SSaurav Kashyap * HZ); 3788579d12b5SSaurav Kashyap break; 3789a9083016SGiridhar Malavali case QLA82XX_DEV_QUIESCENT: 3790579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3791579d12b5SSaurav Kashyap * to get changed 3792579d12b5SSaurav Kashyap */ 3793579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 3794579d12b5SSaurav Kashyap goto exit; 3795579d12b5SSaurav Kashyap 3796a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3797a9083016SGiridhar Malavali msleep(1000); 3798a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3799579d12b5SSaurav Kashyap 3800579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3801579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3802579d12b5SSaurav Kashyap * HZ); 3803a9083016SGiridhar Malavali break; 3804a9083016SGiridhar Malavali case QLA82XX_DEV_FAILED: 3805a9083016SGiridhar Malavali qla82xx_dev_failed_handler(vha); 3806a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3807a9083016SGiridhar Malavali goto exit; 3808a9083016SGiridhar Malavali default: 3809a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3810a9083016SGiridhar Malavali msleep(1000); 3811a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3812a9083016SGiridhar Malavali } 381392dbf273SGiridhar Malavali loopcount++; 3814a9083016SGiridhar Malavali } 3815a9083016SGiridhar Malavali exit: 3816a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3817a9083016SGiridhar Malavali return rval; 3818a9083016SGiridhar Malavali } 3819a9083016SGiridhar Malavali 3820c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3821c8f6544eSChad Dupuis { 3822c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3823c8f6544eSChad Dupuis 3824c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3825c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 3826c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3827c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 3828c8f6544eSChad Dupuis if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3829c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3830c8f6544eSChad Dupuis } 3831c8f6544eSChad Dupuis } 3832c8f6544eSChad Dupuis 3833a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3834a9083016SGiridhar Malavali { 38357190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3836a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3837a9083016SGiridhar Malavali 3838a9083016SGiridhar Malavali /* don't poll if reset is going on */ 38397190575fSGiridhar Malavali if (!ha->flags.isp82xx_reset_hdlr_active) { 38407190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 38417190575fSGiridhar Malavali if (dev_state == QLA82XX_DEV_NEED_RESET && 38427190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 38437c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 38447c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3845a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3846a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3847579d12b5SSaurav Kashyap } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3848579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 38497c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 38507c3df132SSaurav Kashyap "Quiescent needed.\n"); 3851579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3852579d12b5SSaurav Kashyap qla2xxx_wake_dpc(vha); 3853a9083016SGiridhar Malavali } else { 38547190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 38557190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 38567190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 38577c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6005, 38587c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 38597c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 38607c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 38617c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 38627c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 38630e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 38640e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 38650e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 38660e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 38670e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 38680e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 38690e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 38700e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 38710e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 38720e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 38730e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 387410a340e6SChad Dupuis if (LSW(MSB(halt_status)) == 0x67) 387510a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 387610a340e6SChad Dupuis "Firmware aborted with " 387710a340e6SChad Dupuis "error code 0x00006700. Device is " 387810a340e6SChad Dupuis "being reset.\n"); 38797190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 38807190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 38817190575fSGiridhar Malavali &vha->dpc_flags); 38827190575fSGiridhar Malavali } else { 38837c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 38847c3df132SSaurav Kashyap "Detect abort needed.\n"); 38857190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 38867190575fSGiridhar Malavali &vha->dpc_flags); 38877190575fSGiridhar Malavali } 38887190575fSGiridhar Malavali qla2xxx_wake_dpc(vha); 38897190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3890c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3891c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 38927190575fSGiridhar Malavali } 3893a9083016SGiridhar Malavali } 3894a9083016SGiridhar Malavali } 3895a9083016SGiridhar Malavali } 3896a9083016SGiridhar Malavali 3897a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3898a9083016SGiridhar Malavali { 3899a9083016SGiridhar Malavali int rval; 3900a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3901a9083016SGiridhar Malavali return rval; 3902a9083016SGiridhar Malavali } 3903a9083016SGiridhar Malavali 390408de2844SGiridhar Malavali void 390508de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 390608de2844SGiridhar Malavali { 390708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 390808de2844SGiridhar Malavali uint32_t dev_state; 390908de2844SGiridhar Malavali 391008de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 391108de2844SGiridhar Malavali if (dev_state == QLA82XX_DEV_READY) { 391208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 391308de2844SGiridhar Malavali "HW State: NEED RESET\n"); 391408de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 391508de2844SGiridhar Malavali QLA82XX_DEV_NEED_RESET); 391608de2844SGiridhar Malavali ha->flags.isp82xx_reset_owner = 1; 391708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 391808de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 391908de2844SGiridhar Malavali } else 392008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 392108de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 392208de2844SGiridhar Malavali dev_state, 392308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 392408de2844SGiridhar Malavali } 392508de2844SGiridhar Malavali 3926a9083016SGiridhar Malavali /* 3927a9083016SGiridhar Malavali * qla82xx_abort_isp 3928a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3929a9083016SGiridhar Malavali * 3930a9083016SGiridhar Malavali * Input: 3931a9083016SGiridhar Malavali * ha = adapter block pointer. 3932a9083016SGiridhar Malavali * 3933a9083016SGiridhar Malavali * Returns: 3934a9083016SGiridhar Malavali * 0 = success 3935a9083016SGiridhar Malavali */ 3936a9083016SGiridhar Malavali int 3937a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3938a9083016SGiridhar Malavali { 3939a9083016SGiridhar Malavali int rval; 3940a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3941a9083016SGiridhar Malavali 3942a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 39437c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 39447c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3945a9083016SGiridhar Malavali return QLA_SUCCESS; 3946a9083016SGiridhar Malavali } 39477190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 1; 3948a9083016SGiridhar Malavali 3949a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 395008de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3951a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3952a9083016SGiridhar Malavali 3953a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3954a9083016SGiridhar Malavali 3955a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3956a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3957a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3958a9083016SGiridhar Malavali 3959cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 39607190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 39617190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 0; 3962a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3963cdbb0a4fSSantosh Vernekar } 3964f1af6208SGiridhar Malavali 3965f1af6208SGiridhar Malavali if (rval) { 3966f1af6208SGiridhar Malavali vha->flags.online = 1; 3967f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3968f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 39697c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 39707c3df132SSaurav Kashyap "ISP error recover failed - board " 39717c3df132SSaurav Kashyap "disabled.\n"); 3972f1af6208SGiridhar Malavali /* 3973f1af6208SGiridhar Malavali * The next call disables the board 3974f1af6208SGiridhar Malavali * completely. 3975f1af6208SGiridhar Malavali */ 3976f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3977f1af6208SGiridhar Malavali vha->flags.online = 0; 3978f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3979f1af6208SGiridhar Malavali &vha->dpc_flags); 3980f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3981f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3982f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 39837c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 39847c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 39857c3df132SSaurav Kashyap ha->isp_abort_cnt); 3986f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3987f1af6208SGiridhar Malavali } 3988f1af6208SGiridhar Malavali } else { 3989f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 39907c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 39917c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 39927c3df132SSaurav Kashyap ha->isp_abort_cnt); 3993f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3994f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3995f1af6208SGiridhar Malavali } 3996f1af6208SGiridhar Malavali } 3997a9083016SGiridhar Malavali return rval; 3998a9083016SGiridhar Malavali } 3999a9083016SGiridhar Malavali 4000a9083016SGiridhar Malavali /* 4001a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 4002a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 4003a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 4004a9083016SGiridhar Malavali * chip reset. 4005a9083016SGiridhar Malavali * 4006a9083016SGiridhar Malavali * Input: 4007a9083016SGiridhar Malavali * ha = adapter block pointer. 4008a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 4009a9083016SGiridhar Malavali * 4010a9083016SGiridhar Malavali * Returns: 4011a9083016SGiridhar Malavali * 0 = success 4012a9083016SGiridhar Malavali */ 4013a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 4014a9083016SGiridhar Malavali { 4015a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 4016a9083016SGiridhar Malavali 4017a9083016SGiridhar Malavali if (vha->flags.online) { 4018a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 4019a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 4020a9083016SGiridhar Malavali } 4021a9083016SGiridhar Malavali 4022a9083016SGiridhar Malavali /* Stop currently executing firmware. 4023a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 4024a9083016SGiridhar Malavali */ 4025a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 4026a9083016SGiridhar Malavali 4027a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 4028a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 4029a9083016SGiridhar Malavali 4030a9083016SGiridhar Malavali return rval; 4031a9083016SGiridhar Malavali } 4032a9083016SGiridhar Malavali 4033a9083016SGiridhar Malavali /* 4034a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 4035a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 4036a9083016SGiridhar Malavali * 4037a9083016SGiridhar Malavali * Note: 4038a9083016SGiridhar Malavali * Does context switching here. 4039a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 4040a9083016SGiridhar Malavali * 4041a9083016SGiridhar Malavali * Return: 4042a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 4043a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 4044a9083016SGiridhar Malavali */ 4045a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 4046a9083016SGiridhar Malavali { 4047a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 4048a9083016SGiridhar Malavali unsigned long wait_reset; 4049a9083016SGiridhar Malavali 4050a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 4051a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 4052a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 4053a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 4054a9083016SGiridhar Malavali 4055a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 4056a9083016SGiridhar Malavali schedule_timeout(HZ); 4057a9083016SGiridhar Malavali 4058a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 4059a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 4060a9083016SGiridhar Malavali status = QLA_SUCCESS; 4061a9083016SGiridhar Malavali break; 4062a9083016SGiridhar Malavali } 4063a9083016SGiridhar Malavali } 40647c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 40657c3df132SSaurav Kashyap "%s status=%d.\n", status); 4066a9083016SGiridhar Malavali 4067a9083016SGiridhar Malavali return status; 4068a9083016SGiridhar Malavali } 40697190575fSGiridhar Malavali 40707190575fSGiridhar Malavali void 40717190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 40727190575fSGiridhar Malavali { 40737190575fSGiridhar Malavali int i; 40747190575fSGiridhar Malavali unsigned long flags; 40757190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 40767190575fSGiridhar Malavali 40777190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 40787190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 40797190575fSGiridhar Malavali * detection only 40807190575fSGiridhar Malavali */ 40817190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 40827190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 40837190575fSGiridhar Malavali msleep(1000); 40847190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 40857190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 4086c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 40877190575fSGiridhar Malavali break; 40887190575fSGiridhar Malavali } 40897190575fSGiridhar Malavali } 40907190575fSGiridhar Malavali } 40917c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 40927c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 40937c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 40947190575fSGiridhar Malavali 40957190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 40967190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 40977190575fSGiridhar Malavali int cnt, que; 40987190575fSGiridhar Malavali srb_t *sp; 40997190575fSGiridhar Malavali struct req_que *req; 41007190575fSGiridhar Malavali 41017190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 41027190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 41037190575fSGiridhar Malavali req = ha->req_q_map[que]; 41047190575fSGiridhar Malavali if (!req) 41057190575fSGiridhar Malavali continue; 41067190575fSGiridhar Malavali for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 41077190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 41087190575fSGiridhar Malavali if (sp) { 41097190575fSGiridhar Malavali if (!sp->ctx || 41107190575fSGiridhar Malavali (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 41117190575fSGiridhar Malavali spin_unlock_irqrestore( 41127190575fSGiridhar Malavali &ha->hardware_lock, flags); 41137190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 41147c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 41157c3df132SSaurav Kashyap 0x00b1, 41167c3df132SSaurav Kashyap "mbx abort failed.\n"); 41177190575fSGiridhar Malavali } else { 41187c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 41197c3df132SSaurav Kashyap 0x00b2, 41207c3df132SSaurav Kashyap "mbx abort success.\n"); 41217190575fSGiridhar Malavali } 41227190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 41237190575fSGiridhar Malavali } 41247190575fSGiridhar Malavali } 41257190575fSGiridhar Malavali } 41267190575fSGiridhar Malavali } 41277190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 41287190575fSGiridhar Malavali 41297190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 41307190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 41317190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 41327c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 41337c3df132SSaurav Kashyap "Done wait for " 41347c3df132SSaurav Kashyap "pending commands.\n"); 41357190575fSGiridhar Malavali } 41367190575fSGiridhar Malavali } 41377190575fSGiridhar Malavali } 413808de2844SGiridhar Malavali 413908de2844SGiridhar Malavali /* Minidump related functions */ 414008de2844SGiridhar Malavali int 414108de2844SGiridhar Malavali qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 414208de2844SGiridhar Malavali { 414308de2844SGiridhar Malavali uint32_t off_value, rval = 0; 414408de2844SGiridhar Malavali 414508de2844SGiridhar Malavali WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 414608de2844SGiridhar Malavali (off & 0xFFFF0000)); 414708de2844SGiridhar Malavali 414808de2844SGiridhar Malavali /* Read back value to make sure write has gone through */ 414908de2844SGiridhar Malavali RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 415008de2844SGiridhar Malavali off_value = (off & 0x0000FFFF); 415108de2844SGiridhar Malavali 415208de2844SGiridhar Malavali if (flag) 415308de2844SGiridhar Malavali WRT_REG_DWORD((void *) 415408de2844SGiridhar Malavali (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 415508de2844SGiridhar Malavali data); 415608de2844SGiridhar Malavali else 415708de2844SGiridhar Malavali rval = RD_REG_DWORD((void *) 415808de2844SGiridhar Malavali (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 415908de2844SGiridhar Malavali 416008de2844SGiridhar Malavali return rval; 416108de2844SGiridhar Malavali } 416208de2844SGiridhar Malavali 416308de2844SGiridhar Malavali static int 416408de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 416508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 416608de2844SGiridhar Malavali { 416708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 416808de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 416908de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 417008de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 417108de2844SGiridhar Malavali unsigned long wtime; 417208de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 417308de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 417408de2844SGiridhar Malavali int i; 417508de2844SGiridhar Malavali 417608de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 417708de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 417808de2844SGiridhar Malavali crb_addr = crb_entry->addr; 417908de2844SGiridhar Malavali 418008de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 418108de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 418208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 418308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 418408de2844SGiridhar Malavali crb_entry->value_1, 1); 418508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 418608de2844SGiridhar Malavali } 418708de2844SGiridhar Malavali 418808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 418908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 419008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 419108de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 419208de2844SGiridhar Malavali } 419308de2844SGiridhar Malavali 419408de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 419508de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 419608de2844SGiridhar Malavali read_value &= crb_entry->value_2; 419708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 419808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 419908de2844SGiridhar Malavali read_value |= crb_entry->value_3; 420008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 420108de2844SGiridhar Malavali } 420208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 420308de2844SGiridhar Malavali } 420408de2844SGiridhar Malavali 420508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 420608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 420708de2844SGiridhar Malavali read_value |= crb_entry->value_3; 420808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 420908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 421008de2844SGiridhar Malavali } 421108de2844SGiridhar Malavali 421208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 421308de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 421408de2844SGiridhar Malavali wtime = jiffies + poll_time; 421508de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 421608de2844SGiridhar Malavali 421708de2844SGiridhar Malavali do { 421808de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 421908de2844SGiridhar Malavali == crb_entry->value_1) 422008de2844SGiridhar Malavali break; 422108de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 422208de2844SGiridhar Malavali /* capturing dump failed */ 422308de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 422408de2844SGiridhar Malavali break; 422508de2844SGiridhar Malavali } else 422608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 422708de2844SGiridhar Malavali crb_addr, 0, 0); 422808de2844SGiridhar Malavali } while (1); 422908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 423008de2844SGiridhar Malavali } 423108de2844SGiridhar Malavali 423208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 423308de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 423408de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 423508de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 423608de2844SGiridhar Malavali } else 423708de2844SGiridhar Malavali addr = crb_addr; 423808de2844SGiridhar Malavali 423908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 424008de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 424108de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 424208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 424308de2844SGiridhar Malavali } 424408de2844SGiridhar Malavali 424508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 424608de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 424708de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 424808de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 424908de2844SGiridhar Malavali } else 425008de2844SGiridhar Malavali addr = crb_addr; 425108de2844SGiridhar Malavali 425208de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 425308de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 425408de2844SGiridhar Malavali read_value = 425508de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 425608de2844SGiridhar Malavali } else 425708de2844SGiridhar Malavali read_value = crb_entry->value_1; 425808de2844SGiridhar Malavali 425908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 426008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 426108de2844SGiridhar Malavali } 426208de2844SGiridhar Malavali 426308de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 426408de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 426508de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 426608de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 426708de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 426808de2844SGiridhar Malavali if (crb_entry->value_2) 426908de2844SGiridhar Malavali read_value &= crb_entry->value_2; 427008de2844SGiridhar Malavali read_value |= crb_entry->value_3; 427108de2844SGiridhar Malavali read_value += crb_entry->value_1; 427208de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 427308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 427408de2844SGiridhar Malavali } 427508de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 427608de2844SGiridhar Malavali } 427708de2844SGiridhar Malavali return rval; 427808de2844SGiridhar Malavali } 427908de2844SGiridhar Malavali 428008de2844SGiridhar Malavali static void 428108de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 428208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 428308de2844SGiridhar Malavali { 428408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 428508de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 428608de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 428708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 428808de2844SGiridhar Malavali 428908de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 429008de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 429108de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 429208de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 429308de2844SGiridhar Malavali 429408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 429508de2844SGiridhar Malavali r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 429608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 429708de2844SGiridhar Malavali r_addr += r_stride; 429808de2844SGiridhar Malavali } 429908de2844SGiridhar Malavali *d_ptr = data_ptr; 430008de2844SGiridhar Malavali } 430108de2844SGiridhar Malavali 430208de2844SGiridhar Malavali static void 430308de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 430408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 430508de2844SGiridhar Malavali { 430608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 430708de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 430808de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 430908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 431008de2844SGiridhar Malavali 431108de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 431208de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 431308de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 431408de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 431508de2844SGiridhar Malavali s_value = mux_hdr->select_value; 431608de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 431708de2844SGiridhar Malavali 431808de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 431908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 432008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 432108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 432208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 432308de2844SGiridhar Malavali s_value += s_stride; 432408de2844SGiridhar Malavali } 432508de2844SGiridhar Malavali *d_ptr = data_ptr; 432608de2844SGiridhar Malavali } 432708de2844SGiridhar Malavali 432808de2844SGiridhar Malavali static void 432908de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 433008de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 433108de2844SGiridhar Malavali { 433208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 433308de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 433408de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 433508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 433608de2844SGiridhar Malavali 433708de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 433808de2844SGiridhar Malavali r_addr = crb_hdr->addr; 433908de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 434008de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 434108de2844SGiridhar Malavali 434208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 434308de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 434408de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 434508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 434608de2844SGiridhar Malavali r_addr += r_stride; 434708de2844SGiridhar Malavali } 434808de2844SGiridhar Malavali *d_ptr = data_ptr; 434908de2844SGiridhar Malavali } 435008de2844SGiridhar Malavali 435108de2844SGiridhar Malavali static int 435208de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 435308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 435408de2844SGiridhar Malavali { 435508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 435608de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 435708de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 435808de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 435908de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 436008de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 436108de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 436208de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 436308de2844SGiridhar Malavali 436408de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 436508de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 436608de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 436708de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 436808de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 436908de2844SGiridhar Malavali 437008de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 437108de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 437208de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 437308de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 437408de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 437508de2844SGiridhar Malavali 437608de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 437708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 437808de2844SGiridhar Malavali if (c_value_w) 437908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 438008de2844SGiridhar Malavali 438108de2844SGiridhar Malavali if (p_mask) { 438208de2844SGiridhar Malavali w_time = jiffies + p_wait; 438308de2844SGiridhar Malavali do { 438408de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 438508de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 438608de2844SGiridhar Malavali break; 438708de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 438808de2844SGiridhar Malavali /* capturing dump failed */ 438908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 439008de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 439108de2844SGiridhar Malavali "w_time: 0x%lx\n", 439208de2844SGiridhar Malavali c_value_r, p_mask, w_time); 439308de2844SGiridhar Malavali return rval; 439408de2844SGiridhar Malavali } 439508de2844SGiridhar Malavali } while (1); 439608de2844SGiridhar Malavali } 439708de2844SGiridhar Malavali 439808de2844SGiridhar Malavali addr = r_addr; 439908de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 440008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 440108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 440208de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 440308de2844SGiridhar Malavali } 440408de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 440508de2844SGiridhar Malavali } 440608de2844SGiridhar Malavali *d_ptr = data_ptr; 440708de2844SGiridhar Malavali return QLA_SUCCESS; 440808de2844SGiridhar Malavali } 440908de2844SGiridhar Malavali 441008de2844SGiridhar Malavali static void 441108de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 441208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 441308de2844SGiridhar Malavali { 441408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 441508de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 441608de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 441708de2844SGiridhar Malavali uint32_t c_value_w; 441808de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 441908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 442008de2844SGiridhar Malavali 442108de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 442208de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 442308de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 442408de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 442508de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 442608de2844SGiridhar Malavali 442708de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 442808de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 442908de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 443008de2844SGiridhar Malavali 443108de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 443208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 443308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 443408de2844SGiridhar Malavali addr = r_addr; 443508de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 443608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 443708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 443808de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 443908de2844SGiridhar Malavali } 444008de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 444108de2844SGiridhar Malavali } 444208de2844SGiridhar Malavali *d_ptr = data_ptr; 444308de2844SGiridhar Malavali } 444408de2844SGiridhar Malavali 444508de2844SGiridhar Malavali static void 444608de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 444708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 444808de2844SGiridhar Malavali { 444908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 445008de2844SGiridhar Malavali uint32_t s_addr, r_addr; 445108de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 445208de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 445308de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 445408de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 445508de2844SGiridhar Malavali 445608de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 445708de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 445808de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 445908de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 446008de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 446108de2844SGiridhar Malavali 446208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 446308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 446408de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 446508de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 446608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 446708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 446808de2844SGiridhar Malavali r_addr += r_stride; 446908de2844SGiridhar Malavali } 447008de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 447108de2844SGiridhar Malavali } 447208de2844SGiridhar Malavali *d_ptr = data_ptr; 447308de2844SGiridhar Malavali } 447408de2844SGiridhar Malavali 447508de2844SGiridhar Malavali static void 447608de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 447708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 447808de2844SGiridhar Malavali { 447908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 448008de2844SGiridhar Malavali uint32_t r_addr, r_value; 448108de2844SGiridhar Malavali uint32_t i, loop_cnt; 448208de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 448308de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 448408de2844SGiridhar Malavali 448508de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 448608de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 448708de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 448808de2844SGiridhar Malavali 448908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 449008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 449108de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 449208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 449308de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 449408de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 449508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 449608de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 449708de2844SGiridhar Malavali } 449808de2844SGiridhar Malavali *d_ptr = data_ptr; 449908de2844SGiridhar Malavali } 450008de2844SGiridhar Malavali 450108de2844SGiridhar Malavali static int 450208de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 450308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 450408de2844SGiridhar Malavali { 450508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 450608de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 450708de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 450808de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 450908de2844SGiridhar Malavali unsigned long flags; 451008de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 451108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 451208de2844SGiridhar Malavali 451308de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 451408de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 451508de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 451608de2844SGiridhar Malavali 451708de2844SGiridhar Malavali if (r_addr & 0xf) { 451808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 451908de2844SGiridhar Malavali "Read addr 0x%x not 16 bytes alligned\n", r_addr); 452008de2844SGiridhar Malavali return rval; 452108de2844SGiridhar Malavali } 452208de2844SGiridhar Malavali 452308de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 452408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 452508de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 452608de2844SGiridhar Malavali m_hdr->read_data_size); 452708de2844SGiridhar Malavali return rval; 452808de2844SGiridhar Malavali } 452908de2844SGiridhar Malavali 453008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 453108de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 453208de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 453308de2844SGiridhar Malavali 453408de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 453508de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 453608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 453708de2844SGiridhar Malavali r_value = 0; 453808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 453908de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 454008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 454108de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 454208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 454308de2844SGiridhar Malavali 454408de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 454508de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 454608de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 454708de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 454808de2844SGiridhar Malavali break; 454908de2844SGiridhar Malavali } 455008de2844SGiridhar Malavali 455108de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 455208de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 455308de2844SGiridhar Malavali "failed to read through agent\n"); 455408de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 455508de2844SGiridhar Malavali return rval; 455608de2844SGiridhar Malavali } 455708de2844SGiridhar Malavali 455808de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 455908de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 456008de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 456108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 456208de2844SGiridhar Malavali } 456308de2844SGiridhar Malavali r_addr += 16; 456408de2844SGiridhar Malavali } 456508de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 456608de2844SGiridhar Malavali *d_ptr = data_ptr; 456708de2844SGiridhar Malavali return QLA_SUCCESS; 456808de2844SGiridhar Malavali } 456908de2844SGiridhar Malavali 457008de2844SGiridhar Malavali static int 457108de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 457208de2844SGiridhar Malavali { 457308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 457408de2844SGiridhar Malavali uint64_t chksum = 0; 457508de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 457608de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 457708de2844SGiridhar Malavali 457808de2844SGiridhar Malavali while (count-- > 0) 457908de2844SGiridhar Malavali chksum += *d_ptr++; 458008de2844SGiridhar Malavali while (chksum >> 32) 458108de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 458208de2844SGiridhar Malavali return ~chksum; 458308de2844SGiridhar Malavali } 458408de2844SGiridhar Malavali 458508de2844SGiridhar Malavali static void 458608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 458708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 458808de2844SGiridhar Malavali { 458908de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 459008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 459108de2844SGiridhar Malavali "Skipping entry[%d]: " 459208de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 459308de2844SGiridhar Malavali index, entry_hdr->entry_type, 459408de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 459508de2844SGiridhar Malavali } 459608de2844SGiridhar Malavali 459708de2844SGiridhar Malavali int 459808de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 459908de2844SGiridhar Malavali { 460008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 460108de2844SGiridhar Malavali int no_entry_hdr = 0; 460208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 460308de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 460408de2844SGiridhar Malavali uint32_t *data_ptr; 460508de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 460608de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 460708de2844SGiridhar Malavali 460808de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 460908de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 461008de2844SGiridhar Malavali 461108de2844SGiridhar Malavali if (ha->fw_dumped) { 461208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb037, 461308de2844SGiridhar Malavali "Firmware dump available to retrive\n"); 461408de2844SGiridhar Malavali goto md_failed; 461508de2844SGiridhar Malavali } 461608de2844SGiridhar Malavali 461708de2844SGiridhar Malavali ha->fw_dumped = 0; 461808de2844SGiridhar Malavali 461908de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 462008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 462108de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 462208de2844SGiridhar Malavali goto md_failed; 462308de2844SGiridhar Malavali } 462408de2844SGiridhar Malavali 462508de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 462608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 462708de2844SGiridhar Malavali "Template checksum validation error\n"); 462808de2844SGiridhar Malavali goto md_failed; 462908de2844SGiridhar Malavali } 463008de2844SGiridhar Malavali 463108de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 463208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 463308de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 463408de2844SGiridhar Malavali 463508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 463608de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 463708de2844SGiridhar Malavali 463808de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 463908de2844SGiridhar Malavali 464008de2844SGiridhar Malavali /* Validate whether required debug level is set */ 464108de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 464208de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 464308de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 464408de2844SGiridhar Malavali f_capture_mask); 464508de2844SGiridhar Malavali goto md_failed; 464608de2844SGiridhar Malavali } 464708de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 464808de2844SGiridhar Malavali 464908de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 465008de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 465108de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 465208de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 465308de2844SGiridhar Malavali 465408de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 465508de2844SGiridhar Malavali 465608de2844SGiridhar Malavali ql_dbg(ql_log_info, vha, 0xb03d, 465708de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 465808de2844SGiridhar Malavali 465908de2844SGiridhar Malavali /* Check whether template obtained is valid */ 466008de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 466108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 466208de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 466308de2844SGiridhar Malavali tmplt_hdr->entry_type); 466408de2844SGiridhar Malavali goto md_failed; 466508de2844SGiridhar Malavali } 466608de2844SGiridhar Malavali 466708de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 466808de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 466908de2844SGiridhar Malavali 467008de2844SGiridhar Malavali /* Walk through the entry headers */ 467108de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 467208de2844SGiridhar Malavali 467308de2844SGiridhar Malavali if (data_collected > total_data_size) { 467408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 467508de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 467608de2844SGiridhar Malavali data_collected); 467708de2844SGiridhar Malavali goto md_failed; 467808de2844SGiridhar Malavali } 467908de2844SGiridhar Malavali 468008de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 468108de2844SGiridhar Malavali ql2xmdcapmask)) { 468208de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 468308de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 468408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 468508de2844SGiridhar Malavali "Skipping entry[%d]: " 468608de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 468708de2844SGiridhar Malavali i, entry_hdr->entry_type, 468808de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 468908de2844SGiridhar Malavali goto skip_nxt_entry; 469008de2844SGiridhar Malavali } 469108de2844SGiridhar Malavali 469208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 469308de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 469408de2844SGiridhar Malavali "entry_type: 0x%x, captrue_mask: 0x%x\n", 469508de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 469608de2844SGiridhar Malavali entry_hdr->entry_type, 469708de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 469808de2844SGiridhar Malavali 469908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 470008de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 470108de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 470208de2844SGiridhar Malavali 470308de2844SGiridhar Malavali /* Decode the entry type and take 470408de2844SGiridhar Malavali * required action to capture debug data */ 470508de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 470608de2844SGiridhar Malavali case QLA82XX_RDEND: 470708de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 470808de2844SGiridhar Malavali break; 470908de2844SGiridhar Malavali case QLA82XX_CNTRL: 471008de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 471108de2844SGiridhar Malavali entry_hdr, &data_ptr); 471208de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 471308de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 471408de2844SGiridhar Malavali goto md_failed; 471508de2844SGiridhar Malavali } 471608de2844SGiridhar Malavali break; 471708de2844SGiridhar Malavali case QLA82XX_RDCRB: 471808de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 471908de2844SGiridhar Malavali entry_hdr, &data_ptr); 472008de2844SGiridhar Malavali break; 472108de2844SGiridhar Malavali case QLA82XX_RDMEM: 472208de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 472308de2844SGiridhar Malavali entry_hdr, &data_ptr); 472408de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 472508de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 472608de2844SGiridhar Malavali goto md_failed; 472708de2844SGiridhar Malavali } 472808de2844SGiridhar Malavali break; 472908de2844SGiridhar Malavali case QLA82XX_BOARD: 473008de2844SGiridhar Malavali case QLA82XX_RDROM: 473108de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 473208de2844SGiridhar Malavali entry_hdr, &data_ptr); 473308de2844SGiridhar Malavali break; 473408de2844SGiridhar Malavali case QLA82XX_L2DTG: 473508de2844SGiridhar Malavali case QLA82XX_L2ITG: 473608de2844SGiridhar Malavali case QLA82XX_L2DAT: 473708de2844SGiridhar Malavali case QLA82XX_L2INS: 473808de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 473908de2844SGiridhar Malavali entry_hdr, &data_ptr); 474008de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 474108de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 474208de2844SGiridhar Malavali goto md_failed; 474308de2844SGiridhar Malavali } 474408de2844SGiridhar Malavali break; 474508de2844SGiridhar Malavali case QLA82XX_L1DAT: 474608de2844SGiridhar Malavali case QLA82XX_L1INS: 474708de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 474808de2844SGiridhar Malavali entry_hdr, &data_ptr); 474908de2844SGiridhar Malavali break; 475008de2844SGiridhar Malavali case QLA82XX_RDOCM: 475108de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 475208de2844SGiridhar Malavali entry_hdr, &data_ptr); 475308de2844SGiridhar Malavali break; 475408de2844SGiridhar Malavali case QLA82XX_RDMUX: 475508de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 475608de2844SGiridhar Malavali entry_hdr, &data_ptr); 475708de2844SGiridhar Malavali break; 475808de2844SGiridhar Malavali case QLA82XX_QUEUE: 475908de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 476008de2844SGiridhar Malavali entry_hdr, &data_ptr); 476108de2844SGiridhar Malavali break; 476208de2844SGiridhar Malavali case QLA82XX_RDNOP: 476308de2844SGiridhar Malavali default: 476408de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 476508de2844SGiridhar Malavali break; 476608de2844SGiridhar Malavali } 476708de2844SGiridhar Malavali 476808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 476908de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 477008de2844SGiridhar Malavali 477108de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 477208de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 477308de2844SGiridhar Malavali skip_nxt_entry: 477408de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 477508de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 477608de2844SGiridhar Malavali } 477708de2844SGiridhar Malavali 477808de2844SGiridhar Malavali if (data_collected != total_data_size) { 477908de2844SGiridhar Malavali ql_dbg(ql_log_warn, vha, 0xb043, 478008de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 478108de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 478208de2844SGiridhar Malavali data_collected, total_data_size); 478308de2844SGiridhar Malavali goto md_failed; 478408de2844SGiridhar Malavali } 478508de2844SGiridhar Malavali 478608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 478708de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 478808de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 478908de2844SGiridhar Malavali ha->fw_dumped = 1; 479008de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 479108de2844SGiridhar Malavali 479208de2844SGiridhar Malavali md_failed: 479308de2844SGiridhar Malavali return rval; 479408de2844SGiridhar Malavali } 479508de2844SGiridhar Malavali 479608de2844SGiridhar Malavali int 479708de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 479808de2844SGiridhar Malavali { 479908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 480008de2844SGiridhar Malavali int i, k; 480108de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 480208de2844SGiridhar Malavali 480308de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 480408de2844SGiridhar Malavali 480508de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 480608de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 480708de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 480808de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 480908de2844SGiridhar Malavali ql2xmdcapmask); 481008de2844SGiridhar Malavali } 481108de2844SGiridhar Malavali 481208de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 481308de2844SGiridhar Malavali if (i & ql2xmdcapmask) 481408de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 481508de2844SGiridhar Malavali } 481608de2844SGiridhar Malavali 481708de2844SGiridhar Malavali if (ha->md_dump) { 481808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 481908de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 482008de2844SGiridhar Malavali return 1; 482108de2844SGiridhar Malavali } 482208de2844SGiridhar Malavali 482308de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 482408de2844SGiridhar Malavali if (ha->md_dump == NULL) { 482508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 482608de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 482708de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 482808de2844SGiridhar Malavali return 1; 482908de2844SGiridhar Malavali } 483008de2844SGiridhar Malavali return 0; 483108de2844SGiridhar Malavali } 483208de2844SGiridhar Malavali 483308de2844SGiridhar Malavali void 483408de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 483508de2844SGiridhar Malavali { 483608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 483708de2844SGiridhar Malavali 483808de2844SGiridhar Malavali /* Release the template header allocated */ 483908de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 484008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 484108de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 484208de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 484308de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 484408de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 484508de2844SGiridhar Malavali ha->md_tmplt_hdr = 0; 484608de2844SGiridhar Malavali } 484708de2844SGiridhar Malavali 484808de2844SGiridhar Malavali /* Release the template data buffer allocated */ 484908de2844SGiridhar Malavali if (ha->md_dump) { 485008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 485108de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 485208de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 485308de2844SGiridhar Malavali vfree(ha->md_dump); 485408de2844SGiridhar Malavali ha->md_dump_size = 0; 485508de2844SGiridhar Malavali ha->md_dump = 0; 485608de2844SGiridhar Malavali } 485708de2844SGiridhar Malavali } 485808de2844SGiridhar Malavali 485908de2844SGiridhar Malavali void 486008de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 486108de2844SGiridhar Malavali { 486208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 486308de2844SGiridhar Malavali int rval; 486408de2844SGiridhar Malavali 486508de2844SGiridhar Malavali /* Get Minidump template size */ 486608de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 486708de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 486808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 486908de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 487008de2844SGiridhar Malavali ha->md_template_size / 1024); 487108de2844SGiridhar Malavali 487208de2844SGiridhar Malavali /* Get Minidump template */ 487308de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 487408de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 487508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 487608de2844SGiridhar Malavali "MiniDump Template obtained\n"); 487708de2844SGiridhar Malavali 487808de2844SGiridhar Malavali /* Allocate memory for minidump */ 487908de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 488008de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 488108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 488208de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 488308de2844SGiridhar Malavali ha->md_dump_size / 1024); 488408de2844SGiridhar Malavali else { 488508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 488608de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 488708de2844SGiridhar Malavali ha->md_tmplt_hdr, 488808de2844SGiridhar Malavali ha->md_template_size / 1024); 488908de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 489008de2844SGiridhar Malavali ha->md_template_size, 489108de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 489208de2844SGiridhar Malavali ha->md_tmplt_hdr = 0; 489308de2844SGiridhar Malavali } 489408de2844SGiridhar Malavali 489508de2844SGiridhar Malavali } 489608de2844SGiridhar Malavali } 489708de2844SGiridhar Malavali } 4898999916dcSSaurav Kashyap 4899999916dcSSaurav Kashyap int 4900999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4901999916dcSSaurav Kashyap { 4902999916dcSSaurav Kashyap 4903999916dcSSaurav Kashyap int rval; 4904999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4905999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4906999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4907999916dcSSaurav Kashyap 4908999916dcSSaurav Kashyap if (rval) { 4909999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4910999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4911999916dcSSaurav Kashyap goto exit; 4912999916dcSSaurav Kashyap } 4913999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4914999916dcSSaurav Kashyap exit: 4915999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4916999916dcSSaurav Kashyap return rval; 4917999916dcSSaurav Kashyap } 4918999916dcSSaurav Kashyap 4919999916dcSSaurav Kashyap int 4920999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4921999916dcSSaurav Kashyap { 4922999916dcSSaurav Kashyap 4923999916dcSSaurav Kashyap int rval; 4924999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4925999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4926999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4927999916dcSSaurav Kashyap 4928999916dcSSaurav Kashyap if (rval) { 4929999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4930999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4931999916dcSSaurav Kashyap goto exit; 4932999916dcSSaurav Kashyap } 4933999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4934999916dcSSaurav Kashyap exit: 4935999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4936999916dcSSaurav Kashyap return rval; 4937999916dcSSaurav Kashyap } 4938