1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 3bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39fa492630SSaurav Kashyap static int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 4561778a1cSBart Van Assche const int MD_MIU_TEST_AGT_RDDATA[] = { 4661778a1cSBart Van Assche 0x410000A8, 0x410000AC, 4761778a1cSBart Van Assche 0x410000B8, 0x410000BC 4861778a1cSBart Van Assche }; 4961778a1cSBart Van Assche 50a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 51a9083016SGiridhar Malavali { 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 97a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 98a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 99a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 101a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 102a9083016SGiridhar Malavali /* 103a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 104a9083016SGiridhar Malavali */ 105a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 106a9083016SGiridhar Malavali 107a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 108a9083016SGiridhar Malavali } 109a9083016SGiridhar Malavali 110fa492630SSaurav Kashyap static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 111a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 112a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 113a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 114a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 115a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 116a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 117a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 118a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 119a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 123a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 124a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 125a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 126a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 127a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 128a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 129a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 130a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 131a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 132a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 133a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 134a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 145a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 150a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 161a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 166a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 177a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 182a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 193a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 194a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 195a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 196a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 197a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 198a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 199a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 200a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 201a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 202a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 204a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 205a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 206a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 207a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 208a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 211a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 212a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 213a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 214a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 215a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 216a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 217a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 218a9083016SGiridhar Malavali {{{0} } }, 219a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 220a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 221a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 222a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 223a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 224a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 225a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 226a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 230a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 231a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 232a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 233a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 234a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 235a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 236a9083016SGiridhar Malavali {{{0} } }, 237a9083016SGiridhar Malavali {{{0} } }, 238a9083016SGiridhar Malavali {{{0} } }, 239a9083016SGiridhar Malavali {{{0} } }, 240a9083016SGiridhar Malavali {{{0} } }, 241a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 243a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 244a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 245a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 246a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 247a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 248a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 249a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 250a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 252a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 253a9083016SGiridhar Malavali {{{0} } }, 254a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 255a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 256a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 257a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 260a9083016SGiridhar Malavali {{{0} } }, 261a9083016SGiridhar Malavali {{{0} } }, 262a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 263a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 264a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 265a9083016SGiridhar Malavali }; 266a9083016SGiridhar Malavali 267a9083016SGiridhar Malavali /* 268a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 269a9083016SGiridhar Malavali */ 270fa492630SSaurav Kashyap static unsigned qla82xx_crb_hub_agt[64] = { 271a9083016SGiridhar Malavali 0, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 275a9083016SGiridhar Malavali 0, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 293a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 296a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 305a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 306a9083016SGiridhar Malavali 0, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali 0, 309a9083016SGiridhar Malavali 0, 310a9083016SGiridhar Malavali 0, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 312a9083016SGiridhar Malavali 0, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 318a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 327a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 328a9083016SGiridhar Malavali 0, 329a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 330a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 331a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 332a9083016SGiridhar Malavali 0, 333a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 334a9083016SGiridhar Malavali 0, 335a9083016SGiridhar Malavali }; 336a9083016SGiridhar Malavali 337f1af6208SGiridhar Malavali /* Device states */ 338fa492630SSaurav Kashyap static char *q_dev_state[] = { 339f1af6208SGiridhar Malavali "Unknown", 340f1af6208SGiridhar Malavali "Cold", 341f1af6208SGiridhar Malavali "Initializing", 342f1af6208SGiridhar Malavali "Ready", 343f1af6208SGiridhar Malavali "Need Reset", 344f1af6208SGiridhar Malavali "Need Quiescent", 345f1af6208SGiridhar Malavali "Failed", 346f1af6208SGiridhar Malavali "Quiescent", 347f1af6208SGiridhar Malavali }; 348f1af6208SGiridhar Malavali 34908de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 35008de2844SGiridhar Malavali { 35108de2844SGiridhar Malavali return q_dev_state[dev_state]; 35208de2844SGiridhar Malavali } 35308de2844SGiridhar Malavali 354a9083016SGiridhar Malavali /* 3558dfa4b5aSBart Van Assche * In: 'off_in' is offset from CRB space in 128M pci map 3568dfa4b5aSBart Van Assche * Out: 'off_out' is 2M pci map addr 357a9083016SGiridhar Malavali * side effect: lock crb window 358a9083016SGiridhar Malavali */ 359a9083016SGiridhar Malavali static void 3608dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 3618dfa4b5aSBart Van Assche void __iomem **off_out) 362a9083016SGiridhar Malavali { 363a9083016SGiridhar Malavali u32 win_read; 3647c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 365a9083016SGiridhar Malavali 3668dfa4b5aSBart Van Assche ha->crb_win = CRB_HI(off_in); 3678dfa4b5aSBart Van Assche writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 368a9083016SGiridhar Malavali 369a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 370a9083016SGiridhar Malavali * to use it. 371a9083016SGiridhar Malavali */ 3728dfa4b5aSBart Van Assche win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 373a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3747c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3757c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3767c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 3778dfa4b5aSBart Van Assche __func__, ha->crb_win, win_read, off_in); 378a9083016SGiridhar Malavali } 3798dfa4b5aSBart Van Assche *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 380a9083016SGiridhar Malavali } 381a9083016SGiridhar Malavali 382a9083016SGiridhar Malavali static inline unsigned long 383a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 384a9083016SGiridhar Malavali { 3857c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 386a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 387a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 388a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 389a9083016SGiridhar Malavali * regs are in both windows. 390a9083016SGiridhar Malavali */ 391a9083016SGiridhar Malavali return off; 392a9083016SGiridhar Malavali } 393a9083016SGiridhar Malavali 394a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 395a9083016SGiridhar Malavali /* We are in first CRB window */ 396a9083016SGiridhar Malavali if (ha->curr_window != 0) 397a9083016SGiridhar Malavali WARN_ON(1); 398a9083016SGiridhar Malavali return off; 399a9083016SGiridhar Malavali } 400a9083016SGiridhar Malavali 401a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 402a9083016SGiridhar Malavali /* We are in second CRB window */ 403a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 404a9083016SGiridhar Malavali 405a9083016SGiridhar Malavali if (ha->curr_window != 1) 406a9083016SGiridhar Malavali return off; 407a9083016SGiridhar Malavali 408a9083016SGiridhar Malavali /* We are in the QM or direct access 409a9083016SGiridhar Malavali * register region - do nothing 410a9083016SGiridhar Malavali */ 411a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 412a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 413a9083016SGiridhar Malavali return off; 414a9083016SGiridhar Malavali } 415a9083016SGiridhar Malavali /* strange address given */ 4167c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 417d8424f68SJoe Perches "%s: Warning: unm_nic_pci_set_crbwindow " 4187c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4197c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 420a9083016SGiridhar Malavali return off; 421a9083016SGiridhar Malavali } 422a9083016SGiridhar Malavali 42377e334d2SGiridhar Malavali static int 4248dfa4b5aSBart Van Assche qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 4258dfa4b5aSBart Van Assche void __iomem **off_out) 42677e334d2SGiridhar Malavali { 42777e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42877e334d2SGiridhar Malavali 4298dfa4b5aSBart Van Assche if (off_in >= QLA82XX_CRB_MAX) 43077e334d2SGiridhar Malavali return -1; 43177e334d2SGiridhar Malavali 4328dfa4b5aSBart Van Assche if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 4338dfa4b5aSBart Van Assche *off_out = (off_in - QLA82XX_PCI_CAMQM) + 43477e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 43577e334d2SGiridhar Malavali return 0; 43677e334d2SGiridhar Malavali } 43777e334d2SGiridhar Malavali 4388dfa4b5aSBart Van Assche if (off_in < QLA82XX_PCI_CRBSPACE) 43977e334d2SGiridhar Malavali return -1; 44077e334d2SGiridhar Malavali 4410874f8ecSBart Van Assche off_in -= QLA82XX_PCI_CRBSPACE; 44277e334d2SGiridhar Malavali 44377e334d2SGiridhar Malavali /* Try direct map */ 4448dfa4b5aSBart Van Assche m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 44577e334d2SGiridhar Malavali 4468dfa4b5aSBart Van Assche if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 4478dfa4b5aSBart Van Assche *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 44877e334d2SGiridhar Malavali return 0; 44977e334d2SGiridhar Malavali } 45077e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 4510874f8ecSBart Van Assche *off_out = (void __iomem *)off_in; 45277e334d2SGiridhar Malavali return 1; 45377e334d2SGiridhar Malavali } 45477e334d2SGiridhar Malavali 45577e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 45677e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45777e334d2SGiridhar Malavali { 45877e334d2SGiridhar Malavali int done = 0, timeout = 0; 45977e334d2SGiridhar Malavali 46077e334d2SGiridhar Malavali while (!done) { 46177e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 46277e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 46377e334d2SGiridhar Malavali if (done == 1) 46477e334d2SGiridhar Malavali break; 46577e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 46677e334d2SGiridhar Malavali return -1; 46777e334d2SGiridhar Malavali timeout++; 46877e334d2SGiridhar Malavali } 46977e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 47077e334d2SGiridhar Malavali return 0; 47177e334d2SGiridhar Malavali } 47277e334d2SGiridhar Malavali 473a9083016SGiridhar Malavali int 4748dfa4b5aSBart Van Assche qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 475a9083016SGiridhar Malavali { 4768dfa4b5aSBart Van Assche void __iomem *off; 477a9083016SGiridhar Malavali unsigned long flags = 0; 478a9083016SGiridhar Malavali int rv; 479a9083016SGiridhar Malavali 4808dfa4b5aSBart Van Assche rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 481a9083016SGiridhar Malavali 482a9083016SGiridhar Malavali BUG_ON(rv == -1); 483a9083016SGiridhar Malavali 484a9083016SGiridhar Malavali if (rv == 1) { 4858d16366bSBart Van Assche #ifndef __CHECKER__ 486a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 4878d16366bSBart Van Assche #endif 488a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 4898dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 490a9083016SGiridhar Malavali } 491a9083016SGiridhar Malavali 492a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 493a9083016SGiridhar Malavali 494a9083016SGiridhar Malavali if (rv == 1) { 495a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 4968d16366bSBart Van Assche #ifndef __CHECKER__ 497a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 4988d16366bSBart Van Assche #endif 499a9083016SGiridhar Malavali } 500a9083016SGiridhar Malavali return 0; 501a9083016SGiridhar Malavali } 502a9083016SGiridhar Malavali 503a9083016SGiridhar Malavali int 5048dfa4b5aSBart Van Assche qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 505a9083016SGiridhar Malavali { 5068dfa4b5aSBart Van Assche void __iomem *off; 507a9083016SGiridhar Malavali unsigned long flags = 0; 508a9083016SGiridhar Malavali int rv; 509a9083016SGiridhar Malavali u32 data; 510a9083016SGiridhar Malavali 5118dfa4b5aSBart Van Assche rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 512a9083016SGiridhar Malavali 513a9083016SGiridhar Malavali BUG_ON(rv == -1); 514a9083016SGiridhar Malavali 515a9083016SGiridhar Malavali if (rv == 1) { 5168d16366bSBart Van Assche #ifndef __CHECKER__ 517a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 5188d16366bSBart Van Assche #endif 519a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 5208dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 521a9083016SGiridhar Malavali } 5228dfa4b5aSBart Van Assche data = RD_REG_DWORD(off); 523a9083016SGiridhar Malavali 524a9083016SGiridhar Malavali if (rv == 1) { 525a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 5268d16366bSBart Van Assche #ifndef __CHECKER__ 527a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 5288d16366bSBart Van Assche #endif 529a9083016SGiridhar Malavali } 530a9083016SGiridhar Malavali return data; 531a9083016SGiridhar Malavali } 532a9083016SGiridhar Malavali 533a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 534a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 535a9083016SGiridhar Malavali { 536a9083016SGiridhar Malavali int i; 537a9083016SGiridhar Malavali int done = 0, timeout = 0; 538a9083016SGiridhar Malavali 539a9083016SGiridhar Malavali while (!done) { 540a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 541a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 542a9083016SGiridhar Malavali if (done == 1) 543a9083016SGiridhar Malavali break; 544a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 545a9083016SGiridhar Malavali return -1; 546a9083016SGiridhar Malavali 547a9083016SGiridhar Malavali timeout++; 548a9083016SGiridhar Malavali 549a9083016SGiridhar Malavali /* Yield CPU */ 550a9083016SGiridhar Malavali if (!in_interrupt()) 551a9083016SGiridhar Malavali schedule(); 552a9083016SGiridhar Malavali else { 553a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 554a9083016SGiridhar Malavali cpu_relax(); 555a9083016SGiridhar Malavali } 556a9083016SGiridhar Malavali } 557a9083016SGiridhar Malavali 558a9083016SGiridhar Malavali return 0; 559a9083016SGiridhar Malavali } 560a9083016SGiridhar Malavali 561a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 562a9083016SGiridhar Malavali { 563a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 564a9083016SGiridhar Malavali } 565a9083016SGiridhar Malavali 566a9083016SGiridhar Malavali /* 567a9083016SGiridhar Malavali * check memory access boundary. 568a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 569a9083016SGiridhar Malavali */ 570a9083016SGiridhar Malavali static unsigned long 571a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 572a9083016SGiridhar Malavali unsigned long long addr, int size) 573a9083016SGiridhar Malavali { 574df3f4cd0SBart Van Assche if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 575a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 576df3f4cd0SBart Van Assche !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 577a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 578a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 579a9083016SGiridhar Malavali return 0; 580a9083016SGiridhar Malavali else 581a9083016SGiridhar Malavali return 1; 582a9083016SGiridhar Malavali } 583a9083016SGiridhar Malavali 584fa492630SSaurav Kashyap static int qla82xx_pci_set_window_warning_count; 585a9083016SGiridhar Malavali 58677e334d2SGiridhar Malavali static unsigned long 587a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 588a9083016SGiridhar Malavali { 589a9083016SGiridhar Malavali int window; 590a9083016SGiridhar Malavali u32 win_read; 5917c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 592a9083016SGiridhar Malavali 593df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 594a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 595a9083016SGiridhar Malavali /* DDR network side */ 596a9083016SGiridhar Malavali window = MN_WIN(addr); 597a9083016SGiridhar Malavali ha->ddr_mn_window = window; 598a9083016SGiridhar Malavali qla82xx_wr_32(ha, 599a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 600a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 601a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 602a9083016SGiridhar Malavali if ((win_read << 17) != window) { 6037c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 6047c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 605a9083016SGiridhar Malavali __func__, window, win_read); 606a9083016SGiridhar Malavali } 607a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 608df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 609a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 610a9083016SGiridhar Malavali unsigned int temp1; 611bd432bb5SBart Van Assche 612a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 6137c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 614a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 615a9083016SGiridhar Malavali addr = -1UL; 616a9083016SGiridhar Malavali } 617a9083016SGiridhar Malavali window = OCM_WIN(addr); 618a9083016SGiridhar Malavali ha->ddr_mn_window = window; 619a9083016SGiridhar Malavali qla82xx_wr_32(ha, 620a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 621a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 622a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 623a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 624a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 625a9083016SGiridhar Malavali if (win_read != temp1) { 6267c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6277c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 628a9083016SGiridhar Malavali __func__, temp1, win_read); 629a9083016SGiridhar Malavali } 630a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 631a9083016SGiridhar Malavali 632df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 633a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 634a9083016SGiridhar Malavali /* QDR network side */ 635a9083016SGiridhar Malavali window = MS_WIN(addr); 636a9083016SGiridhar Malavali ha->qdr_sn_window = window; 637a9083016SGiridhar Malavali qla82xx_wr_32(ha, 638a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 639a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 640a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 641a9083016SGiridhar Malavali if (win_read != window) { 6427c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6437c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 644a9083016SGiridhar Malavali __func__, window, win_read); 645a9083016SGiridhar Malavali } 646a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 647a9083016SGiridhar Malavali } else { 648a9083016SGiridhar Malavali /* 649a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 650a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 651a9083016SGiridhar Malavali */ 652a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 653a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6557c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6567c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 657a9083016SGiridhar Malavali } 658a9083016SGiridhar Malavali addr = -1UL; 659a9083016SGiridhar Malavali } 660a9083016SGiridhar Malavali return addr; 661a9083016SGiridhar Malavali } 662a9083016SGiridhar Malavali 663a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 664a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 665a9083016SGiridhar Malavali unsigned long long addr) 666a9083016SGiridhar Malavali { 667a9083016SGiridhar Malavali int window; 668a9083016SGiridhar Malavali unsigned long long qdr_max; 669a9083016SGiridhar Malavali 670a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 671a9083016SGiridhar Malavali 672a9083016SGiridhar Malavali /* DDR network side */ 673df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 674a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 675a9083016SGiridhar Malavali BUG(); 676df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 677a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 678a9083016SGiridhar Malavali return 1; 679df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 680a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 681a9083016SGiridhar Malavali return 1; 682df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 683a9083016SGiridhar Malavali /* QDR network side */ 684a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 685a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 686a9083016SGiridhar Malavali return 1; 687a9083016SGiridhar Malavali } 688a9083016SGiridhar Malavali return 0; 689a9083016SGiridhar Malavali } 690a9083016SGiridhar Malavali 691a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 692a9083016SGiridhar Malavali u64 off, void *data, int size) 693a9083016SGiridhar Malavali { 694a9083016SGiridhar Malavali unsigned long flags; 695fa492630SSaurav Kashyap void __iomem *addr = NULL; 696a9083016SGiridhar Malavali int ret = 0; 697a9083016SGiridhar Malavali u64 start; 698fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 699a9083016SGiridhar Malavali unsigned long mem_base; 700a9083016SGiridhar Malavali unsigned long mem_page; 7017c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 702a9083016SGiridhar Malavali 703a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 704a9083016SGiridhar Malavali 705a9083016SGiridhar Malavali /* 706a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 707a9083016SGiridhar Malavali * do not access. 708a9083016SGiridhar Malavali */ 709a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 710a9083016SGiridhar Malavali if ((start == -1UL) || 711a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 712a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7137c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 7147c3df132SSaurav Kashyap "%s out of bound pci memory " 7157c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7167c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 717a9083016SGiridhar Malavali return -1; 718a9083016SGiridhar Malavali } 719a9083016SGiridhar Malavali 720a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 721a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 722a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 723a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 724a9083016SGiridhar Malavali * consecutive pages. 725a9083016SGiridhar Malavali */ 726a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 727a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 728a9083016SGiridhar Malavali else 729a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 730fa492630SSaurav Kashyap if (mem_ptr == NULL) { 731a9083016SGiridhar Malavali *(u8 *)data = 0; 732a9083016SGiridhar Malavali return -1; 733a9083016SGiridhar Malavali } 734a9083016SGiridhar Malavali addr = mem_ptr; 735a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 736a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 737a9083016SGiridhar Malavali 738a9083016SGiridhar Malavali switch (size) { 739a9083016SGiridhar Malavali case 1: 740a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 741a9083016SGiridhar Malavali break; 742a9083016SGiridhar Malavali case 2: 743a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 744a9083016SGiridhar Malavali break; 745a9083016SGiridhar Malavali case 4: 746a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 747a9083016SGiridhar Malavali break; 748a9083016SGiridhar Malavali case 8: 749a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 750a9083016SGiridhar Malavali break; 751a9083016SGiridhar Malavali default: 752a9083016SGiridhar Malavali ret = -1; 753a9083016SGiridhar Malavali break; 754a9083016SGiridhar Malavali } 755a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 756a9083016SGiridhar Malavali 757a9083016SGiridhar Malavali if (mem_ptr) 758a9083016SGiridhar Malavali iounmap(mem_ptr); 759a9083016SGiridhar Malavali return ret; 760a9083016SGiridhar Malavali } 761a9083016SGiridhar Malavali 762a9083016SGiridhar Malavali static int 763a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 764a9083016SGiridhar Malavali u64 off, void *data, int size) 765a9083016SGiridhar Malavali { 766a9083016SGiridhar Malavali unsigned long flags; 767fa492630SSaurav Kashyap void __iomem *addr = NULL; 768a9083016SGiridhar Malavali int ret = 0; 769a9083016SGiridhar Malavali u64 start; 770fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 771a9083016SGiridhar Malavali unsigned long mem_base; 772a9083016SGiridhar Malavali unsigned long mem_page; 7737c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 774a9083016SGiridhar Malavali 775a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 776a9083016SGiridhar Malavali 777a9083016SGiridhar Malavali /* 778a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 779a9083016SGiridhar Malavali * do not access. 780a9083016SGiridhar Malavali */ 781a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 782a9083016SGiridhar Malavali if ((start == -1UL) || 783a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 784a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7857c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7860bf0efa1SColin Ian King "%s out of bound memory " 7877c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7887c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 789a9083016SGiridhar Malavali return -1; 790a9083016SGiridhar Malavali } 791a9083016SGiridhar Malavali 792a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 793a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 794a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 795a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 796a9083016SGiridhar Malavali * consecutive pages. 797a9083016SGiridhar Malavali */ 798a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 799a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 800a9083016SGiridhar Malavali else 801a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 802fa492630SSaurav Kashyap if (mem_ptr == NULL) 803a9083016SGiridhar Malavali return -1; 804a9083016SGiridhar Malavali 805a9083016SGiridhar Malavali addr = mem_ptr; 806a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 807a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 808a9083016SGiridhar Malavali 809a9083016SGiridhar Malavali switch (size) { 810a9083016SGiridhar Malavali case 1: 811a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 812a9083016SGiridhar Malavali break; 813a9083016SGiridhar Malavali case 2: 814a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 815a9083016SGiridhar Malavali break; 816a9083016SGiridhar Malavali case 4: 817a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 818a9083016SGiridhar Malavali break; 819a9083016SGiridhar Malavali case 8: 820a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 821a9083016SGiridhar Malavali break; 822a9083016SGiridhar Malavali default: 823a9083016SGiridhar Malavali ret = -1; 824a9083016SGiridhar Malavali break; 825a9083016SGiridhar Malavali } 826a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 827a9083016SGiridhar Malavali if (mem_ptr) 828a9083016SGiridhar Malavali iounmap(mem_ptr); 829a9083016SGiridhar Malavali return ret; 830a9083016SGiridhar Malavali } 831a9083016SGiridhar Malavali 832a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 83377e334d2SGiridhar Malavali static unsigned long 83477e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 835a9083016SGiridhar Malavali { 836a9083016SGiridhar Malavali int i; 837a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 838a9083016SGiridhar Malavali 839a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 840a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 841a9083016SGiridhar Malavali 842a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 843a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 844a9083016SGiridhar Malavali offset = addr & 0x000fffff; 845a9083016SGiridhar Malavali 846a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 847a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 848a9083016SGiridhar Malavali pci_base = i << 20; 849a9083016SGiridhar Malavali break; 850a9083016SGiridhar Malavali } 851a9083016SGiridhar Malavali } 852a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 853a9083016SGiridhar Malavali return pci_base; 854a9083016SGiridhar Malavali return pci_base + offset; 855a9083016SGiridhar Malavali } 856a9083016SGiridhar Malavali 857a9083016SGiridhar Malavali static long rom_max_timeout = 100; 858a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 859a9083016SGiridhar Malavali 86077e334d2SGiridhar Malavali static int 861a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 862a9083016SGiridhar Malavali { 863a9083016SGiridhar Malavali int done = 0, timeout = 0; 8646c315553SSaurav Kashyap uint32_t lock_owner = 0; 86527f4b72fSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 866a9083016SGiridhar Malavali 867a9083016SGiridhar Malavali while (!done) { 868a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 869a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 870a9083016SGiridhar Malavali if (done == 1) 871a9083016SGiridhar Malavali break; 8726c315553SSaurav Kashyap if (timeout >= qla82xx_rom_lock_timeout) { 8736c315553SSaurav Kashyap lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 8747ab3d962SSawan Chandak ql_dbg(ql_dbg_p3p, vha, 0xb157, 87527f4b72fSAtul Deshmukh "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 87627f4b72fSAtul Deshmukh __func__, ha->portnum, lock_owner); 877a9083016SGiridhar Malavali return -1; 8786c315553SSaurav Kashyap } 879a9083016SGiridhar Malavali timeout++; 880a9083016SGiridhar Malavali } 8814babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 882a9083016SGiridhar Malavali return 0; 883a9083016SGiridhar Malavali } 884a9083016SGiridhar Malavali 885d652e093SChad Dupuis static void 886d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 887d652e093SChad Dupuis { 8884babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 889d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 890d652e093SChad Dupuis } 891d652e093SChad Dupuis 89277e334d2SGiridhar Malavali static int 893a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 894a9083016SGiridhar Malavali { 895a9083016SGiridhar Malavali long timeout = 0; 896a9083016SGiridhar Malavali long done = 0 ; 8977c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 898a9083016SGiridhar Malavali 899a9083016SGiridhar Malavali while (done == 0) { 900a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 901a9083016SGiridhar Malavali done &= 4; 902a9083016SGiridhar Malavali timeout++; 903a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9047c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 9057c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 9067c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 907a9083016SGiridhar Malavali return -1; 908a9083016SGiridhar Malavali } 909a9083016SGiridhar Malavali } 910a9083016SGiridhar Malavali return 0; 911a9083016SGiridhar Malavali } 912a9083016SGiridhar Malavali 91377e334d2SGiridhar Malavali static int 914a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 915a9083016SGiridhar Malavali { 916a9083016SGiridhar Malavali long timeout = 0; 917a9083016SGiridhar Malavali long done = 0 ; 9187c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 919a9083016SGiridhar Malavali 920a9083016SGiridhar Malavali while (done == 0) { 921a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 922a9083016SGiridhar Malavali done &= 2; 923a9083016SGiridhar Malavali timeout++; 924a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9257c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9267c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9277c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 928a9083016SGiridhar Malavali return -1; 929a9083016SGiridhar Malavali } 930a9083016SGiridhar Malavali } 931a9083016SGiridhar Malavali return 0; 932a9083016SGiridhar Malavali } 933a9083016SGiridhar Malavali 934fa492630SSaurav Kashyap static int 9352b29d96dSChad Dupuis qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 9362b29d96dSChad Dupuis { 9372b29d96dSChad Dupuis uint32_t off_value, rval = 0; 9382b29d96dSChad Dupuis 9398dfa4b5aSBart Van Assche WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 9402b29d96dSChad Dupuis 9412b29d96dSChad Dupuis /* Read back value to make sure write has gone through */ 9428dfa4b5aSBart Van Assche RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); 9432b29d96dSChad Dupuis off_value = (off & 0x0000FFFF); 9442b29d96dSChad Dupuis 9452b29d96dSChad Dupuis if (flag) 9468dfa4b5aSBart Van Assche WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 9472b29d96dSChad Dupuis data); 9482b29d96dSChad Dupuis else 9498dfa4b5aSBart Van Assche rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M + 9508dfa4b5aSBart Van Assche ha->nx_pcibase); 9512b29d96dSChad Dupuis 9522b29d96dSChad Dupuis return rval; 9532b29d96dSChad Dupuis } 9542b29d96dSChad Dupuis 95577e334d2SGiridhar Malavali static int 956a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 957a9083016SGiridhar Malavali { 9582b29d96dSChad Dupuis /* Dword reads to flash. */ 9592b29d96dSChad Dupuis qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 9602b29d96dSChad Dupuis *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 9612b29d96dSChad Dupuis (addr & 0x0000FFFF), 0, 0); 9627c3df132SSaurav Kashyap 963a9083016SGiridhar Malavali return 0; 964a9083016SGiridhar Malavali } 965a9083016SGiridhar Malavali 96677e334d2SGiridhar Malavali static int 967a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 968a9083016SGiridhar Malavali { 969a9083016SGiridhar Malavali int ret, loops = 0; 9704babb90eSHiral Patel uint32_t lock_owner = 0; 9717c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 972a9083016SGiridhar Malavali 973a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 974a9083016SGiridhar Malavali udelay(100); 975a9083016SGiridhar Malavali schedule(); 976a9083016SGiridhar Malavali loops++; 977a9083016SGiridhar Malavali } 978a9083016SGiridhar Malavali if (loops >= 50000) { 9794babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 9807c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9814babb90eSHiral Patel "Failed to acquire SEM2 lock, Lock Owner %u.\n", 9824babb90eSHiral Patel lock_owner); 983a9083016SGiridhar Malavali return -1; 984a9083016SGiridhar Malavali } 985a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 986d652e093SChad Dupuis qla82xx_rom_unlock(ha); 987a9083016SGiridhar Malavali return ret; 988a9083016SGiridhar Malavali } 989a9083016SGiridhar Malavali 99077e334d2SGiridhar Malavali static int 991a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 992a9083016SGiridhar Malavali { 9937c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 994bd432bb5SBart Van Assche 995a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 996a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 997a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9997c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1000a9083016SGiridhar Malavali return -1; 1001a9083016SGiridhar Malavali } 1002a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 1003a9083016SGiridhar Malavali return 0; 1004a9083016SGiridhar Malavali } 1005a9083016SGiridhar Malavali 100677e334d2SGiridhar Malavali static int 1007a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 1008a9083016SGiridhar Malavali { 1009a9083016SGiridhar Malavali long timeout = 0; 1010a9083016SGiridhar Malavali uint32_t done = 1 ; 1011a9083016SGiridhar Malavali uint32_t val; 1012a9083016SGiridhar Malavali int ret = 0; 10137c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1014a9083016SGiridhar Malavali 1015a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1016a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 1017a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 1018a9083016SGiridhar Malavali done = val & 1; 1019a9083016SGiridhar Malavali timeout++; 1020a9083016SGiridhar Malavali udelay(10); 1021a9083016SGiridhar Malavali cond_resched(); 1022a9083016SGiridhar Malavali if (timeout >= 50000) { 10237c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 10247c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 1025a9083016SGiridhar Malavali return -1; 1026a9083016SGiridhar Malavali } 1027a9083016SGiridhar Malavali } 1028a9083016SGiridhar Malavali return ret; 1029a9083016SGiridhar Malavali } 1030a9083016SGiridhar Malavali 103177e334d2SGiridhar Malavali static int 1032a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1033a9083016SGiridhar Malavali { 1034a9083016SGiridhar Malavali uint32_t val; 1035bd432bb5SBart Van Assche 1036a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1037a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1038a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1039a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1040a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1041a9083016SGiridhar Malavali return -1; 1042a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1043a9083016SGiridhar Malavali return -1; 1044a9083016SGiridhar Malavali if ((val & 2) != 2) 1045a9083016SGiridhar Malavali return -1; 1046a9083016SGiridhar Malavali return 0; 1047a9083016SGiridhar Malavali } 1048a9083016SGiridhar Malavali 104977e334d2SGiridhar Malavali static int 1050a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1051a9083016SGiridhar Malavali { 10527c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1053bd432bb5SBart Van Assche 1054a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1055a9083016SGiridhar Malavali return -1; 1056a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1057a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1058a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10597c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10607c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1061a9083016SGiridhar Malavali return -1; 1062a9083016SGiridhar Malavali } 1063a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1064a9083016SGiridhar Malavali } 1065a9083016SGiridhar Malavali 106677e334d2SGiridhar Malavali static int 1067a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1068a9083016SGiridhar Malavali { 10697c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1070bd432bb5SBart Van Assche 1071a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1072a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10737c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10747c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1075a9083016SGiridhar Malavali return -1; 1076a9083016SGiridhar Malavali } 1077a9083016SGiridhar Malavali return 0; 1078a9083016SGiridhar Malavali } 1079a9083016SGiridhar Malavali 108077e334d2SGiridhar Malavali static int 1081a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1082a9083016SGiridhar Malavali { 1083a9083016SGiridhar Malavali int loops = 0; 10844babb90eSHiral Patel uint32_t lock_owner = 0; 10857c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10867c3df132SSaurav Kashyap 1087a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1088a9083016SGiridhar Malavali udelay(100); 1089a9083016SGiridhar Malavali cond_resched(); 1090a9083016SGiridhar Malavali loops++; 1091a9083016SGiridhar Malavali } 1092a9083016SGiridhar Malavali if (loops >= 50000) { 10934babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 10947c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10954babb90eSHiral Patel "ROM lock failed, Lock Owner %u.\n", lock_owner); 1096a9083016SGiridhar Malavali return -1; 1097a9083016SGiridhar Malavali } 1098cd6dbb03SJesper Juhl return 0; 1099a9083016SGiridhar Malavali } 1100a9083016SGiridhar Malavali 110177e334d2SGiridhar Malavali static int 1102a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1103a9083016SGiridhar Malavali uint32_t data) 1104a9083016SGiridhar Malavali { 1105a9083016SGiridhar Malavali int ret = 0; 11067c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1107a9083016SGiridhar Malavali 1108a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1109a9083016SGiridhar Malavali if (ret < 0) { 11107c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 11117c3df132SSaurav Kashyap "ROM lock failed.\n"); 1112a9083016SGiridhar Malavali return ret; 1113a9083016SGiridhar Malavali } 1114a9083016SGiridhar Malavali 1115a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1116a9083016SGiridhar Malavali goto done_write; 1117a9083016SGiridhar Malavali 1118a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1119a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1120a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1121a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1122a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1123a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 11247c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 11257c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1126a9083016SGiridhar Malavali ret = -1; 1127a9083016SGiridhar Malavali goto done_write; 1128a9083016SGiridhar Malavali } 1129a9083016SGiridhar Malavali 1130a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1131a9083016SGiridhar Malavali 1132a9083016SGiridhar Malavali done_write: 1133d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1134a9083016SGiridhar Malavali return ret; 1135a9083016SGiridhar Malavali } 1136a9083016SGiridhar Malavali 1137a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1138a9083016SGiridhar Malavali * to put the ISP into operational state 1139a9083016SGiridhar Malavali */ 114077e334d2SGiridhar Malavali static int 114177e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1142a9083016SGiridhar Malavali { 1143a9083016SGiridhar Malavali int addr, val; 1144a9083016SGiridhar Malavali int i ; 1145a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1146a9083016SGiridhar Malavali unsigned long off; 1147a9083016SGiridhar Malavali unsigned offset, n; 1148a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1149a9083016SGiridhar Malavali 1150a9083016SGiridhar Malavali struct crb_addr_pair { 1151a9083016SGiridhar Malavali long addr; 1152a9083016SGiridhar Malavali long data; 1153a9083016SGiridhar Malavali }; 1154a9083016SGiridhar Malavali 1155a720101dSMasanari Iida /* Halt all the individual PEGs and other blocks of the ISP */ 1156a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1157c9e8fd5cSMadhuranath Iyengar 115802be2215SGiridhar Malavali /* disable all I2Q */ 115902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 116002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 116102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 116202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 116302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 116402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 116502be2215SGiridhar Malavali 116602be2215SGiridhar Malavali /* disable all niu interrupts */ 1167c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1168c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1169c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1170c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1171c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 117202be2215SGiridhar Malavali /* disable sideband mac */ 117302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 117402be2215SGiridhar Malavali /* disable ap0 mac */ 117502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 117602be2215SGiridhar Malavali /* disable ap1 mac */ 117702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1178c9e8fd5cSMadhuranath Iyengar 1179c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1180c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1181c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1182c9e8fd5cSMadhuranath Iyengar 1183c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1184c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1185c9e8fd5cSMadhuranath Iyengar 1186c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1187c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1188c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1189c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1190c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1191c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 119202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1193c9e8fd5cSMadhuranath Iyengar 1194c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1195c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1196c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1197c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1198c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1199c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 120002be2215SGiridhar Malavali msleep(20); 1201c9e8fd5cSMadhuranath Iyengar 1202c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1203a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1204a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1205a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1206a9083016SGiridhar Malavali else 1207a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1208d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1209a9083016SGiridhar Malavali 1210a9083016SGiridhar Malavali /* Read the signature value from the flash. 1211a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1212a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1213a9083016SGiridhar Malavali * that present in CRB initialize sequence 1214a9083016SGiridhar Malavali */ 1215a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1216a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 12177c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 12187c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1219a9083016SGiridhar Malavali return -1; 1220a9083016SGiridhar Malavali } 1221a9083016SGiridhar Malavali 1222a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 122300adc9a0SSaurav Kashyap * Number of entries = upper 16 bits 1224a9083016SGiridhar Malavali */ 1225a9083016SGiridhar Malavali offset = n & 0xffffU; 1226a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1227a9083016SGiridhar Malavali 122800adc9a0SSaurav Kashyap /* number of addr/value pair should not exceed 1024 entries */ 1229a9083016SGiridhar Malavali if (n >= 1024) { 12307c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 12317c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1232a9083016SGiridhar Malavali return -1; 1233a9083016SGiridhar Malavali } 1234a9083016SGiridhar Malavali 12357c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12367c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1237a9083016SGiridhar Malavali 12386da2ec56SKees Cook buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1239a9083016SGiridhar Malavali if (buf == NULL) { 12407c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12417c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 12425cfe8d5bSBart Van Assche return -ENOMEM; 1243a9083016SGiridhar Malavali } 1244a9083016SGiridhar Malavali 1245a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1246a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1247a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1248a9083016SGiridhar Malavali kfree(buf); 1249a9083016SGiridhar Malavali return -1; 1250a9083016SGiridhar Malavali } 1251a9083016SGiridhar Malavali 1252a9083016SGiridhar Malavali buf[i].addr = addr; 1253a9083016SGiridhar Malavali buf[i].data = val; 1254a9083016SGiridhar Malavali } 1255a9083016SGiridhar Malavali 1256a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1257a9083016SGiridhar Malavali /* Translate internal CRB initialization 1258a9083016SGiridhar Malavali * address to PCI bus address 1259a9083016SGiridhar Malavali */ 1260a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1261a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1262a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1263a9083016SGiridhar Malavali * some of them are skipped 1264a9083016SGiridhar Malavali */ 1265a9083016SGiridhar Malavali 1266a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1267a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1268a9083016SGiridhar Malavali continue; 1269a9083016SGiridhar Malavali 1270a9083016SGiridhar Malavali /* do not reset PCI */ 1271a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1272a9083016SGiridhar Malavali continue; 1273a9083016SGiridhar Malavali 1274a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1275a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1276a9083016SGiridhar Malavali continue; 1277a9083016SGiridhar Malavali 1278a9083016SGiridhar Malavali /* skip the function enable register */ 1279a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1280a9083016SGiridhar Malavali continue; 1281a9083016SGiridhar Malavali 1282a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1283a9083016SGiridhar Malavali continue; 1284a9083016SGiridhar Malavali 1285a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1286a9083016SGiridhar Malavali continue; 1287a9083016SGiridhar Malavali 1288a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1289a9083016SGiridhar Malavali continue; 1290a9083016SGiridhar Malavali 1291a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12927c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 1293d939be3aSMasanari Iida "Unknown addr: 0x%08lx.\n", buf[i].addr); 1294a9083016SGiridhar Malavali continue; 1295a9083016SGiridhar Malavali } 1296a9083016SGiridhar Malavali 1297a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1298a9083016SGiridhar Malavali 1299a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1300a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1301a9083016SGiridhar Malavali */ 1302a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1303a9083016SGiridhar Malavali msleep(1000); 1304a9083016SGiridhar Malavali 1305a9083016SGiridhar Malavali /* ISP requires millisec delay between 1306a9083016SGiridhar Malavali * successive CRB register updation 1307a9083016SGiridhar Malavali */ 1308a9083016SGiridhar Malavali msleep(1); 1309a9083016SGiridhar Malavali } 1310a9083016SGiridhar Malavali 1311a9083016SGiridhar Malavali kfree(buf); 1312a9083016SGiridhar Malavali 1313a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1314a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1315a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1316a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1317a9083016SGiridhar Malavali 1318a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1319a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1320a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1321a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1322a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1323a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1324a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1325a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1326a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1327a9083016SGiridhar Malavali return 0; 1328a9083016SGiridhar Malavali } 1329a9083016SGiridhar Malavali 133077e334d2SGiridhar Malavali static int 133177e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 133277e334d2SGiridhar Malavali u64 off, void *data, int size) 133377e334d2SGiridhar Malavali { 133477e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 133577e334d2SGiridhar Malavali int scale, shift_amount, startword; 133677e334d2SGiridhar Malavali uint32_t temp; 133777e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 133877e334d2SGiridhar Malavali 133977e334d2SGiridhar Malavali /* 134077e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 134177e334d2SGiridhar Malavali */ 134277e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 134377e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 134477e334d2SGiridhar Malavali else { 134577e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 134677e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 134777e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 134877e334d2SGiridhar Malavali off, data, size); 134977e334d2SGiridhar Malavali } 135077e334d2SGiridhar Malavali 135177e334d2SGiridhar Malavali off0 = off & 0x7; 135277e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 135377e334d2SGiridhar Malavali sz[1] = size - sz[0]; 135477e334d2SGiridhar Malavali 135577e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 135677e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 135777e334d2SGiridhar Malavali shift_amount = 4; 135877e334d2SGiridhar Malavali scale = 2; 135977e334d2SGiridhar Malavali startword = (off & 0xf)/8; 136077e334d2SGiridhar Malavali 136177e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 136277e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 136377e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 136477e334d2SGiridhar Malavali return -1; 136577e334d2SGiridhar Malavali } 136677e334d2SGiridhar Malavali 136777e334d2SGiridhar Malavali switch (size) { 136877e334d2SGiridhar Malavali case 1: 136977e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 137077e334d2SGiridhar Malavali break; 137177e334d2SGiridhar Malavali case 2: 137277e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 137377e334d2SGiridhar Malavali break; 137477e334d2SGiridhar Malavali case 4: 137577e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 137677e334d2SGiridhar Malavali break; 137777e334d2SGiridhar Malavali case 8: 137877e334d2SGiridhar Malavali default: 137977e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 138077e334d2SGiridhar Malavali break; 138177e334d2SGiridhar Malavali } 138277e334d2SGiridhar Malavali 138377e334d2SGiridhar Malavali if (sz[0] == 8) { 138477e334d2SGiridhar Malavali word[startword] = tmpw; 138577e334d2SGiridhar Malavali } else { 138677e334d2SGiridhar Malavali word[startword] &= 138777e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 138877e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 138977e334d2SGiridhar Malavali } 139077e334d2SGiridhar Malavali if (sz[1] != 0) { 139177e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 139277e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 139377e334d2SGiridhar Malavali } 139477e334d2SGiridhar Malavali 139577e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 139677e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 139777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 139877e334d2SGiridhar Malavali temp = 0; 139977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 140077e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 140177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 140277e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 140377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 140477e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 140577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 140677e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 140777e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 140877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 140977e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 141077e334d2SGiridhar Malavali 141177e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 141277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 141377e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 141477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 141577e334d2SGiridhar Malavali 141677e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 141777e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 141877e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 141977e334d2SGiridhar Malavali break; 142077e334d2SGiridhar Malavali } 142177e334d2SGiridhar Malavali 142277e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 142377e334d2SGiridhar Malavali if (printk_ratelimit()) 142477e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 14257c3df132SSaurav Kashyap "failed to write through agent.\n"); 142677e334d2SGiridhar Malavali ret = -1; 142777e334d2SGiridhar Malavali break; 142877e334d2SGiridhar Malavali } 142977e334d2SGiridhar Malavali } 143077e334d2SGiridhar Malavali 143177e334d2SGiridhar Malavali return ret; 143277e334d2SGiridhar Malavali } 143377e334d2SGiridhar Malavali 143477e334d2SGiridhar Malavali static int 1435a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1436a9083016SGiridhar Malavali { 1437a9083016SGiridhar Malavali int i; 1438a9083016SGiridhar Malavali long size = 0; 14399c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14409c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1441a9083016SGiridhar Malavali u64 data; 1442a9083016SGiridhar Malavali u32 high, low; 1443bd432bb5SBart Van Assche 1444a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1445a9083016SGiridhar Malavali 1446a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1447a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1448a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1449a9083016SGiridhar Malavali return -1; 1450a9083016SGiridhar Malavali } 1451a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1452a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1453a9083016SGiridhar Malavali flashaddr += 8; 1454a9083016SGiridhar Malavali memaddr += 8; 1455a9083016SGiridhar Malavali 1456a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1457a9083016SGiridhar Malavali msleep(1); 1458a9083016SGiridhar Malavali } 1459a9083016SGiridhar Malavali udelay(100); 1460a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1461a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1462a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1463a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1464a9083016SGiridhar Malavali return 0; 1465a9083016SGiridhar Malavali } 1466a9083016SGiridhar Malavali 1467a9083016SGiridhar Malavali int 1468a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1469a9083016SGiridhar Malavali u64 off, void *data, int size) 1470a9083016SGiridhar Malavali { 1471a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1472a9083016SGiridhar Malavali int shift_amount; 1473a9083016SGiridhar Malavali uint32_t temp; 1474a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1475a9083016SGiridhar Malavali 1476a9083016SGiridhar Malavali /* 1477a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1478a9083016SGiridhar Malavali */ 1479a9083016SGiridhar Malavali 1480a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1481a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1482a9083016SGiridhar Malavali else { 1483a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1484a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1485a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1486a9083016SGiridhar Malavali off, data, size); 1487a9083016SGiridhar Malavali } 1488a9083016SGiridhar Malavali 1489a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1490a9083016SGiridhar Malavali off0[0] = off & 0xf; 1491a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1492a9083016SGiridhar Malavali shift_amount = 4; 1493a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1494a9083016SGiridhar Malavali off0[1] = 0; 1495a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1496a9083016SGiridhar Malavali 1497a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1498a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1499a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1500a9083016SGiridhar Malavali temp = 0; 1501a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1502a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1503a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1504a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1505a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1506a9083016SGiridhar Malavali 1507a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1508a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1509a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1510a9083016SGiridhar Malavali break; 1511a9083016SGiridhar Malavali } 1512a9083016SGiridhar Malavali 1513a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1514a9083016SGiridhar Malavali if (printk_ratelimit()) 1515a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 15167c3df132SSaurav Kashyap "failed to read through agent.\n"); 1517a9083016SGiridhar Malavali break; 1518a9083016SGiridhar Malavali } 1519a9083016SGiridhar Malavali 1520a9083016SGiridhar Malavali start = off0[i] >> 2; 1521a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1522a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1523a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1524a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1525a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1526a9083016SGiridhar Malavali } 1527a9083016SGiridhar Malavali } 1528a9083016SGiridhar Malavali 1529a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1530a9083016SGiridhar Malavali return -1; 1531a9083016SGiridhar Malavali 1532a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1533a9083016SGiridhar Malavali val = word[0]; 1534a9083016SGiridhar Malavali } else { 1535a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1536a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1537a9083016SGiridhar Malavali } 1538a9083016SGiridhar Malavali 1539a9083016SGiridhar Malavali switch (size) { 1540a9083016SGiridhar Malavali case 1: 1541a9083016SGiridhar Malavali *(uint8_t *)data = val; 1542a9083016SGiridhar Malavali break; 1543a9083016SGiridhar Malavali case 2: 1544a9083016SGiridhar Malavali *(uint16_t *)data = val; 1545a9083016SGiridhar Malavali break; 1546a9083016SGiridhar Malavali case 4: 1547a9083016SGiridhar Malavali *(uint32_t *)data = val; 1548a9083016SGiridhar Malavali break; 1549a9083016SGiridhar Malavali case 8: 1550a9083016SGiridhar Malavali *(uint64_t *)data = val; 1551a9083016SGiridhar Malavali break; 1552a9083016SGiridhar Malavali } 1553a9083016SGiridhar Malavali return 0; 1554a9083016SGiridhar Malavali } 1555a9083016SGiridhar Malavali 1556a9083016SGiridhar Malavali 15579c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15589c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15599c2b2975SHarish Zunjarrao { 15609c2b2975SHarish Zunjarrao uint32_t i; 15619c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15629c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15639c2b2975SHarish Zunjarrao __le32 offset; 15649c2b2975SHarish Zunjarrao __le32 tab_type; 15659c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15669c2b2975SHarish Zunjarrao 15679c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15689c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15699c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15709c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15719c2b2975SHarish Zunjarrao 15729c2b2975SHarish Zunjarrao if (tab_type == section) 15739c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15749c2b2975SHarish Zunjarrao } 15759c2b2975SHarish Zunjarrao 15769c2b2975SHarish Zunjarrao return NULL; 15779c2b2975SHarish Zunjarrao } 15789c2b2975SHarish Zunjarrao 15799c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15809c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15819c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15829c2b2975SHarish Zunjarrao { 15839c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15849c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15859c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15869c2b2975SHarish Zunjarrao __le32 offset; 15879c2b2975SHarish Zunjarrao 15889c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15899c2b2975SHarish Zunjarrao if (!tab_desc) 15909c2b2975SHarish Zunjarrao return NULL; 15919c2b2975SHarish Zunjarrao 15929c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15939c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15949c2b2975SHarish Zunjarrao 15959c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15969c2b2975SHarish Zunjarrao } 15979c2b2975SHarish Zunjarrao 15989c2b2975SHarish Zunjarrao static u8 * 15999c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 16009c2b2975SHarish Zunjarrao { 16019c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 16029c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16039c2b2975SHarish Zunjarrao 16049c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16059c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 16069c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 16079c2b2975SHarish Zunjarrao if (uri_desc) 16089c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16099c2b2975SHarish Zunjarrao } 16109c2b2975SHarish Zunjarrao 16119c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16129c2b2975SHarish Zunjarrao } 16139c2b2975SHarish Zunjarrao 16149c2b2975SHarish Zunjarrao static __le32 16159c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 16169c2b2975SHarish Zunjarrao { 16179c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16189c2b2975SHarish Zunjarrao 16199c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16209c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16219c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16229c2b2975SHarish Zunjarrao if (uri_desc) 16239c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 16249c2b2975SHarish Zunjarrao } 16259c2b2975SHarish Zunjarrao 16269c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 16279c2b2975SHarish Zunjarrao } 16289c2b2975SHarish Zunjarrao 16299c2b2975SHarish Zunjarrao static u8 * 16309c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 16319c2b2975SHarish Zunjarrao { 16329c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 16339c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16349c2b2975SHarish Zunjarrao 16359c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16369c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16379c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16389c2b2975SHarish Zunjarrao if (uri_desc) 16399c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16409c2b2975SHarish Zunjarrao } 16419c2b2975SHarish Zunjarrao 16429c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16439c2b2975SHarish Zunjarrao } 16449c2b2975SHarish Zunjarrao 1645a9083016SGiridhar Malavali /* PCI related functions */ 1646a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1647a9083016SGiridhar Malavali { 1648a9083016SGiridhar Malavali unsigned long val = 0; 1649a9083016SGiridhar Malavali u32 control; 1650a9083016SGiridhar Malavali 1651a9083016SGiridhar Malavali switch (region) { 1652a9083016SGiridhar Malavali case 0: 1653a9083016SGiridhar Malavali val = 0; 1654a9083016SGiridhar Malavali break; 1655a9083016SGiridhar Malavali case 1: 1656a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1657a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1658a9083016SGiridhar Malavali break; 1659a9083016SGiridhar Malavali } 1660a9083016SGiridhar Malavali return val; 1661a9083016SGiridhar Malavali } 1662a9083016SGiridhar Malavali 1663a9083016SGiridhar Malavali 1664a9083016SGiridhar Malavali int 1665a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1666a9083016SGiridhar Malavali { 1667a9083016SGiridhar Malavali uint32_t len = 0; 1668a9083016SGiridhar Malavali 1669a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16707c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16717c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1672a9083016SGiridhar Malavali goto iospace_error_exit; 1673a9083016SGiridhar Malavali } 1674a9083016SGiridhar Malavali 1675a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1676a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16777c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16787c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1679a9083016SGiridhar Malavali goto iospace_error_exit; 1680a9083016SGiridhar Malavali } 1681a9083016SGiridhar Malavali 1682a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 16838dfa4b5aSBart Van Assche ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1684a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16857c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16867c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1687a9083016SGiridhar Malavali goto iospace_error_exit; 1688a9083016SGiridhar Malavali } 1689a9083016SGiridhar Malavali 1690a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 16917ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) { 16928dfa4b5aSBart Van Assche ha->iobase = ha->nx_pcibase; 16937ec0effdSAtul Deshmukh } else if (IS_QLA82XX(ha)) { 16948dfa4b5aSBart Van Assche ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 16957ec0effdSAtul Deshmukh } 1696a9083016SGiridhar Malavali 1697a9083016SGiridhar Malavali if (!ql2xdbwr) { 16988dfa4b5aSBart Van Assche ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1699a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1700a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 17017c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 17027c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1703a9083016SGiridhar Malavali goto iospace_error_exit; 1704a9083016SGiridhar Malavali } 1705a9083016SGiridhar Malavali 1706a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1707a9083016SGiridhar Malavali * door bell read and write pointer 1708a9083016SGiridhar Malavali */ 17098dfa4b5aSBart Van Assche ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1710a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1711a9083016SGiridhar Malavali } else { 17128dfa4b5aSBart Van Assche ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1713a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1714a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1715a9083016SGiridhar Malavali } 1716a9083016SGiridhar Malavali 1717a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1718a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 17197c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 17207c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17217c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17228dfa4b5aSBart Van Assche ha->nx_pcibase, ha->iobase, 17237c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17247c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17257c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17267c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17278dfa4b5aSBart Van Assche ha->nx_pcibase, ha->iobase, 17287c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1729a9083016SGiridhar Malavali return 0; 1730a9083016SGiridhar Malavali 1731a9083016SGiridhar Malavali iospace_error_exit: 1732a9083016SGiridhar Malavali return -ENOMEM; 1733a9083016SGiridhar Malavali } 1734a9083016SGiridhar Malavali 1735a9083016SGiridhar Malavali /* GS related functions */ 1736a9083016SGiridhar Malavali 1737a9083016SGiridhar Malavali /* Initialization related functions */ 1738a9083016SGiridhar Malavali 1739a9083016SGiridhar Malavali /** 1740a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 17412db6228dSBart Van Assche * @vha: HA context 1742a9083016SGiridhar Malavali * 1743a9083016SGiridhar Malavali * Returns 0 on success. 1744a9083016SGiridhar Malavali */ 1745a9083016SGiridhar Malavali int 1746a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1747a9083016SGiridhar Malavali { 1748a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1749a9083016SGiridhar Malavali int ret; 1750a9083016SGiridhar Malavali 1751a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1752a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1753a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17547c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 175552c82823SBart Van Assche "Chip revision:%d; pci_set_mwi() returned %d.\n", 175652c82823SBart Van Assche ha->chip_revision, ret); 1757a9083016SGiridhar Malavali return 0; 1758a9083016SGiridhar Malavali } 1759a9083016SGiridhar Malavali 1760a9083016SGiridhar Malavali /** 1761a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 17622db6228dSBart Van Assche * @vha: HA context 1763a9083016SGiridhar Malavali * 1764a9083016SGiridhar Malavali * Returns 0 on success. 1765a9083016SGiridhar Malavali */ 17663f006ac3SMichael Hernandez int 1767a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1768a9083016SGiridhar Malavali { 1769a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1770bd432bb5SBart Van Assche 1771a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 17723f006ac3SMichael Hernandez 17733f006ac3SMichael Hernandez return QLA_SUCCESS; 1774a9083016SGiridhar Malavali } 1775a9083016SGiridhar Malavali 1776a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1777a9083016SGiridhar Malavali { 1778a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1779a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1780a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1781a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1782a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1783a9083016SGiridhar Malavali 1784a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1785a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1786ad950360SBart Van Assche icb->request_q_outpointer = cpu_to_le16(0); 1787ad950360SBart Van Assche icb->response_q_inpointer = cpu_to_le16(0); 1788a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1789a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1790a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1791a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1792a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1793a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1794a9083016SGiridhar Malavali 17958dfa4b5aSBart Van Assche WRT_REG_DWORD(®->req_q_out[0], 0); 17968dfa4b5aSBart Van Assche WRT_REG_DWORD(®->rsp_q_in[0], 0); 17978dfa4b5aSBart Van Assche WRT_REG_DWORD(®->rsp_q_out[0], 0); 1798a9083016SGiridhar Malavali } 1799a9083016SGiridhar Malavali 180077e334d2SGiridhar Malavali static int 180177e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1802a9083016SGiridhar Malavali { 1803a9083016SGiridhar Malavali u64 *ptr64; 1804a9083016SGiridhar Malavali u32 i, flashaddr, size; 1805a9083016SGiridhar Malavali __le64 data; 1806a9083016SGiridhar Malavali 1807a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1808a9083016SGiridhar Malavali 18099c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1810a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1811a9083016SGiridhar Malavali 1812a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1813a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 18149c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 18159c2b2975SHarish Zunjarrao return -EIO; 1816a9083016SGiridhar Malavali flashaddr += 8; 1817a9083016SGiridhar Malavali } 1818a9083016SGiridhar Malavali 1819a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18209c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18219c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1822a9083016SGiridhar Malavali 1823a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1824a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1825a9083016SGiridhar Malavali 1826a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1827a9083016SGiridhar Malavali return -EIO; 1828a9083016SGiridhar Malavali flashaddr += 8; 1829a9083016SGiridhar Malavali } 18309c2b2975SHarish Zunjarrao udelay(100); 1831a9083016SGiridhar Malavali 1832a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1833a9083016SGiridhar Malavali * at a specified offset to indicate 1834a9083016SGiridhar Malavali * that all data is written and 1835a9083016SGiridhar Malavali * ready for firmware to initialize. 1836a9083016SGiridhar Malavali */ 18379c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1838a9083016SGiridhar Malavali 18399c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1840a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1841a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18429c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18439c2b2975SHarish Zunjarrao return 0; 18449c2b2975SHarish Zunjarrao } 18459c2b2975SHarish Zunjarrao 18469c2b2975SHarish Zunjarrao static int 18479c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18489c2b2975SHarish Zunjarrao { 18499c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18509c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18519c2b2975SHarish Zunjarrao uint32_t i; 18529c2b2975SHarish Zunjarrao __le32 entries; 18539c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18549c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18559c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18569c2b2975SHarish Zunjarrao int mn_present = 0; 18579c2b2975SHarish Zunjarrao uint32_t flagbit; 18589c2b2975SHarish Zunjarrao 18599c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18609c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18619c2b2975SHarish Zunjarrao if (!ptab_desc) 18629c2b2975SHarish Zunjarrao return -1; 18639c2b2975SHarish Zunjarrao 18649c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18659c2b2975SHarish Zunjarrao 18669c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18679c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18689c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18699c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18709c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18719c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18729c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18739c2b2975SHarish Zunjarrao 18749c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18759c2b2975SHarish Zunjarrao 18769c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18779c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18789c2b2975SHarish Zunjarrao return 0; 18799c2b2975SHarish Zunjarrao } 18809c2b2975SHarish Zunjarrao } 18819c2b2975SHarish Zunjarrao return -1; 18829c2b2975SHarish Zunjarrao } 18839c2b2975SHarish Zunjarrao 1884fa492630SSaurav Kashyap static int 18859c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18869c2b2975SHarish Zunjarrao { 18879c2b2975SHarish Zunjarrao __le32 val; 18889c2b2975SHarish Zunjarrao uint32_t min_size; 18899c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18909c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18919c2b2975SHarish Zunjarrao 18929c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18939c2b2975SHarish Zunjarrao 18949c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18959c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18969c2b2975SHarish Zunjarrao return -EINVAL; 18979c2b2975SHarish Zunjarrao 18989c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18999c2b2975SHarish Zunjarrao } else { 19009c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 19019c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 19029c2b2975SHarish Zunjarrao return -EINVAL; 19039c2b2975SHarish Zunjarrao 19049c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 19059c2b2975SHarish Zunjarrao } 19069c2b2975SHarish Zunjarrao 19079c2b2975SHarish Zunjarrao if (fw->size < min_size) 19089c2b2975SHarish Zunjarrao return -EINVAL; 1909a9083016SGiridhar Malavali return 0; 1910a9083016SGiridhar Malavali } 1911a9083016SGiridhar Malavali 191277e334d2SGiridhar Malavali static int 191377e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1914a9083016SGiridhar Malavali { 1915a9083016SGiridhar Malavali u32 val = 0; 1916a9083016SGiridhar Malavali int retries = 60; 19177c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1918a9083016SGiridhar Malavali 1919a9083016SGiridhar Malavali do { 1920a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1921a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1922a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1923a9083016SGiridhar Malavali 1924a9083016SGiridhar Malavali switch (val) { 1925a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1926a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1927a9083016SGiridhar Malavali return QLA_SUCCESS; 1928a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1929a9083016SGiridhar Malavali break; 1930a9083016SGiridhar Malavali default: 1931a9083016SGiridhar Malavali break; 1932a9083016SGiridhar Malavali } 19337c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19347c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1935a9083016SGiridhar Malavali val, retries); 1936a9083016SGiridhar Malavali 1937a9083016SGiridhar Malavali msleep(500); 1938a9083016SGiridhar Malavali 1939a9083016SGiridhar Malavali } while (--retries); 1940a9083016SGiridhar Malavali 19417c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1942a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1943a9083016SGiridhar Malavali 1944a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1945a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1946a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1947a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1948a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1949a9083016SGiridhar Malavali } 1950a9083016SGiridhar Malavali 195177e334d2SGiridhar Malavali static int 195277e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1953a9083016SGiridhar Malavali { 1954a9083016SGiridhar Malavali u32 val = 0; 1955a9083016SGiridhar Malavali int retries = 60; 19567c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1957a9083016SGiridhar Malavali 1958a9083016SGiridhar Malavali do { 1959a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1960a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1961a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1962a9083016SGiridhar Malavali 1963a9083016SGiridhar Malavali switch (val) { 1964a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1965a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1966a9083016SGiridhar Malavali return QLA_SUCCESS; 1967a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1968a9083016SGiridhar Malavali break; 1969a9083016SGiridhar Malavali default: 1970a9083016SGiridhar Malavali break; 1971a9083016SGiridhar Malavali } 19727c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19737c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1974a9083016SGiridhar Malavali val, retries); 1975a9083016SGiridhar Malavali 1976a9083016SGiridhar Malavali msleep(500); 1977a9083016SGiridhar Malavali 1978a9083016SGiridhar Malavali } while (--retries); 1979a9083016SGiridhar Malavali 19807c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19817c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1982a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1983a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1984a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1985a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1986a9083016SGiridhar Malavali } 1987a9083016SGiridhar Malavali 1988a9083016SGiridhar Malavali /* ISR related functions */ 1989a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1990a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1991a9083016SGiridhar Malavali 1992a9083016SGiridhar Malavali /* 1993a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1994a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1995a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1996a9083016SGiridhar Malavali */ 19977ec0effdSAtul Deshmukh void 1998a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1999a9083016SGiridhar Malavali { 2000a9083016SGiridhar Malavali uint16_t cnt; 2001a9083016SGiridhar Malavali uint16_t __iomem *wptr; 2002a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2003a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2004bd432bb5SBart Van Assche 2005a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2006a9083016SGiridhar Malavali 2007a9083016SGiridhar Malavali /* Load return mailbox registers. */ 2008a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 2009a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 2010a9083016SGiridhar Malavali 2011a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2012a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2013a9083016SGiridhar Malavali wptr++; 2014a9083016SGiridhar Malavali } 2015a9083016SGiridhar Malavali 2016cfb0919cSChad Dupuis if (!ha->mcp) 20177c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 20187c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 2019a9083016SGiridhar Malavali } 2020a9083016SGiridhar Malavali 20212db6228dSBart Van Assche /** 2022a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2023807eb907SBart Van Assche * @irq: interrupt number 2024a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2025a9083016SGiridhar Malavali * 2026a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2027a9083016SGiridhar Malavali * 2028a9083016SGiridhar Malavali * Returns handled flag. 2029a9083016SGiridhar Malavali */ 2030a9083016SGiridhar Malavali irqreturn_t 2031a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2032a9083016SGiridhar Malavali { 2033a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2034a9083016SGiridhar Malavali struct qla_hw_data *ha; 2035a9083016SGiridhar Malavali struct rsp_que *rsp; 2036a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2037a9083016SGiridhar Malavali int status = 0, status1 = 0; 2038a9083016SGiridhar Malavali unsigned long flags; 2039a9083016SGiridhar Malavali unsigned long iter; 20407c3df132SSaurav Kashyap uint32_t stat = 0; 2041a9083016SGiridhar Malavali uint16_t mb[4]; 2042a9083016SGiridhar Malavali 2043a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2044a9083016SGiridhar Malavali if (!rsp) { 2045b6d0d9d5SGiridhar Malavali ql_log(ql_log_info, NULL, 0xb053, 20463256b435SChad Dupuis "%s: NULL response queue pointer.\n", __func__); 2047a9083016SGiridhar Malavali return IRQ_NONE; 2048a9083016SGiridhar Malavali } 2049a9083016SGiridhar Malavali ha = rsp->hw; 2050a9083016SGiridhar Malavali 2051a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2052a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2053a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2054a9083016SGiridhar Malavali return IRQ_NONE; 2055a9083016SGiridhar Malavali 2056a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2057a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2058a9083016SGiridhar Malavali return IRQ_NONE; 2059a9083016SGiridhar Malavali } 2060a9083016SGiridhar Malavali 2061a9083016SGiridhar Malavali /* clear the interrupt */ 2062a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2063a9083016SGiridhar Malavali 2064a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2065a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2066a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2067a9083016SGiridhar Malavali 2068a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2069a9083016SGiridhar Malavali 2070a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2071a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2072a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2073a9083016SGiridhar Malavali 2074a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2075a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2076a9083016SGiridhar Malavali 2077a9083016SGiridhar Malavali switch (stat & 0xff) { 2078a9083016SGiridhar Malavali case 0x1: 2079a9083016SGiridhar Malavali case 0x2: 2080a9083016SGiridhar Malavali case 0x10: 2081a9083016SGiridhar Malavali case 0x11: 2082a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2083a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2084a9083016SGiridhar Malavali break; 2085a9083016SGiridhar Malavali case 0x12: 2086a9083016SGiridhar Malavali mb[0] = MSW(stat); 2087a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2088a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2089a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2090a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2091a9083016SGiridhar Malavali break; 2092a9083016SGiridhar Malavali case 0x13: 2093a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2094a9083016SGiridhar Malavali break; 2095a9083016SGiridhar Malavali default: 20967c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2097a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20987c3df132SSaurav Kashyap stat & 0xff); 2099a9083016SGiridhar Malavali break; 2100a9083016SGiridhar Malavali } 2101a9083016SGiridhar Malavali } 2102a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2103a9083016SGiridhar Malavali } 2104a9083016SGiridhar Malavali 210536439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 210636439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 210736439832Sgurinder.shergill@hp.com 210836439832Sgurinder.shergill@hp.com if (!ha->flags.msi_enabled) 210936439832Sgurinder.shergill@hp.com qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 211036439832Sgurinder.shergill@hp.com 2111a9083016SGiridhar Malavali return IRQ_HANDLED; 2112a9083016SGiridhar Malavali } 2113a9083016SGiridhar Malavali 2114a9083016SGiridhar Malavali irqreturn_t 2115a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2116a9083016SGiridhar Malavali { 2117a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2118a9083016SGiridhar Malavali struct qla_hw_data *ha; 2119a9083016SGiridhar Malavali struct rsp_que *rsp; 2120a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2121a9083016SGiridhar Malavali int status = 0; 2122a9083016SGiridhar Malavali unsigned long flags; 21237c3df132SSaurav Kashyap uint32_t stat = 0; 2124f3ddac19SChad Dupuis uint32_t host_int = 0; 2125a9083016SGiridhar Malavali uint16_t mb[4]; 2126a9083016SGiridhar Malavali 2127a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2128a9083016SGiridhar Malavali if (!rsp) { 2129a9083016SGiridhar Malavali printk(KERN_INFO 21307c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2131a9083016SGiridhar Malavali return IRQ_NONE; 2132a9083016SGiridhar Malavali } 2133a9083016SGiridhar Malavali ha = rsp->hw; 2134a9083016SGiridhar Malavali 2135a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2136a9083016SGiridhar Malavali 2137a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2138a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2139a9083016SGiridhar Malavali do { 2140f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2141c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2142f3ddac19SChad Dupuis break; 2143f3ddac19SChad Dupuis if (host_int) { 2144a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2145a9083016SGiridhar Malavali 2146a9083016SGiridhar Malavali switch (stat & 0xff) { 2147a9083016SGiridhar Malavali case 0x1: 2148a9083016SGiridhar Malavali case 0x2: 2149a9083016SGiridhar Malavali case 0x10: 2150a9083016SGiridhar Malavali case 0x11: 2151a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2152a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2153a9083016SGiridhar Malavali break; 2154a9083016SGiridhar Malavali case 0x12: 2155a9083016SGiridhar Malavali mb[0] = MSW(stat); 2156a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2157a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2158a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2159a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2160a9083016SGiridhar Malavali break; 2161a9083016SGiridhar Malavali case 0x13: 2162a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2163a9083016SGiridhar Malavali break; 2164a9083016SGiridhar Malavali default: 21657c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2166a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21677c3df132SSaurav Kashyap stat & 0xff); 2168a9083016SGiridhar Malavali break; 2169a9083016SGiridhar Malavali } 2170a9083016SGiridhar Malavali } 2171a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2172a9083016SGiridhar Malavali } while (0); 2173a9083016SGiridhar Malavali 217436439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 217536439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 217636439832Sgurinder.shergill@hp.com 2177a9083016SGiridhar Malavali return IRQ_HANDLED; 2178a9083016SGiridhar Malavali } 2179a9083016SGiridhar Malavali 2180a9083016SGiridhar Malavali irqreturn_t 2181a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2182a9083016SGiridhar Malavali { 2183a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2184a9083016SGiridhar Malavali struct qla_hw_data *ha; 2185a9083016SGiridhar Malavali struct rsp_que *rsp; 2186a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 21873553d343SSaurav Kashyap unsigned long flags; 2188f3ddac19SChad Dupuis uint32_t host_int = 0; 2189a9083016SGiridhar Malavali 2190a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2191a9083016SGiridhar Malavali if (!rsp) { 2192a9083016SGiridhar Malavali printk(KERN_INFO 21937c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2194a9083016SGiridhar Malavali return IRQ_NONE; 2195a9083016SGiridhar Malavali } 2196a9083016SGiridhar Malavali 2197a9083016SGiridhar Malavali ha = rsp->hw; 2198a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 21993553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2200a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2201f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2202c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2203f3ddac19SChad Dupuis goto out; 2204a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2205a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2206f3ddac19SChad Dupuis out: 22073553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2208a9083016SGiridhar Malavali return IRQ_HANDLED; 2209a9083016SGiridhar Malavali } 2210a9083016SGiridhar Malavali 2211a9083016SGiridhar Malavali void 2212a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2213a9083016SGiridhar Malavali { 2214a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2215a9083016SGiridhar Malavali struct qla_hw_data *ha; 2216a9083016SGiridhar Malavali struct rsp_que *rsp; 2217a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2218a9083016SGiridhar Malavali int status = 0; 2219a9083016SGiridhar Malavali uint32_t stat; 2220f3ddac19SChad Dupuis uint32_t host_int = 0; 2221a9083016SGiridhar Malavali uint16_t mb[4]; 2222a9083016SGiridhar Malavali unsigned long flags; 2223a9083016SGiridhar Malavali 2224a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2225a9083016SGiridhar Malavali if (!rsp) { 2226a9083016SGiridhar Malavali printk(KERN_INFO 22277c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2228a9083016SGiridhar Malavali return; 2229a9083016SGiridhar Malavali } 2230a9083016SGiridhar Malavali ha = rsp->hw; 2231a9083016SGiridhar Malavali 2232a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2233a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2234a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2235a9083016SGiridhar Malavali 2236f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2237c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2238f3ddac19SChad Dupuis goto out; 2239f3ddac19SChad Dupuis if (host_int) { 2240a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2241a9083016SGiridhar Malavali switch (stat & 0xff) { 2242a9083016SGiridhar Malavali case 0x1: 2243a9083016SGiridhar Malavali case 0x2: 2244a9083016SGiridhar Malavali case 0x10: 2245a9083016SGiridhar Malavali case 0x11: 2246a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2247a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2248a9083016SGiridhar Malavali break; 2249a9083016SGiridhar Malavali case 0x12: 2250a9083016SGiridhar Malavali mb[0] = MSW(stat); 2251a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2252a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2253a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2254a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2255a9083016SGiridhar Malavali break; 2256a9083016SGiridhar Malavali case 0x13: 2257a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2258a9083016SGiridhar Malavali break; 2259a9083016SGiridhar Malavali default: 22607c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22617c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22627c3df132SSaurav Kashyap stat * 0xff); 2263a9083016SGiridhar Malavali break; 2264a9083016SGiridhar Malavali } 2265a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 226602a9ae6eSAtul Deshmukh } 2267f3ddac19SChad Dupuis out: 2268a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2269a9083016SGiridhar Malavali } 2270a9083016SGiridhar Malavali 2271a9083016SGiridhar Malavali void 2272a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2273a9083016SGiridhar Malavali { 2274a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2275bd432bb5SBart Van Assche 2276a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2277a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22787ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22797ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 22807ec0effdSAtul Deshmukh else 2281a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2282a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2283a9083016SGiridhar Malavali ha->interrupts_on = 1; 2284a9083016SGiridhar Malavali } 2285a9083016SGiridhar Malavali 2286a9083016SGiridhar Malavali void 2287a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2288a9083016SGiridhar Malavali { 2289a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2290bd432bb5SBart Van Assche 2291a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2292a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22937ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22947ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 22957ec0effdSAtul Deshmukh else 2296a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2297a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2298a9083016SGiridhar Malavali ha->interrupts_on = 0; 2299a9083016SGiridhar Malavali } 2300a9083016SGiridhar Malavali 2301a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2302a9083016SGiridhar Malavali { 2303a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2304a9083016SGiridhar Malavali 2305a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2306a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2307a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2308a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2309a9083016SGiridhar Malavali ha->curr_window = 255; 2310a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2311a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2312a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2313a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2314a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2315a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2316a9083016SGiridhar Malavali } 2317a9083016SGiridhar Malavali 23182374dd23SBart Van Assche static inline void 23190251ce8cSSaurav Kashyap qla82xx_set_idc_version(scsi_qla_host_t *vha) 23200251ce8cSSaurav Kashyap { 23210251ce8cSSaurav Kashyap int idc_ver; 23220251ce8cSSaurav Kashyap uint32_t drv_active; 23230251ce8cSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 23240251ce8cSSaurav Kashyap 23250251ce8cSSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 23260251ce8cSSaurav Kashyap if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 23270251ce8cSSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 23280251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION); 23290251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb082, 23300251ce8cSSaurav Kashyap "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 23310251ce8cSSaurav Kashyap } else { 23320251ce8cSSaurav Kashyap idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 23330251ce8cSSaurav Kashyap if (idc_ver != QLA82XX_IDC_VERSION) 23340251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb083, 23350251ce8cSSaurav Kashyap "qla2xxx driver IDC version %d is not compatible " 23360251ce8cSSaurav Kashyap "with IDC version %d of the other drivers\n", 23370251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION, idc_ver); 23380251ce8cSSaurav Kashyap } 23390251ce8cSSaurav Kashyap } 23400251ce8cSSaurav Kashyap 23410251ce8cSSaurav Kashyap inline void 2342a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2343a9083016SGiridhar Malavali { 2344a9083016SGiridhar Malavali uint32_t drv_active; 2345a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2346a9083016SGiridhar Malavali 2347a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2348a9083016SGiridhar Malavali 2349a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2350a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 235177e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 235277e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2353a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2354a9083016SGiridhar Malavali } 235577e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2356a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2357a9083016SGiridhar Malavali } 2358a9083016SGiridhar Malavali 2359a9083016SGiridhar Malavali inline void 2360a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2361a9083016SGiridhar Malavali { 2362a9083016SGiridhar Malavali uint32_t drv_active; 2363a9083016SGiridhar Malavali 2364a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 236577e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2366a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2367a9083016SGiridhar Malavali } 2368a9083016SGiridhar Malavali 2369a9083016SGiridhar Malavali static inline int 2370a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2371a9083016SGiridhar Malavali { 2372a9083016SGiridhar Malavali uint32_t drv_state; 2373a9083016SGiridhar Malavali int rval; 2374a9083016SGiridhar Malavali 23757d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 237608de2844SGiridhar Malavali return 1; 237708de2844SGiridhar Malavali else { 2378a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 237977e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2380a9083016SGiridhar Malavali return rval; 2381a9083016SGiridhar Malavali } 238208de2844SGiridhar Malavali } 2383a9083016SGiridhar Malavali 2384a9083016SGiridhar Malavali static inline void 2385a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2386a9083016SGiridhar Malavali { 2387a9083016SGiridhar Malavali uint32_t drv_state; 2388a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2389a9083016SGiridhar Malavali 2390a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2391a9083016SGiridhar Malavali 2392a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2393a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 239477e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2395a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2396a9083016SGiridhar Malavali } 2397a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 239808de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 239908de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2400a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2401a9083016SGiridhar Malavali } 2402a9083016SGiridhar Malavali 2403a9083016SGiridhar Malavali static inline void 2404a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2405a9083016SGiridhar Malavali { 2406a9083016SGiridhar Malavali uint32_t drv_state; 2407a9083016SGiridhar Malavali 2408a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2409a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2410a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2411a9083016SGiridhar Malavali } 2412a9083016SGiridhar Malavali 2413a9083016SGiridhar Malavali static inline void 2414a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2415a9083016SGiridhar Malavali { 2416a9083016SGiridhar Malavali uint32_t qsnt_state; 2417a9083016SGiridhar Malavali 2418a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2419a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2420a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2421a9083016SGiridhar Malavali } 2422a9083016SGiridhar Malavali 2423579d12b5SSaurav Kashyap void 2424579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2425579d12b5SSaurav Kashyap { 2426579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2427579d12b5SSaurav Kashyap uint32_t qsnt_state; 2428579d12b5SSaurav Kashyap 2429579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2430579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2431579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2432579d12b5SSaurav Kashyap } 2433579d12b5SSaurav Kashyap 243477e334d2SGiridhar Malavali static int 243577e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2436a9083016SGiridhar Malavali { 2437a9083016SGiridhar Malavali int rst; 2438a9083016SGiridhar Malavali struct fw_blob *blob; 2439a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2440a9083016SGiridhar Malavali 2441a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24427c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24437c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2444a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2445a9083016SGiridhar Malavali } 2446a9083016SGiridhar Malavali udelay(500); 2447a9083016SGiridhar Malavali 2448a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2449a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2450a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2451a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2452a9083016SGiridhar Malavali 2453a9083016SGiridhar Malavali /* 2454a9083016SGiridhar Malavali * FW Load priority: 2455a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2456a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2457a9083016SGiridhar Malavali */ 2458a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2459a9083016SGiridhar Malavali goto try_blob_fw; 2460a9083016SGiridhar Malavali 24617c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24627c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2463a9083016SGiridhar Malavali 2464a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24657c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 246600adc9a0SSaurav Kashyap "Firmware loaded successfully from flash.\n"); 2467a9083016SGiridhar Malavali return QLA_SUCCESS; 2468875efad7SChad Dupuis } else { 24697c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24707c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2471a9083016SGiridhar Malavali } 2472875efad7SChad Dupuis 2473a9083016SGiridhar Malavali try_blob_fw: 24747c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24757c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2476a9083016SGiridhar Malavali 2477a9083016SGiridhar Malavali /* Load firmware blob. */ 2478a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2479a9083016SGiridhar Malavali if (!blob) { 24807c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 248100adc9a0SSaurav Kashyap "Firmware image not present.\n"); 2482a9083016SGiridhar Malavali goto fw_load_failed; 2483a9083016SGiridhar Malavali } 2484a9083016SGiridhar Malavali 24859c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24869c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24879c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24889c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24899c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24909c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24917c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24927c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24939c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24949c2b2975SHarish Zunjarrao } 24959c2b2975SHarish Zunjarrao } 24969c2b2975SHarish Zunjarrao 2497a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24987c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24997c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2500a9083016SGiridhar Malavali return QLA_SUCCESS; 25018a318fe1SBart Van Assche } 25028a318fe1SBart Van Assche 25037c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 25047c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2505a9083016SGiridhar Malavali blob->fw = NULL; 2506a9083016SGiridhar Malavali blob = NULL; 2507a9083016SGiridhar Malavali 2508a9083016SGiridhar Malavali fw_load_failed: 2509a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2510a9083016SGiridhar Malavali } 2511a9083016SGiridhar Malavali 2512a5b36321SLalit Chandivade int 2513a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2514a9083016SGiridhar Malavali { 2515a9083016SGiridhar Malavali uint16_t lnk; 2516a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2517a9083016SGiridhar Malavali 2518a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 251977e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2520a9083016SGiridhar Malavali 25213711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 25223711333dSGiridhar Malavali * of 0 before resetting the hardware 25233711333dSGiridhar Malavali */ 25243711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25253711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25263711333dSGiridhar Malavali 2527a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2528a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2529a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2530a9083016SGiridhar Malavali 2531a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25327c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25337c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2534a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2535a9083016SGiridhar Malavali } 2536a9083016SGiridhar Malavali 2537a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2538a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25397c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25407c3df132SSaurav Kashyap "Error during card handshake.\n"); 2541a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2542a9083016SGiridhar Malavali } 2543a9083016SGiridhar Malavali 2544a9083016SGiridhar Malavali /* Negotiated Link width */ 254510092438SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2546a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2547a9083016SGiridhar Malavali 2548a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2549a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2550a9083016SGiridhar Malavali } 2551a9083016SGiridhar Malavali 255277e334d2SGiridhar Malavali static uint32_t * 2553a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2554a9083016SGiridhar Malavali uint32_t length) 2555a9083016SGiridhar Malavali { 2556a9083016SGiridhar Malavali uint32_t i; 2557a9083016SGiridhar Malavali uint32_t val; 2558a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2559a9083016SGiridhar Malavali 2560a9083016SGiridhar Malavali /* Dword reads to flash. */ 2561a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2562a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25647c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2565a9083016SGiridhar Malavali goto done_read; 2566a9083016SGiridhar Malavali } 2567ad950360SBart Van Assche dwptr[i] = cpu_to_le32(val); 2568a9083016SGiridhar Malavali } 2569a9083016SGiridhar Malavali done_read: 2570a9083016SGiridhar Malavali return dwptr; 2571a9083016SGiridhar Malavali } 2572a9083016SGiridhar Malavali 257377e334d2SGiridhar Malavali static int 2574a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2575a9083016SGiridhar Malavali { 2576a9083016SGiridhar Malavali int ret; 2577a9083016SGiridhar Malavali uint32_t val; 25787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2579a9083016SGiridhar Malavali 2580a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2581a9083016SGiridhar Malavali if (ret < 0) { 25827c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25837c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2584a9083016SGiridhar Malavali return ret; 2585a9083016SGiridhar Malavali } 2586a9083016SGiridhar Malavali 2587a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2588a9083016SGiridhar Malavali if (ret < 0) 2589a9083016SGiridhar Malavali goto done_unprotect; 2590a9083016SGiridhar Malavali 25910547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2592a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2593a9083016SGiridhar Malavali if (ret < 0) { 25940547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2595a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2596a9083016SGiridhar Malavali } 2597a9083016SGiridhar Malavali 2598a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25997c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 26007c3df132SSaurav Kashyap "Write disable failed.\n"); 2601a9083016SGiridhar Malavali 2602a9083016SGiridhar Malavali done_unprotect: 2603d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2604a9083016SGiridhar Malavali return ret; 2605a9083016SGiridhar Malavali } 2606a9083016SGiridhar Malavali 260777e334d2SGiridhar Malavali static int 2608a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2609a9083016SGiridhar Malavali { 2610a9083016SGiridhar Malavali int ret; 2611a9083016SGiridhar Malavali uint32_t val; 26127c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2613a9083016SGiridhar Malavali 2614a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2615a9083016SGiridhar Malavali if (ret < 0) { 26167c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 26177c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2618a9083016SGiridhar Malavali return ret; 2619a9083016SGiridhar Malavali } 2620a9083016SGiridhar Malavali 2621a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2622a9083016SGiridhar Malavali if (ret < 0) 2623a9083016SGiridhar Malavali goto done_protect; 2624a9083016SGiridhar Malavali 26250547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2626a9083016SGiridhar Malavali /* LOCK all sectors */ 2627a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2628a9083016SGiridhar Malavali if (ret < 0) 26297c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 26307c3df132SSaurav Kashyap "Write status register failed.\n"); 2631a9083016SGiridhar Malavali 2632a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 26337c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 26347c3df132SSaurav Kashyap "Write disable failed.\n"); 2635a9083016SGiridhar Malavali done_protect: 2636d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2637a9083016SGiridhar Malavali return ret; 2638a9083016SGiridhar Malavali } 2639a9083016SGiridhar Malavali 264077e334d2SGiridhar Malavali static int 2641a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2642a9083016SGiridhar Malavali { 2643a9083016SGiridhar Malavali int ret = 0; 26447c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2645a9083016SGiridhar Malavali 2646a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2647a9083016SGiridhar Malavali if (ret < 0) { 26487c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26497c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2650a9083016SGiridhar Malavali return ret; 2651a9083016SGiridhar Malavali } 2652a9083016SGiridhar Malavali 2653a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2654a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2655a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2656a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2657a9083016SGiridhar Malavali 2658a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26597c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26607c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2661a9083016SGiridhar Malavali ret = -1; 2662a9083016SGiridhar Malavali goto done; 2663a9083016SGiridhar Malavali } 2664a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2665a9083016SGiridhar Malavali done: 2666d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2667a9083016SGiridhar Malavali return ret; 2668a9083016SGiridhar Malavali } 2669a9083016SGiridhar Malavali 2670a9083016SGiridhar Malavali /* 2671a9083016SGiridhar Malavali * Address and length are byte address 2672a9083016SGiridhar Malavali */ 26733695310eSJoe Carnuccio void * 26743695310eSJoe Carnuccio qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2675a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2676a9083016SGiridhar Malavali { 2677a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2678a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2679a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2680a9083016SGiridhar Malavali return buf; 2681a9083016SGiridhar Malavali } 2682a9083016SGiridhar Malavali 2683a9083016SGiridhar Malavali static int 2684a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2685a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2686a9083016SGiridhar Malavali { 2687a9083016SGiridhar Malavali int ret; 2688a9083016SGiridhar Malavali uint32_t liter; 268952c82823SBart Van Assche uint32_t rest_addr; 2690a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2691a9083016SGiridhar Malavali void *optrom = NULL; 2692a9083016SGiridhar Malavali int page_mode = 0; 2693a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2694a9083016SGiridhar Malavali 2695a9083016SGiridhar Malavali ret = -1; 2696a9083016SGiridhar Malavali 2697a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2698a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2699a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2700a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2701a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2702a9083016SGiridhar Malavali if (!optrom) { 27037c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 27047c3df132SSaurav Kashyap "Unable to allocate memory " 270500adc9a0SSaurav Kashyap "for optrom burst write (%x KB).\n", 2706a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2707a9083016SGiridhar Malavali } 2708a9083016SGiridhar Malavali } 2709a9083016SGiridhar Malavali 2710a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2711a9083016SGiridhar Malavali 2712a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2713a9083016SGiridhar Malavali if (ret) { 27147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2715a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2716a9083016SGiridhar Malavali goto write_done; 2717a9083016SGiridhar Malavali } 2718a9083016SGiridhar Malavali 2719a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2720a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2721a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2722a9083016SGiridhar Malavali 2723a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2724a9083016SGiridhar Malavali if (ret) { 27257c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 27267c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 27277c3df132SSaurav Kashyap faddr); 2728a9083016SGiridhar Malavali break; 2729a9083016SGiridhar Malavali } 2730a9083016SGiridhar Malavali } 2731a9083016SGiridhar Malavali 2732a9083016SGiridhar Malavali /* Go with burst-write. */ 2733a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2734a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2735a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2736a9083016SGiridhar Malavali 2737a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2738a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2739a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2740a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 27417c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2742a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2743a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2744a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2745a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27467c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2747a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2748a9083016SGiridhar Malavali 2749a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2750a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2751a9083016SGiridhar Malavali optrom = NULL; 2752a9083016SGiridhar Malavali } else { 2753a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2754a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2755a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2756a9083016SGiridhar Malavali continue; 2757a9083016SGiridhar Malavali } 2758a9083016SGiridhar Malavali } 2759a9083016SGiridhar Malavali 2760a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 2761a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 2762a9083016SGiridhar Malavali if (ret) { 27637c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27647c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27657c3df132SSaurav Kashyap faddr, *dwptr); 2766a9083016SGiridhar Malavali break; 2767a9083016SGiridhar Malavali } 2768a9083016SGiridhar Malavali } 2769a9083016SGiridhar Malavali 2770a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2771a9083016SGiridhar Malavali if (ret) 27727c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2773a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2774a9083016SGiridhar Malavali write_done: 2775a9083016SGiridhar Malavali if (optrom) 2776a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2777a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2778a9083016SGiridhar Malavali return ret; 2779a9083016SGiridhar Malavali } 2780a9083016SGiridhar Malavali 2781a9083016SGiridhar Malavali int 27823695310eSJoe Carnuccio qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2783a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2784a9083016SGiridhar Malavali { 2785a9083016SGiridhar Malavali int rval; 2786a9083016SGiridhar Malavali 2787a9083016SGiridhar Malavali /* Suspend HBA. */ 2788a9083016SGiridhar Malavali scsi_block_requests(vha->host); 27893695310eSJoe Carnuccio rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2790a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2791a9083016SGiridhar Malavali 2792a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2793a9083016SGiridhar Malavali if (rval) 2794a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2795a9083016SGiridhar Malavali else 2796a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2797a9083016SGiridhar Malavali return rval; 2798a9083016SGiridhar Malavali } 2799a9083016SGiridhar Malavali 2800a9083016SGiridhar Malavali void 28015162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2802a9083016SGiridhar Malavali { 28035162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2804a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2805a9083016SGiridhar Malavali uint32_t dbval; 2806a9083016SGiridhar Malavali 2807a9083016SGiridhar Malavali /* Adjust ring index. */ 2808a9083016SGiridhar Malavali req->ring_index++; 2809a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2810a9083016SGiridhar Malavali req->ring_index = 0; 2811a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2812a9083016SGiridhar Malavali } else 2813a9083016SGiridhar Malavali req->ring_ptr++; 2814a9083016SGiridhar Malavali 2815a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2816a9083016SGiridhar Malavali 2817a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 28186907869dSGiridhar Malavali if (ql2xdbwr) 28198dfa4b5aSBart Van Assche qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 28206907869dSGiridhar Malavali else { 28218dfa4b5aSBart Van Assche WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2822a9083016SGiridhar Malavali wmb(); 28238dfa4b5aSBart Van Assche while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 28248dfa4b5aSBart Van Assche WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval); 2825a9083016SGiridhar Malavali wmb(); 2826a9083016SGiridhar Malavali } 2827a9083016SGiridhar Malavali } 28286907869dSGiridhar Malavali } 2829a9083016SGiridhar Malavali 2830fa492630SSaurav Kashyap static void 2831fa492630SSaurav Kashyap qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2832e6a4202aSShyam Sundar { 28337c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 28344babb90eSHiral Patel uint32_t lock_owner = 0; 28357c3df132SSaurav Kashyap 28364babb90eSHiral Patel if (qla82xx_rom_lock(ha)) { 28374babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2838e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 28397c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 28404babb90eSHiral Patel "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 28414babb90eSHiral Patel } 2842e6a4202aSShyam Sundar /* 2843e6a4202aSShyam Sundar * Either we got the lock, or someone 2844e6a4202aSShyam Sundar * else died while holding it. 2845e6a4202aSShyam Sundar * In either case, unlock. 2846e6a4202aSShyam Sundar */ 2847d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2848e6a4202aSShyam Sundar } 2849e6a4202aSShyam Sundar 2850a9083016SGiridhar Malavali /* 2851a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2852a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2853a9083016SGiridhar Malavali * 2854a9083016SGiridhar Malavali * Note: 2855a9083016SGiridhar Malavali * IDC lock must be held upon entry 2856a9083016SGiridhar Malavali * 2857a9083016SGiridhar Malavali * Return: 2858a9083016SGiridhar Malavali * Success : 0 2859a9083016SGiridhar Malavali * Failed : 1 2860a9083016SGiridhar Malavali */ 2861a9083016SGiridhar Malavali static int 2862a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2863a9083016SGiridhar Malavali { 2864e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 286503d32f97STej Prakash int i; 2866a9083016SGiridhar Malavali uint32_t old_count, count; 2867a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 286803d32f97STej Prakash int need_reset = 0; 2869a9083016SGiridhar Malavali 2870e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2871a9083016SGiridhar Malavali 2872e6a4202aSShyam Sundar if (need_reset) { 2873e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 287403d32f97STej Prakash if (ha->flags.isp82xx_fw_hung) 2875e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2876e6a4202aSShyam Sundar } else { 287703d32f97STej Prakash old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 287803d32f97STej Prakash for (i = 0; i < 10; i++) { 287903d32f97STej Prakash msleep(200); 288003d32f97STej Prakash count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 288103d32f97STej Prakash if (count != old_count) { 288203d32f97STej Prakash rval = QLA_SUCCESS; 2883a9083016SGiridhar Malavali goto dev_ready; 2884a9083016SGiridhar Malavali } 288503d32f97STej Prakash } 288603d32f97STej Prakash qla82xx_rom_lock_recovery(ha); 288703d32f97STej Prakash } 2888a9083016SGiridhar Malavali 2889a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28907c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28917c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 28927d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2893a9083016SGiridhar Malavali 2894a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2895a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2896a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2897a9083016SGiridhar Malavali 2898a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 28997c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 29007c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2901a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 29027d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2903a9083016SGiridhar Malavali return rval; 2904a9083016SGiridhar Malavali } 2905a9083016SGiridhar Malavali 2906a9083016SGiridhar Malavali dev_ready: 29077c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 29087c3df132SSaurav Kashyap "HW State: READY.\n"); 29097d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2910a9083016SGiridhar Malavali 2911a9083016SGiridhar Malavali return QLA_SUCCESS; 2912a9083016SGiridhar Malavali } 2913a9083016SGiridhar Malavali 2914579d12b5SSaurav Kashyap /* 2915579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2916579d12b5SSaurav Kashyap * Code to start quiescence sequence 2917579d12b5SSaurav Kashyap * 2918579d12b5SSaurav Kashyap * Note: 2919579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2920579d12b5SSaurav Kashyap * 2921579d12b5SSaurav Kashyap * Return: void 2922579d12b5SSaurav Kashyap */ 2923579d12b5SSaurav Kashyap 2924579d12b5SSaurav Kashyap static void 2925579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2926579d12b5SSaurav Kashyap { 2927579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2928579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2929579d12b5SSaurav Kashyap unsigned long reset_timeout; 2930579d12b5SSaurav Kashyap 2931579d12b5SSaurav Kashyap if (vha->flags.online) { 2932579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 29338fcd6b8bSChad Dupuis qla2x00_quiesce_io(vha); 2934579d12b5SSaurav Kashyap } 2935579d12b5SSaurav Kashyap 2936579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2937579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2938579d12b5SSaurav Kashyap 2939579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2940579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2941579d12b5SSaurav Kashyap 2942579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2943579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2944579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2945579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2946579d12b5SSaurav Kashyap 2947579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2948579d12b5SSaurav Kashyap 2949579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2950579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2951579d12b5SSaurav Kashyap * changing the state to DEV_READY 2952579d12b5SSaurav Kashyap */ 29537c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29545f28d2d7SSaurav Kashyap "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 29555f28d2d7SSaurav Kashyap "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 29567c3df132SSaurav Kashyap drv_active, drv_state); 2957579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 29587d613ac6SSantosh Vernekar QLA8XXX_DEV_READY); 29597c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29607c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2961579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2962579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2963579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2964579d12b5SSaurav Kashyap 2965579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2966579d12b5SSaurav Kashyap return; 2967579d12b5SSaurav Kashyap } 2968579d12b5SSaurav Kashyap 2969579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2970579d12b5SSaurav Kashyap msleep(1000); 2971579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2972579d12b5SSaurav Kashyap 2973579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2974579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2975579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2976579d12b5SSaurav Kashyap } 2977579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2978579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 29797d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 29807c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29817c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 29827d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2983579d12b5SSaurav Kashyap } 2984579d12b5SSaurav Kashyap } 2985579d12b5SSaurav Kashyap 2986579d12b5SSaurav Kashyap /* 2987579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2988579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2989579d12b5SSaurav Kashyap * 2990579d12b5SSaurav Kashyap * Note: 2991579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2992579d12b5SSaurav Kashyap * 2993579d12b5SSaurav Kashyap * Return: 2994579d12b5SSaurav Kashyap * Changed device state. 2995579d12b5SSaurav Kashyap */ 2996579d12b5SSaurav Kashyap uint32_t 2997579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2998579d12b5SSaurav Kashyap { 2999579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3000579d12b5SSaurav Kashyap uint32_t dev_state; 3001579d12b5SSaurav Kashyap 3002579d12b5SSaurav Kashyap do { 3003579d12b5SSaurav Kashyap msleep(1000); 3004579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3005579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3006579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3007579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3008579d12b5SSaurav Kashyap 3009579d12b5SSaurav Kashyap return dev_state; 3010579d12b5SSaurav Kashyap } 3011579d12b5SSaurav Kashyap 30127d613ac6SSantosh Vernekar void 30137d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3014a9083016SGiridhar Malavali { 3015a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3016a9083016SGiridhar Malavali 3017a9083016SGiridhar Malavali /* Disable the board */ 30187c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 30197c3df132SSaurav Kashyap "Disabling the board.\n"); 3020a9083016SGiridhar Malavali 30211459c0e1SSaurav Kashyap if (IS_QLA82XX(ha)) { 3022b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3023b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 30247ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) { 3025c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha); 30267ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 30271459c0e1SSaurav Kashyap } 3028b963752fSGiridhar Malavali 3029a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3030a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3031a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3032a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3033a9083016SGiridhar Malavali vha->flags.online = 0; 3034a9083016SGiridhar Malavali vha->flags.init_done = 0; 3035a9083016SGiridhar Malavali } 3036a9083016SGiridhar Malavali 3037a9083016SGiridhar Malavali /* 3038a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3039a9083016SGiridhar Malavali * Code to start reset sequence 3040a9083016SGiridhar Malavali * 3041a9083016SGiridhar Malavali * Note: 3042a9083016SGiridhar Malavali * IDC lock must be held upon entry 3043a9083016SGiridhar Malavali * 3044a9083016SGiridhar Malavali * Return: 3045a9083016SGiridhar Malavali * Success : 0 3046a9083016SGiridhar Malavali * Failed : 1 3047a9083016SGiridhar Malavali */ 3048a9083016SGiridhar Malavali static void 3049a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3050a9083016SGiridhar Malavali { 3051e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3052e5fdae55SChad Dupuis uint32_t active_mask = 0; 3053a9083016SGiridhar Malavali unsigned long reset_timeout; 3054a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3055a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3056a9083016SGiridhar Malavali 3057a9083016SGiridhar Malavali if (vha->flags.online) { 3058a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3059a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3060a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3061a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3062a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3063a9083016SGiridhar Malavali } 3064a9083016SGiridhar Malavali 306508de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30667d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_owner) { 306708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 306808de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3069a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 307008de2844SGiridhar Malavali } else { 307108de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 307208de2844SGiridhar Malavali drv_active &= active_mask; 307308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 307408de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 307508de2844SGiridhar Malavali } 3076a9083016SGiridhar Malavali 3077a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 30787d613ac6SSantosh Vernekar reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3079a9083016SGiridhar Malavali 3080a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3081a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 308208de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3083a9083016SGiridhar Malavali 308408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 308508de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 308608de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 308708de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 308808de2844SGiridhar Malavali 308908de2844SGiridhar Malavali while (drv_state != drv_active && 30907d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_INITIALIZING) { 3091a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30927c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30937c3df132SSaurav Kashyap "Reset timeout.\n"); 3094a9083016SGiridhar Malavali break; 3095a9083016SGiridhar Malavali } 3096a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3097a9083016SGiridhar Malavali msleep(1000); 3098a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3099a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3100a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 31017d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 310208de2844SGiridhar Malavali drv_active &= active_mask; 310308de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3104a9083016SGiridhar Malavali } 3105a9083016SGiridhar Malavali 310608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 310708de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 310808de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 310908de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 311008de2844SGiridhar Malavali 31117c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 31127c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 31137c3df132SSaurav Kashyap dev_state, 311408de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3115f1af6208SGiridhar Malavali 3116a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 31177d613ac6SSantosh Vernekar if (dev_state != QLA8XXX_DEV_INITIALIZING && 31187d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_COLD) { 31197c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 31207c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 31217d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3122f4e1648aSVikas Chaudhary qla82xx_set_rst_ready(ha); 312308de2844SGiridhar Malavali if (ql2xmdenable) { 312408de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 312508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 3126b6d0d9d5SGiridhar Malavali "Minidump not collected.\n"); 312708de2844SGiridhar Malavali } else 312808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 312908de2844SGiridhar Malavali "Minidump disabled.\n"); 3130a9083016SGiridhar Malavali } 3131a9083016SGiridhar Malavali } 3132a9083016SGiridhar Malavali 31333173167fSGiridhar Malavali int 313408de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 313508de2844SGiridhar Malavali { 313608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 313708de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 31383173167fSGiridhar Malavali int rval = QLA_SUCCESS; 313908de2844SGiridhar Malavali 31403173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 31413173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 31423173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 31433173167fSGiridhar Malavali 31446246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31453173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31463173167fSGiridhar Malavali return rval; 31473173167fSGiridhar Malavali 31483173167fSGiridhar Malavali if (ql2xmdenable) { 314908de2844SGiridhar Malavali if (!ha->fw_dumped) { 3150edaa5c74SSaurav Kashyap if ((fw_major_version != ha->fw_major_version || 315108de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 3152edaa5c74SSaurav Kashyap fw_subminor_version != ha->fw_subminor_version) || 3153edaa5c74SSaurav Kashyap (ha->prev_minidump_failed)) { 31547ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3155edaa5c74SSaurav Kashyap "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 31569bc3bf27SGiridhar Malavali fw_major_version, fw_minor_version, 31579bc3bf27SGiridhar Malavali fw_subminor_version, 315808de2844SGiridhar Malavali ha->fw_major_version, 31593173167fSGiridhar Malavali ha->fw_minor_version, 3160edaa5c74SSaurav Kashyap ha->fw_subminor_version, 3161edaa5c74SSaurav Kashyap ha->prev_minidump_failed); 316208de2844SGiridhar Malavali /* Release MiniDump resources */ 316308de2844SGiridhar Malavali qla82xx_md_free(vha); 316408de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 316508de2844SGiridhar Malavali qla82xx_md_prep(vha); 31662e264269SGiridhar Malavali } 316708de2844SGiridhar Malavali } else 316808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3169d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 317008de2844SGiridhar Malavali } 31713173167fSGiridhar Malavali return rval; 31723173167fSGiridhar Malavali } 317308de2844SGiridhar Malavali 317408de2844SGiridhar Malavali 3175fa492630SSaurav Kashyap static int 3176a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3177a9083016SGiridhar Malavali { 31787190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31797190575fSGiridhar Malavali int status = 0; 3180a9083016SGiridhar Malavali 31817190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31827190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3183a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31847c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31857c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31867c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31877c3df132SSaurav Kashyap "returning status=%d.\n", status); 31887190575fSGiridhar Malavali return status; 31897c3df132SSaurav Kashyap } 3190a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3191a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3192a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3193a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3194a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31957190575fSGiridhar Malavali status = 1; 3196a9083016SGiridhar Malavali } 3197efa786ccSLalit Chandivade } else 3198efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3199a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 32007c3df132SSaurav Kashyap if (status) 32017c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 32027c3df132SSaurav Kashyap "Returning status=%d.\n", status); 32037190575fSGiridhar Malavali return status; 3204a9083016SGiridhar Malavali } 3205a9083016SGiridhar Malavali 3206a9083016SGiridhar Malavali /* 3207a9083016SGiridhar Malavali * qla82xx_device_state_handler 3208a9083016SGiridhar Malavali * Main state handler 3209a9083016SGiridhar Malavali * 3210a9083016SGiridhar Malavali * Note: 3211a9083016SGiridhar Malavali * IDC lock must be held upon entry 3212a9083016SGiridhar Malavali * 3213a9083016SGiridhar Malavali * Return: 3214a9083016SGiridhar Malavali * Success : 0 3215a9083016SGiridhar Malavali * Failed : 1 3216a9083016SGiridhar Malavali */ 3217a9083016SGiridhar Malavali int 3218a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3219a9083016SGiridhar Malavali { 3220a9083016SGiridhar Malavali uint32_t dev_state; 322192dbf273SGiridhar Malavali uint32_t old_dev_state; 3222a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3223a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3224a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 322592dbf273SGiridhar Malavali int loopcount = 0; 3226a9083016SGiridhar Malavali 3227a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 32280251ce8cSSaurav Kashyap if (!vha->flags.init_done) { 3229a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 32300251ce8cSSaurav Kashyap qla82xx_set_idc_version(vha); 32310251ce8cSSaurav Kashyap } 3232a9083016SGiridhar Malavali 3233a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 323492dbf273SGiridhar Malavali old_dev_state = dev_state; 32357c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 32367c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32377c3df132SSaurav Kashyap dev_state, 323808de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3239a9083016SGiridhar Malavali 3240a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 32417d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3242a9083016SGiridhar Malavali 3243a9083016SGiridhar Malavali while (1) { 3244a9083016SGiridhar Malavali 3245a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32467c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32477c3df132SSaurav Kashyap "Device init failed.\n"); 3248a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3249a9083016SGiridhar Malavali break; 3250a9083016SGiridhar Malavali } 3251a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 325292dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 325392dbf273SGiridhar Malavali loopcount = 0; 325492dbf273SGiridhar Malavali old_dev_state = dev_state; 325592dbf273SGiridhar Malavali } 325692dbf273SGiridhar Malavali if (loopcount < 5) { 32577c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32587c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32597c3df132SSaurav Kashyap dev_state, 326008de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32617c3df132SSaurav Kashyap "Unknown"); 326292dbf273SGiridhar Malavali } 3263f1af6208SGiridhar Malavali 3264a9083016SGiridhar Malavali switch (dev_state) { 32657d613ac6SSantosh Vernekar case QLA8XXX_DEV_READY: 32667d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 0; 32677916bb90SChad Dupuis goto rel_lock; 32687d613ac6SSantosh Vernekar case QLA8XXX_DEV_COLD: 3269a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 327008de2844SGiridhar Malavali break; 32717d613ac6SSantosh Vernekar case QLA8XXX_DEV_INITIALIZING: 3272a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3273a9083016SGiridhar Malavali msleep(1000); 3274a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3275a9083016SGiridhar Malavali break; 32767d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_RESET: 3277ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3278a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3279c8582ad9SSaurav Kashyap else { 3280c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3281c8582ad9SSaurav Kashyap msleep(1000); 3282c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3283c8582ad9SSaurav Kashyap } 32840060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32857d613ac6SSantosh Vernekar (ha->fcoe_dev_init_timeout * HZ); 3286a9083016SGiridhar Malavali break; 32877d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_QUIESCENT: 3288579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3289579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32907d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3291579d12b5SSaurav Kashyap * HZ); 3292579d12b5SSaurav Kashyap break; 32937d613ac6SSantosh Vernekar case QLA8XXX_DEV_QUIESCENT: 3294579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3295579d12b5SSaurav Kashyap * to get changed 3296579d12b5SSaurav Kashyap */ 3297579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 32987916bb90SChad Dupuis goto rel_lock; 3299579d12b5SSaurav Kashyap 3300a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3301a9083016SGiridhar Malavali msleep(1000); 3302a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3303579d12b5SSaurav Kashyap 3304579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 33057d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3306579d12b5SSaurav Kashyap * HZ); 3307a9083016SGiridhar Malavali break; 33087d613ac6SSantosh Vernekar case QLA8XXX_DEV_FAILED: 33097d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(vha); 3310a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3311a9083016SGiridhar Malavali goto exit; 3312a9083016SGiridhar Malavali default: 3313a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3314a9083016SGiridhar Malavali msleep(1000); 3315a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3316a9083016SGiridhar Malavali } 331792dbf273SGiridhar Malavali loopcount++; 3318a9083016SGiridhar Malavali } 33197916bb90SChad Dupuis rel_lock: 3320a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 33217916bb90SChad Dupuis exit: 3322a9083016SGiridhar Malavali return rval; 3323a9083016SGiridhar Malavali } 3324a9083016SGiridhar Malavali 33255988aeb2SGiridhar Malavali static int qla82xx_check_temp(scsi_qla_host_t *vha) 33265988aeb2SGiridhar Malavali { 33275988aeb2SGiridhar Malavali uint32_t temp, temp_state, temp_val; 33285988aeb2SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 33295988aeb2SGiridhar Malavali 33305988aeb2SGiridhar Malavali temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 33315988aeb2SGiridhar Malavali temp_state = qla82xx_get_temp_state(temp); 33325988aeb2SGiridhar Malavali temp_val = qla82xx_get_temp_val(temp); 33335988aeb2SGiridhar Malavali 33345988aeb2SGiridhar Malavali if (temp_state == QLA82XX_TEMP_PANIC) { 33355988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600e, 33365988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33375988aeb2SGiridhar Malavali " maximum allowed. Hardware has been shut down.\n", 33385988aeb2SGiridhar Malavali temp_val); 33395988aeb2SGiridhar Malavali return 1; 33405988aeb2SGiridhar Malavali } else if (temp_state == QLA82XX_TEMP_WARN) { 33415988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600f, 33425988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33435988aeb2SGiridhar Malavali "operating range. Immediate action needed.\n", 33445988aeb2SGiridhar Malavali temp_val); 33455988aeb2SGiridhar Malavali } 33465988aeb2SGiridhar Malavali return 0; 33475988aeb2SGiridhar Malavali } 33485988aeb2SGiridhar Malavali 33491ae47cf3SJoe Carnuccio int qla82xx_read_temperature(scsi_qla_host_t *vha) 33501ae47cf3SJoe Carnuccio { 33511ae47cf3SJoe Carnuccio uint32_t temp; 33521ae47cf3SJoe Carnuccio 33531ae47cf3SJoe Carnuccio temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 33541ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp); 33551ae47cf3SJoe Carnuccio } 33561ae47cf3SJoe Carnuccio 3357c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3358c8f6544eSChad Dupuis { 3359c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3360c8f6544eSChad Dupuis 3361c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3362c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33638937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3364c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3365c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 336636439832Sgurinder.shergill@hp.com if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3367c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3368c8f6544eSChad Dupuis } 3369c8f6544eSChad Dupuis } 3370c8f6544eSChad Dupuis 3371a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3372a9083016SGiridhar Malavali { 33737190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3374a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3375a9083016SGiridhar Malavali 3376a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33777d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_hdlr_active) { 33787190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33795988aeb2SGiridhar Malavali if (qla82xx_check_temp(vha)) { 33805988aeb2SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33815988aeb2SGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 33825988aeb2SGiridhar Malavali qla82xx_clear_pending_mbx(vha); 33837d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 33847190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33857c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33867c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3387a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 33887d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3389579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33907c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33917c3df132SSaurav Kashyap "Quiescent needed.\n"); 3392579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 33937d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_FAILED && 33947916bb90SChad Dupuis !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 33957916bb90SChad Dupuis vha->flags.online == 1) { 33967916bb90SChad Dupuis ql_log(ql_log_warn, vha, 0xb055, 33977916bb90SChad Dupuis "Adapter state is failed. Offlining.\n"); 33987916bb90SChad Dupuis set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33997916bb90SChad Dupuis ha->flags.isp82xx_fw_hung = 1; 34007916bb90SChad Dupuis qla82xx_clear_pending_mbx(vha); 3401a9083016SGiridhar Malavali } else { 34027190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 340363154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 340463154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 340563154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 340663154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 34077190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 34087190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 340963154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 34107c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 34117c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 34127c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 34137c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 34147c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 34150e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 34160e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34170e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 34180e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34190e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 34200e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34210e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 34220e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34230e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 34240e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34250e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 34262cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 342710a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 342810a340e6SChad Dupuis "Firmware aborted with " 342910a340e6SChad Dupuis "error code 0x00006700. Device is " 343010a340e6SChad Dupuis "being reset.\n"); 34317190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 34327190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 34337190575fSGiridhar Malavali &vha->dpc_flags); 34347190575fSGiridhar Malavali } else { 34357c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 34367c3df132SSaurav Kashyap "Detect abort needed.\n"); 34377190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 34387190575fSGiridhar Malavali &vha->dpc_flags); 34397190575fSGiridhar Malavali } 34407190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3441c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3442c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 34437190575fSGiridhar Malavali } 3444a9083016SGiridhar Malavali } 3445a9083016SGiridhar Malavali } 3446a9083016SGiridhar Malavali } 3447a9083016SGiridhar Malavali 3448a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3449a9083016SGiridhar Malavali { 34507ec0effdSAtul Deshmukh int rval = -1; 34517ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 34527ec0effdSAtul Deshmukh 34537ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3454a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 34557ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 34567ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 34577ec0effdSAtul Deshmukh /* Decide the reset ownership */ 34587ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 34597ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 34607ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 34617ec0effdSAtul Deshmukh } 3462a9083016SGiridhar Malavali return rval; 3463a9083016SGiridhar Malavali } 3464a9083016SGiridhar Malavali 346508de2844SGiridhar Malavali void 346608de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 346708de2844SGiridhar Malavali { 346808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 34697ec0effdSAtul Deshmukh uint32_t dev_state = 0; 347008de2844SGiridhar Malavali 34717ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 347208de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 34737ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 34747ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 34757ec0effdSAtul Deshmukh 34767d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_READY) { 347708de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 347808de2844SGiridhar Malavali "HW State: NEED RESET\n"); 34797ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) { 348008de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 34817d613ac6SSantosh Vernekar QLA8XXX_DEV_NEED_RESET); 34827d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 1; 348308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 348408de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 34857ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) 34867ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 34877ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET); 348808de2844SGiridhar Malavali } else 348908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 349008de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 349108de2844SGiridhar Malavali dev_state, 349208de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 349308de2844SGiridhar Malavali } 349408de2844SGiridhar Malavali 3495a9083016SGiridhar Malavali /* 3496a9083016SGiridhar Malavali * qla82xx_abort_isp 3497a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3498a9083016SGiridhar Malavali * 3499a9083016SGiridhar Malavali * Input: 3500a9083016SGiridhar Malavali * ha = adapter block pointer. 3501a9083016SGiridhar Malavali * 3502a9083016SGiridhar Malavali * Returns: 3503a9083016SGiridhar Malavali * 0 = success 3504a9083016SGiridhar Malavali */ 3505a9083016SGiridhar Malavali int 3506a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3507a9083016SGiridhar Malavali { 35087ec0effdSAtul Deshmukh int rval = -1; 3509a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3510a9083016SGiridhar Malavali 3511a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 35127c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 35137c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3514a9083016SGiridhar Malavali return QLA_SUCCESS; 3515a9083016SGiridhar Malavali } 35167d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 1; 3517a9083016SGiridhar Malavali 3518a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 351908de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3520a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3521a9083016SGiridhar Malavali 35227ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3523a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 35247ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 35257ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 35267ec0effdSAtul Deshmukh /* Decide the reset ownership */ 35277ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 35287ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 35297ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 35307ec0effdSAtul Deshmukh } 3531a9083016SGiridhar Malavali 3532a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3533a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3534a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3535a9083016SGiridhar Malavali 3536cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 35377190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 35387d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 0; 3539a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3540cdbb0a4fSSantosh Vernekar } 3541f1af6208SGiridhar Malavali 3542f1af6208SGiridhar Malavali if (rval) { 3543f1af6208SGiridhar Malavali vha->flags.online = 1; 3544f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3545f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 35467c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 35477c3df132SSaurav Kashyap "ISP error recover failed - board " 35487c3df132SSaurav Kashyap "disabled.\n"); 3549f1af6208SGiridhar Malavali /* 3550f1af6208SGiridhar Malavali * The next call disables the board 3551f1af6208SGiridhar Malavali * completely. 3552f1af6208SGiridhar Malavali */ 3553f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3554f1af6208SGiridhar Malavali vha->flags.online = 0; 3555f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3556f1af6208SGiridhar Malavali &vha->dpc_flags); 3557f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3558f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3559f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 35607c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 35617c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 35627c3df132SSaurav Kashyap ha->isp_abort_cnt); 3563f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3564f1af6208SGiridhar Malavali } 3565f1af6208SGiridhar Malavali } else { 3566f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 35677c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 35687c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 35697c3df132SSaurav Kashyap ha->isp_abort_cnt); 3570f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3571f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3572f1af6208SGiridhar Malavali } 3573f1af6208SGiridhar Malavali } 3574a9083016SGiridhar Malavali return rval; 3575a9083016SGiridhar Malavali } 3576a9083016SGiridhar Malavali 3577a9083016SGiridhar Malavali /* 3578a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3579a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3580a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3581a9083016SGiridhar Malavali * chip reset. 3582a9083016SGiridhar Malavali * 3583a9083016SGiridhar Malavali * Input: 3584a9083016SGiridhar Malavali * ha = adapter block pointer. 3585a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3586a9083016SGiridhar Malavali * 3587a9083016SGiridhar Malavali * Returns: 3588a9083016SGiridhar Malavali * 0 = success 3589a9083016SGiridhar Malavali */ 3590a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3591a9083016SGiridhar Malavali { 3592a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3593a9083016SGiridhar Malavali 3594a9083016SGiridhar Malavali if (vha->flags.online) { 3595a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3596a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3597a9083016SGiridhar Malavali } 3598a9083016SGiridhar Malavali 3599a9083016SGiridhar Malavali /* Stop currently executing firmware. 3600a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3601a9083016SGiridhar Malavali */ 3602a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3603a9083016SGiridhar Malavali 3604a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3605a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3606a9083016SGiridhar Malavali 3607a9083016SGiridhar Malavali return rval; 3608a9083016SGiridhar Malavali } 3609a9083016SGiridhar Malavali 3610a9083016SGiridhar Malavali /* 3611a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3612a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3613a9083016SGiridhar Malavali * 3614a9083016SGiridhar Malavali * Note: 3615a9083016SGiridhar Malavali * Does context switching here. 3616a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3617a9083016SGiridhar Malavali * 3618a9083016SGiridhar Malavali * Return: 3619a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3620a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3621a9083016SGiridhar Malavali */ 3622a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3623a9083016SGiridhar Malavali { 3624a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3625a9083016SGiridhar Malavali unsigned long wait_reset; 3626a9083016SGiridhar Malavali 3627a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3628a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3629a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3630a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3631a9083016SGiridhar Malavali 3632a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3633a9083016SGiridhar Malavali schedule_timeout(HZ); 3634a9083016SGiridhar Malavali 3635a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3636a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3637a9083016SGiridhar Malavali status = QLA_SUCCESS; 3638a9083016SGiridhar Malavali break; 3639a9083016SGiridhar Malavali } 3640a9083016SGiridhar Malavali } 36417c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3642d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3643a9083016SGiridhar Malavali 3644a9083016SGiridhar Malavali return status; 3645a9083016SGiridhar Malavali } 36467190575fSGiridhar Malavali 36477190575fSGiridhar Malavali void 36487190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 36497190575fSGiridhar Malavali { 36507ec0effdSAtul Deshmukh int i, fw_state = 0; 36517190575fSGiridhar Malavali unsigned long flags; 36527190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 36537190575fSGiridhar Malavali 36547190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 36557190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 36567190575fSGiridhar Malavali * detection only 36577190575fSGiridhar Malavali */ 36587190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36597190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 36607190575fSGiridhar Malavali msleep(1000); 36617ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 36627ec0effdSAtul Deshmukh fw_state = qla82xx_check_fw_alive(vha); 36637ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 36647ec0effdSAtul Deshmukh fw_state = qla8044_check_fw_alive(vha); 36657ec0effdSAtul Deshmukh if (fw_state) { 36667190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3667c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 36687190575fSGiridhar Malavali break; 36697190575fSGiridhar Malavali } 36707190575fSGiridhar Malavali } 36717190575fSGiridhar Malavali } 36727c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 36737c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 36747c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 36757190575fSGiridhar Malavali 36767190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 36777190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36787190575fSGiridhar Malavali int cnt, que; 36797190575fSGiridhar Malavali srb_t *sp; 36807190575fSGiridhar Malavali struct req_que *req; 36817190575fSGiridhar Malavali 36827190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36837190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36847190575fSGiridhar Malavali req = ha->req_q_map[que]; 36857190575fSGiridhar Malavali if (!req) 36867190575fSGiridhar Malavali continue; 36878d93f550SChad Dupuis for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 36887190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36897190575fSGiridhar Malavali if (sp) { 3690af13b700SGiridhar Malavali if ((!sp->u.scmd.ctx || 3691af13b700SGiridhar Malavali (sp->flags & 3692af13b700SGiridhar Malavali SRB_FCP_CMND_DMA_VALID)) && 3693af13b700SGiridhar Malavali !ha->flags.isp82xx_fw_hung) { 36947190575fSGiridhar Malavali spin_unlock_irqrestore( 36957190575fSGiridhar Malavali &ha->hardware_lock, flags); 36967190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 36977c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36987c3df132SSaurav Kashyap 0x00b1, 36997c3df132SSaurav Kashyap "mbx abort failed.\n"); 37007190575fSGiridhar Malavali } else { 37017c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 37027c3df132SSaurav Kashyap 0x00b2, 37037c3df132SSaurav Kashyap "mbx abort success.\n"); 37047190575fSGiridhar Malavali } 37057190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 37067190575fSGiridhar Malavali } 37077190575fSGiridhar Malavali } 37087190575fSGiridhar Malavali } 37097190575fSGiridhar Malavali } 37107190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 37117190575fSGiridhar Malavali 37127190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 371346333cebSNathan Chancellor if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 371446333cebSNathan Chancellor WAIT_HOST)) { 37157c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 37167c3df132SSaurav Kashyap "Done wait for " 37177c3df132SSaurav Kashyap "pending commands.\n"); 37187190575fSGiridhar Malavali } 37197190575fSGiridhar Malavali } 37207190575fSGiridhar Malavali } 372108de2844SGiridhar Malavali 372208de2844SGiridhar Malavali /* Minidump related functions */ 372308de2844SGiridhar Malavali static int 372408de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 372508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 372608de2844SGiridhar Malavali { 372708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 372808de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 372908de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 373008de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 373108de2844SGiridhar Malavali unsigned long wtime; 373208de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 373308de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 373408de2844SGiridhar Malavali int i; 373508de2844SGiridhar Malavali 373608de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 373708de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 373808de2844SGiridhar Malavali crb_addr = crb_entry->addr; 373908de2844SGiridhar Malavali 374008de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 374108de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 374208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 374308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 374408de2844SGiridhar Malavali crb_entry->value_1, 1); 374508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 374608de2844SGiridhar Malavali } 374708de2844SGiridhar Malavali 374808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 374908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 375008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 375108de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 375208de2844SGiridhar Malavali } 375308de2844SGiridhar Malavali 375408de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 375508de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 375608de2844SGiridhar Malavali read_value &= crb_entry->value_2; 375708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 375808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 375908de2844SGiridhar Malavali read_value |= crb_entry->value_3; 376008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 376108de2844SGiridhar Malavali } 376208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 376308de2844SGiridhar Malavali } 376408de2844SGiridhar Malavali 376508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 376608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 376708de2844SGiridhar Malavali read_value |= crb_entry->value_3; 376808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 376908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 377008de2844SGiridhar Malavali } 377108de2844SGiridhar Malavali 377208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 377308de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 377408de2844SGiridhar Malavali wtime = jiffies + poll_time; 377508de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 377608de2844SGiridhar Malavali 377708de2844SGiridhar Malavali do { 377808de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 377908de2844SGiridhar Malavali == crb_entry->value_1) 378008de2844SGiridhar Malavali break; 378108de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 378208de2844SGiridhar Malavali /* capturing dump failed */ 378308de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 378408de2844SGiridhar Malavali break; 378508de2844SGiridhar Malavali } else 378608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 378708de2844SGiridhar Malavali crb_addr, 0, 0); 378808de2844SGiridhar Malavali } while (1); 378908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 379008de2844SGiridhar Malavali } 379108de2844SGiridhar Malavali 379208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 379308de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 379408de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 379508de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 379608de2844SGiridhar Malavali } else 379708de2844SGiridhar Malavali addr = crb_addr; 379808de2844SGiridhar Malavali 379908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 380008de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 380108de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 380208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 380308de2844SGiridhar Malavali } 380408de2844SGiridhar Malavali 380508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 380608de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 380708de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 380808de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 380908de2844SGiridhar Malavali } else 381008de2844SGiridhar Malavali addr = crb_addr; 381108de2844SGiridhar Malavali 381208de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 381308de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 381408de2844SGiridhar Malavali read_value = 381508de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 381608de2844SGiridhar Malavali } else 381708de2844SGiridhar Malavali read_value = crb_entry->value_1; 381808de2844SGiridhar Malavali 381908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 382008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 382108de2844SGiridhar Malavali } 382208de2844SGiridhar Malavali 382308de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 382408de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 382508de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 382608de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 382708de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 382808de2844SGiridhar Malavali if (crb_entry->value_2) 382908de2844SGiridhar Malavali read_value &= crb_entry->value_2; 383008de2844SGiridhar Malavali read_value |= crb_entry->value_3; 383108de2844SGiridhar Malavali read_value += crb_entry->value_1; 383208de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 383308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 383408de2844SGiridhar Malavali } 383508de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 383608de2844SGiridhar Malavali } 383708de2844SGiridhar Malavali return rval; 383808de2844SGiridhar Malavali } 383908de2844SGiridhar Malavali 384008de2844SGiridhar Malavali static void 384108de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 384208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 384308de2844SGiridhar Malavali { 384408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 384508de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 384608de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 384708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 384808de2844SGiridhar Malavali 384908de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 385008de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 385108de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 385208de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 385308de2844SGiridhar Malavali 385408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 38558dfa4b5aSBart Van Assche r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase); 385608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 385708de2844SGiridhar Malavali r_addr += r_stride; 385808de2844SGiridhar Malavali } 385908de2844SGiridhar Malavali *d_ptr = data_ptr; 386008de2844SGiridhar Malavali } 386108de2844SGiridhar Malavali 386208de2844SGiridhar Malavali static void 386308de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 386408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 386508de2844SGiridhar Malavali { 386608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 386708de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 386808de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 386908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 387008de2844SGiridhar Malavali 387108de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 387208de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 387308de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 387408de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 387508de2844SGiridhar Malavali s_value = mux_hdr->select_value; 387608de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 387708de2844SGiridhar Malavali 387808de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 387908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 388008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 388108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 388208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 388308de2844SGiridhar Malavali s_value += s_stride; 388408de2844SGiridhar Malavali } 388508de2844SGiridhar Malavali *d_ptr = data_ptr; 388608de2844SGiridhar Malavali } 388708de2844SGiridhar Malavali 388808de2844SGiridhar Malavali static void 388908de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 389008de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 389108de2844SGiridhar Malavali { 389208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 389308de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 389408de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 389508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 389608de2844SGiridhar Malavali 389708de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 389808de2844SGiridhar Malavali r_addr = crb_hdr->addr; 389908de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 390008de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 390108de2844SGiridhar Malavali 390208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 390308de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 390408de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 390508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 390608de2844SGiridhar Malavali r_addr += r_stride; 390708de2844SGiridhar Malavali } 390808de2844SGiridhar Malavali *d_ptr = data_ptr; 390908de2844SGiridhar Malavali } 391008de2844SGiridhar Malavali 391108de2844SGiridhar Malavali static int 391208de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 391308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 391408de2844SGiridhar Malavali { 391508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 391608de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 391708de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 391808de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 391908de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 392008de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 392108de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 392208de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 392308de2844SGiridhar Malavali 392408de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 392508de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 392608de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 392708de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 392808de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 392908de2844SGiridhar Malavali 393008de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 393108de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 393208de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 393308de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 393408de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 393508de2844SGiridhar Malavali 393608de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 393708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 393808de2844SGiridhar Malavali if (c_value_w) 393908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 394008de2844SGiridhar Malavali 394108de2844SGiridhar Malavali if (p_mask) { 394208de2844SGiridhar Malavali w_time = jiffies + p_wait; 394308de2844SGiridhar Malavali do { 394408de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 394508de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 394608de2844SGiridhar Malavali break; 394708de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 394808de2844SGiridhar Malavali /* capturing dump failed */ 394908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 395008de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 395108de2844SGiridhar Malavali "w_time: 0x%lx\n", 395208de2844SGiridhar Malavali c_value_r, p_mask, w_time); 395308de2844SGiridhar Malavali return rval; 395408de2844SGiridhar Malavali } 395508de2844SGiridhar Malavali } while (1); 395608de2844SGiridhar Malavali } 395708de2844SGiridhar Malavali 395808de2844SGiridhar Malavali addr = r_addr; 395908de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 396008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 396108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 396208de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 396308de2844SGiridhar Malavali } 396408de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 396508de2844SGiridhar Malavali } 396608de2844SGiridhar Malavali *d_ptr = data_ptr; 396708de2844SGiridhar Malavali return QLA_SUCCESS; 396808de2844SGiridhar Malavali } 396908de2844SGiridhar Malavali 397008de2844SGiridhar Malavali static void 397108de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 397208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 397308de2844SGiridhar Malavali { 397408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 397508de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 397608de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 397708de2844SGiridhar Malavali uint32_t c_value_w; 397808de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 397908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 398008de2844SGiridhar Malavali 398108de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 398208de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 398308de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 398408de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 398508de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 398608de2844SGiridhar Malavali 398708de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 398808de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 398908de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 399008de2844SGiridhar Malavali 399108de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 399208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 399308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 399408de2844SGiridhar Malavali addr = r_addr; 399508de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 399608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 399708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 399808de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 399908de2844SGiridhar Malavali } 400008de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 400108de2844SGiridhar Malavali } 400208de2844SGiridhar Malavali *d_ptr = data_ptr; 400308de2844SGiridhar Malavali } 400408de2844SGiridhar Malavali 400508de2844SGiridhar Malavali static void 400608de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 400708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 400808de2844SGiridhar Malavali { 400908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 401008de2844SGiridhar Malavali uint32_t s_addr, r_addr; 401108de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 401208de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 401308de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 401408de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 401508de2844SGiridhar Malavali 401608de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 401708de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 401808de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 401908de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 402008de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 402108de2844SGiridhar Malavali 402208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 402308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 402408de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 402508de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 402608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 402708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 402808de2844SGiridhar Malavali r_addr += r_stride; 402908de2844SGiridhar Malavali } 403008de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 403108de2844SGiridhar Malavali } 403208de2844SGiridhar Malavali *d_ptr = data_ptr; 403308de2844SGiridhar Malavali } 403408de2844SGiridhar Malavali 403508de2844SGiridhar Malavali static void 403608de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 403708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 403808de2844SGiridhar Malavali { 403908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 404008de2844SGiridhar Malavali uint32_t r_addr, r_value; 404108de2844SGiridhar Malavali uint32_t i, loop_cnt; 404208de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 404308de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 404408de2844SGiridhar Malavali 404508de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 404608de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 404708de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 404808de2844SGiridhar Malavali 404908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 405008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 405108de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 405208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 405308de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 405408de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 405508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 405608de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 405708de2844SGiridhar Malavali } 405808de2844SGiridhar Malavali *d_ptr = data_ptr; 405908de2844SGiridhar Malavali } 406008de2844SGiridhar Malavali 406108de2844SGiridhar Malavali static int 406208de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 406308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 406408de2844SGiridhar Malavali { 406508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 406608de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 406708de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 406808de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 406908de2844SGiridhar Malavali unsigned long flags; 407008de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 407108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 407208de2844SGiridhar Malavali 407308de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 407408de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 407508de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 407608de2844SGiridhar Malavali 407708de2844SGiridhar Malavali if (r_addr & 0xf) { 407808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 4079d6a03581SMasanari Iida "Read addr 0x%x not 16 bytes aligned\n", r_addr); 408008de2844SGiridhar Malavali return rval; 408108de2844SGiridhar Malavali } 408208de2844SGiridhar Malavali 408308de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 408408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 408508de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 408608de2844SGiridhar Malavali m_hdr->read_data_size); 408708de2844SGiridhar Malavali return rval; 408808de2844SGiridhar Malavali } 408908de2844SGiridhar Malavali 409008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 409108de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 409208de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 409308de2844SGiridhar Malavali 409408de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 409508de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 409608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 409708de2844SGiridhar Malavali r_value = 0; 409808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 409908de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 410008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 410108de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 410208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 410308de2844SGiridhar Malavali 410408de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 410508de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 410608de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 410708de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 410808de2844SGiridhar Malavali break; 410908de2844SGiridhar Malavali } 411008de2844SGiridhar Malavali 411108de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 411208de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 411308de2844SGiridhar Malavali "failed to read through agent\n"); 411408de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 411508de2844SGiridhar Malavali return rval; 411608de2844SGiridhar Malavali } 411708de2844SGiridhar Malavali 411808de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 411908de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 412008de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 412108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 412208de2844SGiridhar Malavali } 412308de2844SGiridhar Malavali r_addr += 16; 412408de2844SGiridhar Malavali } 412508de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 412608de2844SGiridhar Malavali *d_ptr = data_ptr; 412708de2844SGiridhar Malavali return QLA_SUCCESS; 412808de2844SGiridhar Malavali } 412908de2844SGiridhar Malavali 41307ec0effdSAtul Deshmukh int 413108de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 413208de2844SGiridhar Malavali { 413308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 413408de2844SGiridhar Malavali uint64_t chksum = 0; 413508de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 413608de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 413708de2844SGiridhar Malavali 413808de2844SGiridhar Malavali while (count-- > 0) 413908de2844SGiridhar Malavali chksum += *d_ptr++; 414008de2844SGiridhar Malavali while (chksum >> 32) 414108de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 414208de2844SGiridhar Malavali return ~chksum; 414308de2844SGiridhar Malavali } 414408de2844SGiridhar Malavali 414508de2844SGiridhar Malavali static void 414608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 414708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 414808de2844SGiridhar Malavali { 414908de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 415008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 415108de2844SGiridhar Malavali "Skipping entry[%d]: " 415208de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 415308de2844SGiridhar Malavali index, entry_hdr->entry_type, 415408de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 415508de2844SGiridhar Malavali } 415608de2844SGiridhar Malavali 415708de2844SGiridhar Malavali int 415808de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 415908de2844SGiridhar Malavali { 416008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 416108de2844SGiridhar Malavali int no_entry_hdr = 0; 416208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 416308de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 416408de2844SGiridhar Malavali uint32_t *data_ptr; 416508de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 416608de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 416708de2844SGiridhar Malavali 416808de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 416908de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 417008de2844SGiridhar Malavali 417108de2844SGiridhar Malavali if (ha->fw_dumped) { 4172a8faa263SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb037, 4173a8faa263SGiridhar Malavali "Firmware has been previously dumped (%p) " 4174a8faa263SGiridhar Malavali "-- ignoring request.\n", ha->fw_dump); 417508de2844SGiridhar Malavali goto md_failed; 417608de2844SGiridhar Malavali } 417708de2844SGiridhar Malavali 417808de2844SGiridhar Malavali ha->fw_dumped = 0; 417908de2844SGiridhar Malavali 418008de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 418108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 418208de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 418308de2844SGiridhar Malavali goto md_failed; 418408de2844SGiridhar Malavali } 418508de2844SGiridhar Malavali 4186b6d0d9d5SGiridhar Malavali if (ha->flags.isp82xx_no_md_cap) { 4187b6d0d9d5SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb054, 4188b6d0d9d5SGiridhar Malavali "Forced reset from application, " 4189b6d0d9d5SGiridhar Malavali "ignore minidump capture\n"); 4190b6d0d9d5SGiridhar Malavali ha->flags.isp82xx_no_md_cap = 0; 4191b6d0d9d5SGiridhar Malavali goto md_failed; 4192b6d0d9d5SGiridhar Malavali } 4193b6d0d9d5SGiridhar Malavali 419408de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 419508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 419608de2844SGiridhar Malavali "Template checksum validation error\n"); 419708de2844SGiridhar Malavali goto md_failed; 419808de2844SGiridhar Malavali } 419908de2844SGiridhar Malavali 420008de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 420108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 420208de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 420308de2844SGiridhar Malavali 420408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 420508de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 420608de2844SGiridhar Malavali 420708de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 420808de2844SGiridhar Malavali 420908de2844SGiridhar Malavali /* Validate whether required debug level is set */ 421008de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 421108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 421208de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 421308de2844SGiridhar Malavali f_capture_mask); 421408de2844SGiridhar Malavali goto md_failed; 421508de2844SGiridhar Malavali } 421608de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 421708de2844SGiridhar Malavali 421808de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 421908de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 422008de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 422108de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 422208de2844SGiridhar Malavali 422308de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 422408de2844SGiridhar Malavali 4225880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb03d, 422608de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 422708de2844SGiridhar Malavali 422808de2844SGiridhar Malavali /* Check whether template obtained is valid */ 422908de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 423008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 423108de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 423208de2844SGiridhar Malavali tmplt_hdr->entry_type); 423308de2844SGiridhar Malavali goto md_failed; 423408de2844SGiridhar Malavali } 423508de2844SGiridhar Malavali 423608de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 423708de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 423808de2844SGiridhar Malavali 423908de2844SGiridhar Malavali /* Walk through the entry headers */ 424008de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 424108de2844SGiridhar Malavali 424208de2844SGiridhar Malavali if (data_collected > total_data_size) { 424308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 424408de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 424508de2844SGiridhar Malavali data_collected); 424608de2844SGiridhar Malavali goto md_failed; 424708de2844SGiridhar Malavali } 424808de2844SGiridhar Malavali 424908de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 425008de2844SGiridhar Malavali ql2xmdcapmask)) { 425108de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 425208de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 425308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 425408de2844SGiridhar Malavali "Skipping entry[%d]: " 425508de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 425608de2844SGiridhar Malavali i, entry_hdr->entry_type, 425708de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 425808de2844SGiridhar Malavali goto skip_nxt_entry; 425908de2844SGiridhar Malavali } 426008de2844SGiridhar Malavali 426108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 426208de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 42630bf0efa1SColin Ian King "entry_type: 0x%x, capture_mask: 0x%x\n", 426408de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 426508de2844SGiridhar Malavali entry_hdr->entry_type, 426608de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 426708de2844SGiridhar Malavali 426808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 426908de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 427008de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 427108de2844SGiridhar Malavali 427208de2844SGiridhar Malavali /* Decode the entry type and take 427308de2844SGiridhar Malavali * required action to capture debug data */ 427408de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 427508de2844SGiridhar Malavali case QLA82XX_RDEND: 427608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 427708de2844SGiridhar Malavali break; 427808de2844SGiridhar Malavali case QLA82XX_CNTRL: 427908de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 428008de2844SGiridhar Malavali entry_hdr, &data_ptr); 428108de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 428208de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 428308de2844SGiridhar Malavali goto md_failed; 428408de2844SGiridhar Malavali } 428508de2844SGiridhar Malavali break; 428608de2844SGiridhar Malavali case QLA82XX_RDCRB: 428708de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 428808de2844SGiridhar Malavali entry_hdr, &data_ptr); 428908de2844SGiridhar Malavali break; 429008de2844SGiridhar Malavali case QLA82XX_RDMEM: 429108de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 429208de2844SGiridhar Malavali entry_hdr, &data_ptr); 429308de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 429408de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 429508de2844SGiridhar Malavali goto md_failed; 429608de2844SGiridhar Malavali } 429708de2844SGiridhar Malavali break; 429808de2844SGiridhar Malavali case QLA82XX_BOARD: 429908de2844SGiridhar Malavali case QLA82XX_RDROM: 430008de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 430108de2844SGiridhar Malavali entry_hdr, &data_ptr); 430208de2844SGiridhar Malavali break; 430308de2844SGiridhar Malavali case QLA82XX_L2DTG: 430408de2844SGiridhar Malavali case QLA82XX_L2ITG: 430508de2844SGiridhar Malavali case QLA82XX_L2DAT: 430608de2844SGiridhar Malavali case QLA82XX_L2INS: 430708de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 430808de2844SGiridhar Malavali entry_hdr, &data_ptr); 430908de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 431008de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 431108de2844SGiridhar Malavali goto md_failed; 431208de2844SGiridhar Malavali } 431308de2844SGiridhar Malavali break; 431408de2844SGiridhar Malavali case QLA82XX_L1DAT: 431508de2844SGiridhar Malavali case QLA82XX_L1INS: 431608de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 431708de2844SGiridhar Malavali entry_hdr, &data_ptr); 431808de2844SGiridhar Malavali break; 431908de2844SGiridhar Malavali case QLA82XX_RDOCM: 432008de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 432108de2844SGiridhar Malavali entry_hdr, &data_ptr); 432208de2844SGiridhar Malavali break; 432308de2844SGiridhar Malavali case QLA82XX_RDMUX: 432408de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 432508de2844SGiridhar Malavali entry_hdr, &data_ptr); 432608de2844SGiridhar Malavali break; 432708de2844SGiridhar Malavali case QLA82XX_QUEUE: 432808de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 432908de2844SGiridhar Malavali entry_hdr, &data_ptr); 433008de2844SGiridhar Malavali break; 433108de2844SGiridhar Malavali case QLA82XX_RDNOP: 433208de2844SGiridhar Malavali default: 433308de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 433408de2844SGiridhar Malavali break; 433508de2844SGiridhar Malavali } 433608de2844SGiridhar Malavali 433708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 433808de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 433908de2844SGiridhar Malavali 434008de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 434108de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 434208de2844SGiridhar Malavali skip_nxt_entry: 434308de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 434408de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 434508de2844SGiridhar Malavali } 434608de2844SGiridhar Malavali 434708de2844SGiridhar Malavali if (data_collected != total_data_size) { 4348880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb043, 434908de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 435008de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 435108de2844SGiridhar Malavali data_collected, total_data_size); 435208de2844SGiridhar Malavali goto md_failed; 435308de2844SGiridhar Malavali } 435408de2844SGiridhar Malavali 435508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 435608de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 435708de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 435808de2844SGiridhar Malavali ha->fw_dumped = 1; 435908de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 436008de2844SGiridhar Malavali 436108de2844SGiridhar Malavali md_failed: 436208de2844SGiridhar Malavali return rval; 436308de2844SGiridhar Malavali } 436408de2844SGiridhar Malavali 436508de2844SGiridhar Malavali int 436608de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 436708de2844SGiridhar Malavali { 436808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 436908de2844SGiridhar Malavali int i, k; 437008de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 437108de2844SGiridhar Malavali 437208de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 437308de2844SGiridhar Malavali 437408de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 437508de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 437608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 437708de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 437808de2844SGiridhar Malavali ql2xmdcapmask); 437908de2844SGiridhar Malavali } 438008de2844SGiridhar Malavali 438108de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 438208de2844SGiridhar Malavali if (i & ql2xmdcapmask) 438308de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 438408de2844SGiridhar Malavali } 438508de2844SGiridhar Malavali 438608de2844SGiridhar Malavali if (ha->md_dump) { 438708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 438808de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 438908de2844SGiridhar Malavali return 1; 439008de2844SGiridhar Malavali } 439108de2844SGiridhar Malavali 439208de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 439308de2844SGiridhar Malavali if (ha->md_dump == NULL) { 439408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 439508de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 439608de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 439708de2844SGiridhar Malavali return 1; 439808de2844SGiridhar Malavali } 439908de2844SGiridhar Malavali return 0; 440008de2844SGiridhar Malavali } 440108de2844SGiridhar Malavali 440208de2844SGiridhar Malavali void 440308de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 440408de2844SGiridhar Malavali { 440508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 440608de2844SGiridhar Malavali 440708de2844SGiridhar Malavali /* Release the template header allocated */ 440808de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 440908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 441008de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 441108de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 441208de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 441308de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4414fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 441508de2844SGiridhar Malavali } 441608de2844SGiridhar Malavali 441708de2844SGiridhar Malavali /* Release the template data buffer allocated */ 441808de2844SGiridhar Malavali if (ha->md_dump) { 441908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 442008de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 442108de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 442208de2844SGiridhar Malavali vfree(ha->md_dump); 442308de2844SGiridhar Malavali ha->md_dump_size = 0; 4424fa492630SSaurav Kashyap ha->md_dump = NULL; 442508de2844SGiridhar Malavali } 442608de2844SGiridhar Malavali } 442708de2844SGiridhar Malavali 442808de2844SGiridhar Malavali void 442908de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 443008de2844SGiridhar Malavali { 443108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 443208de2844SGiridhar Malavali int rval; 443308de2844SGiridhar Malavali 443408de2844SGiridhar Malavali /* Get Minidump template size */ 443508de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 443608de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 443708de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 443808de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 443908de2844SGiridhar Malavali ha->md_template_size / 1024); 444008de2844SGiridhar Malavali 444108de2844SGiridhar Malavali /* Get Minidump template */ 44427ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 44437ec0effdSAtul Deshmukh rval = qla8044_md_get_template(vha); 44447ec0effdSAtul Deshmukh else 444508de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 44467ec0effdSAtul Deshmukh 444708de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 444808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 444908de2844SGiridhar Malavali "MiniDump Template obtained\n"); 445008de2844SGiridhar Malavali 445108de2844SGiridhar Malavali /* Allocate memory for minidump */ 445208de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 445308de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 445408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 445508de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 445608de2844SGiridhar Malavali ha->md_dump_size / 1024); 445708de2844SGiridhar Malavali else { 445808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 445908de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 446008de2844SGiridhar Malavali ha->md_tmplt_hdr, 446108de2844SGiridhar Malavali ha->md_template_size / 1024); 446208de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 446308de2844SGiridhar Malavali ha->md_template_size, 446408de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4465fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 446608de2844SGiridhar Malavali } 446708de2844SGiridhar Malavali 446808de2844SGiridhar Malavali } 446908de2844SGiridhar Malavali } 447008de2844SGiridhar Malavali } 4471999916dcSSaurav Kashyap 4472999916dcSSaurav Kashyap int 4473999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4474999916dcSSaurav Kashyap { 4475999916dcSSaurav Kashyap 4476999916dcSSaurav Kashyap int rval; 4477999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4478bd432bb5SBart Van Assche 4479999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4480999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4481999916dcSSaurav Kashyap 4482999916dcSSaurav Kashyap if (rval) { 4483999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4484999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4485999916dcSSaurav Kashyap goto exit; 4486999916dcSSaurav Kashyap } 4487999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4488999916dcSSaurav Kashyap exit: 4489999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4490999916dcSSaurav Kashyap return rval; 4491999916dcSSaurav Kashyap } 4492999916dcSSaurav Kashyap 4493999916dcSSaurav Kashyap int 4494999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4495999916dcSSaurav Kashyap { 4496999916dcSSaurav Kashyap 4497999916dcSSaurav Kashyap int rval; 4498999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4499bd432bb5SBart Van Assche 4500999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4501999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4502999916dcSSaurav Kashyap 4503999916dcSSaurav Kashyap if (rval) { 4504999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4505999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4506999916dcSSaurav Kashyap goto exit; 4507999916dcSSaurav Kashyap } 4508999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4509999916dcSSaurav Kashyap exit: 4510999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4511999916dcSSaurav Kashyap return rval; 4512999916dcSSaurav Kashyap } 4513a1b23c5aSChad Dupuis 4514a1b23c5aSChad Dupuis void 4515a1b23c5aSChad Dupuis qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4516a1b23c5aSChad Dupuis { 4517a1b23c5aSChad Dupuis struct qla_hw_data *ha = vha->hw; 4518a1b23c5aSChad Dupuis 4519a1b23c5aSChad Dupuis if (!ha->allow_cna_fw_dump) 4520a1b23c5aSChad Dupuis return; 4521a1b23c5aSChad Dupuis 4522a1b23c5aSChad Dupuis scsi_block_requests(vha->host); 4523a1b23c5aSChad Dupuis ha->flags.isp82xx_no_md_cap = 1; 4524a1b23c5aSChad Dupuis qla82xx_idc_lock(ha); 4525a1b23c5aSChad Dupuis qla82xx_set_reset_owner(vha); 4526a1b23c5aSChad Dupuis qla82xx_idc_unlock(ha); 4527a1b23c5aSChad Dupuis qla2x00_wait_for_chip_reset(vha); 4528a1b23c5aSChad Dupuis scsi_unblock_requests(vha->host); 4529a1b23c5aSChad Dupuis } 4530