1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 3bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39fa492630SSaurav Kashyap static int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 45a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 46a9083016SGiridhar Malavali { 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 97a9083016SGiridhar Malavali /* 98a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 99a9083016SGiridhar Malavali */ 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 101a9083016SGiridhar Malavali 102a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 103a9083016SGiridhar Malavali } 104a9083016SGiridhar Malavali 105fa492630SSaurav Kashyap static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 107a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 108a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 109a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 110a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 111a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 112a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 113a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 114a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 123a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 125a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213a9083016SGiridhar Malavali {{{0} } }, 214a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 215a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 216a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 217a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 218a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 219a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 220a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 221a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 230a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{0} } }, 235a9083016SGiridhar Malavali {{{0} } }, 236a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248a9083016SGiridhar Malavali {{{0} } }, 249a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255a9083016SGiridhar Malavali {{{0} } }, 256a9083016SGiridhar Malavali {{{0} } }, 257a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260a9083016SGiridhar Malavali }; 261a9083016SGiridhar Malavali 262a9083016SGiridhar Malavali /* 263a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 264a9083016SGiridhar Malavali */ 265fa492630SSaurav Kashyap static unsigned qla82xx_crb_hub_agt[64] = { 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270a9083016SGiridhar Malavali 0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293a9083016SGiridhar Malavali 0, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318a9083016SGiridhar Malavali 0, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali }; 331a9083016SGiridhar Malavali 332f1af6208SGiridhar Malavali /* Device states */ 333fa492630SSaurav Kashyap static char *q_dev_state[] = { 334f1af6208SGiridhar Malavali "Unknown", 335f1af6208SGiridhar Malavali "Cold", 336f1af6208SGiridhar Malavali "Initializing", 337f1af6208SGiridhar Malavali "Ready", 338f1af6208SGiridhar Malavali "Need Reset", 339f1af6208SGiridhar Malavali "Need Quiescent", 340f1af6208SGiridhar Malavali "Failed", 341f1af6208SGiridhar Malavali "Quiescent", 342f1af6208SGiridhar Malavali }; 343f1af6208SGiridhar Malavali 34408de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 34508de2844SGiridhar Malavali { 34608de2844SGiridhar Malavali return q_dev_state[dev_state]; 34708de2844SGiridhar Malavali } 34808de2844SGiridhar Malavali 349a9083016SGiridhar Malavali /* 350a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 351a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 352a9083016SGiridhar Malavali * side effect: lock crb window 353a9083016SGiridhar Malavali */ 354a9083016SGiridhar Malavali static void 355a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356a9083016SGiridhar Malavali { 357a9083016SGiridhar Malavali u32 win_read; 3587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359a9083016SGiridhar Malavali 360a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 361a9083016SGiridhar Malavali writel(ha->crb_win, 362fa492630SSaurav Kashyap (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363a9083016SGiridhar Malavali 364a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 365a9083016SGiridhar Malavali * to use it. 366a9083016SGiridhar Malavali */ 367fa492630SSaurav Kashyap win_read = RD_REG_DWORD((void __iomem *) 368fa492630SSaurav Kashyap (CRB_WINDOW_2M + ha->nx_pcibase)); 369a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3707c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3717c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3727c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 373d8424f68SJoe Perches __func__, ha->crb_win, win_read, *off); 374a9083016SGiridhar Malavali } 375a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376a9083016SGiridhar Malavali } 377a9083016SGiridhar Malavali 378a9083016SGiridhar Malavali static inline unsigned long 379a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380a9083016SGiridhar Malavali { 3817c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 383a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 385a9083016SGiridhar Malavali * regs are in both windows. 386a9083016SGiridhar Malavali */ 387a9083016SGiridhar Malavali return off; 388a9083016SGiridhar Malavali } 389a9083016SGiridhar Malavali 390a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391a9083016SGiridhar Malavali /* We are in first CRB window */ 392a9083016SGiridhar Malavali if (ha->curr_window != 0) 393a9083016SGiridhar Malavali WARN_ON(1); 394a9083016SGiridhar Malavali return off; 395a9083016SGiridhar Malavali } 396a9083016SGiridhar Malavali 397a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398a9083016SGiridhar Malavali /* We are in second CRB window */ 399a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400a9083016SGiridhar Malavali 401a9083016SGiridhar Malavali if (ha->curr_window != 1) 402a9083016SGiridhar Malavali return off; 403a9083016SGiridhar Malavali 404a9083016SGiridhar Malavali /* We are in the QM or direct access 405a9083016SGiridhar Malavali * register region - do nothing 406a9083016SGiridhar Malavali */ 407a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 409a9083016SGiridhar Malavali return off; 410a9083016SGiridhar Malavali } 411a9083016SGiridhar Malavali /* strange address given */ 4127c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 413d8424f68SJoe Perches "%s: Warning: unm_nic_pci_set_crbwindow " 4147c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4157c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 416a9083016SGiridhar Malavali return off; 417a9083016SGiridhar Malavali } 418a9083016SGiridhar Malavali 41977e334d2SGiridhar Malavali static int 42077e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 42177e334d2SGiridhar Malavali { 42277e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42377e334d2SGiridhar Malavali 42477e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 42577e334d2SGiridhar Malavali return -1; 42677e334d2SGiridhar Malavali 42777e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42877e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42977e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 43077e334d2SGiridhar Malavali return 0; 43177e334d2SGiridhar Malavali } 43277e334d2SGiridhar Malavali 43377e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 43477e334d2SGiridhar Malavali return -1; 43577e334d2SGiridhar Malavali 43677e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 43777e334d2SGiridhar Malavali 43877e334d2SGiridhar Malavali /* Try direct map */ 43977e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 44077e334d2SGiridhar Malavali 44177e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 44277e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 44377e334d2SGiridhar Malavali return 0; 44477e334d2SGiridhar Malavali } 44577e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 44677e334d2SGiridhar Malavali return 1; 44777e334d2SGiridhar Malavali } 44877e334d2SGiridhar Malavali 44977e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 45077e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45177e334d2SGiridhar Malavali { 45277e334d2SGiridhar Malavali int done = 0, timeout = 0; 45377e334d2SGiridhar Malavali 45477e334d2SGiridhar Malavali while (!done) { 45577e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 45677e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 45777e334d2SGiridhar Malavali if (done == 1) 45877e334d2SGiridhar Malavali break; 45977e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 46077e334d2SGiridhar Malavali return -1; 46177e334d2SGiridhar Malavali timeout++; 46277e334d2SGiridhar Malavali } 46377e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 46477e334d2SGiridhar Malavali return 0; 46577e334d2SGiridhar Malavali } 46677e334d2SGiridhar Malavali 467a9083016SGiridhar Malavali int 468a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469a9083016SGiridhar Malavali { 470a9083016SGiridhar Malavali unsigned long flags = 0; 471a9083016SGiridhar Malavali int rv; 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474a9083016SGiridhar Malavali 475a9083016SGiridhar Malavali BUG_ON(rv == -1); 476a9083016SGiridhar Malavali 477a9083016SGiridhar Malavali if (rv == 1) { 478a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 479a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 480a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 481a9083016SGiridhar Malavali } 482a9083016SGiridhar Malavali 483a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 484a9083016SGiridhar Malavali 485a9083016SGiridhar Malavali if (rv == 1) { 486a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 488a9083016SGiridhar Malavali } 489a9083016SGiridhar Malavali return 0; 490a9083016SGiridhar Malavali } 491a9083016SGiridhar Malavali 492a9083016SGiridhar Malavali int 493a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494a9083016SGiridhar Malavali { 495a9083016SGiridhar Malavali unsigned long flags = 0; 496a9083016SGiridhar Malavali int rv; 497a9083016SGiridhar Malavali u32 data; 498a9083016SGiridhar Malavali 499a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500a9083016SGiridhar Malavali 501a9083016SGiridhar Malavali BUG_ON(rv == -1); 502a9083016SGiridhar Malavali 503a9083016SGiridhar Malavali if (rv == 1) { 504a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 505a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 506a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 507a9083016SGiridhar Malavali } 508a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 509a9083016SGiridhar Malavali 510a9083016SGiridhar Malavali if (rv == 1) { 511a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 513a9083016SGiridhar Malavali } 514a9083016SGiridhar Malavali return data; 515a9083016SGiridhar Malavali } 516a9083016SGiridhar Malavali 517a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 518a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 519a9083016SGiridhar Malavali { 520a9083016SGiridhar Malavali int i; 521a9083016SGiridhar Malavali int done = 0, timeout = 0; 522a9083016SGiridhar Malavali 523a9083016SGiridhar Malavali while (!done) { 524a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 525a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526a9083016SGiridhar Malavali if (done == 1) 527a9083016SGiridhar Malavali break; 528a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 529a9083016SGiridhar Malavali return -1; 530a9083016SGiridhar Malavali 531a9083016SGiridhar Malavali timeout++; 532a9083016SGiridhar Malavali 533a9083016SGiridhar Malavali /* Yield CPU */ 534a9083016SGiridhar Malavali if (!in_interrupt()) 535a9083016SGiridhar Malavali schedule(); 536a9083016SGiridhar Malavali else { 537a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 538a9083016SGiridhar Malavali cpu_relax(); 539a9083016SGiridhar Malavali } 540a9083016SGiridhar Malavali } 541a9083016SGiridhar Malavali 542a9083016SGiridhar Malavali return 0; 543a9083016SGiridhar Malavali } 544a9083016SGiridhar Malavali 545a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 546a9083016SGiridhar Malavali { 547a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548a9083016SGiridhar Malavali } 549a9083016SGiridhar Malavali 550a9083016SGiridhar Malavali /* 551a9083016SGiridhar Malavali * check memory access boundary. 552a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 553a9083016SGiridhar Malavali */ 554a9083016SGiridhar Malavali static unsigned long 555a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 556a9083016SGiridhar Malavali unsigned long long addr, int size) 557a9083016SGiridhar Malavali { 558df3f4cd0SBart Van Assche if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 559a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 560df3f4cd0SBart Van Assche !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 561a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 562a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 563a9083016SGiridhar Malavali return 0; 564a9083016SGiridhar Malavali else 565a9083016SGiridhar Malavali return 1; 566a9083016SGiridhar Malavali } 567a9083016SGiridhar Malavali 568fa492630SSaurav Kashyap static int qla82xx_pci_set_window_warning_count; 569a9083016SGiridhar Malavali 57077e334d2SGiridhar Malavali static unsigned long 571a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 572a9083016SGiridhar Malavali { 573a9083016SGiridhar Malavali int window; 574a9083016SGiridhar Malavali u32 win_read; 5757c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 576a9083016SGiridhar Malavali 577df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 578a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 579a9083016SGiridhar Malavali /* DDR network side */ 580a9083016SGiridhar Malavali window = MN_WIN(addr); 581a9083016SGiridhar Malavali ha->ddr_mn_window = window; 582a9083016SGiridhar Malavali qla82xx_wr_32(ha, 583a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 584a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 585a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 586a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5877c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5887c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 589a9083016SGiridhar Malavali __func__, window, win_read); 590a9083016SGiridhar Malavali } 591a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 592df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 593a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 594a9083016SGiridhar Malavali unsigned int temp1; 595a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5967c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 597a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 598a9083016SGiridhar Malavali addr = -1UL; 599a9083016SGiridhar Malavali } 600a9083016SGiridhar Malavali window = OCM_WIN(addr); 601a9083016SGiridhar Malavali ha->ddr_mn_window = window; 602a9083016SGiridhar Malavali qla82xx_wr_32(ha, 603a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 604a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 605a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 606a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 607a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 608a9083016SGiridhar Malavali if (win_read != temp1) { 6097c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6107c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 611a9083016SGiridhar Malavali __func__, temp1, win_read); 612a9083016SGiridhar Malavali } 613a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 614a9083016SGiridhar Malavali 615df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 616a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 617a9083016SGiridhar Malavali /* QDR network side */ 618a9083016SGiridhar Malavali window = MS_WIN(addr); 619a9083016SGiridhar Malavali ha->qdr_sn_window = window; 620a9083016SGiridhar Malavali qla82xx_wr_32(ha, 621a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 622a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 623a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 624a9083016SGiridhar Malavali if (win_read != window) { 6257c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6267c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 627a9083016SGiridhar Malavali __func__, window, win_read); 628a9083016SGiridhar Malavali } 629a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 630a9083016SGiridhar Malavali } else { 631a9083016SGiridhar Malavali /* 632a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 633a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 634a9083016SGiridhar Malavali */ 635a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 636a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6377c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6387c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6397c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 640a9083016SGiridhar Malavali } 641a9083016SGiridhar Malavali addr = -1UL; 642a9083016SGiridhar Malavali } 643a9083016SGiridhar Malavali return addr; 644a9083016SGiridhar Malavali } 645a9083016SGiridhar Malavali 646a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 647a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 648a9083016SGiridhar Malavali unsigned long long addr) 649a9083016SGiridhar Malavali { 650a9083016SGiridhar Malavali int window; 651a9083016SGiridhar Malavali unsigned long long qdr_max; 652a9083016SGiridhar Malavali 653a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 654a9083016SGiridhar Malavali 655a9083016SGiridhar Malavali /* DDR network side */ 656df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 657a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 658a9083016SGiridhar Malavali BUG(); 659df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 660a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 661a9083016SGiridhar Malavali return 1; 662df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 663a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 664a9083016SGiridhar Malavali return 1; 665df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 666a9083016SGiridhar Malavali /* QDR network side */ 667a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 668a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 669a9083016SGiridhar Malavali return 1; 670a9083016SGiridhar Malavali } 671a9083016SGiridhar Malavali return 0; 672a9083016SGiridhar Malavali } 673a9083016SGiridhar Malavali 674a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 675a9083016SGiridhar Malavali u64 off, void *data, int size) 676a9083016SGiridhar Malavali { 677a9083016SGiridhar Malavali unsigned long flags; 678fa492630SSaurav Kashyap void __iomem *addr = NULL; 679a9083016SGiridhar Malavali int ret = 0; 680a9083016SGiridhar Malavali u64 start; 681fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 682a9083016SGiridhar Malavali unsigned long mem_base; 683a9083016SGiridhar Malavali unsigned long mem_page; 6847c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 685a9083016SGiridhar Malavali 686a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 687a9083016SGiridhar Malavali 688a9083016SGiridhar Malavali /* 689a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 690a9083016SGiridhar Malavali * do not access. 691a9083016SGiridhar Malavali */ 692a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 693a9083016SGiridhar Malavali if ((start == -1UL) || 694a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 695a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6967c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 6977c3df132SSaurav Kashyap "%s out of bound pci memory " 6987c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 6997c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 700a9083016SGiridhar Malavali return -1; 701a9083016SGiridhar Malavali } 702a9083016SGiridhar Malavali 703a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 704a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 705a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 706a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 707a9083016SGiridhar Malavali * consecutive pages. 708a9083016SGiridhar Malavali */ 709a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 710a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 711a9083016SGiridhar Malavali else 712a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 713fa492630SSaurav Kashyap if (mem_ptr == NULL) { 714a9083016SGiridhar Malavali *(u8 *)data = 0; 715a9083016SGiridhar Malavali return -1; 716a9083016SGiridhar Malavali } 717a9083016SGiridhar Malavali addr = mem_ptr; 718a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 719a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 720a9083016SGiridhar Malavali 721a9083016SGiridhar Malavali switch (size) { 722a9083016SGiridhar Malavali case 1: 723a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 724a9083016SGiridhar Malavali break; 725a9083016SGiridhar Malavali case 2: 726a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 727a9083016SGiridhar Malavali break; 728a9083016SGiridhar Malavali case 4: 729a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 730a9083016SGiridhar Malavali break; 731a9083016SGiridhar Malavali case 8: 732a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 733a9083016SGiridhar Malavali break; 734a9083016SGiridhar Malavali default: 735a9083016SGiridhar Malavali ret = -1; 736a9083016SGiridhar Malavali break; 737a9083016SGiridhar Malavali } 738a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 739a9083016SGiridhar Malavali 740a9083016SGiridhar Malavali if (mem_ptr) 741a9083016SGiridhar Malavali iounmap(mem_ptr); 742a9083016SGiridhar Malavali return ret; 743a9083016SGiridhar Malavali } 744a9083016SGiridhar Malavali 745a9083016SGiridhar Malavali static int 746a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 747a9083016SGiridhar Malavali u64 off, void *data, int size) 748a9083016SGiridhar Malavali { 749a9083016SGiridhar Malavali unsigned long flags; 750fa492630SSaurav Kashyap void __iomem *addr = NULL; 751a9083016SGiridhar Malavali int ret = 0; 752a9083016SGiridhar Malavali u64 start; 753fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 754a9083016SGiridhar Malavali unsigned long mem_base; 755a9083016SGiridhar Malavali unsigned long mem_page; 7567c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 757a9083016SGiridhar Malavali 758a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 759a9083016SGiridhar Malavali 760a9083016SGiridhar Malavali /* 761a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 762a9083016SGiridhar Malavali * do not access. 763a9083016SGiridhar Malavali */ 764a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 765a9083016SGiridhar Malavali if ((start == -1UL) || 766a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 767a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7687c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7697c3df132SSaurav Kashyap "%s out of bount memory " 7707c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7717c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 772a9083016SGiridhar Malavali return -1; 773a9083016SGiridhar Malavali } 774a9083016SGiridhar Malavali 775a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 776a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 777a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 778a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 779a9083016SGiridhar Malavali * consecutive pages. 780a9083016SGiridhar Malavali */ 781a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 782a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 783a9083016SGiridhar Malavali else 784a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 785fa492630SSaurav Kashyap if (mem_ptr == NULL) 786a9083016SGiridhar Malavali return -1; 787a9083016SGiridhar Malavali 788a9083016SGiridhar Malavali addr = mem_ptr; 789a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 790a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 791a9083016SGiridhar Malavali 792a9083016SGiridhar Malavali switch (size) { 793a9083016SGiridhar Malavali case 1: 794a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 795a9083016SGiridhar Malavali break; 796a9083016SGiridhar Malavali case 2: 797a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 798a9083016SGiridhar Malavali break; 799a9083016SGiridhar Malavali case 4: 800a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 801a9083016SGiridhar Malavali break; 802a9083016SGiridhar Malavali case 8: 803a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 804a9083016SGiridhar Malavali break; 805a9083016SGiridhar Malavali default: 806a9083016SGiridhar Malavali ret = -1; 807a9083016SGiridhar Malavali break; 808a9083016SGiridhar Malavali } 809a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 810a9083016SGiridhar Malavali if (mem_ptr) 811a9083016SGiridhar Malavali iounmap(mem_ptr); 812a9083016SGiridhar Malavali return ret; 813a9083016SGiridhar Malavali } 814a9083016SGiridhar Malavali 815a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81677e334d2SGiridhar Malavali static unsigned long 81777e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 818a9083016SGiridhar Malavali { 819a9083016SGiridhar Malavali int i; 820a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 821a9083016SGiridhar Malavali 822a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 823a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 824a9083016SGiridhar Malavali 825a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 826a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 827a9083016SGiridhar Malavali offset = addr & 0x000fffff; 828a9083016SGiridhar Malavali 829a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 830a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 831a9083016SGiridhar Malavali pci_base = i << 20; 832a9083016SGiridhar Malavali break; 833a9083016SGiridhar Malavali } 834a9083016SGiridhar Malavali } 835a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 836a9083016SGiridhar Malavali return pci_base; 837a9083016SGiridhar Malavali return pci_base + offset; 838a9083016SGiridhar Malavali } 839a9083016SGiridhar Malavali 840a9083016SGiridhar Malavali static long rom_max_timeout = 100; 841a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 842a9083016SGiridhar Malavali 84377e334d2SGiridhar Malavali static int 844a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 845a9083016SGiridhar Malavali { 846a9083016SGiridhar Malavali int done = 0, timeout = 0; 8476c315553SSaurav Kashyap uint32_t lock_owner = 0; 84827f4b72fSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 849a9083016SGiridhar Malavali 850a9083016SGiridhar Malavali while (!done) { 851a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 852a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853a9083016SGiridhar Malavali if (done == 1) 854a9083016SGiridhar Malavali break; 8556c315553SSaurav Kashyap if (timeout >= qla82xx_rom_lock_timeout) { 8566c315553SSaurav Kashyap lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 8577ab3d962SSawan Chandak ql_dbg(ql_dbg_p3p, vha, 0xb157, 85827f4b72fSAtul Deshmukh "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 85927f4b72fSAtul Deshmukh __func__, ha->portnum, lock_owner); 860a9083016SGiridhar Malavali return -1; 8616c315553SSaurav Kashyap } 862a9083016SGiridhar Malavali timeout++; 863a9083016SGiridhar Malavali } 8644babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 865a9083016SGiridhar Malavali return 0; 866a9083016SGiridhar Malavali } 867a9083016SGiridhar Malavali 868d652e093SChad Dupuis static void 869d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 870d652e093SChad Dupuis { 8714babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 872d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 873d652e093SChad Dupuis } 874d652e093SChad Dupuis 87577e334d2SGiridhar Malavali static int 876a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 877a9083016SGiridhar Malavali { 878a9083016SGiridhar Malavali long timeout = 0; 879a9083016SGiridhar Malavali long done = 0 ; 8807c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 881a9083016SGiridhar Malavali 882a9083016SGiridhar Malavali while (done == 0) { 883a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 884a9083016SGiridhar Malavali done &= 4; 885a9083016SGiridhar Malavali timeout++; 886a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8877c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8887c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8897c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 890a9083016SGiridhar Malavali return -1; 891a9083016SGiridhar Malavali } 892a9083016SGiridhar Malavali } 893a9083016SGiridhar Malavali return 0; 894a9083016SGiridhar Malavali } 895a9083016SGiridhar Malavali 89677e334d2SGiridhar Malavali static int 897a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 898a9083016SGiridhar Malavali { 899a9083016SGiridhar Malavali long timeout = 0; 900a9083016SGiridhar Malavali long done = 0 ; 9017c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 902a9083016SGiridhar Malavali 903a9083016SGiridhar Malavali while (done == 0) { 904a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 905a9083016SGiridhar Malavali done &= 2; 906a9083016SGiridhar Malavali timeout++; 907a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9087c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9097c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9107c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 911a9083016SGiridhar Malavali return -1; 912a9083016SGiridhar Malavali } 913a9083016SGiridhar Malavali } 914a9083016SGiridhar Malavali return 0; 915a9083016SGiridhar Malavali } 916a9083016SGiridhar Malavali 917fa492630SSaurav Kashyap static int 9182b29d96dSChad Dupuis qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 9192b29d96dSChad Dupuis { 9202b29d96dSChad Dupuis uint32_t off_value, rval = 0; 9212b29d96dSChad Dupuis 922fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 9232b29d96dSChad Dupuis (off & 0xFFFF0000)); 9242b29d96dSChad Dupuis 9252b29d96dSChad Dupuis /* Read back value to make sure write has gone through */ 926fa492630SSaurav Kashyap RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 9272b29d96dSChad Dupuis off_value = (off & 0x0000FFFF); 9282b29d96dSChad Dupuis 9292b29d96dSChad Dupuis if (flag) 930fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *) 9312b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 9322b29d96dSChad Dupuis data); 9332b29d96dSChad Dupuis else 934fa492630SSaurav Kashyap rval = RD_REG_DWORD((void __iomem *) 9352b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 9362b29d96dSChad Dupuis 9372b29d96dSChad Dupuis return rval; 9382b29d96dSChad Dupuis } 9392b29d96dSChad Dupuis 94077e334d2SGiridhar Malavali static int 941a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 942a9083016SGiridhar Malavali { 9432b29d96dSChad Dupuis /* Dword reads to flash. */ 9442b29d96dSChad Dupuis qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 9452b29d96dSChad Dupuis *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 9462b29d96dSChad Dupuis (addr & 0x0000FFFF), 0, 0); 9477c3df132SSaurav Kashyap 948a9083016SGiridhar Malavali return 0; 949a9083016SGiridhar Malavali } 950a9083016SGiridhar Malavali 95177e334d2SGiridhar Malavali static int 952a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 953a9083016SGiridhar Malavali { 954a9083016SGiridhar Malavali int ret, loops = 0; 9554babb90eSHiral Patel uint32_t lock_owner = 0; 9567c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 957a9083016SGiridhar Malavali 958a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 959a9083016SGiridhar Malavali udelay(100); 960a9083016SGiridhar Malavali schedule(); 961a9083016SGiridhar Malavali loops++; 962a9083016SGiridhar Malavali } 963a9083016SGiridhar Malavali if (loops >= 50000) { 9644babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 9657c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9664babb90eSHiral Patel "Failed to acquire SEM2 lock, Lock Owner %u.\n", 9674babb90eSHiral Patel lock_owner); 968a9083016SGiridhar Malavali return -1; 969a9083016SGiridhar Malavali } 970a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 971d652e093SChad Dupuis qla82xx_rom_unlock(ha); 972a9083016SGiridhar Malavali return ret; 973a9083016SGiridhar Malavali } 974a9083016SGiridhar Malavali 97577e334d2SGiridhar Malavali static int 976a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 977a9083016SGiridhar Malavali { 9787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 980a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 981a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9827c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9837c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 984a9083016SGiridhar Malavali return -1; 985a9083016SGiridhar Malavali } 986a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 987a9083016SGiridhar Malavali return 0; 988a9083016SGiridhar Malavali } 989a9083016SGiridhar Malavali 99077e334d2SGiridhar Malavali static int 991a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 992a9083016SGiridhar Malavali { 993a9083016SGiridhar Malavali long timeout = 0; 994a9083016SGiridhar Malavali uint32_t done = 1 ; 995a9083016SGiridhar Malavali uint32_t val; 996a9083016SGiridhar Malavali int ret = 0; 9977c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 998a9083016SGiridhar Malavali 999a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1000a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 1001a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 1002a9083016SGiridhar Malavali done = val & 1; 1003a9083016SGiridhar Malavali timeout++; 1004a9083016SGiridhar Malavali udelay(10); 1005a9083016SGiridhar Malavali cond_resched(); 1006a9083016SGiridhar Malavali if (timeout >= 50000) { 10077c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 10087c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 1009a9083016SGiridhar Malavali return -1; 1010a9083016SGiridhar Malavali } 1011a9083016SGiridhar Malavali } 1012a9083016SGiridhar Malavali return ret; 1013a9083016SGiridhar Malavali } 1014a9083016SGiridhar Malavali 101577e334d2SGiridhar Malavali static int 1016a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1017a9083016SGiridhar Malavali { 1018a9083016SGiridhar Malavali uint32_t val; 1019a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1020a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1021a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1022a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1023a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1024a9083016SGiridhar Malavali return -1; 1025a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1026a9083016SGiridhar Malavali return -1; 1027a9083016SGiridhar Malavali if ((val & 2) != 2) 1028a9083016SGiridhar Malavali return -1; 1029a9083016SGiridhar Malavali return 0; 1030a9083016SGiridhar Malavali } 1031a9083016SGiridhar Malavali 103277e334d2SGiridhar Malavali static int 1033a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1034a9083016SGiridhar Malavali { 10357c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1036a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1037a9083016SGiridhar Malavali return -1; 1038a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1039a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1040a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10417c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10427c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1043a9083016SGiridhar Malavali return -1; 1044a9083016SGiridhar Malavali } 1045a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1046a9083016SGiridhar Malavali } 1047a9083016SGiridhar Malavali 104877e334d2SGiridhar Malavali static int 1049a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1050a9083016SGiridhar Malavali { 10517c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1052a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1053a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10557c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1056a9083016SGiridhar Malavali return -1; 1057a9083016SGiridhar Malavali } 1058a9083016SGiridhar Malavali return 0; 1059a9083016SGiridhar Malavali } 1060a9083016SGiridhar Malavali 106177e334d2SGiridhar Malavali static int 1062a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1063a9083016SGiridhar Malavali { 1064a9083016SGiridhar Malavali int loops = 0; 10654babb90eSHiral Patel uint32_t lock_owner = 0; 10667c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10677c3df132SSaurav Kashyap 1068a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1069a9083016SGiridhar Malavali udelay(100); 1070a9083016SGiridhar Malavali cond_resched(); 1071a9083016SGiridhar Malavali loops++; 1072a9083016SGiridhar Malavali } 1073a9083016SGiridhar Malavali if (loops >= 50000) { 10744babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 10757c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10764babb90eSHiral Patel "ROM lock failed, Lock Owner %u.\n", lock_owner); 1077a9083016SGiridhar Malavali return -1; 1078a9083016SGiridhar Malavali } 1079cd6dbb03SJesper Juhl return 0; 1080a9083016SGiridhar Malavali } 1081a9083016SGiridhar Malavali 108277e334d2SGiridhar Malavali static int 1083a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1084a9083016SGiridhar Malavali uint32_t data) 1085a9083016SGiridhar Malavali { 1086a9083016SGiridhar Malavali int ret = 0; 10877c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1088a9083016SGiridhar Malavali 1089a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1090a9083016SGiridhar Malavali if (ret < 0) { 10917c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10927c3df132SSaurav Kashyap "ROM lock failed.\n"); 1093a9083016SGiridhar Malavali return ret; 1094a9083016SGiridhar Malavali } 1095a9083016SGiridhar Malavali 1096a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1097a9083016SGiridhar Malavali goto done_write; 1098a9083016SGiridhar Malavali 1099a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1100a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1101a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1102a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1103a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1104a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 11057c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 11067c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1107a9083016SGiridhar Malavali ret = -1; 1108a9083016SGiridhar Malavali goto done_write; 1109a9083016SGiridhar Malavali } 1110a9083016SGiridhar Malavali 1111a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1112a9083016SGiridhar Malavali 1113a9083016SGiridhar Malavali done_write: 1114d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1115a9083016SGiridhar Malavali return ret; 1116a9083016SGiridhar Malavali } 1117a9083016SGiridhar Malavali 1118a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1119a9083016SGiridhar Malavali * to put the ISP into operational state 1120a9083016SGiridhar Malavali */ 112177e334d2SGiridhar Malavali static int 112277e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1123a9083016SGiridhar Malavali { 1124a9083016SGiridhar Malavali int addr, val; 1125a9083016SGiridhar Malavali int i ; 1126a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1127a9083016SGiridhar Malavali unsigned long off; 1128a9083016SGiridhar Malavali unsigned offset, n; 1129a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1130a9083016SGiridhar Malavali 1131a9083016SGiridhar Malavali struct crb_addr_pair { 1132a9083016SGiridhar Malavali long addr; 1133a9083016SGiridhar Malavali long data; 1134a9083016SGiridhar Malavali }; 1135a9083016SGiridhar Malavali 1136a720101dSMasanari Iida /* Halt all the individual PEGs and other blocks of the ISP */ 1137a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1138c9e8fd5cSMadhuranath Iyengar 113902be2215SGiridhar Malavali /* disable all I2Q */ 114002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 114102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 114202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 114302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 114402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 114502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 114602be2215SGiridhar Malavali 114702be2215SGiridhar Malavali /* disable all niu interrupts */ 1148c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1149c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1150c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1151c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1152c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 115302be2215SGiridhar Malavali /* disable sideband mac */ 115402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 115502be2215SGiridhar Malavali /* disable ap0 mac */ 115602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 115702be2215SGiridhar Malavali /* disable ap1 mac */ 115802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1159c9e8fd5cSMadhuranath Iyengar 1160c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1161c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1162c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1163c9e8fd5cSMadhuranath Iyengar 1164c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1165c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1166c9e8fd5cSMadhuranath Iyengar 1167c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1168c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1169c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1170c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1171c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1172c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 117302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1174c9e8fd5cSMadhuranath Iyengar 1175c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1176c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1177c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1178c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1179c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1180c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 118102be2215SGiridhar Malavali msleep(20); 1182c9e8fd5cSMadhuranath Iyengar 1183c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1184a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1185a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1186a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1187a9083016SGiridhar Malavali else 1188a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1189d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1190a9083016SGiridhar Malavali 1191a9083016SGiridhar Malavali /* Read the signature value from the flash. 1192a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1193a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1194a9083016SGiridhar Malavali * that present in CRB initialize sequence 1195a9083016SGiridhar Malavali */ 1196a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1197a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11987c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11997c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1200a9083016SGiridhar Malavali return -1; 1201a9083016SGiridhar Malavali } 1202a9083016SGiridhar Malavali 1203a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 120400adc9a0SSaurav Kashyap * Number of entries = upper 16 bits 1205a9083016SGiridhar Malavali */ 1206a9083016SGiridhar Malavali offset = n & 0xffffU; 1207a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1208a9083016SGiridhar Malavali 120900adc9a0SSaurav Kashyap /* number of addr/value pair should not exceed 1024 entries */ 1210a9083016SGiridhar Malavali if (n >= 1024) { 12117c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 12127c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1213a9083016SGiridhar Malavali return -1; 1214a9083016SGiridhar Malavali } 1215a9083016SGiridhar Malavali 12167c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12177c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1218a9083016SGiridhar Malavali 1219a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1220a9083016SGiridhar Malavali if (buf == NULL) { 12217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12227c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1223a9083016SGiridhar Malavali return -1; 1224a9083016SGiridhar Malavali } 1225a9083016SGiridhar Malavali 1226a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1227a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1228a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1229a9083016SGiridhar Malavali kfree(buf); 1230a9083016SGiridhar Malavali return -1; 1231a9083016SGiridhar Malavali } 1232a9083016SGiridhar Malavali 1233a9083016SGiridhar Malavali buf[i].addr = addr; 1234a9083016SGiridhar Malavali buf[i].data = val; 1235a9083016SGiridhar Malavali } 1236a9083016SGiridhar Malavali 1237a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1238a9083016SGiridhar Malavali /* Translate internal CRB initialization 1239a9083016SGiridhar Malavali * address to PCI bus address 1240a9083016SGiridhar Malavali */ 1241a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1242a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1243a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1244a9083016SGiridhar Malavali * some of them are skipped 1245a9083016SGiridhar Malavali */ 1246a9083016SGiridhar Malavali 1247a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1248a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1249a9083016SGiridhar Malavali continue; 1250a9083016SGiridhar Malavali 1251a9083016SGiridhar Malavali /* do not reset PCI */ 1252a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1253a9083016SGiridhar Malavali continue; 1254a9083016SGiridhar Malavali 1255a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1256a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1257a9083016SGiridhar Malavali continue; 1258a9083016SGiridhar Malavali 1259a9083016SGiridhar Malavali /* skip the function enable register */ 1260a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1261a9083016SGiridhar Malavali continue; 1262a9083016SGiridhar Malavali 1263a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1264a9083016SGiridhar Malavali continue; 1265a9083016SGiridhar Malavali 1266a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1267a9083016SGiridhar Malavali continue; 1268a9083016SGiridhar Malavali 1269a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1270a9083016SGiridhar Malavali continue; 1271a9083016SGiridhar Malavali 1272a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12737c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 1274d939be3aSMasanari Iida "Unknown addr: 0x%08lx.\n", buf[i].addr); 1275a9083016SGiridhar Malavali continue; 1276a9083016SGiridhar Malavali } 1277a9083016SGiridhar Malavali 1278a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1279a9083016SGiridhar Malavali 1280a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1281a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1282a9083016SGiridhar Malavali */ 1283a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1284a9083016SGiridhar Malavali msleep(1000); 1285a9083016SGiridhar Malavali 1286a9083016SGiridhar Malavali /* ISP requires millisec delay between 1287a9083016SGiridhar Malavali * successive CRB register updation 1288a9083016SGiridhar Malavali */ 1289a9083016SGiridhar Malavali msleep(1); 1290a9083016SGiridhar Malavali } 1291a9083016SGiridhar Malavali 1292a9083016SGiridhar Malavali kfree(buf); 1293a9083016SGiridhar Malavali 1294a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1295a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1296a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1297a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1298a9083016SGiridhar Malavali 1299a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1300a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1301a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1302a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1303a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1304a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1305a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1306a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1307a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1308a9083016SGiridhar Malavali return 0; 1309a9083016SGiridhar Malavali } 1310a9083016SGiridhar Malavali 131177e334d2SGiridhar Malavali static int 131277e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 131377e334d2SGiridhar Malavali u64 off, void *data, int size) 131477e334d2SGiridhar Malavali { 131577e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 131677e334d2SGiridhar Malavali int scale, shift_amount, startword; 131777e334d2SGiridhar Malavali uint32_t temp; 131877e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 131977e334d2SGiridhar Malavali 132077e334d2SGiridhar Malavali /* 132177e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 132277e334d2SGiridhar Malavali */ 132377e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 132477e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 132577e334d2SGiridhar Malavali else { 132677e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 132777e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 132877e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 132977e334d2SGiridhar Malavali off, data, size); 133077e334d2SGiridhar Malavali } 133177e334d2SGiridhar Malavali 133277e334d2SGiridhar Malavali off0 = off & 0x7; 133377e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 133477e334d2SGiridhar Malavali sz[1] = size - sz[0]; 133577e334d2SGiridhar Malavali 133677e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 133777e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 133877e334d2SGiridhar Malavali shift_amount = 4; 133977e334d2SGiridhar Malavali scale = 2; 134077e334d2SGiridhar Malavali startword = (off & 0xf)/8; 134177e334d2SGiridhar Malavali 134277e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 134377e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 134477e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 134577e334d2SGiridhar Malavali return -1; 134677e334d2SGiridhar Malavali } 134777e334d2SGiridhar Malavali 134877e334d2SGiridhar Malavali switch (size) { 134977e334d2SGiridhar Malavali case 1: 135077e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 135177e334d2SGiridhar Malavali break; 135277e334d2SGiridhar Malavali case 2: 135377e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 135477e334d2SGiridhar Malavali break; 135577e334d2SGiridhar Malavali case 4: 135677e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 135777e334d2SGiridhar Malavali break; 135877e334d2SGiridhar Malavali case 8: 135977e334d2SGiridhar Malavali default: 136077e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 136177e334d2SGiridhar Malavali break; 136277e334d2SGiridhar Malavali } 136377e334d2SGiridhar Malavali 136477e334d2SGiridhar Malavali if (sz[0] == 8) { 136577e334d2SGiridhar Malavali word[startword] = tmpw; 136677e334d2SGiridhar Malavali } else { 136777e334d2SGiridhar Malavali word[startword] &= 136877e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 136977e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 137077e334d2SGiridhar Malavali } 137177e334d2SGiridhar Malavali if (sz[1] != 0) { 137277e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 137377e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 137477e334d2SGiridhar Malavali } 137577e334d2SGiridhar Malavali 137677e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 137777e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 137877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 137977e334d2SGiridhar Malavali temp = 0; 138077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 138177e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 138277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 138377e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 138477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 138577e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 138677e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 138777e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 138877e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 138977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 139077e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 139177e334d2SGiridhar Malavali 139277e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 139377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 139477e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 139577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 139677e334d2SGiridhar Malavali 139777e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 139877e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 139977e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 140077e334d2SGiridhar Malavali break; 140177e334d2SGiridhar Malavali } 140277e334d2SGiridhar Malavali 140377e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 140477e334d2SGiridhar Malavali if (printk_ratelimit()) 140577e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 14067c3df132SSaurav Kashyap "failed to write through agent.\n"); 140777e334d2SGiridhar Malavali ret = -1; 140877e334d2SGiridhar Malavali break; 140977e334d2SGiridhar Malavali } 141077e334d2SGiridhar Malavali } 141177e334d2SGiridhar Malavali 141277e334d2SGiridhar Malavali return ret; 141377e334d2SGiridhar Malavali } 141477e334d2SGiridhar Malavali 141577e334d2SGiridhar Malavali static int 1416a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1417a9083016SGiridhar Malavali { 1418a9083016SGiridhar Malavali int i; 1419a9083016SGiridhar Malavali long size = 0; 14209c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14219c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1422a9083016SGiridhar Malavali u64 data; 1423a9083016SGiridhar Malavali u32 high, low; 1424a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1425a9083016SGiridhar Malavali 1426a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1427a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1428a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1429a9083016SGiridhar Malavali return -1; 1430a9083016SGiridhar Malavali } 1431a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1432a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1433a9083016SGiridhar Malavali flashaddr += 8; 1434a9083016SGiridhar Malavali memaddr += 8; 1435a9083016SGiridhar Malavali 1436a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1437a9083016SGiridhar Malavali msleep(1); 1438a9083016SGiridhar Malavali } 1439a9083016SGiridhar Malavali udelay(100); 1440a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1441a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1442a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1443a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1444a9083016SGiridhar Malavali return 0; 1445a9083016SGiridhar Malavali } 1446a9083016SGiridhar Malavali 1447a9083016SGiridhar Malavali int 1448a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1449a9083016SGiridhar Malavali u64 off, void *data, int size) 1450a9083016SGiridhar Malavali { 1451a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1452a9083016SGiridhar Malavali int shift_amount; 1453a9083016SGiridhar Malavali uint32_t temp; 1454a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1455a9083016SGiridhar Malavali 1456a9083016SGiridhar Malavali /* 1457a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1458a9083016SGiridhar Malavali */ 1459a9083016SGiridhar Malavali 1460a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1461a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1462a9083016SGiridhar Malavali else { 1463a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1464a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1465a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1466a9083016SGiridhar Malavali off, data, size); 1467a9083016SGiridhar Malavali } 1468a9083016SGiridhar Malavali 1469a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1470a9083016SGiridhar Malavali off0[0] = off & 0xf; 1471a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1472a9083016SGiridhar Malavali shift_amount = 4; 1473a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1474a9083016SGiridhar Malavali off0[1] = 0; 1475a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1476a9083016SGiridhar Malavali 1477a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1478a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1479a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1480a9083016SGiridhar Malavali temp = 0; 1481a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1482a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1483a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1484a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1485a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1486a9083016SGiridhar Malavali 1487a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1488a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1489a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1490a9083016SGiridhar Malavali break; 1491a9083016SGiridhar Malavali } 1492a9083016SGiridhar Malavali 1493a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1494a9083016SGiridhar Malavali if (printk_ratelimit()) 1495a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14967c3df132SSaurav Kashyap "failed to read through agent.\n"); 1497a9083016SGiridhar Malavali break; 1498a9083016SGiridhar Malavali } 1499a9083016SGiridhar Malavali 1500a9083016SGiridhar Malavali start = off0[i] >> 2; 1501a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1502a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1503a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1504a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1505a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1506a9083016SGiridhar Malavali } 1507a9083016SGiridhar Malavali } 1508a9083016SGiridhar Malavali 1509a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1510a9083016SGiridhar Malavali return -1; 1511a9083016SGiridhar Malavali 1512a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1513a9083016SGiridhar Malavali val = word[0]; 1514a9083016SGiridhar Malavali } else { 1515a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1516a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1517a9083016SGiridhar Malavali } 1518a9083016SGiridhar Malavali 1519a9083016SGiridhar Malavali switch (size) { 1520a9083016SGiridhar Malavali case 1: 1521a9083016SGiridhar Malavali *(uint8_t *)data = val; 1522a9083016SGiridhar Malavali break; 1523a9083016SGiridhar Malavali case 2: 1524a9083016SGiridhar Malavali *(uint16_t *)data = val; 1525a9083016SGiridhar Malavali break; 1526a9083016SGiridhar Malavali case 4: 1527a9083016SGiridhar Malavali *(uint32_t *)data = val; 1528a9083016SGiridhar Malavali break; 1529a9083016SGiridhar Malavali case 8: 1530a9083016SGiridhar Malavali *(uint64_t *)data = val; 1531a9083016SGiridhar Malavali break; 1532a9083016SGiridhar Malavali } 1533a9083016SGiridhar Malavali return 0; 1534a9083016SGiridhar Malavali } 1535a9083016SGiridhar Malavali 1536a9083016SGiridhar Malavali 15379c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15389c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15399c2b2975SHarish Zunjarrao { 15409c2b2975SHarish Zunjarrao uint32_t i; 15419c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15429c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15439c2b2975SHarish Zunjarrao __le32 offset; 15449c2b2975SHarish Zunjarrao __le32 tab_type; 15459c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15469c2b2975SHarish Zunjarrao 15479c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15489c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15499c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15509c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15519c2b2975SHarish Zunjarrao 15529c2b2975SHarish Zunjarrao if (tab_type == section) 15539c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15549c2b2975SHarish Zunjarrao } 15559c2b2975SHarish Zunjarrao 15569c2b2975SHarish Zunjarrao return NULL; 15579c2b2975SHarish Zunjarrao } 15589c2b2975SHarish Zunjarrao 15599c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15609c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15619c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15629c2b2975SHarish Zunjarrao { 15639c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15649c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15659c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15669c2b2975SHarish Zunjarrao __le32 offset; 15679c2b2975SHarish Zunjarrao 15689c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15699c2b2975SHarish Zunjarrao if (!tab_desc) 15709c2b2975SHarish Zunjarrao return NULL; 15719c2b2975SHarish Zunjarrao 15729c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15739c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15749c2b2975SHarish Zunjarrao 15759c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15769c2b2975SHarish Zunjarrao } 15779c2b2975SHarish Zunjarrao 15789c2b2975SHarish Zunjarrao static u8 * 15799c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15809c2b2975SHarish Zunjarrao { 15819c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15829c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15839c2b2975SHarish Zunjarrao 15849c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15859c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15869c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15879c2b2975SHarish Zunjarrao if (uri_desc) 15889c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15899c2b2975SHarish Zunjarrao } 15909c2b2975SHarish Zunjarrao 15919c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15929c2b2975SHarish Zunjarrao } 15939c2b2975SHarish Zunjarrao 15949c2b2975SHarish Zunjarrao static __le32 15959c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15969c2b2975SHarish Zunjarrao { 15979c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15989c2b2975SHarish Zunjarrao 15999c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16009c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16019c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16029c2b2975SHarish Zunjarrao if (uri_desc) 16039c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 16049c2b2975SHarish Zunjarrao } 16059c2b2975SHarish Zunjarrao 16069c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 16079c2b2975SHarish Zunjarrao } 16089c2b2975SHarish Zunjarrao 16099c2b2975SHarish Zunjarrao static u8 * 16109c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 16119c2b2975SHarish Zunjarrao { 16129c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 16139c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16149c2b2975SHarish Zunjarrao 16159c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16169c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16179c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16189c2b2975SHarish Zunjarrao if (uri_desc) 16199c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16209c2b2975SHarish Zunjarrao } 16219c2b2975SHarish Zunjarrao 16229c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16239c2b2975SHarish Zunjarrao } 16249c2b2975SHarish Zunjarrao 1625a9083016SGiridhar Malavali /* PCI related functions */ 1626a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1627a9083016SGiridhar Malavali { 1628a9083016SGiridhar Malavali unsigned long val = 0; 1629a9083016SGiridhar Malavali u32 control; 1630a9083016SGiridhar Malavali 1631a9083016SGiridhar Malavali switch (region) { 1632a9083016SGiridhar Malavali case 0: 1633a9083016SGiridhar Malavali val = 0; 1634a9083016SGiridhar Malavali break; 1635a9083016SGiridhar Malavali case 1: 1636a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1637a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1638a9083016SGiridhar Malavali break; 1639a9083016SGiridhar Malavali } 1640a9083016SGiridhar Malavali return val; 1641a9083016SGiridhar Malavali } 1642a9083016SGiridhar Malavali 1643a9083016SGiridhar Malavali 1644a9083016SGiridhar Malavali int 1645a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1646a9083016SGiridhar Malavali { 1647a9083016SGiridhar Malavali uint32_t len = 0; 1648a9083016SGiridhar Malavali 1649a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16507c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16517c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1652a9083016SGiridhar Malavali goto iospace_error_exit; 1653a9083016SGiridhar Malavali } 1654a9083016SGiridhar Malavali 1655a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1656a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16577c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16587c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1659a9083016SGiridhar Malavali goto iospace_error_exit; 1660a9083016SGiridhar Malavali } 1661a9083016SGiridhar Malavali 1662a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1663a9083016SGiridhar Malavali ha->nx_pcibase = 1664a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1665a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16667c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16677c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1668a9083016SGiridhar Malavali goto iospace_error_exit; 1669a9083016SGiridhar Malavali } 1670a9083016SGiridhar Malavali 1671a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 16727ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) { 16737ec0effdSAtul Deshmukh ha->iobase = 1674f73cb695SChad Dupuis (device_reg_t *)((uint8_t *)ha->nx_pcibase); 16757ec0effdSAtul Deshmukh } else if (IS_QLA82XX(ha)) { 16767ec0effdSAtul Deshmukh ha->iobase = 1677f73cb695SChad Dupuis (device_reg_t *)((uint8_t *)ha->nx_pcibase + 1678a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 16797ec0effdSAtul Deshmukh } 1680a9083016SGiridhar Malavali 1681a9083016SGiridhar Malavali if (!ql2xdbwr) { 1682a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1683a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1684a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1685a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16867c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16877c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1688a9083016SGiridhar Malavali goto iospace_error_exit; 1689a9083016SGiridhar Malavali } 1690a9083016SGiridhar Malavali 1691a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1692a9083016SGiridhar Malavali * door bell read and write pointer 1693a9083016SGiridhar Malavali */ 1694a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1695a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1696a9083016SGiridhar Malavali } else { 1697a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1698a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1699a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1700a9083016SGiridhar Malavali } 1701a9083016SGiridhar Malavali 1702a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1703a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 17047c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 17057c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17067c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1707d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17087c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17097c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17107c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17117c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1712d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17137c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1714a9083016SGiridhar Malavali return 0; 1715a9083016SGiridhar Malavali 1716a9083016SGiridhar Malavali iospace_error_exit: 1717a9083016SGiridhar Malavali return -ENOMEM; 1718a9083016SGiridhar Malavali } 1719a9083016SGiridhar Malavali 1720a9083016SGiridhar Malavali /* GS related functions */ 1721a9083016SGiridhar Malavali 1722a9083016SGiridhar Malavali /* Initialization related functions */ 1723a9083016SGiridhar Malavali 1724a9083016SGiridhar Malavali /** 1725a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1726a9083016SGiridhar Malavali * @ha: HA context 1727a9083016SGiridhar Malavali * 1728a9083016SGiridhar Malavali * Returns 0 on success. 1729a9083016SGiridhar Malavali */ 1730a9083016SGiridhar Malavali int 1731a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1732a9083016SGiridhar Malavali { 1733a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1734a9083016SGiridhar Malavali int ret; 1735a9083016SGiridhar Malavali 1736a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1737a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1738a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17397c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 174052c82823SBart Van Assche "Chip revision:%d; pci_set_mwi() returned %d.\n", 174152c82823SBart Van Assche ha->chip_revision, ret); 1742a9083016SGiridhar Malavali return 0; 1743a9083016SGiridhar Malavali } 1744a9083016SGiridhar Malavali 1745a9083016SGiridhar Malavali /** 1746a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1747a9083016SGiridhar Malavali * @ha: HA context 1748a9083016SGiridhar Malavali * 1749a9083016SGiridhar Malavali * Returns 0 on success. 1750a9083016SGiridhar Malavali */ 1751a9083016SGiridhar Malavali void 1752a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1753a9083016SGiridhar Malavali { 1754a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1755a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1756a9083016SGiridhar Malavali } 1757a9083016SGiridhar Malavali 1758a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1759a9083016SGiridhar Malavali { 1760a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1761a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1762a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1763a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1764a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1765a9083016SGiridhar Malavali 1766a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1767a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1768ad950360SBart Van Assche icb->request_q_outpointer = cpu_to_le16(0); 1769ad950360SBart Van Assche icb->response_q_inpointer = cpu_to_le16(0); 1770a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1771a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1772a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1773a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1774a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1775a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1776a9083016SGiridhar Malavali 1777a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1778a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1779a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1780a9083016SGiridhar Malavali } 1781a9083016SGiridhar Malavali 178277e334d2SGiridhar Malavali static int 178377e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1784a9083016SGiridhar Malavali { 1785a9083016SGiridhar Malavali u64 *ptr64; 1786a9083016SGiridhar Malavali u32 i, flashaddr, size; 1787a9083016SGiridhar Malavali __le64 data; 1788a9083016SGiridhar Malavali 1789a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1790a9083016SGiridhar Malavali 17919c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1792a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1793a9083016SGiridhar Malavali 1794a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1795a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17969c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17979c2b2975SHarish Zunjarrao return -EIO; 1798a9083016SGiridhar Malavali flashaddr += 8; 1799a9083016SGiridhar Malavali } 1800a9083016SGiridhar Malavali 1801a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18029c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18039c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1804a9083016SGiridhar Malavali 1805a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1806a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1807a9083016SGiridhar Malavali 1808a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1809a9083016SGiridhar Malavali return -EIO; 1810a9083016SGiridhar Malavali flashaddr += 8; 1811a9083016SGiridhar Malavali } 18129c2b2975SHarish Zunjarrao udelay(100); 1813a9083016SGiridhar Malavali 1814a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1815a9083016SGiridhar Malavali * at a specified offset to indicate 1816a9083016SGiridhar Malavali * that all data is written and 1817a9083016SGiridhar Malavali * ready for firmware to initialize. 1818a9083016SGiridhar Malavali */ 18199c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1820a9083016SGiridhar Malavali 18219c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1822a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1823a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18249c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18259c2b2975SHarish Zunjarrao return 0; 18269c2b2975SHarish Zunjarrao } 18279c2b2975SHarish Zunjarrao 18289c2b2975SHarish Zunjarrao static int 18299c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18309c2b2975SHarish Zunjarrao { 18319c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18329c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18339c2b2975SHarish Zunjarrao uint32_t i; 18349c2b2975SHarish Zunjarrao __le32 entries; 18359c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18369c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18379c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18389c2b2975SHarish Zunjarrao int mn_present = 0; 18399c2b2975SHarish Zunjarrao uint32_t flagbit; 18409c2b2975SHarish Zunjarrao 18419c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18429c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18439c2b2975SHarish Zunjarrao if (!ptab_desc) 18449c2b2975SHarish Zunjarrao return -1; 18459c2b2975SHarish Zunjarrao 18469c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18479c2b2975SHarish Zunjarrao 18489c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18499c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18509c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18519c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18529c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18539c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18549c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18559c2b2975SHarish Zunjarrao 18569c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18579c2b2975SHarish Zunjarrao 18589c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18599c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18609c2b2975SHarish Zunjarrao return 0; 18619c2b2975SHarish Zunjarrao } 18629c2b2975SHarish Zunjarrao } 18639c2b2975SHarish Zunjarrao return -1; 18649c2b2975SHarish Zunjarrao } 18659c2b2975SHarish Zunjarrao 1866fa492630SSaurav Kashyap static int 18679c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18689c2b2975SHarish Zunjarrao { 18699c2b2975SHarish Zunjarrao __le32 val; 18709c2b2975SHarish Zunjarrao uint32_t min_size; 18719c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18729c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18739c2b2975SHarish Zunjarrao 18749c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18759c2b2975SHarish Zunjarrao 18769c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18779c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18789c2b2975SHarish Zunjarrao return -EINVAL; 18799c2b2975SHarish Zunjarrao 18809c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18819c2b2975SHarish Zunjarrao } else { 18829c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18839c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18849c2b2975SHarish Zunjarrao return -EINVAL; 18859c2b2975SHarish Zunjarrao 18869c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18879c2b2975SHarish Zunjarrao } 18889c2b2975SHarish Zunjarrao 18899c2b2975SHarish Zunjarrao if (fw->size < min_size) 18909c2b2975SHarish Zunjarrao return -EINVAL; 1891a9083016SGiridhar Malavali return 0; 1892a9083016SGiridhar Malavali } 1893a9083016SGiridhar Malavali 189477e334d2SGiridhar Malavali static int 189577e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1896a9083016SGiridhar Malavali { 1897a9083016SGiridhar Malavali u32 val = 0; 1898a9083016SGiridhar Malavali int retries = 60; 18997c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1900a9083016SGiridhar Malavali 1901a9083016SGiridhar Malavali do { 1902a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1903a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1904a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1905a9083016SGiridhar Malavali 1906a9083016SGiridhar Malavali switch (val) { 1907a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1908a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1909a9083016SGiridhar Malavali return QLA_SUCCESS; 1910a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1911a9083016SGiridhar Malavali break; 1912a9083016SGiridhar Malavali default: 1913a9083016SGiridhar Malavali break; 1914a9083016SGiridhar Malavali } 19157c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19167c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1917a9083016SGiridhar Malavali val, retries); 1918a9083016SGiridhar Malavali 1919a9083016SGiridhar Malavali msleep(500); 1920a9083016SGiridhar Malavali 1921a9083016SGiridhar Malavali } while (--retries); 1922a9083016SGiridhar Malavali 19237c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1924a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1925a9083016SGiridhar Malavali 1926a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1927a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1928a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1929a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1930a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1931a9083016SGiridhar Malavali } 1932a9083016SGiridhar Malavali 193377e334d2SGiridhar Malavali static int 193477e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1935a9083016SGiridhar Malavali { 1936a9083016SGiridhar Malavali u32 val = 0; 1937a9083016SGiridhar Malavali int retries = 60; 19387c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1939a9083016SGiridhar Malavali 1940a9083016SGiridhar Malavali do { 1941a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1942a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1943a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1944a9083016SGiridhar Malavali 1945a9083016SGiridhar Malavali switch (val) { 1946a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1947a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1948a9083016SGiridhar Malavali return QLA_SUCCESS; 1949a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1950a9083016SGiridhar Malavali break; 1951a9083016SGiridhar Malavali default: 1952a9083016SGiridhar Malavali break; 1953a9083016SGiridhar Malavali } 19547c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19557c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1956a9083016SGiridhar Malavali val, retries); 1957a9083016SGiridhar Malavali 1958a9083016SGiridhar Malavali msleep(500); 1959a9083016SGiridhar Malavali 1960a9083016SGiridhar Malavali } while (--retries); 1961a9083016SGiridhar Malavali 19627c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19637c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1964a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1965a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1966a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1967a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1968a9083016SGiridhar Malavali } 1969a9083016SGiridhar Malavali 1970a9083016SGiridhar Malavali /* ISR related functions */ 1971a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1972a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1973a9083016SGiridhar Malavali 1974a9083016SGiridhar Malavali /* 1975a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1976a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1977a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1978a9083016SGiridhar Malavali */ 19797ec0effdSAtul Deshmukh void 1980a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1981a9083016SGiridhar Malavali { 1982a9083016SGiridhar Malavali uint16_t cnt; 1983a9083016SGiridhar Malavali uint16_t __iomem *wptr; 1984a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1985a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1986a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1987a9083016SGiridhar Malavali 1988a9083016SGiridhar Malavali /* Load return mailbox registers. */ 1989a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 1990a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 1991a9083016SGiridhar Malavali 1992a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1993a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1994a9083016SGiridhar Malavali wptr++; 1995a9083016SGiridhar Malavali } 1996a9083016SGiridhar Malavali 1997cfb0919cSChad Dupuis if (!ha->mcp) 19987c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 19997c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 2000a9083016SGiridhar Malavali } 2001a9083016SGiridhar Malavali 2002a9083016SGiridhar Malavali /* 2003a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2004a9083016SGiridhar Malavali * @irq: 2005a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2006a9083016SGiridhar Malavali * @regs: 2007a9083016SGiridhar Malavali * 2008a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2009a9083016SGiridhar Malavali * 2010a9083016SGiridhar Malavali * Returns handled flag. 2011a9083016SGiridhar Malavali */ 2012a9083016SGiridhar Malavali irqreturn_t 2013a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2014a9083016SGiridhar Malavali { 2015a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2016a9083016SGiridhar Malavali struct qla_hw_data *ha; 2017a9083016SGiridhar Malavali struct rsp_que *rsp; 2018a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2019a9083016SGiridhar Malavali int status = 0, status1 = 0; 2020a9083016SGiridhar Malavali unsigned long flags; 2021a9083016SGiridhar Malavali unsigned long iter; 20227c3df132SSaurav Kashyap uint32_t stat = 0; 2023a9083016SGiridhar Malavali uint16_t mb[4]; 2024a9083016SGiridhar Malavali 2025a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2026a9083016SGiridhar Malavali if (!rsp) { 2027b6d0d9d5SGiridhar Malavali ql_log(ql_log_info, NULL, 0xb053, 20283256b435SChad Dupuis "%s: NULL response queue pointer.\n", __func__); 2029a9083016SGiridhar Malavali return IRQ_NONE; 2030a9083016SGiridhar Malavali } 2031a9083016SGiridhar Malavali ha = rsp->hw; 2032a9083016SGiridhar Malavali 2033a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2034a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2035a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2036a9083016SGiridhar Malavali return IRQ_NONE; 2037a9083016SGiridhar Malavali 2038a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2039a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2040a9083016SGiridhar Malavali return IRQ_NONE; 2041a9083016SGiridhar Malavali } 2042a9083016SGiridhar Malavali 2043a9083016SGiridhar Malavali /* clear the interrupt */ 2044a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2045a9083016SGiridhar Malavali 2046a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2047a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2048a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2049a9083016SGiridhar Malavali 2050a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2051a9083016SGiridhar Malavali 2052a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2053a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2054a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2055a9083016SGiridhar Malavali 2056a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2057a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2058a9083016SGiridhar Malavali 2059a9083016SGiridhar Malavali switch (stat & 0xff) { 2060a9083016SGiridhar Malavali case 0x1: 2061a9083016SGiridhar Malavali case 0x2: 2062a9083016SGiridhar Malavali case 0x10: 2063a9083016SGiridhar Malavali case 0x11: 2064a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2065a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2066a9083016SGiridhar Malavali break; 2067a9083016SGiridhar Malavali case 0x12: 2068a9083016SGiridhar Malavali mb[0] = MSW(stat); 2069a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2070a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2071a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2072a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2073a9083016SGiridhar Malavali break; 2074a9083016SGiridhar Malavali case 0x13: 2075a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2076a9083016SGiridhar Malavali break; 2077a9083016SGiridhar Malavali default: 20787c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2079a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20807c3df132SSaurav Kashyap stat & 0xff); 2081a9083016SGiridhar Malavali break; 2082a9083016SGiridhar Malavali } 2083a9083016SGiridhar Malavali } 2084a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2085a9083016SGiridhar Malavali } 2086a9083016SGiridhar Malavali 208736439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 208836439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 208936439832Sgurinder.shergill@hp.com 209036439832Sgurinder.shergill@hp.com if (!ha->flags.msi_enabled) 209136439832Sgurinder.shergill@hp.com qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 209236439832Sgurinder.shergill@hp.com 2093a9083016SGiridhar Malavali return IRQ_HANDLED; 2094a9083016SGiridhar Malavali } 2095a9083016SGiridhar Malavali 2096a9083016SGiridhar Malavali irqreturn_t 2097a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2098a9083016SGiridhar Malavali { 2099a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2100a9083016SGiridhar Malavali struct qla_hw_data *ha; 2101a9083016SGiridhar Malavali struct rsp_que *rsp; 2102a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2103a9083016SGiridhar Malavali int status = 0; 2104a9083016SGiridhar Malavali unsigned long flags; 21057c3df132SSaurav Kashyap uint32_t stat = 0; 2106f3ddac19SChad Dupuis uint32_t host_int = 0; 2107a9083016SGiridhar Malavali uint16_t mb[4]; 2108a9083016SGiridhar Malavali 2109a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2110a9083016SGiridhar Malavali if (!rsp) { 2111a9083016SGiridhar Malavali printk(KERN_INFO 21127c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2113a9083016SGiridhar Malavali return IRQ_NONE; 2114a9083016SGiridhar Malavali } 2115a9083016SGiridhar Malavali ha = rsp->hw; 2116a9083016SGiridhar Malavali 2117a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2118a9083016SGiridhar Malavali 2119a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2120a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2121a9083016SGiridhar Malavali do { 2122f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2123c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2124f3ddac19SChad Dupuis break; 2125f3ddac19SChad Dupuis if (host_int) { 2126a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2127a9083016SGiridhar Malavali 2128a9083016SGiridhar Malavali switch (stat & 0xff) { 2129a9083016SGiridhar Malavali case 0x1: 2130a9083016SGiridhar Malavali case 0x2: 2131a9083016SGiridhar Malavali case 0x10: 2132a9083016SGiridhar Malavali case 0x11: 2133a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2134a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2135a9083016SGiridhar Malavali break; 2136a9083016SGiridhar Malavali case 0x12: 2137a9083016SGiridhar Malavali mb[0] = MSW(stat); 2138a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2139a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2140a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2141a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2142a9083016SGiridhar Malavali break; 2143a9083016SGiridhar Malavali case 0x13: 2144a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2145a9083016SGiridhar Malavali break; 2146a9083016SGiridhar Malavali default: 21477c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2148a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21497c3df132SSaurav Kashyap stat & 0xff); 2150a9083016SGiridhar Malavali break; 2151a9083016SGiridhar Malavali } 2152a9083016SGiridhar Malavali } 2153a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2154a9083016SGiridhar Malavali } while (0); 2155a9083016SGiridhar Malavali 215636439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 215736439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 215836439832Sgurinder.shergill@hp.com 2159a9083016SGiridhar Malavali return IRQ_HANDLED; 2160a9083016SGiridhar Malavali } 2161a9083016SGiridhar Malavali 2162a9083016SGiridhar Malavali irqreturn_t 2163a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2164a9083016SGiridhar Malavali { 2165a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2166a9083016SGiridhar Malavali struct qla_hw_data *ha; 2167a9083016SGiridhar Malavali struct rsp_que *rsp; 2168a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 21693553d343SSaurav Kashyap unsigned long flags; 2170f3ddac19SChad Dupuis uint32_t host_int = 0; 2171a9083016SGiridhar Malavali 2172a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2173a9083016SGiridhar Malavali if (!rsp) { 2174a9083016SGiridhar Malavali printk(KERN_INFO 21757c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2176a9083016SGiridhar Malavali return IRQ_NONE; 2177a9083016SGiridhar Malavali } 2178a9083016SGiridhar Malavali 2179a9083016SGiridhar Malavali ha = rsp->hw; 2180a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 21813553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2182a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2183f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2184c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2185f3ddac19SChad Dupuis goto out; 2186a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2187a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2188f3ddac19SChad Dupuis out: 21893553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2190a9083016SGiridhar Malavali return IRQ_HANDLED; 2191a9083016SGiridhar Malavali } 2192a9083016SGiridhar Malavali 2193a9083016SGiridhar Malavali void 2194a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2195a9083016SGiridhar Malavali { 2196a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2197a9083016SGiridhar Malavali struct qla_hw_data *ha; 2198a9083016SGiridhar Malavali struct rsp_que *rsp; 2199a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2200a9083016SGiridhar Malavali int status = 0; 2201a9083016SGiridhar Malavali uint32_t stat; 2202f3ddac19SChad Dupuis uint32_t host_int = 0; 2203a9083016SGiridhar Malavali uint16_t mb[4]; 2204a9083016SGiridhar Malavali unsigned long flags; 2205a9083016SGiridhar Malavali 2206a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2207a9083016SGiridhar Malavali if (!rsp) { 2208a9083016SGiridhar Malavali printk(KERN_INFO 22097c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2210a9083016SGiridhar Malavali return; 2211a9083016SGiridhar Malavali } 2212a9083016SGiridhar Malavali ha = rsp->hw; 2213a9083016SGiridhar Malavali 2214a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2215a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2216a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2217a9083016SGiridhar Malavali 2218f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2219c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2220f3ddac19SChad Dupuis goto out; 2221f3ddac19SChad Dupuis if (host_int) { 2222a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2223a9083016SGiridhar Malavali switch (stat & 0xff) { 2224a9083016SGiridhar Malavali case 0x1: 2225a9083016SGiridhar Malavali case 0x2: 2226a9083016SGiridhar Malavali case 0x10: 2227a9083016SGiridhar Malavali case 0x11: 2228a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2229a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2230a9083016SGiridhar Malavali break; 2231a9083016SGiridhar Malavali case 0x12: 2232a9083016SGiridhar Malavali mb[0] = MSW(stat); 2233a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2234a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2235a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2236a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2237a9083016SGiridhar Malavali break; 2238a9083016SGiridhar Malavali case 0x13: 2239a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2240a9083016SGiridhar Malavali break; 2241a9083016SGiridhar Malavali default: 22427c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22437c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22447c3df132SSaurav Kashyap stat * 0xff); 2245a9083016SGiridhar Malavali break; 2246a9083016SGiridhar Malavali } 2247a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 224802a9ae6eSAtul Deshmukh } 2249f3ddac19SChad Dupuis out: 2250a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2251a9083016SGiridhar Malavali } 2252a9083016SGiridhar Malavali 2253a9083016SGiridhar Malavali void 2254a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2255a9083016SGiridhar Malavali { 2256a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2257a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2258a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22597ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22607ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 22617ec0effdSAtul Deshmukh else 2262a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2263a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2264a9083016SGiridhar Malavali ha->interrupts_on = 1; 2265a9083016SGiridhar Malavali } 2266a9083016SGiridhar Malavali 2267a9083016SGiridhar Malavali void 2268a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2269a9083016SGiridhar Malavali { 2270a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2271a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2272a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22737ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22747ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 22757ec0effdSAtul Deshmukh else 2276a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2277a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2278a9083016SGiridhar Malavali ha->interrupts_on = 0; 2279a9083016SGiridhar Malavali } 2280a9083016SGiridhar Malavali 2281a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2282a9083016SGiridhar Malavali { 2283a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2284a9083016SGiridhar Malavali 2285a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2286a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2287a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2288a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2289a9083016SGiridhar Malavali ha->curr_window = 255; 2290a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2291a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2292a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2293a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2294a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2295a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2296a9083016SGiridhar Malavali } 2297a9083016SGiridhar Malavali 22982374dd23SBart Van Assche static inline void 22990251ce8cSSaurav Kashyap qla82xx_set_idc_version(scsi_qla_host_t *vha) 23000251ce8cSSaurav Kashyap { 23010251ce8cSSaurav Kashyap int idc_ver; 23020251ce8cSSaurav Kashyap uint32_t drv_active; 23030251ce8cSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 23040251ce8cSSaurav Kashyap 23050251ce8cSSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 23060251ce8cSSaurav Kashyap if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 23070251ce8cSSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 23080251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION); 23090251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb082, 23100251ce8cSSaurav Kashyap "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 23110251ce8cSSaurav Kashyap } else { 23120251ce8cSSaurav Kashyap idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 23130251ce8cSSaurav Kashyap if (idc_ver != QLA82XX_IDC_VERSION) 23140251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb083, 23150251ce8cSSaurav Kashyap "qla2xxx driver IDC version %d is not compatible " 23160251ce8cSSaurav Kashyap "with IDC version %d of the other drivers\n", 23170251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION, idc_ver); 23180251ce8cSSaurav Kashyap } 23190251ce8cSSaurav Kashyap } 23200251ce8cSSaurav Kashyap 23210251ce8cSSaurav Kashyap inline void 2322a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2323a9083016SGiridhar Malavali { 2324a9083016SGiridhar Malavali uint32_t drv_active; 2325a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2326a9083016SGiridhar Malavali 2327a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2328a9083016SGiridhar Malavali 2329a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2330a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 233177e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 233277e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2333a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2334a9083016SGiridhar Malavali } 233577e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2336a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2337a9083016SGiridhar Malavali } 2338a9083016SGiridhar Malavali 2339a9083016SGiridhar Malavali inline void 2340a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2341a9083016SGiridhar Malavali { 2342a9083016SGiridhar Malavali uint32_t drv_active; 2343a9083016SGiridhar Malavali 2344a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 234577e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2346a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2347a9083016SGiridhar Malavali } 2348a9083016SGiridhar Malavali 2349a9083016SGiridhar Malavali static inline int 2350a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2351a9083016SGiridhar Malavali { 2352a9083016SGiridhar Malavali uint32_t drv_state; 2353a9083016SGiridhar Malavali int rval; 2354a9083016SGiridhar Malavali 23557d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 235608de2844SGiridhar Malavali return 1; 235708de2844SGiridhar Malavali else { 2358a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 235977e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2360a9083016SGiridhar Malavali return rval; 2361a9083016SGiridhar Malavali } 236208de2844SGiridhar Malavali } 2363a9083016SGiridhar Malavali 2364a9083016SGiridhar Malavali static inline void 2365a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2366a9083016SGiridhar Malavali { 2367a9083016SGiridhar Malavali uint32_t drv_state; 2368a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2369a9083016SGiridhar Malavali 2370a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2371a9083016SGiridhar Malavali 2372a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2373a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 237477e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2375a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2376a9083016SGiridhar Malavali } 2377a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 237808de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 237908de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2380a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2381a9083016SGiridhar Malavali } 2382a9083016SGiridhar Malavali 2383a9083016SGiridhar Malavali static inline void 2384a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2385a9083016SGiridhar Malavali { 2386a9083016SGiridhar Malavali uint32_t drv_state; 2387a9083016SGiridhar Malavali 2388a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2389a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2390a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2391a9083016SGiridhar Malavali } 2392a9083016SGiridhar Malavali 2393a9083016SGiridhar Malavali static inline void 2394a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2395a9083016SGiridhar Malavali { 2396a9083016SGiridhar Malavali uint32_t qsnt_state; 2397a9083016SGiridhar Malavali 2398a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2399a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2400a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2401a9083016SGiridhar Malavali } 2402a9083016SGiridhar Malavali 2403579d12b5SSaurav Kashyap void 2404579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2405579d12b5SSaurav Kashyap { 2406579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2407579d12b5SSaurav Kashyap uint32_t qsnt_state; 2408579d12b5SSaurav Kashyap 2409579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2410579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2411579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2412579d12b5SSaurav Kashyap } 2413579d12b5SSaurav Kashyap 241477e334d2SGiridhar Malavali static int 241577e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2416a9083016SGiridhar Malavali { 2417a9083016SGiridhar Malavali int rst; 2418a9083016SGiridhar Malavali struct fw_blob *blob; 2419a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2420a9083016SGiridhar Malavali 2421a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24227c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24237c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2424a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2425a9083016SGiridhar Malavali } 2426a9083016SGiridhar Malavali udelay(500); 2427a9083016SGiridhar Malavali 2428a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2429a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2430a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2431a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2432a9083016SGiridhar Malavali 2433a9083016SGiridhar Malavali /* 2434a9083016SGiridhar Malavali * FW Load priority: 2435a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2436a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2437a9083016SGiridhar Malavali */ 2438a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2439a9083016SGiridhar Malavali goto try_blob_fw; 2440a9083016SGiridhar Malavali 24417c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24427c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2443a9083016SGiridhar Malavali 2444a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24457c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 244600adc9a0SSaurav Kashyap "Firmware loaded successfully from flash.\n"); 2447a9083016SGiridhar Malavali return QLA_SUCCESS; 2448875efad7SChad Dupuis } else { 24497c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24507c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2451a9083016SGiridhar Malavali } 2452875efad7SChad Dupuis 2453a9083016SGiridhar Malavali try_blob_fw: 24547c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24557c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2456a9083016SGiridhar Malavali 2457a9083016SGiridhar Malavali /* Load firmware blob. */ 2458a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2459a9083016SGiridhar Malavali if (!blob) { 24607c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 246100adc9a0SSaurav Kashyap "Firmware image not present.\n"); 2462a9083016SGiridhar Malavali goto fw_load_failed; 2463a9083016SGiridhar Malavali } 2464a9083016SGiridhar Malavali 24659c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24669c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24679c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24689c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24699c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24709c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24717c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24727c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24739c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24749c2b2975SHarish Zunjarrao } 24759c2b2975SHarish Zunjarrao } 24769c2b2975SHarish Zunjarrao 2477a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24787c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24797c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2480a9083016SGiridhar Malavali return QLA_SUCCESS; 2481a9083016SGiridhar Malavali } else { 24827c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24837c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2484a9083016SGiridhar Malavali blob->fw = NULL; 2485a9083016SGiridhar Malavali blob = NULL; 2486a9083016SGiridhar Malavali goto fw_load_failed; 2487a9083016SGiridhar Malavali } 2488a9083016SGiridhar Malavali return QLA_SUCCESS; 2489a9083016SGiridhar Malavali 2490a9083016SGiridhar Malavali fw_load_failed: 2491a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2492a9083016SGiridhar Malavali } 2493a9083016SGiridhar Malavali 2494a5b36321SLalit Chandivade int 2495a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2496a9083016SGiridhar Malavali { 2497a9083016SGiridhar Malavali uint16_t lnk; 2498a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2499a9083016SGiridhar Malavali 2500a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 250177e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2502a9083016SGiridhar Malavali 25033711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 25043711333dSGiridhar Malavali * of 0 before resetting the hardware 25053711333dSGiridhar Malavali */ 25063711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25073711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25083711333dSGiridhar Malavali 2509a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2510a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2511a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2512a9083016SGiridhar Malavali 2513a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25147c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25157c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2516a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2517a9083016SGiridhar Malavali } 2518a9083016SGiridhar Malavali 2519a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2520a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25227c3df132SSaurav Kashyap "Error during card handshake.\n"); 2523a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2524a9083016SGiridhar Malavali } 2525a9083016SGiridhar Malavali 2526a9083016SGiridhar Malavali /* Negotiated Link width */ 252710092438SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2528a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2529a9083016SGiridhar Malavali 2530a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2531a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2532a9083016SGiridhar Malavali } 2533a9083016SGiridhar Malavali 253477e334d2SGiridhar Malavali static uint32_t * 2535a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2536a9083016SGiridhar Malavali uint32_t length) 2537a9083016SGiridhar Malavali { 2538a9083016SGiridhar Malavali uint32_t i; 2539a9083016SGiridhar Malavali uint32_t val; 2540a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2541a9083016SGiridhar Malavali 2542a9083016SGiridhar Malavali /* Dword reads to flash. */ 2543a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2544a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25457c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25467c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2547a9083016SGiridhar Malavali goto done_read; 2548a9083016SGiridhar Malavali } 2549ad950360SBart Van Assche dwptr[i] = cpu_to_le32(val); 2550a9083016SGiridhar Malavali } 2551a9083016SGiridhar Malavali done_read: 2552a9083016SGiridhar Malavali return dwptr; 2553a9083016SGiridhar Malavali } 2554a9083016SGiridhar Malavali 255577e334d2SGiridhar Malavali static int 2556a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2557a9083016SGiridhar Malavali { 2558a9083016SGiridhar Malavali int ret; 2559a9083016SGiridhar Malavali uint32_t val; 25607c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2561a9083016SGiridhar Malavali 2562a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2563a9083016SGiridhar Malavali if (ret < 0) { 25647c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25657c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2566a9083016SGiridhar Malavali return ret; 2567a9083016SGiridhar Malavali } 2568a9083016SGiridhar Malavali 2569a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2570a9083016SGiridhar Malavali if (ret < 0) 2571a9083016SGiridhar Malavali goto done_unprotect; 2572a9083016SGiridhar Malavali 25730547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2574a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2575a9083016SGiridhar Malavali if (ret < 0) { 25760547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2577a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2578a9083016SGiridhar Malavali } 2579a9083016SGiridhar Malavali 2580a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 25827c3df132SSaurav Kashyap "Write disable failed.\n"); 2583a9083016SGiridhar Malavali 2584a9083016SGiridhar Malavali done_unprotect: 2585d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2586a9083016SGiridhar Malavali return ret; 2587a9083016SGiridhar Malavali } 2588a9083016SGiridhar Malavali 258977e334d2SGiridhar Malavali static int 2590a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2591a9083016SGiridhar Malavali { 2592a9083016SGiridhar Malavali int ret; 2593a9083016SGiridhar Malavali uint32_t val; 25947c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2595a9083016SGiridhar Malavali 2596a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2597a9083016SGiridhar Malavali if (ret < 0) { 25987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 25997c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2600a9083016SGiridhar Malavali return ret; 2601a9083016SGiridhar Malavali } 2602a9083016SGiridhar Malavali 2603a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2604a9083016SGiridhar Malavali if (ret < 0) 2605a9083016SGiridhar Malavali goto done_protect; 2606a9083016SGiridhar Malavali 26070547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2608a9083016SGiridhar Malavali /* LOCK all sectors */ 2609a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2610a9083016SGiridhar Malavali if (ret < 0) 26117c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 26127c3df132SSaurav Kashyap "Write status register failed.\n"); 2613a9083016SGiridhar Malavali 2614a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 26157c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 26167c3df132SSaurav Kashyap "Write disable failed.\n"); 2617a9083016SGiridhar Malavali done_protect: 2618d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2619a9083016SGiridhar Malavali return ret; 2620a9083016SGiridhar Malavali } 2621a9083016SGiridhar Malavali 262277e334d2SGiridhar Malavali static int 2623a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2624a9083016SGiridhar Malavali { 2625a9083016SGiridhar Malavali int ret = 0; 26267c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2627a9083016SGiridhar Malavali 2628a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2629a9083016SGiridhar Malavali if (ret < 0) { 26307c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26317c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2632a9083016SGiridhar Malavali return ret; 2633a9083016SGiridhar Malavali } 2634a9083016SGiridhar Malavali 2635a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2636a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2637a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2638a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2639a9083016SGiridhar Malavali 2640a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26417c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26427c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2643a9083016SGiridhar Malavali ret = -1; 2644a9083016SGiridhar Malavali goto done; 2645a9083016SGiridhar Malavali } 2646a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2647a9083016SGiridhar Malavali done: 2648d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2649a9083016SGiridhar Malavali return ret; 2650a9083016SGiridhar Malavali } 2651a9083016SGiridhar Malavali 2652a9083016SGiridhar Malavali /* 2653a9083016SGiridhar Malavali * Address and length are byte address 2654a9083016SGiridhar Malavali */ 2655a9083016SGiridhar Malavali uint8_t * 2656a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2657a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2658a9083016SGiridhar Malavali { 2659a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2660a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2661a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2662a9083016SGiridhar Malavali return buf; 2663a9083016SGiridhar Malavali } 2664a9083016SGiridhar Malavali 2665a9083016SGiridhar Malavali static int 2666a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2667a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2668a9083016SGiridhar Malavali { 2669a9083016SGiridhar Malavali int ret; 2670a9083016SGiridhar Malavali uint32_t liter; 267152c82823SBart Van Assche uint32_t rest_addr; 2672a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2673a9083016SGiridhar Malavali void *optrom = NULL; 2674a9083016SGiridhar Malavali int page_mode = 0; 2675a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2676a9083016SGiridhar Malavali 2677a9083016SGiridhar Malavali ret = -1; 2678a9083016SGiridhar Malavali 2679a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2680a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2681a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2682a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2683a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2684a9083016SGiridhar Malavali if (!optrom) { 26857c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 26867c3df132SSaurav Kashyap "Unable to allocate memory " 268700adc9a0SSaurav Kashyap "for optrom burst write (%x KB).\n", 2688a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2689a9083016SGiridhar Malavali } 2690a9083016SGiridhar Malavali } 2691a9083016SGiridhar Malavali 2692a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2693a9083016SGiridhar Malavali 2694a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2695a9083016SGiridhar Malavali if (ret) { 26967c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2697a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2698a9083016SGiridhar Malavali goto write_done; 2699a9083016SGiridhar Malavali } 2700a9083016SGiridhar Malavali 2701a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2702a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2703a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2704a9083016SGiridhar Malavali 2705a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2706a9083016SGiridhar Malavali if (ret) { 27077c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 27087c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 27097c3df132SSaurav Kashyap faddr); 2710a9083016SGiridhar Malavali break; 2711a9083016SGiridhar Malavali } 2712a9083016SGiridhar Malavali } 2713a9083016SGiridhar Malavali 2714a9083016SGiridhar Malavali /* Go with burst-write. */ 2715a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2716a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2717a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2718a9083016SGiridhar Malavali 2719a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2720a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2721a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2722a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 27237c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2724a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2725a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2726a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2727a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2729a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2730a9083016SGiridhar Malavali 2731a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2732a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2733a9083016SGiridhar Malavali optrom = NULL; 2734a9083016SGiridhar Malavali } else { 2735a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2736a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2737a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2738a9083016SGiridhar Malavali continue; 2739a9083016SGiridhar Malavali } 2740a9083016SGiridhar Malavali } 2741a9083016SGiridhar Malavali 2742a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 2743a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 2744a9083016SGiridhar Malavali if (ret) { 27457c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27467c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27477c3df132SSaurav Kashyap faddr, *dwptr); 2748a9083016SGiridhar Malavali break; 2749a9083016SGiridhar Malavali } 2750a9083016SGiridhar Malavali } 2751a9083016SGiridhar Malavali 2752a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2753a9083016SGiridhar Malavali if (ret) 27547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2755a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2756a9083016SGiridhar Malavali write_done: 2757a9083016SGiridhar Malavali if (optrom) 2758a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2759a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2760a9083016SGiridhar Malavali return ret; 2761a9083016SGiridhar Malavali } 2762a9083016SGiridhar Malavali 2763a9083016SGiridhar Malavali int 2764a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2765a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2766a9083016SGiridhar Malavali { 2767a9083016SGiridhar Malavali int rval; 2768a9083016SGiridhar Malavali 2769a9083016SGiridhar Malavali /* Suspend HBA. */ 2770a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2771a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2772a9083016SGiridhar Malavali length >> 2); 2773a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2774a9083016SGiridhar Malavali 2775a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2776a9083016SGiridhar Malavali if (rval) 2777a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2778a9083016SGiridhar Malavali else 2779a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2780a9083016SGiridhar Malavali return rval; 2781a9083016SGiridhar Malavali } 2782a9083016SGiridhar Malavali 2783a9083016SGiridhar Malavali void 27845162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2785a9083016SGiridhar Malavali { 27865162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2787a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2788a9083016SGiridhar Malavali uint32_t dbval; 2789a9083016SGiridhar Malavali 2790a9083016SGiridhar Malavali /* Adjust ring index. */ 2791a9083016SGiridhar Malavali req->ring_index++; 2792a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2793a9083016SGiridhar Malavali req->ring_index = 0; 2794a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2795a9083016SGiridhar Malavali } else 2796a9083016SGiridhar Malavali req->ring_ptr++; 2797a9083016SGiridhar Malavali 2798a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2799a9083016SGiridhar Malavali 2800a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 28016907869dSGiridhar Malavali if (ql2xdbwr) 28026907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 28036907869dSGiridhar Malavali else { 2804a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2805a9083016SGiridhar Malavali wmb(); 2806fa492630SSaurav Kashyap while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 28076907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 28086907869dSGiridhar Malavali dbval); 2809a9083016SGiridhar Malavali wmb(); 2810a9083016SGiridhar Malavali } 2811a9083016SGiridhar Malavali } 28126907869dSGiridhar Malavali } 2813a9083016SGiridhar Malavali 2814fa492630SSaurav Kashyap static void 2815fa492630SSaurav Kashyap qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2816e6a4202aSShyam Sundar { 28177c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 28184babb90eSHiral Patel uint32_t lock_owner = 0; 28197c3df132SSaurav Kashyap 28204babb90eSHiral Patel if (qla82xx_rom_lock(ha)) { 28214babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2822e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 28237c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 28244babb90eSHiral Patel "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 28254babb90eSHiral Patel } 2826e6a4202aSShyam Sundar /* 2827e6a4202aSShyam Sundar * Either we got the lock, or someone 2828e6a4202aSShyam Sundar * else died while holding it. 2829e6a4202aSShyam Sundar * In either case, unlock. 2830e6a4202aSShyam Sundar */ 2831d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2832e6a4202aSShyam Sundar } 2833e6a4202aSShyam Sundar 2834a9083016SGiridhar Malavali /* 2835a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2836a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2837a9083016SGiridhar Malavali * 2838a9083016SGiridhar Malavali * Note: 2839a9083016SGiridhar Malavali * IDC lock must be held upon entry 2840a9083016SGiridhar Malavali * 2841a9083016SGiridhar Malavali * Return: 2842a9083016SGiridhar Malavali * Success : 0 2843a9083016SGiridhar Malavali * Failed : 1 2844a9083016SGiridhar Malavali */ 2845a9083016SGiridhar Malavali static int 2846a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2847a9083016SGiridhar Malavali { 2848e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 284903d32f97STej Prakash int i; 2850a9083016SGiridhar Malavali uint32_t old_count, count; 2851a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 285203d32f97STej Prakash int need_reset = 0; 2853a9083016SGiridhar Malavali 2854e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2855a9083016SGiridhar Malavali 2856e6a4202aSShyam Sundar if (need_reset) { 2857e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 285803d32f97STej Prakash if (ha->flags.isp82xx_fw_hung) 2859e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2860e6a4202aSShyam Sundar } else { 286103d32f97STej Prakash old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 286203d32f97STej Prakash for (i = 0; i < 10; i++) { 286303d32f97STej Prakash msleep(200); 286403d32f97STej Prakash count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 286503d32f97STej Prakash if (count != old_count) { 286603d32f97STej Prakash rval = QLA_SUCCESS; 2867a9083016SGiridhar Malavali goto dev_ready; 2868a9083016SGiridhar Malavali } 286903d32f97STej Prakash } 287003d32f97STej Prakash qla82xx_rom_lock_recovery(ha); 287103d32f97STej Prakash } 2872a9083016SGiridhar Malavali 2873a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28747c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28757c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 28767d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2877a9083016SGiridhar Malavali 2878a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2879a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2880a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2881a9083016SGiridhar Malavali 2882a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 28837c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 28847c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2885a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 28867d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2887a9083016SGiridhar Malavali return rval; 2888a9083016SGiridhar Malavali } 2889a9083016SGiridhar Malavali 2890a9083016SGiridhar Malavali dev_ready: 28917c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 28927c3df132SSaurav Kashyap "HW State: READY.\n"); 28937d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2894a9083016SGiridhar Malavali 2895a9083016SGiridhar Malavali return QLA_SUCCESS; 2896a9083016SGiridhar Malavali } 2897a9083016SGiridhar Malavali 2898579d12b5SSaurav Kashyap /* 2899579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2900579d12b5SSaurav Kashyap * Code to start quiescence sequence 2901579d12b5SSaurav Kashyap * 2902579d12b5SSaurav Kashyap * Note: 2903579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2904579d12b5SSaurav Kashyap * 2905579d12b5SSaurav Kashyap * Return: void 2906579d12b5SSaurav Kashyap */ 2907579d12b5SSaurav Kashyap 2908579d12b5SSaurav Kashyap static void 2909579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2910579d12b5SSaurav Kashyap { 2911579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2912579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2913579d12b5SSaurav Kashyap unsigned long reset_timeout; 2914579d12b5SSaurav Kashyap 2915579d12b5SSaurav Kashyap if (vha->flags.online) { 2916579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 29178fcd6b8bSChad Dupuis qla2x00_quiesce_io(vha); 2918579d12b5SSaurav Kashyap } 2919579d12b5SSaurav Kashyap 2920579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2921579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2922579d12b5SSaurav Kashyap 2923579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2924579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2925579d12b5SSaurav Kashyap 2926579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2927579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2928579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2929579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2930579d12b5SSaurav Kashyap 2931579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2932579d12b5SSaurav Kashyap 2933579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2934579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2935579d12b5SSaurav Kashyap * changing the state to DEV_READY 2936579d12b5SSaurav Kashyap */ 29377c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29385f28d2d7SSaurav Kashyap "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 29395f28d2d7SSaurav Kashyap "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 29407c3df132SSaurav Kashyap drv_active, drv_state); 2941579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 29427d613ac6SSantosh Vernekar QLA8XXX_DEV_READY); 29437c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29447c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2945579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2946579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2947579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2948579d12b5SSaurav Kashyap 2949579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2950579d12b5SSaurav Kashyap return; 2951579d12b5SSaurav Kashyap } 2952579d12b5SSaurav Kashyap 2953579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2954579d12b5SSaurav Kashyap msleep(1000); 2955579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2956579d12b5SSaurav Kashyap 2957579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2958579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2959579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2960579d12b5SSaurav Kashyap } 2961579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2962579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 29637d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 29647c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29657c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 29667d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2967579d12b5SSaurav Kashyap } 2968579d12b5SSaurav Kashyap } 2969579d12b5SSaurav Kashyap 2970579d12b5SSaurav Kashyap /* 2971579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2972579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2973579d12b5SSaurav Kashyap * 2974579d12b5SSaurav Kashyap * Note: 2975579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2976579d12b5SSaurav Kashyap * 2977579d12b5SSaurav Kashyap * Return: 2978579d12b5SSaurav Kashyap * Changed device state. 2979579d12b5SSaurav Kashyap */ 2980579d12b5SSaurav Kashyap uint32_t 2981579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2982579d12b5SSaurav Kashyap { 2983579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2984579d12b5SSaurav Kashyap uint32_t dev_state; 2985579d12b5SSaurav Kashyap 2986579d12b5SSaurav Kashyap do { 2987579d12b5SSaurav Kashyap msleep(1000); 2988579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2989579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2990579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2991579d12b5SSaurav Kashyap } while (dev_state == curr_state); 2992579d12b5SSaurav Kashyap 2993579d12b5SSaurav Kashyap return dev_state; 2994579d12b5SSaurav Kashyap } 2995579d12b5SSaurav Kashyap 29967d613ac6SSantosh Vernekar void 29977d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2998a9083016SGiridhar Malavali { 2999a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3000a9083016SGiridhar Malavali 3001a9083016SGiridhar Malavali /* Disable the board */ 30027c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 30037c3df132SSaurav Kashyap "Disabling the board.\n"); 3004a9083016SGiridhar Malavali 30051459c0e1SSaurav Kashyap if (IS_QLA82XX(ha)) { 3006b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3007b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 30087ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) { 3009c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha); 30107ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 30111459c0e1SSaurav Kashyap } 3012b963752fSGiridhar Malavali 3013a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3014a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3015a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3016a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3017a9083016SGiridhar Malavali vha->flags.online = 0; 3018a9083016SGiridhar Malavali vha->flags.init_done = 0; 3019a9083016SGiridhar Malavali } 3020a9083016SGiridhar Malavali 3021a9083016SGiridhar Malavali /* 3022a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3023a9083016SGiridhar Malavali * Code to start reset sequence 3024a9083016SGiridhar Malavali * 3025a9083016SGiridhar Malavali * Note: 3026a9083016SGiridhar Malavali * IDC lock must be held upon entry 3027a9083016SGiridhar Malavali * 3028a9083016SGiridhar Malavali * Return: 3029a9083016SGiridhar Malavali * Success : 0 3030a9083016SGiridhar Malavali * Failed : 1 3031a9083016SGiridhar Malavali */ 3032a9083016SGiridhar Malavali static void 3033a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3034a9083016SGiridhar Malavali { 3035e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3036e5fdae55SChad Dupuis uint32_t active_mask = 0; 3037a9083016SGiridhar Malavali unsigned long reset_timeout; 3038a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3039a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3040a9083016SGiridhar Malavali 3041a9083016SGiridhar Malavali if (vha->flags.online) { 3042a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3043a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3044a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3045a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3046a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3047a9083016SGiridhar Malavali } 3048a9083016SGiridhar Malavali 304908de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30507d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_owner) { 305108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 305208de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3053a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 305408de2844SGiridhar Malavali } else { 305508de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 305608de2844SGiridhar Malavali drv_active &= active_mask; 305708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 305808de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 305908de2844SGiridhar Malavali } 3060a9083016SGiridhar Malavali 3061a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 30627d613ac6SSantosh Vernekar reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3063a9083016SGiridhar Malavali 3064a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3065a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 306608de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3067a9083016SGiridhar Malavali 306808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 306908de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 307008de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 307108de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 307208de2844SGiridhar Malavali 307308de2844SGiridhar Malavali while (drv_state != drv_active && 30747d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_INITIALIZING) { 3075a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30767c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30777c3df132SSaurav Kashyap "Reset timeout.\n"); 3078a9083016SGiridhar Malavali break; 3079a9083016SGiridhar Malavali } 3080a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3081a9083016SGiridhar Malavali msleep(1000); 3082a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3083a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3084a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30857d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 308608de2844SGiridhar Malavali drv_active &= active_mask; 308708de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3088a9083016SGiridhar Malavali } 3089a9083016SGiridhar Malavali 309008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 309108de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 309208de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 309308de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 309408de2844SGiridhar Malavali 30957c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 30967c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 30977c3df132SSaurav Kashyap dev_state, 309808de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3099f1af6208SGiridhar Malavali 3100a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 31017d613ac6SSantosh Vernekar if (dev_state != QLA8XXX_DEV_INITIALIZING && 31027d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_COLD) { 31037c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 31047c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 31057d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3106f4e1648aSVikas Chaudhary qla82xx_set_rst_ready(ha); 310708de2844SGiridhar Malavali if (ql2xmdenable) { 310808de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 310908de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 3110b6d0d9d5SGiridhar Malavali "Minidump not collected.\n"); 311108de2844SGiridhar Malavali } else 311208de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 311308de2844SGiridhar Malavali "Minidump disabled.\n"); 3114a9083016SGiridhar Malavali } 3115a9083016SGiridhar Malavali } 3116a9083016SGiridhar Malavali 31173173167fSGiridhar Malavali int 311808de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 311908de2844SGiridhar Malavali { 312008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 312108de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 31223173167fSGiridhar Malavali int rval = QLA_SUCCESS; 312308de2844SGiridhar Malavali 31243173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 31253173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 31263173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 31273173167fSGiridhar Malavali 31286246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31293173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31303173167fSGiridhar Malavali return rval; 31313173167fSGiridhar Malavali 31323173167fSGiridhar Malavali if (ql2xmdenable) { 313308de2844SGiridhar Malavali if (!ha->fw_dumped) { 3134edaa5c74SSaurav Kashyap if ((fw_major_version != ha->fw_major_version || 313508de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 3136edaa5c74SSaurav Kashyap fw_subminor_version != ha->fw_subminor_version) || 3137edaa5c74SSaurav Kashyap (ha->prev_minidump_failed)) { 31387ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3139edaa5c74SSaurav Kashyap "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 31409bc3bf27SGiridhar Malavali fw_major_version, fw_minor_version, 31419bc3bf27SGiridhar Malavali fw_subminor_version, 314208de2844SGiridhar Malavali ha->fw_major_version, 31433173167fSGiridhar Malavali ha->fw_minor_version, 3144edaa5c74SSaurav Kashyap ha->fw_subminor_version, 3145edaa5c74SSaurav Kashyap ha->prev_minidump_failed); 314608de2844SGiridhar Malavali /* Release MiniDump resources */ 314708de2844SGiridhar Malavali qla82xx_md_free(vha); 314808de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 314908de2844SGiridhar Malavali qla82xx_md_prep(vha); 31502e264269SGiridhar Malavali } 315108de2844SGiridhar Malavali } else 315208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3153d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 315408de2844SGiridhar Malavali } 31553173167fSGiridhar Malavali return rval; 31563173167fSGiridhar Malavali } 315708de2844SGiridhar Malavali 315808de2844SGiridhar Malavali 3159fa492630SSaurav Kashyap static int 3160a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3161a9083016SGiridhar Malavali { 31627190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31637190575fSGiridhar Malavali int status = 0; 3164a9083016SGiridhar Malavali 31657190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31667190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3167a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31687c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31697c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31707c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31717c3df132SSaurav Kashyap "returning status=%d.\n", status); 31727190575fSGiridhar Malavali return status; 31737c3df132SSaurav Kashyap } 3174a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3175a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3176a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3177a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3178a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31797190575fSGiridhar Malavali status = 1; 3180a9083016SGiridhar Malavali } 3181efa786ccSLalit Chandivade } else 3182efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3183a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 31847c3df132SSaurav Kashyap if (status) 31857c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 31867c3df132SSaurav Kashyap "Returning status=%d.\n", status); 31877190575fSGiridhar Malavali return status; 3188a9083016SGiridhar Malavali } 3189a9083016SGiridhar Malavali 3190a9083016SGiridhar Malavali /* 3191a9083016SGiridhar Malavali * qla82xx_device_state_handler 3192a9083016SGiridhar Malavali * Main state handler 3193a9083016SGiridhar Malavali * 3194a9083016SGiridhar Malavali * Note: 3195a9083016SGiridhar Malavali * IDC lock must be held upon entry 3196a9083016SGiridhar Malavali * 3197a9083016SGiridhar Malavali * Return: 3198a9083016SGiridhar Malavali * Success : 0 3199a9083016SGiridhar Malavali * Failed : 1 3200a9083016SGiridhar Malavali */ 3201a9083016SGiridhar Malavali int 3202a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3203a9083016SGiridhar Malavali { 3204a9083016SGiridhar Malavali uint32_t dev_state; 320592dbf273SGiridhar Malavali uint32_t old_dev_state; 3206a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3207a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3208a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 320992dbf273SGiridhar Malavali int loopcount = 0; 3210a9083016SGiridhar Malavali 3211a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 32120251ce8cSSaurav Kashyap if (!vha->flags.init_done) { 3213a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 32140251ce8cSSaurav Kashyap qla82xx_set_idc_version(vha); 32150251ce8cSSaurav Kashyap } 3216a9083016SGiridhar Malavali 3217a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 321892dbf273SGiridhar Malavali old_dev_state = dev_state; 32197c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 32207c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32217c3df132SSaurav Kashyap dev_state, 322208de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3223a9083016SGiridhar Malavali 3224a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 32257d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3226a9083016SGiridhar Malavali 3227a9083016SGiridhar Malavali while (1) { 3228a9083016SGiridhar Malavali 3229a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32307c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32317c3df132SSaurav Kashyap "Device init failed.\n"); 3232a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3233a9083016SGiridhar Malavali break; 3234a9083016SGiridhar Malavali } 3235a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 323692dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 323792dbf273SGiridhar Malavali loopcount = 0; 323892dbf273SGiridhar Malavali old_dev_state = dev_state; 323992dbf273SGiridhar Malavali } 324092dbf273SGiridhar Malavali if (loopcount < 5) { 32417c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32427c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32437c3df132SSaurav Kashyap dev_state, 324408de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32457c3df132SSaurav Kashyap "Unknown"); 324692dbf273SGiridhar Malavali } 3247f1af6208SGiridhar Malavali 3248a9083016SGiridhar Malavali switch (dev_state) { 32497d613ac6SSantosh Vernekar case QLA8XXX_DEV_READY: 32507d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 0; 32517916bb90SChad Dupuis goto rel_lock; 32527d613ac6SSantosh Vernekar case QLA8XXX_DEV_COLD: 3253a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 325408de2844SGiridhar Malavali break; 32557d613ac6SSantosh Vernekar case QLA8XXX_DEV_INITIALIZING: 3256a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3257a9083016SGiridhar Malavali msleep(1000); 3258a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3259a9083016SGiridhar Malavali break; 32607d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_RESET: 3261ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3262a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3263c8582ad9SSaurav Kashyap else { 3264c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3265c8582ad9SSaurav Kashyap msleep(1000); 3266c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3267c8582ad9SSaurav Kashyap } 32680060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32697d613ac6SSantosh Vernekar (ha->fcoe_dev_init_timeout * HZ); 3270a9083016SGiridhar Malavali break; 32717d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_QUIESCENT: 3272579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3273579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32747d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3275579d12b5SSaurav Kashyap * HZ); 3276579d12b5SSaurav Kashyap break; 32777d613ac6SSantosh Vernekar case QLA8XXX_DEV_QUIESCENT: 3278579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3279579d12b5SSaurav Kashyap * to get changed 3280579d12b5SSaurav Kashyap */ 3281579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 32827916bb90SChad Dupuis goto rel_lock; 3283579d12b5SSaurav Kashyap 3284a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3285a9083016SGiridhar Malavali msleep(1000); 3286a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3287579d12b5SSaurav Kashyap 3288579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32897d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3290579d12b5SSaurav Kashyap * HZ); 3291a9083016SGiridhar Malavali break; 32927d613ac6SSantosh Vernekar case QLA8XXX_DEV_FAILED: 32937d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(vha); 3294a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3295a9083016SGiridhar Malavali goto exit; 3296a9083016SGiridhar Malavali default: 3297a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3298a9083016SGiridhar Malavali msleep(1000); 3299a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3300a9083016SGiridhar Malavali } 330192dbf273SGiridhar Malavali loopcount++; 3302a9083016SGiridhar Malavali } 33037916bb90SChad Dupuis rel_lock: 3304a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 33057916bb90SChad Dupuis exit: 3306a9083016SGiridhar Malavali return rval; 3307a9083016SGiridhar Malavali } 3308a9083016SGiridhar Malavali 33095988aeb2SGiridhar Malavali static int qla82xx_check_temp(scsi_qla_host_t *vha) 33105988aeb2SGiridhar Malavali { 33115988aeb2SGiridhar Malavali uint32_t temp, temp_state, temp_val; 33125988aeb2SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 33135988aeb2SGiridhar Malavali 33145988aeb2SGiridhar Malavali temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 33155988aeb2SGiridhar Malavali temp_state = qla82xx_get_temp_state(temp); 33165988aeb2SGiridhar Malavali temp_val = qla82xx_get_temp_val(temp); 33175988aeb2SGiridhar Malavali 33185988aeb2SGiridhar Malavali if (temp_state == QLA82XX_TEMP_PANIC) { 33195988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600e, 33205988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33215988aeb2SGiridhar Malavali " maximum allowed. Hardware has been shut down.\n", 33225988aeb2SGiridhar Malavali temp_val); 33235988aeb2SGiridhar Malavali return 1; 33245988aeb2SGiridhar Malavali } else if (temp_state == QLA82XX_TEMP_WARN) { 33255988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600f, 33265988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33275988aeb2SGiridhar Malavali "operating range. Immediate action needed.\n", 33285988aeb2SGiridhar Malavali temp_val); 33295988aeb2SGiridhar Malavali } 33305988aeb2SGiridhar Malavali return 0; 33315988aeb2SGiridhar Malavali } 33325988aeb2SGiridhar Malavali 33331ae47cf3SJoe Carnuccio int qla82xx_read_temperature(scsi_qla_host_t *vha) 33341ae47cf3SJoe Carnuccio { 33351ae47cf3SJoe Carnuccio uint32_t temp; 33361ae47cf3SJoe Carnuccio 33371ae47cf3SJoe Carnuccio temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 33381ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp); 33391ae47cf3SJoe Carnuccio } 33401ae47cf3SJoe Carnuccio 3341c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3342c8f6544eSChad Dupuis { 3343c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3344c8f6544eSChad Dupuis 3345c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3346c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33478937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3348c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3349c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 335036439832Sgurinder.shergill@hp.com if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3351c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3352c8f6544eSChad Dupuis } 3353c8f6544eSChad Dupuis } 3354c8f6544eSChad Dupuis 3355a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3356a9083016SGiridhar Malavali { 33577190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3358a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3359a9083016SGiridhar Malavali 3360a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33617d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_hdlr_active) { 33627190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33635988aeb2SGiridhar Malavali if (qla82xx_check_temp(vha)) { 33645988aeb2SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33655988aeb2SGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 33665988aeb2SGiridhar Malavali qla82xx_clear_pending_mbx(vha); 33677d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 33687190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33697c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33707c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3371a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 33727d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3373579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33747c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33757c3df132SSaurav Kashyap "Quiescent needed.\n"); 3376579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 33777d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_FAILED && 33787916bb90SChad Dupuis !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 33797916bb90SChad Dupuis vha->flags.online == 1) { 33807916bb90SChad Dupuis ql_log(ql_log_warn, vha, 0xb055, 33817916bb90SChad Dupuis "Adapter state is failed. Offlining.\n"); 33827916bb90SChad Dupuis set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33837916bb90SChad Dupuis ha->flags.isp82xx_fw_hung = 1; 33847916bb90SChad Dupuis qla82xx_clear_pending_mbx(vha); 3385a9083016SGiridhar Malavali } else { 33867190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 338763154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 338863154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 338963154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 339063154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 33917190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 33927190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 339363154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 33947c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 33957c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 33967c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 33977c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 33987c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 33990e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 34000e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34010e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 34020e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34030e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 34040e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34050e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 34060e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34070e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 34080e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34090e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 34102cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 341110a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 341210a340e6SChad Dupuis "Firmware aborted with " 341310a340e6SChad Dupuis "error code 0x00006700. Device is " 341410a340e6SChad Dupuis "being reset.\n"); 34157190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 34167190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 34177190575fSGiridhar Malavali &vha->dpc_flags); 34187190575fSGiridhar Malavali } else { 34197c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 34207c3df132SSaurav Kashyap "Detect abort needed.\n"); 34217190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 34227190575fSGiridhar Malavali &vha->dpc_flags); 34237190575fSGiridhar Malavali } 34247190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3425c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3426c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 34277190575fSGiridhar Malavali } 3428a9083016SGiridhar Malavali } 3429a9083016SGiridhar Malavali } 3430a9083016SGiridhar Malavali } 3431a9083016SGiridhar Malavali 3432a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3433a9083016SGiridhar Malavali { 34347ec0effdSAtul Deshmukh int rval = -1; 34357ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 34367ec0effdSAtul Deshmukh 34377ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3438a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 34397ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 34407ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 34417ec0effdSAtul Deshmukh /* Decide the reset ownership */ 34427ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 34437ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 34447ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 34457ec0effdSAtul Deshmukh } 3446a9083016SGiridhar Malavali return rval; 3447a9083016SGiridhar Malavali } 3448a9083016SGiridhar Malavali 344908de2844SGiridhar Malavali void 345008de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 345108de2844SGiridhar Malavali { 345208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 34537ec0effdSAtul Deshmukh uint32_t dev_state = 0; 345408de2844SGiridhar Malavali 34557ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 345608de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 34577ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 34587ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 34597ec0effdSAtul Deshmukh 34607d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_READY) { 346108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 346208de2844SGiridhar Malavali "HW State: NEED RESET\n"); 34637ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) { 346408de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 34657d613ac6SSantosh Vernekar QLA8XXX_DEV_NEED_RESET); 34667d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 1; 346708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 346808de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 34697ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) 34707ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 34717ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET); 347208de2844SGiridhar Malavali } else 347308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 347408de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 347508de2844SGiridhar Malavali dev_state, 347608de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 347708de2844SGiridhar Malavali } 347808de2844SGiridhar Malavali 3479a9083016SGiridhar Malavali /* 3480a9083016SGiridhar Malavali * qla82xx_abort_isp 3481a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3482a9083016SGiridhar Malavali * 3483a9083016SGiridhar Malavali * Input: 3484a9083016SGiridhar Malavali * ha = adapter block pointer. 3485a9083016SGiridhar Malavali * 3486a9083016SGiridhar Malavali * Returns: 3487a9083016SGiridhar Malavali * 0 = success 3488a9083016SGiridhar Malavali */ 3489a9083016SGiridhar Malavali int 3490a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3491a9083016SGiridhar Malavali { 34927ec0effdSAtul Deshmukh int rval = -1; 3493a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3494a9083016SGiridhar Malavali 3495a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 34967c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 34977c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3498a9083016SGiridhar Malavali return QLA_SUCCESS; 3499a9083016SGiridhar Malavali } 35007d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 1; 3501a9083016SGiridhar Malavali 3502a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 350308de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3504a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3505a9083016SGiridhar Malavali 35067ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3507a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 35087ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 35097ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 35107ec0effdSAtul Deshmukh /* Decide the reset ownership */ 35117ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 35127ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 35137ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 35147ec0effdSAtul Deshmukh } 3515a9083016SGiridhar Malavali 3516a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3517a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3518a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3519a9083016SGiridhar Malavali 3520cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 35217190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 35227d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 0; 3523a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3524cdbb0a4fSSantosh Vernekar } 3525f1af6208SGiridhar Malavali 3526f1af6208SGiridhar Malavali if (rval) { 3527f1af6208SGiridhar Malavali vha->flags.online = 1; 3528f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3529f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 35307c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 35317c3df132SSaurav Kashyap "ISP error recover failed - board " 35327c3df132SSaurav Kashyap "disabled.\n"); 3533f1af6208SGiridhar Malavali /* 3534f1af6208SGiridhar Malavali * The next call disables the board 3535f1af6208SGiridhar Malavali * completely. 3536f1af6208SGiridhar Malavali */ 3537f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3538f1af6208SGiridhar Malavali vha->flags.online = 0; 3539f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3540f1af6208SGiridhar Malavali &vha->dpc_flags); 3541f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3542f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3543f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 35447c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 35457c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 35467c3df132SSaurav Kashyap ha->isp_abort_cnt); 3547f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3548f1af6208SGiridhar Malavali } 3549f1af6208SGiridhar Malavali } else { 3550f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 35517c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 35527c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 35537c3df132SSaurav Kashyap ha->isp_abort_cnt); 3554f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3555f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3556f1af6208SGiridhar Malavali } 3557f1af6208SGiridhar Malavali } 3558a9083016SGiridhar Malavali return rval; 3559a9083016SGiridhar Malavali } 3560a9083016SGiridhar Malavali 3561a9083016SGiridhar Malavali /* 3562a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3563a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3564a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3565a9083016SGiridhar Malavali * chip reset. 3566a9083016SGiridhar Malavali * 3567a9083016SGiridhar Malavali * Input: 3568a9083016SGiridhar Malavali * ha = adapter block pointer. 3569a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3570a9083016SGiridhar Malavali * 3571a9083016SGiridhar Malavali * Returns: 3572a9083016SGiridhar Malavali * 0 = success 3573a9083016SGiridhar Malavali */ 3574a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3575a9083016SGiridhar Malavali { 3576a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3577a9083016SGiridhar Malavali 3578a9083016SGiridhar Malavali if (vha->flags.online) { 3579a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3580a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3581a9083016SGiridhar Malavali } 3582a9083016SGiridhar Malavali 3583a9083016SGiridhar Malavali /* Stop currently executing firmware. 3584a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3585a9083016SGiridhar Malavali */ 3586a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3587a9083016SGiridhar Malavali 3588a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3589a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3590a9083016SGiridhar Malavali 3591a9083016SGiridhar Malavali return rval; 3592a9083016SGiridhar Malavali } 3593a9083016SGiridhar Malavali 3594a9083016SGiridhar Malavali /* 3595a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3596a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3597a9083016SGiridhar Malavali * 3598a9083016SGiridhar Malavali * Note: 3599a9083016SGiridhar Malavali * Does context switching here. 3600a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3601a9083016SGiridhar Malavali * 3602a9083016SGiridhar Malavali * Return: 3603a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3604a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3605a9083016SGiridhar Malavali */ 3606a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3607a9083016SGiridhar Malavali { 3608a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3609a9083016SGiridhar Malavali unsigned long wait_reset; 3610a9083016SGiridhar Malavali 3611a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3612a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3613a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3614a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3615a9083016SGiridhar Malavali 3616a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3617a9083016SGiridhar Malavali schedule_timeout(HZ); 3618a9083016SGiridhar Malavali 3619a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3620a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3621a9083016SGiridhar Malavali status = QLA_SUCCESS; 3622a9083016SGiridhar Malavali break; 3623a9083016SGiridhar Malavali } 3624a9083016SGiridhar Malavali } 36257c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3626d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3627a9083016SGiridhar Malavali 3628a9083016SGiridhar Malavali return status; 3629a9083016SGiridhar Malavali } 36307190575fSGiridhar Malavali 36317190575fSGiridhar Malavali void 36327190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 36337190575fSGiridhar Malavali { 36347ec0effdSAtul Deshmukh int i, fw_state = 0; 36357190575fSGiridhar Malavali unsigned long flags; 36367190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 36377190575fSGiridhar Malavali 36387190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 36397190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 36407190575fSGiridhar Malavali * detection only 36417190575fSGiridhar Malavali */ 36427190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36437190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 36447190575fSGiridhar Malavali msleep(1000); 36457ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 36467ec0effdSAtul Deshmukh fw_state = qla82xx_check_fw_alive(vha); 36477ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 36487ec0effdSAtul Deshmukh fw_state = qla8044_check_fw_alive(vha); 36497ec0effdSAtul Deshmukh if (fw_state) { 36507190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3651c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 36527190575fSGiridhar Malavali break; 36537190575fSGiridhar Malavali } 36547190575fSGiridhar Malavali } 36557190575fSGiridhar Malavali } 36567c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 36577c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 36587c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 36597190575fSGiridhar Malavali 36607190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 36617190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36627190575fSGiridhar Malavali int cnt, que; 36637190575fSGiridhar Malavali srb_t *sp; 36647190575fSGiridhar Malavali struct req_que *req; 36657190575fSGiridhar Malavali 36667190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36677190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36687190575fSGiridhar Malavali req = ha->req_q_map[que]; 36697190575fSGiridhar Malavali if (!req) 36707190575fSGiridhar Malavali continue; 36718d93f550SChad Dupuis for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 36727190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36737190575fSGiridhar Malavali if (sp) { 3674af13b700SGiridhar Malavali if ((!sp->u.scmd.ctx || 3675af13b700SGiridhar Malavali (sp->flags & 3676af13b700SGiridhar Malavali SRB_FCP_CMND_DMA_VALID)) && 3677af13b700SGiridhar Malavali !ha->flags.isp82xx_fw_hung) { 36787190575fSGiridhar Malavali spin_unlock_irqrestore( 36797190575fSGiridhar Malavali &ha->hardware_lock, flags); 36807190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 36817c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36827c3df132SSaurav Kashyap 0x00b1, 36837c3df132SSaurav Kashyap "mbx abort failed.\n"); 36847190575fSGiridhar Malavali } else { 36857c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36867c3df132SSaurav Kashyap 0x00b2, 36877c3df132SSaurav Kashyap "mbx abort success.\n"); 36887190575fSGiridhar Malavali } 36897190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36907190575fSGiridhar Malavali } 36917190575fSGiridhar Malavali } 36927190575fSGiridhar Malavali } 36937190575fSGiridhar Malavali } 36947190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 36957190575fSGiridhar Malavali 36967190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 36977190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 36987190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 36997c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 37007c3df132SSaurav Kashyap "Done wait for " 37017c3df132SSaurav Kashyap "pending commands.\n"); 37027190575fSGiridhar Malavali } 37037190575fSGiridhar Malavali } 37047190575fSGiridhar Malavali } 370508de2844SGiridhar Malavali 370608de2844SGiridhar Malavali /* Minidump related functions */ 370708de2844SGiridhar Malavali static int 370808de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 370908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 371008de2844SGiridhar Malavali { 371108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 371208de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 371308de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 371408de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 371508de2844SGiridhar Malavali unsigned long wtime; 371608de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 371708de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 371808de2844SGiridhar Malavali int i; 371908de2844SGiridhar Malavali 372008de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 372108de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 372208de2844SGiridhar Malavali crb_addr = crb_entry->addr; 372308de2844SGiridhar Malavali 372408de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 372508de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 372608de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 372708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 372808de2844SGiridhar Malavali crb_entry->value_1, 1); 372908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 373008de2844SGiridhar Malavali } 373108de2844SGiridhar Malavali 373208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 373308de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 373408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 373508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 373608de2844SGiridhar Malavali } 373708de2844SGiridhar Malavali 373808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 373908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 374008de2844SGiridhar Malavali read_value &= crb_entry->value_2; 374108de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 374208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 374308de2844SGiridhar Malavali read_value |= crb_entry->value_3; 374408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 374508de2844SGiridhar Malavali } 374608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 374708de2844SGiridhar Malavali } 374808de2844SGiridhar Malavali 374908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 375008de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 375108de2844SGiridhar Malavali read_value |= crb_entry->value_3; 375208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 375308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 375408de2844SGiridhar Malavali } 375508de2844SGiridhar Malavali 375608de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 375708de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 375808de2844SGiridhar Malavali wtime = jiffies + poll_time; 375908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 376008de2844SGiridhar Malavali 376108de2844SGiridhar Malavali do { 376208de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 376308de2844SGiridhar Malavali == crb_entry->value_1) 376408de2844SGiridhar Malavali break; 376508de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 376608de2844SGiridhar Malavali /* capturing dump failed */ 376708de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 376808de2844SGiridhar Malavali break; 376908de2844SGiridhar Malavali } else 377008de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 377108de2844SGiridhar Malavali crb_addr, 0, 0); 377208de2844SGiridhar Malavali } while (1); 377308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 377408de2844SGiridhar Malavali } 377508de2844SGiridhar Malavali 377608de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 377708de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 377808de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 377908de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 378008de2844SGiridhar Malavali } else 378108de2844SGiridhar Malavali addr = crb_addr; 378208de2844SGiridhar Malavali 378308de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 378408de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 378508de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 378608de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 378708de2844SGiridhar Malavali } 378808de2844SGiridhar Malavali 378908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 379008de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 379108de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 379208de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 379308de2844SGiridhar Malavali } else 379408de2844SGiridhar Malavali addr = crb_addr; 379508de2844SGiridhar Malavali 379608de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 379708de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 379808de2844SGiridhar Malavali read_value = 379908de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 380008de2844SGiridhar Malavali } else 380108de2844SGiridhar Malavali read_value = crb_entry->value_1; 380208de2844SGiridhar Malavali 380308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 380408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 380508de2844SGiridhar Malavali } 380608de2844SGiridhar Malavali 380708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 380808de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 380908de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 381008de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 381108de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 381208de2844SGiridhar Malavali if (crb_entry->value_2) 381308de2844SGiridhar Malavali read_value &= crb_entry->value_2; 381408de2844SGiridhar Malavali read_value |= crb_entry->value_3; 381508de2844SGiridhar Malavali read_value += crb_entry->value_1; 381608de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 381708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 381808de2844SGiridhar Malavali } 381908de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 382008de2844SGiridhar Malavali } 382108de2844SGiridhar Malavali return rval; 382208de2844SGiridhar Malavali } 382308de2844SGiridhar Malavali 382408de2844SGiridhar Malavali static void 382508de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 382608de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 382708de2844SGiridhar Malavali { 382808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 382908de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 383008de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 383108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 383208de2844SGiridhar Malavali 383308de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 383408de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 383508de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 383608de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 383708de2844SGiridhar Malavali 383808de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 3839fa492630SSaurav Kashyap r_value = RD_REG_DWORD((void __iomem *) 3840fa492630SSaurav Kashyap (r_addr + ha->nx_pcibase)); 384108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 384208de2844SGiridhar Malavali r_addr += r_stride; 384308de2844SGiridhar Malavali } 384408de2844SGiridhar Malavali *d_ptr = data_ptr; 384508de2844SGiridhar Malavali } 384608de2844SGiridhar Malavali 384708de2844SGiridhar Malavali static void 384808de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 384908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 385008de2844SGiridhar Malavali { 385108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 385208de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 385308de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 385408de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 385508de2844SGiridhar Malavali 385608de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 385708de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 385808de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 385908de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 386008de2844SGiridhar Malavali s_value = mux_hdr->select_value; 386108de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 386208de2844SGiridhar Malavali 386308de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 386408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 386508de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 386608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 386708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 386808de2844SGiridhar Malavali s_value += s_stride; 386908de2844SGiridhar Malavali } 387008de2844SGiridhar Malavali *d_ptr = data_ptr; 387108de2844SGiridhar Malavali } 387208de2844SGiridhar Malavali 387308de2844SGiridhar Malavali static void 387408de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 387508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 387608de2844SGiridhar Malavali { 387708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 387808de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 387908de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 388008de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 388108de2844SGiridhar Malavali 388208de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 388308de2844SGiridhar Malavali r_addr = crb_hdr->addr; 388408de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 388508de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 388608de2844SGiridhar Malavali 388708de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 388808de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 388908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 389008de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 389108de2844SGiridhar Malavali r_addr += r_stride; 389208de2844SGiridhar Malavali } 389308de2844SGiridhar Malavali *d_ptr = data_ptr; 389408de2844SGiridhar Malavali } 389508de2844SGiridhar Malavali 389608de2844SGiridhar Malavali static int 389708de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 389808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 389908de2844SGiridhar Malavali { 390008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 390108de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 390208de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 390308de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 390408de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 390508de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 390608de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 390708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 390808de2844SGiridhar Malavali 390908de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 391008de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 391108de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 391208de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 391308de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 391408de2844SGiridhar Malavali 391508de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 391608de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 391708de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 391808de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 391908de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 392008de2844SGiridhar Malavali 392108de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 392208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 392308de2844SGiridhar Malavali if (c_value_w) 392408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 392508de2844SGiridhar Malavali 392608de2844SGiridhar Malavali if (p_mask) { 392708de2844SGiridhar Malavali w_time = jiffies + p_wait; 392808de2844SGiridhar Malavali do { 392908de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 393008de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 393108de2844SGiridhar Malavali break; 393208de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 393308de2844SGiridhar Malavali /* capturing dump failed */ 393408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 393508de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 393608de2844SGiridhar Malavali "w_time: 0x%lx\n", 393708de2844SGiridhar Malavali c_value_r, p_mask, w_time); 393808de2844SGiridhar Malavali return rval; 393908de2844SGiridhar Malavali } 394008de2844SGiridhar Malavali } while (1); 394108de2844SGiridhar Malavali } 394208de2844SGiridhar Malavali 394308de2844SGiridhar Malavali addr = r_addr; 394408de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 394508de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 394608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 394708de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 394808de2844SGiridhar Malavali } 394908de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 395008de2844SGiridhar Malavali } 395108de2844SGiridhar Malavali *d_ptr = data_ptr; 395208de2844SGiridhar Malavali return QLA_SUCCESS; 395308de2844SGiridhar Malavali } 395408de2844SGiridhar Malavali 395508de2844SGiridhar Malavali static void 395608de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 395708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 395808de2844SGiridhar Malavali { 395908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 396008de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 396108de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 396208de2844SGiridhar Malavali uint32_t c_value_w; 396308de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 396408de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 396508de2844SGiridhar Malavali 396608de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 396708de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 396808de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 396908de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 397008de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 397108de2844SGiridhar Malavali 397208de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 397308de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 397408de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 397508de2844SGiridhar Malavali 397608de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 397708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 397808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 397908de2844SGiridhar Malavali addr = r_addr; 398008de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 398108de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 398208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 398308de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 398408de2844SGiridhar Malavali } 398508de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 398608de2844SGiridhar Malavali } 398708de2844SGiridhar Malavali *d_ptr = data_ptr; 398808de2844SGiridhar Malavali } 398908de2844SGiridhar Malavali 399008de2844SGiridhar Malavali static void 399108de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 399208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 399308de2844SGiridhar Malavali { 399408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 399508de2844SGiridhar Malavali uint32_t s_addr, r_addr; 399608de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 399708de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 399808de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 399908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 400008de2844SGiridhar Malavali 400108de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 400208de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 400308de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 400408de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 400508de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 400608de2844SGiridhar Malavali 400708de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 400808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 400908de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 401008de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 401108de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 401208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 401308de2844SGiridhar Malavali r_addr += r_stride; 401408de2844SGiridhar Malavali } 401508de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 401608de2844SGiridhar Malavali } 401708de2844SGiridhar Malavali *d_ptr = data_ptr; 401808de2844SGiridhar Malavali } 401908de2844SGiridhar Malavali 402008de2844SGiridhar Malavali static void 402108de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 402208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 402308de2844SGiridhar Malavali { 402408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 402508de2844SGiridhar Malavali uint32_t r_addr, r_value; 402608de2844SGiridhar Malavali uint32_t i, loop_cnt; 402708de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 402808de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 402908de2844SGiridhar Malavali 403008de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 403108de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 403208de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 403308de2844SGiridhar Malavali 403408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 403508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 403608de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 403708de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 403808de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 403908de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 404008de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 404108de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 404208de2844SGiridhar Malavali } 404308de2844SGiridhar Malavali *d_ptr = data_ptr; 404408de2844SGiridhar Malavali } 404508de2844SGiridhar Malavali 404608de2844SGiridhar Malavali static int 404708de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 404808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 404908de2844SGiridhar Malavali { 405008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 405108de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 405208de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 405308de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 405408de2844SGiridhar Malavali unsigned long flags; 405508de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 405608de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 405708de2844SGiridhar Malavali 405808de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 405908de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 406008de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 406108de2844SGiridhar Malavali 406208de2844SGiridhar Malavali if (r_addr & 0xf) { 406308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 4064d6a03581SMasanari Iida "Read addr 0x%x not 16 bytes aligned\n", r_addr); 406508de2844SGiridhar Malavali return rval; 406608de2844SGiridhar Malavali } 406708de2844SGiridhar Malavali 406808de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 406908de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 407008de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 407108de2844SGiridhar Malavali m_hdr->read_data_size); 407208de2844SGiridhar Malavali return rval; 407308de2844SGiridhar Malavali } 407408de2844SGiridhar Malavali 407508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 407608de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 407708de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 407808de2844SGiridhar Malavali 407908de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 408008de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 408108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 408208de2844SGiridhar Malavali r_value = 0; 408308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 408408de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 408508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 408608de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 408708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 408808de2844SGiridhar Malavali 408908de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 409008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 409108de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 409208de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 409308de2844SGiridhar Malavali break; 409408de2844SGiridhar Malavali } 409508de2844SGiridhar Malavali 409608de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 409708de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 409808de2844SGiridhar Malavali "failed to read through agent\n"); 409908de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 410008de2844SGiridhar Malavali return rval; 410108de2844SGiridhar Malavali } 410208de2844SGiridhar Malavali 410308de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 410408de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 410508de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 410608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 410708de2844SGiridhar Malavali } 410808de2844SGiridhar Malavali r_addr += 16; 410908de2844SGiridhar Malavali } 411008de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 411108de2844SGiridhar Malavali *d_ptr = data_ptr; 411208de2844SGiridhar Malavali return QLA_SUCCESS; 411308de2844SGiridhar Malavali } 411408de2844SGiridhar Malavali 41157ec0effdSAtul Deshmukh int 411608de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 411708de2844SGiridhar Malavali { 411808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 411908de2844SGiridhar Malavali uint64_t chksum = 0; 412008de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 412108de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 412208de2844SGiridhar Malavali 412308de2844SGiridhar Malavali while (count-- > 0) 412408de2844SGiridhar Malavali chksum += *d_ptr++; 412508de2844SGiridhar Malavali while (chksum >> 32) 412608de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 412708de2844SGiridhar Malavali return ~chksum; 412808de2844SGiridhar Malavali } 412908de2844SGiridhar Malavali 413008de2844SGiridhar Malavali static void 413108de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 413208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 413308de2844SGiridhar Malavali { 413408de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 413508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 413608de2844SGiridhar Malavali "Skipping entry[%d]: " 413708de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 413808de2844SGiridhar Malavali index, entry_hdr->entry_type, 413908de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 414008de2844SGiridhar Malavali } 414108de2844SGiridhar Malavali 414208de2844SGiridhar Malavali int 414308de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 414408de2844SGiridhar Malavali { 414508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 414608de2844SGiridhar Malavali int no_entry_hdr = 0; 414708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 414808de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 414908de2844SGiridhar Malavali uint32_t *data_ptr; 415008de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 415108de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 415208de2844SGiridhar Malavali 415308de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 415408de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 415508de2844SGiridhar Malavali 415608de2844SGiridhar Malavali if (ha->fw_dumped) { 4157a8faa263SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb037, 4158a8faa263SGiridhar Malavali "Firmware has been previously dumped (%p) " 4159a8faa263SGiridhar Malavali "-- ignoring request.\n", ha->fw_dump); 416008de2844SGiridhar Malavali goto md_failed; 416108de2844SGiridhar Malavali } 416208de2844SGiridhar Malavali 416308de2844SGiridhar Malavali ha->fw_dumped = 0; 416408de2844SGiridhar Malavali 416508de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 416608de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 416708de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 416808de2844SGiridhar Malavali goto md_failed; 416908de2844SGiridhar Malavali } 417008de2844SGiridhar Malavali 4171b6d0d9d5SGiridhar Malavali if (ha->flags.isp82xx_no_md_cap) { 4172b6d0d9d5SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb054, 4173b6d0d9d5SGiridhar Malavali "Forced reset from application, " 4174b6d0d9d5SGiridhar Malavali "ignore minidump capture\n"); 4175b6d0d9d5SGiridhar Malavali ha->flags.isp82xx_no_md_cap = 0; 4176b6d0d9d5SGiridhar Malavali goto md_failed; 4177b6d0d9d5SGiridhar Malavali } 4178b6d0d9d5SGiridhar Malavali 417908de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 418008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 418108de2844SGiridhar Malavali "Template checksum validation error\n"); 418208de2844SGiridhar Malavali goto md_failed; 418308de2844SGiridhar Malavali } 418408de2844SGiridhar Malavali 418508de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 418608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 418708de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 418808de2844SGiridhar Malavali 418908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 419008de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 419108de2844SGiridhar Malavali 419208de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 419308de2844SGiridhar Malavali 419408de2844SGiridhar Malavali /* Validate whether required debug level is set */ 419508de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 419608de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 419708de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 419808de2844SGiridhar Malavali f_capture_mask); 419908de2844SGiridhar Malavali goto md_failed; 420008de2844SGiridhar Malavali } 420108de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 420208de2844SGiridhar Malavali 420308de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 420408de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 420508de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 420608de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 420708de2844SGiridhar Malavali 420808de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 420908de2844SGiridhar Malavali 4210880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb03d, 421108de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 421208de2844SGiridhar Malavali 421308de2844SGiridhar Malavali /* Check whether template obtained is valid */ 421408de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 421508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 421608de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 421708de2844SGiridhar Malavali tmplt_hdr->entry_type); 421808de2844SGiridhar Malavali goto md_failed; 421908de2844SGiridhar Malavali } 422008de2844SGiridhar Malavali 422108de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 422208de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 422308de2844SGiridhar Malavali 422408de2844SGiridhar Malavali /* Walk through the entry headers */ 422508de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 422608de2844SGiridhar Malavali 422708de2844SGiridhar Malavali if (data_collected > total_data_size) { 422808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 422908de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 423008de2844SGiridhar Malavali data_collected); 423108de2844SGiridhar Malavali goto md_failed; 423208de2844SGiridhar Malavali } 423308de2844SGiridhar Malavali 423408de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 423508de2844SGiridhar Malavali ql2xmdcapmask)) { 423608de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 423708de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 423808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 423908de2844SGiridhar Malavali "Skipping entry[%d]: " 424008de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 424108de2844SGiridhar Malavali i, entry_hdr->entry_type, 424208de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 424308de2844SGiridhar Malavali goto skip_nxt_entry; 424408de2844SGiridhar Malavali } 424508de2844SGiridhar Malavali 424608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 424708de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 424808de2844SGiridhar Malavali "entry_type: 0x%x, captrue_mask: 0x%x\n", 424908de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 425008de2844SGiridhar Malavali entry_hdr->entry_type, 425108de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 425208de2844SGiridhar Malavali 425308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 425408de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 425508de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 425608de2844SGiridhar Malavali 425708de2844SGiridhar Malavali /* Decode the entry type and take 425808de2844SGiridhar Malavali * required action to capture debug data */ 425908de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 426008de2844SGiridhar Malavali case QLA82XX_RDEND: 426108de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 426208de2844SGiridhar Malavali break; 426308de2844SGiridhar Malavali case QLA82XX_CNTRL: 426408de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 426508de2844SGiridhar Malavali entry_hdr, &data_ptr); 426608de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 426708de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 426808de2844SGiridhar Malavali goto md_failed; 426908de2844SGiridhar Malavali } 427008de2844SGiridhar Malavali break; 427108de2844SGiridhar Malavali case QLA82XX_RDCRB: 427208de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 427308de2844SGiridhar Malavali entry_hdr, &data_ptr); 427408de2844SGiridhar Malavali break; 427508de2844SGiridhar Malavali case QLA82XX_RDMEM: 427608de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 427708de2844SGiridhar Malavali entry_hdr, &data_ptr); 427808de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 427908de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 428008de2844SGiridhar Malavali goto md_failed; 428108de2844SGiridhar Malavali } 428208de2844SGiridhar Malavali break; 428308de2844SGiridhar Malavali case QLA82XX_BOARD: 428408de2844SGiridhar Malavali case QLA82XX_RDROM: 428508de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 428608de2844SGiridhar Malavali entry_hdr, &data_ptr); 428708de2844SGiridhar Malavali break; 428808de2844SGiridhar Malavali case QLA82XX_L2DTG: 428908de2844SGiridhar Malavali case QLA82XX_L2ITG: 429008de2844SGiridhar Malavali case QLA82XX_L2DAT: 429108de2844SGiridhar Malavali case QLA82XX_L2INS: 429208de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 429308de2844SGiridhar Malavali entry_hdr, &data_ptr); 429408de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 429508de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 429608de2844SGiridhar Malavali goto md_failed; 429708de2844SGiridhar Malavali } 429808de2844SGiridhar Malavali break; 429908de2844SGiridhar Malavali case QLA82XX_L1DAT: 430008de2844SGiridhar Malavali case QLA82XX_L1INS: 430108de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 430208de2844SGiridhar Malavali entry_hdr, &data_ptr); 430308de2844SGiridhar Malavali break; 430408de2844SGiridhar Malavali case QLA82XX_RDOCM: 430508de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 430608de2844SGiridhar Malavali entry_hdr, &data_ptr); 430708de2844SGiridhar Malavali break; 430808de2844SGiridhar Malavali case QLA82XX_RDMUX: 430908de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 431008de2844SGiridhar Malavali entry_hdr, &data_ptr); 431108de2844SGiridhar Malavali break; 431208de2844SGiridhar Malavali case QLA82XX_QUEUE: 431308de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 431408de2844SGiridhar Malavali entry_hdr, &data_ptr); 431508de2844SGiridhar Malavali break; 431608de2844SGiridhar Malavali case QLA82XX_RDNOP: 431708de2844SGiridhar Malavali default: 431808de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 431908de2844SGiridhar Malavali break; 432008de2844SGiridhar Malavali } 432108de2844SGiridhar Malavali 432208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 432308de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 432408de2844SGiridhar Malavali 432508de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 432608de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 432708de2844SGiridhar Malavali skip_nxt_entry: 432808de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 432908de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 433008de2844SGiridhar Malavali } 433108de2844SGiridhar Malavali 433208de2844SGiridhar Malavali if (data_collected != total_data_size) { 4333880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb043, 433408de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 433508de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 433608de2844SGiridhar Malavali data_collected, total_data_size); 433708de2844SGiridhar Malavali goto md_failed; 433808de2844SGiridhar Malavali } 433908de2844SGiridhar Malavali 434008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 434108de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 434208de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 434308de2844SGiridhar Malavali ha->fw_dumped = 1; 434408de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 434508de2844SGiridhar Malavali 434608de2844SGiridhar Malavali md_failed: 434708de2844SGiridhar Malavali return rval; 434808de2844SGiridhar Malavali } 434908de2844SGiridhar Malavali 435008de2844SGiridhar Malavali int 435108de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 435208de2844SGiridhar Malavali { 435308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 435408de2844SGiridhar Malavali int i, k; 435508de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 435608de2844SGiridhar Malavali 435708de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 435808de2844SGiridhar Malavali 435908de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 436008de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 436108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 436208de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 436308de2844SGiridhar Malavali ql2xmdcapmask); 436408de2844SGiridhar Malavali } 436508de2844SGiridhar Malavali 436608de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 436708de2844SGiridhar Malavali if (i & ql2xmdcapmask) 436808de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 436908de2844SGiridhar Malavali } 437008de2844SGiridhar Malavali 437108de2844SGiridhar Malavali if (ha->md_dump) { 437208de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 437308de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 437408de2844SGiridhar Malavali return 1; 437508de2844SGiridhar Malavali } 437608de2844SGiridhar Malavali 437708de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 437808de2844SGiridhar Malavali if (ha->md_dump == NULL) { 437908de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 438008de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 438108de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 438208de2844SGiridhar Malavali return 1; 438308de2844SGiridhar Malavali } 438408de2844SGiridhar Malavali return 0; 438508de2844SGiridhar Malavali } 438608de2844SGiridhar Malavali 438708de2844SGiridhar Malavali void 438808de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 438908de2844SGiridhar Malavali { 439008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 439108de2844SGiridhar Malavali 439208de2844SGiridhar Malavali /* Release the template header allocated */ 439308de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 439408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 439508de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 439608de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 439708de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 439808de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4399fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 440008de2844SGiridhar Malavali } 440108de2844SGiridhar Malavali 440208de2844SGiridhar Malavali /* Release the template data buffer allocated */ 440308de2844SGiridhar Malavali if (ha->md_dump) { 440408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 440508de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 440608de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 440708de2844SGiridhar Malavali vfree(ha->md_dump); 440808de2844SGiridhar Malavali ha->md_dump_size = 0; 4409fa492630SSaurav Kashyap ha->md_dump = NULL; 441008de2844SGiridhar Malavali } 441108de2844SGiridhar Malavali } 441208de2844SGiridhar Malavali 441308de2844SGiridhar Malavali void 441408de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 441508de2844SGiridhar Malavali { 441608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 441708de2844SGiridhar Malavali int rval; 441808de2844SGiridhar Malavali 441908de2844SGiridhar Malavali /* Get Minidump template size */ 442008de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 442108de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 442208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 442308de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 442408de2844SGiridhar Malavali ha->md_template_size / 1024); 442508de2844SGiridhar Malavali 442608de2844SGiridhar Malavali /* Get Minidump template */ 44277ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 44287ec0effdSAtul Deshmukh rval = qla8044_md_get_template(vha); 44297ec0effdSAtul Deshmukh else 443008de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 44317ec0effdSAtul Deshmukh 443208de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 443308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 443408de2844SGiridhar Malavali "MiniDump Template obtained\n"); 443508de2844SGiridhar Malavali 443608de2844SGiridhar Malavali /* Allocate memory for minidump */ 443708de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 443808de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 443908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 444008de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 444108de2844SGiridhar Malavali ha->md_dump_size / 1024); 444208de2844SGiridhar Malavali else { 444308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 444408de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 444508de2844SGiridhar Malavali ha->md_tmplt_hdr, 444608de2844SGiridhar Malavali ha->md_template_size / 1024); 444708de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 444808de2844SGiridhar Malavali ha->md_template_size, 444908de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4450fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 445108de2844SGiridhar Malavali } 445208de2844SGiridhar Malavali 445308de2844SGiridhar Malavali } 445408de2844SGiridhar Malavali } 445508de2844SGiridhar Malavali } 4456999916dcSSaurav Kashyap 4457999916dcSSaurav Kashyap int 4458999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4459999916dcSSaurav Kashyap { 4460999916dcSSaurav Kashyap 4461999916dcSSaurav Kashyap int rval; 4462999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4463999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4464999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4465999916dcSSaurav Kashyap 4466999916dcSSaurav Kashyap if (rval) { 4467999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4468999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4469999916dcSSaurav Kashyap goto exit; 4470999916dcSSaurav Kashyap } 4471999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4472999916dcSSaurav Kashyap exit: 4473999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4474999916dcSSaurav Kashyap return rval; 4475999916dcSSaurav Kashyap } 4476999916dcSSaurav Kashyap 4477999916dcSSaurav Kashyap int 4478999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4479999916dcSSaurav Kashyap { 4480999916dcSSaurav Kashyap 4481999916dcSSaurav Kashyap int rval; 4482999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4483999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4484999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4485999916dcSSaurav Kashyap 4486999916dcSSaurav Kashyap if (rval) { 4487999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4488999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4489999916dcSSaurav Kashyap goto exit; 4490999916dcSSaurav Kashyap } 4491999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4492999916dcSSaurav Kashyap exit: 4493999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4494999916dcSSaurav Kashyap return rval; 4495999916dcSSaurav Kashyap } 4496a1b23c5aSChad Dupuis 4497a1b23c5aSChad Dupuis void 4498a1b23c5aSChad Dupuis qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4499a1b23c5aSChad Dupuis { 4500a1b23c5aSChad Dupuis struct qla_hw_data *ha = vha->hw; 4501a1b23c5aSChad Dupuis 4502a1b23c5aSChad Dupuis if (!ha->allow_cna_fw_dump) 4503a1b23c5aSChad Dupuis return; 4504a1b23c5aSChad Dupuis 4505a1b23c5aSChad Dupuis scsi_block_requests(vha->host); 4506a1b23c5aSChad Dupuis ha->flags.isp82xx_no_md_cap = 1; 4507a1b23c5aSChad Dupuis qla82xx_idc_lock(ha); 4508a1b23c5aSChad Dupuis qla82xx_set_reset_owner(vha); 4509a1b23c5aSChad Dupuis qla82xx_idc_unlock(ha); 4510a1b23c5aSChad Dupuis qla2x00_wait_for_chip_reset(vha); 4511a1b23c5aSChad Dupuis scsi_unblock_requests(vha->host); 4512a1b23c5aSChad Dupuis } 4513