1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 346152cebSChad Dupuis * Copyright (c) 2003-2012 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39fa492630SSaurav Kashyap static int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 45a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 46a9083016SGiridhar Malavali { 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 97a9083016SGiridhar Malavali /* 98a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 99a9083016SGiridhar Malavali */ 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 101a9083016SGiridhar Malavali 102a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 103a9083016SGiridhar Malavali } 104a9083016SGiridhar Malavali 105fa492630SSaurav Kashyap static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 107a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 108a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 109a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 110a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 111a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 112a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 113a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 114a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 123a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 125a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213a9083016SGiridhar Malavali {{{0} } }, 214a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 215a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 216a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 217a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 218a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 219a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 220a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 221a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 230a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{0} } }, 235a9083016SGiridhar Malavali {{{0} } }, 236a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248a9083016SGiridhar Malavali {{{0} } }, 249a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255a9083016SGiridhar Malavali {{{0} } }, 256a9083016SGiridhar Malavali {{{0} } }, 257a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260a9083016SGiridhar Malavali }; 261a9083016SGiridhar Malavali 262a9083016SGiridhar Malavali /* 263a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 264a9083016SGiridhar Malavali */ 265fa492630SSaurav Kashyap static unsigned qla82xx_crb_hub_agt[64] = { 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270a9083016SGiridhar Malavali 0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293a9083016SGiridhar Malavali 0, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318a9083016SGiridhar Malavali 0, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali }; 331a9083016SGiridhar Malavali 332f1af6208SGiridhar Malavali /* Device states */ 333fa492630SSaurav Kashyap static char *q_dev_state[] = { 334f1af6208SGiridhar Malavali "Unknown", 335f1af6208SGiridhar Malavali "Cold", 336f1af6208SGiridhar Malavali "Initializing", 337f1af6208SGiridhar Malavali "Ready", 338f1af6208SGiridhar Malavali "Need Reset", 339f1af6208SGiridhar Malavali "Need Quiescent", 340f1af6208SGiridhar Malavali "Failed", 341f1af6208SGiridhar Malavali "Quiescent", 342f1af6208SGiridhar Malavali }; 343f1af6208SGiridhar Malavali 34408de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 34508de2844SGiridhar Malavali { 34608de2844SGiridhar Malavali return q_dev_state[dev_state]; 34708de2844SGiridhar Malavali } 34808de2844SGiridhar Malavali 349a9083016SGiridhar Malavali /* 350a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 351a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 352a9083016SGiridhar Malavali * side effect: lock crb window 353a9083016SGiridhar Malavali */ 354a9083016SGiridhar Malavali static void 355a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356a9083016SGiridhar Malavali { 357a9083016SGiridhar Malavali u32 win_read; 3587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359a9083016SGiridhar Malavali 360a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 361a9083016SGiridhar Malavali writel(ha->crb_win, 362fa492630SSaurav Kashyap (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363a9083016SGiridhar Malavali 364a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 365a9083016SGiridhar Malavali * to use it. 366a9083016SGiridhar Malavali */ 367fa492630SSaurav Kashyap win_read = RD_REG_DWORD((void __iomem *) 368fa492630SSaurav Kashyap (CRB_WINDOW_2M + ha->nx_pcibase)); 369a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3707c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3717c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3727c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 373d8424f68SJoe Perches __func__, ha->crb_win, win_read, *off); 374a9083016SGiridhar Malavali } 375a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376a9083016SGiridhar Malavali } 377a9083016SGiridhar Malavali 378a9083016SGiridhar Malavali static inline unsigned long 379a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380a9083016SGiridhar Malavali { 3817c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 383a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 385a9083016SGiridhar Malavali * regs are in both windows. 386a9083016SGiridhar Malavali */ 387a9083016SGiridhar Malavali return off; 388a9083016SGiridhar Malavali } 389a9083016SGiridhar Malavali 390a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391a9083016SGiridhar Malavali /* We are in first CRB window */ 392a9083016SGiridhar Malavali if (ha->curr_window != 0) 393a9083016SGiridhar Malavali WARN_ON(1); 394a9083016SGiridhar Malavali return off; 395a9083016SGiridhar Malavali } 396a9083016SGiridhar Malavali 397a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398a9083016SGiridhar Malavali /* We are in second CRB window */ 399a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400a9083016SGiridhar Malavali 401a9083016SGiridhar Malavali if (ha->curr_window != 1) 402a9083016SGiridhar Malavali return off; 403a9083016SGiridhar Malavali 404a9083016SGiridhar Malavali /* We are in the QM or direct access 405a9083016SGiridhar Malavali * register region - do nothing 406a9083016SGiridhar Malavali */ 407a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 409a9083016SGiridhar Malavali return off; 410a9083016SGiridhar Malavali } 411a9083016SGiridhar Malavali /* strange address given */ 4127c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 413d8424f68SJoe Perches "%s: Warning: unm_nic_pci_set_crbwindow " 4147c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4157c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 416a9083016SGiridhar Malavali return off; 417a9083016SGiridhar Malavali } 418a9083016SGiridhar Malavali 41977e334d2SGiridhar Malavali static int 42077e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 42177e334d2SGiridhar Malavali { 42277e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42377e334d2SGiridhar Malavali 42477e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 42577e334d2SGiridhar Malavali return -1; 42677e334d2SGiridhar Malavali 42777e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42877e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42977e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 43077e334d2SGiridhar Malavali return 0; 43177e334d2SGiridhar Malavali } 43277e334d2SGiridhar Malavali 43377e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 43477e334d2SGiridhar Malavali return -1; 43577e334d2SGiridhar Malavali 43677e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 43777e334d2SGiridhar Malavali 43877e334d2SGiridhar Malavali /* Try direct map */ 43977e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 44077e334d2SGiridhar Malavali 44177e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 44277e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 44377e334d2SGiridhar Malavali return 0; 44477e334d2SGiridhar Malavali } 44577e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 44677e334d2SGiridhar Malavali return 1; 44777e334d2SGiridhar Malavali } 44877e334d2SGiridhar Malavali 44977e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 45077e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45177e334d2SGiridhar Malavali { 45277e334d2SGiridhar Malavali int done = 0, timeout = 0; 45377e334d2SGiridhar Malavali 45477e334d2SGiridhar Malavali while (!done) { 45577e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 45677e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 45777e334d2SGiridhar Malavali if (done == 1) 45877e334d2SGiridhar Malavali break; 45977e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 46077e334d2SGiridhar Malavali return -1; 46177e334d2SGiridhar Malavali timeout++; 46277e334d2SGiridhar Malavali } 46377e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 46477e334d2SGiridhar Malavali return 0; 46577e334d2SGiridhar Malavali } 46677e334d2SGiridhar Malavali 467a9083016SGiridhar Malavali int 468a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469a9083016SGiridhar Malavali { 470a9083016SGiridhar Malavali unsigned long flags = 0; 471a9083016SGiridhar Malavali int rv; 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474a9083016SGiridhar Malavali 475a9083016SGiridhar Malavali BUG_ON(rv == -1); 476a9083016SGiridhar Malavali 477a9083016SGiridhar Malavali if (rv == 1) { 478a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 479a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 480a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 481a9083016SGiridhar Malavali } 482a9083016SGiridhar Malavali 483a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 484a9083016SGiridhar Malavali 485a9083016SGiridhar Malavali if (rv == 1) { 486a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 488a9083016SGiridhar Malavali } 489a9083016SGiridhar Malavali return 0; 490a9083016SGiridhar Malavali } 491a9083016SGiridhar Malavali 492a9083016SGiridhar Malavali int 493a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494a9083016SGiridhar Malavali { 495a9083016SGiridhar Malavali unsigned long flags = 0; 496a9083016SGiridhar Malavali int rv; 497a9083016SGiridhar Malavali u32 data; 498a9083016SGiridhar Malavali 499a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500a9083016SGiridhar Malavali 501a9083016SGiridhar Malavali BUG_ON(rv == -1); 502a9083016SGiridhar Malavali 503a9083016SGiridhar Malavali if (rv == 1) { 504a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 505a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 506a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 507a9083016SGiridhar Malavali } 508a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 509a9083016SGiridhar Malavali 510a9083016SGiridhar Malavali if (rv == 1) { 511a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 513a9083016SGiridhar Malavali } 514a9083016SGiridhar Malavali return data; 515a9083016SGiridhar Malavali } 516a9083016SGiridhar Malavali 517a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 518a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 519a9083016SGiridhar Malavali { 520a9083016SGiridhar Malavali int i; 521a9083016SGiridhar Malavali int done = 0, timeout = 0; 522a9083016SGiridhar Malavali 523a9083016SGiridhar Malavali while (!done) { 524a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 525a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526a9083016SGiridhar Malavali if (done == 1) 527a9083016SGiridhar Malavali break; 528a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 529a9083016SGiridhar Malavali return -1; 530a9083016SGiridhar Malavali 531a9083016SGiridhar Malavali timeout++; 532a9083016SGiridhar Malavali 533a9083016SGiridhar Malavali /* Yield CPU */ 534a9083016SGiridhar Malavali if (!in_interrupt()) 535a9083016SGiridhar Malavali schedule(); 536a9083016SGiridhar Malavali else { 537a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 538a9083016SGiridhar Malavali cpu_relax(); 539a9083016SGiridhar Malavali } 540a9083016SGiridhar Malavali } 541a9083016SGiridhar Malavali 542a9083016SGiridhar Malavali return 0; 543a9083016SGiridhar Malavali } 544a9083016SGiridhar Malavali 545a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 546a9083016SGiridhar Malavali { 547a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548a9083016SGiridhar Malavali } 549a9083016SGiridhar Malavali 550a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 551a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 552a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 553a9083016SGiridhar Malavali /* 554a9083016SGiridhar Malavali * check memory access boundary. 555a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 556a9083016SGiridhar Malavali */ 557a9083016SGiridhar Malavali static unsigned long 558a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 559a9083016SGiridhar Malavali unsigned long long addr, int size) 560a9083016SGiridhar Malavali { 561a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 562a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 563a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 564a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 565a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 566a9083016SGiridhar Malavali return 0; 567a9083016SGiridhar Malavali else 568a9083016SGiridhar Malavali return 1; 569a9083016SGiridhar Malavali } 570a9083016SGiridhar Malavali 571fa492630SSaurav Kashyap static int qla82xx_pci_set_window_warning_count; 572a9083016SGiridhar Malavali 57377e334d2SGiridhar Malavali static unsigned long 574a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 575a9083016SGiridhar Malavali { 576a9083016SGiridhar Malavali int window; 577a9083016SGiridhar Malavali u32 win_read; 5787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 579a9083016SGiridhar Malavali 580a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 581a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 582a9083016SGiridhar Malavali /* DDR network side */ 583a9083016SGiridhar Malavali window = MN_WIN(addr); 584a9083016SGiridhar Malavali ha->ddr_mn_window = window; 585a9083016SGiridhar Malavali qla82xx_wr_32(ha, 586a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 587a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 588a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 589a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5907c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5917c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 592a9083016SGiridhar Malavali __func__, window, win_read); 593a9083016SGiridhar Malavali } 594a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 595a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 596a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 597a9083016SGiridhar Malavali unsigned int temp1; 598a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5997c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 600a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 601a9083016SGiridhar Malavali addr = -1UL; 602a9083016SGiridhar Malavali } 603a9083016SGiridhar Malavali window = OCM_WIN(addr); 604a9083016SGiridhar Malavali ha->ddr_mn_window = window; 605a9083016SGiridhar Malavali qla82xx_wr_32(ha, 606a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 607a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 608a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 609a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 610a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 611a9083016SGiridhar Malavali if (win_read != temp1) { 6127c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6137c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 614a9083016SGiridhar Malavali __func__, temp1, win_read); 615a9083016SGiridhar Malavali } 616a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 617a9083016SGiridhar Malavali 618a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 619a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 620a9083016SGiridhar Malavali /* QDR network side */ 621a9083016SGiridhar Malavali window = MS_WIN(addr); 622a9083016SGiridhar Malavali ha->qdr_sn_window = window; 623a9083016SGiridhar Malavali qla82xx_wr_32(ha, 624a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 625a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 626a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 627a9083016SGiridhar Malavali if (win_read != window) { 6287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6297c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 630a9083016SGiridhar Malavali __func__, window, win_read); 631a9083016SGiridhar Malavali } 632a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 633a9083016SGiridhar Malavali } else { 634a9083016SGiridhar Malavali /* 635a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 636a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 637a9083016SGiridhar Malavali */ 638a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 639a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6417c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6427c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 643a9083016SGiridhar Malavali } 644a9083016SGiridhar Malavali addr = -1UL; 645a9083016SGiridhar Malavali } 646a9083016SGiridhar Malavali return addr; 647a9083016SGiridhar Malavali } 648a9083016SGiridhar Malavali 649a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 650a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 651a9083016SGiridhar Malavali unsigned long long addr) 652a9083016SGiridhar Malavali { 653a9083016SGiridhar Malavali int window; 654a9083016SGiridhar Malavali unsigned long long qdr_max; 655a9083016SGiridhar Malavali 656a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 657a9083016SGiridhar Malavali 658a9083016SGiridhar Malavali /* DDR network side */ 659a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 660a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 661a9083016SGiridhar Malavali BUG(); 662a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 663a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 664a9083016SGiridhar Malavali return 1; 665a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 666a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 667a9083016SGiridhar Malavali return 1; 668a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 669a9083016SGiridhar Malavali /* QDR network side */ 670a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 671a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 672a9083016SGiridhar Malavali return 1; 673a9083016SGiridhar Malavali } 674a9083016SGiridhar Malavali return 0; 675a9083016SGiridhar Malavali } 676a9083016SGiridhar Malavali 677a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 678a9083016SGiridhar Malavali u64 off, void *data, int size) 679a9083016SGiridhar Malavali { 680a9083016SGiridhar Malavali unsigned long flags; 681fa492630SSaurav Kashyap void __iomem *addr = NULL; 682a9083016SGiridhar Malavali int ret = 0; 683a9083016SGiridhar Malavali u64 start; 684fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 685a9083016SGiridhar Malavali unsigned long mem_base; 686a9083016SGiridhar Malavali unsigned long mem_page; 6877c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 688a9083016SGiridhar Malavali 689a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 690a9083016SGiridhar Malavali 691a9083016SGiridhar Malavali /* 692a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 693a9083016SGiridhar Malavali * do not access. 694a9083016SGiridhar Malavali */ 695a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 696a9083016SGiridhar Malavali if ((start == -1UL) || 697a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 698a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6997c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 7007c3df132SSaurav Kashyap "%s out of bound pci memory " 7017c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7027c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 703a9083016SGiridhar Malavali return -1; 704a9083016SGiridhar Malavali } 705a9083016SGiridhar Malavali 706a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 707a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 708a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 709a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 710a9083016SGiridhar Malavali * consecutive pages. 711a9083016SGiridhar Malavali */ 712a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 713a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 714a9083016SGiridhar Malavali else 715a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 716fa492630SSaurav Kashyap if (mem_ptr == NULL) { 717a9083016SGiridhar Malavali *(u8 *)data = 0; 718a9083016SGiridhar Malavali return -1; 719a9083016SGiridhar Malavali } 720a9083016SGiridhar Malavali addr = mem_ptr; 721a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 722a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 723a9083016SGiridhar Malavali 724a9083016SGiridhar Malavali switch (size) { 725a9083016SGiridhar Malavali case 1: 726a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 727a9083016SGiridhar Malavali break; 728a9083016SGiridhar Malavali case 2: 729a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 730a9083016SGiridhar Malavali break; 731a9083016SGiridhar Malavali case 4: 732a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 733a9083016SGiridhar Malavali break; 734a9083016SGiridhar Malavali case 8: 735a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 736a9083016SGiridhar Malavali break; 737a9083016SGiridhar Malavali default: 738a9083016SGiridhar Malavali ret = -1; 739a9083016SGiridhar Malavali break; 740a9083016SGiridhar Malavali } 741a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 742a9083016SGiridhar Malavali 743a9083016SGiridhar Malavali if (mem_ptr) 744a9083016SGiridhar Malavali iounmap(mem_ptr); 745a9083016SGiridhar Malavali return ret; 746a9083016SGiridhar Malavali } 747a9083016SGiridhar Malavali 748a9083016SGiridhar Malavali static int 749a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 750a9083016SGiridhar Malavali u64 off, void *data, int size) 751a9083016SGiridhar Malavali { 752a9083016SGiridhar Malavali unsigned long flags; 753fa492630SSaurav Kashyap void __iomem *addr = NULL; 754a9083016SGiridhar Malavali int ret = 0; 755a9083016SGiridhar Malavali u64 start; 756fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 757a9083016SGiridhar Malavali unsigned long mem_base; 758a9083016SGiridhar Malavali unsigned long mem_page; 7597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 760a9083016SGiridhar Malavali 761a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 762a9083016SGiridhar Malavali 763a9083016SGiridhar Malavali /* 764a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 765a9083016SGiridhar Malavali * do not access. 766a9083016SGiridhar Malavali */ 767a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 768a9083016SGiridhar Malavali if ((start == -1UL) || 769a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 770a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7717c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7727c3df132SSaurav Kashyap "%s out of bount memory " 7737c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7747c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 775a9083016SGiridhar Malavali return -1; 776a9083016SGiridhar Malavali } 777a9083016SGiridhar Malavali 778a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 779a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 780a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 781a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 782a9083016SGiridhar Malavali * consecutive pages. 783a9083016SGiridhar Malavali */ 784a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 785a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 786a9083016SGiridhar Malavali else 787a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 788fa492630SSaurav Kashyap if (mem_ptr == NULL) 789a9083016SGiridhar Malavali return -1; 790a9083016SGiridhar Malavali 791a9083016SGiridhar Malavali addr = mem_ptr; 792a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 793a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 794a9083016SGiridhar Malavali 795a9083016SGiridhar Malavali switch (size) { 796a9083016SGiridhar Malavali case 1: 797a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 798a9083016SGiridhar Malavali break; 799a9083016SGiridhar Malavali case 2: 800a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 801a9083016SGiridhar Malavali break; 802a9083016SGiridhar Malavali case 4: 803a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 804a9083016SGiridhar Malavali break; 805a9083016SGiridhar Malavali case 8: 806a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 807a9083016SGiridhar Malavali break; 808a9083016SGiridhar Malavali default: 809a9083016SGiridhar Malavali ret = -1; 810a9083016SGiridhar Malavali break; 811a9083016SGiridhar Malavali } 812a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 813a9083016SGiridhar Malavali if (mem_ptr) 814a9083016SGiridhar Malavali iounmap(mem_ptr); 815a9083016SGiridhar Malavali return ret; 816a9083016SGiridhar Malavali } 817a9083016SGiridhar Malavali 818a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81977e334d2SGiridhar Malavali static unsigned long 82077e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 821a9083016SGiridhar Malavali { 822a9083016SGiridhar Malavali int i; 823a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 824a9083016SGiridhar Malavali 825a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 826a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 827a9083016SGiridhar Malavali 828a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 829a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 830a9083016SGiridhar Malavali offset = addr & 0x000fffff; 831a9083016SGiridhar Malavali 832a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 833a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 834a9083016SGiridhar Malavali pci_base = i << 20; 835a9083016SGiridhar Malavali break; 836a9083016SGiridhar Malavali } 837a9083016SGiridhar Malavali } 838a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 839a9083016SGiridhar Malavali return pci_base; 840a9083016SGiridhar Malavali return pci_base + offset; 841a9083016SGiridhar Malavali } 842a9083016SGiridhar Malavali 843a9083016SGiridhar Malavali static long rom_max_timeout = 100; 844a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 845a9083016SGiridhar Malavali 84677e334d2SGiridhar Malavali static int 847a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 848a9083016SGiridhar Malavali { 849a9083016SGiridhar Malavali int done = 0, timeout = 0; 850a9083016SGiridhar Malavali 851a9083016SGiridhar Malavali while (!done) { 852a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 853a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 854a9083016SGiridhar Malavali if (done == 1) 855a9083016SGiridhar Malavali break; 856a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 857a9083016SGiridhar Malavali return -1; 858a9083016SGiridhar Malavali timeout++; 859a9083016SGiridhar Malavali } 860a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 861a9083016SGiridhar Malavali return 0; 862a9083016SGiridhar Malavali } 863a9083016SGiridhar Malavali 864d652e093SChad Dupuis static void 865d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 866d652e093SChad Dupuis { 867d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 868d652e093SChad Dupuis } 869d652e093SChad Dupuis 87077e334d2SGiridhar Malavali static int 871a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 872a9083016SGiridhar Malavali { 873a9083016SGiridhar Malavali long timeout = 0; 874a9083016SGiridhar Malavali long done = 0 ; 8757c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 876a9083016SGiridhar Malavali 877a9083016SGiridhar Malavali while (done == 0) { 878a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 879a9083016SGiridhar Malavali done &= 4; 880a9083016SGiridhar Malavali timeout++; 881a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8827c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8837c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8847c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 885a9083016SGiridhar Malavali return -1; 886a9083016SGiridhar Malavali } 887a9083016SGiridhar Malavali } 888a9083016SGiridhar Malavali return 0; 889a9083016SGiridhar Malavali } 890a9083016SGiridhar Malavali 89177e334d2SGiridhar Malavali static int 892a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 893a9083016SGiridhar Malavali { 894a9083016SGiridhar Malavali long timeout = 0; 895a9083016SGiridhar Malavali long done = 0 ; 8967c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 897a9083016SGiridhar Malavali 898a9083016SGiridhar Malavali while (done == 0) { 899a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 900a9083016SGiridhar Malavali done &= 2; 901a9083016SGiridhar Malavali timeout++; 902a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9037c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9047c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9057c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 906a9083016SGiridhar Malavali return -1; 907a9083016SGiridhar Malavali } 908a9083016SGiridhar Malavali } 909a9083016SGiridhar Malavali return 0; 910a9083016SGiridhar Malavali } 911a9083016SGiridhar Malavali 912fa492630SSaurav Kashyap static int 9132b29d96dSChad Dupuis qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 9142b29d96dSChad Dupuis { 9152b29d96dSChad Dupuis uint32_t off_value, rval = 0; 9162b29d96dSChad Dupuis 917fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 9182b29d96dSChad Dupuis (off & 0xFFFF0000)); 9192b29d96dSChad Dupuis 9202b29d96dSChad Dupuis /* Read back value to make sure write has gone through */ 921fa492630SSaurav Kashyap RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 9222b29d96dSChad Dupuis off_value = (off & 0x0000FFFF); 9232b29d96dSChad Dupuis 9242b29d96dSChad Dupuis if (flag) 925fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *) 9262b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 9272b29d96dSChad Dupuis data); 9282b29d96dSChad Dupuis else 929fa492630SSaurav Kashyap rval = RD_REG_DWORD((void __iomem *) 9302b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 9312b29d96dSChad Dupuis 9322b29d96dSChad Dupuis return rval; 9332b29d96dSChad Dupuis } 9342b29d96dSChad Dupuis 93577e334d2SGiridhar Malavali static int 936a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937a9083016SGiridhar Malavali { 9382b29d96dSChad Dupuis /* Dword reads to flash. */ 9392b29d96dSChad Dupuis qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 9402b29d96dSChad Dupuis *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 9412b29d96dSChad Dupuis (addr & 0x0000FFFF), 0, 0); 9427c3df132SSaurav Kashyap 943a9083016SGiridhar Malavali return 0; 944a9083016SGiridhar Malavali } 945a9083016SGiridhar Malavali 94677e334d2SGiridhar Malavali static int 947a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 948a9083016SGiridhar Malavali { 949a9083016SGiridhar Malavali int ret, loops = 0; 9507c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 951a9083016SGiridhar Malavali 952a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 953a9083016SGiridhar Malavali udelay(100); 954a9083016SGiridhar Malavali schedule(); 955a9083016SGiridhar Malavali loops++; 956a9083016SGiridhar Malavali } 957a9083016SGiridhar Malavali if (loops >= 50000) { 9587c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 959a720101dSMasanari Iida "Failed to acquire SEM2 lock.\n"); 960a9083016SGiridhar Malavali return -1; 961a9083016SGiridhar Malavali } 962a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 963d652e093SChad Dupuis qla82xx_rom_unlock(ha); 964a9083016SGiridhar Malavali return ret; 965a9083016SGiridhar Malavali } 966a9083016SGiridhar Malavali 96777e334d2SGiridhar Malavali static int 968a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 969a9083016SGiridhar Malavali { 9707c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 971a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 972a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 973a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9747c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9757c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 976a9083016SGiridhar Malavali return -1; 977a9083016SGiridhar Malavali } 978a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 979a9083016SGiridhar Malavali return 0; 980a9083016SGiridhar Malavali } 981a9083016SGiridhar Malavali 98277e334d2SGiridhar Malavali static int 983a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 984a9083016SGiridhar Malavali { 985a9083016SGiridhar Malavali long timeout = 0; 986a9083016SGiridhar Malavali uint32_t done = 1 ; 987a9083016SGiridhar Malavali uint32_t val; 988a9083016SGiridhar Malavali int ret = 0; 9897c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 990a9083016SGiridhar Malavali 991a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 992a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 993a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 994a9083016SGiridhar Malavali done = val & 1; 995a9083016SGiridhar Malavali timeout++; 996a9083016SGiridhar Malavali udelay(10); 997a9083016SGiridhar Malavali cond_resched(); 998a9083016SGiridhar Malavali if (timeout >= 50000) { 9997c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 10007c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 1001a9083016SGiridhar Malavali return -1; 1002a9083016SGiridhar Malavali } 1003a9083016SGiridhar Malavali } 1004a9083016SGiridhar Malavali return ret; 1005a9083016SGiridhar Malavali } 1006a9083016SGiridhar Malavali 100777e334d2SGiridhar Malavali static int 1008a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1009a9083016SGiridhar Malavali { 1010a9083016SGiridhar Malavali uint32_t val; 1011a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1012a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1013a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1014a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1015a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1016a9083016SGiridhar Malavali return -1; 1017a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1018a9083016SGiridhar Malavali return -1; 1019a9083016SGiridhar Malavali if ((val & 2) != 2) 1020a9083016SGiridhar Malavali return -1; 1021a9083016SGiridhar Malavali return 0; 1022a9083016SGiridhar Malavali } 1023a9083016SGiridhar Malavali 102477e334d2SGiridhar Malavali static int 1025a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1026a9083016SGiridhar Malavali { 10277c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1028a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1029a9083016SGiridhar Malavali return -1; 1030a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1031a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1032a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10337c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10347c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1035a9083016SGiridhar Malavali return -1; 1036a9083016SGiridhar Malavali } 1037a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1038a9083016SGiridhar Malavali } 1039a9083016SGiridhar Malavali 104077e334d2SGiridhar Malavali static int 1041a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1042a9083016SGiridhar Malavali { 10437c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1044a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1045a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10467c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10477c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1048a9083016SGiridhar Malavali return -1; 1049a9083016SGiridhar Malavali } 1050a9083016SGiridhar Malavali return 0; 1051a9083016SGiridhar Malavali } 1052a9083016SGiridhar Malavali 105377e334d2SGiridhar Malavali static int 1054a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1055a9083016SGiridhar Malavali { 1056a9083016SGiridhar Malavali int loops = 0; 10577c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10587c3df132SSaurav Kashyap 1059a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1060a9083016SGiridhar Malavali udelay(100); 1061a9083016SGiridhar Malavali cond_resched(); 1062a9083016SGiridhar Malavali loops++; 1063a9083016SGiridhar Malavali } 1064a9083016SGiridhar Malavali if (loops >= 50000) { 10657c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10667c3df132SSaurav Kashyap "ROM lock failed.\n"); 1067a9083016SGiridhar Malavali return -1; 1068a9083016SGiridhar Malavali } 1069cd6dbb03SJesper Juhl return 0; 1070a9083016SGiridhar Malavali } 1071a9083016SGiridhar Malavali 107277e334d2SGiridhar Malavali static int 1073a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1074a9083016SGiridhar Malavali uint32_t data) 1075a9083016SGiridhar Malavali { 1076a9083016SGiridhar Malavali int ret = 0; 10777c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1078a9083016SGiridhar Malavali 1079a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1080a9083016SGiridhar Malavali if (ret < 0) { 10817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10827c3df132SSaurav Kashyap "ROM lock failed.\n"); 1083a9083016SGiridhar Malavali return ret; 1084a9083016SGiridhar Malavali } 1085a9083016SGiridhar Malavali 1086a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1087a9083016SGiridhar Malavali goto done_write; 1088a9083016SGiridhar Malavali 1089a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1090a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1091a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1092a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1093a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1094a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10957c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 10967c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1097a9083016SGiridhar Malavali ret = -1; 1098a9083016SGiridhar Malavali goto done_write; 1099a9083016SGiridhar Malavali } 1100a9083016SGiridhar Malavali 1101a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1102a9083016SGiridhar Malavali 1103a9083016SGiridhar Malavali done_write: 1104d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1105a9083016SGiridhar Malavali return ret; 1106a9083016SGiridhar Malavali } 1107a9083016SGiridhar Malavali 1108a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1109a9083016SGiridhar Malavali * to put the ISP into operational state 1110a9083016SGiridhar Malavali */ 111177e334d2SGiridhar Malavali static int 111277e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1113a9083016SGiridhar Malavali { 1114a9083016SGiridhar Malavali int addr, val; 1115a9083016SGiridhar Malavali int i ; 1116a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1117a9083016SGiridhar Malavali unsigned long off; 1118a9083016SGiridhar Malavali unsigned offset, n; 1119a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1120a9083016SGiridhar Malavali 1121a9083016SGiridhar Malavali struct crb_addr_pair { 1122a9083016SGiridhar Malavali long addr; 1123a9083016SGiridhar Malavali long data; 1124a9083016SGiridhar Malavali }; 1125a9083016SGiridhar Malavali 1126a720101dSMasanari Iida /* Halt all the individual PEGs and other blocks of the ISP */ 1127a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1128c9e8fd5cSMadhuranath Iyengar 112902be2215SGiridhar Malavali /* disable all I2Q */ 113002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 113102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 113202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 113302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 113402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 113502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 113602be2215SGiridhar Malavali 113702be2215SGiridhar Malavali /* disable all niu interrupts */ 1138c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1139c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1140c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1141c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1142c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 114302be2215SGiridhar Malavali /* disable sideband mac */ 114402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 114502be2215SGiridhar Malavali /* disable ap0 mac */ 114602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 114702be2215SGiridhar Malavali /* disable ap1 mac */ 114802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1149c9e8fd5cSMadhuranath Iyengar 1150c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1151c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1152c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1153c9e8fd5cSMadhuranath Iyengar 1154c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1155c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1156c9e8fd5cSMadhuranath Iyengar 1157c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1158c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1159c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1160c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1161c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1162c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 116302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1164c9e8fd5cSMadhuranath Iyengar 1165c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1166c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1167c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1168c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1169c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1170c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 117102be2215SGiridhar Malavali msleep(20); 1172c9e8fd5cSMadhuranath Iyengar 1173c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1174a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1175a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1176a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1177a9083016SGiridhar Malavali else 1178a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1179d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1180a9083016SGiridhar Malavali 1181a9083016SGiridhar Malavali /* Read the signature value from the flash. 1182a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1183a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1184a9083016SGiridhar Malavali * that present in CRB initialize sequence 1185a9083016SGiridhar Malavali */ 1186a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1187a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11887c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11897c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1190a9083016SGiridhar Malavali return -1; 1191a9083016SGiridhar Malavali } 1192a9083016SGiridhar Malavali 1193a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 119400adc9a0SSaurav Kashyap * Number of entries = upper 16 bits 1195a9083016SGiridhar Malavali */ 1196a9083016SGiridhar Malavali offset = n & 0xffffU; 1197a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1198a9083016SGiridhar Malavali 119900adc9a0SSaurav Kashyap /* number of addr/value pair should not exceed 1024 entries */ 1200a9083016SGiridhar Malavali if (n >= 1024) { 12017c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 12027c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1203a9083016SGiridhar Malavali return -1; 1204a9083016SGiridhar Malavali } 1205a9083016SGiridhar Malavali 12067c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12077c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1208a9083016SGiridhar Malavali 1209a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1210a9083016SGiridhar Malavali if (buf == NULL) { 12117c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12127c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1213a9083016SGiridhar Malavali return -1; 1214a9083016SGiridhar Malavali } 1215a9083016SGiridhar Malavali 1216a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1217a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1218a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1219a9083016SGiridhar Malavali kfree(buf); 1220a9083016SGiridhar Malavali return -1; 1221a9083016SGiridhar Malavali } 1222a9083016SGiridhar Malavali 1223a9083016SGiridhar Malavali buf[i].addr = addr; 1224a9083016SGiridhar Malavali buf[i].data = val; 1225a9083016SGiridhar Malavali } 1226a9083016SGiridhar Malavali 1227a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1228a9083016SGiridhar Malavali /* Translate internal CRB initialization 1229a9083016SGiridhar Malavali * address to PCI bus address 1230a9083016SGiridhar Malavali */ 1231a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1232a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1233a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1234a9083016SGiridhar Malavali * some of them are skipped 1235a9083016SGiridhar Malavali */ 1236a9083016SGiridhar Malavali 1237a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1238a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1239a9083016SGiridhar Malavali continue; 1240a9083016SGiridhar Malavali 1241a9083016SGiridhar Malavali /* do not reset PCI */ 1242a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1243a9083016SGiridhar Malavali continue; 1244a9083016SGiridhar Malavali 1245a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1246a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1247a9083016SGiridhar Malavali continue; 1248a9083016SGiridhar Malavali 1249a9083016SGiridhar Malavali /* skip the function enable register */ 1250a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1251a9083016SGiridhar Malavali continue; 1252a9083016SGiridhar Malavali 1253a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1254a9083016SGiridhar Malavali continue; 1255a9083016SGiridhar Malavali 1256a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1257a9083016SGiridhar Malavali continue; 1258a9083016SGiridhar Malavali 1259a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1260a9083016SGiridhar Malavali continue; 1261a9083016SGiridhar Malavali 1262a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12637c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 12647c3df132SSaurav Kashyap "Unknow addr: 0x%08lx.\n", buf[i].addr); 1265a9083016SGiridhar Malavali continue; 1266a9083016SGiridhar Malavali } 1267a9083016SGiridhar Malavali 1268a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1269a9083016SGiridhar Malavali 1270a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1271a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1272a9083016SGiridhar Malavali */ 1273a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1274a9083016SGiridhar Malavali msleep(1000); 1275a9083016SGiridhar Malavali 1276a9083016SGiridhar Malavali /* ISP requires millisec delay between 1277a9083016SGiridhar Malavali * successive CRB register updation 1278a9083016SGiridhar Malavali */ 1279a9083016SGiridhar Malavali msleep(1); 1280a9083016SGiridhar Malavali } 1281a9083016SGiridhar Malavali 1282a9083016SGiridhar Malavali kfree(buf); 1283a9083016SGiridhar Malavali 1284a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1285a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1286a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1287a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1288a9083016SGiridhar Malavali 1289a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1290a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1291a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1292a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1293a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1294a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1295a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1296a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1297a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1298a9083016SGiridhar Malavali return 0; 1299a9083016SGiridhar Malavali } 1300a9083016SGiridhar Malavali 130177e334d2SGiridhar Malavali static int 130277e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 130377e334d2SGiridhar Malavali u64 off, void *data, int size) 130477e334d2SGiridhar Malavali { 130577e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 130677e334d2SGiridhar Malavali int scale, shift_amount, startword; 130777e334d2SGiridhar Malavali uint32_t temp; 130877e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 130977e334d2SGiridhar Malavali 131077e334d2SGiridhar Malavali /* 131177e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 131277e334d2SGiridhar Malavali */ 131377e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 131477e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 131577e334d2SGiridhar Malavali else { 131677e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 131777e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 131877e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 131977e334d2SGiridhar Malavali off, data, size); 132077e334d2SGiridhar Malavali } 132177e334d2SGiridhar Malavali 132277e334d2SGiridhar Malavali off0 = off & 0x7; 132377e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 132477e334d2SGiridhar Malavali sz[1] = size - sz[0]; 132577e334d2SGiridhar Malavali 132677e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 132777e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 132877e334d2SGiridhar Malavali shift_amount = 4; 132977e334d2SGiridhar Malavali scale = 2; 133077e334d2SGiridhar Malavali startword = (off & 0xf)/8; 133177e334d2SGiridhar Malavali 133277e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 133377e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 133477e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 133577e334d2SGiridhar Malavali return -1; 133677e334d2SGiridhar Malavali } 133777e334d2SGiridhar Malavali 133877e334d2SGiridhar Malavali switch (size) { 133977e334d2SGiridhar Malavali case 1: 134077e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 134177e334d2SGiridhar Malavali break; 134277e334d2SGiridhar Malavali case 2: 134377e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 134477e334d2SGiridhar Malavali break; 134577e334d2SGiridhar Malavali case 4: 134677e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 134777e334d2SGiridhar Malavali break; 134877e334d2SGiridhar Malavali case 8: 134977e334d2SGiridhar Malavali default: 135077e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 135177e334d2SGiridhar Malavali break; 135277e334d2SGiridhar Malavali } 135377e334d2SGiridhar Malavali 135477e334d2SGiridhar Malavali if (sz[0] == 8) { 135577e334d2SGiridhar Malavali word[startword] = tmpw; 135677e334d2SGiridhar Malavali } else { 135777e334d2SGiridhar Malavali word[startword] &= 135877e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 135977e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 136077e334d2SGiridhar Malavali } 136177e334d2SGiridhar Malavali if (sz[1] != 0) { 136277e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 136377e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 136477e334d2SGiridhar Malavali } 136577e334d2SGiridhar Malavali 136677e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 136777e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 136877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 136977e334d2SGiridhar Malavali temp = 0; 137077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 137177e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 137277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 137377e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 137477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 137577e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 137677e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 137777e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 137877e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 137977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 138077e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 138177e334d2SGiridhar Malavali 138277e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 138377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 138477e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 138577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 138677e334d2SGiridhar Malavali 138777e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 138877e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 138977e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 139077e334d2SGiridhar Malavali break; 139177e334d2SGiridhar Malavali } 139277e334d2SGiridhar Malavali 139377e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 139477e334d2SGiridhar Malavali if (printk_ratelimit()) 139577e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 13967c3df132SSaurav Kashyap "failed to write through agent.\n"); 139777e334d2SGiridhar Malavali ret = -1; 139877e334d2SGiridhar Malavali break; 139977e334d2SGiridhar Malavali } 140077e334d2SGiridhar Malavali } 140177e334d2SGiridhar Malavali 140277e334d2SGiridhar Malavali return ret; 140377e334d2SGiridhar Malavali } 140477e334d2SGiridhar Malavali 140577e334d2SGiridhar Malavali static int 1406a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1407a9083016SGiridhar Malavali { 1408a9083016SGiridhar Malavali int i; 1409a9083016SGiridhar Malavali long size = 0; 14109c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14119c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1412a9083016SGiridhar Malavali u64 data; 1413a9083016SGiridhar Malavali u32 high, low; 1414a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1415a9083016SGiridhar Malavali 1416a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1417a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1418a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1419a9083016SGiridhar Malavali return -1; 1420a9083016SGiridhar Malavali } 1421a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1422a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1423a9083016SGiridhar Malavali flashaddr += 8; 1424a9083016SGiridhar Malavali memaddr += 8; 1425a9083016SGiridhar Malavali 1426a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1427a9083016SGiridhar Malavali msleep(1); 1428a9083016SGiridhar Malavali } 1429a9083016SGiridhar Malavali udelay(100); 1430a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1431a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1432a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1433a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1434a9083016SGiridhar Malavali return 0; 1435a9083016SGiridhar Malavali } 1436a9083016SGiridhar Malavali 1437a9083016SGiridhar Malavali int 1438a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1439a9083016SGiridhar Malavali u64 off, void *data, int size) 1440a9083016SGiridhar Malavali { 1441a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1442a9083016SGiridhar Malavali int shift_amount; 1443a9083016SGiridhar Malavali uint32_t temp; 1444a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1445a9083016SGiridhar Malavali 1446a9083016SGiridhar Malavali /* 1447a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1448a9083016SGiridhar Malavali */ 1449a9083016SGiridhar Malavali 1450a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1451a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1452a9083016SGiridhar Malavali else { 1453a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1454a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1455a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1456a9083016SGiridhar Malavali off, data, size); 1457a9083016SGiridhar Malavali } 1458a9083016SGiridhar Malavali 1459a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1460a9083016SGiridhar Malavali off0[0] = off & 0xf; 1461a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1462a9083016SGiridhar Malavali shift_amount = 4; 1463a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1464a9083016SGiridhar Malavali off0[1] = 0; 1465a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1466a9083016SGiridhar Malavali 1467a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1468a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1469a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1470a9083016SGiridhar Malavali temp = 0; 1471a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1472a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1473a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1474a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1475a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1476a9083016SGiridhar Malavali 1477a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1478a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1479a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1480a9083016SGiridhar Malavali break; 1481a9083016SGiridhar Malavali } 1482a9083016SGiridhar Malavali 1483a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1484a9083016SGiridhar Malavali if (printk_ratelimit()) 1485a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14867c3df132SSaurav Kashyap "failed to read through agent.\n"); 1487a9083016SGiridhar Malavali break; 1488a9083016SGiridhar Malavali } 1489a9083016SGiridhar Malavali 1490a9083016SGiridhar Malavali start = off0[i] >> 2; 1491a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1492a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1493a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1494a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1495a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1496a9083016SGiridhar Malavali } 1497a9083016SGiridhar Malavali } 1498a9083016SGiridhar Malavali 1499a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1500a9083016SGiridhar Malavali return -1; 1501a9083016SGiridhar Malavali 1502a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1503a9083016SGiridhar Malavali val = word[0]; 1504a9083016SGiridhar Malavali } else { 1505a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1506a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1507a9083016SGiridhar Malavali } 1508a9083016SGiridhar Malavali 1509a9083016SGiridhar Malavali switch (size) { 1510a9083016SGiridhar Malavali case 1: 1511a9083016SGiridhar Malavali *(uint8_t *)data = val; 1512a9083016SGiridhar Malavali break; 1513a9083016SGiridhar Malavali case 2: 1514a9083016SGiridhar Malavali *(uint16_t *)data = val; 1515a9083016SGiridhar Malavali break; 1516a9083016SGiridhar Malavali case 4: 1517a9083016SGiridhar Malavali *(uint32_t *)data = val; 1518a9083016SGiridhar Malavali break; 1519a9083016SGiridhar Malavali case 8: 1520a9083016SGiridhar Malavali *(uint64_t *)data = val; 1521a9083016SGiridhar Malavali break; 1522a9083016SGiridhar Malavali } 1523a9083016SGiridhar Malavali return 0; 1524a9083016SGiridhar Malavali } 1525a9083016SGiridhar Malavali 1526a9083016SGiridhar Malavali 15279c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15289c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15299c2b2975SHarish Zunjarrao { 15309c2b2975SHarish Zunjarrao uint32_t i; 15319c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15329c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15339c2b2975SHarish Zunjarrao __le32 offset; 15349c2b2975SHarish Zunjarrao __le32 tab_type; 15359c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15369c2b2975SHarish Zunjarrao 15379c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15389c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15399c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15409c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15419c2b2975SHarish Zunjarrao 15429c2b2975SHarish Zunjarrao if (tab_type == section) 15439c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15449c2b2975SHarish Zunjarrao } 15459c2b2975SHarish Zunjarrao 15469c2b2975SHarish Zunjarrao return NULL; 15479c2b2975SHarish Zunjarrao } 15489c2b2975SHarish Zunjarrao 15499c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15509c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15519c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15529c2b2975SHarish Zunjarrao { 15539c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15549c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15559c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15569c2b2975SHarish Zunjarrao __le32 offset; 15579c2b2975SHarish Zunjarrao 15589c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15599c2b2975SHarish Zunjarrao if (!tab_desc) 15609c2b2975SHarish Zunjarrao return NULL; 15619c2b2975SHarish Zunjarrao 15629c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15639c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15649c2b2975SHarish Zunjarrao 15659c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15669c2b2975SHarish Zunjarrao } 15679c2b2975SHarish Zunjarrao 15689c2b2975SHarish Zunjarrao static u8 * 15699c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15709c2b2975SHarish Zunjarrao { 15719c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15729c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15739c2b2975SHarish Zunjarrao 15749c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15759c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15769c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15779c2b2975SHarish Zunjarrao if (uri_desc) 15789c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15799c2b2975SHarish Zunjarrao } 15809c2b2975SHarish Zunjarrao 15819c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15829c2b2975SHarish Zunjarrao } 15839c2b2975SHarish Zunjarrao 15849c2b2975SHarish Zunjarrao static __le32 15859c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15869c2b2975SHarish Zunjarrao { 15879c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15889c2b2975SHarish Zunjarrao 15899c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15909c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15919c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15929c2b2975SHarish Zunjarrao if (uri_desc) 15939c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 15949c2b2975SHarish Zunjarrao } 15959c2b2975SHarish Zunjarrao 15969c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15979c2b2975SHarish Zunjarrao } 15989c2b2975SHarish Zunjarrao 15999c2b2975SHarish Zunjarrao static u8 * 16009c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 16019c2b2975SHarish Zunjarrao { 16029c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 16039c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16049c2b2975SHarish Zunjarrao 16059c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16069c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16079c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16089c2b2975SHarish Zunjarrao if (uri_desc) 16099c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16109c2b2975SHarish Zunjarrao } 16119c2b2975SHarish Zunjarrao 16129c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16139c2b2975SHarish Zunjarrao } 16149c2b2975SHarish Zunjarrao 1615a9083016SGiridhar Malavali /* PCI related functions */ 1616a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1617a9083016SGiridhar Malavali { 1618a9083016SGiridhar Malavali unsigned long val = 0; 1619a9083016SGiridhar Malavali u32 control; 1620a9083016SGiridhar Malavali 1621a9083016SGiridhar Malavali switch (region) { 1622a9083016SGiridhar Malavali case 0: 1623a9083016SGiridhar Malavali val = 0; 1624a9083016SGiridhar Malavali break; 1625a9083016SGiridhar Malavali case 1: 1626a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1627a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1628a9083016SGiridhar Malavali break; 1629a9083016SGiridhar Malavali } 1630a9083016SGiridhar Malavali return val; 1631a9083016SGiridhar Malavali } 1632a9083016SGiridhar Malavali 1633a9083016SGiridhar Malavali 1634a9083016SGiridhar Malavali int 1635a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1636a9083016SGiridhar Malavali { 1637a9083016SGiridhar Malavali uint32_t len = 0; 1638a9083016SGiridhar Malavali 1639a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16407c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16417c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1642a9083016SGiridhar Malavali goto iospace_error_exit; 1643a9083016SGiridhar Malavali } 1644a9083016SGiridhar Malavali 1645a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1646a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16477c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16487c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1649a9083016SGiridhar Malavali goto iospace_error_exit; 1650a9083016SGiridhar Malavali } 1651a9083016SGiridhar Malavali 1652a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1653a9083016SGiridhar Malavali ha->nx_pcibase = 1654a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1655a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16567c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16577c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1658a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1659a9083016SGiridhar Malavali goto iospace_error_exit; 1660a9083016SGiridhar Malavali } 1661a9083016SGiridhar Malavali 1662a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1663a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1664a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1665a9083016SGiridhar Malavali 1666a9083016SGiridhar Malavali if (!ql2xdbwr) { 1667a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1668a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1669a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1670a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16717c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16727c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1673a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1674a9083016SGiridhar Malavali goto iospace_error_exit; 1675a9083016SGiridhar Malavali } 1676a9083016SGiridhar Malavali 1677a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1678a9083016SGiridhar Malavali * door bell read and write pointer 1679a9083016SGiridhar Malavali */ 1680a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1681a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1682a9083016SGiridhar Malavali } else { 1683a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1684a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1685a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1686a9083016SGiridhar Malavali } 1687a9083016SGiridhar Malavali 1688a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1689a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 16907c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 16917c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 16927c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1693d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 16947c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 16957c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 16967c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 16977c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1698d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 16997c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1700a9083016SGiridhar Malavali return 0; 1701a9083016SGiridhar Malavali 1702a9083016SGiridhar Malavali iospace_error_exit: 1703a9083016SGiridhar Malavali return -ENOMEM; 1704a9083016SGiridhar Malavali } 1705a9083016SGiridhar Malavali 1706a9083016SGiridhar Malavali /* GS related functions */ 1707a9083016SGiridhar Malavali 1708a9083016SGiridhar Malavali /* Initialization related functions */ 1709a9083016SGiridhar Malavali 1710a9083016SGiridhar Malavali /** 1711a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1712a9083016SGiridhar Malavali * @ha: HA context 1713a9083016SGiridhar Malavali * 1714a9083016SGiridhar Malavali * Returns 0 on success. 1715a9083016SGiridhar Malavali */ 1716a9083016SGiridhar Malavali int 1717a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1718a9083016SGiridhar Malavali { 1719a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1720a9083016SGiridhar Malavali int ret; 1721a9083016SGiridhar Malavali 1722a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1723a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1724a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17257c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 1726d8424f68SJoe Perches "Chip revision:%d.\n", 17277c3df132SSaurav Kashyap ha->chip_revision); 1728a9083016SGiridhar Malavali return 0; 1729a9083016SGiridhar Malavali } 1730a9083016SGiridhar Malavali 1731a9083016SGiridhar Malavali /** 1732a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1733a9083016SGiridhar Malavali * @ha: HA context 1734a9083016SGiridhar Malavali * 1735a9083016SGiridhar Malavali * Returns 0 on success. 1736a9083016SGiridhar Malavali */ 1737a9083016SGiridhar Malavali void 1738a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1739a9083016SGiridhar Malavali { 1740a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1741a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1742a9083016SGiridhar Malavali } 1743a9083016SGiridhar Malavali 1744a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1745a9083016SGiridhar Malavali { 1746a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1747a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1748a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1749a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1750a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1751a9083016SGiridhar Malavali 1752a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1753a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1754a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1755a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1756a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1757a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1758a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1759a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1760a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1761a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1762a9083016SGiridhar Malavali 1763a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1764a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1765a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1766a9083016SGiridhar Malavali } 1767a9083016SGiridhar Malavali 176877e334d2SGiridhar Malavali static int 176977e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1770a9083016SGiridhar Malavali { 1771a9083016SGiridhar Malavali u64 *ptr64; 1772a9083016SGiridhar Malavali u32 i, flashaddr, size; 1773a9083016SGiridhar Malavali __le64 data; 1774a9083016SGiridhar Malavali 1775a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1776a9083016SGiridhar Malavali 17779c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1778a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1779a9083016SGiridhar Malavali 1780a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1781a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17829c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17839c2b2975SHarish Zunjarrao return -EIO; 1784a9083016SGiridhar Malavali flashaddr += 8; 1785a9083016SGiridhar Malavali } 1786a9083016SGiridhar Malavali 1787a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 17889c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 17899c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1790a9083016SGiridhar Malavali 1791a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1792a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1793a9083016SGiridhar Malavali 1794a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1795a9083016SGiridhar Malavali return -EIO; 1796a9083016SGiridhar Malavali flashaddr += 8; 1797a9083016SGiridhar Malavali } 17989c2b2975SHarish Zunjarrao udelay(100); 1799a9083016SGiridhar Malavali 1800a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1801a9083016SGiridhar Malavali * at a specified offset to indicate 1802a9083016SGiridhar Malavali * that all data is written and 1803a9083016SGiridhar Malavali * ready for firmware to initialize. 1804a9083016SGiridhar Malavali */ 18059c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1806a9083016SGiridhar Malavali 18079c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1808a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1809a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18109c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18119c2b2975SHarish Zunjarrao return 0; 18129c2b2975SHarish Zunjarrao } 18139c2b2975SHarish Zunjarrao 18149c2b2975SHarish Zunjarrao static int 18159c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18169c2b2975SHarish Zunjarrao { 18179c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18189c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18199c2b2975SHarish Zunjarrao uint32_t i; 18209c2b2975SHarish Zunjarrao __le32 entries; 18219c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18229c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18239c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18249c2b2975SHarish Zunjarrao int mn_present = 0; 18259c2b2975SHarish Zunjarrao uint32_t flagbit; 18269c2b2975SHarish Zunjarrao 18279c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18289c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18299c2b2975SHarish Zunjarrao if (!ptab_desc) 18309c2b2975SHarish Zunjarrao return -1; 18319c2b2975SHarish Zunjarrao 18329c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18339c2b2975SHarish Zunjarrao 18349c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18359c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18369c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18379c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18389c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18399c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18409c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18419c2b2975SHarish Zunjarrao 18429c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18439c2b2975SHarish Zunjarrao 18449c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18459c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18469c2b2975SHarish Zunjarrao return 0; 18479c2b2975SHarish Zunjarrao } 18489c2b2975SHarish Zunjarrao } 18499c2b2975SHarish Zunjarrao return -1; 18509c2b2975SHarish Zunjarrao } 18519c2b2975SHarish Zunjarrao 1852fa492630SSaurav Kashyap static int 18539c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18549c2b2975SHarish Zunjarrao { 18559c2b2975SHarish Zunjarrao __le32 val; 18569c2b2975SHarish Zunjarrao uint32_t min_size; 18579c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18589c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18599c2b2975SHarish Zunjarrao 18609c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18619c2b2975SHarish Zunjarrao 18629c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18639c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18649c2b2975SHarish Zunjarrao return -EINVAL; 18659c2b2975SHarish Zunjarrao 18669c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18679c2b2975SHarish Zunjarrao } else { 18689c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18699c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18709c2b2975SHarish Zunjarrao return -EINVAL; 18719c2b2975SHarish Zunjarrao 18729c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18739c2b2975SHarish Zunjarrao } 18749c2b2975SHarish Zunjarrao 18759c2b2975SHarish Zunjarrao if (fw->size < min_size) 18769c2b2975SHarish Zunjarrao return -EINVAL; 1877a9083016SGiridhar Malavali return 0; 1878a9083016SGiridhar Malavali } 1879a9083016SGiridhar Malavali 188077e334d2SGiridhar Malavali static int 188177e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1882a9083016SGiridhar Malavali { 1883a9083016SGiridhar Malavali u32 val = 0; 1884a9083016SGiridhar Malavali int retries = 60; 18857c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1886a9083016SGiridhar Malavali 1887a9083016SGiridhar Malavali do { 1888a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1889a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1890a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1891a9083016SGiridhar Malavali 1892a9083016SGiridhar Malavali switch (val) { 1893a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1894a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1895a9083016SGiridhar Malavali return QLA_SUCCESS; 1896a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1897a9083016SGiridhar Malavali break; 1898a9083016SGiridhar Malavali default: 1899a9083016SGiridhar Malavali break; 1900a9083016SGiridhar Malavali } 19017c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19027c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1903a9083016SGiridhar Malavali val, retries); 1904a9083016SGiridhar Malavali 1905a9083016SGiridhar Malavali msleep(500); 1906a9083016SGiridhar Malavali 1907a9083016SGiridhar Malavali } while (--retries); 1908a9083016SGiridhar Malavali 19097c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1910a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1911a9083016SGiridhar Malavali 1912a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1913a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1914a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1915a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1916a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1917a9083016SGiridhar Malavali } 1918a9083016SGiridhar Malavali 191977e334d2SGiridhar Malavali static int 192077e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1921a9083016SGiridhar Malavali { 1922a9083016SGiridhar Malavali u32 val = 0; 1923a9083016SGiridhar Malavali int retries = 60; 19247c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1925a9083016SGiridhar Malavali 1926a9083016SGiridhar Malavali do { 1927a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1928a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1929a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1930a9083016SGiridhar Malavali 1931a9083016SGiridhar Malavali switch (val) { 1932a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1933a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1934a9083016SGiridhar Malavali return QLA_SUCCESS; 1935a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1936a9083016SGiridhar Malavali break; 1937a9083016SGiridhar Malavali default: 1938a9083016SGiridhar Malavali break; 1939a9083016SGiridhar Malavali } 19407c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19417c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1942a9083016SGiridhar Malavali val, retries); 1943a9083016SGiridhar Malavali 1944a9083016SGiridhar Malavali msleep(500); 1945a9083016SGiridhar Malavali 1946a9083016SGiridhar Malavali } while (--retries); 1947a9083016SGiridhar Malavali 19487c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19497c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1950a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1951a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1952a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1953a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1954a9083016SGiridhar Malavali } 1955a9083016SGiridhar Malavali 1956a9083016SGiridhar Malavali /* ISR related functions */ 1957a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1958a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1959a9083016SGiridhar Malavali 1960a9083016SGiridhar Malavali /* 1961a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1962a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1963a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1964a9083016SGiridhar Malavali */ 196577e334d2SGiridhar Malavali static void 1966a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1967a9083016SGiridhar Malavali { 1968a9083016SGiridhar Malavali uint16_t cnt; 1969a9083016SGiridhar Malavali uint16_t __iomem *wptr; 1970a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1971a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1972a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1973a9083016SGiridhar Malavali 1974a9083016SGiridhar Malavali /* Load return mailbox registers. */ 1975a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 1976a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 1977a9083016SGiridhar Malavali 1978a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1979a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1980a9083016SGiridhar Malavali wptr++; 1981a9083016SGiridhar Malavali } 1982a9083016SGiridhar Malavali 1983cfb0919cSChad Dupuis if (!ha->mcp) 19847c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 19857c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 1986a9083016SGiridhar Malavali } 1987a9083016SGiridhar Malavali 1988a9083016SGiridhar Malavali /* 1989a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1990a9083016SGiridhar Malavali * @irq: 1991a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 1992a9083016SGiridhar Malavali * @regs: 1993a9083016SGiridhar Malavali * 1994a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 1995a9083016SGiridhar Malavali * 1996a9083016SGiridhar Malavali * Returns handled flag. 1997a9083016SGiridhar Malavali */ 1998a9083016SGiridhar Malavali irqreturn_t 1999a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2000a9083016SGiridhar Malavali { 2001a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2002a9083016SGiridhar Malavali struct qla_hw_data *ha; 2003a9083016SGiridhar Malavali struct rsp_que *rsp; 2004a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2005a9083016SGiridhar Malavali int status = 0, status1 = 0; 2006a9083016SGiridhar Malavali unsigned long flags; 2007a9083016SGiridhar Malavali unsigned long iter; 20087c3df132SSaurav Kashyap uint32_t stat = 0; 2009a9083016SGiridhar Malavali uint16_t mb[4]; 2010a9083016SGiridhar Malavali 2011a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2012a9083016SGiridhar Malavali if (!rsp) { 2013b6d0d9d5SGiridhar Malavali ql_log(ql_log_info, NULL, 0xb053, 20143256b435SChad Dupuis "%s: NULL response queue pointer.\n", __func__); 2015a9083016SGiridhar Malavali return IRQ_NONE; 2016a9083016SGiridhar Malavali } 2017a9083016SGiridhar Malavali ha = rsp->hw; 2018a9083016SGiridhar Malavali 2019a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2020a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2021a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2022a9083016SGiridhar Malavali return IRQ_NONE; 2023a9083016SGiridhar Malavali 2024a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2025a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2026a9083016SGiridhar Malavali return IRQ_NONE; 2027a9083016SGiridhar Malavali } 2028a9083016SGiridhar Malavali 2029a9083016SGiridhar Malavali /* clear the interrupt */ 2030a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2031a9083016SGiridhar Malavali 2032a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2033a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2034a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2035a9083016SGiridhar Malavali 2036a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2037a9083016SGiridhar Malavali 2038a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2039a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2040a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2041a9083016SGiridhar Malavali 2042a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2043a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2044a9083016SGiridhar Malavali 2045a9083016SGiridhar Malavali switch (stat & 0xff) { 2046a9083016SGiridhar Malavali case 0x1: 2047a9083016SGiridhar Malavali case 0x2: 2048a9083016SGiridhar Malavali case 0x10: 2049a9083016SGiridhar Malavali case 0x11: 2050a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2051a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2052a9083016SGiridhar Malavali break; 2053a9083016SGiridhar Malavali case 0x12: 2054a9083016SGiridhar Malavali mb[0] = MSW(stat); 2055a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2056a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2057a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2058a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2059a9083016SGiridhar Malavali break; 2060a9083016SGiridhar Malavali case 0x13: 2061a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2062a9083016SGiridhar Malavali break; 2063a9083016SGiridhar Malavali default: 20647c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2065a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20667c3df132SSaurav Kashyap stat & 0xff); 2067a9083016SGiridhar Malavali break; 2068a9083016SGiridhar Malavali } 2069a9083016SGiridhar Malavali } 2070a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2071a9083016SGiridhar Malavali } 2072a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2073a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2074a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2075a9083016SGiridhar Malavali 2076a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2077a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 20787c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x503d, 20797c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2080a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2081a9083016SGiridhar Malavali #endif 2082a9083016SGiridhar Malavali 2083a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2084a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2085a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2086a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2087a9083016SGiridhar Malavali } 2088a9083016SGiridhar Malavali return IRQ_HANDLED; 2089a9083016SGiridhar Malavali } 2090a9083016SGiridhar Malavali 2091a9083016SGiridhar Malavali irqreturn_t 2092a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2093a9083016SGiridhar Malavali { 2094a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2095a9083016SGiridhar Malavali struct qla_hw_data *ha; 2096a9083016SGiridhar Malavali struct rsp_que *rsp; 2097a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2098a9083016SGiridhar Malavali int status = 0; 2099a9083016SGiridhar Malavali unsigned long flags; 21007c3df132SSaurav Kashyap uint32_t stat = 0; 2101a9083016SGiridhar Malavali uint16_t mb[4]; 2102a9083016SGiridhar Malavali 2103a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2104a9083016SGiridhar Malavali if (!rsp) { 2105a9083016SGiridhar Malavali printk(KERN_INFO 21067c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2107a9083016SGiridhar Malavali return IRQ_NONE; 2108a9083016SGiridhar Malavali } 2109a9083016SGiridhar Malavali ha = rsp->hw; 2110a9083016SGiridhar Malavali 2111a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2112a9083016SGiridhar Malavali 2113a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2114a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2115a9083016SGiridhar Malavali do { 2116a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2117a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2118a9083016SGiridhar Malavali 2119a9083016SGiridhar Malavali switch (stat & 0xff) { 2120a9083016SGiridhar Malavali case 0x1: 2121a9083016SGiridhar Malavali case 0x2: 2122a9083016SGiridhar Malavali case 0x10: 2123a9083016SGiridhar Malavali case 0x11: 2124a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2125a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2126a9083016SGiridhar Malavali break; 2127a9083016SGiridhar Malavali case 0x12: 2128a9083016SGiridhar Malavali mb[0] = MSW(stat); 2129a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2130a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2131a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2132a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2133a9083016SGiridhar Malavali break; 2134a9083016SGiridhar Malavali case 0x13: 2135a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2136a9083016SGiridhar Malavali break; 2137a9083016SGiridhar Malavali default: 21387c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2139a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21407c3df132SSaurav Kashyap stat & 0xff); 2141a9083016SGiridhar Malavali break; 2142a9083016SGiridhar Malavali } 2143a9083016SGiridhar Malavali } 2144a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2145a9083016SGiridhar Malavali } while (0); 2146a9083016SGiridhar Malavali 2147a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2148a9083016SGiridhar Malavali 2149a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2150a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21517c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x5044, 21527c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2153a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2154a9083016SGiridhar Malavali #endif 2155a9083016SGiridhar Malavali 2156a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2157a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2158a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2159a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2160a9083016SGiridhar Malavali } 2161a9083016SGiridhar Malavali return IRQ_HANDLED; 2162a9083016SGiridhar Malavali } 2163a9083016SGiridhar Malavali 2164a9083016SGiridhar Malavali irqreturn_t 2165a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2166a9083016SGiridhar Malavali { 2167a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2168a9083016SGiridhar Malavali struct qla_hw_data *ha; 2169a9083016SGiridhar Malavali struct rsp_que *rsp; 2170a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 21713553d343SSaurav Kashyap unsigned long flags; 2172a9083016SGiridhar Malavali 2173a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2174a9083016SGiridhar Malavali if (!rsp) { 2175a9083016SGiridhar Malavali printk(KERN_INFO 21767c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2177a9083016SGiridhar Malavali return IRQ_NONE; 2178a9083016SGiridhar Malavali } 2179a9083016SGiridhar Malavali 2180a9083016SGiridhar Malavali ha = rsp->hw; 2181a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 21823553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2183a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2184a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2185a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 21863553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2187a9083016SGiridhar Malavali return IRQ_HANDLED; 2188a9083016SGiridhar Malavali } 2189a9083016SGiridhar Malavali 2190a9083016SGiridhar Malavali void 2191a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2192a9083016SGiridhar Malavali { 2193a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2194a9083016SGiridhar Malavali struct qla_hw_data *ha; 2195a9083016SGiridhar Malavali struct rsp_que *rsp; 2196a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2197a9083016SGiridhar Malavali int status = 0; 2198a9083016SGiridhar Malavali uint32_t stat; 2199a9083016SGiridhar Malavali uint16_t mb[4]; 2200a9083016SGiridhar Malavali unsigned long flags; 2201a9083016SGiridhar Malavali 2202a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2203a9083016SGiridhar Malavali if (!rsp) { 2204a9083016SGiridhar Malavali printk(KERN_INFO 22057c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2206a9083016SGiridhar Malavali return; 2207a9083016SGiridhar Malavali } 2208a9083016SGiridhar Malavali ha = rsp->hw; 2209a9083016SGiridhar Malavali 2210a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2211a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2212a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2213a9083016SGiridhar Malavali 2214a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2215a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2216a9083016SGiridhar Malavali switch (stat & 0xff) { 2217a9083016SGiridhar Malavali case 0x1: 2218a9083016SGiridhar Malavali case 0x2: 2219a9083016SGiridhar Malavali case 0x10: 2220a9083016SGiridhar Malavali case 0x11: 2221a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2222a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2223a9083016SGiridhar Malavali break; 2224a9083016SGiridhar Malavali case 0x12: 2225a9083016SGiridhar Malavali mb[0] = MSW(stat); 2226a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2227a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2228a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2229a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2230a9083016SGiridhar Malavali break; 2231a9083016SGiridhar Malavali case 0x13: 2232a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2233a9083016SGiridhar Malavali break; 2234a9083016SGiridhar Malavali default: 22357c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22367c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22377c3df132SSaurav Kashyap stat * 0xff); 2238a9083016SGiridhar Malavali break; 2239a9083016SGiridhar Malavali } 2240a9083016SGiridhar Malavali } 2241a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2242a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2243a9083016SGiridhar Malavali } 2244a9083016SGiridhar Malavali 2245a9083016SGiridhar Malavali void 2246a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2247a9083016SGiridhar Malavali { 2248a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2249a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2250a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2251a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2252a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2253a9083016SGiridhar Malavali ha->interrupts_on = 1; 2254a9083016SGiridhar Malavali } 2255a9083016SGiridhar Malavali 2256a9083016SGiridhar Malavali void 2257a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2258a9083016SGiridhar Malavali { 2259a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2260a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2261a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2262a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2263a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2264a9083016SGiridhar Malavali ha->interrupts_on = 0; 2265a9083016SGiridhar Malavali } 2266a9083016SGiridhar Malavali 2267a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2268a9083016SGiridhar Malavali { 2269a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2270a9083016SGiridhar Malavali 2271a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2272a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2273a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2274a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2275a9083016SGiridhar Malavali ha->curr_window = 255; 2276a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2277a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2278a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2279a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2280a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2281a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2282a9083016SGiridhar Malavali } 2283a9083016SGiridhar Malavali 2284a5b36321SLalit Chandivade inline void 22850251ce8cSSaurav Kashyap qla82xx_set_idc_version(scsi_qla_host_t *vha) 22860251ce8cSSaurav Kashyap { 22870251ce8cSSaurav Kashyap int idc_ver; 22880251ce8cSSaurav Kashyap uint32_t drv_active; 22890251ce8cSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 22900251ce8cSSaurav Kashyap 22910251ce8cSSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 22920251ce8cSSaurav Kashyap if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 22930251ce8cSSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 22940251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION); 22950251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb082, 22960251ce8cSSaurav Kashyap "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 22970251ce8cSSaurav Kashyap } else { 22980251ce8cSSaurav Kashyap idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 22990251ce8cSSaurav Kashyap if (idc_ver != QLA82XX_IDC_VERSION) 23000251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb083, 23010251ce8cSSaurav Kashyap "qla2xxx driver IDC version %d is not compatible " 23020251ce8cSSaurav Kashyap "with IDC version %d of the other drivers\n", 23030251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION, idc_ver); 23040251ce8cSSaurav Kashyap } 23050251ce8cSSaurav Kashyap } 23060251ce8cSSaurav Kashyap 23070251ce8cSSaurav Kashyap inline void 2308a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2309a9083016SGiridhar Malavali { 2310a9083016SGiridhar Malavali uint32_t drv_active; 2311a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2312a9083016SGiridhar Malavali 2313a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2314a9083016SGiridhar Malavali 2315a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2316a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 231777e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 231877e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2319a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2320a9083016SGiridhar Malavali } 232177e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2322a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2323a9083016SGiridhar Malavali } 2324a9083016SGiridhar Malavali 2325a9083016SGiridhar Malavali inline void 2326a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2327a9083016SGiridhar Malavali { 2328a9083016SGiridhar Malavali uint32_t drv_active; 2329a9083016SGiridhar Malavali 2330a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 233177e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2332a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2333a9083016SGiridhar Malavali } 2334a9083016SGiridhar Malavali 2335a9083016SGiridhar Malavali static inline int 2336a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2337a9083016SGiridhar Malavali { 2338a9083016SGiridhar Malavali uint32_t drv_state; 2339a9083016SGiridhar Malavali int rval; 2340a9083016SGiridhar Malavali 23417d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 234208de2844SGiridhar Malavali return 1; 234308de2844SGiridhar Malavali else { 2344a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 234577e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2346a9083016SGiridhar Malavali return rval; 2347a9083016SGiridhar Malavali } 234808de2844SGiridhar Malavali } 2349a9083016SGiridhar Malavali 2350a9083016SGiridhar Malavali static inline void 2351a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2352a9083016SGiridhar Malavali { 2353a9083016SGiridhar Malavali uint32_t drv_state; 2354a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2355a9083016SGiridhar Malavali 2356a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2357a9083016SGiridhar Malavali 2358a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2359a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 236077e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2361a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2362a9083016SGiridhar Malavali } 2363a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 236408de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 236508de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2366a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2367a9083016SGiridhar Malavali } 2368a9083016SGiridhar Malavali 2369a9083016SGiridhar Malavali static inline void 2370a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2371a9083016SGiridhar Malavali { 2372a9083016SGiridhar Malavali uint32_t drv_state; 2373a9083016SGiridhar Malavali 2374a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2375a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2376a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2377a9083016SGiridhar Malavali } 2378a9083016SGiridhar Malavali 2379a9083016SGiridhar Malavali static inline void 2380a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2381a9083016SGiridhar Malavali { 2382a9083016SGiridhar Malavali uint32_t qsnt_state; 2383a9083016SGiridhar Malavali 2384a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2385a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2386a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2387a9083016SGiridhar Malavali } 2388a9083016SGiridhar Malavali 2389579d12b5SSaurav Kashyap void 2390579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2391579d12b5SSaurav Kashyap { 2392579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2393579d12b5SSaurav Kashyap uint32_t qsnt_state; 2394579d12b5SSaurav Kashyap 2395579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2396579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2397579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2398579d12b5SSaurav Kashyap } 2399579d12b5SSaurav Kashyap 240077e334d2SGiridhar Malavali static int 240177e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2402a9083016SGiridhar Malavali { 2403a9083016SGiridhar Malavali int rst; 2404a9083016SGiridhar Malavali struct fw_blob *blob; 2405a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2406a9083016SGiridhar Malavali 2407a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24087c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24097c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2410a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2411a9083016SGiridhar Malavali } 2412a9083016SGiridhar Malavali udelay(500); 2413a9083016SGiridhar Malavali 2414a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2415a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2416a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2417a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2418a9083016SGiridhar Malavali 2419a9083016SGiridhar Malavali /* 2420a9083016SGiridhar Malavali * FW Load priority: 2421a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2422a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2423a9083016SGiridhar Malavali */ 2424a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2425a9083016SGiridhar Malavali goto try_blob_fw; 2426a9083016SGiridhar Malavali 24277c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24287c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2429a9083016SGiridhar Malavali 2430a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24317c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 243200adc9a0SSaurav Kashyap "Firmware loaded successfully from flash.\n"); 2433a9083016SGiridhar Malavali return QLA_SUCCESS; 2434875efad7SChad Dupuis } else { 24357c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24367c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2437a9083016SGiridhar Malavali } 2438875efad7SChad Dupuis 2439a9083016SGiridhar Malavali try_blob_fw: 24407c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24417c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2442a9083016SGiridhar Malavali 2443a9083016SGiridhar Malavali /* Load firmware blob. */ 2444a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2445a9083016SGiridhar Malavali if (!blob) { 24467c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 244700adc9a0SSaurav Kashyap "Firmware image not present.\n"); 2448a9083016SGiridhar Malavali goto fw_load_failed; 2449a9083016SGiridhar Malavali } 2450a9083016SGiridhar Malavali 24519c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24529c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24539c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24549c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24559c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24569c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24577c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24587c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24599c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24609c2b2975SHarish Zunjarrao } 24619c2b2975SHarish Zunjarrao } 24629c2b2975SHarish Zunjarrao 2463a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24647c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24657c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2466a9083016SGiridhar Malavali return QLA_SUCCESS; 2467a9083016SGiridhar Malavali } else { 24687c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24697c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2470a9083016SGiridhar Malavali blob->fw = NULL; 2471a9083016SGiridhar Malavali blob = NULL; 2472a9083016SGiridhar Malavali goto fw_load_failed; 2473a9083016SGiridhar Malavali } 2474a9083016SGiridhar Malavali return QLA_SUCCESS; 2475a9083016SGiridhar Malavali 2476a9083016SGiridhar Malavali fw_load_failed: 2477a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2478a9083016SGiridhar Malavali } 2479a9083016SGiridhar Malavali 2480a5b36321SLalit Chandivade int 2481a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2482a9083016SGiridhar Malavali { 2483a9083016SGiridhar Malavali uint16_t lnk; 2484a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2485a9083016SGiridhar Malavali 2486a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 248777e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2488a9083016SGiridhar Malavali 24893711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 24903711333dSGiridhar Malavali * of 0 before resetting the hardware 24913711333dSGiridhar Malavali */ 24923711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 24933711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 24943711333dSGiridhar Malavali 2495a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2496a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2497a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2498a9083016SGiridhar Malavali 2499a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25007c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25017c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2502a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2503a9083016SGiridhar Malavali } 2504a9083016SGiridhar Malavali 2505a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2506a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25077c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25087c3df132SSaurav Kashyap "Error during card handshake.\n"); 2509a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2510a9083016SGiridhar Malavali } 2511a9083016SGiridhar Malavali 2512a9083016SGiridhar Malavali /* Negotiated Link width */ 251310092438SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2514a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2515a9083016SGiridhar Malavali 2516a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2517a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2518a9083016SGiridhar Malavali } 2519a9083016SGiridhar Malavali 252077e334d2SGiridhar Malavali static uint32_t * 2521a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2522a9083016SGiridhar Malavali uint32_t length) 2523a9083016SGiridhar Malavali { 2524a9083016SGiridhar Malavali uint32_t i; 2525a9083016SGiridhar Malavali uint32_t val; 2526a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2527a9083016SGiridhar Malavali 2528a9083016SGiridhar Malavali /* Dword reads to flash. */ 2529a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2530a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25317c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25327c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2533a9083016SGiridhar Malavali goto done_read; 2534a9083016SGiridhar Malavali } 2535a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 2536a9083016SGiridhar Malavali } 2537a9083016SGiridhar Malavali done_read: 2538a9083016SGiridhar Malavali return dwptr; 2539a9083016SGiridhar Malavali } 2540a9083016SGiridhar Malavali 254177e334d2SGiridhar Malavali static int 2542a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2543a9083016SGiridhar Malavali { 2544a9083016SGiridhar Malavali int ret; 2545a9083016SGiridhar Malavali uint32_t val; 25467c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2547a9083016SGiridhar Malavali 2548a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2549a9083016SGiridhar Malavali if (ret < 0) { 25507c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25517c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2552a9083016SGiridhar Malavali return ret; 2553a9083016SGiridhar Malavali } 2554a9083016SGiridhar Malavali 2555a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2556a9083016SGiridhar Malavali if (ret < 0) 2557a9083016SGiridhar Malavali goto done_unprotect; 2558a9083016SGiridhar Malavali 25590547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2560a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2561a9083016SGiridhar Malavali if (ret < 0) { 25620547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2563a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2564a9083016SGiridhar Malavali } 2565a9083016SGiridhar Malavali 2566a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25677c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 25687c3df132SSaurav Kashyap "Write disable failed.\n"); 2569a9083016SGiridhar Malavali 2570a9083016SGiridhar Malavali done_unprotect: 2571d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2572a9083016SGiridhar Malavali return ret; 2573a9083016SGiridhar Malavali } 2574a9083016SGiridhar Malavali 257577e334d2SGiridhar Malavali static int 2576a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2577a9083016SGiridhar Malavali { 2578a9083016SGiridhar Malavali int ret; 2579a9083016SGiridhar Malavali uint32_t val; 25807c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2581a9083016SGiridhar Malavali 2582a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2583a9083016SGiridhar Malavali if (ret < 0) { 25847c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 25857c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2586a9083016SGiridhar Malavali return ret; 2587a9083016SGiridhar Malavali } 2588a9083016SGiridhar Malavali 2589a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2590a9083016SGiridhar Malavali if (ret < 0) 2591a9083016SGiridhar Malavali goto done_protect; 2592a9083016SGiridhar Malavali 25930547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2594a9083016SGiridhar Malavali /* LOCK all sectors */ 2595a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2596a9083016SGiridhar Malavali if (ret < 0) 25977c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 25987c3df132SSaurav Kashyap "Write status register failed.\n"); 2599a9083016SGiridhar Malavali 2600a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 26017c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 26027c3df132SSaurav Kashyap "Write disable failed.\n"); 2603a9083016SGiridhar Malavali done_protect: 2604d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2605a9083016SGiridhar Malavali return ret; 2606a9083016SGiridhar Malavali } 2607a9083016SGiridhar Malavali 260877e334d2SGiridhar Malavali static int 2609a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2610a9083016SGiridhar Malavali { 2611a9083016SGiridhar Malavali int ret = 0; 26127c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2613a9083016SGiridhar Malavali 2614a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2615a9083016SGiridhar Malavali if (ret < 0) { 26167c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26177c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2618a9083016SGiridhar Malavali return ret; 2619a9083016SGiridhar Malavali } 2620a9083016SGiridhar Malavali 2621a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2622a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2623a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2624a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2625a9083016SGiridhar Malavali 2626a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26277c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26287c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2629a9083016SGiridhar Malavali ret = -1; 2630a9083016SGiridhar Malavali goto done; 2631a9083016SGiridhar Malavali } 2632a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2633a9083016SGiridhar Malavali done: 2634d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2635a9083016SGiridhar Malavali return ret; 2636a9083016SGiridhar Malavali } 2637a9083016SGiridhar Malavali 2638a9083016SGiridhar Malavali /* 2639a9083016SGiridhar Malavali * Address and length are byte address 2640a9083016SGiridhar Malavali */ 2641a9083016SGiridhar Malavali uint8_t * 2642a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2643a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2644a9083016SGiridhar Malavali { 2645a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2646a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2647a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2648a9083016SGiridhar Malavali return buf; 2649a9083016SGiridhar Malavali } 2650a9083016SGiridhar Malavali 2651a9083016SGiridhar Malavali static int 2652a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2653a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2654a9083016SGiridhar Malavali { 2655a9083016SGiridhar Malavali int ret; 2656a9083016SGiridhar Malavali uint32_t liter; 2657a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 2658a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2659a9083016SGiridhar Malavali void *optrom = NULL; 2660a9083016SGiridhar Malavali int page_mode = 0; 2661a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2662a9083016SGiridhar Malavali 2663a9083016SGiridhar Malavali ret = -1; 2664a9083016SGiridhar Malavali 2665a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2666a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2667a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2668a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2669a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2670a9083016SGiridhar Malavali if (!optrom) { 26717c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 26727c3df132SSaurav Kashyap "Unable to allocate memory " 267300adc9a0SSaurav Kashyap "for optrom burst write (%x KB).\n", 2674a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2675a9083016SGiridhar Malavali } 2676a9083016SGiridhar Malavali } 2677a9083016SGiridhar Malavali 2678a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2679a9083016SGiridhar Malavali sec_mask = ~rest_addr; 2680a9083016SGiridhar Malavali 2681a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2682a9083016SGiridhar Malavali if (ret) { 26837c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2684a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2685a9083016SGiridhar Malavali goto write_done; 2686a9083016SGiridhar Malavali } 2687a9083016SGiridhar Malavali 2688a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2689a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2690a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2691a9083016SGiridhar Malavali 2692a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2693a9083016SGiridhar Malavali if (ret) { 26947c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 26957c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 26967c3df132SSaurav Kashyap faddr); 2697a9083016SGiridhar Malavali break; 2698a9083016SGiridhar Malavali } 2699a9083016SGiridhar Malavali } 2700a9083016SGiridhar Malavali 2701a9083016SGiridhar Malavali /* Go with burst-write. */ 2702a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2703a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2704a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2705a9083016SGiridhar Malavali 2706a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2707a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2708a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2709a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 27107c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2711a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2712a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2713a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2714a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27157c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2716a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2717a9083016SGiridhar Malavali 2718a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2719a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2720a9083016SGiridhar Malavali optrom = NULL; 2721a9083016SGiridhar Malavali } else { 2722a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2723a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2724a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2725a9083016SGiridhar Malavali continue; 2726a9083016SGiridhar Malavali } 2727a9083016SGiridhar Malavali } 2728a9083016SGiridhar Malavali 2729a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 2730a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 2731a9083016SGiridhar Malavali if (ret) { 27327c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27337c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27347c3df132SSaurav Kashyap faddr, *dwptr); 2735a9083016SGiridhar Malavali break; 2736a9083016SGiridhar Malavali } 2737a9083016SGiridhar Malavali } 2738a9083016SGiridhar Malavali 2739a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2740a9083016SGiridhar Malavali if (ret) 27417c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2742a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2743a9083016SGiridhar Malavali write_done: 2744a9083016SGiridhar Malavali if (optrom) 2745a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2746a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2747a9083016SGiridhar Malavali return ret; 2748a9083016SGiridhar Malavali } 2749a9083016SGiridhar Malavali 2750a9083016SGiridhar Malavali int 2751a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2752a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2753a9083016SGiridhar Malavali { 2754a9083016SGiridhar Malavali int rval; 2755a9083016SGiridhar Malavali 2756a9083016SGiridhar Malavali /* Suspend HBA. */ 2757a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2758a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2759a9083016SGiridhar Malavali length >> 2); 2760a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2761a9083016SGiridhar Malavali 2762a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2763a9083016SGiridhar Malavali if (rval) 2764a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2765a9083016SGiridhar Malavali else 2766a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2767a9083016SGiridhar Malavali return rval; 2768a9083016SGiridhar Malavali } 2769a9083016SGiridhar Malavali 2770a9083016SGiridhar Malavali void 27715162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2772a9083016SGiridhar Malavali { 27735162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2774a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2775a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2776a9083016SGiridhar Malavali uint32_t dbval; 2777a9083016SGiridhar Malavali 2778a9083016SGiridhar Malavali /* Adjust ring index. */ 2779a9083016SGiridhar Malavali req->ring_index++; 2780a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2781a9083016SGiridhar Malavali req->ring_index = 0; 2782a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2783a9083016SGiridhar Malavali } else 2784a9083016SGiridhar Malavali req->ring_ptr++; 2785a9083016SGiridhar Malavali 2786a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2787a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2788a9083016SGiridhar Malavali 2789a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 27906907869dSGiridhar Malavali if (ql2xdbwr) 27916907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 27926907869dSGiridhar Malavali else { 2793a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2794a9083016SGiridhar Malavali wmb(); 2795fa492630SSaurav Kashyap while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 27966907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 27976907869dSGiridhar Malavali dbval); 2798a9083016SGiridhar Malavali wmb(); 2799a9083016SGiridhar Malavali } 2800a9083016SGiridhar Malavali } 28016907869dSGiridhar Malavali } 2802a9083016SGiridhar Malavali 2803fa492630SSaurav Kashyap static void 2804fa492630SSaurav Kashyap qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2805e6a4202aSShyam Sundar { 28067c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 28077c3df132SSaurav Kashyap 2808e6a4202aSShyam Sundar if (qla82xx_rom_lock(ha)) 2809e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 28107c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 28117c3df132SSaurav Kashyap "Resetting rom_lock.\n"); 2812e6a4202aSShyam Sundar 2813e6a4202aSShyam Sundar /* 2814e6a4202aSShyam Sundar * Either we got the lock, or someone 2815e6a4202aSShyam Sundar * else died while holding it. 2816e6a4202aSShyam Sundar * In either case, unlock. 2817e6a4202aSShyam Sundar */ 2818d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2819e6a4202aSShyam Sundar } 2820e6a4202aSShyam Sundar 2821a9083016SGiridhar Malavali /* 2822a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2823a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2824a9083016SGiridhar Malavali * 2825a9083016SGiridhar Malavali * Note: 2826a9083016SGiridhar Malavali * IDC lock must be held upon entry 2827a9083016SGiridhar Malavali * 2828a9083016SGiridhar Malavali * Return: 2829a9083016SGiridhar Malavali * Success : 0 2830a9083016SGiridhar Malavali * Failed : 1 2831a9083016SGiridhar Malavali */ 2832a9083016SGiridhar Malavali static int 2833a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2834a9083016SGiridhar Malavali { 2835e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 2836e6a4202aSShyam Sundar int i, timeout; 2837a9083016SGiridhar Malavali uint32_t old_count, count; 2838a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2839e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 2840a9083016SGiridhar Malavali 2841e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2842a9083016SGiridhar Malavali 2843a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2844a9083016SGiridhar Malavali 2845a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 2846a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 2847a9083016SGiridhar Malavali if (timeout) { 2848a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 28497d613ac6SSantosh Vernekar QLA8XXX_DEV_FAILED); 2850a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2851a9083016SGiridhar Malavali } 2852a9083016SGiridhar Malavali 2853a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2854a9083016SGiridhar Malavali if (count != old_count) 2855e6a4202aSShyam Sundar peg_stuck = 0; 2856e6a4202aSShyam Sundar } 2857e6a4202aSShyam Sundar 2858e6a4202aSShyam Sundar if (need_reset) { 2859e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 2860e6a4202aSShyam Sundar if (peg_stuck) 2861e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2862e6a4202aSShyam Sundar goto dev_initialize; 2863e6a4202aSShyam Sundar } else { 2864e6a4202aSShyam Sundar /* Start of day for this ha context. */ 2865e6a4202aSShyam Sundar if (peg_stuck) { 2866e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 2867e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2868e6a4202aSShyam Sundar goto dev_initialize; 2869e6a4202aSShyam Sundar } else 2870e6a4202aSShyam Sundar /* Firmware already running. */ 2871a9083016SGiridhar Malavali goto dev_ready; 2872a9083016SGiridhar Malavali } 2873a9083016SGiridhar Malavali 2874e6a4202aSShyam Sundar return rval; 2875e6a4202aSShyam Sundar 2876a9083016SGiridhar Malavali dev_initialize: 2877a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28787c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28797c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 28807d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2881a9083016SGiridhar Malavali 2882a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2883a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2884a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2885a9083016SGiridhar Malavali 2886a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 28877c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 28887c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2889a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 28907d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2891a9083016SGiridhar Malavali return rval; 2892a9083016SGiridhar Malavali } 2893a9083016SGiridhar Malavali 2894a9083016SGiridhar Malavali dev_ready: 28957c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 28967c3df132SSaurav Kashyap "HW State: READY.\n"); 28977d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2898a9083016SGiridhar Malavali 2899a9083016SGiridhar Malavali return QLA_SUCCESS; 2900a9083016SGiridhar Malavali } 2901a9083016SGiridhar Malavali 2902579d12b5SSaurav Kashyap /* 2903579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2904579d12b5SSaurav Kashyap * Code to start quiescence sequence 2905579d12b5SSaurav Kashyap * 2906579d12b5SSaurav Kashyap * Note: 2907579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2908579d12b5SSaurav Kashyap * 2909579d12b5SSaurav Kashyap * Return: void 2910579d12b5SSaurav Kashyap */ 2911579d12b5SSaurav Kashyap 2912579d12b5SSaurav Kashyap static void 2913579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2914579d12b5SSaurav Kashyap { 2915579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2916579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2917579d12b5SSaurav Kashyap unsigned long reset_timeout; 2918579d12b5SSaurav Kashyap 2919579d12b5SSaurav Kashyap if (vha->flags.online) { 2920579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 29218fcd6b8bSChad Dupuis qla2x00_quiesce_io(vha); 2922579d12b5SSaurav Kashyap } 2923579d12b5SSaurav Kashyap 2924579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2925579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2926579d12b5SSaurav Kashyap 2927579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2928579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2929579d12b5SSaurav Kashyap 2930579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2931579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2932579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2933579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2934579d12b5SSaurav Kashyap 2935579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2936579d12b5SSaurav Kashyap 2937579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2938579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2939579d12b5SSaurav Kashyap * changing the state to DEV_READY 2940579d12b5SSaurav Kashyap */ 29417c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29425f28d2d7SSaurav Kashyap "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 29435f28d2d7SSaurav Kashyap "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 29447c3df132SSaurav Kashyap drv_active, drv_state); 2945579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 29467d613ac6SSantosh Vernekar QLA8XXX_DEV_READY); 29477c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29487c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2949579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2950579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2951579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2952579d12b5SSaurav Kashyap 2953579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2954579d12b5SSaurav Kashyap return; 2955579d12b5SSaurav Kashyap } 2956579d12b5SSaurav Kashyap 2957579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2958579d12b5SSaurav Kashyap msleep(1000); 2959579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2960579d12b5SSaurav Kashyap 2961579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2962579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2963579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2964579d12b5SSaurav Kashyap } 2965579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2966579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 29677d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 29687c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29697c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 29707d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2971579d12b5SSaurav Kashyap } 2972579d12b5SSaurav Kashyap } 2973579d12b5SSaurav Kashyap 2974579d12b5SSaurav Kashyap /* 2975579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2976579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2977579d12b5SSaurav Kashyap * 2978579d12b5SSaurav Kashyap * Note: 2979579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2980579d12b5SSaurav Kashyap * 2981579d12b5SSaurav Kashyap * Return: 2982579d12b5SSaurav Kashyap * Changed device state. 2983579d12b5SSaurav Kashyap */ 2984579d12b5SSaurav Kashyap uint32_t 2985579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2986579d12b5SSaurav Kashyap { 2987579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2988579d12b5SSaurav Kashyap uint32_t dev_state; 2989579d12b5SSaurav Kashyap 2990579d12b5SSaurav Kashyap do { 2991579d12b5SSaurav Kashyap msleep(1000); 2992579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2993579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2994579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2995579d12b5SSaurav Kashyap } while (dev_state == curr_state); 2996579d12b5SSaurav Kashyap 2997579d12b5SSaurav Kashyap return dev_state; 2998579d12b5SSaurav Kashyap } 2999579d12b5SSaurav Kashyap 30007d613ac6SSantosh Vernekar void 30017d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3002a9083016SGiridhar Malavali { 3003a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3004a9083016SGiridhar Malavali 3005a9083016SGiridhar Malavali /* Disable the board */ 30067c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 30077c3df132SSaurav Kashyap "Disabling the board.\n"); 3008a9083016SGiridhar Malavali 30091459c0e1SSaurav Kashyap if (IS_QLA82XX(ha)) { 3010b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3011b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 30121459c0e1SSaurav Kashyap } 3013b963752fSGiridhar Malavali 3014a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3015a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3016a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3017a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3018a9083016SGiridhar Malavali vha->flags.online = 0; 3019a9083016SGiridhar Malavali vha->flags.init_done = 0; 3020a9083016SGiridhar Malavali } 3021a9083016SGiridhar Malavali 3022a9083016SGiridhar Malavali /* 3023a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3024a9083016SGiridhar Malavali * Code to start reset sequence 3025a9083016SGiridhar Malavali * 3026a9083016SGiridhar Malavali * Note: 3027a9083016SGiridhar Malavali * IDC lock must be held upon entry 3028a9083016SGiridhar Malavali * 3029a9083016SGiridhar Malavali * Return: 3030a9083016SGiridhar Malavali * Success : 0 3031a9083016SGiridhar Malavali * Failed : 1 3032a9083016SGiridhar Malavali */ 3033a9083016SGiridhar Malavali static void 3034a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3035a9083016SGiridhar Malavali { 3036e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3037e5fdae55SChad Dupuis uint32_t active_mask = 0; 3038a9083016SGiridhar Malavali unsigned long reset_timeout; 3039a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3040a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3041a9083016SGiridhar Malavali 3042a9083016SGiridhar Malavali if (vha->flags.online) { 3043a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3044a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3045a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3046a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3047a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3048a9083016SGiridhar Malavali } 3049a9083016SGiridhar Malavali 305008de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30517d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_owner) { 305208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 305308de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3054a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 305508de2844SGiridhar Malavali } else { 305608de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 305708de2844SGiridhar Malavali drv_active &= active_mask; 305808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 305908de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 306008de2844SGiridhar Malavali } 3061a9083016SGiridhar Malavali 3062a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 30637d613ac6SSantosh Vernekar reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3064a9083016SGiridhar Malavali 3065a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3066a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 306708de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3068a9083016SGiridhar Malavali 306908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 307008de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 307108de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 307208de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 307308de2844SGiridhar Malavali 307408de2844SGiridhar Malavali while (drv_state != drv_active && 30757d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_INITIALIZING) { 3076a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30777c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30787c3df132SSaurav Kashyap "Reset timeout.\n"); 3079a9083016SGiridhar Malavali break; 3080a9083016SGiridhar Malavali } 3081a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3082a9083016SGiridhar Malavali msleep(1000); 3083a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3084a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3085a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30867d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 308708de2844SGiridhar Malavali drv_active &= active_mask; 308808de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3089a9083016SGiridhar Malavali } 3090a9083016SGiridhar Malavali 309108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 309208de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 309308de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 309408de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 309508de2844SGiridhar Malavali 30967c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 30977c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 30987c3df132SSaurav Kashyap dev_state, 309908de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3100f1af6208SGiridhar Malavali 3101a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 31027d613ac6SSantosh Vernekar if (dev_state != QLA8XXX_DEV_INITIALIZING && 31037d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_COLD) { 31047c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 31057c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 31067d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3107f4e1648aSVikas Chaudhary qla82xx_set_rst_ready(ha); 310808de2844SGiridhar Malavali if (ql2xmdenable) { 310908de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 311008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 3111b6d0d9d5SGiridhar Malavali "Minidump not collected.\n"); 311208de2844SGiridhar Malavali } else 311308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 311408de2844SGiridhar Malavali "Minidump disabled.\n"); 3115a9083016SGiridhar Malavali } 3116a9083016SGiridhar Malavali } 3117a9083016SGiridhar Malavali 31183173167fSGiridhar Malavali int 311908de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 312008de2844SGiridhar Malavali { 312108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 312208de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 31233173167fSGiridhar Malavali int rval = QLA_SUCCESS; 312408de2844SGiridhar Malavali 31253173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 31263173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 31273173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 31283173167fSGiridhar Malavali 31296246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31303173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31313173167fSGiridhar Malavali return rval; 31323173167fSGiridhar Malavali 31333173167fSGiridhar Malavali if (ql2xmdenable) { 313408de2844SGiridhar Malavali if (!ha->fw_dumped) { 313508de2844SGiridhar Malavali if (fw_major_version != ha->fw_major_version || 313608de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 313708de2844SGiridhar Malavali fw_subminor_version != ha->fw_subminor_version) { 313808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02d, 313908de2844SGiridhar Malavali "Firmware version differs " 314008de2844SGiridhar Malavali "Previous version: %d:%d:%d - " 314108de2844SGiridhar Malavali "New version: %d:%d:%d\n", 31429bc3bf27SGiridhar Malavali fw_major_version, fw_minor_version, 31439bc3bf27SGiridhar Malavali fw_subminor_version, 314408de2844SGiridhar Malavali ha->fw_major_version, 31453173167fSGiridhar Malavali ha->fw_minor_version, 31469bc3bf27SGiridhar Malavali ha->fw_subminor_version); 314708de2844SGiridhar Malavali /* Release MiniDump resources */ 314808de2844SGiridhar Malavali qla82xx_md_free(vha); 314908de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 315008de2844SGiridhar Malavali qla82xx_md_prep(vha); 31512e264269SGiridhar Malavali } 315208de2844SGiridhar Malavali } else 315308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3154d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 315508de2844SGiridhar Malavali } 31563173167fSGiridhar Malavali return rval; 31573173167fSGiridhar Malavali } 315808de2844SGiridhar Malavali 315908de2844SGiridhar Malavali 3160fa492630SSaurav Kashyap static int 3161a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3162a9083016SGiridhar Malavali { 31637190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31647190575fSGiridhar Malavali int status = 0; 3165a9083016SGiridhar Malavali 31667190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31677190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3168a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31697c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31707c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31717c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31727c3df132SSaurav Kashyap "returning status=%d.\n", status); 31737190575fSGiridhar Malavali return status; 31747c3df132SSaurav Kashyap } 3175a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3176a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3177a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3178a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3179a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31807190575fSGiridhar Malavali status = 1; 3181a9083016SGiridhar Malavali } 3182efa786ccSLalit Chandivade } else 3183efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3184a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 31857c3df132SSaurav Kashyap if (status) 31867c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 31877c3df132SSaurav Kashyap "Returning status=%d.\n", status); 31887190575fSGiridhar Malavali return status; 3189a9083016SGiridhar Malavali } 3190a9083016SGiridhar Malavali 3191a9083016SGiridhar Malavali /* 3192a9083016SGiridhar Malavali * qla82xx_device_state_handler 3193a9083016SGiridhar Malavali * Main state handler 3194a9083016SGiridhar Malavali * 3195a9083016SGiridhar Malavali * Note: 3196a9083016SGiridhar Malavali * IDC lock must be held upon entry 3197a9083016SGiridhar Malavali * 3198a9083016SGiridhar Malavali * Return: 3199a9083016SGiridhar Malavali * Success : 0 3200a9083016SGiridhar Malavali * Failed : 1 3201a9083016SGiridhar Malavali */ 3202a9083016SGiridhar Malavali int 3203a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3204a9083016SGiridhar Malavali { 3205a9083016SGiridhar Malavali uint32_t dev_state; 320692dbf273SGiridhar Malavali uint32_t old_dev_state; 3207a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3208a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3209a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 321092dbf273SGiridhar Malavali int loopcount = 0; 3211a9083016SGiridhar Malavali 3212a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 32130251ce8cSSaurav Kashyap if (!vha->flags.init_done) { 3214a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 32150251ce8cSSaurav Kashyap qla82xx_set_idc_version(vha); 32160251ce8cSSaurav Kashyap } 3217a9083016SGiridhar Malavali 3218a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 321992dbf273SGiridhar Malavali old_dev_state = dev_state; 32207c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 32217c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32227c3df132SSaurav Kashyap dev_state, 322308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3224a9083016SGiridhar Malavali 3225a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 32267d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3227a9083016SGiridhar Malavali 3228a9083016SGiridhar Malavali while (1) { 3229a9083016SGiridhar Malavali 3230a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32317c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32327c3df132SSaurav Kashyap "Device init failed.\n"); 3233a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3234a9083016SGiridhar Malavali break; 3235a9083016SGiridhar Malavali } 3236a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 323792dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 323892dbf273SGiridhar Malavali loopcount = 0; 323992dbf273SGiridhar Malavali old_dev_state = dev_state; 324092dbf273SGiridhar Malavali } 324192dbf273SGiridhar Malavali if (loopcount < 5) { 32427c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32437c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32447c3df132SSaurav Kashyap dev_state, 324508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32467c3df132SSaurav Kashyap "Unknown"); 324792dbf273SGiridhar Malavali } 3248f1af6208SGiridhar Malavali 3249a9083016SGiridhar Malavali switch (dev_state) { 32507d613ac6SSantosh Vernekar case QLA8XXX_DEV_READY: 32517d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 0; 32527916bb90SChad Dupuis goto rel_lock; 32537d613ac6SSantosh Vernekar case QLA8XXX_DEV_COLD: 3254a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 325508de2844SGiridhar Malavali break; 32567d613ac6SSantosh Vernekar case QLA8XXX_DEV_INITIALIZING: 3257a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3258a9083016SGiridhar Malavali msleep(1000); 3259a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3260a9083016SGiridhar Malavali break; 32617d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_RESET: 3262ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3263a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3264c8582ad9SSaurav Kashyap else { 3265c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3266c8582ad9SSaurav Kashyap msleep(1000); 3267c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3268c8582ad9SSaurav Kashyap } 32690060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32707d613ac6SSantosh Vernekar (ha->fcoe_dev_init_timeout * HZ); 3271a9083016SGiridhar Malavali break; 32727d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_QUIESCENT: 3273579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3274579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32757d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3276579d12b5SSaurav Kashyap * HZ); 3277579d12b5SSaurav Kashyap break; 32787d613ac6SSantosh Vernekar case QLA8XXX_DEV_QUIESCENT: 3279579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3280579d12b5SSaurav Kashyap * to get changed 3281579d12b5SSaurav Kashyap */ 3282579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 32837916bb90SChad Dupuis goto rel_lock; 3284579d12b5SSaurav Kashyap 3285a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3286a9083016SGiridhar Malavali msleep(1000); 3287a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3288579d12b5SSaurav Kashyap 3289579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32907d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3291579d12b5SSaurav Kashyap * HZ); 3292a9083016SGiridhar Malavali break; 32937d613ac6SSantosh Vernekar case QLA8XXX_DEV_FAILED: 32947d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(vha); 3295a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3296a9083016SGiridhar Malavali goto exit; 3297a9083016SGiridhar Malavali default: 3298a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3299a9083016SGiridhar Malavali msleep(1000); 3300a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3301a9083016SGiridhar Malavali } 330292dbf273SGiridhar Malavali loopcount++; 3303a9083016SGiridhar Malavali } 33047916bb90SChad Dupuis rel_lock: 3305a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 33067916bb90SChad Dupuis exit: 3307a9083016SGiridhar Malavali return rval; 3308a9083016SGiridhar Malavali } 3309a9083016SGiridhar Malavali 33105988aeb2SGiridhar Malavali static int qla82xx_check_temp(scsi_qla_host_t *vha) 33115988aeb2SGiridhar Malavali { 33125988aeb2SGiridhar Malavali uint32_t temp, temp_state, temp_val; 33135988aeb2SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 33145988aeb2SGiridhar Malavali 33155988aeb2SGiridhar Malavali temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 33165988aeb2SGiridhar Malavali temp_state = qla82xx_get_temp_state(temp); 33175988aeb2SGiridhar Malavali temp_val = qla82xx_get_temp_val(temp); 33185988aeb2SGiridhar Malavali 33195988aeb2SGiridhar Malavali if (temp_state == QLA82XX_TEMP_PANIC) { 33205988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600e, 33215988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33225988aeb2SGiridhar Malavali " maximum allowed. Hardware has been shut down.\n", 33235988aeb2SGiridhar Malavali temp_val); 33245988aeb2SGiridhar Malavali return 1; 33255988aeb2SGiridhar Malavali } else if (temp_state == QLA82XX_TEMP_WARN) { 33265988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600f, 33275988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33285988aeb2SGiridhar Malavali "operating range. Immediate action needed.\n", 33295988aeb2SGiridhar Malavali temp_val); 33305988aeb2SGiridhar Malavali } 33315988aeb2SGiridhar Malavali return 0; 33325988aeb2SGiridhar Malavali } 33335988aeb2SGiridhar Malavali 3334c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3335c8f6544eSChad Dupuis { 3336c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3337c8f6544eSChad Dupuis 3338c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3339c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33408937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3341c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3342c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 3343c8f6544eSChad Dupuis if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3344c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3345c8f6544eSChad Dupuis } 3346c8f6544eSChad Dupuis } 3347c8f6544eSChad Dupuis 3348a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3349a9083016SGiridhar Malavali { 33507190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3351a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3352a9083016SGiridhar Malavali 3353a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33547d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_hdlr_active) { 33557190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33565988aeb2SGiridhar Malavali if (qla82xx_check_temp(vha)) { 33575988aeb2SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33585988aeb2SGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 33595988aeb2SGiridhar Malavali qla82xx_clear_pending_mbx(vha); 33607d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 33617190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33627c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33637c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3364a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 33657d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3366579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33677c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33687c3df132SSaurav Kashyap "Quiescent needed.\n"); 3369579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 33707d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_FAILED && 33717916bb90SChad Dupuis !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 33727916bb90SChad Dupuis vha->flags.online == 1) { 33737916bb90SChad Dupuis ql_log(ql_log_warn, vha, 0xb055, 33747916bb90SChad Dupuis "Adapter state is failed. Offlining.\n"); 33757916bb90SChad Dupuis set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33767916bb90SChad Dupuis ha->flags.isp82xx_fw_hung = 1; 33777916bb90SChad Dupuis qla82xx_clear_pending_mbx(vha); 3378a9083016SGiridhar Malavali } else { 33797190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 338063154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 338163154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 338263154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 338363154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 33847190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 33857190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 338663154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 33877c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 33887c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 33897c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 33907c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 33917c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 33920e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 33930e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33940e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 33950e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33960e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 33970e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33980e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 33990e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34000e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 34010e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34020e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 34032cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 340410a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 340510a340e6SChad Dupuis "Firmware aborted with " 340610a340e6SChad Dupuis "error code 0x00006700. Device is " 340710a340e6SChad Dupuis "being reset.\n"); 34087190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 34097190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 34107190575fSGiridhar Malavali &vha->dpc_flags); 34117190575fSGiridhar Malavali } else { 34127c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 34137c3df132SSaurav Kashyap "Detect abort needed.\n"); 34147190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 34157190575fSGiridhar Malavali &vha->dpc_flags); 34167190575fSGiridhar Malavali } 34177190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3418c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3419c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 34207190575fSGiridhar Malavali } 3421a9083016SGiridhar Malavali } 3422a9083016SGiridhar Malavali } 3423a9083016SGiridhar Malavali } 3424a9083016SGiridhar Malavali 3425a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3426a9083016SGiridhar Malavali { 3427a9083016SGiridhar Malavali int rval; 3428a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3429a9083016SGiridhar Malavali return rval; 3430a9083016SGiridhar Malavali } 3431a9083016SGiridhar Malavali 343208de2844SGiridhar Malavali void 343308de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 343408de2844SGiridhar Malavali { 343508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 343608de2844SGiridhar Malavali uint32_t dev_state; 343708de2844SGiridhar Malavali 343808de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 34397d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_READY) { 344008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 344108de2844SGiridhar Malavali "HW State: NEED RESET\n"); 344208de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 34437d613ac6SSantosh Vernekar QLA8XXX_DEV_NEED_RESET); 34447d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 1; 344508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 344608de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 344708de2844SGiridhar Malavali } else 344808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 344908de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 345008de2844SGiridhar Malavali dev_state, 345108de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 345208de2844SGiridhar Malavali } 345308de2844SGiridhar Malavali 3454a9083016SGiridhar Malavali /* 3455a9083016SGiridhar Malavali * qla82xx_abort_isp 3456a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3457a9083016SGiridhar Malavali * 3458a9083016SGiridhar Malavali * Input: 3459a9083016SGiridhar Malavali * ha = adapter block pointer. 3460a9083016SGiridhar Malavali * 3461a9083016SGiridhar Malavali * Returns: 3462a9083016SGiridhar Malavali * 0 = success 3463a9083016SGiridhar Malavali */ 3464a9083016SGiridhar Malavali int 3465a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3466a9083016SGiridhar Malavali { 3467a9083016SGiridhar Malavali int rval; 3468a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3469a9083016SGiridhar Malavali 3470a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 34717c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 34727c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3473a9083016SGiridhar Malavali return QLA_SUCCESS; 3474a9083016SGiridhar Malavali } 34757d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 1; 3476a9083016SGiridhar Malavali 3477a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 347808de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3479a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3480a9083016SGiridhar Malavali 3481a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3482a9083016SGiridhar Malavali 3483a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3484a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3485a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3486a9083016SGiridhar Malavali 3487cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 34887190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 34897d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 0; 3490a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3491cdbb0a4fSSantosh Vernekar } 3492f1af6208SGiridhar Malavali 3493f1af6208SGiridhar Malavali if (rval) { 3494f1af6208SGiridhar Malavali vha->flags.online = 1; 3495f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3496f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 34977c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 34987c3df132SSaurav Kashyap "ISP error recover failed - board " 34997c3df132SSaurav Kashyap "disabled.\n"); 3500f1af6208SGiridhar Malavali /* 3501f1af6208SGiridhar Malavali * The next call disables the board 3502f1af6208SGiridhar Malavali * completely. 3503f1af6208SGiridhar Malavali */ 3504f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3505f1af6208SGiridhar Malavali vha->flags.online = 0; 3506f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3507f1af6208SGiridhar Malavali &vha->dpc_flags); 3508f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3509f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3510f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 35117c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 35127c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 35137c3df132SSaurav Kashyap ha->isp_abort_cnt); 3514f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3515f1af6208SGiridhar Malavali } 3516f1af6208SGiridhar Malavali } else { 3517f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 35187c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 35197c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 35207c3df132SSaurav Kashyap ha->isp_abort_cnt); 3521f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3522f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3523f1af6208SGiridhar Malavali } 3524f1af6208SGiridhar Malavali } 3525a9083016SGiridhar Malavali return rval; 3526a9083016SGiridhar Malavali } 3527a9083016SGiridhar Malavali 3528a9083016SGiridhar Malavali /* 3529a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3530a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3531a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3532a9083016SGiridhar Malavali * chip reset. 3533a9083016SGiridhar Malavali * 3534a9083016SGiridhar Malavali * Input: 3535a9083016SGiridhar Malavali * ha = adapter block pointer. 3536a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3537a9083016SGiridhar Malavali * 3538a9083016SGiridhar Malavali * Returns: 3539a9083016SGiridhar Malavali * 0 = success 3540a9083016SGiridhar Malavali */ 3541a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3542a9083016SGiridhar Malavali { 3543a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3544a9083016SGiridhar Malavali 3545a9083016SGiridhar Malavali if (vha->flags.online) { 3546a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3547a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3548a9083016SGiridhar Malavali } 3549a9083016SGiridhar Malavali 3550a9083016SGiridhar Malavali /* Stop currently executing firmware. 3551a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3552a9083016SGiridhar Malavali */ 3553a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3554a9083016SGiridhar Malavali 3555a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3556a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3557a9083016SGiridhar Malavali 3558a9083016SGiridhar Malavali return rval; 3559a9083016SGiridhar Malavali } 3560a9083016SGiridhar Malavali 3561a9083016SGiridhar Malavali /* 3562a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3563a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3564a9083016SGiridhar Malavali * 3565a9083016SGiridhar Malavali * Note: 3566a9083016SGiridhar Malavali * Does context switching here. 3567a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3568a9083016SGiridhar Malavali * 3569a9083016SGiridhar Malavali * Return: 3570a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3571a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3572a9083016SGiridhar Malavali */ 3573a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3574a9083016SGiridhar Malavali { 3575a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3576a9083016SGiridhar Malavali unsigned long wait_reset; 3577a9083016SGiridhar Malavali 3578a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3579a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3580a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3581a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3582a9083016SGiridhar Malavali 3583a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3584a9083016SGiridhar Malavali schedule_timeout(HZ); 3585a9083016SGiridhar Malavali 3586a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3587a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3588a9083016SGiridhar Malavali status = QLA_SUCCESS; 3589a9083016SGiridhar Malavali break; 3590a9083016SGiridhar Malavali } 3591a9083016SGiridhar Malavali } 35927c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3593d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3594a9083016SGiridhar Malavali 3595a9083016SGiridhar Malavali return status; 3596a9083016SGiridhar Malavali } 35977190575fSGiridhar Malavali 35987190575fSGiridhar Malavali void 35997190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 36007190575fSGiridhar Malavali { 36017190575fSGiridhar Malavali int i; 36027190575fSGiridhar Malavali unsigned long flags; 36037190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 36047190575fSGiridhar Malavali 36057190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 36067190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 36077190575fSGiridhar Malavali * detection only 36087190575fSGiridhar Malavali */ 36097190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36107190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 36117190575fSGiridhar Malavali msleep(1000); 36127190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 36137190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3614c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 36157190575fSGiridhar Malavali break; 36167190575fSGiridhar Malavali } 36177190575fSGiridhar Malavali } 36187190575fSGiridhar Malavali } 36197c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 36207c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 36217c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 36227190575fSGiridhar Malavali 36237190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 36247190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36257190575fSGiridhar Malavali int cnt, que; 36267190575fSGiridhar Malavali srb_t *sp; 36277190575fSGiridhar Malavali struct req_que *req; 36287190575fSGiridhar Malavali 36297190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36307190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36317190575fSGiridhar Malavali req = ha->req_q_map[que]; 36327190575fSGiridhar Malavali if (!req) 36337190575fSGiridhar Malavali continue; 36347190575fSGiridhar Malavali for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 36357190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36367190575fSGiridhar Malavali if (sp) { 36379ba56b95SGiridhar Malavali if (!sp->u.scmd.ctx || 36387190575fSGiridhar Malavali (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 36397190575fSGiridhar Malavali spin_unlock_irqrestore( 36407190575fSGiridhar Malavali &ha->hardware_lock, flags); 36417190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 36427c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36437c3df132SSaurav Kashyap 0x00b1, 36447c3df132SSaurav Kashyap "mbx abort failed.\n"); 36457190575fSGiridhar Malavali } else { 36467c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36477c3df132SSaurav Kashyap 0x00b2, 36487c3df132SSaurav Kashyap "mbx abort success.\n"); 36497190575fSGiridhar Malavali } 36507190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36517190575fSGiridhar Malavali } 36527190575fSGiridhar Malavali } 36537190575fSGiridhar Malavali } 36547190575fSGiridhar Malavali } 36557190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 36567190575fSGiridhar Malavali 36577190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 36587190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 36597190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 36607c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 36617c3df132SSaurav Kashyap "Done wait for " 36627c3df132SSaurav Kashyap "pending commands.\n"); 36637190575fSGiridhar Malavali } 36647190575fSGiridhar Malavali } 36657190575fSGiridhar Malavali } 366608de2844SGiridhar Malavali 366708de2844SGiridhar Malavali /* Minidump related functions */ 366808de2844SGiridhar Malavali static int 366908de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 367008de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 367108de2844SGiridhar Malavali { 367208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 367308de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 367408de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 367508de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 367608de2844SGiridhar Malavali unsigned long wtime; 367708de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 367808de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 367908de2844SGiridhar Malavali int i; 368008de2844SGiridhar Malavali 368108de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 368208de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 368308de2844SGiridhar Malavali crb_addr = crb_entry->addr; 368408de2844SGiridhar Malavali 368508de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 368608de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 368708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 368808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 368908de2844SGiridhar Malavali crb_entry->value_1, 1); 369008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 369108de2844SGiridhar Malavali } 369208de2844SGiridhar Malavali 369308de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 369408de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 369508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 369608de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 369708de2844SGiridhar Malavali } 369808de2844SGiridhar Malavali 369908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 370008de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 370108de2844SGiridhar Malavali read_value &= crb_entry->value_2; 370208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 370308de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 370408de2844SGiridhar Malavali read_value |= crb_entry->value_3; 370508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 370608de2844SGiridhar Malavali } 370708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 370808de2844SGiridhar Malavali } 370908de2844SGiridhar Malavali 371008de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 371108de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 371208de2844SGiridhar Malavali read_value |= crb_entry->value_3; 371308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 371408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 371508de2844SGiridhar Malavali } 371608de2844SGiridhar Malavali 371708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 371808de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 371908de2844SGiridhar Malavali wtime = jiffies + poll_time; 372008de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 372108de2844SGiridhar Malavali 372208de2844SGiridhar Malavali do { 372308de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 372408de2844SGiridhar Malavali == crb_entry->value_1) 372508de2844SGiridhar Malavali break; 372608de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 372708de2844SGiridhar Malavali /* capturing dump failed */ 372808de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 372908de2844SGiridhar Malavali break; 373008de2844SGiridhar Malavali } else 373108de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 373208de2844SGiridhar Malavali crb_addr, 0, 0); 373308de2844SGiridhar Malavali } while (1); 373408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 373508de2844SGiridhar Malavali } 373608de2844SGiridhar Malavali 373708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 373808de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 373908de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 374008de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 374108de2844SGiridhar Malavali } else 374208de2844SGiridhar Malavali addr = crb_addr; 374308de2844SGiridhar Malavali 374408de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 374508de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 374608de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 374708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 374808de2844SGiridhar Malavali } 374908de2844SGiridhar Malavali 375008de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 375108de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 375208de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 375308de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 375408de2844SGiridhar Malavali } else 375508de2844SGiridhar Malavali addr = crb_addr; 375608de2844SGiridhar Malavali 375708de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 375808de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 375908de2844SGiridhar Malavali read_value = 376008de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 376108de2844SGiridhar Malavali } else 376208de2844SGiridhar Malavali read_value = crb_entry->value_1; 376308de2844SGiridhar Malavali 376408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 376508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 376608de2844SGiridhar Malavali } 376708de2844SGiridhar Malavali 376808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 376908de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 377008de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 377108de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 377208de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 377308de2844SGiridhar Malavali if (crb_entry->value_2) 377408de2844SGiridhar Malavali read_value &= crb_entry->value_2; 377508de2844SGiridhar Malavali read_value |= crb_entry->value_3; 377608de2844SGiridhar Malavali read_value += crb_entry->value_1; 377708de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 377808de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 377908de2844SGiridhar Malavali } 378008de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 378108de2844SGiridhar Malavali } 378208de2844SGiridhar Malavali return rval; 378308de2844SGiridhar Malavali } 378408de2844SGiridhar Malavali 378508de2844SGiridhar Malavali static void 378608de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 378708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 378808de2844SGiridhar Malavali { 378908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 379008de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 379108de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 379208de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 379308de2844SGiridhar Malavali 379408de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 379508de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 379608de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 379708de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 379808de2844SGiridhar Malavali 379908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 3800fa492630SSaurav Kashyap r_value = RD_REG_DWORD((void __iomem *) 3801fa492630SSaurav Kashyap (r_addr + ha->nx_pcibase)); 380208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 380308de2844SGiridhar Malavali r_addr += r_stride; 380408de2844SGiridhar Malavali } 380508de2844SGiridhar Malavali *d_ptr = data_ptr; 380608de2844SGiridhar Malavali } 380708de2844SGiridhar Malavali 380808de2844SGiridhar Malavali static void 380908de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 381008de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 381108de2844SGiridhar Malavali { 381208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 381308de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 381408de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 381508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 381608de2844SGiridhar Malavali 381708de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 381808de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 381908de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 382008de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 382108de2844SGiridhar Malavali s_value = mux_hdr->select_value; 382208de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 382308de2844SGiridhar Malavali 382408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 382508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 382608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 382708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 382808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 382908de2844SGiridhar Malavali s_value += s_stride; 383008de2844SGiridhar Malavali } 383108de2844SGiridhar Malavali *d_ptr = data_ptr; 383208de2844SGiridhar Malavali } 383308de2844SGiridhar Malavali 383408de2844SGiridhar Malavali static void 383508de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 383608de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 383708de2844SGiridhar Malavali { 383808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 383908de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 384008de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 384108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 384208de2844SGiridhar Malavali 384308de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 384408de2844SGiridhar Malavali r_addr = crb_hdr->addr; 384508de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 384608de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 384708de2844SGiridhar Malavali 384808de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 384908de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 385008de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 385108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 385208de2844SGiridhar Malavali r_addr += r_stride; 385308de2844SGiridhar Malavali } 385408de2844SGiridhar Malavali *d_ptr = data_ptr; 385508de2844SGiridhar Malavali } 385608de2844SGiridhar Malavali 385708de2844SGiridhar Malavali static int 385808de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 385908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 386008de2844SGiridhar Malavali { 386108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 386208de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 386308de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 386408de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 386508de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 386608de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 386708de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 386808de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 386908de2844SGiridhar Malavali 387008de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 387108de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 387208de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 387308de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 387408de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 387508de2844SGiridhar Malavali 387608de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 387708de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 387808de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 387908de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 388008de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 388108de2844SGiridhar Malavali 388208de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 388308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 388408de2844SGiridhar Malavali if (c_value_w) 388508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 388608de2844SGiridhar Malavali 388708de2844SGiridhar Malavali if (p_mask) { 388808de2844SGiridhar Malavali w_time = jiffies + p_wait; 388908de2844SGiridhar Malavali do { 389008de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 389108de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 389208de2844SGiridhar Malavali break; 389308de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 389408de2844SGiridhar Malavali /* capturing dump failed */ 389508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 389608de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 389708de2844SGiridhar Malavali "w_time: 0x%lx\n", 389808de2844SGiridhar Malavali c_value_r, p_mask, w_time); 389908de2844SGiridhar Malavali return rval; 390008de2844SGiridhar Malavali } 390108de2844SGiridhar Malavali } while (1); 390208de2844SGiridhar Malavali } 390308de2844SGiridhar Malavali 390408de2844SGiridhar Malavali addr = r_addr; 390508de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 390608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 390708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 390808de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 390908de2844SGiridhar Malavali } 391008de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 391108de2844SGiridhar Malavali } 391208de2844SGiridhar Malavali *d_ptr = data_ptr; 391308de2844SGiridhar Malavali return QLA_SUCCESS; 391408de2844SGiridhar Malavali } 391508de2844SGiridhar Malavali 391608de2844SGiridhar Malavali static void 391708de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 391808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 391908de2844SGiridhar Malavali { 392008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 392108de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 392208de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 392308de2844SGiridhar Malavali uint32_t c_value_w; 392408de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 392508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 392608de2844SGiridhar Malavali 392708de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 392808de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 392908de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 393008de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 393108de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 393208de2844SGiridhar Malavali 393308de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 393408de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 393508de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 393608de2844SGiridhar Malavali 393708de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 393808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 393908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 394008de2844SGiridhar Malavali addr = r_addr; 394108de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 394208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 394308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 394408de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 394508de2844SGiridhar Malavali } 394608de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 394708de2844SGiridhar Malavali } 394808de2844SGiridhar Malavali *d_ptr = data_ptr; 394908de2844SGiridhar Malavali } 395008de2844SGiridhar Malavali 395108de2844SGiridhar Malavali static void 395208de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 395308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 395408de2844SGiridhar Malavali { 395508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 395608de2844SGiridhar Malavali uint32_t s_addr, r_addr; 395708de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 395808de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 395908de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 396008de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 396108de2844SGiridhar Malavali 396208de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 396308de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 396408de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 396508de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 396608de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 396708de2844SGiridhar Malavali 396808de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 396908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 397008de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 397108de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 397208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 397308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 397408de2844SGiridhar Malavali r_addr += r_stride; 397508de2844SGiridhar Malavali } 397608de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 397708de2844SGiridhar Malavali } 397808de2844SGiridhar Malavali *d_ptr = data_ptr; 397908de2844SGiridhar Malavali } 398008de2844SGiridhar Malavali 398108de2844SGiridhar Malavali static void 398208de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 398308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 398408de2844SGiridhar Malavali { 398508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 398608de2844SGiridhar Malavali uint32_t r_addr, r_value; 398708de2844SGiridhar Malavali uint32_t i, loop_cnt; 398808de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 398908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 399008de2844SGiridhar Malavali 399108de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 399208de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 399308de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 399408de2844SGiridhar Malavali 399508de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 399608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 399708de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 399808de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 399908de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 400008de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 400108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 400208de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 400308de2844SGiridhar Malavali } 400408de2844SGiridhar Malavali *d_ptr = data_ptr; 400508de2844SGiridhar Malavali } 400608de2844SGiridhar Malavali 400708de2844SGiridhar Malavali static int 400808de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 400908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 401008de2844SGiridhar Malavali { 401108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 401208de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 401308de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 401408de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 401508de2844SGiridhar Malavali unsigned long flags; 401608de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 401708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 401808de2844SGiridhar Malavali 401908de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 402008de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 402108de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 402208de2844SGiridhar Malavali 402308de2844SGiridhar Malavali if (r_addr & 0xf) { 402408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 4025d6a03581SMasanari Iida "Read addr 0x%x not 16 bytes aligned\n", r_addr); 402608de2844SGiridhar Malavali return rval; 402708de2844SGiridhar Malavali } 402808de2844SGiridhar Malavali 402908de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 403008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 403108de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 403208de2844SGiridhar Malavali m_hdr->read_data_size); 403308de2844SGiridhar Malavali return rval; 403408de2844SGiridhar Malavali } 403508de2844SGiridhar Malavali 403608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 403708de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 403808de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 403908de2844SGiridhar Malavali 404008de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 404108de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 404208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 404308de2844SGiridhar Malavali r_value = 0; 404408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 404508de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 404608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 404708de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 404808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 404908de2844SGiridhar Malavali 405008de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 405108de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 405208de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 405308de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 405408de2844SGiridhar Malavali break; 405508de2844SGiridhar Malavali } 405608de2844SGiridhar Malavali 405708de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 405808de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 405908de2844SGiridhar Malavali "failed to read through agent\n"); 406008de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 406108de2844SGiridhar Malavali return rval; 406208de2844SGiridhar Malavali } 406308de2844SGiridhar Malavali 406408de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 406508de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 406608de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 406708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 406808de2844SGiridhar Malavali } 406908de2844SGiridhar Malavali r_addr += 16; 407008de2844SGiridhar Malavali } 407108de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 407208de2844SGiridhar Malavali *d_ptr = data_ptr; 407308de2844SGiridhar Malavali return QLA_SUCCESS; 407408de2844SGiridhar Malavali } 407508de2844SGiridhar Malavali 407608de2844SGiridhar Malavali static int 407708de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 407808de2844SGiridhar Malavali { 407908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 408008de2844SGiridhar Malavali uint64_t chksum = 0; 408108de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 408208de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 408308de2844SGiridhar Malavali 408408de2844SGiridhar Malavali while (count-- > 0) 408508de2844SGiridhar Malavali chksum += *d_ptr++; 408608de2844SGiridhar Malavali while (chksum >> 32) 408708de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 408808de2844SGiridhar Malavali return ~chksum; 408908de2844SGiridhar Malavali } 409008de2844SGiridhar Malavali 409108de2844SGiridhar Malavali static void 409208de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 409308de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 409408de2844SGiridhar Malavali { 409508de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 409608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 409708de2844SGiridhar Malavali "Skipping entry[%d]: " 409808de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 409908de2844SGiridhar Malavali index, entry_hdr->entry_type, 410008de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 410108de2844SGiridhar Malavali } 410208de2844SGiridhar Malavali 410308de2844SGiridhar Malavali int 410408de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 410508de2844SGiridhar Malavali { 410608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 410708de2844SGiridhar Malavali int no_entry_hdr = 0; 410808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 410908de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 411008de2844SGiridhar Malavali uint32_t *data_ptr; 411108de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 411208de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 411308de2844SGiridhar Malavali 411408de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 411508de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 411608de2844SGiridhar Malavali 411708de2844SGiridhar Malavali if (ha->fw_dumped) { 4118a8faa263SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb037, 4119a8faa263SGiridhar Malavali "Firmware has been previously dumped (%p) " 4120a8faa263SGiridhar Malavali "-- ignoring request.\n", ha->fw_dump); 412108de2844SGiridhar Malavali goto md_failed; 412208de2844SGiridhar Malavali } 412308de2844SGiridhar Malavali 412408de2844SGiridhar Malavali ha->fw_dumped = 0; 412508de2844SGiridhar Malavali 412608de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 412708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 412808de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 412908de2844SGiridhar Malavali goto md_failed; 413008de2844SGiridhar Malavali } 413108de2844SGiridhar Malavali 4132b6d0d9d5SGiridhar Malavali if (ha->flags.isp82xx_no_md_cap) { 4133b6d0d9d5SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb054, 4134b6d0d9d5SGiridhar Malavali "Forced reset from application, " 4135b6d0d9d5SGiridhar Malavali "ignore minidump capture\n"); 4136b6d0d9d5SGiridhar Malavali ha->flags.isp82xx_no_md_cap = 0; 4137b6d0d9d5SGiridhar Malavali goto md_failed; 4138b6d0d9d5SGiridhar Malavali } 4139b6d0d9d5SGiridhar Malavali 414008de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 414108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 414208de2844SGiridhar Malavali "Template checksum validation error\n"); 414308de2844SGiridhar Malavali goto md_failed; 414408de2844SGiridhar Malavali } 414508de2844SGiridhar Malavali 414608de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 414708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 414808de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 414908de2844SGiridhar Malavali 415008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 415108de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 415208de2844SGiridhar Malavali 415308de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 415408de2844SGiridhar Malavali 415508de2844SGiridhar Malavali /* Validate whether required debug level is set */ 415608de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 415708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 415808de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 415908de2844SGiridhar Malavali f_capture_mask); 416008de2844SGiridhar Malavali goto md_failed; 416108de2844SGiridhar Malavali } 416208de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 416308de2844SGiridhar Malavali 416408de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 416508de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 416608de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 416708de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 416808de2844SGiridhar Malavali 416908de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 417008de2844SGiridhar Malavali 4171880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb03d, 417208de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 417308de2844SGiridhar Malavali 417408de2844SGiridhar Malavali /* Check whether template obtained is valid */ 417508de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 417608de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 417708de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 417808de2844SGiridhar Malavali tmplt_hdr->entry_type); 417908de2844SGiridhar Malavali goto md_failed; 418008de2844SGiridhar Malavali } 418108de2844SGiridhar Malavali 418208de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 418308de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 418408de2844SGiridhar Malavali 418508de2844SGiridhar Malavali /* Walk through the entry headers */ 418608de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 418708de2844SGiridhar Malavali 418808de2844SGiridhar Malavali if (data_collected > total_data_size) { 418908de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 419008de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 419108de2844SGiridhar Malavali data_collected); 419208de2844SGiridhar Malavali goto md_failed; 419308de2844SGiridhar Malavali } 419408de2844SGiridhar Malavali 419508de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 419608de2844SGiridhar Malavali ql2xmdcapmask)) { 419708de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 419808de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 419908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 420008de2844SGiridhar Malavali "Skipping entry[%d]: " 420108de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 420208de2844SGiridhar Malavali i, entry_hdr->entry_type, 420308de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 420408de2844SGiridhar Malavali goto skip_nxt_entry; 420508de2844SGiridhar Malavali } 420608de2844SGiridhar Malavali 420708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 420808de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 420908de2844SGiridhar Malavali "entry_type: 0x%x, captrue_mask: 0x%x\n", 421008de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 421108de2844SGiridhar Malavali entry_hdr->entry_type, 421208de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 421308de2844SGiridhar Malavali 421408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 421508de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 421608de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 421708de2844SGiridhar Malavali 421808de2844SGiridhar Malavali /* Decode the entry type and take 421908de2844SGiridhar Malavali * required action to capture debug data */ 422008de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 422108de2844SGiridhar Malavali case QLA82XX_RDEND: 422208de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 422308de2844SGiridhar Malavali break; 422408de2844SGiridhar Malavali case QLA82XX_CNTRL: 422508de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 422608de2844SGiridhar Malavali entry_hdr, &data_ptr); 422708de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 422808de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 422908de2844SGiridhar Malavali goto md_failed; 423008de2844SGiridhar Malavali } 423108de2844SGiridhar Malavali break; 423208de2844SGiridhar Malavali case QLA82XX_RDCRB: 423308de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 423408de2844SGiridhar Malavali entry_hdr, &data_ptr); 423508de2844SGiridhar Malavali break; 423608de2844SGiridhar Malavali case QLA82XX_RDMEM: 423708de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 423808de2844SGiridhar Malavali entry_hdr, &data_ptr); 423908de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 424008de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 424108de2844SGiridhar Malavali goto md_failed; 424208de2844SGiridhar Malavali } 424308de2844SGiridhar Malavali break; 424408de2844SGiridhar Malavali case QLA82XX_BOARD: 424508de2844SGiridhar Malavali case QLA82XX_RDROM: 424608de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 424708de2844SGiridhar Malavali entry_hdr, &data_ptr); 424808de2844SGiridhar Malavali break; 424908de2844SGiridhar Malavali case QLA82XX_L2DTG: 425008de2844SGiridhar Malavali case QLA82XX_L2ITG: 425108de2844SGiridhar Malavali case QLA82XX_L2DAT: 425208de2844SGiridhar Malavali case QLA82XX_L2INS: 425308de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 425408de2844SGiridhar Malavali entry_hdr, &data_ptr); 425508de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 425608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 425708de2844SGiridhar Malavali goto md_failed; 425808de2844SGiridhar Malavali } 425908de2844SGiridhar Malavali break; 426008de2844SGiridhar Malavali case QLA82XX_L1DAT: 426108de2844SGiridhar Malavali case QLA82XX_L1INS: 426208de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 426308de2844SGiridhar Malavali entry_hdr, &data_ptr); 426408de2844SGiridhar Malavali break; 426508de2844SGiridhar Malavali case QLA82XX_RDOCM: 426608de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 426708de2844SGiridhar Malavali entry_hdr, &data_ptr); 426808de2844SGiridhar Malavali break; 426908de2844SGiridhar Malavali case QLA82XX_RDMUX: 427008de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 427108de2844SGiridhar Malavali entry_hdr, &data_ptr); 427208de2844SGiridhar Malavali break; 427308de2844SGiridhar Malavali case QLA82XX_QUEUE: 427408de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 427508de2844SGiridhar Malavali entry_hdr, &data_ptr); 427608de2844SGiridhar Malavali break; 427708de2844SGiridhar Malavali case QLA82XX_RDNOP: 427808de2844SGiridhar Malavali default: 427908de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 428008de2844SGiridhar Malavali break; 428108de2844SGiridhar Malavali } 428208de2844SGiridhar Malavali 428308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 428408de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 428508de2844SGiridhar Malavali 428608de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 428708de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 428808de2844SGiridhar Malavali skip_nxt_entry: 428908de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 429008de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 429108de2844SGiridhar Malavali } 429208de2844SGiridhar Malavali 429308de2844SGiridhar Malavali if (data_collected != total_data_size) { 4294880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb043, 429508de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 429608de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 429708de2844SGiridhar Malavali data_collected, total_data_size); 429808de2844SGiridhar Malavali goto md_failed; 429908de2844SGiridhar Malavali } 430008de2844SGiridhar Malavali 430108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 430208de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 430308de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 430408de2844SGiridhar Malavali ha->fw_dumped = 1; 430508de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 430608de2844SGiridhar Malavali 430708de2844SGiridhar Malavali md_failed: 430808de2844SGiridhar Malavali return rval; 430908de2844SGiridhar Malavali } 431008de2844SGiridhar Malavali 431108de2844SGiridhar Malavali int 431208de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 431308de2844SGiridhar Malavali { 431408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 431508de2844SGiridhar Malavali int i, k; 431608de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 431708de2844SGiridhar Malavali 431808de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 431908de2844SGiridhar Malavali 432008de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 432108de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 432208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 432308de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 432408de2844SGiridhar Malavali ql2xmdcapmask); 432508de2844SGiridhar Malavali } 432608de2844SGiridhar Malavali 432708de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 432808de2844SGiridhar Malavali if (i & ql2xmdcapmask) 432908de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 433008de2844SGiridhar Malavali } 433108de2844SGiridhar Malavali 433208de2844SGiridhar Malavali if (ha->md_dump) { 433308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 433408de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 433508de2844SGiridhar Malavali return 1; 433608de2844SGiridhar Malavali } 433708de2844SGiridhar Malavali 433808de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 433908de2844SGiridhar Malavali if (ha->md_dump == NULL) { 434008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 434108de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 434208de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 434308de2844SGiridhar Malavali return 1; 434408de2844SGiridhar Malavali } 434508de2844SGiridhar Malavali return 0; 434608de2844SGiridhar Malavali } 434708de2844SGiridhar Malavali 434808de2844SGiridhar Malavali void 434908de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 435008de2844SGiridhar Malavali { 435108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 435208de2844SGiridhar Malavali 435308de2844SGiridhar Malavali /* Release the template header allocated */ 435408de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 435508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 435608de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 435708de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 435808de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 435908de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4360fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 436108de2844SGiridhar Malavali } 436208de2844SGiridhar Malavali 436308de2844SGiridhar Malavali /* Release the template data buffer allocated */ 436408de2844SGiridhar Malavali if (ha->md_dump) { 436508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 436608de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 436708de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 436808de2844SGiridhar Malavali vfree(ha->md_dump); 436908de2844SGiridhar Malavali ha->md_dump_size = 0; 4370fa492630SSaurav Kashyap ha->md_dump = NULL; 437108de2844SGiridhar Malavali } 437208de2844SGiridhar Malavali } 437308de2844SGiridhar Malavali 437408de2844SGiridhar Malavali void 437508de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 437608de2844SGiridhar Malavali { 437708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 437808de2844SGiridhar Malavali int rval; 437908de2844SGiridhar Malavali 438008de2844SGiridhar Malavali /* Get Minidump template size */ 438108de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 438208de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 438308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 438408de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 438508de2844SGiridhar Malavali ha->md_template_size / 1024); 438608de2844SGiridhar Malavali 438708de2844SGiridhar Malavali /* Get Minidump template */ 438808de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 438908de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 439008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 439108de2844SGiridhar Malavali "MiniDump Template obtained\n"); 439208de2844SGiridhar Malavali 439308de2844SGiridhar Malavali /* Allocate memory for minidump */ 439408de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 439508de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 439608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 439708de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 439808de2844SGiridhar Malavali ha->md_dump_size / 1024); 439908de2844SGiridhar Malavali else { 440008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 440108de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 440208de2844SGiridhar Malavali ha->md_tmplt_hdr, 440308de2844SGiridhar Malavali ha->md_template_size / 1024); 440408de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 440508de2844SGiridhar Malavali ha->md_template_size, 440608de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4407fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 440808de2844SGiridhar Malavali } 440908de2844SGiridhar Malavali 441008de2844SGiridhar Malavali } 441108de2844SGiridhar Malavali } 441208de2844SGiridhar Malavali } 4413999916dcSSaurav Kashyap 4414999916dcSSaurav Kashyap int 4415999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4416999916dcSSaurav Kashyap { 4417999916dcSSaurav Kashyap 4418999916dcSSaurav Kashyap int rval; 4419999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4420999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4421999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4422999916dcSSaurav Kashyap 4423999916dcSSaurav Kashyap if (rval) { 4424999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4425999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4426999916dcSSaurav Kashyap goto exit; 4427999916dcSSaurav Kashyap } 4428999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4429999916dcSSaurav Kashyap exit: 4430999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4431999916dcSSaurav Kashyap return rval; 4432999916dcSSaurav Kashyap } 4433999916dcSSaurav Kashyap 4434999916dcSSaurav Kashyap int 4435999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4436999916dcSSaurav Kashyap { 4437999916dcSSaurav Kashyap 4438999916dcSSaurav Kashyap int rval; 4439999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4440999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4441999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4442999916dcSSaurav Kashyap 4443999916dcSSaurav Kashyap if (rval) { 4444999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4445999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4446999916dcSSaurav Kashyap goto exit; 4447999916dcSSaurav Kashyap } 4448999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4449999916dcSSaurav Kashyap exit: 4450999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4451999916dcSSaurav Kashyap return rval; 4452999916dcSSaurav Kashyap } 4453