1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 307e264b7SAndrew Vasquez * Copyright (c) 2003-2011 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 10ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 11a9083016SGiridhar Malavali 12a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 13a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 14a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 15a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 18a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 19a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 21a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 22a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 230547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 24a9083016SGiridhar Malavali 25a9083016SGiridhar Malavali /* CRB window related */ 26a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 27a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 28a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 29a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 30a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 31a9083016SGiridhar Malavali ((off) & 0xf0000)) 32a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 33a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 34a9083016SGiridhar Malavali 35a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 36a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 37a9083016SGiridhar Malavali int qla82xx_crb_table_initialized; 38a9083016SGiridhar Malavali 39a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 40a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 41a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 42a9083016SGiridhar Malavali 43a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 44a9083016SGiridhar Malavali { 45a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 46a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 95a9083016SGiridhar Malavali /* 96a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 97a9083016SGiridhar Malavali */ 98a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 99a9083016SGiridhar Malavali 100a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 101a9083016SGiridhar Malavali } 102a9083016SGiridhar Malavali 103a9083016SGiridhar Malavali struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 104a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 105a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 106a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 107a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 108a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 109a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 110a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 111a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 112a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 113a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 114a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 121a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 122a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 123a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 124a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 125a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 128a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 129a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 143a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 144a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 145a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 159a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 160a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 161a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 175a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 176a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 177a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 191a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 192a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 195a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 196a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 197a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 202a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 203a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 209a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 210a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 211a9083016SGiridhar Malavali {{{0} } }, 212a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 213a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 214a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 215a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 216a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 217a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 218a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 219a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 220a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 221a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 228a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 229a9083016SGiridhar Malavali {{{0} } }, 230a9083016SGiridhar Malavali {{{0} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 235a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 236a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 237a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 238a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 239a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 240a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 241a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 242a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 243a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 244a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 245a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 246a9083016SGiridhar Malavali {{{0} } }, 247a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 248a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 249a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 250a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 252a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 253a9083016SGiridhar Malavali {{{0} } }, 254a9083016SGiridhar Malavali {{{0} } }, 255a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 256a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 257a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 258a9083016SGiridhar Malavali }; 259a9083016SGiridhar Malavali 260a9083016SGiridhar Malavali /* 261a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 262a9083016SGiridhar Malavali */ 263a9083016SGiridhar Malavali unsigned qla82xx_crb_hub_agt[64] = { 264a9083016SGiridhar Malavali 0, 265a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 266a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 268a9083016SGiridhar Malavali 0, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 270a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 291a9083016SGiridhar Malavali 0, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 293a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 294a9083016SGiridhar Malavali 0, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 298a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 299a9083016SGiridhar Malavali 0, 300a9083016SGiridhar Malavali 0, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 307a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 316a9083016SGiridhar Malavali 0, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 318a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 321a9083016SGiridhar Malavali 0, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 323a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 325a9083016SGiridhar Malavali 0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali }; 329a9083016SGiridhar Malavali 330f1af6208SGiridhar Malavali /* Device states */ 331f1af6208SGiridhar Malavali char *qdev_state[] = { 332f1af6208SGiridhar Malavali "Unknown", 333f1af6208SGiridhar Malavali "Cold", 334f1af6208SGiridhar Malavali "Initializing", 335f1af6208SGiridhar Malavali "Ready", 336f1af6208SGiridhar Malavali "Need Reset", 337f1af6208SGiridhar Malavali "Need Quiescent", 338f1af6208SGiridhar Malavali "Failed", 339f1af6208SGiridhar Malavali "Quiescent", 340f1af6208SGiridhar Malavali }; 341f1af6208SGiridhar Malavali 342a9083016SGiridhar Malavali /* 343a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 344a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 345a9083016SGiridhar Malavali * side effect: lock crb window 346a9083016SGiridhar Malavali */ 347a9083016SGiridhar Malavali static void 348a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 349a9083016SGiridhar Malavali { 350a9083016SGiridhar Malavali u32 win_read; 351a9083016SGiridhar Malavali 352a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 353a9083016SGiridhar Malavali writel(ha->crb_win, 354a9083016SGiridhar Malavali (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 355a9083016SGiridhar Malavali 356a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 357a9083016SGiridhar Malavali * to use it. 358a9083016SGiridhar Malavali */ 359a9083016SGiridhar Malavali win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 360a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 361a9083016SGiridhar Malavali DEBUG2(qla_printk(KERN_INFO, ha, 362a9083016SGiridhar Malavali "%s: Written crbwin (0x%x) != Read crbwin (0x%x), " 363a9083016SGiridhar Malavali "off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 364a9083016SGiridhar Malavali } 365a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 366a9083016SGiridhar Malavali } 367a9083016SGiridhar Malavali 368a9083016SGiridhar Malavali static inline unsigned long 369a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 370a9083016SGiridhar Malavali { 371a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 372a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 373a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 374a9083016SGiridhar Malavali * regs are in both windows. 375a9083016SGiridhar Malavali */ 376a9083016SGiridhar Malavali return off; 377a9083016SGiridhar Malavali } 378a9083016SGiridhar Malavali 379a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 380a9083016SGiridhar Malavali /* We are in first CRB window */ 381a9083016SGiridhar Malavali if (ha->curr_window != 0) 382a9083016SGiridhar Malavali WARN_ON(1); 383a9083016SGiridhar Malavali return off; 384a9083016SGiridhar Malavali } 385a9083016SGiridhar Malavali 386a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 387a9083016SGiridhar Malavali /* We are in second CRB window */ 388a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 389a9083016SGiridhar Malavali 390a9083016SGiridhar Malavali if (ha->curr_window != 1) 391a9083016SGiridhar Malavali return off; 392a9083016SGiridhar Malavali 393a9083016SGiridhar Malavali /* We are in the QM or direct access 394a9083016SGiridhar Malavali * register region - do nothing 395a9083016SGiridhar Malavali */ 396a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 397a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 398a9083016SGiridhar Malavali return off; 399a9083016SGiridhar Malavali } 400a9083016SGiridhar Malavali /* strange address given */ 401a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 402a9083016SGiridhar Malavali "%s: Warning: unm_nic_pci_set_crbwindow called with" 403a9083016SGiridhar Malavali " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off); 404a9083016SGiridhar Malavali return off; 405a9083016SGiridhar Malavali } 406a9083016SGiridhar Malavali 40777e334d2SGiridhar Malavali static int 40877e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 40977e334d2SGiridhar Malavali { 41077e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 41177e334d2SGiridhar Malavali 41277e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 41377e334d2SGiridhar Malavali return -1; 41477e334d2SGiridhar Malavali 41577e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 41677e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 41777e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 41877e334d2SGiridhar Malavali return 0; 41977e334d2SGiridhar Malavali } 42077e334d2SGiridhar Malavali 42177e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 42277e334d2SGiridhar Malavali return -1; 42377e334d2SGiridhar Malavali 42477e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 42577e334d2SGiridhar Malavali 42677e334d2SGiridhar Malavali /* Try direct map */ 42777e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 42877e334d2SGiridhar Malavali 42977e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 43077e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 43177e334d2SGiridhar Malavali return 0; 43277e334d2SGiridhar Malavali } 43377e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 43477e334d2SGiridhar Malavali return 1; 43577e334d2SGiridhar Malavali } 43677e334d2SGiridhar Malavali 43777e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 43877e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 43977e334d2SGiridhar Malavali { 44077e334d2SGiridhar Malavali int done = 0, timeout = 0; 44177e334d2SGiridhar Malavali 44277e334d2SGiridhar Malavali while (!done) { 44377e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 44477e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 44577e334d2SGiridhar Malavali if (done == 1) 44677e334d2SGiridhar Malavali break; 44777e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 44877e334d2SGiridhar Malavali return -1; 44977e334d2SGiridhar Malavali timeout++; 45077e334d2SGiridhar Malavali } 45177e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 45277e334d2SGiridhar Malavali return 0; 45377e334d2SGiridhar Malavali } 45477e334d2SGiridhar Malavali 455a9083016SGiridhar Malavali int 456a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 457a9083016SGiridhar Malavali { 458a9083016SGiridhar Malavali unsigned long flags = 0; 459a9083016SGiridhar Malavali int rv; 460a9083016SGiridhar Malavali 461a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 462a9083016SGiridhar Malavali 463a9083016SGiridhar Malavali BUG_ON(rv == -1); 464a9083016SGiridhar Malavali 465a9083016SGiridhar Malavali if (rv == 1) { 466a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 467a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 468a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 469a9083016SGiridhar Malavali } 470a9083016SGiridhar Malavali 471a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali if (rv == 1) { 474a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 475a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 476a9083016SGiridhar Malavali } 477a9083016SGiridhar Malavali return 0; 478a9083016SGiridhar Malavali } 479a9083016SGiridhar Malavali 480a9083016SGiridhar Malavali int 481a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 482a9083016SGiridhar Malavali { 483a9083016SGiridhar Malavali unsigned long flags = 0; 484a9083016SGiridhar Malavali int rv; 485a9083016SGiridhar Malavali u32 data; 486a9083016SGiridhar Malavali 487a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 488a9083016SGiridhar Malavali 489a9083016SGiridhar Malavali BUG_ON(rv == -1); 490a9083016SGiridhar Malavali 491a9083016SGiridhar Malavali if (rv == 1) { 492a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 493a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 494a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 495a9083016SGiridhar Malavali } 496a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 497a9083016SGiridhar Malavali 498a9083016SGiridhar Malavali if (rv == 1) { 499a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 500a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 501a9083016SGiridhar Malavali } 502a9083016SGiridhar Malavali return data; 503a9083016SGiridhar Malavali } 504a9083016SGiridhar Malavali 505a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 506a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 507a9083016SGiridhar Malavali { 508a9083016SGiridhar Malavali int i; 509a9083016SGiridhar Malavali int done = 0, timeout = 0; 510a9083016SGiridhar Malavali 511a9083016SGiridhar Malavali while (!done) { 512a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 513a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 514a9083016SGiridhar Malavali if (done == 1) 515a9083016SGiridhar Malavali break; 516a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 517a9083016SGiridhar Malavali return -1; 518a9083016SGiridhar Malavali 519a9083016SGiridhar Malavali timeout++; 520a9083016SGiridhar Malavali 521a9083016SGiridhar Malavali /* Yield CPU */ 522a9083016SGiridhar Malavali if (!in_interrupt()) 523a9083016SGiridhar Malavali schedule(); 524a9083016SGiridhar Malavali else { 525a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 526a9083016SGiridhar Malavali cpu_relax(); 527a9083016SGiridhar Malavali } 528a9083016SGiridhar Malavali } 529a9083016SGiridhar Malavali 530a9083016SGiridhar Malavali return 0; 531a9083016SGiridhar Malavali } 532a9083016SGiridhar Malavali 533a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 534a9083016SGiridhar Malavali { 535a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 536a9083016SGiridhar Malavali } 537a9083016SGiridhar Malavali 538a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 539a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 540a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 541a9083016SGiridhar Malavali /* 542a9083016SGiridhar Malavali * check memory access boundary. 543a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 544a9083016SGiridhar Malavali */ 545a9083016SGiridhar Malavali static unsigned long 546a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 547a9083016SGiridhar Malavali unsigned long long addr, int size) 548a9083016SGiridhar Malavali { 549a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 550a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 551a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 552a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 553a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 554a9083016SGiridhar Malavali return 0; 555a9083016SGiridhar Malavali else 556a9083016SGiridhar Malavali return 1; 557a9083016SGiridhar Malavali } 558a9083016SGiridhar Malavali 559a9083016SGiridhar Malavali int qla82xx_pci_set_window_warning_count; 560a9083016SGiridhar Malavali 56177e334d2SGiridhar Malavali static unsigned long 562a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 563a9083016SGiridhar Malavali { 564a9083016SGiridhar Malavali int window; 565a9083016SGiridhar Malavali u32 win_read; 566a9083016SGiridhar Malavali 567a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 568a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 569a9083016SGiridhar Malavali /* DDR network side */ 570a9083016SGiridhar Malavali window = MN_WIN(addr); 571a9083016SGiridhar Malavali ha->ddr_mn_window = window; 572a9083016SGiridhar Malavali qla82xx_wr_32(ha, 573a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 574a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 575a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 576a9083016SGiridhar Malavali if ((win_read << 17) != window) { 577a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 578a9083016SGiridhar Malavali "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 579a9083016SGiridhar Malavali __func__, window, win_read); 580a9083016SGiridhar Malavali } 581a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 582a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 583a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 584a9083016SGiridhar Malavali unsigned int temp1; 585a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 586a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 587a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 588a9083016SGiridhar Malavali addr = -1UL; 589a9083016SGiridhar Malavali } 590a9083016SGiridhar Malavali window = OCM_WIN(addr); 591a9083016SGiridhar Malavali ha->ddr_mn_window = window; 592a9083016SGiridhar Malavali qla82xx_wr_32(ha, 593a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 594a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 595a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 596a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 597a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 598a9083016SGiridhar Malavali if (win_read != temp1) { 599a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 600a9083016SGiridhar Malavali "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n", 601a9083016SGiridhar Malavali __func__, temp1, win_read); 602a9083016SGiridhar Malavali } 603a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 604a9083016SGiridhar Malavali 605a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 606a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 607a9083016SGiridhar Malavali /* QDR network side */ 608a9083016SGiridhar Malavali window = MS_WIN(addr); 609a9083016SGiridhar Malavali ha->qdr_sn_window = window; 610a9083016SGiridhar Malavali qla82xx_wr_32(ha, 611a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 612a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 613a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 614a9083016SGiridhar Malavali if (win_read != window) { 615a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 616a9083016SGiridhar Malavali "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n", 617a9083016SGiridhar Malavali __func__, window, win_read); 618a9083016SGiridhar Malavali } 619a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 620a9083016SGiridhar Malavali } else { 621a9083016SGiridhar Malavali /* 622a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 623a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 624a9083016SGiridhar Malavali */ 625a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 626a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 627a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 628a9083016SGiridhar Malavali "%s: Warning:%s Unknown address range!\n", __func__, 629a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 630a9083016SGiridhar Malavali } 631a9083016SGiridhar Malavali addr = -1UL; 632a9083016SGiridhar Malavali } 633a9083016SGiridhar Malavali return addr; 634a9083016SGiridhar Malavali } 635a9083016SGiridhar Malavali 636a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 637a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 638a9083016SGiridhar Malavali unsigned long long addr) 639a9083016SGiridhar Malavali { 640a9083016SGiridhar Malavali int window; 641a9083016SGiridhar Malavali unsigned long long qdr_max; 642a9083016SGiridhar Malavali 643a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 644a9083016SGiridhar Malavali 645a9083016SGiridhar Malavali /* DDR network side */ 646a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 647a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 648a9083016SGiridhar Malavali BUG(); 649a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 650a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 651a9083016SGiridhar Malavali return 1; 652a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 653a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 654a9083016SGiridhar Malavali return 1; 655a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 656a9083016SGiridhar Malavali /* QDR network side */ 657a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 658a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 659a9083016SGiridhar Malavali return 1; 660a9083016SGiridhar Malavali } 661a9083016SGiridhar Malavali return 0; 662a9083016SGiridhar Malavali } 663a9083016SGiridhar Malavali 664a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 665a9083016SGiridhar Malavali u64 off, void *data, int size) 666a9083016SGiridhar Malavali { 667a9083016SGiridhar Malavali unsigned long flags; 668f1af6208SGiridhar Malavali void *addr = NULL; 669a9083016SGiridhar Malavali int ret = 0; 670a9083016SGiridhar Malavali u64 start; 671a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 672a9083016SGiridhar Malavali unsigned long mem_base; 673a9083016SGiridhar Malavali unsigned long mem_page; 674a9083016SGiridhar Malavali 675a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 676a9083016SGiridhar Malavali 677a9083016SGiridhar Malavali /* 678a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 679a9083016SGiridhar Malavali * do not access. 680a9083016SGiridhar Malavali */ 681a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 682a9083016SGiridhar Malavali if ((start == -1UL) || 683a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 684a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 685a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 686a9083016SGiridhar Malavali "%s out of bound pci memory access. " 687a9083016SGiridhar Malavali "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 688a9083016SGiridhar Malavali return -1; 689a9083016SGiridhar Malavali } 690a9083016SGiridhar Malavali 691a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 692a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 693a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 694a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 695a9083016SGiridhar Malavali * consecutive pages. 696a9083016SGiridhar Malavali */ 697a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 698a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 699a9083016SGiridhar Malavali else 700a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 701a9083016SGiridhar Malavali if (mem_ptr == 0UL) { 702a9083016SGiridhar Malavali *(u8 *)data = 0; 703a9083016SGiridhar Malavali return -1; 704a9083016SGiridhar Malavali } 705a9083016SGiridhar Malavali addr = mem_ptr; 706a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 707a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 708a9083016SGiridhar Malavali 709a9083016SGiridhar Malavali switch (size) { 710a9083016SGiridhar Malavali case 1: 711a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 712a9083016SGiridhar Malavali break; 713a9083016SGiridhar Malavali case 2: 714a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 715a9083016SGiridhar Malavali break; 716a9083016SGiridhar Malavali case 4: 717a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 718a9083016SGiridhar Malavali break; 719a9083016SGiridhar Malavali case 8: 720a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 721a9083016SGiridhar Malavali break; 722a9083016SGiridhar Malavali default: 723a9083016SGiridhar Malavali ret = -1; 724a9083016SGiridhar Malavali break; 725a9083016SGiridhar Malavali } 726a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 727a9083016SGiridhar Malavali 728a9083016SGiridhar Malavali if (mem_ptr) 729a9083016SGiridhar Malavali iounmap(mem_ptr); 730a9083016SGiridhar Malavali return ret; 731a9083016SGiridhar Malavali } 732a9083016SGiridhar Malavali 733a9083016SGiridhar Malavali static int 734a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 735a9083016SGiridhar Malavali u64 off, void *data, int size) 736a9083016SGiridhar Malavali { 737a9083016SGiridhar Malavali unsigned long flags; 738f1af6208SGiridhar Malavali void *addr = NULL; 739a9083016SGiridhar Malavali int ret = 0; 740a9083016SGiridhar Malavali u64 start; 741a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 742a9083016SGiridhar Malavali unsigned long mem_base; 743a9083016SGiridhar Malavali unsigned long mem_page; 744a9083016SGiridhar Malavali 745a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 746a9083016SGiridhar Malavali 747a9083016SGiridhar Malavali /* 748a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 749a9083016SGiridhar Malavali * do not access. 750a9083016SGiridhar Malavali */ 751a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 752a9083016SGiridhar Malavali if ((start == -1UL) || 753a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 754a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 755a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 756a9083016SGiridhar Malavali "%s out of bound pci memory access. " 757a9083016SGiridhar Malavali "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); 758a9083016SGiridhar Malavali return -1; 759a9083016SGiridhar Malavali } 760a9083016SGiridhar Malavali 761a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 762a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 763a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 764a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 765a9083016SGiridhar Malavali * consecutive pages. 766a9083016SGiridhar Malavali */ 767a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 768a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 769a9083016SGiridhar Malavali else 770a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 771a9083016SGiridhar Malavali if (mem_ptr == 0UL) 772a9083016SGiridhar Malavali return -1; 773a9083016SGiridhar Malavali 774a9083016SGiridhar Malavali addr = mem_ptr; 775a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 776a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 777a9083016SGiridhar Malavali 778a9083016SGiridhar Malavali switch (size) { 779a9083016SGiridhar Malavali case 1: 780a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 781a9083016SGiridhar Malavali break; 782a9083016SGiridhar Malavali case 2: 783a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 784a9083016SGiridhar Malavali break; 785a9083016SGiridhar Malavali case 4: 786a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 787a9083016SGiridhar Malavali break; 788a9083016SGiridhar Malavali case 8: 789a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 790a9083016SGiridhar Malavali break; 791a9083016SGiridhar Malavali default: 792a9083016SGiridhar Malavali ret = -1; 793a9083016SGiridhar Malavali break; 794a9083016SGiridhar Malavali } 795a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 796a9083016SGiridhar Malavali if (mem_ptr) 797a9083016SGiridhar Malavali iounmap(mem_ptr); 798a9083016SGiridhar Malavali return ret; 799a9083016SGiridhar Malavali } 800a9083016SGiridhar Malavali 801a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 80277e334d2SGiridhar Malavali static unsigned long 80377e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 804a9083016SGiridhar Malavali { 805a9083016SGiridhar Malavali int i; 806a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 807a9083016SGiridhar Malavali 808a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 809a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 810a9083016SGiridhar Malavali 811a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 812a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 813a9083016SGiridhar Malavali offset = addr & 0x000fffff; 814a9083016SGiridhar Malavali 815a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 816a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 817a9083016SGiridhar Malavali pci_base = i << 20; 818a9083016SGiridhar Malavali break; 819a9083016SGiridhar Malavali } 820a9083016SGiridhar Malavali } 821a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 822a9083016SGiridhar Malavali return pci_base; 823a9083016SGiridhar Malavali return pci_base + offset; 824a9083016SGiridhar Malavali } 825a9083016SGiridhar Malavali 826a9083016SGiridhar Malavali static long rom_max_timeout = 100; 827a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 828a9083016SGiridhar Malavali 82977e334d2SGiridhar Malavali static int 830a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 831a9083016SGiridhar Malavali { 832a9083016SGiridhar Malavali int done = 0, timeout = 0; 833a9083016SGiridhar Malavali 834a9083016SGiridhar Malavali while (!done) { 835a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 836a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 837a9083016SGiridhar Malavali if (done == 1) 838a9083016SGiridhar Malavali break; 839a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 840a9083016SGiridhar Malavali return -1; 841a9083016SGiridhar Malavali timeout++; 842a9083016SGiridhar Malavali } 843a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 844a9083016SGiridhar Malavali return 0; 845a9083016SGiridhar Malavali } 846a9083016SGiridhar Malavali 84777e334d2SGiridhar Malavali static int 848a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 849a9083016SGiridhar Malavali { 850a9083016SGiridhar Malavali long timeout = 0; 851a9083016SGiridhar Malavali long done = 0 ; 852a9083016SGiridhar Malavali 853a9083016SGiridhar Malavali while (done == 0) { 854a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 855a9083016SGiridhar Malavali done &= 4; 856a9083016SGiridhar Malavali timeout++; 857a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 858a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 859a9083016SGiridhar Malavali "%s: Timeout reached waiting for rom busy", 860a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 861a9083016SGiridhar Malavali return -1; 862a9083016SGiridhar Malavali } 863a9083016SGiridhar Malavali } 864a9083016SGiridhar Malavali return 0; 865a9083016SGiridhar Malavali } 866a9083016SGiridhar Malavali 86777e334d2SGiridhar Malavali static int 868a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 869a9083016SGiridhar Malavali { 870a9083016SGiridhar Malavali long timeout = 0; 871a9083016SGiridhar Malavali long done = 0 ; 872a9083016SGiridhar Malavali 873a9083016SGiridhar Malavali while (done == 0) { 874a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 875a9083016SGiridhar Malavali done &= 2; 876a9083016SGiridhar Malavali timeout++; 877a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 878a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 879a9083016SGiridhar Malavali "%s: Timeout reached waiting for rom done", 880a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 881a9083016SGiridhar Malavali return -1; 882a9083016SGiridhar Malavali } 883a9083016SGiridhar Malavali } 884a9083016SGiridhar Malavali return 0; 885a9083016SGiridhar Malavali } 886a9083016SGiridhar Malavali 88777e334d2SGiridhar Malavali static int 888a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 889a9083016SGiridhar Malavali { 890a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 891a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 892a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 893a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 894a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 895a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 896a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 897a9083016SGiridhar Malavali "%s: Error waiting for rom done\n", 898a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 899a9083016SGiridhar Malavali return -1; 900a9083016SGiridhar Malavali } 901a9083016SGiridhar Malavali /* Reset abyte_cnt and dummy_byte_cnt */ 902a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 903a9083016SGiridhar Malavali udelay(10); 904a9083016SGiridhar Malavali cond_resched(); 905a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 906a9083016SGiridhar Malavali *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 907a9083016SGiridhar Malavali return 0; 908a9083016SGiridhar Malavali } 909a9083016SGiridhar Malavali 91077e334d2SGiridhar Malavali static int 911a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 912a9083016SGiridhar Malavali { 913a9083016SGiridhar Malavali int ret, loops = 0; 914a9083016SGiridhar Malavali 915a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 916a9083016SGiridhar Malavali udelay(100); 917a9083016SGiridhar Malavali schedule(); 918a9083016SGiridhar Malavali loops++; 919a9083016SGiridhar Malavali } 920a9083016SGiridhar Malavali if (loops >= 50000) { 921a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 922a9083016SGiridhar Malavali "%s: qla82xx_rom_lock failed\n", 923a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 924a9083016SGiridhar Malavali return -1; 925a9083016SGiridhar Malavali } 926a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 927a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 928a9083016SGiridhar Malavali return ret; 929a9083016SGiridhar Malavali } 930a9083016SGiridhar Malavali 93177e334d2SGiridhar Malavali static int 932a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 933a9083016SGiridhar Malavali { 934a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 935a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 936a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 937a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 938a9083016SGiridhar Malavali "Error waiting for rom done\n"); 939a9083016SGiridhar Malavali return -1; 940a9083016SGiridhar Malavali } 941a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 942a9083016SGiridhar Malavali return 0; 943a9083016SGiridhar Malavali } 944a9083016SGiridhar Malavali 94577e334d2SGiridhar Malavali static int 946a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 947a9083016SGiridhar Malavali { 948a9083016SGiridhar Malavali long timeout = 0; 949a9083016SGiridhar Malavali uint32_t done = 1 ; 950a9083016SGiridhar Malavali uint32_t val; 951a9083016SGiridhar Malavali int ret = 0; 952a9083016SGiridhar Malavali 953a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 954a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 955a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 956a9083016SGiridhar Malavali done = val & 1; 957a9083016SGiridhar Malavali timeout++; 958a9083016SGiridhar Malavali udelay(10); 959a9083016SGiridhar Malavali cond_resched(); 960a9083016SGiridhar Malavali if (timeout >= 50000) { 961a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 962a9083016SGiridhar Malavali "Timeout reached waiting for write finish"); 963a9083016SGiridhar Malavali return -1; 964a9083016SGiridhar Malavali } 965a9083016SGiridhar Malavali } 966a9083016SGiridhar Malavali return ret; 967a9083016SGiridhar Malavali } 968a9083016SGiridhar Malavali 96977e334d2SGiridhar Malavali static int 970a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 971a9083016SGiridhar Malavali { 972a9083016SGiridhar Malavali uint32_t val; 973a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 974a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 975a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 976a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 977a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 978a9083016SGiridhar Malavali return -1; 979a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 980a9083016SGiridhar Malavali return -1; 981a9083016SGiridhar Malavali if ((val & 2) != 2) 982a9083016SGiridhar Malavali return -1; 983a9083016SGiridhar Malavali return 0; 984a9083016SGiridhar Malavali } 985a9083016SGiridhar Malavali 98677e334d2SGiridhar Malavali static int 987a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 988a9083016SGiridhar Malavali { 989a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 990a9083016SGiridhar Malavali return -1; 991a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 992a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 993a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 994a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 995a9083016SGiridhar Malavali "Error waiting for rom done\n"); 996a9083016SGiridhar Malavali return -1; 997a9083016SGiridhar Malavali } 998a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 999a9083016SGiridhar Malavali } 1000a9083016SGiridhar Malavali 100177e334d2SGiridhar Malavali static int 1002a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1003a9083016SGiridhar Malavali { 1004a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1005a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1006a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1007a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1008a9083016SGiridhar Malavali return -1; 1009a9083016SGiridhar Malavali } 1010a9083016SGiridhar Malavali return 0; 1011a9083016SGiridhar Malavali } 1012a9083016SGiridhar Malavali 101377e334d2SGiridhar Malavali static int 1014a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1015a9083016SGiridhar Malavali { 1016a9083016SGiridhar Malavali int loops = 0; 1017a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1018a9083016SGiridhar Malavali udelay(100); 1019a9083016SGiridhar Malavali cond_resched(); 1020a9083016SGiridhar Malavali loops++; 1021a9083016SGiridhar Malavali } 1022a9083016SGiridhar Malavali if (loops >= 50000) { 1023a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1024a9083016SGiridhar Malavali return -1; 1025a9083016SGiridhar Malavali } 1026a9083016SGiridhar Malavali return 0;; 1027a9083016SGiridhar Malavali } 1028a9083016SGiridhar Malavali 102977e334d2SGiridhar Malavali static int 1030a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1031a9083016SGiridhar Malavali uint32_t data) 1032a9083016SGiridhar Malavali { 1033a9083016SGiridhar Malavali int ret = 0; 1034a9083016SGiridhar Malavali 1035a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1036a9083016SGiridhar Malavali if (ret < 0) { 1037a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 1038a9083016SGiridhar Malavali return ret; 1039a9083016SGiridhar Malavali } 1040a9083016SGiridhar Malavali 1041a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1042a9083016SGiridhar Malavali goto done_write; 1043a9083016SGiridhar Malavali 1044a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1045a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1046a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1047a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1048a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1049a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 1050a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1051a9083016SGiridhar Malavali "Error waiting for rom done\n"); 1052a9083016SGiridhar Malavali ret = -1; 1053a9083016SGiridhar Malavali goto done_write; 1054a9083016SGiridhar Malavali } 1055a9083016SGiridhar Malavali 1056a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1057a9083016SGiridhar Malavali 1058a9083016SGiridhar Malavali done_write: 1059a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1060a9083016SGiridhar Malavali return ret; 1061a9083016SGiridhar Malavali } 1062a9083016SGiridhar Malavali 1063a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1064a9083016SGiridhar Malavali * to put the ISP into operational state 1065a9083016SGiridhar Malavali */ 106677e334d2SGiridhar Malavali static int 106777e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1068a9083016SGiridhar Malavali { 1069a9083016SGiridhar Malavali int addr, val; 1070a9083016SGiridhar Malavali int i ; 1071a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1072a9083016SGiridhar Malavali unsigned long off; 1073a9083016SGiridhar Malavali unsigned offset, n; 1074a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1075a9083016SGiridhar Malavali 1076a9083016SGiridhar Malavali struct crb_addr_pair { 1077a9083016SGiridhar Malavali long addr; 1078a9083016SGiridhar Malavali long data; 1079a9083016SGiridhar Malavali }; 1080a9083016SGiridhar Malavali 1081a9083016SGiridhar Malavali /* Halt all the indiviual PEGs and other blocks of the ISP */ 1082a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1083c9e8fd5cSMadhuranath Iyengar 108402be2215SGiridhar Malavali /* disable all I2Q */ 108502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 108602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 108702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 108802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 108902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 109002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 109102be2215SGiridhar Malavali 109202be2215SGiridhar Malavali /* disable all niu interrupts */ 1093c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1094c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1095c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1096c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1097c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 109802be2215SGiridhar Malavali /* disable sideband mac */ 109902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 110002be2215SGiridhar Malavali /* disable ap0 mac */ 110102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 110202be2215SGiridhar Malavali /* disable ap1 mac */ 110302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1104c9e8fd5cSMadhuranath Iyengar 1105c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1106c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1107c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1108c9e8fd5cSMadhuranath Iyengar 1109c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1110c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1111c9e8fd5cSMadhuranath Iyengar 1112c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1113c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1114c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1115c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1116c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1117c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 111802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1119c9e8fd5cSMadhuranath Iyengar 1120c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1121c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1122c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1123c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1124c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1125c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 112602be2215SGiridhar Malavali msleep(20); 1127c9e8fd5cSMadhuranath Iyengar 1128c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1129a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1130a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1131a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1132a9083016SGiridhar Malavali else 1133a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1134c9e8fd5cSMadhuranath Iyengar 1135c9e8fd5cSMadhuranath Iyengar /* reset ms */ 1136c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1137c9e8fd5cSMadhuranath Iyengar val |= (1 << 1); 1138c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1139c9e8fd5cSMadhuranath Iyengar msleep(20); 1140c9e8fd5cSMadhuranath Iyengar 1141c9e8fd5cSMadhuranath Iyengar /* unreset ms */ 1142c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1143c9e8fd5cSMadhuranath Iyengar val &= ~(1 << 1); 1144c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1145c9e8fd5cSMadhuranath Iyengar msleep(20); 1146c9e8fd5cSMadhuranath Iyengar 1147a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 1148a9083016SGiridhar Malavali 1149a9083016SGiridhar Malavali /* Read the signature value from the flash. 1150a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1151a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1152a9083016SGiridhar Malavali * that present in CRB initialize sequence 1153a9083016SGiridhar Malavali */ 1154a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1155a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1156a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1157a9083016SGiridhar Malavali "[ERROR] Reading crb_init area: n: %08x\n", n); 1158a9083016SGiridhar Malavali return -1; 1159a9083016SGiridhar Malavali } 1160a9083016SGiridhar Malavali 1161a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 1162a9083016SGiridhar Malavali * Number of enteries = upper 16 bits 1163a9083016SGiridhar Malavali */ 1164a9083016SGiridhar Malavali offset = n & 0xffffU; 1165a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1166a9083016SGiridhar Malavali 1167a9083016SGiridhar Malavali /* number of addr/value pair should not exceed 1024 enteries */ 1168a9083016SGiridhar Malavali if (n >= 1024) { 1169a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1170a9083016SGiridhar Malavali "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1171a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME, __func__, n); 1172a9083016SGiridhar Malavali return -1; 1173a9083016SGiridhar Malavali } 1174a9083016SGiridhar Malavali 1175a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1176a9083016SGiridhar Malavali "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n); 1177a9083016SGiridhar Malavali 1178a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1179a9083016SGiridhar Malavali if (buf == NULL) { 1180a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1181a9083016SGiridhar Malavali "%s: [ERROR] Unable to malloc memory.\n", 1182a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME); 1183a9083016SGiridhar Malavali return -1; 1184a9083016SGiridhar Malavali } 1185a9083016SGiridhar Malavali 1186a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1187a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1188a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1189a9083016SGiridhar Malavali kfree(buf); 1190a9083016SGiridhar Malavali return -1; 1191a9083016SGiridhar Malavali } 1192a9083016SGiridhar Malavali 1193a9083016SGiridhar Malavali buf[i].addr = addr; 1194a9083016SGiridhar Malavali buf[i].data = val; 1195a9083016SGiridhar Malavali } 1196a9083016SGiridhar Malavali 1197a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1198a9083016SGiridhar Malavali /* Translate internal CRB initialization 1199a9083016SGiridhar Malavali * address to PCI bus address 1200a9083016SGiridhar Malavali */ 1201a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1202a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1203a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1204a9083016SGiridhar Malavali * some of them are skipped 1205a9083016SGiridhar Malavali */ 1206a9083016SGiridhar Malavali 1207a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1208a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1209a9083016SGiridhar Malavali continue; 1210a9083016SGiridhar Malavali 1211a9083016SGiridhar Malavali /* do not reset PCI */ 1212a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1213a9083016SGiridhar Malavali continue; 1214a9083016SGiridhar Malavali 1215a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1216a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1217a9083016SGiridhar Malavali continue; 1218a9083016SGiridhar Malavali 1219a9083016SGiridhar Malavali /* skip the function enable register */ 1220a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1221a9083016SGiridhar Malavali continue; 1222a9083016SGiridhar Malavali 1223a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1224a9083016SGiridhar Malavali continue; 1225a9083016SGiridhar Malavali 1226a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1227a9083016SGiridhar Malavali continue; 1228a9083016SGiridhar Malavali 1229a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1230a9083016SGiridhar Malavali continue; 1231a9083016SGiridhar Malavali 1232a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 1233a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1234a9083016SGiridhar Malavali "%s: [ERROR] Unknown addr: 0x%08lx\n", 1235a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME, buf[i].addr); 1236a9083016SGiridhar Malavali continue; 1237a9083016SGiridhar Malavali } 1238a9083016SGiridhar Malavali 1239a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1240a9083016SGiridhar Malavali 1241a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1242a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1243a9083016SGiridhar Malavali */ 1244a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1245a9083016SGiridhar Malavali msleep(1000); 1246a9083016SGiridhar Malavali 1247a9083016SGiridhar Malavali /* ISP requires millisec delay between 1248a9083016SGiridhar Malavali * successive CRB register updation 1249a9083016SGiridhar Malavali */ 1250a9083016SGiridhar Malavali msleep(1); 1251a9083016SGiridhar Malavali } 1252a9083016SGiridhar Malavali 1253a9083016SGiridhar Malavali kfree(buf); 1254a9083016SGiridhar Malavali 1255a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1256a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1257a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1258a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1259a9083016SGiridhar Malavali 1260a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1261a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1262a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1263a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1264a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1265a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1266a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1267a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1268a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1269a9083016SGiridhar Malavali return 0; 1270a9083016SGiridhar Malavali } 1271a9083016SGiridhar Malavali 127277e334d2SGiridhar Malavali static int 127377e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 127477e334d2SGiridhar Malavali u64 off, void *data, int size) 127577e334d2SGiridhar Malavali { 127677e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 127777e334d2SGiridhar Malavali int scale, shift_amount, startword; 127877e334d2SGiridhar Malavali uint32_t temp; 127977e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 128077e334d2SGiridhar Malavali 128177e334d2SGiridhar Malavali /* 128277e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 128377e334d2SGiridhar Malavali */ 128477e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 128577e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 128677e334d2SGiridhar Malavali else { 128777e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 128877e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 128977e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 129077e334d2SGiridhar Malavali off, data, size); 129177e334d2SGiridhar Malavali } 129277e334d2SGiridhar Malavali 129377e334d2SGiridhar Malavali off0 = off & 0x7; 129477e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 129577e334d2SGiridhar Malavali sz[1] = size - sz[0]; 129677e334d2SGiridhar Malavali 129777e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 129877e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 129977e334d2SGiridhar Malavali shift_amount = 4; 130077e334d2SGiridhar Malavali scale = 2; 130177e334d2SGiridhar Malavali startword = (off & 0xf)/8; 130277e334d2SGiridhar Malavali 130377e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 130477e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 130577e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 130677e334d2SGiridhar Malavali return -1; 130777e334d2SGiridhar Malavali } 130877e334d2SGiridhar Malavali 130977e334d2SGiridhar Malavali switch (size) { 131077e334d2SGiridhar Malavali case 1: 131177e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 131277e334d2SGiridhar Malavali break; 131377e334d2SGiridhar Malavali case 2: 131477e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 131577e334d2SGiridhar Malavali break; 131677e334d2SGiridhar Malavali case 4: 131777e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 131877e334d2SGiridhar Malavali break; 131977e334d2SGiridhar Malavali case 8: 132077e334d2SGiridhar Malavali default: 132177e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 132277e334d2SGiridhar Malavali break; 132377e334d2SGiridhar Malavali } 132477e334d2SGiridhar Malavali 132577e334d2SGiridhar Malavali if (sz[0] == 8) { 132677e334d2SGiridhar Malavali word[startword] = tmpw; 132777e334d2SGiridhar Malavali } else { 132877e334d2SGiridhar Malavali word[startword] &= 132977e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 133077e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 133177e334d2SGiridhar Malavali } 133277e334d2SGiridhar Malavali if (sz[1] != 0) { 133377e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 133477e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 133577e334d2SGiridhar Malavali } 133677e334d2SGiridhar Malavali 133777e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 133877e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 133977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 134077e334d2SGiridhar Malavali temp = 0; 134177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 134277e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 134377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 134477e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 134577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 134677e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 134777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 134877e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 134977e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 135077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 135177e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 135277e334d2SGiridhar Malavali 135377e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 135477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 135577e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 135677e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 135777e334d2SGiridhar Malavali 135877e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 135977e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 136077e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 136177e334d2SGiridhar Malavali break; 136277e334d2SGiridhar Malavali } 136377e334d2SGiridhar Malavali 136477e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 136577e334d2SGiridhar Malavali if (printk_ratelimit()) 136677e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 136777e334d2SGiridhar Malavali "failed to write through agent\n"); 136877e334d2SGiridhar Malavali ret = -1; 136977e334d2SGiridhar Malavali break; 137077e334d2SGiridhar Malavali } 137177e334d2SGiridhar Malavali } 137277e334d2SGiridhar Malavali 137377e334d2SGiridhar Malavali return ret; 137477e334d2SGiridhar Malavali } 137577e334d2SGiridhar Malavali 137677e334d2SGiridhar Malavali static int 1377a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1378a9083016SGiridhar Malavali { 1379a9083016SGiridhar Malavali int i; 1380a9083016SGiridhar Malavali long size = 0; 13819c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 13829c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1383a9083016SGiridhar Malavali u64 data; 1384a9083016SGiridhar Malavali u32 high, low; 1385a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1386a9083016SGiridhar Malavali 1387a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1388a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1389a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1390a9083016SGiridhar Malavali return -1; 1391a9083016SGiridhar Malavali } 1392a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1393a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1394a9083016SGiridhar Malavali flashaddr += 8; 1395a9083016SGiridhar Malavali memaddr += 8; 1396a9083016SGiridhar Malavali 1397a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1398a9083016SGiridhar Malavali msleep(1); 1399a9083016SGiridhar Malavali } 1400a9083016SGiridhar Malavali udelay(100); 1401a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1402a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1403a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1404a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1405a9083016SGiridhar Malavali return 0; 1406a9083016SGiridhar Malavali } 1407a9083016SGiridhar Malavali 1408a9083016SGiridhar Malavali int 1409a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1410a9083016SGiridhar Malavali u64 off, void *data, int size) 1411a9083016SGiridhar Malavali { 1412a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1413a9083016SGiridhar Malavali int shift_amount; 1414a9083016SGiridhar Malavali uint32_t temp; 1415a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1416a9083016SGiridhar Malavali 1417a9083016SGiridhar Malavali /* 1418a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1419a9083016SGiridhar Malavali */ 1420a9083016SGiridhar Malavali 1421a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1422a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1423a9083016SGiridhar Malavali else { 1424a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1425a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1426a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1427a9083016SGiridhar Malavali off, data, size); 1428a9083016SGiridhar Malavali } 1429a9083016SGiridhar Malavali 1430a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1431a9083016SGiridhar Malavali off0[0] = off & 0xf; 1432a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1433a9083016SGiridhar Malavali shift_amount = 4; 1434a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1435a9083016SGiridhar Malavali off0[1] = 0; 1436a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1437a9083016SGiridhar Malavali 1438a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1439a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1440a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1441a9083016SGiridhar Malavali temp = 0; 1442a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1443a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1444a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1445a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1446a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1447a9083016SGiridhar Malavali 1448a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1449a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1450a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1451a9083016SGiridhar Malavali break; 1452a9083016SGiridhar Malavali } 1453a9083016SGiridhar Malavali 1454a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1455a9083016SGiridhar Malavali if (printk_ratelimit()) 1456a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 1457a9083016SGiridhar Malavali "failed to read through agent\n"); 1458a9083016SGiridhar Malavali break; 1459a9083016SGiridhar Malavali } 1460a9083016SGiridhar Malavali 1461a9083016SGiridhar Malavali start = off0[i] >> 2; 1462a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1463a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1464a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1465a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1466a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1467a9083016SGiridhar Malavali } 1468a9083016SGiridhar Malavali } 1469a9083016SGiridhar Malavali 1470a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1471a9083016SGiridhar Malavali return -1; 1472a9083016SGiridhar Malavali 1473a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1474a9083016SGiridhar Malavali val = word[0]; 1475a9083016SGiridhar Malavali } else { 1476a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1477a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1478a9083016SGiridhar Malavali } 1479a9083016SGiridhar Malavali 1480a9083016SGiridhar Malavali switch (size) { 1481a9083016SGiridhar Malavali case 1: 1482a9083016SGiridhar Malavali *(uint8_t *)data = val; 1483a9083016SGiridhar Malavali break; 1484a9083016SGiridhar Malavali case 2: 1485a9083016SGiridhar Malavali *(uint16_t *)data = val; 1486a9083016SGiridhar Malavali break; 1487a9083016SGiridhar Malavali case 4: 1488a9083016SGiridhar Malavali *(uint32_t *)data = val; 1489a9083016SGiridhar Malavali break; 1490a9083016SGiridhar Malavali case 8: 1491a9083016SGiridhar Malavali *(uint64_t *)data = val; 1492a9083016SGiridhar Malavali break; 1493a9083016SGiridhar Malavali } 1494a9083016SGiridhar Malavali return 0; 1495a9083016SGiridhar Malavali } 1496a9083016SGiridhar Malavali 1497a9083016SGiridhar Malavali 14989c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 14999c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15009c2b2975SHarish Zunjarrao { 15019c2b2975SHarish Zunjarrao uint32_t i; 15029c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15039c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15049c2b2975SHarish Zunjarrao __le32 offset; 15059c2b2975SHarish Zunjarrao __le32 tab_type; 15069c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15079c2b2975SHarish Zunjarrao 15089c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15099c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15109c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15119c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15129c2b2975SHarish Zunjarrao 15139c2b2975SHarish Zunjarrao if (tab_type == section) 15149c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15159c2b2975SHarish Zunjarrao } 15169c2b2975SHarish Zunjarrao 15179c2b2975SHarish Zunjarrao return NULL; 15189c2b2975SHarish Zunjarrao } 15199c2b2975SHarish Zunjarrao 15209c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15219c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15229c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15239c2b2975SHarish Zunjarrao { 15249c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15259c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15269c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15279c2b2975SHarish Zunjarrao __le32 offset; 15289c2b2975SHarish Zunjarrao 15299c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15309c2b2975SHarish Zunjarrao if (!tab_desc) 15319c2b2975SHarish Zunjarrao return NULL; 15329c2b2975SHarish Zunjarrao 15339c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15349c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15359c2b2975SHarish Zunjarrao 15369c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15379c2b2975SHarish Zunjarrao } 15389c2b2975SHarish Zunjarrao 15399c2b2975SHarish Zunjarrao static u8 * 15409c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15419c2b2975SHarish Zunjarrao { 15429c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15439c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15449c2b2975SHarish Zunjarrao 15459c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15469c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15479c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15489c2b2975SHarish Zunjarrao if (uri_desc) 15499c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15509c2b2975SHarish Zunjarrao } 15519c2b2975SHarish Zunjarrao 15529c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15539c2b2975SHarish Zunjarrao } 15549c2b2975SHarish Zunjarrao 15559c2b2975SHarish Zunjarrao static __le32 15569c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15579c2b2975SHarish Zunjarrao { 15589c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15599c2b2975SHarish Zunjarrao 15609c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15619c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15629c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15639c2b2975SHarish Zunjarrao if (uri_desc) 15649c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 15659c2b2975SHarish Zunjarrao } 15669c2b2975SHarish Zunjarrao 15679c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15689c2b2975SHarish Zunjarrao } 15699c2b2975SHarish Zunjarrao 15709c2b2975SHarish Zunjarrao static u8 * 15719c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 15729c2b2975SHarish Zunjarrao { 15739c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 15749c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15759c2b2975SHarish Zunjarrao 15769c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15779c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15789c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15799c2b2975SHarish Zunjarrao if (uri_desc) 15809c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15819c2b2975SHarish Zunjarrao } 15829c2b2975SHarish Zunjarrao 15839c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15849c2b2975SHarish Zunjarrao } 15859c2b2975SHarish Zunjarrao 1586a9083016SGiridhar Malavali /* PCI related functions */ 1587a9083016SGiridhar Malavali char * 1588a9083016SGiridhar Malavali qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1589a9083016SGiridhar Malavali { 1590a9083016SGiridhar Malavali int pcie_reg; 1591a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1592a9083016SGiridhar Malavali char lwstr[6]; 1593a9083016SGiridhar Malavali uint16_t lnk; 1594a9083016SGiridhar Malavali 1595a9083016SGiridhar Malavali pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1596a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1597a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 1598a9083016SGiridhar Malavali 1599a9083016SGiridhar Malavali strcpy(str, "PCIe ("); 1600a9083016SGiridhar Malavali strcat(str, "2.5Gb/s "); 1601a9083016SGiridhar Malavali snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1602a9083016SGiridhar Malavali strcat(str, lwstr); 1603a9083016SGiridhar Malavali return str; 1604a9083016SGiridhar Malavali } 1605a9083016SGiridhar Malavali 1606a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1607a9083016SGiridhar Malavali { 1608a9083016SGiridhar Malavali unsigned long val = 0; 1609a9083016SGiridhar Malavali u32 control; 1610a9083016SGiridhar Malavali 1611a9083016SGiridhar Malavali switch (region) { 1612a9083016SGiridhar Malavali case 0: 1613a9083016SGiridhar Malavali val = 0; 1614a9083016SGiridhar Malavali break; 1615a9083016SGiridhar Malavali case 1: 1616a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1617a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1618a9083016SGiridhar Malavali break; 1619a9083016SGiridhar Malavali } 1620a9083016SGiridhar Malavali return val; 1621a9083016SGiridhar Malavali } 1622a9083016SGiridhar Malavali 1623a9083016SGiridhar Malavali 1624a9083016SGiridhar Malavali int 1625a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1626a9083016SGiridhar Malavali { 1627a9083016SGiridhar Malavali uint32_t len = 0; 1628a9083016SGiridhar Malavali 1629a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1630a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1631a9083016SGiridhar Malavali "Failed to reserve selected regions (%s)\n", 1632a9083016SGiridhar Malavali pci_name(ha->pdev)); 1633a9083016SGiridhar Malavali goto iospace_error_exit; 1634a9083016SGiridhar Malavali } 1635a9083016SGiridhar Malavali 1636a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1637a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1638a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1639a9083016SGiridhar Malavali "region #0 not an MMIO resource (%s), aborting\n", 1640a9083016SGiridhar Malavali pci_name(ha->pdev)); 1641a9083016SGiridhar Malavali goto iospace_error_exit; 1642a9083016SGiridhar Malavali } 1643a9083016SGiridhar Malavali 1644a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1645a9083016SGiridhar Malavali ha->nx_pcibase = 1646a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1647a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 1648a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1649a9083016SGiridhar Malavali "cannot remap pcibase MMIO (%s), aborting\n", 1650a9083016SGiridhar Malavali pci_name(ha->pdev)); 1651a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1652a9083016SGiridhar Malavali goto iospace_error_exit; 1653a9083016SGiridhar Malavali } 1654a9083016SGiridhar Malavali 1655a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1656a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1657a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1658a9083016SGiridhar Malavali 1659a9083016SGiridhar Malavali if (!ql2xdbwr) { 1660a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1661a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1662a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1663a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 1664a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 1665a9083016SGiridhar Malavali "cannot remap MMIO (%s), aborting\n", 1666a9083016SGiridhar Malavali pci_name(ha->pdev)); 1667a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1668a9083016SGiridhar Malavali goto iospace_error_exit; 1669a9083016SGiridhar Malavali } 1670a9083016SGiridhar Malavali 1671a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1672a9083016SGiridhar Malavali * door bell read and write pointer 1673a9083016SGiridhar Malavali */ 1674a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1675a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1676a9083016SGiridhar Malavali } else { 1677a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1678a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1679a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1680a9083016SGiridhar Malavali } 1681a9083016SGiridhar Malavali 1682a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1683a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 1684a9083016SGiridhar Malavali return 0; 1685a9083016SGiridhar Malavali 1686a9083016SGiridhar Malavali iospace_error_exit: 1687a9083016SGiridhar Malavali return -ENOMEM; 1688a9083016SGiridhar Malavali } 1689a9083016SGiridhar Malavali 1690a9083016SGiridhar Malavali /* GS related functions */ 1691a9083016SGiridhar Malavali 1692a9083016SGiridhar Malavali /* Initialization related functions */ 1693a9083016SGiridhar Malavali 1694a9083016SGiridhar Malavali /** 1695a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1696a9083016SGiridhar Malavali * @ha: HA context 1697a9083016SGiridhar Malavali * 1698a9083016SGiridhar Malavali * Returns 0 on success. 1699a9083016SGiridhar Malavali */ 1700a9083016SGiridhar Malavali int 1701a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1702a9083016SGiridhar Malavali { 1703a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1704a9083016SGiridhar Malavali int ret; 1705a9083016SGiridhar Malavali 1706a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1707a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1708a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 1709a9083016SGiridhar Malavali return 0; 1710a9083016SGiridhar Malavali } 1711a9083016SGiridhar Malavali 1712a9083016SGiridhar Malavali /** 1713a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1714a9083016SGiridhar Malavali * @ha: HA context 1715a9083016SGiridhar Malavali * 1716a9083016SGiridhar Malavali * Returns 0 on success. 1717a9083016SGiridhar Malavali */ 1718a9083016SGiridhar Malavali void 1719a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1720a9083016SGiridhar Malavali { 1721a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1722a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1723a9083016SGiridhar Malavali } 1724a9083016SGiridhar Malavali 1725a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1726a9083016SGiridhar Malavali { 1727a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1728a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1729a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1730a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1731a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1732a9083016SGiridhar Malavali 1733a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1734a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1735a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1736a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1737a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1738a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1739a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1740a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1741a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1742a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1743a9083016SGiridhar Malavali 1744a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1745a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1746a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1747a9083016SGiridhar Malavali } 1748a9083016SGiridhar Malavali 1749f1af6208SGiridhar Malavali void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1750f1af6208SGiridhar Malavali { 1751f1af6208SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1752f1af6208SGiridhar Malavali vha->flags.online = 0; 1753f1af6208SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 1754f1af6208SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1755f1af6208SGiridhar Malavali } 1756f1af6208SGiridhar Malavali 175777e334d2SGiridhar Malavali static int 175877e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1759a9083016SGiridhar Malavali { 1760a9083016SGiridhar Malavali u64 *ptr64; 1761a9083016SGiridhar Malavali u32 i, flashaddr, size; 1762a9083016SGiridhar Malavali __le64 data; 1763a9083016SGiridhar Malavali 1764a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1765a9083016SGiridhar Malavali 17669c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1767a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1768a9083016SGiridhar Malavali 1769a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1770a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17719c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17729c2b2975SHarish Zunjarrao return -EIO; 1773a9083016SGiridhar Malavali flashaddr += 8; 1774a9083016SGiridhar Malavali } 1775a9083016SGiridhar Malavali 1776a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 17779c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 17789c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1779a9083016SGiridhar Malavali 1780a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1781a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1782a9083016SGiridhar Malavali 1783a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1784a9083016SGiridhar Malavali return -EIO; 1785a9083016SGiridhar Malavali flashaddr += 8; 1786a9083016SGiridhar Malavali } 17879c2b2975SHarish Zunjarrao udelay(100); 1788a9083016SGiridhar Malavali 1789a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1790a9083016SGiridhar Malavali * at a specified offset to indicate 1791a9083016SGiridhar Malavali * that all data is written and 1792a9083016SGiridhar Malavali * ready for firmware to initialize. 1793a9083016SGiridhar Malavali */ 17949c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1795a9083016SGiridhar Malavali 17969c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1797a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1798a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 17999c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18009c2b2975SHarish Zunjarrao return 0; 18019c2b2975SHarish Zunjarrao } 18029c2b2975SHarish Zunjarrao 18039c2b2975SHarish Zunjarrao static int 18049c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18059c2b2975SHarish Zunjarrao { 18069c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18079c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18089c2b2975SHarish Zunjarrao uint32_t i; 18099c2b2975SHarish Zunjarrao __le32 entries; 18109c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18119c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18129c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18139c2b2975SHarish Zunjarrao int mn_present = 0; 18149c2b2975SHarish Zunjarrao uint32_t flagbit; 18159c2b2975SHarish Zunjarrao 18169c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18179c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18189c2b2975SHarish Zunjarrao if (!ptab_desc) 18199c2b2975SHarish Zunjarrao return -1; 18209c2b2975SHarish Zunjarrao 18219c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18229c2b2975SHarish Zunjarrao 18239c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18249c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18259c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18269c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18279c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18289c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18299c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18309c2b2975SHarish Zunjarrao 18319c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18329c2b2975SHarish Zunjarrao 18339c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18349c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18359c2b2975SHarish Zunjarrao return 0; 18369c2b2975SHarish Zunjarrao } 18379c2b2975SHarish Zunjarrao } 18389c2b2975SHarish Zunjarrao return -1; 18399c2b2975SHarish Zunjarrao } 18409c2b2975SHarish Zunjarrao 18419c2b2975SHarish Zunjarrao int 18429c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18439c2b2975SHarish Zunjarrao { 18449c2b2975SHarish Zunjarrao __le32 val; 18459c2b2975SHarish Zunjarrao uint32_t min_size; 18469c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18479c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18489c2b2975SHarish Zunjarrao 18499c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18509c2b2975SHarish Zunjarrao 18519c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18529c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18539c2b2975SHarish Zunjarrao return -EINVAL; 18549c2b2975SHarish Zunjarrao 18559c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18569c2b2975SHarish Zunjarrao } else { 18579c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18589c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18599c2b2975SHarish Zunjarrao return -EINVAL; 18609c2b2975SHarish Zunjarrao 18619c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18629c2b2975SHarish Zunjarrao } 18639c2b2975SHarish Zunjarrao 18649c2b2975SHarish Zunjarrao if (fw->size < min_size) 18659c2b2975SHarish Zunjarrao return -EINVAL; 1866a9083016SGiridhar Malavali return 0; 1867a9083016SGiridhar Malavali } 1868a9083016SGiridhar Malavali 186977e334d2SGiridhar Malavali static int 187077e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1871a9083016SGiridhar Malavali { 1872a9083016SGiridhar Malavali u32 val = 0; 1873a9083016SGiridhar Malavali int retries = 60; 1874a9083016SGiridhar Malavali 1875a9083016SGiridhar Malavali do { 1876a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1877a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1878a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1879a9083016SGiridhar Malavali 1880a9083016SGiridhar Malavali switch (val) { 1881a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1882a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1883a9083016SGiridhar Malavali return QLA_SUCCESS; 1884a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1885a9083016SGiridhar Malavali break; 1886a9083016SGiridhar Malavali default: 1887a9083016SGiridhar Malavali break; 1888a9083016SGiridhar Malavali } 1889a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1890a9083016SGiridhar Malavali "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n", 1891a9083016SGiridhar Malavali val, retries); 1892a9083016SGiridhar Malavali 1893a9083016SGiridhar Malavali msleep(500); 1894a9083016SGiridhar Malavali 1895a9083016SGiridhar Malavali } while (--retries); 1896a9083016SGiridhar Malavali 1897a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1898a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1899a9083016SGiridhar Malavali 1900a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1901a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1902a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1903a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1904a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1905a9083016SGiridhar Malavali } 1906a9083016SGiridhar Malavali 190777e334d2SGiridhar Malavali static int 190877e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1909a9083016SGiridhar Malavali { 1910a9083016SGiridhar Malavali u32 val = 0; 1911a9083016SGiridhar Malavali int retries = 60; 1912a9083016SGiridhar Malavali 1913a9083016SGiridhar Malavali do { 1914a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1915a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1916a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1917a9083016SGiridhar Malavali 1918a9083016SGiridhar Malavali switch (val) { 1919a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1920a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1921a9083016SGiridhar Malavali return QLA_SUCCESS; 1922a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1923a9083016SGiridhar Malavali break; 1924a9083016SGiridhar Malavali default: 1925a9083016SGiridhar Malavali break; 1926a9083016SGiridhar Malavali } 1927a9083016SGiridhar Malavali 1928a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 1929a9083016SGiridhar Malavali "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n", 1930a9083016SGiridhar Malavali val, retries); 1931a9083016SGiridhar Malavali 1932a9083016SGiridhar Malavali msleep(500); 1933a9083016SGiridhar Malavali 1934a9083016SGiridhar Malavali } while (--retries); 1935a9083016SGiridhar Malavali 1936a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1937a9083016SGiridhar Malavali "Rcv Peg initialization failed: 0x%x.\n", val); 1938a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1939a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1940a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1941a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1942a9083016SGiridhar Malavali } 1943a9083016SGiridhar Malavali 1944a9083016SGiridhar Malavali /* ISR related functions */ 1945a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1946a9083016SGiridhar Malavali ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1947a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1948a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1949a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1950a9083016SGiridhar Malavali }; 1951a9083016SGiridhar Malavali 1952a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_status[8] = { 1953a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1954a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1955a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1956a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1957a9083016SGiridhar Malavali }; 1958a9083016SGiridhar Malavali 1959a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1960a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1961a9083016SGiridhar Malavali 1962a9083016SGiridhar Malavali /* 1963a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1964a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1965a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1966a9083016SGiridhar Malavali */ 196777e334d2SGiridhar Malavali static void 1968a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1969a9083016SGiridhar Malavali { 1970a9083016SGiridhar Malavali uint16_t cnt; 1971a9083016SGiridhar Malavali uint16_t __iomem *wptr; 1972a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1973a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1974a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1975a9083016SGiridhar Malavali 1976a9083016SGiridhar Malavali /* Load return mailbox registers. */ 1977a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 1978a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 1979a9083016SGiridhar Malavali 1980a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1981a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1982a9083016SGiridhar Malavali wptr++; 1983a9083016SGiridhar Malavali } 1984a9083016SGiridhar Malavali 1985a9083016SGiridhar Malavali if (ha->mcp) { 1986a9083016SGiridhar Malavali DEBUG3_11(printk(KERN_INFO "%s(%ld): " 1987a9083016SGiridhar Malavali "Got mailbox completion. cmd=%x.\n", 1988a9083016SGiridhar Malavali __func__, vha->host_no, ha->mcp->mb[0])); 1989a9083016SGiridhar Malavali } else { 1990a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 1991a9083016SGiridhar Malavali "%s(%ld): MBX pointer ERROR!\n", 1992a9083016SGiridhar Malavali __func__, vha->host_no); 1993a9083016SGiridhar Malavali } 1994a9083016SGiridhar Malavali } 1995a9083016SGiridhar Malavali 1996a9083016SGiridhar Malavali /* 1997a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1998a9083016SGiridhar Malavali * @irq: 1999a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2000a9083016SGiridhar Malavali * @regs: 2001a9083016SGiridhar Malavali * 2002a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2003a9083016SGiridhar Malavali * 2004a9083016SGiridhar Malavali * Returns handled flag. 2005a9083016SGiridhar Malavali */ 2006a9083016SGiridhar Malavali irqreturn_t 2007a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2008a9083016SGiridhar Malavali { 2009a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2010a9083016SGiridhar Malavali struct qla_hw_data *ha; 2011a9083016SGiridhar Malavali struct rsp_que *rsp; 2012a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2013a9083016SGiridhar Malavali int status = 0, status1 = 0; 2014a9083016SGiridhar Malavali unsigned long flags; 2015a9083016SGiridhar Malavali unsigned long iter; 2016a9083016SGiridhar Malavali uint32_t stat; 2017a9083016SGiridhar Malavali uint16_t mb[4]; 2018a9083016SGiridhar Malavali 2019a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2020a9083016SGiridhar Malavali if (!rsp) { 2021a9083016SGiridhar Malavali printk(KERN_INFO 2022a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2023a9083016SGiridhar Malavali return IRQ_NONE; 2024a9083016SGiridhar Malavali } 2025a9083016SGiridhar Malavali ha = rsp->hw; 2026a9083016SGiridhar Malavali 2027a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2028a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2029a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2030a9083016SGiridhar Malavali return IRQ_NONE; 2031a9083016SGiridhar Malavali 2032a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2033a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2034a9083016SGiridhar Malavali return IRQ_NONE; 2035a9083016SGiridhar Malavali } 2036a9083016SGiridhar Malavali 2037a9083016SGiridhar Malavali /* clear the interrupt */ 2038a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2039a9083016SGiridhar Malavali 2040a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2041a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2042a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2043a9083016SGiridhar Malavali 2044a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2045a9083016SGiridhar Malavali 2046a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2047a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2048a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2049a9083016SGiridhar Malavali 2050a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2051a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2052a9083016SGiridhar Malavali 2053a9083016SGiridhar Malavali switch (stat & 0xff) { 2054a9083016SGiridhar Malavali case 0x1: 2055a9083016SGiridhar Malavali case 0x2: 2056a9083016SGiridhar Malavali case 0x10: 2057a9083016SGiridhar Malavali case 0x11: 2058a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2059a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2060a9083016SGiridhar Malavali break; 2061a9083016SGiridhar Malavali case 0x12: 2062a9083016SGiridhar Malavali mb[0] = MSW(stat); 2063a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2064a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2065a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2066a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2067a9083016SGiridhar Malavali break; 2068a9083016SGiridhar Malavali case 0x13: 2069a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2070a9083016SGiridhar Malavali break; 2071a9083016SGiridhar Malavali default: 2072a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): " 2073a9083016SGiridhar Malavali " Unrecognized interrupt type (%d).\n", 2074a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2075a9083016SGiridhar Malavali break; 2076a9083016SGiridhar Malavali } 2077a9083016SGiridhar Malavali } 2078a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2079a9083016SGiridhar Malavali } 2080a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2081a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2082a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2083a9083016SGiridhar Malavali 2084a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2085a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 2086a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2087a9083016SGiridhar Malavali "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2088a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2089a9083016SGiridhar Malavali #endif 2090a9083016SGiridhar Malavali 2091a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2092a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2093a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2094a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2095a9083016SGiridhar Malavali } 2096a9083016SGiridhar Malavali return IRQ_HANDLED; 2097a9083016SGiridhar Malavali } 2098a9083016SGiridhar Malavali 2099a9083016SGiridhar Malavali irqreturn_t 2100a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2101a9083016SGiridhar Malavali { 2102a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2103a9083016SGiridhar Malavali struct qla_hw_data *ha; 2104a9083016SGiridhar Malavali struct rsp_que *rsp; 2105a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2106a9083016SGiridhar Malavali int status = 0; 2107a9083016SGiridhar Malavali unsigned long flags; 2108a9083016SGiridhar Malavali uint32_t stat; 2109a9083016SGiridhar Malavali uint16_t mb[4]; 2110a9083016SGiridhar Malavali 2111a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2112a9083016SGiridhar Malavali if (!rsp) { 2113a9083016SGiridhar Malavali printk(KERN_INFO 2114a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2115a9083016SGiridhar Malavali return IRQ_NONE; 2116a9083016SGiridhar Malavali } 2117a9083016SGiridhar Malavali ha = rsp->hw; 2118a9083016SGiridhar Malavali 2119a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2120a9083016SGiridhar Malavali 2121a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2122a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2123a9083016SGiridhar Malavali do { 2124a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2125a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2126a9083016SGiridhar Malavali 2127a9083016SGiridhar Malavali switch (stat & 0xff) { 2128a9083016SGiridhar Malavali case 0x1: 2129a9083016SGiridhar Malavali case 0x2: 2130a9083016SGiridhar Malavali case 0x10: 2131a9083016SGiridhar Malavali case 0x11: 2132a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2133a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2134a9083016SGiridhar Malavali break; 2135a9083016SGiridhar Malavali case 0x12: 2136a9083016SGiridhar Malavali mb[0] = MSW(stat); 2137a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2138a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2139a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2140a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2141a9083016SGiridhar Malavali break; 2142a9083016SGiridhar Malavali case 0x13: 2143a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2144a9083016SGiridhar Malavali break; 2145a9083016SGiridhar Malavali default: 2146a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): " 2147a9083016SGiridhar Malavali " Unrecognized interrupt type (%d).\n", 2148a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2149a9083016SGiridhar Malavali break; 2150a9083016SGiridhar Malavali } 2151a9083016SGiridhar Malavali } 2152a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2153a9083016SGiridhar Malavali } while (0); 2154a9083016SGiridhar Malavali 2155a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2156a9083016SGiridhar Malavali 2157a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2158a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 2159a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2160a9083016SGiridhar Malavali "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", 2161a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2162a9083016SGiridhar Malavali #endif 2163a9083016SGiridhar Malavali 2164a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2165a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2166a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2167a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2168a9083016SGiridhar Malavali } 2169a9083016SGiridhar Malavali return IRQ_HANDLED; 2170a9083016SGiridhar Malavali } 2171a9083016SGiridhar Malavali 2172a9083016SGiridhar Malavali irqreturn_t 2173a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2174a9083016SGiridhar Malavali { 2175a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2176a9083016SGiridhar Malavali struct qla_hw_data *ha; 2177a9083016SGiridhar Malavali struct rsp_que *rsp; 2178a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2179a9083016SGiridhar Malavali 2180a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2181a9083016SGiridhar Malavali if (!rsp) { 2182a9083016SGiridhar Malavali printk(KERN_INFO 2183a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2184a9083016SGiridhar Malavali return IRQ_NONE; 2185a9083016SGiridhar Malavali } 2186a9083016SGiridhar Malavali 2187a9083016SGiridhar Malavali ha = rsp->hw; 2188a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2189a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2190a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2191a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2192a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2193a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2194a9083016SGiridhar Malavali return IRQ_HANDLED; 2195a9083016SGiridhar Malavali } 2196a9083016SGiridhar Malavali 2197a9083016SGiridhar Malavali void 2198a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2199a9083016SGiridhar Malavali { 2200a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2201a9083016SGiridhar Malavali struct qla_hw_data *ha; 2202a9083016SGiridhar Malavali struct rsp_que *rsp; 2203a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2204a9083016SGiridhar Malavali int status = 0; 2205a9083016SGiridhar Malavali uint32_t stat; 2206a9083016SGiridhar Malavali uint16_t mb[4]; 2207a9083016SGiridhar Malavali unsigned long flags; 2208a9083016SGiridhar Malavali 2209a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2210a9083016SGiridhar Malavali if (!rsp) { 2211a9083016SGiridhar Malavali printk(KERN_INFO 2212a9083016SGiridhar Malavali "%s(): NULL response queue pointer\n", __func__); 2213a9083016SGiridhar Malavali return; 2214a9083016SGiridhar Malavali } 2215a9083016SGiridhar Malavali ha = rsp->hw; 2216a9083016SGiridhar Malavali 2217a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2218a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2219a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2220a9083016SGiridhar Malavali 2221a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2222a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2223a9083016SGiridhar Malavali switch (stat & 0xff) { 2224a9083016SGiridhar Malavali case 0x1: 2225a9083016SGiridhar Malavali case 0x2: 2226a9083016SGiridhar Malavali case 0x10: 2227a9083016SGiridhar Malavali case 0x11: 2228a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2229a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2230a9083016SGiridhar Malavali break; 2231a9083016SGiridhar Malavali case 0x12: 2232a9083016SGiridhar Malavali mb[0] = MSW(stat); 2233a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2234a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2235a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2236a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2237a9083016SGiridhar Malavali break; 2238a9083016SGiridhar Malavali case 0x13: 2239a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2240a9083016SGiridhar Malavali break; 2241a9083016SGiridhar Malavali default: 2242a9083016SGiridhar Malavali DEBUG2(printk("scsi(%ld): Unrecognized interrupt type " 2243a9083016SGiridhar Malavali "(%d).\n", 2244a9083016SGiridhar Malavali vha->host_no, stat & 0xff)); 2245a9083016SGiridhar Malavali break; 2246a9083016SGiridhar Malavali } 2247a9083016SGiridhar Malavali } 2248a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2249a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2250a9083016SGiridhar Malavali } 2251a9083016SGiridhar Malavali 2252a9083016SGiridhar Malavali void 2253a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2254a9083016SGiridhar Malavali { 2255a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2256a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2257a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2258a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2259a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2260a9083016SGiridhar Malavali ha->interrupts_on = 1; 2261a9083016SGiridhar Malavali } 2262a9083016SGiridhar Malavali 2263a9083016SGiridhar Malavali void 2264a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2265a9083016SGiridhar Malavali { 2266a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2267a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2268a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2269a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2270a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2271a9083016SGiridhar Malavali ha->interrupts_on = 0; 2272a9083016SGiridhar Malavali } 2273a9083016SGiridhar Malavali 2274a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2275a9083016SGiridhar Malavali { 2276a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2277a9083016SGiridhar Malavali 2278a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2279a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2280a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2281a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2282a9083016SGiridhar Malavali ha->curr_window = 255; 2283a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2284a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2285a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2286a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2287a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2288a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2289a9083016SGiridhar Malavali } 2290a9083016SGiridhar Malavali 2291a5b36321SLalit Chandivade inline void 2292a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2293a9083016SGiridhar Malavali { 2294a9083016SGiridhar Malavali uint32_t drv_active; 2295a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2296a9083016SGiridhar Malavali 2297a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2298a9083016SGiridhar Malavali 2299a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2300a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 230177e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 230277e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2303a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2304a9083016SGiridhar Malavali } 230577e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2306a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2307a9083016SGiridhar Malavali } 2308a9083016SGiridhar Malavali 2309a9083016SGiridhar Malavali inline void 2310a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2311a9083016SGiridhar Malavali { 2312a9083016SGiridhar Malavali uint32_t drv_active; 2313a9083016SGiridhar Malavali 2314a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 231577e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2316a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2317a9083016SGiridhar Malavali } 2318a9083016SGiridhar Malavali 2319a9083016SGiridhar Malavali static inline int 2320a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2321a9083016SGiridhar Malavali { 2322a9083016SGiridhar Malavali uint32_t drv_state; 2323a9083016SGiridhar Malavali int rval; 2324a9083016SGiridhar Malavali 2325a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 232677e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2327a9083016SGiridhar Malavali return rval; 2328a9083016SGiridhar Malavali } 2329a9083016SGiridhar Malavali 2330a9083016SGiridhar Malavali static inline void 2331a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2332a9083016SGiridhar Malavali { 2333a9083016SGiridhar Malavali uint32_t drv_state; 2334a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2335a9083016SGiridhar Malavali 2336a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2337a9083016SGiridhar Malavali 2338a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2339a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 234077e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2341a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2342a9083016SGiridhar Malavali } 2343a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2344a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2345a9083016SGiridhar Malavali "%s(%ld):drv_state = 0x%x\n", 2346a9083016SGiridhar Malavali __func__, vha->host_no, drv_state); 2347a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2348a9083016SGiridhar Malavali } 2349a9083016SGiridhar Malavali 2350a9083016SGiridhar Malavali static inline void 2351a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2352a9083016SGiridhar Malavali { 2353a9083016SGiridhar Malavali uint32_t drv_state; 2354a9083016SGiridhar Malavali 2355a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2356a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2357a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2358a9083016SGiridhar Malavali } 2359a9083016SGiridhar Malavali 2360a9083016SGiridhar Malavali static inline void 2361a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2362a9083016SGiridhar Malavali { 2363a9083016SGiridhar Malavali uint32_t qsnt_state; 2364a9083016SGiridhar Malavali 2365a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2366a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2367a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2368a9083016SGiridhar Malavali } 2369a9083016SGiridhar Malavali 2370579d12b5SSaurav Kashyap void 2371579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2372579d12b5SSaurav Kashyap { 2373579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2374579d12b5SSaurav Kashyap uint32_t qsnt_state; 2375579d12b5SSaurav Kashyap 2376579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2377579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2378579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2379579d12b5SSaurav Kashyap } 2380579d12b5SSaurav Kashyap 238177e334d2SGiridhar Malavali static int 238277e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2383a9083016SGiridhar Malavali { 2384a9083016SGiridhar Malavali int rst; 2385a9083016SGiridhar Malavali struct fw_blob *blob; 2386a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2387a9083016SGiridhar Malavali 2388a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2389a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2390a9083016SGiridhar Malavali "%s: Error during CRB Initialization\n", __func__); 2391a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2392a9083016SGiridhar Malavali } 2393a9083016SGiridhar Malavali udelay(500); 2394a9083016SGiridhar Malavali 2395a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2396a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2397a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2398a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2399a9083016SGiridhar Malavali 2400a9083016SGiridhar Malavali /* 2401a9083016SGiridhar Malavali * FW Load priority: 2402a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2403a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2404a9083016SGiridhar Malavali */ 2405a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2406a9083016SGiridhar Malavali goto try_blob_fw; 2407a9083016SGiridhar Malavali 2408a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2409a9083016SGiridhar Malavali "Attempting to load firmware from flash\n"); 2410a9083016SGiridhar Malavali 2411a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2412a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2413a9083016SGiridhar Malavali "Firmware loaded successfully from flash\n"); 2414a9083016SGiridhar Malavali return QLA_SUCCESS; 2415875efad7SChad Dupuis } else { 2416875efad7SChad Dupuis qla_printk(KERN_ERR, ha, 2417875efad7SChad Dupuis "Firmware load from flash failed\n"); 2418a9083016SGiridhar Malavali } 2419875efad7SChad Dupuis 2420a9083016SGiridhar Malavali try_blob_fw: 2421a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2422a9083016SGiridhar Malavali "Attempting to load firmware from blob\n"); 2423a9083016SGiridhar Malavali 2424a9083016SGiridhar Malavali /* Load firmware blob. */ 2425a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2426a9083016SGiridhar Malavali if (!blob) { 2427a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2428a9083016SGiridhar Malavali "Firmware image not present.\n"); 2429a9083016SGiridhar Malavali goto fw_load_failed; 2430a9083016SGiridhar Malavali } 2431a9083016SGiridhar Malavali 24329c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24339c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24349c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24359c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24369c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24379c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24389c2b2975SHarish Zunjarrao qla_printk(KERN_ERR, ha, 24399c2b2975SHarish Zunjarrao "No valid firmware image found!!!"); 24409c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24419c2b2975SHarish Zunjarrao } 24429c2b2975SHarish Zunjarrao } 24439c2b2975SHarish Zunjarrao 2444a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2445a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2446a9083016SGiridhar Malavali "%s: Firmware loaded successfully " 2447a9083016SGiridhar Malavali " from binary blob\n", __func__); 2448a9083016SGiridhar Malavali return QLA_SUCCESS; 2449a9083016SGiridhar Malavali } else { 2450a9083016SGiridhar Malavali qla_printk(KERN_ERR, ha, 2451a9083016SGiridhar Malavali "Firmware load failed from binary blob\n"); 2452a9083016SGiridhar Malavali blob->fw = NULL; 2453a9083016SGiridhar Malavali blob = NULL; 2454a9083016SGiridhar Malavali goto fw_load_failed; 2455a9083016SGiridhar Malavali } 2456a9083016SGiridhar Malavali return QLA_SUCCESS; 2457a9083016SGiridhar Malavali 2458a9083016SGiridhar Malavali fw_load_failed: 2459a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2460a9083016SGiridhar Malavali } 2461a9083016SGiridhar Malavali 2462a5b36321SLalit Chandivade int 2463a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2464a9083016SGiridhar Malavali { 2465a9083016SGiridhar Malavali int pcie_cap; 2466a9083016SGiridhar Malavali uint16_t lnk; 2467a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2468a9083016SGiridhar Malavali 2469a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 247077e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2471a9083016SGiridhar Malavali 24723711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 24733711333dSGiridhar Malavali * of 0 before resetting the hardware 24743711333dSGiridhar Malavali */ 24753711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 24763711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 24773711333dSGiridhar Malavali 2478a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2479a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2480a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2481a9083016SGiridhar Malavali 2482a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2483a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2484a9083016SGiridhar Malavali "%s: Error trying to start fw!\n", __func__); 2485a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2486a9083016SGiridhar Malavali } 2487a9083016SGiridhar Malavali 2488a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2489a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2490a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 2491a9083016SGiridhar Malavali "%s: Error during card handshake!\n", __func__); 2492a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2493a9083016SGiridhar Malavali } 2494a9083016SGiridhar Malavali 2495a9083016SGiridhar Malavali /* Negotiated Link width */ 2496a9083016SGiridhar Malavali pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2497a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2498a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2499a9083016SGiridhar Malavali 2500a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2501a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2502a9083016SGiridhar Malavali } 2503a9083016SGiridhar Malavali 2504a9083016SGiridhar Malavali static inline int 2505a9083016SGiridhar Malavali qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2506a9083016SGiridhar Malavali uint16_t tot_dsds) 2507a9083016SGiridhar Malavali { 2508a9083016SGiridhar Malavali uint32_t *cur_dsd = NULL; 2509a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2510a9083016SGiridhar Malavali struct qla_hw_data *ha; 2511a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2512a9083016SGiridhar Malavali struct scatterlist *cur_seg; 2513a9083016SGiridhar Malavali uint32_t *dsd_seg; 2514a9083016SGiridhar Malavali void *next_dsd; 2515a9083016SGiridhar Malavali uint8_t avail_dsds; 2516a9083016SGiridhar Malavali uint8_t first_iocb = 1; 2517a9083016SGiridhar Malavali uint32_t dsd_list_len; 2518a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2519a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2520a9083016SGiridhar Malavali 2521a9083016SGiridhar Malavali cmd = sp->cmd; 2522a9083016SGiridhar Malavali 2523a9083016SGiridhar Malavali /* Update entry type to indicate Command Type 3 IOCB */ 2524a9083016SGiridhar Malavali *((uint32_t *)(&cmd_pkt->entry_type)) = 2525a9083016SGiridhar Malavali __constant_cpu_to_le32(COMMAND_TYPE_6); 2526a9083016SGiridhar Malavali 2527a9083016SGiridhar Malavali /* No data transfer */ 2528a9083016SGiridhar Malavali if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2529a9083016SGiridhar Malavali cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2530a9083016SGiridhar Malavali return 0; 2531a9083016SGiridhar Malavali } 2532a9083016SGiridhar Malavali 2533a9083016SGiridhar Malavali vha = sp->fcport->vha; 2534a9083016SGiridhar Malavali ha = vha->hw; 2535a9083016SGiridhar Malavali 2536a9083016SGiridhar Malavali /* Set transfer direction */ 2537a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2538a9083016SGiridhar Malavali cmd_pkt->control_flags = 2539a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_WRITE_DATA); 2540a9083016SGiridhar Malavali ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2541a9083016SGiridhar Malavali } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2542a9083016SGiridhar Malavali cmd_pkt->control_flags = 2543a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_READ_DATA); 2544a9083016SGiridhar Malavali ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2545a9083016SGiridhar Malavali } 2546a9083016SGiridhar Malavali 2547a9083016SGiridhar Malavali cur_seg = scsi_sglist(cmd); 2548a9083016SGiridhar Malavali ctx = sp->ctx; 2549a9083016SGiridhar Malavali 2550a9083016SGiridhar Malavali while (tot_dsds) { 2551a9083016SGiridhar Malavali avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2552a9083016SGiridhar Malavali QLA_DSDS_PER_IOCB : tot_dsds; 2553a9083016SGiridhar Malavali tot_dsds -= avail_dsds; 2554a9083016SGiridhar Malavali dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2555a9083016SGiridhar Malavali 2556a9083016SGiridhar Malavali dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2557a9083016SGiridhar Malavali struct dsd_dma, list); 2558a9083016SGiridhar Malavali next_dsd = dsd_ptr->dsd_addr; 2559a9083016SGiridhar Malavali list_del(&dsd_ptr->list); 2560a9083016SGiridhar Malavali ha->gbl_dsd_avail--; 2561a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2562a9083016SGiridhar Malavali ctx->dsd_use_cnt++; 2563a9083016SGiridhar Malavali ha->gbl_dsd_inuse++; 2564a9083016SGiridhar Malavali 2565a9083016SGiridhar Malavali if (first_iocb) { 2566a9083016SGiridhar Malavali first_iocb = 0; 2567a9083016SGiridhar Malavali dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2568a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2569a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2570fa96d927SAndrew Vasquez *dsd_seg++ = cpu_to_le32(dsd_list_len); 2571a9083016SGiridhar Malavali } else { 2572a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2573a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2574fa96d927SAndrew Vasquez *cur_dsd++ = cpu_to_le32(dsd_list_len); 2575a9083016SGiridhar Malavali } 2576a9083016SGiridhar Malavali cur_dsd = (uint32_t *)next_dsd; 2577a9083016SGiridhar Malavali while (avail_dsds) { 2578a9083016SGiridhar Malavali dma_addr_t sle_dma; 2579a9083016SGiridhar Malavali 2580a9083016SGiridhar Malavali sle_dma = sg_dma_address(cur_seg); 2581a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2582a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2583a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2584aa5cbf8aSGiridhar Malavali cur_seg = sg_next(cur_seg); 2585a9083016SGiridhar Malavali avail_dsds--; 2586a9083016SGiridhar Malavali } 2587a9083016SGiridhar Malavali } 2588a9083016SGiridhar Malavali 2589a9083016SGiridhar Malavali /* Null termination */ 2590a9083016SGiridhar Malavali *cur_dsd++ = 0; 2591a9083016SGiridhar Malavali *cur_dsd++ = 0; 2592a9083016SGiridhar Malavali *cur_dsd++ = 0; 2593a9083016SGiridhar Malavali cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2594a9083016SGiridhar Malavali return 0; 2595a9083016SGiridhar Malavali } 2596a9083016SGiridhar Malavali 2597a9083016SGiridhar Malavali /* 2598a9083016SGiridhar Malavali * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2599a9083016SGiridhar Malavali * for Command Type 6. 2600a9083016SGiridhar Malavali * 2601a9083016SGiridhar Malavali * @dsds: number of data segment decriptors needed 2602a9083016SGiridhar Malavali * 2603a9083016SGiridhar Malavali * Returns the number of dsd list needed to store @dsds. 2604a9083016SGiridhar Malavali */ 2605a9083016SGiridhar Malavali inline uint16_t 2606a9083016SGiridhar Malavali qla82xx_calc_dsd_lists(uint16_t dsds) 2607a9083016SGiridhar Malavali { 2608a9083016SGiridhar Malavali uint16_t dsd_lists = 0; 2609a9083016SGiridhar Malavali 2610a9083016SGiridhar Malavali dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2611a9083016SGiridhar Malavali if (dsds % QLA_DSDS_PER_IOCB) 2612a9083016SGiridhar Malavali dsd_lists++; 2613a9083016SGiridhar Malavali return dsd_lists; 2614a9083016SGiridhar Malavali } 2615a9083016SGiridhar Malavali 2616a9083016SGiridhar Malavali /* 2617a9083016SGiridhar Malavali * qla82xx_start_scsi() - Send a SCSI command to the ISP 2618a9083016SGiridhar Malavali * @sp: command to send to the ISP 2619a9083016SGiridhar Malavali * 262025985edcSLucas De Marchi * Returns non-zero if a failure occurred, else zero. 2621a9083016SGiridhar Malavali */ 2622a9083016SGiridhar Malavali int 2623a9083016SGiridhar Malavali qla82xx_start_scsi(srb_t *sp) 2624a9083016SGiridhar Malavali { 2625a9083016SGiridhar Malavali int ret, nseg; 2626a9083016SGiridhar Malavali unsigned long flags; 2627a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2628a9083016SGiridhar Malavali uint32_t *clr_ptr; 2629a9083016SGiridhar Malavali uint32_t index; 2630a9083016SGiridhar Malavali uint32_t handle; 2631a9083016SGiridhar Malavali uint16_t cnt; 2632a9083016SGiridhar Malavali uint16_t req_cnt; 2633a9083016SGiridhar Malavali uint16_t tot_dsds; 2634a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2635a9083016SGiridhar Malavali uint32_t dbval; 2636a9083016SGiridhar Malavali uint32_t *fcp_dl; 2637a9083016SGiridhar Malavali uint8_t additional_cdb_len; 2638a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2639a9083016SGiridhar Malavali struct scsi_qla_host *vha = sp->fcport->vha; 2640a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2641a9083016SGiridhar Malavali struct req_que *req = NULL; 2642a9083016SGiridhar Malavali struct rsp_que *rsp = NULL; 2643ff2fc42eSAndrew Vasquez char tag[2]; 2644a9083016SGiridhar Malavali 2645a9083016SGiridhar Malavali /* Setup device pointers. */ 2646a9083016SGiridhar Malavali ret = 0; 2647a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2648a9083016SGiridhar Malavali cmd = sp->cmd; 2649a9083016SGiridhar Malavali req = vha->req; 2650a9083016SGiridhar Malavali rsp = ha->rsp_q_map[0]; 2651a9083016SGiridhar Malavali 2652a9083016SGiridhar Malavali /* So we know we haven't pci_map'ed anything yet */ 2653a9083016SGiridhar Malavali tot_dsds = 0; 2654a9083016SGiridhar Malavali 2655a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2656a9083016SGiridhar Malavali 2657a9083016SGiridhar Malavali /* Send marker if required */ 2658a9083016SGiridhar Malavali if (vha->marker_needed != 0) { 2659a9083016SGiridhar Malavali if (qla2x00_marker(vha, req, 2660a9083016SGiridhar Malavali rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) 2661a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2662a9083016SGiridhar Malavali vha->marker_needed = 0; 2663a9083016SGiridhar Malavali } 2664a9083016SGiridhar Malavali 2665a9083016SGiridhar Malavali /* Acquire ring specific lock */ 2666a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2667a9083016SGiridhar Malavali 2668a9083016SGiridhar Malavali /* Check for room in outstanding command list. */ 2669a9083016SGiridhar Malavali handle = req->current_outstanding_cmd; 2670a9083016SGiridhar Malavali for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2671a9083016SGiridhar Malavali handle++; 2672a9083016SGiridhar Malavali if (handle == MAX_OUTSTANDING_COMMANDS) 2673a9083016SGiridhar Malavali handle = 1; 2674a9083016SGiridhar Malavali if (!req->outstanding_cmds[handle]) 2675a9083016SGiridhar Malavali break; 2676a9083016SGiridhar Malavali } 2677a9083016SGiridhar Malavali if (index == MAX_OUTSTANDING_COMMANDS) 2678a9083016SGiridhar Malavali goto queuing_error; 2679a9083016SGiridhar Malavali 2680a9083016SGiridhar Malavali /* Map the sg table so we have an accurate count of sg entries needed */ 2681a9083016SGiridhar Malavali if (scsi_sg_count(cmd)) { 2682a9083016SGiridhar Malavali nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2683a9083016SGiridhar Malavali scsi_sg_count(cmd), cmd->sc_data_direction); 2684a9083016SGiridhar Malavali if (unlikely(!nseg)) 2685a9083016SGiridhar Malavali goto queuing_error; 2686a9083016SGiridhar Malavali } else 2687a9083016SGiridhar Malavali nseg = 0; 2688a9083016SGiridhar Malavali 2689a9083016SGiridhar Malavali tot_dsds = nseg; 2690a9083016SGiridhar Malavali 2691a9083016SGiridhar Malavali if (tot_dsds > ql2xshiftctondsd) { 2692a9083016SGiridhar Malavali struct cmd_type_6 *cmd_pkt; 2693a9083016SGiridhar Malavali uint16_t more_dsd_lists = 0; 2694a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2695a9083016SGiridhar Malavali uint16_t i; 2696a9083016SGiridhar Malavali 2697a9083016SGiridhar Malavali more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 2698a9083016SGiridhar Malavali if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) 2699a9083016SGiridhar Malavali goto queuing_error; 2700a9083016SGiridhar Malavali 2701a9083016SGiridhar Malavali if (more_dsd_lists <= ha->gbl_dsd_avail) 2702a9083016SGiridhar Malavali goto sufficient_dsds; 2703a9083016SGiridhar Malavali else 2704a9083016SGiridhar Malavali more_dsd_lists -= ha->gbl_dsd_avail; 2705a9083016SGiridhar Malavali 2706a9083016SGiridhar Malavali for (i = 0; i < more_dsd_lists; i++) { 2707a9083016SGiridhar Malavali dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 2708a9083016SGiridhar Malavali if (!dsd_ptr) 2709a9083016SGiridhar Malavali goto queuing_error; 2710a9083016SGiridhar Malavali 2711a9083016SGiridhar Malavali dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2712a9083016SGiridhar Malavali GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2713a9083016SGiridhar Malavali if (!dsd_ptr->dsd_addr) { 2714a9083016SGiridhar Malavali kfree(dsd_ptr); 2715a9083016SGiridhar Malavali goto queuing_error; 2716a9083016SGiridhar Malavali } 2717a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2718a9083016SGiridhar Malavali ha->gbl_dsd_avail++; 2719a9083016SGiridhar Malavali } 2720a9083016SGiridhar Malavali 2721a9083016SGiridhar Malavali sufficient_dsds: 2722a9083016SGiridhar Malavali req_cnt = 1; 2723a9083016SGiridhar Malavali 27241bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 27251bd58b89SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 27261bd58b89SGiridhar Malavali ®->req_q_out[0]); 27271bd58b89SGiridhar Malavali if (req->ring_index < cnt) 27281bd58b89SGiridhar Malavali req->cnt = cnt - req->ring_index; 27291bd58b89SGiridhar Malavali else 27301bd58b89SGiridhar Malavali req->cnt = req->length - 27311bd58b89SGiridhar Malavali (req->ring_index - cnt); 27321bd58b89SGiridhar Malavali } 27331bd58b89SGiridhar Malavali 27341bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 27351bd58b89SGiridhar Malavali goto queuing_error; 27361bd58b89SGiridhar Malavali 2737a9083016SGiridhar Malavali ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2738a9083016SGiridhar Malavali if (!sp->ctx) { 2739a9083016SGiridhar Malavali DEBUG(printk(KERN_INFO 2740a9083016SGiridhar Malavali "%s(%ld): failed to allocate" 2741a9083016SGiridhar Malavali " ctx.\n", __func__, vha->host_no)); 2742a9083016SGiridhar Malavali goto queuing_error; 2743a9083016SGiridhar Malavali } 2744a9083016SGiridhar Malavali memset(ctx, 0, sizeof(struct ct6_dsd)); 2745a9083016SGiridhar Malavali ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2746a9083016SGiridhar Malavali GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2747a9083016SGiridhar Malavali if (!ctx->fcp_cmnd) { 2748a9083016SGiridhar Malavali DEBUG2_3(printk("%s(%ld): failed to allocate" 2749a9083016SGiridhar Malavali " fcp_cmnd.\n", __func__, vha->host_no)); 2750a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2751a9083016SGiridhar Malavali } 2752a9083016SGiridhar Malavali 2753a9083016SGiridhar Malavali /* Initialize the DSD list and dma handle */ 2754a9083016SGiridhar Malavali INIT_LIST_HEAD(&ctx->dsd_list); 2755a9083016SGiridhar Malavali ctx->dsd_use_cnt = 0; 2756a9083016SGiridhar Malavali 2757a9083016SGiridhar Malavali if (cmd->cmd_len > 16) { 2758a9083016SGiridhar Malavali additional_cdb_len = cmd->cmd_len - 16; 2759a9083016SGiridhar Malavali if ((cmd->cmd_len % 4) != 0) { 2760a9083016SGiridhar Malavali /* SCSI command bigger than 16 bytes must be 2761a9083016SGiridhar Malavali * multiple of 4 2762a9083016SGiridhar Malavali */ 2763a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2764a9083016SGiridhar Malavali } 2765a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2766a9083016SGiridhar Malavali } else { 2767a9083016SGiridhar Malavali additional_cdb_len = 0; 2768a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + 16 + 4; 2769a9083016SGiridhar Malavali } 2770a9083016SGiridhar Malavali 2771a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2772a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2773a9083016SGiridhar Malavali 2774a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2775a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2776a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2777a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2778a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2779a9083016SGiridhar Malavali 2780a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2781a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2782a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2783a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2784a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2785a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2786a9083016SGiridhar Malavali 2787a9083016SGiridhar Malavali /* Build IOCB segments */ 2788a9083016SGiridhar Malavali if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2789a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2790a9083016SGiridhar Malavali 2791a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 279285727e1fSMike Hernandez host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun)); 2793a9083016SGiridhar Malavali 2794ff2fc42eSAndrew Vasquez /* 2795ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2796ff2fc42eSAndrew Vasquez */ 2797ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2798ff2fc42eSAndrew Vasquez switch (tag[0]) { 2799ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2800ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2801ff2fc42eSAndrew Vasquez TSK_HEAD_OF_QUEUE; 2802ff2fc42eSAndrew Vasquez break; 2803ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2804ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2805ff2fc42eSAndrew Vasquez TSK_ORDERED; 2806ff2fc42eSAndrew Vasquez break; 2807ff2fc42eSAndrew Vasquez } 2808ff2fc42eSAndrew Vasquez } 2809ff2fc42eSAndrew Vasquez 2810a9083016SGiridhar Malavali /* build FCP_CMND IU */ 2811a9083016SGiridhar Malavali memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 2812a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 2813a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 2814a9083016SGiridhar Malavali 2815a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) 2816a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 1; 2817a9083016SGiridhar Malavali else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 2818a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 2; 2819a9083016SGiridhar Malavali 2820a9083016SGiridhar Malavali memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2821a9083016SGiridhar Malavali 2822a9083016SGiridhar Malavali fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2823a9083016SGiridhar Malavali additional_cdb_len); 2824a9083016SGiridhar Malavali *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2825a9083016SGiridhar Malavali 2826a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2827a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[0] = 2828a9083016SGiridhar Malavali cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2829a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[1] = 2830a9083016SGiridhar Malavali cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2831a9083016SGiridhar Malavali 2832a9083016SGiridhar Malavali sp->flags |= SRB_FCP_CMND_DMA_VALID; 2833a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2834a9083016SGiridhar Malavali /* Set total data segment count. */ 2835a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2836a9083016SGiridhar Malavali /* Specify response queue number where 2837a9083016SGiridhar Malavali * completion should happen 2838a9083016SGiridhar Malavali */ 2839a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2840a9083016SGiridhar Malavali } else { 2841a9083016SGiridhar Malavali struct cmd_type_7 *cmd_pkt; 2842a9083016SGiridhar Malavali req_cnt = qla24xx_calc_iocbs(tot_dsds); 2843a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 2844a9083016SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 2845a9083016SGiridhar Malavali ®->req_q_out[0]); 2846a9083016SGiridhar Malavali if (req->ring_index < cnt) 2847a9083016SGiridhar Malavali req->cnt = cnt - req->ring_index; 2848a9083016SGiridhar Malavali else 2849a9083016SGiridhar Malavali req->cnt = req->length - 2850a9083016SGiridhar Malavali (req->ring_index - cnt); 2851a9083016SGiridhar Malavali } 2852a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 2853a9083016SGiridhar Malavali goto queuing_error; 2854a9083016SGiridhar Malavali 2855a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 2856a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2857a9083016SGiridhar Malavali 2858a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2859a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 2860a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2861a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2862a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2863a9083016SGiridhar Malavali 2864a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2865a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2866a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2867a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2868a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2869a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2870a9083016SGiridhar Malavali 2871a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2872a9083016SGiridhar Malavali host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 2873a9083016SGiridhar Malavali sizeof(cmd_pkt->lun)); 2874a9083016SGiridhar Malavali 2875ff2fc42eSAndrew Vasquez /* 2876ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2877ff2fc42eSAndrew Vasquez */ 2878ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2879ff2fc42eSAndrew Vasquez switch (tag[0]) { 2880ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2881ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_HEAD_OF_QUEUE; 2882ff2fc42eSAndrew Vasquez break; 2883ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2884ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_ORDERED; 2885ff2fc42eSAndrew Vasquez break; 2886ff2fc42eSAndrew Vasquez } 2887ff2fc42eSAndrew Vasquez } 2888ff2fc42eSAndrew Vasquez 2889a9083016SGiridhar Malavali /* Load SCSI command packet. */ 2890a9083016SGiridhar Malavali memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 2891a9083016SGiridhar Malavali host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 2892a9083016SGiridhar Malavali 2893a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2894a9083016SGiridhar Malavali 2895a9083016SGiridhar Malavali /* Build IOCB segments */ 2896a9083016SGiridhar Malavali qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 2897a9083016SGiridhar Malavali 2898a9083016SGiridhar Malavali /* Set total data segment count. */ 2899a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2900a9083016SGiridhar Malavali /* Specify response queue number where 2901a9083016SGiridhar Malavali * completion should happen. 2902a9083016SGiridhar Malavali */ 2903a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2904a9083016SGiridhar Malavali 2905a9083016SGiridhar Malavali } 2906a9083016SGiridhar Malavali /* Build command packet. */ 2907a9083016SGiridhar Malavali req->current_outstanding_cmd = handle; 2908a9083016SGiridhar Malavali req->outstanding_cmds[handle] = sp; 2909a9083016SGiridhar Malavali sp->handle = handle; 2910a9083016SGiridhar Malavali sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 2911a9083016SGiridhar Malavali req->cnt -= req_cnt; 2912a9083016SGiridhar Malavali wmb(); 2913a9083016SGiridhar Malavali 2914a9083016SGiridhar Malavali /* Adjust ring index. */ 2915a9083016SGiridhar Malavali req->ring_index++; 2916a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2917a9083016SGiridhar Malavali req->ring_index = 0; 2918a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2919a9083016SGiridhar Malavali } else 2920a9083016SGiridhar Malavali req->ring_ptr++; 2921a9083016SGiridhar Malavali 2922a9083016SGiridhar Malavali sp->flags |= SRB_DMA_VALID; 2923a9083016SGiridhar Malavali 2924a9083016SGiridhar Malavali /* Set chip new ring index. */ 2925a9083016SGiridhar Malavali /* write, read and verify logic */ 2926a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2927a9083016SGiridhar Malavali if (ql2xdbwr) 2928a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2929a9083016SGiridhar Malavali else { 2930a9083016SGiridhar Malavali WRT_REG_DWORD( 2931a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2932a9083016SGiridhar Malavali dbval); 2933a9083016SGiridhar Malavali wmb(); 2934a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2935a9083016SGiridhar Malavali WRT_REG_DWORD( 2936a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2937a9083016SGiridhar Malavali dbval); 2938a9083016SGiridhar Malavali wmb(); 2939a9083016SGiridhar Malavali } 2940a9083016SGiridhar Malavali } 2941a9083016SGiridhar Malavali 2942a9083016SGiridhar Malavali /* Manage unprocessed RIO/ZIO commands in response queue. */ 2943a9083016SGiridhar Malavali if (vha->flags.process_response_queue && 2944a9083016SGiridhar Malavali rsp->ring_ptr->signature != RESPONSE_PROCESSED) 2945a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2946a9083016SGiridhar Malavali 2947a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2948a9083016SGiridhar Malavali return QLA_SUCCESS; 2949a9083016SGiridhar Malavali 2950a9083016SGiridhar Malavali queuing_error_fcp_cmnd: 2951a9083016SGiridhar Malavali dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 2952a9083016SGiridhar Malavali queuing_error: 2953a9083016SGiridhar Malavali if (tot_dsds) 2954a9083016SGiridhar Malavali scsi_dma_unmap(cmd); 2955a9083016SGiridhar Malavali 2956a9083016SGiridhar Malavali if (sp->ctx) { 2957a9083016SGiridhar Malavali mempool_free(sp->ctx, ha->ctx_mempool); 2958a9083016SGiridhar Malavali sp->ctx = NULL; 2959a9083016SGiridhar Malavali } 2960a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2961a9083016SGiridhar Malavali 2962a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2963a9083016SGiridhar Malavali } 2964a9083016SGiridhar Malavali 296577e334d2SGiridhar Malavali static uint32_t * 2966a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2967a9083016SGiridhar Malavali uint32_t length) 2968a9083016SGiridhar Malavali { 2969a9083016SGiridhar Malavali uint32_t i; 2970a9083016SGiridhar Malavali uint32_t val; 2971a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2972a9083016SGiridhar Malavali 2973a9083016SGiridhar Malavali /* Dword reads to flash. */ 2974a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2975a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2976a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 2977a9083016SGiridhar Malavali "Do ROM fast read failed\n"); 2978a9083016SGiridhar Malavali goto done_read; 2979a9083016SGiridhar Malavali } 2980a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 2981a9083016SGiridhar Malavali } 2982a9083016SGiridhar Malavali done_read: 2983a9083016SGiridhar Malavali return dwptr; 2984a9083016SGiridhar Malavali } 2985a9083016SGiridhar Malavali 298677e334d2SGiridhar Malavali static int 2987a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2988a9083016SGiridhar Malavali { 2989a9083016SGiridhar Malavali int ret; 2990a9083016SGiridhar Malavali uint32_t val; 2991a9083016SGiridhar Malavali 2992a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2993a9083016SGiridhar Malavali if (ret < 0) { 2994a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 2995a9083016SGiridhar Malavali return ret; 2996a9083016SGiridhar Malavali } 2997a9083016SGiridhar Malavali 2998a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2999a9083016SGiridhar Malavali if (ret < 0) 3000a9083016SGiridhar Malavali goto done_unprotect; 3001a9083016SGiridhar Malavali 30020547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 3003a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3004a9083016SGiridhar Malavali if (ret < 0) { 30050547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3006a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 3007a9083016SGiridhar Malavali } 3008a9083016SGiridhar Malavali 3009a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 3010a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3011a9083016SGiridhar Malavali 3012a9083016SGiridhar Malavali done_unprotect: 3013a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3014a9083016SGiridhar Malavali return ret; 3015a9083016SGiridhar Malavali } 3016a9083016SGiridhar Malavali 301777e334d2SGiridhar Malavali static int 3018a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 3019a9083016SGiridhar Malavali { 3020a9083016SGiridhar Malavali int ret; 3021a9083016SGiridhar Malavali uint32_t val; 3022a9083016SGiridhar Malavali 3023a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3024a9083016SGiridhar Malavali if (ret < 0) { 3025a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3026a9083016SGiridhar Malavali return ret; 3027a9083016SGiridhar Malavali } 3028a9083016SGiridhar Malavali 3029a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3030a9083016SGiridhar Malavali if (ret < 0) 3031a9083016SGiridhar Malavali goto done_protect; 3032a9083016SGiridhar Malavali 30330547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3034a9083016SGiridhar Malavali /* LOCK all sectors */ 3035a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3036a9083016SGiridhar Malavali if (ret < 0) 3037a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write status register failed\n"); 3038a9083016SGiridhar Malavali 3039a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 3040a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "Write disable failed\n"); 3041a9083016SGiridhar Malavali done_protect: 3042a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3043a9083016SGiridhar Malavali return ret; 3044a9083016SGiridhar Malavali } 3045a9083016SGiridhar Malavali 304677e334d2SGiridhar Malavali static int 3047a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3048a9083016SGiridhar Malavali { 3049a9083016SGiridhar Malavali int ret = 0; 3050a9083016SGiridhar Malavali 3051a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3052a9083016SGiridhar Malavali if (ret < 0) { 3053a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); 3054a9083016SGiridhar Malavali return ret; 3055a9083016SGiridhar Malavali } 3056a9083016SGiridhar Malavali 3057a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 3058a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3059a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3060a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3061a9083016SGiridhar Malavali 3062a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 3063a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3064a9083016SGiridhar Malavali "Error waiting for rom done\n"); 3065a9083016SGiridhar Malavali ret = -1; 3066a9083016SGiridhar Malavali goto done; 3067a9083016SGiridhar Malavali } 3068a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 3069a9083016SGiridhar Malavali done: 3070a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3071a9083016SGiridhar Malavali return ret; 3072a9083016SGiridhar Malavali } 3073a9083016SGiridhar Malavali 3074a9083016SGiridhar Malavali /* 3075a9083016SGiridhar Malavali * Address and length are byte address 3076a9083016SGiridhar Malavali */ 3077a9083016SGiridhar Malavali uint8_t * 3078a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3079a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3080a9083016SGiridhar Malavali { 3081a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3082a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3083a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3084a9083016SGiridhar Malavali return buf; 3085a9083016SGiridhar Malavali } 3086a9083016SGiridhar Malavali 3087a9083016SGiridhar Malavali static int 3088a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3089a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 3090a9083016SGiridhar Malavali { 3091a9083016SGiridhar Malavali int ret; 3092a9083016SGiridhar Malavali uint32_t liter; 3093a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 3094a9083016SGiridhar Malavali dma_addr_t optrom_dma; 3095a9083016SGiridhar Malavali void *optrom = NULL; 3096a9083016SGiridhar Malavali int page_mode = 0; 3097a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3098a9083016SGiridhar Malavali 3099a9083016SGiridhar Malavali ret = -1; 3100a9083016SGiridhar Malavali 3101a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 3102a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 3103a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 3104a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3105a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 3106a9083016SGiridhar Malavali if (!optrom) { 3107a9083016SGiridhar Malavali qla_printk(KERN_DEBUG, ha, 3108a9083016SGiridhar Malavali "Unable to allocate memory for optrom " 3109a9083016SGiridhar Malavali "burst write (%x KB).\n", 3110a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 3111a9083016SGiridhar Malavali } 3112a9083016SGiridhar Malavali } 3113a9083016SGiridhar Malavali 3114a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 3115a9083016SGiridhar Malavali sec_mask = ~rest_addr; 3116a9083016SGiridhar Malavali 3117a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 3118a9083016SGiridhar Malavali if (ret) { 3119a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3120a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 3121a9083016SGiridhar Malavali goto write_done; 3122a9083016SGiridhar Malavali } 3123a9083016SGiridhar Malavali 3124a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3125a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 3126a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 3127a9083016SGiridhar Malavali 3128a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 3129a9083016SGiridhar Malavali if (ret) { 3130a9083016SGiridhar Malavali DEBUG9(qla_printk(KERN_ERR, ha, 3131a9083016SGiridhar Malavali "Unable to erase sector: " 3132a9083016SGiridhar Malavali "address=%x.\n", faddr)); 3133a9083016SGiridhar Malavali break; 3134a9083016SGiridhar Malavali } 3135a9083016SGiridhar Malavali } 3136a9083016SGiridhar Malavali 3137a9083016SGiridhar Malavali /* Go with burst-write. */ 3138a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3139a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 3140a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3141a9083016SGiridhar Malavali 3142a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 3143a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3144a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 3145a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 3146a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3147a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 3148a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 3149a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3150a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 3151a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3152a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 3153a9083016SGiridhar Malavali 3154a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3155a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3156a9083016SGiridhar Malavali optrom = NULL; 3157a9083016SGiridhar Malavali } else { 3158a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 3159a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 3160a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 3161a9083016SGiridhar Malavali continue; 3162a9083016SGiridhar Malavali } 3163a9083016SGiridhar Malavali } 3164a9083016SGiridhar Malavali 3165a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 3166a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 3167a9083016SGiridhar Malavali if (ret) { 3168a9083016SGiridhar Malavali DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program" 3169a9083016SGiridhar Malavali "flash address=%x data=%x.\n", __func__, 3170a9083016SGiridhar Malavali ha->host_no, faddr, *dwptr)); 3171a9083016SGiridhar Malavali break; 3172a9083016SGiridhar Malavali } 3173a9083016SGiridhar Malavali } 3174a9083016SGiridhar Malavali 3175a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 3176a9083016SGiridhar Malavali if (ret) 3177a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3178a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 3179a9083016SGiridhar Malavali write_done: 3180a9083016SGiridhar Malavali if (optrom) 3181a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3182a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3183a9083016SGiridhar Malavali return ret; 3184a9083016SGiridhar Malavali } 3185a9083016SGiridhar Malavali 3186a9083016SGiridhar Malavali int 3187a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3188a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3189a9083016SGiridhar Malavali { 3190a9083016SGiridhar Malavali int rval; 3191a9083016SGiridhar Malavali 3192a9083016SGiridhar Malavali /* Suspend HBA. */ 3193a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3194a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3195a9083016SGiridhar Malavali length >> 2); 3196a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3197a9083016SGiridhar Malavali 3198a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 3199a9083016SGiridhar Malavali if (rval) 3200a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3201a9083016SGiridhar Malavali else 3202a9083016SGiridhar Malavali rval = QLA_SUCCESS; 3203a9083016SGiridhar Malavali return rval; 3204a9083016SGiridhar Malavali } 3205a9083016SGiridhar Malavali 3206a9083016SGiridhar Malavali void 3207a9083016SGiridhar Malavali qla82xx_start_iocbs(srb_t *sp) 3208a9083016SGiridhar Malavali { 3209a9083016SGiridhar Malavali struct qla_hw_data *ha = sp->fcport->vha->hw; 3210a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3211a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 3212a9083016SGiridhar Malavali uint32_t dbval; 3213a9083016SGiridhar Malavali 3214a9083016SGiridhar Malavali /* Adjust ring index. */ 3215a9083016SGiridhar Malavali req->ring_index++; 3216a9083016SGiridhar Malavali if (req->ring_index == req->length) { 3217a9083016SGiridhar Malavali req->ring_index = 0; 3218a9083016SGiridhar Malavali req->ring_ptr = req->ring; 3219a9083016SGiridhar Malavali } else 3220a9083016SGiridhar Malavali req->ring_ptr++; 3221a9083016SGiridhar Malavali 3222a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 3223a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 3224a9083016SGiridhar Malavali 3225a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 32266907869dSGiridhar Malavali if (ql2xdbwr) 32276907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 32286907869dSGiridhar Malavali else { 3229a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3230a9083016SGiridhar Malavali wmb(); 3231a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 32326907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 32336907869dSGiridhar Malavali dbval); 3234a9083016SGiridhar Malavali wmb(); 3235a9083016SGiridhar Malavali } 3236a9083016SGiridhar Malavali } 32376907869dSGiridhar Malavali } 3238a9083016SGiridhar Malavali 3239e6a4202aSShyam Sundar void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 3240e6a4202aSShyam Sundar { 3241e6a4202aSShyam Sundar if (qla82xx_rom_lock(ha)) 3242e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 3243e6a4202aSShyam Sundar qla_printk(KERN_INFO, ha, "Resetting rom_lock\n"); 3244e6a4202aSShyam Sundar 3245e6a4202aSShyam Sundar /* 3246e6a4202aSShyam Sundar * Either we got the lock, or someone 3247e6a4202aSShyam Sundar * else died while holding it. 3248e6a4202aSShyam Sundar * In either case, unlock. 3249e6a4202aSShyam Sundar */ 3250e6a4202aSShyam Sundar qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 3251e6a4202aSShyam Sundar } 3252e6a4202aSShyam Sundar 3253a9083016SGiridhar Malavali /* 3254a9083016SGiridhar Malavali * qla82xx_device_bootstrap 3255a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 3256a9083016SGiridhar Malavali * 3257a9083016SGiridhar Malavali * Note: 3258a9083016SGiridhar Malavali * IDC lock must be held upon entry 3259a9083016SGiridhar Malavali * 3260a9083016SGiridhar Malavali * Return: 3261a9083016SGiridhar Malavali * Success : 0 3262a9083016SGiridhar Malavali * Failed : 1 3263a9083016SGiridhar Malavali */ 3264a9083016SGiridhar Malavali static int 3265a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3266a9083016SGiridhar Malavali { 3267e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 3268e6a4202aSShyam Sundar int i, timeout; 3269a9083016SGiridhar Malavali uint32_t old_count, count; 3270a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3271e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 3272a9083016SGiridhar Malavali 3273e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 3274a9083016SGiridhar Malavali 3275a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3276a9083016SGiridhar Malavali 3277a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 3278a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 3279a9083016SGiridhar Malavali if (timeout) { 3280a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3281a9083016SGiridhar Malavali QLA82XX_DEV_FAILED); 3282a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3283a9083016SGiridhar Malavali } 3284a9083016SGiridhar Malavali 3285a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3286a9083016SGiridhar Malavali if (count != old_count) 3287e6a4202aSShyam Sundar peg_stuck = 0; 3288e6a4202aSShyam Sundar } 3289e6a4202aSShyam Sundar 3290e6a4202aSShyam Sundar if (need_reset) { 3291e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 3292e6a4202aSShyam Sundar if (peg_stuck) 3293e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3294e6a4202aSShyam Sundar goto dev_initialize; 3295e6a4202aSShyam Sundar } else { 3296e6a4202aSShyam Sundar /* Start of day for this ha context. */ 3297e6a4202aSShyam Sundar if (peg_stuck) { 3298e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 3299e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3300e6a4202aSShyam Sundar goto dev_initialize; 3301e6a4202aSShyam Sundar } else 3302e6a4202aSShyam Sundar /* Firmware already running. */ 3303a9083016SGiridhar Malavali goto dev_ready; 3304a9083016SGiridhar Malavali } 3305a9083016SGiridhar Malavali 3306e6a4202aSShyam Sundar return rval; 3307e6a4202aSShyam Sundar 3308a9083016SGiridhar Malavali dev_initialize: 3309a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 3310a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 3311a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3312a9083016SGiridhar Malavali 3313a9083016SGiridhar Malavali /* Driver that sets device state to initializating sets IDC version */ 3314a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3315a9083016SGiridhar Malavali 3316a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3317a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 3318a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3319a9083016SGiridhar Malavali 3320a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 3321a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3322a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 3323a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3324a9083016SGiridhar Malavali return rval; 3325a9083016SGiridhar Malavali } 3326a9083016SGiridhar Malavali 3327a9083016SGiridhar Malavali dev_ready: 3328a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: READY\n"); 3329a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3330a9083016SGiridhar Malavali 3331a9083016SGiridhar Malavali return QLA_SUCCESS; 3332a9083016SGiridhar Malavali } 3333a9083016SGiridhar Malavali 3334579d12b5SSaurav Kashyap /* 3335579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 3336579d12b5SSaurav Kashyap * Code to start quiescence sequence 3337579d12b5SSaurav Kashyap * 3338579d12b5SSaurav Kashyap * Note: 3339579d12b5SSaurav Kashyap * IDC lock must be held upon entry 3340579d12b5SSaurav Kashyap * 3341579d12b5SSaurav Kashyap * Return: void 3342579d12b5SSaurav Kashyap */ 3343579d12b5SSaurav Kashyap 3344579d12b5SSaurav Kashyap static void 3345579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 3346579d12b5SSaurav Kashyap { 3347579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3348579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 3349579d12b5SSaurav Kashyap unsigned long reset_timeout; 3350579d12b5SSaurav Kashyap 3351579d12b5SSaurav Kashyap if (vha->flags.online) { 3352579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 3353579d12b5SSaurav Kashyap qla82xx_quiescent_state_cleanup(vha); 3354579d12b5SSaurav Kashyap } 3355579d12b5SSaurav Kashyap 3356579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 3357579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 3358579d12b5SSaurav Kashyap 3359579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 3360579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 3361579d12b5SSaurav Kashyap 3362579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3363579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3364579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 3365579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3366579d12b5SSaurav Kashyap 3367579d12b5SSaurav Kashyap while (drv_state != drv_active) { 3368579d12b5SSaurav Kashyap 3369579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 3370579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 3371579d12b5SSaurav Kashyap * changing the state to DEV_READY 3372579d12b5SSaurav Kashyap */ 3373579d12b5SSaurav Kashyap qla_printk(KERN_INFO, ha, 3374579d12b5SSaurav Kashyap "%s: QUIESCENT TIMEOUT\n", QLA2XXX_DRIVER_NAME); 3375579d12b5SSaurav Kashyap qla_printk(KERN_INFO, ha, 3376579d12b5SSaurav Kashyap "DRV_ACTIVE:%d DRV_STATE:%d\n", drv_active, 3377579d12b5SSaurav Kashyap drv_state); 3378579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3379579d12b5SSaurav Kashyap QLA82XX_DEV_READY); 3380579d12b5SSaurav Kashyap qla_printk(KERN_INFO, ha, 3381579d12b5SSaurav Kashyap "HW State: DEV_READY\n"); 3382579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3383579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 3384579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3385579d12b5SSaurav Kashyap 3386579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 3387579d12b5SSaurav Kashyap return; 3388579d12b5SSaurav Kashyap } 3389579d12b5SSaurav Kashyap 3390579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3391579d12b5SSaurav Kashyap msleep(1000); 3392579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3393579d12b5SSaurav Kashyap 3394579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3395579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3396579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3397579d12b5SSaurav Kashyap } 3398579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3399579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 3400579d12b5SSaurav Kashyap if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 3401579d12b5SSaurav Kashyap qla_printk(KERN_INFO, ha, "HW State: DEV_QUIESCENT\n"); 3402579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 3403579d12b5SSaurav Kashyap } 3404579d12b5SSaurav Kashyap } 3405579d12b5SSaurav Kashyap 3406579d12b5SSaurav Kashyap /* 3407579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 3408579d12b5SSaurav Kashyap * Wait for device state to change from given current state 3409579d12b5SSaurav Kashyap * 3410579d12b5SSaurav Kashyap * Note: 3411579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 3412579d12b5SSaurav Kashyap * 3413579d12b5SSaurav Kashyap * Return: 3414579d12b5SSaurav Kashyap * Changed device state. 3415579d12b5SSaurav Kashyap */ 3416579d12b5SSaurav Kashyap uint32_t 3417579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3418579d12b5SSaurav Kashyap { 3419579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3420579d12b5SSaurav Kashyap uint32_t dev_state; 3421579d12b5SSaurav Kashyap 3422579d12b5SSaurav Kashyap do { 3423579d12b5SSaurav Kashyap msleep(1000); 3424579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3425579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3426579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3427579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3428579d12b5SSaurav Kashyap 3429579d12b5SSaurav Kashyap return dev_state; 3430579d12b5SSaurav Kashyap } 3431579d12b5SSaurav Kashyap 3432a9083016SGiridhar Malavali static void 3433a9083016SGiridhar Malavali qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3434a9083016SGiridhar Malavali { 3435a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3436a9083016SGiridhar Malavali 3437a9083016SGiridhar Malavali /* Disable the board */ 3438a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "Disabling the board\n"); 3439a9083016SGiridhar Malavali 3440b963752fSGiridhar Malavali qla82xx_idc_lock(ha); 3441b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3442b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 3443b963752fSGiridhar Malavali 3444a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3445a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3446a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3447a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3448a9083016SGiridhar Malavali vha->flags.online = 0; 3449a9083016SGiridhar Malavali vha->flags.init_done = 0; 3450a9083016SGiridhar Malavali } 3451a9083016SGiridhar Malavali 3452a9083016SGiridhar Malavali /* 3453a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3454a9083016SGiridhar Malavali * Code to start reset sequence 3455a9083016SGiridhar Malavali * 3456a9083016SGiridhar Malavali * Note: 3457a9083016SGiridhar Malavali * IDC lock must be held upon entry 3458a9083016SGiridhar Malavali * 3459a9083016SGiridhar Malavali * Return: 3460a9083016SGiridhar Malavali * Success : 0 3461a9083016SGiridhar Malavali * Failed : 1 3462a9083016SGiridhar Malavali */ 3463a9083016SGiridhar Malavali static void 3464a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3465a9083016SGiridhar Malavali { 3466a9083016SGiridhar Malavali uint32_t dev_state, drv_state, drv_active; 3467a9083016SGiridhar Malavali unsigned long reset_timeout; 3468a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3469a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3470a9083016SGiridhar Malavali 3471a9083016SGiridhar Malavali if (vha->flags.online) { 3472a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3473a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3474a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3475a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3476a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3477a9083016SGiridhar Malavali } 3478a9083016SGiridhar Malavali 3479a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 3480a9083016SGiridhar Malavali 3481a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 3482a9083016SGiridhar Malavali reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3483a9083016SGiridhar Malavali 3484a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3485a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3486a9083016SGiridhar Malavali 3487a9083016SGiridhar Malavali while (drv_state != drv_active) { 3488a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 3489a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, 3490a9083016SGiridhar Malavali "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME); 3491a9083016SGiridhar Malavali break; 3492a9083016SGiridhar Malavali } 3493a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3494a9083016SGiridhar Malavali msleep(1000); 3495a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3496a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3497a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3498a9083016SGiridhar Malavali } 3499a9083016SGiridhar Malavali 3500a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3501f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 3502f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3503f1af6208SGiridhar Malavali 3504a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 3505a9083016SGiridhar Malavali if (dev_state != QLA82XX_DEV_INITIALIZING) { 3506a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3507a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3508a9083016SGiridhar Malavali } 3509a9083016SGiridhar Malavali } 3510a9083016SGiridhar Malavali 35117190575fSGiridhar Malavali int 3512a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3513a9083016SGiridhar Malavali { 35147190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 35157190575fSGiridhar Malavali int status = 0; 3516a9083016SGiridhar Malavali 35177190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 35187190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3519a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 3520a5b36321SLalit Chandivade if (fw_heartbeat_counter == 0xffffffff) 35217190575fSGiridhar Malavali return status; 3522a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3523a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3524a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3525a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3526a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 35277190575fSGiridhar Malavali status = 1; 3528a9083016SGiridhar Malavali } 3529efa786ccSLalit Chandivade } else 3530efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3531a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 35327190575fSGiridhar Malavali return status; 3533a9083016SGiridhar Malavali } 3534a9083016SGiridhar Malavali 3535a9083016SGiridhar Malavali /* 3536a9083016SGiridhar Malavali * qla82xx_device_state_handler 3537a9083016SGiridhar Malavali * Main state handler 3538a9083016SGiridhar Malavali * 3539a9083016SGiridhar Malavali * Note: 3540a9083016SGiridhar Malavali * IDC lock must be held upon entry 3541a9083016SGiridhar Malavali * 3542a9083016SGiridhar Malavali * Return: 3543a9083016SGiridhar Malavali * Success : 0 3544a9083016SGiridhar Malavali * Failed : 1 3545a9083016SGiridhar Malavali */ 3546a9083016SGiridhar Malavali int 3547a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3548a9083016SGiridhar Malavali { 3549a9083016SGiridhar Malavali uint32_t dev_state; 355092dbf273SGiridhar Malavali uint32_t old_dev_state; 3551a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3552a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3553a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 355492dbf273SGiridhar Malavali int loopcount = 0; 3555a9083016SGiridhar Malavali 3556a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3557a9083016SGiridhar Malavali if (!vha->flags.init_done) 3558a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 3559a9083016SGiridhar Malavali 3560a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 356192dbf273SGiridhar Malavali old_dev_state = dev_state; 3562f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 3563f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3564a9083016SGiridhar Malavali 3565a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 3566a9083016SGiridhar Malavali dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3567a9083016SGiridhar Malavali 3568a9083016SGiridhar Malavali while (1) { 3569a9083016SGiridhar Malavali 3570a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 3571a9083016SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3572a9083016SGiridhar Malavali "%s: device init failed!\n", 3573a9083016SGiridhar Malavali QLA2XXX_DRIVER_NAME)); 3574a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3575a9083016SGiridhar Malavali break; 3576a9083016SGiridhar Malavali } 3577a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 357892dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 357992dbf273SGiridhar Malavali loopcount = 0; 358092dbf273SGiridhar Malavali old_dev_state = dev_state; 358192dbf273SGiridhar Malavali } 358292dbf273SGiridhar Malavali if (loopcount < 5) { 3583f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, 3584f1af6208SGiridhar Malavali "2:Device state is 0x%x = %s\n", dev_state, 3585f1af6208SGiridhar Malavali dev_state < MAX_STATES ? 3586f1af6208SGiridhar Malavali qdev_state[dev_state] : "Unknown"); 358792dbf273SGiridhar Malavali } 3588f1af6208SGiridhar Malavali 3589a9083016SGiridhar Malavali switch (dev_state) { 3590a9083016SGiridhar Malavali case QLA82XX_DEV_READY: 3591a9083016SGiridhar Malavali goto exit; 3592a9083016SGiridhar Malavali case QLA82XX_DEV_COLD: 3593a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 3594a9083016SGiridhar Malavali goto exit; 3595a9083016SGiridhar Malavali case QLA82XX_DEV_INITIALIZING: 3596a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3597a9083016SGiridhar Malavali msleep(1000); 3598a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3599a9083016SGiridhar Malavali break; 3600a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_RESET: 3601ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3602a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 36030060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 36040060ddf8SGiridhar Malavali (ha->nx_dev_init_timeout * HZ); 3605a9083016SGiridhar Malavali break; 3606a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_QUIESCENT: 3607579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3608579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3609579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3610579d12b5SSaurav Kashyap * HZ); 3611579d12b5SSaurav Kashyap break; 3612a9083016SGiridhar Malavali case QLA82XX_DEV_QUIESCENT: 3613579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3614579d12b5SSaurav Kashyap * to get changed 3615579d12b5SSaurav Kashyap */ 3616579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 3617579d12b5SSaurav Kashyap goto exit; 3618579d12b5SSaurav Kashyap 3619a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3620a9083016SGiridhar Malavali msleep(1000); 3621a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3622579d12b5SSaurav Kashyap 3623579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3624579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3625579d12b5SSaurav Kashyap * HZ); 3626a9083016SGiridhar Malavali break; 3627a9083016SGiridhar Malavali case QLA82XX_DEV_FAILED: 3628a9083016SGiridhar Malavali qla82xx_dev_failed_handler(vha); 3629a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3630a9083016SGiridhar Malavali goto exit; 3631a9083016SGiridhar Malavali default: 3632a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3633a9083016SGiridhar Malavali msleep(1000); 3634a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3635a9083016SGiridhar Malavali } 363692dbf273SGiridhar Malavali loopcount++; 3637a9083016SGiridhar Malavali } 3638a9083016SGiridhar Malavali exit: 3639a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3640a9083016SGiridhar Malavali return rval; 3641a9083016SGiridhar Malavali } 3642a9083016SGiridhar Malavali 3643a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3644a9083016SGiridhar Malavali { 36457190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3646a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3647a9083016SGiridhar Malavali 3648a9083016SGiridhar Malavali /* don't poll if reset is going on */ 36497190575fSGiridhar Malavali if (!ha->flags.isp82xx_reset_hdlr_active) { 36507190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 36517190575fSGiridhar Malavali if (dev_state == QLA82XX_DEV_NEED_RESET && 36527190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3653a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3654a9083016SGiridhar Malavali "%s(): Adapter reset needed!\n", __func__); 3655a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3656a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3657579d12b5SSaurav Kashyap } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3658579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3659579d12b5SSaurav Kashyap DEBUG(qla_printk(KERN_INFO, ha, 3660579d12b5SSaurav Kashyap "scsi(%ld) %s - detected quiescence needed\n", 3661579d12b5SSaurav Kashyap vha->host_no, __func__)); 3662579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3663579d12b5SSaurav Kashyap qla2xxx_wake_dpc(vha); 3664a9083016SGiridhar Malavali } else { 36657190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 36667190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 36677190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 36680e8edb03SGiridhar Malavali qla_printk(KERN_INFO, ha, 36690e8edb03SGiridhar Malavali "scsi(%ld): %s, Dumping hw/fw registers:\n " 36700e8edb03SGiridhar Malavali " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n " 36710e8edb03SGiridhar Malavali " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n " 36720e8edb03SGiridhar Malavali " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n " 36730e8edb03SGiridhar Malavali " PEG_NET_4_PC: 0x%x\n", 36740e8edb03SGiridhar Malavali vha->host_no, __func__, halt_status, 36750e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 36760e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 36770e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 36780e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 36790e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 36800e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 36810e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 36820e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 36830e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 36840e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 36850e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 36867190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 36877190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 36887190575fSGiridhar Malavali &vha->dpc_flags); 36897190575fSGiridhar Malavali } else { 36907190575fSGiridhar Malavali qla_printk(KERN_INFO, ha, 36917190575fSGiridhar Malavali "scsi(%ld): %s - detect abort needed\n", 36927190575fSGiridhar Malavali vha->host_no, __func__); 36937190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 36947190575fSGiridhar Malavali &vha->dpc_flags); 36957190575fSGiridhar Malavali } 36967190575fSGiridhar Malavali qla2xxx_wake_dpc(vha); 36977190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 36987190575fSGiridhar Malavali if (ha->flags.mbox_busy) { 36997190575fSGiridhar Malavali ha->flags.mbox_int = 1; 37007190575fSGiridhar Malavali DEBUG2(qla_printk(KERN_ERR, ha, 37017190575fSGiridhar Malavali "Due to fw hung, doing premature " 37027190575fSGiridhar Malavali "completion of mbx command\n")); 37037190575fSGiridhar Malavali if (test_bit(MBX_INTR_WAIT, 37047190575fSGiridhar Malavali &ha->mbx_cmd_flags)) 37057190575fSGiridhar Malavali complete(&ha->mbx_intr_comp); 37067190575fSGiridhar Malavali } 37077190575fSGiridhar Malavali } 3708a9083016SGiridhar Malavali } 3709a9083016SGiridhar Malavali } 3710a9083016SGiridhar Malavali } 3711a9083016SGiridhar Malavali 3712a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3713a9083016SGiridhar Malavali { 3714a9083016SGiridhar Malavali int rval; 3715a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3716a9083016SGiridhar Malavali return rval; 3717a9083016SGiridhar Malavali } 3718a9083016SGiridhar Malavali 3719a9083016SGiridhar Malavali /* 3720a9083016SGiridhar Malavali * qla82xx_abort_isp 3721a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3722a9083016SGiridhar Malavali * 3723a9083016SGiridhar Malavali * Input: 3724a9083016SGiridhar Malavali * ha = adapter block pointer. 3725a9083016SGiridhar Malavali * 3726a9083016SGiridhar Malavali * Returns: 3727a9083016SGiridhar Malavali * 0 = success 3728a9083016SGiridhar Malavali */ 3729a9083016SGiridhar Malavali int 3730a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3731a9083016SGiridhar Malavali { 3732a9083016SGiridhar Malavali int rval; 3733a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3734a9083016SGiridhar Malavali uint32_t dev_state; 3735a9083016SGiridhar Malavali 3736a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 3737a9083016SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3738a9083016SGiridhar Malavali "%s(%ld): Device in failed state, " 3739a9083016SGiridhar Malavali "Exiting.\n", __func__, vha->host_no); 3740a9083016SGiridhar Malavali return QLA_SUCCESS; 3741a9083016SGiridhar Malavali } 37427190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 1; 3743a9083016SGiridhar Malavali 3744a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3745a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3746f1af6208SGiridhar Malavali if (dev_state == QLA82XX_DEV_READY) { 3747a9083016SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3748a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3749a9083016SGiridhar Malavali QLA82XX_DEV_NEED_RESET); 3750a9083016SGiridhar Malavali } else 3751f1af6208SGiridhar Malavali qla_printk(KERN_INFO, ha, "HW State: %s\n", 3752f1af6208SGiridhar Malavali dev_state < MAX_STATES ? 3753f1af6208SGiridhar Malavali qdev_state[dev_state] : "Unknown"); 3754a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3755a9083016SGiridhar Malavali 3756a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3757a9083016SGiridhar Malavali 3758a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3759a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3760a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3761a9083016SGiridhar Malavali 3762cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 37637190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 37647190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 0; 3765a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3766cdbb0a4fSSantosh Vernekar } 3767f1af6208SGiridhar Malavali 3768f1af6208SGiridhar Malavali if (rval) { 3769f1af6208SGiridhar Malavali vha->flags.online = 1; 3770f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3771f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 3772f1af6208SGiridhar Malavali qla_printk(KERN_WARNING, ha, 3773f1af6208SGiridhar Malavali "ISP error recovery failed - " 3774f1af6208SGiridhar Malavali "board disabled\n"); 3775f1af6208SGiridhar Malavali /* 3776f1af6208SGiridhar Malavali * The next call disables the board 3777f1af6208SGiridhar Malavali * completely. 3778f1af6208SGiridhar Malavali */ 3779f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3780f1af6208SGiridhar Malavali vha->flags.online = 0; 3781f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3782f1af6208SGiridhar Malavali &vha->dpc_flags); 3783f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3784f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3785f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 3786f1af6208SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3787f1af6208SGiridhar Malavali "qla%ld: ISP abort - retry remaining %d\n", 3788f1af6208SGiridhar Malavali vha->host_no, ha->isp_abort_cnt)); 3789f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3790f1af6208SGiridhar Malavali } 3791f1af6208SGiridhar Malavali } else { 3792f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3793f1af6208SGiridhar Malavali DEBUG(qla_printk(KERN_INFO, ha, 3794f1af6208SGiridhar Malavali "(%ld): ISP error recovery - retrying (%d) " 3795f1af6208SGiridhar Malavali "more times\n", vha->host_no, ha->isp_abort_cnt)); 3796f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3797f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3798f1af6208SGiridhar Malavali } 3799f1af6208SGiridhar Malavali } 3800a9083016SGiridhar Malavali return rval; 3801a9083016SGiridhar Malavali } 3802a9083016SGiridhar Malavali 3803a9083016SGiridhar Malavali /* 3804a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3805a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3806a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3807a9083016SGiridhar Malavali * chip reset. 3808a9083016SGiridhar Malavali * 3809a9083016SGiridhar Malavali * Input: 3810a9083016SGiridhar Malavali * ha = adapter block pointer. 3811a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3812a9083016SGiridhar Malavali * 3813a9083016SGiridhar Malavali * Returns: 3814a9083016SGiridhar Malavali * 0 = success 3815a9083016SGiridhar Malavali */ 3816a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3817a9083016SGiridhar Malavali { 3818a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3819a9083016SGiridhar Malavali 3820a9083016SGiridhar Malavali if (vha->flags.online) { 3821a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3822a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3823a9083016SGiridhar Malavali } 3824a9083016SGiridhar Malavali 3825a9083016SGiridhar Malavali /* Stop currently executing firmware. 3826a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3827a9083016SGiridhar Malavali */ 3828a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3829a9083016SGiridhar Malavali 3830a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3831a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3832a9083016SGiridhar Malavali 3833a9083016SGiridhar Malavali return rval; 3834a9083016SGiridhar Malavali } 3835a9083016SGiridhar Malavali 3836a9083016SGiridhar Malavali /* 3837a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3838a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3839a9083016SGiridhar Malavali * 3840a9083016SGiridhar Malavali * Note: 3841a9083016SGiridhar Malavali * Does context switching here. 3842a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3843a9083016SGiridhar Malavali * 3844a9083016SGiridhar Malavali * Return: 3845a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3846a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3847a9083016SGiridhar Malavali */ 3848a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3849a9083016SGiridhar Malavali { 3850a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3851a9083016SGiridhar Malavali unsigned long wait_reset; 3852a9083016SGiridhar Malavali 3853a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3854a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3855a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3856a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3857a9083016SGiridhar Malavali 3858a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3859a9083016SGiridhar Malavali schedule_timeout(HZ); 3860a9083016SGiridhar Malavali 3861a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3862a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3863a9083016SGiridhar Malavali status = QLA_SUCCESS; 3864a9083016SGiridhar Malavali break; 3865a9083016SGiridhar Malavali } 3866a9083016SGiridhar Malavali } 3867a9083016SGiridhar Malavali DEBUG2(printk(KERN_INFO 3868a9083016SGiridhar Malavali "%s status=%d\n", __func__, status)); 3869a9083016SGiridhar Malavali 3870a9083016SGiridhar Malavali return status; 3871a9083016SGiridhar Malavali } 38727190575fSGiridhar Malavali 38737190575fSGiridhar Malavali void 38747190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 38757190575fSGiridhar Malavali { 38767190575fSGiridhar Malavali int i; 38777190575fSGiridhar Malavali unsigned long flags; 38787190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 38797190575fSGiridhar Malavali 38807190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 38817190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 38827190575fSGiridhar Malavali * detection only 38837190575fSGiridhar Malavali */ 38847190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 38857190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 38867190575fSGiridhar Malavali msleep(1000); 38877190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 38887190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 38897190575fSGiridhar Malavali if (ha->flags.mbox_busy) { 38907190575fSGiridhar Malavali ha->flags.mbox_int = 1; 38917190575fSGiridhar Malavali complete(&ha->mbx_intr_comp); 38927190575fSGiridhar Malavali } 38937190575fSGiridhar Malavali break; 38947190575fSGiridhar Malavali } 38957190575fSGiridhar Malavali } 38967190575fSGiridhar Malavali } 38977190575fSGiridhar Malavali 38987190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 38997190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 39007190575fSGiridhar Malavali int cnt, que; 39017190575fSGiridhar Malavali srb_t *sp; 39027190575fSGiridhar Malavali struct req_que *req; 39037190575fSGiridhar Malavali 39047190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 39057190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 39067190575fSGiridhar Malavali req = ha->req_q_map[que]; 39077190575fSGiridhar Malavali if (!req) 39087190575fSGiridhar Malavali continue; 39097190575fSGiridhar Malavali for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 39107190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 39117190575fSGiridhar Malavali if (sp) { 39127190575fSGiridhar Malavali if (!sp->ctx || 39137190575fSGiridhar Malavali (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 39147190575fSGiridhar Malavali spin_unlock_irqrestore( 39157190575fSGiridhar Malavali &ha->hardware_lock, flags); 39167190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 39177190575fSGiridhar Malavali qla_printk(KERN_INFO, ha, 39187190575fSGiridhar Malavali "scsi(%ld): mbx abort command failed in %s\n", 39197190575fSGiridhar Malavali vha->host_no, __func__); 39207190575fSGiridhar Malavali } else { 39217190575fSGiridhar Malavali qla_printk(KERN_INFO, ha, 39227190575fSGiridhar Malavali "scsi(%ld): mbx abort command success in %s\n", 39237190575fSGiridhar Malavali vha->host_no, __func__); 39247190575fSGiridhar Malavali } 39257190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 39267190575fSGiridhar Malavali } 39277190575fSGiridhar Malavali } 39287190575fSGiridhar Malavali } 39297190575fSGiridhar Malavali } 39307190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 39317190575fSGiridhar Malavali 39327190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 39337190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 39347190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 39357190575fSGiridhar Malavali DEBUG2(qla_printk(KERN_INFO, ha, 39367190575fSGiridhar Malavali "Done wait for pending commands\n")); 39377190575fSGiridhar Malavali } 39387190575fSGiridhar Malavali } 39397190575fSGiridhar Malavali } 3940