1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 307e264b7SAndrew Vasquez * Copyright (c) 2003-2011 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39a9083016SGiridhar Malavali int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 45a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 46a9083016SGiridhar Malavali { 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 97a9083016SGiridhar Malavali /* 98a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 99a9083016SGiridhar Malavali */ 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 101a9083016SGiridhar Malavali 102a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 103a9083016SGiridhar Malavali } 104a9083016SGiridhar Malavali 105a9083016SGiridhar Malavali struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 107a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 108a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 109a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 110a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 111a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 112a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 113a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 114a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 123a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 125a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213a9083016SGiridhar Malavali {{{0} } }, 214a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 215a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 216a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 217a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 218a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 219a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 220a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 221a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 230a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{0} } }, 235a9083016SGiridhar Malavali {{{0} } }, 236a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248a9083016SGiridhar Malavali {{{0} } }, 249a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255a9083016SGiridhar Malavali {{{0} } }, 256a9083016SGiridhar Malavali {{{0} } }, 257a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260a9083016SGiridhar Malavali }; 261a9083016SGiridhar Malavali 262a9083016SGiridhar Malavali /* 263a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 264a9083016SGiridhar Malavali */ 265a9083016SGiridhar Malavali unsigned qla82xx_crb_hub_agt[64] = { 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270a9083016SGiridhar Malavali 0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293a9083016SGiridhar Malavali 0, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318a9083016SGiridhar Malavali 0, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali }; 331a9083016SGiridhar Malavali 332f1af6208SGiridhar Malavali /* Device states */ 33308de2844SGiridhar Malavali char *q_dev_state[] = { 334f1af6208SGiridhar Malavali "Unknown", 335f1af6208SGiridhar Malavali "Cold", 336f1af6208SGiridhar Malavali "Initializing", 337f1af6208SGiridhar Malavali "Ready", 338f1af6208SGiridhar Malavali "Need Reset", 339f1af6208SGiridhar Malavali "Need Quiescent", 340f1af6208SGiridhar Malavali "Failed", 341f1af6208SGiridhar Malavali "Quiescent", 342f1af6208SGiridhar Malavali }; 343f1af6208SGiridhar Malavali 34408de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 34508de2844SGiridhar Malavali { 34608de2844SGiridhar Malavali return q_dev_state[dev_state]; 34708de2844SGiridhar Malavali } 34808de2844SGiridhar Malavali 349a9083016SGiridhar Malavali /* 350a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 351a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 352a9083016SGiridhar Malavali * side effect: lock crb window 353a9083016SGiridhar Malavali */ 354a9083016SGiridhar Malavali static void 355a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356a9083016SGiridhar Malavali { 357a9083016SGiridhar Malavali u32 win_read; 3587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359a9083016SGiridhar Malavali 360a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 361a9083016SGiridhar Malavali writel(ha->crb_win, 362a9083016SGiridhar Malavali (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363a9083016SGiridhar Malavali 364a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 365a9083016SGiridhar Malavali * to use it. 366a9083016SGiridhar Malavali */ 367a9083016SGiridhar Malavali win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3697c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3707c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3717c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 372d8424f68SJoe Perches __func__, ha->crb_win, win_read, *off); 373a9083016SGiridhar Malavali } 374a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375a9083016SGiridhar Malavali } 376a9083016SGiridhar Malavali 377a9083016SGiridhar Malavali static inline unsigned long 378a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379a9083016SGiridhar Malavali { 3807c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 382a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 384a9083016SGiridhar Malavali * regs are in both windows. 385a9083016SGiridhar Malavali */ 386a9083016SGiridhar Malavali return off; 387a9083016SGiridhar Malavali } 388a9083016SGiridhar Malavali 389a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390a9083016SGiridhar Malavali /* We are in first CRB window */ 391a9083016SGiridhar Malavali if (ha->curr_window != 0) 392a9083016SGiridhar Malavali WARN_ON(1); 393a9083016SGiridhar Malavali return off; 394a9083016SGiridhar Malavali } 395a9083016SGiridhar Malavali 396a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397a9083016SGiridhar Malavali /* We are in second CRB window */ 398a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399a9083016SGiridhar Malavali 400a9083016SGiridhar Malavali if (ha->curr_window != 1) 401a9083016SGiridhar Malavali return off; 402a9083016SGiridhar Malavali 403a9083016SGiridhar Malavali /* We are in the QM or direct access 404a9083016SGiridhar Malavali * register region - do nothing 405a9083016SGiridhar Malavali */ 406a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 408a9083016SGiridhar Malavali return off; 409a9083016SGiridhar Malavali } 410a9083016SGiridhar Malavali /* strange address given */ 4117c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 412d8424f68SJoe Perches "%s: Warning: unm_nic_pci_set_crbwindow " 4137c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4147c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 415a9083016SGiridhar Malavali return off; 416a9083016SGiridhar Malavali } 417a9083016SGiridhar Malavali 41877e334d2SGiridhar Malavali static int 41977e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 42077e334d2SGiridhar Malavali { 42177e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42277e334d2SGiridhar Malavali 42377e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 42477e334d2SGiridhar Malavali return -1; 42577e334d2SGiridhar Malavali 42677e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42777e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42877e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 42977e334d2SGiridhar Malavali return 0; 43077e334d2SGiridhar Malavali } 43177e334d2SGiridhar Malavali 43277e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 43377e334d2SGiridhar Malavali return -1; 43477e334d2SGiridhar Malavali 43577e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 43677e334d2SGiridhar Malavali 43777e334d2SGiridhar Malavali /* Try direct map */ 43877e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 43977e334d2SGiridhar Malavali 44077e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 44177e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 44277e334d2SGiridhar Malavali return 0; 44377e334d2SGiridhar Malavali } 44477e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 44577e334d2SGiridhar Malavali return 1; 44677e334d2SGiridhar Malavali } 44777e334d2SGiridhar Malavali 44877e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 44977e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45077e334d2SGiridhar Malavali { 45177e334d2SGiridhar Malavali int done = 0, timeout = 0; 45277e334d2SGiridhar Malavali 45377e334d2SGiridhar Malavali while (!done) { 45477e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 45577e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 45677e334d2SGiridhar Malavali if (done == 1) 45777e334d2SGiridhar Malavali break; 45877e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 45977e334d2SGiridhar Malavali return -1; 46077e334d2SGiridhar Malavali timeout++; 46177e334d2SGiridhar Malavali } 46277e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 46377e334d2SGiridhar Malavali return 0; 46477e334d2SGiridhar Malavali } 46577e334d2SGiridhar Malavali 466a9083016SGiridhar Malavali int 467a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468a9083016SGiridhar Malavali { 469a9083016SGiridhar Malavali unsigned long flags = 0; 470a9083016SGiridhar Malavali int rv; 471a9083016SGiridhar Malavali 472a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473a9083016SGiridhar Malavali 474a9083016SGiridhar Malavali BUG_ON(rv == -1); 475a9083016SGiridhar Malavali 476a9083016SGiridhar Malavali if (rv == 1) { 477a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 478a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 479a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 480a9083016SGiridhar Malavali } 481a9083016SGiridhar Malavali 482a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 483a9083016SGiridhar Malavali 484a9083016SGiridhar Malavali if (rv == 1) { 485a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 487a9083016SGiridhar Malavali } 488a9083016SGiridhar Malavali return 0; 489a9083016SGiridhar Malavali } 490a9083016SGiridhar Malavali 491a9083016SGiridhar Malavali int 492a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493a9083016SGiridhar Malavali { 494a9083016SGiridhar Malavali unsigned long flags = 0; 495a9083016SGiridhar Malavali int rv; 496a9083016SGiridhar Malavali u32 data; 497a9083016SGiridhar Malavali 498a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499a9083016SGiridhar Malavali 500a9083016SGiridhar Malavali BUG_ON(rv == -1); 501a9083016SGiridhar Malavali 502a9083016SGiridhar Malavali if (rv == 1) { 503a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 504a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 505a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 506a9083016SGiridhar Malavali } 507a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 508a9083016SGiridhar Malavali 509a9083016SGiridhar Malavali if (rv == 1) { 510a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 512a9083016SGiridhar Malavali } 513a9083016SGiridhar Malavali return data; 514a9083016SGiridhar Malavali } 515a9083016SGiridhar Malavali 516a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 517a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 518a9083016SGiridhar Malavali { 519a9083016SGiridhar Malavali int i; 520a9083016SGiridhar Malavali int done = 0, timeout = 0; 521a9083016SGiridhar Malavali 522a9083016SGiridhar Malavali while (!done) { 523a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 524a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525a9083016SGiridhar Malavali if (done == 1) 526a9083016SGiridhar Malavali break; 527a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 528a9083016SGiridhar Malavali return -1; 529a9083016SGiridhar Malavali 530a9083016SGiridhar Malavali timeout++; 531a9083016SGiridhar Malavali 532a9083016SGiridhar Malavali /* Yield CPU */ 533a9083016SGiridhar Malavali if (!in_interrupt()) 534a9083016SGiridhar Malavali schedule(); 535a9083016SGiridhar Malavali else { 536a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 537a9083016SGiridhar Malavali cpu_relax(); 538a9083016SGiridhar Malavali } 539a9083016SGiridhar Malavali } 540a9083016SGiridhar Malavali 541a9083016SGiridhar Malavali return 0; 542a9083016SGiridhar Malavali } 543a9083016SGiridhar Malavali 544a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 545a9083016SGiridhar Malavali { 546a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547a9083016SGiridhar Malavali } 548a9083016SGiridhar Malavali 549a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 550a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 552a9083016SGiridhar Malavali /* 553a9083016SGiridhar Malavali * check memory access boundary. 554a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 555a9083016SGiridhar Malavali */ 556a9083016SGiridhar Malavali static unsigned long 557a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558a9083016SGiridhar Malavali unsigned long long addr, int size) 559a9083016SGiridhar Malavali { 560a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 562a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 564a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565a9083016SGiridhar Malavali return 0; 566a9083016SGiridhar Malavali else 567a9083016SGiridhar Malavali return 1; 568a9083016SGiridhar Malavali } 569a9083016SGiridhar Malavali 570a9083016SGiridhar Malavali int qla82xx_pci_set_window_warning_count; 571a9083016SGiridhar Malavali 57277e334d2SGiridhar Malavali static unsigned long 573a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574a9083016SGiridhar Malavali { 575a9083016SGiridhar Malavali int window; 576a9083016SGiridhar Malavali u32 win_read; 5777c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578a9083016SGiridhar Malavali 579a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 581a9083016SGiridhar Malavali /* DDR network side */ 582a9083016SGiridhar Malavali window = MN_WIN(addr); 583a9083016SGiridhar Malavali ha->ddr_mn_window = window; 584a9083016SGiridhar Malavali qla82xx_wr_32(ha, 585a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 587a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5897c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5907c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591a9083016SGiridhar Malavali __func__, window, win_read); 592a9083016SGiridhar Malavali } 593a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 596a9083016SGiridhar Malavali unsigned int temp1; 597a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5987c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 599a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 600a9083016SGiridhar Malavali addr = -1UL; 601a9083016SGiridhar Malavali } 602a9083016SGiridhar Malavali window = OCM_WIN(addr); 603a9083016SGiridhar Malavali ha->ddr_mn_window = window; 604a9083016SGiridhar Malavali qla82xx_wr_32(ha, 605a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 607a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 609a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 610a9083016SGiridhar Malavali if (win_read != temp1) { 6117c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6127c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613a9083016SGiridhar Malavali __func__, temp1, win_read); 614a9083016SGiridhar Malavali } 615a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616a9083016SGiridhar Malavali 617a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619a9083016SGiridhar Malavali /* QDR network side */ 620a9083016SGiridhar Malavali window = MS_WIN(addr); 621a9083016SGiridhar Malavali ha->qdr_sn_window = window; 622a9083016SGiridhar Malavali qla82xx_wr_32(ha, 623a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 625a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626a9083016SGiridhar Malavali if (win_read != window) { 6277c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6287c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629a9083016SGiridhar Malavali __func__, window, win_read); 630a9083016SGiridhar Malavali } 631a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632a9083016SGiridhar Malavali } else { 633a9083016SGiridhar Malavali /* 634a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 635a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 636a9083016SGiridhar Malavali */ 637a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 638a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6397c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6407c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6417c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 642a9083016SGiridhar Malavali } 643a9083016SGiridhar Malavali addr = -1UL; 644a9083016SGiridhar Malavali } 645a9083016SGiridhar Malavali return addr; 646a9083016SGiridhar Malavali } 647a9083016SGiridhar Malavali 648a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 649a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650a9083016SGiridhar Malavali unsigned long long addr) 651a9083016SGiridhar Malavali { 652a9083016SGiridhar Malavali int window; 653a9083016SGiridhar Malavali unsigned long long qdr_max; 654a9083016SGiridhar Malavali 655a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656a9083016SGiridhar Malavali 657a9083016SGiridhar Malavali /* DDR network side */ 658a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 660a9083016SGiridhar Malavali BUG(); 661a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 663a9083016SGiridhar Malavali return 1; 664a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 666a9083016SGiridhar Malavali return 1; 667a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668a9083016SGiridhar Malavali /* QDR network side */ 669a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 671a9083016SGiridhar Malavali return 1; 672a9083016SGiridhar Malavali } 673a9083016SGiridhar Malavali return 0; 674a9083016SGiridhar Malavali } 675a9083016SGiridhar Malavali 676a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677a9083016SGiridhar Malavali u64 off, void *data, int size) 678a9083016SGiridhar Malavali { 679a9083016SGiridhar Malavali unsigned long flags; 680f1af6208SGiridhar Malavali void *addr = NULL; 681a9083016SGiridhar Malavali int ret = 0; 682a9083016SGiridhar Malavali u64 start; 683a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 684a9083016SGiridhar Malavali unsigned long mem_base; 685a9083016SGiridhar Malavali unsigned long mem_page; 6867c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687a9083016SGiridhar Malavali 688a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 689a9083016SGiridhar Malavali 690a9083016SGiridhar Malavali /* 691a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 692a9083016SGiridhar Malavali * do not access. 693a9083016SGiridhar Malavali */ 694a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 695a9083016SGiridhar Malavali if ((start == -1UL) || 696a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6987c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 6997c3df132SSaurav Kashyap "%s out of bound pci memory " 7007c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7017c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 702a9083016SGiridhar Malavali return -1; 703a9083016SGiridhar Malavali } 704a9083016SGiridhar Malavali 705a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 706a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 707a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 708a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 709a9083016SGiridhar Malavali * consecutive pages. 710a9083016SGiridhar Malavali */ 711a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 712a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713a9083016SGiridhar Malavali else 714a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715a9083016SGiridhar Malavali if (mem_ptr == 0UL) { 716a9083016SGiridhar Malavali *(u8 *)data = 0; 717a9083016SGiridhar Malavali return -1; 718a9083016SGiridhar Malavali } 719a9083016SGiridhar Malavali addr = mem_ptr; 720a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 721a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 722a9083016SGiridhar Malavali 723a9083016SGiridhar Malavali switch (size) { 724a9083016SGiridhar Malavali case 1: 725a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 726a9083016SGiridhar Malavali break; 727a9083016SGiridhar Malavali case 2: 728a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 729a9083016SGiridhar Malavali break; 730a9083016SGiridhar Malavali case 4: 731a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 732a9083016SGiridhar Malavali break; 733a9083016SGiridhar Malavali case 8: 734a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 735a9083016SGiridhar Malavali break; 736a9083016SGiridhar Malavali default: 737a9083016SGiridhar Malavali ret = -1; 738a9083016SGiridhar Malavali break; 739a9083016SGiridhar Malavali } 740a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 741a9083016SGiridhar Malavali 742a9083016SGiridhar Malavali if (mem_ptr) 743a9083016SGiridhar Malavali iounmap(mem_ptr); 744a9083016SGiridhar Malavali return ret; 745a9083016SGiridhar Malavali } 746a9083016SGiridhar Malavali 747a9083016SGiridhar Malavali static int 748a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749a9083016SGiridhar Malavali u64 off, void *data, int size) 750a9083016SGiridhar Malavali { 751a9083016SGiridhar Malavali unsigned long flags; 752f1af6208SGiridhar Malavali void *addr = NULL; 753a9083016SGiridhar Malavali int ret = 0; 754a9083016SGiridhar Malavali u64 start; 755a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 756a9083016SGiridhar Malavali unsigned long mem_base; 757a9083016SGiridhar Malavali unsigned long mem_page; 7587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759a9083016SGiridhar Malavali 760a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 761a9083016SGiridhar Malavali 762a9083016SGiridhar Malavali /* 763a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 764a9083016SGiridhar Malavali * do not access. 765a9083016SGiridhar Malavali */ 766a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 767a9083016SGiridhar Malavali if ((start == -1UL) || 768a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7717c3df132SSaurav Kashyap "%s out of bount memory " 7727c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7737c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 774a9083016SGiridhar Malavali return -1; 775a9083016SGiridhar Malavali } 776a9083016SGiridhar Malavali 777a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 778a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 779a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 780a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 781a9083016SGiridhar Malavali * consecutive pages. 782a9083016SGiridhar Malavali */ 783a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 784a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785a9083016SGiridhar Malavali else 786a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787a9083016SGiridhar Malavali if (mem_ptr == 0UL) 788a9083016SGiridhar Malavali return -1; 789a9083016SGiridhar Malavali 790a9083016SGiridhar Malavali addr = mem_ptr; 791a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 792a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 793a9083016SGiridhar Malavali 794a9083016SGiridhar Malavali switch (size) { 795a9083016SGiridhar Malavali case 1: 796a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 797a9083016SGiridhar Malavali break; 798a9083016SGiridhar Malavali case 2: 799a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 800a9083016SGiridhar Malavali break; 801a9083016SGiridhar Malavali case 4: 802a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 803a9083016SGiridhar Malavali break; 804a9083016SGiridhar Malavali case 8: 805a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 806a9083016SGiridhar Malavali break; 807a9083016SGiridhar Malavali default: 808a9083016SGiridhar Malavali ret = -1; 809a9083016SGiridhar Malavali break; 810a9083016SGiridhar Malavali } 811a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 812a9083016SGiridhar Malavali if (mem_ptr) 813a9083016SGiridhar Malavali iounmap(mem_ptr); 814a9083016SGiridhar Malavali return ret; 815a9083016SGiridhar Malavali } 816a9083016SGiridhar Malavali 817a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81877e334d2SGiridhar Malavali static unsigned long 81977e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 820a9083016SGiridhar Malavali { 821a9083016SGiridhar Malavali int i; 822a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 823a9083016SGiridhar Malavali 824a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 825a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 826a9083016SGiridhar Malavali 827a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 828a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 829a9083016SGiridhar Malavali offset = addr & 0x000fffff; 830a9083016SGiridhar Malavali 831a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 832a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 833a9083016SGiridhar Malavali pci_base = i << 20; 834a9083016SGiridhar Malavali break; 835a9083016SGiridhar Malavali } 836a9083016SGiridhar Malavali } 837a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 838a9083016SGiridhar Malavali return pci_base; 839a9083016SGiridhar Malavali return pci_base + offset; 840a9083016SGiridhar Malavali } 841a9083016SGiridhar Malavali 842a9083016SGiridhar Malavali static long rom_max_timeout = 100; 843a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 844a9083016SGiridhar Malavali 84577e334d2SGiridhar Malavali static int 846a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 847a9083016SGiridhar Malavali { 848a9083016SGiridhar Malavali int done = 0, timeout = 0; 849a9083016SGiridhar Malavali 850a9083016SGiridhar Malavali while (!done) { 851a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 852a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853a9083016SGiridhar Malavali if (done == 1) 854a9083016SGiridhar Malavali break; 855a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 856a9083016SGiridhar Malavali return -1; 857a9083016SGiridhar Malavali timeout++; 858a9083016SGiridhar Malavali } 859a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860a9083016SGiridhar Malavali return 0; 861a9083016SGiridhar Malavali } 862a9083016SGiridhar Malavali 863d652e093SChad Dupuis static void 864d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 865d652e093SChad Dupuis { 866d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867d652e093SChad Dupuis } 868d652e093SChad Dupuis 86977e334d2SGiridhar Malavali static int 870a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871a9083016SGiridhar Malavali { 872a9083016SGiridhar Malavali long timeout = 0; 873a9083016SGiridhar Malavali long done = 0 ; 8747c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875a9083016SGiridhar Malavali 876a9083016SGiridhar Malavali while (done == 0) { 877a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878a9083016SGiridhar Malavali done &= 4; 879a9083016SGiridhar Malavali timeout++; 880a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8817c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8827c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8837c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 884a9083016SGiridhar Malavali return -1; 885a9083016SGiridhar Malavali } 886a9083016SGiridhar Malavali } 887a9083016SGiridhar Malavali return 0; 888a9083016SGiridhar Malavali } 889a9083016SGiridhar Malavali 89077e334d2SGiridhar Malavali static int 891a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 892a9083016SGiridhar Malavali { 893a9083016SGiridhar Malavali long timeout = 0; 894a9083016SGiridhar Malavali long done = 0 ; 8957c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896a9083016SGiridhar Malavali 897a9083016SGiridhar Malavali while (done == 0) { 898a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899a9083016SGiridhar Malavali done &= 2; 900a9083016SGiridhar Malavali timeout++; 901a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9027c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9037c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9047c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 905a9083016SGiridhar Malavali return -1; 906a9083016SGiridhar Malavali } 907a9083016SGiridhar Malavali } 908a9083016SGiridhar Malavali return 0; 909a9083016SGiridhar Malavali } 910a9083016SGiridhar Malavali 91177e334d2SGiridhar Malavali static int 912a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913a9083016SGiridhar Malavali { 9147c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 9157c3df132SSaurav Kashyap 916a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 917a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 918a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 919a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 920a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 921a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9227c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ba, 9237c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 924a9083016SGiridhar Malavali return -1; 925a9083016SGiridhar Malavali } 926a9083016SGiridhar Malavali /* Reset abyte_cnt and dummy_byte_cnt */ 927a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 928a9083016SGiridhar Malavali udelay(10); 929a9083016SGiridhar Malavali cond_resched(); 930a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 931a9083016SGiridhar Malavali *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 932a9083016SGiridhar Malavali return 0; 933a9083016SGiridhar Malavali } 934a9083016SGiridhar Malavali 93577e334d2SGiridhar Malavali static int 936a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937a9083016SGiridhar Malavali { 938a9083016SGiridhar Malavali int ret, loops = 0; 9397c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 940a9083016SGiridhar Malavali 941a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 942a9083016SGiridhar Malavali udelay(100); 943a9083016SGiridhar Malavali schedule(); 944a9083016SGiridhar Malavali loops++; 945a9083016SGiridhar Malavali } 946a9083016SGiridhar Malavali if (loops >= 50000) { 9477c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9487c3df132SSaurav Kashyap "Failed to aquire SEM2 lock.\n"); 949a9083016SGiridhar Malavali return -1; 950a9083016SGiridhar Malavali } 951a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 952d652e093SChad Dupuis qla82xx_rom_unlock(ha); 953a9083016SGiridhar Malavali return ret; 954a9083016SGiridhar Malavali } 955a9083016SGiridhar Malavali 95677e334d2SGiridhar Malavali static int 957a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 958a9083016SGiridhar Malavali { 9597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 960a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 961a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 962a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9647c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 965a9083016SGiridhar Malavali return -1; 966a9083016SGiridhar Malavali } 967a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 968a9083016SGiridhar Malavali return 0; 969a9083016SGiridhar Malavali } 970a9083016SGiridhar Malavali 97177e334d2SGiridhar Malavali static int 972a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 973a9083016SGiridhar Malavali { 974a9083016SGiridhar Malavali long timeout = 0; 975a9083016SGiridhar Malavali uint32_t done = 1 ; 976a9083016SGiridhar Malavali uint32_t val; 977a9083016SGiridhar Malavali int ret = 0; 9787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979a9083016SGiridhar Malavali 980a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 981a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 982a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 983a9083016SGiridhar Malavali done = val & 1; 984a9083016SGiridhar Malavali timeout++; 985a9083016SGiridhar Malavali udelay(10); 986a9083016SGiridhar Malavali cond_resched(); 987a9083016SGiridhar Malavali if (timeout >= 50000) { 9887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 9897c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 990a9083016SGiridhar Malavali return -1; 991a9083016SGiridhar Malavali } 992a9083016SGiridhar Malavali } 993a9083016SGiridhar Malavali return ret; 994a9083016SGiridhar Malavali } 995a9083016SGiridhar Malavali 99677e334d2SGiridhar Malavali static int 997a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 998a9083016SGiridhar Malavali { 999a9083016SGiridhar Malavali uint32_t val; 1000a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1001a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1002a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1003a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1004a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1005a9083016SGiridhar Malavali return -1; 1006a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1007a9083016SGiridhar Malavali return -1; 1008a9083016SGiridhar Malavali if ((val & 2) != 2) 1009a9083016SGiridhar Malavali return -1; 1010a9083016SGiridhar Malavali return 0; 1011a9083016SGiridhar Malavali } 1012a9083016SGiridhar Malavali 101377e334d2SGiridhar Malavali static int 1014a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1015a9083016SGiridhar Malavali { 10167c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1017a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1018a9083016SGiridhar Malavali return -1; 1019a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1020a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1021a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10227c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10237c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1024a9083016SGiridhar Malavali return -1; 1025a9083016SGiridhar Malavali } 1026a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1027a9083016SGiridhar Malavali } 1028a9083016SGiridhar Malavali 102977e334d2SGiridhar Malavali static int 1030a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1031a9083016SGiridhar Malavali { 10327c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1033a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1034a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10357c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10367c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1037a9083016SGiridhar Malavali return -1; 1038a9083016SGiridhar Malavali } 1039a9083016SGiridhar Malavali return 0; 1040a9083016SGiridhar Malavali } 1041a9083016SGiridhar Malavali 104277e334d2SGiridhar Malavali static int 1043a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1044a9083016SGiridhar Malavali { 1045a9083016SGiridhar Malavali int loops = 0; 10467c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10477c3df132SSaurav Kashyap 1048a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1049a9083016SGiridhar Malavali udelay(100); 1050a9083016SGiridhar Malavali cond_resched(); 1051a9083016SGiridhar Malavali loops++; 1052a9083016SGiridhar Malavali } 1053a9083016SGiridhar Malavali if (loops >= 50000) { 10547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10557c3df132SSaurav Kashyap "ROM lock failed.\n"); 1056a9083016SGiridhar Malavali return -1; 1057a9083016SGiridhar Malavali } 1058cd6dbb03SJesper Juhl return 0; 1059a9083016SGiridhar Malavali } 1060a9083016SGiridhar Malavali 106177e334d2SGiridhar Malavali static int 1062a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063a9083016SGiridhar Malavali uint32_t data) 1064a9083016SGiridhar Malavali { 1065a9083016SGiridhar Malavali int ret = 0; 10667c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067a9083016SGiridhar Malavali 1068a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1069a9083016SGiridhar Malavali if (ret < 0) { 10707c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10717c3df132SSaurav Kashyap "ROM lock failed.\n"); 1072a9083016SGiridhar Malavali return ret; 1073a9083016SGiridhar Malavali } 1074a9083016SGiridhar Malavali 1075a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1076a9083016SGiridhar Malavali goto done_write; 1077a9083016SGiridhar Malavali 1078a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1083a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10847c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 10857c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1086a9083016SGiridhar Malavali ret = -1; 1087a9083016SGiridhar Malavali goto done_write; 1088a9083016SGiridhar Malavali } 1089a9083016SGiridhar Malavali 1090a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1091a9083016SGiridhar Malavali 1092a9083016SGiridhar Malavali done_write: 1093d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1094a9083016SGiridhar Malavali return ret; 1095a9083016SGiridhar Malavali } 1096a9083016SGiridhar Malavali 1097a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1098a9083016SGiridhar Malavali * to put the ISP into operational state 1099a9083016SGiridhar Malavali */ 110077e334d2SGiridhar Malavali static int 110177e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102a9083016SGiridhar Malavali { 1103a9083016SGiridhar Malavali int addr, val; 1104a9083016SGiridhar Malavali int i ; 1105a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1106a9083016SGiridhar Malavali unsigned long off; 1107a9083016SGiridhar Malavali unsigned offset, n; 1108a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1109a9083016SGiridhar Malavali 1110a9083016SGiridhar Malavali struct crb_addr_pair { 1111a9083016SGiridhar Malavali long addr; 1112a9083016SGiridhar Malavali long data; 1113a9083016SGiridhar Malavali }; 1114a9083016SGiridhar Malavali 1115a9083016SGiridhar Malavali /* Halt all the indiviual PEGs and other blocks of the ISP */ 1116a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1117c9e8fd5cSMadhuranath Iyengar 111802be2215SGiridhar Malavali /* disable all I2Q */ 111902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 112002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 112102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 112202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 112302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 112402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 112502be2215SGiridhar Malavali 112602be2215SGiridhar Malavali /* disable all niu interrupts */ 1127c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1129c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1131c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 113202be2215SGiridhar Malavali /* disable sideband mac */ 113302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 113402be2215SGiridhar Malavali /* disable ap0 mac */ 113502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 113602be2215SGiridhar Malavali /* disable ap1 mac */ 113702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138c9e8fd5cSMadhuranath Iyengar 1139c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1140c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142c9e8fd5cSMadhuranath Iyengar 1143c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1144c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145c9e8fd5cSMadhuranath Iyengar 1146c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1147c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 115202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153c9e8fd5cSMadhuranath Iyengar 1154c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1155c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 116002be2215SGiridhar Malavali msleep(20); 1161c9e8fd5cSMadhuranath Iyengar 1162c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1163a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1165a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166a9083016SGiridhar Malavali else 1167a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1169a9083016SGiridhar Malavali 1170a9083016SGiridhar Malavali /* Read the signature value from the flash. 1171a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1172a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1173a9083016SGiridhar Malavali * that present in CRB initialize sequence 1174a9083016SGiridhar Malavali */ 1175a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1176a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11777c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11787c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1179a9083016SGiridhar Malavali return -1; 1180a9083016SGiridhar Malavali } 1181a9083016SGiridhar Malavali 1182a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 1183a9083016SGiridhar Malavali * Number of enteries = upper 16 bits 1184a9083016SGiridhar Malavali */ 1185a9083016SGiridhar Malavali offset = n & 0xffffU; 1186a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1187a9083016SGiridhar Malavali 1188a9083016SGiridhar Malavali /* number of addr/value pair should not exceed 1024 enteries */ 1189a9083016SGiridhar Malavali if (n >= 1024) { 11907c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 11917c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1192a9083016SGiridhar Malavali return -1; 1193a9083016SGiridhar Malavali } 1194a9083016SGiridhar Malavali 11957c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 11967c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1197a9083016SGiridhar Malavali 1198a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1199a9083016SGiridhar Malavali if (buf == NULL) { 12007c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12017c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1202a9083016SGiridhar Malavali return -1; 1203a9083016SGiridhar Malavali } 1204a9083016SGiridhar Malavali 1205a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1206a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1207a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1208a9083016SGiridhar Malavali kfree(buf); 1209a9083016SGiridhar Malavali return -1; 1210a9083016SGiridhar Malavali } 1211a9083016SGiridhar Malavali 1212a9083016SGiridhar Malavali buf[i].addr = addr; 1213a9083016SGiridhar Malavali buf[i].data = val; 1214a9083016SGiridhar Malavali } 1215a9083016SGiridhar Malavali 1216a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1217a9083016SGiridhar Malavali /* Translate internal CRB initialization 1218a9083016SGiridhar Malavali * address to PCI bus address 1219a9083016SGiridhar Malavali */ 1220a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1221a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1222a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1223a9083016SGiridhar Malavali * some of them are skipped 1224a9083016SGiridhar Malavali */ 1225a9083016SGiridhar Malavali 1226a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1227a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1228a9083016SGiridhar Malavali continue; 1229a9083016SGiridhar Malavali 1230a9083016SGiridhar Malavali /* do not reset PCI */ 1231a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1232a9083016SGiridhar Malavali continue; 1233a9083016SGiridhar Malavali 1234a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1235a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1236a9083016SGiridhar Malavali continue; 1237a9083016SGiridhar Malavali 1238a9083016SGiridhar Malavali /* skip the function enable register */ 1239a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1240a9083016SGiridhar Malavali continue; 1241a9083016SGiridhar Malavali 1242a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1243a9083016SGiridhar Malavali continue; 1244a9083016SGiridhar Malavali 1245a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1246a9083016SGiridhar Malavali continue; 1247a9083016SGiridhar Malavali 1248a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1249a9083016SGiridhar Malavali continue; 1250a9083016SGiridhar Malavali 1251a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12527c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 12537c3df132SSaurav Kashyap "Unknow addr: 0x%08lx.\n", buf[i].addr); 1254a9083016SGiridhar Malavali continue; 1255a9083016SGiridhar Malavali } 1256a9083016SGiridhar Malavali 1257a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1258a9083016SGiridhar Malavali 1259a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1260a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1261a9083016SGiridhar Malavali */ 1262a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1263a9083016SGiridhar Malavali msleep(1000); 1264a9083016SGiridhar Malavali 1265a9083016SGiridhar Malavali /* ISP requires millisec delay between 1266a9083016SGiridhar Malavali * successive CRB register updation 1267a9083016SGiridhar Malavali */ 1268a9083016SGiridhar Malavali msleep(1); 1269a9083016SGiridhar Malavali } 1270a9083016SGiridhar Malavali 1271a9083016SGiridhar Malavali kfree(buf); 1272a9083016SGiridhar Malavali 1273a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1274a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1275a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1276a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1277a9083016SGiridhar Malavali 1278a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1279a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1280a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1281a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1282a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1283a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1284a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1285a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1286a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1287a9083016SGiridhar Malavali return 0; 1288a9083016SGiridhar Malavali } 1289a9083016SGiridhar Malavali 129077e334d2SGiridhar Malavali static int 129177e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 129277e334d2SGiridhar Malavali u64 off, void *data, int size) 129377e334d2SGiridhar Malavali { 129477e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 129577e334d2SGiridhar Malavali int scale, shift_amount, startword; 129677e334d2SGiridhar Malavali uint32_t temp; 129777e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 129877e334d2SGiridhar Malavali 129977e334d2SGiridhar Malavali /* 130077e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 130177e334d2SGiridhar Malavali */ 130277e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 130377e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 130477e334d2SGiridhar Malavali else { 130577e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 130677e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 130777e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 130877e334d2SGiridhar Malavali off, data, size); 130977e334d2SGiridhar Malavali } 131077e334d2SGiridhar Malavali 131177e334d2SGiridhar Malavali off0 = off & 0x7; 131277e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 131377e334d2SGiridhar Malavali sz[1] = size - sz[0]; 131477e334d2SGiridhar Malavali 131577e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 131677e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 131777e334d2SGiridhar Malavali shift_amount = 4; 131877e334d2SGiridhar Malavali scale = 2; 131977e334d2SGiridhar Malavali startword = (off & 0xf)/8; 132077e334d2SGiridhar Malavali 132177e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 132277e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 132377e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 132477e334d2SGiridhar Malavali return -1; 132577e334d2SGiridhar Malavali } 132677e334d2SGiridhar Malavali 132777e334d2SGiridhar Malavali switch (size) { 132877e334d2SGiridhar Malavali case 1: 132977e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 133077e334d2SGiridhar Malavali break; 133177e334d2SGiridhar Malavali case 2: 133277e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 133377e334d2SGiridhar Malavali break; 133477e334d2SGiridhar Malavali case 4: 133577e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 133677e334d2SGiridhar Malavali break; 133777e334d2SGiridhar Malavali case 8: 133877e334d2SGiridhar Malavali default: 133977e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 134077e334d2SGiridhar Malavali break; 134177e334d2SGiridhar Malavali } 134277e334d2SGiridhar Malavali 134377e334d2SGiridhar Malavali if (sz[0] == 8) { 134477e334d2SGiridhar Malavali word[startword] = tmpw; 134577e334d2SGiridhar Malavali } else { 134677e334d2SGiridhar Malavali word[startword] &= 134777e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 134877e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 134977e334d2SGiridhar Malavali } 135077e334d2SGiridhar Malavali if (sz[1] != 0) { 135177e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 135277e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 135377e334d2SGiridhar Malavali } 135477e334d2SGiridhar Malavali 135577e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 135677e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 135777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 135877e334d2SGiridhar Malavali temp = 0; 135977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 136077e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 136177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 136277e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 136377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 136477e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 136577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 136677e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 136777e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 136877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 136977e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 137077e334d2SGiridhar Malavali 137177e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 137277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 137377e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 137477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 137577e334d2SGiridhar Malavali 137677e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 137777e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 137877e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 137977e334d2SGiridhar Malavali break; 138077e334d2SGiridhar Malavali } 138177e334d2SGiridhar Malavali 138277e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 138377e334d2SGiridhar Malavali if (printk_ratelimit()) 138477e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 13857c3df132SSaurav Kashyap "failed to write through agent.\n"); 138677e334d2SGiridhar Malavali ret = -1; 138777e334d2SGiridhar Malavali break; 138877e334d2SGiridhar Malavali } 138977e334d2SGiridhar Malavali } 139077e334d2SGiridhar Malavali 139177e334d2SGiridhar Malavali return ret; 139277e334d2SGiridhar Malavali } 139377e334d2SGiridhar Malavali 139477e334d2SGiridhar Malavali static int 1395a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1396a9083016SGiridhar Malavali { 1397a9083016SGiridhar Malavali int i; 1398a9083016SGiridhar Malavali long size = 0; 13999c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14009c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1401a9083016SGiridhar Malavali u64 data; 1402a9083016SGiridhar Malavali u32 high, low; 1403a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1404a9083016SGiridhar Malavali 1405a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1406a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1407a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1408a9083016SGiridhar Malavali return -1; 1409a9083016SGiridhar Malavali } 1410a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1411a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1412a9083016SGiridhar Malavali flashaddr += 8; 1413a9083016SGiridhar Malavali memaddr += 8; 1414a9083016SGiridhar Malavali 1415a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1416a9083016SGiridhar Malavali msleep(1); 1417a9083016SGiridhar Malavali } 1418a9083016SGiridhar Malavali udelay(100); 1419a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1420a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1421a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1422a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1423a9083016SGiridhar Malavali return 0; 1424a9083016SGiridhar Malavali } 1425a9083016SGiridhar Malavali 1426a9083016SGiridhar Malavali int 1427a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1428a9083016SGiridhar Malavali u64 off, void *data, int size) 1429a9083016SGiridhar Malavali { 1430a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1431a9083016SGiridhar Malavali int shift_amount; 1432a9083016SGiridhar Malavali uint32_t temp; 1433a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1434a9083016SGiridhar Malavali 1435a9083016SGiridhar Malavali /* 1436a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1437a9083016SGiridhar Malavali */ 1438a9083016SGiridhar Malavali 1439a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1440a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1441a9083016SGiridhar Malavali else { 1442a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1443a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1444a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1445a9083016SGiridhar Malavali off, data, size); 1446a9083016SGiridhar Malavali } 1447a9083016SGiridhar Malavali 1448a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1449a9083016SGiridhar Malavali off0[0] = off & 0xf; 1450a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1451a9083016SGiridhar Malavali shift_amount = 4; 1452a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1453a9083016SGiridhar Malavali off0[1] = 0; 1454a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1455a9083016SGiridhar Malavali 1456a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1457a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1458a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1459a9083016SGiridhar Malavali temp = 0; 1460a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1461a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1462a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1463a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1464a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1465a9083016SGiridhar Malavali 1466a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1467a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1468a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1469a9083016SGiridhar Malavali break; 1470a9083016SGiridhar Malavali } 1471a9083016SGiridhar Malavali 1472a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1473a9083016SGiridhar Malavali if (printk_ratelimit()) 1474a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14757c3df132SSaurav Kashyap "failed to read through agent.\n"); 1476a9083016SGiridhar Malavali break; 1477a9083016SGiridhar Malavali } 1478a9083016SGiridhar Malavali 1479a9083016SGiridhar Malavali start = off0[i] >> 2; 1480a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1481a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1482a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1483a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1484a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1485a9083016SGiridhar Malavali } 1486a9083016SGiridhar Malavali } 1487a9083016SGiridhar Malavali 1488a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1489a9083016SGiridhar Malavali return -1; 1490a9083016SGiridhar Malavali 1491a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1492a9083016SGiridhar Malavali val = word[0]; 1493a9083016SGiridhar Malavali } else { 1494a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1495a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1496a9083016SGiridhar Malavali } 1497a9083016SGiridhar Malavali 1498a9083016SGiridhar Malavali switch (size) { 1499a9083016SGiridhar Malavali case 1: 1500a9083016SGiridhar Malavali *(uint8_t *)data = val; 1501a9083016SGiridhar Malavali break; 1502a9083016SGiridhar Malavali case 2: 1503a9083016SGiridhar Malavali *(uint16_t *)data = val; 1504a9083016SGiridhar Malavali break; 1505a9083016SGiridhar Malavali case 4: 1506a9083016SGiridhar Malavali *(uint32_t *)data = val; 1507a9083016SGiridhar Malavali break; 1508a9083016SGiridhar Malavali case 8: 1509a9083016SGiridhar Malavali *(uint64_t *)data = val; 1510a9083016SGiridhar Malavali break; 1511a9083016SGiridhar Malavali } 1512a9083016SGiridhar Malavali return 0; 1513a9083016SGiridhar Malavali } 1514a9083016SGiridhar Malavali 1515a9083016SGiridhar Malavali 15169c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15179c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15189c2b2975SHarish Zunjarrao { 15199c2b2975SHarish Zunjarrao uint32_t i; 15209c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15219c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15229c2b2975SHarish Zunjarrao __le32 offset; 15239c2b2975SHarish Zunjarrao __le32 tab_type; 15249c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15259c2b2975SHarish Zunjarrao 15269c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15279c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15289c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15299c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15309c2b2975SHarish Zunjarrao 15319c2b2975SHarish Zunjarrao if (tab_type == section) 15329c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15339c2b2975SHarish Zunjarrao } 15349c2b2975SHarish Zunjarrao 15359c2b2975SHarish Zunjarrao return NULL; 15369c2b2975SHarish Zunjarrao } 15379c2b2975SHarish Zunjarrao 15389c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15399c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15409c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15419c2b2975SHarish Zunjarrao { 15429c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15439c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15449c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15459c2b2975SHarish Zunjarrao __le32 offset; 15469c2b2975SHarish Zunjarrao 15479c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15489c2b2975SHarish Zunjarrao if (!tab_desc) 15499c2b2975SHarish Zunjarrao return NULL; 15509c2b2975SHarish Zunjarrao 15519c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15529c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15539c2b2975SHarish Zunjarrao 15549c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15559c2b2975SHarish Zunjarrao } 15569c2b2975SHarish Zunjarrao 15579c2b2975SHarish Zunjarrao static u8 * 15589c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15599c2b2975SHarish Zunjarrao { 15609c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15619c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15629c2b2975SHarish Zunjarrao 15639c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15649c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15659c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15669c2b2975SHarish Zunjarrao if (uri_desc) 15679c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15689c2b2975SHarish Zunjarrao } 15699c2b2975SHarish Zunjarrao 15709c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15719c2b2975SHarish Zunjarrao } 15729c2b2975SHarish Zunjarrao 15739c2b2975SHarish Zunjarrao static __le32 15749c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15759c2b2975SHarish Zunjarrao { 15769c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15779c2b2975SHarish Zunjarrao 15789c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15799c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15809c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15819c2b2975SHarish Zunjarrao if (uri_desc) 15829c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 15839c2b2975SHarish Zunjarrao } 15849c2b2975SHarish Zunjarrao 15859c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15869c2b2975SHarish Zunjarrao } 15879c2b2975SHarish Zunjarrao 15889c2b2975SHarish Zunjarrao static u8 * 15899c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 15909c2b2975SHarish Zunjarrao { 15919c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 15929c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15939c2b2975SHarish Zunjarrao 15949c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15959c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15969c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15979c2b2975SHarish Zunjarrao if (uri_desc) 15989c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15999c2b2975SHarish Zunjarrao } 16009c2b2975SHarish Zunjarrao 16019c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16029c2b2975SHarish Zunjarrao } 16039c2b2975SHarish Zunjarrao 1604a9083016SGiridhar Malavali /* PCI related functions */ 1605a9083016SGiridhar Malavali char * 1606a9083016SGiridhar Malavali qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1607a9083016SGiridhar Malavali { 1608a9083016SGiridhar Malavali int pcie_reg; 1609a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1610a9083016SGiridhar Malavali char lwstr[6]; 1611a9083016SGiridhar Malavali uint16_t lnk; 1612a9083016SGiridhar Malavali 1613a9083016SGiridhar Malavali pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1614a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1615a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 1616a9083016SGiridhar Malavali 1617a9083016SGiridhar Malavali strcpy(str, "PCIe ("); 1618a9083016SGiridhar Malavali strcat(str, "2.5Gb/s "); 1619a9083016SGiridhar Malavali snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1620a9083016SGiridhar Malavali strcat(str, lwstr); 1621a9083016SGiridhar Malavali return str; 1622a9083016SGiridhar Malavali } 1623a9083016SGiridhar Malavali 1624a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1625a9083016SGiridhar Malavali { 1626a9083016SGiridhar Malavali unsigned long val = 0; 1627a9083016SGiridhar Malavali u32 control; 1628a9083016SGiridhar Malavali 1629a9083016SGiridhar Malavali switch (region) { 1630a9083016SGiridhar Malavali case 0: 1631a9083016SGiridhar Malavali val = 0; 1632a9083016SGiridhar Malavali break; 1633a9083016SGiridhar Malavali case 1: 1634a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1635a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1636a9083016SGiridhar Malavali break; 1637a9083016SGiridhar Malavali } 1638a9083016SGiridhar Malavali return val; 1639a9083016SGiridhar Malavali } 1640a9083016SGiridhar Malavali 1641a9083016SGiridhar Malavali 1642a9083016SGiridhar Malavali int 1643a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1644a9083016SGiridhar Malavali { 1645a9083016SGiridhar Malavali uint32_t len = 0; 1646a9083016SGiridhar Malavali 1647a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16487c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16497c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1650a9083016SGiridhar Malavali goto iospace_error_exit; 1651a9083016SGiridhar Malavali } 1652a9083016SGiridhar Malavali 1653a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1654a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16557c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16567c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1657a9083016SGiridhar Malavali goto iospace_error_exit; 1658a9083016SGiridhar Malavali } 1659a9083016SGiridhar Malavali 1660a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1661a9083016SGiridhar Malavali ha->nx_pcibase = 1662a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1663a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16647c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16657c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1666a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1667a9083016SGiridhar Malavali goto iospace_error_exit; 1668a9083016SGiridhar Malavali } 1669a9083016SGiridhar Malavali 1670a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1671a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1672a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1673a9083016SGiridhar Malavali 1674a9083016SGiridhar Malavali if (!ql2xdbwr) { 1675a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1676a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1677a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1678a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16797c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16807c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1681a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1682a9083016SGiridhar Malavali goto iospace_error_exit; 1683a9083016SGiridhar Malavali } 1684a9083016SGiridhar Malavali 1685a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1686a9083016SGiridhar Malavali * door bell read and write pointer 1687a9083016SGiridhar Malavali */ 1688a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1689a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1690a9083016SGiridhar Malavali } else { 1691a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1692a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1693a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1694a9083016SGiridhar Malavali } 1695a9083016SGiridhar Malavali 1696a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1697a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 16987c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 16997c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17007c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1701d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17027c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17037c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17047c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17057c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1706d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17077c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1708a9083016SGiridhar Malavali return 0; 1709a9083016SGiridhar Malavali 1710a9083016SGiridhar Malavali iospace_error_exit: 1711a9083016SGiridhar Malavali return -ENOMEM; 1712a9083016SGiridhar Malavali } 1713a9083016SGiridhar Malavali 1714a9083016SGiridhar Malavali /* GS related functions */ 1715a9083016SGiridhar Malavali 1716a9083016SGiridhar Malavali /* Initialization related functions */ 1717a9083016SGiridhar Malavali 1718a9083016SGiridhar Malavali /** 1719a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1720a9083016SGiridhar Malavali * @ha: HA context 1721a9083016SGiridhar Malavali * 1722a9083016SGiridhar Malavali * Returns 0 on success. 1723a9083016SGiridhar Malavali */ 1724a9083016SGiridhar Malavali int 1725a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1726a9083016SGiridhar Malavali { 1727a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1728a9083016SGiridhar Malavali int ret; 1729a9083016SGiridhar Malavali 1730a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1731a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1732a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17337c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 1734d8424f68SJoe Perches "Chip revision:%d.\n", 17357c3df132SSaurav Kashyap ha->chip_revision); 1736a9083016SGiridhar Malavali return 0; 1737a9083016SGiridhar Malavali } 1738a9083016SGiridhar Malavali 1739a9083016SGiridhar Malavali /** 1740a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1741a9083016SGiridhar Malavali * @ha: HA context 1742a9083016SGiridhar Malavali * 1743a9083016SGiridhar Malavali * Returns 0 on success. 1744a9083016SGiridhar Malavali */ 1745a9083016SGiridhar Malavali void 1746a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1747a9083016SGiridhar Malavali { 1748a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1749a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1750a9083016SGiridhar Malavali } 1751a9083016SGiridhar Malavali 1752a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1753a9083016SGiridhar Malavali { 1754a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1755a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1756a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1757a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1758a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1759a9083016SGiridhar Malavali 1760a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1761a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1762a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1763a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1764a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1765a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1766a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1767a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1768a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1769a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1770a9083016SGiridhar Malavali 1771a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1772a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1773a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1774a9083016SGiridhar Malavali } 1775a9083016SGiridhar Malavali 1776f1af6208SGiridhar Malavali void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1777f1af6208SGiridhar Malavali { 1778f1af6208SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1779f1af6208SGiridhar Malavali vha->flags.online = 0; 1780f1af6208SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 1781f1af6208SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1782f1af6208SGiridhar Malavali } 1783f1af6208SGiridhar Malavali 178477e334d2SGiridhar Malavali static int 178577e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1786a9083016SGiridhar Malavali { 1787a9083016SGiridhar Malavali u64 *ptr64; 1788a9083016SGiridhar Malavali u32 i, flashaddr, size; 1789a9083016SGiridhar Malavali __le64 data; 1790a9083016SGiridhar Malavali 1791a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1792a9083016SGiridhar Malavali 17939c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1794a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1795a9083016SGiridhar Malavali 1796a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1797a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17989c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17999c2b2975SHarish Zunjarrao return -EIO; 1800a9083016SGiridhar Malavali flashaddr += 8; 1801a9083016SGiridhar Malavali } 1802a9083016SGiridhar Malavali 1803a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18049c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18059c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1806a9083016SGiridhar Malavali 1807a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1808a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1809a9083016SGiridhar Malavali 1810a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1811a9083016SGiridhar Malavali return -EIO; 1812a9083016SGiridhar Malavali flashaddr += 8; 1813a9083016SGiridhar Malavali } 18149c2b2975SHarish Zunjarrao udelay(100); 1815a9083016SGiridhar Malavali 1816a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1817a9083016SGiridhar Malavali * at a specified offset to indicate 1818a9083016SGiridhar Malavali * that all data is written and 1819a9083016SGiridhar Malavali * ready for firmware to initialize. 1820a9083016SGiridhar Malavali */ 18219c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1822a9083016SGiridhar Malavali 18239c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1824a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1825a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18269c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18279c2b2975SHarish Zunjarrao return 0; 18289c2b2975SHarish Zunjarrao } 18299c2b2975SHarish Zunjarrao 18309c2b2975SHarish Zunjarrao static int 18319c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18329c2b2975SHarish Zunjarrao { 18339c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18349c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18359c2b2975SHarish Zunjarrao uint32_t i; 18369c2b2975SHarish Zunjarrao __le32 entries; 18379c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18389c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18399c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18409c2b2975SHarish Zunjarrao int mn_present = 0; 18419c2b2975SHarish Zunjarrao uint32_t flagbit; 18429c2b2975SHarish Zunjarrao 18439c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18449c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18459c2b2975SHarish Zunjarrao if (!ptab_desc) 18469c2b2975SHarish Zunjarrao return -1; 18479c2b2975SHarish Zunjarrao 18489c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18499c2b2975SHarish Zunjarrao 18509c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18519c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18529c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18539c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18549c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18559c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18569c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18579c2b2975SHarish Zunjarrao 18589c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18599c2b2975SHarish Zunjarrao 18609c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18619c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18629c2b2975SHarish Zunjarrao return 0; 18639c2b2975SHarish Zunjarrao } 18649c2b2975SHarish Zunjarrao } 18659c2b2975SHarish Zunjarrao return -1; 18669c2b2975SHarish Zunjarrao } 18679c2b2975SHarish Zunjarrao 18689c2b2975SHarish Zunjarrao int 18699c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18709c2b2975SHarish Zunjarrao { 18719c2b2975SHarish Zunjarrao __le32 val; 18729c2b2975SHarish Zunjarrao uint32_t min_size; 18739c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18749c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18759c2b2975SHarish Zunjarrao 18769c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18779c2b2975SHarish Zunjarrao 18789c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18799c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18809c2b2975SHarish Zunjarrao return -EINVAL; 18819c2b2975SHarish Zunjarrao 18829c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18839c2b2975SHarish Zunjarrao } else { 18849c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18859c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18869c2b2975SHarish Zunjarrao return -EINVAL; 18879c2b2975SHarish Zunjarrao 18889c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18899c2b2975SHarish Zunjarrao } 18909c2b2975SHarish Zunjarrao 18919c2b2975SHarish Zunjarrao if (fw->size < min_size) 18929c2b2975SHarish Zunjarrao return -EINVAL; 1893a9083016SGiridhar Malavali return 0; 1894a9083016SGiridhar Malavali } 1895a9083016SGiridhar Malavali 189677e334d2SGiridhar Malavali static int 189777e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1898a9083016SGiridhar Malavali { 1899a9083016SGiridhar Malavali u32 val = 0; 1900a9083016SGiridhar Malavali int retries = 60; 19017c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1902a9083016SGiridhar Malavali 1903a9083016SGiridhar Malavali do { 1904a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1905a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1906a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1907a9083016SGiridhar Malavali 1908a9083016SGiridhar Malavali switch (val) { 1909a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1910a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1911a9083016SGiridhar Malavali return QLA_SUCCESS; 1912a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1913a9083016SGiridhar Malavali break; 1914a9083016SGiridhar Malavali default: 1915a9083016SGiridhar Malavali break; 1916a9083016SGiridhar Malavali } 19177c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19187c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1919a9083016SGiridhar Malavali val, retries); 1920a9083016SGiridhar Malavali 1921a9083016SGiridhar Malavali msleep(500); 1922a9083016SGiridhar Malavali 1923a9083016SGiridhar Malavali } while (--retries); 1924a9083016SGiridhar Malavali 19257c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1926a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1927a9083016SGiridhar Malavali 1928a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1929a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1930a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1931a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1932a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1933a9083016SGiridhar Malavali } 1934a9083016SGiridhar Malavali 193577e334d2SGiridhar Malavali static int 193677e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1937a9083016SGiridhar Malavali { 1938a9083016SGiridhar Malavali u32 val = 0; 1939a9083016SGiridhar Malavali int retries = 60; 19407c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1941a9083016SGiridhar Malavali 1942a9083016SGiridhar Malavali do { 1943a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1944a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1945a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1946a9083016SGiridhar Malavali 1947a9083016SGiridhar Malavali switch (val) { 1948a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1949a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1950a9083016SGiridhar Malavali return QLA_SUCCESS; 1951a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1952a9083016SGiridhar Malavali break; 1953a9083016SGiridhar Malavali default: 1954a9083016SGiridhar Malavali break; 1955a9083016SGiridhar Malavali } 19567c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19577c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1958a9083016SGiridhar Malavali val, retries); 1959a9083016SGiridhar Malavali 1960a9083016SGiridhar Malavali msleep(500); 1961a9083016SGiridhar Malavali 1962a9083016SGiridhar Malavali } while (--retries); 1963a9083016SGiridhar Malavali 19647c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19657c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1966a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1967a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1968a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1969a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1970a9083016SGiridhar Malavali } 1971a9083016SGiridhar Malavali 1972a9083016SGiridhar Malavali /* ISR related functions */ 1973a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1974a9083016SGiridhar Malavali ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1975a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1976a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1977a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1978a9083016SGiridhar Malavali }; 1979a9083016SGiridhar Malavali 1980a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_status[8] = { 1981a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1982a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1983a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1984a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1985a9083016SGiridhar Malavali }; 1986a9083016SGiridhar Malavali 1987a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1988a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1989a9083016SGiridhar Malavali 1990a9083016SGiridhar Malavali /* 1991a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1992a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1993a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1994a9083016SGiridhar Malavali */ 199577e334d2SGiridhar Malavali static void 1996a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1997a9083016SGiridhar Malavali { 1998a9083016SGiridhar Malavali uint16_t cnt; 1999a9083016SGiridhar Malavali uint16_t __iomem *wptr; 2000a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2001a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2002a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2003a9083016SGiridhar Malavali 2004a9083016SGiridhar Malavali /* Load return mailbox registers. */ 2005a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 2006a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 2007a9083016SGiridhar Malavali 2008a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2009a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2010a9083016SGiridhar Malavali wptr++; 2011a9083016SGiridhar Malavali } 2012a9083016SGiridhar Malavali 2013cfb0919cSChad Dupuis if (!ha->mcp) 20147c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 20157c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 2016a9083016SGiridhar Malavali } 2017a9083016SGiridhar Malavali 2018a9083016SGiridhar Malavali /* 2019a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2020a9083016SGiridhar Malavali * @irq: 2021a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2022a9083016SGiridhar Malavali * @regs: 2023a9083016SGiridhar Malavali * 2024a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2025a9083016SGiridhar Malavali * 2026a9083016SGiridhar Malavali * Returns handled flag. 2027a9083016SGiridhar Malavali */ 2028a9083016SGiridhar Malavali irqreturn_t 2029a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2030a9083016SGiridhar Malavali { 2031a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2032a9083016SGiridhar Malavali struct qla_hw_data *ha; 2033a9083016SGiridhar Malavali struct rsp_que *rsp; 2034a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2035a9083016SGiridhar Malavali int status = 0, status1 = 0; 2036a9083016SGiridhar Malavali unsigned long flags; 2037a9083016SGiridhar Malavali unsigned long iter; 20387c3df132SSaurav Kashyap uint32_t stat = 0; 2039a9083016SGiridhar Malavali uint16_t mb[4]; 2040a9083016SGiridhar Malavali 2041a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2042a9083016SGiridhar Malavali if (!rsp) { 2043a9083016SGiridhar Malavali printk(KERN_INFO 20447c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2045a9083016SGiridhar Malavali return IRQ_NONE; 2046a9083016SGiridhar Malavali } 2047a9083016SGiridhar Malavali ha = rsp->hw; 2048a9083016SGiridhar Malavali 2049a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2050a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2051a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2052a9083016SGiridhar Malavali return IRQ_NONE; 2053a9083016SGiridhar Malavali 2054a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2055a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2056a9083016SGiridhar Malavali return IRQ_NONE; 2057a9083016SGiridhar Malavali } 2058a9083016SGiridhar Malavali 2059a9083016SGiridhar Malavali /* clear the interrupt */ 2060a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2061a9083016SGiridhar Malavali 2062a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2063a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2064a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2065a9083016SGiridhar Malavali 2066a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2067a9083016SGiridhar Malavali 2068a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2069a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2070a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2071a9083016SGiridhar Malavali 2072a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2073a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2074a9083016SGiridhar Malavali 2075a9083016SGiridhar Malavali switch (stat & 0xff) { 2076a9083016SGiridhar Malavali case 0x1: 2077a9083016SGiridhar Malavali case 0x2: 2078a9083016SGiridhar Malavali case 0x10: 2079a9083016SGiridhar Malavali case 0x11: 2080a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2081a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2082a9083016SGiridhar Malavali break; 2083a9083016SGiridhar Malavali case 0x12: 2084a9083016SGiridhar Malavali mb[0] = MSW(stat); 2085a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2086a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2087a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2088a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2089a9083016SGiridhar Malavali break; 2090a9083016SGiridhar Malavali case 0x13: 2091a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2092a9083016SGiridhar Malavali break; 2093a9083016SGiridhar Malavali default: 20947c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2095a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20967c3df132SSaurav Kashyap stat & 0xff); 2097a9083016SGiridhar Malavali break; 2098a9083016SGiridhar Malavali } 2099a9083016SGiridhar Malavali } 2100a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2101a9083016SGiridhar Malavali } 2102a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2103a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2104a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2105a9083016SGiridhar Malavali 2106a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2107a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21087c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x503d, 21097c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2110a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2111a9083016SGiridhar Malavali #endif 2112a9083016SGiridhar Malavali 2113a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2114a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2115a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2116a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2117a9083016SGiridhar Malavali } 2118a9083016SGiridhar Malavali return IRQ_HANDLED; 2119a9083016SGiridhar Malavali } 2120a9083016SGiridhar Malavali 2121a9083016SGiridhar Malavali irqreturn_t 2122a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2123a9083016SGiridhar Malavali { 2124a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2125a9083016SGiridhar Malavali struct qla_hw_data *ha; 2126a9083016SGiridhar Malavali struct rsp_que *rsp; 2127a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2128a9083016SGiridhar Malavali int status = 0; 2129a9083016SGiridhar Malavali unsigned long flags; 21307c3df132SSaurav Kashyap uint32_t stat = 0; 2131a9083016SGiridhar Malavali uint16_t mb[4]; 2132a9083016SGiridhar Malavali 2133a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2134a9083016SGiridhar Malavali if (!rsp) { 2135a9083016SGiridhar Malavali printk(KERN_INFO 21367c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2137a9083016SGiridhar Malavali return IRQ_NONE; 2138a9083016SGiridhar Malavali } 2139a9083016SGiridhar Malavali ha = rsp->hw; 2140a9083016SGiridhar Malavali 2141a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2142a9083016SGiridhar Malavali 2143a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2144a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2145a9083016SGiridhar Malavali do { 2146a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2147a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2148a9083016SGiridhar Malavali 2149a9083016SGiridhar Malavali switch (stat & 0xff) { 2150a9083016SGiridhar Malavali case 0x1: 2151a9083016SGiridhar Malavali case 0x2: 2152a9083016SGiridhar Malavali case 0x10: 2153a9083016SGiridhar Malavali case 0x11: 2154a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2155a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2156a9083016SGiridhar Malavali break; 2157a9083016SGiridhar Malavali case 0x12: 2158a9083016SGiridhar Malavali mb[0] = MSW(stat); 2159a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2160a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2161a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2162a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2163a9083016SGiridhar Malavali break; 2164a9083016SGiridhar Malavali case 0x13: 2165a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2166a9083016SGiridhar Malavali break; 2167a9083016SGiridhar Malavali default: 21687c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2169a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21707c3df132SSaurav Kashyap stat & 0xff); 2171a9083016SGiridhar Malavali break; 2172a9083016SGiridhar Malavali } 2173a9083016SGiridhar Malavali } 2174a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2175a9083016SGiridhar Malavali } while (0); 2176a9083016SGiridhar Malavali 2177a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2178a9083016SGiridhar Malavali 2179a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2180a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x5044, 21827c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2183a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2184a9083016SGiridhar Malavali #endif 2185a9083016SGiridhar Malavali 2186a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2187a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2188a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2189a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2190a9083016SGiridhar Malavali } 2191a9083016SGiridhar Malavali return IRQ_HANDLED; 2192a9083016SGiridhar Malavali } 2193a9083016SGiridhar Malavali 2194a9083016SGiridhar Malavali irqreturn_t 2195a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2196a9083016SGiridhar Malavali { 2197a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2198a9083016SGiridhar Malavali struct qla_hw_data *ha; 2199a9083016SGiridhar Malavali struct rsp_que *rsp; 2200a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 22013553d343SSaurav Kashyap unsigned long flags; 2202a9083016SGiridhar Malavali 2203a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2204a9083016SGiridhar Malavali if (!rsp) { 2205a9083016SGiridhar Malavali printk(KERN_INFO 22067c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2207a9083016SGiridhar Malavali return IRQ_NONE; 2208a9083016SGiridhar Malavali } 2209a9083016SGiridhar Malavali 2210a9083016SGiridhar Malavali ha = rsp->hw; 2211a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 22123553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2213a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2214a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2215a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 22163553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2217a9083016SGiridhar Malavali return IRQ_HANDLED; 2218a9083016SGiridhar Malavali } 2219a9083016SGiridhar Malavali 2220a9083016SGiridhar Malavali void 2221a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2222a9083016SGiridhar Malavali { 2223a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2224a9083016SGiridhar Malavali struct qla_hw_data *ha; 2225a9083016SGiridhar Malavali struct rsp_que *rsp; 2226a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2227a9083016SGiridhar Malavali int status = 0; 2228a9083016SGiridhar Malavali uint32_t stat; 2229a9083016SGiridhar Malavali uint16_t mb[4]; 2230a9083016SGiridhar Malavali unsigned long flags; 2231a9083016SGiridhar Malavali 2232a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2233a9083016SGiridhar Malavali if (!rsp) { 2234a9083016SGiridhar Malavali printk(KERN_INFO 22357c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2236a9083016SGiridhar Malavali return; 2237a9083016SGiridhar Malavali } 2238a9083016SGiridhar Malavali ha = rsp->hw; 2239a9083016SGiridhar Malavali 2240a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2241a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2242a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2243a9083016SGiridhar Malavali 2244a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2245a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2246a9083016SGiridhar Malavali switch (stat & 0xff) { 2247a9083016SGiridhar Malavali case 0x1: 2248a9083016SGiridhar Malavali case 0x2: 2249a9083016SGiridhar Malavali case 0x10: 2250a9083016SGiridhar Malavali case 0x11: 2251a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2252a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2253a9083016SGiridhar Malavali break; 2254a9083016SGiridhar Malavali case 0x12: 2255a9083016SGiridhar Malavali mb[0] = MSW(stat); 2256a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2257a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2258a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2259a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2260a9083016SGiridhar Malavali break; 2261a9083016SGiridhar Malavali case 0x13: 2262a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2263a9083016SGiridhar Malavali break; 2264a9083016SGiridhar Malavali default: 22657c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22667c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22677c3df132SSaurav Kashyap stat * 0xff); 2268a9083016SGiridhar Malavali break; 2269a9083016SGiridhar Malavali } 2270a9083016SGiridhar Malavali } 2271a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2272a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2273a9083016SGiridhar Malavali } 2274a9083016SGiridhar Malavali 2275a9083016SGiridhar Malavali void 2276a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2277a9083016SGiridhar Malavali { 2278a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2279a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2280a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2281a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2282a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2283a9083016SGiridhar Malavali ha->interrupts_on = 1; 2284a9083016SGiridhar Malavali } 2285a9083016SGiridhar Malavali 2286a9083016SGiridhar Malavali void 2287a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2288a9083016SGiridhar Malavali { 2289a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2290a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2291a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2292a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2293a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2294a9083016SGiridhar Malavali ha->interrupts_on = 0; 2295a9083016SGiridhar Malavali } 2296a9083016SGiridhar Malavali 2297a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2298a9083016SGiridhar Malavali { 2299a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2300a9083016SGiridhar Malavali 2301a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2302a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2303a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2304a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2305a9083016SGiridhar Malavali ha->curr_window = 255; 2306a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2307a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2308a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2309a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2310a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2311a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2312a9083016SGiridhar Malavali } 2313a9083016SGiridhar Malavali 2314a5b36321SLalit Chandivade inline void 2315a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2316a9083016SGiridhar Malavali { 2317a9083016SGiridhar Malavali uint32_t drv_active; 2318a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2319a9083016SGiridhar Malavali 2320a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2321a9083016SGiridhar Malavali 2322a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2323a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 232477e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 232577e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2326a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2327a9083016SGiridhar Malavali } 232877e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2329a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2330a9083016SGiridhar Malavali } 2331a9083016SGiridhar Malavali 2332a9083016SGiridhar Malavali inline void 2333a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2334a9083016SGiridhar Malavali { 2335a9083016SGiridhar Malavali uint32_t drv_active; 2336a9083016SGiridhar Malavali 2337a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 233877e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2339a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2340a9083016SGiridhar Malavali } 2341a9083016SGiridhar Malavali 2342a9083016SGiridhar Malavali static inline int 2343a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2344a9083016SGiridhar Malavali { 2345a9083016SGiridhar Malavali uint32_t drv_state; 2346a9083016SGiridhar Malavali int rval; 2347a9083016SGiridhar Malavali 234808de2844SGiridhar Malavali if (ha->flags.isp82xx_reset_owner) 234908de2844SGiridhar Malavali return 1; 235008de2844SGiridhar Malavali else { 2351a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 235277e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2353a9083016SGiridhar Malavali return rval; 2354a9083016SGiridhar Malavali } 235508de2844SGiridhar Malavali } 2356a9083016SGiridhar Malavali 2357a9083016SGiridhar Malavali static inline void 2358a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2359a9083016SGiridhar Malavali { 2360a9083016SGiridhar Malavali uint32_t drv_state; 2361a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2362a9083016SGiridhar Malavali 2363a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2364a9083016SGiridhar Malavali 2365a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2366a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 236777e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2368a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2369a9083016SGiridhar Malavali } 2370a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 237108de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 237208de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2373a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2374a9083016SGiridhar Malavali } 2375a9083016SGiridhar Malavali 2376a9083016SGiridhar Malavali static inline void 2377a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2378a9083016SGiridhar Malavali { 2379a9083016SGiridhar Malavali uint32_t drv_state; 2380a9083016SGiridhar Malavali 2381a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2383a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2384a9083016SGiridhar Malavali } 2385a9083016SGiridhar Malavali 2386a9083016SGiridhar Malavali static inline void 2387a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2388a9083016SGiridhar Malavali { 2389a9083016SGiridhar Malavali uint32_t qsnt_state; 2390a9083016SGiridhar Malavali 2391a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2392a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2393a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2394a9083016SGiridhar Malavali } 2395a9083016SGiridhar Malavali 2396579d12b5SSaurav Kashyap void 2397579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2398579d12b5SSaurav Kashyap { 2399579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2400579d12b5SSaurav Kashyap uint32_t qsnt_state; 2401579d12b5SSaurav Kashyap 2402579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2403579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2404579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2405579d12b5SSaurav Kashyap } 2406579d12b5SSaurav Kashyap 240777e334d2SGiridhar Malavali static int 240877e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2409a9083016SGiridhar Malavali { 2410a9083016SGiridhar Malavali int rst; 2411a9083016SGiridhar Malavali struct fw_blob *blob; 2412a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2413a9083016SGiridhar Malavali 2414a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24157c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24167c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2417a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2418a9083016SGiridhar Malavali } 2419a9083016SGiridhar Malavali udelay(500); 2420a9083016SGiridhar Malavali 2421a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2422a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2423a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2424a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2425a9083016SGiridhar Malavali 2426a9083016SGiridhar Malavali /* 2427a9083016SGiridhar Malavali * FW Load priority: 2428a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2429a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2430a9083016SGiridhar Malavali */ 2431a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2432a9083016SGiridhar Malavali goto try_blob_fw; 2433a9083016SGiridhar Malavali 24347c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24357c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2436a9083016SGiridhar Malavali 2437a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24387c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 24397c3df132SSaurav Kashyap "Firmware loaded successully from flash.\n"); 2440a9083016SGiridhar Malavali return QLA_SUCCESS; 2441875efad7SChad Dupuis } else { 24427c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24437c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2444a9083016SGiridhar Malavali } 2445875efad7SChad Dupuis 2446a9083016SGiridhar Malavali try_blob_fw: 24477c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24487c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2449a9083016SGiridhar Malavali 2450a9083016SGiridhar Malavali /* Load firmware blob. */ 2451a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2452a9083016SGiridhar Malavali if (!blob) { 24537c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 24547c3df132SSaurav Kashyap "Firmware image not preset.\n"); 2455a9083016SGiridhar Malavali goto fw_load_failed; 2456a9083016SGiridhar Malavali } 2457a9083016SGiridhar Malavali 24589c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24599c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24609c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24619c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24629c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24639c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24647c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24657c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24669c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24679c2b2975SHarish Zunjarrao } 24689c2b2975SHarish Zunjarrao } 24699c2b2975SHarish Zunjarrao 2470a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24717c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24727c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2473a9083016SGiridhar Malavali return QLA_SUCCESS; 2474a9083016SGiridhar Malavali } else { 24757c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24767c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2477a9083016SGiridhar Malavali blob->fw = NULL; 2478a9083016SGiridhar Malavali blob = NULL; 2479a9083016SGiridhar Malavali goto fw_load_failed; 2480a9083016SGiridhar Malavali } 2481a9083016SGiridhar Malavali return QLA_SUCCESS; 2482a9083016SGiridhar Malavali 2483a9083016SGiridhar Malavali fw_load_failed: 2484a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2485a9083016SGiridhar Malavali } 2486a9083016SGiridhar Malavali 2487a5b36321SLalit Chandivade int 2488a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2489a9083016SGiridhar Malavali { 2490a9083016SGiridhar Malavali int pcie_cap; 2491a9083016SGiridhar Malavali uint16_t lnk; 2492a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2493a9083016SGiridhar Malavali 2494a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 249577e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2496a9083016SGiridhar Malavali 24973711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 24983711333dSGiridhar Malavali * of 0 before resetting the hardware 24993711333dSGiridhar Malavali */ 25003711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25013711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25023711333dSGiridhar Malavali 2503a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2504a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2505a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2506a9083016SGiridhar Malavali 2507a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25087c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25097c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2510a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2511a9083016SGiridhar Malavali } 2512a9083016SGiridhar Malavali 2513a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2514a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25157c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25167c3df132SSaurav Kashyap "Error during card handshake.\n"); 2517a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2518a9083016SGiridhar Malavali } 2519a9083016SGiridhar Malavali 2520a9083016SGiridhar Malavali /* Negotiated Link width */ 2521a9083016SGiridhar Malavali pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2522a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2523a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2524a9083016SGiridhar Malavali 2525a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2526a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2527a9083016SGiridhar Malavali } 2528a9083016SGiridhar Malavali 252977e334d2SGiridhar Malavali static uint32_t * 2530a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2531a9083016SGiridhar Malavali uint32_t length) 2532a9083016SGiridhar Malavali { 2533a9083016SGiridhar Malavali uint32_t i; 2534a9083016SGiridhar Malavali uint32_t val; 2535a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2536a9083016SGiridhar Malavali 2537a9083016SGiridhar Malavali /* Dword reads to flash. */ 2538a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2539a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25417c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2542a9083016SGiridhar Malavali goto done_read; 2543a9083016SGiridhar Malavali } 2544a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 2545a9083016SGiridhar Malavali } 2546a9083016SGiridhar Malavali done_read: 2547a9083016SGiridhar Malavali return dwptr; 2548a9083016SGiridhar Malavali } 2549a9083016SGiridhar Malavali 255077e334d2SGiridhar Malavali static int 2551a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2552a9083016SGiridhar Malavali { 2553a9083016SGiridhar Malavali int ret; 2554a9083016SGiridhar Malavali uint32_t val; 25557c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2556a9083016SGiridhar Malavali 2557a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2558a9083016SGiridhar Malavali if (ret < 0) { 25597c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25607c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2561a9083016SGiridhar Malavali return ret; 2562a9083016SGiridhar Malavali } 2563a9083016SGiridhar Malavali 2564a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2565a9083016SGiridhar Malavali if (ret < 0) 2566a9083016SGiridhar Malavali goto done_unprotect; 2567a9083016SGiridhar Malavali 25680547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2569a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2570a9083016SGiridhar Malavali if (ret < 0) { 25710547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2572a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2573a9083016SGiridhar Malavali } 2574a9083016SGiridhar Malavali 2575a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25767c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 25777c3df132SSaurav Kashyap "Write disable failed.\n"); 2578a9083016SGiridhar Malavali 2579a9083016SGiridhar Malavali done_unprotect: 2580d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2581a9083016SGiridhar Malavali return ret; 2582a9083016SGiridhar Malavali } 2583a9083016SGiridhar Malavali 258477e334d2SGiridhar Malavali static int 2585a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2586a9083016SGiridhar Malavali { 2587a9083016SGiridhar Malavali int ret; 2588a9083016SGiridhar Malavali uint32_t val; 25897c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2590a9083016SGiridhar Malavali 2591a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2592a9083016SGiridhar Malavali if (ret < 0) { 25937c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 25947c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2595a9083016SGiridhar Malavali return ret; 2596a9083016SGiridhar Malavali } 2597a9083016SGiridhar Malavali 2598a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2599a9083016SGiridhar Malavali if (ret < 0) 2600a9083016SGiridhar Malavali goto done_protect; 2601a9083016SGiridhar Malavali 26020547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2603a9083016SGiridhar Malavali /* LOCK all sectors */ 2604a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2605a9083016SGiridhar Malavali if (ret < 0) 26067c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 26077c3df132SSaurav Kashyap "Write status register failed.\n"); 2608a9083016SGiridhar Malavali 2609a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 26107c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 26117c3df132SSaurav Kashyap "Write disable failed.\n"); 2612a9083016SGiridhar Malavali done_protect: 2613d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2614a9083016SGiridhar Malavali return ret; 2615a9083016SGiridhar Malavali } 2616a9083016SGiridhar Malavali 261777e334d2SGiridhar Malavali static int 2618a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2619a9083016SGiridhar Malavali { 2620a9083016SGiridhar Malavali int ret = 0; 26217c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2622a9083016SGiridhar Malavali 2623a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2624a9083016SGiridhar Malavali if (ret < 0) { 26257c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26267c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2627a9083016SGiridhar Malavali return ret; 2628a9083016SGiridhar Malavali } 2629a9083016SGiridhar Malavali 2630a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2631a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2632a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2633a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2634a9083016SGiridhar Malavali 2635a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26367c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26377c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2638a9083016SGiridhar Malavali ret = -1; 2639a9083016SGiridhar Malavali goto done; 2640a9083016SGiridhar Malavali } 2641a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2642a9083016SGiridhar Malavali done: 2643d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2644a9083016SGiridhar Malavali return ret; 2645a9083016SGiridhar Malavali } 2646a9083016SGiridhar Malavali 2647a9083016SGiridhar Malavali /* 2648a9083016SGiridhar Malavali * Address and length are byte address 2649a9083016SGiridhar Malavali */ 2650a9083016SGiridhar Malavali uint8_t * 2651a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2652a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2653a9083016SGiridhar Malavali { 2654a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2655a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2656a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2657a9083016SGiridhar Malavali return buf; 2658a9083016SGiridhar Malavali } 2659a9083016SGiridhar Malavali 2660a9083016SGiridhar Malavali static int 2661a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2662a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2663a9083016SGiridhar Malavali { 2664a9083016SGiridhar Malavali int ret; 2665a9083016SGiridhar Malavali uint32_t liter; 2666a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 2667a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2668a9083016SGiridhar Malavali void *optrom = NULL; 2669a9083016SGiridhar Malavali int page_mode = 0; 2670a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2671a9083016SGiridhar Malavali 2672a9083016SGiridhar Malavali ret = -1; 2673a9083016SGiridhar Malavali 2674a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2675a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2676a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2677a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2678a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2679a9083016SGiridhar Malavali if (!optrom) { 26807c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 26817c3df132SSaurav Kashyap "Unable to allocate memory " 26827c3df132SSaurav Kashyap "for optron burst write (%x KB).\n", 2683a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2684a9083016SGiridhar Malavali } 2685a9083016SGiridhar Malavali } 2686a9083016SGiridhar Malavali 2687a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2688a9083016SGiridhar Malavali sec_mask = ~rest_addr; 2689a9083016SGiridhar Malavali 2690a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2691a9083016SGiridhar Malavali if (ret) { 26927c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2693a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2694a9083016SGiridhar Malavali goto write_done; 2695a9083016SGiridhar Malavali } 2696a9083016SGiridhar Malavali 2697a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2698a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2699a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2700a9083016SGiridhar Malavali 2701a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2702a9083016SGiridhar Malavali if (ret) { 27037c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 27047c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 27057c3df132SSaurav Kashyap faddr); 2706a9083016SGiridhar Malavali break; 2707a9083016SGiridhar Malavali } 2708a9083016SGiridhar Malavali } 2709a9083016SGiridhar Malavali 2710a9083016SGiridhar Malavali /* Go with burst-write. */ 2711a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2712a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2713a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2714a9083016SGiridhar Malavali 2715a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2716a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2717a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2718a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 27197c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2720a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2721a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2722a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2723a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27247c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2725a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2726a9083016SGiridhar Malavali 2727a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2728a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2729a9083016SGiridhar Malavali optrom = NULL; 2730a9083016SGiridhar Malavali } else { 2731a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2732a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2733a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2734a9083016SGiridhar Malavali continue; 2735a9083016SGiridhar Malavali } 2736a9083016SGiridhar Malavali } 2737a9083016SGiridhar Malavali 2738a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 2739a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 2740a9083016SGiridhar Malavali if (ret) { 27417c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27427c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27437c3df132SSaurav Kashyap faddr, *dwptr); 2744a9083016SGiridhar Malavali break; 2745a9083016SGiridhar Malavali } 2746a9083016SGiridhar Malavali } 2747a9083016SGiridhar Malavali 2748a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2749a9083016SGiridhar Malavali if (ret) 27507c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2751a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2752a9083016SGiridhar Malavali write_done: 2753a9083016SGiridhar Malavali if (optrom) 2754a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2755a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2756a9083016SGiridhar Malavali return ret; 2757a9083016SGiridhar Malavali } 2758a9083016SGiridhar Malavali 2759a9083016SGiridhar Malavali int 2760a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2761a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2762a9083016SGiridhar Malavali { 2763a9083016SGiridhar Malavali int rval; 2764a9083016SGiridhar Malavali 2765a9083016SGiridhar Malavali /* Suspend HBA. */ 2766a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2767a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2768a9083016SGiridhar Malavali length >> 2); 2769a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2770a9083016SGiridhar Malavali 2771a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2772a9083016SGiridhar Malavali if (rval) 2773a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2774a9083016SGiridhar Malavali else 2775a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2776a9083016SGiridhar Malavali return rval; 2777a9083016SGiridhar Malavali } 2778a9083016SGiridhar Malavali 2779a9083016SGiridhar Malavali void 27805162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2781a9083016SGiridhar Malavali { 27825162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2783a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2784a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2785a9083016SGiridhar Malavali uint32_t dbval; 2786a9083016SGiridhar Malavali 2787a9083016SGiridhar Malavali /* Adjust ring index. */ 2788a9083016SGiridhar Malavali req->ring_index++; 2789a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2790a9083016SGiridhar Malavali req->ring_index = 0; 2791a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2792a9083016SGiridhar Malavali } else 2793a9083016SGiridhar Malavali req->ring_ptr++; 2794a9083016SGiridhar Malavali 2795a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2796a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2797a9083016SGiridhar Malavali 2798a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 27996907869dSGiridhar Malavali if (ql2xdbwr) 28006907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 28016907869dSGiridhar Malavali else { 2802a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2803a9083016SGiridhar Malavali wmb(); 2804a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 28056907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 28066907869dSGiridhar Malavali dbval); 2807a9083016SGiridhar Malavali wmb(); 2808a9083016SGiridhar Malavali } 2809a9083016SGiridhar Malavali } 28106907869dSGiridhar Malavali } 2811a9083016SGiridhar Malavali 2812e6a4202aSShyam Sundar void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2813e6a4202aSShyam Sundar { 28147c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 28157c3df132SSaurav Kashyap 2816e6a4202aSShyam Sundar if (qla82xx_rom_lock(ha)) 2817e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 28187c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 28197c3df132SSaurav Kashyap "Resetting rom_lock.\n"); 2820e6a4202aSShyam Sundar 2821e6a4202aSShyam Sundar /* 2822e6a4202aSShyam Sundar * Either we got the lock, or someone 2823e6a4202aSShyam Sundar * else died while holding it. 2824e6a4202aSShyam Sundar * In either case, unlock. 2825e6a4202aSShyam Sundar */ 2826d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2827e6a4202aSShyam Sundar } 2828e6a4202aSShyam Sundar 2829a9083016SGiridhar Malavali /* 2830a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2831a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2832a9083016SGiridhar Malavali * 2833a9083016SGiridhar Malavali * Note: 2834a9083016SGiridhar Malavali * IDC lock must be held upon entry 2835a9083016SGiridhar Malavali * 2836a9083016SGiridhar Malavali * Return: 2837a9083016SGiridhar Malavali * Success : 0 2838a9083016SGiridhar Malavali * Failed : 1 2839a9083016SGiridhar Malavali */ 2840a9083016SGiridhar Malavali static int 2841a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2842a9083016SGiridhar Malavali { 2843e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 2844e6a4202aSShyam Sundar int i, timeout; 2845a9083016SGiridhar Malavali uint32_t old_count, count; 2846a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2847e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 2848a9083016SGiridhar Malavali 2849e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2850a9083016SGiridhar Malavali 2851a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2852a9083016SGiridhar Malavali 2853a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 2854a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 2855a9083016SGiridhar Malavali if (timeout) { 2856a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2857a9083016SGiridhar Malavali QLA82XX_DEV_FAILED); 2858a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2859a9083016SGiridhar Malavali } 2860a9083016SGiridhar Malavali 2861a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2862a9083016SGiridhar Malavali if (count != old_count) 2863e6a4202aSShyam Sundar peg_stuck = 0; 2864e6a4202aSShyam Sundar } 2865e6a4202aSShyam Sundar 2866e6a4202aSShyam Sundar if (need_reset) { 2867e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 2868e6a4202aSShyam Sundar if (peg_stuck) 2869e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2870e6a4202aSShyam Sundar goto dev_initialize; 2871e6a4202aSShyam Sundar } else { 2872e6a4202aSShyam Sundar /* Start of day for this ha context. */ 2873e6a4202aSShyam Sundar if (peg_stuck) { 2874e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 2875e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2876e6a4202aSShyam Sundar goto dev_initialize; 2877e6a4202aSShyam Sundar } else 2878e6a4202aSShyam Sundar /* Firmware already running. */ 2879a9083016SGiridhar Malavali goto dev_ready; 2880a9083016SGiridhar Malavali } 2881a9083016SGiridhar Malavali 2882e6a4202aSShyam Sundar return rval; 2883e6a4202aSShyam Sundar 2884a9083016SGiridhar Malavali dev_initialize: 2885a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28867c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28877c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 2888a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2889a9083016SGiridhar Malavali 2890a9083016SGiridhar Malavali /* Driver that sets device state to initializating sets IDC version */ 2891a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2892a9083016SGiridhar Malavali 2893a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2894a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2895a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2896a9083016SGiridhar Malavali 2897a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 28987c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 28997c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2900a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 2901a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2902a9083016SGiridhar Malavali return rval; 2903a9083016SGiridhar Malavali } 2904a9083016SGiridhar Malavali 2905a9083016SGiridhar Malavali dev_ready: 29067c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 29077c3df132SSaurav Kashyap "HW State: READY.\n"); 2908a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2909a9083016SGiridhar Malavali 2910a9083016SGiridhar Malavali return QLA_SUCCESS; 2911a9083016SGiridhar Malavali } 2912a9083016SGiridhar Malavali 2913579d12b5SSaurav Kashyap /* 2914579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2915579d12b5SSaurav Kashyap * Code to start quiescence sequence 2916579d12b5SSaurav Kashyap * 2917579d12b5SSaurav Kashyap * Note: 2918579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2919579d12b5SSaurav Kashyap * 2920579d12b5SSaurav Kashyap * Return: void 2921579d12b5SSaurav Kashyap */ 2922579d12b5SSaurav Kashyap 2923579d12b5SSaurav Kashyap static void 2924579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2925579d12b5SSaurav Kashyap { 2926579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2927579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2928579d12b5SSaurav Kashyap unsigned long reset_timeout; 2929579d12b5SSaurav Kashyap 2930579d12b5SSaurav Kashyap if (vha->flags.online) { 2931579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 2932579d12b5SSaurav Kashyap qla82xx_quiescent_state_cleanup(vha); 2933579d12b5SSaurav Kashyap } 2934579d12b5SSaurav Kashyap 2935579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2936579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2937579d12b5SSaurav Kashyap 2938579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2939579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2940579d12b5SSaurav Kashyap 2941579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2942579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2943579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2944579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2945579d12b5SSaurav Kashyap 2946579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2947579d12b5SSaurav Kashyap 2948579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2949579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2950579d12b5SSaurav Kashyap * changing the state to DEV_READY 2951579d12b5SSaurav Kashyap */ 29527c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29537c3df132SSaurav Kashyap "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 29547c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb024, 29557c3df132SSaurav Kashyap "DRV_ACTIVE:%d DRV_STATE:%d.\n", 29567c3df132SSaurav Kashyap drv_active, drv_state); 2957579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2958579d12b5SSaurav Kashyap QLA82XX_DEV_READY); 29597c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29607c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2961579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2962579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2963579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2964579d12b5SSaurav Kashyap 2965579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2966579d12b5SSaurav Kashyap return; 2967579d12b5SSaurav Kashyap } 2968579d12b5SSaurav Kashyap 2969579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2970579d12b5SSaurav Kashyap msleep(1000); 2971579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2972579d12b5SSaurav Kashyap 2973579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2974579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2975579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2976579d12b5SSaurav Kashyap } 2977579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2978579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 2979579d12b5SSaurav Kashyap if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 29807c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29817c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 2982579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 2983579d12b5SSaurav Kashyap } 2984579d12b5SSaurav Kashyap } 2985579d12b5SSaurav Kashyap 2986579d12b5SSaurav Kashyap /* 2987579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2988579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2989579d12b5SSaurav Kashyap * 2990579d12b5SSaurav Kashyap * Note: 2991579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2992579d12b5SSaurav Kashyap * 2993579d12b5SSaurav Kashyap * Return: 2994579d12b5SSaurav Kashyap * Changed device state. 2995579d12b5SSaurav Kashyap */ 2996579d12b5SSaurav Kashyap uint32_t 2997579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2998579d12b5SSaurav Kashyap { 2999579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3000579d12b5SSaurav Kashyap uint32_t dev_state; 3001579d12b5SSaurav Kashyap 3002579d12b5SSaurav Kashyap do { 3003579d12b5SSaurav Kashyap msleep(1000); 3004579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3005579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3006579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3007579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3008579d12b5SSaurav Kashyap 3009579d12b5SSaurav Kashyap return dev_state; 3010579d12b5SSaurav Kashyap } 3011579d12b5SSaurav Kashyap 3012a9083016SGiridhar Malavali static void 3013a9083016SGiridhar Malavali qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3014a9083016SGiridhar Malavali { 3015a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3016a9083016SGiridhar Malavali 3017a9083016SGiridhar Malavali /* Disable the board */ 30187c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 30197c3df132SSaurav Kashyap "Disabling the board.\n"); 3020a9083016SGiridhar Malavali 3021b963752fSGiridhar Malavali qla82xx_idc_lock(ha); 3022b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3023b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 3024b963752fSGiridhar Malavali 3025a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3026a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3027a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3028a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3029a9083016SGiridhar Malavali vha->flags.online = 0; 3030a9083016SGiridhar Malavali vha->flags.init_done = 0; 3031a9083016SGiridhar Malavali } 3032a9083016SGiridhar Malavali 3033a9083016SGiridhar Malavali /* 3034a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3035a9083016SGiridhar Malavali * Code to start reset sequence 3036a9083016SGiridhar Malavali * 3037a9083016SGiridhar Malavali * Note: 3038a9083016SGiridhar Malavali * IDC lock must be held upon entry 3039a9083016SGiridhar Malavali * 3040a9083016SGiridhar Malavali * Return: 3041a9083016SGiridhar Malavali * Success : 0 3042a9083016SGiridhar Malavali * Failed : 1 3043a9083016SGiridhar Malavali */ 3044a9083016SGiridhar Malavali static void 3045a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3046a9083016SGiridhar Malavali { 3047e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3048e5fdae55SChad Dupuis uint32_t active_mask = 0; 3049a9083016SGiridhar Malavali unsigned long reset_timeout; 3050a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3051a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3052a9083016SGiridhar Malavali 3053a9083016SGiridhar Malavali if (vha->flags.online) { 3054a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3055a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3056a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3057a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3058a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3059a9083016SGiridhar Malavali } 3060a9083016SGiridhar Malavali 306108de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 306208de2844SGiridhar Malavali if (!ha->flags.isp82xx_reset_owner) { 306308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 306408de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3065a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 306608de2844SGiridhar Malavali } else { 306708de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 306808de2844SGiridhar Malavali drv_active &= active_mask; 306908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 307008de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 307108de2844SGiridhar Malavali } 3072a9083016SGiridhar Malavali 3073a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 3074a9083016SGiridhar Malavali reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3075a9083016SGiridhar Malavali 3076a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3077a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 307808de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3079a9083016SGiridhar Malavali 308008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 308108de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 308208de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 308308de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 308408de2844SGiridhar Malavali 308508de2844SGiridhar Malavali while (drv_state != drv_active && 308608de2844SGiridhar Malavali dev_state != QLA82XX_DEV_INITIALIZING) { 3087a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30897c3df132SSaurav Kashyap "Reset timeout.\n"); 3090a9083016SGiridhar Malavali break; 3091a9083016SGiridhar Malavali } 3092a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3093a9083016SGiridhar Malavali msleep(1000); 3094a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3095a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3096a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 309708de2844SGiridhar Malavali if (ha->flags.isp82xx_reset_owner) 309808de2844SGiridhar Malavali drv_active &= active_mask; 309908de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3100a9083016SGiridhar Malavali } 3101a9083016SGiridhar Malavali 310208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 310308de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 310408de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 310508de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 310608de2844SGiridhar Malavali 31077c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 31087c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 31097c3df132SSaurav Kashyap dev_state, 311008de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3111f1af6208SGiridhar Malavali 3112a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 311308de2844SGiridhar Malavali if (dev_state != QLA82XX_DEV_INITIALIZING && 311408de2844SGiridhar Malavali dev_state != QLA82XX_DEV_COLD) { 31157c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 31167c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 3117a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 311808de2844SGiridhar Malavali if (ql2xmdenable) { 311908de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 312008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 312108de2844SGiridhar Malavali "Not able to collect minidump.\n"); 312208de2844SGiridhar Malavali } else 312308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 312408de2844SGiridhar Malavali "Minidump disabled.\n"); 3125a9083016SGiridhar Malavali } 3126a9083016SGiridhar Malavali } 3127a9083016SGiridhar Malavali 31283173167fSGiridhar Malavali int 312908de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 313008de2844SGiridhar Malavali { 313108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 313208de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 31333173167fSGiridhar Malavali int rval = QLA_SUCCESS; 313408de2844SGiridhar Malavali 31353173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 31363173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 31373173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 31383173167fSGiridhar Malavali 31396246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31403173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31413173167fSGiridhar Malavali return rval; 31423173167fSGiridhar Malavali 31433173167fSGiridhar Malavali if (ql2xmdenable) { 314408de2844SGiridhar Malavali if (!ha->fw_dumped) { 314508de2844SGiridhar Malavali if (fw_major_version != ha->fw_major_version || 314608de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 314708de2844SGiridhar Malavali fw_subminor_version != ha->fw_subminor_version) { 314808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02d, 314908de2844SGiridhar Malavali "Firmware version differs " 315008de2844SGiridhar Malavali "Previous version: %d:%d:%d - " 315108de2844SGiridhar Malavali "New version: %d:%d:%d\n", 315208de2844SGiridhar Malavali ha->fw_major_version, 31533173167fSGiridhar Malavali ha->fw_minor_version, 31543173167fSGiridhar Malavali ha->fw_subminor_version, 315508de2844SGiridhar Malavali fw_major_version, fw_minor_version, 315608de2844SGiridhar Malavali fw_subminor_version); 315708de2844SGiridhar Malavali /* Release MiniDump resources */ 315808de2844SGiridhar Malavali qla82xx_md_free(vha); 315908de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 316008de2844SGiridhar Malavali qla82xx_md_prep(vha); 31612e264269SGiridhar Malavali } 316208de2844SGiridhar Malavali } else 316308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3164d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 316508de2844SGiridhar Malavali } 31663173167fSGiridhar Malavali return rval; 31673173167fSGiridhar Malavali } 316808de2844SGiridhar Malavali 316908de2844SGiridhar Malavali 31707190575fSGiridhar Malavali int 3171a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3172a9083016SGiridhar Malavali { 31737190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31747190575fSGiridhar Malavali int status = 0; 3175a9083016SGiridhar Malavali 31767190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31777190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3178a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31797c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31807c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31817c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31827c3df132SSaurav Kashyap "returning status=%d.\n", status); 31837190575fSGiridhar Malavali return status; 31847c3df132SSaurav Kashyap } 3185a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3186a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3187a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3188a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3189a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31907190575fSGiridhar Malavali status = 1; 3191a9083016SGiridhar Malavali } 3192efa786ccSLalit Chandivade } else 3193efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3194a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 31957c3df132SSaurav Kashyap if (status) 31967c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 31977c3df132SSaurav Kashyap "Returning status=%d.\n", status); 31987190575fSGiridhar Malavali return status; 3199a9083016SGiridhar Malavali } 3200a9083016SGiridhar Malavali 3201a9083016SGiridhar Malavali /* 3202a9083016SGiridhar Malavali * qla82xx_device_state_handler 3203a9083016SGiridhar Malavali * Main state handler 3204a9083016SGiridhar Malavali * 3205a9083016SGiridhar Malavali * Note: 3206a9083016SGiridhar Malavali * IDC lock must be held upon entry 3207a9083016SGiridhar Malavali * 3208a9083016SGiridhar Malavali * Return: 3209a9083016SGiridhar Malavali * Success : 0 3210a9083016SGiridhar Malavali * Failed : 1 3211a9083016SGiridhar Malavali */ 3212a9083016SGiridhar Malavali int 3213a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3214a9083016SGiridhar Malavali { 3215a9083016SGiridhar Malavali uint32_t dev_state; 321692dbf273SGiridhar Malavali uint32_t old_dev_state; 3217a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3218a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3219a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 322092dbf273SGiridhar Malavali int loopcount = 0; 3221a9083016SGiridhar Malavali 3222a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3223a9083016SGiridhar Malavali if (!vha->flags.init_done) 3224a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 3225a9083016SGiridhar Malavali 3226a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 322792dbf273SGiridhar Malavali old_dev_state = dev_state; 32287c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 32297c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32307c3df132SSaurav Kashyap dev_state, 323108de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3232a9083016SGiridhar Malavali 3233a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 3234a9083016SGiridhar Malavali dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3235a9083016SGiridhar Malavali 3236a9083016SGiridhar Malavali while (1) { 3237a9083016SGiridhar Malavali 3238a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32397c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32407c3df132SSaurav Kashyap "Device init failed.\n"); 3241a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3242a9083016SGiridhar Malavali break; 3243a9083016SGiridhar Malavali } 3244a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 324592dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 324692dbf273SGiridhar Malavali loopcount = 0; 324792dbf273SGiridhar Malavali old_dev_state = dev_state; 324892dbf273SGiridhar Malavali } 324992dbf273SGiridhar Malavali if (loopcount < 5) { 32507c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32517c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32527c3df132SSaurav Kashyap dev_state, 325308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32547c3df132SSaurav Kashyap "Unknown"); 325592dbf273SGiridhar Malavali } 3256f1af6208SGiridhar Malavali 3257a9083016SGiridhar Malavali switch (dev_state) { 3258a9083016SGiridhar Malavali case QLA82XX_DEV_READY: 325908de2844SGiridhar Malavali ha->flags.isp82xx_reset_owner = 0; 3260a9083016SGiridhar Malavali goto exit; 3261a9083016SGiridhar Malavali case QLA82XX_DEV_COLD: 3262a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 326308de2844SGiridhar Malavali break; 3264a9083016SGiridhar Malavali case QLA82XX_DEV_INITIALIZING: 3265a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3266a9083016SGiridhar Malavali msleep(1000); 3267a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3268a9083016SGiridhar Malavali break; 3269a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_RESET: 3270ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3271a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3272c8582ad9SSaurav Kashyap else { 3273c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3274c8582ad9SSaurav Kashyap msleep(1000); 3275c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3276c8582ad9SSaurav Kashyap } 32770060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32780060ddf8SGiridhar Malavali (ha->nx_dev_init_timeout * HZ); 3279a9083016SGiridhar Malavali break; 3280a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_QUIESCENT: 3281579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3282579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3283579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3284579d12b5SSaurav Kashyap * HZ); 3285579d12b5SSaurav Kashyap break; 3286a9083016SGiridhar Malavali case QLA82XX_DEV_QUIESCENT: 3287579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3288579d12b5SSaurav Kashyap * to get changed 3289579d12b5SSaurav Kashyap */ 3290579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 3291579d12b5SSaurav Kashyap goto exit; 3292579d12b5SSaurav Kashyap 3293a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3294a9083016SGiridhar Malavali msleep(1000); 3295a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3296579d12b5SSaurav Kashyap 3297579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3298579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3299579d12b5SSaurav Kashyap * HZ); 3300a9083016SGiridhar Malavali break; 3301a9083016SGiridhar Malavali case QLA82XX_DEV_FAILED: 3302a9083016SGiridhar Malavali qla82xx_dev_failed_handler(vha); 3303a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3304a9083016SGiridhar Malavali goto exit; 3305a9083016SGiridhar Malavali default: 3306a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3307a9083016SGiridhar Malavali msleep(1000); 3308a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3309a9083016SGiridhar Malavali } 331092dbf273SGiridhar Malavali loopcount++; 3311a9083016SGiridhar Malavali } 3312a9083016SGiridhar Malavali exit: 3313a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3314a9083016SGiridhar Malavali return rval; 3315a9083016SGiridhar Malavali } 3316a9083016SGiridhar Malavali 3317c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3318c8f6544eSChad Dupuis { 3319c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3320c8f6544eSChad Dupuis 3321c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3322c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33238937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3324c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3325c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 3326c8f6544eSChad Dupuis if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3327c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3328c8f6544eSChad Dupuis } 3329c8f6544eSChad Dupuis } 3330c8f6544eSChad Dupuis 3331a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3332a9083016SGiridhar Malavali { 33337190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3334a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3335a9083016SGiridhar Malavali 3336a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33377190575fSGiridhar Malavali if (!ha->flags.isp82xx_reset_hdlr_active) { 33387190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33397190575fSGiridhar Malavali if (dev_state == QLA82XX_DEV_NEED_RESET && 33407190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33417c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33427c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3343a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3344a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3345579d12b5SSaurav Kashyap } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3346579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33477c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33487c3df132SSaurav Kashyap "Quiescent needed.\n"); 3349579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3350579d12b5SSaurav Kashyap qla2xxx_wake_dpc(vha); 3351a9083016SGiridhar Malavali } else { 33527190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 335363154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 335463154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 335563154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 335663154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 33577190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 33587190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 335963154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 33607c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 33617c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 33627c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 33637c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 33647c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 33650e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 33660e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33670e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 33680e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33690e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 33700e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33710e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 33720e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33730e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 33740e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33750e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 33762cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 337710a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 337810a340e6SChad Dupuis "Firmware aborted with " 337910a340e6SChad Dupuis "error code 0x00006700. Device is " 338010a340e6SChad Dupuis "being reset.\n"); 33817190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 33827190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 33837190575fSGiridhar Malavali &vha->dpc_flags); 33847190575fSGiridhar Malavali } else { 33857c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 33867c3df132SSaurav Kashyap "Detect abort needed.\n"); 33877190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 33887190575fSGiridhar Malavali &vha->dpc_flags); 33897190575fSGiridhar Malavali } 33907190575fSGiridhar Malavali qla2xxx_wake_dpc(vha); 33917190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3392c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3393c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 33947190575fSGiridhar Malavali } 3395a9083016SGiridhar Malavali } 3396a9083016SGiridhar Malavali } 3397a9083016SGiridhar Malavali } 3398a9083016SGiridhar Malavali 3399a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3400a9083016SGiridhar Malavali { 3401a9083016SGiridhar Malavali int rval; 3402a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3403a9083016SGiridhar Malavali return rval; 3404a9083016SGiridhar Malavali } 3405a9083016SGiridhar Malavali 340608de2844SGiridhar Malavali void 340708de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 340808de2844SGiridhar Malavali { 340908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 341008de2844SGiridhar Malavali uint32_t dev_state; 341108de2844SGiridhar Malavali 341208de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 341308de2844SGiridhar Malavali if (dev_state == QLA82XX_DEV_READY) { 341408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 341508de2844SGiridhar Malavali "HW State: NEED RESET\n"); 341608de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 341708de2844SGiridhar Malavali QLA82XX_DEV_NEED_RESET); 341808de2844SGiridhar Malavali ha->flags.isp82xx_reset_owner = 1; 341908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 342008de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 342108de2844SGiridhar Malavali } else 342208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 342308de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 342408de2844SGiridhar Malavali dev_state, 342508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 342608de2844SGiridhar Malavali } 342708de2844SGiridhar Malavali 3428a9083016SGiridhar Malavali /* 3429a9083016SGiridhar Malavali * qla82xx_abort_isp 3430a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3431a9083016SGiridhar Malavali * 3432a9083016SGiridhar Malavali * Input: 3433a9083016SGiridhar Malavali * ha = adapter block pointer. 3434a9083016SGiridhar Malavali * 3435a9083016SGiridhar Malavali * Returns: 3436a9083016SGiridhar Malavali * 0 = success 3437a9083016SGiridhar Malavali */ 3438a9083016SGiridhar Malavali int 3439a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3440a9083016SGiridhar Malavali { 3441a9083016SGiridhar Malavali int rval; 3442a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3443a9083016SGiridhar Malavali 3444a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 34457c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 34467c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3447a9083016SGiridhar Malavali return QLA_SUCCESS; 3448a9083016SGiridhar Malavali } 34497190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 1; 3450a9083016SGiridhar Malavali 3451a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 345208de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3453a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3454a9083016SGiridhar Malavali 3455a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3456a9083016SGiridhar Malavali 3457a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3458a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3459a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3460a9083016SGiridhar Malavali 3461cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 34627190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 34637190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 0; 3464a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3465cdbb0a4fSSantosh Vernekar } 3466f1af6208SGiridhar Malavali 3467f1af6208SGiridhar Malavali if (rval) { 3468f1af6208SGiridhar Malavali vha->flags.online = 1; 3469f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3470f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 34717c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 34727c3df132SSaurav Kashyap "ISP error recover failed - board " 34737c3df132SSaurav Kashyap "disabled.\n"); 3474f1af6208SGiridhar Malavali /* 3475f1af6208SGiridhar Malavali * The next call disables the board 3476f1af6208SGiridhar Malavali * completely. 3477f1af6208SGiridhar Malavali */ 3478f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3479f1af6208SGiridhar Malavali vha->flags.online = 0; 3480f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3481f1af6208SGiridhar Malavali &vha->dpc_flags); 3482f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3483f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3484f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 34857c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 34867c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 34877c3df132SSaurav Kashyap ha->isp_abort_cnt); 3488f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3489f1af6208SGiridhar Malavali } 3490f1af6208SGiridhar Malavali } else { 3491f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 34927c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 34937c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 34947c3df132SSaurav Kashyap ha->isp_abort_cnt); 3495f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3496f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3497f1af6208SGiridhar Malavali } 3498f1af6208SGiridhar Malavali } 3499a9083016SGiridhar Malavali return rval; 3500a9083016SGiridhar Malavali } 3501a9083016SGiridhar Malavali 3502a9083016SGiridhar Malavali /* 3503a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3504a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3505a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3506a9083016SGiridhar Malavali * chip reset. 3507a9083016SGiridhar Malavali * 3508a9083016SGiridhar Malavali * Input: 3509a9083016SGiridhar Malavali * ha = adapter block pointer. 3510a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3511a9083016SGiridhar Malavali * 3512a9083016SGiridhar Malavali * Returns: 3513a9083016SGiridhar Malavali * 0 = success 3514a9083016SGiridhar Malavali */ 3515a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3516a9083016SGiridhar Malavali { 3517a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3518a9083016SGiridhar Malavali 3519a9083016SGiridhar Malavali if (vha->flags.online) { 3520a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3521a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3522a9083016SGiridhar Malavali } 3523a9083016SGiridhar Malavali 3524a9083016SGiridhar Malavali /* Stop currently executing firmware. 3525a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3526a9083016SGiridhar Malavali */ 3527a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3528a9083016SGiridhar Malavali 3529a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3530a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3531a9083016SGiridhar Malavali 3532a9083016SGiridhar Malavali return rval; 3533a9083016SGiridhar Malavali } 3534a9083016SGiridhar Malavali 3535a9083016SGiridhar Malavali /* 3536a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3537a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3538a9083016SGiridhar Malavali * 3539a9083016SGiridhar Malavali * Note: 3540a9083016SGiridhar Malavali * Does context switching here. 3541a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3542a9083016SGiridhar Malavali * 3543a9083016SGiridhar Malavali * Return: 3544a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3545a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3546a9083016SGiridhar Malavali */ 3547a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3548a9083016SGiridhar Malavali { 3549a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3550a9083016SGiridhar Malavali unsigned long wait_reset; 3551a9083016SGiridhar Malavali 3552a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3553a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3554a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3555a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3556a9083016SGiridhar Malavali 3557a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3558a9083016SGiridhar Malavali schedule_timeout(HZ); 3559a9083016SGiridhar Malavali 3560a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3561a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3562a9083016SGiridhar Malavali status = QLA_SUCCESS; 3563a9083016SGiridhar Malavali break; 3564a9083016SGiridhar Malavali } 3565a9083016SGiridhar Malavali } 35667c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3567d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3568a9083016SGiridhar Malavali 3569a9083016SGiridhar Malavali return status; 3570a9083016SGiridhar Malavali } 35717190575fSGiridhar Malavali 35727190575fSGiridhar Malavali void 35737190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 35747190575fSGiridhar Malavali { 35757190575fSGiridhar Malavali int i; 35767190575fSGiridhar Malavali unsigned long flags; 35777190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 35787190575fSGiridhar Malavali 35797190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 35807190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 35817190575fSGiridhar Malavali * detection only 35827190575fSGiridhar Malavali */ 35837190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 35847190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 35857190575fSGiridhar Malavali msleep(1000); 35867190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 35877190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3588c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 35897190575fSGiridhar Malavali break; 35907190575fSGiridhar Malavali } 35917190575fSGiridhar Malavali } 35927190575fSGiridhar Malavali } 35937c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 35947c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 35957c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 35967190575fSGiridhar Malavali 35977190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 35987190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 35997190575fSGiridhar Malavali int cnt, que; 36007190575fSGiridhar Malavali srb_t *sp; 36017190575fSGiridhar Malavali struct req_que *req; 36027190575fSGiridhar Malavali 36037190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36047190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36057190575fSGiridhar Malavali req = ha->req_q_map[que]; 36067190575fSGiridhar Malavali if (!req) 36077190575fSGiridhar Malavali continue; 36087190575fSGiridhar Malavali for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 36097190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36107190575fSGiridhar Malavali if (sp) { 36117190575fSGiridhar Malavali if (!sp->ctx || 36127190575fSGiridhar Malavali (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 36137190575fSGiridhar Malavali spin_unlock_irqrestore( 36147190575fSGiridhar Malavali &ha->hardware_lock, flags); 36157190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 36167c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36177c3df132SSaurav Kashyap 0x00b1, 36187c3df132SSaurav Kashyap "mbx abort failed.\n"); 36197190575fSGiridhar Malavali } else { 36207c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36217c3df132SSaurav Kashyap 0x00b2, 36227c3df132SSaurav Kashyap "mbx abort success.\n"); 36237190575fSGiridhar Malavali } 36247190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36257190575fSGiridhar Malavali } 36267190575fSGiridhar Malavali } 36277190575fSGiridhar Malavali } 36287190575fSGiridhar Malavali } 36297190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 36307190575fSGiridhar Malavali 36317190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 36327190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 36337190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 36347c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 36357c3df132SSaurav Kashyap "Done wait for " 36367c3df132SSaurav Kashyap "pending commands.\n"); 36377190575fSGiridhar Malavali } 36387190575fSGiridhar Malavali } 36397190575fSGiridhar Malavali } 364008de2844SGiridhar Malavali 364108de2844SGiridhar Malavali /* Minidump related functions */ 364208de2844SGiridhar Malavali int 364308de2844SGiridhar Malavali qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 364408de2844SGiridhar Malavali { 364508de2844SGiridhar Malavali uint32_t off_value, rval = 0; 364608de2844SGiridhar Malavali 364708de2844SGiridhar Malavali WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 364808de2844SGiridhar Malavali (off & 0xFFFF0000)); 364908de2844SGiridhar Malavali 365008de2844SGiridhar Malavali /* Read back value to make sure write has gone through */ 365108de2844SGiridhar Malavali RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 365208de2844SGiridhar Malavali off_value = (off & 0x0000FFFF); 365308de2844SGiridhar Malavali 365408de2844SGiridhar Malavali if (flag) 365508de2844SGiridhar Malavali WRT_REG_DWORD((void *) 365608de2844SGiridhar Malavali (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 365708de2844SGiridhar Malavali data); 365808de2844SGiridhar Malavali else 365908de2844SGiridhar Malavali rval = RD_REG_DWORD((void *) 366008de2844SGiridhar Malavali (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 366108de2844SGiridhar Malavali 366208de2844SGiridhar Malavali return rval; 366308de2844SGiridhar Malavali } 366408de2844SGiridhar Malavali 366508de2844SGiridhar Malavali static int 366608de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 366708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 366808de2844SGiridhar Malavali { 366908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 367008de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 367108de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 367208de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 367308de2844SGiridhar Malavali unsigned long wtime; 367408de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 367508de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 367608de2844SGiridhar Malavali int i; 367708de2844SGiridhar Malavali 367808de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 367908de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 368008de2844SGiridhar Malavali crb_addr = crb_entry->addr; 368108de2844SGiridhar Malavali 368208de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 368308de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 368408de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 368508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 368608de2844SGiridhar Malavali crb_entry->value_1, 1); 368708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 368808de2844SGiridhar Malavali } 368908de2844SGiridhar Malavali 369008de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 369108de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 369208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 369308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 369408de2844SGiridhar Malavali } 369508de2844SGiridhar Malavali 369608de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 369708de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 369808de2844SGiridhar Malavali read_value &= crb_entry->value_2; 369908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 370008de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 370108de2844SGiridhar Malavali read_value |= crb_entry->value_3; 370208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 370308de2844SGiridhar Malavali } 370408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 370508de2844SGiridhar Malavali } 370608de2844SGiridhar Malavali 370708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 370808de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 370908de2844SGiridhar Malavali read_value |= crb_entry->value_3; 371008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 371108de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 371208de2844SGiridhar Malavali } 371308de2844SGiridhar Malavali 371408de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 371508de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 371608de2844SGiridhar Malavali wtime = jiffies + poll_time; 371708de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 371808de2844SGiridhar Malavali 371908de2844SGiridhar Malavali do { 372008de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 372108de2844SGiridhar Malavali == crb_entry->value_1) 372208de2844SGiridhar Malavali break; 372308de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 372408de2844SGiridhar Malavali /* capturing dump failed */ 372508de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 372608de2844SGiridhar Malavali break; 372708de2844SGiridhar Malavali } else 372808de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 372908de2844SGiridhar Malavali crb_addr, 0, 0); 373008de2844SGiridhar Malavali } while (1); 373108de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 373208de2844SGiridhar Malavali } 373308de2844SGiridhar Malavali 373408de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 373508de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 373608de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 373708de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 373808de2844SGiridhar Malavali } else 373908de2844SGiridhar Malavali addr = crb_addr; 374008de2844SGiridhar Malavali 374108de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 374208de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 374308de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 374408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 374508de2844SGiridhar Malavali } 374608de2844SGiridhar Malavali 374708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 374808de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 374908de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 375008de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 375108de2844SGiridhar Malavali } else 375208de2844SGiridhar Malavali addr = crb_addr; 375308de2844SGiridhar Malavali 375408de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 375508de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 375608de2844SGiridhar Malavali read_value = 375708de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 375808de2844SGiridhar Malavali } else 375908de2844SGiridhar Malavali read_value = crb_entry->value_1; 376008de2844SGiridhar Malavali 376108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 376208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 376308de2844SGiridhar Malavali } 376408de2844SGiridhar Malavali 376508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 376608de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 376708de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 376808de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 376908de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 377008de2844SGiridhar Malavali if (crb_entry->value_2) 377108de2844SGiridhar Malavali read_value &= crb_entry->value_2; 377208de2844SGiridhar Malavali read_value |= crb_entry->value_3; 377308de2844SGiridhar Malavali read_value += crb_entry->value_1; 377408de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 377508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 377608de2844SGiridhar Malavali } 377708de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 377808de2844SGiridhar Malavali } 377908de2844SGiridhar Malavali return rval; 378008de2844SGiridhar Malavali } 378108de2844SGiridhar Malavali 378208de2844SGiridhar Malavali static void 378308de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 378408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 378508de2844SGiridhar Malavali { 378608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 378708de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 378808de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 378908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 379008de2844SGiridhar Malavali 379108de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 379208de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 379308de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 379408de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 379508de2844SGiridhar Malavali 379608de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 379708de2844SGiridhar Malavali r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 379808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 379908de2844SGiridhar Malavali r_addr += r_stride; 380008de2844SGiridhar Malavali } 380108de2844SGiridhar Malavali *d_ptr = data_ptr; 380208de2844SGiridhar Malavali } 380308de2844SGiridhar Malavali 380408de2844SGiridhar Malavali static void 380508de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 380608de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 380708de2844SGiridhar Malavali { 380808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 380908de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 381008de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 381108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 381208de2844SGiridhar Malavali 381308de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 381408de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 381508de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 381608de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 381708de2844SGiridhar Malavali s_value = mux_hdr->select_value; 381808de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 381908de2844SGiridhar Malavali 382008de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 382108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 382208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 382308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 382408de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 382508de2844SGiridhar Malavali s_value += s_stride; 382608de2844SGiridhar Malavali } 382708de2844SGiridhar Malavali *d_ptr = data_ptr; 382808de2844SGiridhar Malavali } 382908de2844SGiridhar Malavali 383008de2844SGiridhar Malavali static void 383108de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 383208de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 383308de2844SGiridhar Malavali { 383408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 383508de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 383608de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 383708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 383808de2844SGiridhar Malavali 383908de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 384008de2844SGiridhar Malavali r_addr = crb_hdr->addr; 384108de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 384208de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 384308de2844SGiridhar Malavali 384408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 384508de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 384608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 384708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 384808de2844SGiridhar Malavali r_addr += r_stride; 384908de2844SGiridhar Malavali } 385008de2844SGiridhar Malavali *d_ptr = data_ptr; 385108de2844SGiridhar Malavali } 385208de2844SGiridhar Malavali 385308de2844SGiridhar Malavali static int 385408de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 385508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 385608de2844SGiridhar Malavali { 385708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 385808de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 385908de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 386008de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 386108de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 386208de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 386308de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 386408de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 386508de2844SGiridhar Malavali 386608de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 386708de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 386808de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 386908de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 387008de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 387108de2844SGiridhar Malavali 387208de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 387308de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 387408de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 387508de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 387608de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 387708de2844SGiridhar Malavali 387808de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 387908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 388008de2844SGiridhar Malavali if (c_value_w) 388108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 388208de2844SGiridhar Malavali 388308de2844SGiridhar Malavali if (p_mask) { 388408de2844SGiridhar Malavali w_time = jiffies + p_wait; 388508de2844SGiridhar Malavali do { 388608de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 388708de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 388808de2844SGiridhar Malavali break; 388908de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 389008de2844SGiridhar Malavali /* capturing dump failed */ 389108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 389208de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 389308de2844SGiridhar Malavali "w_time: 0x%lx\n", 389408de2844SGiridhar Malavali c_value_r, p_mask, w_time); 389508de2844SGiridhar Malavali return rval; 389608de2844SGiridhar Malavali } 389708de2844SGiridhar Malavali } while (1); 389808de2844SGiridhar Malavali } 389908de2844SGiridhar Malavali 390008de2844SGiridhar Malavali addr = r_addr; 390108de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 390208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 390308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 390408de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 390508de2844SGiridhar Malavali } 390608de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 390708de2844SGiridhar Malavali } 390808de2844SGiridhar Malavali *d_ptr = data_ptr; 390908de2844SGiridhar Malavali return QLA_SUCCESS; 391008de2844SGiridhar Malavali } 391108de2844SGiridhar Malavali 391208de2844SGiridhar Malavali static void 391308de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 391408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 391508de2844SGiridhar Malavali { 391608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 391708de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 391808de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 391908de2844SGiridhar Malavali uint32_t c_value_w; 392008de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 392108de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 392208de2844SGiridhar Malavali 392308de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 392408de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 392508de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 392608de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 392708de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 392808de2844SGiridhar Malavali 392908de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 393008de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 393108de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 393208de2844SGiridhar Malavali 393308de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 393408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 393508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 393608de2844SGiridhar Malavali addr = r_addr; 393708de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 393808de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 393908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 394008de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 394108de2844SGiridhar Malavali } 394208de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 394308de2844SGiridhar Malavali } 394408de2844SGiridhar Malavali *d_ptr = data_ptr; 394508de2844SGiridhar Malavali } 394608de2844SGiridhar Malavali 394708de2844SGiridhar Malavali static void 394808de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 394908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 395008de2844SGiridhar Malavali { 395108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 395208de2844SGiridhar Malavali uint32_t s_addr, r_addr; 395308de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 395408de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 395508de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 395608de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 395708de2844SGiridhar Malavali 395808de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 395908de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 396008de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 396108de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 396208de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 396308de2844SGiridhar Malavali 396408de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 396508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 396608de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 396708de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 396808de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 396908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 397008de2844SGiridhar Malavali r_addr += r_stride; 397108de2844SGiridhar Malavali } 397208de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 397308de2844SGiridhar Malavali } 397408de2844SGiridhar Malavali *d_ptr = data_ptr; 397508de2844SGiridhar Malavali } 397608de2844SGiridhar Malavali 397708de2844SGiridhar Malavali static void 397808de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 397908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 398008de2844SGiridhar Malavali { 398108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 398208de2844SGiridhar Malavali uint32_t r_addr, r_value; 398308de2844SGiridhar Malavali uint32_t i, loop_cnt; 398408de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 398508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 398608de2844SGiridhar Malavali 398708de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 398808de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 398908de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 399008de2844SGiridhar Malavali 399108de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 399208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 399308de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 399408de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 399508de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 399608de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 399708de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 399808de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 399908de2844SGiridhar Malavali } 400008de2844SGiridhar Malavali *d_ptr = data_ptr; 400108de2844SGiridhar Malavali } 400208de2844SGiridhar Malavali 400308de2844SGiridhar Malavali static int 400408de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 400508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 400608de2844SGiridhar Malavali { 400708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 400808de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 400908de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 401008de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 401108de2844SGiridhar Malavali unsigned long flags; 401208de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 401308de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 401408de2844SGiridhar Malavali 401508de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 401608de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 401708de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 401808de2844SGiridhar Malavali 401908de2844SGiridhar Malavali if (r_addr & 0xf) { 402008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 402108de2844SGiridhar Malavali "Read addr 0x%x not 16 bytes alligned\n", r_addr); 402208de2844SGiridhar Malavali return rval; 402308de2844SGiridhar Malavali } 402408de2844SGiridhar Malavali 402508de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 402608de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 402708de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 402808de2844SGiridhar Malavali m_hdr->read_data_size); 402908de2844SGiridhar Malavali return rval; 403008de2844SGiridhar Malavali } 403108de2844SGiridhar Malavali 403208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 403308de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 403408de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 403508de2844SGiridhar Malavali 403608de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 403708de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 403808de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 403908de2844SGiridhar Malavali r_value = 0; 404008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 404108de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 404208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 404308de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 404408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 404508de2844SGiridhar Malavali 404608de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 404708de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 404808de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 404908de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 405008de2844SGiridhar Malavali break; 405108de2844SGiridhar Malavali } 405208de2844SGiridhar Malavali 405308de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 405408de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 405508de2844SGiridhar Malavali "failed to read through agent\n"); 405608de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 405708de2844SGiridhar Malavali return rval; 405808de2844SGiridhar Malavali } 405908de2844SGiridhar Malavali 406008de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 406108de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 406208de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 406308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 406408de2844SGiridhar Malavali } 406508de2844SGiridhar Malavali r_addr += 16; 406608de2844SGiridhar Malavali } 406708de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 406808de2844SGiridhar Malavali *d_ptr = data_ptr; 406908de2844SGiridhar Malavali return QLA_SUCCESS; 407008de2844SGiridhar Malavali } 407108de2844SGiridhar Malavali 407208de2844SGiridhar Malavali static int 407308de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 407408de2844SGiridhar Malavali { 407508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 407608de2844SGiridhar Malavali uint64_t chksum = 0; 407708de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 407808de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 407908de2844SGiridhar Malavali 408008de2844SGiridhar Malavali while (count-- > 0) 408108de2844SGiridhar Malavali chksum += *d_ptr++; 408208de2844SGiridhar Malavali while (chksum >> 32) 408308de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 408408de2844SGiridhar Malavali return ~chksum; 408508de2844SGiridhar Malavali } 408608de2844SGiridhar Malavali 408708de2844SGiridhar Malavali static void 408808de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 408908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 409008de2844SGiridhar Malavali { 409108de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 409208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 409308de2844SGiridhar Malavali "Skipping entry[%d]: " 409408de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 409508de2844SGiridhar Malavali index, entry_hdr->entry_type, 409608de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 409708de2844SGiridhar Malavali } 409808de2844SGiridhar Malavali 409908de2844SGiridhar Malavali int 410008de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 410108de2844SGiridhar Malavali { 410208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 410308de2844SGiridhar Malavali int no_entry_hdr = 0; 410408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 410508de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 410608de2844SGiridhar Malavali uint32_t *data_ptr; 410708de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 410808de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 410908de2844SGiridhar Malavali 411008de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 411108de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 411208de2844SGiridhar Malavali 411308de2844SGiridhar Malavali if (ha->fw_dumped) { 411408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb037, 411508de2844SGiridhar Malavali "Firmware dump available to retrive\n"); 411608de2844SGiridhar Malavali goto md_failed; 411708de2844SGiridhar Malavali } 411808de2844SGiridhar Malavali 411908de2844SGiridhar Malavali ha->fw_dumped = 0; 412008de2844SGiridhar Malavali 412108de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 412208de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 412308de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 412408de2844SGiridhar Malavali goto md_failed; 412508de2844SGiridhar Malavali } 412608de2844SGiridhar Malavali 412708de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 412808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 412908de2844SGiridhar Malavali "Template checksum validation error\n"); 413008de2844SGiridhar Malavali goto md_failed; 413108de2844SGiridhar Malavali } 413208de2844SGiridhar Malavali 413308de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 413408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 413508de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 413608de2844SGiridhar Malavali 413708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 413808de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 413908de2844SGiridhar Malavali 414008de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 414108de2844SGiridhar Malavali 414208de2844SGiridhar Malavali /* Validate whether required debug level is set */ 414308de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 414408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 414508de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 414608de2844SGiridhar Malavali f_capture_mask); 414708de2844SGiridhar Malavali goto md_failed; 414808de2844SGiridhar Malavali } 414908de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 415008de2844SGiridhar Malavali 415108de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 415208de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 415308de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 415408de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 415508de2844SGiridhar Malavali 415608de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 415708de2844SGiridhar Malavali 415808de2844SGiridhar Malavali ql_dbg(ql_log_info, vha, 0xb03d, 415908de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 416008de2844SGiridhar Malavali 416108de2844SGiridhar Malavali /* Check whether template obtained is valid */ 416208de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 416308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 416408de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 416508de2844SGiridhar Malavali tmplt_hdr->entry_type); 416608de2844SGiridhar Malavali goto md_failed; 416708de2844SGiridhar Malavali } 416808de2844SGiridhar Malavali 416908de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 417008de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 417108de2844SGiridhar Malavali 417208de2844SGiridhar Malavali /* Walk through the entry headers */ 417308de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 417408de2844SGiridhar Malavali 417508de2844SGiridhar Malavali if (data_collected > total_data_size) { 417608de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 417708de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 417808de2844SGiridhar Malavali data_collected); 417908de2844SGiridhar Malavali goto md_failed; 418008de2844SGiridhar Malavali } 418108de2844SGiridhar Malavali 418208de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 418308de2844SGiridhar Malavali ql2xmdcapmask)) { 418408de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 418508de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 418608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 418708de2844SGiridhar Malavali "Skipping entry[%d]: " 418808de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 418908de2844SGiridhar Malavali i, entry_hdr->entry_type, 419008de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 419108de2844SGiridhar Malavali goto skip_nxt_entry; 419208de2844SGiridhar Malavali } 419308de2844SGiridhar Malavali 419408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 419508de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 419608de2844SGiridhar Malavali "entry_type: 0x%x, captrue_mask: 0x%x\n", 419708de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 419808de2844SGiridhar Malavali entry_hdr->entry_type, 419908de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 420008de2844SGiridhar Malavali 420108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 420208de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 420308de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 420408de2844SGiridhar Malavali 420508de2844SGiridhar Malavali /* Decode the entry type and take 420608de2844SGiridhar Malavali * required action to capture debug data */ 420708de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 420808de2844SGiridhar Malavali case QLA82XX_RDEND: 420908de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 421008de2844SGiridhar Malavali break; 421108de2844SGiridhar Malavali case QLA82XX_CNTRL: 421208de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 421308de2844SGiridhar Malavali entry_hdr, &data_ptr); 421408de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 421508de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 421608de2844SGiridhar Malavali goto md_failed; 421708de2844SGiridhar Malavali } 421808de2844SGiridhar Malavali break; 421908de2844SGiridhar Malavali case QLA82XX_RDCRB: 422008de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 422108de2844SGiridhar Malavali entry_hdr, &data_ptr); 422208de2844SGiridhar Malavali break; 422308de2844SGiridhar Malavali case QLA82XX_RDMEM: 422408de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 422508de2844SGiridhar Malavali entry_hdr, &data_ptr); 422608de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 422708de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 422808de2844SGiridhar Malavali goto md_failed; 422908de2844SGiridhar Malavali } 423008de2844SGiridhar Malavali break; 423108de2844SGiridhar Malavali case QLA82XX_BOARD: 423208de2844SGiridhar Malavali case QLA82XX_RDROM: 423308de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 423408de2844SGiridhar Malavali entry_hdr, &data_ptr); 423508de2844SGiridhar Malavali break; 423608de2844SGiridhar Malavali case QLA82XX_L2DTG: 423708de2844SGiridhar Malavali case QLA82XX_L2ITG: 423808de2844SGiridhar Malavali case QLA82XX_L2DAT: 423908de2844SGiridhar Malavali case QLA82XX_L2INS: 424008de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 424108de2844SGiridhar Malavali entry_hdr, &data_ptr); 424208de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 424308de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 424408de2844SGiridhar Malavali goto md_failed; 424508de2844SGiridhar Malavali } 424608de2844SGiridhar Malavali break; 424708de2844SGiridhar Malavali case QLA82XX_L1DAT: 424808de2844SGiridhar Malavali case QLA82XX_L1INS: 424908de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 425008de2844SGiridhar Malavali entry_hdr, &data_ptr); 425108de2844SGiridhar Malavali break; 425208de2844SGiridhar Malavali case QLA82XX_RDOCM: 425308de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 425408de2844SGiridhar Malavali entry_hdr, &data_ptr); 425508de2844SGiridhar Malavali break; 425608de2844SGiridhar Malavali case QLA82XX_RDMUX: 425708de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 425808de2844SGiridhar Malavali entry_hdr, &data_ptr); 425908de2844SGiridhar Malavali break; 426008de2844SGiridhar Malavali case QLA82XX_QUEUE: 426108de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 426208de2844SGiridhar Malavali entry_hdr, &data_ptr); 426308de2844SGiridhar Malavali break; 426408de2844SGiridhar Malavali case QLA82XX_RDNOP: 426508de2844SGiridhar Malavali default: 426608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 426708de2844SGiridhar Malavali break; 426808de2844SGiridhar Malavali } 426908de2844SGiridhar Malavali 427008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 427108de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 427208de2844SGiridhar Malavali 427308de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 427408de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 427508de2844SGiridhar Malavali skip_nxt_entry: 427608de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 427708de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 427808de2844SGiridhar Malavali } 427908de2844SGiridhar Malavali 428008de2844SGiridhar Malavali if (data_collected != total_data_size) { 428108de2844SGiridhar Malavali ql_dbg(ql_log_warn, vha, 0xb043, 428208de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 428308de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 428408de2844SGiridhar Malavali data_collected, total_data_size); 428508de2844SGiridhar Malavali goto md_failed; 428608de2844SGiridhar Malavali } 428708de2844SGiridhar Malavali 428808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 428908de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 429008de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 429108de2844SGiridhar Malavali ha->fw_dumped = 1; 429208de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 429308de2844SGiridhar Malavali 429408de2844SGiridhar Malavali md_failed: 429508de2844SGiridhar Malavali return rval; 429608de2844SGiridhar Malavali } 429708de2844SGiridhar Malavali 429808de2844SGiridhar Malavali int 429908de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 430008de2844SGiridhar Malavali { 430108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 430208de2844SGiridhar Malavali int i, k; 430308de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 430408de2844SGiridhar Malavali 430508de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 430608de2844SGiridhar Malavali 430708de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 430808de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 430908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 431008de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 431108de2844SGiridhar Malavali ql2xmdcapmask); 431208de2844SGiridhar Malavali } 431308de2844SGiridhar Malavali 431408de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 431508de2844SGiridhar Malavali if (i & ql2xmdcapmask) 431608de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 431708de2844SGiridhar Malavali } 431808de2844SGiridhar Malavali 431908de2844SGiridhar Malavali if (ha->md_dump) { 432008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 432108de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 432208de2844SGiridhar Malavali return 1; 432308de2844SGiridhar Malavali } 432408de2844SGiridhar Malavali 432508de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 432608de2844SGiridhar Malavali if (ha->md_dump == NULL) { 432708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 432808de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 432908de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 433008de2844SGiridhar Malavali return 1; 433108de2844SGiridhar Malavali } 433208de2844SGiridhar Malavali return 0; 433308de2844SGiridhar Malavali } 433408de2844SGiridhar Malavali 433508de2844SGiridhar Malavali void 433608de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 433708de2844SGiridhar Malavali { 433808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 433908de2844SGiridhar Malavali 434008de2844SGiridhar Malavali /* Release the template header allocated */ 434108de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 434208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 434308de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 434408de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 434508de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 434608de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 434708de2844SGiridhar Malavali ha->md_tmplt_hdr = 0; 434808de2844SGiridhar Malavali } 434908de2844SGiridhar Malavali 435008de2844SGiridhar Malavali /* Release the template data buffer allocated */ 435108de2844SGiridhar Malavali if (ha->md_dump) { 435208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 435308de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 435408de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 435508de2844SGiridhar Malavali vfree(ha->md_dump); 435608de2844SGiridhar Malavali ha->md_dump_size = 0; 435708de2844SGiridhar Malavali ha->md_dump = 0; 435808de2844SGiridhar Malavali } 435908de2844SGiridhar Malavali } 436008de2844SGiridhar Malavali 436108de2844SGiridhar Malavali void 436208de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 436308de2844SGiridhar Malavali { 436408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 436508de2844SGiridhar Malavali int rval; 436608de2844SGiridhar Malavali 436708de2844SGiridhar Malavali /* Get Minidump template size */ 436808de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 436908de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 437008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 437108de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 437208de2844SGiridhar Malavali ha->md_template_size / 1024); 437308de2844SGiridhar Malavali 437408de2844SGiridhar Malavali /* Get Minidump template */ 437508de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 437608de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 437708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 437808de2844SGiridhar Malavali "MiniDump Template obtained\n"); 437908de2844SGiridhar Malavali 438008de2844SGiridhar Malavali /* Allocate memory for minidump */ 438108de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 438208de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 438308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 438408de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 438508de2844SGiridhar Malavali ha->md_dump_size / 1024); 438608de2844SGiridhar Malavali else { 438708de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 438808de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 438908de2844SGiridhar Malavali ha->md_tmplt_hdr, 439008de2844SGiridhar Malavali ha->md_template_size / 1024); 439108de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 439208de2844SGiridhar Malavali ha->md_template_size, 439308de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 439408de2844SGiridhar Malavali ha->md_tmplt_hdr = 0; 439508de2844SGiridhar Malavali } 439608de2844SGiridhar Malavali 439708de2844SGiridhar Malavali } 439808de2844SGiridhar Malavali } 439908de2844SGiridhar Malavali } 4400999916dcSSaurav Kashyap 4401999916dcSSaurav Kashyap int 4402999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4403999916dcSSaurav Kashyap { 4404999916dcSSaurav Kashyap 4405999916dcSSaurav Kashyap int rval; 4406999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4407999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4408999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4409999916dcSSaurav Kashyap 4410999916dcSSaurav Kashyap if (rval) { 4411999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4412999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4413999916dcSSaurav Kashyap goto exit; 4414999916dcSSaurav Kashyap } 4415999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4416999916dcSSaurav Kashyap exit: 4417999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4418999916dcSSaurav Kashyap return rval; 4419999916dcSSaurav Kashyap } 4420999916dcSSaurav Kashyap 4421999916dcSSaurav Kashyap int 4422999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4423999916dcSSaurav Kashyap { 4424999916dcSSaurav Kashyap 4425999916dcSSaurav Kashyap int rval; 4426999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4427999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4428999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4429999916dcSSaurav Kashyap 4430999916dcSSaurav Kashyap if (rval) { 4431999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4432999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4433999916dcSSaurav Kashyap goto exit; 4434999916dcSSaurav Kashyap } 4435999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4436999916dcSSaurav Kashyap exit: 4437999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4438999916dcSSaurav Kashyap return rval; 4439999916dcSSaurav Kashyap } 4440