1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 31e63395cSSaurav Kashyap * Copyright (c) 2003-2013 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 1008de2844SGiridhar Malavali #include <linux/ratelimit.h> 1108de2844SGiridhar Malavali #include <linux/vmalloc.h> 12ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 13a9083016SGiridhar Malavali 14a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 15a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 19a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 23a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 250547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 26a9083016SGiridhar Malavali 27a9083016SGiridhar Malavali /* CRB window related */ 28a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 29a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 31a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33a9083016SGiridhar Malavali ((off) & 0xf0000)) 34a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 36a9083016SGiridhar Malavali 37a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 38a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39fa492630SSaurav Kashyap static int qla82xx_crb_table_initialized; 40a9083016SGiridhar Malavali 41a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 42a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44a9083016SGiridhar Malavali 45a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 46a9083016SGiridhar Malavali { 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 97a9083016SGiridhar Malavali /* 98a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 99a9083016SGiridhar Malavali */ 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 101a9083016SGiridhar Malavali 102a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 103a9083016SGiridhar Malavali } 104a9083016SGiridhar Malavali 105fa492630SSaurav Kashyap static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 107a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 108a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 109a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 110a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 111a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 112a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 113a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 114a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 121a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 123a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 125a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 209a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 210a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213a9083016SGiridhar Malavali {{{0} } }, 214a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 215a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 216a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 217a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 218a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 219a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 220a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 221a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 230a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{0} } }, 235a9083016SGiridhar Malavali {{{0} } }, 236a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248a9083016SGiridhar Malavali {{{0} } }, 249a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255a9083016SGiridhar Malavali {{{0} } }, 256a9083016SGiridhar Malavali {{{0} } }, 257a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260a9083016SGiridhar Malavali }; 261a9083016SGiridhar Malavali 262a9083016SGiridhar Malavali /* 263a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 264a9083016SGiridhar Malavali */ 265fa492630SSaurav Kashyap static unsigned qla82xx_crb_hub_agt[64] = { 266a9083016SGiridhar Malavali 0, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270a9083016SGiridhar Malavali 0, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293a9083016SGiridhar Malavali 0, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298a9083016SGiridhar Malavali 0, 299a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318a9083016SGiridhar Malavali 0, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323a9083016SGiridhar Malavali 0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali }; 331a9083016SGiridhar Malavali 332f1af6208SGiridhar Malavali /* Device states */ 333fa492630SSaurav Kashyap static char *q_dev_state[] = { 334f1af6208SGiridhar Malavali "Unknown", 335f1af6208SGiridhar Malavali "Cold", 336f1af6208SGiridhar Malavali "Initializing", 337f1af6208SGiridhar Malavali "Ready", 338f1af6208SGiridhar Malavali "Need Reset", 339f1af6208SGiridhar Malavali "Need Quiescent", 340f1af6208SGiridhar Malavali "Failed", 341f1af6208SGiridhar Malavali "Quiescent", 342f1af6208SGiridhar Malavali }; 343f1af6208SGiridhar Malavali 34408de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 34508de2844SGiridhar Malavali { 34608de2844SGiridhar Malavali return q_dev_state[dev_state]; 34708de2844SGiridhar Malavali } 34808de2844SGiridhar Malavali 349a9083016SGiridhar Malavali /* 350a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 351a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 352a9083016SGiridhar Malavali * side effect: lock crb window 353a9083016SGiridhar Malavali */ 354a9083016SGiridhar Malavali static void 355a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356a9083016SGiridhar Malavali { 357a9083016SGiridhar Malavali u32 win_read; 3587c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359a9083016SGiridhar Malavali 360a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 361a9083016SGiridhar Malavali writel(ha->crb_win, 362fa492630SSaurav Kashyap (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363a9083016SGiridhar Malavali 364a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 365a9083016SGiridhar Malavali * to use it. 366a9083016SGiridhar Malavali */ 367fa492630SSaurav Kashyap win_read = RD_REG_DWORD((void __iomem *) 368fa492630SSaurav Kashyap (CRB_WINDOW_2M + ha->nx_pcibase)); 369a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3707c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3717c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3727c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 373d8424f68SJoe Perches __func__, ha->crb_win, win_read, *off); 374a9083016SGiridhar Malavali } 375a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376a9083016SGiridhar Malavali } 377a9083016SGiridhar Malavali 378a9083016SGiridhar Malavali static inline unsigned long 379a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 380a9083016SGiridhar Malavali { 3817c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 382a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 383a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 384a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 385a9083016SGiridhar Malavali * regs are in both windows. 386a9083016SGiridhar Malavali */ 387a9083016SGiridhar Malavali return off; 388a9083016SGiridhar Malavali } 389a9083016SGiridhar Malavali 390a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 391a9083016SGiridhar Malavali /* We are in first CRB window */ 392a9083016SGiridhar Malavali if (ha->curr_window != 0) 393a9083016SGiridhar Malavali WARN_ON(1); 394a9083016SGiridhar Malavali return off; 395a9083016SGiridhar Malavali } 396a9083016SGiridhar Malavali 397a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 398a9083016SGiridhar Malavali /* We are in second CRB window */ 399a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 400a9083016SGiridhar Malavali 401a9083016SGiridhar Malavali if (ha->curr_window != 1) 402a9083016SGiridhar Malavali return off; 403a9083016SGiridhar Malavali 404a9083016SGiridhar Malavali /* We are in the QM or direct access 405a9083016SGiridhar Malavali * register region - do nothing 406a9083016SGiridhar Malavali */ 407a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 408a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 409a9083016SGiridhar Malavali return off; 410a9083016SGiridhar Malavali } 411a9083016SGiridhar Malavali /* strange address given */ 4127c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 413d8424f68SJoe Perches "%s: Warning: unm_nic_pci_set_crbwindow " 4147c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4157c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 416a9083016SGiridhar Malavali return off; 417a9083016SGiridhar Malavali } 418a9083016SGiridhar Malavali 41977e334d2SGiridhar Malavali static int 42077e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 42177e334d2SGiridhar Malavali { 42277e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 42377e334d2SGiridhar Malavali 42477e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 42577e334d2SGiridhar Malavali return -1; 42677e334d2SGiridhar Malavali 42777e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42877e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42977e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 43077e334d2SGiridhar Malavali return 0; 43177e334d2SGiridhar Malavali } 43277e334d2SGiridhar Malavali 43377e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 43477e334d2SGiridhar Malavali return -1; 43577e334d2SGiridhar Malavali 43677e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 43777e334d2SGiridhar Malavali 43877e334d2SGiridhar Malavali /* Try direct map */ 43977e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 44077e334d2SGiridhar Malavali 44177e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 44277e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 44377e334d2SGiridhar Malavali return 0; 44477e334d2SGiridhar Malavali } 44577e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 44677e334d2SGiridhar Malavali return 1; 44777e334d2SGiridhar Malavali } 44877e334d2SGiridhar Malavali 44977e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 45077e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 45177e334d2SGiridhar Malavali { 45277e334d2SGiridhar Malavali int done = 0, timeout = 0; 45377e334d2SGiridhar Malavali 45477e334d2SGiridhar Malavali while (!done) { 45577e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 45677e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 45777e334d2SGiridhar Malavali if (done == 1) 45877e334d2SGiridhar Malavali break; 45977e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 46077e334d2SGiridhar Malavali return -1; 46177e334d2SGiridhar Malavali timeout++; 46277e334d2SGiridhar Malavali } 46377e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 46477e334d2SGiridhar Malavali return 0; 46577e334d2SGiridhar Malavali } 46677e334d2SGiridhar Malavali 467a9083016SGiridhar Malavali int 468a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 469a9083016SGiridhar Malavali { 470a9083016SGiridhar Malavali unsigned long flags = 0; 471a9083016SGiridhar Malavali int rv; 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474a9083016SGiridhar Malavali 475a9083016SGiridhar Malavali BUG_ON(rv == -1); 476a9083016SGiridhar Malavali 477a9083016SGiridhar Malavali if (rv == 1) { 478a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 479a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 480a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 481a9083016SGiridhar Malavali } 482a9083016SGiridhar Malavali 483a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 484a9083016SGiridhar Malavali 485a9083016SGiridhar Malavali if (rv == 1) { 486a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 487a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 488a9083016SGiridhar Malavali } 489a9083016SGiridhar Malavali return 0; 490a9083016SGiridhar Malavali } 491a9083016SGiridhar Malavali 492a9083016SGiridhar Malavali int 493a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494a9083016SGiridhar Malavali { 495a9083016SGiridhar Malavali unsigned long flags = 0; 496a9083016SGiridhar Malavali int rv; 497a9083016SGiridhar Malavali u32 data; 498a9083016SGiridhar Malavali 499a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 500a9083016SGiridhar Malavali 501a9083016SGiridhar Malavali BUG_ON(rv == -1); 502a9083016SGiridhar Malavali 503a9083016SGiridhar Malavali if (rv == 1) { 504a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 505a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 506a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 507a9083016SGiridhar Malavali } 508a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 509a9083016SGiridhar Malavali 510a9083016SGiridhar Malavali if (rv == 1) { 511a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 512a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 513a9083016SGiridhar Malavali } 514a9083016SGiridhar Malavali return data; 515a9083016SGiridhar Malavali } 516a9083016SGiridhar Malavali 517a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 518a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 519a9083016SGiridhar Malavali { 520a9083016SGiridhar Malavali int i; 521a9083016SGiridhar Malavali int done = 0, timeout = 0; 522a9083016SGiridhar Malavali 523a9083016SGiridhar Malavali while (!done) { 524a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 525a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 526a9083016SGiridhar Malavali if (done == 1) 527a9083016SGiridhar Malavali break; 528a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 529a9083016SGiridhar Malavali return -1; 530a9083016SGiridhar Malavali 531a9083016SGiridhar Malavali timeout++; 532a9083016SGiridhar Malavali 533a9083016SGiridhar Malavali /* Yield CPU */ 534a9083016SGiridhar Malavali if (!in_interrupt()) 535a9083016SGiridhar Malavali schedule(); 536a9083016SGiridhar Malavali else { 537a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 538a9083016SGiridhar Malavali cpu_relax(); 539a9083016SGiridhar Malavali } 540a9083016SGiridhar Malavali } 541a9083016SGiridhar Malavali 542a9083016SGiridhar Malavali return 0; 543a9083016SGiridhar Malavali } 544a9083016SGiridhar Malavali 545a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 546a9083016SGiridhar Malavali { 547a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548a9083016SGiridhar Malavali } 549a9083016SGiridhar Malavali 550a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 551a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 552a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 553a9083016SGiridhar Malavali /* 554a9083016SGiridhar Malavali * check memory access boundary. 555a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 556a9083016SGiridhar Malavali */ 557a9083016SGiridhar Malavali static unsigned long 558a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 559a9083016SGiridhar Malavali unsigned long long addr, int size) 560a9083016SGiridhar Malavali { 561a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 562a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 563a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 564a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 565a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 566a9083016SGiridhar Malavali return 0; 567a9083016SGiridhar Malavali else 568a9083016SGiridhar Malavali return 1; 569a9083016SGiridhar Malavali } 570a9083016SGiridhar Malavali 571fa492630SSaurav Kashyap static int qla82xx_pci_set_window_warning_count; 572a9083016SGiridhar Malavali 57377e334d2SGiridhar Malavali static unsigned long 574a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 575a9083016SGiridhar Malavali { 576a9083016SGiridhar Malavali int window; 577a9083016SGiridhar Malavali u32 win_read; 5787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 579a9083016SGiridhar Malavali 580a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 581a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 582a9083016SGiridhar Malavali /* DDR network side */ 583a9083016SGiridhar Malavali window = MN_WIN(addr); 584a9083016SGiridhar Malavali ha->ddr_mn_window = window; 585a9083016SGiridhar Malavali qla82xx_wr_32(ha, 586a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 587a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 588a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 589a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5907c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5917c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 592a9083016SGiridhar Malavali __func__, window, win_read); 593a9083016SGiridhar Malavali } 594a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 595a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 596a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 597a9083016SGiridhar Malavali unsigned int temp1; 598a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5997c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 600a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 601a9083016SGiridhar Malavali addr = -1UL; 602a9083016SGiridhar Malavali } 603a9083016SGiridhar Malavali window = OCM_WIN(addr); 604a9083016SGiridhar Malavali ha->ddr_mn_window = window; 605a9083016SGiridhar Malavali qla82xx_wr_32(ha, 606a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 607a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 608a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 609a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 610a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 611a9083016SGiridhar Malavali if (win_read != temp1) { 6127c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6137c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 614a9083016SGiridhar Malavali __func__, temp1, win_read); 615a9083016SGiridhar Malavali } 616a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 617a9083016SGiridhar Malavali 618a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 619a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 620a9083016SGiridhar Malavali /* QDR network side */ 621a9083016SGiridhar Malavali window = MS_WIN(addr); 622a9083016SGiridhar Malavali ha->qdr_sn_window = window; 623a9083016SGiridhar Malavali qla82xx_wr_32(ha, 624a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 625a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 626a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 627a9083016SGiridhar Malavali if (win_read != window) { 6287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6297c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 630a9083016SGiridhar Malavali __func__, window, win_read); 631a9083016SGiridhar Malavali } 632a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 633a9083016SGiridhar Malavali } else { 634a9083016SGiridhar Malavali /* 635a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 636a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 637a9083016SGiridhar Malavali */ 638a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 639a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6417c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6427c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 643a9083016SGiridhar Malavali } 644a9083016SGiridhar Malavali addr = -1UL; 645a9083016SGiridhar Malavali } 646a9083016SGiridhar Malavali return addr; 647a9083016SGiridhar Malavali } 648a9083016SGiridhar Malavali 649a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 650a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 651a9083016SGiridhar Malavali unsigned long long addr) 652a9083016SGiridhar Malavali { 653a9083016SGiridhar Malavali int window; 654a9083016SGiridhar Malavali unsigned long long qdr_max; 655a9083016SGiridhar Malavali 656a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 657a9083016SGiridhar Malavali 658a9083016SGiridhar Malavali /* DDR network side */ 659a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 660a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 661a9083016SGiridhar Malavali BUG(); 662a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 663a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 664a9083016SGiridhar Malavali return 1; 665a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 666a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 667a9083016SGiridhar Malavali return 1; 668a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 669a9083016SGiridhar Malavali /* QDR network side */ 670a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 671a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 672a9083016SGiridhar Malavali return 1; 673a9083016SGiridhar Malavali } 674a9083016SGiridhar Malavali return 0; 675a9083016SGiridhar Malavali } 676a9083016SGiridhar Malavali 677a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 678a9083016SGiridhar Malavali u64 off, void *data, int size) 679a9083016SGiridhar Malavali { 680a9083016SGiridhar Malavali unsigned long flags; 681fa492630SSaurav Kashyap void __iomem *addr = NULL; 682a9083016SGiridhar Malavali int ret = 0; 683a9083016SGiridhar Malavali u64 start; 684fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 685a9083016SGiridhar Malavali unsigned long mem_base; 686a9083016SGiridhar Malavali unsigned long mem_page; 6877c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 688a9083016SGiridhar Malavali 689a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 690a9083016SGiridhar Malavali 691a9083016SGiridhar Malavali /* 692a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 693a9083016SGiridhar Malavali * do not access. 694a9083016SGiridhar Malavali */ 695a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 696a9083016SGiridhar Malavali if ((start == -1UL) || 697a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 698a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6997c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 7007c3df132SSaurav Kashyap "%s out of bound pci memory " 7017c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7027c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 703a9083016SGiridhar Malavali return -1; 704a9083016SGiridhar Malavali } 705a9083016SGiridhar Malavali 706a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 707a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 708a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 709a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 710a9083016SGiridhar Malavali * consecutive pages. 711a9083016SGiridhar Malavali */ 712a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 713a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 714a9083016SGiridhar Malavali else 715a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 716fa492630SSaurav Kashyap if (mem_ptr == NULL) { 717a9083016SGiridhar Malavali *(u8 *)data = 0; 718a9083016SGiridhar Malavali return -1; 719a9083016SGiridhar Malavali } 720a9083016SGiridhar Malavali addr = mem_ptr; 721a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 722a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 723a9083016SGiridhar Malavali 724a9083016SGiridhar Malavali switch (size) { 725a9083016SGiridhar Malavali case 1: 726a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 727a9083016SGiridhar Malavali break; 728a9083016SGiridhar Malavali case 2: 729a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 730a9083016SGiridhar Malavali break; 731a9083016SGiridhar Malavali case 4: 732a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 733a9083016SGiridhar Malavali break; 734a9083016SGiridhar Malavali case 8: 735a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 736a9083016SGiridhar Malavali break; 737a9083016SGiridhar Malavali default: 738a9083016SGiridhar Malavali ret = -1; 739a9083016SGiridhar Malavali break; 740a9083016SGiridhar Malavali } 741a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 742a9083016SGiridhar Malavali 743a9083016SGiridhar Malavali if (mem_ptr) 744a9083016SGiridhar Malavali iounmap(mem_ptr); 745a9083016SGiridhar Malavali return ret; 746a9083016SGiridhar Malavali } 747a9083016SGiridhar Malavali 748a9083016SGiridhar Malavali static int 749a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 750a9083016SGiridhar Malavali u64 off, void *data, int size) 751a9083016SGiridhar Malavali { 752a9083016SGiridhar Malavali unsigned long flags; 753fa492630SSaurav Kashyap void __iomem *addr = NULL; 754a9083016SGiridhar Malavali int ret = 0; 755a9083016SGiridhar Malavali u64 start; 756fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 757a9083016SGiridhar Malavali unsigned long mem_base; 758a9083016SGiridhar Malavali unsigned long mem_page; 7597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 760a9083016SGiridhar Malavali 761a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 762a9083016SGiridhar Malavali 763a9083016SGiridhar Malavali /* 764a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 765a9083016SGiridhar Malavali * do not access. 766a9083016SGiridhar Malavali */ 767a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 768a9083016SGiridhar Malavali if ((start == -1UL) || 769a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 770a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7717c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7727c3df132SSaurav Kashyap "%s out of bount memory " 7737c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7747c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 775a9083016SGiridhar Malavali return -1; 776a9083016SGiridhar Malavali } 777a9083016SGiridhar Malavali 778a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 779a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 780a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 781a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 782a9083016SGiridhar Malavali * consecutive pages. 783a9083016SGiridhar Malavali */ 784a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 785a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 786a9083016SGiridhar Malavali else 787a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 788fa492630SSaurav Kashyap if (mem_ptr == NULL) 789a9083016SGiridhar Malavali return -1; 790a9083016SGiridhar Malavali 791a9083016SGiridhar Malavali addr = mem_ptr; 792a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 793a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 794a9083016SGiridhar Malavali 795a9083016SGiridhar Malavali switch (size) { 796a9083016SGiridhar Malavali case 1: 797a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 798a9083016SGiridhar Malavali break; 799a9083016SGiridhar Malavali case 2: 800a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 801a9083016SGiridhar Malavali break; 802a9083016SGiridhar Malavali case 4: 803a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 804a9083016SGiridhar Malavali break; 805a9083016SGiridhar Malavali case 8: 806a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 807a9083016SGiridhar Malavali break; 808a9083016SGiridhar Malavali default: 809a9083016SGiridhar Malavali ret = -1; 810a9083016SGiridhar Malavali break; 811a9083016SGiridhar Malavali } 812a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 813a9083016SGiridhar Malavali if (mem_ptr) 814a9083016SGiridhar Malavali iounmap(mem_ptr); 815a9083016SGiridhar Malavali return ret; 816a9083016SGiridhar Malavali } 817a9083016SGiridhar Malavali 818a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81977e334d2SGiridhar Malavali static unsigned long 82077e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 821a9083016SGiridhar Malavali { 822a9083016SGiridhar Malavali int i; 823a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 824a9083016SGiridhar Malavali 825a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 826a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 827a9083016SGiridhar Malavali 828a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 829a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 830a9083016SGiridhar Malavali offset = addr & 0x000fffff; 831a9083016SGiridhar Malavali 832a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 833a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 834a9083016SGiridhar Malavali pci_base = i << 20; 835a9083016SGiridhar Malavali break; 836a9083016SGiridhar Malavali } 837a9083016SGiridhar Malavali } 838a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 839a9083016SGiridhar Malavali return pci_base; 840a9083016SGiridhar Malavali return pci_base + offset; 841a9083016SGiridhar Malavali } 842a9083016SGiridhar Malavali 843a9083016SGiridhar Malavali static long rom_max_timeout = 100; 844a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 845a9083016SGiridhar Malavali 84677e334d2SGiridhar Malavali static int 847a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 848a9083016SGiridhar Malavali { 849a9083016SGiridhar Malavali int done = 0, timeout = 0; 8506c315553SSaurav Kashyap uint32_t lock_owner = 0; 851a9083016SGiridhar Malavali 852a9083016SGiridhar Malavali while (!done) { 853a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 854a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 855a9083016SGiridhar Malavali if (done == 1) 856a9083016SGiridhar Malavali break; 8576c315553SSaurav Kashyap if (timeout >= qla82xx_rom_lock_timeout) { 8586c315553SSaurav Kashyap lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 859a9083016SGiridhar Malavali return -1; 8606c315553SSaurav Kashyap } 861a9083016SGiridhar Malavali timeout++; 862a9083016SGiridhar Malavali } 8634babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 864a9083016SGiridhar Malavali return 0; 865a9083016SGiridhar Malavali } 866a9083016SGiridhar Malavali 867d652e093SChad Dupuis static void 868d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 869d652e093SChad Dupuis { 8704babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 871d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 872d652e093SChad Dupuis } 873d652e093SChad Dupuis 87477e334d2SGiridhar Malavali static int 875a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 876a9083016SGiridhar Malavali { 877a9083016SGiridhar Malavali long timeout = 0; 878a9083016SGiridhar Malavali long done = 0 ; 8797c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 880a9083016SGiridhar Malavali 881a9083016SGiridhar Malavali while (done == 0) { 882a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 883a9083016SGiridhar Malavali done &= 4; 884a9083016SGiridhar Malavali timeout++; 885a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8867c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8877c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8887c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 889a9083016SGiridhar Malavali return -1; 890a9083016SGiridhar Malavali } 891a9083016SGiridhar Malavali } 892a9083016SGiridhar Malavali return 0; 893a9083016SGiridhar Malavali } 894a9083016SGiridhar Malavali 89577e334d2SGiridhar Malavali static int 896a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 897a9083016SGiridhar Malavali { 898a9083016SGiridhar Malavali long timeout = 0; 899a9083016SGiridhar Malavali long done = 0 ; 9007c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 901a9083016SGiridhar Malavali 902a9083016SGiridhar Malavali while (done == 0) { 903a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 904a9083016SGiridhar Malavali done &= 2; 905a9083016SGiridhar Malavali timeout++; 906a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 9077c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 9087c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 9097c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 910a9083016SGiridhar Malavali return -1; 911a9083016SGiridhar Malavali } 912a9083016SGiridhar Malavali } 913a9083016SGiridhar Malavali return 0; 914a9083016SGiridhar Malavali } 915a9083016SGiridhar Malavali 916fa492630SSaurav Kashyap static int 9172b29d96dSChad Dupuis qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 9182b29d96dSChad Dupuis { 9192b29d96dSChad Dupuis uint32_t off_value, rval = 0; 9202b29d96dSChad Dupuis 921fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 9222b29d96dSChad Dupuis (off & 0xFFFF0000)); 9232b29d96dSChad Dupuis 9242b29d96dSChad Dupuis /* Read back value to make sure write has gone through */ 925fa492630SSaurav Kashyap RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 9262b29d96dSChad Dupuis off_value = (off & 0x0000FFFF); 9272b29d96dSChad Dupuis 9282b29d96dSChad Dupuis if (flag) 929fa492630SSaurav Kashyap WRT_REG_DWORD((void __iomem *) 9302b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 9312b29d96dSChad Dupuis data); 9322b29d96dSChad Dupuis else 933fa492630SSaurav Kashyap rval = RD_REG_DWORD((void __iomem *) 9342b29d96dSChad Dupuis (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 9352b29d96dSChad Dupuis 9362b29d96dSChad Dupuis return rval; 9372b29d96dSChad Dupuis } 9382b29d96dSChad Dupuis 93977e334d2SGiridhar Malavali static int 940a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 941a9083016SGiridhar Malavali { 9422b29d96dSChad Dupuis /* Dword reads to flash. */ 9432b29d96dSChad Dupuis qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 9442b29d96dSChad Dupuis *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 9452b29d96dSChad Dupuis (addr & 0x0000FFFF), 0, 0); 9467c3df132SSaurav Kashyap 947a9083016SGiridhar Malavali return 0; 948a9083016SGiridhar Malavali } 949a9083016SGiridhar Malavali 95077e334d2SGiridhar Malavali static int 951a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 952a9083016SGiridhar Malavali { 953a9083016SGiridhar Malavali int ret, loops = 0; 9544babb90eSHiral Patel uint32_t lock_owner = 0; 9557c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 956a9083016SGiridhar Malavali 957a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 958a9083016SGiridhar Malavali udelay(100); 959a9083016SGiridhar Malavali schedule(); 960a9083016SGiridhar Malavali loops++; 961a9083016SGiridhar Malavali } 962a9083016SGiridhar Malavali if (loops >= 50000) { 9634babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 9647c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9654babb90eSHiral Patel "Failed to acquire SEM2 lock, Lock Owner %u.\n", 9664babb90eSHiral Patel lock_owner); 967a9083016SGiridhar Malavali return -1; 968a9083016SGiridhar Malavali } 969a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 970d652e093SChad Dupuis qla82xx_rom_unlock(ha); 971a9083016SGiridhar Malavali return ret; 972a9083016SGiridhar Malavali } 973a9083016SGiridhar Malavali 97477e334d2SGiridhar Malavali static int 975a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 976a9083016SGiridhar Malavali { 9777c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 978a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 979a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 980a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9827c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 983a9083016SGiridhar Malavali return -1; 984a9083016SGiridhar Malavali } 985a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 986a9083016SGiridhar Malavali return 0; 987a9083016SGiridhar Malavali } 988a9083016SGiridhar Malavali 98977e334d2SGiridhar Malavali static int 990a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 991a9083016SGiridhar Malavali { 992a9083016SGiridhar Malavali long timeout = 0; 993a9083016SGiridhar Malavali uint32_t done = 1 ; 994a9083016SGiridhar Malavali uint32_t val; 995a9083016SGiridhar Malavali int ret = 0; 9967c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 997a9083016SGiridhar Malavali 998a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 999a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 1000a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 1001a9083016SGiridhar Malavali done = val & 1; 1002a9083016SGiridhar Malavali timeout++; 1003a9083016SGiridhar Malavali udelay(10); 1004a9083016SGiridhar Malavali cond_resched(); 1005a9083016SGiridhar Malavali if (timeout >= 50000) { 10067c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 10077c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 1008a9083016SGiridhar Malavali return -1; 1009a9083016SGiridhar Malavali } 1010a9083016SGiridhar Malavali } 1011a9083016SGiridhar Malavali return ret; 1012a9083016SGiridhar Malavali } 1013a9083016SGiridhar Malavali 101477e334d2SGiridhar Malavali static int 1015a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1016a9083016SGiridhar Malavali { 1017a9083016SGiridhar Malavali uint32_t val; 1018a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1019a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1020a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1021a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1022a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 1023a9083016SGiridhar Malavali return -1; 1024a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1025a9083016SGiridhar Malavali return -1; 1026a9083016SGiridhar Malavali if ((val & 2) != 2) 1027a9083016SGiridhar Malavali return -1; 1028a9083016SGiridhar Malavali return 0; 1029a9083016SGiridhar Malavali } 1030a9083016SGiridhar Malavali 103177e334d2SGiridhar Malavali static int 1032a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1033a9083016SGiridhar Malavali { 10347c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1035a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1036a9083016SGiridhar Malavali return -1; 1037a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1038a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1039a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10417c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1042a9083016SGiridhar Malavali return -1; 1043a9083016SGiridhar Malavali } 1044a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1045a9083016SGiridhar Malavali } 1046a9083016SGiridhar Malavali 104777e334d2SGiridhar Malavali static int 1048a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1049a9083016SGiridhar Malavali { 10507c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1051a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1052a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10537c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10547c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1055a9083016SGiridhar Malavali return -1; 1056a9083016SGiridhar Malavali } 1057a9083016SGiridhar Malavali return 0; 1058a9083016SGiridhar Malavali } 1059a9083016SGiridhar Malavali 106077e334d2SGiridhar Malavali static int 1061a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1062a9083016SGiridhar Malavali { 1063a9083016SGiridhar Malavali int loops = 0; 10644babb90eSHiral Patel uint32_t lock_owner = 0; 10657c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10667c3df132SSaurav Kashyap 1067a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1068a9083016SGiridhar Malavali udelay(100); 1069a9083016SGiridhar Malavali cond_resched(); 1070a9083016SGiridhar Malavali loops++; 1071a9083016SGiridhar Malavali } 1072a9083016SGiridhar Malavali if (loops >= 50000) { 10734babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 10747c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10754babb90eSHiral Patel "ROM lock failed, Lock Owner %u.\n", lock_owner); 1076a9083016SGiridhar Malavali return -1; 1077a9083016SGiridhar Malavali } 1078cd6dbb03SJesper Juhl return 0; 1079a9083016SGiridhar Malavali } 1080a9083016SGiridhar Malavali 108177e334d2SGiridhar Malavali static int 1082a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1083a9083016SGiridhar Malavali uint32_t data) 1084a9083016SGiridhar Malavali { 1085a9083016SGiridhar Malavali int ret = 0; 10867c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1087a9083016SGiridhar Malavali 1088a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1089a9083016SGiridhar Malavali if (ret < 0) { 10907c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10917c3df132SSaurav Kashyap "ROM lock failed.\n"); 1092a9083016SGiridhar Malavali return ret; 1093a9083016SGiridhar Malavali } 1094a9083016SGiridhar Malavali 1095a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1096a9083016SGiridhar Malavali goto done_write; 1097a9083016SGiridhar Malavali 1098a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1099a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1100a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1101a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1102a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1103a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 11047c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 11057c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1106a9083016SGiridhar Malavali ret = -1; 1107a9083016SGiridhar Malavali goto done_write; 1108a9083016SGiridhar Malavali } 1109a9083016SGiridhar Malavali 1110a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1111a9083016SGiridhar Malavali 1112a9083016SGiridhar Malavali done_write: 1113d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1114a9083016SGiridhar Malavali return ret; 1115a9083016SGiridhar Malavali } 1116a9083016SGiridhar Malavali 1117a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1118a9083016SGiridhar Malavali * to put the ISP into operational state 1119a9083016SGiridhar Malavali */ 112077e334d2SGiridhar Malavali static int 112177e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1122a9083016SGiridhar Malavali { 1123a9083016SGiridhar Malavali int addr, val; 1124a9083016SGiridhar Malavali int i ; 1125a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1126a9083016SGiridhar Malavali unsigned long off; 1127a9083016SGiridhar Malavali unsigned offset, n; 1128a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1129a9083016SGiridhar Malavali 1130a9083016SGiridhar Malavali struct crb_addr_pair { 1131a9083016SGiridhar Malavali long addr; 1132a9083016SGiridhar Malavali long data; 1133a9083016SGiridhar Malavali }; 1134a9083016SGiridhar Malavali 1135a720101dSMasanari Iida /* Halt all the individual PEGs and other blocks of the ISP */ 1136a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1137c9e8fd5cSMadhuranath Iyengar 113802be2215SGiridhar Malavali /* disable all I2Q */ 113902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 114002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 114102be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 114202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 114302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 114402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 114502be2215SGiridhar Malavali 114602be2215SGiridhar Malavali /* disable all niu interrupts */ 1147c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1148c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1149c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1150c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1151c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 115202be2215SGiridhar Malavali /* disable sideband mac */ 115302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 115402be2215SGiridhar Malavali /* disable ap0 mac */ 115502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 115602be2215SGiridhar Malavali /* disable ap1 mac */ 115702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1158c9e8fd5cSMadhuranath Iyengar 1159c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1160c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1161c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1162c9e8fd5cSMadhuranath Iyengar 1163c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1164c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1165c9e8fd5cSMadhuranath Iyengar 1166c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1167c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1168c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1169c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1170c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1171c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 117202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1173c9e8fd5cSMadhuranath Iyengar 1174c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1175c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1176c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1177c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1178c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1179c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 118002be2215SGiridhar Malavali msleep(20); 1181c9e8fd5cSMadhuranath Iyengar 1182c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1183a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1184a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1185a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1186a9083016SGiridhar Malavali else 1187a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1188d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1189a9083016SGiridhar Malavali 1190a9083016SGiridhar Malavali /* Read the signature value from the flash. 1191a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1192a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1193a9083016SGiridhar Malavali * that present in CRB initialize sequence 1194a9083016SGiridhar Malavali */ 1195a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1196a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11977c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11987c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1199a9083016SGiridhar Malavali return -1; 1200a9083016SGiridhar Malavali } 1201a9083016SGiridhar Malavali 1202a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 120300adc9a0SSaurav Kashyap * Number of entries = upper 16 bits 1204a9083016SGiridhar Malavali */ 1205a9083016SGiridhar Malavali offset = n & 0xffffU; 1206a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1207a9083016SGiridhar Malavali 120800adc9a0SSaurav Kashyap /* number of addr/value pair should not exceed 1024 entries */ 1209a9083016SGiridhar Malavali if (n >= 1024) { 12107c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 12117c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1212a9083016SGiridhar Malavali return -1; 1213a9083016SGiridhar Malavali } 1214a9083016SGiridhar Malavali 12157c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12167c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1217a9083016SGiridhar Malavali 1218a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1219a9083016SGiridhar Malavali if (buf == NULL) { 12207c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12217c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1222a9083016SGiridhar Malavali return -1; 1223a9083016SGiridhar Malavali } 1224a9083016SGiridhar Malavali 1225a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1226a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1227a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1228a9083016SGiridhar Malavali kfree(buf); 1229a9083016SGiridhar Malavali return -1; 1230a9083016SGiridhar Malavali } 1231a9083016SGiridhar Malavali 1232a9083016SGiridhar Malavali buf[i].addr = addr; 1233a9083016SGiridhar Malavali buf[i].data = val; 1234a9083016SGiridhar Malavali } 1235a9083016SGiridhar Malavali 1236a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1237a9083016SGiridhar Malavali /* Translate internal CRB initialization 1238a9083016SGiridhar Malavali * address to PCI bus address 1239a9083016SGiridhar Malavali */ 1240a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1241a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1242a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1243a9083016SGiridhar Malavali * some of them are skipped 1244a9083016SGiridhar Malavali */ 1245a9083016SGiridhar Malavali 1246a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1247a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1248a9083016SGiridhar Malavali continue; 1249a9083016SGiridhar Malavali 1250a9083016SGiridhar Malavali /* do not reset PCI */ 1251a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1252a9083016SGiridhar Malavali continue; 1253a9083016SGiridhar Malavali 1254a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1255a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1256a9083016SGiridhar Malavali continue; 1257a9083016SGiridhar Malavali 1258a9083016SGiridhar Malavali /* skip the function enable register */ 1259a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1260a9083016SGiridhar Malavali continue; 1261a9083016SGiridhar Malavali 1262a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1263a9083016SGiridhar Malavali continue; 1264a9083016SGiridhar Malavali 1265a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1266a9083016SGiridhar Malavali continue; 1267a9083016SGiridhar Malavali 1268a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1269a9083016SGiridhar Malavali continue; 1270a9083016SGiridhar Malavali 1271a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12727c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 12737c3df132SSaurav Kashyap "Unknow addr: 0x%08lx.\n", buf[i].addr); 1274a9083016SGiridhar Malavali continue; 1275a9083016SGiridhar Malavali } 1276a9083016SGiridhar Malavali 1277a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1278a9083016SGiridhar Malavali 1279a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1280a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1281a9083016SGiridhar Malavali */ 1282a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1283a9083016SGiridhar Malavali msleep(1000); 1284a9083016SGiridhar Malavali 1285a9083016SGiridhar Malavali /* ISP requires millisec delay between 1286a9083016SGiridhar Malavali * successive CRB register updation 1287a9083016SGiridhar Malavali */ 1288a9083016SGiridhar Malavali msleep(1); 1289a9083016SGiridhar Malavali } 1290a9083016SGiridhar Malavali 1291a9083016SGiridhar Malavali kfree(buf); 1292a9083016SGiridhar Malavali 1293a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1294a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1295a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1296a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1297a9083016SGiridhar Malavali 1298a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1299a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1300a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1301a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1302a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1303a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1304a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1305a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1306a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1307a9083016SGiridhar Malavali return 0; 1308a9083016SGiridhar Malavali } 1309a9083016SGiridhar Malavali 131077e334d2SGiridhar Malavali static int 131177e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 131277e334d2SGiridhar Malavali u64 off, void *data, int size) 131377e334d2SGiridhar Malavali { 131477e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 131577e334d2SGiridhar Malavali int scale, shift_amount, startword; 131677e334d2SGiridhar Malavali uint32_t temp; 131777e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 131877e334d2SGiridhar Malavali 131977e334d2SGiridhar Malavali /* 132077e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 132177e334d2SGiridhar Malavali */ 132277e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 132377e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 132477e334d2SGiridhar Malavali else { 132577e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 132677e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 132777e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 132877e334d2SGiridhar Malavali off, data, size); 132977e334d2SGiridhar Malavali } 133077e334d2SGiridhar Malavali 133177e334d2SGiridhar Malavali off0 = off & 0x7; 133277e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 133377e334d2SGiridhar Malavali sz[1] = size - sz[0]; 133477e334d2SGiridhar Malavali 133577e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 133677e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 133777e334d2SGiridhar Malavali shift_amount = 4; 133877e334d2SGiridhar Malavali scale = 2; 133977e334d2SGiridhar Malavali startword = (off & 0xf)/8; 134077e334d2SGiridhar Malavali 134177e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 134277e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 134377e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 134477e334d2SGiridhar Malavali return -1; 134577e334d2SGiridhar Malavali } 134677e334d2SGiridhar Malavali 134777e334d2SGiridhar Malavali switch (size) { 134877e334d2SGiridhar Malavali case 1: 134977e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 135077e334d2SGiridhar Malavali break; 135177e334d2SGiridhar Malavali case 2: 135277e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 135377e334d2SGiridhar Malavali break; 135477e334d2SGiridhar Malavali case 4: 135577e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 135677e334d2SGiridhar Malavali break; 135777e334d2SGiridhar Malavali case 8: 135877e334d2SGiridhar Malavali default: 135977e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 136077e334d2SGiridhar Malavali break; 136177e334d2SGiridhar Malavali } 136277e334d2SGiridhar Malavali 136377e334d2SGiridhar Malavali if (sz[0] == 8) { 136477e334d2SGiridhar Malavali word[startword] = tmpw; 136577e334d2SGiridhar Malavali } else { 136677e334d2SGiridhar Malavali word[startword] &= 136777e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 136877e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 136977e334d2SGiridhar Malavali } 137077e334d2SGiridhar Malavali if (sz[1] != 0) { 137177e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 137277e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 137377e334d2SGiridhar Malavali } 137477e334d2SGiridhar Malavali 137577e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 137677e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 137777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 137877e334d2SGiridhar Malavali temp = 0; 137977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 138077e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 138177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 138277e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 138377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 138477e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 138577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 138677e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 138777e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 138877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 138977e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 139077e334d2SGiridhar Malavali 139177e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 139277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 139377e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 139477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 139577e334d2SGiridhar Malavali 139677e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 139777e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 139877e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 139977e334d2SGiridhar Malavali break; 140077e334d2SGiridhar Malavali } 140177e334d2SGiridhar Malavali 140277e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 140377e334d2SGiridhar Malavali if (printk_ratelimit()) 140477e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 14057c3df132SSaurav Kashyap "failed to write through agent.\n"); 140677e334d2SGiridhar Malavali ret = -1; 140777e334d2SGiridhar Malavali break; 140877e334d2SGiridhar Malavali } 140977e334d2SGiridhar Malavali } 141077e334d2SGiridhar Malavali 141177e334d2SGiridhar Malavali return ret; 141277e334d2SGiridhar Malavali } 141377e334d2SGiridhar Malavali 141477e334d2SGiridhar Malavali static int 1415a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1416a9083016SGiridhar Malavali { 1417a9083016SGiridhar Malavali int i; 1418a9083016SGiridhar Malavali long size = 0; 14199c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14209c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1421a9083016SGiridhar Malavali u64 data; 1422a9083016SGiridhar Malavali u32 high, low; 1423a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1424a9083016SGiridhar Malavali 1425a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1426a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1427a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1428a9083016SGiridhar Malavali return -1; 1429a9083016SGiridhar Malavali } 1430a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1431a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1432a9083016SGiridhar Malavali flashaddr += 8; 1433a9083016SGiridhar Malavali memaddr += 8; 1434a9083016SGiridhar Malavali 1435a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1436a9083016SGiridhar Malavali msleep(1); 1437a9083016SGiridhar Malavali } 1438a9083016SGiridhar Malavali udelay(100); 1439a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1440a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1441a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1442a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1443a9083016SGiridhar Malavali return 0; 1444a9083016SGiridhar Malavali } 1445a9083016SGiridhar Malavali 1446a9083016SGiridhar Malavali int 1447a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1448a9083016SGiridhar Malavali u64 off, void *data, int size) 1449a9083016SGiridhar Malavali { 1450a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1451a9083016SGiridhar Malavali int shift_amount; 1452a9083016SGiridhar Malavali uint32_t temp; 1453a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1454a9083016SGiridhar Malavali 1455a9083016SGiridhar Malavali /* 1456a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1457a9083016SGiridhar Malavali */ 1458a9083016SGiridhar Malavali 1459a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1460a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1461a9083016SGiridhar Malavali else { 1462a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1463a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1464a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1465a9083016SGiridhar Malavali off, data, size); 1466a9083016SGiridhar Malavali } 1467a9083016SGiridhar Malavali 1468a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1469a9083016SGiridhar Malavali off0[0] = off & 0xf; 1470a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1471a9083016SGiridhar Malavali shift_amount = 4; 1472a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1473a9083016SGiridhar Malavali off0[1] = 0; 1474a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1475a9083016SGiridhar Malavali 1476a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1477a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1478a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1479a9083016SGiridhar Malavali temp = 0; 1480a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1481a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1482a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1483a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1484a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1485a9083016SGiridhar Malavali 1486a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1487a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1488a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1489a9083016SGiridhar Malavali break; 1490a9083016SGiridhar Malavali } 1491a9083016SGiridhar Malavali 1492a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1493a9083016SGiridhar Malavali if (printk_ratelimit()) 1494a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14957c3df132SSaurav Kashyap "failed to read through agent.\n"); 1496a9083016SGiridhar Malavali break; 1497a9083016SGiridhar Malavali } 1498a9083016SGiridhar Malavali 1499a9083016SGiridhar Malavali start = off0[i] >> 2; 1500a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1501a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1502a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1503a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1504a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1505a9083016SGiridhar Malavali } 1506a9083016SGiridhar Malavali } 1507a9083016SGiridhar Malavali 1508a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1509a9083016SGiridhar Malavali return -1; 1510a9083016SGiridhar Malavali 1511a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1512a9083016SGiridhar Malavali val = word[0]; 1513a9083016SGiridhar Malavali } else { 1514a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1515a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1516a9083016SGiridhar Malavali } 1517a9083016SGiridhar Malavali 1518a9083016SGiridhar Malavali switch (size) { 1519a9083016SGiridhar Malavali case 1: 1520a9083016SGiridhar Malavali *(uint8_t *)data = val; 1521a9083016SGiridhar Malavali break; 1522a9083016SGiridhar Malavali case 2: 1523a9083016SGiridhar Malavali *(uint16_t *)data = val; 1524a9083016SGiridhar Malavali break; 1525a9083016SGiridhar Malavali case 4: 1526a9083016SGiridhar Malavali *(uint32_t *)data = val; 1527a9083016SGiridhar Malavali break; 1528a9083016SGiridhar Malavali case 8: 1529a9083016SGiridhar Malavali *(uint64_t *)data = val; 1530a9083016SGiridhar Malavali break; 1531a9083016SGiridhar Malavali } 1532a9083016SGiridhar Malavali return 0; 1533a9083016SGiridhar Malavali } 1534a9083016SGiridhar Malavali 1535a9083016SGiridhar Malavali 15369c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15379c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15389c2b2975SHarish Zunjarrao { 15399c2b2975SHarish Zunjarrao uint32_t i; 15409c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15419c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15429c2b2975SHarish Zunjarrao __le32 offset; 15439c2b2975SHarish Zunjarrao __le32 tab_type; 15449c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15459c2b2975SHarish Zunjarrao 15469c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15479c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15489c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15499c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15509c2b2975SHarish Zunjarrao 15519c2b2975SHarish Zunjarrao if (tab_type == section) 15529c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15539c2b2975SHarish Zunjarrao } 15549c2b2975SHarish Zunjarrao 15559c2b2975SHarish Zunjarrao return NULL; 15569c2b2975SHarish Zunjarrao } 15579c2b2975SHarish Zunjarrao 15589c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15599c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15609c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15619c2b2975SHarish Zunjarrao { 15629c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15639c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15649c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15659c2b2975SHarish Zunjarrao __le32 offset; 15669c2b2975SHarish Zunjarrao 15679c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15689c2b2975SHarish Zunjarrao if (!tab_desc) 15699c2b2975SHarish Zunjarrao return NULL; 15709c2b2975SHarish Zunjarrao 15719c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15729c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15739c2b2975SHarish Zunjarrao 15749c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15759c2b2975SHarish Zunjarrao } 15769c2b2975SHarish Zunjarrao 15779c2b2975SHarish Zunjarrao static u8 * 15789c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15799c2b2975SHarish Zunjarrao { 15809c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15819c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15829c2b2975SHarish Zunjarrao 15839c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15849c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15859c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15869c2b2975SHarish Zunjarrao if (uri_desc) 15879c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15889c2b2975SHarish Zunjarrao } 15899c2b2975SHarish Zunjarrao 15909c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15919c2b2975SHarish Zunjarrao } 15929c2b2975SHarish Zunjarrao 15939c2b2975SHarish Zunjarrao static __le32 15949c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15959c2b2975SHarish Zunjarrao { 15969c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15979c2b2975SHarish Zunjarrao 15989c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15999c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16009c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16019c2b2975SHarish Zunjarrao if (uri_desc) 16029c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 16039c2b2975SHarish Zunjarrao } 16049c2b2975SHarish Zunjarrao 16059c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 16069c2b2975SHarish Zunjarrao } 16079c2b2975SHarish Zunjarrao 16089c2b2975SHarish Zunjarrao static u8 * 16099c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 16109c2b2975SHarish Zunjarrao { 16119c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 16129c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 16139c2b2975SHarish Zunjarrao 16149c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16159c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16169c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16179c2b2975SHarish Zunjarrao if (uri_desc) 16189c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16199c2b2975SHarish Zunjarrao } 16209c2b2975SHarish Zunjarrao 16219c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16229c2b2975SHarish Zunjarrao } 16239c2b2975SHarish Zunjarrao 1624a9083016SGiridhar Malavali /* PCI related functions */ 1625a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1626a9083016SGiridhar Malavali { 1627a9083016SGiridhar Malavali unsigned long val = 0; 1628a9083016SGiridhar Malavali u32 control; 1629a9083016SGiridhar Malavali 1630a9083016SGiridhar Malavali switch (region) { 1631a9083016SGiridhar Malavali case 0: 1632a9083016SGiridhar Malavali val = 0; 1633a9083016SGiridhar Malavali break; 1634a9083016SGiridhar Malavali case 1: 1635a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1636a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1637a9083016SGiridhar Malavali break; 1638a9083016SGiridhar Malavali } 1639a9083016SGiridhar Malavali return val; 1640a9083016SGiridhar Malavali } 1641a9083016SGiridhar Malavali 1642a9083016SGiridhar Malavali 1643a9083016SGiridhar Malavali int 1644a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1645a9083016SGiridhar Malavali { 1646a9083016SGiridhar Malavali uint32_t len = 0; 1647a9083016SGiridhar Malavali 1648a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16497c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16507c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1651a9083016SGiridhar Malavali goto iospace_error_exit; 1652a9083016SGiridhar Malavali } 1653a9083016SGiridhar Malavali 1654a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1655a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16567c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16577c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1658a9083016SGiridhar Malavali goto iospace_error_exit; 1659a9083016SGiridhar Malavali } 1660a9083016SGiridhar Malavali 1661a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1662a9083016SGiridhar Malavali ha->nx_pcibase = 1663a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1664a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16657c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16667c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1667a9083016SGiridhar Malavali goto iospace_error_exit; 1668a9083016SGiridhar Malavali } 1669a9083016SGiridhar Malavali 1670a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 16717ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) { 16727ec0effdSAtul Deshmukh ha->iobase = 1673f73cb695SChad Dupuis (device_reg_t *)((uint8_t *)ha->nx_pcibase); 16747ec0effdSAtul Deshmukh } else if (IS_QLA82XX(ha)) { 16757ec0effdSAtul Deshmukh ha->iobase = 1676f73cb695SChad Dupuis (device_reg_t *)((uint8_t *)ha->nx_pcibase + 1677a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 16787ec0effdSAtul Deshmukh } 1679a9083016SGiridhar Malavali 1680a9083016SGiridhar Malavali if (!ql2xdbwr) { 1681a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1682a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1683a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1684a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16857c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16867c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1687a9083016SGiridhar Malavali goto iospace_error_exit; 1688a9083016SGiridhar Malavali } 1689a9083016SGiridhar Malavali 1690a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1691a9083016SGiridhar Malavali * door bell read and write pointer 1692a9083016SGiridhar Malavali */ 1693a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1694a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1695a9083016SGiridhar Malavali } else { 1696a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1697a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1698a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1699a9083016SGiridhar Malavali } 1700a9083016SGiridhar Malavali 1701a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1702a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 17037c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 17047c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17057c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1706d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17077c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17087c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17097c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17107c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 1711d8424f68SJoe Perches (void *)ha->nx_pcibase, ha->iobase, 17127c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1713a9083016SGiridhar Malavali return 0; 1714a9083016SGiridhar Malavali 1715a9083016SGiridhar Malavali iospace_error_exit: 1716a9083016SGiridhar Malavali return -ENOMEM; 1717a9083016SGiridhar Malavali } 1718a9083016SGiridhar Malavali 1719a9083016SGiridhar Malavali /* GS related functions */ 1720a9083016SGiridhar Malavali 1721a9083016SGiridhar Malavali /* Initialization related functions */ 1722a9083016SGiridhar Malavali 1723a9083016SGiridhar Malavali /** 1724a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1725a9083016SGiridhar Malavali * @ha: HA context 1726a9083016SGiridhar Malavali * 1727a9083016SGiridhar Malavali * Returns 0 on success. 1728a9083016SGiridhar Malavali */ 1729a9083016SGiridhar Malavali int 1730a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1731a9083016SGiridhar Malavali { 1732a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1733a9083016SGiridhar Malavali int ret; 1734a9083016SGiridhar Malavali 1735a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1736a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1737a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17387c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 1739d8424f68SJoe Perches "Chip revision:%d.\n", 17407c3df132SSaurav Kashyap ha->chip_revision); 1741a9083016SGiridhar Malavali return 0; 1742a9083016SGiridhar Malavali } 1743a9083016SGiridhar Malavali 1744a9083016SGiridhar Malavali /** 1745a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1746a9083016SGiridhar Malavali * @ha: HA context 1747a9083016SGiridhar Malavali * 1748a9083016SGiridhar Malavali * Returns 0 on success. 1749a9083016SGiridhar Malavali */ 1750a9083016SGiridhar Malavali void 1751a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1752a9083016SGiridhar Malavali { 1753a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1754a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1755a9083016SGiridhar Malavali } 1756a9083016SGiridhar Malavali 1757a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1758a9083016SGiridhar Malavali { 1759a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1760a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1761a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1762a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1763a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1764a9083016SGiridhar Malavali 1765a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1766a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1767a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1768a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1769a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1770a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1771a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1772a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1773a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1774a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1775a9083016SGiridhar Malavali 1776a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1777a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1778a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1779a9083016SGiridhar Malavali } 1780a9083016SGiridhar Malavali 178177e334d2SGiridhar Malavali static int 178277e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1783a9083016SGiridhar Malavali { 1784a9083016SGiridhar Malavali u64 *ptr64; 1785a9083016SGiridhar Malavali u32 i, flashaddr, size; 1786a9083016SGiridhar Malavali __le64 data; 1787a9083016SGiridhar Malavali 1788a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1789a9083016SGiridhar Malavali 17909c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1791a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1792a9083016SGiridhar Malavali 1793a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1794a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17959c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17969c2b2975SHarish Zunjarrao return -EIO; 1797a9083016SGiridhar Malavali flashaddr += 8; 1798a9083016SGiridhar Malavali } 1799a9083016SGiridhar Malavali 1800a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18019c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18029c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1803a9083016SGiridhar Malavali 1804a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1805a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1806a9083016SGiridhar Malavali 1807a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1808a9083016SGiridhar Malavali return -EIO; 1809a9083016SGiridhar Malavali flashaddr += 8; 1810a9083016SGiridhar Malavali } 18119c2b2975SHarish Zunjarrao udelay(100); 1812a9083016SGiridhar Malavali 1813a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1814a9083016SGiridhar Malavali * at a specified offset to indicate 1815a9083016SGiridhar Malavali * that all data is written and 1816a9083016SGiridhar Malavali * ready for firmware to initialize. 1817a9083016SGiridhar Malavali */ 18189c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1819a9083016SGiridhar Malavali 18209c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1821a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1822a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18239c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18249c2b2975SHarish Zunjarrao return 0; 18259c2b2975SHarish Zunjarrao } 18269c2b2975SHarish Zunjarrao 18279c2b2975SHarish Zunjarrao static int 18289c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18299c2b2975SHarish Zunjarrao { 18309c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18319c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18329c2b2975SHarish Zunjarrao uint32_t i; 18339c2b2975SHarish Zunjarrao __le32 entries; 18349c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18359c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18369c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18379c2b2975SHarish Zunjarrao int mn_present = 0; 18389c2b2975SHarish Zunjarrao uint32_t flagbit; 18399c2b2975SHarish Zunjarrao 18409c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18419c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18429c2b2975SHarish Zunjarrao if (!ptab_desc) 18439c2b2975SHarish Zunjarrao return -1; 18449c2b2975SHarish Zunjarrao 18459c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18469c2b2975SHarish Zunjarrao 18479c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18489c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18499c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18509c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18519c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18529c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18539c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18549c2b2975SHarish Zunjarrao 18559c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18569c2b2975SHarish Zunjarrao 18579c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18589c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18599c2b2975SHarish Zunjarrao return 0; 18609c2b2975SHarish Zunjarrao } 18619c2b2975SHarish Zunjarrao } 18629c2b2975SHarish Zunjarrao return -1; 18639c2b2975SHarish Zunjarrao } 18649c2b2975SHarish Zunjarrao 1865fa492630SSaurav Kashyap static int 18669c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18679c2b2975SHarish Zunjarrao { 18689c2b2975SHarish Zunjarrao __le32 val; 18699c2b2975SHarish Zunjarrao uint32_t min_size; 18709c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18719c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18729c2b2975SHarish Zunjarrao 18739c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18749c2b2975SHarish Zunjarrao 18759c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18769c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18779c2b2975SHarish Zunjarrao return -EINVAL; 18789c2b2975SHarish Zunjarrao 18799c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18809c2b2975SHarish Zunjarrao } else { 18819c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18829c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18839c2b2975SHarish Zunjarrao return -EINVAL; 18849c2b2975SHarish Zunjarrao 18859c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18869c2b2975SHarish Zunjarrao } 18879c2b2975SHarish Zunjarrao 18889c2b2975SHarish Zunjarrao if (fw->size < min_size) 18899c2b2975SHarish Zunjarrao return -EINVAL; 1890a9083016SGiridhar Malavali return 0; 1891a9083016SGiridhar Malavali } 1892a9083016SGiridhar Malavali 189377e334d2SGiridhar Malavali static int 189477e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1895a9083016SGiridhar Malavali { 1896a9083016SGiridhar Malavali u32 val = 0; 1897a9083016SGiridhar Malavali int retries = 60; 18987c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1899a9083016SGiridhar Malavali 1900a9083016SGiridhar Malavali do { 1901a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1902a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1903a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1904a9083016SGiridhar Malavali 1905a9083016SGiridhar Malavali switch (val) { 1906a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1907a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1908a9083016SGiridhar Malavali return QLA_SUCCESS; 1909a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1910a9083016SGiridhar Malavali break; 1911a9083016SGiridhar Malavali default: 1912a9083016SGiridhar Malavali break; 1913a9083016SGiridhar Malavali } 19147c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19157c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1916a9083016SGiridhar Malavali val, retries); 1917a9083016SGiridhar Malavali 1918a9083016SGiridhar Malavali msleep(500); 1919a9083016SGiridhar Malavali 1920a9083016SGiridhar Malavali } while (--retries); 1921a9083016SGiridhar Malavali 19227c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1923a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1924a9083016SGiridhar Malavali 1925a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1926a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1927a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1928a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1929a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1930a9083016SGiridhar Malavali } 1931a9083016SGiridhar Malavali 193277e334d2SGiridhar Malavali static int 193377e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1934a9083016SGiridhar Malavali { 1935a9083016SGiridhar Malavali u32 val = 0; 1936a9083016SGiridhar Malavali int retries = 60; 19377c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1938a9083016SGiridhar Malavali 1939a9083016SGiridhar Malavali do { 1940a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1941a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1942a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1943a9083016SGiridhar Malavali 1944a9083016SGiridhar Malavali switch (val) { 1945a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1946a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1947a9083016SGiridhar Malavali return QLA_SUCCESS; 1948a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1949a9083016SGiridhar Malavali break; 1950a9083016SGiridhar Malavali default: 1951a9083016SGiridhar Malavali break; 1952a9083016SGiridhar Malavali } 19537c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19547c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1955a9083016SGiridhar Malavali val, retries); 1956a9083016SGiridhar Malavali 1957a9083016SGiridhar Malavali msleep(500); 1958a9083016SGiridhar Malavali 1959a9083016SGiridhar Malavali } while (--retries); 1960a9083016SGiridhar Malavali 19617c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19627c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1963a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1964a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1965a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1966a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1967a9083016SGiridhar Malavali } 1968a9083016SGiridhar Malavali 1969a9083016SGiridhar Malavali /* ISR related functions */ 1970a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1971a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1972a9083016SGiridhar Malavali 1973a9083016SGiridhar Malavali /* 1974a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1975a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1976a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1977a9083016SGiridhar Malavali */ 19787ec0effdSAtul Deshmukh void 1979a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1980a9083016SGiridhar Malavali { 1981a9083016SGiridhar Malavali uint16_t cnt; 1982a9083016SGiridhar Malavali uint16_t __iomem *wptr; 1983a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1984a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1985a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1986a9083016SGiridhar Malavali 1987a9083016SGiridhar Malavali /* Load return mailbox registers. */ 1988a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 1989a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 1990a9083016SGiridhar Malavali 1991a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 1992a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1993a9083016SGiridhar Malavali wptr++; 1994a9083016SGiridhar Malavali } 1995a9083016SGiridhar Malavali 1996cfb0919cSChad Dupuis if (!ha->mcp) 19977c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 19987c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 1999a9083016SGiridhar Malavali } 2000a9083016SGiridhar Malavali 2001a9083016SGiridhar Malavali /* 2002a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2003a9083016SGiridhar Malavali * @irq: 2004a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2005a9083016SGiridhar Malavali * @regs: 2006a9083016SGiridhar Malavali * 2007a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2008a9083016SGiridhar Malavali * 2009a9083016SGiridhar Malavali * Returns handled flag. 2010a9083016SGiridhar Malavali */ 2011a9083016SGiridhar Malavali irqreturn_t 2012a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2013a9083016SGiridhar Malavali { 2014a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2015a9083016SGiridhar Malavali struct qla_hw_data *ha; 2016a9083016SGiridhar Malavali struct rsp_que *rsp; 2017a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2018a9083016SGiridhar Malavali int status = 0, status1 = 0; 2019a9083016SGiridhar Malavali unsigned long flags; 2020a9083016SGiridhar Malavali unsigned long iter; 20217c3df132SSaurav Kashyap uint32_t stat = 0; 2022a9083016SGiridhar Malavali uint16_t mb[4]; 2023a9083016SGiridhar Malavali 2024a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2025a9083016SGiridhar Malavali if (!rsp) { 2026b6d0d9d5SGiridhar Malavali ql_log(ql_log_info, NULL, 0xb053, 20273256b435SChad Dupuis "%s: NULL response queue pointer.\n", __func__); 2028a9083016SGiridhar Malavali return IRQ_NONE; 2029a9083016SGiridhar Malavali } 2030a9083016SGiridhar Malavali ha = rsp->hw; 2031a9083016SGiridhar Malavali 2032a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2033a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2034a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2035a9083016SGiridhar Malavali return IRQ_NONE; 2036a9083016SGiridhar Malavali 2037a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2038a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2039a9083016SGiridhar Malavali return IRQ_NONE; 2040a9083016SGiridhar Malavali } 2041a9083016SGiridhar Malavali 2042a9083016SGiridhar Malavali /* clear the interrupt */ 2043a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2044a9083016SGiridhar Malavali 2045a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2046a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2047a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2048a9083016SGiridhar Malavali 2049a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2050a9083016SGiridhar Malavali 2051a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2052a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2053a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2054a9083016SGiridhar Malavali 2055a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2056a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2057a9083016SGiridhar Malavali 2058a9083016SGiridhar Malavali switch (stat & 0xff) { 2059a9083016SGiridhar Malavali case 0x1: 2060a9083016SGiridhar Malavali case 0x2: 2061a9083016SGiridhar Malavali case 0x10: 2062a9083016SGiridhar Malavali case 0x11: 2063a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2064a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2065a9083016SGiridhar Malavali break; 2066a9083016SGiridhar Malavali case 0x12: 2067a9083016SGiridhar Malavali mb[0] = MSW(stat); 2068a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2069a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2070a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2071a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2072a9083016SGiridhar Malavali break; 2073a9083016SGiridhar Malavali case 0x13: 2074a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2075a9083016SGiridhar Malavali break; 2076a9083016SGiridhar Malavali default: 20777c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2078a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20797c3df132SSaurav Kashyap stat & 0xff); 2080a9083016SGiridhar Malavali break; 2081a9083016SGiridhar Malavali } 2082a9083016SGiridhar Malavali } 2083a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2084a9083016SGiridhar Malavali } 2085a9083016SGiridhar Malavali 208636439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 208736439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 208836439832Sgurinder.shergill@hp.com 208936439832Sgurinder.shergill@hp.com if (!ha->flags.msi_enabled) 209036439832Sgurinder.shergill@hp.com qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 209136439832Sgurinder.shergill@hp.com 2092a9083016SGiridhar Malavali return IRQ_HANDLED; 2093a9083016SGiridhar Malavali } 2094a9083016SGiridhar Malavali 2095a9083016SGiridhar Malavali irqreturn_t 2096a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2097a9083016SGiridhar Malavali { 2098a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2099a9083016SGiridhar Malavali struct qla_hw_data *ha; 2100a9083016SGiridhar Malavali struct rsp_que *rsp; 2101a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2102a9083016SGiridhar Malavali int status = 0; 2103a9083016SGiridhar Malavali unsigned long flags; 21047c3df132SSaurav Kashyap uint32_t stat = 0; 2105f3ddac19SChad Dupuis uint32_t host_int = 0; 2106a9083016SGiridhar Malavali uint16_t mb[4]; 2107a9083016SGiridhar Malavali 2108a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2109a9083016SGiridhar Malavali if (!rsp) { 2110a9083016SGiridhar Malavali printk(KERN_INFO 21117c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2112a9083016SGiridhar Malavali return IRQ_NONE; 2113a9083016SGiridhar Malavali } 2114a9083016SGiridhar Malavali ha = rsp->hw; 2115a9083016SGiridhar Malavali 2116a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2117a9083016SGiridhar Malavali 2118a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2119a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2120a9083016SGiridhar Malavali do { 2121f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2122f3ddac19SChad Dupuis if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2123f3ddac19SChad Dupuis break; 2124f3ddac19SChad Dupuis if (host_int) { 2125a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2126a9083016SGiridhar Malavali 2127a9083016SGiridhar Malavali switch (stat & 0xff) { 2128a9083016SGiridhar Malavali case 0x1: 2129a9083016SGiridhar Malavali case 0x2: 2130a9083016SGiridhar Malavali case 0x10: 2131a9083016SGiridhar Malavali case 0x11: 2132a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2133a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2134a9083016SGiridhar Malavali break; 2135a9083016SGiridhar Malavali case 0x12: 2136a9083016SGiridhar Malavali mb[0] = MSW(stat); 2137a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2138a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2139a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2140a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2141a9083016SGiridhar Malavali break; 2142a9083016SGiridhar Malavali case 0x13: 2143a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2144a9083016SGiridhar Malavali break; 2145a9083016SGiridhar Malavali default: 21467c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2147a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21487c3df132SSaurav Kashyap stat & 0xff); 2149a9083016SGiridhar Malavali break; 2150a9083016SGiridhar Malavali } 2151a9083016SGiridhar Malavali } 2152a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2153a9083016SGiridhar Malavali } while (0); 2154a9083016SGiridhar Malavali 215536439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 215636439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 215736439832Sgurinder.shergill@hp.com 2158a9083016SGiridhar Malavali return IRQ_HANDLED; 2159a9083016SGiridhar Malavali } 2160a9083016SGiridhar Malavali 2161a9083016SGiridhar Malavali irqreturn_t 2162a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2163a9083016SGiridhar Malavali { 2164a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2165a9083016SGiridhar Malavali struct qla_hw_data *ha; 2166a9083016SGiridhar Malavali struct rsp_que *rsp; 2167a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 21683553d343SSaurav Kashyap unsigned long flags; 2169f3ddac19SChad Dupuis uint32_t host_int = 0; 2170a9083016SGiridhar Malavali 2171a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2172a9083016SGiridhar Malavali if (!rsp) { 2173a9083016SGiridhar Malavali printk(KERN_INFO 21747c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2175a9083016SGiridhar Malavali return IRQ_NONE; 2176a9083016SGiridhar Malavali } 2177a9083016SGiridhar Malavali 2178a9083016SGiridhar Malavali ha = rsp->hw; 2179a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 21803553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2181a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2182f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2183f3ddac19SChad Dupuis if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2184f3ddac19SChad Dupuis goto out; 2185a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2186a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2187f3ddac19SChad Dupuis out: 21883553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2189a9083016SGiridhar Malavali return IRQ_HANDLED; 2190a9083016SGiridhar Malavali } 2191a9083016SGiridhar Malavali 2192a9083016SGiridhar Malavali void 2193a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2194a9083016SGiridhar Malavali { 2195a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2196a9083016SGiridhar Malavali struct qla_hw_data *ha; 2197a9083016SGiridhar Malavali struct rsp_que *rsp; 2198a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2199a9083016SGiridhar Malavali int status = 0; 2200a9083016SGiridhar Malavali uint32_t stat; 2201f3ddac19SChad Dupuis uint32_t host_int = 0; 2202a9083016SGiridhar Malavali uint16_t mb[4]; 2203a9083016SGiridhar Malavali unsigned long flags; 2204a9083016SGiridhar Malavali 2205a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2206a9083016SGiridhar Malavali if (!rsp) { 2207a9083016SGiridhar Malavali printk(KERN_INFO 22087c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2209a9083016SGiridhar Malavali return; 2210a9083016SGiridhar Malavali } 2211a9083016SGiridhar Malavali ha = rsp->hw; 2212a9083016SGiridhar Malavali 2213a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2214a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2215a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2216a9083016SGiridhar Malavali 2217f3ddac19SChad Dupuis host_int = RD_REG_DWORD(®->host_int); 2218f3ddac19SChad Dupuis if (qla2x00_check_reg_for_disconnect(vha, host_int)) 2219f3ddac19SChad Dupuis goto out; 2220f3ddac19SChad Dupuis if (host_int) { 2221a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2222a9083016SGiridhar Malavali switch (stat & 0xff) { 2223a9083016SGiridhar Malavali case 0x1: 2224a9083016SGiridhar Malavali case 0x2: 2225a9083016SGiridhar Malavali case 0x10: 2226a9083016SGiridhar Malavali case 0x11: 2227a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2228a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2229a9083016SGiridhar Malavali break; 2230a9083016SGiridhar Malavali case 0x12: 2231a9083016SGiridhar Malavali mb[0] = MSW(stat); 2232a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2233a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2234a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2235a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2236a9083016SGiridhar Malavali break; 2237a9083016SGiridhar Malavali case 0x13: 2238a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2239a9083016SGiridhar Malavali break; 2240a9083016SGiridhar Malavali default: 22417c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22427c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22437c3df132SSaurav Kashyap stat * 0xff); 2244a9083016SGiridhar Malavali break; 2245a9083016SGiridhar Malavali } 2246a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 224702a9ae6eSAtul Deshmukh } 2248f3ddac19SChad Dupuis out: 2249a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2250a9083016SGiridhar Malavali } 2251a9083016SGiridhar Malavali 2252a9083016SGiridhar Malavali void 2253a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2254a9083016SGiridhar Malavali { 2255a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2256a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2257a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22587ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22597ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 22607ec0effdSAtul Deshmukh else 2261a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2262a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2263a9083016SGiridhar Malavali ha->interrupts_on = 1; 2264a9083016SGiridhar Malavali } 2265a9083016SGiridhar Malavali 2266a9083016SGiridhar Malavali void 2267a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2268a9083016SGiridhar Malavali { 2269a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2270a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2271a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22727ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22737ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 22747ec0effdSAtul Deshmukh else 2275a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2276a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2277a9083016SGiridhar Malavali ha->interrupts_on = 0; 2278a9083016SGiridhar Malavali } 2279a9083016SGiridhar Malavali 2280a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2281a9083016SGiridhar Malavali { 2282a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2283a9083016SGiridhar Malavali 2284a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2285a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2286a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2287a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2288a9083016SGiridhar Malavali ha->curr_window = 255; 2289a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2290a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2291a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2292a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2293a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2294a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2295a9083016SGiridhar Malavali } 2296a9083016SGiridhar Malavali 2297a5b36321SLalit Chandivade inline void 22980251ce8cSSaurav Kashyap qla82xx_set_idc_version(scsi_qla_host_t *vha) 22990251ce8cSSaurav Kashyap { 23000251ce8cSSaurav Kashyap int idc_ver; 23010251ce8cSSaurav Kashyap uint32_t drv_active; 23020251ce8cSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 23030251ce8cSSaurav Kashyap 23040251ce8cSSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 23050251ce8cSSaurav Kashyap if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 23060251ce8cSSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 23070251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION); 23080251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb082, 23090251ce8cSSaurav Kashyap "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 23100251ce8cSSaurav Kashyap } else { 23110251ce8cSSaurav Kashyap idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 23120251ce8cSSaurav Kashyap if (idc_ver != QLA82XX_IDC_VERSION) 23130251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb083, 23140251ce8cSSaurav Kashyap "qla2xxx driver IDC version %d is not compatible " 23150251ce8cSSaurav Kashyap "with IDC version %d of the other drivers\n", 23160251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION, idc_ver); 23170251ce8cSSaurav Kashyap } 23180251ce8cSSaurav Kashyap } 23190251ce8cSSaurav Kashyap 23200251ce8cSSaurav Kashyap inline void 2321a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2322a9083016SGiridhar Malavali { 2323a9083016SGiridhar Malavali uint32_t drv_active; 2324a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2325a9083016SGiridhar Malavali 2326a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2327a9083016SGiridhar Malavali 2328a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2329a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 233077e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 233177e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2332a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2333a9083016SGiridhar Malavali } 233477e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2335a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2336a9083016SGiridhar Malavali } 2337a9083016SGiridhar Malavali 2338a9083016SGiridhar Malavali inline void 2339a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2340a9083016SGiridhar Malavali { 2341a9083016SGiridhar Malavali uint32_t drv_active; 2342a9083016SGiridhar Malavali 2343a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 234477e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2345a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2346a9083016SGiridhar Malavali } 2347a9083016SGiridhar Malavali 2348a9083016SGiridhar Malavali static inline int 2349a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2350a9083016SGiridhar Malavali { 2351a9083016SGiridhar Malavali uint32_t drv_state; 2352a9083016SGiridhar Malavali int rval; 2353a9083016SGiridhar Malavali 23547d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 235508de2844SGiridhar Malavali return 1; 235608de2844SGiridhar Malavali else { 2357a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 235877e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2359a9083016SGiridhar Malavali return rval; 2360a9083016SGiridhar Malavali } 236108de2844SGiridhar Malavali } 2362a9083016SGiridhar Malavali 2363a9083016SGiridhar Malavali static inline void 2364a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2365a9083016SGiridhar Malavali { 2366a9083016SGiridhar Malavali uint32_t drv_state; 2367a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2368a9083016SGiridhar Malavali 2369a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2370a9083016SGiridhar Malavali 2371a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2372a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 237377e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2374a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2375a9083016SGiridhar Malavali } 2376a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 237708de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 237808de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2379a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2380a9083016SGiridhar Malavali } 2381a9083016SGiridhar Malavali 2382a9083016SGiridhar Malavali static inline void 2383a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2384a9083016SGiridhar Malavali { 2385a9083016SGiridhar Malavali uint32_t drv_state; 2386a9083016SGiridhar Malavali 2387a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2388a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2389a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2390a9083016SGiridhar Malavali } 2391a9083016SGiridhar Malavali 2392a9083016SGiridhar Malavali static inline void 2393a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2394a9083016SGiridhar Malavali { 2395a9083016SGiridhar Malavali uint32_t qsnt_state; 2396a9083016SGiridhar Malavali 2397a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2398a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2399a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2400a9083016SGiridhar Malavali } 2401a9083016SGiridhar Malavali 2402579d12b5SSaurav Kashyap void 2403579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2404579d12b5SSaurav Kashyap { 2405579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2406579d12b5SSaurav Kashyap uint32_t qsnt_state; 2407579d12b5SSaurav Kashyap 2408579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2409579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2410579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2411579d12b5SSaurav Kashyap } 2412579d12b5SSaurav Kashyap 241377e334d2SGiridhar Malavali static int 241477e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2415a9083016SGiridhar Malavali { 2416a9083016SGiridhar Malavali int rst; 2417a9083016SGiridhar Malavali struct fw_blob *blob; 2418a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2419a9083016SGiridhar Malavali 2420a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24227c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2423a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2424a9083016SGiridhar Malavali } 2425a9083016SGiridhar Malavali udelay(500); 2426a9083016SGiridhar Malavali 2427a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2428a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2429a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2430a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2431a9083016SGiridhar Malavali 2432a9083016SGiridhar Malavali /* 2433a9083016SGiridhar Malavali * FW Load priority: 2434a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2435a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2436a9083016SGiridhar Malavali */ 2437a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2438a9083016SGiridhar Malavali goto try_blob_fw; 2439a9083016SGiridhar Malavali 24407c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24417c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2442a9083016SGiridhar Malavali 2443a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24447c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 244500adc9a0SSaurav Kashyap "Firmware loaded successfully from flash.\n"); 2446a9083016SGiridhar Malavali return QLA_SUCCESS; 2447875efad7SChad Dupuis } else { 24487c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24497c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2450a9083016SGiridhar Malavali } 2451875efad7SChad Dupuis 2452a9083016SGiridhar Malavali try_blob_fw: 24537c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24547c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2455a9083016SGiridhar Malavali 2456a9083016SGiridhar Malavali /* Load firmware blob. */ 2457a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2458a9083016SGiridhar Malavali if (!blob) { 24597c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 246000adc9a0SSaurav Kashyap "Firmware image not present.\n"); 2461a9083016SGiridhar Malavali goto fw_load_failed; 2462a9083016SGiridhar Malavali } 2463a9083016SGiridhar Malavali 24649c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24659c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24669c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24679c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24689c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24699c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24717c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24729c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24739c2b2975SHarish Zunjarrao } 24749c2b2975SHarish Zunjarrao } 24759c2b2975SHarish Zunjarrao 2476a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24777c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24787c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2479a9083016SGiridhar Malavali return QLA_SUCCESS; 2480a9083016SGiridhar Malavali } else { 24817c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24827c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2483a9083016SGiridhar Malavali blob->fw = NULL; 2484a9083016SGiridhar Malavali blob = NULL; 2485a9083016SGiridhar Malavali goto fw_load_failed; 2486a9083016SGiridhar Malavali } 2487a9083016SGiridhar Malavali return QLA_SUCCESS; 2488a9083016SGiridhar Malavali 2489a9083016SGiridhar Malavali fw_load_failed: 2490a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2491a9083016SGiridhar Malavali } 2492a9083016SGiridhar Malavali 2493a5b36321SLalit Chandivade int 2494a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2495a9083016SGiridhar Malavali { 2496a9083016SGiridhar Malavali uint16_t lnk; 2497a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2498a9083016SGiridhar Malavali 2499a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 250077e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2501a9083016SGiridhar Malavali 25023711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 25033711333dSGiridhar Malavali * of 0 before resetting the hardware 25043711333dSGiridhar Malavali */ 25053711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25063711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25073711333dSGiridhar Malavali 2508a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2509a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2510a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2511a9083016SGiridhar Malavali 2512a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25137c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25147c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2515a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2516a9083016SGiridhar Malavali } 2517a9083016SGiridhar Malavali 2518a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2519a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25207c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25217c3df132SSaurav Kashyap "Error during card handshake.\n"); 2522a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2523a9083016SGiridhar Malavali } 2524a9083016SGiridhar Malavali 2525a9083016SGiridhar Malavali /* Negotiated Link width */ 252610092438SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2527a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2528a9083016SGiridhar Malavali 2529a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2530a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2531a9083016SGiridhar Malavali } 2532a9083016SGiridhar Malavali 253377e334d2SGiridhar Malavali static uint32_t * 2534a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2535a9083016SGiridhar Malavali uint32_t length) 2536a9083016SGiridhar Malavali { 2537a9083016SGiridhar Malavali uint32_t i; 2538a9083016SGiridhar Malavali uint32_t val; 2539a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2540a9083016SGiridhar Malavali 2541a9083016SGiridhar Malavali /* Dword reads to flash. */ 2542a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2543a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25447c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25457c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2546a9083016SGiridhar Malavali goto done_read; 2547a9083016SGiridhar Malavali } 2548a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 2549a9083016SGiridhar Malavali } 2550a9083016SGiridhar Malavali done_read: 2551a9083016SGiridhar Malavali return dwptr; 2552a9083016SGiridhar Malavali } 2553a9083016SGiridhar Malavali 255477e334d2SGiridhar Malavali static int 2555a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2556a9083016SGiridhar Malavali { 2557a9083016SGiridhar Malavali int ret; 2558a9083016SGiridhar Malavali uint32_t val; 25597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2560a9083016SGiridhar Malavali 2561a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2562a9083016SGiridhar Malavali if (ret < 0) { 25637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25647c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2565a9083016SGiridhar Malavali return ret; 2566a9083016SGiridhar Malavali } 2567a9083016SGiridhar Malavali 2568a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2569a9083016SGiridhar Malavali if (ret < 0) 2570a9083016SGiridhar Malavali goto done_unprotect; 2571a9083016SGiridhar Malavali 25720547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2573a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2574a9083016SGiridhar Malavali if (ret < 0) { 25750547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2576a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2577a9083016SGiridhar Malavali } 2578a9083016SGiridhar Malavali 2579a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25807c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 25817c3df132SSaurav Kashyap "Write disable failed.\n"); 2582a9083016SGiridhar Malavali 2583a9083016SGiridhar Malavali done_unprotect: 2584d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2585a9083016SGiridhar Malavali return ret; 2586a9083016SGiridhar Malavali } 2587a9083016SGiridhar Malavali 258877e334d2SGiridhar Malavali static int 2589a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2590a9083016SGiridhar Malavali { 2591a9083016SGiridhar Malavali int ret; 2592a9083016SGiridhar Malavali uint32_t val; 25937c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2594a9083016SGiridhar Malavali 2595a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2596a9083016SGiridhar Malavali if (ret < 0) { 25977c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 25987c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2599a9083016SGiridhar Malavali return ret; 2600a9083016SGiridhar Malavali } 2601a9083016SGiridhar Malavali 2602a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2603a9083016SGiridhar Malavali if (ret < 0) 2604a9083016SGiridhar Malavali goto done_protect; 2605a9083016SGiridhar Malavali 26060547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2607a9083016SGiridhar Malavali /* LOCK all sectors */ 2608a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2609a9083016SGiridhar Malavali if (ret < 0) 26107c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 26117c3df132SSaurav Kashyap "Write status register failed.\n"); 2612a9083016SGiridhar Malavali 2613a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 26147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 26157c3df132SSaurav Kashyap "Write disable failed.\n"); 2616a9083016SGiridhar Malavali done_protect: 2617d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2618a9083016SGiridhar Malavali return ret; 2619a9083016SGiridhar Malavali } 2620a9083016SGiridhar Malavali 262177e334d2SGiridhar Malavali static int 2622a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2623a9083016SGiridhar Malavali { 2624a9083016SGiridhar Malavali int ret = 0; 26257c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2626a9083016SGiridhar Malavali 2627a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2628a9083016SGiridhar Malavali if (ret < 0) { 26297c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26307c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2631a9083016SGiridhar Malavali return ret; 2632a9083016SGiridhar Malavali } 2633a9083016SGiridhar Malavali 2634a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2635a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2636a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2637a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2638a9083016SGiridhar Malavali 2639a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26417c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2642a9083016SGiridhar Malavali ret = -1; 2643a9083016SGiridhar Malavali goto done; 2644a9083016SGiridhar Malavali } 2645a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2646a9083016SGiridhar Malavali done: 2647d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2648a9083016SGiridhar Malavali return ret; 2649a9083016SGiridhar Malavali } 2650a9083016SGiridhar Malavali 2651a9083016SGiridhar Malavali /* 2652a9083016SGiridhar Malavali * Address and length are byte address 2653a9083016SGiridhar Malavali */ 2654a9083016SGiridhar Malavali uint8_t * 2655a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2656a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2657a9083016SGiridhar Malavali { 2658a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2659a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2660a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2661a9083016SGiridhar Malavali return buf; 2662a9083016SGiridhar Malavali } 2663a9083016SGiridhar Malavali 2664a9083016SGiridhar Malavali static int 2665a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2666a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2667a9083016SGiridhar Malavali { 2668a9083016SGiridhar Malavali int ret; 2669a9083016SGiridhar Malavali uint32_t liter; 2670a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 2671a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2672a9083016SGiridhar Malavali void *optrom = NULL; 2673a9083016SGiridhar Malavali int page_mode = 0; 2674a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2675a9083016SGiridhar Malavali 2676a9083016SGiridhar Malavali ret = -1; 2677a9083016SGiridhar Malavali 2678a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2679a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2680a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2681a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2682a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2683a9083016SGiridhar Malavali if (!optrom) { 26847c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 26857c3df132SSaurav Kashyap "Unable to allocate memory " 268600adc9a0SSaurav Kashyap "for optrom burst write (%x KB).\n", 2687a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2688a9083016SGiridhar Malavali } 2689a9083016SGiridhar Malavali } 2690a9083016SGiridhar Malavali 2691a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2692a9083016SGiridhar Malavali sec_mask = ~rest_addr; 2693a9083016SGiridhar Malavali 2694a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2695a9083016SGiridhar Malavali if (ret) { 26967c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2697a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2698a9083016SGiridhar Malavali goto write_done; 2699a9083016SGiridhar Malavali } 2700a9083016SGiridhar Malavali 2701a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2702a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2703a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2704a9083016SGiridhar Malavali 2705a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2706a9083016SGiridhar Malavali if (ret) { 27077c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 27087c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 27097c3df132SSaurav Kashyap faddr); 2710a9083016SGiridhar Malavali break; 2711a9083016SGiridhar Malavali } 2712a9083016SGiridhar Malavali } 2713a9083016SGiridhar Malavali 2714a9083016SGiridhar Malavali /* Go with burst-write. */ 2715a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2716a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2717a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2718a9083016SGiridhar Malavali 2719a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2720a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2721a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2722a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 27237c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2724a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2725a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2726a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2727a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2729a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2730a9083016SGiridhar Malavali 2731a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2732a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2733a9083016SGiridhar Malavali optrom = NULL; 2734a9083016SGiridhar Malavali } else { 2735a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2736a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2737a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2738a9083016SGiridhar Malavali continue; 2739a9083016SGiridhar Malavali } 2740a9083016SGiridhar Malavali } 2741a9083016SGiridhar Malavali 2742a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 2743a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 2744a9083016SGiridhar Malavali if (ret) { 27457c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27467c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27477c3df132SSaurav Kashyap faddr, *dwptr); 2748a9083016SGiridhar Malavali break; 2749a9083016SGiridhar Malavali } 2750a9083016SGiridhar Malavali } 2751a9083016SGiridhar Malavali 2752a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2753a9083016SGiridhar Malavali if (ret) 27547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2755a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2756a9083016SGiridhar Malavali write_done: 2757a9083016SGiridhar Malavali if (optrom) 2758a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2759a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2760a9083016SGiridhar Malavali return ret; 2761a9083016SGiridhar Malavali } 2762a9083016SGiridhar Malavali 2763a9083016SGiridhar Malavali int 2764a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2765a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2766a9083016SGiridhar Malavali { 2767a9083016SGiridhar Malavali int rval; 2768a9083016SGiridhar Malavali 2769a9083016SGiridhar Malavali /* Suspend HBA. */ 2770a9083016SGiridhar Malavali scsi_block_requests(vha->host); 2771a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2772a9083016SGiridhar Malavali length >> 2); 2773a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2774a9083016SGiridhar Malavali 2775a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2776a9083016SGiridhar Malavali if (rval) 2777a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2778a9083016SGiridhar Malavali else 2779a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2780a9083016SGiridhar Malavali return rval; 2781a9083016SGiridhar Malavali } 2782a9083016SGiridhar Malavali 2783a9083016SGiridhar Malavali void 27845162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2785a9083016SGiridhar Malavali { 27865162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2787a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2788a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2789a9083016SGiridhar Malavali uint32_t dbval; 2790a9083016SGiridhar Malavali 2791a9083016SGiridhar Malavali /* Adjust ring index. */ 2792a9083016SGiridhar Malavali req->ring_index++; 2793a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2794a9083016SGiridhar Malavali req->ring_index = 0; 2795a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2796a9083016SGiridhar Malavali } else 2797a9083016SGiridhar Malavali req->ring_ptr++; 2798a9083016SGiridhar Malavali 2799a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2800a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2801a9083016SGiridhar Malavali 2802a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 28036907869dSGiridhar Malavali if (ql2xdbwr) 28046907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 28056907869dSGiridhar Malavali else { 2806a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2807a9083016SGiridhar Malavali wmb(); 2808fa492630SSaurav Kashyap while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 28096907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 28106907869dSGiridhar Malavali dbval); 2811a9083016SGiridhar Malavali wmb(); 2812a9083016SGiridhar Malavali } 2813a9083016SGiridhar Malavali } 28146907869dSGiridhar Malavali } 2815a9083016SGiridhar Malavali 2816fa492630SSaurav Kashyap static void 2817fa492630SSaurav Kashyap qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2818e6a4202aSShyam Sundar { 28197c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 28204babb90eSHiral Patel uint32_t lock_owner = 0; 28217c3df132SSaurav Kashyap 28224babb90eSHiral Patel if (qla82xx_rom_lock(ha)) { 28234babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2824e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 28257c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 28264babb90eSHiral Patel "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 28274babb90eSHiral Patel } 2828e6a4202aSShyam Sundar /* 2829e6a4202aSShyam Sundar * Either we got the lock, or someone 2830e6a4202aSShyam Sundar * else died while holding it. 2831e6a4202aSShyam Sundar * In either case, unlock. 2832e6a4202aSShyam Sundar */ 2833d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2834e6a4202aSShyam Sundar } 2835e6a4202aSShyam Sundar 2836a9083016SGiridhar Malavali /* 2837a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2838a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2839a9083016SGiridhar Malavali * 2840a9083016SGiridhar Malavali * Note: 2841a9083016SGiridhar Malavali * IDC lock must be held upon entry 2842a9083016SGiridhar Malavali * 2843a9083016SGiridhar Malavali * Return: 2844a9083016SGiridhar Malavali * Success : 0 2845a9083016SGiridhar Malavali * Failed : 1 2846a9083016SGiridhar Malavali */ 2847a9083016SGiridhar Malavali static int 2848a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2849a9083016SGiridhar Malavali { 2850e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 2851e6a4202aSShyam Sundar int i, timeout; 2852a9083016SGiridhar Malavali uint32_t old_count, count; 2853a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2854e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 2855a9083016SGiridhar Malavali 2856e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2857a9083016SGiridhar Malavali 2858a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2859a9083016SGiridhar Malavali 2860a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 2861a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 2862a9083016SGiridhar Malavali if (timeout) { 2863a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 28647d613ac6SSantosh Vernekar QLA8XXX_DEV_FAILED); 2865a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2866a9083016SGiridhar Malavali } 2867a9083016SGiridhar Malavali 2868a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2869a9083016SGiridhar Malavali if (count != old_count) 2870e6a4202aSShyam Sundar peg_stuck = 0; 2871e6a4202aSShyam Sundar } 2872e6a4202aSShyam Sundar 2873e6a4202aSShyam Sundar if (need_reset) { 2874e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 2875e6a4202aSShyam Sundar if (peg_stuck) 2876e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2877e6a4202aSShyam Sundar goto dev_initialize; 2878e6a4202aSShyam Sundar } else { 2879e6a4202aSShyam Sundar /* Start of day for this ha context. */ 2880e6a4202aSShyam Sundar if (peg_stuck) { 2881e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 2882e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2883e6a4202aSShyam Sundar goto dev_initialize; 2884e6a4202aSShyam Sundar } else 2885e6a4202aSShyam Sundar /* Firmware already running. */ 2886a9083016SGiridhar Malavali goto dev_ready; 2887a9083016SGiridhar Malavali } 2888a9083016SGiridhar Malavali 2889e6a4202aSShyam Sundar return rval; 2890e6a4202aSShyam Sundar 2891a9083016SGiridhar Malavali dev_initialize: 2892a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28937c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28947c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 28957d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2896a9083016SGiridhar Malavali 2897a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2898a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2899a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2900a9083016SGiridhar Malavali 2901a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 29027c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 29037c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2904a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 29057d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2906a9083016SGiridhar Malavali return rval; 2907a9083016SGiridhar Malavali } 2908a9083016SGiridhar Malavali 2909a9083016SGiridhar Malavali dev_ready: 29107c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 29117c3df132SSaurav Kashyap "HW State: READY.\n"); 29127d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2913a9083016SGiridhar Malavali 2914a9083016SGiridhar Malavali return QLA_SUCCESS; 2915a9083016SGiridhar Malavali } 2916a9083016SGiridhar Malavali 2917579d12b5SSaurav Kashyap /* 2918579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2919579d12b5SSaurav Kashyap * Code to start quiescence sequence 2920579d12b5SSaurav Kashyap * 2921579d12b5SSaurav Kashyap * Note: 2922579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2923579d12b5SSaurav Kashyap * 2924579d12b5SSaurav Kashyap * Return: void 2925579d12b5SSaurav Kashyap */ 2926579d12b5SSaurav Kashyap 2927579d12b5SSaurav Kashyap static void 2928579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2929579d12b5SSaurav Kashyap { 2930579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2931579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2932579d12b5SSaurav Kashyap unsigned long reset_timeout; 2933579d12b5SSaurav Kashyap 2934579d12b5SSaurav Kashyap if (vha->flags.online) { 2935579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 29368fcd6b8bSChad Dupuis qla2x00_quiesce_io(vha); 2937579d12b5SSaurav Kashyap } 2938579d12b5SSaurav Kashyap 2939579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2940579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2941579d12b5SSaurav Kashyap 2942579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2943579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2944579d12b5SSaurav Kashyap 2945579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2946579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2947579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2948579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2949579d12b5SSaurav Kashyap 2950579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2951579d12b5SSaurav Kashyap 2952579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2953579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2954579d12b5SSaurav Kashyap * changing the state to DEV_READY 2955579d12b5SSaurav Kashyap */ 29567c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29575f28d2d7SSaurav Kashyap "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 29585f28d2d7SSaurav Kashyap "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 29597c3df132SSaurav Kashyap drv_active, drv_state); 2960579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 29617d613ac6SSantosh Vernekar QLA8XXX_DEV_READY); 29627c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29637c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2964579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2965579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2966579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2967579d12b5SSaurav Kashyap 2968579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2969579d12b5SSaurav Kashyap return; 2970579d12b5SSaurav Kashyap } 2971579d12b5SSaurav Kashyap 2972579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2973579d12b5SSaurav Kashyap msleep(1000); 2974579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2975579d12b5SSaurav Kashyap 2976579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2977579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2978579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2979579d12b5SSaurav Kashyap } 2980579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2981579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 29827d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 29837c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29847c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 29857d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2986579d12b5SSaurav Kashyap } 2987579d12b5SSaurav Kashyap } 2988579d12b5SSaurav Kashyap 2989579d12b5SSaurav Kashyap /* 2990579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2991579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2992579d12b5SSaurav Kashyap * 2993579d12b5SSaurav Kashyap * Note: 2994579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2995579d12b5SSaurav Kashyap * 2996579d12b5SSaurav Kashyap * Return: 2997579d12b5SSaurav Kashyap * Changed device state. 2998579d12b5SSaurav Kashyap */ 2999579d12b5SSaurav Kashyap uint32_t 3000579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3001579d12b5SSaurav Kashyap { 3002579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3003579d12b5SSaurav Kashyap uint32_t dev_state; 3004579d12b5SSaurav Kashyap 3005579d12b5SSaurav Kashyap do { 3006579d12b5SSaurav Kashyap msleep(1000); 3007579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3008579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3009579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3010579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3011579d12b5SSaurav Kashyap 3012579d12b5SSaurav Kashyap return dev_state; 3013579d12b5SSaurav Kashyap } 3014579d12b5SSaurav Kashyap 30157d613ac6SSantosh Vernekar void 30167d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 3017a9083016SGiridhar Malavali { 3018a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3019a9083016SGiridhar Malavali 3020a9083016SGiridhar Malavali /* Disable the board */ 30217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 30227c3df132SSaurav Kashyap "Disabling the board.\n"); 3023a9083016SGiridhar Malavali 30241459c0e1SSaurav Kashyap if (IS_QLA82XX(ha)) { 3025b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3026b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 30277ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) { 3028c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha); 30297ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 30301459c0e1SSaurav Kashyap } 3031b963752fSGiridhar Malavali 3032a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3033a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3034a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3035a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3036a9083016SGiridhar Malavali vha->flags.online = 0; 3037a9083016SGiridhar Malavali vha->flags.init_done = 0; 3038a9083016SGiridhar Malavali } 3039a9083016SGiridhar Malavali 3040a9083016SGiridhar Malavali /* 3041a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3042a9083016SGiridhar Malavali * Code to start reset sequence 3043a9083016SGiridhar Malavali * 3044a9083016SGiridhar Malavali * Note: 3045a9083016SGiridhar Malavali * IDC lock must be held upon entry 3046a9083016SGiridhar Malavali * 3047a9083016SGiridhar Malavali * Return: 3048a9083016SGiridhar Malavali * Success : 0 3049a9083016SGiridhar Malavali * Failed : 1 3050a9083016SGiridhar Malavali */ 3051a9083016SGiridhar Malavali static void 3052a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3053a9083016SGiridhar Malavali { 3054e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3055e5fdae55SChad Dupuis uint32_t active_mask = 0; 3056a9083016SGiridhar Malavali unsigned long reset_timeout; 3057a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3058a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3059a9083016SGiridhar Malavali 3060a9083016SGiridhar Malavali if (vha->flags.online) { 3061a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3062a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3063a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3064a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3065a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3066a9083016SGiridhar Malavali } 3067a9083016SGiridhar Malavali 306808de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30697d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_owner) { 307008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 307108de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3072a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 307308de2844SGiridhar Malavali } else { 307408de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 307508de2844SGiridhar Malavali drv_active &= active_mask; 307608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 307708de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 307808de2844SGiridhar Malavali } 3079a9083016SGiridhar Malavali 3080a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 30817d613ac6SSantosh Vernekar reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3082a9083016SGiridhar Malavali 3083a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3084a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 308508de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3086a9083016SGiridhar Malavali 308708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 308808de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 308908de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 309008de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 309108de2844SGiridhar Malavali 309208de2844SGiridhar Malavali while (drv_state != drv_active && 30937d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_INITIALIZING) { 3094a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30957c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30967c3df132SSaurav Kashyap "Reset timeout.\n"); 3097a9083016SGiridhar Malavali break; 3098a9083016SGiridhar Malavali } 3099a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3100a9083016SGiridhar Malavali msleep(1000); 3101a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3102a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3103a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 31047d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 310508de2844SGiridhar Malavali drv_active &= active_mask; 310608de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3107a9083016SGiridhar Malavali } 3108a9083016SGiridhar Malavali 310908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 311008de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 311108de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 311208de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 311308de2844SGiridhar Malavali 31147c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 31157c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 31167c3df132SSaurav Kashyap dev_state, 311708de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3118f1af6208SGiridhar Malavali 3119a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 31207d613ac6SSantosh Vernekar if (dev_state != QLA8XXX_DEV_INITIALIZING && 31217d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_COLD) { 31227c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 31237c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 31247d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3125f4e1648aSVikas Chaudhary qla82xx_set_rst_ready(ha); 312608de2844SGiridhar Malavali if (ql2xmdenable) { 312708de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 312808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 3129b6d0d9d5SGiridhar Malavali "Minidump not collected.\n"); 313008de2844SGiridhar Malavali } else 313108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 313208de2844SGiridhar Malavali "Minidump disabled.\n"); 3133a9083016SGiridhar Malavali } 3134a9083016SGiridhar Malavali } 3135a9083016SGiridhar Malavali 31363173167fSGiridhar Malavali int 313708de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 313808de2844SGiridhar Malavali { 313908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 314008de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 31413173167fSGiridhar Malavali int rval = QLA_SUCCESS; 314208de2844SGiridhar Malavali 31433173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 31443173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 31453173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 31463173167fSGiridhar Malavali 31476246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31483173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31493173167fSGiridhar Malavali return rval; 31503173167fSGiridhar Malavali 31513173167fSGiridhar Malavali if (ql2xmdenable) { 315208de2844SGiridhar Malavali if (!ha->fw_dumped) { 3153edaa5c74SSaurav Kashyap if ((fw_major_version != ha->fw_major_version || 315408de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 3155edaa5c74SSaurav Kashyap fw_subminor_version != ha->fw_subminor_version) || 3156edaa5c74SSaurav Kashyap (ha->prev_minidump_failed)) { 31577ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3158edaa5c74SSaurav Kashyap "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 31599bc3bf27SGiridhar Malavali fw_major_version, fw_minor_version, 31609bc3bf27SGiridhar Malavali fw_subminor_version, 316108de2844SGiridhar Malavali ha->fw_major_version, 31623173167fSGiridhar Malavali ha->fw_minor_version, 3163edaa5c74SSaurav Kashyap ha->fw_subminor_version, 3164edaa5c74SSaurav Kashyap ha->prev_minidump_failed); 316508de2844SGiridhar Malavali /* Release MiniDump resources */ 316608de2844SGiridhar Malavali qla82xx_md_free(vha); 316708de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 316808de2844SGiridhar Malavali qla82xx_md_prep(vha); 31692e264269SGiridhar Malavali } 317008de2844SGiridhar Malavali } else 317108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3172d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 317308de2844SGiridhar Malavali } 31743173167fSGiridhar Malavali return rval; 31753173167fSGiridhar Malavali } 317608de2844SGiridhar Malavali 317708de2844SGiridhar Malavali 3178fa492630SSaurav Kashyap static int 3179a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3180a9083016SGiridhar Malavali { 31817190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31827190575fSGiridhar Malavali int status = 0; 3183a9083016SGiridhar Malavali 31847190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31857190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3186a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31877c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31887c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31897c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31907c3df132SSaurav Kashyap "returning status=%d.\n", status); 31917190575fSGiridhar Malavali return status; 31927c3df132SSaurav Kashyap } 3193a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3194a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3195a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3196a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3197a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31987190575fSGiridhar Malavali status = 1; 3199a9083016SGiridhar Malavali } 3200efa786ccSLalit Chandivade } else 3201efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3202a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 32037c3df132SSaurav Kashyap if (status) 32047c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 32057c3df132SSaurav Kashyap "Returning status=%d.\n", status); 32067190575fSGiridhar Malavali return status; 3207a9083016SGiridhar Malavali } 3208a9083016SGiridhar Malavali 3209a9083016SGiridhar Malavali /* 3210a9083016SGiridhar Malavali * qla82xx_device_state_handler 3211a9083016SGiridhar Malavali * Main state handler 3212a9083016SGiridhar Malavali * 3213a9083016SGiridhar Malavali * Note: 3214a9083016SGiridhar Malavali * IDC lock must be held upon entry 3215a9083016SGiridhar Malavali * 3216a9083016SGiridhar Malavali * Return: 3217a9083016SGiridhar Malavali * Success : 0 3218a9083016SGiridhar Malavali * Failed : 1 3219a9083016SGiridhar Malavali */ 3220a9083016SGiridhar Malavali int 3221a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3222a9083016SGiridhar Malavali { 3223a9083016SGiridhar Malavali uint32_t dev_state; 322492dbf273SGiridhar Malavali uint32_t old_dev_state; 3225a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3226a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3227a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 322892dbf273SGiridhar Malavali int loopcount = 0; 3229a9083016SGiridhar Malavali 3230a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 32310251ce8cSSaurav Kashyap if (!vha->flags.init_done) { 3232a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 32330251ce8cSSaurav Kashyap qla82xx_set_idc_version(vha); 32340251ce8cSSaurav Kashyap } 3235a9083016SGiridhar Malavali 3236a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 323792dbf273SGiridhar Malavali old_dev_state = dev_state; 32387c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 32397c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32407c3df132SSaurav Kashyap dev_state, 324108de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3242a9083016SGiridhar Malavali 3243a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 32447d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3245a9083016SGiridhar Malavali 3246a9083016SGiridhar Malavali while (1) { 3247a9083016SGiridhar Malavali 3248a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32497c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32507c3df132SSaurav Kashyap "Device init failed.\n"); 3251a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3252a9083016SGiridhar Malavali break; 3253a9083016SGiridhar Malavali } 3254a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 325592dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 325692dbf273SGiridhar Malavali loopcount = 0; 325792dbf273SGiridhar Malavali old_dev_state = dev_state; 325892dbf273SGiridhar Malavali } 325992dbf273SGiridhar Malavali if (loopcount < 5) { 32607c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32617c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32627c3df132SSaurav Kashyap dev_state, 326308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32647c3df132SSaurav Kashyap "Unknown"); 326592dbf273SGiridhar Malavali } 3266f1af6208SGiridhar Malavali 3267a9083016SGiridhar Malavali switch (dev_state) { 32687d613ac6SSantosh Vernekar case QLA8XXX_DEV_READY: 32697d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 0; 32707916bb90SChad Dupuis goto rel_lock; 32717d613ac6SSantosh Vernekar case QLA8XXX_DEV_COLD: 3272a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 327308de2844SGiridhar Malavali break; 32747d613ac6SSantosh Vernekar case QLA8XXX_DEV_INITIALIZING: 3275a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3276a9083016SGiridhar Malavali msleep(1000); 3277a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3278a9083016SGiridhar Malavali break; 32797d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_RESET: 3280ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3281a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3282c8582ad9SSaurav Kashyap else { 3283c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3284c8582ad9SSaurav Kashyap msleep(1000); 3285c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3286c8582ad9SSaurav Kashyap } 32870060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32887d613ac6SSantosh Vernekar (ha->fcoe_dev_init_timeout * HZ); 3289a9083016SGiridhar Malavali break; 32907d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_QUIESCENT: 3291579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3292579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 32937d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3294579d12b5SSaurav Kashyap * HZ); 3295579d12b5SSaurav Kashyap break; 32967d613ac6SSantosh Vernekar case QLA8XXX_DEV_QUIESCENT: 3297579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3298579d12b5SSaurav Kashyap * to get changed 3299579d12b5SSaurav Kashyap */ 3300579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 33017916bb90SChad Dupuis goto rel_lock; 3302579d12b5SSaurav Kashyap 3303a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3304a9083016SGiridhar Malavali msleep(1000); 3305a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3306579d12b5SSaurav Kashyap 3307579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 33087d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ 3309579d12b5SSaurav Kashyap * HZ); 3310a9083016SGiridhar Malavali break; 33117d613ac6SSantosh Vernekar case QLA8XXX_DEV_FAILED: 33127d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(vha); 3313a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3314a9083016SGiridhar Malavali goto exit; 3315a9083016SGiridhar Malavali default: 3316a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3317a9083016SGiridhar Malavali msleep(1000); 3318a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3319a9083016SGiridhar Malavali } 332092dbf273SGiridhar Malavali loopcount++; 3321a9083016SGiridhar Malavali } 33227916bb90SChad Dupuis rel_lock: 3323a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 33247916bb90SChad Dupuis exit: 3325a9083016SGiridhar Malavali return rval; 3326a9083016SGiridhar Malavali } 3327a9083016SGiridhar Malavali 33285988aeb2SGiridhar Malavali static int qla82xx_check_temp(scsi_qla_host_t *vha) 33295988aeb2SGiridhar Malavali { 33305988aeb2SGiridhar Malavali uint32_t temp, temp_state, temp_val; 33315988aeb2SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 33325988aeb2SGiridhar Malavali 33335988aeb2SGiridhar Malavali temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 33345988aeb2SGiridhar Malavali temp_state = qla82xx_get_temp_state(temp); 33355988aeb2SGiridhar Malavali temp_val = qla82xx_get_temp_val(temp); 33365988aeb2SGiridhar Malavali 33375988aeb2SGiridhar Malavali if (temp_state == QLA82XX_TEMP_PANIC) { 33385988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600e, 33395988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33405988aeb2SGiridhar Malavali " maximum allowed. Hardware has been shut down.\n", 33415988aeb2SGiridhar Malavali temp_val); 33425988aeb2SGiridhar Malavali return 1; 33435988aeb2SGiridhar Malavali } else if (temp_state == QLA82XX_TEMP_WARN) { 33445988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600f, 33455988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 33465988aeb2SGiridhar Malavali "operating range. Immediate action needed.\n", 33475988aeb2SGiridhar Malavali temp_val); 33485988aeb2SGiridhar Malavali } 33495988aeb2SGiridhar Malavali return 0; 33505988aeb2SGiridhar Malavali } 33515988aeb2SGiridhar Malavali 33521ae47cf3SJoe Carnuccio int qla82xx_read_temperature(scsi_qla_host_t *vha) 33531ae47cf3SJoe Carnuccio { 33541ae47cf3SJoe Carnuccio uint32_t temp; 33551ae47cf3SJoe Carnuccio 33561ae47cf3SJoe Carnuccio temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 33571ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp); 33581ae47cf3SJoe Carnuccio } 33591ae47cf3SJoe Carnuccio 3360c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3361c8f6544eSChad Dupuis { 3362c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3363c8f6544eSChad Dupuis 3364c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3365c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33668937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3367c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3368c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 336936439832Sgurinder.shergill@hp.com if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3370c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3371c8f6544eSChad Dupuis } 3372c8f6544eSChad Dupuis } 3373c8f6544eSChad Dupuis 3374a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3375a9083016SGiridhar Malavali { 33767190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3377a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3378a9083016SGiridhar Malavali 3379a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33807d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_hdlr_active) { 33817190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33825988aeb2SGiridhar Malavali if (qla82xx_check_temp(vha)) { 33835988aeb2SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33845988aeb2SGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 33855988aeb2SGiridhar Malavali qla82xx_clear_pending_mbx(vha); 33867d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 33877190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33897c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3390a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 33917d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3392579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33937c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33947c3df132SSaurav Kashyap "Quiescent needed.\n"); 3395579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 33967d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_FAILED && 33977916bb90SChad Dupuis !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 33987916bb90SChad Dupuis vha->flags.online == 1) { 33997916bb90SChad Dupuis ql_log(ql_log_warn, vha, 0xb055, 34007916bb90SChad Dupuis "Adapter state is failed. Offlining.\n"); 34017916bb90SChad Dupuis set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 34027916bb90SChad Dupuis ha->flags.isp82xx_fw_hung = 1; 34037916bb90SChad Dupuis qla82xx_clear_pending_mbx(vha); 3404a9083016SGiridhar Malavali } else { 34057190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 340663154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 340763154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 340863154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 340963154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 34107190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 34117190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 341263154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 34137c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 34147c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 34157c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 34167c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 34177c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 34180e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 34190e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34200e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 34210e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34220e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 34230e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34240e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 34250e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34260e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 34270e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 34280e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 34292cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 343010a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 343110a340e6SChad Dupuis "Firmware aborted with " 343210a340e6SChad Dupuis "error code 0x00006700. Device is " 343310a340e6SChad Dupuis "being reset.\n"); 34347190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 34357190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 34367190575fSGiridhar Malavali &vha->dpc_flags); 34377190575fSGiridhar Malavali } else { 34387c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 34397c3df132SSaurav Kashyap "Detect abort needed.\n"); 34407190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 34417190575fSGiridhar Malavali &vha->dpc_flags); 34427190575fSGiridhar Malavali } 34437190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3444c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3445c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 34467190575fSGiridhar Malavali } 3447a9083016SGiridhar Malavali } 3448a9083016SGiridhar Malavali } 3449a9083016SGiridhar Malavali } 3450a9083016SGiridhar Malavali 3451a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3452a9083016SGiridhar Malavali { 34537ec0effdSAtul Deshmukh int rval = -1; 34547ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 34557ec0effdSAtul Deshmukh 34567ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3457a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 34587ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 34597ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 34607ec0effdSAtul Deshmukh /* Decide the reset ownership */ 34617ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 34627ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 34637ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 34647ec0effdSAtul Deshmukh } 3465a9083016SGiridhar Malavali return rval; 3466a9083016SGiridhar Malavali } 3467a9083016SGiridhar Malavali 346808de2844SGiridhar Malavali void 346908de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 347008de2844SGiridhar Malavali { 347108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 34727ec0effdSAtul Deshmukh uint32_t dev_state = 0; 347308de2844SGiridhar Malavali 34747ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 347508de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 34767ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 34777ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 34787ec0effdSAtul Deshmukh 34797d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_READY) { 348008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 348108de2844SGiridhar Malavali "HW State: NEED RESET\n"); 34827ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) { 348308de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 34847d613ac6SSantosh Vernekar QLA8XXX_DEV_NEED_RESET); 34857d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 1; 348608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 348708de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 34887ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) 34897ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 34907ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET); 349108de2844SGiridhar Malavali } else 349208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 349308de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 349408de2844SGiridhar Malavali dev_state, 349508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 349608de2844SGiridhar Malavali } 349708de2844SGiridhar Malavali 3498a9083016SGiridhar Malavali /* 3499a9083016SGiridhar Malavali * qla82xx_abort_isp 3500a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3501a9083016SGiridhar Malavali * 3502a9083016SGiridhar Malavali * Input: 3503a9083016SGiridhar Malavali * ha = adapter block pointer. 3504a9083016SGiridhar Malavali * 3505a9083016SGiridhar Malavali * Returns: 3506a9083016SGiridhar Malavali * 0 = success 3507a9083016SGiridhar Malavali */ 3508a9083016SGiridhar Malavali int 3509a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3510a9083016SGiridhar Malavali { 35117ec0effdSAtul Deshmukh int rval = -1; 3512a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3513a9083016SGiridhar Malavali 3514a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 35157c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 35167c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3517a9083016SGiridhar Malavali return QLA_SUCCESS; 3518a9083016SGiridhar Malavali } 35197d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 1; 3520a9083016SGiridhar Malavali 3521a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 352208de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3523a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3524a9083016SGiridhar Malavali 35257ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3526a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 35277ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 35287ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 35297ec0effdSAtul Deshmukh /* Decide the reset ownership */ 35307ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 35317ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 35327ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 35337ec0effdSAtul Deshmukh } 3534a9083016SGiridhar Malavali 3535a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3536a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3537a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3538a9083016SGiridhar Malavali 3539cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 35407190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 35417d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 0; 3542a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3543cdbb0a4fSSantosh Vernekar } 3544f1af6208SGiridhar Malavali 3545f1af6208SGiridhar Malavali if (rval) { 3546f1af6208SGiridhar Malavali vha->flags.online = 1; 3547f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3548f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 35497c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 35507c3df132SSaurav Kashyap "ISP error recover failed - board " 35517c3df132SSaurav Kashyap "disabled.\n"); 3552f1af6208SGiridhar Malavali /* 3553f1af6208SGiridhar Malavali * The next call disables the board 3554f1af6208SGiridhar Malavali * completely. 3555f1af6208SGiridhar Malavali */ 3556f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3557f1af6208SGiridhar Malavali vha->flags.online = 0; 3558f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3559f1af6208SGiridhar Malavali &vha->dpc_flags); 3560f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3561f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3562f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 35637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 35647c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 35657c3df132SSaurav Kashyap ha->isp_abort_cnt); 3566f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3567f1af6208SGiridhar Malavali } 3568f1af6208SGiridhar Malavali } else { 3569f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 35707c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 35717c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 35727c3df132SSaurav Kashyap ha->isp_abort_cnt); 3573f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3574f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3575f1af6208SGiridhar Malavali } 3576f1af6208SGiridhar Malavali } 3577a9083016SGiridhar Malavali return rval; 3578a9083016SGiridhar Malavali } 3579a9083016SGiridhar Malavali 3580a9083016SGiridhar Malavali /* 3581a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3582a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3583a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3584a9083016SGiridhar Malavali * chip reset. 3585a9083016SGiridhar Malavali * 3586a9083016SGiridhar Malavali * Input: 3587a9083016SGiridhar Malavali * ha = adapter block pointer. 3588a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3589a9083016SGiridhar Malavali * 3590a9083016SGiridhar Malavali * Returns: 3591a9083016SGiridhar Malavali * 0 = success 3592a9083016SGiridhar Malavali */ 3593a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3594a9083016SGiridhar Malavali { 3595a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3596a9083016SGiridhar Malavali 3597a9083016SGiridhar Malavali if (vha->flags.online) { 3598a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3599a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3600a9083016SGiridhar Malavali } 3601a9083016SGiridhar Malavali 3602a9083016SGiridhar Malavali /* Stop currently executing firmware. 3603a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3604a9083016SGiridhar Malavali */ 3605a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3606a9083016SGiridhar Malavali 3607a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3608a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3609a9083016SGiridhar Malavali 3610a9083016SGiridhar Malavali return rval; 3611a9083016SGiridhar Malavali } 3612a9083016SGiridhar Malavali 3613a9083016SGiridhar Malavali /* 3614a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3615a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3616a9083016SGiridhar Malavali * 3617a9083016SGiridhar Malavali * Note: 3618a9083016SGiridhar Malavali * Does context switching here. 3619a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3620a9083016SGiridhar Malavali * 3621a9083016SGiridhar Malavali * Return: 3622a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3623a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3624a9083016SGiridhar Malavali */ 3625a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3626a9083016SGiridhar Malavali { 3627a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3628a9083016SGiridhar Malavali unsigned long wait_reset; 3629a9083016SGiridhar Malavali 3630a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3631a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3632a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3633a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3634a9083016SGiridhar Malavali 3635a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3636a9083016SGiridhar Malavali schedule_timeout(HZ); 3637a9083016SGiridhar Malavali 3638a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3639a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3640a9083016SGiridhar Malavali status = QLA_SUCCESS; 3641a9083016SGiridhar Malavali break; 3642a9083016SGiridhar Malavali } 3643a9083016SGiridhar Malavali } 36447c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3645d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3646a9083016SGiridhar Malavali 3647a9083016SGiridhar Malavali return status; 3648a9083016SGiridhar Malavali } 36497190575fSGiridhar Malavali 36507190575fSGiridhar Malavali void 36517190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 36527190575fSGiridhar Malavali { 36537ec0effdSAtul Deshmukh int i, fw_state = 0; 36547190575fSGiridhar Malavali unsigned long flags; 36557190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 36567190575fSGiridhar Malavali 36577190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 36587190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 36597190575fSGiridhar Malavali * detection only 36607190575fSGiridhar Malavali */ 36617190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36627190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 36637190575fSGiridhar Malavali msleep(1000); 36647ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 36657ec0effdSAtul Deshmukh fw_state = qla82xx_check_fw_alive(vha); 36667ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 36677ec0effdSAtul Deshmukh fw_state = qla8044_check_fw_alive(vha); 36687ec0effdSAtul Deshmukh if (fw_state) { 36697190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3670c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 36717190575fSGiridhar Malavali break; 36727190575fSGiridhar Malavali } 36737190575fSGiridhar Malavali } 36747190575fSGiridhar Malavali } 36757c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 36767c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 36777c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 36787190575fSGiridhar Malavali 36797190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 36807190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36817190575fSGiridhar Malavali int cnt, que; 36827190575fSGiridhar Malavali srb_t *sp; 36837190575fSGiridhar Malavali struct req_que *req; 36847190575fSGiridhar Malavali 36857190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36867190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36877190575fSGiridhar Malavali req = ha->req_q_map[que]; 36887190575fSGiridhar Malavali if (!req) 36897190575fSGiridhar Malavali continue; 36908d93f550SChad Dupuis for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 36917190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36927190575fSGiridhar Malavali if (sp) { 3693af13b700SGiridhar Malavali if ((!sp->u.scmd.ctx || 3694af13b700SGiridhar Malavali (sp->flags & 3695af13b700SGiridhar Malavali SRB_FCP_CMND_DMA_VALID)) && 3696af13b700SGiridhar Malavali !ha->flags.isp82xx_fw_hung) { 36977190575fSGiridhar Malavali spin_unlock_irqrestore( 36987190575fSGiridhar Malavali &ha->hardware_lock, flags); 36997190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 37007c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 37017c3df132SSaurav Kashyap 0x00b1, 37027c3df132SSaurav Kashyap "mbx abort failed.\n"); 37037190575fSGiridhar Malavali } else { 37047c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 37057c3df132SSaurav Kashyap 0x00b2, 37067c3df132SSaurav Kashyap "mbx abort success.\n"); 37077190575fSGiridhar Malavali } 37087190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 37097190575fSGiridhar Malavali } 37107190575fSGiridhar Malavali } 37117190575fSGiridhar Malavali } 37127190575fSGiridhar Malavali } 37137190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 37147190575fSGiridhar Malavali 37157190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 37167190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 37177190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 37187c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 37197c3df132SSaurav Kashyap "Done wait for " 37207c3df132SSaurav Kashyap "pending commands.\n"); 37217190575fSGiridhar Malavali } 37227190575fSGiridhar Malavali } 37237190575fSGiridhar Malavali } 372408de2844SGiridhar Malavali 372508de2844SGiridhar Malavali /* Minidump related functions */ 372608de2844SGiridhar Malavali static int 372708de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 372808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 372908de2844SGiridhar Malavali { 373008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 373108de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 373208de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 373308de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 373408de2844SGiridhar Malavali unsigned long wtime; 373508de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 373608de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 373708de2844SGiridhar Malavali int i; 373808de2844SGiridhar Malavali 373908de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 374008de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 374108de2844SGiridhar Malavali crb_addr = crb_entry->addr; 374208de2844SGiridhar Malavali 374308de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 374408de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 374508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 374608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 374708de2844SGiridhar Malavali crb_entry->value_1, 1); 374808de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 374908de2844SGiridhar Malavali } 375008de2844SGiridhar Malavali 375108de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 375208de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 375308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 375408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 375508de2844SGiridhar Malavali } 375608de2844SGiridhar Malavali 375708de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 375808de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 375908de2844SGiridhar Malavali read_value &= crb_entry->value_2; 376008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 376108de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 376208de2844SGiridhar Malavali read_value |= crb_entry->value_3; 376308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 376408de2844SGiridhar Malavali } 376508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 376608de2844SGiridhar Malavali } 376708de2844SGiridhar Malavali 376808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 376908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 377008de2844SGiridhar Malavali read_value |= crb_entry->value_3; 377108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 377208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 377308de2844SGiridhar Malavali } 377408de2844SGiridhar Malavali 377508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 377608de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 377708de2844SGiridhar Malavali wtime = jiffies + poll_time; 377808de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 377908de2844SGiridhar Malavali 378008de2844SGiridhar Malavali do { 378108de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 378208de2844SGiridhar Malavali == crb_entry->value_1) 378308de2844SGiridhar Malavali break; 378408de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 378508de2844SGiridhar Malavali /* capturing dump failed */ 378608de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 378708de2844SGiridhar Malavali break; 378808de2844SGiridhar Malavali } else 378908de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 379008de2844SGiridhar Malavali crb_addr, 0, 0); 379108de2844SGiridhar Malavali } while (1); 379208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 379308de2844SGiridhar Malavali } 379408de2844SGiridhar Malavali 379508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 379608de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 379708de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 379808de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 379908de2844SGiridhar Malavali } else 380008de2844SGiridhar Malavali addr = crb_addr; 380108de2844SGiridhar Malavali 380208de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 380308de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 380408de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 380508de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 380608de2844SGiridhar Malavali } 380708de2844SGiridhar Malavali 380808de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 380908de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 381008de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 381108de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 381208de2844SGiridhar Malavali } else 381308de2844SGiridhar Malavali addr = crb_addr; 381408de2844SGiridhar Malavali 381508de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 381608de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 381708de2844SGiridhar Malavali read_value = 381808de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 381908de2844SGiridhar Malavali } else 382008de2844SGiridhar Malavali read_value = crb_entry->value_1; 382108de2844SGiridhar Malavali 382208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 382308de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 382408de2844SGiridhar Malavali } 382508de2844SGiridhar Malavali 382608de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 382708de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 382808de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 382908de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 383008de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 383108de2844SGiridhar Malavali if (crb_entry->value_2) 383208de2844SGiridhar Malavali read_value &= crb_entry->value_2; 383308de2844SGiridhar Malavali read_value |= crb_entry->value_3; 383408de2844SGiridhar Malavali read_value += crb_entry->value_1; 383508de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 383608de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 383708de2844SGiridhar Malavali } 383808de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 383908de2844SGiridhar Malavali } 384008de2844SGiridhar Malavali return rval; 384108de2844SGiridhar Malavali } 384208de2844SGiridhar Malavali 384308de2844SGiridhar Malavali static void 384408de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 384508de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 384608de2844SGiridhar Malavali { 384708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 384808de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 384908de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 385008de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 385108de2844SGiridhar Malavali 385208de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 385308de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 385408de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 385508de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 385608de2844SGiridhar Malavali 385708de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 3858fa492630SSaurav Kashyap r_value = RD_REG_DWORD((void __iomem *) 3859fa492630SSaurav Kashyap (r_addr + ha->nx_pcibase)); 386008de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 386108de2844SGiridhar Malavali r_addr += r_stride; 386208de2844SGiridhar Malavali } 386308de2844SGiridhar Malavali *d_ptr = data_ptr; 386408de2844SGiridhar Malavali } 386508de2844SGiridhar Malavali 386608de2844SGiridhar Malavali static void 386708de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 386808de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 386908de2844SGiridhar Malavali { 387008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 387108de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 387208de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 387308de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 387408de2844SGiridhar Malavali 387508de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 387608de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 387708de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 387808de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 387908de2844SGiridhar Malavali s_value = mux_hdr->select_value; 388008de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 388108de2844SGiridhar Malavali 388208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 388308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 388408de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 388508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 388608de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 388708de2844SGiridhar Malavali s_value += s_stride; 388808de2844SGiridhar Malavali } 388908de2844SGiridhar Malavali *d_ptr = data_ptr; 389008de2844SGiridhar Malavali } 389108de2844SGiridhar Malavali 389208de2844SGiridhar Malavali static void 389308de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 389408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 389508de2844SGiridhar Malavali { 389608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 389708de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 389808de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 389908de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 390008de2844SGiridhar Malavali 390108de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 390208de2844SGiridhar Malavali r_addr = crb_hdr->addr; 390308de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 390408de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 390508de2844SGiridhar Malavali 390608de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 390708de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 390808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 390908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 391008de2844SGiridhar Malavali r_addr += r_stride; 391108de2844SGiridhar Malavali } 391208de2844SGiridhar Malavali *d_ptr = data_ptr; 391308de2844SGiridhar Malavali } 391408de2844SGiridhar Malavali 391508de2844SGiridhar Malavali static int 391608de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 391708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 391808de2844SGiridhar Malavali { 391908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 392008de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 392108de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 392208de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 392308de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 392408de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 392508de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 392608de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 392708de2844SGiridhar Malavali 392808de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 392908de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 393008de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 393108de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 393208de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 393308de2844SGiridhar Malavali 393408de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 393508de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 393608de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 393708de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 393808de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 393908de2844SGiridhar Malavali 394008de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 394108de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 394208de2844SGiridhar Malavali if (c_value_w) 394308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 394408de2844SGiridhar Malavali 394508de2844SGiridhar Malavali if (p_mask) { 394608de2844SGiridhar Malavali w_time = jiffies + p_wait; 394708de2844SGiridhar Malavali do { 394808de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 394908de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 395008de2844SGiridhar Malavali break; 395108de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 395208de2844SGiridhar Malavali /* capturing dump failed */ 395308de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 395408de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 395508de2844SGiridhar Malavali "w_time: 0x%lx\n", 395608de2844SGiridhar Malavali c_value_r, p_mask, w_time); 395708de2844SGiridhar Malavali return rval; 395808de2844SGiridhar Malavali } 395908de2844SGiridhar Malavali } while (1); 396008de2844SGiridhar Malavali } 396108de2844SGiridhar Malavali 396208de2844SGiridhar Malavali addr = r_addr; 396308de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 396408de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 396508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 396608de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 396708de2844SGiridhar Malavali } 396808de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 396908de2844SGiridhar Malavali } 397008de2844SGiridhar Malavali *d_ptr = data_ptr; 397108de2844SGiridhar Malavali return QLA_SUCCESS; 397208de2844SGiridhar Malavali } 397308de2844SGiridhar Malavali 397408de2844SGiridhar Malavali static void 397508de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 397608de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 397708de2844SGiridhar Malavali { 397808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 397908de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 398008de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 398108de2844SGiridhar Malavali uint32_t c_value_w; 398208de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 398308de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 398408de2844SGiridhar Malavali 398508de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 398608de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 398708de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 398808de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 398908de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 399008de2844SGiridhar Malavali 399108de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 399208de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 399308de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 399408de2844SGiridhar Malavali 399508de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 399608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 399708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 399808de2844SGiridhar Malavali addr = r_addr; 399908de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 400008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 400108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 400208de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 400308de2844SGiridhar Malavali } 400408de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 400508de2844SGiridhar Malavali } 400608de2844SGiridhar Malavali *d_ptr = data_ptr; 400708de2844SGiridhar Malavali } 400808de2844SGiridhar Malavali 400908de2844SGiridhar Malavali static void 401008de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 401108de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 401208de2844SGiridhar Malavali { 401308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 401408de2844SGiridhar Malavali uint32_t s_addr, r_addr; 401508de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 401608de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 401708de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 401808de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 401908de2844SGiridhar Malavali 402008de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 402108de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 402208de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 402308de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 402408de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 402508de2844SGiridhar Malavali 402608de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 402708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 402808de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 402908de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 403008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 403108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 403208de2844SGiridhar Malavali r_addr += r_stride; 403308de2844SGiridhar Malavali } 403408de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 403508de2844SGiridhar Malavali } 403608de2844SGiridhar Malavali *d_ptr = data_ptr; 403708de2844SGiridhar Malavali } 403808de2844SGiridhar Malavali 403908de2844SGiridhar Malavali static void 404008de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 404108de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 404208de2844SGiridhar Malavali { 404308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 404408de2844SGiridhar Malavali uint32_t r_addr, r_value; 404508de2844SGiridhar Malavali uint32_t i, loop_cnt; 404608de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 404708de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 404808de2844SGiridhar Malavali 404908de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 405008de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 405108de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 405208de2844SGiridhar Malavali 405308de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 405408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 405508de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 405608de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 405708de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 405808de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 405908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 406008de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 406108de2844SGiridhar Malavali } 406208de2844SGiridhar Malavali *d_ptr = data_ptr; 406308de2844SGiridhar Malavali } 406408de2844SGiridhar Malavali 406508de2844SGiridhar Malavali static int 406608de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 406708de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 406808de2844SGiridhar Malavali { 406908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 407008de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 407108de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 407208de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 407308de2844SGiridhar Malavali unsigned long flags; 407408de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 407508de2844SGiridhar Malavali uint32_t *data_ptr = *d_ptr; 407608de2844SGiridhar Malavali 407708de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 407808de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 407908de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 408008de2844SGiridhar Malavali 408108de2844SGiridhar Malavali if (r_addr & 0xf) { 408208de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 4083d6a03581SMasanari Iida "Read addr 0x%x not 16 bytes aligned\n", r_addr); 408408de2844SGiridhar Malavali return rval; 408508de2844SGiridhar Malavali } 408608de2844SGiridhar Malavali 408708de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 408808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 408908de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 409008de2844SGiridhar Malavali m_hdr->read_data_size); 409108de2844SGiridhar Malavali return rval; 409208de2844SGiridhar Malavali } 409308de2844SGiridhar Malavali 409408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 409508de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 409608de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 409708de2844SGiridhar Malavali 409808de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 409908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 410008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 410108de2844SGiridhar Malavali r_value = 0; 410208de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 410308de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 410408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 410508de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 410608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 410708de2844SGiridhar Malavali 410808de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 410908de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 411008de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 411108de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 411208de2844SGiridhar Malavali break; 411308de2844SGiridhar Malavali } 411408de2844SGiridhar Malavali 411508de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 411608de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 411708de2844SGiridhar Malavali "failed to read through agent\n"); 411808de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 411908de2844SGiridhar Malavali return rval; 412008de2844SGiridhar Malavali } 412108de2844SGiridhar Malavali 412208de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 412308de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 412408de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 412508de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 412608de2844SGiridhar Malavali } 412708de2844SGiridhar Malavali r_addr += 16; 412808de2844SGiridhar Malavali } 412908de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 413008de2844SGiridhar Malavali *d_ptr = data_ptr; 413108de2844SGiridhar Malavali return QLA_SUCCESS; 413208de2844SGiridhar Malavali } 413308de2844SGiridhar Malavali 41347ec0effdSAtul Deshmukh int 413508de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 413608de2844SGiridhar Malavali { 413708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 413808de2844SGiridhar Malavali uint64_t chksum = 0; 413908de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 414008de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 414108de2844SGiridhar Malavali 414208de2844SGiridhar Malavali while (count-- > 0) 414308de2844SGiridhar Malavali chksum += *d_ptr++; 414408de2844SGiridhar Malavali while (chksum >> 32) 414508de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 414608de2844SGiridhar Malavali return ~chksum; 414708de2844SGiridhar Malavali } 414808de2844SGiridhar Malavali 414908de2844SGiridhar Malavali static void 415008de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 415108de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 415208de2844SGiridhar Malavali { 415308de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 415408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 415508de2844SGiridhar Malavali "Skipping entry[%d]: " 415608de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 415708de2844SGiridhar Malavali index, entry_hdr->entry_type, 415808de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 415908de2844SGiridhar Malavali } 416008de2844SGiridhar Malavali 416108de2844SGiridhar Malavali int 416208de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 416308de2844SGiridhar Malavali { 416408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 416508de2844SGiridhar Malavali int no_entry_hdr = 0; 416608de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 416708de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 416808de2844SGiridhar Malavali uint32_t *data_ptr; 416908de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 417008de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 417108de2844SGiridhar Malavali 417208de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 417308de2844SGiridhar Malavali data_ptr = (uint32_t *)ha->md_dump; 417408de2844SGiridhar Malavali 417508de2844SGiridhar Malavali if (ha->fw_dumped) { 4176a8faa263SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb037, 4177a8faa263SGiridhar Malavali "Firmware has been previously dumped (%p) " 4178a8faa263SGiridhar Malavali "-- ignoring request.\n", ha->fw_dump); 417908de2844SGiridhar Malavali goto md_failed; 418008de2844SGiridhar Malavali } 418108de2844SGiridhar Malavali 418208de2844SGiridhar Malavali ha->fw_dumped = 0; 418308de2844SGiridhar Malavali 418408de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 418508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 418608de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 418708de2844SGiridhar Malavali goto md_failed; 418808de2844SGiridhar Malavali } 418908de2844SGiridhar Malavali 4190b6d0d9d5SGiridhar Malavali if (ha->flags.isp82xx_no_md_cap) { 4191b6d0d9d5SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb054, 4192b6d0d9d5SGiridhar Malavali "Forced reset from application, " 4193b6d0d9d5SGiridhar Malavali "ignore minidump capture\n"); 4194b6d0d9d5SGiridhar Malavali ha->flags.isp82xx_no_md_cap = 0; 4195b6d0d9d5SGiridhar Malavali goto md_failed; 4196b6d0d9d5SGiridhar Malavali } 4197b6d0d9d5SGiridhar Malavali 419808de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 419908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 420008de2844SGiridhar Malavali "Template checksum validation error\n"); 420108de2844SGiridhar Malavali goto md_failed; 420208de2844SGiridhar Malavali } 420308de2844SGiridhar Malavali 420408de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 420508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 420608de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 420708de2844SGiridhar Malavali 420808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 420908de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 421008de2844SGiridhar Malavali 421108de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 421208de2844SGiridhar Malavali 421308de2844SGiridhar Malavali /* Validate whether required debug level is set */ 421408de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 421508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 421608de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 421708de2844SGiridhar Malavali f_capture_mask); 421808de2844SGiridhar Malavali goto md_failed; 421908de2844SGiridhar Malavali } 422008de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 422108de2844SGiridhar Malavali 422208de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 422308de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 422408de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 422508de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 422608de2844SGiridhar Malavali 422708de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 422808de2844SGiridhar Malavali 4229880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb03d, 423008de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 423108de2844SGiridhar Malavali 423208de2844SGiridhar Malavali /* Check whether template obtained is valid */ 423308de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 423408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 423508de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 423608de2844SGiridhar Malavali tmplt_hdr->entry_type); 423708de2844SGiridhar Malavali goto md_failed; 423808de2844SGiridhar Malavali } 423908de2844SGiridhar Malavali 424008de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 424108de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 424208de2844SGiridhar Malavali 424308de2844SGiridhar Malavali /* Walk through the entry headers */ 424408de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 424508de2844SGiridhar Malavali 424608de2844SGiridhar Malavali if (data_collected > total_data_size) { 424708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 424808de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 424908de2844SGiridhar Malavali data_collected); 425008de2844SGiridhar Malavali goto md_failed; 425108de2844SGiridhar Malavali } 425208de2844SGiridhar Malavali 425308de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 425408de2844SGiridhar Malavali ql2xmdcapmask)) { 425508de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 425608de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 425708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 425808de2844SGiridhar Malavali "Skipping entry[%d]: " 425908de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 426008de2844SGiridhar Malavali i, entry_hdr->entry_type, 426108de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 426208de2844SGiridhar Malavali goto skip_nxt_entry; 426308de2844SGiridhar Malavali } 426408de2844SGiridhar Malavali 426508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 426608de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 426708de2844SGiridhar Malavali "entry_type: 0x%x, captrue_mask: 0x%x\n", 426808de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 426908de2844SGiridhar Malavali entry_hdr->entry_type, 427008de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 427108de2844SGiridhar Malavali 427208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 427308de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 427408de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 427508de2844SGiridhar Malavali 427608de2844SGiridhar Malavali /* Decode the entry type and take 427708de2844SGiridhar Malavali * required action to capture debug data */ 427808de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 427908de2844SGiridhar Malavali case QLA82XX_RDEND: 428008de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 428108de2844SGiridhar Malavali break; 428208de2844SGiridhar Malavali case QLA82XX_CNTRL: 428308de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 428408de2844SGiridhar Malavali entry_hdr, &data_ptr); 428508de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 428608de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 428708de2844SGiridhar Malavali goto md_failed; 428808de2844SGiridhar Malavali } 428908de2844SGiridhar Malavali break; 429008de2844SGiridhar Malavali case QLA82XX_RDCRB: 429108de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 429208de2844SGiridhar Malavali entry_hdr, &data_ptr); 429308de2844SGiridhar Malavali break; 429408de2844SGiridhar Malavali case QLA82XX_RDMEM: 429508de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 429608de2844SGiridhar Malavali entry_hdr, &data_ptr); 429708de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 429808de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 429908de2844SGiridhar Malavali goto md_failed; 430008de2844SGiridhar Malavali } 430108de2844SGiridhar Malavali break; 430208de2844SGiridhar Malavali case QLA82XX_BOARD: 430308de2844SGiridhar Malavali case QLA82XX_RDROM: 430408de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 430508de2844SGiridhar Malavali entry_hdr, &data_ptr); 430608de2844SGiridhar Malavali break; 430708de2844SGiridhar Malavali case QLA82XX_L2DTG: 430808de2844SGiridhar Malavali case QLA82XX_L2ITG: 430908de2844SGiridhar Malavali case QLA82XX_L2DAT: 431008de2844SGiridhar Malavali case QLA82XX_L2INS: 431108de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 431208de2844SGiridhar Malavali entry_hdr, &data_ptr); 431308de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 431408de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 431508de2844SGiridhar Malavali goto md_failed; 431608de2844SGiridhar Malavali } 431708de2844SGiridhar Malavali break; 431808de2844SGiridhar Malavali case QLA82XX_L1DAT: 431908de2844SGiridhar Malavali case QLA82XX_L1INS: 432008de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 432108de2844SGiridhar Malavali entry_hdr, &data_ptr); 432208de2844SGiridhar Malavali break; 432308de2844SGiridhar Malavali case QLA82XX_RDOCM: 432408de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 432508de2844SGiridhar Malavali entry_hdr, &data_ptr); 432608de2844SGiridhar Malavali break; 432708de2844SGiridhar Malavali case QLA82XX_RDMUX: 432808de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 432908de2844SGiridhar Malavali entry_hdr, &data_ptr); 433008de2844SGiridhar Malavali break; 433108de2844SGiridhar Malavali case QLA82XX_QUEUE: 433208de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 433308de2844SGiridhar Malavali entry_hdr, &data_ptr); 433408de2844SGiridhar Malavali break; 433508de2844SGiridhar Malavali case QLA82XX_RDNOP: 433608de2844SGiridhar Malavali default: 433708de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 433808de2844SGiridhar Malavali break; 433908de2844SGiridhar Malavali } 434008de2844SGiridhar Malavali 434108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 434208de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 434308de2844SGiridhar Malavali 434408de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 434508de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 434608de2844SGiridhar Malavali skip_nxt_entry: 434708de2844SGiridhar Malavali entry_hdr = (qla82xx_md_entry_hdr_t *) \ 434808de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 434908de2844SGiridhar Malavali } 435008de2844SGiridhar Malavali 435108de2844SGiridhar Malavali if (data_collected != total_data_size) { 4352880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb043, 435308de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 435408de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 435508de2844SGiridhar Malavali data_collected, total_data_size); 435608de2844SGiridhar Malavali goto md_failed; 435708de2844SGiridhar Malavali } 435808de2844SGiridhar Malavali 435908de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 436008de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 436108de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 436208de2844SGiridhar Malavali ha->fw_dumped = 1; 436308de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 436408de2844SGiridhar Malavali 436508de2844SGiridhar Malavali md_failed: 436608de2844SGiridhar Malavali return rval; 436708de2844SGiridhar Malavali } 436808de2844SGiridhar Malavali 436908de2844SGiridhar Malavali int 437008de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 437108de2844SGiridhar Malavali { 437208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 437308de2844SGiridhar Malavali int i, k; 437408de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 437508de2844SGiridhar Malavali 437608de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 437708de2844SGiridhar Malavali 437808de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 437908de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 438008de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 438108de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 438208de2844SGiridhar Malavali ql2xmdcapmask); 438308de2844SGiridhar Malavali } 438408de2844SGiridhar Malavali 438508de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 438608de2844SGiridhar Malavali if (i & ql2xmdcapmask) 438708de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 438808de2844SGiridhar Malavali } 438908de2844SGiridhar Malavali 439008de2844SGiridhar Malavali if (ha->md_dump) { 439108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 439208de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 439308de2844SGiridhar Malavali return 1; 439408de2844SGiridhar Malavali } 439508de2844SGiridhar Malavali 439608de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 439708de2844SGiridhar Malavali if (ha->md_dump == NULL) { 439808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 439908de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 440008de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 440108de2844SGiridhar Malavali return 1; 440208de2844SGiridhar Malavali } 440308de2844SGiridhar Malavali return 0; 440408de2844SGiridhar Malavali } 440508de2844SGiridhar Malavali 440608de2844SGiridhar Malavali void 440708de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 440808de2844SGiridhar Malavali { 440908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 441008de2844SGiridhar Malavali 441108de2844SGiridhar Malavali /* Release the template header allocated */ 441208de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 441308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 441408de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 441508de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 441608de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 441708de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4418fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 441908de2844SGiridhar Malavali } 442008de2844SGiridhar Malavali 442108de2844SGiridhar Malavali /* Release the template data buffer allocated */ 442208de2844SGiridhar Malavali if (ha->md_dump) { 442308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 442408de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 442508de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 442608de2844SGiridhar Malavali vfree(ha->md_dump); 442708de2844SGiridhar Malavali ha->md_dump_size = 0; 4428fa492630SSaurav Kashyap ha->md_dump = NULL; 442908de2844SGiridhar Malavali } 443008de2844SGiridhar Malavali } 443108de2844SGiridhar Malavali 443208de2844SGiridhar Malavali void 443308de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 443408de2844SGiridhar Malavali { 443508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 443608de2844SGiridhar Malavali int rval; 443708de2844SGiridhar Malavali 443808de2844SGiridhar Malavali /* Get Minidump template size */ 443908de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 444008de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 444108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 444208de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 444308de2844SGiridhar Malavali ha->md_template_size / 1024); 444408de2844SGiridhar Malavali 444508de2844SGiridhar Malavali /* Get Minidump template */ 44467ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 44477ec0effdSAtul Deshmukh rval = qla8044_md_get_template(vha); 44487ec0effdSAtul Deshmukh else 444908de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 44507ec0effdSAtul Deshmukh 445108de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 445208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 445308de2844SGiridhar Malavali "MiniDump Template obtained\n"); 445408de2844SGiridhar Malavali 445508de2844SGiridhar Malavali /* Allocate memory for minidump */ 445608de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 445708de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 445808de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 445908de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 446008de2844SGiridhar Malavali ha->md_dump_size / 1024); 446108de2844SGiridhar Malavali else { 446208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 446308de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 446408de2844SGiridhar Malavali ha->md_tmplt_hdr, 446508de2844SGiridhar Malavali ha->md_template_size / 1024); 446608de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 446708de2844SGiridhar Malavali ha->md_template_size, 446808de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4469fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 447008de2844SGiridhar Malavali } 447108de2844SGiridhar Malavali 447208de2844SGiridhar Malavali } 447308de2844SGiridhar Malavali } 447408de2844SGiridhar Malavali } 4475999916dcSSaurav Kashyap 4476999916dcSSaurav Kashyap int 4477999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4478999916dcSSaurav Kashyap { 4479999916dcSSaurav Kashyap 4480999916dcSSaurav Kashyap int rval; 4481999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4482999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4483999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4484999916dcSSaurav Kashyap 4485999916dcSSaurav Kashyap if (rval) { 4486999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4487999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4488999916dcSSaurav Kashyap goto exit; 4489999916dcSSaurav Kashyap } 4490999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4491999916dcSSaurav Kashyap exit: 4492999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4493999916dcSSaurav Kashyap return rval; 4494999916dcSSaurav Kashyap } 4495999916dcSSaurav Kashyap 4496999916dcSSaurav Kashyap int 4497999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4498999916dcSSaurav Kashyap { 4499999916dcSSaurav Kashyap 4500999916dcSSaurav Kashyap int rval; 4501999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4502999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4503999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4504999916dcSSaurav Kashyap 4505999916dcSSaurav Kashyap if (rval) { 4506999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4507999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4508999916dcSSaurav Kashyap goto exit; 4509999916dcSSaurav Kashyap } 4510999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4511999916dcSSaurav Kashyap exit: 4512999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4513999916dcSSaurav Kashyap return rval; 4514999916dcSSaurav Kashyap } 4515a1b23c5aSChad Dupuis 4516a1b23c5aSChad Dupuis void 4517a1b23c5aSChad Dupuis qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4518a1b23c5aSChad Dupuis { 4519a1b23c5aSChad Dupuis struct qla_hw_data *ha = vha->hw; 4520a1b23c5aSChad Dupuis 4521a1b23c5aSChad Dupuis if (!ha->allow_cna_fw_dump) 4522a1b23c5aSChad Dupuis return; 4523a1b23c5aSChad Dupuis 4524a1b23c5aSChad Dupuis scsi_block_requests(vha->host); 4525a1b23c5aSChad Dupuis ha->flags.isp82xx_no_md_cap = 1; 4526a1b23c5aSChad Dupuis qla82xx_idc_lock(ha); 4527a1b23c5aSChad Dupuis qla82xx_set_reset_owner(vha); 4528a1b23c5aSChad Dupuis qla82xx_idc_unlock(ha); 4529a1b23c5aSChad Dupuis qla2x00_wait_for_chip_reset(vha); 4530a1b23c5aSChad Dupuis scsi_unblock_requests(vha->host); 4531a1b23c5aSChad Dupuis } 4532