1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 307e264b7SAndrew Vasquez * Copyright (c) 2003-2011 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 9a9083016SGiridhar Malavali #include <linux/pci.h> 10ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 11a9083016SGiridhar Malavali 12a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 13a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 14a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 15a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 16a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 17a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 18a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 19a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 20a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 21a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 22a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 230547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 24a9083016SGiridhar Malavali 25a9083016SGiridhar Malavali /* CRB window related */ 26a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 27a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 28a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 29a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 30a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 31a9083016SGiridhar Malavali ((off) & 0xf0000)) 32a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 33a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 34a9083016SGiridhar Malavali 35a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 36a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 37a9083016SGiridhar Malavali int qla82xx_crb_table_initialized; 38a9083016SGiridhar Malavali 39a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 40a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 41a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 42a9083016SGiridhar Malavali 43a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 44a9083016SGiridhar Malavali { 45a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 46a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 47a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 48a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 49a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 50a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 51a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 52a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 95a9083016SGiridhar Malavali /* 96a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 97a9083016SGiridhar Malavali */ 98a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 99a9083016SGiridhar Malavali 100a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 101a9083016SGiridhar Malavali } 102a9083016SGiridhar Malavali 103a9083016SGiridhar Malavali struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 104a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 105a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 106a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 107a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 108a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 109a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 110a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 111a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 112a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 113a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 114a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 115a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 116a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 117a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 118a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 119a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 120a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 121a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 122a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 123a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 124a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 125a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 126a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 127a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 128a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 129a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 130a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 131a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 132a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 133a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 134a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 135a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 143a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 144a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 145a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 151a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 159a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 160a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 161a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 167a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 175a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 176a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 177a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 183a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 191a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 192a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 193a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 194a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 195a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 196a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 197a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 198a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 199a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 200a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 201a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 202a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 203a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 204a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 205a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 206a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 207a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 208a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 209a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 210a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 211a9083016SGiridhar Malavali {{{0} } }, 212a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 213a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 214a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 215a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 216a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 217a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 218a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 219a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 220a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 221a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 222a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 223a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 224a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 225a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 226a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 227a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 228a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 229a9083016SGiridhar Malavali {{{0} } }, 230a9083016SGiridhar Malavali {{{0} } }, 231a9083016SGiridhar Malavali {{{0} } }, 232a9083016SGiridhar Malavali {{{0} } }, 233a9083016SGiridhar Malavali {{{0} } }, 234a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 235a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 236a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 237a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 238a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 239a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 240a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 241a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 242a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 243a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 244a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 245a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 246a9083016SGiridhar Malavali {{{0} } }, 247a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 248a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 249a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 250a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 251a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 252a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 253a9083016SGiridhar Malavali {{{0} } }, 254a9083016SGiridhar Malavali {{{0} } }, 255a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 256a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 257a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 258a9083016SGiridhar Malavali }; 259a9083016SGiridhar Malavali 260a9083016SGiridhar Malavali /* 261a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 262a9083016SGiridhar Malavali */ 263a9083016SGiridhar Malavali unsigned qla82xx_crb_hub_agt[64] = { 264a9083016SGiridhar Malavali 0, 265a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 266a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 267a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 268a9083016SGiridhar Malavali 0, 269a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 270a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 271a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 272a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 276a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 291a9083016SGiridhar Malavali 0, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 293a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 294a9083016SGiridhar Malavali 0, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 296a9083016SGiridhar Malavali 0, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 298a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 299a9083016SGiridhar Malavali 0, 300a9083016SGiridhar Malavali 0, 301a9083016SGiridhar Malavali 0, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali 0, 304a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 305a9083016SGiridhar Malavali 0, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 307a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 308a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 309a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 310a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 311a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 313a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 316a9083016SGiridhar Malavali 0, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 318a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 321a9083016SGiridhar Malavali 0, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 323a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 324a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 325a9083016SGiridhar Malavali 0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 327a9083016SGiridhar Malavali 0, 328a9083016SGiridhar Malavali }; 329a9083016SGiridhar Malavali 330f1af6208SGiridhar Malavali /* Device states */ 331f1af6208SGiridhar Malavali char *qdev_state[] = { 332f1af6208SGiridhar Malavali "Unknown", 333f1af6208SGiridhar Malavali "Cold", 334f1af6208SGiridhar Malavali "Initializing", 335f1af6208SGiridhar Malavali "Ready", 336f1af6208SGiridhar Malavali "Need Reset", 337f1af6208SGiridhar Malavali "Need Quiescent", 338f1af6208SGiridhar Malavali "Failed", 339f1af6208SGiridhar Malavali "Quiescent", 340f1af6208SGiridhar Malavali }; 341f1af6208SGiridhar Malavali 342a9083016SGiridhar Malavali /* 343a9083016SGiridhar Malavali * In: 'off' is offset from CRB space in 128M pci map 344a9083016SGiridhar Malavali * Out: 'off' is 2M pci map addr 345a9083016SGiridhar Malavali * side effect: lock crb window 346a9083016SGiridhar Malavali */ 347a9083016SGiridhar Malavali static void 348a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 349a9083016SGiridhar Malavali { 350a9083016SGiridhar Malavali u32 win_read; 3517c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 352a9083016SGiridhar Malavali 353a9083016SGiridhar Malavali ha->crb_win = CRB_HI(*off); 354a9083016SGiridhar Malavali writel(ha->crb_win, 355a9083016SGiridhar Malavali (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 356a9083016SGiridhar Malavali 357a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 358a9083016SGiridhar Malavali * to use it. 359a9083016SGiridhar Malavali */ 360a9083016SGiridhar Malavali win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 361a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3627c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3637c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3647c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 3657c3df132SSaurav Kashyap ha->crb_win, win_read, *off); 366a9083016SGiridhar Malavali } 367a9083016SGiridhar Malavali *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 368a9083016SGiridhar Malavali } 369a9083016SGiridhar Malavali 370a9083016SGiridhar Malavali static inline unsigned long 371a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 372a9083016SGiridhar Malavali { 3737c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 374a9083016SGiridhar Malavali /* See if we are currently pointing to the region we want to use next */ 375a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 376a9083016SGiridhar Malavali /* No need to change window. PCIX and PCIEregs are in both 377a9083016SGiridhar Malavali * regs are in both windows. 378a9083016SGiridhar Malavali */ 379a9083016SGiridhar Malavali return off; 380a9083016SGiridhar Malavali } 381a9083016SGiridhar Malavali 382a9083016SGiridhar Malavali if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 383a9083016SGiridhar Malavali /* We are in first CRB window */ 384a9083016SGiridhar Malavali if (ha->curr_window != 0) 385a9083016SGiridhar Malavali WARN_ON(1); 386a9083016SGiridhar Malavali return off; 387a9083016SGiridhar Malavali } 388a9083016SGiridhar Malavali 389a9083016SGiridhar Malavali if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 390a9083016SGiridhar Malavali /* We are in second CRB window */ 391a9083016SGiridhar Malavali off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 392a9083016SGiridhar Malavali 393a9083016SGiridhar Malavali if (ha->curr_window != 1) 394a9083016SGiridhar Malavali return off; 395a9083016SGiridhar Malavali 396a9083016SGiridhar Malavali /* We are in the QM or direct access 397a9083016SGiridhar Malavali * register region - do nothing 398a9083016SGiridhar Malavali */ 399a9083016SGiridhar Malavali if ((off >= QLA82XX_PCI_DIRECT_CRB) && 400a9083016SGiridhar Malavali (off < QLA82XX_PCI_CAMQM_MAX)) 401a9083016SGiridhar Malavali return off; 402a9083016SGiridhar Malavali } 403a9083016SGiridhar Malavali /* strange address given */ 4047c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb001, 4057c3df132SSaurav Kashyap "%x: Warning: unm_nic_pci_set_crbwindow " 4067c3df132SSaurav Kashyap "called with an unknown address(%llx).\n", 4077c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 408a9083016SGiridhar Malavali return off; 409a9083016SGiridhar Malavali } 410a9083016SGiridhar Malavali 41177e334d2SGiridhar Malavali static int 41277e334d2SGiridhar Malavali qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 41377e334d2SGiridhar Malavali { 41477e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 41577e334d2SGiridhar Malavali 41677e334d2SGiridhar Malavali if (*off >= QLA82XX_CRB_MAX) 41777e334d2SGiridhar Malavali return -1; 41877e334d2SGiridhar Malavali 41977e334d2SGiridhar Malavali if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 42077e334d2SGiridhar Malavali *off = (*off - QLA82XX_PCI_CAMQM) + 42177e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 42277e334d2SGiridhar Malavali return 0; 42377e334d2SGiridhar Malavali } 42477e334d2SGiridhar Malavali 42577e334d2SGiridhar Malavali if (*off < QLA82XX_PCI_CRBSPACE) 42677e334d2SGiridhar Malavali return -1; 42777e334d2SGiridhar Malavali 42877e334d2SGiridhar Malavali *off -= QLA82XX_PCI_CRBSPACE; 42977e334d2SGiridhar Malavali 43077e334d2SGiridhar Malavali /* Try direct map */ 43177e334d2SGiridhar Malavali m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 43277e334d2SGiridhar Malavali 43377e334d2SGiridhar Malavali if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 43477e334d2SGiridhar Malavali *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 43577e334d2SGiridhar Malavali return 0; 43677e334d2SGiridhar Malavali } 43777e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 43877e334d2SGiridhar Malavali return 1; 43977e334d2SGiridhar Malavali } 44077e334d2SGiridhar Malavali 44177e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 44277e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 44377e334d2SGiridhar Malavali { 44477e334d2SGiridhar Malavali int done = 0, timeout = 0; 44577e334d2SGiridhar Malavali 44677e334d2SGiridhar Malavali while (!done) { 44777e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 44877e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 44977e334d2SGiridhar Malavali if (done == 1) 45077e334d2SGiridhar Malavali break; 45177e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 45277e334d2SGiridhar Malavali return -1; 45377e334d2SGiridhar Malavali timeout++; 45477e334d2SGiridhar Malavali } 45577e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 45677e334d2SGiridhar Malavali return 0; 45777e334d2SGiridhar Malavali } 45877e334d2SGiridhar Malavali 459a9083016SGiridhar Malavali int 460a9083016SGiridhar Malavali qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 461a9083016SGiridhar Malavali { 462a9083016SGiridhar Malavali unsigned long flags = 0; 463a9083016SGiridhar Malavali int rv; 464a9083016SGiridhar Malavali 465a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 466a9083016SGiridhar Malavali 467a9083016SGiridhar Malavali BUG_ON(rv == -1); 468a9083016SGiridhar Malavali 469a9083016SGiridhar Malavali if (rv == 1) { 470a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 471a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 472a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 473a9083016SGiridhar Malavali } 474a9083016SGiridhar Malavali 475a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 476a9083016SGiridhar Malavali 477a9083016SGiridhar Malavali if (rv == 1) { 478a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 479a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 480a9083016SGiridhar Malavali } 481a9083016SGiridhar Malavali return 0; 482a9083016SGiridhar Malavali } 483a9083016SGiridhar Malavali 484a9083016SGiridhar Malavali int 485a9083016SGiridhar Malavali qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 486a9083016SGiridhar Malavali { 487a9083016SGiridhar Malavali unsigned long flags = 0; 488a9083016SGiridhar Malavali int rv; 489a9083016SGiridhar Malavali u32 data; 490a9083016SGiridhar Malavali 491a9083016SGiridhar Malavali rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 492a9083016SGiridhar Malavali 493a9083016SGiridhar Malavali BUG_ON(rv == -1); 494a9083016SGiridhar Malavali 495a9083016SGiridhar Malavali if (rv == 1) { 496a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 497a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 498a9083016SGiridhar Malavali qla82xx_pci_set_crbwindow_2M(ha, &off); 499a9083016SGiridhar Malavali } 500a9083016SGiridhar Malavali data = RD_REG_DWORD((void __iomem *)off); 501a9083016SGiridhar Malavali 502a9083016SGiridhar Malavali if (rv == 1) { 503a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 504a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 505a9083016SGiridhar Malavali } 506a9083016SGiridhar Malavali return data; 507a9083016SGiridhar Malavali } 508a9083016SGiridhar Malavali 509a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 510a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 511a9083016SGiridhar Malavali { 512a9083016SGiridhar Malavali int i; 513a9083016SGiridhar Malavali int done = 0, timeout = 0; 514a9083016SGiridhar Malavali 515a9083016SGiridhar Malavali while (!done) { 516a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 517a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 518a9083016SGiridhar Malavali if (done == 1) 519a9083016SGiridhar Malavali break; 520a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 521a9083016SGiridhar Malavali return -1; 522a9083016SGiridhar Malavali 523a9083016SGiridhar Malavali timeout++; 524a9083016SGiridhar Malavali 525a9083016SGiridhar Malavali /* Yield CPU */ 526a9083016SGiridhar Malavali if (!in_interrupt()) 527a9083016SGiridhar Malavali schedule(); 528a9083016SGiridhar Malavali else { 529a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 530a9083016SGiridhar Malavali cpu_relax(); 531a9083016SGiridhar Malavali } 532a9083016SGiridhar Malavali } 533a9083016SGiridhar Malavali 534a9083016SGiridhar Malavali return 0; 535a9083016SGiridhar Malavali } 536a9083016SGiridhar Malavali 537a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 538a9083016SGiridhar Malavali { 539a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 540a9083016SGiridhar Malavali } 541a9083016SGiridhar Malavali 542a9083016SGiridhar Malavali /* PCI Windowing for DDR regions. */ 543a9083016SGiridhar Malavali #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 544a9083016SGiridhar Malavali (((addr) <= (high)) && ((addr) >= (low))) 545a9083016SGiridhar Malavali /* 546a9083016SGiridhar Malavali * check memory access boundary. 547a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 548a9083016SGiridhar Malavali */ 549a9083016SGiridhar Malavali static unsigned long 550a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 551a9083016SGiridhar Malavali unsigned long long addr, int size) 552a9083016SGiridhar Malavali { 553a9083016SGiridhar Malavali if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 554a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 555a9083016SGiridhar Malavali !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 556a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 557a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 558a9083016SGiridhar Malavali return 0; 559a9083016SGiridhar Malavali else 560a9083016SGiridhar Malavali return 1; 561a9083016SGiridhar Malavali } 562a9083016SGiridhar Malavali 563a9083016SGiridhar Malavali int qla82xx_pci_set_window_warning_count; 564a9083016SGiridhar Malavali 56577e334d2SGiridhar Malavali static unsigned long 566a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 567a9083016SGiridhar Malavali { 568a9083016SGiridhar Malavali int window; 569a9083016SGiridhar Malavali u32 win_read; 5707c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 571a9083016SGiridhar Malavali 572a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 573a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 574a9083016SGiridhar Malavali /* DDR network side */ 575a9083016SGiridhar Malavali window = MN_WIN(addr); 576a9083016SGiridhar Malavali ha->ddr_mn_window = window; 577a9083016SGiridhar Malavali qla82xx_wr_32(ha, 578a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 579a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 580a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 581a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5827c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5837c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 584a9083016SGiridhar Malavali __func__, window, win_read); 585a9083016SGiridhar Malavali } 586a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 587a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 588a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 589a9083016SGiridhar Malavali unsigned int temp1; 590a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5917c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 592a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 593a9083016SGiridhar Malavali addr = -1UL; 594a9083016SGiridhar Malavali } 595a9083016SGiridhar Malavali window = OCM_WIN(addr); 596a9083016SGiridhar Malavali ha->ddr_mn_window = window; 597a9083016SGiridhar Malavali qla82xx_wr_32(ha, 598a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 599a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 600a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 601a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 602a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 603a9083016SGiridhar Malavali if (win_read != temp1) { 6047c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 6057c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 606a9083016SGiridhar Malavali __func__, temp1, win_read); 607a9083016SGiridhar Malavali } 608a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 609a9083016SGiridhar Malavali 610a9083016SGiridhar Malavali } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 611a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 612a9083016SGiridhar Malavali /* QDR network side */ 613a9083016SGiridhar Malavali window = MS_WIN(addr); 614a9083016SGiridhar Malavali ha->qdr_sn_window = window; 615a9083016SGiridhar Malavali qla82xx_wr_32(ha, 616a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 617a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 618a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 619a9083016SGiridhar Malavali if (win_read != window) { 6207c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6217c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 622a9083016SGiridhar Malavali __func__, window, win_read); 623a9083016SGiridhar Malavali } 624a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 625a9083016SGiridhar Malavali } else { 626a9083016SGiridhar Malavali /* 627a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 628a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 629a9083016SGiridhar Malavali */ 630a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 631a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6327c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6337c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6347c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 635a9083016SGiridhar Malavali } 636a9083016SGiridhar Malavali addr = -1UL; 637a9083016SGiridhar Malavali } 638a9083016SGiridhar Malavali return addr; 639a9083016SGiridhar Malavali } 640a9083016SGiridhar Malavali 641a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 642a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 643a9083016SGiridhar Malavali unsigned long long addr) 644a9083016SGiridhar Malavali { 645a9083016SGiridhar Malavali int window; 646a9083016SGiridhar Malavali unsigned long long qdr_max; 647a9083016SGiridhar Malavali 648a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 649a9083016SGiridhar Malavali 650a9083016SGiridhar Malavali /* DDR network side */ 651a9083016SGiridhar Malavali if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 652a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 653a9083016SGiridhar Malavali BUG(); 654a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 655a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 656a9083016SGiridhar Malavali return 1; 657a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 658a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 659a9083016SGiridhar Malavali return 1; 660a9083016SGiridhar Malavali else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 661a9083016SGiridhar Malavali /* QDR network side */ 662a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 663a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 664a9083016SGiridhar Malavali return 1; 665a9083016SGiridhar Malavali } 666a9083016SGiridhar Malavali return 0; 667a9083016SGiridhar Malavali } 668a9083016SGiridhar Malavali 669a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 670a9083016SGiridhar Malavali u64 off, void *data, int size) 671a9083016SGiridhar Malavali { 672a9083016SGiridhar Malavali unsigned long flags; 673f1af6208SGiridhar Malavali void *addr = NULL; 674a9083016SGiridhar Malavali int ret = 0; 675a9083016SGiridhar Malavali u64 start; 676a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 677a9083016SGiridhar Malavali unsigned long mem_base; 678a9083016SGiridhar Malavali unsigned long mem_page; 6797c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 680a9083016SGiridhar Malavali 681a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 682a9083016SGiridhar Malavali 683a9083016SGiridhar Malavali /* 684a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 685a9083016SGiridhar Malavali * do not access. 686a9083016SGiridhar Malavali */ 687a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 688a9083016SGiridhar Malavali if ((start == -1UL) || 689a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 690a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6917c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 6927c3df132SSaurav Kashyap "%s out of bound pci memory " 6937c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 6947c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 695a9083016SGiridhar Malavali return -1; 696a9083016SGiridhar Malavali } 697a9083016SGiridhar Malavali 698a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 699a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 700a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 701a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 702a9083016SGiridhar Malavali * consecutive pages. 703a9083016SGiridhar Malavali */ 704a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 705a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 706a9083016SGiridhar Malavali else 707a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 708a9083016SGiridhar Malavali if (mem_ptr == 0UL) { 709a9083016SGiridhar Malavali *(u8 *)data = 0; 710a9083016SGiridhar Malavali return -1; 711a9083016SGiridhar Malavali } 712a9083016SGiridhar Malavali addr = mem_ptr; 713a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 714a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 715a9083016SGiridhar Malavali 716a9083016SGiridhar Malavali switch (size) { 717a9083016SGiridhar Malavali case 1: 718a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 719a9083016SGiridhar Malavali break; 720a9083016SGiridhar Malavali case 2: 721a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 722a9083016SGiridhar Malavali break; 723a9083016SGiridhar Malavali case 4: 724a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 725a9083016SGiridhar Malavali break; 726a9083016SGiridhar Malavali case 8: 727a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 728a9083016SGiridhar Malavali break; 729a9083016SGiridhar Malavali default: 730a9083016SGiridhar Malavali ret = -1; 731a9083016SGiridhar Malavali break; 732a9083016SGiridhar Malavali } 733a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 734a9083016SGiridhar Malavali 735a9083016SGiridhar Malavali if (mem_ptr) 736a9083016SGiridhar Malavali iounmap(mem_ptr); 737a9083016SGiridhar Malavali return ret; 738a9083016SGiridhar Malavali } 739a9083016SGiridhar Malavali 740a9083016SGiridhar Malavali static int 741a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 742a9083016SGiridhar Malavali u64 off, void *data, int size) 743a9083016SGiridhar Malavali { 744a9083016SGiridhar Malavali unsigned long flags; 745f1af6208SGiridhar Malavali void *addr = NULL; 746a9083016SGiridhar Malavali int ret = 0; 747a9083016SGiridhar Malavali u64 start; 748a9083016SGiridhar Malavali uint8_t *mem_ptr = NULL; 749a9083016SGiridhar Malavali unsigned long mem_base; 750a9083016SGiridhar Malavali unsigned long mem_page; 7517c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 752a9083016SGiridhar Malavali 753a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 754a9083016SGiridhar Malavali 755a9083016SGiridhar Malavali /* 756a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 757a9083016SGiridhar Malavali * do not access. 758a9083016SGiridhar Malavali */ 759a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 760a9083016SGiridhar Malavali if ((start == -1UL) || 761a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 762a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7637c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7647c3df132SSaurav Kashyap "%s out of bount memory " 7657c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7667c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 767a9083016SGiridhar Malavali return -1; 768a9083016SGiridhar Malavali } 769a9083016SGiridhar Malavali 770a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 771a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 772a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 773a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 774a9083016SGiridhar Malavali * consecutive pages. 775a9083016SGiridhar Malavali */ 776a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 777a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 778a9083016SGiridhar Malavali else 779a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 780a9083016SGiridhar Malavali if (mem_ptr == 0UL) 781a9083016SGiridhar Malavali return -1; 782a9083016SGiridhar Malavali 783a9083016SGiridhar Malavali addr = mem_ptr; 784a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 785a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 786a9083016SGiridhar Malavali 787a9083016SGiridhar Malavali switch (size) { 788a9083016SGiridhar Malavali case 1: 789a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 790a9083016SGiridhar Malavali break; 791a9083016SGiridhar Malavali case 2: 792a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 793a9083016SGiridhar Malavali break; 794a9083016SGiridhar Malavali case 4: 795a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 796a9083016SGiridhar Malavali break; 797a9083016SGiridhar Malavali case 8: 798a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 799a9083016SGiridhar Malavali break; 800a9083016SGiridhar Malavali default: 801a9083016SGiridhar Malavali ret = -1; 802a9083016SGiridhar Malavali break; 803a9083016SGiridhar Malavali } 804a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 805a9083016SGiridhar Malavali if (mem_ptr) 806a9083016SGiridhar Malavali iounmap(mem_ptr); 807a9083016SGiridhar Malavali return ret; 808a9083016SGiridhar Malavali } 809a9083016SGiridhar Malavali 810a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 81177e334d2SGiridhar Malavali static unsigned long 81277e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 813a9083016SGiridhar Malavali { 814a9083016SGiridhar Malavali int i; 815a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 816a9083016SGiridhar Malavali 817a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 818a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 819a9083016SGiridhar Malavali 820a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 821a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 822a9083016SGiridhar Malavali offset = addr & 0x000fffff; 823a9083016SGiridhar Malavali 824a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 825a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 826a9083016SGiridhar Malavali pci_base = i << 20; 827a9083016SGiridhar Malavali break; 828a9083016SGiridhar Malavali } 829a9083016SGiridhar Malavali } 830a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 831a9083016SGiridhar Malavali return pci_base; 832a9083016SGiridhar Malavali return pci_base + offset; 833a9083016SGiridhar Malavali } 834a9083016SGiridhar Malavali 835a9083016SGiridhar Malavali static long rom_max_timeout = 100; 836a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 837a9083016SGiridhar Malavali 83877e334d2SGiridhar Malavali static int 839a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 840a9083016SGiridhar Malavali { 841a9083016SGiridhar Malavali int done = 0, timeout = 0; 842a9083016SGiridhar Malavali 843a9083016SGiridhar Malavali while (!done) { 844a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 845a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 846a9083016SGiridhar Malavali if (done == 1) 847a9083016SGiridhar Malavali break; 848a9083016SGiridhar Malavali if (timeout >= qla82xx_rom_lock_timeout) 849a9083016SGiridhar Malavali return -1; 850a9083016SGiridhar Malavali timeout++; 851a9083016SGiridhar Malavali } 852a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 853a9083016SGiridhar Malavali return 0; 854a9083016SGiridhar Malavali } 855a9083016SGiridhar Malavali 856d652e093SChad Dupuis static void 857d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 858d652e093SChad Dupuis { 859d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 860d652e093SChad Dupuis } 861d652e093SChad Dupuis 86277e334d2SGiridhar Malavali static int 863a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 864a9083016SGiridhar Malavali { 865a9083016SGiridhar Malavali long timeout = 0; 866a9083016SGiridhar Malavali long done = 0 ; 8677c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 868a9083016SGiridhar Malavali 869a9083016SGiridhar Malavali while (done == 0) { 870a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 871a9083016SGiridhar Malavali done &= 4; 872a9083016SGiridhar Malavali timeout++; 873a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8747c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8757c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8767c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 877a9083016SGiridhar Malavali return -1; 878a9083016SGiridhar Malavali } 879a9083016SGiridhar Malavali } 880a9083016SGiridhar Malavali return 0; 881a9083016SGiridhar Malavali } 882a9083016SGiridhar Malavali 88377e334d2SGiridhar Malavali static int 884a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 885a9083016SGiridhar Malavali { 886a9083016SGiridhar Malavali long timeout = 0; 887a9083016SGiridhar Malavali long done = 0 ; 8887c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 889a9083016SGiridhar Malavali 890a9083016SGiridhar Malavali while (done == 0) { 891a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 892a9083016SGiridhar Malavali done &= 2; 893a9083016SGiridhar Malavali timeout++; 894a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8957c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 8967c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 8977c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 898a9083016SGiridhar Malavali return -1; 899a9083016SGiridhar Malavali } 900a9083016SGiridhar Malavali } 901a9083016SGiridhar Malavali return 0; 902a9083016SGiridhar Malavali } 903a9083016SGiridhar Malavali 90477e334d2SGiridhar Malavali static int 905a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 906a9083016SGiridhar Malavali { 9077c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 9087c3df132SSaurav Kashyap 909a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 910a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 911a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 912a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 913a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 914a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9157c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ba, 9167c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 917a9083016SGiridhar Malavali return -1; 918a9083016SGiridhar Malavali } 919a9083016SGiridhar Malavali /* Reset abyte_cnt and dummy_byte_cnt */ 920a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 921a9083016SGiridhar Malavali udelay(10); 922a9083016SGiridhar Malavali cond_resched(); 923a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 924a9083016SGiridhar Malavali *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 925a9083016SGiridhar Malavali return 0; 926a9083016SGiridhar Malavali } 927a9083016SGiridhar Malavali 92877e334d2SGiridhar Malavali static int 929a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 930a9083016SGiridhar Malavali { 931a9083016SGiridhar Malavali int ret, loops = 0; 9327c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 933a9083016SGiridhar Malavali 934a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 935a9083016SGiridhar Malavali udelay(100); 936a9083016SGiridhar Malavali schedule(); 937a9083016SGiridhar Malavali loops++; 938a9083016SGiridhar Malavali } 939a9083016SGiridhar Malavali if (loops >= 50000) { 9407c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9417c3df132SSaurav Kashyap "Failed to aquire SEM2 lock.\n"); 942a9083016SGiridhar Malavali return -1; 943a9083016SGiridhar Malavali } 944a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 945d652e093SChad Dupuis qla82xx_rom_unlock(ha); 946a9083016SGiridhar Malavali return ret; 947a9083016SGiridhar Malavali } 948a9083016SGiridhar Malavali 94977e334d2SGiridhar Malavali static int 950a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 951a9083016SGiridhar Malavali { 9527c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 953a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 954a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 955a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9567c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9577c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 958a9083016SGiridhar Malavali return -1; 959a9083016SGiridhar Malavali } 960a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 961a9083016SGiridhar Malavali return 0; 962a9083016SGiridhar Malavali } 963a9083016SGiridhar Malavali 96477e334d2SGiridhar Malavali static int 965a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 966a9083016SGiridhar Malavali { 967a9083016SGiridhar Malavali long timeout = 0; 968a9083016SGiridhar Malavali uint32_t done = 1 ; 969a9083016SGiridhar Malavali uint32_t val; 970a9083016SGiridhar Malavali int ret = 0; 9717c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 972a9083016SGiridhar Malavali 973a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 974a9083016SGiridhar Malavali while ((done != 0) && (ret == 0)) { 975a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 976a9083016SGiridhar Malavali done = val & 1; 977a9083016SGiridhar Malavali timeout++; 978a9083016SGiridhar Malavali udelay(10); 979a9083016SGiridhar Malavali cond_resched(); 980a9083016SGiridhar Malavali if (timeout >= 50000) { 9817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 9827c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 983a9083016SGiridhar Malavali return -1; 984a9083016SGiridhar Malavali } 985a9083016SGiridhar Malavali } 986a9083016SGiridhar Malavali return ret; 987a9083016SGiridhar Malavali } 988a9083016SGiridhar Malavali 98977e334d2SGiridhar Malavali static int 990a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 991a9083016SGiridhar Malavali { 992a9083016SGiridhar Malavali uint32_t val; 993a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 994a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 995a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 996a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 997a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 998a9083016SGiridhar Malavali return -1; 999a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 1000a9083016SGiridhar Malavali return -1; 1001a9083016SGiridhar Malavali if ((val & 2) != 2) 1002a9083016SGiridhar Malavali return -1; 1003a9083016SGiridhar Malavali return 0; 1004a9083016SGiridhar Malavali } 1005a9083016SGiridhar Malavali 100677e334d2SGiridhar Malavali static int 1007a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1008a9083016SGiridhar Malavali { 10097c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1010a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1011a9083016SGiridhar Malavali return -1; 1012a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1013a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1014a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10157c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10167c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1017a9083016SGiridhar Malavali return -1; 1018a9083016SGiridhar Malavali } 1019a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1020a9083016SGiridhar Malavali } 1021a9083016SGiridhar Malavali 102277e334d2SGiridhar Malavali static int 1023a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1024a9083016SGiridhar Malavali { 10257c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1026a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1027a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10297c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1030a9083016SGiridhar Malavali return -1; 1031a9083016SGiridhar Malavali } 1032a9083016SGiridhar Malavali return 0; 1033a9083016SGiridhar Malavali } 1034a9083016SGiridhar Malavali 103577e334d2SGiridhar Malavali static int 1036a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1037a9083016SGiridhar Malavali { 1038a9083016SGiridhar Malavali int loops = 0; 10397c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10407c3df132SSaurav Kashyap 1041a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1042a9083016SGiridhar Malavali udelay(100); 1043a9083016SGiridhar Malavali cond_resched(); 1044a9083016SGiridhar Malavali loops++; 1045a9083016SGiridhar Malavali } 1046a9083016SGiridhar Malavali if (loops >= 50000) { 10477c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10487c3df132SSaurav Kashyap "ROM lock failed.\n"); 1049a9083016SGiridhar Malavali return -1; 1050a9083016SGiridhar Malavali } 1051a9083016SGiridhar Malavali return 0;; 1052a9083016SGiridhar Malavali } 1053a9083016SGiridhar Malavali 105477e334d2SGiridhar Malavali static int 1055a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1056a9083016SGiridhar Malavali uint32_t data) 1057a9083016SGiridhar Malavali { 1058a9083016SGiridhar Malavali int ret = 0; 10597c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1060a9083016SGiridhar Malavali 1061a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1062a9083016SGiridhar Malavali if (ret < 0) { 10637c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10647c3df132SSaurav Kashyap "ROM lock failed.\n"); 1065a9083016SGiridhar Malavali return ret; 1066a9083016SGiridhar Malavali } 1067a9083016SGiridhar Malavali 1068a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1069a9083016SGiridhar Malavali goto done_write; 1070a9083016SGiridhar Malavali 1071a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1072a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1073a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1074a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1075a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1076a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10777c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 10787c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1079a9083016SGiridhar Malavali ret = -1; 1080a9083016SGiridhar Malavali goto done_write; 1081a9083016SGiridhar Malavali } 1082a9083016SGiridhar Malavali 1083a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1084a9083016SGiridhar Malavali 1085a9083016SGiridhar Malavali done_write: 1086d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1087a9083016SGiridhar Malavali return ret; 1088a9083016SGiridhar Malavali } 1089a9083016SGiridhar Malavali 1090a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1091a9083016SGiridhar Malavali * to put the ISP into operational state 1092a9083016SGiridhar Malavali */ 109377e334d2SGiridhar Malavali static int 109477e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1095a9083016SGiridhar Malavali { 1096a9083016SGiridhar Malavali int addr, val; 1097a9083016SGiridhar Malavali int i ; 1098a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1099a9083016SGiridhar Malavali unsigned long off; 1100a9083016SGiridhar Malavali unsigned offset, n; 1101a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1102a9083016SGiridhar Malavali 1103a9083016SGiridhar Malavali struct crb_addr_pair { 1104a9083016SGiridhar Malavali long addr; 1105a9083016SGiridhar Malavali long data; 1106a9083016SGiridhar Malavali }; 1107a9083016SGiridhar Malavali 1108a9083016SGiridhar Malavali /* Halt all the indiviual PEGs and other blocks of the ISP */ 1109a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1110c9e8fd5cSMadhuranath Iyengar 111102be2215SGiridhar Malavali /* disable all I2Q */ 111202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 111302be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 111402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 111502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 111602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 111702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 111802be2215SGiridhar Malavali 111902be2215SGiridhar Malavali /* disable all niu interrupts */ 1120c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1121c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1122c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1123c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1124c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 112502be2215SGiridhar Malavali /* disable sideband mac */ 112602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 112702be2215SGiridhar Malavali /* disable ap0 mac */ 112802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 112902be2215SGiridhar Malavali /* disable ap1 mac */ 113002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1131c9e8fd5cSMadhuranath Iyengar 1132c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1133c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1134c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1135c9e8fd5cSMadhuranath Iyengar 1136c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1137c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1138c9e8fd5cSMadhuranath Iyengar 1139c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1140c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1141c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1142c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1143c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1144c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 114502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1146c9e8fd5cSMadhuranath Iyengar 1147c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1148c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1149c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1150c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1151c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1152c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 115302be2215SGiridhar Malavali msleep(20); 1154c9e8fd5cSMadhuranath Iyengar 1155c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1156a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1157a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1158a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1159a9083016SGiridhar Malavali else 1160a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1161c9e8fd5cSMadhuranath Iyengar 1162c9e8fd5cSMadhuranath Iyengar /* reset ms */ 1163c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1164c9e8fd5cSMadhuranath Iyengar val |= (1 << 1); 1165c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1166c9e8fd5cSMadhuranath Iyengar msleep(20); 1167c9e8fd5cSMadhuranath Iyengar 1168c9e8fd5cSMadhuranath Iyengar /* unreset ms */ 1169c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1170c9e8fd5cSMadhuranath Iyengar val &= ~(1 << 1); 1171c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1172c9e8fd5cSMadhuranath Iyengar msleep(20); 1173c9e8fd5cSMadhuranath Iyengar 1174d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1175a9083016SGiridhar Malavali 1176a9083016SGiridhar Malavali /* Read the signature value from the flash. 1177a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1178a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1179a9083016SGiridhar Malavali * that present in CRB initialize sequence 1180a9083016SGiridhar Malavali */ 1181a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1182a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11837c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11847c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1185a9083016SGiridhar Malavali return -1; 1186a9083016SGiridhar Malavali } 1187a9083016SGiridhar Malavali 1188a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 1189a9083016SGiridhar Malavali * Number of enteries = upper 16 bits 1190a9083016SGiridhar Malavali */ 1191a9083016SGiridhar Malavali offset = n & 0xffffU; 1192a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1193a9083016SGiridhar Malavali 1194a9083016SGiridhar Malavali /* number of addr/value pair should not exceed 1024 enteries */ 1195a9083016SGiridhar Malavali if (n >= 1024) { 11967c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 11977c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1198a9083016SGiridhar Malavali return -1; 1199a9083016SGiridhar Malavali } 1200a9083016SGiridhar Malavali 12017c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 12027c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1203a9083016SGiridhar Malavali 1204a9083016SGiridhar Malavali buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1205a9083016SGiridhar Malavali if (buf == NULL) { 12067c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 12077c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 1208a9083016SGiridhar Malavali return -1; 1209a9083016SGiridhar Malavali } 1210a9083016SGiridhar Malavali 1211a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1212a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1213a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1214a9083016SGiridhar Malavali kfree(buf); 1215a9083016SGiridhar Malavali return -1; 1216a9083016SGiridhar Malavali } 1217a9083016SGiridhar Malavali 1218a9083016SGiridhar Malavali buf[i].addr = addr; 1219a9083016SGiridhar Malavali buf[i].data = val; 1220a9083016SGiridhar Malavali } 1221a9083016SGiridhar Malavali 1222a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1223a9083016SGiridhar Malavali /* Translate internal CRB initialization 1224a9083016SGiridhar Malavali * address to PCI bus address 1225a9083016SGiridhar Malavali */ 1226a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1227a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1228a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1229a9083016SGiridhar Malavali * some of them are skipped 1230a9083016SGiridhar Malavali */ 1231a9083016SGiridhar Malavali 1232a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1233a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1234a9083016SGiridhar Malavali continue; 1235a9083016SGiridhar Malavali 1236a9083016SGiridhar Malavali /* do not reset PCI */ 1237a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1238a9083016SGiridhar Malavali continue; 1239a9083016SGiridhar Malavali 1240a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1241a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1242a9083016SGiridhar Malavali continue; 1243a9083016SGiridhar Malavali 1244a9083016SGiridhar Malavali /* skip the function enable register */ 1245a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1246a9083016SGiridhar Malavali continue; 1247a9083016SGiridhar Malavali 1248a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1249a9083016SGiridhar Malavali continue; 1250a9083016SGiridhar Malavali 1251a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1252a9083016SGiridhar Malavali continue; 1253a9083016SGiridhar Malavali 1254a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1255a9083016SGiridhar Malavali continue; 1256a9083016SGiridhar Malavali 1257a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12587c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 12597c3df132SSaurav Kashyap "Unknow addr: 0x%08lx.\n", buf[i].addr); 1260a9083016SGiridhar Malavali continue; 1261a9083016SGiridhar Malavali } 1262a9083016SGiridhar Malavali 1263a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1264a9083016SGiridhar Malavali 1265a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1266a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1267a9083016SGiridhar Malavali */ 1268a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1269a9083016SGiridhar Malavali msleep(1000); 1270a9083016SGiridhar Malavali 1271a9083016SGiridhar Malavali /* ISP requires millisec delay between 1272a9083016SGiridhar Malavali * successive CRB register updation 1273a9083016SGiridhar Malavali */ 1274a9083016SGiridhar Malavali msleep(1); 1275a9083016SGiridhar Malavali } 1276a9083016SGiridhar Malavali 1277a9083016SGiridhar Malavali kfree(buf); 1278a9083016SGiridhar Malavali 1279a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1280a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1281a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1282a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1283a9083016SGiridhar Malavali 1284a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1285a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1286a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1287a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1288a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1289a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1290a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1291a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1292a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1293a9083016SGiridhar Malavali return 0; 1294a9083016SGiridhar Malavali } 1295a9083016SGiridhar Malavali 129677e334d2SGiridhar Malavali static int 129777e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 129877e334d2SGiridhar Malavali u64 off, void *data, int size) 129977e334d2SGiridhar Malavali { 130077e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 130177e334d2SGiridhar Malavali int scale, shift_amount, startword; 130277e334d2SGiridhar Malavali uint32_t temp; 130377e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 130477e334d2SGiridhar Malavali 130577e334d2SGiridhar Malavali /* 130677e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 130777e334d2SGiridhar Malavali */ 130877e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 130977e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 131077e334d2SGiridhar Malavali else { 131177e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 131277e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 131377e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 131477e334d2SGiridhar Malavali off, data, size); 131577e334d2SGiridhar Malavali } 131677e334d2SGiridhar Malavali 131777e334d2SGiridhar Malavali off0 = off & 0x7; 131877e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 131977e334d2SGiridhar Malavali sz[1] = size - sz[0]; 132077e334d2SGiridhar Malavali 132177e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 132277e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 132377e334d2SGiridhar Malavali shift_amount = 4; 132477e334d2SGiridhar Malavali scale = 2; 132577e334d2SGiridhar Malavali startword = (off & 0xf)/8; 132677e334d2SGiridhar Malavali 132777e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 132877e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 132977e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 133077e334d2SGiridhar Malavali return -1; 133177e334d2SGiridhar Malavali } 133277e334d2SGiridhar Malavali 133377e334d2SGiridhar Malavali switch (size) { 133477e334d2SGiridhar Malavali case 1: 133577e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 133677e334d2SGiridhar Malavali break; 133777e334d2SGiridhar Malavali case 2: 133877e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 133977e334d2SGiridhar Malavali break; 134077e334d2SGiridhar Malavali case 4: 134177e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 134277e334d2SGiridhar Malavali break; 134377e334d2SGiridhar Malavali case 8: 134477e334d2SGiridhar Malavali default: 134577e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 134677e334d2SGiridhar Malavali break; 134777e334d2SGiridhar Malavali } 134877e334d2SGiridhar Malavali 134977e334d2SGiridhar Malavali if (sz[0] == 8) { 135077e334d2SGiridhar Malavali word[startword] = tmpw; 135177e334d2SGiridhar Malavali } else { 135277e334d2SGiridhar Malavali word[startword] &= 135377e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 135477e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 135577e334d2SGiridhar Malavali } 135677e334d2SGiridhar Malavali if (sz[1] != 0) { 135777e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 135877e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 135977e334d2SGiridhar Malavali } 136077e334d2SGiridhar Malavali 136177e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 136277e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 136377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 136477e334d2SGiridhar Malavali temp = 0; 136577e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 136677e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 136777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 136877e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 136977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 137077e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 137177e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 137277e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 137377e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 137477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 137577e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 137677e334d2SGiridhar Malavali 137777e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 137877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 137977e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 138077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 138177e334d2SGiridhar Malavali 138277e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 138377e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 138477e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 138577e334d2SGiridhar Malavali break; 138677e334d2SGiridhar Malavali } 138777e334d2SGiridhar Malavali 138877e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 138977e334d2SGiridhar Malavali if (printk_ratelimit()) 139077e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 13917c3df132SSaurav Kashyap "failed to write through agent.\n"); 139277e334d2SGiridhar Malavali ret = -1; 139377e334d2SGiridhar Malavali break; 139477e334d2SGiridhar Malavali } 139577e334d2SGiridhar Malavali } 139677e334d2SGiridhar Malavali 139777e334d2SGiridhar Malavali return ret; 139877e334d2SGiridhar Malavali } 139977e334d2SGiridhar Malavali 140077e334d2SGiridhar Malavali static int 1401a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1402a9083016SGiridhar Malavali { 1403a9083016SGiridhar Malavali int i; 1404a9083016SGiridhar Malavali long size = 0; 14059c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 14069c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1407a9083016SGiridhar Malavali u64 data; 1408a9083016SGiridhar Malavali u32 high, low; 1409a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1410a9083016SGiridhar Malavali 1411a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1412a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1413a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1414a9083016SGiridhar Malavali return -1; 1415a9083016SGiridhar Malavali } 1416a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1417a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1418a9083016SGiridhar Malavali flashaddr += 8; 1419a9083016SGiridhar Malavali memaddr += 8; 1420a9083016SGiridhar Malavali 1421a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1422a9083016SGiridhar Malavali msleep(1); 1423a9083016SGiridhar Malavali } 1424a9083016SGiridhar Malavali udelay(100); 1425a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1426a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1427a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1428a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1429a9083016SGiridhar Malavali return 0; 1430a9083016SGiridhar Malavali } 1431a9083016SGiridhar Malavali 1432a9083016SGiridhar Malavali int 1433a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1434a9083016SGiridhar Malavali u64 off, void *data, int size) 1435a9083016SGiridhar Malavali { 1436a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1437a9083016SGiridhar Malavali int shift_amount; 1438a9083016SGiridhar Malavali uint32_t temp; 1439a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1440a9083016SGiridhar Malavali 1441a9083016SGiridhar Malavali /* 1442a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1443a9083016SGiridhar Malavali */ 1444a9083016SGiridhar Malavali 1445a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1446a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1447a9083016SGiridhar Malavali else { 1448a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1449a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1450a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1451a9083016SGiridhar Malavali off, data, size); 1452a9083016SGiridhar Malavali } 1453a9083016SGiridhar Malavali 1454a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1455a9083016SGiridhar Malavali off0[0] = off & 0xf; 1456a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1457a9083016SGiridhar Malavali shift_amount = 4; 1458a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1459a9083016SGiridhar Malavali off0[1] = 0; 1460a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1461a9083016SGiridhar Malavali 1462a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1463a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1464a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1465a9083016SGiridhar Malavali temp = 0; 1466a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1467a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1468a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1469a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1470a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1471a9083016SGiridhar Malavali 1472a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1473a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1474a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1475a9083016SGiridhar Malavali break; 1476a9083016SGiridhar Malavali } 1477a9083016SGiridhar Malavali 1478a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1479a9083016SGiridhar Malavali if (printk_ratelimit()) 1480a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14817c3df132SSaurav Kashyap "failed to read through agent.\n"); 1482a9083016SGiridhar Malavali break; 1483a9083016SGiridhar Malavali } 1484a9083016SGiridhar Malavali 1485a9083016SGiridhar Malavali start = off0[i] >> 2; 1486a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1487a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1488a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1489a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1490a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1491a9083016SGiridhar Malavali } 1492a9083016SGiridhar Malavali } 1493a9083016SGiridhar Malavali 1494a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1495a9083016SGiridhar Malavali return -1; 1496a9083016SGiridhar Malavali 1497a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1498a9083016SGiridhar Malavali val = word[0]; 1499a9083016SGiridhar Malavali } else { 1500a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1501a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1502a9083016SGiridhar Malavali } 1503a9083016SGiridhar Malavali 1504a9083016SGiridhar Malavali switch (size) { 1505a9083016SGiridhar Malavali case 1: 1506a9083016SGiridhar Malavali *(uint8_t *)data = val; 1507a9083016SGiridhar Malavali break; 1508a9083016SGiridhar Malavali case 2: 1509a9083016SGiridhar Malavali *(uint16_t *)data = val; 1510a9083016SGiridhar Malavali break; 1511a9083016SGiridhar Malavali case 4: 1512a9083016SGiridhar Malavali *(uint32_t *)data = val; 1513a9083016SGiridhar Malavali break; 1514a9083016SGiridhar Malavali case 8: 1515a9083016SGiridhar Malavali *(uint64_t *)data = val; 1516a9083016SGiridhar Malavali break; 1517a9083016SGiridhar Malavali } 1518a9083016SGiridhar Malavali return 0; 1519a9083016SGiridhar Malavali } 1520a9083016SGiridhar Malavali 1521a9083016SGiridhar Malavali 15229c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15239c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15249c2b2975SHarish Zunjarrao { 15259c2b2975SHarish Zunjarrao uint32_t i; 15269c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15279c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15289c2b2975SHarish Zunjarrao __le32 offset; 15299c2b2975SHarish Zunjarrao __le32 tab_type; 15309c2b2975SHarish Zunjarrao __le32 entries = cpu_to_le32(directory->num_entries); 15319c2b2975SHarish Zunjarrao 15329c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15339c2b2975SHarish Zunjarrao offset = cpu_to_le32(directory->findex) + 15349c2b2975SHarish Zunjarrao (i * cpu_to_le32(directory->entry_size)); 15359c2b2975SHarish Zunjarrao tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 15369c2b2975SHarish Zunjarrao 15379c2b2975SHarish Zunjarrao if (tab_type == section) 15389c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15399c2b2975SHarish Zunjarrao } 15409c2b2975SHarish Zunjarrao 15419c2b2975SHarish Zunjarrao return NULL; 15429c2b2975SHarish Zunjarrao } 15439c2b2975SHarish Zunjarrao 15449c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15459c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15469c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15479c2b2975SHarish Zunjarrao { 15489c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15499c2b2975SHarish Zunjarrao int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 15509c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15519c2b2975SHarish Zunjarrao __le32 offset; 15529c2b2975SHarish Zunjarrao 15539c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15549c2b2975SHarish Zunjarrao if (!tab_desc) 15559c2b2975SHarish Zunjarrao return NULL; 15569c2b2975SHarish Zunjarrao 15579c2b2975SHarish Zunjarrao offset = cpu_to_le32(tab_desc->findex) + 15589c2b2975SHarish Zunjarrao (cpu_to_le32(tab_desc->entry_size) * idx); 15599c2b2975SHarish Zunjarrao 15609c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15619c2b2975SHarish Zunjarrao } 15629c2b2975SHarish Zunjarrao 15639c2b2975SHarish Zunjarrao static u8 * 15649c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15659c2b2975SHarish Zunjarrao { 15669c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15679c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15689c2b2975SHarish Zunjarrao 15699c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15709c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15719c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15729c2b2975SHarish Zunjarrao if (uri_desc) 15739c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 15749c2b2975SHarish Zunjarrao } 15759c2b2975SHarish Zunjarrao 15769c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15779c2b2975SHarish Zunjarrao } 15789c2b2975SHarish Zunjarrao 15799c2b2975SHarish Zunjarrao static __le32 15809c2b2975SHarish Zunjarrao qla82xx_get_fw_size(struct qla_hw_data *ha) 15819c2b2975SHarish Zunjarrao { 15829c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15839c2b2975SHarish Zunjarrao 15849c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15859c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15869c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15879c2b2975SHarish Zunjarrao if (uri_desc) 15889c2b2975SHarish Zunjarrao return cpu_to_le32(uri_desc->size); 15899c2b2975SHarish Zunjarrao } 15909c2b2975SHarish Zunjarrao 15919c2b2975SHarish Zunjarrao return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15929c2b2975SHarish Zunjarrao } 15939c2b2975SHarish Zunjarrao 15949c2b2975SHarish Zunjarrao static u8 * 15959c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 15969c2b2975SHarish Zunjarrao { 15979c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 15989c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15999c2b2975SHarish Zunjarrao 16009c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 16019c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 16029c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 16039c2b2975SHarish Zunjarrao if (uri_desc) 16049c2b2975SHarish Zunjarrao offset = cpu_to_le32(uri_desc->findex); 16059c2b2975SHarish Zunjarrao } 16069c2b2975SHarish Zunjarrao 16079c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 16089c2b2975SHarish Zunjarrao } 16099c2b2975SHarish Zunjarrao 1610a9083016SGiridhar Malavali /* PCI related functions */ 1611a9083016SGiridhar Malavali char * 1612a9083016SGiridhar Malavali qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1613a9083016SGiridhar Malavali { 1614a9083016SGiridhar Malavali int pcie_reg; 1615a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1616a9083016SGiridhar Malavali char lwstr[6]; 1617a9083016SGiridhar Malavali uint16_t lnk; 1618a9083016SGiridhar Malavali 1619a9083016SGiridhar Malavali pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1620a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1621a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 1622a9083016SGiridhar Malavali 1623a9083016SGiridhar Malavali strcpy(str, "PCIe ("); 1624a9083016SGiridhar Malavali strcat(str, "2.5Gb/s "); 1625a9083016SGiridhar Malavali snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1626a9083016SGiridhar Malavali strcat(str, lwstr); 1627a9083016SGiridhar Malavali return str; 1628a9083016SGiridhar Malavali } 1629a9083016SGiridhar Malavali 1630a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1631a9083016SGiridhar Malavali { 1632a9083016SGiridhar Malavali unsigned long val = 0; 1633a9083016SGiridhar Malavali u32 control; 1634a9083016SGiridhar Malavali 1635a9083016SGiridhar Malavali switch (region) { 1636a9083016SGiridhar Malavali case 0: 1637a9083016SGiridhar Malavali val = 0; 1638a9083016SGiridhar Malavali break; 1639a9083016SGiridhar Malavali case 1: 1640a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1641a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1642a9083016SGiridhar Malavali break; 1643a9083016SGiridhar Malavali } 1644a9083016SGiridhar Malavali return val; 1645a9083016SGiridhar Malavali } 1646a9083016SGiridhar Malavali 1647a9083016SGiridhar Malavali 1648a9083016SGiridhar Malavali int 1649a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1650a9083016SGiridhar Malavali { 1651a9083016SGiridhar Malavali uint32_t len = 0; 1652a9083016SGiridhar Malavali 1653a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16547c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16557c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1656a9083016SGiridhar Malavali goto iospace_error_exit; 1657a9083016SGiridhar Malavali } 1658a9083016SGiridhar Malavali 1659a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1660a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16617c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16627c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1663a9083016SGiridhar Malavali goto iospace_error_exit; 1664a9083016SGiridhar Malavali } 1665a9083016SGiridhar Malavali 1666a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 1667a9083016SGiridhar Malavali ha->nx_pcibase = 1668a9083016SGiridhar Malavali (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1669a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16707c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16717c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1672a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1673a9083016SGiridhar Malavali goto iospace_error_exit; 1674a9083016SGiridhar Malavali } 1675a9083016SGiridhar Malavali 1676a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 1677a9083016SGiridhar Malavali ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1678a9083016SGiridhar Malavali 0xbc000 + (ha->pdev->devfn << 11)); 1679a9083016SGiridhar Malavali 1680a9083016SGiridhar Malavali if (!ql2xdbwr) { 1681a9083016SGiridhar Malavali ha->nxdb_wr_ptr = 1682a9083016SGiridhar Malavali (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1683a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1684a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16857c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16867c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1687a9083016SGiridhar Malavali pci_release_regions(ha->pdev); 1688a9083016SGiridhar Malavali goto iospace_error_exit; 1689a9083016SGiridhar Malavali } 1690a9083016SGiridhar Malavali 1691a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1692a9083016SGiridhar Malavali * door bell read and write pointer 1693a9083016SGiridhar Malavali */ 1694a9083016SGiridhar Malavali ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1695a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1696a9083016SGiridhar Malavali } else { 1697a9083016SGiridhar Malavali ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1698a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1699a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1700a9083016SGiridhar Malavali } 1701a9083016SGiridhar Malavali 1702a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1703a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 17047c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 17057c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17067c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17077c3df132SSaurav Kashyap ha->nx_pcibase, ha->iobase, 17087c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 17097c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 17107c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 17117c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 17127c3df132SSaurav Kashyap ha->nx_pcibase, ha->iobase, 17137c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1714a9083016SGiridhar Malavali return 0; 1715a9083016SGiridhar Malavali 1716a9083016SGiridhar Malavali iospace_error_exit: 1717a9083016SGiridhar Malavali return -ENOMEM; 1718a9083016SGiridhar Malavali } 1719a9083016SGiridhar Malavali 1720a9083016SGiridhar Malavali /* GS related functions */ 1721a9083016SGiridhar Malavali 1722a9083016SGiridhar Malavali /* Initialization related functions */ 1723a9083016SGiridhar Malavali 1724a9083016SGiridhar Malavali /** 1725a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1726a9083016SGiridhar Malavali * @ha: HA context 1727a9083016SGiridhar Malavali * 1728a9083016SGiridhar Malavali * Returns 0 on success. 1729a9083016SGiridhar Malavali */ 1730a9083016SGiridhar Malavali int 1731a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1732a9083016SGiridhar Malavali { 1733a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1734a9083016SGiridhar Malavali int ret; 1735a9083016SGiridhar Malavali 1736a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1737a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1738a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17397c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 17407c3df132SSaurav Kashyap "Chip revision:%ld.\n", 17417c3df132SSaurav Kashyap ha->chip_revision); 1742a9083016SGiridhar Malavali return 0; 1743a9083016SGiridhar Malavali } 1744a9083016SGiridhar Malavali 1745a9083016SGiridhar Malavali /** 1746a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1747a9083016SGiridhar Malavali * @ha: HA context 1748a9083016SGiridhar Malavali * 1749a9083016SGiridhar Malavali * Returns 0 on success. 1750a9083016SGiridhar Malavali */ 1751a9083016SGiridhar Malavali void 1752a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1753a9083016SGiridhar Malavali { 1754a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1755a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1756a9083016SGiridhar Malavali } 1757a9083016SGiridhar Malavali 1758a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1759a9083016SGiridhar Malavali { 1760a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1761a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1762a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1763a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1764a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1765a9083016SGiridhar Malavali 1766a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1767a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1768a9083016SGiridhar Malavali icb->request_q_outpointer = __constant_cpu_to_le16(0); 1769a9083016SGiridhar Malavali icb->response_q_inpointer = __constant_cpu_to_le16(0); 1770a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1771a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1772a9083016SGiridhar Malavali icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1773a9083016SGiridhar Malavali icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1774a9083016SGiridhar Malavali icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1775a9083016SGiridhar Malavali icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1776a9083016SGiridhar Malavali 1777a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1778a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1779a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1780a9083016SGiridhar Malavali } 1781a9083016SGiridhar Malavali 1782f1af6208SGiridhar Malavali void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1783f1af6208SGiridhar Malavali { 1784f1af6208SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1785f1af6208SGiridhar Malavali vha->flags.online = 0; 1786f1af6208SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 1787f1af6208SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 1788f1af6208SGiridhar Malavali } 1789f1af6208SGiridhar Malavali 179077e334d2SGiridhar Malavali static int 179177e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1792a9083016SGiridhar Malavali { 1793a9083016SGiridhar Malavali u64 *ptr64; 1794a9083016SGiridhar Malavali u32 i, flashaddr, size; 1795a9083016SGiridhar Malavali __le64 data; 1796a9083016SGiridhar Malavali 1797a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1798a9083016SGiridhar Malavali 17999c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1800a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1801a9083016SGiridhar Malavali 1802a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1803a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 18049c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 18059c2b2975SHarish Zunjarrao return -EIO; 1806a9083016SGiridhar Malavali flashaddr += 8; 1807a9083016SGiridhar Malavali } 1808a9083016SGiridhar Malavali 1809a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 18109c2b2975SHarish Zunjarrao size = (__force u32)qla82xx_get_fw_size(ha) / 8; 18119c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1812a9083016SGiridhar Malavali 1813a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1814a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1815a9083016SGiridhar Malavali 1816a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1817a9083016SGiridhar Malavali return -EIO; 1818a9083016SGiridhar Malavali flashaddr += 8; 1819a9083016SGiridhar Malavali } 18209c2b2975SHarish Zunjarrao udelay(100); 1821a9083016SGiridhar Malavali 1822a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1823a9083016SGiridhar Malavali * at a specified offset to indicate 1824a9083016SGiridhar Malavali * that all data is written and 1825a9083016SGiridhar Malavali * ready for firmware to initialize. 1826a9083016SGiridhar Malavali */ 18279c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1828a9083016SGiridhar Malavali 18299c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1830a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1831a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 18329c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 18339c2b2975SHarish Zunjarrao return 0; 18349c2b2975SHarish Zunjarrao } 18359c2b2975SHarish Zunjarrao 18369c2b2975SHarish Zunjarrao static int 18379c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18389c2b2975SHarish Zunjarrao { 18399c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18409c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18419c2b2975SHarish Zunjarrao uint32_t i; 18429c2b2975SHarish Zunjarrao __le32 entries; 18439c2b2975SHarish Zunjarrao __le32 flags, file_chiprev, offset; 18449c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18459c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18469c2b2975SHarish Zunjarrao int mn_present = 0; 18479c2b2975SHarish Zunjarrao uint32_t flagbit; 18489c2b2975SHarish Zunjarrao 18499c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18509c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18519c2b2975SHarish Zunjarrao if (!ptab_desc) 18529c2b2975SHarish Zunjarrao return -1; 18539c2b2975SHarish Zunjarrao 18549c2b2975SHarish Zunjarrao entries = cpu_to_le32(ptab_desc->num_entries); 18559c2b2975SHarish Zunjarrao 18569c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18579c2b2975SHarish Zunjarrao offset = cpu_to_le32(ptab_desc->findex) + 18589c2b2975SHarish Zunjarrao (i * cpu_to_le32(ptab_desc->entry_size)); 18599c2b2975SHarish Zunjarrao flags = cpu_to_le32(*((int *)&unirom[offset] + 18609c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18619c2b2975SHarish Zunjarrao file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 18629c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18639c2b2975SHarish Zunjarrao 18649c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18659c2b2975SHarish Zunjarrao 18669c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18679c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18689c2b2975SHarish Zunjarrao return 0; 18699c2b2975SHarish Zunjarrao } 18709c2b2975SHarish Zunjarrao } 18719c2b2975SHarish Zunjarrao return -1; 18729c2b2975SHarish Zunjarrao } 18739c2b2975SHarish Zunjarrao 18749c2b2975SHarish Zunjarrao int 18759c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18769c2b2975SHarish Zunjarrao { 18779c2b2975SHarish Zunjarrao __le32 val; 18789c2b2975SHarish Zunjarrao uint32_t min_size; 18799c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18809c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18819c2b2975SHarish Zunjarrao 18829c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18839c2b2975SHarish Zunjarrao 18849c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18859c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18869c2b2975SHarish Zunjarrao return -EINVAL; 18879c2b2975SHarish Zunjarrao 18889c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18899c2b2975SHarish Zunjarrao } else { 18909c2b2975SHarish Zunjarrao val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 18919c2b2975SHarish Zunjarrao if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 18929c2b2975SHarish Zunjarrao return -EINVAL; 18939c2b2975SHarish Zunjarrao 18949c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18959c2b2975SHarish Zunjarrao } 18969c2b2975SHarish Zunjarrao 18979c2b2975SHarish Zunjarrao if (fw->size < min_size) 18989c2b2975SHarish Zunjarrao return -EINVAL; 1899a9083016SGiridhar Malavali return 0; 1900a9083016SGiridhar Malavali } 1901a9083016SGiridhar Malavali 190277e334d2SGiridhar Malavali static int 190377e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1904a9083016SGiridhar Malavali { 1905a9083016SGiridhar Malavali u32 val = 0; 1906a9083016SGiridhar Malavali int retries = 60; 19077c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1908a9083016SGiridhar Malavali 1909a9083016SGiridhar Malavali do { 1910a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1911a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1912a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1913a9083016SGiridhar Malavali 1914a9083016SGiridhar Malavali switch (val) { 1915a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1916a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1917a9083016SGiridhar Malavali return QLA_SUCCESS; 1918a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1919a9083016SGiridhar Malavali break; 1920a9083016SGiridhar Malavali default: 1921a9083016SGiridhar Malavali break; 1922a9083016SGiridhar Malavali } 19237c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 19247c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1925a9083016SGiridhar Malavali val, retries); 1926a9083016SGiridhar Malavali 1927a9083016SGiridhar Malavali msleep(500); 1928a9083016SGiridhar Malavali 1929a9083016SGiridhar Malavali } while (--retries); 1930a9083016SGiridhar Malavali 19317c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1932a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1933a9083016SGiridhar Malavali 1934a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1935a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1936a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1937a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1938a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1939a9083016SGiridhar Malavali } 1940a9083016SGiridhar Malavali 194177e334d2SGiridhar Malavali static int 194277e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1943a9083016SGiridhar Malavali { 1944a9083016SGiridhar Malavali u32 val = 0; 1945a9083016SGiridhar Malavali int retries = 60; 19467c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1947a9083016SGiridhar Malavali 1948a9083016SGiridhar Malavali do { 1949a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1950a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1951a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1952a9083016SGiridhar Malavali 1953a9083016SGiridhar Malavali switch (val) { 1954a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1955a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1956a9083016SGiridhar Malavali return QLA_SUCCESS; 1957a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1958a9083016SGiridhar Malavali break; 1959a9083016SGiridhar Malavali default: 1960a9083016SGiridhar Malavali break; 1961a9083016SGiridhar Malavali } 19627c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19637c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1964a9083016SGiridhar Malavali val, retries); 1965a9083016SGiridhar Malavali 1966a9083016SGiridhar Malavali msleep(500); 1967a9083016SGiridhar Malavali 1968a9083016SGiridhar Malavali } while (--retries); 1969a9083016SGiridhar Malavali 19707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 19717c3df132SSaurav Kashyap "Rcv Peg initializatin failed: 0x%x.\n", val); 1972a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1973a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1974a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1975a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1976a9083016SGiridhar Malavali } 1977a9083016SGiridhar Malavali 1978a9083016SGiridhar Malavali /* ISR related functions */ 1979a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1980a9083016SGiridhar Malavali ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1981a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1982a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1983a9083016SGiridhar Malavali ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1984a9083016SGiridhar Malavali }; 1985a9083016SGiridhar Malavali 1986a9083016SGiridhar Malavali uint32_t qla82xx_isr_int_target_status[8] = { 1987a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1988a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1989a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1990a9083016SGiridhar Malavali ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1991a9083016SGiridhar Malavali }; 1992a9083016SGiridhar Malavali 1993a9083016SGiridhar Malavali static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1994a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1995a9083016SGiridhar Malavali 1996a9083016SGiridhar Malavali /* 1997a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1998a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1999a9083016SGiridhar Malavali * @mb0: Mailbox0 register 2000a9083016SGiridhar Malavali */ 200177e334d2SGiridhar Malavali static void 2002a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2003a9083016SGiridhar Malavali { 2004a9083016SGiridhar Malavali uint16_t cnt; 2005a9083016SGiridhar Malavali uint16_t __iomem *wptr; 2006a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2007a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2008a9083016SGiridhar Malavali wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2009a9083016SGiridhar Malavali 2010a9083016SGiridhar Malavali /* Load return mailbox registers. */ 2011a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 2012a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 2013a9083016SGiridhar Malavali 2014a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2015a9083016SGiridhar Malavali ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2016a9083016SGiridhar Malavali wptr++; 2017a9083016SGiridhar Malavali } 2018a9083016SGiridhar Malavali 2019a9083016SGiridhar Malavali if (ha->mcp) { 20207c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5052, 20217c3df132SSaurav Kashyap "Got mailbox completion. cmd=%x.\n", ha->mcp->mb[0]); 2022a9083016SGiridhar Malavali } else { 20237c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 20247c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 2025a9083016SGiridhar Malavali } 2026a9083016SGiridhar Malavali } 2027a9083016SGiridhar Malavali 2028a9083016SGiridhar Malavali /* 2029a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2030a9083016SGiridhar Malavali * @irq: 2031a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 2032a9083016SGiridhar Malavali * @regs: 2033a9083016SGiridhar Malavali * 2034a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 2035a9083016SGiridhar Malavali * 2036a9083016SGiridhar Malavali * Returns handled flag. 2037a9083016SGiridhar Malavali */ 2038a9083016SGiridhar Malavali irqreturn_t 2039a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 2040a9083016SGiridhar Malavali { 2041a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2042a9083016SGiridhar Malavali struct qla_hw_data *ha; 2043a9083016SGiridhar Malavali struct rsp_que *rsp; 2044a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2045a9083016SGiridhar Malavali int status = 0, status1 = 0; 2046a9083016SGiridhar Malavali unsigned long flags; 2047a9083016SGiridhar Malavali unsigned long iter; 20487c3df132SSaurav Kashyap uint32_t stat = 0; 2049a9083016SGiridhar Malavali uint16_t mb[4]; 2050a9083016SGiridhar Malavali 2051a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2052a9083016SGiridhar Malavali if (!rsp) { 2053a9083016SGiridhar Malavali printk(KERN_INFO 20547c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2055a9083016SGiridhar Malavali return IRQ_NONE; 2056a9083016SGiridhar Malavali } 2057a9083016SGiridhar Malavali ha = rsp->hw; 2058a9083016SGiridhar Malavali 2059a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2060a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2061a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2062a9083016SGiridhar Malavali return IRQ_NONE; 2063a9083016SGiridhar Malavali 2064a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2065a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2066a9083016SGiridhar Malavali return IRQ_NONE; 2067a9083016SGiridhar Malavali } 2068a9083016SGiridhar Malavali 2069a9083016SGiridhar Malavali /* clear the interrupt */ 2070a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2071a9083016SGiridhar Malavali 2072a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2073a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2074a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2075a9083016SGiridhar Malavali 2076a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2077a9083016SGiridhar Malavali 2078a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2079a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2080a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2081a9083016SGiridhar Malavali 2082a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2083a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2084a9083016SGiridhar Malavali 2085a9083016SGiridhar Malavali switch (stat & 0xff) { 2086a9083016SGiridhar Malavali case 0x1: 2087a9083016SGiridhar Malavali case 0x2: 2088a9083016SGiridhar Malavali case 0x10: 2089a9083016SGiridhar Malavali case 0x11: 2090a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2091a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2092a9083016SGiridhar Malavali break; 2093a9083016SGiridhar Malavali case 0x12: 2094a9083016SGiridhar Malavali mb[0] = MSW(stat); 2095a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2096a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2097a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2098a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2099a9083016SGiridhar Malavali break; 2100a9083016SGiridhar Malavali case 0x13: 2101a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2102a9083016SGiridhar Malavali break; 2103a9083016SGiridhar Malavali default: 21047c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2105a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21067c3df132SSaurav Kashyap stat & 0xff); 2107a9083016SGiridhar Malavali break; 2108a9083016SGiridhar Malavali } 2109a9083016SGiridhar Malavali } 2110a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2111a9083016SGiridhar Malavali } 2112a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2113a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) 2114a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2115a9083016SGiridhar Malavali 2116a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2117a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21187c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x503d, 21197c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2120a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2121a9083016SGiridhar Malavali #endif 2122a9083016SGiridhar Malavali 2123a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2124a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2125a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2126a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2127a9083016SGiridhar Malavali } 2128a9083016SGiridhar Malavali return IRQ_HANDLED; 2129a9083016SGiridhar Malavali } 2130a9083016SGiridhar Malavali 2131a9083016SGiridhar Malavali irqreturn_t 2132a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2133a9083016SGiridhar Malavali { 2134a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2135a9083016SGiridhar Malavali struct qla_hw_data *ha; 2136a9083016SGiridhar Malavali struct rsp_que *rsp; 2137a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2138a9083016SGiridhar Malavali int status = 0; 2139a9083016SGiridhar Malavali unsigned long flags; 21407c3df132SSaurav Kashyap uint32_t stat = 0; 2141a9083016SGiridhar Malavali uint16_t mb[4]; 2142a9083016SGiridhar Malavali 2143a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2144a9083016SGiridhar Malavali if (!rsp) { 2145a9083016SGiridhar Malavali printk(KERN_INFO 21467c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2147a9083016SGiridhar Malavali return IRQ_NONE; 2148a9083016SGiridhar Malavali } 2149a9083016SGiridhar Malavali ha = rsp->hw; 2150a9083016SGiridhar Malavali 2151a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2152a9083016SGiridhar Malavali 2153a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2154a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2155a9083016SGiridhar Malavali do { 2156a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2157a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2158a9083016SGiridhar Malavali 2159a9083016SGiridhar Malavali switch (stat & 0xff) { 2160a9083016SGiridhar Malavali case 0x1: 2161a9083016SGiridhar Malavali case 0x2: 2162a9083016SGiridhar Malavali case 0x10: 2163a9083016SGiridhar Malavali case 0x11: 2164a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2165a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2166a9083016SGiridhar Malavali break; 2167a9083016SGiridhar Malavali case 0x12: 2168a9083016SGiridhar Malavali mb[0] = MSW(stat); 2169a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2170a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2171a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2172a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2173a9083016SGiridhar Malavali break; 2174a9083016SGiridhar Malavali case 0x13: 2175a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2176a9083016SGiridhar Malavali break; 2177a9083016SGiridhar Malavali default: 21787c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2179a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21807c3df132SSaurav Kashyap stat & 0xff); 2181a9083016SGiridhar Malavali break; 2182a9083016SGiridhar Malavali } 2183a9083016SGiridhar Malavali } 2184a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2185a9083016SGiridhar Malavali } while (0); 2186a9083016SGiridhar Malavali 2187a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2188a9083016SGiridhar Malavali 2189a9083016SGiridhar Malavali #ifdef QL_DEBUG_LEVEL_17 2190a9083016SGiridhar Malavali if (!irq && ha->flags.eeh_busy) 21917c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x5044, 21927c3df132SSaurav Kashyap "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2193a9083016SGiridhar Malavali status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2194a9083016SGiridhar Malavali #endif 2195a9083016SGiridhar Malavali 2196a9083016SGiridhar Malavali if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2197a9083016SGiridhar Malavali (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2198a9083016SGiridhar Malavali set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2199a9083016SGiridhar Malavali complete(&ha->mbx_intr_comp); 2200a9083016SGiridhar Malavali } 2201a9083016SGiridhar Malavali return IRQ_HANDLED; 2202a9083016SGiridhar Malavali } 2203a9083016SGiridhar Malavali 2204a9083016SGiridhar Malavali irqreturn_t 2205a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2206a9083016SGiridhar Malavali { 2207a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2208a9083016SGiridhar Malavali struct qla_hw_data *ha; 2209a9083016SGiridhar Malavali struct rsp_que *rsp; 2210a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 22113553d343SSaurav Kashyap unsigned long flags; 2212a9083016SGiridhar Malavali 2213a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2214a9083016SGiridhar Malavali if (!rsp) { 2215a9083016SGiridhar Malavali printk(KERN_INFO 22167c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2217a9083016SGiridhar Malavali return IRQ_NONE; 2218a9083016SGiridhar Malavali } 2219a9083016SGiridhar Malavali 2220a9083016SGiridhar Malavali ha = rsp->hw; 2221a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 22223553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2223a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2224a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2225a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 22263553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2227a9083016SGiridhar Malavali return IRQ_HANDLED; 2228a9083016SGiridhar Malavali } 2229a9083016SGiridhar Malavali 2230a9083016SGiridhar Malavali void 2231a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2232a9083016SGiridhar Malavali { 2233a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2234a9083016SGiridhar Malavali struct qla_hw_data *ha; 2235a9083016SGiridhar Malavali struct rsp_que *rsp; 2236a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2237a9083016SGiridhar Malavali int status = 0; 2238a9083016SGiridhar Malavali uint32_t stat; 2239a9083016SGiridhar Malavali uint16_t mb[4]; 2240a9083016SGiridhar Malavali unsigned long flags; 2241a9083016SGiridhar Malavali 2242a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2243a9083016SGiridhar Malavali if (!rsp) { 2244a9083016SGiridhar Malavali printk(KERN_INFO 22457c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2246a9083016SGiridhar Malavali return; 2247a9083016SGiridhar Malavali } 2248a9083016SGiridhar Malavali ha = rsp->hw; 2249a9083016SGiridhar Malavali 2250a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2251a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2252a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2253a9083016SGiridhar Malavali 2254a9083016SGiridhar Malavali if (RD_REG_DWORD(®->host_int)) { 2255a9083016SGiridhar Malavali stat = RD_REG_DWORD(®->host_status); 2256a9083016SGiridhar Malavali switch (stat & 0xff) { 2257a9083016SGiridhar Malavali case 0x1: 2258a9083016SGiridhar Malavali case 0x2: 2259a9083016SGiridhar Malavali case 0x10: 2260a9083016SGiridhar Malavali case 0x11: 2261a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2262a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2263a9083016SGiridhar Malavali break; 2264a9083016SGiridhar Malavali case 0x12: 2265a9083016SGiridhar Malavali mb[0] = MSW(stat); 2266a9083016SGiridhar Malavali mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2267a9083016SGiridhar Malavali mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2268a9083016SGiridhar Malavali mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2269a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2270a9083016SGiridhar Malavali break; 2271a9083016SGiridhar Malavali case 0x13: 2272a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2273a9083016SGiridhar Malavali break; 2274a9083016SGiridhar Malavali default: 22757c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22767c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22777c3df132SSaurav Kashyap stat * 0xff); 2278a9083016SGiridhar Malavali break; 2279a9083016SGiridhar Malavali } 2280a9083016SGiridhar Malavali } 2281a9083016SGiridhar Malavali WRT_REG_DWORD(®->host_int, 0); 2282a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2283a9083016SGiridhar Malavali } 2284a9083016SGiridhar Malavali 2285a9083016SGiridhar Malavali void 2286a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2287a9083016SGiridhar Malavali { 2288a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2289a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2290a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2291a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2292a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2293a9083016SGiridhar Malavali ha->interrupts_on = 1; 2294a9083016SGiridhar Malavali } 2295a9083016SGiridhar Malavali 2296a9083016SGiridhar Malavali void 2297a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2298a9083016SGiridhar Malavali { 2299a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2300a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2301a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 2302a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2303a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2304a9083016SGiridhar Malavali ha->interrupts_on = 0; 2305a9083016SGiridhar Malavali } 2306a9083016SGiridhar Malavali 2307a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2308a9083016SGiridhar Malavali { 2309a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2310a9083016SGiridhar Malavali 2311a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2312a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2313a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2314a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2315a9083016SGiridhar Malavali ha->curr_window = 255; 2316a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2317a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2318a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2319a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2320a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2321a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2322a9083016SGiridhar Malavali } 2323a9083016SGiridhar Malavali 2324a5b36321SLalit Chandivade inline void 2325a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2326a9083016SGiridhar Malavali { 2327a9083016SGiridhar Malavali uint32_t drv_active; 2328a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2329a9083016SGiridhar Malavali 2330a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2331a9083016SGiridhar Malavali 2332a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2333a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 233477e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 233577e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2336a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2337a9083016SGiridhar Malavali } 233877e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2339a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2340a9083016SGiridhar Malavali } 2341a9083016SGiridhar Malavali 2342a9083016SGiridhar Malavali inline void 2343a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2344a9083016SGiridhar Malavali { 2345a9083016SGiridhar Malavali uint32_t drv_active; 2346a9083016SGiridhar Malavali 2347a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 234877e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2349a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2350a9083016SGiridhar Malavali } 2351a9083016SGiridhar Malavali 2352a9083016SGiridhar Malavali static inline int 2353a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2354a9083016SGiridhar Malavali { 2355a9083016SGiridhar Malavali uint32_t drv_state; 2356a9083016SGiridhar Malavali int rval; 2357a9083016SGiridhar Malavali 2358a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 235977e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2360a9083016SGiridhar Malavali return rval; 2361a9083016SGiridhar Malavali } 2362a9083016SGiridhar Malavali 2363a9083016SGiridhar Malavali static inline void 2364a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2365a9083016SGiridhar Malavali { 2366a9083016SGiridhar Malavali uint32_t drv_state; 2367a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2368a9083016SGiridhar Malavali 2369a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2370a9083016SGiridhar Malavali 2371a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2372a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 237377e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2374a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2375a9083016SGiridhar Malavali } 2376a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 23777c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00bb, 23787c3df132SSaurav Kashyap "drv_state = 0x%x.\n", drv_state); 2379a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2380a9083016SGiridhar Malavali } 2381a9083016SGiridhar Malavali 2382a9083016SGiridhar Malavali static inline void 2383a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2384a9083016SGiridhar Malavali { 2385a9083016SGiridhar Malavali uint32_t drv_state; 2386a9083016SGiridhar Malavali 2387a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2388a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2389a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2390a9083016SGiridhar Malavali } 2391a9083016SGiridhar Malavali 2392a9083016SGiridhar Malavali static inline void 2393a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2394a9083016SGiridhar Malavali { 2395a9083016SGiridhar Malavali uint32_t qsnt_state; 2396a9083016SGiridhar Malavali 2397a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2398a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2399a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2400a9083016SGiridhar Malavali } 2401a9083016SGiridhar Malavali 2402579d12b5SSaurav Kashyap void 2403579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2404579d12b5SSaurav Kashyap { 2405579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2406579d12b5SSaurav Kashyap uint32_t qsnt_state; 2407579d12b5SSaurav Kashyap 2408579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2409579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2410579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2411579d12b5SSaurav Kashyap } 2412579d12b5SSaurav Kashyap 241377e334d2SGiridhar Malavali static int 241477e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2415a9083016SGiridhar Malavali { 2416a9083016SGiridhar Malavali int rst; 2417a9083016SGiridhar Malavali struct fw_blob *blob; 2418a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2419a9083016SGiridhar Malavali 2420a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 24217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 24227c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2423a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2424a9083016SGiridhar Malavali } 2425a9083016SGiridhar Malavali udelay(500); 2426a9083016SGiridhar Malavali 2427a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2428a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2429a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2430a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2431a9083016SGiridhar Malavali 2432a9083016SGiridhar Malavali /* 2433a9083016SGiridhar Malavali * FW Load priority: 2434a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2435a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2436a9083016SGiridhar Malavali */ 2437a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2438a9083016SGiridhar Malavali goto try_blob_fw; 2439a9083016SGiridhar Malavali 24407c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24417c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2442a9083016SGiridhar Malavali 2443a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24447c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 24457c3df132SSaurav Kashyap "Firmware loaded successully from flash.\n"); 2446a9083016SGiridhar Malavali return QLA_SUCCESS; 2447875efad7SChad Dupuis } else { 24487c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24497c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2450a9083016SGiridhar Malavali } 2451875efad7SChad Dupuis 2452a9083016SGiridhar Malavali try_blob_fw: 24537c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24547c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2455a9083016SGiridhar Malavali 2456a9083016SGiridhar Malavali /* Load firmware blob. */ 2457a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2458a9083016SGiridhar Malavali if (!blob) { 24597c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 24607c3df132SSaurav Kashyap "Firmware image not preset.\n"); 2461a9083016SGiridhar Malavali goto fw_load_failed; 2462a9083016SGiridhar Malavali } 2463a9083016SGiridhar Malavali 24649c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24659c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24669c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24679c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24689c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24699c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24707c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24717c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24729c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24739c2b2975SHarish Zunjarrao } 24749c2b2975SHarish Zunjarrao } 24759c2b2975SHarish Zunjarrao 2476a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24777c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24787c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2479a9083016SGiridhar Malavali return QLA_SUCCESS; 2480a9083016SGiridhar Malavali } else { 24817c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24827c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2483a9083016SGiridhar Malavali blob->fw = NULL; 2484a9083016SGiridhar Malavali blob = NULL; 2485a9083016SGiridhar Malavali goto fw_load_failed; 2486a9083016SGiridhar Malavali } 2487a9083016SGiridhar Malavali return QLA_SUCCESS; 2488a9083016SGiridhar Malavali 2489a9083016SGiridhar Malavali fw_load_failed: 2490a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2491a9083016SGiridhar Malavali } 2492a9083016SGiridhar Malavali 2493a5b36321SLalit Chandivade int 2494a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2495a9083016SGiridhar Malavali { 2496a9083016SGiridhar Malavali int pcie_cap; 2497a9083016SGiridhar Malavali uint16_t lnk; 2498a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2499a9083016SGiridhar Malavali 2500a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 250177e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2502a9083016SGiridhar Malavali 25033711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 25043711333dSGiridhar Malavali * of 0 before resetting the hardware 25053711333dSGiridhar Malavali */ 25063711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 25073711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 25083711333dSGiridhar Malavali 2509a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2510a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2511a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2512a9083016SGiridhar Malavali 2513a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 25147c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 25157c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2516a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2517a9083016SGiridhar Malavali } 2518a9083016SGiridhar Malavali 2519a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2520a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 25217c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 25227c3df132SSaurav Kashyap "Error during card handshake.\n"); 2523a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2524a9083016SGiridhar Malavali } 2525a9083016SGiridhar Malavali 2526a9083016SGiridhar Malavali /* Negotiated Link width */ 2527a9083016SGiridhar Malavali pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2528a9083016SGiridhar Malavali pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2529a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2530a9083016SGiridhar Malavali 2531a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2532a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2533a9083016SGiridhar Malavali } 2534a9083016SGiridhar Malavali 2535a9083016SGiridhar Malavali static inline int 2536a9083016SGiridhar Malavali qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2537a9083016SGiridhar Malavali uint16_t tot_dsds) 2538a9083016SGiridhar Malavali { 2539a9083016SGiridhar Malavali uint32_t *cur_dsd = NULL; 2540a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2541a9083016SGiridhar Malavali struct qla_hw_data *ha; 2542a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2543a9083016SGiridhar Malavali struct scatterlist *cur_seg; 2544a9083016SGiridhar Malavali uint32_t *dsd_seg; 2545a9083016SGiridhar Malavali void *next_dsd; 2546a9083016SGiridhar Malavali uint8_t avail_dsds; 2547a9083016SGiridhar Malavali uint8_t first_iocb = 1; 2548a9083016SGiridhar Malavali uint32_t dsd_list_len; 2549a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2550a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2551a9083016SGiridhar Malavali 2552a9083016SGiridhar Malavali cmd = sp->cmd; 2553a9083016SGiridhar Malavali 2554a9083016SGiridhar Malavali /* Update entry type to indicate Command Type 3 IOCB */ 2555a9083016SGiridhar Malavali *((uint32_t *)(&cmd_pkt->entry_type)) = 2556a9083016SGiridhar Malavali __constant_cpu_to_le32(COMMAND_TYPE_6); 2557a9083016SGiridhar Malavali 2558a9083016SGiridhar Malavali /* No data transfer */ 2559a9083016SGiridhar Malavali if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2560a9083016SGiridhar Malavali cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2561a9083016SGiridhar Malavali return 0; 2562a9083016SGiridhar Malavali } 2563a9083016SGiridhar Malavali 2564a9083016SGiridhar Malavali vha = sp->fcport->vha; 2565a9083016SGiridhar Malavali ha = vha->hw; 2566a9083016SGiridhar Malavali 2567a9083016SGiridhar Malavali /* Set transfer direction */ 2568a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2569a9083016SGiridhar Malavali cmd_pkt->control_flags = 2570a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_WRITE_DATA); 2571a9083016SGiridhar Malavali ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2572a9083016SGiridhar Malavali } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2573a9083016SGiridhar Malavali cmd_pkt->control_flags = 2574a9083016SGiridhar Malavali __constant_cpu_to_le16(CF_READ_DATA); 2575a9083016SGiridhar Malavali ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2576a9083016SGiridhar Malavali } 2577a9083016SGiridhar Malavali 2578a9083016SGiridhar Malavali cur_seg = scsi_sglist(cmd); 2579a9083016SGiridhar Malavali ctx = sp->ctx; 2580a9083016SGiridhar Malavali 2581a9083016SGiridhar Malavali while (tot_dsds) { 2582a9083016SGiridhar Malavali avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2583a9083016SGiridhar Malavali QLA_DSDS_PER_IOCB : tot_dsds; 2584a9083016SGiridhar Malavali tot_dsds -= avail_dsds; 2585a9083016SGiridhar Malavali dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2586a9083016SGiridhar Malavali 2587a9083016SGiridhar Malavali dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2588a9083016SGiridhar Malavali struct dsd_dma, list); 2589a9083016SGiridhar Malavali next_dsd = dsd_ptr->dsd_addr; 2590a9083016SGiridhar Malavali list_del(&dsd_ptr->list); 2591a9083016SGiridhar Malavali ha->gbl_dsd_avail--; 2592a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2593a9083016SGiridhar Malavali ctx->dsd_use_cnt++; 2594a9083016SGiridhar Malavali ha->gbl_dsd_inuse++; 2595a9083016SGiridhar Malavali 2596a9083016SGiridhar Malavali if (first_iocb) { 2597a9083016SGiridhar Malavali first_iocb = 0; 2598a9083016SGiridhar Malavali dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2599a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2600a9083016SGiridhar Malavali *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2601fa96d927SAndrew Vasquez *dsd_seg++ = cpu_to_le32(dsd_list_len); 2602a9083016SGiridhar Malavali } else { 2603a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2604a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2605fa96d927SAndrew Vasquez *cur_dsd++ = cpu_to_le32(dsd_list_len); 2606a9083016SGiridhar Malavali } 2607a9083016SGiridhar Malavali cur_dsd = (uint32_t *)next_dsd; 2608a9083016SGiridhar Malavali while (avail_dsds) { 2609a9083016SGiridhar Malavali dma_addr_t sle_dma; 2610a9083016SGiridhar Malavali 2611a9083016SGiridhar Malavali sle_dma = sg_dma_address(cur_seg); 2612a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2613a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2614a9083016SGiridhar Malavali *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2615aa5cbf8aSGiridhar Malavali cur_seg = sg_next(cur_seg); 2616a9083016SGiridhar Malavali avail_dsds--; 2617a9083016SGiridhar Malavali } 2618a9083016SGiridhar Malavali } 2619a9083016SGiridhar Malavali 2620a9083016SGiridhar Malavali /* Null termination */ 2621a9083016SGiridhar Malavali *cur_dsd++ = 0; 2622a9083016SGiridhar Malavali *cur_dsd++ = 0; 2623a9083016SGiridhar Malavali *cur_dsd++ = 0; 2624a9083016SGiridhar Malavali cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2625a9083016SGiridhar Malavali return 0; 2626a9083016SGiridhar Malavali } 2627a9083016SGiridhar Malavali 2628a9083016SGiridhar Malavali /* 2629a9083016SGiridhar Malavali * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2630a9083016SGiridhar Malavali * for Command Type 6. 2631a9083016SGiridhar Malavali * 2632a9083016SGiridhar Malavali * @dsds: number of data segment decriptors needed 2633a9083016SGiridhar Malavali * 2634a9083016SGiridhar Malavali * Returns the number of dsd list needed to store @dsds. 2635a9083016SGiridhar Malavali */ 2636a9083016SGiridhar Malavali inline uint16_t 2637a9083016SGiridhar Malavali qla82xx_calc_dsd_lists(uint16_t dsds) 2638a9083016SGiridhar Malavali { 2639a9083016SGiridhar Malavali uint16_t dsd_lists = 0; 2640a9083016SGiridhar Malavali 2641a9083016SGiridhar Malavali dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2642a9083016SGiridhar Malavali if (dsds % QLA_DSDS_PER_IOCB) 2643a9083016SGiridhar Malavali dsd_lists++; 2644a9083016SGiridhar Malavali return dsd_lists; 2645a9083016SGiridhar Malavali } 2646a9083016SGiridhar Malavali 2647a9083016SGiridhar Malavali /* 2648a9083016SGiridhar Malavali * qla82xx_start_scsi() - Send a SCSI command to the ISP 2649a9083016SGiridhar Malavali * @sp: command to send to the ISP 2650a9083016SGiridhar Malavali * 265125985edcSLucas De Marchi * Returns non-zero if a failure occurred, else zero. 2652a9083016SGiridhar Malavali */ 2653a9083016SGiridhar Malavali int 2654a9083016SGiridhar Malavali qla82xx_start_scsi(srb_t *sp) 2655a9083016SGiridhar Malavali { 2656a9083016SGiridhar Malavali int ret, nseg; 2657a9083016SGiridhar Malavali unsigned long flags; 2658a9083016SGiridhar Malavali struct scsi_cmnd *cmd; 2659a9083016SGiridhar Malavali uint32_t *clr_ptr; 2660a9083016SGiridhar Malavali uint32_t index; 2661a9083016SGiridhar Malavali uint32_t handle; 2662a9083016SGiridhar Malavali uint16_t cnt; 2663a9083016SGiridhar Malavali uint16_t req_cnt; 2664a9083016SGiridhar Malavali uint16_t tot_dsds; 2665a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2666a9083016SGiridhar Malavali uint32_t dbval; 2667a9083016SGiridhar Malavali uint32_t *fcp_dl; 2668a9083016SGiridhar Malavali uint8_t additional_cdb_len; 2669a9083016SGiridhar Malavali struct ct6_dsd *ctx; 2670a9083016SGiridhar Malavali struct scsi_qla_host *vha = sp->fcport->vha; 2671a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2672a9083016SGiridhar Malavali struct req_que *req = NULL; 2673a9083016SGiridhar Malavali struct rsp_que *rsp = NULL; 2674ff2fc42eSAndrew Vasquez char tag[2]; 2675a9083016SGiridhar Malavali 2676a9083016SGiridhar Malavali /* Setup device pointers. */ 2677a9083016SGiridhar Malavali ret = 0; 2678a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2679a9083016SGiridhar Malavali cmd = sp->cmd; 2680a9083016SGiridhar Malavali req = vha->req; 2681a9083016SGiridhar Malavali rsp = ha->rsp_q_map[0]; 2682a9083016SGiridhar Malavali 2683a9083016SGiridhar Malavali /* So we know we haven't pci_map'ed anything yet */ 2684a9083016SGiridhar Malavali tot_dsds = 0; 2685a9083016SGiridhar Malavali 2686a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2687a9083016SGiridhar Malavali 2688a9083016SGiridhar Malavali /* Send marker if required */ 2689a9083016SGiridhar Malavali if (vha->marker_needed != 0) { 2690a9083016SGiridhar Malavali if (qla2x00_marker(vha, req, 26917c3df132SSaurav Kashyap rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) { 26927c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x300c, 26937c3df132SSaurav Kashyap "qla2x00_marker failed for cmd=%p.\n", cmd); 2694a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 26957c3df132SSaurav Kashyap } 2696a9083016SGiridhar Malavali vha->marker_needed = 0; 2697a9083016SGiridhar Malavali } 2698a9083016SGiridhar Malavali 2699a9083016SGiridhar Malavali /* Acquire ring specific lock */ 2700a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2701a9083016SGiridhar Malavali 2702a9083016SGiridhar Malavali /* Check for room in outstanding command list. */ 2703a9083016SGiridhar Malavali handle = req->current_outstanding_cmd; 2704a9083016SGiridhar Malavali for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2705a9083016SGiridhar Malavali handle++; 2706a9083016SGiridhar Malavali if (handle == MAX_OUTSTANDING_COMMANDS) 2707a9083016SGiridhar Malavali handle = 1; 2708a9083016SGiridhar Malavali if (!req->outstanding_cmds[handle]) 2709a9083016SGiridhar Malavali break; 2710a9083016SGiridhar Malavali } 2711a9083016SGiridhar Malavali if (index == MAX_OUTSTANDING_COMMANDS) 2712a9083016SGiridhar Malavali goto queuing_error; 2713a9083016SGiridhar Malavali 2714a9083016SGiridhar Malavali /* Map the sg table so we have an accurate count of sg entries needed */ 2715a9083016SGiridhar Malavali if (scsi_sg_count(cmd)) { 2716a9083016SGiridhar Malavali nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2717a9083016SGiridhar Malavali scsi_sg_count(cmd), cmd->sc_data_direction); 2718a9083016SGiridhar Malavali if (unlikely(!nseg)) 2719a9083016SGiridhar Malavali goto queuing_error; 2720a9083016SGiridhar Malavali } else 2721a9083016SGiridhar Malavali nseg = 0; 2722a9083016SGiridhar Malavali 2723a9083016SGiridhar Malavali tot_dsds = nseg; 2724a9083016SGiridhar Malavali 2725a9083016SGiridhar Malavali if (tot_dsds > ql2xshiftctondsd) { 2726a9083016SGiridhar Malavali struct cmd_type_6 *cmd_pkt; 2727a9083016SGiridhar Malavali uint16_t more_dsd_lists = 0; 2728a9083016SGiridhar Malavali struct dsd_dma *dsd_ptr; 2729a9083016SGiridhar Malavali uint16_t i; 2730a9083016SGiridhar Malavali 2731a9083016SGiridhar Malavali more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 27327c3df132SSaurav Kashyap if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) { 27337c3df132SSaurav Kashyap ql_dbg(ql_dbg_io, vha, 0x300d, 27347c3df132SSaurav Kashyap "Num of DSD list %d is than %d for cmd=%p.\n", 27357c3df132SSaurav Kashyap more_dsd_lists + ha->gbl_dsd_inuse, NUM_DSD_CHAIN, 27367c3df132SSaurav Kashyap cmd); 2737a9083016SGiridhar Malavali goto queuing_error; 27387c3df132SSaurav Kashyap } 2739a9083016SGiridhar Malavali 2740a9083016SGiridhar Malavali if (more_dsd_lists <= ha->gbl_dsd_avail) 2741a9083016SGiridhar Malavali goto sufficient_dsds; 2742a9083016SGiridhar Malavali else 2743a9083016SGiridhar Malavali more_dsd_lists -= ha->gbl_dsd_avail; 2744a9083016SGiridhar Malavali 2745a9083016SGiridhar Malavali for (i = 0; i < more_dsd_lists; i++) { 2746a9083016SGiridhar Malavali dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 27477c3df132SSaurav Kashyap if (!dsd_ptr) { 27487c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x300e, 27497c3df132SSaurav Kashyap "Failed to allocate memory for dsd_dma " 27507c3df132SSaurav Kashyap "for cmd=%p.\n", cmd); 2751a9083016SGiridhar Malavali goto queuing_error; 27527c3df132SSaurav Kashyap } 2753a9083016SGiridhar Malavali 2754a9083016SGiridhar Malavali dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2755a9083016SGiridhar Malavali GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2756a9083016SGiridhar Malavali if (!dsd_ptr->dsd_addr) { 2757a9083016SGiridhar Malavali kfree(dsd_ptr); 27587c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x300f, 27597c3df132SSaurav Kashyap "Failed to allocate memory for dsd_addr " 27607c3df132SSaurav Kashyap "for cmd=%p.\n", cmd); 2761a9083016SGiridhar Malavali goto queuing_error; 2762a9083016SGiridhar Malavali } 2763a9083016SGiridhar Malavali list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2764a9083016SGiridhar Malavali ha->gbl_dsd_avail++; 2765a9083016SGiridhar Malavali } 2766a9083016SGiridhar Malavali 2767a9083016SGiridhar Malavali sufficient_dsds: 2768a9083016SGiridhar Malavali req_cnt = 1; 2769a9083016SGiridhar Malavali 27701bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 27711bd58b89SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 27721bd58b89SGiridhar Malavali ®->req_q_out[0]); 27731bd58b89SGiridhar Malavali if (req->ring_index < cnt) 27741bd58b89SGiridhar Malavali req->cnt = cnt - req->ring_index; 27751bd58b89SGiridhar Malavali else 27761bd58b89SGiridhar Malavali req->cnt = req->length - 27771bd58b89SGiridhar Malavali (req->ring_index - cnt); 27781bd58b89SGiridhar Malavali } 27791bd58b89SGiridhar Malavali 27801bd58b89SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 27811bd58b89SGiridhar Malavali goto queuing_error; 27821bd58b89SGiridhar Malavali 2783a9083016SGiridhar Malavali ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2784a9083016SGiridhar Malavali if (!sp->ctx) { 27857c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x3010, 27867c3df132SSaurav Kashyap "Failed to allocate ctx for cmd=%p.\n", cmd); 2787a9083016SGiridhar Malavali goto queuing_error; 2788a9083016SGiridhar Malavali } 2789a9083016SGiridhar Malavali memset(ctx, 0, sizeof(struct ct6_dsd)); 2790a9083016SGiridhar Malavali ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2791a9083016SGiridhar Malavali GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2792a9083016SGiridhar Malavali if (!ctx->fcp_cmnd) { 27937c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x3011, 27947c3df132SSaurav Kashyap "Failed to allocate fcp_cmnd for cmd=%p.\n", cmd); 2795a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2796a9083016SGiridhar Malavali } 2797a9083016SGiridhar Malavali 2798a9083016SGiridhar Malavali /* Initialize the DSD list and dma handle */ 2799a9083016SGiridhar Malavali INIT_LIST_HEAD(&ctx->dsd_list); 2800a9083016SGiridhar Malavali ctx->dsd_use_cnt = 0; 2801a9083016SGiridhar Malavali 2802a9083016SGiridhar Malavali if (cmd->cmd_len > 16) { 2803a9083016SGiridhar Malavali additional_cdb_len = cmd->cmd_len - 16; 2804a9083016SGiridhar Malavali if ((cmd->cmd_len % 4) != 0) { 2805a9083016SGiridhar Malavali /* SCSI command bigger than 16 bytes must be 2806a9083016SGiridhar Malavali * multiple of 4 2807a9083016SGiridhar Malavali */ 28087c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x3012, 28097c3df132SSaurav Kashyap "scsi cmd len %d not multiple of 4 " 28107c3df132SSaurav Kashyap "for cmd=%p.\n", cmd->cmd_len, cmd); 2811a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2812a9083016SGiridhar Malavali } 2813a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2814a9083016SGiridhar Malavali } else { 2815a9083016SGiridhar Malavali additional_cdb_len = 0; 2816a9083016SGiridhar Malavali ctx->fcp_cmnd_len = 12 + 16 + 4; 2817a9083016SGiridhar Malavali } 2818a9083016SGiridhar Malavali 2819a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2820a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2821a9083016SGiridhar Malavali 2822a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2823a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2824a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2825a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2826a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2827a9083016SGiridhar Malavali 2828a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2829a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2830a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2831a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2832a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2833a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2834a9083016SGiridhar Malavali 2835a9083016SGiridhar Malavali /* Build IOCB segments */ 2836a9083016SGiridhar Malavali if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2837a9083016SGiridhar Malavali goto queuing_error_fcp_cmnd; 2838a9083016SGiridhar Malavali 2839a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 284085727e1fSMike Hernandez host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun)); 2841a9083016SGiridhar Malavali 2842ff2fc42eSAndrew Vasquez /* 2843ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2844ff2fc42eSAndrew Vasquez */ 2845ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2846ff2fc42eSAndrew Vasquez switch (tag[0]) { 2847ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2848ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2849ff2fc42eSAndrew Vasquez TSK_HEAD_OF_QUEUE; 2850ff2fc42eSAndrew Vasquez break; 2851ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2852ff2fc42eSAndrew Vasquez ctx->fcp_cmnd->task_attribute = 2853ff2fc42eSAndrew Vasquez TSK_ORDERED; 2854ff2fc42eSAndrew Vasquez break; 2855ff2fc42eSAndrew Vasquez } 2856ff2fc42eSAndrew Vasquez } 2857ff2fc42eSAndrew Vasquez 2858a9083016SGiridhar Malavali /* build FCP_CMND IU */ 2859a9083016SGiridhar Malavali memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 2860a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 2861a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 2862a9083016SGiridhar Malavali 2863a9083016SGiridhar Malavali if (cmd->sc_data_direction == DMA_TO_DEVICE) 2864a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 1; 2865a9083016SGiridhar Malavali else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 2866a9083016SGiridhar Malavali ctx->fcp_cmnd->additional_cdb_len |= 2; 2867a9083016SGiridhar Malavali 2868a9083016SGiridhar Malavali memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2869a9083016SGiridhar Malavali 2870a9083016SGiridhar Malavali fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2871a9083016SGiridhar Malavali additional_cdb_len); 2872a9083016SGiridhar Malavali *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2873a9083016SGiridhar Malavali 2874a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2875a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[0] = 2876a9083016SGiridhar Malavali cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2877a9083016SGiridhar Malavali cmd_pkt->fcp_cmnd_dseg_address[1] = 2878a9083016SGiridhar Malavali cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2879a9083016SGiridhar Malavali 2880a9083016SGiridhar Malavali sp->flags |= SRB_FCP_CMND_DMA_VALID; 2881a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2882a9083016SGiridhar Malavali /* Set total data segment count. */ 2883a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2884a9083016SGiridhar Malavali /* Specify response queue number where 2885a9083016SGiridhar Malavali * completion should happen 2886a9083016SGiridhar Malavali */ 2887a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2888a9083016SGiridhar Malavali } else { 2889a9083016SGiridhar Malavali struct cmd_type_7 *cmd_pkt; 28907c3df132SSaurav Kashyap req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); 2891a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) { 2892a9083016SGiridhar Malavali cnt = (uint16_t)RD_REG_DWORD_RELAXED( 2893a9083016SGiridhar Malavali ®->req_q_out[0]); 2894a9083016SGiridhar Malavali if (req->ring_index < cnt) 2895a9083016SGiridhar Malavali req->cnt = cnt - req->ring_index; 2896a9083016SGiridhar Malavali else 2897a9083016SGiridhar Malavali req->cnt = req->length - 2898a9083016SGiridhar Malavali (req->ring_index - cnt); 2899a9083016SGiridhar Malavali } 2900a9083016SGiridhar Malavali if (req->cnt < (req_cnt + 2)) 2901a9083016SGiridhar Malavali goto queuing_error; 2902a9083016SGiridhar Malavali 2903a9083016SGiridhar Malavali cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 2904a9083016SGiridhar Malavali cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2905a9083016SGiridhar Malavali 2906a9083016SGiridhar Malavali /* Zero out remaining portion of packet. */ 2907a9083016SGiridhar Malavali /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 2908a9083016SGiridhar Malavali clr_ptr = (uint32_t *)cmd_pkt + 2; 2909a9083016SGiridhar Malavali memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2910a9083016SGiridhar Malavali cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2911a9083016SGiridhar Malavali 2912a9083016SGiridhar Malavali /* Set NPORT-ID and LUN number*/ 2913a9083016SGiridhar Malavali cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2914a9083016SGiridhar Malavali cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2915a9083016SGiridhar Malavali cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2916a9083016SGiridhar Malavali cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2917a9083016SGiridhar Malavali cmd_pkt->vp_index = sp->fcport->vp_idx; 2918a9083016SGiridhar Malavali 2919a9083016SGiridhar Malavali int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2920a9083016SGiridhar Malavali host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 2921a9083016SGiridhar Malavali sizeof(cmd_pkt->lun)); 2922a9083016SGiridhar Malavali 2923ff2fc42eSAndrew Vasquez /* 2924ff2fc42eSAndrew Vasquez * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2925ff2fc42eSAndrew Vasquez */ 2926ff2fc42eSAndrew Vasquez if (scsi_populate_tag_msg(cmd, tag)) { 2927ff2fc42eSAndrew Vasquez switch (tag[0]) { 2928ff2fc42eSAndrew Vasquez case HEAD_OF_QUEUE_TAG: 2929ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_HEAD_OF_QUEUE; 2930ff2fc42eSAndrew Vasquez break; 2931ff2fc42eSAndrew Vasquez case ORDERED_QUEUE_TAG: 2932ff2fc42eSAndrew Vasquez cmd_pkt->task = TSK_ORDERED; 2933ff2fc42eSAndrew Vasquez break; 2934ff2fc42eSAndrew Vasquez } 2935ff2fc42eSAndrew Vasquez } 2936ff2fc42eSAndrew Vasquez 2937a9083016SGiridhar Malavali /* Load SCSI command packet. */ 2938a9083016SGiridhar Malavali memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 2939a9083016SGiridhar Malavali host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 2940a9083016SGiridhar Malavali 2941a9083016SGiridhar Malavali cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2942a9083016SGiridhar Malavali 2943a9083016SGiridhar Malavali /* Build IOCB segments */ 2944a9083016SGiridhar Malavali qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 2945a9083016SGiridhar Malavali 2946a9083016SGiridhar Malavali /* Set total data segment count. */ 2947a9083016SGiridhar Malavali cmd_pkt->entry_count = (uint8_t)req_cnt; 2948a9083016SGiridhar Malavali /* Specify response queue number where 2949a9083016SGiridhar Malavali * completion should happen. 2950a9083016SGiridhar Malavali */ 2951a9083016SGiridhar Malavali cmd_pkt->entry_status = (uint8_t) rsp->id; 2952a9083016SGiridhar Malavali 2953a9083016SGiridhar Malavali } 2954a9083016SGiridhar Malavali /* Build command packet. */ 2955a9083016SGiridhar Malavali req->current_outstanding_cmd = handle; 2956a9083016SGiridhar Malavali req->outstanding_cmds[handle] = sp; 2957a9083016SGiridhar Malavali sp->handle = handle; 2958a9083016SGiridhar Malavali sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 2959a9083016SGiridhar Malavali req->cnt -= req_cnt; 2960a9083016SGiridhar Malavali wmb(); 2961a9083016SGiridhar Malavali 2962a9083016SGiridhar Malavali /* Adjust ring index. */ 2963a9083016SGiridhar Malavali req->ring_index++; 2964a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2965a9083016SGiridhar Malavali req->ring_index = 0; 2966a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2967a9083016SGiridhar Malavali } else 2968a9083016SGiridhar Malavali req->ring_ptr++; 2969a9083016SGiridhar Malavali 2970a9083016SGiridhar Malavali sp->flags |= SRB_DMA_VALID; 2971a9083016SGiridhar Malavali 2972a9083016SGiridhar Malavali /* Set chip new ring index. */ 2973a9083016SGiridhar Malavali /* write, read and verify logic */ 2974a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2975a9083016SGiridhar Malavali if (ql2xdbwr) 2976a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2977a9083016SGiridhar Malavali else { 2978a9083016SGiridhar Malavali WRT_REG_DWORD( 2979a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2980a9083016SGiridhar Malavali dbval); 2981a9083016SGiridhar Malavali wmb(); 2982a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2983a9083016SGiridhar Malavali WRT_REG_DWORD( 2984a9083016SGiridhar Malavali (unsigned long __iomem *)ha->nxdb_wr_ptr, 2985a9083016SGiridhar Malavali dbval); 2986a9083016SGiridhar Malavali wmb(); 2987a9083016SGiridhar Malavali } 2988a9083016SGiridhar Malavali } 2989a9083016SGiridhar Malavali 2990a9083016SGiridhar Malavali /* Manage unprocessed RIO/ZIO commands in response queue. */ 2991a9083016SGiridhar Malavali if (vha->flags.process_response_queue && 2992a9083016SGiridhar Malavali rsp->ring_ptr->signature != RESPONSE_PROCESSED) 2993a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2994a9083016SGiridhar Malavali 2995a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2996a9083016SGiridhar Malavali return QLA_SUCCESS; 2997a9083016SGiridhar Malavali 2998a9083016SGiridhar Malavali queuing_error_fcp_cmnd: 2999a9083016SGiridhar Malavali dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 3000a9083016SGiridhar Malavali queuing_error: 3001a9083016SGiridhar Malavali if (tot_dsds) 3002a9083016SGiridhar Malavali scsi_dma_unmap(cmd); 3003a9083016SGiridhar Malavali 3004a9083016SGiridhar Malavali if (sp->ctx) { 3005a9083016SGiridhar Malavali mempool_free(sp->ctx, ha->ctx_mempool); 3006a9083016SGiridhar Malavali sp->ctx = NULL; 3007a9083016SGiridhar Malavali } 3008a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 3009a9083016SGiridhar Malavali 3010a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3011a9083016SGiridhar Malavali } 3012a9083016SGiridhar Malavali 301377e334d2SGiridhar Malavali static uint32_t * 3014a9083016SGiridhar Malavali qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 3015a9083016SGiridhar Malavali uint32_t length) 3016a9083016SGiridhar Malavali { 3017a9083016SGiridhar Malavali uint32_t i; 3018a9083016SGiridhar Malavali uint32_t val; 3019a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3020a9083016SGiridhar Malavali 3021a9083016SGiridhar Malavali /* Dword reads to flash. */ 3022a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 3023a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 30247c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 30257c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 3026a9083016SGiridhar Malavali goto done_read; 3027a9083016SGiridhar Malavali } 3028a9083016SGiridhar Malavali dwptr[i] = __constant_cpu_to_le32(val); 3029a9083016SGiridhar Malavali } 3030a9083016SGiridhar Malavali done_read: 3031a9083016SGiridhar Malavali return dwptr; 3032a9083016SGiridhar Malavali } 3033a9083016SGiridhar Malavali 303477e334d2SGiridhar Malavali static int 3035a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 3036a9083016SGiridhar Malavali { 3037a9083016SGiridhar Malavali int ret; 3038a9083016SGiridhar Malavali uint32_t val; 30397c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3040a9083016SGiridhar Malavali 3041a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3042a9083016SGiridhar Malavali if (ret < 0) { 30437c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 30447c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3045a9083016SGiridhar Malavali return ret; 3046a9083016SGiridhar Malavali } 3047a9083016SGiridhar Malavali 3048a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3049a9083016SGiridhar Malavali if (ret < 0) 3050a9083016SGiridhar Malavali goto done_unprotect; 3051a9083016SGiridhar Malavali 30520547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 3053a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3054a9083016SGiridhar Malavali if (ret < 0) { 30550547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3056a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 3057a9083016SGiridhar Malavali } 3058a9083016SGiridhar Malavali 3059a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 30607c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 30617c3df132SSaurav Kashyap "Write disable failed.\n"); 3062a9083016SGiridhar Malavali 3063a9083016SGiridhar Malavali done_unprotect: 3064d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3065a9083016SGiridhar Malavali return ret; 3066a9083016SGiridhar Malavali } 3067a9083016SGiridhar Malavali 306877e334d2SGiridhar Malavali static int 3069a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 3070a9083016SGiridhar Malavali { 3071a9083016SGiridhar Malavali int ret; 3072a9083016SGiridhar Malavali uint32_t val; 30737c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3074a9083016SGiridhar Malavali 3075a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3076a9083016SGiridhar Malavali if (ret < 0) { 30777c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 30787c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3079a9083016SGiridhar Malavali return ret; 3080a9083016SGiridhar Malavali } 3081a9083016SGiridhar Malavali 3082a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 3083a9083016SGiridhar Malavali if (ret < 0) 3084a9083016SGiridhar Malavali goto done_protect; 3085a9083016SGiridhar Malavali 30860547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 3087a9083016SGiridhar Malavali /* LOCK all sectors */ 3088a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 3089a9083016SGiridhar Malavali if (ret < 0) 30907c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 30917c3df132SSaurav Kashyap "Write status register failed.\n"); 3092a9083016SGiridhar Malavali 3093a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 30947c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 30957c3df132SSaurav Kashyap "Write disable failed.\n"); 3096a9083016SGiridhar Malavali done_protect: 3097d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3098a9083016SGiridhar Malavali return ret; 3099a9083016SGiridhar Malavali } 3100a9083016SGiridhar Malavali 310177e334d2SGiridhar Malavali static int 3102a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3103a9083016SGiridhar Malavali { 3104a9083016SGiridhar Malavali int ret = 0; 31057c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3106a9083016SGiridhar Malavali 3107a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 3108a9083016SGiridhar Malavali if (ret < 0) { 31097c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 31107c3df132SSaurav Kashyap "ROM Lock failed.\n"); 3111a9083016SGiridhar Malavali return ret; 3112a9083016SGiridhar Malavali } 3113a9083016SGiridhar Malavali 3114a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 3115a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3116a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3117a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3118a9083016SGiridhar Malavali 3119a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 31207c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 31217c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 3122a9083016SGiridhar Malavali ret = -1; 3123a9083016SGiridhar Malavali goto done; 3124a9083016SGiridhar Malavali } 3125a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 3126a9083016SGiridhar Malavali done: 3127d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3128a9083016SGiridhar Malavali return ret; 3129a9083016SGiridhar Malavali } 3130a9083016SGiridhar Malavali 3131a9083016SGiridhar Malavali /* 3132a9083016SGiridhar Malavali * Address and length are byte address 3133a9083016SGiridhar Malavali */ 3134a9083016SGiridhar Malavali uint8_t * 3135a9083016SGiridhar Malavali qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3136a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3137a9083016SGiridhar Malavali { 3138a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3139a9083016SGiridhar Malavali qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3140a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3141a9083016SGiridhar Malavali return buf; 3142a9083016SGiridhar Malavali } 3143a9083016SGiridhar Malavali 3144a9083016SGiridhar Malavali static int 3145a9083016SGiridhar Malavali qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3146a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 3147a9083016SGiridhar Malavali { 3148a9083016SGiridhar Malavali int ret; 3149a9083016SGiridhar Malavali uint32_t liter; 3150a9083016SGiridhar Malavali uint32_t sec_mask, rest_addr; 3151a9083016SGiridhar Malavali dma_addr_t optrom_dma; 3152a9083016SGiridhar Malavali void *optrom = NULL; 3153a9083016SGiridhar Malavali int page_mode = 0; 3154a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3155a9083016SGiridhar Malavali 3156a9083016SGiridhar Malavali ret = -1; 3157a9083016SGiridhar Malavali 3158a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 3159a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 3160a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 3161a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3162a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 3163a9083016SGiridhar Malavali if (!optrom) { 31647c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 31657c3df132SSaurav Kashyap "Unable to allocate memory " 31667c3df132SSaurav Kashyap "for optron burst write (%x KB).\n", 3167a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 3168a9083016SGiridhar Malavali } 3169a9083016SGiridhar Malavali } 3170a9083016SGiridhar Malavali 3171a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 3172a9083016SGiridhar Malavali sec_mask = ~rest_addr; 3173a9083016SGiridhar Malavali 3174a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 3175a9083016SGiridhar Malavali if (ret) { 31767c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 3177a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 3178a9083016SGiridhar Malavali goto write_done; 3179a9083016SGiridhar Malavali } 3180a9083016SGiridhar Malavali 3181a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3182a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 3183a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 3184a9083016SGiridhar Malavali 3185a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 3186a9083016SGiridhar Malavali if (ret) { 31877c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 31887c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 31897c3df132SSaurav Kashyap faddr); 3190a9083016SGiridhar Malavali break; 3191a9083016SGiridhar Malavali } 3192a9083016SGiridhar Malavali } 3193a9083016SGiridhar Malavali 3194a9083016SGiridhar Malavali /* Go with burst-write. */ 3195a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3196a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 3197a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3198a9083016SGiridhar Malavali 3199a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 3200a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3201a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 3202a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 32037c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 3204a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 3205a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 3206a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 3207a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 32087c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 3209a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 3210a9083016SGiridhar Malavali 3211a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3212a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3213a9083016SGiridhar Malavali optrom = NULL; 3214a9083016SGiridhar Malavali } else { 3215a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 3216a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 3217a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 3218a9083016SGiridhar Malavali continue; 3219a9083016SGiridhar Malavali } 3220a9083016SGiridhar Malavali } 3221a9083016SGiridhar Malavali 3222a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 3223a9083016SGiridhar Malavali cpu_to_le32(*dwptr)); 3224a9083016SGiridhar Malavali if (ret) { 32257c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 32267c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 32277c3df132SSaurav Kashyap faddr, *dwptr); 3228a9083016SGiridhar Malavali break; 3229a9083016SGiridhar Malavali } 3230a9083016SGiridhar Malavali } 3231a9083016SGiridhar Malavali 3232a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 3233a9083016SGiridhar Malavali if (ret) 32347c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 3235a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 3236a9083016SGiridhar Malavali write_done: 3237a9083016SGiridhar Malavali if (optrom) 3238a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 3239a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 3240a9083016SGiridhar Malavali return ret; 3241a9083016SGiridhar Malavali } 3242a9083016SGiridhar Malavali 3243a9083016SGiridhar Malavali int 3244a9083016SGiridhar Malavali qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3245a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 3246a9083016SGiridhar Malavali { 3247a9083016SGiridhar Malavali int rval; 3248a9083016SGiridhar Malavali 3249a9083016SGiridhar Malavali /* Suspend HBA. */ 3250a9083016SGiridhar Malavali scsi_block_requests(vha->host); 3251a9083016SGiridhar Malavali rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3252a9083016SGiridhar Malavali length >> 2); 3253a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 3254a9083016SGiridhar Malavali 3255a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 3256a9083016SGiridhar Malavali if (rval) 3257a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3258a9083016SGiridhar Malavali else 3259a9083016SGiridhar Malavali rval = QLA_SUCCESS; 3260a9083016SGiridhar Malavali return rval; 3261a9083016SGiridhar Malavali } 3262a9083016SGiridhar Malavali 3263a9083016SGiridhar Malavali void 3264a9083016SGiridhar Malavali qla82xx_start_iocbs(srb_t *sp) 3265a9083016SGiridhar Malavali { 3266a9083016SGiridhar Malavali struct qla_hw_data *ha = sp->fcport->vha->hw; 3267a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3268a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 3269a9083016SGiridhar Malavali uint32_t dbval; 3270a9083016SGiridhar Malavali 3271a9083016SGiridhar Malavali /* Adjust ring index. */ 3272a9083016SGiridhar Malavali req->ring_index++; 3273a9083016SGiridhar Malavali if (req->ring_index == req->length) { 3274a9083016SGiridhar Malavali req->ring_index = 0; 3275a9083016SGiridhar Malavali req->ring_ptr = req->ring; 3276a9083016SGiridhar Malavali } else 3277a9083016SGiridhar Malavali req->ring_ptr++; 3278a9083016SGiridhar Malavali 3279a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 3280a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 3281a9083016SGiridhar Malavali 3282a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 32836907869dSGiridhar Malavali if (ql2xdbwr) 32846907869dSGiridhar Malavali qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 32856907869dSGiridhar Malavali else { 3286a9083016SGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3287a9083016SGiridhar Malavali wmb(); 3288a9083016SGiridhar Malavali while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 32896907869dSGiridhar Malavali WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 32906907869dSGiridhar Malavali dbval); 3291a9083016SGiridhar Malavali wmb(); 3292a9083016SGiridhar Malavali } 3293a9083016SGiridhar Malavali } 32946907869dSGiridhar Malavali } 3295a9083016SGiridhar Malavali 3296e6a4202aSShyam Sundar void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 3297e6a4202aSShyam Sundar { 32987c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 32997c3df132SSaurav Kashyap 3300e6a4202aSShyam Sundar if (qla82xx_rom_lock(ha)) 3301e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 33027c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 33037c3df132SSaurav Kashyap "Resetting rom_lock.\n"); 3304e6a4202aSShyam Sundar 3305e6a4202aSShyam Sundar /* 3306e6a4202aSShyam Sundar * Either we got the lock, or someone 3307e6a4202aSShyam Sundar * else died while holding it. 3308e6a4202aSShyam Sundar * In either case, unlock. 3309e6a4202aSShyam Sundar */ 3310d652e093SChad Dupuis qla82xx_rom_unlock(ha); 3311e6a4202aSShyam Sundar } 3312e6a4202aSShyam Sundar 3313a9083016SGiridhar Malavali /* 3314a9083016SGiridhar Malavali * qla82xx_device_bootstrap 3315a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 3316a9083016SGiridhar Malavali * 3317a9083016SGiridhar Malavali * Note: 3318a9083016SGiridhar Malavali * IDC lock must be held upon entry 3319a9083016SGiridhar Malavali * 3320a9083016SGiridhar Malavali * Return: 3321a9083016SGiridhar Malavali * Success : 0 3322a9083016SGiridhar Malavali * Failed : 1 3323a9083016SGiridhar Malavali */ 3324a9083016SGiridhar Malavali static int 3325a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3326a9083016SGiridhar Malavali { 3327e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 3328e6a4202aSShyam Sundar int i, timeout; 3329a9083016SGiridhar Malavali uint32_t old_count, count; 3330a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3331e6a4202aSShyam Sundar int need_reset = 0, peg_stuck = 1; 3332a9083016SGiridhar Malavali 3333e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 3334a9083016SGiridhar Malavali 3335a9083016SGiridhar Malavali old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3336a9083016SGiridhar Malavali 3337a9083016SGiridhar Malavali for (i = 0; i < 10; i++) { 3338a9083016SGiridhar Malavali timeout = msleep_interruptible(200); 3339a9083016SGiridhar Malavali if (timeout) { 3340a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3341a9083016SGiridhar Malavali QLA82XX_DEV_FAILED); 3342a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 3343a9083016SGiridhar Malavali } 3344a9083016SGiridhar Malavali 3345a9083016SGiridhar Malavali count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3346a9083016SGiridhar Malavali if (count != old_count) 3347e6a4202aSShyam Sundar peg_stuck = 0; 3348e6a4202aSShyam Sundar } 3349e6a4202aSShyam Sundar 3350e6a4202aSShyam Sundar if (need_reset) { 3351e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 3352e6a4202aSShyam Sundar if (peg_stuck) 3353e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3354e6a4202aSShyam Sundar goto dev_initialize; 3355e6a4202aSShyam Sundar } else { 3356e6a4202aSShyam Sundar /* Start of day for this ha context. */ 3357e6a4202aSShyam Sundar if (peg_stuck) { 3358e6a4202aSShyam Sundar /* Either we are the first or recovery in progress. */ 3359e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 3360e6a4202aSShyam Sundar goto dev_initialize; 3361e6a4202aSShyam Sundar } else 3362e6a4202aSShyam Sundar /* Firmware already running. */ 3363a9083016SGiridhar Malavali goto dev_ready; 3364a9083016SGiridhar Malavali } 3365a9083016SGiridhar Malavali 3366e6a4202aSShyam Sundar return rval; 3367e6a4202aSShyam Sundar 3368a9083016SGiridhar Malavali dev_initialize: 3369a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 33707c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 33717c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 3372a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3373a9083016SGiridhar Malavali 3374a9083016SGiridhar Malavali /* Driver that sets device state to initializating sets IDC version */ 3375a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3376a9083016SGiridhar Malavali 3377a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3378a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 3379a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3380a9083016SGiridhar Malavali 3381a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 33827c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 33837c3df132SSaurav Kashyap "HW State: FAILED.\n"); 3384a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 3385a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3386a9083016SGiridhar Malavali return rval; 3387a9083016SGiridhar Malavali } 3388a9083016SGiridhar Malavali 3389a9083016SGiridhar Malavali dev_ready: 33907c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 33917c3df132SSaurav Kashyap "HW State: READY.\n"); 3392a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3393a9083016SGiridhar Malavali 3394a9083016SGiridhar Malavali return QLA_SUCCESS; 3395a9083016SGiridhar Malavali } 3396a9083016SGiridhar Malavali 3397579d12b5SSaurav Kashyap /* 3398579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 3399579d12b5SSaurav Kashyap * Code to start quiescence sequence 3400579d12b5SSaurav Kashyap * 3401579d12b5SSaurav Kashyap * Note: 3402579d12b5SSaurav Kashyap * IDC lock must be held upon entry 3403579d12b5SSaurav Kashyap * 3404579d12b5SSaurav Kashyap * Return: void 3405579d12b5SSaurav Kashyap */ 3406579d12b5SSaurav Kashyap 3407579d12b5SSaurav Kashyap static void 3408579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 3409579d12b5SSaurav Kashyap { 3410579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3411579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 3412579d12b5SSaurav Kashyap unsigned long reset_timeout; 3413579d12b5SSaurav Kashyap 3414579d12b5SSaurav Kashyap if (vha->flags.online) { 3415579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 3416579d12b5SSaurav Kashyap qla82xx_quiescent_state_cleanup(vha); 3417579d12b5SSaurav Kashyap } 3418579d12b5SSaurav Kashyap 3419579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 3420579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 3421579d12b5SSaurav Kashyap 3422579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 3423579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 3424579d12b5SSaurav Kashyap 3425579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3426579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3427579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 3428579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3429579d12b5SSaurav Kashyap 3430579d12b5SSaurav Kashyap while (drv_state != drv_active) { 3431579d12b5SSaurav Kashyap 3432579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 3433579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 3434579d12b5SSaurav Kashyap * changing the state to DEV_READY 3435579d12b5SSaurav Kashyap */ 34367c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 34377c3df132SSaurav Kashyap "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 34387c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb024, 34397c3df132SSaurav Kashyap "DRV_ACTIVE:%d DRV_STATE:%d.\n", 34407c3df132SSaurav Kashyap drv_active, drv_state); 3441579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3442579d12b5SSaurav Kashyap QLA82XX_DEV_READY); 34437c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 34447c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 3445579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3446579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 3447579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3448579d12b5SSaurav Kashyap 3449579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 3450579d12b5SSaurav Kashyap return; 3451579d12b5SSaurav Kashyap } 3452579d12b5SSaurav Kashyap 3453579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3454579d12b5SSaurav Kashyap msleep(1000); 3455579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3456579d12b5SSaurav Kashyap 3457579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3458579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3459579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 3460579d12b5SSaurav Kashyap } 3461579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3462579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 3463579d12b5SSaurav Kashyap if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 34647c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 34657c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 3466579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 3467579d12b5SSaurav Kashyap } 3468579d12b5SSaurav Kashyap } 3469579d12b5SSaurav Kashyap 3470579d12b5SSaurav Kashyap /* 3471579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 3472579d12b5SSaurav Kashyap * Wait for device state to change from given current state 3473579d12b5SSaurav Kashyap * 3474579d12b5SSaurav Kashyap * Note: 3475579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 3476579d12b5SSaurav Kashyap * 3477579d12b5SSaurav Kashyap * Return: 3478579d12b5SSaurav Kashyap * Changed device state. 3479579d12b5SSaurav Kashyap */ 3480579d12b5SSaurav Kashyap uint32_t 3481579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3482579d12b5SSaurav Kashyap { 3483579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 3484579d12b5SSaurav Kashyap uint32_t dev_state; 3485579d12b5SSaurav Kashyap 3486579d12b5SSaurav Kashyap do { 3487579d12b5SSaurav Kashyap msleep(1000); 3488579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 3489579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3490579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 3491579d12b5SSaurav Kashyap } while (dev_state == curr_state); 3492579d12b5SSaurav Kashyap 3493579d12b5SSaurav Kashyap return dev_state; 3494579d12b5SSaurav Kashyap } 3495579d12b5SSaurav Kashyap 3496a9083016SGiridhar Malavali static void 3497a9083016SGiridhar Malavali qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3498a9083016SGiridhar Malavali { 3499a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3500a9083016SGiridhar Malavali 3501a9083016SGiridhar Malavali /* Disable the board */ 35027c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 35037c3df132SSaurav Kashyap "Disabling the board.\n"); 3504a9083016SGiridhar Malavali 3505b963752fSGiridhar Malavali qla82xx_idc_lock(ha); 3506b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 3507b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 3508b963752fSGiridhar Malavali 3509a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 3510a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 3511a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3512a9083016SGiridhar Malavali qla2x00_mark_all_devices_lost(vha, 0); 3513a9083016SGiridhar Malavali vha->flags.online = 0; 3514a9083016SGiridhar Malavali vha->flags.init_done = 0; 3515a9083016SGiridhar Malavali } 3516a9083016SGiridhar Malavali 3517a9083016SGiridhar Malavali /* 3518a9083016SGiridhar Malavali * qla82xx_need_reset_handler 3519a9083016SGiridhar Malavali * Code to start reset sequence 3520a9083016SGiridhar Malavali * 3521a9083016SGiridhar Malavali * Note: 3522a9083016SGiridhar Malavali * IDC lock must be held upon entry 3523a9083016SGiridhar Malavali * 3524a9083016SGiridhar Malavali * Return: 3525a9083016SGiridhar Malavali * Success : 0 3526a9083016SGiridhar Malavali * Failed : 1 3527a9083016SGiridhar Malavali */ 3528a9083016SGiridhar Malavali static void 3529a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3530a9083016SGiridhar Malavali { 3531a9083016SGiridhar Malavali uint32_t dev_state, drv_state, drv_active; 3532a9083016SGiridhar Malavali unsigned long reset_timeout; 3533a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3534a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3535a9083016SGiridhar Malavali 3536a9083016SGiridhar Malavali if (vha->flags.online) { 3537a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3538a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3539a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3540a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3541a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3542a9083016SGiridhar Malavali } 3543a9083016SGiridhar Malavali 3544a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 3545a9083016SGiridhar Malavali 3546a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 3547a9083016SGiridhar Malavali reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3548a9083016SGiridhar Malavali 3549a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3550a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3551a9083016SGiridhar Malavali 3552a9083016SGiridhar Malavali while (drv_state != drv_active) { 3553a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 35547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 35557c3df132SSaurav Kashyap "Reset timeout.\n"); 3556a9083016SGiridhar Malavali break; 3557a9083016SGiridhar Malavali } 3558a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3559a9083016SGiridhar Malavali msleep(1000); 3560a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3561a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3562a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3563a9083016SGiridhar Malavali } 3564a9083016SGiridhar Malavali 3565a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 35667c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 35677c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 35687c3df132SSaurav Kashyap dev_state, 3569f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3570f1af6208SGiridhar Malavali 3571a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 3572a9083016SGiridhar Malavali if (dev_state != QLA82XX_DEV_INITIALIZING) { 35737c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 35747c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 3575a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3576a9083016SGiridhar Malavali } 3577a9083016SGiridhar Malavali } 3578a9083016SGiridhar Malavali 35797190575fSGiridhar Malavali int 3580a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3581a9083016SGiridhar Malavali { 35827190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 35837190575fSGiridhar Malavali int status = 0; 3584a9083016SGiridhar Malavali 35857190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 35867190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3587a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 35887c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 35897c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 35907c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 35917c3df132SSaurav Kashyap "returning status=%d.\n", status); 35927190575fSGiridhar Malavali return status; 35937c3df132SSaurav Kashyap } 3594a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3595a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3596a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3597a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3598a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 35997190575fSGiridhar Malavali status = 1; 3600a9083016SGiridhar Malavali } 3601efa786ccSLalit Chandivade } else 3602efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3603a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 36047c3df132SSaurav Kashyap if (status) 36057c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 36067c3df132SSaurav Kashyap "Returning status=%d.\n", status); 36077190575fSGiridhar Malavali return status; 3608a9083016SGiridhar Malavali } 3609a9083016SGiridhar Malavali 3610a9083016SGiridhar Malavali /* 3611a9083016SGiridhar Malavali * qla82xx_device_state_handler 3612a9083016SGiridhar Malavali * Main state handler 3613a9083016SGiridhar Malavali * 3614a9083016SGiridhar Malavali * Note: 3615a9083016SGiridhar Malavali * IDC lock must be held upon entry 3616a9083016SGiridhar Malavali * 3617a9083016SGiridhar Malavali * Return: 3618a9083016SGiridhar Malavali * Success : 0 3619a9083016SGiridhar Malavali * Failed : 1 3620a9083016SGiridhar Malavali */ 3621a9083016SGiridhar Malavali int 3622a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3623a9083016SGiridhar Malavali { 3624a9083016SGiridhar Malavali uint32_t dev_state; 362592dbf273SGiridhar Malavali uint32_t old_dev_state; 3626a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3627a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3628a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 362992dbf273SGiridhar Malavali int loopcount = 0; 3630a9083016SGiridhar Malavali 3631a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3632a9083016SGiridhar Malavali if (!vha->flags.init_done) 3633a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 3634a9083016SGiridhar Malavali 3635a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 363692dbf273SGiridhar Malavali old_dev_state = dev_state; 36377c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 36387c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 36397c3df132SSaurav Kashyap dev_state, 3640f1af6208SGiridhar Malavali dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3641a9083016SGiridhar Malavali 3642a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 3643a9083016SGiridhar Malavali dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3644a9083016SGiridhar Malavali 3645a9083016SGiridhar Malavali while (1) { 3646a9083016SGiridhar Malavali 3647a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 36487c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 36497c3df132SSaurav Kashyap "Device init failed.\n"); 3650a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3651a9083016SGiridhar Malavali break; 3652a9083016SGiridhar Malavali } 3653a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 365492dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 365592dbf273SGiridhar Malavali loopcount = 0; 365692dbf273SGiridhar Malavali old_dev_state = dev_state; 365792dbf273SGiridhar Malavali } 365892dbf273SGiridhar Malavali if (loopcount < 5) { 36597c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 36607c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 36617c3df132SSaurav Kashyap dev_state, 36627c3df132SSaurav Kashyap dev_state < MAX_STATES ? qdev_state[dev_state] : 36637c3df132SSaurav Kashyap "Unknown"); 366492dbf273SGiridhar Malavali } 3665f1af6208SGiridhar Malavali 3666a9083016SGiridhar Malavali switch (dev_state) { 3667a9083016SGiridhar Malavali case QLA82XX_DEV_READY: 3668a9083016SGiridhar Malavali goto exit; 3669a9083016SGiridhar Malavali case QLA82XX_DEV_COLD: 3670a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 3671a9083016SGiridhar Malavali goto exit; 3672a9083016SGiridhar Malavali case QLA82XX_DEV_INITIALIZING: 3673a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3674a9083016SGiridhar Malavali msleep(1000); 3675a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3676a9083016SGiridhar Malavali break; 3677a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_RESET: 3678ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3679a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 36800060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 36810060ddf8SGiridhar Malavali (ha->nx_dev_init_timeout * HZ); 3682a9083016SGiridhar Malavali break; 3683a9083016SGiridhar Malavali case QLA82XX_DEV_NEED_QUIESCENT: 3684579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3685579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3686579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3687579d12b5SSaurav Kashyap * HZ); 3688579d12b5SSaurav Kashyap break; 3689a9083016SGiridhar Malavali case QLA82XX_DEV_QUIESCENT: 3690579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3691579d12b5SSaurav Kashyap * to get changed 3692579d12b5SSaurav Kashyap */ 3693579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 3694579d12b5SSaurav Kashyap goto exit; 3695579d12b5SSaurav Kashyap 3696a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3697a9083016SGiridhar Malavali msleep(1000); 3698a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3699579d12b5SSaurav Kashyap 3700579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3701579d12b5SSaurav Kashyap dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3702579d12b5SSaurav Kashyap * HZ); 3703a9083016SGiridhar Malavali break; 3704a9083016SGiridhar Malavali case QLA82XX_DEV_FAILED: 3705a9083016SGiridhar Malavali qla82xx_dev_failed_handler(vha); 3706a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3707a9083016SGiridhar Malavali goto exit; 3708a9083016SGiridhar Malavali default: 3709a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3710a9083016SGiridhar Malavali msleep(1000); 3711a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3712a9083016SGiridhar Malavali } 371392dbf273SGiridhar Malavali loopcount++; 3714a9083016SGiridhar Malavali } 3715a9083016SGiridhar Malavali exit: 3716a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3717a9083016SGiridhar Malavali return rval; 3718a9083016SGiridhar Malavali } 3719a9083016SGiridhar Malavali 3720a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3721a9083016SGiridhar Malavali { 37227190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3723a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3724a9083016SGiridhar Malavali 3725a9083016SGiridhar Malavali /* don't poll if reset is going on */ 37267190575fSGiridhar Malavali if (!ha->flags.isp82xx_reset_hdlr_active) { 37277190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 37287190575fSGiridhar Malavali if (dev_state == QLA82XX_DEV_NEED_RESET && 37297190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 37307c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 37317c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3732a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3733a9083016SGiridhar Malavali qla2xxx_wake_dpc(vha); 3734579d12b5SSaurav Kashyap } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3735579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 37367c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 37377c3df132SSaurav Kashyap "Quiescent needed.\n"); 3738579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3739579d12b5SSaurav Kashyap qla2xxx_wake_dpc(vha); 3740a9083016SGiridhar Malavali } else { 37417190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 37427190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 37437190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 37447c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6005, 37457c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 37467c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 37477c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 37487c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 37497c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 37500e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 37510e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 37520e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 37530e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 37540e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 37550e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 37560e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 37570e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 37580e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 37590e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 37600e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 37617190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 37627190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 37637190575fSGiridhar Malavali &vha->dpc_flags); 37647190575fSGiridhar Malavali } else { 37657c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 37667c3df132SSaurav Kashyap "Detect abort needed.\n"); 37677190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 37687190575fSGiridhar Malavali &vha->dpc_flags); 37697190575fSGiridhar Malavali } 37707190575fSGiridhar Malavali qla2xxx_wake_dpc(vha); 37717190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 37727190575fSGiridhar Malavali if (ha->flags.mbox_busy) { 37737190575fSGiridhar Malavali ha->flags.mbox_int = 1; 37747c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6007, 37757c3df132SSaurav Kashyap "Due to FW hung, doing " 377624014d04SSaurav Kashyap "premature completion of mbx " 37777c3df132SSaurav Kashyap "command.\n"); 37787190575fSGiridhar Malavali if (test_bit(MBX_INTR_WAIT, 37797190575fSGiridhar Malavali &ha->mbx_cmd_flags)) 37807190575fSGiridhar Malavali complete(&ha->mbx_intr_comp); 37817190575fSGiridhar Malavali } 37827190575fSGiridhar Malavali } 3783a9083016SGiridhar Malavali } 3784a9083016SGiridhar Malavali } 3785a9083016SGiridhar Malavali } 3786a9083016SGiridhar Malavali 3787a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3788a9083016SGiridhar Malavali { 3789a9083016SGiridhar Malavali int rval; 3790a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3791a9083016SGiridhar Malavali return rval; 3792a9083016SGiridhar Malavali } 3793a9083016SGiridhar Malavali 3794a9083016SGiridhar Malavali /* 3795a9083016SGiridhar Malavali * qla82xx_abort_isp 3796a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3797a9083016SGiridhar Malavali * 3798a9083016SGiridhar Malavali * Input: 3799a9083016SGiridhar Malavali * ha = adapter block pointer. 3800a9083016SGiridhar Malavali * 3801a9083016SGiridhar Malavali * Returns: 3802a9083016SGiridhar Malavali * 0 = success 3803a9083016SGiridhar Malavali */ 3804a9083016SGiridhar Malavali int 3805a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3806a9083016SGiridhar Malavali { 3807a9083016SGiridhar Malavali int rval; 3808a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3809a9083016SGiridhar Malavali uint32_t dev_state; 3810a9083016SGiridhar Malavali 3811a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 38127c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 38137c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3814a9083016SGiridhar Malavali return QLA_SUCCESS; 3815a9083016SGiridhar Malavali } 38167190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 1; 3817a9083016SGiridhar Malavali 3818a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3819a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3820f1af6208SGiridhar Malavali if (dev_state == QLA82XX_DEV_READY) { 38217c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x8025, 38227c3df132SSaurav Kashyap "HW State: NEED RESET.\n"); 3823a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3824a9083016SGiridhar Malavali QLA82XX_DEV_NEED_RESET); 3825a9083016SGiridhar Malavali } else 38267c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x8026, 38277c3df132SSaurav Kashyap "Hw State: %s.\n", dev_state < MAX_STATES ? 3828f1af6208SGiridhar Malavali qdev_state[dev_state] : "Unknown"); 3829a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3830a9083016SGiridhar Malavali 3831a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 3832a9083016SGiridhar Malavali 3833a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3834a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3835a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3836a9083016SGiridhar Malavali 3837cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 38387190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 38397190575fSGiridhar Malavali ha->flags.isp82xx_reset_hdlr_active = 0; 3840a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3841cdbb0a4fSSantosh Vernekar } 3842f1af6208SGiridhar Malavali 3843f1af6208SGiridhar Malavali if (rval) { 3844f1af6208SGiridhar Malavali vha->flags.online = 1; 3845f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3846f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 38477c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 38487c3df132SSaurav Kashyap "ISP error recover failed - board " 38497c3df132SSaurav Kashyap "disabled.\n"); 3850f1af6208SGiridhar Malavali /* 3851f1af6208SGiridhar Malavali * The next call disables the board 3852f1af6208SGiridhar Malavali * completely. 3853f1af6208SGiridhar Malavali */ 3854f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3855f1af6208SGiridhar Malavali vha->flags.online = 0; 3856f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3857f1af6208SGiridhar Malavali &vha->dpc_flags); 3858f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3859f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3860f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 38617c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 38627c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 38637c3df132SSaurav Kashyap ha->isp_abort_cnt); 3864f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3865f1af6208SGiridhar Malavali } 3866f1af6208SGiridhar Malavali } else { 3867f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 38687c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 38697c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 38707c3df132SSaurav Kashyap ha->isp_abort_cnt); 3871f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3872f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3873f1af6208SGiridhar Malavali } 3874f1af6208SGiridhar Malavali } 3875a9083016SGiridhar Malavali return rval; 3876a9083016SGiridhar Malavali } 3877a9083016SGiridhar Malavali 3878a9083016SGiridhar Malavali /* 3879a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3880a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3881a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3882a9083016SGiridhar Malavali * chip reset. 3883a9083016SGiridhar Malavali * 3884a9083016SGiridhar Malavali * Input: 3885a9083016SGiridhar Malavali * ha = adapter block pointer. 3886a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3887a9083016SGiridhar Malavali * 3888a9083016SGiridhar Malavali * Returns: 3889a9083016SGiridhar Malavali * 0 = success 3890a9083016SGiridhar Malavali */ 3891a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3892a9083016SGiridhar Malavali { 3893a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3894a9083016SGiridhar Malavali 3895a9083016SGiridhar Malavali if (vha->flags.online) { 3896a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3897a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3898a9083016SGiridhar Malavali } 3899a9083016SGiridhar Malavali 3900a9083016SGiridhar Malavali /* Stop currently executing firmware. 3901a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3902a9083016SGiridhar Malavali */ 3903a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3904a9083016SGiridhar Malavali 3905a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3906a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3907a9083016SGiridhar Malavali 3908a9083016SGiridhar Malavali return rval; 3909a9083016SGiridhar Malavali } 3910a9083016SGiridhar Malavali 3911a9083016SGiridhar Malavali /* 3912a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3913a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3914a9083016SGiridhar Malavali * 3915a9083016SGiridhar Malavali * Note: 3916a9083016SGiridhar Malavali * Does context switching here. 3917a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3918a9083016SGiridhar Malavali * 3919a9083016SGiridhar Malavali * Return: 3920a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3921a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3922a9083016SGiridhar Malavali */ 3923a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3924a9083016SGiridhar Malavali { 3925a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3926a9083016SGiridhar Malavali unsigned long wait_reset; 3927a9083016SGiridhar Malavali 3928a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3929a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3930a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3931a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3932a9083016SGiridhar Malavali 3933a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3934a9083016SGiridhar Malavali schedule_timeout(HZ); 3935a9083016SGiridhar Malavali 3936a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3937a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3938a9083016SGiridhar Malavali status = QLA_SUCCESS; 3939a9083016SGiridhar Malavali break; 3940a9083016SGiridhar Malavali } 3941a9083016SGiridhar Malavali } 39427c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 39437c3df132SSaurav Kashyap "%s status=%d.\n", status); 3944a9083016SGiridhar Malavali 3945a9083016SGiridhar Malavali return status; 3946a9083016SGiridhar Malavali } 39477190575fSGiridhar Malavali 39487190575fSGiridhar Malavali void 39497190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 39507190575fSGiridhar Malavali { 39517190575fSGiridhar Malavali int i; 39527190575fSGiridhar Malavali unsigned long flags; 39537190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 39547190575fSGiridhar Malavali 39557190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 39567190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 39577190575fSGiridhar Malavali * detection only 39587190575fSGiridhar Malavali */ 39597190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 39607190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 39617190575fSGiridhar Malavali msleep(1000); 39627190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 39637190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 39647190575fSGiridhar Malavali if (ha->flags.mbox_busy) { 39657190575fSGiridhar Malavali ha->flags.mbox_int = 1; 39667190575fSGiridhar Malavali complete(&ha->mbx_intr_comp); 39677190575fSGiridhar Malavali } 39687190575fSGiridhar Malavali break; 39697190575fSGiridhar Malavali } 39707190575fSGiridhar Malavali } 39717190575fSGiridhar Malavali } 39727c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 39737c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 39747c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 39757190575fSGiridhar Malavali 39767190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 39777190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 39787190575fSGiridhar Malavali int cnt, que; 39797190575fSGiridhar Malavali srb_t *sp; 39807190575fSGiridhar Malavali struct req_que *req; 39817190575fSGiridhar Malavali 39827190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 39837190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 39847190575fSGiridhar Malavali req = ha->req_q_map[que]; 39857190575fSGiridhar Malavali if (!req) 39867190575fSGiridhar Malavali continue; 39877190575fSGiridhar Malavali for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 39887190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 39897190575fSGiridhar Malavali if (sp) { 39907190575fSGiridhar Malavali if (!sp->ctx || 39917190575fSGiridhar Malavali (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 39927190575fSGiridhar Malavali spin_unlock_irqrestore( 39937190575fSGiridhar Malavali &ha->hardware_lock, flags); 39947190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 39957c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 39967c3df132SSaurav Kashyap 0x00b1, 39977c3df132SSaurav Kashyap "mbx abort failed.\n"); 39987190575fSGiridhar Malavali } else { 39997c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 40007c3df132SSaurav Kashyap 0x00b2, 40017c3df132SSaurav Kashyap "mbx abort success.\n"); 40027190575fSGiridhar Malavali } 40037190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 40047190575fSGiridhar Malavali } 40057190575fSGiridhar Malavali } 40067190575fSGiridhar Malavali } 40077190575fSGiridhar Malavali } 40087190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 40097190575fSGiridhar Malavali 40107190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 40117190575fSGiridhar Malavali if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 40127190575fSGiridhar Malavali WAIT_HOST) == QLA_SUCCESS) { 40137c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 40147c3df132SSaurav Kashyap "Done wait for " 40157c3df132SSaurav Kashyap "pending commands.\n"); 40167190575fSGiridhar Malavali } 40177190575fSGiridhar Malavali } 40187190575fSGiridhar Malavali } 4019