1a9083016SGiridhar Malavali /* 2a9083016SGiridhar Malavali * QLogic Fibre Channel HBA Driver 3bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation 4a9083016SGiridhar Malavali * 5a9083016SGiridhar Malavali * See LICENSE.qla2xxx for copyright and licensing details. 6a9083016SGiridhar Malavali */ 7a9083016SGiridhar Malavali #include "qla_def.h" 8a9083016SGiridhar Malavali #include <linux/delay.h> 99dfb59a0SBart Van Assche #include <linux/io-64-nonatomic-lo-hi.h> 10a9083016SGiridhar Malavali #include <linux/pci.h> 1108de2844SGiridhar Malavali #include <linux/ratelimit.h> 1208de2844SGiridhar Malavali #include <linux/vmalloc.h> 13ff2fc42eSAndrew Vasquez #include <scsi/scsi_tcq.h> 14a9083016SGiridhar Malavali 15a9083016SGiridhar Malavali #define MASK(n) ((1ULL<<(n))-1) 16a9083016SGiridhar Malavali #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 17a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 18a9083016SGiridhar Malavali #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 19a9083016SGiridhar Malavali ((addr >> 25) & 0x3ff)) 20a9083016SGiridhar Malavali #define MS_WIN(addr) (addr & 0x0ffc0000) 21a9083016SGiridhar Malavali #define QLA82XX_PCI_MN_2M (0) 22a9083016SGiridhar Malavali #define QLA82XX_PCI_MS_2M (0x80000) 23a9083016SGiridhar Malavali #define QLA82XX_PCI_OCM0_2M (0xc0000) 24a9083016SGiridhar Malavali #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25a9083016SGiridhar Malavali #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 260547fb37SLalit Chandivade #define BLOCK_PROTECT_BITS 0x0F 27a9083016SGiridhar Malavali 28a9083016SGiridhar Malavali /* CRB window related */ 29a9083016SGiridhar Malavali #define CRB_BLK(off) ((off >> 20) & 0x3f) 30a9083016SGiridhar Malavali #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 31a9083016SGiridhar Malavali #define CRB_WINDOW_2M (0x130060) 32a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33a9083016SGiridhar Malavali #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 34a9083016SGiridhar Malavali ((off) & 0xf0000)) 35a9083016SGiridhar Malavali #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 36a9083016SGiridhar Malavali #define CRB_INDIRECT_2M (0x1e0000UL) 37a9083016SGiridhar Malavali 38a9083016SGiridhar Malavali #define MAX_CRB_XFORM 60 39a9083016SGiridhar Malavali static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 40fa492630SSaurav Kashyap static int qla82xx_crb_table_initialized; 41a9083016SGiridhar Malavali 42a9083016SGiridhar Malavali #define qla82xx_crb_addr_transform(name) \ 43a9083016SGiridhar Malavali (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 44a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 45a9083016SGiridhar Malavali 4661778a1cSBart Van Assche const int MD_MIU_TEST_AGT_RDDATA[] = { 4761778a1cSBart Van Assche 0x410000A8, 0x410000AC, 4861778a1cSBart Van Assche 0x410000B8, 0x410000BC 4961778a1cSBart Van Assche }; 5061778a1cSBart Van Assche 51a9083016SGiridhar Malavali static void qla82xx_crb_addr_transform_setup(void) 52a9083016SGiridhar Malavali { 53a9083016SGiridhar Malavali qla82xx_crb_addr_transform(XDMA); 54a9083016SGiridhar Malavali qla82xx_crb_addr_transform(TIMR); 55a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SRE); 56a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN3); 57a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN2); 58a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN1); 59a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQN0); 60a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS3); 61a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS2); 62a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS1); 63a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SQS0); 64a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX7); 65a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX6); 66a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX5); 67a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX4); 68a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX3); 69a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX2); 70a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX1); 71a9083016SGiridhar Malavali qla82xx_crb_addr_transform(RPMX0); 72a9083016SGiridhar Malavali qla82xx_crb_addr_transform(ROMUSB); 73a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SN); 74a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMN); 75a9083016SGiridhar Malavali qla82xx_crb_addr_transform(QMS); 76a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGNI); 77a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGND); 78a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN3); 79a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN2); 80a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN1); 81a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGN0); 82a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSI); 83a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGSD); 84a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS3); 85a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS2); 86a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS1); 87a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PGS0); 88a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PS); 89a9083016SGiridhar Malavali qla82xx_crb_addr_transform(PH); 90a9083016SGiridhar Malavali qla82xx_crb_addr_transform(NIU); 91a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2Q); 92a9083016SGiridhar Malavali qla82xx_crb_addr_transform(EG); 93a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MN); 94a9083016SGiridhar Malavali qla82xx_crb_addr_transform(MS); 95a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS2); 96a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS1); 97a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAS0); 98a9083016SGiridhar Malavali qla82xx_crb_addr_transform(CAM); 99a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C1); 100a9083016SGiridhar Malavali qla82xx_crb_addr_transform(C2C0); 101a9083016SGiridhar Malavali qla82xx_crb_addr_transform(SMB); 102a9083016SGiridhar Malavali qla82xx_crb_addr_transform(OCM0); 103a9083016SGiridhar Malavali /* 104a9083016SGiridhar Malavali * Used only in P3 just define it for P2 also. 105a9083016SGiridhar Malavali */ 106a9083016SGiridhar Malavali qla82xx_crb_addr_transform(I2C0); 107a9083016SGiridhar Malavali 108a9083016SGiridhar Malavali qla82xx_crb_table_initialized = 1; 109a9083016SGiridhar Malavali } 110a9083016SGiridhar Malavali 111fa492630SSaurav Kashyap static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 112a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 113a9083016SGiridhar Malavali {{{1, 0x0100000, 0x0102000, 0x120000}, 114a9083016SGiridhar Malavali {1, 0x0110000, 0x0120000, 0x130000}, 115a9083016SGiridhar Malavali {1, 0x0120000, 0x0122000, 0x124000}, 116a9083016SGiridhar Malavali {1, 0x0130000, 0x0132000, 0x126000}, 117a9083016SGiridhar Malavali {1, 0x0140000, 0x0142000, 0x128000}, 118a9083016SGiridhar Malavali {1, 0x0150000, 0x0152000, 0x12a000}, 119a9083016SGiridhar Malavali {1, 0x0160000, 0x0170000, 0x110000}, 120a9083016SGiridhar Malavali {1, 0x0170000, 0x0172000, 0x12e000}, 121a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 122a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 123a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 124a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 125a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 126a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 127a9083016SGiridhar Malavali {1, 0x01e0000, 0x01e0800, 0x122000}, 128a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } } , 129a9083016SGiridhar Malavali {{{1, 0x0200000, 0x0210000, 0x180000} } }, 130a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 131a9083016SGiridhar Malavali {{{1, 0x0400000, 0x0401000, 0x169000} } }, 132a9083016SGiridhar Malavali {{{1, 0x0500000, 0x0510000, 0x140000} } }, 133a9083016SGiridhar Malavali {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 134a9083016SGiridhar Malavali {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 135a9083016SGiridhar Malavali {{{1, 0x0800000, 0x0802000, 0x170000}, 136a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 137a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 138a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 139a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 140a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 141a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 142a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 143a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 144a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 145a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 146a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 147a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 148a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 149a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 150a9083016SGiridhar Malavali {1, 0x08f0000, 0x08f2000, 0x172000} } }, 151a9083016SGiridhar Malavali {{{1, 0x0900000, 0x0902000, 0x174000}, 152a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 153a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 154a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 155a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 156a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 157a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 158a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 159a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 160a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 161a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 162a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 163a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 164a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 165a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 166a9083016SGiridhar Malavali {1, 0x09f0000, 0x09f2000, 0x176000} } }, 167a9083016SGiridhar Malavali {{{0, 0x0a00000, 0x0a02000, 0x178000}, 168a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 169a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 170a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 171a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 172a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 173a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 174a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 175a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 176a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 177a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 178a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 179a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 180a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 181a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 182a9083016SGiridhar Malavali {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 183a9083016SGiridhar Malavali {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 184a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 185a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 186a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 187a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 188a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 189a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 190a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 191a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 192a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 193a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 194a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 195a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 196a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 197a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 198a9083016SGiridhar Malavali {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 199a9083016SGiridhar Malavali {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 200a9083016SGiridhar Malavali {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 201a9083016SGiridhar Malavali {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 202a9083016SGiridhar Malavali {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 203a9083016SGiridhar Malavali {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 204a9083016SGiridhar Malavali {{{1, 0x1100000, 0x1101000, 0x160000} } }, 205a9083016SGiridhar Malavali {{{1, 0x1200000, 0x1201000, 0x161000} } }, 206a9083016SGiridhar Malavali {{{1, 0x1300000, 0x1301000, 0x162000} } }, 207a9083016SGiridhar Malavali {{{1, 0x1400000, 0x1401000, 0x163000} } }, 208a9083016SGiridhar Malavali {{{1, 0x1500000, 0x1501000, 0x165000} } }, 209a9083016SGiridhar Malavali {{{1, 0x1600000, 0x1601000, 0x166000} } }, 210a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 211a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 212a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 213a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 214a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 215a9083016SGiridhar Malavali {{{0, 0, 0, 0} } }, 216a9083016SGiridhar Malavali {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 217a9083016SGiridhar Malavali {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 218a9083016SGiridhar Malavali {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 219a9083016SGiridhar Malavali {{{0} } }, 220a9083016SGiridhar Malavali {{{1, 0x2100000, 0x2102000, 0x120000}, 221a9083016SGiridhar Malavali {1, 0x2110000, 0x2120000, 0x130000}, 222a9083016SGiridhar Malavali {1, 0x2120000, 0x2122000, 0x124000}, 223a9083016SGiridhar Malavali {1, 0x2130000, 0x2132000, 0x126000}, 224a9083016SGiridhar Malavali {1, 0x2140000, 0x2142000, 0x128000}, 225a9083016SGiridhar Malavali {1, 0x2150000, 0x2152000, 0x12a000}, 226a9083016SGiridhar Malavali {1, 0x2160000, 0x2170000, 0x110000}, 227a9083016SGiridhar Malavali {1, 0x2170000, 0x2172000, 0x12e000}, 228a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 229a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 230a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 231a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 232a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 233a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 234a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000}, 235a9083016SGiridhar Malavali {0, 0x0000000, 0x0000000, 0x000000} } }, 236a9083016SGiridhar Malavali {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 237a9083016SGiridhar Malavali {{{0} } }, 238a9083016SGiridhar Malavali {{{0} } }, 239a9083016SGiridhar Malavali {{{0} } }, 240a9083016SGiridhar Malavali {{{0} } }, 241a9083016SGiridhar Malavali {{{0} } }, 242a9083016SGiridhar Malavali {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 243a9083016SGiridhar Malavali {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 244a9083016SGiridhar Malavali {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 245a9083016SGiridhar Malavali {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 246a9083016SGiridhar Malavali {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 247a9083016SGiridhar Malavali {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 248a9083016SGiridhar Malavali {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 249a9083016SGiridhar Malavali {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 250a9083016SGiridhar Malavali {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 251a9083016SGiridhar Malavali {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 252a9083016SGiridhar Malavali {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 253a9083016SGiridhar Malavali {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 254a9083016SGiridhar Malavali {{{0} } }, 255a9083016SGiridhar Malavali {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 256a9083016SGiridhar Malavali {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 257a9083016SGiridhar Malavali {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 258a9083016SGiridhar Malavali {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 259a9083016SGiridhar Malavali {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 260a9083016SGiridhar Malavali {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 261a9083016SGiridhar Malavali {{{0} } }, 262a9083016SGiridhar Malavali {{{0} } }, 263a9083016SGiridhar Malavali {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 264a9083016SGiridhar Malavali {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 265a9083016SGiridhar Malavali {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 266a9083016SGiridhar Malavali }; 267a9083016SGiridhar Malavali 268a9083016SGiridhar Malavali /* 269a9083016SGiridhar Malavali * top 12 bits of crb internal address (hub, agent) 270a9083016SGiridhar Malavali */ 271fa492630SSaurav Kashyap static unsigned qla82xx_crb_hub_agt[64] = { 272a9083016SGiridhar Malavali 0, 273a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 276a9083016SGiridhar Malavali 0, 277a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 278a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 279a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 280a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 281a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 282a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 283a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 284a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 285a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 286a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 287a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 288a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 289a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 290a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 291a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 292a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 293a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 294a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 295a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 296a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 297a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 298a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 299a9083016SGiridhar Malavali 0, 300a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 301a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 302a9083016SGiridhar Malavali 0, 303a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 304a9083016SGiridhar Malavali 0, 305a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 306a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 307a9083016SGiridhar Malavali 0, 308a9083016SGiridhar Malavali 0, 309a9083016SGiridhar Malavali 0, 310a9083016SGiridhar Malavali 0, 311a9083016SGiridhar Malavali 0, 312a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 313a9083016SGiridhar Malavali 0, 314a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 315a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 316a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 317a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 318a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 319a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 320a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 321a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 322a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 323a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 324a9083016SGiridhar Malavali 0, 325a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 326a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 327a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 328a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 329a9083016SGiridhar Malavali 0, 330a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 331a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 332a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 333a9083016SGiridhar Malavali 0, 334a9083016SGiridhar Malavali QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 335a9083016SGiridhar Malavali 0, 336a9083016SGiridhar Malavali }; 337a9083016SGiridhar Malavali 338f1af6208SGiridhar Malavali /* Device states */ 339fa492630SSaurav Kashyap static char *q_dev_state[] = { 340f1af6208SGiridhar Malavali "Unknown", 341f1af6208SGiridhar Malavali "Cold", 342f1af6208SGiridhar Malavali "Initializing", 343f1af6208SGiridhar Malavali "Ready", 344f1af6208SGiridhar Malavali "Need Reset", 345f1af6208SGiridhar Malavali "Need Quiescent", 346f1af6208SGiridhar Malavali "Failed", 347f1af6208SGiridhar Malavali "Quiescent", 348f1af6208SGiridhar Malavali }; 349f1af6208SGiridhar Malavali 35008de2844SGiridhar Malavali char *qdev_state(uint32_t dev_state) 35108de2844SGiridhar Malavali { 35208de2844SGiridhar Malavali return q_dev_state[dev_state]; 35308de2844SGiridhar Malavali } 35408de2844SGiridhar Malavali 355a9083016SGiridhar Malavali /* 3568dfa4b5aSBart Van Assche * In: 'off_in' is offset from CRB space in 128M pci map 3578dfa4b5aSBart Van Assche * Out: 'off_out' is 2M pci map addr 358a9083016SGiridhar Malavali * side effect: lock crb window 359a9083016SGiridhar Malavali */ 360a9083016SGiridhar Malavali static void 3618dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in, 3628dfa4b5aSBart Van Assche void __iomem **off_out) 363a9083016SGiridhar Malavali { 364a9083016SGiridhar Malavali u32 win_read; 3657c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 366a9083016SGiridhar Malavali 3678dfa4b5aSBart Van Assche ha->crb_win = CRB_HI(off_in); 3688dfa4b5aSBart Van Assche writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); 369a9083016SGiridhar Malavali 370a9083016SGiridhar Malavali /* Read back value to make sure write has gone through before trying 371a9083016SGiridhar Malavali * to use it. 372a9083016SGiridhar Malavali */ 37304474d3aSBart Van Assche win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 374a9083016SGiridhar Malavali if (win_read != ha->crb_win) { 3757c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb000, 3767c3df132SSaurav Kashyap "%s: Written crbwin (0x%x) " 3777c3df132SSaurav Kashyap "!= Read crbwin (0x%x), off=0x%lx.\n", 3788dfa4b5aSBart Van Assche __func__, ha->crb_win, win_read, off_in); 379a9083016SGiridhar Malavali } 3808dfa4b5aSBart Van Assche *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 381a9083016SGiridhar Malavali } 382a9083016SGiridhar Malavali 38377e334d2SGiridhar Malavali static int 3848dfa4b5aSBart Van Assche qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in, 3858dfa4b5aSBart Van Assche void __iomem **off_out) 38677e334d2SGiridhar Malavali { 38777e334d2SGiridhar Malavali struct crb_128M_2M_sub_block_map *m; 38877e334d2SGiridhar Malavali 3898dfa4b5aSBart Van Assche if (off_in >= QLA82XX_CRB_MAX) 39077e334d2SGiridhar Malavali return -1; 39177e334d2SGiridhar Malavali 3928dfa4b5aSBart Van Assche if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) { 3938dfa4b5aSBart Van Assche *off_out = (off_in - QLA82XX_PCI_CAMQM) + 39477e334d2SGiridhar Malavali QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 39577e334d2SGiridhar Malavali return 0; 39677e334d2SGiridhar Malavali } 39777e334d2SGiridhar Malavali 3988dfa4b5aSBart Van Assche if (off_in < QLA82XX_PCI_CRBSPACE) 39977e334d2SGiridhar Malavali return -1; 40077e334d2SGiridhar Malavali 4010874f8ecSBart Van Assche off_in -= QLA82XX_PCI_CRBSPACE; 40277e334d2SGiridhar Malavali 40377e334d2SGiridhar Malavali /* Try direct map */ 4048dfa4b5aSBart Van Assche m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)]; 40577e334d2SGiridhar Malavali 4068dfa4b5aSBart Van Assche if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) { 4078dfa4b5aSBart Van Assche *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase; 40877e334d2SGiridhar Malavali return 0; 40977e334d2SGiridhar Malavali } 41077e334d2SGiridhar Malavali /* Not in direct map, use crb window */ 4110874f8ecSBart Van Assche *off_out = (void __iomem *)off_in; 41277e334d2SGiridhar Malavali return 1; 41377e334d2SGiridhar Malavali } 41477e334d2SGiridhar Malavali 41577e334d2SGiridhar Malavali #define CRB_WIN_LOCK_TIMEOUT 100000000 41677e334d2SGiridhar Malavali static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 41777e334d2SGiridhar Malavali { 41877e334d2SGiridhar Malavali int done = 0, timeout = 0; 41977e334d2SGiridhar Malavali 42077e334d2SGiridhar Malavali while (!done) { 42177e334d2SGiridhar Malavali /* acquire semaphore3 from PCI HW block */ 42277e334d2SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 42377e334d2SGiridhar Malavali if (done == 1) 42477e334d2SGiridhar Malavali break; 42577e334d2SGiridhar Malavali if (timeout >= CRB_WIN_LOCK_TIMEOUT) 42677e334d2SGiridhar Malavali return -1; 42777e334d2SGiridhar Malavali timeout++; 42877e334d2SGiridhar Malavali } 42977e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 43077e334d2SGiridhar Malavali return 0; 43177e334d2SGiridhar Malavali } 43277e334d2SGiridhar Malavali 433a9083016SGiridhar Malavali int 4348dfa4b5aSBart Van Assche qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data) 435a9083016SGiridhar Malavali { 4368dfa4b5aSBart Van Assche void __iomem *off; 437a9083016SGiridhar Malavali unsigned long flags = 0; 438a9083016SGiridhar Malavali int rv; 439a9083016SGiridhar Malavali 4408dfa4b5aSBart Van Assche rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 441a9083016SGiridhar Malavali 442a9083016SGiridhar Malavali BUG_ON(rv == -1); 443a9083016SGiridhar Malavali 444a9083016SGiridhar Malavali if (rv == 1) { 4458d16366bSBart Van Assche #ifndef __CHECKER__ 446a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 4478d16366bSBart Van Assche #endif 448a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 4498dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 450a9083016SGiridhar Malavali } 451a9083016SGiridhar Malavali 452a9083016SGiridhar Malavali writel(data, (void __iomem *)off); 453a9083016SGiridhar Malavali 454a9083016SGiridhar Malavali if (rv == 1) { 455a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 4568d16366bSBart Van Assche #ifndef __CHECKER__ 457a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 4588d16366bSBart Van Assche #endif 459a9083016SGiridhar Malavali } 460a9083016SGiridhar Malavali return 0; 461a9083016SGiridhar Malavali } 462a9083016SGiridhar Malavali 463a9083016SGiridhar Malavali int 4648dfa4b5aSBart Van Assche qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in) 465a9083016SGiridhar Malavali { 4668dfa4b5aSBart Van Assche void __iomem *off; 467a9083016SGiridhar Malavali unsigned long flags = 0; 468a9083016SGiridhar Malavali int rv; 469a9083016SGiridhar Malavali u32 data; 470a9083016SGiridhar Malavali 4718dfa4b5aSBart Van Assche rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off); 472a9083016SGiridhar Malavali 473a9083016SGiridhar Malavali BUG_ON(rv == -1); 474a9083016SGiridhar Malavali 475a9083016SGiridhar Malavali if (rv == 1) { 4768d16366bSBart Van Assche #ifndef __CHECKER__ 477a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 4788d16366bSBart Van Assche #endif 479a9083016SGiridhar Malavali qla82xx_crb_win_lock(ha); 4808dfa4b5aSBart Van Assche qla82xx_pci_set_crbwindow_2M(ha, off_in, &off); 481a9083016SGiridhar Malavali } 48204474d3aSBart Van Assche data = rd_reg_dword(off); 483a9083016SGiridhar Malavali 484a9083016SGiridhar Malavali if (rv == 1) { 485a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 4868d16366bSBart Van Assche #ifndef __CHECKER__ 487a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 4888d16366bSBart Van Assche #endif 489a9083016SGiridhar Malavali } 490a9083016SGiridhar Malavali return data; 491a9083016SGiridhar Malavali } 492a9083016SGiridhar Malavali 493a9083016SGiridhar Malavali #define IDC_LOCK_TIMEOUT 100000000 494a9083016SGiridhar Malavali int qla82xx_idc_lock(struct qla_hw_data *ha) 495a9083016SGiridhar Malavali { 496a9083016SGiridhar Malavali int i; 497a9083016SGiridhar Malavali int done = 0, timeout = 0; 498a9083016SGiridhar Malavali 499a9083016SGiridhar Malavali while (!done) { 500a9083016SGiridhar Malavali /* acquire semaphore5 from PCI HW block */ 501a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 502a9083016SGiridhar Malavali if (done == 1) 503a9083016SGiridhar Malavali break; 504a9083016SGiridhar Malavali if (timeout >= IDC_LOCK_TIMEOUT) 505a9083016SGiridhar Malavali return -1; 506a9083016SGiridhar Malavali 507a9083016SGiridhar Malavali timeout++; 508a9083016SGiridhar Malavali 509a9083016SGiridhar Malavali /* Yield CPU */ 510a9083016SGiridhar Malavali if (!in_interrupt()) 511a9083016SGiridhar Malavali schedule(); 512a9083016SGiridhar Malavali else { 513a9083016SGiridhar Malavali for (i = 0; i < 20; i++) 514a9083016SGiridhar Malavali cpu_relax(); 515a9083016SGiridhar Malavali } 516a9083016SGiridhar Malavali } 517a9083016SGiridhar Malavali 518a9083016SGiridhar Malavali return 0; 519a9083016SGiridhar Malavali } 520a9083016SGiridhar Malavali 521a9083016SGiridhar Malavali void qla82xx_idc_unlock(struct qla_hw_data *ha) 522a9083016SGiridhar Malavali { 523a9083016SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 524a9083016SGiridhar Malavali } 525a9083016SGiridhar Malavali 526a9083016SGiridhar Malavali /* 527a9083016SGiridhar Malavali * check memory access boundary. 528a9083016SGiridhar Malavali * used by test agent. support ddr access only for now 529a9083016SGiridhar Malavali */ 530a9083016SGiridhar Malavali static unsigned long 531a9083016SGiridhar Malavali qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 532a9083016SGiridhar Malavali unsigned long long addr, int size) 533a9083016SGiridhar Malavali { 534df3f4cd0SBart Van Assche if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 535a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 536df3f4cd0SBart Van Assche !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET, 537a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX) || 538a9083016SGiridhar Malavali ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 539a9083016SGiridhar Malavali return 0; 540a9083016SGiridhar Malavali else 541a9083016SGiridhar Malavali return 1; 542a9083016SGiridhar Malavali } 543a9083016SGiridhar Malavali 544fa492630SSaurav Kashyap static int qla82xx_pci_set_window_warning_count; 545a9083016SGiridhar Malavali 54677e334d2SGiridhar Malavali static unsigned long 547a9083016SGiridhar Malavali qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 548a9083016SGiridhar Malavali { 549a9083016SGiridhar Malavali int window; 550a9083016SGiridhar Malavali u32 win_read; 5517c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 552a9083016SGiridhar Malavali 553df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 554a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) { 555a9083016SGiridhar Malavali /* DDR network side */ 556a9083016SGiridhar Malavali window = MN_WIN(addr); 557a9083016SGiridhar Malavali ha->ddr_mn_window = window; 558a9083016SGiridhar Malavali qla82xx_wr_32(ha, 559a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 560a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 561a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 562a9083016SGiridhar Malavali if ((win_read << 17) != window) { 5637c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb003, 5647c3df132SSaurav Kashyap "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 565a9083016SGiridhar Malavali __func__, window, win_read); 566a9083016SGiridhar Malavali } 567a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 568df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 569a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) { 570a9083016SGiridhar Malavali unsigned int temp1; 571bd432bb5SBart Van Assche 572a9083016SGiridhar Malavali if ((addr & 0x00ff800) == 0xff800) { 5737c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb004, 574a9083016SGiridhar Malavali "%s: QM access not handled.\n", __func__); 575a9083016SGiridhar Malavali addr = -1UL; 576a9083016SGiridhar Malavali } 577a9083016SGiridhar Malavali window = OCM_WIN(addr); 578a9083016SGiridhar Malavali ha->ddr_mn_window = window; 579a9083016SGiridhar Malavali qla82xx_wr_32(ha, 580a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 581a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 582a9083016SGiridhar Malavali ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 583a9083016SGiridhar Malavali temp1 = ((window & 0x1FF) << 7) | 584a9083016SGiridhar Malavali ((window & 0x0FFFE0000) >> 17); 585a9083016SGiridhar Malavali if (win_read != temp1) { 5867c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb005, 5877c3df132SSaurav Kashyap "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 588a9083016SGiridhar Malavali __func__, temp1, win_read); 589a9083016SGiridhar Malavali } 590a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 591a9083016SGiridhar Malavali 592df3f4cd0SBart Van Assche } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, 593a9083016SGiridhar Malavali QLA82XX_P3_ADDR_QDR_NET_MAX)) { 594a9083016SGiridhar Malavali /* QDR network side */ 595a9083016SGiridhar Malavali window = MS_WIN(addr); 596a9083016SGiridhar Malavali ha->qdr_sn_window = window; 597a9083016SGiridhar Malavali qla82xx_wr_32(ha, 598a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 599a9083016SGiridhar Malavali win_read = qla82xx_rd_32(ha, 600a9083016SGiridhar Malavali ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 601a9083016SGiridhar Malavali if (win_read != window) { 6027c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb006, 6037c3df132SSaurav Kashyap "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 604a9083016SGiridhar Malavali __func__, window, win_read); 605a9083016SGiridhar Malavali } 606a9083016SGiridhar Malavali addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 607a9083016SGiridhar Malavali } else { 608a9083016SGiridhar Malavali /* 609a9083016SGiridhar Malavali * peg gdb frequently accesses memory that doesn't exist, 610a9083016SGiridhar Malavali * this limits the chit chat so debugging isn't slowed down. 611a9083016SGiridhar Malavali */ 612a9083016SGiridhar Malavali if ((qla82xx_pci_set_window_warning_count++ < 8) || 613a9083016SGiridhar Malavali (qla82xx_pci_set_window_warning_count%64 == 0)) { 6147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb007, 6157c3df132SSaurav Kashyap "%s: Warning:%s Unknown address range!.\n", 6167c3df132SSaurav Kashyap __func__, QLA2XXX_DRIVER_NAME); 617a9083016SGiridhar Malavali } 618a9083016SGiridhar Malavali addr = -1UL; 619a9083016SGiridhar Malavali } 620a9083016SGiridhar Malavali return addr; 621a9083016SGiridhar Malavali } 622a9083016SGiridhar Malavali 623a9083016SGiridhar Malavali /* check if address is in the same windows as the previous access */ 624a9083016SGiridhar Malavali static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 625a9083016SGiridhar Malavali unsigned long long addr) 626a9083016SGiridhar Malavali { 627a9083016SGiridhar Malavali int window; 628a9083016SGiridhar Malavali unsigned long long qdr_max; 629a9083016SGiridhar Malavali 630a9083016SGiridhar Malavali qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 631a9083016SGiridhar Malavali 632a9083016SGiridhar Malavali /* DDR network side */ 633df3f4cd0SBart Van Assche if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET, 634a9083016SGiridhar Malavali QLA82XX_ADDR_DDR_NET_MAX)) 635a9083016SGiridhar Malavali BUG(); 636df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM0, 637a9083016SGiridhar Malavali QLA82XX_ADDR_OCM0_MAX)) 638a9083016SGiridhar Malavali return 1; 639df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_OCM1, 640a9083016SGiridhar Malavali QLA82XX_ADDR_OCM1_MAX)) 641a9083016SGiridhar Malavali return 1; 642df3f4cd0SBart Van Assche else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 643a9083016SGiridhar Malavali /* QDR network side */ 644a9083016SGiridhar Malavali window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 645a9083016SGiridhar Malavali if (ha->qdr_sn_window == window) 646a9083016SGiridhar Malavali return 1; 647a9083016SGiridhar Malavali } 648a9083016SGiridhar Malavali return 0; 649a9083016SGiridhar Malavali } 650a9083016SGiridhar Malavali 651a9083016SGiridhar Malavali static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 652a9083016SGiridhar Malavali u64 off, void *data, int size) 653a9083016SGiridhar Malavali { 654a9083016SGiridhar Malavali unsigned long flags; 655fa492630SSaurav Kashyap void __iomem *addr = NULL; 656a9083016SGiridhar Malavali int ret = 0; 657a9083016SGiridhar Malavali u64 start; 658fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 659a9083016SGiridhar Malavali unsigned long mem_base; 660a9083016SGiridhar Malavali unsigned long mem_page; 6617c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 662a9083016SGiridhar Malavali 663a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 664a9083016SGiridhar Malavali 665a9083016SGiridhar Malavali /* 666a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 667a9083016SGiridhar Malavali * do not access. 668a9083016SGiridhar Malavali */ 669a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 670a9083016SGiridhar Malavali if ((start == -1UL) || 671a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 672a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 6737c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb008, 6747c3df132SSaurav Kashyap "%s out of bound pci memory " 6757c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 6767c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 677a9083016SGiridhar Malavali return -1; 678a9083016SGiridhar Malavali } 679a9083016SGiridhar Malavali 680a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 681a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 682a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 683a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 684a9083016SGiridhar Malavali * consecutive pages. 685a9083016SGiridhar Malavali */ 686a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 687a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 688a9083016SGiridhar Malavali else 689a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 690fa492630SSaurav Kashyap if (mem_ptr == NULL) { 691a9083016SGiridhar Malavali *(u8 *)data = 0; 692a9083016SGiridhar Malavali return -1; 693a9083016SGiridhar Malavali } 694a9083016SGiridhar Malavali addr = mem_ptr; 695a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 696a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 697a9083016SGiridhar Malavali 698a9083016SGiridhar Malavali switch (size) { 699a9083016SGiridhar Malavali case 1: 700a9083016SGiridhar Malavali *(u8 *)data = readb(addr); 701a9083016SGiridhar Malavali break; 702a9083016SGiridhar Malavali case 2: 703a9083016SGiridhar Malavali *(u16 *)data = readw(addr); 704a9083016SGiridhar Malavali break; 705a9083016SGiridhar Malavali case 4: 706a9083016SGiridhar Malavali *(u32 *)data = readl(addr); 707a9083016SGiridhar Malavali break; 708a9083016SGiridhar Malavali case 8: 709a9083016SGiridhar Malavali *(u64 *)data = readq(addr); 710a9083016SGiridhar Malavali break; 711a9083016SGiridhar Malavali default: 712a9083016SGiridhar Malavali ret = -1; 713a9083016SGiridhar Malavali break; 714a9083016SGiridhar Malavali } 715a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 716a9083016SGiridhar Malavali 717a9083016SGiridhar Malavali if (mem_ptr) 718a9083016SGiridhar Malavali iounmap(mem_ptr); 719a9083016SGiridhar Malavali return ret; 720a9083016SGiridhar Malavali } 721a9083016SGiridhar Malavali 722a9083016SGiridhar Malavali static int 723a9083016SGiridhar Malavali qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 724a9083016SGiridhar Malavali u64 off, void *data, int size) 725a9083016SGiridhar Malavali { 726a9083016SGiridhar Malavali unsigned long flags; 727fa492630SSaurav Kashyap void __iomem *addr = NULL; 728a9083016SGiridhar Malavali int ret = 0; 729a9083016SGiridhar Malavali u64 start; 730fa492630SSaurav Kashyap uint8_t __iomem *mem_ptr = NULL; 731a9083016SGiridhar Malavali unsigned long mem_base; 732a9083016SGiridhar Malavali unsigned long mem_page; 7337c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 734a9083016SGiridhar Malavali 735a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 736a9083016SGiridhar Malavali 737a9083016SGiridhar Malavali /* 738a9083016SGiridhar Malavali * If attempting to access unknown address or straddle hw windows, 739a9083016SGiridhar Malavali * do not access. 740a9083016SGiridhar Malavali */ 741a9083016SGiridhar Malavali start = qla82xx_pci_set_window(ha, off); 742a9083016SGiridhar Malavali if ((start == -1UL) || 743a9083016SGiridhar Malavali (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 744a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 7457c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0xb009, 7460bf0efa1SColin Ian King "%s out of bound memory " 7477c3df132SSaurav Kashyap "access, offset is 0x%llx.\n", 7487c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME, off); 749a9083016SGiridhar Malavali return -1; 750a9083016SGiridhar Malavali } 751a9083016SGiridhar Malavali 752a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 753a9083016SGiridhar Malavali mem_base = pci_resource_start(ha->pdev, 0); 754a9083016SGiridhar Malavali mem_page = start & PAGE_MASK; 755a9083016SGiridhar Malavali /* Map two pages whenever user tries to access addresses in two 756a9083016SGiridhar Malavali * consecutive pages. 757a9083016SGiridhar Malavali */ 758a9083016SGiridhar Malavali if (mem_page != ((start + size - 1) & PAGE_MASK)) 759a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 760a9083016SGiridhar Malavali else 761a9083016SGiridhar Malavali mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 762fa492630SSaurav Kashyap if (mem_ptr == NULL) 763a9083016SGiridhar Malavali return -1; 764a9083016SGiridhar Malavali 765a9083016SGiridhar Malavali addr = mem_ptr; 766a9083016SGiridhar Malavali addr += start & (PAGE_SIZE - 1); 767a9083016SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 768a9083016SGiridhar Malavali 769a9083016SGiridhar Malavali switch (size) { 770a9083016SGiridhar Malavali case 1: 771a9083016SGiridhar Malavali writeb(*(u8 *)data, addr); 772a9083016SGiridhar Malavali break; 773a9083016SGiridhar Malavali case 2: 774a9083016SGiridhar Malavali writew(*(u16 *)data, addr); 775a9083016SGiridhar Malavali break; 776a9083016SGiridhar Malavali case 4: 777a9083016SGiridhar Malavali writel(*(u32 *)data, addr); 778a9083016SGiridhar Malavali break; 779a9083016SGiridhar Malavali case 8: 780a9083016SGiridhar Malavali writeq(*(u64 *)data, addr); 781a9083016SGiridhar Malavali break; 782a9083016SGiridhar Malavali default: 783a9083016SGiridhar Malavali ret = -1; 784a9083016SGiridhar Malavali break; 785a9083016SGiridhar Malavali } 786a9083016SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 787a9083016SGiridhar Malavali if (mem_ptr) 788a9083016SGiridhar Malavali iounmap(mem_ptr); 789a9083016SGiridhar Malavali return ret; 790a9083016SGiridhar Malavali } 791a9083016SGiridhar Malavali 792a9083016SGiridhar Malavali #define MTU_FUDGE_FACTOR 100 79377e334d2SGiridhar Malavali static unsigned long 79477e334d2SGiridhar Malavali qla82xx_decode_crb_addr(unsigned long addr) 795a9083016SGiridhar Malavali { 796a9083016SGiridhar Malavali int i; 797a9083016SGiridhar Malavali unsigned long base_addr, offset, pci_base; 798a9083016SGiridhar Malavali 799a9083016SGiridhar Malavali if (!qla82xx_crb_table_initialized) 800a9083016SGiridhar Malavali qla82xx_crb_addr_transform_setup(); 801a9083016SGiridhar Malavali 802a9083016SGiridhar Malavali pci_base = ADDR_ERROR; 803a9083016SGiridhar Malavali base_addr = addr & 0xfff00000; 804a9083016SGiridhar Malavali offset = addr & 0x000fffff; 805a9083016SGiridhar Malavali 806a9083016SGiridhar Malavali for (i = 0; i < MAX_CRB_XFORM; i++) { 807a9083016SGiridhar Malavali if (crb_addr_xform[i] == base_addr) { 808a9083016SGiridhar Malavali pci_base = i << 20; 809a9083016SGiridhar Malavali break; 810a9083016SGiridhar Malavali } 811a9083016SGiridhar Malavali } 812a9083016SGiridhar Malavali if (pci_base == ADDR_ERROR) 813a9083016SGiridhar Malavali return pci_base; 814a9083016SGiridhar Malavali return pci_base + offset; 815a9083016SGiridhar Malavali } 816a9083016SGiridhar Malavali 817a9083016SGiridhar Malavali static long rom_max_timeout = 100; 818a9083016SGiridhar Malavali static long qla82xx_rom_lock_timeout = 100; 819a9083016SGiridhar Malavali 82077e334d2SGiridhar Malavali static int 821a9083016SGiridhar Malavali qla82xx_rom_lock(struct qla_hw_data *ha) 822a9083016SGiridhar Malavali { 823a9083016SGiridhar Malavali int done = 0, timeout = 0; 8246c315553SSaurav Kashyap uint32_t lock_owner = 0; 82527f4b72fSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 826a9083016SGiridhar Malavali 827a9083016SGiridhar Malavali while (!done) { 828a9083016SGiridhar Malavali /* acquire semaphore2 from PCI HW block */ 829a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 830a9083016SGiridhar Malavali if (done == 1) 831a9083016SGiridhar Malavali break; 8326c315553SSaurav Kashyap if (timeout >= qla82xx_rom_lock_timeout) { 8336c315553SSaurav Kashyap lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 8347ab3d962SSawan Chandak ql_dbg(ql_dbg_p3p, vha, 0xb157, 83527f4b72fSAtul Deshmukh "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 83627f4b72fSAtul Deshmukh __func__, ha->portnum, lock_owner); 837a9083016SGiridhar Malavali return -1; 8386c315553SSaurav Kashyap } 839a9083016SGiridhar Malavali timeout++; 840a9083016SGiridhar Malavali } 8414babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); 842a9083016SGiridhar Malavali return 0; 843a9083016SGiridhar Malavali } 844a9083016SGiridhar Malavali 845d652e093SChad Dupuis static void 846d652e093SChad Dupuis qla82xx_rom_unlock(struct qla_hw_data *ha) 847d652e093SChad Dupuis { 8484babb90eSHiral Patel qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); 849d652e093SChad Dupuis qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 850d652e093SChad Dupuis } 851d652e093SChad Dupuis 85277e334d2SGiridhar Malavali static int 853a9083016SGiridhar Malavali qla82xx_wait_rom_busy(struct qla_hw_data *ha) 854a9083016SGiridhar Malavali { 855a9083016SGiridhar Malavali long timeout = 0; 856a9083016SGiridhar Malavali long done = 0 ; 8577c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 858a9083016SGiridhar Malavali 859a9083016SGiridhar Malavali while (done == 0) { 860a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 861a9083016SGiridhar Malavali done &= 4; 862a9083016SGiridhar Malavali timeout++; 863a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8647c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00a, 8657c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom busy.\n", 8667c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 867a9083016SGiridhar Malavali return -1; 868a9083016SGiridhar Malavali } 869a9083016SGiridhar Malavali } 870a9083016SGiridhar Malavali return 0; 871a9083016SGiridhar Malavali } 872a9083016SGiridhar Malavali 87377e334d2SGiridhar Malavali static int 874a9083016SGiridhar Malavali qla82xx_wait_rom_done(struct qla_hw_data *ha) 875a9083016SGiridhar Malavali { 876a9083016SGiridhar Malavali long timeout = 0; 877a9083016SGiridhar Malavali long done = 0 ; 8787c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 879a9083016SGiridhar Malavali 880a9083016SGiridhar Malavali while (done == 0) { 881a9083016SGiridhar Malavali done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 882a9083016SGiridhar Malavali done &= 2; 883a9083016SGiridhar Malavali timeout++; 884a9083016SGiridhar Malavali if (timeout >= rom_max_timeout) { 8857c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb00b, 8867c3df132SSaurav Kashyap "%s: Timeout reached waiting for rom done.\n", 8877c3df132SSaurav Kashyap QLA2XXX_DRIVER_NAME); 888a9083016SGiridhar Malavali return -1; 889a9083016SGiridhar Malavali } 890a9083016SGiridhar Malavali } 891a9083016SGiridhar Malavali return 0; 892a9083016SGiridhar Malavali } 893a9083016SGiridhar Malavali 894fa492630SSaurav Kashyap static int 8952b29d96dSChad Dupuis qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 8962b29d96dSChad Dupuis { 8972b29d96dSChad Dupuis uint32_t off_value, rval = 0; 8982b29d96dSChad Dupuis 89904474d3aSBart Van Assche wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); 9002b29d96dSChad Dupuis 9012b29d96dSChad Dupuis /* Read back value to make sure write has gone through */ 90204474d3aSBart Van Assche rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); 9032b29d96dSChad Dupuis off_value = (off & 0x0000FFFF); 9042b29d96dSChad Dupuis 9052b29d96dSChad Dupuis if (flag) 90604474d3aSBart Van Assche wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase, 9072b29d96dSChad Dupuis data); 9082b29d96dSChad Dupuis else 90904474d3aSBart Van Assche rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + 9108dfa4b5aSBart Van Assche ha->nx_pcibase); 9112b29d96dSChad Dupuis 9122b29d96dSChad Dupuis return rval; 9132b29d96dSChad Dupuis } 9142b29d96dSChad Dupuis 91577e334d2SGiridhar Malavali static int 916a9083016SGiridhar Malavali qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 917a9083016SGiridhar Malavali { 9182b29d96dSChad Dupuis /* Dword reads to flash. */ 9192b29d96dSChad Dupuis qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 9202b29d96dSChad Dupuis *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 9212b29d96dSChad Dupuis (addr & 0x0000FFFF), 0, 0); 9227c3df132SSaurav Kashyap 923a9083016SGiridhar Malavali return 0; 924a9083016SGiridhar Malavali } 925a9083016SGiridhar Malavali 92677e334d2SGiridhar Malavali static int 927a9083016SGiridhar Malavali qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 928a9083016SGiridhar Malavali { 929a9083016SGiridhar Malavali int ret, loops = 0; 9304babb90eSHiral Patel uint32_t lock_owner = 0; 9317c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 932a9083016SGiridhar Malavali 933a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 934a9083016SGiridhar Malavali udelay(100); 935a9083016SGiridhar Malavali schedule(); 936a9083016SGiridhar Malavali loops++; 937a9083016SGiridhar Malavali } 938a9083016SGiridhar Malavali if (loops >= 50000) { 9394babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 9407c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b9, 9414babb90eSHiral Patel "Failed to acquire SEM2 lock, Lock Owner %u.\n", 9424babb90eSHiral Patel lock_owner); 943a9083016SGiridhar Malavali return -1; 944a9083016SGiridhar Malavali } 945a9083016SGiridhar Malavali ret = qla82xx_do_rom_fast_read(ha, addr, valp); 946d652e093SChad Dupuis qla82xx_rom_unlock(ha); 947a9083016SGiridhar Malavali return ret; 948a9083016SGiridhar Malavali } 949a9083016SGiridhar Malavali 95077e334d2SGiridhar Malavali static int 951a9083016SGiridhar Malavali qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 952a9083016SGiridhar Malavali { 9537c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 954bd432bb5SBart Van Assche 955a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 956a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 957a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 9587c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00c, 9597c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 960a9083016SGiridhar Malavali return -1; 961a9083016SGiridhar Malavali } 962a9083016SGiridhar Malavali *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 963a9083016SGiridhar Malavali return 0; 964a9083016SGiridhar Malavali } 965a9083016SGiridhar Malavali 96677e334d2SGiridhar Malavali static int 967a9083016SGiridhar Malavali qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 968a9083016SGiridhar Malavali { 969a9083016SGiridhar Malavali uint32_t val; 9702f91a0a0SBart Van Assche int i, ret; 9717c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 972a9083016SGiridhar Malavali 973a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 9742f91a0a0SBart Van Assche for (i = 0; i < 50000; i++) { 975a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 9762f91a0a0SBart Van Assche if (ret < 0 || (val & 1) == 0) 9772f91a0a0SBart Van Assche return ret; 978a9083016SGiridhar Malavali udelay(10); 979a9083016SGiridhar Malavali cond_resched(); 9802f91a0a0SBart Van Assche } 9817c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00d, 9827c3df132SSaurav Kashyap "Timeout reached waiting for write finish.\n"); 983a9083016SGiridhar Malavali return -1; 984a9083016SGiridhar Malavali } 985a9083016SGiridhar Malavali 98677e334d2SGiridhar Malavali static int 987a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 988a9083016SGiridhar Malavali { 989a9083016SGiridhar Malavali uint32_t val; 990bd432bb5SBart Van Assche 991a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 992a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 993a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 994a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 995a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) 996a9083016SGiridhar Malavali return -1; 997a9083016SGiridhar Malavali if (qla82xx_read_status_reg(ha, &val) != 0) 998a9083016SGiridhar Malavali return -1; 999a9083016SGiridhar Malavali if ((val & 2) != 2) 1000a9083016SGiridhar Malavali return -1; 1001a9083016SGiridhar Malavali return 0; 1002a9083016SGiridhar Malavali } 1003a9083016SGiridhar Malavali 100477e334d2SGiridhar Malavali static int 1005a9083016SGiridhar Malavali qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1006a9083016SGiridhar Malavali { 10077c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1008bd432bb5SBart Van Assche 1009a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1010a9083016SGiridhar Malavali return -1; 1011a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1012a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1013a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00e, 10157c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1016a9083016SGiridhar Malavali return -1; 1017a9083016SGiridhar Malavali } 1018a9083016SGiridhar Malavali return qla82xx_flash_wait_write_finish(ha); 1019a9083016SGiridhar Malavali } 1020a9083016SGiridhar Malavali 102177e334d2SGiridhar Malavali static int 1022a9083016SGiridhar Malavali qla82xx_write_disable_flash(struct qla_hw_data *ha) 1023a9083016SGiridhar Malavali { 10247c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1025bd432bb5SBart Van Assche 1026a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1027a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10287c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb00f, 10297c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1030a9083016SGiridhar Malavali return -1; 1031a9083016SGiridhar Malavali } 1032a9083016SGiridhar Malavali return 0; 1033a9083016SGiridhar Malavali } 1034a9083016SGiridhar Malavali 103577e334d2SGiridhar Malavali static int 1036a9083016SGiridhar Malavali ql82xx_rom_lock_d(struct qla_hw_data *ha) 1037a9083016SGiridhar Malavali { 1038a9083016SGiridhar Malavali int loops = 0; 10394babb90eSHiral Patel uint32_t lock_owner = 0; 10407c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 10417c3df132SSaurav Kashyap 1042a9083016SGiridhar Malavali while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1043a9083016SGiridhar Malavali udelay(100); 1044a9083016SGiridhar Malavali cond_resched(); 1045a9083016SGiridhar Malavali loops++; 1046a9083016SGiridhar Malavali } 1047a9083016SGiridhar Malavali if (loops >= 50000) { 10484babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 10497c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb010, 10504babb90eSHiral Patel "ROM lock failed, Lock Owner %u.\n", lock_owner); 1051a9083016SGiridhar Malavali return -1; 1052a9083016SGiridhar Malavali } 1053cd6dbb03SJesper Juhl return 0; 1054a9083016SGiridhar Malavali } 1055a9083016SGiridhar Malavali 105677e334d2SGiridhar Malavali static int 1057a9083016SGiridhar Malavali qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1058a9083016SGiridhar Malavali uint32_t data) 1059a9083016SGiridhar Malavali { 1060a9083016SGiridhar Malavali int ret = 0; 10617c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1062a9083016SGiridhar Malavali 1063a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 1064a9083016SGiridhar Malavali if (ret < 0) { 10657c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb011, 10667c3df132SSaurav Kashyap "ROM lock failed.\n"); 1067a9083016SGiridhar Malavali return ret; 1068a9083016SGiridhar Malavali } 1069a9083016SGiridhar Malavali 1070a9083016SGiridhar Malavali if (qla82xx_flash_set_write_enable(ha)) 1071a9083016SGiridhar Malavali goto done_write; 1072a9083016SGiridhar Malavali 1073a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1074a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1075a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1076a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1077a9083016SGiridhar Malavali qla82xx_wait_rom_busy(ha); 1078a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 10797c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb012, 10807c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 1081a9083016SGiridhar Malavali ret = -1; 1082a9083016SGiridhar Malavali goto done_write; 1083a9083016SGiridhar Malavali } 1084a9083016SGiridhar Malavali 1085a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 1086a9083016SGiridhar Malavali 1087a9083016SGiridhar Malavali done_write: 1088d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1089a9083016SGiridhar Malavali return ret; 1090a9083016SGiridhar Malavali } 1091a9083016SGiridhar Malavali 1092a9083016SGiridhar Malavali /* This routine does CRB initialize sequence 1093a9083016SGiridhar Malavali * to put the ISP into operational state 1094a9083016SGiridhar Malavali */ 109577e334d2SGiridhar Malavali static int 109677e334d2SGiridhar Malavali qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1097a9083016SGiridhar Malavali { 1098a9083016SGiridhar Malavali int addr, val; 1099a9083016SGiridhar Malavali int i ; 1100a9083016SGiridhar Malavali struct crb_addr_pair *buf; 1101a9083016SGiridhar Malavali unsigned long off; 1102a9083016SGiridhar Malavali unsigned offset, n; 1103a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1104a9083016SGiridhar Malavali 1105a9083016SGiridhar Malavali struct crb_addr_pair { 1106a9083016SGiridhar Malavali long addr; 1107a9083016SGiridhar Malavali long data; 1108a9083016SGiridhar Malavali }; 1109a9083016SGiridhar Malavali 1110a720101dSMasanari Iida /* Halt all the individual PEGs and other blocks of the ISP */ 1111a9083016SGiridhar Malavali qla82xx_rom_lock(ha); 1112c9e8fd5cSMadhuranath Iyengar 111302be2215SGiridhar Malavali /* disable all I2Q */ 111402be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 111502be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 111602be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 111702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 111802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 111902be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 112002be2215SGiridhar Malavali 112102be2215SGiridhar Malavali /* disable all niu interrupts */ 1122c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1123c9e8fd5cSMadhuranath Iyengar /* disable xge rx/tx */ 1124c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1125c9e8fd5cSMadhuranath Iyengar /* disable xg1 rx/tx */ 1126c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 112702be2215SGiridhar Malavali /* disable sideband mac */ 112802be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 112902be2215SGiridhar Malavali /* disable ap0 mac */ 113002be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 113102be2215SGiridhar Malavali /* disable ap1 mac */ 113202be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1133c9e8fd5cSMadhuranath Iyengar 1134c9e8fd5cSMadhuranath Iyengar /* halt sre */ 1135c9e8fd5cSMadhuranath Iyengar val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1136c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1137c9e8fd5cSMadhuranath Iyengar 1138c9e8fd5cSMadhuranath Iyengar /* halt epg */ 1139c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1140c9e8fd5cSMadhuranath Iyengar 1141c9e8fd5cSMadhuranath Iyengar /* halt timers */ 1142c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1143c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1144c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1145c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1146c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 114702be2215SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1148c9e8fd5cSMadhuranath Iyengar 1149c9e8fd5cSMadhuranath Iyengar /* halt pegs */ 1150c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1151c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1152c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1153c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1154c9e8fd5cSMadhuranath Iyengar qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 115502be2215SGiridhar Malavali msleep(20); 1156c9e8fd5cSMadhuranath Iyengar 1157c9e8fd5cSMadhuranath Iyengar /* big hammer */ 1158a9083016SGiridhar Malavali if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1159a9083016SGiridhar Malavali /* don't reset CAM block on reset */ 1160a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1161a9083016SGiridhar Malavali else 1162a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1163d652e093SChad Dupuis qla82xx_rom_unlock(ha); 1164a9083016SGiridhar Malavali 1165a9083016SGiridhar Malavali /* Read the signature value from the flash. 1166a9083016SGiridhar Malavali * Offset 0: Contain signature (0xcafecafe) 1167a9083016SGiridhar Malavali * Offset 4: Offset and number of addr/value pairs 1168a9083016SGiridhar Malavali * that present in CRB initialize sequence 1169a9083016SGiridhar Malavali */ 1170a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1171a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 4, &n) != 0) { 11727c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x006e, 11737c3df132SSaurav Kashyap "Error Reading crb_init area: n: %08x.\n", n); 1174a9083016SGiridhar Malavali return -1; 1175a9083016SGiridhar Malavali } 1176a9083016SGiridhar Malavali 1177a9083016SGiridhar Malavali /* Offset in flash = lower 16 bits 117800adc9a0SSaurav Kashyap * Number of entries = upper 16 bits 1179a9083016SGiridhar Malavali */ 1180a9083016SGiridhar Malavali offset = n & 0xffffU; 1181a9083016SGiridhar Malavali n = (n >> 16) & 0xffffU; 1182a9083016SGiridhar Malavali 118300adc9a0SSaurav Kashyap /* number of addr/value pair should not exceed 1024 entries */ 1184a9083016SGiridhar Malavali if (n >= 1024) { 11857c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0071, 11867c3df132SSaurav Kashyap "Card flash not initialized:n=0x%x.\n", n); 1187a9083016SGiridhar Malavali return -1; 1188a9083016SGiridhar Malavali } 1189a9083016SGiridhar Malavali 11907c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x0072, 11917c3df132SSaurav Kashyap "%d CRB init values found in ROM.\n", n); 1192a9083016SGiridhar Malavali 11936da2ec56SKees Cook buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1194a9083016SGiridhar Malavali if (buf == NULL) { 11957c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x010c, 11967c3df132SSaurav Kashyap "Unable to allocate memory.\n"); 11975cfe8d5bSBart Van Assche return -ENOMEM; 1198a9083016SGiridhar Malavali } 1199a9083016SGiridhar Malavali 1200a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1201a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1202a9083016SGiridhar Malavali qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1203a9083016SGiridhar Malavali kfree(buf); 1204a9083016SGiridhar Malavali return -1; 1205a9083016SGiridhar Malavali } 1206a9083016SGiridhar Malavali 1207a9083016SGiridhar Malavali buf[i].addr = addr; 1208a9083016SGiridhar Malavali buf[i].data = val; 1209a9083016SGiridhar Malavali } 1210a9083016SGiridhar Malavali 1211a9083016SGiridhar Malavali for (i = 0; i < n; i++) { 1212a9083016SGiridhar Malavali /* Translate internal CRB initialization 1213a9083016SGiridhar Malavali * address to PCI bus address 1214a9083016SGiridhar Malavali */ 1215a9083016SGiridhar Malavali off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1216a9083016SGiridhar Malavali QLA82XX_PCI_CRBSPACE; 1217a9083016SGiridhar Malavali /* Not all CRB addr/value pair to be written, 1218a9083016SGiridhar Malavali * some of them are skipped 1219a9083016SGiridhar Malavali */ 1220a9083016SGiridhar Malavali 1221a9083016SGiridhar Malavali /* skipping cold reboot MAGIC */ 1222a9083016SGiridhar Malavali if (off == QLA82XX_CAM_RAM(0x1fc)) 1223a9083016SGiridhar Malavali continue; 1224a9083016SGiridhar Malavali 1225a9083016SGiridhar Malavali /* do not reset PCI */ 1226a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xbc)) 1227a9083016SGiridhar Malavali continue; 1228a9083016SGiridhar Malavali 1229a9083016SGiridhar Malavali /* skip core clock, so that firmware can increase the clock */ 1230a9083016SGiridhar Malavali if (off == (ROMUSB_GLB + 0xc8)) 1231a9083016SGiridhar Malavali continue; 1232a9083016SGiridhar Malavali 1233a9083016SGiridhar Malavali /* skip the function enable register */ 1234a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1235a9083016SGiridhar Malavali continue; 1236a9083016SGiridhar Malavali 1237a9083016SGiridhar Malavali if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1238a9083016SGiridhar Malavali continue; 1239a9083016SGiridhar Malavali 1240a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1241a9083016SGiridhar Malavali continue; 1242a9083016SGiridhar Malavali 1243a9083016SGiridhar Malavali if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1244a9083016SGiridhar Malavali continue; 1245a9083016SGiridhar Malavali 1246a9083016SGiridhar Malavali if (off == ADDR_ERROR) { 12477c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x0116, 1248d939be3aSMasanari Iida "Unknown addr: 0x%08lx.\n", buf[i].addr); 1249a9083016SGiridhar Malavali continue; 1250a9083016SGiridhar Malavali } 1251a9083016SGiridhar Malavali 1252a9083016SGiridhar Malavali qla82xx_wr_32(ha, off, buf[i].data); 1253a9083016SGiridhar Malavali 1254a9083016SGiridhar Malavali /* ISP requires much bigger delay to settle down, 1255a9083016SGiridhar Malavali * else crb_window returns 0xffffffff 1256a9083016SGiridhar Malavali */ 1257a9083016SGiridhar Malavali if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1258a9083016SGiridhar Malavali msleep(1000); 1259a9083016SGiridhar Malavali 1260a9083016SGiridhar Malavali /* ISP requires millisec delay between 1261a9083016SGiridhar Malavali * successive CRB register updation 1262a9083016SGiridhar Malavali */ 1263a9083016SGiridhar Malavali msleep(1); 1264a9083016SGiridhar Malavali } 1265a9083016SGiridhar Malavali 1266a9083016SGiridhar Malavali kfree(buf); 1267a9083016SGiridhar Malavali 1268a9083016SGiridhar Malavali /* Resetting the data and instruction cache */ 1269a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1270a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1271a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1272a9083016SGiridhar Malavali 1273a9083016SGiridhar Malavali /* Clear all protocol processing engines */ 1274a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1275a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1276a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1277a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1278a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1279a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1280a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1281a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1282a9083016SGiridhar Malavali return 0; 1283a9083016SGiridhar Malavali } 1284a9083016SGiridhar Malavali 128577e334d2SGiridhar Malavali static int 128677e334d2SGiridhar Malavali qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 128777e334d2SGiridhar Malavali u64 off, void *data, int size) 128877e334d2SGiridhar Malavali { 128977e334d2SGiridhar Malavali int i, j, ret = 0, loop, sz[2], off0; 129077e334d2SGiridhar Malavali int scale, shift_amount, startword; 129177e334d2SGiridhar Malavali uint32_t temp; 129277e334d2SGiridhar Malavali uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 129377e334d2SGiridhar Malavali 129477e334d2SGiridhar Malavali /* 129577e334d2SGiridhar Malavali * If not MN, go check for MS or invalid. 129677e334d2SGiridhar Malavali */ 129777e334d2SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 129877e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 129977e334d2SGiridhar Malavali else { 130077e334d2SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 130177e334d2SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 130277e334d2SGiridhar Malavali return qla82xx_pci_mem_write_direct(ha, 130377e334d2SGiridhar Malavali off, data, size); 130477e334d2SGiridhar Malavali } 130577e334d2SGiridhar Malavali 130677e334d2SGiridhar Malavali off0 = off & 0x7; 130777e334d2SGiridhar Malavali sz[0] = (size < (8 - off0)) ? size : (8 - off0); 130877e334d2SGiridhar Malavali sz[1] = size - sz[0]; 130977e334d2SGiridhar Malavali 131077e334d2SGiridhar Malavali off8 = off & 0xfffffff0; 131177e334d2SGiridhar Malavali loop = (((off & 0xf) + size - 1) >> 4) + 1; 131277e334d2SGiridhar Malavali shift_amount = 4; 131377e334d2SGiridhar Malavali scale = 2; 131477e334d2SGiridhar Malavali startword = (off & 0xf)/8; 131577e334d2SGiridhar Malavali 131677e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 131777e334d2SGiridhar Malavali if (qla82xx_pci_mem_read_2M(ha, off8 + 131877e334d2SGiridhar Malavali (i << shift_amount), &word[i * scale], 8)) 131977e334d2SGiridhar Malavali return -1; 132077e334d2SGiridhar Malavali } 132177e334d2SGiridhar Malavali 132277e334d2SGiridhar Malavali switch (size) { 132377e334d2SGiridhar Malavali case 1: 132477e334d2SGiridhar Malavali tmpw = *((uint8_t *)data); 132577e334d2SGiridhar Malavali break; 132677e334d2SGiridhar Malavali case 2: 132777e334d2SGiridhar Malavali tmpw = *((uint16_t *)data); 132877e334d2SGiridhar Malavali break; 132977e334d2SGiridhar Malavali case 4: 133077e334d2SGiridhar Malavali tmpw = *((uint32_t *)data); 133177e334d2SGiridhar Malavali break; 133277e334d2SGiridhar Malavali case 8: 133377e334d2SGiridhar Malavali default: 133477e334d2SGiridhar Malavali tmpw = *((uint64_t *)data); 133577e334d2SGiridhar Malavali break; 133677e334d2SGiridhar Malavali } 133777e334d2SGiridhar Malavali 133877e334d2SGiridhar Malavali if (sz[0] == 8) { 133977e334d2SGiridhar Malavali word[startword] = tmpw; 134077e334d2SGiridhar Malavali } else { 134177e334d2SGiridhar Malavali word[startword] &= 134277e334d2SGiridhar Malavali ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 134377e334d2SGiridhar Malavali word[startword] |= tmpw << (off0 * 8); 134477e334d2SGiridhar Malavali } 134577e334d2SGiridhar Malavali if (sz[1] != 0) { 134677e334d2SGiridhar Malavali word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 134777e334d2SGiridhar Malavali word[startword+1] |= tmpw >> (sz[0] * 8); 134877e334d2SGiridhar Malavali } 134977e334d2SGiridhar Malavali 135077e334d2SGiridhar Malavali for (i = 0; i < loop; i++) { 135177e334d2SGiridhar Malavali temp = off8 + (i << shift_amount); 135277e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 135377e334d2SGiridhar Malavali temp = 0; 135477e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 135577e334d2SGiridhar Malavali temp = word[i * scale] & 0xffffffff; 135677e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 135777e334d2SGiridhar Malavali temp = (word[i * scale] >> 32) & 0xffffffff; 135877e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 135977e334d2SGiridhar Malavali temp = word[i*scale + 1] & 0xffffffff; 136077e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 136177e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 136277e334d2SGiridhar Malavali temp = (word[i*scale + 1] >> 32) & 0xffffffff; 136377e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + 136477e334d2SGiridhar Malavali MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 136577e334d2SGiridhar Malavali 136677e334d2SGiridhar Malavali temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 136777e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 136877e334d2SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 136977e334d2SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 137077e334d2SGiridhar Malavali 137177e334d2SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 137277e334d2SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 137377e334d2SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 137477e334d2SGiridhar Malavali break; 137577e334d2SGiridhar Malavali } 137677e334d2SGiridhar Malavali 137777e334d2SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 137877e334d2SGiridhar Malavali if (printk_ratelimit()) 137977e334d2SGiridhar Malavali dev_err(&ha->pdev->dev, 13807c3df132SSaurav Kashyap "failed to write through agent.\n"); 138177e334d2SGiridhar Malavali ret = -1; 138277e334d2SGiridhar Malavali break; 138377e334d2SGiridhar Malavali } 138477e334d2SGiridhar Malavali } 138577e334d2SGiridhar Malavali 138677e334d2SGiridhar Malavali return ret; 138777e334d2SGiridhar Malavali } 138877e334d2SGiridhar Malavali 138977e334d2SGiridhar Malavali static int 1390a9083016SGiridhar Malavali qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1391a9083016SGiridhar Malavali { 1392a9083016SGiridhar Malavali int i; 1393a9083016SGiridhar Malavali long size = 0; 13949c2b2975SHarish Zunjarrao long flashaddr = ha->flt_region_bootload << 2; 13959c2b2975SHarish Zunjarrao long memaddr = BOOTLD_START; 1396a9083016SGiridhar Malavali u64 data; 1397a9083016SGiridhar Malavali u32 high, low; 1398bd432bb5SBart Van Assche 1399a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1400a9083016SGiridhar Malavali 1401a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1402a9083016SGiridhar Malavali if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1403a9083016SGiridhar Malavali (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1404a9083016SGiridhar Malavali return -1; 1405a9083016SGiridhar Malavali } 1406a9083016SGiridhar Malavali data = ((u64)high << 32) | low ; 1407a9083016SGiridhar Malavali qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1408a9083016SGiridhar Malavali flashaddr += 8; 1409a9083016SGiridhar Malavali memaddr += 8; 1410a9083016SGiridhar Malavali 1411a9083016SGiridhar Malavali if (i % 0x1000 == 0) 1412a9083016SGiridhar Malavali msleep(1); 1413a9083016SGiridhar Malavali } 1414a9083016SGiridhar Malavali udelay(100); 1415a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1416a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1417a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1418a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1419a9083016SGiridhar Malavali return 0; 1420a9083016SGiridhar Malavali } 1421a9083016SGiridhar Malavali 1422a9083016SGiridhar Malavali int 1423a9083016SGiridhar Malavali qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1424a9083016SGiridhar Malavali u64 off, void *data, int size) 1425a9083016SGiridhar Malavali { 1426a9083016SGiridhar Malavali int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1427a9083016SGiridhar Malavali int shift_amount; 1428a9083016SGiridhar Malavali uint32_t temp; 1429a9083016SGiridhar Malavali uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1430a9083016SGiridhar Malavali 1431a9083016SGiridhar Malavali /* 1432a9083016SGiridhar Malavali * If not MN, go check for MS or invalid. 1433a9083016SGiridhar Malavali */ 1434a9083016SGiridhar Malavali 1435a9083016SGiridhar Malavali if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1436a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_QDR_NET; 1437a9083016SGiridhar Malavali else { 1438a9083016SGiridhar Malavali mem_crb = QLA82XX_CRB_DDR_NET; 1439a9083016SGiridhar Malavali if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1440a9083016SGiridhar Malavali return qla82xx_pci_mem_read_direct(ha, 1441a9083016SGiridhar Malavali off, data, size); 1442a9083016SGiridhar Malavali } 1443a9083016SGiridhar Malavali 1444a9083016SGiridhar Malavali off8 = off & 0xfffffff0; 1445a9083016SGiridhar Malavali off0[0] = off & 0xf; 1446a9083016SGiridhar Malavali sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1447a9083016SGiridhar Malavali shift_amount = 4; 1448a9083016SGiridhar Malavali loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1449a9083016SGiridhar Malavali off0[1] = 0; 1450a9083016SGiridhar Malavali sz[1] = size - sz[0]; 1451a9083016SGiridhar Malavali 1452a9083016SGiridhar Malavali for (i = 0; i < loop; i++) { 1453a9083016SGiridhar Malavali temp = off8 + (i << shift_amount); 1454a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1455a9083016SGiridhar Malavali temp = 0; 1456a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1457a9083016SGiridhar Malavali temp = MIU_TA_CTL_ENABLE; 1458a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1459a9083016SGiridhar Malavali temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1460a9083016SGiridhar Malavali qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1461a9083016SGiridhar Malavali 1462a9083016SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 1463a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1464a9083016SGiridhar Malavali if ((temp & MIU_TA_CTL_BUSY) == 0) 1465a9083016SGiridhar Malavali break; 1466a9083016SGiridhar Malavali } 1467a9083016SGiridhar Malavali 1468a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 1469a9083016SGiridhar Malavali if (printk_ratelimit()) 1470a9083016SGiridhar Malavali dev_err(&ha->pdev->dev, 14717c3df132SSaurav Kashyap "failed to read through agent.\n"); 1472a9083016SGiridhar Malavali break; 1473a9083016SGiridhar Malavali } 1474a9083016SGiridhar Malavali 1475a9083016SGiridhar Malavali start = off0[i] >> 2; 1476a9083016SGiridhar Malavali end = (off0[i] + sz[i] - 1) >> 2; 1477a9083016SGiridhar Malavali for (k = start; k <= end; k++) { 1478a9083016SGiridhar Malavali temp = qla82xx_rd_32(ha, 1479a9083016SGiridhar Malavali mem_crb + MIU_TEST_AGT_RDDATA(k)); 1480a9083016SGiridhar Malavali word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1481a9083016SGiridhar Malavali } 1482a9083016SGiridhar Malavali } 1483a9083016SGiridhar Malavali 1484a9083016SGiridhar Malavali if (j >= MAX_CTL_CHECK) 1485a9083016SGiridhar Malavali return -1; 1486a9083016SGiridhar Malavali 1487a9083016SGiridhar Malavali if ((off0[0] & 7) == 0) { 1488a9083016SGiridhar Malavali val = word[0]; 1489a9083016SGiridhar Malavali } else { 1490a9083016SGiridhar Malavali val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1491a9083016SGiridhar Malavali ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1492a9083016SGiridhar Malavali } 1493a9083016SGiridhar Malavali 1494a9083016SGiridhar Malavali switch (size) { 1495a9083016SGiridhar Malavali case 1: 1496a9083016SGiridhar Malavali *(uint8_t *)data = val; 1497a9083016SGiridhar Malavali break; 1498a9083016SGiridhar Malavali case 2: 1499a9083016SGiridhar Malavali *(uint16_t *)data = val; 1500a9083016SGiridhar Malavali break; 1501a9083016SGiridhar Malavali case 4: 1502a9083016SGiridhar Malavali *(uint32_t *)data = val; 1503a9083016SGiridhar Malavali break; 1504a9083016SGiridhar Malavali case 8: 1505a9083016SGiridhar Malavali *(uint64_t *)data = val; 1506a9083016SGiridhar Malavali break; 1507a9083016SGiridhar Malavali } 1508a9083016SGiridhar Malavali return 0; 1509a9083016SGiridhar Malavali } 1510a9083016SGiridhar Malavali 1511a9083016SGiridhar Malavali 15129c2b2975SHarish Zunjarrao static struct qla82xx_uri_table_desc * 15139c2b2975SHarish Zunjarrao qla82xx_get_table_desc(const u8 *unirom, int section) 15149c2b2975SHarish Zunjarrao { 15159c2b2975SHarish Zunjarrao uint32_t i; 15169c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *directory = 15179c2b2975SHarish Zunjarrao (struct qla82xx_uri_table_desc *)&unirom[0]; 15187ffa5b93SBart Van Assche uint32_t offset; 15197ffa5b93SBart Van Assche uint32_t tab_type; 15207ffa5b93SBart Van Assche uint32_t entries = le32_to_cpu(directory->num_entries); 15219c2b2975SHarish Zunjarrao 15229c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 15237ffa5b93SBart Van Assche offset = le32_to_cpu(directory->findex) + 15247ffa5b93SBart Van Assche (i * le32_to_cpu(directory->entry_size)); 15257ffa5b93SBart Van Assche tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8); 15269c2b2975SHarish Zunjarrao 15279c2b2975SHarish Zunjarrao if (tab_type == section) 15289c2b2975SHarish Zunjarrao return (struct qla82xx_uri_table_desc *)&unirom[offset]; 15299c2b2975SHarish Zunjarrao } 15309c2b2975SHarish Zunjarrao 15319c2b2975SHarish Zunjarrao return NULL; 15329c2b2975SHarish Zunjarrao } 15339c2b2975SHarish Zunjarrao 15349c2b2975SHarish Zunjarrao static struct qla82xx_uri_data_desc * 15359c2b2975SHarish Zunjarrao qla82xx_get_data_desc(struct qla_hw_data *ha, 15369c2b2975SHarish Zunjarrao u32 section, u32 idx_offset) 15379c2b2975SHarish Zunjarrao { 15389c2b2975SHarish Zunjarrao const u8 *unirom = ha->hablob->fw->data; 15397ffa5b93SBart Van Assche int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] + 15407ffa5b93SBart Van Assche idx_offset); 15419c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *tab_desc = NULL; 15427ffa5b93SBart Van Assche uint32_t offset; 15439c2b2975SHarish Zunjarrao 15449c2b2975SHarish Zunjarrao tab_desc = qla82xx_get_table_desc(unirom, section); 15459c2b2975SHarish Zunjarrao if (!tab_desc) 15469c2b2975SHarish Zunjarrao return NULL; 15479c2b2975SHarish Zunjarrao 15487ffa5b93SBart Van Assche offset = le32_to_cpu(tab_desc->findex) + 15497ffa5b93SBart Van Assche (le32_to_cpu(tab_desc->entry_size) * idx); 15509c2b2975SHarish Zunjarrao 15519c2b2975SHarish Zunjarrao return (struct qla82xx_uri_data_desc *)&unirom[offset]; 15529c2b2975SHarish Zunjarrao } 15539c2b2975SHarish Zunjarrao 15549c2b2975SHarish Zunjarrao static u8 * 15559c2b2975SHarish Zunjarrao qla82xx_get_bootld_offset(struct qla_hw_data *ha) 15569c2b2975SHarish Zunjarrao { 15579c2b2975SHarish Zunjarrao u32 offset = BOOTLD_START; 15589c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15599c2b2975SHarish Zunjarrao 15609c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15619c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, 15629c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 15639c2b2975SHarish Zunjarrao if (uri_desc) 15647ffa5b93SBart Van Assche offset = le32_to_cpu(uri_desc->findex); 15659c2b2975SHarish Zunjarrao } 15669c2b2975SHarish Zunjarrao 15679c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15689c2b2975SHarish Zunjarrao } 15699c2b2975SHarish Zunjarrao 15703f5f7335SBart Van Assche static u32 qla82xx_get_fw_size(struct qla_hw_data *ha) 15719c2b2975SHarish Zunjarrao { 15729c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15739c2b2975SHarish Zunjarrao 15749c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15759c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15769c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15779c2b2975SHarish Zunjarrao if (uri_desc) 15787ffa5b93SBart Van Assche return le32_to_cpu(uri_desc->size); 15799c2b2975SHarish Zunjarrao } 15809c2b2975SHarish Zunjarrao 15813f5f7335SBart Van Assche return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]); 15829c2b2975SHarish Zunjarrao } 15839c2b2975SHarish Zunjarrao 15849c2b2975SHarish Zunjarrao static u8 * 15859c2b2975SHarish Zunjarrao qla82xx_get_fw_offs(struct qla_hw_data *ha) 15869c2b2975SHarish Zunjarrao { 15879c2b2975SHarish Zunjarrao u32 offset = IMAGE_START; 15889c2b2975SHarish Zunjarrao struct qla82xx_uri_data_desc *uri_desc = NULL; 15899c2b2975SHarish Zunjarrao 15909c2b2975SHarish Zunjarrao if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 15919c2b2975SHarish Zunjarrao uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 15929c2b2975SHarish Zunjarrao QLA82XX_URI_FIRMWARE_IDX_OFF); 15939c2b2975SHarish Zunjarrao if (uri_desc) 15947ffa5b93SBart Van Assche offset = le32_to_cpu(uri_desc->findex); 15959c2b2975SHarish Zunjarrao } 15969c2b2975SHarish Zunjarrao 15979c2b2975SHarish Zunjarrao return (u8 *)&ha->hablob->fw->data[offset]; 15989c2b2975SHarish Zunjarrao } 15999c2b2975SHarish Zunjarrao 1600a9083016SGiridhar Malavali /* PCI related functions */ 1601a9083016SGiridhar Malavali int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1602a9083016SGiridhar Malavali { 1603a9083016SGiridhar Malavali unsigned long val = 0; 1604a9083016SGiridhar Malavali u32 control; 1605a9083016SGiridhar Malavali 1606a9083016SGiridhar Malavali switch (region) { 1607a9083016SGiridhar Malavali case 0: 1608a9083016SGiridhar Malavali val = 0; 1609a9083016SGiridhar Malavali break; 1610a9083016SGiridhar Malavali case 1: 1611a9083016SGiridhar Malavali pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1612a9083016SGiridhar Malavali val = control + QLA82XX_MSIX_TBL_SPACE; 1613a9083016SGiridhar Malavali break; 1614a9083016SGiridhar Malavali } 1615a9083016SGiridhar Malavali return val; 1616a9083016SGiridhar Malavali } 1617a9083016SGiridhar Malavali 1618a9083016SGiridhar Malavali 1619a9083016SGiridhar Malavali int 1620a9083016SGiridhar Malavali qla82xx_iospace_config(struct qla_hw_data *ha) 1621a9083016SGiridhar Malavali { 1622a9083016SGiridhar Malavali uint32_t len = 0; 1623a9083016SGiridhar Malavali 1624a9083016SGiridhar Malavali if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 16257c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 16267c3df132SSaurav Kashyap "Failed to reserver selected regions.\n"); 1627a9083016SGiridhar Malavali goto iospace_error_exit; 1628a9083016SGiridhar Malavali } 1629a9083016SGiridhar Malavali 1630a9083016SGiridhar Malavali /* Use MMIO operations for all accesses. */ 1631a9083016SGiridhar Malavali if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 16327c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 16337c3df132SSaurav Kashyap "Region #0 not an MMIO resource, aborting.\n"); 1634a9083016SGiridhar Malavali goto iospace_error_exit; 1635a9083016SGiridhar Malavali } 1636a9083016SGiridhar Malavali 1637a9083016SGiridhar Malavali len = pci_resource_len(ha->pdev, 0); 16388dfa4b5aSBart Van Assche ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); 1639a9083016SGiridhar Malavali if (!ha->nx_pcibase) { 16407c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 16417c3df132SSaurav Kashyap "Cannot remap pcibase MMIO, aborting.\n"); 1642a9083016SGiridhar Malavali goto iospace_error_exit; 1643a9083016SGiridhar Malavali } 1644a9083016SGiridhar Malavali 1645a9083016SGiridhar Malavali /* Mapping of IO base pointer */ 16467ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) { 16478dfa4b5aSBart Van Assche ha->iobase = ha->nx_pcibase; 16487ec0effdSAtul Deshmukh } else if (IS_QLA82XX(ha)) { 16498dfa4b5aSBart Van Assche ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); 16507ec0effdSAtul Deshmukh } 1651a9083016SGiridhar Malavali 1652a9083016SGiridhar Malavali if (!ql2xdbwr) { 16538dfa4b5aSBart Van Assche ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) + 1654a9083016SGiridhar Malavali (ha->pdev->devfn << 12)), 4); 1655a9083016SGiridhar Malavali if (!ha->nxdb_wr_ptr) { 16567c3df132SSaurav Kashyap ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 16577c3df132SSaurav Kashyap "Cannot remap MMIO, aborting.\n"); 1658a9083016SGiridhar Malavali goto iospace_error_exit; 1659a9083016SGiridhar Malavali } 1660a9083016SGiridhar Malavali 1661a9083016SGiridhar Malavali /* Mapping of IO base pointer, 1662a9083016SGiridhar Malavali * door bell read and write pointer 1663a9083016SGiridhar Malavali */ 16648dfa4b5aSBart Van Assche ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) + 1665a9083016SGiridhar Malavali (ha->pdev->devfn * 8); 1666a9083016SGiridhar Malavali } else { 16678dfa4b5aSBart Van Assche ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ? 1668a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB1 : 1669a9083016SGiridhar Malavali QLA82XX_CAMRAM_DB2); 1670a9083016SGiridhar Malavali } 1671a9083016SGiridhar Malavali 1672a9083016SGiridhar Malavali ha->max_req_queues = ha->max_rsp_queues = 1; 1673a9083016SGiridhar Malavali ha->msix_count = ha->max_rsp_queues + 1; 16747c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 16757c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 16767c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 16778dfa4b5aSBart Van Assche ha->nx_pcibase, ha->iobase, 16787c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 16797c3df132SSaurav Kashyap ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 16807c3df132SSaurav Kashyap "nx_pci_base=%p iobase=%p " 16817c3df132SSaurav Kashyap "max_req_queues=%d msix_count=%d.\n", 16828dfa4b5aSBart Van Assche ha->nx_pcibase, ha->iobase, 16837c3df132SSaurav Kashyap ha->max_req_queues, ha->msix_count); 1684a9083016SGiridhar Malavali return 0; 1685a9083016SGiridhar Malavali 1686a9083016SGiridhar Malavali iospace_error_exit: 1687a9083016SGiridhar Malavali return -ENOMEM; 1688a9083016SGiridhar Malavali } 1689a9083016SGiridhar Malavali 1690a9083016SGiridhar Malavali /* GS related functions */ 1691a9083016SGiridhar Malavali 1692a9083016SGiridhar Malavali /* Initialization related functions */ 1693a9083016SGiridhar Malavali 1694a9083016SGiridhar Malavali /** 1695a9083016SGiridhar Malavali * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 16962db6228dSBart Van Assche * @vha: HA context 1697a9083016SGiridhar Malavali * 1698a9083016SGiridhar Malavali * Returns 0 on success. 1699a9083016SGiridhar Malavali */ 1700a9083016SGiridhar Malavali int 1701a9083016SGiridhar Malavali qla82xx_pci_config(scsi_qla_host_t *vha) 1702a9083016SGiridhar Malavali { 1703a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1704a9083016SGiridhar Malavali int ret; 1705a9083016SGiridhar Malavali 1706a9083016SGiridhar Malavali pci_set_master(ha->pdev); 1707a9083016SGiridhar Malavali ret = pci_set_mwi(ha->pdev); 1708a9083016SGiridhar Malavali ha->chip_revision = ha->pdev->revision; 17097c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x0043, 171052c82823SBart Van Assche "Chip revision:%d; pci_set_mwi() returned %d.\n", 171152c82823SBart Van Assche ha->chip_revision, ret); 1712a9083016SGiridhar Malavali return 0; 1713a9083016SGiridhar Malavali } 1714a9083016SGiridhar Malavali 1715a9083016SGiridhar Malavali /** 1716a9083016SGiridhar Malavali * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 17172db6228dSBart Van Assche * @vha: HA context 1718a9083016SGiridhar Malavali * 1719a9083016SGiridhar Malavali * Returns 0 on success. 1720a9083016SGiridhar Malavali */ 17213f006ac3SMichael Hernandez int 1722a9083016SGiridhar Malavali qla82xx_reset_chip(scsi_qla_host_t *vha) 1723a9083016SGiridhar Malavali { 1724a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1725bd432bb5SBart Van Assche 1726a9083016SGiridhar Malavali ha->isp_ops->disable_intrs(ha); 17273f006ac3SMichael Hernandez 17283f006ac3SMichael Hernandez return QLA_SUCCESS; 1729a9083016SGiridhar Malavali } 1730a9083016SGiridhar Malavali 1731a9083016SGiridhar Malavali void qla82xx_config_rings(struct scsi_qla_host *vha) 1732a9083016SGiridhar Malavali { 1733a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1734a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1735a9083016SGiridhar Malavali struct init_cb_81xx *icb; 1736a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 1737a9083016SGiridhar Malavali struct rsp_que *rsp = ha->rsp_q_map[0]; 1738a9083016SGiridhar Malavali 1739a9083016SGiridhar Malavali /* Setup ring parameters in initialization control block. */ 1740a9083016SGiridhar Malavali icb = (struct init_cb_81xx *)ha->init_cb; 1741ad950360SBart Van Assche icb->request_q_outpointer = cpu_to_le16(0); 1742ad950360SBart Van Assche icb->response_q_inpointer = cpu_to_le16(0); 1743a9083016SGiridhar Malavali icb->request_q_length = cpu_to_le16(req->length); 1744a9083016SGiridhar Malavali icb->response_q_length = cpu_to_le16(rsp->length); 1745d4556a49SBart Van Assche put_unaligned_le64(req->dma, &icb->request_q_address); 1746d4556a49SBart Van Assche put_unaligned_le64(rsp->dma, &icb->response_q_address); 1747a9083016SGiridhar Malavali 174804474d3aSBart Van Assche wrt_reg_dword(®->req_q_out[0], 0); 174904474d3aSBart Van Assche wrt_reg_dword(®->rsp_q_in[0], 0); 175004474d3aSBart Van Assche wrt_reg_dword(®->rsp_q_out[0], 0); 1751a9083016SGiridhar Malavali } 1752a9083016SGiridhar Malavali 175377e334d2SGiridhar Malavali static int 175477e334d2SGiridhar Malavali qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1755a9083016SGiridhar Malavali { 1756a9083016SGiridhar Malavali u64 *ptr64; 1757a9083016SGiridhar Malavali u32 i, flashaddr, size; 1758a9083016SGiridhar Malavali __le64 data; 1759a9083016SGiridhar Malavali 1760a9083016SGiridhar Malavali size = (IMAGE_START - BOOTLD_START) / 8; 1761a9083016SGiridhar Malavali 17629c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1763a9083016SGiridhar Malavali flashaddr = BOOTLD_START; 1764a9083016SGiridhar Malavali 1765a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1766a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 17679c2b2975SHarish Zunjarrao if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 17689c2b2975SHarish Zunjarrao return -EIO; 1769a9083016SGiridhar Malavali flashaddr += 8; 1770a9083016SGiridhar Malavali } 1771a9083016SGiridhar Malavali 1772a9083016SGiridhar Malavali flashaddr = FLASH_ADDR_START; 17733f5f7335SBart Van Assche size = qla82xx_get_fw_size(ha) / 8; 17749c2b2975SHarish Zunjarrao ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1775a9083016SGiridhar Malavali 1776a9083016SGiridhar Malavali for (i = 0; i < size; i++) { 1777a9083016SGiridhar Malavali data = cpu_to_le64(ptr64[i]); 1778a9083016SGiridhar Malavali 1779a9083016SGiridhar Malavali if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1780a9083016SGiridhar Malavali return -EIO; 1781a9083016SGiridhar Malavali flashaddr += 8; 1782a9083016SGiridhar Malavali } 17839c2b2975SHarish Zunjarrao udelay(100); 1784a9083016SGiridhar Malavali 1785a9083016SGiridhar Malavali /* Write a magic value to CAMRAM register 1786a9083016SGiridhar Malavali * at a specified offset to indicate 1787a9083016SGiridhar Malavali * that all data is written and 1788a9083016SGiridhar Malavali * ready for firmware to initialize. 1789a9083016SGiridhar Malavali */ 17909c2b2975SHarish Zunjarrao qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1791a9083016SGiridhar Malavali 17929c2b2975SHarish Zunjarrao read_lock(&ha->hw_lock); 1793a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1794a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 17959c2b2975SHarish Zunjarrao read_unlock(&ha->hw_lock); 17969c2b2975SHarish Zunjarrao return 0; 17979c2b2975SHarish Zunjarrao } 17989c2b2975SHarish Zunjarrao 17999c2b2975SHarish Zunjarrao static int 18009c2b2975SHarish Zunjarrao qla82xx_set_product_offset(struct qla_hw_data *ha) 18019c2b2975SHarish Zunjarrao { 18029c2b2975SHarish Zunjarrao struct qla82xx_uri_table_desc *ptab_desc = NULL; 18039c2b2975SHarish Zunjarrao const uint8_t *unirom = ha->hablob->fw->data; 18049c2b2975SHarish Zunjarrao uint32_t i; 18057ffa5b93SBart Van Assche uint32_t entries; 18067ffa5b93SBart Van Assche uint32_t flags, file_chiprev, offset; 18079c2b2975SHarish Zunjarrao uint8_t chiprev = ha->chip_revision; 18089c2b2975SHarish Zunjarrao /* Hardcoding mn_present flag for P3P */ 18099c2b2975SHarish Zunjarrao int mn_present = 0; 18109c2b2975SHarish Zunjarrao uint32_t flagbit; 18119c2b2975SHarish Zunjarrao 18129c2b2975SHarish Zunjarrao ptab_desc = qla82xx_get_table_desc(unirom, 18139c2b2975SHarish Zunjarrao QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 18149c2b2975SHarish Zunjarrao if (!ptab_desc) 18159c2b2975SHarish Zunjarrao return -1; 18169c2b2975SHarish Zunjarrao 18177ffa5b93SBart Van Assche entries = le32_to_cpu(ptab_desc->num_entries); 18189c2b2975SHarish Zunjarrao 18199c2b2975SHarish Zunjarrao for (i = 0; i < entries; i++) { 18207ffa5b93SBart Van Assche offset = le32_to_cpu(ptab_desc->findex) + 18217ffa5b93SBart Van Assche (i * le32_to_cpu(ptab_desc->entry_size)); 18227ffa5b93SBart Van Assche flags = le32_to_cpu(*((__le32 *)&unirom[offset] + 18239c2b2975SHarish Zunjarrao QLA82XX_URI_FLAGS_OFF)); 18247ffa5b93SBart Van Assche file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] + 18259c2b2975SHarish Zunjarrao QLA82XX_URI_CHIP_REV_OFF)); 18269c2b2975SHarish Zunjarrao 18279c2b2975SHarish Zunjarrao flagbit = mn_present ? 1 : 2; 18289c2b2975SHarish Zunjarrao 18299c2b2975SHarish Zunjarrao if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 18309c2b2975SHarish Zunjarrao ha->file_prd_off = offset; 18319c2b2975SHarish Zunjarrao return 0; 18329c2b2975SHarish Zunjarrao } 18339c2b2975SHarish Zunjarrao } 18349c2b2975SHarish Zunjarrao return -1; 18359c2b2975SHarish Zunjarrao } 18369c2b2975SHarish Zunjarrao 1837fa492630SSaurav Kashyap static int 18389c2b2975SHarish Zunjarrao qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 18399c2b2975SHarish Zunjarrao { 1840a9c4ae10SBart Van Assche uint32_t val; 18419c2b2975SHarish Zunjarrao uint32_t min_size; 18429c2b2975SHarish Zunjarrao struct qla_hw_data *ha = vha->hw; 18439c2b2975SHarish Zunjarrao const struct firmware *fw = ha->hablob->fw; 18449c2b2975SHarish Zunjarrao 18459c2b2975SHarish Zunjarrao ha->fw_type = fw_type; 18469c2b2975SHarish Zunjarrao 18479c2b2975SHarish Zunjarrao if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 18489c2b2975SHarish Zunjarrao if (qla82xx_set_product_offset(ha)) 18499c2b2975SHarish Zunjarrao return -EINVAL; 18509c2b2975SHarish Zunjarrao 18519c2b2975SHarish Zunjarrao min_size = QLA82XX_URI_FW_MIN_SIZE; 18529c2b2975SHarish Zunjarrao } else { 1853a9c4ae10SBart Van Assche val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1854a9c4ae10SBart Van Assche if (val != QLA82XX_BDINFO_MAGIC) 18559c2b2975SHarish Zunjarrao return -EINVAL; 18569c2b2975SHarish Zunjarrao 18579c2b2975SHarish Zunjarrao min_size = QLA82XX_FW_MIN_SIZE; 18589c2b2975SHarish Zunjarrao } 18599c2b2975SHarish Zunjarrao 18609c2b2975SHarish Zunjarrao if (fw->size < min_size) 18619c2b2975SHarish Zunjarrao return -EINVAL; 1862a9083016SGiridhar Malavali return 0; 1863a9083016SGiridhar Malavali } 1864a9083016SGiridhar Malavali 186577e334d2SGiridhar Malavali static int 186677e334d2SGiridhar Malavali qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1867a9083016SGiridhar Malavali { 1868a9083016SGiridhar Malavali u32 val = 0; 1869a9083016SGiridhar Malavali int retries = 60; 18707c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1871a9083016SGiridhar Malavali 1872a9083016SGiridhar Malavali do { 1873a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1874a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1875a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1876a9083016SGiridhar Malavali 1877a9083016SGiridhar Malavali switch (val) { 1878a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1879a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1880a9083016SGiridhar Malavali return QLA_SUCCESS; 1881a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1882a9083016SGiridhar Malavali break; 1883a9083016SGiridhar Malavali default: 1884a9083016SGiridhar Malavali break; 1885a9083016SGiridhar Malavali } 18867c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a8, 18877c3df132SSaurav Kashyap "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1888a9083016SGiridhar Malavali val, retries); 1889a9083016SGiridhar Malavali 1890a9083016SGiridhar Malavali msleep(500); 1891a9083016SGiridhar Malavali 1892a9083016SGiridhar Malavali } while (--retries); 1893a9083016SGiridhar Malavali 18947c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a9, 1895a9083016SGiridhar Malavali "Cmd Peg initialization failed: 0x%x.\n", val); 1896a9083016SGiridhar Malavali 1897a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1898a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1899a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1900a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1901a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1902a9083016SGiridhar Malavali } 1903a9083016SGiridhar Malavali 190477e334d2SGiridhar Malavali static int 190577e334d2SGiridhar Malavali qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1906a9083016SGiridhar Malavali { 1907a9083016SGiridhar Malavali u32 val = 0; 1908a9083016SGiridhar Malavali int retries = 60; 19097c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1910a9083016SGiridhar Malavali 1911a9083016SGiridhar Malavali do { 1912a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1913a9083016SGiridhar Malavali val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1914a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1915a9083016SGiridhar Malavali 1916a9083016SGiridhar Malavali switch (val) { 1917a9083016SGiridhar Malavali case PHAN_INITIALIZE_COMPLETE: 1918a9083016SGiridhar Malavali case PHAN_INITIALIZE_ACK: 1919a9083016SGiridhar Malavali return QLA_SUCCESS; 1920a9083016SGiridhar Malavali case PHAN_INITIALIZE_FAILED: 1921a9083016SGiridhar Malavali break; 1922a9083016SGiridhar Malavali default: 1923a9083016SGiridhar Malavali break; 1924a9083016SGiridhar Malavali } 19257c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ab, 19267c3df132SSaurav Kashyap "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1927a9083016SGiridhar Malavali val, retries); 1928a9083016SGiridhar Malavali 1929a9083016SGiridhar Malavali msleep(500); 1930a9083016SGiridhar Malavali 1931a9083016SGiridhar Malavali } while (--retries); 1932a9083016SGiridhar Malavali 19337c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ac, 1934401fe8e9SColin Ian King "Rcv Peg initialization failed: 0x%x.\n", val); 1935a9083016SGiridhar Malavali read_lock(&ha->hw_lock); 1936a9083016SGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1937a9083016SGiridhar Malavali read_unlock(&ha->hw_lock); 1938a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 1939a9083016SGiridhar Malavali } 1940a9083016SGiridhar Malavali 1941a9083016SGiridhar Malavali /* ISR related functions */ 1942c1c7178cSBart Van Assche static struct qla82xx_legacy_intr_set legacy_intr[] = 1943a9083016SGiridhar Malavali QLA82XX_LEGACY_INTR_CONFIG; 1944a9083016SGiridhar Malavali 1945a9083016SGiridhar Malavali /* 1946a9083016SGiridhar Malavali * qla82xx_mbx_completion() - Process mailbox command completions. 1947a9083016SGiridhar Malavali * @ha: SCSI driver HA context 1948a9083016SGiridhar Malavali * @mb0: Mailbox0 register 1949a9083016SGiridhar Malavali */ 19507ec0effdSAtul Deshmukh void 1951a9083016SGiridhar Malavali qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1952a9083016SGiridhar Malavali { 1953a9083016SGiridhar Malavali uint16_t cnt; 195437139da1SBart Van Assche __le16 __iomem *wptr; 1955a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 1956a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1957bd432bb5SBart Van Assche 195837139da1SBart Van Assche wptr = ®->mailbox_out[1]; 1959a9083016SGiridhar Malavali 1960a9083016SGiridhar Malavali /* Load return mailbox registers. */ 1961a9083016SGiridhar Malavali ha->flags.mbox_int = 1; 1962a9083016SGiridhar Malavali ha->mailbox_out[0] = mb0; 1963a9083016SGiridhar Malavali 1964a9083016SGiridhar Malavali for (cnt = 1; cnt < ha->mbx_count; cnt++) { 196504474d3aSBart Van Assche ha->mailbox_out[cnt] = rd_reg_word(wptr); 1966a9083016SGiridhar Malavali wptr++; 1967a9083016SGiridhar Malavali } 1968a9083016SGiridhar Malavali 1969cfb0919cSChad Dupuis if (!ha->mcp) 19707c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5053, 19717c3df132SSaurav Kashyap "MBX pointer ERROR.\n"); 1972a9083016SGiridhar Malavali } 1973a9083016SGiridhar Malavali 19742db6228dSBart Van Assche /** 1975a9083016SGiridhar Malavali * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 1976807eb907SBart Van Assche * @irq: interrupt number 1977a9083016SGiridhar Malavali * @dev_id: SCSI driver HA context 1978a9083016SGiridhar Malavali * 1979a9083016SGiridhar Malavali * Called by system whenever the host adapter generates an interrupt. 1980a9083016SGiridhar Malavali * 1981a9083016SGiridhar Malavali * Returns handled flag. 1982a9083016SGiridhar Malavali */ 1983a9083016SGiridhar Malavali irqreturn_t 1984a9083016SGiridhar Malavali qla82xx_intr_handler(int irq, void *dev_id) 1985a9083016SGiridhar Malavali { 1986a9083016SGiridhar Malavali scsi_qla_host_t *vha; 1987a9083016SGiridhar Malavali struct qla_hw_data *ha; 1988a9083016SGiridhar Malavali struct rsp_que *rsp; 1989a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 1990a9083016SGiridhar Malavali int status = 0, status1 = 0; 1991a9083016SGiridhar Malavali unsigned long flags; 1992a9083016SGiridhar Malavali unsigned long iter; 19937c3df132SSaurav Kashyap uint32_t stat = 0; 19940a59cea4SBart Van Assche uint16_t mb[8]; 1995a9083016SGiridhar Malavali 1996a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 1997a9083016SGiridhar Malavali if (!rsp) { 1998b6d0d9d5SGiridhar Malavali ql_log(ql_log_info, NULL, 0xb053, 19993256b435SChad Dupuis "%s: NULL response queue pointer.\n", __func__); 2000a9083016SGiridhar Malavali return IRQ_NONE; 2001a9083016SGiridhar Malavali } 2002a9083016SGiridhar Malavali ha = rsp->hw; 2003a9083016SGiridhar Malavali 2004a9083016SGiridhar Malavali if (!ha->flags.msi_enabled) { 2005a9083016SGiridhar Malavali status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2006a9083016SGiridhar Malavali if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2007a9083016SGiridhar Malavali return IRQ_NONE; 2008a9083016SGiridhar Malavali 2009a9083016SGiridhar Malavali status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2010a9083016SGiridhar Malavali if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2011a9083016SGiridhar Malavali return IRQ_NONE; 2012a9083016SGiridhar Malavali } 2013a9083016SGiridhar Malavali 2014a9083016SGiridhar Malavali /* clear the interrupt */ 2015a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2016a9083016SGiridhar Malavali 2017a9083016SGiridhar Malavali /* read twice to ensure write is flushed */ 2018a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2019a9083016SGiridhar Malavali qla82xx_rd_32(ha, ISR_INT_VECTOR); 2020a9083016SGiridhar Malavali 2021a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2022a9083016SGiridhar Malavali 2023a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2024a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2025a9083016SGiridhar Malavali for (iter = 1; iter--; ) { 2026a9083016SGiridhar Malavali 202704474d3aSBart Van Assche if (rd_reg_dword(®->host_int)) { 202804474d3aSBart Van Assche stat = rd_reg_dword(®->host_status); 2029a9083016SGiridhar Malavali 2030a9083016SGiridhar Malavali switch (stat & 0xff) { 2031a9083016SGiridhar Malavali case 0x1: 2032a9083016SGiridhar Malavali case 0x2: 2033a9083016SGiridhar Malavali case 0x10: 2034a9083016SGiridhar Malavali case 0x11: 2035a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2036a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2037a9083016SGiridhar Malavali break; 2038a9083016SGiridhar Malavali case 0x12: 2039a9083016SGiridhar Malavali mb[0] = MSW(stat); 204004474d3aSBart Van Assche mb[1] = rd_reg_word(®->mailbox_out[1]); 204104474d3aSBart Van Assche mb[2] = rd_reg_word(®->mailbox_out[2]); 204204474d3aSBart Van Assche mb[3] = rd_reg_word(®->mailbox_out[3]); 2043a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2044a9083016SGiridhar Malavali break; 2045a9083016SGiridhar Malavali case 0x13: 2046a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2047a9083016SGiridhar Malavali break; 2048a9083016SGiridhar Malavali default: 20497c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5054, 2050a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 20517c3df132SSaurav Kashyap stat & 0xff); 2052a9083016SGiridhar Malavali break; 2053a9083016SGiridhar Malavali } 2054a9083016SGiridhar Malavali } 205504474d3aSBart Van Assche wrt_reg_dword(®->host_int, 0); 2056a9083016SGiridhar Malavali } 2057a9083016SGiridhar Malavali 205836439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 205936439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 206036439832Sgurinder.shergill@hp.com 206136439832Sgurinder.shergill@hp.com if (!ha->flags.msi_enabled) 206236439832Sgurinder.shergill@hp.com qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 206336439832Sgurinder.shergill@hp.com 2064a9083016SGiridhar Malavali return IRQ_HANDLED; 2065a9083016SGiridhar Malavali } 2066a9083016SGiridhar Malavali 2067a9083016SGiridhar Malavali irqreturn_t 2068a9083016SGiridhar Malavali qla82xx_msix_default(int irq, void *dev_id) 2069a9083016SGiridhar Malavali { 2070a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2071a9083016SGiridhar Malavali struct qla_hw_data *ha; 2072a9083016SGiridhar Malavali struct rsp_que *rsp; 2073a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2074a9083016SGiridhar Malavali int status = 0; 2075a9083016SGiridhar Malavali unsigned long flags; 20767c3df132SSaurav Kashyap uint32_t stat = 0; 2077f3ddac19SChad Dupuis uint32_t host_int = 0; 20780a59cea4SBart Van Assche uint16_t mb[8]; 2079a9083016SGiridhar Malavali 2080a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2081a9083016SGiridhar Malavali if (!rsp) { 2082a9083016SGiridhar Malavali printk(KERN_INFO 20837c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2084a9083016SGiridhar Malavali return IRQ_NONE; 2085a9083016SGiridhar Malavali } 2086a9083016SGiridhar Malavali ha = rsp->hw; 2087a9083016SGiridhar Malavali 2088a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2089a9083016SGiridhar Malavali 2090a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2091a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2092a9083016SGiridhar Malavali do { 209304474d3aSBart Van Assche host_int = rd_reg_dword(®->host_int); 2094c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2095f3ddac19SChad Dupuis break; 2096f3ddac19SChad Dupuis if (host_int) { 209704474d3aSBart Van Assche stat = rd_reg_dword(®->host_status); 2098a9083016SGiridhar Malavali 2099a9083016SGiridhar Malavali switch (stat & 0xff) { 2100a9083016SGiridhar Malavali case 0x1: 2101a9083016SGiridhar Malavali case 0x2: 2102a9083016SGiridhar Malavali case 0x10: 2103a9083016SGiridhar Malavali case 0x11: 2104a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2105a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2106a9083016SGiridhar Malavali break; 2107a9083016SGiridhar Malavali case 0x12: 2108a9083016SGiridhar Malavali mb[0] = MSW(stat); 210904474d3aSBart Van Assche mb[1] = rd_reg_word(®->mailbox_out[1]); 211004474d3aSBart Van Assche mb[2] = rd_reg_word(®->mailbox_out[2]); 211104474d3aSBart Van Assche mb[3] = rd_reg_word(®->mailbox_out[3]); 2112a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2113a9083016SGiridhar Malavali break; 2114a9083016SGiridhar Malavali case 0x13: 2115a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2116a9083016SGiridhar Malavali break; 2117a9083016SGiridhar Malavali default: 21187c3df132SSaurav Kashyap ql_dbg(ql_dbg_async, vha, 0x5041, 2119a9083016SGiridhar Malavali "Unrecognized interrupt type (%d).\n", 21207c3df132SSaurav Kashyap stat & 0xff); 2121a9083016SGiridhar Malavali break; 2122a9083016SGiridhar Malavali } 2123a9083016SGiridhar Malavali } 212404474d3aSBart Van Assche wrt_reg_dword(®->host_int, 0); 2125a9083016SGiridhar Malavali } while (0); 2126a9083016SGiridhar Malavali 212736439832Sgurinder.shergill@hp.com qla2x00_handle_mbx_completion(ha, status); 212836439832Sgurinder.shergill@hp.com spin_unlock_irqrestore(&ha->hardware_lock, flags); 212936439832Sgurinder.shergill@hp.com 2130a9083016SGiridhar Malavali return IRQ_HANDLED; 2131a9083016SGiridhar Malavali } 2132a9083016SGiridhar Malavali 2133a9083016SGiridhar Malavali irqreturn_t 2134a9083016SGiridhar Malavali qla82xx_msix_rsp_q(int irq, void *dev_id) 2135a9083016SGiridhar Malavali { 2136a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2137a9083016SGiridhar Malavali struct qla_hw_data *ha; 2138a9083016SGiridhar Malavali struct rsp_que *rsp; 2139a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 21403553d343SSaurav Kashyap unsigned long flags; 2141f3ddac19SChad Dupuis uint32_t host_int = 0; 2142a9083016SGiridhar Malavali 2143a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2144a9083016SGiridhar Malavali if (!rsp) { 2145a9083016SGiridhar Malavali printk(KERN_INFO 21467c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2147a9083016SGiridhar Malavali return IRQ_NONE; 2148a9083016SGiridhar Malavali } 2149a9083016SGiridhar Malavali 2150a9083016SGiridhar Malavali ha = rsp->hw; 2151a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 21523553d343SSaurav Kashyap spin_lock_irqsave(&ha->hardware_lock, flags); 2153a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 215404474d3aSBart Van Assche host_int = rd_reg_dword(®->host_int); 2155c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2156f3ddac19SChad Dupuis goto out; 2157a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 215804474d3aSBart Van Assche wrt_reg_dword(®->host_int, 0); 2159f3ddac19SChad Dupuis out: 21603553d343SSaurav Kashyap spin_unlock_irqrestore(&ha->hardware_lock, flags); 2161a9083016SGiridhar Malavali return IRQ_HANDLED; 2162a9083016SGiridhar Malavali } 2163a9083016SGiridhar Malavali 2164a9083016SGiridhar Malavali void 2165a9083016SGiridhar Malavali qla82xx_poll(int irq, void *dev_id) 2166a9083016SGiridhar Malavali { 2167a9083016SGiridhar Malavali scsi_qla_host_t *vha; 2168a9083016SGiridhar Malavali struct qla_hw_data *ha; 2169a9083016SGiridhar Malavali struct rsp_que *rsp; 2170a9083016SGiridhar Malavali struct device_reg_82xx __iomem *reg; 2171a9083016SGiridhar Malavali int status = 0; 2172a9083016SGiridhar Malavali uint32_t stat; 2173f3ddac19SChad Dupuis uint32_t host_int = 0; 21740a59cea4SBart Van Assche uint16_t mb[8]; 2175a9083016SGiridhar Malavali unsigned long flags; 2176a9083016SGiridhar Malavali 2177a9083016SGiridhar Malavali rsp = (struct rsp_que *) dev_id; 2178a9083016SGiridhar Malavali if (!rsp) { 2179a9083016SGiridhar Malavali printk(KERN_INFO 21807c3df132SSaurav Kashyap "%s(): NULL response queue pointer.\n", __func__); 2181a9083016SGiridhar Malavali return; 2182a9083016SGiridhar Malavali } 2183a9083016SGiridhar Malavali ha = rsp->hw; 2184a9083016SGiridhar Malavali 2185a9083016SGiridhar Malavali reg = &ha->iobase->isp82; 2186a9083016SGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 2187a9083016SGiridhar Malavali vha = pci_get_drvdata(ha->pdev); 2188a9083016SGiridhar Malavali 218904474d3aSBart Van Assche host_int = rd_reg_dword(®->host_int); 2190c821e0d5SJoe Lawrence if (qla2x00_check_reg32_for_disconnect(vha, host_int)) 2191f3ddac19SChad Dupuis goto out; 2192f3ddac19SChad Dupuis if (host_int) { 219304474d3aSBart Van Assche stat = rd_reg_dword(®->host_status); 2194a9083016SGiridhar Malavali switch (stat & 0xff) { 2195a9083016SGiridhar Malavali case 0x1: 2196a9083016SGiridhar Malavali case 0x2: 2197a9083016SGiridhar Malavali case 0x10: 2198a9083016SGiridhar Malavali case 0x11: 2199a9083016SGiridhar Malavali qla82xx_mbx_completion(vha, MSW(stat)); 2200a9083016SGiridhar Malavali status |= MBX_INTERRUPT; 2201a9083016SGiridhar Malavali break; 2202a9083016SGiridhar Malavali case 0x12: 2203a9083016SGiridhar Malavali mb[0] = MSW(stat); 220404474d3aSBart Van Assche mb[1] = rd_reg_word(®->mailbox_out[1]); 220504474d3aSBart Van Assche mb[2] = rd_reg_word(®->mailbox_out[2]); 220604474d3aSBart Van Assche mb[3] = rd_reg_word(®->mailbox_out[3]); 2207a9083016SGiridhar Malavali qla2x00_async_event(vha, rsp, mb); 2208a9083016SGiridhar Malavali break; 2209a9083016SGiridhar Malavali case 0x13: 2210a9083016SGiridhar Malavali qla24xx_process_response_queue(vha, rsp); 2211a9083016SGiridhar Malavali break; 2212a9083016SGiridhar Malavali default: 22137c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb013, 22147c3df132SSaurav Kashyap "Unrecognized interrupt type (%d).\n", 22157c3df132SSaurav Kashyap stat * 0xff); 2216a9083016SGiridhar Malavali break; 2217a9083016SGiridhar Malavali } 221804474d3aSBart Van Assche wrt_reg_dword(®->host_int, 0); 221902a9ae6eSAtul Deshmukh } 2220f3ddac19SChad Dupuis out: 2221a9083016SGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 2222a9083016SGiridhar Malavali } 2223a9083016SGiridhar Malavali 2224a9083016SGiridhar Malavali void 2225a9083016SGiridhar Malavali qla82xx_enable_intrs(struct qla_hw_data *ha) 2226a9083016SGiridhar Malavali { 2227a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2228bd432bb5SBart Van Assche 2229a9083016SGiridhar Malavali qla82xx_mbx_intr_enable(vha); 2230a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22317ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22327ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); 22337ec0effdSAtul Deshmukh else 2234a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2235a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2236a9083016SGiridhar Malavali ha->interrupts_on = 1; 2237a9083016SGiridhar Malavali } 2238a9083016SGiridhar Malavali 2239a9083016SGiridhar Malavali void 2240a9083016SGiridhar Malavali qla82xx_disable_intrs(struct qla_hw_data *ha) 2241a9083016SGiridhar Malavali { 2242a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2243bd432bb5SBart Van Assche 224432a13df2SHimanshu Madhani if (ha->interrupts_on) 2245a9083016SGiridhar Malavali qla82xx_mbx_intr_disable(vha); 2246cb92cb16SQuinn Tran 2247a9083016SGiridhar Malavali spin_lock_irq(&ha->hardware_lock); 22487ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 22497ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); 22507ec0effdSAtul Deshmukh else 2251a9083016SGiridhar Malavali qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2252a9083016SGiridhar Malavali spin_unlock_irq(&ha->hardware_lock); 2253a9083016SGiridhar Malavali ha->interrupts_on = 0; 2254a9083016SGiridhar Malavali } 2255a9083016SGiridhar Malavali 2256a9083016SGiridhar Malavali void qla82xx_init_flags(struct qla_hw_data *ha) 2257a9083016SGiridhar Malavali { 2258a9083016SGiridhar Malavali struct qla82xx_legacy_intr_set *nx_legacy_intr; 2259a9083016SGiridhar Malavali 2260a9083016SGiridhar Malavali /* ISP 8021 initializations */ 2261a9083016SGiridhar Malavali rwlock_init(&ha->hw_lock); 2262a9083016SGiridhar Malavali ha->qdr_sn_window = -1; 2263a9083016SGiridhar Malavali ha->ddr_mn_window = -1; 2264a9083016SGiridhar Malavali ha->curr_window = 255; 2265a9083016SGiridhar Malavali ha->portnum = PCI_FUNC(ha->pdev->devfn); 2266a9083016SGiridhar Malavali nx_legacy_intr = &legacy_intr[ha->portnum]; 2267a9083016SGiridhar Malavali ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2268a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2269a9083016SGiridhar Malavali ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2270a9083016SGiridhar Malavali ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2271a9083016SGiridhar Malavali } 2272a9083016SGiridhar Malavali 22732374dd23SBart Van Assche static inline void 22740251ce8cSSaurav Kashyap qla82xx_set_idc_version(scsi_qla_host_t *vha) 22750251ce8cSSaurav Kashyap { 22760251ce8cSSaurav Kashyap int idc_ver; 22770251ce8cSSaurav Kashyap uint32_t drv_active; 22780251ce8cSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 22790251ce8cSSaurav Kashyap 22800251ce8cSSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 22810251ce8cSSaurav Kashyap if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { 22820251ce8cSSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 22830251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION); 22840251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb082, 22850251ce8cSSaurav Kashyap "IDC version updated to %d\n", QLA82XX_IDC_VERSION); 22860251ce8cSSaurav Kashyap } else { 22870251ce8cSSaurav Kashyap idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); 22880251ce8cSSaurav Kashyap if (idc_ver != QLA82XX_IDC_VERSION) 22890251ce8cSSaurav Kashyap ql_log(ql_log_info, vha, 0xb083, 22900251ce8cSSaurav Kashyap "qla2xxx driver IDC version %d is not compatible " 22910251ce8cSSaurav Kashyap "with IDC version %d of the other drivers\n", 22920251ce8cSSaurav Kashyap QLA82XX_IDC_VERSION, idc_ver); 22930251ce8cSSaurav Kashyap } 22940251ce8cSSaurav Kashyap } 22950251ce8cSSaurav Kashyap 22960251ce8cSSaurav Kashyap inline void 2297a9083016SGiridhar Malavali qla82xx_set_drv_active(scsi_qla_host_t *vha) 2298a9083016SGiridhar Malavali { 2299a9083016SGiridhar Malavali uint32_t drv_active; 2300a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2301a9083016SGiridhar Malavali 2302a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2303a9083016SGiridhar Malavali 2304a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_ACTIVE */ 2305a9083016SGiridhar Malavali if (drv_active == 0xffffffff) { 230677e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 230777e334d2SGiridhar Malavali QLA82XX_DRV_NOT_ACTIVE); 2308a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2309a9083016SGiridhar Malavali } 231077e334d2SGiridhar Malavali drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2311a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2312a9083016SGiridhar Malavali } 2313a9083016SGiridhar Malavali 2314a9083016SGiridhar Malavali inline void 2315a9083016SGiridhar Malavali qla82xx_clear_drv_active(struct qla_hw_data *ha) 2316a9083016SGiridhar Malavali { 2317a9083016SGiridhar Malavali uint32_t drv_active; 2318a9083016SGiridhar Malavali 2319a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 232077e334d2SGiridhar Malavali drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2321a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2322a9083016SGiridhar Malavali } 2323a9083016SGiridhar Malavali 2324a9083016SGiridhar Malavali static inline int 2325a9083016SGiridhar Malavali qla82xx_need_reset(struct qla_hw_data *ha) 2326a9083016SGiridhar Malavali { 2327a9083016SGiridhar Malavali uint32_t drv_state; 2328a9083016SGiridhar Malavali int rval; 2329a9083016SGiridhar Malavali 23307d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 233108de2844SGiridhar Malavali return 1; 233208de2844SGiridhar Malavali else { 2333a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 233477e334d2SGiridhar Malavali rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2335a9083016SGiridhar Malavali return rval; 2336a9083016SGiridhar Malavali } 233708de2844SGiridhar Malavali } 2338a9083016SGiridhar Malavali 2339a9083016SGiridhar Malavali static inline void 2340a9083016SGiridhar Malavali qla82xx_set_rst_ready(struct qla_hw_data *ha) 2341a9083016SGiridhar Malavali { 2342a9083016SGiridhar Malavali uint32_t drv_state; 2343a9083016SGiridhar Malavali scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2344a9083016SGiridhar Malavali 2345a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2346a9083016SGiridhar Malavali 2347a9083016SGiridhar Malavali /* If reset value is all FF's, initialize DRV_STATE */ 2348a9083016SGiridhar Malavali if (drv_state == 0xffffffff) { 234977e334d2SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2350a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2351a9083016SGiridhar Malavali } 2352a9083016SGiridhar Malavali drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 235308de2844SGiridhar Malavali ql_dbg(ql_dbg_init, vha, 0x00bb, 235408de2844SGiridhar Malavali "drv_state = 0x%08x.\n", drv_state); 2355a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2356a9083016SGiridhar Malavali } 2357a9083016SGiridhar Malavali 2358a9083016SGiridhar Malavali static inline void 2359a9083016SGiridhar Malavali qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2360a9083016SGiridhar Malavali { 2361a9083016SGiridhar Malavali uint32_t drv_state; 2362a9083016SGiridhar Malavali 2363a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2364a9083016SGiridhar Malavali drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2365a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2366a9083016SGiridhar Malavali } 2367a9083016SGiridhar Malavali 2368a9083016SGiridhar Malavali static inline void 2369a9083016SGiridhar Malavali qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2370a9083016SGiridhar Malavali { 2371a9083016SGiridhar Malavali uint32_t qsnt_state; 2372a9083016SGiridhar Malavali 2373a9083016SGiridhar Malavali qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2374a9083016SGiridhar Malavali qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2375a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2376a9083016SGiridhar Malavali } 2377a9083016SGiridhar Malavali 2378579d12b5SSaurav Kashyap void 2379579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2380579d12b5SSaurav Kashyap { 2381579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2382579d12b5SSaurav Kashyap uint32_t qsnt_state; 2383579d12b5SSaurav Kashyap 2384579d12b5SSaurav Kashyap qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2385579d12b5SSaurav Kashyap qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2386579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2387579d12b5SSaurav Kashyap } 2388579d12b5SSaurav Kashyap 238977e334d2SGiridhar Malavali static int 239077e334d2SGiridhar Malavali qla82xx_load_fw(scsi_qla_host_t *vha) 2391a9083016SGiridhar Malavali { 2392a9083016SGiridhar Malavali int rst; 2393a9083016SGiridhar Malavali struct fw_blob *blob; 2394a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2395a9083016SGiridhar Malavali 2396a9083016SGiridhar Malavali if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 23977c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009f, 23987c3df132SSaurav Kashyap "Error during CRB initialization.\n"); 2399a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2400a9083016SGiridhar Malavali } 2401a9083016SGiridhar Malavali udelay(500); 2402a9083016SGiridhar Malavali 2403a9083016SGiridhar Malavali /* Bring QM and CAMRAM out of reset */ 2404a9083016SGiridhar Malavali rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2405a9083016SGiridhar Malavali rst &= ~((1 << 28) | (1 << 24)); 2406a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2407a9083016SGiridhar Malavali 2408a9083016SGiridhar Malavali /* 2409a9083016SGiridhar Malavali * FW Load priority: 2410a9083016SGiridhar Malavali * 1) Operational firmware residing in flash. 2411a9083016SGiridhar Malavali * 2) Firmware via request-firmware interface (.bin file). 2412a9083016SGiridhar Malavali */ 2413a9083016SGiridhar Malavali if (ql2xfwloadbin == 2) 2414a9083016SGiridhar Malavali goto try_blob_fw; 2415a9083016SGiridhar Malavali 24167c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a0, 24177c3df132SSaurav Kashyap "Attempting to load firmware from flash.\n"); 2418a9083016SGiridhar Malavali 2419a9083016SGiridhar Malavali if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 24207c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a1, 242100adc9a0SSaurav Kashyap "Firmware loaded successfully from flash.\n"); 2422a9083016SGiridhar Malavali return QLA_SUCCESS; 2423875efad7SChad Dupuis } else { 24247c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0108, 24257c3df132SSaurav Kashyap "Firmware load from flash failed.\n"); 2426a9083016SGiridhar Malavali } 2427875efad7SChad Dupuis 2428a9083016SGiridhar Malavali try_blob_fw: 24297c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a2, 24307c3df132SSaurav Kashyap "Attempting to load firmware from blob.\n"); 2431a9083016SGiridhar Malavali 2432a9083016SGiridhar Malavali /* Load firmware blob. */ 2433a9083016SGiridhar Malavali blob = ha->hablob = qla2x00_request_firmware(vha); 2434a9083016SGiridhar Malavali if (!blob) { 24357c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a3, 243600adc9a0SSaurav Kashyap "Firmware image not present.\n"); 2437a9083016SGiridhar Malavali goto fw_load_failed; 2438a9083016SGiridhar Malavali } 2439a9083016SGiridhar Malavali 24409c2b2975SHarish Zunjarrao /* Validating firmware blob */ 24419c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24429c2b2975SHarish Zunjarrao QLA82XX_FLASH_ROMIMAGE)) { 24439c2b2975SHarish Zunjarrao /* Fallback to URI format */ 24449c2b2975SHarish Zunjarrao if (qla82xx_validate_firmware_blob(vha, 24459c2b2975SHarish Zunjarrao QLA82XX_UNIFIED_ROMIMAGE)) { 24467c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a4, 24477c3df132SSaurav Kashyap "No valid firmware image found.\n"); 24489c2b2975SHarish Zunjarrao return QLA_FUNCTION_FAILED; 24499c2b2975SHarish Zunjarrao } 24509c2b2975SHarish Zunjarrao } 24519c2b2975SHarish Zunjarrao 2452a9083016SGiridhar Malavali if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 24537c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00a5, 24547c3df132SSaurav Kashyap "Firmware loaded successfully from binary blob.\n"); 2455a9083016SGiridhar Malavali return QLA_SUCCESS; 24568a318fe1SBart Van Assche } 24578a318fe1SBart Van Assche 24587c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a6, 24597c3df132SSaurav Kashyap "Firmware load failed for binary blob.\n"); 2460a9083016SGiridhar Malavali blob->fw = NULL; 2461a9083016SGiridhar Malavali blob = NULL; 2462a9083016SGiridhar Malavali 2463a9083016SGiridhar Malavali fw_load_failed: 2464a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2465a9083016SGiridhar Malavali } 2466a9083016SGiridhar Malavali 2467a5b36321SLalit Chandivade int 2468a9083016SGiridhar Malavali qla82xx_start_firmware(scsi_qla_host_t *vha) 2469a9083016SGiridhar Malavali { 2470a9083016SGiridhar Malavali uint16_t lnk; 2471a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2472a9083016SGiridhar Malavali 2473a9083016SGiridhar Malavali /* scrub dma mask expansion register */ 247477e334d2SGiridhar Malavali qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2475a9083016SGiridhar Malavali 24763711333dSGiridhar Malavali /* Put both the PEG CMD and RCV PEG to default state 24773711333dSGiridhar Malavali * of 0 before resetting the hardware 24783711333dSGiridhar Malavali */ 24793711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 24803711333dSGiridhar Malavali qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 24813711333dSGiridhar Malavali 2482a9083016SGiridhar Malavali /* Overwrite stale initialization register values */ 2483a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2484a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2485a9083016SGiridhar Malavali 2486a9083016SGiridhar Malavali if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 24877c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00a7, 24887c3df132SSaurav Kashyap "Error trying to start fw.\n"); 2489a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2490a9083016SGiridhar Malavali } 2491a9083016SGiridhar Malavali 2492a9083016SGiridhar Malavali /* Handshake with the card before we register the devices. */ 2493a9083016SGiridhar Malavali if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 24947c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00aa, 24957c3df132SSaurav Kashyap "Error during card handshake.\n"); 2496a9083016SGiridhar Malavali return QLA_FUNCTION_FAILED; 2497a9083016SGiridhar Malavali } 2498a9083016SGiridhar Malavali 2499a9083016SGiridhar Malavali /* Negotiated Link width */ 250010092438SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 2501a9083016SGiridhar Malavali ha->link_width = (lnk >> 4) & 0x3f; 2502a9083016SGiridhar Malavali 2503a9083016SGiridhar Malavali /* Synchronize with Receive peg */ 2504a9083016SGiridhar Malavali return qla82xx_check_rcvpeg_state(ha); 2505a9083016SGiridhar Malavali } 2506a9083016SGiridhar Malavali 25077ffa5b93SBart Van Assche static __le32 * 25087ffa5b93SBart Van Assche qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 2509a9083016SGiridhar Malavali uint32_t length) 2510a9083016SGiridhar Malavali { 2511a9083016SGiridhar Malavali uint32_t i; 2512a9083016SGiridhar Malavali uint32_t val; 2513a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2514a9083016SGiridhar Malavali 2515a9083016SGiridhar Malavali /* Dword reads to flash. */ 2516a9083016SGiridhar Malavali for (i = 0; i < length/4; i++, faddr += 4) { 2517a9083016SGiridhar Malavali if (qla82xx_rom_fast_read(ha, faddr, &val)) { 25187c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x0106, 25197c3df132SSaurav Kashyap "Do ROM fast read failed.\n"); 2520a9083016SGiridhar Malavali goto done_read; 2521a9083016SGiridhar Malavali } 2522ad950360SBart Van Assche dwptr[i] = cpu_to_le32(val); 2523a9083016SGiridhar Malavali } 2524a9083016SGiridhar Malavali done_read: 2525a9083016SGiridhar Malavali return dwptr; 2526a9083016SGiridhar Malavali } 2527a9083016SGiridhar Malavali 252877e334d2SGiridhar Malavali static int 2529a9083016SGiridhar Malavali qla82xx_unprotect_flash(struct qla_hw_data *ha) 2530a9083016SGiridhar Malavali { 2531a9083016SGiridhar Malavali int ret; 2532a9083016SGiridhar Malavali uint32_t val; 25337c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2534a9083016SGiridhar Malavali 2535a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2536a9083016SGiridhar Malavali if (ret < 0) { 25377c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb014, 25387c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2539a9083016SGiridhar Malavali return ret; 2540a9083016SGiridhar Malavali } 2541a9083016SGiridhar Malavali 2542a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2543a9083016SGiridhar Malavali if (ret < 0) 2544a9083016SGiridhar Malavali goto done_unprotect; 2545a9083016SGiridhar Malavali 25460547fb37SLalit Chandivade val &= ~(BLOCK_PROTECT_BITS << 2); 2547a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2548a9083016SGiridhar Malavali if (ret < 0) { 25490547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2550a9083016SGiridhar Malavali qla82xx_write_status_reg(ha, val); 2551a9083016SGiridhar Malavali } 2552a9083016SGiridhar Malavali 2553a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25547c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb015, 25557c3df132SSaurav Kashyap "Write disable failed.\n"); 2556a9083016SGiridhar Malavali 2557a9083016SGiridhar Malavali done_unprotect: 2558d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2559a9083016SGiridhar Malavali return ret; 2560a9083016SGiridhar Malavali } 2561a9083016SGiridhar Malavali 256277e334d2SGiridhar Malavali static int 2563a9083016SGiridhar Malavali qla82xx_protect_flash(struct qla_hw_data *ha) 2564a9083016SGiridhar Malavali { 2565a9083016SGiridhar Malavali int ret; 2566a9083016SGiridhar Malavali uint32_t val; 25677c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2568a9083016SGiridhar Malavali 2569a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2570a9083016SGiridhar Malavali if (ret < 0) { 25717c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb016, 25727c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2573a9083016SGiridhar Malavali return ret; 2574a9083016SGiridhar Malavali } 2575a9083016SGiridhar Malavali 2576a9083016SGiridhar Malavali ret = qla82xx_read_status_reg(ha, &val); 2577a9083016SGiridhar Malavali if (ret < 0) 2578a9083016SGiridhar Malavali goto done_protect; 2579a9083016SGiridhar Malavali 25800547fb37SLalit Chandivade val |= (BLOCK_PROTECT_BITS << 2); 2581a9083016SGiridhar Malavali /* LOCK all sectors */ 2582a9083016SGiridhar Malavali ret = qla82xx_write_status_reg(ha, val); 2583a9083016SGiridhar Malavali if (ret < 0) 25847c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb017, 25857c3df132SSaurav Kashyap "Write status register failed.\n"); 2586a9083016SGiridhar Malavali 2587a9083016SGiridhar Malavali if (qla82xx_write_disable_flash(ha) != 0) 25887c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb018, 25897c3df132SSaurav Kashyap "Write disable failed.\n"); 2590a9083016SGiridhar Malavali done_protect: 2591d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2592a9083016SGiridhar Malavali return ret; 2593a9083016SGiridhar Malavali } 2594a9083016SGiridhar Malavali 259577e334d2SGiridhar Malavali static int 2596a9083016SGiridhar Malavali qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2597a9083016SGiridhar Malavali { 2598a9083016SGiridhar Malavali int ret = 0; 25997c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2600a9083016SGiridhar Malavali 2601a9083016SGiridhar Malavali ret = ql82xx_rom_lock_d(ha); 2602a9083016SGiridhar Malavali if (ret < 0) { 26037c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb019, 26047c3df132SSaurav Kashyap "ROM Lock failed.\n"); 2605a9083016SGiridhar Malavali return ret; 2606a9083016SGiridhar Malavali } 2607a9083016SGiridhar Malavali 2608a9083016SGiridhar Malavali qla82xx_flash_set_write_enable(ha); 2609a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2610a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2611a9083016SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2612a9083016SGiridhar Malavali 2613a9083016SGiridhar Malavali if (qla82xx_wait_rom_done(ha)) { 26147c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01a, 26157c3df132SSaurav Kashyap "Error waiting for rom done.\n"); 2616a9083016SGiridhar Malavali ret = -1; 2617a9083016SGiridhar Malavali goto done; 2618a9083016SGiridhar Malavali } 2619a9083016SGiridhar Malavali ret = qla82xx_flash_wait_write_finish(ha); 2620a9083016SGiridhar Malavali done: 2621d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2622a9083016SGiridhar Malavali return ret; 2623a9083016SGiridhar Malavali } 2624a9083016SGiridhar Malavali 2625a9083016SGiridhar Malavali /* 2626a9083016SGiridhar Malavali * Address and length are byte address 2627a9083016SGiridhar Malavali */ 26283695310eSJoe Carnuccio void * 26293695310eSJoe Carnuccio qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2630a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2631a9083016SGiridhar Malavali { 2632a9083016SGiridhar Malavali scsi_block_requests(vha->host); 26337ffa5b93SBart Van Assche qla82xx_read_flash_data(vha, buf, offset, length); 2634a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2635a9083016SGiridhar Malavali return buf; 2636a9083016SGiridhar Malavali } 2637a9083016SGiridhar Malavali 2638a9083016SGiridhar Malavali static int 26397ffa5b93SBart Van Assche qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr, 2640a9083016SGiridhar Malavali uint32_t faddr, uint32_t dwords) 2641a9083016SGiridhar Malavali { 2642a9083016SGiridhar Malavali int ret; 2643a9083016SGiridhar Malavali uint32_t liter; 264452c82823SBart Van Assche uint32_t rest_addr; 2645a9083016SGiridhar Malavali dma_addr_t optrom_dma; 2646a9083016SGiridhar Malavali void *optrom = NULL; 2647a9083016SGiridhar Malavali int page_mode = 0; 2648a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2649a9083016SGiridhar Malavali 2650a9083016SGiridhar Malavali ret = -1; 2651a9083016SGiridhar Malavali 2652a9083016SGiridhar Malavali /* Prepare burst-capable write on supported ISPs. */ 2653a9083016SGiridhar Malavali if (page_mode && !(faddr & 0xfff) && 2654a9083016SGiridhar Malavali dwords > OPTROM_BURST_DWORDS) { 2655a9083016SGiridhar Malavali optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2656a9083016SGiridhar Malavali &optrom_dma, GFP_KERNEL); 2657a9083016SGiridhar Malavali if (!optrom) { 26587c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01b, 26597c3df132SSaurav Kashyap "Unable to allocate memory " 266000adc9a0SSaurav Kashyap "for optrom burst write (%x KB).\n", 2661a9083016SGiridhar Malavali OPTROM_BURST_SIZE / 1024); 2662a9083016SGiridhar Malavali } 2663a9083016SGiridhar Malavali } 2664a9083016SGiridhar Malavali 2665a9083016SGiridhar Malavali rest_addr = ha->fdt_block_size - 1; 2666a9083016SGiridhar Malavali 2667a9083016SGiridhar Malavali ret = qla82xx_unprotect_flash(ha); 2668a9083016SGiridhar Malavali if (ret) { 26697c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01c, 2670a9083016SGiridhar Malavali "Unable to unprotect flash for update.\n"); 2671a9083016SGiridhar Malavali goto write_done; 2672a9083016SGiridhar Malavali } 2673a9083016SGiridhar Malavali 2674a9083016SGiridhar Malavali for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2675a9083016SGiridhar Malavali /* Are we at the beginning of a sector? */ 2676a9083016SGiridhar Malavali if ((faddr & rest_addr) == 0) { 2677a9083016SGiridhar Malavali 2678a9083016SGiridhar Malavali ret = qla82xx_erase_sector(ha, faddr); 2679a9083016SGiridhar Malavali if (ret) { 26807c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01d, 26817c3df132SSaurav Kashyap "Unable to erase sector: address=%x.\n", 26827c3df132SSaurav Kashyap faddr); 2683a9083016SGiridhar Malavali break; 2684a9083016SGiridhar Malavali } 2685a9083016SGiridhar Malavali } 2686a9083016SGiridhar Malavali 2687a9083016SGiridhar Malavali /* Go with burst-write. */ 2688a9083016SGiridhar Malavali if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2689a9083016SGiridhar Malavali /* Copy data to DMA'ble buffer. */ 2690a9083016SGiridhar Malavali memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2691a9083016SGiridhar Malavali 2692a9083016SGiridhar Malavali ret = qla2x00_load_ram(vha, optrom_dma, 2693a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2694a9083016SGiridhar Malavali OPTROM_BURST_DWORDS); 2695a9083016SGiridhar Malavali if (ret != QLA_SUCCESS) { 26967c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01e, 2697a9083016SGiridhar Malavali "Unable to burst-write optrom segment " 2698a9083016SGiridhar Malavali "(%x/%x/%llx).\n", ret, 2699a9083016SGiridhar Malavali (ha->flash_data_off | faddr), 2700a9083016SGiridhar Malavali (unsigned long long)optrom_dma); 27017c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb01f, 2702a9083016SGiridhar Malavali "Reverting to slow-write.\n"); 2703a9083016SGiridhar Malavali 2704a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2705a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2706a9083016SGiridhar Malavali optrom = NULL; 2707a9083016SGiridhar Malavali } else { 2708a9083016SGiridhar Malavali liter += OPTROM_BURST_DWORDS - 1; 2709a9083016SGiridhar Malavali faddr += OPTROM_BURST_DWORDS - 1; 2710a9083016SGiridhar Malavali dwptr += OPTROM_BURST_DWORDS - 1; 2711a9083016SGiridhar Malavali continue; 2712a9083016SGiridhar Malavali } 2713a9083016SGiridhar Malavali } 2714a9083016SGiridhar Malavali 2715a9083016SGiridhar Malavali ret = qla82xx_write_flash_dword(ha, faddr, 27167ffa5b93SBart Van Assche le32_to_cpu(*dwptr)); 2717a9083016SGiridhar Malavali if (ret) { 27187c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb020, 27197c3df132SSaurav Kashyap "Unable to program flash address=%x data=%x.\n", 27207c3df132SSaurav Kashyap faddr, *dwptr); 2721a9083016SGiridhar Malavali break; 2722a9083016SGiridhar Malavali } 2723a9083016SGiridhar Malavali } 2724a9083016SGiridhar Malavali 2725a9083016SGiridhar Malavali ret = qla82xx_protect_flash(ha); 2726a9083016SGiridhar Malavali if (ret) 27277c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb021, 2728a9083016SGiridhar Malavali "Unable to protect flash after update.\n"); 2729a9083016SGiridhar Malavali write_done: 2730a9083016SGiridhar Malavali if (optrom) 2731a9083016SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 2732a9083016SGiridhar Malavali OPTROM_BURST_SIZE, optrom, optrom_dma); 2733a9083016SGiridhar Malavali return ret; 2734a9083016SGiridhar Malavali } 2735a9083016SGiridhar Malavali 2736a9083016SGiridhar Malavali int 27373695310eSJoe Carnuccio qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2738a9083016SGiridhar Malavali uint32_t offset, uint32_t length) 2739a9083016SGiridhar Malavali { 2740a9083016SGiridhar Malavali int rval; 2741a9083016SGiridhar Malavali 2742a9083016SGiridhar Malavali /* Suspend HBA. */ 2743a9083016SGiridhar Malavali scsi_block_requests(vha->host); 27443695310eSJoe Carnuccio rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2); 2745a9083016SGiridhar Malavali scsi_unblock_requests(vha->host); 2746a9083016SGiridhar Malavali 2747a9083016SGiridhar Malavali /* Convert return ISP82xx to generic */ 2748a9083016SGiridhar Malavali if (rval) 2749a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 2750a9083016SGiridhar Malavali else 2751a9083016SGiridhar Malavali rval = QLA_SUCCESS; 2752a9083016SGiridhar Malavali return rval; 2753a9083016SGiridhar Malavali } 2754a9083016SGiridhar Malavali 2755a9083016SGiridhar Malavali void 27565162cf0cSGiridhar Malavali qla82xx_start_iocbs(scsi_qla_host_t *vha) 2757a9083016SGiridhar Malavali { 27585162cf0cSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2759a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 2760a9083016SGiridhar Malavali uint32_t dbval; 2761a9083016SGiridhar Malavali 2762a9083016SGiridhar Malavali /* Adjust ring index. */ 2763a9083016SGiridhar Malavali req->ring_index++; 2764a9083016SGiridhar Malavali if (req->ring_index == req->length) { 2765a9083016SGiridhar Malavali req->ring_index = 0; 2766a9083016SGiridhar Malavali req->ring_ptr = req->ring; 2767a9083016SGiridhar Malavali } else 2768a9083016SGiridhar Malavali req->ring_ptr++; 2769a9083016SGiridhar Malavali 2770a9083016SGiridhar Malavali dbval = 0x04 | (ha->portnum << 5); 2771a9083016SGiridhar Malavali 2772a9083016SGiridhar Malavali dbval = dbval | (req->id << 8) | (req->ring_index << 16); 27736907869dSGiridhar Malavali if (ql2xdbwr) 27748dfa4b5aSBart Van Assche qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval); 27756907869dSGiridhar Malavali else { 277604474d3aSBart Van Assche wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2777a9083016SGiridhar Malavali wmb(); 277804474d3aSBart Van Assche while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { 277904474d3aSBart Van Assche wrt_reg_dword(ha->nxdb_wr_ptr, dbval); 2780a9083016SGiridhar Malavali wmb(); 2781a9083016SGiridhar Malavali } 2782a9083016SGiridhar Malavali } 27836907869dSGiridhar Malavali } 2784a9083016SGiridhar Malavali 2785fa492630SSaurav Kashyap static void 2786fa492630SSaurav Kashyap qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2787e6a4202aSShyam Sundar { 27887c3df132SSaurav Kashyap scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 27894babb90eSHiral Patel uint32_t lock_owner = 0; 27907c3df132SSaurav Kashyap 27914babb90eSHiral Patel if (qla82xx_rom_lock(ha)) { 27924babb90eSHiral Patel lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); 2793e6a4202aSShyam Sundar /* Someone else is holding the lock. */ 27947c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb022, 27954babb90eSHiral Patel "Resetting rom_lock, Lock Owner %u.\n", lock_owner); 27964babb90eSHiral Patel } 2797e6a4202aSShyam Sundar /* 2798e6a4202aSShyam Sundar * Either we got the lock, or someone 2799e6a4202aSShyam Sundar * else died while holding it. 2800e6a4202aSShyam Sundar * In either case, unlock. 2801e6a4202aSShyam Sundar */ 2802d652e093SChad Dupuis qla82xx_rom_unlock(ha); 2803e6a4202aSShyam Sundar } 2804e6a4202aSShyam Sundar 2805a9083016SGiridhar Malavali /* 2806a9083016SGiridhar Malavali * qla82xx_device_bootstrap 2807a9083016SGiridhar Malavali * Initialize device, set DEV_READY, start fw 2808a9083016SGiridhar Malavali * 2809a9083016SGiridhar Malavali * Note: 2810a9083016SGiridhar Malavali * IDC lock must be held upon entry 2811a9083016SGiridhar Malavali * 2812a9083016SGiridhar Malavali * Return: 2813a9083016SGiridhar Malavali * Success : 0 2814a9083016SGiridhar Malavali * Failed : 1 2815a9083016SGiridhar Malavali */ 2816a9083016SGiridhar Malavali static int 2817a9083016SGiridhar Malavali qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2818a9083016SGiridhar Malavali { 2819e6a4202aSShyam Sundar int rval = QLA_SUCCESS; 282003d32f97STej Prakash int i; 2821a9083016SGiridhar Malavali uint32_t old_count, count; 2822a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 282303d32f97STej Prakash int need_reset = 0; 2824a9083016SGiridhar Malavali 2825e6a4202aSShyam Sundar need_reset = qla82xx_need_reset(ha); 2826a9083016SGiridhar Malavali 2827e6a4202aSShyam Sundar if (need_reset) { 2828e6a4202aSShyam Sundar /* We are trying to perform a recovery here. */ 282903d32f97STej Prakash if (ha->flags.isp82xx_fw_hung) 2830e6a4202aSShyam Sundar qla82xx_rom_lock_recovery(ha); 2831e6a4202aSShyam Sundar } else { 283203d32f97STej Prakash old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 283303d32f97STej Prakash for (i = 0; i < 10; i++) { 283403d32f97STej Prakash msleep(200); 283503d32f97STej Prakash count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 283603d32f97STej Prakash if (count != old_count) { 283703d32f97STej Prakash rval = QLA_SUCCESS; 2838a9083016SGiridhar Malavali goto dev_ready; 2839a9083016SGiridhar Malavali } 284003d32f97STej Prakash } 284103d32f97STej Prakash qla82xx_rom_lock_recovery(ha); 284203d32f97STej Prakash } 2843a9083016SGiridhar Malavali 2844a9083016SGiridhar Malavali /* set to DEV_INITIALIZING */ 28457c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009e, 28467c3df132SSaurav Kashyap "HW State: INITIALIZING.\n"); 28477d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2848a9083016SGiridhar Malavali 2849a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 2850a9083016SGiridhar Malavali rval = qla82xx_start_firmware(vha); 2851a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 2852a9083016SGiridhar Malavali 2853a9083016SGiridhar Malavali if (rval != QLA_SUCCESS) { 28547c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00ad, 28557c3df132SSaurav Kashyap "HW State: FAILED.\n"); 2856a9083016SGiridhar Malavali qla82xx_clear_drv_active(ha); 28577d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2858a9083016SGiridhar Malavali return rval; 2859a9083016SGiridhar Malavali } 2860a9083016SGiridhar Malavali 2861a9083016SGiridhar Malavali dev_ready: 28627c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00ae, 28637c3df132SSaurav Kashyap "HW State: READY.\n"); 28647d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2865a9083016SGiridhar Malavali 2866a9083016SGiridhar Malavali return QLA_SUCCESS; 2867a9083016SGiridhar Malavali } 2868a9083016SGiridhar Malavali 2869579d12b5SSaurav Kashyap /* 2870579d12b5SSaurav Kashyap * qla82xx_need_qsnt_handler 2871579d12b5SSaurav Kashyap * Code to start quiescence sequence 2872579d12b5SSaurav Kashyap * 2873579d12b5SSaurav Kashyap * Note: 2874579d12b5SSaurav Kashyap * IDC lock must be held upon entry 2875579d12b5SSaurav Kashyap * 2876579d12b5SSaurav Kashyap * Return: void 2877579d12b5SSaurav Kashyap */ 2878579d12b5SSaurav Kashyap 2879579d12b5SSaurav Kashyap static void 2880579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2881579d12b5SSaurav Kashyap { 2882579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2883579d12b5SSaurav Kashyap uint32_t dev_state, drv_state, drv_active; 2884579d12b5SSaurav Kashyap unsigned long reset_timeout; 2885579d12b5SSaurav Kashyap 2886579d12b5SSaurav Kashyap if (vha->flags.online) { 2887579d12b5SSaurav Kashyap /*Block any further I/O and wait for pending cmnds to complete*/ 28888fcd6b8bSChad Dupuis qla2x00_quiesce_io(vha); 2889579d12b5SSaurav Kashyap } 2890579d12b5SSaurav Kashyap 2891579d12b5SSaurav Kashyap /* Set the quiescence ready bit */ 2892579d12b5SSaurav Kashyap qla82xx_set_qsnt_ready(ha); 2893579d12b5SSaurav Kashyap 2894579d12b5SSaurav Kashyap /*wait for 30 secs for other functions to ack */ 2895579d12b5SSaurav Kashyap reset_timeout = jiffies + (30 * HZ); 2896579d12b5SSaurav Kashyap 2897579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2898579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2899579d12b5SSaurav Kashyap /* Its 2 that is written when qsnt is acked, moving one bit */ 2900579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2901579d12b5SSaurav Kashyap 2902579d12b5SSaurav Kashyap while (drv_state != drv_active) { 2903579d12b5SSaurav Kashyap 2904579d12b5SSaurav Kashyap if (time_after_eq(jiffies, reset_timeout)) { 2905579d12b5SSaurav Kashyap /* quiescence timeout, other functions didn't ack 2906579d12b5SSaurav Kashyap * changing the state to DEV_READY 2907579d12b5SSaurav Kashyap */ 29087c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb023, 29095f28d2d7SSaurav Kashyap "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d " 29105f28d2d7SSaurav Kashyap "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME, 29117c3df132SSaurav Kashyap drv_active, drv_state); 2912579d12b5SSaurav Kashyap qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 29137d613ac6SSantosh Vernekar QLA8XXX_DEV_READY); 29147c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb025, 29157c3df132SSaurav Kashyap "HW State: DEV_READY.\n"); 2916579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2917579d12b5SSaurav Kashyap qla2x00_perform_loop_resync(vha); 2918579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2919579d12b5SSaurav Kashyap 2920579d12b5SSaurav Kashyap qla82xx_clear_qsnt_ready(vha); 2921579d12b5SSaurav Kashyap return; 2922579d12b5SSaurav Kashyap } 2923579d12b5SSaurav Kashyap 2924579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2925579d12b5SSaurav Kashyap msleep(1000); 2926579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2927579d12b5SSaurav Kashyap 2928579d12b5SSaurav Kashyap drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2929579d12b5SSaurav Kashyap drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2930579d12b5SSaurav Kashyap drv_active = drv_active << 0x01; 2931579d12b5SSaurav Kashyap } 2932579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2933579d12b5SSaurav Kashyap /* everyone acked so set the state to DEV_QUIESCENCE */ 29347d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 29357c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0xb026, 29367c3df132SSaurav Kashyap "HW State: DEV_QUIESCENT.\n"); 29377d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); 2938579d12b5SSaurav Kashyap } 2939579d12b5SSaurav Kashyap } 2940579d12b5SSaurav Kashyap 2941579d12b5SSaurav Kashyap /* 2942579d12b5SSaurav Kashyap * qla82xx_wait_for_state_change 2943579d12b5SSaurav Kashyap * Wait for device state to change from given current state 2944579d12b5SSaurav Kashyap * 2945579d12b5SSaurav Kashyap * Note: 2946579d12b5SSaurav Kashyap * IDC lock must not be held upon entry 2947579d12b5SSaurav Kashyap * 2948579d12b5SSaurav Kashyap * Return: 2949579d12b5SSaurav Kashyap * Changed device state. 2950579d12b5SSaurav Kashyap */ 2951579d12b5SSaurav Kashyap uint32_t 2952579d12b5SSaurav Kashyap qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2953579d12b5SSaurav Kashyap { 2954579d12b5SSaurav Kashyap struct qla_hw_data *ha = vha->hw; 2955579d12b5SSaurav Kashyap uint32_t dev_state; 2956579d12b5SSaurav Kashyap 2957579d12b5SSaurav Kashyap do { 2958579d12b5SSaurav Kashyap msleep(1000); 2959579d12b5SSaurav Kashyap qla82xx_idc_lock(ha); 2960579d12b5SSaurav Kashyap dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2961579d12b5SSaurav Kashyap qla82xx_idc_unlock(ha); 2962579d12b5SSaurav Kashyap } while (dev_state == curr_state); 2963579d12b5SSaurav Kashyap 2964579d12b5SSaurav Kashyap return dev_state; 2965579d12b5SSaurav Kashyap } 2966579d12b5SSaurav Kashyap 29677d613ac6SSantosh Vernekar void 29687d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(scsi_qla_host_t *vha) 2969a9083016SGiridhar Malavali { 2970a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 2971a9083016SGiridhar Malavali 2972a9083016SGiridhar Malavali /* Disable the board */ 29737c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x00b8, 29747c3df132SSaurav Kashyap "Disabling the board.\n"); 2975a9083016SGiridhar Malavali 29761459c0e1SSaurav Kashyap if (IS_QLA82XX(ha)) { 2977b963752fSGiridhar Malavali qla82xx_clear_drv_active(ha); 2978b963752fSGiridhar Malavali qla82xx_idc_unlock(ha); 29797ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) { 2980c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha); 29817ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 29821459c0e1SSaurav Kashyap } 2983b963752fSGiridhar Malavali 2984a9083016SGiridhar Malavali /* Set DEV_FAILED flag to disable timer */ 2985a9083016SGiridhar Malavali vha->device_flags |= DFLG_DEV_FAILED; 2986a9083016SGiridhar Malavali qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 29873c75ad1dSHimanshu Madhani qla2x00_mark_all_devices_lost(vha); 2988a9083016SGiridhar Malavali vha->flags.online = 0; 2989a9083016SGiridhar Malavali vha->flags.init_done = 0; 2990a9083016SGiridhar Malavali } 2991a9083016SGiridhar Malavali 2992a9083016SGiridhar Malavali /* 2993a9083016SGiridhar Malavali * qla82xx_need_reset_handler 2994a9083016SGiridhar Malavali * Code to start reset sequence 2995a9083016SGiridhar Malavali * 2996a9083016SGiridhar Malavali * Note: 2997a9083016SGiridhar Malavali * IDC lock must be held upon entry 2998a9083016SGiridhar Malavali * 2999a9083016SGiridhar Malavali * Return: 3000a9083016SGiridhar Malavali * Success : 0 3001a9083016SGiridhar Malavali * Failed : 1 3002a9083016SGiridhar Malavali */ 3003a9083016SGiridhar Malavali static void 3004a9083016SGiridhar Malavali qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3005a9083016SGiridhar Malavali { 3006e5fdae55SChad Dupuis uint32_t dev_state, drv_state, drv_active; 3007e5fdae55SChad Dupuis uint32_t active_mask = 0; 3008a9083016SGiridhar Malavali unsigned long reset_timeout; 3009a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3010a9083016SGiridhar Malavali struct req_que *req = ha->req_q_map[0]; 3011a9083016SGiridhar Malavali 3012a9083016SGiridhar Malavali if (vha->flags.online) { 3013a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3014a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3015a9083016SGiridhar Malavali ha->isp_ops->get_flash_version(vha, req->ring); 3016a9083016SGiridhar Malavali ha->isp_ops->nvram_config(vha); 3017a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3018a9083016SGiridhar Malavali } 3019a9083016SGiridhar Malavali 302008de2844SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30217d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_owner) { 302208de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb028, 302308de2844SGiridhar Malavali "reset_acknowledged by 0x%x\n", ha->portnum); 3024a9083016SGiridhar Malavali qla82xx_set_rst_ready(ha); 302508de2844SGiridhar Malavali } else { 302608de2844SGiridhar Malavali active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 302708de2844SGiridhar Malavali drv_active &= active_mask; 302808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb029, 302908de2844SGiridhar Malavali "active_mask: 0x%08x\n", active_mask); 303008de2844SGiridhar Malavali } 3031a9083016SGiridhar Malavali 3032a9083016SGiridhar Malavali /* wait for 10 seconds for reset ack from all functions */ 30337d613ac6SSantosh Vernekar reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 3034a9083016SGiridhar Malavali 3035a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3036a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 303708de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3038a9083016SGiridhar Malavali 303908de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02a, 304008de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 304108de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 304208de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 304308de2844SGiridhar Malavali 304408de2844SGiridhar Malavali while (drv_state != drv_active && 30457d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_INITIALIZING) { 3046a9083016SGiridhar Malavali if (time_after_eq(jiffies, reset_timeout)) { 30477c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x00b5, 30487c3df132SSaurav Kashyap "Reset timeout.\n"); 3049a9083016SGiridhar Malavali break; 3050a9083016SGiridhar Malavali } 3051a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3052a9083016SGiridhar Malavali msleep(1000); 3053a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3054a9083016SGiridhar Malavali drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3055a9083016SGiridhar Malavali drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 30567d613ac6SSantosh Vernekar if (ha->flags.nic_core_reset_owner) 305708de2844SGiridhar Malavali drv_active &= active_mask; 305808de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3059a9083016SGiridhar Malavali } 3060a9083016SGiridhar Malavali 306108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb02b, 306208de2844SGiridhar Malavali "drv_state: 0x%08x, drv_active: 0x%08x, " 306308de2844SGiridhar Malavali "dev_state: 0x%08x, active_mask: 0x%08x\n", 306408de2844SGiridhar Malavali drv_state, drv_active, dev_state, active_mask); 306508de2844SGiridhar Malavali 30667c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b6, 30677c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 30687c3df132SSaurav Kashyap dev_state, 306908de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3070f1af6208SGiridhar Malavali 3071a9083016SGiridhar Malavali /* Force to DEV_COLD unless someone else is starting a reset */ 30727d613ac6SSantosh Vernekar if (dev_state != QLA8XXX_DEV_INITIALIZING && 30737d613ac6SSantosh Vernekar dev_state != QLA8XXX_DEV_COLD) { 30747c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x00b7, 30757c3df132SSaurav Kashyap "HW State: COLD/RE-INIT.\n"); 30767d613ac6SSantosh Vernekar qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3077f4e1648aSVikas Chaudhary qla82xx_set_rst_ready(ha); 307808de2844SGiridhar Malavali if (ql2xmdenable) { 307908de2844SGiridhar Malavali if (qla82xx_md_collect(vha)) 308008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb02c, 3081b6d0d9d5SGiridhar Malavali "Minidump not collected.\n"); 308208de2844SGiridhar Malavali } else 308308de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04f, 308408de2844SGiridhar Malavali "Minidump disabled.\n"); 3085a9083016SGiridhar Malavali } 3086a9083016SGiridhar Malavali } 3087a9083016SGiridhar Malavali 30883173167fSGiridhar Malavali int 308908de2844SGiridhar Malavali qla82xx_check_md_needed(scsi_qla_host_t *vha) 309008de2844SGiridhar Malavali { 309108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 309208de2844SGiridhar Malavali uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 30933173167fSGiridhar Malavali int rval = QLA_SUCCESS; 309408de2844SGiridhar Malavali 30953173167fSGiridhar Malavali fw_major_version = ha->fw_major_version; 30963173167fSGiridhar Malavali fw_minor_version = ha->fw_minor_version; 30973173167fSGiridhar Malavali fw_subminor_version = ha->fw_subminor_version; 30983173167fSGiridhar Malavali 30996246b8a1SGiridhar Malavali rval = qla2x00_get_fw_version(vha); 31003173167fSGiridhar Malavali if (rval != QLA_SUCCESS) 31013173167fSGiridhar Malavali return rval; 31023173167fSGiridhar Malavali 31033173167fSGiridhar Malavali if (ql2xmdenable) { 310408de2844SGiridhar Malavali if (!ha->fw_dumped) { 3105edaa5c74SSaurav Kashyap if ((fw_major_version != ha->fw_major_version || 310608de2844SGiridhar Malavali fw_minor_version != ha->fw_minor_version || 3107edaa5c74SSaurav Kashyap fw_subminor_version != ha->fw_subminor_version) || 3108edaa5c74SSaurav Kashyap (ha->prev_minidump_failed)) { 31097ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb02d, 3110edaa5c74SSaurav Kashyap "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n", 31119bc3bf27SGiridhar Malavali fw_major_version, fw_minor_version, 31129bc3bf27SGiridhar Malavali fw_subminor_version, 311308de2844SGiridhar Malavali ha->fw_major_version, 31143173167fSGiridhar Malavali ha->fw_minor_version, 3115edaa5c74SSaurav Kashyap ha->fw_subminor_version, 3116edaa5c74SSaurav Kashyap ha->prev_minidump_failed); 311708de2844SGiridhar Malavali /* Release MiniDump resources */ 311808de2844SGiridhar Malavali qla82xx_md_free(vha); 311908de2844SGiridhar Malavali /* ALlocate MiniDump resources */ 312008de2844SGiridhar Malavali qla82xx_md_prep(vha); 31212e264269SGiridhar Malavali } 312208de2844SGiridhar Malavali } else 312308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02e, 3124d8424f68SJoe Perches "Firmware dump available to retrieve\n"); 312508de2844SGiridhar Malavali } 31263173167fSGiridhar Malavali return rval; 31273173167fSGiridhar Malavali } 312808de2844SGiridhar Malavali 312908de2844SGiridhar Malavali 3130fa492630SSaurav Kashyap static int 3131a9083016SGiridhar Malavali qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3132a9083016SGiridhar Malavali { 31337190575fSGiridhar Malavali uint32_t fw_heartbeat_counter; 31347190575fSGiridhar Malavali int status = 0; 3135a9083016SGiridhar Malavali 31367190575fSGiridhar Malavali fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 31377190575fSGiridhar Malavali QLA82XX_PEG_ALIVE_COUNTER); 3138a5b36321SLalit Chandivade /* all 0xff, assume AER/EEH in progress, ignore */ 31397c3df132SSaurav Kashyap if (fw_heartbeat_counter == 0xffffffff) { 31407c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6003, 31417c3df132SSaurav Kashyap "FW heartbeat counter is 0xffffffff, " 31427c3df132SSaurav Kashyap "returning status=%d.\n", status); 31437190575fSGiridhar Malavali return status; 31447c3df132SSaurav Kashyap } 3145a9083016SGiridhar Malavali if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3146a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat++; 3147a9083016SGiridhar Malavali /* FW not alive after 2 seconds */ 3148a9083016SGiridhar Malavali if (vha->seconds_since_last_heartbeat == 2) { 3149a9083016SGiridhar Malavali vha->seconds_since_last_heartbeat = 0; 31507190575fSGiridhar Malavali status = 1; 3151a9083016SGiridhar Malavali } 3152efa786ccSLalit Chandivade } else 3153efa786ccSLalit Chandivade vha->seconds_since_last_heartbeat = 0; 3154a9083016SGiridhar Malavali vha->fw_heartbeat_counter = fw_heartbeat_counter; 31557c3df132SSaurav Kashyap if (status) 31567c3df132SSaurav Kashyap ql_dbg(ql_dbg_timer, vha, 0x6004, 31577c3df132SSaurav Kashyap "Returning status=%d.\n", status); 31587190575fSGiridhar Malavali return status; 3159a9083016SGiridhar Malavali } 3160a9083016SGiridhar Malavali 3161a9083016SGiridhar Malavali /* 3162a9083016SGiridhar Malavali * qla82xx_device_state_handler 3163a9083016SGiridhar Malavali * Main state handler 3164a9083016SGiridhar Malavali * 3165a9083016SGiridhar Malavali * Note: 3166a9083016SGiridhar Malavali * IDC lock must be held upon entry 3167a9083016SGiridhar Malavali * 3168a9083016SGiridhar Malavali * Return: 3169a9083016SGiridhar Malavali * Success : 0 3170a9083016SGiridhar Malavali * Failed : 1 3171a9083016SGiridhar Malavali */ 3172a9083016SGiridhar Malavali int 3173a9083016SGiridhar Malavali qla82xx_device_state_handler(scsi_qla_host_t *vha) 3174a9083016SGiridhar Malavali { 3175a9083016SGiridhar Malavali uint32_t dev_state; 317692dbf273SGiridhar Malavali uint32_t old_dev_state; 3177a9083016SGiridhar Malavali int rval = QLA_SUCCESS; 3178a9083016SGiridhar Malavali unsigned long dev_init_timeout; 3179a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 318092dbf273SGiridhar Malavali int loopcount = 0; 3181a9083016SGiridhar Malavali 3182a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 31830251ce8cSSaurav Kashyap if (!vha->flags.init_done) { 3184a9083016SGiridhar Malavali qla82xx_set_drv_active(vha); 31850251ce8cSSaurav Kashyap qla82xx_set_idc_version(vha); 31860251ce8cSSaurav Kashyap } 3187a9083016SGiridhar Malavali 3188a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 318992dbf273SGiridhar Malavali old_dev_state = dev_state; 31907c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009b, 31917c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 31927c3df132SSaurav Kashyap dev_state, 319308de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3194a9083016SGiridhar Malavali 3195a9083016SGiridhar Malavali /* wait for 30 seconds for device to go ready */ 31967d613ac6SSantosh Vernekar dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 3197a9083016SGiridhar Malavali 3198a9083016SGiridhar Malavali while (1) { 3199a9083016SGiridhar Malavali 3200a9083016SGiridhar Malavali if (time_after_eq(jiffies, dev_init_timeout)) { 32017c3df132SSaurav Kashyap ql_log(ql_log_fatal, vha, 0x009c, 32027c3df132SSaurav Kashyap "Device init failed.\n"); 3203a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3204a9083016SGiridhar Malavali break; 3205a9083016SGiridhar Malavali } 3206a9083016SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 320792dbf273SGiridhar Malavali if (old_dev_state != dev_state) { 320892dbf273SGiridhar Malavali loopcount = 0; 320992dbf273SGiridhar Malavali old_dev_state = dev_state; 321092dbf273SGiridhar Malavali } 321192dbf273SGiridhar Malavali if (loopcount < 5) { 32127c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x009d, 32137c3df132SSaurav Kashyap "Device state is 0x%x = %s.\n", 32147c3df132SSaurav Kashyap dev_state, 321508de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : 32167c3df132SSaurav Kashyap "Unknown"); 321792dbf273SGiridhar Malavali } 3218f1af6208SGiridhar Malavali 3219a9083016SGiridhar Malavali switch (dev_state) { 32207d613ac6SSantosh Vernekar case QLA8XXX_DEV_READY: 32217d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 0; 32227916bb90SChad Dupuis goto rel_lock; 32237d613ac6SSantosh Vernekar case QLA8XXX_DEV_COLD: 3224a9083016SGiridhar Malavali rval = qla82xx_device_bootstrap(vha); 322508de2844SGiridhar Malavali break; 32267d613ac6SSantosh Vernekar case QLA8XXX_DEV_INITIALIZING: 3227a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3228a9083016SGiridhar Malavali msleep(1000); 3229a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3230a9083016SGiridhar Malavali break; 32317d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_RESET: 3232ed0de87cSGiridhar Malavali if (!ql2xdontresethba) 3233a9083016SGiridhar Malavali qla82xx_need_reset_handler(vha); 3234c8582ad9SSaurav Kashyap else { 3235c8582ad9SSaurav Kashyap qla82xx_idc_unlock(ha); 3236c8582ad9SSaurav Kashyap msleep(1000); 3237c8582ad9SSaurav Kashyap qla82xx_idc_lock(ha); 3238c8582ad9SSaurav Kashyap } 32390060ddf8SGiridhar Malavali dev_init_timeout = jiffies + 32407d613ac6SSantosh Vernekar (ha->fcoe_dev_init_timeout * HZ); 3241a9083016SGiridhar Malavali break; 32427d613ac6SSantosh Vernekar case QLA8XXX_DEV_NEED_QUIESCENT: 3243579d12b5SSaurav Kashyap qla82xx_need_qsnt_handler(vha); 3244579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3245c1c7178cSBart Van Assche dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3246579d12b5SSaurav Kashyap * HZ); 3247579d12b5SSaurav Kashyap break; 32487d613ac6SSantosh Vernekar case QLA8XXX_DEV_QUIESCENT: 3249579d12b5SSaurav Kashyap /* Owner will exit and other will wait for the state 3250579d12b5SSaurav Kashyap * to get changed 3251579d12b5SSaurav Kashyap */ 3252579d12b5SSaurav Kashyap if (ha->flags.quiesce_owner) 32537916bb90SChad Dupuis goto rel_lock; 3254579d12b5SSaurav Kashyap 3255a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3256a9083016SGiridhar Malavali msleep(1000); 3257a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3258579d12b5SSaurav Kashyap 3259579d12b5SSaurav Kashyap /* Reset timeout value after quiescence handler */ 3260c1c7178cSBart Van Assche dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout 3261579d12b5SSaurav Kashyap * HZ); 3262a9083016SGiridhar Malavali break; 32637d613ac6SSantosh Vernekar case QLA8XXX_DEV_FAILED: 32647d613ac6SSantosh Vernekar qla8xxx_dev_failed_handler(vha); 3265a9083016SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3266a9083016SGiridhar Malavali goto exit; 3267a9083016SGiridhar Malavali default: 3268a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3269a9083016SGiridhar Malavali msleep(1000); 3270a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3271a9083016SGiridhar Malavali } 327292dbf273SGiridhar Malavali loopcount++; 3273a9083016SGiridhar Malavali } 32747916bb90SChad Dupuis rel_lock: 3275a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 32767916bb90SChad Dupuis exit: 3277a9083016SGiridhar Malavali return rval; 3278a9083016SGiridhar Malavali } 3279a9083016SGiridhar Malavali 32805988aeb2SGiridhar Malavali static int qla82xx_check_temp(scsi_qla_host_t *vha) 32815988aeb2SGiridhar Malavali { 32825988aeb2SGiridhar Malavali uint32_t temp, temp_state, temp_val; 32835988aeb2SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 32845988aeb2SGiridhar Malavali 32855988aeb2SGiridhar Malavali temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); 32865988aeb2SGiridhar Malavali temp_state = qla82xx_get_temp_state(temp); 32875988aeb2SGiridhar Malavali temp_val = qla82xx_get_temp_val(temp); 32885988aeb2SGiridhar Malavali 32895988aeb2SGiridhar Malavali if (temp_state == QLA82XX_TEMP_PANIC) { 32905988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600e, 32915988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 32925988aeb2SGiridhar Malavali " maximum allowed. Hardware has been shut down.\n", 32935988aeb2SGiridhar Malavali temp_val); 32945988aeb2SGiridhar Malavali return 1; 32955988aeb2SGiridhar Malavali } else if (temp_state == QLA82XX_TEMP_WARN) { 32965988aeb2SGiridhar Malavali ql_log(ql_log_warn, vha, 0x600f, 32975988aeb2SGiridhar Malavali "Device temperature %d degrees C exceeds " 32985988aeb2SGiridhar Malavali "operating range. Immediate action needed.\n", 32995988aeb2SGiridhar Malavali temp_val); 33005988aeb2SGiridhar Malavali } 33015988aeb2SGiridhar Malavali return 0; 33025988aeb2SGiridhar Malavali } 33035988aeb2SGiridhar Malavali 33041ae47cf3SJoe Carnuccio int qla82xx_read_temperature(scsi_qla_host_t *vha) 33051ae47cf3SJoe Carnuccio { 33061ae47cf3SJoe Carnuccio uint32_t temp; 33071ae47cf3SJoe Carnuccio 33081ae47cf3SJoe Carnuccio temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE); 33091ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp); 33101ae47cf3SJoe Carnuccio } 33111ae47cf3SJoe Carnuccio 3312c8f6544eSChad Dupuis void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3313c8f6544eSChad Dupuis { 3314c8f6544eSChad Dupuis struct qla_hw_data *ha = vha->hw; 3315c8f6544eSChad Dupuis 3316c8f6544eSChad Dupuis if (ha->flags.mbox_busy) { 3317c8f6544eSChad Dupuis ha->flags.mbox_int = 1; 33188937f2f1SGiridhar Malavali ha->flags.mbox_busy = 0; 3319c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6010, 3320c8f6544eSChad Dupuis "Doing premature completion of mbx command.\n"); 332136439832Sgurinder.shergill@hp.com if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3322c8f6544eSChad Dupuis complete(&ha->mbx_intr_comp); 3323c8f6544eSChad Dupuis } 3324c8f6544eSChad Dupuis } 3325c8f6544eSChad Dupuis 3326a9083016SGiridhar Malavali void qla82xx_watchdog(scsi_qla_host_t *vha) 3327a9083016SGiridhar Malavali { 33287190575fSGiridhar Malavali uint32_t dev_state, halt_status; 3329a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3330a9083016SGiridhar Malavali 3331a9083016SGiridhar Malavali /* don't poll if reset is going on */ 33327d613ac6SSantosh Vernekar if (!ha->flags.nic_core_reset_hdlr_active) { 33337190575fSGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 33345988aeb2SGiridhar Malavali if (qla82xx_check_temp(vha)) { 33355988aeb2SGiridhar Malavali set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33365988aeb2SGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 33375988aeb2SGiridhar Malavali qla82xx_clear_pending_mbx(vha); 33387d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 33397190575fSGiridhar Malavali !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 33407c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6001, 33417c3df132SSaurav Kashyap "Adapter reset needed.\n"); 3342a9083016SGiridhar Malavali set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 33437d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 3344579d12b5SSaurav Kashyap !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 33457c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x6002, 33467c3df132SSaurav Kashyap "Quiescent needed.\n"); 3347579d12b5SSaurav Kashyap set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 33487d613ac6SSantosh Vernekar } else if (dev_state == QLA8XXX_DEV_FAILED && 33497916bb90SChad Dupuis !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) && 33507916bb90SChad Dupuis vha->flags.online == 1) { 33517916bb90SChad Dupuis ql_log(ql_log_warn, vha, 0xb055, 33527916bb90SChad Dupuis "Adapter state is failed. Offlining.\n"); 33537916bb90SChad Dupuis set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 33547916bb90SChad Dupuis ha->flags.isp82xx_fw_hung = 1; 33557916bb90SChad Dupuis qla82xx_clear_pending_mbx(vha); 3356a9083016SGiridhar Malavali } else { 33577190575fSGiridhar Malavali if (qla82xx_check_fw_alive(vha)) { 335863154916SGiridhar Malavali ql_dbg(ql_dbg_timer, vha, 0x6011, 335963154916SGiridhar Malavali "disabling pause transmit on port 0 & 1.\n"); 336063154916SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 336163154916SGiridhar Malavali CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 33627190575fSGiridhar Malavali halt_status = qla82xx_rd_32(ha, 33637190575fSGiridhar Malavali QLA82XX_PEG_HALT_STATUS1); 336463154916SGiridhar Malavali ql_log(ql_log_info, vha, 0x6005, 33657c3df132SSaurav Kashyap "dumping hw/fw registers:.\n " 33667c3df132SSaurav Kashyap " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 33677c3df132SSaurav Kashyap " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 33687c3df132SSaurav Kashyap " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 33697c3df132SSaurav Kashyap " PEG_NET_4_PC: 0x%x.\n", halt_status, 33700e8edb03SGiridhar Malavali qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 33710e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33720e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_0 + 0x3c), 33730e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33740e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_1 + 0x3c), 33750e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33760e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_2 + 0x3c), 33770e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33780e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_3 + 0x3c), 33790e8edb03SGiridhar Malavali qla82xx_rd_32(ha, 33800e8edb03SGiridhar Malavali QLA82XX_CRB_PEG_NET_4 + 0x3c)); 33812cc97965SGiridhar Malavali if (((halt_status & 0x1fffff00) >> 8) == 0x67) 338210a340e6SChad Dupuis ql_log(ql_log_warn, vha, 0xb052, 338310a340e6SChad Dupuis "Firmware aborted with " 338410a340e6SChad Dupuis "error code 0x00006700. Device is " 338510a340e6SChad Dupuis "being reset.\n"); 33867190575fSGiridhar Malavali if (halt_status & HALT_STATUS_UNRECOVERABLE) { 33877190575fSGiridhar Malavali set_bit(ISP_UNRECOVERABLE, 33887190575fSGiridhar Malavali &vha->dpc_flags); 33897190575fSGiridhar Malavali } else { 33907c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 0x6006, 33917c3df132SSaurav Kashyap "Detect abort needed.\n"); 33927190575fSGiridhar Malavali set_bit(ISP_ABORT_NEEDED, 33937190575fSGiridhar Malavali &vha->dpc_flags); 33947190575fSGiridhar Malavali } 33957190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3396c8f6544eSChad Dupuis ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3397c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 33987190575fSGiridhar Malavali } 3399a9083016SGiridhar Malavali } 3400a9083016SGiridhar Malavali } 3401a9083016SGiridhar Malavali } 3402a9083016SGiridhar Malavali 3403a9083016SGiridhar Malavali int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3404a9083016SGiridhar Malavali { 34057ec0effdSAtul Deshmukh int rval = -1; 34067ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 34077ec0effdSAtul Deshmukh 34087ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3409a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 34107ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 34117ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 34127ec0effdSAtul Deshmukh /* Decide the reset ownership */ 34137ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 34147ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 34157ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 34167ec0effdSAtul Deshmukh } 3417a9083016SGiridhar Malavali return rval; 3418a9083016SGiridhar Malavali } 3419a9083016SGiridhar Malavali 342008de2844SGiridhar Malavali void 342108de2844SGiridhar Malavali qla82xx_set_reset_owner(scsi_qla_host_t *vha) 342208de2844SGiridhar Malavali { 342308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 34247ec0effdSAtul Deshmukh uint32_t dev_state = 0; 342508de2844SGiridhar Malavali 34267ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 342708de2844SGiridhar Malavali dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 34287ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 34297ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 34307ec0effdSAtul Deshmukh 34317d613ac6SSantosh Vernekar if (dev_state == QLA8XXX_DEV_READY) { 343208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb02f, 343308de2844SGiridhar Malavali "HW State: NEED RESET\n"); 34347ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) { 343508de2844SGiridhar Malavali qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 34367d613ac6SSantosh Vernekar QLA8XXX_DEV_NEED_RESET); 34377d613ac6SSantosh Vernekar ha->flags.nic_core_reset_owner = 1; 343808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb030, 343908de2844SGiridhar Malavali "reset_owner is 0x%x\n", ha->portnum); 34407ec0effdSAtul Deshmukh } else if (IS_QLA8044(ha)) 34417ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 34427ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET); 344308de2844SGiridhar Malavali } else 344408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb031, 344508de2844SGiridhar Malavali "Device state is 0x%x = %s.\n", 344608de2844SGiridhar Malavali dev_state, 344708de2844SGiridhar Malavali dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 344808de2844SGiridhar Malavali } 344908de2844SGiridhar Malavali 3450a9083016SGiridhar Malavali /* 3451a9083016SGiridhar Malavali * qla82xx_abort_isp 3452a9083016SGiridhar Malavali * Resets ISP and aborts all outstanding commands. 3453a9083016SGiridhar Malavali * 3454a9083016SGiridhar Malavali * Input: 3455a9083016SGiridhar Malavali * ha = adapter block pointer. 3456a9083016SGiridhar Malavali * 3457a9083016SGiridhar Malavali * Returns: 3458a9083016SGiridhar Malavali * 0 = success 3459a9083016SGiridhar Malavali */ 3460a9083016SGiridhar Malavali int 3461a9083016SGiridhar Malavali qla82xx_abort_isp(scsi_qla_host_t *vha) 3462a9083016SGiridhar Malavali { 34637ec0effdSAtul Deshmukh int rval = -1; 3464a9083016SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 3465a9083016SGiridhar Malavali 3466a9083016SGiridhar Malavali if (vha->device_flags & DFLG_DEV_FAILED) { 34677c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8024, 34687c3df132SSaurav Kashyap "Device in failed state, exiting.\n"); 3469a9083016SGiridhar Malavali return QLA_SUCCESS; 3470a9083016SGiridhar Malavali } 34717d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 1; 3472a9083016SGiridhar Malavali 3473a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 347408de2844SGiridhar Malavali qla82xx_set_reset_owner(vha); 3475a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3476a9083016SGiridhar Malavali 34777ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 3478a9083016SGiridhar Malavali rval = qla82xx_device_state_handler(vha); 34797ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) { 34807ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 34817ec0effdSAtul Deshmukh /* Decide the reset ownership */ 34827ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 34837ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 34847ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 34857ec0effdSAtul Deshmukh } 3486a9083016SGiridhar Malavali 3487a9083016SGiridhar Malavali qla82xx_idc_lock(ha); 3488a9083016SGiridhar Malavali qla82xx_clear_rst_ready(ha); 3489a9083016SGiridhar Malavali qla82xx_idc_unlock(ha); 3490a9083016SGiridhar Malavali 3491cdbb0a4fSSantosh Vernekar if (rval == QLA_SUCCESS) { 34927190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 0; 34937d613ac6SSantosh Vernekar ha->flags.nic_core_reset_hdlr_active = 0; 3494a9083016SGiridhar Malavali qla82xx_restart_isp(vha); 3495cdbb0a4fSSantosh Vernekar } 3496f1af6208SGiridhar Malavali 3497f1af6208SGiridhar Malavali if (rval) { 3498f1af6208SGiridhar Malavali vha->flags.online = 1; 3499f1af6208SGiridhar Malavali if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3500f1af6208SGiridhar Malavali if (ha->isp_abort_cnt == 0) { 35017c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8027, 35027c3df132SSaurav Kashyap "ISP error recover failed - board " 35037c3df132SSaurav Kashyap "disabled.\n"); 3504f1af6208SGiridhar Malavali /* 3505f1af6208SGiridhar Malavali * The next call disables the board 3506f1af6208SGiridhar Malavali * completely. 3507f1af6208SGiridhar Malavali */ 3508f1af6208SGiridhar Malavali ha->isp_ops->reset_adapter(vha); 3509f1af6208SGiridhar Malavali vha->flags.online = 0; 3510f1af6208SGiridhar Malavali clear_bit(ISP_ABORT_RETRY, 3511f1af6208SGiridhar Malavali &vha->dpc_flags); 3512f1af6208SGiridhar Malavali rval = QLA_SUCCESS; 3513f1af6208SGiridhar Malavali } else { /* schedule another ISP abort */ 3514f1af6208SGiridhar Malavali ha->isp_abort_cnt--; 35157c3df132SSaurav Kashyap ql_log(ql_log_warn, vha, 0x8036, 35167c3df132SSaurav Kashyap "ISP abort - retry remaining %d.\n", 35177c3df132SSaurav Kashyap ha->isp_abort_cnt); 3518f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3519f1af6208SGiridhar Malavali } 3520f1af6208SGiridhar Malavali } else { 3521f1af6208SGiridhar Malavali ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 35227c3df132SSaurav Kashyap ql_dbg(ql_dbg_taskm, vha, 0x8029, 35237c3df132SSaurav Kashyap "ISP error recovery - retrying (%d) more times.\n", 35247c3df132SSaurav Kashyap ha->isp_abort_cnt); 3525f1af6208SGiridhar Malavali set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3526f1af6208SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 3527f1af6208SGiridhar Malavali } 3528f1af6208SGiridhar Malavali } 3529a9083016SGiridhar Malavali return rval; 3530a9083016SGiridhar Malavali } 3531a9083016SGiridhar Malavali 3532a9083016SGiridhar Malavali /* 3533a9083016SGiridhar Malavali * qla82xx_fcoe_ctx_reset 3534a9083016SGiridhar Malavali * Perform a quick reset and aborts all outstanding commands. 3535a9083016SGiridhar Malavali * This will only perform an FCoE context reset and avoids a full blown 3536a9083016SGiridhar Malavali * chip reset. 3537a9083016SGiridhar Malavali * 3538a9083016SGiridhar Malavali * Input: 3539a9083016SGiridhar Malavali * ha = adapter block pointer. 3540a9083016SGiridhar Malavali * is_reset_path = flag for identifying the reset path. 3541a9083016SGiridhar Malavali * 3542a9083016SGiridhar Malavali * Returns: 3543a9083016SGiridhar Malavali * 0 = success 3544a9083016SGiridhar Malavali */ 3545a9083016SGiridhar Malavali int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3546a9083016SGiridhar Malavali { 3547a9083016SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 3548a9083016SGiridhar Malavali 3549a9083016SGiridhar Malavali if (vha->flags.online) { 3550a9083016SGiridhar Malavali /* Abort all outstanding commands, so as to be requeued later */ 3551a9083016SGiridhar Malavali qla2x00_abort_isp_cleanup(vha); 3552a9083016SGiridhar Malavali } 3553a9083016SGiridhar Malavali 3554a9083016SGiridhar Malavali /* Stop currently executing firmware. 3555a9083016SGiridhar Malavali * This will destroy existing FCoE context at the F/W end. 3556a9083016SGiridhar Malavali */ 3557a9083016SGiridhar Malavali qla2x00_try_to_stop_firmware(vha); 3558a9083016SGiridhar Malavali 3559a9083016SGiridhar Malavali /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3560a9083016SGiridhar Malavali rval = qla82xx_restart_isp(vha); 3561a9083016SGiridhar Malavali 3562a9083016SGiridhar Malavali return rval; 3563a9083016SGiridhar Malavali } 3564a9083016SGiridhar Malavali 3565a9083016SGiridhar Malavali /* 3566a9083016SGiridhar Malavali * qla2x00_wait_for_fcoe_ctx_reset 3567a9083016SGiridhar Malavali * Wait till the FCoE context is reset. 3568a9083016SGiridhar Malavali * 3569a9083016SGiridhar Malavali * Note: 3570a9083016SGiridhar Malavali * Does context switching here. 3571a9083016SGiridhar Malavali * Release SPIN_LOCK (if any) before calling this routine. 3572a9083016SGiridhar Malavali * 3573a9083016SGiridhar Malavali * Return: 3574a9083016SGiridhar Malavali * Success (fcoe_ctx reset is done) : 0 3575a9083016SGiridhar Malavali * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3576a9083016SGiridhar Malavali */ 3577a9083016SGiridhar Malavali int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3578a9083016SGiridhar Malavali { 3579a9083016SGiridhar Malavali int status = QLA_FUNCTION_FAILED; 3580a9083016SGiridhar Malavali unsigned long wait_reset; 3581a9083016SGiridhar Malavali 3582a9083016SGiridhar Malavali wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3583a9083016SGiridhar Malavali while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3584a9083016SGiridhar Malavali test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3585a9083016SGiridhar Malavali && time_before(jiffies, wait_reset)) { 3586a9083016SGiridhar Malavali 3587a9083016SGiridhar Malavali set_current_state(TASK_UNINTERRUPTIBLE); 3588a9083016SGiridhar Malavali schedule_timeout(HZ); 3589a9083016SGiridhar Malavali 3590a9083016SGiridhar Malavali if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3591a9083016SGiridhar Malavali !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3592a9083016SGiridhar Malavali status = QLA_SUCCESS; 3593a9083016SGiridhar Malavali break; 3594a9083016SGiridhar Malavali } 3595a9083016SGiridhar Malavali } 35967c3df132SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb027, 3597d8424f68SJoe Perches "%s: status=%d.\n", __func__, status); 3598a9083016SGiridhar Malavali 3599a9083016SGiridhar Malavali return status; 3600a9083016SGiridhar Malavali } 36017190575fSGiridhar Malavali 36027190575fSGiridhar Malavali void 36037190575fSGiridhar Malavali qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 36047190575fSGiridhar Malavali { 36057ec0effdSAtul Deshmukh int i, fw_state = 0; 36067190575fSGiridhar Malavali unsigned long flags; 36077190575fSGiridhar Malavali struct qla_hw_data *ha = vha->hw; 36087190575fSGiridhar Malavali 36097190575fSGiridhar Malavali /* Check if 82XX firmware is alive or not 36107190575fSGiridhar Malavali * We may have arrived here from NEED_RESET 36117190575fSGiridhar Malavali * detection only 36127190575fSGiridhar Malavali */ 36137190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36147190575fSGiridhar Malavali for (i = 0; i < 2; i++) { 36157190575fSGiridhar Malavali msleep(1000); 36167ec0effdSAtul Deshmukh if (IS_QLA82XX(ha)) 36177ec0effdSAtul Deshmukh fw_state = qla82xx_check_fw_alive(vha); 36187ec0effdSAtul Deshmukh else if (IS_QLA8044(ha)) 36197ec0effdSAtul Deshmukh fw_state = qla8044_check_fw_alive(vha); 36207ec0effdSAtul Deshmukh if (fw_state) { 36217190575fSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1; 3622c8f6544eSChad Dupuis qla82xx_clear_pending_mbx(vha); 36237190575fSGiridhar Malavali break; 36247190575fSGiridhar Malavali } 36257190575fSGiridhar Malavali } 36267190575fSGiridhar Malavali } 36277c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b0, 36287c3df132SSaurav Kashyap "Entered %s fw_hung=%d.\n", 36297c3df132SSaurav Kashyap __func__, ha->flags.isp82xx_fw_hung); 36307190575fSGiridhar Malavali 36317190575fSGiridhar Malavali /* Abort all commands gracefully if fw NOT hung */ 36327190575fSGiridhar Malavali if (!ha->flags.isp82xx_fw_hung) { 36337190575fSGiridhar Malavali int cnt, que; 36347190575fSGiridhar Malavali srb_t *sp; 36357190575fSGiridhar Malavali struct req_que *req; 36367190575fSGiridhar Malavali 36377190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36387190575fSGiridhar Malavali for (que = 0; que < ha->max_req_queues; que++) { 36397190575fSGiridhar Malavali req = ha->req_q_map[que]; 36407190575fSGiridhar Malavali if (!req) 36417190575fSGiridhar Malavali continue; 36428d93f550SChad Dupuis for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 36437190575fSGiridhar Malavali sp = req->outstanding_cmds[cnt]; 36447190575fSGiridhar Malavali if (sp) { 36455ec9f904SBart Van Assche if ((!sp->u.scmd.crc_ctx || 3646af13b700SGiridhar Malavali (sp->flags & 3647af13b700SGiridhar Malavali SRB_FCP_CMND_DMA_VALID)) && 3648af13b700SGiridhar Malavali !ha->flags.isp82xx_fw_hung) { 36497190575fSGiridhar Malavali spin_unlock_irqrestore( 36507190575fSGiridhar Malavali &ha->hardware_lock, flags); 36517190575fSGiridhar Malavali if (ha->isp_ops->abort_command(sp)) { 36527c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36537c3df132SSaurav Kashyap 0x00b1, 36547c3df132SSaurav Kashyap "mbx abort failed.\n"); 36557190575fSGiridhar Malavali } else { 36567c3df132SSaurav Kashyap ql_log(ql_log_info, vha, 36577c3df132SSaurav Kashyap 0x00b2, 36587c3df132SSaurav Kashyap "mbx abort success.\n"); 36597190575fSGiridhar Malavali } 36607190575fSGiridhar Malavali spin_lock_irqsave(&ha->hardware_lock, flags); 36617190575fSGiridhar Malavali } 36627190575fSGiridhar Malavali } 36637190575fSGiridhar Malavali } 36647190575fSGiridhar Malavali } 36657190575fSGiridhar Malavali spin_unlock_irqrestore(&ha->hardware_lock, flags); 36667190575fSGiridhar Malavali 36677190575fSGiridhar Malavali /* Wait for pending cmds (physical and virtual) to complete */ 366846333cebSNathan Chancellor if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3669fcef0893SBart Van Assche WAIT_HOST) == QLA_SUCCESS) { 36707c3df132SSaurav Kashyap ql_dbg(ql_dbg_init, vha, 0x00b3, 36717c3df132SSaurav Kashyap "Done wait for " 36727c3df132SSaurav Kashyap "pending commands.\n"); 3673fcef0893SBart Van Assche } else { 3674fcef0893SBart Van Assche WARN_ON_ONCE(true); 36757190575fSGiridhar Malavali } 36767190575fSGiridhar Malavali } 36777190575fSGiridhar Malavali } 367808de2844SGiridhar Malavali 367908de2844SGiridhar Malavali /* Minidump related functions */ 368008de2844SGiridhar Malavali static int 368108de2844SGiridhar Malavali qla82xx_minidump_process_control(scsi_qla_host_t *vha, 36827ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 368308de2844SGiridhar Malavali { 368408de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 368508de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_entry; 368608de2844SGiridhar Malavali uint32_t read_value, opcode, poll_time; 368708de2844SGiridhar Malavali uint32_t addr, index, crb_addr; 368808de2844SGiridhar Malavali unsigned long wtime; 368908de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 369008de2844SGiridhar Malavali uint32_t rval = QLA_SUCCESS; 369108de2844SGiridhar Malavali int i; 369208de2844SGiridhar Malavali 369308de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 369408de2844SGiridhar Malavali crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 369508de2844SGiridhar Malavali crb_addr = crb_entry->addr; 369608de2844SGiridhar Malavali 369708de2844SGiridhar Malavali for (i = 0; i < crb_entry->op_count; i++) { 369808de2844SGiridhar Malavali opcode = crb_entry->crb_ctrl.opcode; 369908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WR) { 370008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, 370108de2844SGiridhar Malavali crb_entry->value_1, 1); 370208de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WR; 370308de2844SGiridhar Malavali } 370408de2844SGiridhar Malavali 370508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RW) { 370608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 370708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 370808de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RW; 370908de2844SGiridhar Malavali } 371008de2844SGiridhar Malavali 371108de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_AND) { 371208de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 371308de2844SGiridhar Malavali read_value &= crb_entry->value_2; 371408de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_AND; 371508de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 371608de2844SGiridhar Malavali read_value |= crb_entry->value_3; 371708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 371808de2844SGiridhar Malavali } 371908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 372008de2844SGiridhar Malavali } 372108de2844SGiridhar Malavali 372208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_OR) { 372308de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 372408de2844SGiridhar Malavali read_value |= crb_entry->value_3; 372508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 372608de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_OR; 372708de2844SGiridhar Malavali } 372808de2844SGiridhar Malavali 372908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_POLL) { 373008de2844SGiridhar Malavali poll_time = crb_entry->crb_strd.poll_timeout; 373108de2844SGiridhar Malavali wtime = jiffies + poll_time; 373208de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 373308de2844SGiridhar Malavali 373408de2844SGiridhar Malavali do { 373508de2844SGiridhar Malavali if ((read_value & crb_entry->value_2) 373608de2844SGiridhar Malavali == crb_entry->value_1) 373708de2844SGiridhar Malavali break; 373808de2844SGiridhar Malavali else if (time_after_eq(jiffies, wtime)) { 373908de2844SGiridhar Malavali /* capturing dump failed */ 374008de2844SGiridhar Malavali rval = QLA_FUNCTION_FAILED; 374108de2844SGiridhar Malavali break; 374208de2844SGiridhar Malavali } else 374308de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, 374408de2844SGiridhar Malavali crb_addr, 0, 0); 374508de2844SGiridhar Malavali } while (1); 374608de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_POLL; 374708de2844SGiridhar Malavali } 374808de2844SGiridhar Malavali 374908de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 375008de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 375108de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 375208de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 375308de2844SGiridhar Malavali } else 375408de2844SGiridhar Malavali addr = crb_addr; 375508de2844SGiridhar Malavali 375608de2844SGiridhar Malavali read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 375708de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 375808de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 375908de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 376008de2844SGiridhar Malavali } 376108de2844SGiridhar Malavali 376208de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 376308de2844SGiridhar Malavali if (crb_entry->crb_strd.state_index_a) { 376408de2844SGiridhar Malavali index = crb_entry->crb_strd.state_index_a; 376508de2844SGiridhar Malavali addr = tmplt_hdr->saved_state_array[index]; 376608de2844SGiridhar Malavali } else 376708de2844SGiridhar Malavali addr = crb_addr; 376808de2844SGiridhar Malavali 376908de2844SGiridhar Malavali if (crb_entry->crb_ctrl.state_index_v) { 377008de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 377108de2844SGiridhar Malavali read_value = 377208de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index]; 377308de2844SGiridhar Malavali } else 377408de2844SGiridhar Malavali read_value = crb_entry->value_1; 377508de2844SGiridhar Malavali 377608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, addr, read_value, 1); 377708de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 377808de2844SGiridhar Malavali } 377908de2844SGiridhar Malavali 378008de2844SGiridhar Malavali if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 378108de2844SGiridhar Malavali index = crb_entry->crb_ctrl.state_index_v; 378208de2844SGiridhar Malavali read_value = tmplt_hdr->saved_state_array[index]; 378308de2844SGiridhar Malavali read_value <<= crb_entry->crb_ctrl.shl; 378408de2844SGiridhar Malavali read_value >>= crb_entry->crb_ctrl.shr; 378508de2844SGiridhar Malavali if (crb_entry->value_2) 378608de2844SGiridhar Malavali read_value &= crb_entry->value_2; 378708de2844SGiridhar Malavali read_value |= crb_entry->value_3; 378808de2844SGiridhar Malavali read_value += crb_entry->value_1; 378908de2844SGiridhar Malavali tmplt_hdr->saved_state_array[index] = read_value; 379008de2844SGiridhar Malavali opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 379108de2844SGiridhar Malavali } 379208de2844SGiridhar Malavali crb_addr += crb_entry->crb_strd.addr_stride; 379308de2844SGiridhar Malavali } 379408de2844SGiridhar Malavali return rval; 379508de2844SGiridhar Malavali } 379608de2844SGiridhar Malavali 379708de2844SGiridhar Malavali static void 379808de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 37997ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 380008de2844SGiridhar Malavali { 380108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 380208de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 380308de2844SGiridhar Malavali struct qla82xx_md_entry_rdocm *ocm_hdr; 38047ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 380508de2844SGiridhar Malavali 380608de2844SGiridhar Malavali ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 380708de2844SGiridhar Malavali r_addr = ocm_hdr->read_addr; 380808de2844SGiridhar Malavali r_stride = ocm_hdr->read_addr_stride; 380908de2844SGiridhar Malavali loop_cnt = ocm_hdr->op_count; 381008de2844SGiridhar Malavali 381108de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 381204474d3aSBart Van Assche r_value = rd_reg_dword(r_addr + ha->nx_pcibase); 381308de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 381408de2844SGiridhar Malavali r_addr += r_stride; 381508de2844SGiridhar Malavali } 381608de2844SGiridhar Malavali *d_ptr = data_ptr; 381708de2844SGiridhar Malavali } 381808de2844SGiridhar Malavali 381908de2844SGiridhar Malavali static void 382008de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 38217ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 382208de2844SGiridhar Malavali { 382308de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 382408de2844SGiridhar Malavali uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 382508de2844SGiridhar Malavali struct qla82xx_md_entry_mux *mux_hdr; 38267ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 382708de2844SGiridhar Malavali 382808de2844SGiridhar Malavali mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 382908de2844SGiridhar Malavali r_addr = mux_hdr->read_addr; 383008de2844SGiridhar Malavali s_addr = mux_hdr->select_addr; 383108de2844SGiridhar Malavali s_stride = mux_hdr->select_value_stride; 383208de2844SGiridhar Malavali s_value = mux_hdr->select_value; 383308de2844SGiridhar Malavali loop_cnt = mux_hdr->op_count; 383408de2844SGiridhar Malavali 383508de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 383608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, s_value, 1); 383708de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 383808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(s_value); 383908de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 384008de2844SGiridhar Malavali s_value += s_stride; 384108de2844SGiridhar Malavali } 384208de2844SGiridhar Malavali *d_ptr = data_ptr; 384308de2844SGiridhar Malavali } 384408de2844SGiridhar Malavali 384508de2844SGiridhar Malavali static void 384608de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 38477ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 384808de2844SGiridhar Malavali { 384908de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 385008de2844SGiridhar Malavali uint32_t r_addr, r_stride, loop_cnt, i, r_value; 385108de2844SGiridhar Malavali struct qla82xx_md_entry_crb *crb_hdr; 38527ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 385308de2844SGiridhar Malavali 385408de2844SGiridhar Malavali crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 385508de2844SGiridhar Malavali r_addr = crb_hdr->addr; 385608de2844SGiridhar Malavali r_stride = crb_hdr->crb_strd.addr_stride; 385708de2844SGiridhar Malavali loop_cnt = crb_hdr->op_count; 385808de2844SGiridhar Malavali 385908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 386008de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 386108de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_addr); 386208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 386308de2844SGiridhar Malavali r_addr += r_stride; 386408de2844SGiridhar Malavali } 386508de2844SGiridhar Malavali *d_ptr = data_ptr; 386608de2844SGiridhar Malavali } 386708de2844SGiridhar Malavali 386808de2844SGiridhar Malavali static int 386908de2844SGiridhar Malavali qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 38707ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 387108de2844SGiridhar Malavali { 387208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 387308de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 387408de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 387508de2844SGiridhar Malavali unsigned long p_wait, w_time, p_mask; 387608de2844SGiridhar Malavali uint32_t c_value_w, c_value_r; 387708de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 387808de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 38797ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 388008de2844SGiridhar Malavali 388108de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 388208de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 388308de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 388408de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 388508de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 388608de2844SGiridhar Malavali 388708de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 388808de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 388908de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 389008de2844SGiridhar Malavali p_wait = cache_hdr->cache_ctrl.poll_wait; 389108de2844SGiridhar Malavali p_mask = cache_hdr->cache_ctrl.poll_mask; 389208de2844SGiridhar Malavali 389308de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 389408de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 389508de2844SGiridhar Malavali if (c_value_w) 389608de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 389708de2844SGiridhar Malavali 389808de2844SGiridhar Malavali if (p_mask) { 389908de2844SGiridhar Malavali w_time = jiffies + p_wait; 390008de2844SGiridhar Malavali do { 390108de2844SGiridhar Malavali c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 390208de2844SGiridhar Malavali if ((c_value_r & p_mask) == 0) 390308de2844SGiridhar Malavali break; 390408de2844SGiridhar Malavali else if (time_after_eq(jiffies, w_time)) { 390508de2844SGiridhar Malavali /* capturing dump failed */ 390608de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb032, 390708de2844SGiridhar Malavali "c_value_r: 0x%x, poll_mask: 0x%lx, " 390808de2844SGiridhar Malavali "w_time: 0x%lx\n", 390908de2844SGiridhar Malavali c_value_r, p_mask, w_time); 391008de2844SGiridhar Malavali return rval; 391108de2844SGiridhar Malavali } 391208de2844SGiridhar Malavali } while (1); 391308de2844SGiridhar Malavali } 391408de2844SGiridhar Malavali 391508de2844SGiridhar Malavali addr = r_addr; 391608de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 391708de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 391808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 391908de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 392008de2844SGiridhar Malavali } 392108de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 392208de2844SGiridhar Malavali } 392308de2844SGiridhar Malavali *d_ptr = data_ptr; 392408de2844SGiridhar Malavali return QLA_SUCCESS; 392508de2844SGiridhar Malavali } 392608de2844SGiridhar Malavali 392708de2844SGiridhar Malavali static void 392808de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 39297ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 393008de2844SGiridhar Malavali { 393108de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 393208de2844SGiridhar Malavali uint32_t addr, r_addr, c_addr, t_r_addr; 393308de2844SGiridhar Malavali uint32_t i, k, loop_count, t_value, r_cnt, r_value; 393408de2844SGiridhar Malavali uint32_t c_value_w; 393508de2844SGiridhar Malavali struct qla82xx_md_entry_cache *cache_hdr; 39367ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 393708de2844SGiridhar Malavali 393808de2844SGiridhar Malavali cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 393908de2844SGiridhar Malavali loop_count = cache_hdr->op_count; 394008de2844SGiridhar Malavali r_addr = cache_hdr->read_addr; 394108de2844SGiridhar Malavali c_addr = cache_hdr->control_addr; 394208de2844SGiridhar Malavali c_value_w = cache_hdr->cache_ctrl.write_value; 394308de2844SGiridhar Malavali 394408de2844SGiridhar Malavali t_r_addr = cache_hdr->tag_reg_addr; 394508de2844SGiridhar Malavali t_value = cache_hdr->addr_ctrl.init_tag_value; 394608de2844SGiridhar Malavali r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 394708de2844SGiridhar Malavali 394808de2844SGiridhar Malavali for (i = 0; i < loop_count; i++) { 394908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 395008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 395108de2844SGiridhar Malavali addr = r_addr; 395208de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 395308de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 395408de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 395508de2844SGiridhar Malavali addr += cache_hdr->read_ctrl.read_addr_stride; 395608de2844SGiridhar Malavali } 395708de2844SGiridhar Malavali t_value += cache_hdr->addr_ctrl.tag_value_stride; 395808de2844SGiridhar Malavali } 395908de2844SGiridhar Malavali *d_ptr = data_ptr; 396008de2844SGiridhar Malavali } 396108de2844SGiridhar Malavali 396208de2844SGiridhar Malavali static void 396308de2844SGiridhar Malavali qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 39647ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 396508de2844SGiridhar Malavali { 396608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 396708de2844SGiridhar Malavali uint32_t s_addr, r_addr; 396808de2844SGiridhar Malavali uint32_t r_stride, r_value, r_cnt, qid = 0; 396908de2844SGiridhar Malavali uint32_t i, k, loop_cnt; 397008de2844SGiridhar Malavali struct qla82xx_md_entry_queue *q_hdr; 39717ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 397208de2844SGiridhar Malavali 397308de2844SGiridhar Malavali q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 397408de2844SGiridhar Malavali s_addr = q_hdr->select_addr; 397508de2844SGiridhar Malavali r_cnt = q_hdr->rd_strd.read_addr_cnt; 397608de2844SGiridhar Malavali r_stride = q_hdr->rd_strd.read_addr_stride; 397708de2844SGiridhar Malavali loop_cnt = q_hdr->op_count; 397808de2844SGiridhar Malavali 397908de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 398008de2844SGiridhar Malavali qla82xx_md_rw_32(ha, s_addr, qid, 1); 398108de2844SGiridhar Malavali r_addr = q_hdr->read_addr; 398208de2844SGiridhar Malavali for (k = 0; k < r_cnt; k++) { 398308de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 398408de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 398508de2844SGiridhar Malavali r_addr += r_stride; 398608de2844SGiridhar Malavali } 398708de2844SGiridhar Malavali qid += q_hdr->q_strd.queue_id_stride; 398808de2844SGiridhar Malavali } 398908de2844SGiridhar Malavali *d_ptr = data_ptr; 399008de2844SGiridhar Malavali } 399108de2844SGiridhar Malavali 399208de2844SGiridhar Malavali static void 399308de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 39947ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 399508de2844SGiridhar Malavali { 399608de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 399708de2844SGiridhar Malavali uint32_t r_addr, r_value; 399808de2844SGiridhar Malavali uint32_t i, loop_cnt; 399908de2844SGiridhar Malavali struct qla82xx_md_entry_rdrom *rom_hdr; 40007ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 400108de2844SGiridhar Malavali 400208de2844SGiridhar Malavali rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 400308de2844SGiridhar Malavali r_addr = rom_hdr->read_addr; 400408de2844SGiridhar Malavali loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 400508de2844SGiridhar Malavali 400608de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 400708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 400808de2844SGiridhar Malavali (r_addr & 0xFFFF0000), 1); 400908de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 401008de2844SGiridhar Malavali MD_DIRECT_ROM_READ_BASE + 401108de2844SGiridhar Malavali (r_addr & 0x0000FFFF), 0, 0); 401208de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_value); 401308de2844SGiridhar Malavali r_addr += sizeof(uint32_t); 401408de2844SGiridhar Malavali } 401508de2844SGiridhar Malavali *d_ptr = data_ptr; 401608de2844SGiridhar Malavali } 401708de2844SGiridhar Malavali 401808de2844SGiridhar Malavali static int 401908de2844SGiridhar Malavali qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 40207ffa5b93SBart Van Assche qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr) 402108de2844SGiridhar Malavali { 402208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 402308de2844SGiridhar Malavali uint32_t r_addr, r_value, r_data; 402408de2844SGiridhar Malavali uint32_t i, j, loop_cnt; 402508de2844SGiridhar Malavali struct qla82xx_md_entry_rdmem *m_hdr; 402608de2844SGiridhar Malavali unsigned long flags; 402708de2844SGiridhar Malavali int rval = QLA_FUNCTION_FAILED; 40287ffa5b93SBart Van Assche __le32 *data_ptr = *d_ptr; 402908de2844SGiridhar Malavali 403008de2844SGiridhar Malavali m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 403108de2844SGiridhar Malavali r_addr = m_hdr->read_addr; 403208de2844SGiridhar Malavali loop_cnt = m_hdr->read_data_size/16; 403308de2844SGiridhar Malavali 403408de2844SGiridhar Malavali if (r_addr & 0xf) { 403508de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb033, 4036d6a03581SMasanari Iida "Read addr 0x%x not 16 bytes aligned\n", r_addr); 403708de2844SGiridhar Malavali return rval; 403808de2844SGiridhar Malavali } 403908de2844SGiridhar Malavali 404008de2844SGiridhar Malavali if (m_hdr->read_data_size % 16) { 404108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb034, 404208de2844SGiridhar Malavali "Read data[0x%x] not multiple of 16 bytes\n", 404308de2844SGiridhar Malavali m_hdr->read_data_size); 404408de2844SGiridhar Malavali return rval; 404508de2844SGiridhar Malavali } 404608de2844SGiridhar Malavali 404708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb035, 404808de2844SGiridhar Malavali "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 404908de2844SGiridhar Malavali __func__, r_addr, m_hdr->read_data_size, loop_cnt); 405008de2844SGiridhar Malavali 405108de2844SGiridhar Malavali write_lock_irqsave(&ha->hw_lock, flags); 405208de2844SGiridhar Malavali for (i = 0; i < loop_cnt; i++) { 405308de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 405408de2844SGiridhar Malavali r_value = 0; 405508de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 405608de2844SGiridhar Malavali r_value = MIU_TA_CTL_ENABLE; 405708de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 405808de2844SGiridhar Malavali r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 405908de2844SGiridhar Malavali qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 406008de2844SGiridhar Malavali 406108de2844SGiridhar Malavali for (j = 0; j < MAX_CTL_CHECK; j++) { 406208de2844SGiridhar Malavali r_value = qla82xx_md_rw_32(ha, 406308de2844SGiridhar Malavali MD_MIU_TEST_AGT_CTRL, 0, 0); 406408de2844SGiridhar Malavali if ((r_value & MIU_TA_CTL_BUSY) == 0) 406508de2844SGiridhar Malavali break; 406608de2844SGiridhar Malavali } 406708de2844SGiridhar Malavali 406808de2844SGiridhar Malavali if (j >= MAX_CTL_CHECK) { 406908de2844SGiridhar Malavali printk_ratelimited(KERN_ERR 407008de2844SGiridhar Malavali "failed to read through agent\n"); 407108de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 407208de2844SGiridhar Malavali return rval; 407308de2844SGiridhar Malavali } 407408de2844SGiridhar Malavali 407508de2844SGiridhar Malavali for (j = 0; j < 4; j++) { 407608de2844SGiridhar Malavali r_data = qla82xx_md_rw_32(ha, 407708de2844SGiridhar Malavali MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 407808de2844SGiridhar Malavali *data_ptr++ = cpu_to_le32(r_data); 407908de2844SGiridhar Malavali } 408008de2844SGiridhar Malavali r_addr += 16; 408108de2844SGiridhar Malavali } 408208de2844SGiridhar Malavali write_unlock_irqrestore(&ha->hw_lock, flags); 408308de2844SGiridhar Malavali *d_ptr = data_ptr; 408408de2844SGiridhar Malavali return QLA_SUCCESS; 408508de2844SGiridhar Malavali } 408608de2844SGiridhar Malavali 40877ec0effdSAtul Deshmukh int 408808de2844SGiridhar Malavali qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 408908de2844SGiridhar Malavali { 409008de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 409108de2844SGiridhar Malavali uint64_t chksum = 0; 409208de2844SGiridhar Malavali uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 409308de2844SGiridhar Malavali int count = ha->md_template_size/sizeof(uint32_t); 409408de2844SGiridhar Malavali 409508de2844SGiridhar Malavali while (count-- > 0) 409608de2844SGiridhar Malavali chksum += *d_ptr++; 409708de2844SGiridhar Malavali while (chksum >> 32) 409808de2844SGiridhar Malavali chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 409908de2844SGiridhar Malavali return ~chksum; 410008de2844SGiridhar Malavali } 410108de2844SGiridhar Malavali 410208de2844SGiridhar Malavali static void 410308de2844SGiridhar Malavali qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 410408de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr, int index) 410508de2844SGiridhar Malavali { 410608de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 410708de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb036, 410808de2844SGiridhar Malavali "Skipping entry[%d]: " 410908de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 411008de2844SGiridhar Malavali index, entry_hdr->entry_type, 411108de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 411208de2844SGiridhar Malavali } 411308de2844SGiridhar Malavali 411408de2844SGiridhar Malavali int 411508de2844SGiridhar Malavali qla82xx_md_collect(scsi_qla_host_t *vha) 411608de2844SGiridhar Malavali { 411708de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 411808de2844SGiridhar Malavali int no_entry_hdr = 0; 411908de2844SGiridhar Malavali qla82xx_md_entry_hdr_t *entry_hdr; 412008de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 41217ffa5b93SBart Van Assche __le32 *data_ptr; 412208de2844SGiridhar Malavali uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 412308de2844SGiridhar Malavali int i = 0, rval = QLA_FUNCTION_FAILED; 412408de2844SGiridhar Malavali 412508de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 41267ffa5b93SBart Van Assche data_ptr = ha->md_dump; 412708de2844SGiridhar Malavali 412808de2844SGiridhar Malavali if (ha->fw_dumped) { 4129a8faa263SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb037, 4130a8faa263SGiridhar Malavali "Firmware has been previously dumped (%p) " 4131a8faa263SGiridhar Malavali "-- ignoring request.\n", ha->fw_dump); 413208de2844SGiridhar Malavali goto md_failed; 413308de2844SGiridhar Malavali } 413408de2844SGiridhar Malavali 4135dbe6f492SJason Yan ha->fw_dumped = false; 413608de2844SGiridhar Malavali 413708de2844SGiridhar Malavali if (!ha->md_tmplt_hdr || !ha->md_dump) { 413808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb038, 413908de2844SGiridhar Malavali "Memory not allocated for minidump capture\n"); 414008de2844SGiridhar Malavali goto md_failed; 414108de2844SGiridhar Malavali } 414208de2844SGiridhar Malavali 4143b6d0d9d5SGiridhar Malavali if (ha->flags.isp82xx_no_md_cap) { 4144b6d0d9d5SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb054, 4145b6d0d9d5SGiridhar Malavali "Forced reset from application, " 4146b6d0d9d5SGiridhar Malavali "ignore minidump capture\n"); 4147b6d0d9d5SGiridhar Malavali ha->flags.isp82xx_no_md_cap = 0; 4148b6d0d9d5SGiridhar Malavali goto md_failed; 4149b6d0d9d5SGiridhar Malavali } 4150b6d0d9d5SGiridhar Malavali 415108de2844SGiridhar Malavali if (qla82xx_validate_template_chksum(vha)) { 415208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb039, 415308de2844SGiridhar Malavali "Template checksum validation error\n"); 415408de2844SGiridhar Malavali goto md_failed; 415508de2844SGiridhar Malavali } 415608de2844SGiridhar Malavali 415708de2844SGiridhar Malavali no_entry_hdr = tmplt_hdr->num_of_entries; 415808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03a, 415908de2844SGiridhar Malavali "No of entry headers in Template: 0x%x\n", no_entry_hdr); 416008de2844SGiridhar Malavali 416108de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03b, 416208de2844SGiridhar Malavali "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 416308de2844SGiridhar Malavali 416408de2844SGiridhar Malavali f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 416508de2844SGiridhar Malavali 416608de2844SGiridhar Malavali /* Validate whether required debug level is set */ 416708de2844SGiridhar Malavali if ((f_capture_mask & 0x3) != 0x3) { 416808de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03c, 416908de2844SGiridhar Malavali "Minimum required capture mask[0x%x] level not set\n", 417008de2844SGiridhar Malavali f_capture_mask); 417108de2844SGiridhar Malavali goto md_failed; 417208de2844SGiridhar Malavali } 417308de2844SGiridhar Malavali tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 417408de2844SGiridhar Malavali 417508de2844SGiridhar Malavali tmplt_hdr->driver_info[0] = vha->host_no; 417608de2844SGiridhar Malavali tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 417708de2844SGiridhar Malavali (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 417808de2844SGiridhar Malavali QLA_DRIVER_BETA_VER; 417908de2844SGiridhar Malavali 418008de2844SGiridhar Malavali total_data_size = ha->md_dump_size; 418108de2844SGiridhar Malavali 4182880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb03d, 418308de2844SGiridhar Malavali "Total minidump data_size 0x%x to be captured\n", total_data_size); 418408de2844SGiridhar Malavali 418508de2844SGiridhar Malavali /* Check whether template obtained is valid */ 418608de2844SGiridhar Malavali if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 418708de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb04e, 418808de2844SGiridhar Malavali "Bad template header entry type: 0x%x obtained\n", 418908de2844SGiridhar Malavali tmplt_hdr->entry_type); 419008de2844SGiridhar Malavali goto md_failed; 419108de2844SGiridhar Malavali } 419208de2844SGiridhar Malavali 4193c1c7178cSBart Van Assche entry_hdr = (qla82xx_md_entry_hdr_t *) 419408de2844SGiridhar Malavali (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 419508de2844SGiridhar Malavali 419608de2844SGiridhar Malavali /* Walk through the entry headers */ 419708de2844SGiridhar Malavali for (i = 0; i < no_entry_hdr; i++) { 419808de2844SGiridhar Malavali 419908de2844SGiridhar Malavali if (data_collected > total_data_size) { 420008de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb03e, 420108de2844SGiridhar Malavali "More MiniDump data collected: [0x%x]\n", 420208de2844SGiridhar Malavali data_collected); 420308de2844SGiridhar Malavali goto md_failed; 420408de2844SGiridhar Malavali } 420508de2844SGiridhar Malavali 420608de2844SGiridhar Malavali if (!(entry_hdr->d_ctrl.entry_capture_mask & 420708de2844SGiridhar Malavali ql2xmdcapmask)) { 420808de2844SGiridhar Malavali entry_hdr->d_ctrl.driver_flags |= 420908de2844SGiridhar Malavali QLA82XX_DBG_SKIPPED_FLAG; 421008de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb03f, 421108de2844SGiridhar Malavali "Skipping entry[%d]: " 421208de2844SGiridhar Malavali "ETYPE[0x%x]-ELEVEL[0x%x]\n", 421308de2844SGiridhar Malavali i, entry_hdr->entry_type, 421408de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 421508de2844SGiridhar Malavali goto skip_nxt_entry; 421608de2844SGiridhar Malavali } 421708de2844SGiridhar Malavali 421808de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb040, 421908de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 42200bf0efa1SColin Ian King "entry_type: 0x%x, capture_mask: 0x%x\n", 422108de2844SGiridhar Malavali __func__, i, data_ptr, entry_hdr, 422208de2844SGiridhar Malavali entry_hdr->entry_type, 422308de2844SGiridhar Malavali entry_hdr->d_ctrl.entry_capture_mask); 422408de2844SGiridhar Malavali 422508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb041, 422608de2844SGiridhar Malavali "Data collected: [0x%x], Dump size left:[0x%x]\n", 422708de2844SGiridhar Malavali data_collected, (ha->md_dump_size - data_collected)); 422808de2844SGiridhar Malavali 422908de2844SGiridhar Malavali /* Decode the entry type and take 423008de2844SGiridhar Malavali * required action to capture debug data */ 423108de2844SGiridhar Malavali switch (entry_hdr->entry_type) { 423208de2844SGiridhar Malavali case QLA82XX_RDEND: 423308de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 423408de2844SGiridhar Malavali break; 423508de2844SGiridhar Malavali case QLA82XX_CNTRL: 423608de2844SGiridhar Malavali rval = qla82xx_minidump_process_control(vha, 423708de2844SGiridhar Malavali entry_hdr, &data_ptr); 423808de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 423908de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 424008de2844SGiridhar Malavali goto md_failed; 424108de2844SGiridhar Malavali } 424208de2844SGiridhar Malavali break; 424308de2844SGiridhar Malavali case QLA82XX_RDCRB: 424408de2844SGiridhar Malavali qla82xx_minidump_process_rdcrb(vha, 424508de2844SGiridhar Malavali entry_hdr, &data_ptr); 424608de2844SGiridhar Malavali break; 424708de2844SGiridhar Malavali case QLA82XX_RDMEM: 424808de2844SGiridhar Malavali rval = qla82xx_minidump_process_rdmem(vha, 424908de2844SGiridhar Malavali entry_hdr, &data_ptr); 425008de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 425108de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 425208de2844SGiridhar Malavali goto md_failed; 425308de2844SGiridhar Malavali } 425408de2844SGiridhar Malavali break; 425508de2844SGiridhar Malavali case QLA82XX_BOARD: 425608de2844SGiridhar Malavali case QLA82XX_RDROM: 425708de2844SGiridhar Malavali qla82xx_minidump_process_rdrom(vha, 425808de2844SGiridhar Malavali entry_hdr, &data_ptr); 425908de2844SGiridhar Malavali break; 426008de2844SGiridhar Malavali case QLA82XX_L2DTG: 426108de2844SGiridhar Malavali case QLA82XX_L2ITG: 426208de2844SGiridhar Malavali case QLA82XX_L2DAT: 426308de2844SGiridhar Malavali case QLA82XX_L2INS: 426408de2844SGiridhar Malavali rval = qla82xx_minidump_process_l2tag(vha, 426508de2844SGiridhar Malavali entry_hdr, &data_ptr); 426608de2844SGiridhar Malavali if (rval != QLA_SUCCESS) { 426708de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 426808de2844SGiridhar Malavali goto md_failed; 426908de2844SGiridhar Malavali } 427008de2844SGiridhar Malavali break; 427108de2844SGiridhar Malavali case QLA82XX_L1DAT: 427208de2844SGiridhar Malavali case QLA82XX_L1INS: 427308de2844SGiridhar Malavali qla82xx_minidump_process_l1cache(vha, 427408de2844SGiridhar Malavali entry_hdr, &data_ptr); 427508de2844SGiridhar Malavali break; 427608de2844SGiridhar Malavali case QLA82XX_RDOCM: 427708de2844SGiridhar Malavali qla82xx_minidump_process_rdocm(vha, 427808de2844SGiridhar Malavali entry_hdr, &data_ptr); 427908de2844SGiridhar Malavali break; 428008de2844SGiridhar Malavali case QLA82XX_RDMUX: 428108de2844SGiridhar Malavali qla82xx_minidump_process_rdmux(vha, 428208de2844SGiridhar Malavali entry_hdr, &data_ptr); 428308de2844SGiridhar Malavali break; 428408de2844SGiridhar Malavali case QLA82XX_QUEUE: 428508de2844SGiridhar Malavali qla82xx_minidump_process_queue(vha, 428608de2844SGiridhar Malavali entry_hdr, &data_ptr); 428708de2844SGiridhar Malavali break; 428808de2844SGiridhar Malavali case QLA82XX_RDNOP: 428908de2844SGiridhar Malavali default: 429008de2844SGiridhar Malavali qla82xx_mark_entry_skipped(vha, entry_hdr, i); 429108de2844SGiridhar Malavali break; 429208de2844SGiridhar Malavali } 429308de2844SGiridhar Malavali 429408de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb042, 429508de2844SGiridhar Malavali "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 429608de2844SGiridhar Malavali 429708de2844SGiridhar Malavali data_collected = (uint8_t *)data_ptr - 429808de2844SGiridhar Malavali (uint8_t *)ha->md_dump; 429908de2844SGiridhar Malavali skip_nxt_entry: 4300c1c7178cSBart Van Assche entry_hdr = (qla82xx_md_entry_hdr_t *) 430108de2844SGiridhar Malavali (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 430208de2844SGiridhar Malavali } 430308de2844SGiridhar Malavali 430408de2844SGiridhar Malavali if (data_collected != total_data_size) { 4305880fdedbSArun Easi ql_dbg(ql_dbg_p3p, vha, 0xb043, 430608de2844SGiridhar Malavali "MiniDump data mismatch: Data collected: [0x%x]," 430708de2844SGiridhar Malavali "total_data_size:[0x%x]\n", 430808de2844SGiridhar Malavali data_collected, total_data_size); 430908de2844SGiridhar Malavali goto md_failed; 431008de2844SGiridhar Malavali } 431108de2844SGiridhar Malavali 431208de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb044, 431308de2844SGiridhar Malavali "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 431408de2844SGiridhar Malavali vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4315dbe6f492SJason Yan ha->fw_dumped = true; 431608de2844SGiridhar Malavali qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 431708de2844SGiridhar Malavali 431808de2844SGiridhar Malavali md_failed: 431908de2844SGiridhar Malavali return rval; 432008de2844SGiridhar Malavali } 432108de2844SGiridhar Malavali 432208de2844SGiridhar Malavali int 432308de2844SGiridhar Malavali qla82xx_md_alloc(scsi_qla_host_t *vha) 432408de2844SGiridhar Malavali { 432508de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 432608de2844SGiridhar Malavali int i, k; 432708de2844SGiridhar Malavali struct qla82xx_md_template_hdr *tmplt_hdr; 432808de2844SGiridhar Malavali 432908de2844SGiridhar Malavali tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 433008de2844SGiridhar Malavali 433108de2844SGiridhar Malavali if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 433208de2844SGiridhar Malavali ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 433308de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb045, 433408de2844SGiridhar Malavali "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 433508de2844SGiridhar Malavali ql2xmdcapmask); 433608de2844SGiridhar Malavali } 433708de2844SGiridhar Malavali 433808de2844SGiridhar Malavali for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 433908de2844SGiridhar Malavali if (i & ql2xmdcapmask) 434008de2844SGiridhar Malavali ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 434108de2844SGiridhar Malavali } 434208de2844SGiridhar Malavali 434308de2844SGiridhar Malavali if (ha->md_dump) { 434408de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb046, 434508de2844SGiridhar Malavali "Firmware dump previously allocated.\n"); 434608de2844SGiridhar Malavali return 1; 434708de2844SGiridhar Malavali } 434808de2844SGiridhar Malavali 434908de2844SGiridhar Malavali ha->md_dump = vmalloc(ha->md_dump_size); 435008de2844SGiridhar Malavali if (ha->md_dump == NULL) { 435108de2844SGiridhar Malavali ql_log(ql_log_warn, vha, 0xb047, 435208de2844SGiridhar Malavali "Unable to allocate memory for Minidump size " 435308de2844SGiridhar Malavali "(0x%x).\n", ha->md_dump_size); 435408de2844SGiridhar Malavali return 1; 435508de2844SGiridhar Malavali } 435608de2844SGiridhar Malavali return 0; 435708de2844SGiridhar Malavali } 435808de2844SGiridhar Malavali 435908de2844SGiridhar Malavali void 436008de2844SGiridhar Malavali qla82xx_md_free(scsi_qla_host_t *vha) 436108de2844SGiridhar Malavali { 436208de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 436308de2844SGiridhar Malavali 436408de2844SGiridhar Malavali /* Release the template header allocated */ 436508de2844SGiridhar Malavali if (ha->md_tmplt_hdr) { 436608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb048, 436708de2844SGiridhar Malavali "Free MiniDump template: %p, size (%d KB)\n", 436808de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_template_size / 1024); 436908de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 437008de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4371fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 437208de2844SGiridhar Malavali } 437308de2844SGiridhar Malavali 437408de2844SGiridhar Malavali /* Release the template data buffer allocated */ 437508de2844SGiridhar Malavali if (ha->md_dump) { 437608de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb049, 437708de2844SGiridhar Malavali "Free MiniDump memory: %p, size (%d KB)\n", 437808de2844SGiridhar Malavali ha->md_dump, ha->md_dump_size / 1024); 437908de2844SGiridhar Malavali vfree(ha->md_dump); 438008de2844SGiridhar Malavali ha->md_dump_size = 0; 4381fa492630SSaurav Kashyap ha->md_dump = NULL; 438208de2844SGiridhar Malavali } 438308de2844SGiridhar Malavali } 438408de2844SGiridhar Malavali 438508de2844SGiridhar Malavali void 438608de2844SGiridhar Malavali qla82xx_md_prep(scsi_qla_host_t *vha) 438708de2844SGiridhar Malavali { 438808de2844SGiridhar Malavali struct qla_hw_data *ha = vha->hw; 438908de2844SGiridhar Malavali int rval; 439008de2844SGiridhar Malavali 439108de2844SGiridhar Malavali /* Get Minidump template size */ 439208de2844SGiridhar Malavali rval = qla82xx_md_get_template_size(vha); 439308de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 439408de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04a, 439508de2844SGiridhar Malavali "MiniDump Template size obtained (%d KB)\n", 439608de2844SGiridhar Malavali ha->md_template_size / 1024); 439708de2844SGiridhar Malavali 439808de2844SGiridhar Malavali /* Get Minidump template */ 43997ec0effdSAtul Deshmukh if (IS_QLA8044(ha)) 44007ec0effdSAtul Deshmukh rval = qla8044_md_get_template(vha); 44017ec0effdSAtul Deshmukh else 440208de2844SGiridhar Malavali rval = qla82xx_md_get_template(vha); 44037ec0effdSAtul Deshmukh 440408de2844SGiridhar Malavali if (rval == QLA_SUCCESS) { 440508de2844SGiridhar Malavali ql_dbg(ql_dbg_p3p, vha, 0xb04b, 440608de2844SGiridhar Malavali "MiniDump Template obtained\n"); 440708de2844SGiridhar Malavali 440808de2844SGiridhar Malavali /* Allocate memory for minidump */ 440908de2844SGiridhar Malavali rval = qla82xx_md_alloc(vha); 441008de2844SGiridhar Malavali if (rval == QLA_SUCCESS) 441108de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04c, 441208de2844SGiridhar Malavali "MiniDump memory allocated (%d KB)\n", 441308de2844SGiridhar Malavali ha->md_dump_size / 1024); 441408de2844SGiridhar Malavali else { 441508de2844SGiridhar Malavali ql_log(ql_log_info, vha, 0xb04d, 441608de2844SGiridhar Malavali "Free MiniDump template: %p, size: (%d KB)\n", 441708de2844SGiridhar Malavali ha->md_tmplt_hdr, 441808de2844SGiridhar Malavali ha->md_template_size / 1024); 441908de2844SGiridhar Malavali dma_free_coherent(&ha->pdev->dev, 442008de2844SGiridhar Malavali ha->md_template_size, 442108de2844SGiridhar Malavali ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4422fa492630SSaurav Kashyap ha->md_tmplt_hdr = NULL; 442308de2844SGiridhar Malavali } 442408de2844SGiridhar Malavali 442508de2844SGiridhar Malavali } 442608de2844SGiridhar Malavali } 442708de2844SGiridhar Malavali } 4428999916dcSSaurav Kashyap 4429999916dcSSaurav Kashyap int 4430999916dcSSaurav Kashyap qla82xx_beacon_on(struct scsi_qla_host *vha) 4431999916dcSSaurav Kashyap { 4432999916dcSSaurav Kashyap 4433999916dcSSaurav Kashyap int rval; 4434999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4435bd432bb5SBart Van Assche 4436999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4437999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 1); 4438999916dcSSaurav Kashyap 4439999916dcSSaurav Kashyap if (rval) { 4440999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb050, 4441999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4442999916dcSSaurav Kashyap goto exit; 4443999916dcSSaurav Kashyap } 4444999916dcSSaurav Kashyap ha->beacon_blink_led = 1; 4445999916dcSSaurav Kashyap exit: 4446999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4447999916dcSSaurav Kashyap return rval; 4448999916dcSSaurav Kashyap } 4449999916dcSSaurav Kashyap 4450999916dcSSaurav Kashyap int 4451999916dcSSaurav Kashyap qla82xx_beacon_off(struct scsi_qla_host *vha) 4452999916dcSSaurav Kashyap { 4453999916dcSSaurav Kashyap 4454999916dcSSaurav Kashyap int rval; 4455999916dcSSaurav Kashyap struct qla_hw_data *ha = vha->hw; 4456bd432bb5SBart Van Assche 4457999916dcSSaurav Kashyap qla82xx_idc_lock(ha); 4458999916dcSSaurav Kashyap rval = qla82xx_mbx_beacon_ctl(vha, 0); 4459999916dcSSaurav Kashyap 4460999916dcSSaurav Kashyap if (rval) { 4461999916dcSSaurav Kashyap ql_log(ql_log_warn, vha, 0xb051, 4462999916dcSSaurav Kashyap "mbx set led config failed in %s\n", __func__); 4463999916dcSSaurav Kashyap goto exit; 4464999916dcSSaurav Kashyap } 4465999916dcSSaurav Kashyap ha->beacon_blink_led = 0; 4466999916dcSSaurav Kashyap exit: 4467999916dcSSaurav Kashyap qla82xx_idc_unlock(ha); 4468999916dcSSaurav Kashyap return rval; 4469999916dcSSaurav Kashyap } 4470a1b23c5aSChad Dupuis 4471a1b23c5aSChad Dupuis void 44728ae17876SBart Van Assche qla82xx_fw_dump(scsi_qla_host_t *vha) 4473a1b23c5aSChad Dupuis { 4474a1b23c5aSChad Dupuis struct qla_hw_data *ha = vha->hw; 4475a1b23c5aSChad Dupuis 4476a1b23c5aSChad Dupuis if (!ha->allow_cna_fw_dump) 4477a1b23c5aSChad Dupuis return; 4478a1b23c5aSChad Dupuis 4479a1b23c5aSChad Dupuis scsi_block_requests(vha->host); 4480a1b23c5aSChad Dupuis ha->flags.isp82xx_no_md_cap = 1; 4481a1b23c5aSChad Dupuis qla82xx_idc_lock(ha); 4482a1b23c5aSChad Dupuis qla82xx_set_reset_owner(vha); 4483a1b23c5aSChad Dupuis qla82xx_idc_unlock(ha); 4484a1b23c5aSChad Dupuis qla2x00_wait_for_chip_reset(vha); 4485a1b23c5aSChad Dupuis scsi_unblock_requests(vha->host); 4486a1b23c5aSChad Dupuis } 4487