1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include <linux/delay.h> 9 #include <linux/ktime.h> 10 #include <linux/pci.h> 11 #include <linux/ratelimit.h> 12 #include <linux/vmalloc.h> 13 #include <linux/bsg-lib.h> 14 #include <scsi/scsi_tcq.h> 15 #include <linux/utsname.h> 16 17 18 /* QLAFX00 specific Mailbox implementation functions */ 19 20 /* 21 * qlafx00_mailbox_command 22 * Issue mailbox command and waits for completion. 23 * 24 * Input: 25 * ha = adapter block pointer. 26 * mcp = driver internal mbx struct pointer. 27 * 28 * Output: 29 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 30 * 31 * Returns: 32 * 0 : QLA_SUCCESS = cmd performed success 33 * 1 : QLA_FUNCTION_FAILED (error encountered) 34 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 35 * 36 * Context: 37 * Kernel context. 38 */ 39 static int 40 qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp) 41 42 { 43 int rval; 44 unsigned long flags = 0; 45 device_reg_t *reg; 46 uint8_t abort_active; 47 uint8_t io_lock_on; 48 uint16_t command = 0; 49 uint32_t *iptr; 50 uint32_t __iomem *optr; 51 uint32_t cnt; 52 uint32_t mboxes; 53 unsigned long wait_time; 54 struct qla_hw_data *ha = vha->hw; 55 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 56 57 if (ha->pdev->error_state > pci_channel_io_frozen) { 58 ql_log(ql_log_warn, vha, 0x115c, 59 "error_state is greater than pci_channel_io_frozen, " 60 "exiting.\n"); 61 return QLA_FUNCTION_TIMEOUT; 62 } 63 64 if (vha->device_flags & DFLG_DEV_FAILED) { 65 ql_log(ql_log_warn, vha, 0x115f, 66 "Device in failed state, exiting.\n"); 67 return QLA_FUNCTION_TIMEOUT; 68 } 69 70 reg = ha->iobase; 71 io_lock_on = base_vha->flags.init_done; 72 73 rval = QLA_SUCCESS; 74 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 75 76 if (ha->flags.pci_channel_io_perm_failure) { 77 ql_log(ql_log_warn, vha, 0x1175, 78 "Perm failure on EEH timeout MBX, exiting.\n"); 79 return QLA_FUNCTION_TIMEOUT; 80 } 81 82 if (ha->flags.isp82xx_fw_hung) { 83 /* Setting Link-Down error */ 84 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 85 ql_log(ql_log_warn, vha, 0x1176, 86 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 87 rval = QLA_FUNCTION_FAILED; 88 goto premature_exit; 89 } 90 91 /* 92 * Wait for active mailbox commands to finish by waiting at most tov 93 * seconds. This is to serialize actual issuing of mailbox cmds during 94 * non ISP abort time. 95 */ 96 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 97 /* Timeout occurred. Return error. */ 98 ql_log(ql_log_warn, vha, 0x1177, 99 "Cmd access timeout, cmd=0x%x, Exiting.\n", 100 mcp->mb[0]); 101 return QLA_FUNCTION_TIMEOUT; 102 } 103 104 ha->flags.mbox_busy = 1; 105 /* Save mailbox command for debug */ 106 ha->mcp32 = mcp; 107 108 ql_dbg(ql_dbg_mbx, vha, 0x1178, 109 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 110 111 spin_lock_irqsave(&ha->hardware_lock, flags); 112 113 /* Load mailbox registers. */ 114 optr = (uint32_t __iomem *)®->ispfx00.mailbox0; 115 116 iptr = mcp->mb; 117 command = mcp->mb[0]; 118 mboxes = mcp->out_mb; 119 120 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 121 if (mboxes & BIT_0) 122 WRT_REG_DWORD(optr, *iptr); 123 124 mboxes >>= 1; 125 optr++; 126 iptr++; 127 } 128 129 /* Issue set host interrupt command to send cmd out. */ 130 ha->flags.mbox_int = 0; 131 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 132 133 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172, 134 (uint8_t *)mcp->mb, 16); 135 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173, 136 ((uint8_t *)mcp->mb + 0x10), 16); 137 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174, 138 ((uint8_t *)mcp->mb + 0x20), 8); 139 140 /* Unlock mbx registers and wait for interrupt */ 141 ql_dbg(ql_dbg_mbx, vha, 0x1179, 142 "Going to unlock irq & waiting for interrupts. " 143 "jiffies=%lx.\n", jiffies); 144 145 /* Wait for mbx cmd completion until timeout */ 146 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 147 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 148 149 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code); 150 spin_unlock_irqrestore(&ha->hardware_lock, flags); 151 152 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); 153 } else { 154 ql_dbg(ql_dbg_mbx, vha, 0x112c, 155 "Cmd=%x Polling Mode.\n", command); 156 157 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code); 158 spin_unlock_irqrestore(&ha->hardware_lock, flags); 159 160 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 161 while (!ha->flags.mbox_int) { 162 if (time_after(jiffies, wait_time)) 163 break; 164 165 /* Check for pending interrupts. */ 166 qla2x00_poll(ha->rsp_q_map[0]); 167 168 if (!ha->flags.mbox_int && 169 !(IS_QLA2200(ha) && 170 command == MBC_LOAD_RISC_RAM_EXTENDED)) 171 usleep_range(10000, 11000); 172 } /* while */ 173 ql_dbg(ql_dbg_mbx, vha, 0x112d, 174 "Waited %d sec.\n", 175 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 176 } 177 178 /* Check whether we timed out */ 179 if (ha->flags.mbox_int) { 180 uint32_t *iptr2; 181 182 ql_dbg(ql_dbg_mbx, vha, 0x112e, 183 "Cmd=%x completed.\n", command); 184 185 /* Got interrupt. Clear the flag. */ 186 ha->flags.mbox_int = 0; 187 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 188 189 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE) 190 rval = QLA_FUNCTION_FAILED; 191 192 /* Load return mailbox registers. */ 193 iptr2 = mcp->mb; 194 iptr = (uint32_t *)&ha->mailbox_out32[0]; 195 mboxes = mcp->in_mb; 196 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 197 if (mboxes & BIT_0) 198 *iptr2 = *iptr; 199 200 mboxes >>= 1; 201 iptr2++; 202 iptr++; 203 } 204 } else { 205 206 rval = QLA_FUNCTION_TIMEOUT; 207 } 208 209 ha->flags.mbox_busy = 0; 210 211 /* Clean up */ 212 ha->mcp32 = NULL; 213 214 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 215 ql_dbg(ql_dbg_mbx, vha, 0x113a, 216 "checking for additional resp interrupt.\n"); 217 218 /* polling mode for non isp_abort commands. */ 219 qla2x00_poll(ha->rsp_q_map[0]); 220 } 221 222 if (rval == QLA_FUNCTION_TIMEOUT && 223 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 224 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 225 ha->flags.eeh_busy) { 226 /* not in dpc. schedule it for dpc to take over. */ 227 ql_dbg(ql_dbg_mbx, vha, 0x115d, 228 "Timeout, schedule isp_abort_needed.\n"); 229 230 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 231 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 232 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 233 234 ql_log(ql_log_info, base_vha, 0x115e, 235 "Mailbox cmd timeout occurred, cmd=0x%x, " 236 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 237 "abort.\n", command, mcp->mb[0], 238 ha->flags.eeh_busy); 239 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 240 qla2xxx_wake_dpc(vha); 241 } 242 } else if (!abort_active) { 243 /* call abort directly since we are in the DPC thread */ 244 ql_dbg(ql_dbg_mbx, vha, 0x1160, 245 "Timeout, calling abort_isp.\n"); 246 247 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 248 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 249 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 250 251 ql_log(ql_log_info, base_vha, 0x1161, 252 "Mailbox cmd timeout occurred, cmd=0x%x, " 253 "mb[0]=0x%x. Scheduling ISP abort ", 254 command, mcp->mb[0]); 255 256 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 257 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 258 if (ha->isp_ops->abort_isp(vha)) { 259 /* Failed. retry later. */ 260 set_bit(ISP_ABORT_NEEDED, 261 &vha->dpc_flags); 262 } 263 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 264 ql_dbg(ql_dbg_mbx, vha, 0x1162, 265 "Finished abort_isp.\n"); 266 } 267 } 268 } 269 270 premature_exit: 271 /* Allow next mbx cmd to come in. */ 272 complete(&ha->mbx_cmd_comp); 273 274 if (rval) { 275 ql_log(ql_log_warn, base_vha, 0x1163, 276 "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 277 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 278 command); 279 } else { 280 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__); 281 } 282 283 return rval; 284 } 285 286 /* 287 * qlafx00_driver_shutdown 288 * Indicate a driver shutdown to firmware. 289 * 290 * Input: 291 * ha = adapter block pointer. 292 * 293 * Returns: 294 * local function return status code. 295 * 296 * Context: 297 * Kernel context. 298 */ 299 int 300 qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo) 301 { 302 int rval; 303 struct mbx_cmd_32 mc; 304 struct mbx_cmd_32 *mcp = &mc; 305 306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166, 307 "Entered %s.\n", __func__); 308 309 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN; 310 mcp->out_mb = MBX_0; 311 mcp->in_mb = MBX_0; 312 if (tmo) 313 mcp->tov = tmo; 314 else 315 mcp->tov = MBX_TOV_SECONDS; 316 mcp->flags = 0; 317 rval = qlafx00_mailbox_command(vha, mcp); 318 319 if (rval != QLA_SUCCESS) { 320 ql_dbg(ql_dbg_mbx, vha, 0x1167, 321 "Failed=%x.\n", rval); 322 } else { 323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168, 324 "Done %s.\n", __func__); 325 } 326 327 return rval; 328 } 329 330 /* 331 * qlafx00_get_firmware_state 332 * Get adapter firmware state. 333 * 334 * Input: 335 * ha = adapter block pointer. 336 * TARGET_QUEUE_LOCK must be released. 337 * ADAPTER_STATE_LOCK must be released. 338 * 339 * Returns: 340 * qla7xxx local function return status code. 341 * 342 * Context: 343 * Kernel context. 344 */ 345 static int 346 qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states) 347 { 348 int rval; 349 struct mbx_cmd_32 mc; 350 struct mbx_cmd_32 *mcp = &mc; 351 352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169, 353 "Entered %s.\n", __func__); 354 355 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 356 mcp->out_mb = MBX_0; 357 mcp->in_mb = MBX_1|MBX_0; 358 mcp->tov = MBX_TOV_SECONDS; 359 mcp->flags = 0; 360 rval = qlafx00_mailbox_command(vha, mcp); 361 362 /* Return firmware states. */ 363 states[0] = mcp->mb[1]; 364 365 if (rval != QLA_SUCCESS) { 366 ql_dbg(ql_dbg_mbx, vha, 0x116a, 367 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 368 } else { 369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b, 370 "Done %s.\n", __func__); 371 } 372 return rval; 373 } 374 375 /* 376 * qlafx00_init_firmware 377 * Initialize adapter firmware. 378 * 379 * Input: 380 * ha = adapter block pointer. 381 * dptr = Initialization control block pointer. 382 * size = size of initialization control block. 383 * TARGET_QUEUE_LOCK must be released. 384 * ADAPTER_STATE_LOCK must be released. 385 * 386 * Returns: 387 * qlafx00 local function return status code. 388 * 389 * Context: 390 * Kernel context. 391 */ 392 int 393 qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 394 { 395 int rval; 396 struct mbx_cmd_32 mc; 397 struct mbx_cmd_32 *mcp = &mc; 398 struct qla_hw_data *ha = vha->hw; 399 400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c, 401 "Entered %s.\n", __func__); 402 403 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 404 405 mcp->mb[1] = 0; 406 mcp->mb[2] = MSD(ha->init_cb_dma); 407 mcp->mb[3] = LSD(ha->init_cb_dma); 408 409 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 410 mcp->in_mb = MBX_0; 411 mcp->buf_size = size; 412 mcp->flags = MBX_DMA_OUT; 413 mcp->tov = MBX_TOV_SECONDS; 414 rval = qlafx00_mailbox_command(vha, mcp); 415 416 if (rval != QLA_SUCCESS) { 417 ql_dbg(ql_dbg_mbx, vha, 0x116d, 418 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 419 } else { 420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e, 421 "Done %s.\n", __func__); 422 } 423 return rval; 424 } 425 426 /* 427 * qlafx00_mbx_reg_test 428 */ 429 static int 430 qlafx00_mbx_reg_test(scsi_qla_host_t *vha) 431 { 432 int rval; 433 struct mbx_cmd_32 mc; 434 struct mbx_cmd_32 *mcp = &mc; 435 436 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f, 437 "Entered %s.\n", __func__); 438 439 440 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 441 mcp->mb[1] = 0xAAAA; 442 mcp->mb[2] = 0x5555; 443 mcp->mb[3] = 0xAA55; 444 mcp->mb[4] = 0x55AA; 445 mcp->mb[5] = 0xA5A5; 446 mcp->mb[6] = 0x5A5A; 447 mcp->mb[7] = 0x2525; 448 mcp->mb[8] = 0xBBBB; 449 mcp->mb[9] = 0x6666; 450 mcp->mb[10] = 0xBB66; 451 mcp->mb[11] = 0x66BB; 452 mcp->mb[12] = 0xB6B6; 453 mcp->mb[13] = 0x6B6B; 454 mcp->mb[14] = 0x3636; 455 mcp->mb[15] = 0xCCCC; 456 457 458 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 460 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 461 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 462 mcp->buf_size = 0; 463 mcp->flags = MBX_DMA_OUT; 464 mcp->tov = MBX_TOV_SECONDS; 465 rval = qlafx00_mailbox_command(vha, mcp); 466 if (rval == QLA_SUCCESS) { 467 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 || 468 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA) 469 rval = QLA_FUNCTION_FAILED; 470 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A || 471 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB) 472 rval = QLA_FUNCTION_FAILED; 473 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 || 474 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6) 475 rval = QLA_FUNCTION_FAILED; 476 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 || 477 mcp->mb[31] != 0xCCCC) 478 rval = QLA_FUNCTION_FAILED; 479 } 480 481 if (rval != QLA_SUCCESS) { 482 ql_dbg(ql_dbg_mbx, vha, 0x1170, 483 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 484 } else { 485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171, 486 "Done %s.\n", __func__); 487 } 488 return rval; 489 } 490 491 /** 492 * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers. 493 * @vha: HA context 494 * 495 * Returns 0 on success. 496 */ 497 int 498 qlafx00_pci_config(scsi_qla_host_t *vha) 499 { 500 uint16_t w; 501 struct qla_hw_data *ha = vha->hw; 502 503 pci_set_master(ha->pdev); 504 pci_try_set_mwi(ha->pdev); 505 506 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 507 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 508 w &= ~PCI_COMMAND_INTX_DISABLE; 509 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 510 511 /* PCIe -- adjust Maximum Read Request Size (2048). */ 512 if (pci_is_pcie(ha->pdev)) 513 pcie_set_readrq(ha->pdev, 2048); 514 515 ha->chip_revision = ha->pdev->revision; 516 517 return QLA_SUCCESS; 518 } 519 520 /** 521 * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC). 522 * @vha: HA context 523 * 524 */ 525 static inline void 526 qlafx00_soc_cpu_reset(scsi_qla_host_t *vha) 527 { 528 unsigned long flags = 0; 529 struct qla_hw_data *ha = vha->hw; 530 int i, core; 531 uint32_t cnt; 532 uint32_t reg_val; 533 534 spin_lock_irqsave(&ha->hardware_lock, flags); 535 536 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0); 537 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0); 538 539 /* stop the XOR DMA engines */ 540 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02); 541 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02); 542 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02); 543 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02); 544 545 /* stop the IDMA engines */ 546 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840); 547 reg_val &= ~(1<<12); 548 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val); 549 550 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844); 551 reg_val &= ~(1<<12); 552 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val); 553 554 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848); 555 reg_val &= ~(1<<12); 556 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val); 557 558 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C); 559 reg_val &= ~(1<<12); 560 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val); 561 562 for (i = 0; i < 100000; i++) { 563 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 && 564 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0) 565 break; 566 udelay(100); 567 } 568 569 /* Set all 4 cores in reset */ 570 for (i = 0; i < 4; i++) { 571 QLAFX00_SET_HBA_SOC_REG(ha, 572 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01)); 573 QLAFX00_SET_HBA_SOC_REG(ha, 574 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101)); 575 } 576 577 /* Reset all units in Fabric */ 578 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101)); 579 580 /* */ 581 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1); 582 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0); 583 584 /* Set all 4 core Memory Power Down Registers */ 585 for (i = 0; i < 5; i++) { 586 QLAFX00_SET_HBA_SOC_REG(ha, 587 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0)); 588 } 589 590 /* Reset all interrupt control registers */ 591 for (i = 0; i < 115; i++) { 592 QLAFX00_SET_HBA_SOC_REG(ha, 593 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0)); 594 } 595 596 /* Reset Timers control registers. per core */ 597 for (core = 0; core < 4; core++) 598 for (i = 0; i < 8; i++) 599 QLAFX00_SET_HBA_SOC_REG(ha, 600 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0)); 601 602 /* Reset per core IRQ ack register */ 603 for (core = 0; core < 4; core++) 604 QLAFX00_SET_HBA_SOC_REG(ha, 605 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF)); 606 607 /* Set Fabric control and config to defaults */ 608 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2)); 609 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3)); 610 611 /* Kick in Fabric units */ 612 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0)); 613 614 /* Kick in Core0 to start boot process */ 615 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00)); 616 617 spin_unlock_irqrestore(&ha->hardware_lock, flags); 618 619 /* Wait 10secs for soft-reset to complete. */ 620 for (cnt = 10; cnt; cnt--) { 621 msleep(1000); 622 barrier(); 623 } 624 } 625 626 /** 627 * qlafx00_soft_reset() - Soft Reset ISPFx00. 628 * @vha: HA context 629 * 630 * Returns 0 on success. 631 */ 632 int 633 qlafx00_soft_reset(scsi_qla_host_t *vha) 634 { 635 struct qla_hw_data *ha = vha->hw; 636 int rval = QLA_FUNCTION_FAILED; 637 638 if (unlikely(pci_channel_offline(ha->pdev) && 639 ha->flags.pci_channel_io_perm_failure)) 640 return rval; 641 642 ha->isp_ops->disable_intrs(ha); 643 qlafx00_soc_cpu_reset(vha); 644 645 return QLA_SUCCESS; 646 } 647 648 /** 649 * qlafx00_chip_diag() - Test ISPFx00 for proper operation. 650 * @vha: HA context 651 * 652 * Returns 0 on success. 653 */ 654 int 655 qlafx00_chip_diag(scsi_qla_host_t *vha) 656 { 657 int rval = 0; 658 struct qla_hw_data *ha = vha->hw; 659 struct req_que *req = ha->req_q_map[0]; 660 661 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 662 663 rval = qlafx00_mbx_reg_test(vha); 664 if (rval) { 665 ql_log(ql_log_warn, vha, 0x1165, 666 "Failed mailbox send register test\n"); 667 } else { 668 /* Flag a successful rval */ 669 rval = QLA_SUCCESS; 670 } 671 return rval; 672 } 673 674 void 675 qlafx00_config_rings(struct scsi_qla_host *vha) 676 { 677 struct qla_hw_data *ha = vha->hw; 678 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; 679 680 WRT_REG_DWORD(®->req_q_in, 0); 681 WRT_REG_DWORD(®->req_q_out, 0); 682 683 WRT_REG_DWORD(®->rsp_q_in, 0); 684 WRT_REG_DWORD(®->rsp_q_out, 0); 685 686 /* PCI posting */ 687 RD_REG_DWORD(®->rsp_q_out); 688 } 689 690 char * 691 qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str) 692 { 693 struct qla_hw_data *ha = vha->hw; 694 695 if (pci_is_pcie(ha->pdev)) { 696 strcpy(str, "PCIe iSA"); 697 return str; 698 } 699 return str; 700 } 701 702 char * 703 qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 704 { 705 struct qla_hw_data *ha = vha->hw; 706 707 snprintf(str, size, "%s", ha->mr.fw_version); 708 return str; 709 } 710 711 void 712 qlafx00_enable_intrs(struct qla_hw_data *ha) 713 { 714 unsigned long flags = 0; 715 716 spin_lock_irqsave(&ha->hardware_lock, flags); 717 ha->interrupts_on = 1; 718 QLAFX00_ENABLE_ICNTRL_REG(ha); 719 spin_unlock_irqrestore(&ha->hardware_lock, flags); 720 } 721 722 void 723 qlafx00_disable_intrs(struct qla_hw_data *ha) 724 { 725 unsigned long flags = 0; 726 727 spin_lock_irqsave(&ha->hardware_lock, flags); 728 ha->interrupts_on = 0; 729 QLAFX00_DISABLE_ICNTRL_REG(ha); 730 spin_unlock_irqrestore(&ha->hardware_lock, flags); 731 } 732 733 int 734 qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag) 735 { 736 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 737 } 738 739 int 740 qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag) 741 { 742 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 743 } 744 745 int 746 qlafx00_loop_reset(scsi_qla_host_t *vha) 747 { 748 int ret; 749 struct fc_port *fcport; 750 struct qla_hw_data *ha = vha->hw; 751 752 if (ql2xtargetreset) { 753 list_for_each_entry(fcport, &vha->vp_fcports, list) { 754 if (fcport->port_type != FCT_TARGET) 755 continue; 756 757 ret = ha->isp_ops->target_reset(fcport, 0, 0); 758 if (ret != QLA_SUCCESS) { 759 ql_dbg(ql_dbg_taskm, vha, 0x803d, 760 "Bus Reset failed: Reset=%d " 761 "d_id=%x.\n", ret, fcport->d_id.b24); 762 } 763 } 764 } 765 return QLA_SUCCESS; 766 } 767 768 int 769 qlafx00_iospace_config(struct qla_hw_data *ha) 770 { 771 if (pci_request_selected_regions(ha->pdev, ha->bars, 772 QLA2XXX_DRIVER_NAME)) { 773 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e, 774 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 775 pci_name(ha->pdev)); 776 goto iospace_error_exit; 777 } 778 779 /* Use MMIO operations for all accesses. */ 780 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 781 ql_log_pci(ql_log_warn, ha->pdev, 0x014f, 782 "Invalid pci I/O region size (%s).\n", 783 pci_name(ha->pdev)); 784 goto iospace_error_exit; 785 } 786 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) { 787 ql_log_pci(ql_log_warn, ha->pdev, 0x0127, 788 "Invalid PCI mem BAR0 region size (%s), aborting\n", 789 pci_name(ha->pdev)); 790 goto iospace_error_exit; 791 } 792 793 ha->cregbase = 794 ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00); 795 if (!ha->cregbase) { 796 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128, 797 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev)); 798 goto iospace_error_exit; 799 } 800 801 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) { 802 ql_log_pci(ql_log_warn, ha->pdev, 0x0129, 803 "region #2 not an MMIO resource (%s), aborting\n", 804 pci_name(ha->pdev)); 805 goto iospace_error_exit; 806 } 807 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) { 808 ql_log_pci(ql_log_warn, ha->pdev, 0x012a, 809 "Invalid PCI mem BAR2 region size (%s), aborting\n", 810 pci_name(ha->pdev)); 811 goto iospace_error_exit; 812 } 813 814 ha->iobase = 815 ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00); 816 if (!ha->iobase) { 817 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b, 818 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev)); 819 goto iospace_error_exit; 820 } 821 822 /* Determine queue resources */ 823 ha->max_req_queues = ha->max_rsp_queues = 1; 824 825 ql_log_pci(ql_log_info, ha->pdev, 0x012c, 826 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n", 827 ha->bars, ha->cregbase, ha->iobase); 828 829 return 0; 830 831 iospace_error_exit: 832 return -ENOMEM; 833 } 834 835 static void 836 qlafx00_save_queue_ptrs(struct scsi_qla_host *vha) 837 { 838 struct qla_hw_data *ha = vha->hw; 839 struct req_que *req = ha->req_q_map[0]; 840 struct rsp_que *rsp = ha->rsp_q_map[0]; 841 842 req->length_fx00 = req->length; 843 req->ring_fx00 = req->ring; 844 req->dma_fx00 = req->dma; 845 846 rsp->length_fx00 = rsp->length; 847 rsp->ring_fx00 = rsp->ring; 848 rsp->dma_fx00 = rsp->dma; 849 850 ql_dbg(ql_dbg_init, vha, 0x012d, 851 "req: %p, ring_fx00: %p, length_fx00: 0x%x," 852 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00, 853 req->length_fx00, (u64)req->dma_fx00); 854 855 ql_dbg(ql_dbg_init, vha, 0x012e, 856 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x," 857 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00, 858 rsp->length_fx00, (u64)rsp->dma_fx00); 859 } 860 861 static int 862 qlafx00_config_queues(struct scsi_qla_host *vha) 863 { 864 struct qla_hw_data *ha = vha->hw; 865 struct req_que *req = ha->req_q_map[0]; 866 struct rsp_que *rsp = ha->rsp_q_map[0]; 867 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2); 868 869 req->length = ha->req_que_len; 870 req->ring = (void __force *)ha->iobase + ha->req_que_off; 871 req->dma = bar2_hdl + ha->req_que_off; 872 if ((!req->ring) || (req->length == 0)) { 873 ql_log_pci(ql_log_info, ha->pdev, 0x012f, 874 "Unable to allocate memory for req_ring\n"); 875 return QLA_FUNCTION_FAILED; 876 } 877 878 ql_dbg(ql_dbg_init, vha, 0x0130, 879 "req: %p req_ring pointer %p req len 0x%x " 880 "req off 0x%x\n, req->dma: 0x%llx", 881 req, req->ring, req->length, 882 ha->req_que_off, (u64)req->dma); 883 884 rsp->length = ha->rsp_que_len; 885 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off; 886 rsp->dma = bar2_hdl + ha->rsp_que_off; 887 if ((!rsp->ring) || (rsp->length == 0)) { 888 ql_log_pci(ql_log_info, ha->pdev, 0x0131, 889 "Unable to allocate memory for rsp_ring\n"); 890 return QLA_FUNCTION_FAILED; 891 } 892 893 ql_dbg(ql_dbg_init, vha, 0x0132, 894 "rsp: %p rsp_ring pointer %p rsp len 0x%x " 895 "rsp off 0x%x, rsp->dma: 0x%llx\n", 896 rsp, rsp->ring, rsp->length, 897 ha->rsp_que_off, (u64)rsp->dma); 898 899 return QLA_SUCCESS; 900 } 901 902 static int 903 qlafx00_init_fw_ready(scsi_qla_host_t *vha) 904 { 905 int rval = 0; 906 unsigned long wtime; 907 uint16_t wait_time; /* Wait time */ 908 struct qla_hw_data *ha = vha->hw; 909 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; 910 uint32_t aenmbx, aenmbx7 = 0; 911 uint32_t pseudo_aen; 912 uint32_t state[5]; 913 bool done = false; 914 915 /* 30 seconds wait - Adjust if required */ 916 wait_time = 30; 917 918 pseudo_aen = RD_REG_DWORD(®->pseudoaen); 919 if (pseudo_aen == 1) { 920 aenmbx7 = RD_REG_DWORD(®->initval7); 921 ha->mbx_intr_code = MSW(aenmbx7); 922 ha->rqstq_intr_code = LSW(aenmbx7); 923 rval = qlafx00_driver_shutdown(vha, 10); 924 if (rval != QLA_SUCCESS) 925 qlafx00_soft_reset(vha); 926 } 927 928 /* wait time before firmware ready */ 929 wtime = jiffies + (wait_time * HZ); 930 do { 931 aenmbx = RD_REG_DWORD(®->aenmailbox0); 932 barrier(); 933 ql_dbg(ql_dbg_mbx, vha, 0x0133, 934 "aenmbx: 0x%x\n", aenmbx); 935 936 switch (aenmbx) { 937 case MBA_FW_NOT_STARTED: 938 case MBA_FW_STARTING: 939 break; 940 941 case MBA_SYSTEM_ERR: 942 case MBA_REQ_TRANSFER_ERR: 943 case MBA_RSP_TRANSFER_ERR: 944 case MBA_FW_INIT_FAILURE: 945 qlafx00_soft_reset(vha); 946 break; 947 948 case MBA_FW_RESTART_CMPLT: 949 /* Set the mbx and rqstq intr code */ 950 aenmbx7 = RD_REG_DWORD(®->aenmailbox7); 951 ha->mbx_intr_code = MSW(aenmbx7); 952 ha->rqstq_intr_code = LSW(aenmbx7); 953 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); 954 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); 955 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); 956 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); 957 WRT_REG_DWORD(®->aenmailbox0, 0); 958 RD_REG_DWORD_RELAXED(®->aenmailbox0); 959 ql_dbg(ql_dbg_init, vha, 0x0134, 960 "f/w returned mbx_intr_code: 0x%x, " 961 "rqstq_intr_code: 0x%x\n", 962 ha->mbx_intr_code, ha->rqstq_intr_code); 963 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); 964 rval = QLA_SUCCESS; 965 done = true; 966 break; 967 968 default: 969 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS) 970 break; 971 972 /* If fw is apparently not ready. In order to continue, 973 * we might need to issue Mbox cmd, but the problem is 974 * that the DoorBell vector values that come with the 975 * 8060 AEN are most likely gone by now (and thus no 976 * bell would be rung on the fw side when mbox cmd is 977 * issued). We have to therefore grab the 8060 AEN 978 * shadow regs (filled in by FW when the last 8060 979 * AEN was being posted). 980 * Do the following to determine what is needed in 981 * order to get the FW ready: 982 * 1. reload the 8060 AEN values from the shadow regs 983 * 2. clear int status to get rid of possible pending 984 * interrupts 985 * 3. issue Get FW State Mbox cmd to determine fw state 986 * Set the mbx and rqstq intr code from Shadow Regs 987 */ 988 aenmbx7 = RD_REG_DWORD(®->initval7); 989 ha->mbx_intr_code = MSW(aenmbx7); 990 ha->rqstq_intr_code = LSW(aenmbx7); 991 ha->req_que_off = RD_REG_DWORD(®->initval1); 992 ha->rsp_que_off = RD_REG_DWORD(®->initval3); 993 ha->req_que_len = RD_REG_DWORD(®->initval5); 994 ha->rsp_que_len = RD_REG_DWORD(®->initval6); 995 ql_dbg(ql_dbg_init, vha, 0x0135, 996 "f/w returned mbx_intr_code: 0x%x, " 997 "rqstq_intr_code: 0x%x\n", 998 ha->mbx_intr_code, ha->rqstq_intr_code); 999 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); 1000 1001 /* Get the FW state */ 1002 rval = qlafx00_get_firmware_state(vha, state); 1003 if (rval != QLA_SUCCESS) { 1004 /* Retry if timer has not expired */ 1005 break; 1006 } 1007 1008 if (state[0] == FSTATE_FX00_CONFIG_WAIT) { 1009 /* Firmware is waiting to be 1010 * initialized by driver 1011 */ 1012 rval = QLA_SUCCESS; 1013 done = true; 1014 break; 1015 } 1016 1017 /* Issue driver shutdown and wait until f/w recovers. 1018 * Driver should continue to poll until 8060 AEN is 1019 * received indicating firmware recovery. 1020 */ 1021 ql_dbg(ql_dbg_init, vha, 0x0136, 1022 "Sending Driver shutdown fw_state 0x%x\n", 1023 state[0]); 1024 1025 rval = qlafx00_driver_shutdown(vha, 10); 1026 if (rval != QLA_SUCCESS) { 1027 rval = QLA_FUNCTION_FAILED; 1028 break; 1029 } 1030 msleep(500); 1031 1032 wtime = jiffies + (wait_time * HZ); 1033 break; 1034 } 1035 1036 if (!done) { 1037 if (time_after_eq(jiffies, wtime)) { 1038 ql_dbg(ql_dbg_init, vha, 0x0137, 1039 "Init f/w failed: aen[7]: 0x%x\n", 1040 RD_REG_DWORD(®->aenmailbox7)); 1041 rval = QLA_FUNCTION_FAILED; 1042 done = true; 1043 break; 1044 } 1045 /* Delay for a while */ 1046 msleep(500); 1047 } 1048 } while (!done); 1049 1050 if (rval) 1051 ql_dbg(ql_dbg_init, vha, 0x0138, 1052 "%s **** FAILED ****.\n", __func__); 1053 else 1054 ql_dbg(ql_dbg_init, vha, 0x0139, 1055 "%s **** SUCCESS ****.\n", __func__); 1056 1057 return rval; 1058 } 1059 1060 /* 1061 * qlafx00_fw_ready() - Waits for firmware ready. 1062 * @ha: HA context 1063 * 1064 * Returns 0 on success. 1065 */ 1066 int 1067 qlafx00_fw_ready(scsi_qla_host_t *vha) 1068 { 1069 int rval; 1070 unsigned long wtime; 1071 uint16_t wait_time; /* Wait time if loop is coming ready */ 1072 uint32_t state[5]; 1073 1074 rval = QLA_SUCCESS; 1075 1076 wait_time = 10; 1077 1078 /* wait time before firmware ready */ 1079 wtime = jiffies + (wait_time * HZ); 1080 1081 /* Wait for ISP to finish init */ 1082 if (!vha->flags.init_done) 1083 ql_dbg(ql_dbg_init, vha, 0x013a, 1084 "Waiting for init to complete...\n"); 1085 1086 do { 1087 rval = qlafx00_get_firmware_state(vha, state); 1088 1089 if (rval == QLA_SUCCESS) { 1090 if (state[0] == FSTATE_FX00_INITIALIZED) { 1091 ql_dbg(ql_dbg_init, vha, 0x013b, 1092 "fw_state=%x\n", state[0]); 1093 rval = QLA_SUCCESS; 1094 break; 1095 } 1096 } 1097 rval = QLA_FUNCTION_FAILED; 1098 1099 if (time_after_eq(jiffies, wtime)) 1100 break; 1101 1102 /* Delay for a while */ 1103 msleep(500); 1104 1105 ql_dbg(ql_dbg_init, vha, 0x013c, 1106 "fw_state=%x curr time=%lx.\n", state[0], jiffies); 1107 } while (1); 1108 1109 1110 if (rval) 1111 ql_dbg(ql_dbg_init, vha, 0x013d, 1112 "Firmware ready **** FAILED ****.\n"); 1113 else 1114 ql_dbg(ql_dbg_init, vha, 0x013e, 1115 "Firmware ready **** SUCCESS ****.\n"); 1116 1117 return rval; 1118 } 1119 1120 static int 1121 qlafx00_find_all_targets(scsi_qla_host_t *vha, 1122 struct list_head *new_fcports) 1123 { 1124 int rval; 1125 uint16_t tgt_id; 1126 fc_port_t *fcport, *new_fcport; 1127 int found; 1128 struct qla_hw_data *ha = vha->hw; 1129 1130 rval = QLA_SUCCESS; 1131 1132 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags)) 1133 return QLA_FUNCTION_FAILED; 1134 1135 if ((atomic_read(&vha->loop_down_timer) || 1136 STATE_TRANSITION(vha))) { 1137 atomic_set(&vha->loop_down_timer, 0); 1138 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1139 return QLA_FUNCTION_FAILED; 1140 } 1141 1142 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088, 1143 "Listing Target bit map...\n"); 1144 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089, 1145 ha->gid_list, 32); 1146 1147 /* Allocate temporary rmtport for any new rmtports discovered. */ 1148 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 1149 if (new_fcport == NULL) 1150 return QLA_MEMORY_ALLOC_FAILED; 1151 1152 for_each_set_bit(tgt_id, (void *)ha->gid_list, 1153 QLAFX00_TGT_NODE_LIST_SIZE) { 1154 1155 /* Send get target node info */ 1156 new_fcport->tgt_id = tgt_id; 1157 rval = qlafx00_fx_disc(vha, new_fcport, 1158 FXDISC_GET_TGT_NODE_INFO); 1159 if (rval != QLA_SUCCESS) { 1160 ql_log(ql_log_warn, vha, 0x208a, 1161 "Target info scan failed -- assuming zero-entry " 1162 "result...\n"); 1163 continue; 1164 } 1165 1166 /* Locate matching device in database. */ 1167 found = 0; 1168 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1169 if (memcmp(new_fcport->port_name, 1170 fcport->port_name, WWN_SIZE)) 1171 continue; 1172 1173 found++; 1174 1175 /* 1176 * If tgt_id is same and state FCS_ONLINE, nothing 1177 * changed. 1178 */ 1179 if (fcport->tgt_id == new_fcport->tgt_id && 1180 atomic_read(&fcport->state) == FCS_ONLINE) 1181 break; 1182 1183 /* 1184 * Tgt ID changed or device was marked to be updated. 1185 */ 1186 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b, 1187 "TGT-ID Change(%s): Present tgt id: " 1188 "0x%x state: 0x%x " 1189 "wwnn = %llx wwpn = %llx.\n", 1190 __func__, fcport->tgt_id, 1191 atomic_read(&fcport->state), 1192 (unsigned long long)wwn_to_u64(fcport->node_name), 1193 (unsigned long long)wwn_to_u64(fcport->port_name)); 1194 1195 ql_log(ql_log_info, vha, 0x208c, 1196 "TGT-ID Announce(%s): Discovered tgt " 1197 "id 0x%x wwnn = %llx " 1198 "wwpn = %llx.\n", __func__, new_fcport->tgt_id, 1199 (unsigned long long) 1200 wwn_to_u64(new_fcport->node_name), 1201 (unsigned long long) 1202 wwn_to_u64(new_fcport->port_name)); 1203 1204 if (atomic_read(&fcport->state) != FCS_ONLINE) { 1205 fcport->old_tgt_id = fcport->tgt_id; 1206 fcport->tgt_id = new_fcport->tgt_id; 1207 ql_log(ql_log_info, vha, 0x208d, 1208 "TGT-ID: New fcport Added: %p\n", fcport); 1209 qla2x00_update_fcport(vha, fcport); 1210 } else { 1211 ql_log(ql_log_info, vha, 0x208e, 1212 " Existing TGT-ID %x did not get " 1213 " offline event from firmware.\n", 1214 fcport->old_tgt_id); 1215 qla2x00_mark_device_lost(vha, fcport, 0, 0); 1216 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1217 kfree(new_fcport); 1218 return rval; 1219 } 1220 break; 1221 } 1222 1223 if (found) 1224 continue; 1225 1226 /* If device was not in our fcports list, then add it. */ 1227 list_add_tail(&new_fcport->list, new_fcports); 1228 1229 /* Allocate a new replacement fcport. */ 1230 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 1231 if (new_fcport == NULL) 1232 return QLA_MEMORY_ALLOC_FAILED; 1233 } 1234 1235 kfree(new_fcport); 1236 return rval; 1237 } 1238 1239 /* 1240 * qlafx00_configure_all_targets 1241 * Setup target devices with node ID's. 1242 * 1243 * Input: 1244 * ha = adapter block pointer. 1245 * 1246 * Returns: 1247 * 0 = success. 1248 * BIT_0 = error 1249 */ 1250 static int 1251 qlafx00_configure_all_targets(scsi_qla_host_t *vha) 1252 { 1253 int rval; 1254 fc_port_t *fcport, *rmptemp; 1255 LIST_HEAD(new_fcports); 1256 1257 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 1258 FXDISC_GET_TGT_NODE_LIST); 1259 if (rval != QLA_SUCCESS) { 1260 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1261 return rval; 1262 } 1263 1264 rval = qlafx00_find_all_targets(vha, &new_fcports); 1265 if (rval != QLA_SUCCESS) { 1266 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1267 return rval; 1268 } 1269 1270 /* 1271 * Delete all previous devices marked lost. 1272 */ 1273 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1274 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 1275 break; 1276 1277 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) { 1278 if (fcport->port_type != FCT_INITIATOR) 1279 qla2x00_mark_device_lost(vha, fcport, 0, 0); 1280 } 1281 } 1282 1283 /* 1284 * Add the new devices to our devices list. 1285 */ 1286 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) { 1287 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 1288 break; 1289 1290 qla2x00_update_fcport(vha, fcport); 1291 list_move_tail(&fcport->list, &vha->vp_fcports); 1292 ql_log(ql_log_info, vha, 0x208f, 1293 "Attach new target id 0x%x wwnn = %llx " 1294 "wwpn = %llx.\n", 1295 fcport->tgt_id, 1296 (unsigned long long)wwn_to_u64(fcport->node_name), 1297 (unsigned long long)wwn_to_u64(fcport->port_name)); 1298 } 1299 1300 /* Free all new device structures not processed. */ 1301 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) { 1302 list_del(&fcport->list); 1303 kfree(fcport); 1304 } 1305 1306 return rval; 1307 } 1308 1309 /* 1310 * qlafx00_configure_devices 1311 * Updates Fibre Channel Device Database with what is actually on loop. 1312 * 1313 * Input: 1314 * ha = adapter block pointer. 1315 * 1316 * Returns: 1317 * 0 = success. 1318 * 1 = error. 1319 * 2 = database was full and device was not configured. 1320 */ 1321 int 1322 qlafx00_configure_devices(scsi_qla_host_t *vha) 1323 { 1324 int rval; 1325 unsigned long flags; 1326 1327 rval = QLA_SUCCESS; 1328 1329 flags = vha->dpc_flags; 1330 1331 ql_dbg(ql_dbg_disc, vha, 0x2090, 1332 "Configure devices -- dpc flags =0x%lx\n", flags); 1333 1334 rval = qlafx00_configure_all_targets(vha); 1335 1336 if (rval == QLA_SUCCESS) { 1337 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 1338 rval = QLA_FUNCTION_FAILED; 1339 } else { 1340 atomic_set(&vha->loop_state, LOOP_READY); 1341 ql_log(ql_log_info, vha, 0x2091, 1342 "Device Ready\n"); 1343 } 1344 } 1345 1346 if (rval) { 1347 ql_dbg(ql_dbg_disc, vha, 0x2092, 1348 "%s *** FAILED ***.\n", __func__); 1349 } else { 1350 ql_dbg(ql_dbg_disc, vha, 0x2093, 1351 "%s: exiting normally.\n", __func__); 1352 } 1353 return rval; 1354 } 1355 1356 static void 1357 qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp) 1358 { 1359 struct qla_hw_data *ha = vha->hw; 1360 fc_port_t *fcport; 1361 1362 vha->flags.online = 0; 1363 ha->mr.fw_hbt_en = 0; 1364 1365 if (!critemp) { 1366 ha->flags.chip_reset_done = 0; 1367 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1368 vha->qla_stats.total_isp_aborts++; 1369 ql_log(ql_log_info, vha, 0x013f, 1370 "Performing ISP error recovery - ha = %p.\n", ha); 1371 ha->isp_ops->reset_chip(vha); 1372 } 1373 1374 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 1375 atomic_set(&vha->loop_state, LOOP_DOWN); 1376 atomic_set(&vha->loop_down_timer, 1377 QLAFX00_LOOP_DOWN_TIME); 1378 } else { 1379 if (!atomic_read(&vha->loop_down_timer)) 1380 atomic_set(&vha->loop_down_timer, 1381 QLAFX00_LOOP_DOWN_TIME); 1382 } 1383 1384 /* Clear all async request states across all VPs. */ 1385 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1386 fcport->flags = 0; 1387 if (atomic_read(&fcport->state) == FCS_ONLINE) 1388 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 1389 } 1390 1391 if (!ha->flags.eeh_busy) { 1392 if (critemp) { 1393 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 1394 } else { 1395 /* Requeue all commands in outstanding command list. */ 1396 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 1397 } 1398 } 1399 1400 qla2x00_free_irqs(vha); 1401 if (critemp) 1402 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags); 1403 else 1404 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); 1405 1406 /* Clear the Interrupts */ 1407 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); 1408 1409 ql_log(ql_log_info, vha, 0x0140, 1410 "%s Done done - ha=%p.\n", __func__, ha); 1411 } 1412 1413 /** 1414 * qlafx00_init_response_q_entries() - Initializes response queue entries. 1415 * @rsp: response queue 1416 * 1417 * Beginning of request ring has initialization control block already built 1418 * by nvram config routine. 1419 * 1420 * Returns 0 on success. 1421 */ 1422 void 1423 qlafx00_init_response_q_entries(struct rsp_que *rsp) 1424 { 1425 uint16_t cnt; 1426 response_t *pkt; 1427 1428 rsp->ring_ptr = rsp->ring; 1429 rsp->ring_index = 0; 1430 rsp->status_srb = NULL; 1431 pkt = rsp->ring_ptr; 1432 for (cnt = 0; cnt < rsp->length; cnt++) { 1433 pkt->signature = RESPONSE_PROCESSED; 1434 WRT_REG_DWORD((void __force __iomem *)&pkt->signature, 1435 RESPONSE_PROCESSED); 1436 pkt++; 1437 } 1438 } 1439 1440 int 1441 qlafx00_rescan_isp(scsi_qla_host_t *vha) 1442 { 1443 uint32_t status = QLA_FUNCTION_FAILED; 1444 struct qla_hw_data *ha = vha->hw; 1445 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; 1446 uint32_t aenmbx7; 1447 1448 qla2x00_request_irqs(ha, ha->rsp_q_map[0]); 1449 1450 aenmbx7 = RD_REG_DWORD(®->aenmailbox7); 1451 ha->mbx_intr_code = MSW(aenmbx7); 1452 ha->rqstq_intr_code = LSW(aenmbx7); 1453 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); 1454 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); 1455 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); 1456 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); 1457 1458 ql_dbg(ql_dbg_disc, vha, 0x2094, 1459 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x " 1460 " Req que offset 0x%x Rsp que offset 0x%x\n", 1461 ha->mbx_intr_code, ha->rqstq_intr_code, 1462 ha->req_que_off, ha->rsp_que_len); 1463 1464 /* Clear the Interrupts */ 1465 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); 1466 1467 status = qla2x00_init_rings(vha); 1468 if (!status) { 1469 vha->flags.online = 1; 1470 1471 /* if no cable then assume it's good */ 1472 if ((vha->device_flags & DFLG_NO_CABLE)) 1473 status = 0; 1474 /* Register system information */ 1475 if (qlafx00_fx_disc(vha, 1476 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO)) 1477 ql_dbg(ql_dbg_disc, vha, 0x2095, 1478 "failed to register host info\n"); 1479 } 1480 scsi_unblock_requests(vha->host); 1481 return status; 1482 } 1483 1484 void 1485 qlafx00_timer_routine(scsi_qla_host_t *vha) 1486 { 1487 struct qla_hw_data *ha = vha->hw; 1488 uint32_t fw_heart_beat; 1489 uint32_t aenmbx0; 1490 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; 1491 uint32_t tempc; 1492 1493 /* Check firmware health */ 1494 if (ha->mr.fw_hbt_cnt) 1495 ha->mr.fw_hbt_cnt--; 1496 else { 1497 if ((!ha->flags.mr_reset_hdlr_active) && 1498 (!test_bit(UNLOADING, &vha->dpc_flags)) && 1499 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 1500 (ha->mr.fw_hbt_en)) { 1501 fw_heart_beat = RD_REG_DWORD(®->fwheartbeat); 1502 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) { 1503 ha->mr.old_fw_hbt_cnt = fw_heart_beat; 1504 ha->mr.fw_hbt_miss_cnt = 0; 1505 } else { 1506 ha->mr.fw_hbt_miss_cnt++; 1507 if (ha->mr.fw_hbt_miss_cnt == 1508 QLAFX00_HEARTBEAT_MISS_CNT) { 1509 set_bit(ISP_ABORT_NEEDED, 1510 &vha->dpc_flags); 1511 qla2xxx_wake_dpc(vha); 1512 ha->mr.fw_hbt_miss_cnt = 0; 1513 } 1514 } 1515 } 1516 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 1517 } 1518 1519 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) { 1520 /* Reset recovery to be performed in timer routine */ 1521 aenmbx0 = RD_REG_DWORD(®->aenmailbox0); 1522 if (ha->mr.fw_reset_timer_exp) { 1523 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1524 qla2xxx_wake_dpc(vha); 1525 ha->mr.fw_reset_timer_exp = 0; 1526 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) { 1527 /* Wake up DPC to rescan the targets */ 1528 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags); 1529 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); 1530 qla2xxx_wake_dpc(vha); 1531 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 1532 } else if ((aenmbx0 == MBA_FW_STARTING) && 1533 (!ha->mr.fw_hbt_en)) { 1534 ha->mr.fw_hbt_en = 1; 1535 } else if (!ha->mr.fw_reset_timer_tick) { 1536 if (aenmbx0 == ha->mr.old_aenmbx0_state) 1537 ha->mr.fw_reset_timer_exp = 1; 1538 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 1539 } else if (aenmbx0 == 0xFFFFFFFF) { 1540 uint32_t data0, data1; 1541 1542 data0 = QLAFX00_RD_REG(ha, 1543 QLAFX00_BAR1_BASE_ADDR_REG); 1544 data1 = QLAFX00_RD_REG(ha, 1545 QLAFX00_PEX0_WIN0_BASE_ADDR_REG); 1546 1547 data0 &= 0xffff0000; 1548 data1 &= 0x0000ffff; 1549 1550 QLAFX00_WR_REG(ha, 1551 QLAFX00_PEX0_WIN0_BASE_ADDR_REG, 1552 (data0 | data1)); 1553 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) { 1554 ha->mr.fw_reset_timer_tick = 1555 QLAFX00_MAX_RESET_INTERVAL; 1556 } else if (aenmbx0 == MBA_FW_RESET_FCT) { 1557 ha->mr.fw_reset_timer_tick = 1558 QLAFX00_MAX_RESET_INTERVAL; 1559 } 1560 if (ha->mr.old_aenmbx0_state != aenmbx0) { 1561 ha->mr.old_aenmbx0_state = aenmbx0; 1562 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 1563 } 1564 ha->mr.fw_reset_timer_tick--; 1565 } 1566 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) { 1567 /* 1568 * Critical temperature recovery to be 1569 * performed in timer routine 1570 */ 1571 if (ha->mr.fw_critemp_timer_tick == 0) { 1572 tempc = QLAFX00_GET_TEMPERATURE(ha); 1573 ql_dbg(ql_dbg_timer, vha, 0x6012, 1574 "ISPFx00(%s): Critical temp timer, " 1575 "current SOC temperature: %d\n", 1576 __func__, tempc); 1577 if (tempc < ha->mr.critical_temperature) { 1578 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1579 clear_bit(FX00_CRITEMP_RECOVERY, 1580 &vha->dpc_flags); 1581 qla2xxx_wake_dpc(vha); 1582 } 1583 ha->mr.fw_critemp_timer_tick = 1584 QLAFX00_CRITEMP_INTERVAL; 1585 } else { 1586 ha->mr.fw_critemp_timer_tick--; 1587 } 1588 } 1589 if (ha->mr.host_info_resend) { 1590 /* 1591 * Incomplete host info might be sent to firmware 1592 * durinng system boot - info should be resend 1593 */ 1594 if (ha->mr.hinfo_resend_timer_tick == 0) { 1595 ha->mr.host_info_resend = false; 1596 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags); 1597 ha->mr.hinfo_resend_timer_tick = 1598 QLAFX00_HINFO_RESEND_INTERVAL; 1599 qla2xxx_wake_dpc(vha); 1600 } else { 1601 ha->mr.hinfo_resend_timer_tick--; 1602 } 1603 } 1604 1605 } 1606 1607 /* 1608 * qlfx00a_reset_initialize 1609 * Re-initialize after a iSA device reset. 1610 * 1611 * Input: 1612 * ha = adapter block pointer. 1613 * 1614 * Returns: 1615 * 0 = success 1616 */ 1617 int 1618 qlafx00_reset_initialize(scsi_qla_host_t *vha) 1619 { 1620 struct qla_hw_data *ha = vha->hw; 1621 1622 if (vha->device_flags & DFLG_DEV_FAILED) { 1623 ql_dbg(ql_dbg_init, vha, 0x0142, 1624 "Device in failed state\n"); 1625 return QLA_SUCCESS; 1626 } 1627 1628 ha->flags.mr_reset_hdlr_active = 1; 1629 1630 if (vha->flags.online) { 1631 scsi_block_requests(vha->host); 1632 qlafx00_abort_isp_cleanup(vha, false); 1633 } 1634 1635 ql_log(ql_log_info, vha, 0x0143, 1636 "(%s): succeeded.\n", __func__); 1637 ha->flags.mr_reset_hdlr_active = 0; 1638 return QLA_SUCCESS; 1639 } 1640 1641 /* 1642 * qlafx00_abort_isp 1643 * Resets ISP and aborts all outstanding commands. 1644 * 1645 * Input: 1646 * ha = adapter block pointer. 1647 * 1648 * Returns: 1649 * 0 = success 1650 */ 1651 int 1652 qlafx00_abort_isp(scsi_qla_host_t *vha) 1653 { 1654 struct qla_hw_data *ha = vha->hw; 1655 1656 if (vha->flags.online) { 1657 if (unlikely(pci_channel_offline(ha->pdev) && 1658 ha->flags.pci_channel_io_perm_failure)) { 1659 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 1660 return QLA_SUCCESS; 1661 } 1662 1663 scsi_block_requests(vha->host); 1664 qlafx00_abort_isp_cleanup(vha, false); 1665 } else { 1666 scsi_block_requests(vha->host); 1667 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1668 vha->qla_stats.total_isp_aborts++; 1669 ha->isp_ops->reset_chip(vha); 1670 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); 1671 /* Clear the Interrupts */ 1672 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); 1673 } 1674 1675 ql_log(ql_log_info, vha, 0x0145, 1676 "(%s): succeeded.\n", __func__); 1677 1678 return QLA_SUCCESS; 1679 } 1680 1681 static inline fc_port_t* 1682 qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id) 1683 { 1684 fc_port_t *fcport; 1685 1686 /* Check for matching device in remote port list. */ 1687 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1688 if (fcport->tgt_id == tgt_id) { 1689 ql_dbg(ql_dbg_async, vha, 0x5072, 1690 "Matching fcport(%p) found with TGT-ID: 0x%x " 1691 "and Remote TGT_ID: 0x%x\n", 1692 fcport, fcport->tgt_id, tgt_id); 1693 return fcport; 1694 } 1695 } 1696 return NULL; 1697 } 1698 1699 static void 1700 qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id) 1701 { 1702 fc_port_t *fcport; 1703 1704 ql_log(ql_log_info, vha, 0x5073, 1705 "Detach TGT-ID: 0x%x\n", tgt_id); 1706 1707 fcport = qlafx00_get_fcport(vha, tgt_id); 1708 if (!fcport) 1709 return; 1710 1711 qla2x00_mark_device_lost(vha, fcport, 0, 0); 1712 1713 return; 1714 } 1715 1716 int 1717 qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt) 1718 { 1719 int rval = 0; 1720 uint32_t aen_code, aen_data; 1721 1722 aen_code = FCH_EVT_VENDOR_UNIQUE; 1723 aen_data = evt->u.aenfx.evtcode; 1724 1725 switch (evt->u.aenfx.evtcode) { 1726 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */ 1727 if (evt->u.aenfx.mbx[1] == 0) { 1728 if (evt->u.aenfx.mbx[2] == 1) { 1729 if (!vha->flags.fw_tgt_reported) 1730 vha->flags.fw_tgt_reported = 1; 1731 atomic_set(&vha->loop_down_timer, 0); 1732 atomic_set(&vha->loop_state, LOOP_UP); 1733 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1734 qla2xxx_wake_dpc(vha); 1735 } else if (evt->u.aenfx.mbx[2] == 2) { 1736 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]); 1737 } 1738 } else if (evt->u.aenfx.mbx[1] == 0xffff) { 1739 if (evt->u.aenfx.mbx[2] == 1) { 1740 if (!vha->flags.fw_tgt_reported) 1741 vha->flags.fw_tgt_reported = 1; 1742 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1743 } else if (evt->u.aenfx.mbx[2] == 2) { 1744 vha->device_flags |= DFLG_NO_CABLE; 1745 qla2x00_mark_all_devices_lost(vha, 1); 1746 } 1747 } 1748 break; 1749 case QLAFX00_MBA_LINK_UP: 1750 aen_code = FCH_EVT_LINKUP; 1751 aen_data = 0; 1752 break; 1753 case QLAFX00_MBA_LINK_DOWN: 1754 aen_code = FCH_EVT_LINKDOWN; 1755 aen_data = 0; 1756 break; 1757 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */ 1758 ql_log(ql_log_info, vha, 0x5082, 1759 "Process critical temperature event " 1760 "aenmb[0]: %x\n", 1761 evt->u.aenfx.evtcode); 1762 scsi_block_requests(vha->host); 1763 qlafx00_abort_isp_cleanup(vha, true); 1764 scsi_unblock_requests(vha->host); 1765 break; 1766 } 1767 1768 fc_host_post_event(vha->host, fc_get_event_number(), 1769 aen_code, aen_data); 1770 1771 return rval; 1772 } 1773 1774 static void 1775 qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo) 1776 { 1777 u64 port_name = 0, node_name = 0; 1778 1779 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name); 1780 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name); 1781 1782 fc_host_node_name(vha->host) = node_name; 1783 fc_host_port_name(vha->host) = port_name; 1784 if (!pinfo->port_type) 1785 vha->hw->current_topology = ISP_CFG_F; 1786 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP) 1787 atomic_set(&vha->loop_state, LOOP_READY); 1788 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN) 1789 atomic_set(&vha->loop_state, LOOP_DOWN); 1790 vha->hw->link_data_rate = (uint16_t)pinfo->link_config; 1791 } 1792 1793 static void 1794 qla2x00_fxdisc_iocb_timeout(void *data) 1795 { 1796 srb_t *sp = data; 1797 struct srb_iocb *lio = &sp->u.iocb_cmd; 1798 1799 complete(&lio->u.fxiocb.fxiocb_comp); 1800 } 1801 1802 static void 1803 qla2x00_fxdisc_sp_done(void *ptr, int res) 1804 { 1805 srb_t *sp = ptr; 1806 struct srb_iocb *lio = &sp->u.iocb_cmd; 1807 1808 complete(&lio->u.fxiocb.fxiocb_comp); 1809 } 1810 1811 int 1812 qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type) 1813 { 1814 srb_t *sp; 1815 struct srb_iocb *fdisc; 1816 int rval = QLA_FUNCTION_FAILED; 1817 struct qla_hw_data *ha = vha->hw; 1818 struct host_system_info *phost_info; 1819 struct register_host_info *preg_hsi; 1820 struct new_utsname *p_sysid = NULL; 1821 1822 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1823 if (!sp) 1824 goto done; 1825 1826 sp->type = SRB_FXIOCB_DCMD; 1827 sp->name = "fxdisc"; 1828 1829 fdisc = &sp->u.iocb_cmd; 1830 fdisc->timeout = qla2x00_fxdisc_iocb_timeout; 1831 qla2x00_init_timer(sp, FXDISC_TIMEOUT); 1832 1833 switch (fx_type) { 1834 case FXDISC_GET_CONFIG_INFO: 1835 fdisc->u.fxiocb.flags = 1836 SRB_FXDISC_RESP_DMA_VALID; 1837 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data); 1838 break; 1839 case FXDISC_GET_PORT_INFO: 1840 fdisc->u.fxiocb.flags = 1841 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; 1842 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO; 1843 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id); 1844 break; 1845 case FXDISC_GET_TGT_NODE_INFO: 1846 fdisc->u.fxiocb.flags = 1847 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; 1848 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO; 1849 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id); 1850 break; 1851 case FXDISC_GET_TGT_NODE_LIST: 1852 fdisc->u.fxiocb.flags = 1853 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; 1854 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE; 1855 break; 1856 case FXDISC_REG_HOST_INFO: 1857 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID; 1858 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info); 1859 p_sysid = utsname(); 1860 if (!p_sysid) { 1861 ql_log(ql_log_warn, vha, 0x303c, 1862 "Not able to get the system information\n"); 1863 goto done_free_sp; 1864 } 1865 break; 1866 case FXDISC_ABORT_IOCTL: 1867 default: 1868 break; 1869 } 1870 1871 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) { 1872 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev, 1873 fdisc->u.fxiocb.req_len, 1874 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL); 1875 if (!fdisc->u.fxiocb.req_addr) 1876 goto done_free_sp; 1877 1878 if (fx_type == FXDISC_REG_HOST_INFO) { 1879 preg_hsi = (struct register_host_info *) 1880 fdisc->u.fxiocb.req_addr; 1881 phost_info = &preg_hsi->hsi; 1882 memset(preg_hsi, 0, sizeof(struct register_host_info)); 1883 phost_info->os_type = OS_TYPE_LINUX; 1884 strncpy(phost_info->sysname, 1885 p_sysid->sysname, SYSNAME_LENGTH); 1886 strncpy(phost_info->nodename, 1887 p_sysid->nodename, NODENAME_LENGTH); 1888 if (!strcmp(phost_info->nodename, "(none)")) 1889 ha->mr.host_info_resend = true; 1890 strncpy(phost_info->release, 1891 p_sysid->release, RELEASE_LENGTH); 1892 strncpy(phost_info->version, 1893 p_sysid->version, VERSION_LENGTH); 1894 strncpy(phost_info->machine, 1895 p_sysid->machine, MACHINE_LENGTH); 1896 strncpy(phost_info->domainname, 1897 p_sysid->domainname, DOMNAME_LENGTH); 1898 strncpy(phost_info->hostdriver, 1899 QLA2XXX_VERSION, VERSION_LENGTH); 1900 preg_hsi->utc = (uint64_t)ktime_get_real_seconds(); 1901 ql_dbg(ql_dbg_init, vha, 0x0149, 1902 "ISP%04X: Host registration with firmware\n", 1903 ha->pdev->device); 1904 ql_dbg(ql_dbg_init, vha, 0x014a, 1905 "os_type = '%d', sysname = '%s', nodname = '%s'\n", 1906 phost_info->os_type, 1907 phost_info->sysname, 1908 phost_info->nodename); 1909 ql_dbg(ql_dbg_init, vha, 0x014b, 1910 "release = '%s', version = '%s'\n", 1911 phost_info->release, 1912 phost_info->version); 1913 ql_dbg(ql_dbg_init, vha, 0x014c, 1914 "machine = '%s' " 1915 "domainname = '%s', hostdriver = '%s'\n", 1916 phost_info->machine, 1917 phost_info->domainname, 1918 phost_info->hostdriver); 1919 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d, 1920 phost_info, sizeof(*phost_info)); 1921 } 1922 } 1923 1924 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) { 1925 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev, 1926 fdisc->u.fxiocb.rsp_len, 1927 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL); 1928 if (!fdisc->u.fxiocb.rsp_addr) 1929 goto done_unmap_req; 1930 } 1931 1932 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type); 1933 sp->done = qla2x00_fxdisc_sp_done; 1934 1935 rval = qla2x00_start_sp(sp); 1936 if (rval != QLA_SUCCESS) 1937 goto done_unmap_dma; 1938 1939 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp); 1940 1941 if (fx_type == FXDISC_GET_CONFIG_INFO) { 1942 struct config_info_data *pinfo = 1943 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr; 1944 strcpy(vha->hw->model_number, pinfo->model_num); 1945 strcpy(vha->hw->model_desc, pinfo->model_description); 1946 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name, 1947 sizeof(vha->hw->mr.symbolic_name)); 1948 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num, 1949 sizeof(vha->hw->mr.serial_num)); 1950 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version, 1951 sizeof(vha->hw->mr.hw_version)); 1952 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version, 1953 sizeof(vha->hw->mr.fw_version)); 1954 strim(vha->hw->mr.fw_version); 1955 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version, 1956 sizeof(vha->hw->mr.uboot_version)); 1957 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num, 1958 sizeof(vha->hw->mr.fru_serial_num)); 1959 vha->hw->mr.critical_temperature = 1960 (pinfo->nominal_temp_value) ? 1961 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD; 1962 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities & 1963 QLAFX00_EXTENDED_IO_EN_MASK) != 0; 1964 } else if (fx_type == FXDISC_GET_PORT_INFO) { 1965 struct port_info_data *pinfo = 1966 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr; 1967 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE); 1968 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE); 1969 vha->d_id.b.domain = pinfo->port_id[0]; 1970 vha->d_id.b.area = pinfo->port_id[1]; 1971 vha->d_id.b.al_pa = pinfo->port_id[2]; 1972 qlafx00_update_host_attr(vha, pinfo); 1973 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141, 1974 pinfo, 16); 1975 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) { 1976 struct qlafx00_tgt_node_info *pinfo = 1977 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr; 1978 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE); 1979 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE); 1980 fcport->port_type = FCT_TARGET; 1981 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144, 1982 pinfo, 16); 1983 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) { 1984 struct qlafx00_tgt_node_info *pinfo = 1985 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr; 1986 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146, 1987 pinfo, 16); 1988 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE); 1989 } else if (fx_type == FXDISC_ABORT_IOCTL) 1990 fdisc->u.fxiocb.result = 1991 (fdisc->u.fxiocb.result == 1992 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ? 1993 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED); 1994 1995 rval = le32_to_cpu(fdisc->u.fxiocb.result); 1996 1997 done_unmap_dma: 1998 if (fdisc->u.fxiocb.rsp_addr) 1999 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len, 2000 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle); 2001 2002 done_unmap_req: 2003 if (fdisc->u.fxiocb.req_addr) 2004 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len, 2005 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle); 2006 done_free_sp: 2007 sp->free(sp); 2008 done: 2009 return rval; 2010 } 2011 2012 /* 2013 * qlafx00_initialize_adapter 2014 * Initialize board. 2015 * 2016 * Input: 2017 * ha = adapter block pointer. 2018 * 2019 * Returns: 2020 * 0 = success 2021 */ 2022 int 2023 qlafx00_initialize_adapter(scsi_qla_host_t *vha) 2024 { 2025 int rval; 2026 struct qla_hw_data *ha = vha->hw; 2027 uint32_t tempc; 2028 2029 /* Clear adapter flags. */ 2030 vha->flags.online = 0; 2031 ha->flags.chip_reset_done = 0; 2032 vha->flags.reset_active = 0; 2033 ha->flags.pci_channel_io_perm_failure = 0; 2034 ha->flags.eeh_busy = 0; 2035 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2036 atomic_set(&vha->loop_state, LOOP_DOWN); 2037 vha->device_flags = DFLG_NO_CABLE; 2038 vha->dpc_flags = 0; 2039 vha->flags.management_server_logged_in = 0; 2040 ha->isp_abort_cnt = 0; 2041 ha->beacon_blink_led = 0; 2042 2043 set_bit(0, ha->req_qid_map); 2044 set_bit(0, ha->rsp_qid_map); 2045 2046 ql_dbg(ql_dbg_init, vha, 0x0147, 2047 "Configuring PCI space...\n"); 2048 2049 rval = ha->isp_ops->pci_config(vha); 2050 if (rval) { 2051 ql_log(ql_log_warn, vha, 0x0148, 2052 "Unable to configure PCI space.\n"); 2053 return rval; 2054 } 2055 2056 rval = qlafx00_init_fw_ready(vha); 2057 if (rval != QLA_SUCCESS) 2058 return rval; 2059 2060 qlafx00_save_queue_ptrs(vha); 2061 2062 rval = qlafx00_config_queues(vha); 2063 if (rval != QLA_SUCCESS) 2064 return rval; 2065 2066 /* 2067 * Allocate the array of outstanding commands 2068 * now that we know the firmware resources. 2069 */ 2070 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req); 2071 if (rval != QLA_SUCCESS) 2072 return rval; 2073 2074 rval = qla2x00_init_rings(vha); 2075 ha->flags.chip_reset_done = 1; 2076 2077 tempc = QLAFX00_GET_TEMPERATURE(ha); 2078 ql_dbg(ql_dbg_init, vha, 0x0152, 2079 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n", 2080 __func__, tempc); 2081 2082 return rval; 2083 } 2084 2085 uint32_t 2086 qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr, 2087 char *buf) 2088 { 2089 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); 2090 int rval = QLA_FUNCTION_FAILED; 2091 uint32_t state[1]; 2092 2093 if (qla2x00_reset_active(vha)) 2094 ql_log(ql_log_warn, vha, 0x70ce, 2095 "ISP reset active.\n"); 2096 else if (!vha->hw->flags.eeh_busy) { 2097 rval = qlafx00_get_firmware_state(vha, state); 2098 } 2099 if (rval != QLA_SUCCESS) 2100 memset(state, -1, sizeof(state)); 2101 2102 return state[0]; 2103 } 2104 2105 void 2106 qlafx00_get_host_speed(struct Scsi_Host *shost) 2107 { 2108 struct qla_hw_data *ha = ((struct scsi_qla_host *) 2109 (shost_priv(shost)))->hw; 2110 u32 speed = FC_PORTSPEED_UNKNOWN; 2111 2112 switch (ha->link_data_rate) { 2113 case QLAFX00_PORT_SPEED_2G: 2114 speed = FC_PORTSPEED_2GBIT; 2115 break; 2116 case QLAFX00_PORT_SPEED_4G: 2117 speed = FC_PORTSPEED_4GBIT; 2118 break; 2119 case QLAFX00_PORT_SPEED_8G: 2120 speed = FC_PORTSPEED_8GBIT; 2121 break; 2122 case QLAFX00_PORT_SPEED_10G: 2123 speed = FC_PORTSPEED_10GBIT; 2124 break; 2125 } 2126 fc_host_speed(shost) = speed; 2127 } 2128 2129 /** QLAFX00 specific ISR implementation functions */ 2130 2131 static inline void 2132 qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len, 2133 uint32_t sense_len, struct rsp_que *rsp, int res) 2134 { 2135 struct scsi_qla_host *vha = sp->vha; 2136 struct scsi_cmnd *cp = GET_CMD_SP(sp); 2137 uint32_t track_sense_len; 2138 2139 SET_FW_SENSE_LEN(sp, sense_len); 2140 2141 if (sense_len >= SCSI_SENSE_BUFFERSIZE) 2142 sense_len = SCSI_SENSE_BUFFERSIZE; 2143 2144 SET_CMD_SENSE_LEN(sp, sense_len); 2145 SET_CMD_SENSE_PTR(sp, cp->sense_buffer); 2146 track_sense_len = sense_len; 2147 2148 if (sense_len > par_sense_len) 2149 sense_len = par_sense_len; 2150 2151 memcpy(cp->sense_buffer, sense_data, sense_len); 2152 2153 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len); 2154 2155 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len); 2156 track_sense_len -= sense_len; 2157 SET_CMD_SENSE_LEN(sp, track_sense_len); 2158 2159 ql_dbg(ql_dbg_io, vha, 0x304d, 2160 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n", 2161 sense_len, par_sense_len, track_sense_len); 2162 if (GET_FW_SENSE_LEN(sp) > 0) { 2163 rsp->status_srb = sp; 2164 cp->result = res; 2165 } 2166 2167 if (sense_len) { 2168 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039, 2169 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n", 2170 sp->vha->host_no, cp->device->id, cp->device->lun, 2171 cp); 2172 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049, 2173 cp->sense_buffer, sense_len); 2174 } 2175 } 2176 2177 static void 2178 qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, 2179 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp, 2180 __le16 sstatus, __le16 cpstatus) 2181 { 2182 struct srb_iocb *tmf; 2183 2184 tmf = &sp->u.iocb_cmd; 2185 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) || 2186 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID))) 2187 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE); 2188 tmf->u.tmf.comp_status = cpstatus; 2189 sp->done(sp, 0); 2190 } 2191 2192 static void 2193 qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, 2194 struct abort_iocb_entry_fx00 *pkt) 2195 { 2196 const char func[] = "ABT_IOCB"; 2197 srb_t *sp; 2198 struct srb_iocb *abt; 2199 2200 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); 2201 if (!sp) 2202 return; 2203 2204 abt = &sp->u.iocb_cmd; 2205 abt->u.abt.comp_status = pkt->tgt_id_sts; 2206 sp->done(sp, 0); 2207 } 2208 2209 static void 2210 qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req, 2211 struct ioctl_iocb_entry_fx00 *pkt) 2212 { 2213 const char func[] = "IOSB_IOCB"; 2214 srb_t *sp; 2215 struct bsg_job *bsg_job; 2216 struct fc_bsg_reply *bsg_reply; 2217 struct srb_iocb *iocb_job; 2218 int res = 0; 2219 struct qla_mt_iocb_rsp_fx00 fstatus; 2220 uint8_t *fw_sts_ptr; 2221 2222 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); 2223 if (!sp) 2224 return; 2225 2226 if (sp->type == SRB_FXIOCB_DCMD) { 2227 iocb_job = &sp->u.iocb_cmd; 2228 iocb_job->u.fxiocb.seq_number = pkt->seq_no; 2229 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags; 2230 iocb_job->u.fxiocb.result = pkt->status; 2231 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID) 2232 iocb_job->u.fxiocb.req_data = 2233 pkt->dataword_r; 2234 } else { 2235 bsg_job = sp->u.bsg_job; 2236 bsg_reply = bsg_job->reply; 2237 2238 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00)); 2239 2240 fstatus.reserved_1 = pkt->reserved_0; 2241 fstatus.func_type = pkt->comp_func_num; 2242 fstatus.ioctl_flags = pkt->fw_iotcl_flags; 2243 fstatus.ioctl_data = pkt->dataword_r; 2244 fstatus.adapid = pkt->adapid; 2245 fstatus.reserved_2 = pkt->dataword_r_extra; 2246 fstatus.res_count = pkt->residuallen; 2247 fstatus.status = pkt->status; 2248 fstatus.seq_number = pkt->seq_no; 2249 memcpy(fstatus.reserved_3, 2250 pkt->reserved_2, 20 * sizeof(uint8_t)); 2251 2252 fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply); 2253 2254 memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus)); 2255 bsg_job->reply_len = sizeof(struct fc_bsg_reply) + 2256 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t); 2257 2258 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, 2259 sp->vha, 0x5080, pkt, sizeof(*pkt)); 2260 2261 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, 2262 sp->vha, 0x5074, 2263 fw_sts_ptr, sizeof(fstatus)); 2264 2265 res = bsg_reply->result = DID_OK << 16; 2266 bsg_reply->reply_payload_rcv_len = 2267 bsg_job->reply_payload.payload_len; 2268 } 2269 sp->done(sp, res); 2270 } 2271 2272 /** 2273 * qlafx00_status_entry() - Process a Status IOCB entry. 2274 * @vha: SCSI driver HA context 2275 * @rsp: response queue 2276 * @pkt: Entry pointer 2277 */ 2278 static void 2279 qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt) 2280 { 2281 srb_t *sp; 2282 fc_port_t *fcport; 2283 struct scsi_cmnd *cp; 2284 struct sts_entry_fx00 *sts; 2285 __le16 comp_status; 2286 __le16 scsi_status; 2287 __le16 lscsi_status; 2288 int32_t resid; 2289 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len, 2290 fw_resid_len; 2291 uint8_t *rsp_info = NULL, *sense_data = NULL; 2292 struct qla_hw_data *ha = vha->hw; 2293 uint32_t hindex, handle; 2294 uint16_t que; 2295 struct req_que *req; 2296 int logit = 1; 2297 int res = 0; 2298 2299 sts = (struct sts_entry_fx00 *) pkt; 2300 2301 comp_status = sts->comp_status; 2302 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK); 2303 hindex = sts->handle; 2304 handle = LSW(hindex); 2305 2306 que = MSW(hindex); 2307 req = ha->req_q_map[que]; 2308 2309 /* Validate handle. */ 2310 if (handle < req->num_outstanding_cmds) 2311 sp = req->outstanding_cmds[handle]; 2312 else 2313 sp = NULL; 2314 2315 if (sp == NULL) { 2316 ql_dbg(ql_dbg_io, vha, 0x3034, 2317 "Invalid status handle (0x%x).\n", handle); 2318 2319 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2320 qla2xxx_wake_dpc(vha); 2321 return; 2322 } 2323 2324 if (sp->type == SRB_TM_CMD) { 2325 req->outstanding_cmds[handle] = NULL; 2326 qlafx00_tm_iocb_entry(vha, req, pkt, sp, 2327 scsi_status, comp_status); 2328 return; 2329 } 2330 2331 /* Fast path completion. */ 2332 if (comp_status == CS_COMPLETE && scsi_status == 0) { 2333 qla2x00_process_completed_request(vha, req, handle); 2334 return; 2335 } 2336 2337 req->outstanding_cmds[handle] = NULL; 2338 cp = GET_CMD_SP(sp); 2339 if (cp == NULL) { 2340 ql_dbg(ql_dbg_io, vha, 0x3048, 2341 "Command already returned (0x%x/%p).\n", 2342 handle, sp); 2343 2344 return; 2345 } 2346 2347 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK); 2348 2349 fcport = sp->fcport; 2350 2351 sense_len = par_sense_len = rsp_info_len = resid_len = 2352 fw_resid_len = 0; 2353 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)) 2354 sense_len = sts->sense_len; 2355 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER 2356 | (uint16_t)SS_RESIDUAL_OVER))) 2357 resid_len = le32_to_cpu(sts->residual_len); 2358 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN)) 2359 fw_resid_len = le32_to_cpu(sts->residual_len); 2360 rsp_info = sense_data = sts->data; 2361 par_sense_len = sizeof(sts->data); 2362 2363 /* Check for overrun. */ 2364 if (comp_status == CS_COMPLETE && 2365 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER)) 2366 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN); 2367 2368 /* 2369 * Based on Host and scsi status generate status code for Linux 2370 */ 2371 switch (le16_to_cpu(comp_status)) { 2372 case CS_COMPLETE: 2373 case CS_QUEUE_FULL: 2374 if (scsi_status == 0) { 2375 res = DID_OK << 16; 2376 break; 2377 } 2378 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER 2379 | (uint16_t)SS_RESIDUAL_OVER))) { 2380 resid = resid_len; 2381 scsi_set_resid(cp, resid); 2382 2383 if (!lscsi_status && 2384 ((unsigned)(scsi_bufflen(cp) - resid) < 2385 cp->underflow)) { 2386 ql_dbg(ql_dbg_io, fcport->vha, 0x3050, 2387 "Mid-layer underflow " 2388 "detected (0x%x of 0x%x bytes).\n", 2389 resid, scsi_bufflen(cp)); 2390 2391 res = DID_ERROR << 16; 2392 break; 2393 } 2394 } 2395 res = DID_OK << 16 | le16_to_cpu(lscsi_status); 2396 2397 if (lscsi_status == 2398 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) { 2399 ql_dbg(ql_dbg_io, fcport->vha, 0x3051, 2400 "QUEUE FULL detected.\n"); 2401 break; 2402 } 2403 logit = 0; 2404 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION)) 2405 break; 2406 2407 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); 2408 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))) 2409 break; 2410 2411 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len, 2412 rsp, res); 2413 break; 2414 2415 case CS_DATA_UNDERRUN: 2416 /* Use F/W calculated residual length. */ 2417 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha)) 2418 resid = fw_resid_len; 2419 else 2420 resid = resid_len; 2421 scsi_set_resid(cp, resid); 2422 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) { 2423 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha)) 2424 && fw_resid_len != resid_len) { 2425 ql_dbg(ql_dbg_io, fcport->vha, 0x3052, 2426 "Dropped frame(s) detected " 2427 "(0x%x of 0x%x bytes).\n", 2428 resid, scsi_bufflen(cp)); 2429 2430 res = DID_ERROR << 16 | 2431 le16_to_cpu(lscsi_status); 2432 goto check_scsi_status; 2433 } 2434 2435 if (!lscsi_status && 2436 ((unsigned)(scsi_bufflen(cp) - resid) < 2437 cp->underflow)) { 2438 ql_dbg(ql_dbg_io, fcport->vha, 0x3053, 2439 "Mid-layer underflow " 2440 "detected (0x%x of 0x%x bytes, " 2441 "cp->underflow: 0x%x).\n", 2442 resid, scsi_bufflen(cp), cp->underflow); 2443 2444 res = DID_ERROR << 16; 2445 break; 2446 } 2447 } else if (lscsi_status != 2448 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) && 2449 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) { 2450 /* 2451 * scsi status of task set and busy are considered 2452 * to be task not completed. 2453 */ 2454 2455 ql_dbg(ql_dbg_io, fcport->vha, 0x3054, 2456 "Dropped frame(s) detected (0x%x " 2457 "of 0x%x bytes).\n", resid, 2458 scsi_bufflen(cp)); 2459 2460 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status); 2461 goto check_scsi_status; 2462 } else { 2463 ql_dbg(ql_dbg_io, fcport->vha, 0x3055, 2464 "scsi_status: 0x%x, lscsi_status: 0x%x\n", 2465 scsi_status, lscsi_status); 2466 } 2467 2468 res = DID_OK << 16 | le16_to_cpu(lscsi_status); 2469 logit = 0; 2470 2471 check_scsi_status: 2472 /* 2473 * Check to see if SCSI Status is non zero. If so report SCSI 2474 * Status. 2475 */ 2476 if (lscsi_status != 0) { 2477 if (lscsi_status == 2478 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) { 2479 ql_dbg(ql_dbg_io, fcport->vha, 0x3056, 2480 "QUEUE FULL detected.\n"); 2481 logit = 1; 2482 break; 2483 } 2484 if (lscsi_status != 2485 cpu_to_le16((uint16_t)SS_CHECK_CONDITION)) 2486 break; 2487 2488 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); 2489 if (!(scsi_status & 2490 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))) 2491 break; 2492 2493 qlafx00_handle_sense(sp, sense_data, par_sense_len, 2494 sense_len, rsp, res); 2495 } 2496 break; 2497 2498 case CS_PORT_LOGGED_OUT: 2499 case CS_PORT_CONFIG_CHG: 2500 case CS_PORT_BUSY: 2501 case CS_INCOMPLETE: 2502 case CS_PORT_UNAVAILABLE: 2503 case CS_TIMEOUT: 2504 case CS_RESET: 2505 2506 /* 2507 * We are going to have the fc class block the rport 2508 * while we try to recover so instruct the mid layer 2509 * to requeue until the class decides how to handle this. 2510 */ 2511 res = DID_TRANSPORT_DISRUPTED << 16; 2512 2513 ql_dbg(ql_dbg_io, fcport->vha, 0x3057, 2514 "Port down status: port-state=0x%x.\n", 2515 atomic_read(&fcport->state)); 2516 2517 if (atomic_read(&fcport->state) == FCS_ONLINE) 2518 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1); 2519 break; 2520 2521 case CS_ABORTED: 2522 res = DID_RESET << 16; 2523 break; 2524 2525 default: 2526 res = DID_ERROR << 16; 2527 break; 2528 } 2529 2530 if (logit) 2531 ql_dbg(ql_dbg_io, fcport->vha, 0x3058, 2532 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu " 2533 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x " 2534 "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, " 2535 "par_sense_len=0x%x, rsp_info_len=0x%x\n", 2536 comp_status, scsi_status, res, vha->host_no, 2537 cp->device->id, cp->device->lun, fcport->tgt_id, 2538 lscsi_status, cp->cmnd, scsi_bufflen(cp), 2539 rsp_info, resid_len, fw_resid_len, sense_len, 2540 par_sense_len, rsp_info_len); 2541 2542 if (rsp->status_srb == NULL) 2543 sp->done(sp, res); 2544 } 2545 2546 /** 2547 * qlafx00_status_cont_entry() - Process a Status Continuations entry. 2548 * @rsp: response queue 2549 * @pkt: Entry pointer 2550 * 2551 * Extended sense data. 2552 */ 2553 static void 2554 qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt) 2555 { 2556 uint8_t sense_sz = 0; 2557 struct qla_hw_data *ha = rsp->hw; 2558 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); 2559 srb_t *sp = rsp->status_srb; 2560 struct scsi_cmnd *cp; 2561 uint32_t sense_len; 2562 uint8_t *sense_ptr; 2563 2564 if (!sp) { 2565 ql_dbg(ql_dbg_io, vha, 0x3037, 2566 "no SP, sp = %p\n", sp); 2567 return; 2568 } 2569 2570 if (!GET_FW_SENSE_LEN(sp)) { 2571 ql_dbg(ql_dbg_io, vha, 0x304b, 2572 "no fw sense data, sp = %p\n", sp); 2573 return; 2574 } 2575 cp = GET_CMD_SP(sp); 2576 if (cp == NULL) { 2577 ql_log(ql_log_warn, vha, 0x303b, 2578 "cmd is NULL: already returned to OS (sp=%p).\n", sp); 2579 2580 rsp->status_srb = NULL; 2581 return; 2582 } 2583 2584 if (!GET_CMD_SENSE_LEN(sp)) { 2585 ql_dbg(ql_dbg_io, vha, 0x304c, 2586 "no sense data, sp = %p\n", sp); 2587 } else { 2588 sense_len = GET_CMD_SENSE_LEN(sp); 2589 sense_ptr = GET_CMD_SENSE_PTR(sp); 2590 ql_dbg(ql_dbg_io, vha, 0x304f, 2591 "sp=%p sense_len=0x%x sense_ptr=%p.\n", 2592 sp, sense_len, sense_ptr); 2593 2594 if (sense_len > sizeof(pkt->data)) 2595 sense_sz = sizeof(pkt->data); 2596 else 2597 sense_sz = sense_len; 2598 2599 /* Move sense data. */ 2600 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e, 2601 pkt, sizeof(*pkt)); 2602 memcpy(sense_ptr, pkt->data, sense_sz); 2603 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a, 2604 sense_ptr, sense_sz); 2605 2606 sense_len -= sense_sz; 2607 sense_ptr += sense_sz; 2608 2609 SET_CMD_SENSE_PTR(sp, sense_ptr); 2610 SET_CMD_SENSE_LEN(sp, sense_len); 2611 } 2612 sense_len = GET_FW_SENSE_LEN(sp); 2613 sense_len = (sense_len > sizeof(pkt->data)) ? 2614 (sense_len - sizeof(pkt->data)) : 0; 2615 SET_FW_SENSE_LEN(sp, sense_len); 2616 2617 /* Place command on done queue. */ 2618 if (sense_len == 0) { 2619 rsp->status_srb = NULL; 2620 sp->done(sp, cp->result); 2621 } 2622 } 2623 2624 /** 2625 * qlafx00_multistatus_entry() - Process Multi response queue entries. 2626 * @vha: SCSI driver HA context 2627 * @rsp: response queue 2628 * @pkt: received packet 2629 */ 2630 static void 2631 qlafx00_multistatus_entry(struct scsi_qla_host *vha, 2632 struct rsp_que *rsp, void *pkt) 2633 { 2634 srb_t *sp; 2635 struct multi_sts_entry_fx00 *stsmfx; 2636 struct qla_hw_data *ha = vha->hw; 2637 uint32_t handle, hindex, handle_count, i; 2638 uint16_t que; 2639 struct req_que *req; 2640 __le32 *handle_ptr; 2641 2642 stsmfx = (struct multi_sts_entry_fx00 *) pkt; 2643 2644 handle_count = stsmfx->handle_count; 2645 2646 if (handle_count > MAX_HANDLE_COUNT) { 2647 ql_dbg(ql_dbg_io, vha, 0x3035, 2648 "Invalid handle count (0x%x).\n", handle_count); 2649 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2650 qla2xxx_wake_dpc(vha); 2651 return; 2652 } 2653 2654 handle_ptr = &stsmfx->handles[0]; 2655 2656 for (i = 0; i < handle_count; i++) { 2657 hindex = le32_to_cpu(*handle_ptr); 2658 handle = LSW(hindex); 2659 que = MSW(hindex); 2660 req = ha->req_q_map[que]; 2661 2662 /* Validate handle. */ 2663 if (handle < req->num_outstanding_cmds) 2664 sp = req->outstanding_cmds[handle]; 2665 else 2666 sp = NULL; 2667 2668 if (sp == NULL) { 2669 ql_dbg(ql_dbg_io, vha, 0x3044, 2670 "Invalid status handle (0x%x).\n", handle); 2671 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2672 qla2xxx_wake_dpc(vha); 2673 return; 2674 } 2675 qla2x00_process_completed_request(vha, req, handle); 2676 handle_ptr++; 2677 } 2678 } 2679 2680 /** 2681 * qlafx00_error_entry() - Process an error entry. 2682 * @vha: SCSI driver HA context 2683 * @rsp: response queue 2684 * @pkt: Entry pointer 2685 */ 2686 static void 2687 qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, 2688 struct sts_entry_fx00 *pkt) 2689 { 2690 srb_t *sp; 2691 struct qla_hw_data *ha = vha->hw; 2692 const char func[] = "ERROR-IOCB"; 2693 uint16_t que = 0; 2694 struct req_que *req = NULL; 2695 int res = DID_ERROR << 16; 2696 2697 req = ha->req_q_map[que]; 2698 2699 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); 2700 if (sp) { 2701 sp->done(sp, res); 2702 return; 2703 } 2704 2705 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2706 qla2xxx_wake_dpc(vha); 2707 } 2708 2709 /** 2710 * qlafx00_process_response_queue() - Process response queue entries. 2711 * @vha: SCSI driver HA context 2712 * @rsp: response queue 2713 */ 2714 static void 2715 qlafx00_process_response_queue(struct scsi_qla_host *vha, 2716 struct rsp_que *rsp) 2717 { 2718 struct sts_entry_fx00 *pkt; 2719 response_t *lptr; 2720 uint16_t lreq_q_in = 0; 2721 uint16_t lreq_q_out = 0; 2722 2723 lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in); 2724 lreq_q_out = rsp->ring_index; 2725 2726 while (lreq_q_in != lreq_q_out) { 2727 lptr = rsp->ring_ptr; 2728 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr, 2729 sizeof(rsp->rsp_pkt)); 2730 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt; 2731 2732 rsp->ring_index++; 2733 lreq_q_out++; 2734 if (rsp->ring_index == rsp->length) { 2735 lreq_q_out = 0; 2736 rsp->ring_index = 0; 2737 rsp->ring_ptr = rsp->ring; 2738 } else { 2739 rsp->ring_ptr++; 2740 } 2741 2742 if (pkt->entry_status != 0 && 2743 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) { 2744 ql_dbg(ql_dbg_async, vha, 0x507f, 2745 "type of error status in response: 0x%x\n", 2746 pkt->entry_status); 2747 qlafx00_error_entry(vha, rsp, 2748 (struct sts_entry_fx00 *)pkt); 2749 continue; 2750 } 2751 2752 switch (pkt->entry_type) { 2753 case STATUS_TYPE_FX00: 2754 qlafx00_status_entry(vha, rsp, pkt); 2755 break; 2756 2757 case STATUS_CONT_TYPE_FX00: 2758 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt); 2759 break; 2760 2761 case MULTI_STATUS_TYPE_FX00: 2762 qlafx00_multistatus_entry(vha, rsp, pkt); 2763 break; 2764 2765 case ABORT_IOCB_TYPE_FX00: 2766 qlafx00_abort_iocb_entry(vha, rsp->req, 2767 (struct abort_iocb_entry_fx00 *)pkt); 2768 break; 2769 2770 case IOCTL_IOSB_TYPE_FX00: 2771 qlafx00_ioctl_iosb_entry(vha, rsp->req, 2772 (struct ioctl_iocb_entry_fx00 *)pkt); 2773 break; 2774 default: 2775 /* Type Not Supported. */ 2776 ql_dbg(ql_dbg_async, vha, 0x5081, 2777 "Received unknown response pkt type %x " 2778 "entry status=%x.\n", 2779 pkt->entry_type, pkt->entry_status); 2780 break; 2781 } 2782 } 2783 2784 /* Adjust ring index */ 2785 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index); 2786 } 2787 2788 /** 2789 * qlafx00_async_event() - Process aynchronous events. 2790 * @vha: SCSI driver HA context 2791 */ 2792 static void 2793 qlafx00_async_event(scsi_qla_host_t *vha) 2794 { 2795 struct qla_hw_data *ha = vha->hw; 2796 struct device_reg_fx00 __iomem *reg; 2797 int data_size = 1; 2798 2799 reg = &ha->iobase->ispfx00; 2800 /* Setup to process RIO completion. */ 2801 switch (ha->aenmb[0]) { 2802 case QLAFX00_MBA_SYSTEM_ERR: /* System Error */ 2803 ql_log(ql_log_warn, vha, 0x5079, 2804 "ISP System Error - mbx1=%x\n", ha->aenmb[0]); 2805 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2806 break; 2807 2808 case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */ 2809 ql_dbg(ql_dbg_async, vha, 0x5076, 2810 "Asynchronous FW shutdown requested.\n"); 2811 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2812 qla2xxx_wake_dpc(vha); 2813 break; 2814 2815 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */ 2816 ha->aenmb[1] = RD_REG_DWORD(®->aenmailbox1); 2817 ha->aenmb[2] = RD_REG_DWORD(®->aenmailbox2); 2818 ha->aenmb[3] = RD_REG_DWORD(®->aenmailbox3); 2819 ql_dbg(ql_dbg_async, vha, 0x5077, 2820 "Asynchronous port Update received " 2821 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n", 2822 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]); 2823 data_size = 4; 2824 break; 2825 2826 case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */ 2827 ql_log(ql_log_info, vha, 0x5085, 2828 "Asynchronous over temperature event received " 2829 "aenmb[0]: %x\n", 2830 ha->aenmb[0]); 2831 break; 2832 2833 case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */ 2834 ql_log(ql_log_info, vha, 0x5086, 2835 "Asynchronous normal temperature event received " 2836 "aenmb[0]: %x\n", 2837 ha->aenmb[0]); 2838 break; 2839 2840 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */ 2841 ql_log(ql_log_info, vha, 0x5083, 2842 "Asynchronous critical temperature event received " 2843 "aenmb[0]: %x\n", 2844 ha->aenmb[0]); 2845 break; 2846 2847 default: 2848 ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1); 2849 ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2); 2850 ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3); 2851 ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4); 2852 ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5); 2853 ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6); 2854 ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7); 2855 ql_dbg(ql_dbg_async, vha, 0x5078, 2856 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n", 2857 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3], 2858 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]); 2859 break; 2860 } 2861 qlafx00_post_aenfx_work(vha, ha->aenmb[0], 2862 (uint32_t *)ha->aenmb, data_size); 2863 } 2864 2865 /** 2866 * qlafx00x_mbx_completion() - Process mailbox command completions. 2867 * @vha: SCSI driver HA context 2868 * @mb0: value to be written into mailbox register 0 2869 */ 2870 static void 2871 qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0) 2872 { 2873 uint16_t cnt; 2874 uint32_t __iomem *wptr; 2875 struct qla_hw_data *ha = vha->hw; 2876 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; 2877 2878 if (!ha->mcp32) 2879 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n"); 2880 2881 /* Load return mailbox registers. */ 2882 ha->flags.mbox_int = 1; 2883 ha->mailbox_out32[0] = mb0; 2884 wptr = (uint32_t __iomem *)®->mailbox17; 2885 2886 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2887 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); 2888 wptr++; 2889 } 2890 } 2891 2892 /** 2893 * qlafx00_intr_handler() - Process interrupts for the ISPFX00. 2894 * @irq: interrupt number 2895 * @dev_id: SCSI driver HA context 2896 * 2897 * Called by system whenever the host adapter generates an interrupt. 2898 * 2899 * Returns handled flag. 2900 */ 2901 irqreturn_t 2902 qlafx00_intr_handler(int irq, void *dev_id) 2903 { 2904 scsi_qla_host_t *vha; 2905 struct qla_hw_data *ha; 2906 struct device_reg_fx00 __iomem *reg; 2907 int status; 2908 unsigned long iter; 2909 uint32_t stat; 2910 uint32_t mb[8]; 2911 struct rsp_que *rsp; 2912 unsigned long flags; 2913 uint32_t clr_intr = 0; 2914 uint32_t intr_stat = 0; 2915 2916 rsp = (struct rsp_que *) dev_id; 2917 if (!rsp) { 2918 ql_log(ql_log_info, NULL, 0x507d, 2919 "%s: NULL response queue pointer.\n", __func__); 2920 return IRQ_NONE; 2921 } 2922 2923 ha = rsp->hw; 2924 reg = &ha->iobase->ispfx00; 2925 status = 0; 2926 2927 if (unlikely(pci_channel_offline(ha->pdev))) 2928 return IRQ_HANDLED; 2929 2930 spin_lock_irqsave(&ha->hardware_lock, flags); 2931 vha = pci_get_drvdata(ha->pdev); 2932 for (iter = 50; iter--; clr_intr = 0) { 2933 stat = QLAFX00_RD_INTR_REG(ha); 2934 if (qla2x00_check_reg32_for_disconnect(vha, stat)) 2935 break; 2936 intr_stat = stat & QLAFX00_HST_INT_STS_BITS; 2937 if (!intr_stat) 2938 break; 2939 2940 if (stat & QLAFX00_INTR_MB_CMPLT) { 2941 mb[0] = RD_REG_WORD(®->mailbox16); 2942 qlafx00_mbx_completion(vha, mb[0]); 2943 status |= MBX_INTERRUPT; 2944 clr_intr |= QLAFX00_INTR_MB_CMPLT; 2945 } 2946 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) { 2947 ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); 2948 qlafx00_async_event(vha); 2949 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT; 2950 } 2951 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) { 2952 qlafx00_process_response_queue(vha, rsp); 2953 clr_intr |= QLAFX00_INTR_RSP_CMPLT; 2954 } 2955 2956 QLAFX00_CLR_INTR_REG(ha, clr_intr); 2957 QLAFX00_RD_INTR_REG(ha); 2958 } 2959 2960 qla2x00_handle_mbx_completion(ha, status); 2961 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2962 2963 return IRQ_HANDLED; 2964 } 2965 2966 /** QLAFX00 specific IOCB implementation functions */ 2967 2968 static inline cont_a64_entry_t * 2969 qlafx00_prep_cont_type1_iocb(struct req_que *req, 2970 cont_a64_entry_t *lcont_pkt) 2971 { 2972 cont_a64_entry_t *cont_pkt; 2973 2974 /* Adjust ring index. */ 2975 req->ring_index++; 2976 if (req->ring_index == req->length) { 2977 req->ring_index = 0; 2978 req->ring_ptr = req->ring; 2979 } else { 2980 req->ring_ptr++; 2981 } 2982 2983 cont_pkt = (cont_a64_entry_t *)req->ring_ptr; 2984 2985 /* Load packet defaults. */ 2986 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00; 2987 2988 return cont_pkt; 2989 } 2990 2991 static inline void 2992 qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt, 2993 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt) 2994 { 2995 uint16_t avail_dsds; 2996 struct dsd64 *cur_dsd; 2997 scsi_qla_host_t *vha; 2998 struct scsi_cmnd *cmd; 2999 struct scatterlist *sg; 3000 int i, cont; 3001 struct req_que *req; 3002 cont_a64_entry_t lcont_pkt; 3003 cont_a64_entry_t *cont_pkt; 3004 3005 vha = sp->vha; 3006 req = vha->req; 3007 3008 cmd = GET_CMD_SP(sp); 3009 cont = 0; 3010 cont_pkt = NULL; 3011 3012 /* Update entry type to indicate Command Type 3 IOCB */ 3013 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7; 3014 3015 /* No data transfer */ 3016 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 3017 lcmd_pkt->byte_count = cpu_to_le32(0); 3018 return; 3019 } 3020 3021 /* Set transfer direction */ 3022 if (cmd->sc_data_direction == DMA_TO_DEVICE) { 3023 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA; 3024 vha->qla_stats.output_bytes += scsi_bufflen(cmd); 3025 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 3026 lcmd_pkt->cntrl_flags = TMF_READ_DATA; 3027 vha->qla_stats.input_bytes += scsi_bufflen(cmd); 3028 } 3029 3030 /* One DSD is available in the Command Type 3 IOCB */ 3031 avail_dsds = 1; 3032 cur_dsd = &lcmd_pkt->dsd; 3033 3034 /* Load data segments */ 3035 scsi_for_each_sg(cmd, sg, tot_dsds, i) { 3036 /* Allocate additional continuation packets? */ 3037 if (avail_dsds == 0) { 3038 /* 3039 * Five DSDs are available in the Continuation 3040 * Type 1 IOCB. 3041 */ 3042 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE); 3043 cont_pkt = 3044 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt); 3045 cur_dsd = lcont_pkt.dsd; 3046 avail_dsds = 5; 3047 cont = 1; 3048 } 3049 3050 append_dsd64(&cur_dsd, sg); 3051 avail_dsds--; 3052 if (avail_dsds == 0 && cont == 1) { 3053 cont = 0; 3054 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt, 3055 sizeof(lcont_pkt)); 3056 } 3057 3058 } 3059 if (avail_dsds != 0 && cont == 1) { 3060 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt, 3061 sizeof(lcont_pkt)); 3062 } 3063 } 3064 3065 /** 3066 * qlafx00_start_scsi() - Send a SCSI command to the ISP 3067 * @sp: command to send to the ISP 3068 * 3069 * Returns non-zero if a failure occurred, else zero. 3070 */ 3071 int 3072 qlafx00_start_scsi(srb_t *sp) 3073 { 3074 int nseg; 3075 unsigned long flags; 3076 uint32_t index; 3077 uint32_t handle; 3078 uint16_t cnt; 3079 uint16_t req_cnt; 3080 uint16_t tot_dsds; 3081 struct req_que *req = NULL; 3082 struct rsp_que *rsp = NULL; 3083 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 3084 struct scsi_qla_host *vha = sp->vha; 3085 struct qla_hw_data *ha = vha->hw; 3086 struct cmd_type_7_fx00 *cmd_pkt; 3087 struct cmd_type_7_fx00 lcmd_pkt; 3088 struct scsi_lun llun; 3089 3090 /* Setup device pointers. */ 3091 rsp = ha->rsp_q_map[0]; 3092 req = vha->req; 3093 3094 /* So we know we haven't pci_map'ed anything yet */ 3095 tot_dsds = 0; 3096 3097 /* Acquire ring specific lock */ 3098 spin_lock_irqsave(&ha->hardware_lock, flags); 3099 3100 /* Check for room in outstanding command list. */ 3101 handle = req->current_outstanding_cmd; 3102 for (index = 1; index < req->num_outstanding_cmds; index++) { 3103 handle++; 3104 if (handle == req->num_outstanding_cmds) 3105 handle = 1; 3106 if (!req->outstanding_cmds[handle]) 3107 break; 3108 } 3109 if (index == req->num_outstanding_cmds) 3110 goto queuing_error; 3111 3112 /* Map the sg table so we have an accurate count of sg entries needed */ 3113 if (scsi_sg_count(cmd)) { 3114 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 3115 scsi_sg_count(cmd), cmd->sc_data_direction); 3116 if (unlikely(!nseg)) 3117 goto queuing_error; 3118 } else 3119 nseg = 0; 3120 3121 tot_dsds = nseg; 3122 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); 3123 if (req->cnt < (req_cnt + 2)) { 3124 cnt = RD_REG_DWORD_RELAXED(req->req_q_out); 3125 3126 if (req->ring_index < cnt) 3127 req->cnt = cnt - req->ring_index; 3128 else 3129 req->cnt = req->length - 3130 (req->ring_index - cnt); 3131 if (req->cnt < (req_cnt + 2)) 3132 goto queuing_error; 3133 } 3134 3135 /* Build command packet. */ 3136 req->current_outstanding_cmd = handle; 3137 req->outstanding_cmds[handle] = sp; 3138 sp->handle = handle; 3139 cmd->host_scribble = (unsigned char *)(unsigned long)handle; 3140 req->cnt -= req_cnt; 3141 3142 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr; 3143 3144 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE); 3145 3146 lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle); 3147 lcmd_pkt.reserved_0 = 0; 3148 lcmd_pkt.port_path_ctrl = 0; 3149 lcmd_pkt.reserved_1 = 0; 3150 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds); 3151 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id); 3152 3153 int_to_scsilun(cmd->device->lun, &llun); 3154 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun, 3155 sizeof(lcmd_pkt.lun)); 3156 3157 /* Load SCSI command packet. */ 3158 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb)); 3159 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 3160 3161 /* Build IOCB segments */ 3162 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt); 3163 3164 /* Set total data segment count. */ 3165 lcmd_pkt.entry_count = (uint8_t)req_cnt; 3166 3167 /* Specify response queue number where completion should happen */ 3168 lcmd_pkt.entry_status = (uint8_t) rsp->id; 3169 3170 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e, 3171 cmd->cmnd, cmd->cmd_len); 3172 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032, 3173 &lcmd_pkt, sizeof(lcmd_pkt)); 3174 3175 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE); 3176 wmb(); 3177 3178 /* Adjust ring index. */ 3179 req->ring_index++; 3180 if (req->ring_index == req->length) { 3181 req->ring_index = 0; 3182 req->ring_ptr = req->ring; 3183 } else 3184 req->ring_ptr++; 3185 3186 sp->flags |= SRB_DMA_VALID; 3187 3188 /* Set chip new ring index. */ 3189 WRT_REG_DWORD(req->req_q_in, req->ring_index); 3190 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code); 3191 3192 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3193 return QLA_SUCCESS; 3194 3195 queuing_error: 3196 if (tot_dsds) 3197 scsi_dma_unmap(cmd); 3198 3199 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3200 3201 return QLA_FUNCTION_FAILED; 3202 } 3203 3204 void 3205 qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb) 3206 { 3207 struct srb_iocb *fxio = &sp->u.iocb_cmd; 3208 scsi_qla_host_t *vha = sp->vha; 3209 struct req_que *req = vha->req; 3210 struct tsk_mgmt_entry_fx00 tm_iocb; 3211 struct scsi_lun llun; 3212 3213 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00)); 3214 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00; 3215 tm_iocb.entry_count = 1; 3216 tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle)); 3217 tm_iocb.reserved_0 = 0; 3218 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id); 3219 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags); 3220 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) { 3221 int_to_scsilun(fxio->u.tmf.lun, &llun); 3222 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun, 3223 sizeof(struct scsi_lun)); 3224 } 3225 3226 memcpy((void *)ptm_iocb, &tm_iocb, 3227 sizeof(struct tsk_mgmt_entry_fx00)); 3228 wmb(); 3229 } 3230 3231 void 3232 qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb) 3233 { 3234 struct srb_iocb *fxio = &sp->u.iocb_cmd; 3235 scsi_qla_host_t *vha = sp->vha; 3236 struct req_que *req = vha->req; 3237 struct abort_iocb_entry_fx00 abt_iocb; 3238 3239 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00)); 3240 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00; 3241 abt_iocb.entry_count = 1; 3242 abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle)); 3243 abt_iocb.abort_handle = 3244 cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl)); 3245 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id); 3246 abt_iocb.req_que_no = cpu_to_le16(req->id); 3247 3248 memcpy((void *)pabt_iocb, &abt_iocb, 3249 sizeof(struct abort_iocb_entry_fx00)); 3250 wmb(); 3251 } 3252 3253 void 3254 qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb) 3255 { 3256 struct srb_iocb *fxio = &sp->u.iocb_cmd; 3257 struct qla_mt_iocb_rqst_fx00 *piocb_rqst; 3258 struct bsg_job *bsg_job; 3259 struct fc_bsg_request *bsg_request; 3260 struct fxdisc_entry_fx00 fx_iocb; 3261 uint8_t entry_cnt = 1; 3262 3263 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00)); 3264 fx_iocb.entry_type = FX00_IOCB_TYPE; 3265 fx_iocb.handle = cpu_to_le32(sp->handle); 3266 fx_iocb.entry_count = entry_cnt; 3267 3268 if (sp->type == SRB_FXIOCB_DCMD) { 3269 fx_iocb.func_num = 3270 sp->u.iocb_cmd.u.fxiocb.req_func_type; 3271 fx_iocb.adapid = fxio->u.fxiocb.adapter_id; 3272 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi; 3273 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0; 3274 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1; 3275 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra; 3276 3277 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) { 3278 fx_iocb.req_dsdcnt = cpu_to_le16(1); 3279 fx_iocb.req_xfrcnt = 3280 cpu_to_le16(fxio->u.fxiocb.req_len); 3281 put_unaligned_le64(fxio->u.fxiocb.req_dma_handle, 3282 &fx_iocb.dseg_rq.address); 3283 fx_iocb.dseg_rq.length = 3284 cpu_to_le32(fxio->u.fxiocb.req_len); 3285 } 3286 3287 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) { 3288 fx_iocb.rsp_dsdcnt = cpu_to_le16(1); 3289 fx_iocb.rsp_xfrcnt = 3290 cpu_to_le16(fxio->u.fxiocb.rsp_len); 3291 put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle, 3292 &fx_iocb.dseg_rsp.address); 3293 fx_iocb.dseg_rsp.length = 3294 cpu_to_le32(fxio->u.fxiocb.rsp_len); 3295 } 3296 3297 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) { 3298 fx_iocb.dataword = fxio->u.fxiocb.req_data; 3299 } 3300 fx_iocb.flags = fxio->u.fxiocb.flags; 3301 } else { 3302 struct scatterlist *sg; 3303 3304 bsg_job = sp->u.bsg_job; 3305 bsg_request = bsg_job->request; 3306 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *) 3307 &bsg_request->rqst_data.h_vendor.vendor_cmd[1]; 3308 3309 fx_iocb.func_num = piocb_rqst->func_type; 3310 fx_iocb.adapid = piocb_rqst->adapid; 3311 fx_iocb.adapid_hi = piocb_rqst->adapid_hi; 3312 fx_iocb.reserved_0 = piocb_rqst->reserved_0; 3313 fx_iocb.reserved_1 = piocb_rqst->reserved_1; 3314 fx_iocb.dataword_extra = piocb_rqst->dataword_extra; 3315 fx_iocb.dataword = piocb_rqst->dataword; 3316 fx_iocb.req_xfrcnt = piocb_rqst->req_len; 3317 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len; 3318 3319 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) { 3320 int avail_dsds, tot_dsds; 3321 cont_a64_entry_t lcont_pkt; 3322 cont_a64_entry_t *cont_pkt = NULL; 3323 struct dsd64 *cur_dsd; 3324 int index = 0, cont = 0; 3325 3326 fx_iocb.req_dsdcnt = 3327 cpu_to_le16(bsg_job->request_payload.sg_cnt); 3328 tot_dsds = 3329 bsg_job->request_payload.sg_cnt; 3330 cur_dsd = &fx_iocb.dseg_rq; 3331 avail_dsds = 1; 3332 for_each_sg(bsg_job->request_payload.sg_list, sg, 3333 tot_dsds, index) { 3334 /* Allocate additional continuation packets? */ 3335 if (avail_dsds == 0) { 3336 /* 3337 * Five DSDs are available in the Cont. 3338 * Type 1 IOCB. 3339 */ 3340 memset(&lcont_pkt, 0, 3341 REQUEST_ENTRY_SIZE); 3342 cont_pkt = 3343 qlafx00_prep_cont_type1_iocb( 3344 sp->vha->req, &lcont_pkt); 3345 cur_dsd = lcont_pkt.dsd; 3346 avail_dsds = 5; 3347 cont = 1; 3348 entry_cnt++; 3349 } 3350 3351 append_dsd64(&cur_dsd, sg); 3352 avail_dsds--; 3353 3354 if (avail_dsds == 0 && cont == 1) { 3355 cont = 0; 3356 memcpy_toio( 3357 (void __iomem *)cont_pkt, 3358 &lcont_pkt, REQUEST_ENTRY_SIZE); 3359 ql_dump_buffer( 3360 ql_dbg_user + ql_dbg_verbose, 3361 sp->vha, 0x3042, 3362 (uint8_t *)&lcont_pkt, 3363 REQUEST_ENTRY_SIZE); 3364 } 3365 } 3366 if (avail_dsds != 0 && cont == 1) { 3367 memcpy_toio((void __iomem *)cont_pkt, 3368 &lcont_pkt, REQUEST_ENTRY_SIZE); 3369 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, 3370 sp->vha, 0x3043, 3371 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE); 3372 } 3373 } 3374 3375 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) { 3376 int avail_dsds, tot_dsds; 3377 cont_a64_entry_t lcont_pkt; 3378 cont_a64_entry_t *cont_pkt = NULL; 3379 struct dsd64 *cur_dsd; 3380 int index = 0, cont = 0; 3381 3382 fx_iocb.rsp_dsdcnt = 3383 cpu_to_le16(bsg_job->reply_payload.sg_cnt); 3384 tot_dsds = bsg_job->reply_payload.sg_cnt; 3385 cur_dsd = &fx_iocb.dseg_rsp; 3386 avail_dsds = 1; 3387 3388 for_each_sg(bsg_job->reply_payload.sg_list, sg, 3389 tot_dsds, index) { 3390 /* Allocate additional continuation packets? */ 3391 if (avail_dsds == 0) { 3392 /* 3393 * Five DSDs are available in the Cont. 3394 * Type 1 IOCB. 3395 */ 3396 memset(&lcont_pkt, 0, 3397 REQUEST_ENTRY_SIZE); 3398 cont_pkt = 3399 qlafx00_prep_cont_type1_iocb( 3400 sp->vha->req, &lcont_pkt); 3401 cur_dsd = lcont_pkt.dsd; 3402 avail_dsds = 5; 3403 cont = 1; 3404 entry_cnt++; 3405 } 3406 3407 append_dsd64(&cur_dsd, sg); 3408 avail_dsds--; 3409 3410 if (avail_dsds == 0 && cont == 1) { 3411 cont = 0; 3412 memcpy_toio((void __iomem *)cont_pkt, 3413 &lcont_pkt, 3414 REQUEST_ENTRY_SIZE); 3415 ql_dump_buffer( 3416 ql_dbg_user + ql_dbg_verbose, 3417 sp->vha, 0x3045, 3418 (uint8_t *)&lcont_pkt, 3419 REQUEST_ENTRY_SIZE); 3420 } 3421 } 3422 if (avail_dsds != 0 && cont == 1) { 3423 memcpy_toio((void __iomem *)cont_pkt, 3424 &lcont_pkt, REQUEST_ENTRY_SIZE); 3425 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, 3426 sp->vha, 0x3046, 3427 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE); 3428 } 3429 } 3430 3431 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID) 3432 fx_iocb.dataword = piocb_rqst->dataword; 3433 fx_iocb.flags = piocb_rqst->flags; 3434 fx_iocb.entry_count = entry_cnt; 3435 } 3436 3437 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, 3438 sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb)); 3439 3440 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb)); 3441 wmb(); 3442 } 3443