1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 struct rom_cmd { 14 uint16_t cmd; 15 } rom_cmds[] = { 16 { MBC_LOAD_RAM }, 17 { MBC_EXECUTE_FIRMWARE }, 18 { MBC_READ_RAM_WORD }, 19 { MBC_MAILBOX_REGISTER_TEST }, 20 { MBC_VERIFY_CHECKSUM }, 21 { MBC_GET_FIRMWARE_VERSION }, 22 { MBC_LOAD_RISC_RAM }, 23 { MBC_DUMP_RISC_RAM }, 24 { MBC_LOAD_RISC_RAM_EXTENDED }, 25 { MBC_DUMP_RISC_RAM_EXTENDED }, 26 { MBC_WRITE_RAM_WORD_EXTENDED }, 27 { MBC_READ_RAM_EXTENDED }, 28 { MBC_GET_RESOURCE_COUNTS }, 29 { MBC_SET_FIRMWARE_OPTION }, 30 { MBC_MID_INITIALIZE_FIRMWARE }, 31 { MBC_GET_FIRMWARE_STATE }, 32 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT }, 33 { MBC_GET_RETRY_COUNT }, 34 { MBC_TRACE_CONTROL }, 35 }; 36 37 static int is_rom_cmd(uint16_t cmd) 38 { 39 int i; 40 struct rom_cmd *wc; 41 42 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) { 43 wc = rom_cmds + i; 44 if (wc->cmd == cmd) 45 return 1; 46 } 47 48 return 0; 49 } 50 51 /* 52 * qla2x00_mailbox_command 53 * Issue mailbox command and waits for completion. 54 * 55 * Input: 56 * ha = adapter block pointer. 57 * mcp = driver internal mbx struct pointer. 58 * 59 * Output: 60 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 61 * 62 * Returns: 63 * 0 : QLA_SUCCESS = cmd performed success 64 * 1 : QLA_FUNCTION_FAILED (error encountered) 65 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 66 * 67 * Context: 68 * Kernel context. 69 */ 70 static int 71 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 72 { 73 int rval, i; 74 unsigned long flags = 0; 75 device_reg_t *reg; 76 uint8_t abort_active; 77 uint8_t io_lock_on; 78 uint16_t command = 0; 79 uint16_t *iptr; 80 uint16_t __iomem *optr; 81 uint32_t cnt; 82 uint32_t mboxes; 83 uint16_t __iomem *mbx_reg; 84 unsigned long wait_time; 85 struct qla_hw_data *ha = vha->hw; 86 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 87 88 89 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 90 91 if (ha->pdev->error_state > pci_channel_io_frozen) { 92 ql_log(ql_log_warn, vha, 0x1001, 93 "error_state is greater than pci_channel_io_frozen, " 94 "exiting.\n"); 95 return QLA_FUNCTION_TIMEOUT; 96 } 97 98 if (vha->device_flags & DFLG_DEV_FAILED) { 99 ql_log(ql_log_warn, vha, 0x1002, 100 "Device in failed state, exiting.\n"); 101 return QLA_FUNCTION_TIMEOUT; 102 } 103 104 /* if PCI error, then avoid mbx processing.*/ 105 if (test_bit(PCI_ERR, &base_vha->dpc_flags)) { 106 ql_log(ql_log_warn, vha, 0x1191, 107 "PCI error, exiting.\n"); 108 return QLA_FUNCTION_TIMEOUT; 109 } 110 111 reg = ha->iobase; 112 io_lock_on = base_vha->flags.init_done; 113 114 rval = QLA_SUCCESS; 115 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 116 117 118 if (ha->flags.pci_channel_io_perm_failure) { 119 ql_log(ql_log_warn, vha, 0x1003, 120 "Perm failure on EEH timeout MBX, exiting.\n"); 121 return QLA_FUNCTION_TIMEOUT; 122 } 123 124 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 125 /* Setting Link-Down error */ 126 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 127 ql_log(ql_log_warn, vha, 0x1004, 128 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 129 return QLA_FUNCTION_TIMEOUT; 130 } 131 132 /* check if ISP abort is active and return cmd with timeout */ 133 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 134 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 135 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) && 136 !is_rom_cmd(mcp->mb[0])) { 137 ql_log(ql_log_info, vha, 0x1005, 138 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n", 139 mcp->mb[0]); 140 return QLA_FUNCTION_TIMEOUT; 141 } 142 143 /* 144 * Wait for active mailbox commands to finish by waiting at most tov 145 * seconds. This is to serialize actual issuing of mailbox cmds during 146 * non ISP abort time. 147 */ 148 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 149 /* Timeout occurred. Return error. */ 150 ql_log(ql_log_warn, vha, 0x1005, 151 "Cmd access timeout, cmd=0x%x, Exiting.\n", 152 mcp->mb[0]); 153 return QLA_FUNCTION_TIMEOUT; 154 } 155 156 ha->flags.mbox_busy = 1; 157 /* Save mailbox command for debug */ 158 ha->mcp = mcp; 159 160 ql_dbg(ql_dbg_mbx, vha, 0x1006, 161 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 162 163 spin_lock_irqsave(&ha->hardware_lock, flags); 164 165 /* Load mailbox registers. */ 166 if (IS_P3P_TYPE(ha)) 167 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 168 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 169 optr = (uint16_t __iomem *)®->isp24.mailbox0; 170 else 171 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 172 173 iptr = mcp->mb; 174 command = mcp->mb[0]; 175 mboxes = mcp->out_mb; 176 177 ql_dbg(ql_dbg_mbx, vha, 0x1111, 178 "Mailbox registers (OUT):\n"); 179 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 180 if (IS_QLA2200(ha) && cnt == 8) 181 optr = 182 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 183 if (mboxes & BIT_0) { 184 ql_dbg(ql_dbg_mbx, vha, 0x1112, 185 "mbox[%d]<-0x%04x\n", cnt, *iptr); 186 WRT_REG_WORD(optr, *iptr); 187 } 188 189 mboxes >>= 1; 190 optr++; 191 iptr++; 192 } 193 194 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 195 "I/O Address = %p.\n", optr); 196 197 /* Issue set host interrupt command to send cmd out. */ 198 ha->flags.mbox_int = 0; 199 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 200 201 /* Unlock mbx registers and wait for interrupt */ 202 ql_dbg(ql_dbg_mbx, vha, 0x100f, 203 "Going to unlock irq & waiting for interrupts. " 204 "jiffies=%lx.\n", jiffies); 205 206 /* Wait for mbx cmd completion until timeout */ 207 208 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 209 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 210 211 if (IS_P3P_TYPE(ha)) { 212 if (RD_REG_DWORD(®->isp82.hint) & 213 HINT_MBX_INT_PENDING) { 214 spin_unlock_irqrestore(&ha->hardware_lock, 215 flags); 216 ha->flags.mbox_busy = 0; 217 ql_dbg(ql_dbg_mbx, vha, 0x1010, 218 "Pending mailbox timeout, exiting.\n"); 219 rval = QLA_FUNCTION_TIMEOUT; 220 goto premature_exit; 221 } 222 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 223 } else if (IS_FWI2_CAPABLE(ha)) 224 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 225 else 226 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 227 spin_unlock_irqrestore(&ha->hardware_lock, flags); 228 229 wait_time = jiffies; 230 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 231 mcp->tov * HZ)) { 232 ql_dbg(ql_dbg_mbx, vha, 0x117a, 233 "cmd=%x Timeout.\n", command); 234 spin_lock_irqsave(&ha->hardware_lock, flags); 235 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 236 spin_unlock_irqrestore(&ha->hardware_lock, flags); 237 } 238 if (time_after(jiffies, wait_time + 5 * HZ)) 239 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n", 240 command, jiffies_to_msecs(jiffies - wait_time)); 241 } else { 242 ql_dbg(ql_dbg_mbx, vha, 0x1011, 243 "Cmd=%x Polling Mode.\n", command); 244 245 if (IS_P3P_TYPE(ha)) { 246 if (RD_REG_DWORD(®->isp82.hint) & 247 HINT_MBX_INT_PENDING) { 248 spin_unlock_irqrestore(&ha->hardware_lock, 249 flags); 250 ha->flags.mbox_busy = 0; 251 ql_dbg(ql_dbg_mbx, vha, 0x1012, 252 "Pending mailbox timeout, exiting.\n"); 253 rval = QLA_FUNCTION_TIMEOUT; 254 goto premature_exit; 255 } 256 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 257 } else if (IS_FWI2_CAPABLE(ha)) 258 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 259 else 260 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 261 spin_unlock_irqrestore(&ha->hardware_lock, flags); 262 263 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 264 while (!ha->flags.mbox_int) { 265 if (time_after(jiffies, wait_time)) 266 break; 267 268 /* Check for pending interrupts. */ 269 qla2x00_poll(ha->rsp_q_map[0]); 270 271 if (!ha->flags.mbox_int && 272 !(IS_QLA2200(ha) && 273 command == MBC_LOAD_RISC_RAM_EXTENDED)) 274 msleep(10); 275 } /* while */ 276 ql_dbg(ql_dbg_mbx, vha, 0x1013, 277 "Waited %d sec.\n", 278 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 279 } 280 281 /* Check whether we timed out */ 282 if (ha->flags.mbox_int) { 283 uint16_t *iptr2; 284 285 ql_dbg(ql_dbg_mbx, vha, 0x1014, 286 "Cmd=%x completed.\n", command); 287 288 /* Got interrupt. Clear the flag. */ 289 ha->flags.mbox_int = 0; 290 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 291 292 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 293 ha->flags.mbox_busy = 0; 294 /* Setting Link-Down error */ 295 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 296 ha->mcp = NULL; 297 rval = QLA_FUNCTION_FAILED; 298 ql_log(ql_log_warn, vha, 0x1015, 299 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 300 goto premature_exit; 301 } 302 303 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 304 rval = QLA_FUNCTION_FAILED; 305 306 /* Load return mailbox registers. */ 307 iptr2 = mcp->mb; 308 iptr = (uint16_t *)&ha->mailbox_out[0]; 309 mboxes = mcp->in_mb; 310 311 ql_dbg(ql_dbg_mbx, vha, 0x1113, 312 "Mailbox registers (IN):\n"); 313 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 314 if (mboxes & BIT_0) { 315 *iptr2 = *iptr; 316 ql_dbg(ql_dbg_mbx, vha, 0x1114, 317 "mbox[%d]->0x%04x\n", cnt, *iptr2); 318 } 319 320 mboxes >>= 1; 321 iptr2++; 322 iptr++; 323 } 324 } else { 325 326 uint16_t mb0; 327 uint32_t ictrl; 328 uint16_t w; 329 330 if (IS_FWI2_CAPABLE(ha)) { 331 mb0 = RD_REG_WORD(®->isp24.mailbox0); 332 ictrl = RD_REG_DWORD(®->isp24.ictrl); 333 } else { 334 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 335 ictrl = RD_REG_WORD(®->isp.ictrl); 336 } 337 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 338 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 339 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0); 340 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 341 342 /* Capture FW dump only, if PCI device active */ 343 if (!pci_channel_offline(vha->hw->pdev)) { 344 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 345 if (w == 0xffff || ictrl == 0xffffffff) { 346 /* This is special case if there is unload 347 * of driver happening and if PCI device go 348 * into bad state due to PCI error condition 349 * then only PCI ERR flag would be set. 350 * we will do premature exit for above case. 351 */ 352 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 353 set_bit(PCI_ERR, &base_vha->dpc_flags); 354 ha->flags.mbox_busy = 0; 355 rval = QLA_FUNCTION_TIMEOUT; 356 goto premature_exit; 357 } 358 359 /* Attempt to capture firmware dump for further 360 * anallysis of the current formware state. we do not 361 * need to do this if we are intentionally generating 362 * a dump 363 */ 364 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 365 ha->isp_ops->fw_dump(vha, 0); 366 rval = QLA_FUNCTION_TIMEOUT; 367 } 368 } 369 370 ha->flags.mbox_busy = 0; 371 372 /* Clean up */ 373 ha->mcp = NULL; 374 375 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 376 ql_dbg(ql_dbg_mbx, vha, 0x101a, 377 "Checking for additional resp interrupt.\n"); 378 379 /* polling mode for non isp_abort commands. */ 380 qla2x00_poll(ha->rsp_q_map[0]); 381 } 382 383 if (rval == QLA_FUNCTION_TIMEOUT && 384 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 385 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 386 ha->flags.eeh_busy) { 387 /* not in dpc. schedule it for dpc to take over. */ 388 ql_dbg(ql_dbg_mbx, vha, 0x101b, 389 "Timeout, schedule isp_abort_needed.\n"); 390 391 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 392 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 393 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 394 if (IS_QLA82XX(ha)) { 395 ql_dbg(ql_dbg_mbx, vha, 0x112a, 396 "disabling pause transmit on port " 397 "0 & 1.\n"); 398 qla82xx_wr_32(ha, 399 QLA82XX_CRB_NIU + 0x98, 400 CRB_NIU_XG_PAUSE_CTL_P0| 401 CRB_NIU_XG_PAUSE_CTL_P1); 402 } 403 ql_log(ql_log_info, base_vha, 0x101c, 404 "Mailbox cmd timeout occurred, cmd=0x%x, " 405 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 406 "abort.\n", command, mcp->mb[0], 407 ha->flags.eeh_busy); 408 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 409 qla2xxx_wake_dpc(vha); 410 } 411 } else if (!abort_active) { 412 /* call abort directly since we are in the DPC thread */ 413 ql_dbg(ql_dbg_mbx, vha, 0x101d, 414 "Timeout, calling abort_isp.\n"); 415 416 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 417 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 418 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 419 if (IS_QLA82XX(ha)) { 420 ql_dbg(ql_dbg_mbx, vha, 0x112b, 421 "disabling pause transmit on port " 422 "0 & 1.\n"); 423 qla82xx_wr_32(ha, 424 QLA82XX_CRB_NIU + 0x98, 425 CRB_NIU_XG_PAUSE_CTL_P0| 426 CRB_NIU_XG_PAUSE_CTL_P1); 427 } 428 ql_log(ql_log_info, base_vha, 0x101e, 429 "Mailbox cmd timeout occurred, cmd=0x%x, " 430 "mb[0]=0x%x. Scheduling ISP abort ", 431 command, mcp->mb[0]); 432 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 433 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 434 /* Allow next mbx cmd to come in. */ 435 complete(&ha->mbx_cmd_comp); 436 if (ha->isp_ops->abort_isp(vha)) { 437 /* Failed. retry later. */ 438 set_bit(ISP_ABORT_NEEDED, 439 &vha->dpc_flags); 440 } 441 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 442 ql_dbg(ql_dbg_mbx, vha, 0x101f, 443 "Finished abort_isp.\n"); 444 goto mbx_done; 445 } 446 } 447 } 448 449 premature_exit: 450 /* Allow next mbx cmd to come in. */ 451 complete(&ha->mbx_cmd_comp); 452 453 mbx_done: 454 if (rval) { 455 ql_dbg(ql_dbg_disc, base_vha, 0x1020, 456 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 457 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 458 459 ql_dbg(ql_dbg_mbx, vha, 0x1198, 460 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n", 461 RD_REG_DWORD(®->isp24.host_status), 462 ha->fw_dump_cap_flags, 463 RD_REG_DWORD(®->isp24.ictrl), 464 RD_REG_DWORD(®->isp24.istatus)); 465 466 mbx_reg = ®->isp24.mailbox0; 467 for (i = 0; i < 6; i++) 468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199, 469 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 470 } else { 471 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 472 } 473 474 return rval; 475 } 476 477 int 478 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 479 uint32_t risc_code_size) 480 { 481 int rval; 482 struct qla_hw_data *ha = vha->hw; 483 mbx_cmd_t mc; 484 mbx_cmd_t *mcp = &mc; 485 486 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 487 "Entered %s.\n", __func__); 488 489 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 490 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 491 mcp->mb[8] = MSW(risc_addr); 492 mcp->out_mb = MBX_8|MBX_0; 493 } else { 494 mcp->mb[0] = MBC_LOAD_RISC_RAM; 495 mcp->out_mb = MBX_0; 496 } 497 mcp->mb[1] = LSW(risc_addr); 498 mcp->mb[2] = MSW(req_dma); 499 mcp->mb[3] = LSW(req_dma); 500 mcp->mb[6] = MSW(MSD(req_dma)); 501 mcp->mb[7] = LSW(MSD(req_dma)); 502 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 503 if (IS_FWI2_CAPABLE(ha)) { 504 mcp->mb[4] = MSW(risc_code_size); 505 mcp->mb[5] = LSW(risc_code_size); 506 mcp->out_mb |= MBX_5|MBX_4; 507 } else { 508 mcp->mb[4] = LSW(risc_code_size); 509 mcp->out_mb |= MBX_4; 510 } 511 512 mcp->in_mb = MBX_0; 513 mcp->tov = MBX_TOV_SECONDS; 514 mcp->flags = 0; 515 rval = qla2x00_mailbox_command(vha, mcp); 516 517 if (rval != QLA_SUCCESS) { 518 ql_dbg(ql_dbg_mbx, vha, 0x1023, 519 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 520 } else { 521 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 522 "Done %s.\n", __func__); 523 } 524 525 return rval; 526 } 527 528 #define EXTENDED_BB_CREDITS BIT_0 529 /* 530 * qla2x00_execute_fw 531 * Start adapter firmware. 532 * 533 * Input: 534 * ha = adapter block pointer. 535 * TARGET_QUEUE_LOCK must be released. 536 * ADAPTER_STATE_LOCK must be released. 537 * 538 * Returns: 539 * qla2x00 local function return status code. 540 * 541 * Context: 542 * Kernel context. 543 */ 544 int 545 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 546 { 547 int rval; 548 struct qla_hw_data *ha = vha->hw; 549 mbx_cmd_t mc; 550 mbx_cmd_t *mcp = &mc; 551 552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 553 "Entered %s.\n", __func__); 554 555 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 556 mcp->out_mb = MBX_0; 557 mcp->in_mb = MBX_0; 558 if (IS_FWI2_CAPABLE(ha)) { 559 mcp->mb[1] = MSW(risc_addr); 560 mcp->mb[2] = LSW(risc_addr); 561 mcp->mb[3] = 0; 562 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 563 IS_QLA27XX(ha)) { 564 struct nvram_81xx *nv = ha->nvram; 565 mcp->mb[4] = (nv->enhanced_features & 566 EXTENDED_BB_CREDITS); 567 } else 568 mcp->mb[4] = 0; 569 570 if (ha->flags.exlogins_enabled) 571 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN; 572 573 if (ha->flags.exchoffld_enabled) 574 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD; 575 576 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 577 mcp->in_mb |= MBX_1; 578 } else { 579 mcp->mb[1] = LSW(risc_addr); 580 mcp->out_mb |= MBX_1; 581 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 582 mcp->mb[2] = 0; 583 mcp->out_mb |= MBX_2; 584 } 585 } 586 587 mcp->tov = MBX_TOV_SECONDS; 588 mcp->flags = 0; 589 rval = qla2x00_mailbox_command(vha, mcp); 590 591 if (rval != QLA_SUCCESS) { 592 ql_dbg(ql_dbg_mbx, vha, 0x1026, 593 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 594 } else { 595 if (IS_FWI2_CAPABLE(ha)) { 596 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 597 "Done exchanges=%x.\n", mcp->mb[1]); 598 } else { 599 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 600 "Done %s.\n", __func__); 601 } 602 } 603 604 return rval; 605 } 606 607 /* 608 * qla_get_exlogin_status 609 * Get extended login status 610 * uses the memory offload control/status Mailbox 611 * 612 * Input: 613 * ha: adapter state pointer. 614 * fwopt: firmware options 615 * 616 * Returns: 617 * qla2x00 local function status 618 * 619 * Context: 620 * Kernel context. 621 */ 622 #define FETCH_XLOGINS_STAT 0x8 623 int 624 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 625 uint16_t *ex_logins_cnt) 626 { 627 int rval; 628 mbx_cmd_t mc; 629 mbx_cmd_t *mcp = &mc; 630 631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f, 632 "Entered %s\n", __func__); 633 634 memset(mcp->mb, 0 , sizeof(mcp->mb)); 635 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 636 mcp->mb[1] = FETCH_XLOGINS_STAT; 637 mcp->out_mb = MBX_1|MBX_0; 638 mcp->in_mb = MBX_10|MBX_4|MBX_0; 639 mcp->tov = MBX_TOV_SECONDS; 640 mcp->flags = 0; 641 642 rval = qla2x00_mailbox_command(vha, mcp); 643 if (rval != QLA_SUCCESS) { 644 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval); 645 } else { 646 *buf_sz = mcp->mb[4]; 647 *ex_logins_cnt = mcp->mb[10]; 648 649 ql_log(ql_log_info, vha, 0x1190, 650 "buffer size 0x%x, exchange login count=%d\n", 651 mcp->mb[4], mcp->mb[10]); 652 653 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116, 654 "Done %s.\n", __func__); 655 } 656 657 return rval; 658 } 659 660 /* 661 * qla_set_exlogin_mem_cfg 662 * set extended login memory configuration 663 * Mbx needs to be issues before init_cb is set 664 * 665 * Input: 666 * ha: adapter state pointer. 667 * buffer: buffer pointer 668 * phys_addr: physical address of buffer 669 * size: size of buffer 670 * TARGET_QUEUE_LOCK must be released 671 * ADAPTER_STATE_LOCK must be release 672 * 673 * Returns: 674 * qla2x00 local funxtion status code. 675 * 676 * Context: 677 * Kernel context. 678 */ 679 #define CONFIG_XLOGINS_MEM 0x3 680 int 681 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 682 { 683 int rval; 684 mbx_cmd_t mc; 685 mbx_cmd_t *mcp = &mc; 686 struct qla_hw_data *ha = vha->hw; 687 int configured_count; 688 689 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a, 690 "Entered %s.\n", __func__); 691 692 memset(mcp->mb, 0 , sizeof(mcp->mb)); 693 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 694 mcp->mb[1] = CONFIG_XLOGINS_MEM; 695 mcp->mb[2] = MSW(phys_addr); 696 mcp->mb[3] = LSW(phys_addr); 697 mcp->mb[6] = MSW(MSD(phys_addr)); 698 mcp->mb[7] = LSW(MSD(phys_addr)); 699 mcp->mb[8] = MSW(ha->exlogin_size); 700 mcp->mb[9] = LSW(ha->exlogin_size); 701 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 702 mcp->in_mb = MBX_11|MBX_0; 703 mcp->tov = MBX_TOV_SECONDS; 704 mcp->flags = 0; 705 rval = qla2x00_mailbox_command(vha, mcp); 706 if (rval != QLA_SUCCESS) { 707 /*EMPTY*/ 708 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval); 709 } else { 710 configured_count = mcp->mb[11]; 711 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 712 "Done %s.\n", __func__); 713 } 714 715 return rval; 716 } 717 718 /* 719 * qla_get_exchoffld_status 720 * Get exchange offload status 721 * uses the memory offload control/status Mailbox 722 * 723 * Input: 724 * ha: adapter state pointer. 725 * fwopt: firmware options 726 * 727 * Returns: 728 * qla2x00 local function status 729 * 730 * Context: 731 * Kernel context. 732 */ 733 #define FETCH_XCHOFFLD_STAT 0x2 734 int 735 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 736 uint16_t *ex_logins_cnt) 737 { 738 int rval; 739 mbx_cmd_t mc; 740 mbx_cmd_t *mcp = &mc; 741 742 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019, 743 "Entered %s\n", __func__); 744 745 memset(mcp->mb, 0 , sizeof(mcp->mb)); 746 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 747 mcp->mb[1] = FETCH_XCHOFFLD_STAT; 748 mcp->out_mb = MBX_1|MBX_0; 749 mcp->in_mb = MBX_10|MBX_4|MBX_0; 750 mcp->tov = MBX_TOV_SECONDS; 751 mcp->flags = 0; 752 753 rval = qla2x00_mailbox_command(vha, mcp); 754 if (rval != QLA_SUCCESS) { 755 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval); 756 } else { 757 *buf_sz = mcp->mb[4]; 758 *ex_logins_cnt = mcp->mb[10]; 759 760 ql_log(ql_log_info, vha, 0x118e, 761 "buffer size 0x%x, exchange offload count=%d\n", 762 mcp->mb[4], mcp->mb[10]); 763 764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156, 765 "Done %s.\n", __func__); 766 } 767 768 return rval; 769 } 770 771 /* 772 * qla_set_exchoffld_mem_cfg 773 * Set exchange offload memory configuration 774 * Mbx needs to be issues before init_cb is set 775 * 776 * Input: 777 * ha: adapter state pointer. 778 * buffer: buffer pointer 779 * phys_addr: physical address of buffer 780 * size: size of buffer 781 * TARGET_QUEUE_LOCK must be released 782 * ADAPTER_STATE_LOCK must be release 783 * 784 * Returns: 785 * qla2x00 local funxtion status code. 786 * 787 * Context: 788 * Kernel context. 789 */ 790 #define CONFIG_XCHOFFLD_MEM 0x3 791 int 792 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 793 { 794 int rval; 795 mbx_cmd_t mc; 796 mbx_cmd_t *mcp = &mc; 797 struct qla_hw_data *ha = vha->hw; 798 799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157, 800 "Entered %s.\n", __func__); 801 802 memset(mcp->mb, 0 , sizeof(mcp->mb)); 803 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 804 mcp->mb[1] = CONFIG_XCHOFFLD_MEM; 805 mcp->mb[2] = MSW(phys_addr); 806 mcp->mb[3] = LSW(phys_addr); 807 mcp->mb[6] = MSW(MSD(phys_addr)); 808 mcp->mb[7] = LSW(MSD(phys_addr)); 809 mcp->mb[8] = MSW(ha->exlogin_size); 810 mcp->mb[9] = LSW(ha->exlogin_size); 811 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 812 mcp->in_mb = MBX_11|MBX_0; 813 mcp->tov = MBX_TOV_SECONDS; 814 mcp->flags = 0; 815 rval = qla2x00_mailbox_command(vha, mcp); 816 if (rval != QLA_SUCCESS) { 817 /*EMPTY*/ 818 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval); 819 } else { 820 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 821 "Done %s.\n", __func__); 822 } 823 824 return rval; 825 } 826 827 /* 828 * qla2x00_get_fw_version 829 * Get firmware version. 830 * 831 * Input: 832 * ha: adapter state pointer. 833 * major: pointer for major number. 834 * minor: pointer for minor number. 835 * subminor: pointer for subminor number. 836 * 837 * Returns: 838 * qla2x00 local function return status code. 839 * 840 * Context: 841 * Kernel context. 842 */ 843 int 844 qla2x00_get_fw_version(scsi_qla_host_t *vha) 845 { 846 int rval; 847 mbx_cmd_t mc; 848 mbx_cmd_t *mcp = &mc; 849 struct qla_hw_data *ha = vha->hw; 850 851 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 852 "Entered %s.\n", __func__); 853 854 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 855 mcp->out_mb = MBX_0; 856 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 857 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 858 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 859 if (IS_FWI2_CAPABLE(ha)) 860 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 861 if (IS_QLA27XX(ha)) 862 mcp->in_mb |= 863 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18| 864 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8; 865 866 mcp->flags = 0; 867 mcp->tov = MBX_TOV_SECONDS; 868 rval = qla2x00_mailbox_command(vha, mcp); 869 if (rval != QLA_SUCCESS) 870 goto failed; 871 872 /* Return mailbox data. */ 873 ha->fw_major_version = mcp->mb[1]; 874 ha->fw_minor_version = mcp->mb[2]; 875 ha->fw_subminor_version = mcp->mb[3]; 876 ha->fw_attributes = mcp->mb[6]; 877 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 878 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 879 else 880 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 881 882 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 883 ha->mpi_version[0] = mcp->mb[10] & 0xff; 884 ha->mpi_version[1] = mcp->mb[11] >> 8; 885 ha->mpi_version[2] = mcp->mb[11] & 0xff; 886 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 887 ha->phy_version[0] = mcp->mb[8] & 0xff; 888 ha->phy_version[1] = mcp->mb[9] >> 8; 889 ha->phy_version[2] = mcp->mb[9] & 0xff; 890 } 891 892 if (IS_FWI2_CAPABLE(ha)) { 893 ha->fw_attributes_h = mcp->mb[15]; 894 ha->fw_attributes_ext[0] = mcp->mb[16]; 895 ha->fw_attributes_ext[1] = mcp->mb[17]; 896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 897 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 898 __func__, mcp->mb[15], mcp->mb[6]); 899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 900 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 901 __func__, mcp->mb[17], mcp->mb[16]); 902 903 if (ha->fw_attributes_h & 0x4) 904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d, 905 "%s: Firmware supports Extended Login 0x%x\n", 906 __func__, ha->fw_attributes_h); 907 908 if (ha->fw_attributes_h & 0x8) 909 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191, 910 "%s: Firmware supports Exchange Offload 0x%x\n", 911 __func__, ha->fw_attributes_h); 912 } 913 914 if (IS_QLA27XX(ha)) { 915 ha->mpi_version[0] = mcp->mb[10] & 0xff; 916 ha->mpi_version[1] = mcp->mb[11] >> 8; 917 ha->mpi_version[2] = mcp->mb[11] & 0xff; 918 ha->pep_version[0] = mcp->mb[13] & 0xff; 919 ha->pep_version[1] = mcp->mb[14] >> 8; 920 ha->pep_version[2] = mcp->mb[14] & 0xff; 921 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 922 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 923 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22]; 924 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24]; 925 } 926 927 failed: 928 if (rval != QLA_SUCCESS) { 929 /*EMPTY*/ 930 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 931 } else { 932 /*EMPTY*/ 933 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 934 "Done %s.\n", __func__); 935 } 936 return rval; 937 } 938 939 /* 940 * qla2x00_get_fw_options 941 * Set firmware options. 942 * 943 * Input: 944 * ha = adapter block pointer. 945 * fwopt = pointer for firmware options. 946 * 947 * Returns: 948 * qla2x00 local function return status code. 949 * 950 * Context: 951 * Kernel context. 952 */ 953 int 954 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 955 { 956 int rval; 957 mbx_cmd_t mc; 958 mbx_cmd_t *mcp = &mc; 959 960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 961 "Entered %s.\n", __func__); 962 963 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 964 mcp->out_mb = MBX_0; 965 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 966 mcp->tov = MBX_TOV_SECONDS; 967 mcp->flags = 0; 968 rval = qla2x00_mailbox_command(vha, mcp); 969 970 if (rval != QLA_SUCCESS) { 971 /*EMPTY*/ 972 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 973 } else { 974 fwopts[0] = mcp->mb[0]; 975 fwopts[1] = mcp->mb[1]; 976 fwopts[2] = mcp->mb[2]; 977 fwopts[3] = mcp->mb[3]; 978 979 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 980 "Done %s.\n", __func__); 981 } 982 983 return rval; 984 } 985 986 987 /* 988 * qla2x00_set_fw_options 989 * Set firmware options. 990 * 991 * Input: 992 * ha = adapter block pointer. 993 * fwopt = pointer for firmware options. 994 * 995 * Returns: 996 * qla2x00 local function return status code. 997 * 998 * Context: 999 * Kernel context. 1000 */ 1001 int 1002 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1003 { 1004 int rval; 1005 mbx_cmd_t mc; 1006 mbx_cmd_t *mcp = &mc; 1007 1008 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 1009 "Entered %s.\n", __func__); 1010 1011 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 1012 mcp->mb[1] = fwopts[1]; 1013 mcp->mb[2] = fwopts[2]; 1014 mcp->mb[3] = fwopts[3]; 1015 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1016 mcp->in_mb = MBX_0; 1017 if (IS_FWI2_CAPABLE(vha->hw)) { 1018 mcp->in_mb |= MBX_1; 1019 } else { 1020 mcp->mb[10] = fwopts[10]; 1021 mcp->mb[11] = fwopts[11]; 1022 mcp->mb[12] = 0; /* Undocumented, but used */ 1023 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 1024 } 1025 mcp->tov = MBX_TOV_SECONDS; 1026 mcp->flags = 0; 1027 rval = qla2x00_mailbox_command(vha, mcp); 1028 1029 fwopts[0] = mcp->mb[0]; 1030 1031 if (rval != QLA_SUCCESS) { 1032 /*EMPTY*/ 1033 ql_dbg(ql_dbg_mbx, vha, 0x1030, 1034 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 1035 } else { 1036 /*EMPTY*/ 1037 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 1038 "Done %s.\n", __func__); 1039 } 1040 1041 return rval; 1042 } 1043 1044 /* 1045 * qla2x00_mbx_reg_test 1046 * Mailbox register wrap test. 1047 * 1048 * Input: 1049 * ha = adapter block pointer. 1050 * TARGET_QUEUE_LOCK must be released. 1051 * ADAPTER_STATE_LOCK must be released. 1052 * 1053 * Returns: 1054 * qla2x00 local function return status code. 1055 * 1056 * Context: 1057 * Kernel context. 1058 */ 1059 int 1060 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 1061 { 1062 int rval; 1063 mbx_cmd_t mc; 1064 mbx_cmd_t *mcp = &mc; 1065 1066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 1067 "Entered %s.\n", __func__); 1068 1069 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 1070 mcp->mb[1] = 0xAAAA; 1071 mcp->mb[2] = 0x5555; 1072 mcp->mb[3] = 0xAA55; 1073 mcp->mb[4] = 0x55AA; 1074 mcp->mb[5] = 0xA5A5; 1075 mcp->mb[6] = 0x5A5A; 1076 mcp->mb[7] = 0x2525; 1077 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1078 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1079 mcp->tov = MBX_TOV_SECONDS; 1080 mcp->flags = 0; 1081 rval = qla2x00_mailbox_command(vha, mcp); 1082 1083 if (rval == QLA_SUCCESS) { 1084 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 1085 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 1086 rval = QLA_FUNCTION_FAILED; 1087 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 1088 mcp->mb[7] != 0x2525) 1089 rval = QLA_FUNCTION_FAILED; 1090 } 1091 1092 if (rval != QLA_SUCCESS) { 1093 /*EMPTY*/ 1094 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 1095 } else { 1096 /*EMPTY*/ 1097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 1098 "Done %s.\n", __func__); 1099 } 1100 1101 return rval; 1102 } 1103 1104 /* 1105 * qla2x00_verify_checksum 1106 * Verify firmware checksum. 1107 * 1108 * Input: 1109 * ha = adapter block pointer. 1110 * TARGET_QUEUE_LOCK must be released. 1111 * ADAPTER_STATE_LOCK must be released. 1112 * 1113 * Returns: 1114 * qla2x00 local function return status code. 1115 * 1116 * Context: 1117 * Kernel context. 1118 */ 1119 int 1120 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 1121 { 1122 int rval; 1123 mbx_cmd_t mc; 1124 mbx_cmd_t *mcp = &mc; 1125 1126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 1127 "Entered %s.\n", __func__); 1128 1129 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 1130 mcp->out_mb = MBX_0; 1131 mcp->in_mb = MBX_0; 1132 if (IS_FWI2_CAPABLE(vha->hw)) { 1133 mcp->mb[1] = MSW(risc_addr); 1134 mcp->mb[2] = LSW(risc_addr); 1135 mcp->out_mb |= MBX_2|MBX_1; 1136 mcp->in_mb |= MBX_2|MBX_1; 1137 } else { 1138 mcp->mb[1] = LSW(risc_addr); 1139 mcp->out_mb |= MBX_1; 1140 mcp->in_mb |= MBX_1; 1141 } 1142 1143 mcp->tov = MBX_TOV_SECONDS; 1144 mcp->flags = 0; 1145 rval = qla2x00_mailbox_command(vha, mcp); 1146 1147 if (rval != QLA_SUCCESS) { 1148 ql_dbg(ql_dbg_mbx, vha, 0x1036, 1149 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 1150 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 1151 } else { 1152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 1153 "Done %s.\n", __func__); 1154 } 1155 1156 return rval; 1157 } 1158 1159 /* 1160 * qla2x00_issue_iocb 1161 * Issue IOCB using mailbox command 1162 * 1163 * Input: 1164 * ha = adapter state pointer. 1165 * buffer = buffer pointer. 1166 * phys_addr = physical address of buffer. 1167 * size = size of buffer. 1168 * TARGET_QUEUE_LOCK must be released. 1169 * ADAPTER_STATE_LOCK must be released. 1170 * 1171 * Returns: 1172 * qla2x00 local function return status code. 1173 * 1174 * Context: 1175 * Kernel context. 1176 */ 1177 int 1178 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 1179 dma_addr_t phys_addr, size_t size, uint32_t tov) 1180 { 1181 int rval; 1182 mbx_cmd_t mc; 1183 mbx_cmd_t *mcp = &mc; 1184 1185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 1186 "Entered %s.\n", __func__); 1187 1188 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 1189 mcp->mb[1] = 0; 1190 mcp->mb[2] = MSW(phys_addr); 1191 mcp->mb[3] = LSW(phys_addr); 1192 mcp->mb[6] = MSW(MSD(phys_addr)); 1193 mcp->mb[7] = LSW(MSD(phys_addr)); 1194 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1195 mcp->in_mb = MBX_2|MBX_0; 1196 mcp->tov = tov; 1197 mcp->flags = 0; 1198 rval = qla2x00_mailbox_command(vha, mcp); 1199 1200 if (rval != QLA_SUCCESS) { 1201 /*EMPTY*/ 1202 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 1203 } else { 1204 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 1205 1206 /* Mask reserved bits. */ 1207 sts_entry->entry_status &= 1208 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 1209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 1210 "Done %s.\n", __func__); 1211 } 1212 1213 return rval; 1214 } 1215 1216 int 1217 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 1218 size_t size) 1219 { 1220 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 1221 MBX_TOV_SECONDS); 1222 } 1223 1224 /* 1225 * qla2x00_abort_command 1226 * Abort command aborts a specified IOCB. 1227 * 1228 * Input: 1229 * ha = adapter block pointer. 1230 * sp = SB structure pointer. 1231 * 1232 * Returns: 1233 * qla2x00 local function return status code. 1234 * 1235 * Context: 1236 * Kernel context. 1237 */ 1238 int 1239 qla2x00_abort_command(srb_t *sp) 1240 { 1241 unsigned long flags = 0; 1242 int rval; 1243 uint32_t handle = 0; 1244 mbx_cmd_t mc; 1245 mbx_cmd_t *mcp = &mc; 1246 fc_port_t *fcport = sp->fcport; 1247 scsi_qla_host_t *vha = fcport->vha; 1248 struct qla_hw_data *ha = vha->hw; 1249 struct req_que *req; 1250 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1251 1252 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 1253 "Entered %s.\n", __func__); 1254 1255 if (vha->flags.qpairs_available && sp->qpair) 1256 req = sp->qpair->req; 1257 else 1258 req = vha->req; 1259 1260 spin_lock_irqsave(&ha->hardware_lock, flags); 1261 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1262 if (req->outstanding_cmds[handle] == sp) 1263 break; 1264 } 1265 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1266 1267 if (handle == req->num_outstanding_cmds) { 1268 /* command not found */ 1269 return QLA_FUNCTION_FAILED; 1270 } 1271 1272 mcp->mb[0] = MBC_ABORT_COMMAND; 1273 if (HAS_EXTENDED_IDS(ha)) 1274 mcp->mb[1] = fcport->loop_id; 1275 else 1276 mcp->mb[1] = fcport->loop_id << 8; 1277 mcp->mb[2] = (uint16_t)handle; 1278 mcp->mb[3] = (uint16_t)(handle >> 16); 1279 mcp->mb[6] = (uint16_t)cmd->device->lun; 1280 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1281 mcp->in_mb = MBX_0; 1282 mcp->tov = MBX_TOV_SECONDS; 1283 mcp->flags = 0; 1284 rval = qla2x00_mailbox_command(vha, mcp); 1285 1286 if (rval != QLA_SUCCESS) { 1287 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 1288 } else { 1289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 1290 "Done %s.\n", __func__); 1291 } 1292 1293 return rval; 1294 } 1295 1296 int 1297 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 1298 { 1299 int rval, rval2; 1300 mbx_cmd_t mc; 1301 mbx_cmd_t *mcp = &mc; 1302 scsi_qla_host_t *vha; 1303 struct req_que *req; 1304 struct rsp_que *rsp; 1305 1306 l = l; 1307 vha = fcport->vha; 1308 1309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 1310 "Entered %s.\n", __func__); 1311 1312 req = vha->hw->req_q_map[0]; 1313 rsp = req->rsp; 1314 mcp->mb[0] = MBC_ABORT_TARGET; 1315 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 1316 if (HAS_EXTENDED_IDS(vha->hw)) { 1317 mcp->mb[1] = fcport->loop_id; 1318 mcp->mb[10] = 0; 1319 mcp->out_mb |= MBX_10; 1320 } else { 1321 mcp->mb[1] = fcport->loop_id << 8; 1322 } 1323 mcp->mb[2] = vha->hw->loop_reset_delay; 1324 mcp->mb[9] = vha->vp_idx; 1325 1326 mcp->in_mb = MBX_0; 1327 mcp->tov = MBX_TOV_SECONDS; 1328 mcp->flags = 0; 1329 rval = qla2x00_mailbox_command(vha, mcp); 1330 if (rval != QLA_SUCCESS) { 1331 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1332 "Failed=%x.\n", rval); 1333 } 1334 1335 /* Issue marker IOCB. */ 1336 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 1337 MK_SYNC_ID); 1338 if (rval2 != QLA_SUCCESS) { 1339 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1340 "Failed to issue marker IOCB (%x).\n", rval2); 1341 } else { 1342 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1343 "Done %s.\n", __func__); 1344 } 1345 1346 return rval; 1347 } 1348 1349 int 1350 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1351 { 1352 int rval, rval2; 1353 mbx_cmd_t mc; 1354 mbx_cmd_t *mcp = &mc; 1355 scsi_qla_host_t *vha; 1356 struct req_que *req; 1357 struct rsp_que *rsp; 1358 1359 vha = fcport->vha; 1360 1361 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1362 "Entered %s.\n", __func__); 1363 1364 req = vha->hw->req_q_map[0]; 1365 rsp = req->rsp; 1366 mcp->mb[0] = MBC_LUN_RESET; 1367 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1368 if (HAS_EXTENDED_IDS(vha->hw)) 1369 mcp->mb[1] = fcport->loop_id; 1370 else 1371 mcp->mb[1] = fcport->loop_id << 8; 1372 mcp->mb[2] = (u32)l; 1373 mcp->mb[3] = 0; 1374 mcp->mb[9] = vha->vp_idx; 1375 1376 mcp->in_mb = MBX_0; 1377 mcp->tov = MBX_TOV_SECONDS; 1378 mcp->flags = 0; 1379 rval = qla2x00_mailbox_command(vha, mcp); 1380 if (rval != QLA_SUCCESS) { 1381 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1382 } 1383 1384 /* Issue marker IOCB. */ 1385 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1386 MK_SYNC_ID_LUN); 1387 if (rval2 != QLA_SUCCESS) { 1388 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1389 "Failed to issue marker IOCB (%x).\n", rval2); 1390 } else { 1391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1392 "Done %s.\n", __func__); 1393 } 1394 1395 return rval; 1396 } 1397 1398 /* 1399 * qla2x00_get_adapter_id 1400 * Get adapter ID and topology. 1401 * 1402 * Input: 1403 * ha = adapter block pointer. 1404 * id = pointer for loop ID. 1405 * al_pa = pointer for AL_PA. 1406 * area = pointer for area. 1407 * domain = pointer for domain. 1408 * top = pointer for topology. 1409 * TARGET_QUEUE_LOCK must be released. 1410 * ADAPTER_STATE_LOCK must be released. 1411 * 1412 * Returns: 1413 * qla2x00 local function return status code. 1414 * 1415 * Context: 1416 * Kernel context. 1417 */ 1418 int 1419 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1420 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1421 { 1422 int rval; 1423 mbx_cmd_t mc; 1424 mbx_cmd_t *mcp = &mc; 1425 1426 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1427 "Entered %s.\n", __func__); 1428 1429 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1430 mcp->mb[9] = vha->vp_idx; 1431 mcp->out_mb = MBX_9|MBX_0; 1432 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1433 if (IS_CNA_CAPABLE(vha->hw)) 1434 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1435 if (IS_FWI2_CAPABLE(vha->hw)) 1436 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1437 if (IS_QLA27XX(vha->hw)) 1438 mcp->in_mb |= MBX_15; 1439 mcp->tov = MBX_TOV_SECONDS; 1440 mcp->flags = 0; 1441 rval = qla2x00_mailbox_command(vha, mcp); 1442 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1443 rval = QLA_COMMAND_ERROR; 1444 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1445 rval = QLA_INVALID_COMMAND; 1446 1447 /* Return data. */ 1448 *id = mcp->mb[1]; 1449 *al_pa = LSB(mcp->mb[2]); 1450 *area = MSB(mcp->mb[2]); 1451 *domain = LSB(mcp->mb[3]); 1452 *top = mcp->mb[6]; 1453 *sw_cap = mcp->mb[7]; 1454 1455 if (rval != QLA_SUCCESS) { 1456 /*EMPTY*/ 1457 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1458 } else { 1459 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1460 "Done %s.\n", __func__); 1461 1462 if (IS_CNA_CAPABLE(vha->hw)) { 1463 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1464 vha->fcoe_fcf_idx = mcp->mb[10]; 1465 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1466 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1467 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1468 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1469 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1470 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1471 } 1472 /* If FA-WWN supported */ 1473 if (IS_FAWWN_CAPABLE(vha->hw)) { 1474 if (mcp->mb[7] & BIT_14) { 1475 vha->port_name[0] = MSB(mcp->mb[16]); 1476 vha->port_name[1] = LSB(mcp->mb[16]); 1477 vha->port_name[2] = MSB(mcp->mb[17]); 1478 vha->port_name[3] = LSB(mcp->mb[17]); 1479 vha->port_name[4] = MSB(mcp->mb[18]); 1480 vha->port_name[5] = LSB(mcp->mb[18]); 1481 vha->port_name[6] = MSB(mcp->mb[19]); 1482 vha->port_name[7] = LSB(mcp->mb[19]); 1483 fc_host_port_name(vha->host) = 1484 wwn_to_u64(vha->port_name); 1485 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1486 "FA-WWN acquired %016llx\n", 1487 wwn_to_u64(vha->port_name)); 1488 } 1489 } 1490 1491 if (IS_QLA27XX(vha->hw)) 1492 vha->bbcr = mcp->mb[15]; 1493 } 1494 1495 return rval; 1496 } 1497 1498 /* 1499 * qla2x00_get_retry_cnt 1500 * Get current firmware login retry count and delay. 1501 * 1502 * Input: 1503 * ha = adapter block pointer. 1504 * retry_cnt = pointer to login retry count. 1505 * tov = pointer to login timeout value. 1506 * 1507 * Returns: 1508 * qla2x00 local function return status code. 1509 * 1510 * Context: 1511 * Kernel context. 1512 */ 1513 int 1514 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1515 uint16_t *r_a_tov) 1516 { 1517 int rval; 1518 uint16_t ratov; 1519 mbx_cmd_t mc; 1520 mbx_cmd_t *mcp = &mc; 1521 1522 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1523 "Entered %s.\n", __func__); 1524 1525 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1526 mcp->out_mb = MBX_0; 1527 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1528 mcp->tov = MBX_TOV_SECONDS; 1529 mcp->flags = 0; 1530 rval = qla2x00_mailbox_command(vha, mcp); 1531 1532 if (rval != QLA_SUCCESS) { 1533 /*EMPTY*/ 1534 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1535 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1536 } else { 1537 /* Convert returned data and check our values. */ 1538 *r_a_tov = mcp->mb[3] / 2; 1539 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1540 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1541 /* Update to the larger values */ 1542 *retry_cnt = (uint8_t)mcp->mb[1]; 1543 *tov = ratov; 1544 } 1545 1546 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1547 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1548 } 1549 1550 return rval; 1551 } 1552 1553 /* 1554 * qla2x00_init_firmware 1555 * Initialize adapter firmware. 1556 * 1557 * Input: 1558 * ha = adapter block pointer. 1559 * dptr = Initialization control block pointer. 1560 * size = size of initialization control block. 1561 * TARGET_QUEUE_LOCK must be released. 1562 * ADAPTER_STATE_LOCK must be released. 1563 * 1564 * Returns: 1565 * qla2x00 local function return status code. 1566 * 1567 * Context: 1568 * Kernel context. 1569 */ 1570 int 1571 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1572 { 1573 int rval; 1574 mbx_cmd_t mc; 1575 mbx_cmd_t *mcp = &mc; 1576 struct qla_hw_data *ha = vha->hw; 1577 1578 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1579 "Entered %s.\n", __func__); 1580 1581 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1582 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1583 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1584 1585 if (ha->flags.npiv_supported) 1586 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1587 else 1588 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1589 1590 mcp->mb[1] = 0; 1591 mcp->mb[2] = MSW(ha->init_cb_dma); 1592 mcp->mb[3] = LSW(ha->init_cb_dma); 1593 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1594 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1595 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1596 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1597 mcp->mb[1] = BIT_0; 1598 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1599 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1600 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1601 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1602 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1603 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1604 } 1605 /* 1 and 2 should normally be captured. */ 1606 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1607 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1608 /* mb3 is additional info about the installed SFP. */ 1609 mcp->in_mb |= MBX_3; 1610 mcp->buf_size = size; 1611 mcp->flags = MBX_DMA_OUT; 1612 mcp->tov = MBX_TOV_SECONDS; 1613 rval = qla2x00_mailbox_command(vha, mcp); 1614 1615 if (rval != QLA_SUCCESS) { 1616 /*EMPTY*/ 1617 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1618 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1619 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1620 } else { 1621 /*EMPTY*/ 1622 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1623 "Done %s.\n", __func__); 1624 } 1625 1626 return rval; 1627 } 1628 1629 /* 1630 * qla2x00_get_node_name_list 1631 * Issue get node name list mailbox command, kmalloc() 1632 * and return the resulting list. Caller must kfree() it! 1633 * 1634 * Input: 1635 * ha = adapter state pointer. 1636 * out_data = resulting list 1637 * out_len = length of the resulting list 1638 * 1639 * Returns: 1640 * qla2x00 local function return status code. 1641 * 1642 * Context: 1643 * Kernel context. 1644 */ 1645 int 1646 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len) 1647 { 1648 struct qla_hw_data *ha = vha->hw; 1649 struct qla_port_24xx_data *list = NULL; 1650 void *pmap; 1651 mbx_cmd_t mc; 1652 dma_addr_t pmap_dma; 1653 ulong dma_size; 1654 int rval, left; 1655 1656 left = 1; 1657 while (left > 0) { 1658 dma_size = left * sizeof(*list); 1659 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size, 1660 &pmap_dma, GFP_KERNEL); 1661 if (!pmap) { 1662 ql_log(ql_log_warn, vha, 0x113f, 1663 "%s(%ld): DMA Alloc failed of %ld\n", 1664 __func__, vha->host_no, dma_size); 1665 rval = QLA_MEMORY_ALLOC_FAILED; 1666 goto out; 1667 } 1668 1669 mc.mb[0] = MBC_PORT_NODE_NAME_LIST; 1670 mc.mb[1] = BIT_1 | BIT_3; 1671 mc.mb[2] = MSW(pmap_dma); 1672 mc.mb[3] = LSW(pmap_dma); 1673 mc.mb[6] = MSW(MSD(pmap_dma)); 1674 mc.mb[7] = LSW(MSD(pmap_dma)); 1675 mc.mb[8] = dma_size; 1676 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8; 1677 mc.in_mb = MBX_0|MBX_1; 1678 mc.tov = 30; 1679 mc.flags = MBX_DMA_IN; 1680 1681 rval = qla2x00_mailbox_command(vha, &mc); 1682 if (rval != QLA_SUCCESS) { 1683 if ((mc.mb[0] == MBS_COMMAND_ERROR) && 1684 (mc.mb[1] == 0xA)) { 1685 left += le16_to_cpu(mc.mb[2]) / 1686 sizeof(struct qla_port_24xx_data); 1687 goto restart; 1688 } 1689 goto out_free; 1690 } 1691 1692 left = 0; 1693 1694 list = kmemdup(pmap, dma_size, GFP_KERNEL); 1695 if (!list) { 1696 ql_log(ql_log_warn, vha, 0x1140, 1697 "%s(%ld): failed to allocate node names list " 1698 "structure.\n", __func__, vha->host_no); 1699 rval = QLA_MEMORY_ALLOC_FAILED; 1700 goto out_free; 1701 } 1702 1703 restart: 1704 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1705 } 1706 1707 *out_data = list; 1708 *out_len = dma_size; 1709 1710 out: 1711 return rval; 1712 1713 out_free: 1714 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1715 return rval; 1716 } 1717 1718 /* 1719 * qla2x00_get_port_database 1720 * Issue normal/enhanced get port database mailbox command 1721 * and copy device name as necessary. 1722 * 1723 * Input: 1724 * ha = adapter state pointer. 1725 * dev = structure pointer. 1726 * opt = enhanced cmd option byte. 1727 * 1728 * Returns: 1729 * qla2x00 local function return status code. 1730 * 1731 * Context: 1732 * Kernel context. 1733 */ 1734 int 1735 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1736 { 1737 int rval; 1738 mbx_cmd_t mc; 1739 mbx_cmd_t *mcp = &mc; 1740 port_database_t *pd; 1741 struct port_database_24xx *pd24; 1742 dma_addr_t pd_dma; 1743 struct qla_hw_data *ha = vha->hw; 1744 1745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1746 "Entered %s.\n", __func__); 1747 1748 pd24 = NULL; 1749 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1750 if (pd == NULL) { 1751 ql_log(ql_log_warn, vha, 0x1050, 1752 "Failed to allocate port database structure.\n"); 1753 return QLA_MEMORY_ALLOC_FAILED; 1754 } 1755 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1756 1757 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1758 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1759 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1760 mcp->mb[2] = MSW(pd_dma); 1761 mcp->mb[3] = LSW(pd_dma); 1762 mcp->mb[6] = MSW(MSD(pd_dma)); 1763 mcp->mb[7] = LSW(MSD(pd_dma)); 1764 mcp->mb[9] = vha->vp_idx; 1765 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1766 mcp->in_mb = MBX_0; 1767 if (IS_FWI2_CAPABLE(ha)) { 1768 mcp->mb[1] = fcport->loop_id; 1769 mcp->mb[10] = opt; 1770 mcp->out_mb |= MBX_10|MBX_1; 1771 mcp->in_mb |= MBX_1; 1772 } else if (HAS_EXTENDED_IDS(ha)) { 1773 mcp->mb[1] = fcport->loop_id; 1774 mcp->mb[10] = opt; 1775 mcp->out_mb |= MBX_10|MBX_1; 1776 } else { 1777 mcp->mb[1] = fcport->loop_id << 8 | opt; 1778 mcp->out_mb |= MBX_1; 1779 } 1780 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1781 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1782 mcp->flags = MBX_DMA_IN; 1783 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1784 rval = qla2x00_mailbox_command(vha, mcp); 1785 if (rval != QLA_SUCCESS) 1786 goto gpd_error_out; 1787 1788 if (IS_FWI2_CAPABLE(ha)) { 1789 uint64_t zero = 0; 1790 pd24 = (struct port_database_24xx *) pd; 1791 1792 /* Check for logged in state. */ 1793 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1794 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1795 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1796 "Unable to verify login-state (%x/%x) for " 1797 "loop_id %x.\n", pd24->current_login_state, 1798 pd24->last_login_state, fcport->loop_id); 1799 rval = QLA_FUNCTION_FAILED; 1800 goto gpd_error_out; 1801 } 1802 1803 if (fcport->loop_id == FC_NO_LOOP_ID || 1804 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1805 memcmp(fcport->port_name, pd24->port_name, 8))) { 1806 /* We lost the device mid way. */ 1807 rval = QLA_NOT_LOGGED_IN; 1808 goto gpd_error_out; 1809 } 1810 1811 /* Names are little-endian. */ 1812 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1813 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1814 1815 /* Get port_id of device. */ 1816 fcport->d_id.b.domain = pd24->port_id[0]; 1817 fcport->d_id.b.area = pd24->port_id[1]; 1818 fcport->d_id.b.al_pa = pd24->port_id[2]; 1819 fcport->d_id.b.rsvd_1 = 0; 1820 1821 /* If not target must be initiator or unknown type. */ 1822 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1823 fcport->port_type = FCT_INITIATOR; 1824 else 1825 fcport->port_type = FCT_TARGET; 1826 1827 /* Passback COS information. */ 1828 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1829 FC_COS_CLASS2 : FC_COS_CLASS3; 1830 1831 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1832 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1833 } else { 1834 uint64_t zero = 0; 1835 1836 /* Check for logged in state. */ 1837 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1838 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1839 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1840 "Unable to verify login-state (%x/%x) - " 1841 "portid=%02x%02x%02x.\n", pd->master_state, 1842 pd->slave_state, fcport->d_id.b.domain, 1843 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1844 rval = QLA_FUNCTION_FAILED; 1845 goto gpd_error_out; 1846 } 1847 1848 if (fcport->loop_id == FC_NO_LOOP_ID || 1849 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1850 memcmp(fcport->port_name, pd->port_name, 8))) { 1851 /* We lost the device mid way. */ 1852 rval = QLA_NOT_LOGGED_IN; 1853 goto gpd_error_out; 1854 } 1855 1856 /* Names are little-endian. */ 1857 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1858 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1859 1860 /* Get port_id of device. */ 1861 fcport->d_id.b.domain = pd->port_id[0]; 1862 fcport->d_id.b.area = pd->port_id[3]; 1863 fcport->d_id.b.al_pa = pd->port_id[2]; 1864 fcport->d_id.b.rsvd_1 = 0; 1865 1866 /* If not target must be initiator or unknown type. */ 1867 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1868 fcport->port_type = FCT_INITIATOR; 1869 else 1870 fcport->port_type = FCT_TARGET; 1871 1872 /* Passback COS information. */ 1873 fcport->supported_classes = (pd->options & BIT_4) ? 1874 FC_COS_CLASS2: FC_COS_CLASS3; 1875 } 1876 1877 gpd_error_out: 1878 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1879 1880 if (rval != QLA_SUCCESS) { 1881 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1882 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1883 mcp->mb[0], mcp->mb[1]); 1884 } else { 1885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1886 "Done %s.\n", __func__); 1887 } 1888 1889 return rval; 1890 } 1891 1892 /* 1893 * qla2x00_get_firmware_state 1894 * Get adapter firmware state. 1895 * 1896 * Input: 1897 * ha = adapter block pointer. 1898 * dptr = pointer for firmware state. 1899 * TARGET_QUEUE_LOCK must be released. 1900 * ADAPTER_STATE_LOCK must be released. 1901 * 1902 * Returns: 1903 * qla2x00 local function return status code. 1904 * 1905 * Context: 1906 * Kernel context. 1907 */ 1908 int 1909 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1910 { 1911 int rval; 1912 mbx_cmd_t mc; 1913 mbx_cmd_t *mcp = &mc; 1914 1915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1916 "Entered %s.\n", __func__); 1917 1918 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1919 mcp->out_mb = MBX_0; 1920 if (IS_FWI2_CAPABLE(vha->hw)) 1921 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1922 else 1923 mcp->in_mb = MBX_1|MBX_0; 1924 mcp->tov = MBX_TOV_SECONDS; 1925 mcp->flags = 0; 1926 rval = qla2x00_mailbox_command(vha, mcp); 1927 1928 /* Return firmware states. */ 1929 states[0] = mcp->mb[1]; 1930 if (IS_FWI2_CAPABLE(vha->hw)) { 1931 states[1] = mcp->mb[2]; 1932 states[2] = mcp->mb[3]; /* SFP info */ 1933 states[3] = mcp->mb[4]; 1934 states[4] = mcp->mb[5]; 1935 states[5] = mcp->mb[6]; /* DPORT status */ 1936 } 1937 1938 if (rval != QLA_SUCCESS) { 1939 /*EMPTY*/ 1940 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1941 } else { 1942 /*EMPTY*/ 1943 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1944 "Done %s.\n", __func__); 1945 } 1946 1947 return rval; 1948 } 1949 1950 /* 1951 * qla2x00_get_port_name 1952 * Issue get port name mailbox command. 1953 * Returned name is in big endian format. 1954 * 1955 * Input: 1956 * ha = adapter block pointer. 1957 * loop_id = loop ID of device. 1958 * name = pointer for name. 1959 * TARGET_QUEUE_LOCK must be released. 1960 * ADAPTER_STATE_LOCK must be released. 1961 * 1962 * Returns: 1963 * qla2x00 local function return status code. 1964 * 1965 * Context: 1966 * Kernel context. 1967 */ 1968 int 1969 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1970 uint8_t opt) 1971 { 1972 int rval; 1973 mbx_cmd_t mc; 1974 mbx_cmd_t *mcp = &mc; 1975 1976 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1977 "Entered %s.\n", __func__); 1978 1979 mcp->mb[0] = MBC_GET_PORT_NAME; 1980 mcp->mb[9] = vha->vp_idx; 1981 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1982 if (HAS_EXTENDED_IDS(vha->hw)) { 1983 mcp->mb[1] = loop_id; 1984 mcp->mb[10] = opt; 1985 mcp->out_mb |= MBX_10; 1986 } else { 1987 mcp->mb[1] = loop_id << 8 | opt; 1988 } 1989 1990 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1991 mcp->tov = MBX_TOV_SECONDS; 1992 mcp->flags = 0; 1993 rval = qla2x00_mailbox_command(vha, mcp); 1994 1995 if (rval != QLA_SUCCESS) { 1996 /*EMPTY*/ 1997 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1998 } else { 1999 if (name != NULL) { 2000 /* This function returns name in big endian. */ 2001 name[0] = MSB(mcp->mb[2]); 2002 name[1] = LSB(mcp->mb[2]); 2003 name[2] = MSB(mcp->mb[3]); 2004 name[3] = LSB(mcp->mb[3]); 2005 name[4] = MSB(mcp->mb[6]); 2006 name[5] = LSB(mcp->mb[6]); 2007 name[6] = MSB(mcp->mb[7]); 2008 name[7] = LSB(mcp->mb[7]); 2009 } 2010 2011 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 2012 "Done %s.\n", __func__); 2013 } 2014 2015 return rval; 2016 } 2017 2018 /* 2019 * qla24xx_link_initialization 2020 * Issue link initialization mailbox command. 2021 * 2022 * Input: 2023 * ha = adapter block pointer. 2024 * TARGET_QUEUE_LOCK must be released. 2025 * ADAPTER_STATE_LOCK must be released. 2026 * 2027 * Returns: 2028 * qla2x00 local function return status code. 2029 * 2030 * Context: 2031 * Kernel context. 2032 */ 2033 int 2034 qla24xx_link_initialize(scsi_qla_host_t *vha) 2035 { 2036 int rval; 2037 mbx_cmd_t mc; 2038 mbx_cmd_t *mcp = &mc; 2039 2040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 2041 "Entered %s.\n", __func__); 2042 2043 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 2044 return QLA_FUNCTION_FAILED; 2045 2046 mcp->mb[0] = MBC_LINK_INITIALIZATION; 2047 mcp->mb[1] = BIT_4; 2048 if (vha->hw->operating_mode == LOOP) 2049 mcp->mb[1] |= BIT_6; 2050 else 2051 mcp->mb[1] |= BIT_5; 2052 mcp->mb[2] = 0; 2053 mcp->mb[3] = 0; 2054 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2055 mcp->in_mb = MBX_0; 2056 mcp->tov = MBX_TOV_SECONDS; 2057 mcp->flags = 0; 2058 rval = qla2x00_mailbox_command(vha, mcp); 2059 2060 if (rval != QLA_SUCCESS) { 2061 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 2062 } else { 2063 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 2064 "Done %s.\n", __func__); 2065 } 2066 2067 return rval; 2068 } 2069 2070 /* 2071 * qla2x00_lip_reset 2072 * Issue LIP reset mailbox command. 2073 * 2074 * Input: 2075 * ha = adapter block pointer. 2076 * TARGET_QUEUE_LOCK must be released. 2077 * ADAPTER_STATE_LOCK must be released. 2078 * 2079 * Returns: 2080 * qla2x00 local function return status code. 2081 * 2082 * Context: 2083 * Kernel context. 2084 */ 2085 int 2086 qla2x00_lip_reset(scsi_qla_host_t *vha) 2087 { 2088 int rval; 2089 mbx_cmd_t mc; 2090 mbx_cmd_t *mcp = &mc; 2091 2092 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 2093 "Entered %s.\n", __func__); 2094 2095 if (IS_CNA_CAPABLE(vha->hw)) { 2096 /* Logout across all FCFs. */ 2097 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2098 mcp->mb[1] = BIT_1; 2099 mcp->mb[2] = 0; 2100 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2101 } else if (IS_FWI2_CAPABLE(vha->hw)) { 2102 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2103 mcp->mb[1] = BIT_6; 2104 mcp->mb[2] = 0; 2105 mcp->mb[3] = vha->hw->loop_reset_delay; 2106 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2107 } else { 2108 mcp->mb[0] = MBC_LIP_RESET; 2109 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2110 if (HAS_EXTENDED_IDS(vha->hw)) { 2111 mcp->mb[1] = 0x00ff; 2112 mcp->mb[10] = 0; 2113 mcp->out_mb |= MBX_10; 2114 } else { 2115 mcp->mb[1] = 0xff00; 2116 } 2117 mcp->mb[2] = vha->hw->loop_reset_delay; 2118 mcp->mb[3] = 0; 2119 } 2120 mcp->in_mb = MBX_0; 2121 mcp->tov = MBX_TOV_SECONDS; 2122 mcp->flags = 0; 2123 rval = qla2x00_mailbox_command(vha, mcp); 2124 2125 if (rval != QLA_SUCCESS) { 2126 /*EMPTY*/ 2127 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 2128 } else { 2129 /*EMPTY*/ 2130 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 2131 "Done %s.\n", __func__); 2132 } 2133 2134 return rval; 2135 } 2136 2137 /* 2138 * qla2x00_send_sns 2139 * Send SNS command. 2140 * 2141 * Input: 2142 * ha = adapter block pointer. 2143 * sns = pointer for command. 2144 * cmd_size = command size. 2145 * buf_size = response/command size. 2146 * TARGET_QUEUE_LOCK must be released. 2147 * ADAPTER_STATE_LOCK must be released. 2148 * 2149 * Returns: 2150 * qla2x00 local function return status code. 2151 * 2152 * Context: 2153 * Kernel context. 2154 */ 2155 int 2156 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 2157 uint16_t cmd_size, size_t buf_size) 2158 { 2159 int rval; 2160 mbx_cmd_t mc; 2161 mbx_cmd_t *mcp = &mc; 2162 2163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 2164 "Entered %s.\n", __func__); 2165 2166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 2167 "Retry cnt=%d ratov=%d total tov=%d.\n", 2168 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 2169 2170 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 2171 mcp->mb[1] = cmd_size; 2172 mcp->mb[2] = MSW(sns_phys_address); 2173 mcp->mb[3] = LSW(sns_phys_address); 2174 mcp->mb[6] = MSW(MSD(sns_phys_address)); 2175 mcp->mb[7] = LSW(MSD(sns_phys_address)); 2176 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2177 mcp->in_mb = MBX_0|MBX_1; 2178 mcp->buf_size = buf_size; 2179 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 2180 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 2181 rval = qla2x00_mailbox_command(vha, mcp); 2182 2183 if (rval != QLA_SUCCESS) { 2184 /*EMPTY*/ 2185 ql_dbg(ql_dbg_mbx, vha, 0x105f, 2186 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2187 rval, mcp->mb[0], mcp->mb[1]); 2188 } else { 2189 /*EMPTY*/ 2190 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 2191 "Done %s.\n", __func__); 2192 } 2193 2194 return rval; 2195 } 2196 2197 int 2198 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2199 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2200 { 2201 int rval; 2202 2203 struct logio_entry_24xx *lg; 2204 dma_addr_t lg_dma; 2205 uint32_t iop[2]; 2206 struct qla_hw_data *ha = vha->hw; 2207 struct req_que *req; 2208 2209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 2210 "Entered %s.\n", __func__); 2211 2212 if (vha->vp_idx && vha->qpair) 2213 req = vha->qpair->req; 2214 else 2215 req = ha->req_q_map[0]; 2216 2217 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2218 if (lg == NULL) { 2219 ql_log(ql_log_warn, vha, 0x1062, 2220 "Failed to allocate login IOCB.\n"); 2221 return QLA_MEMORY_ALLOC_FAILED; 2222 } 2223 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2224 2225 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2226 lg->entry_count = 1; 2227 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2228 lg->nport_handle = cpu_to_le16(loop_id); 2229 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 2230 if (opt & BIT_0) 2231 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 2232 if (opt & BIT_1) 2233 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 2234 lg->port_id[0] = al_pa; 2235 lg->port_id[1] = area; 2236 lg->port_id[2] = domain; 2237 lg->vp_index = vha->vp_idx; 2238 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2239 (ha->r_a_tov / 10 * 2) + 2); 2240 if (rval != QLA_SUCCESS) { 2241 ql_dbg(ql_dbg_mbx, vha, 0x1063, 2242 "Failed to issue login IOCB (%x).\n", rval); 2243 } else if (lg->entry_status != 0) { 2244 ql_dbg(ql_dbg_mbx, vha, 0x1064, 2245 "Failed to complete IOCB -- error status (%x).\n", 2246 lg->entry_status); 2247 rval = QLA_FUNCTION_FAILED; 2248 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2249 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2250 iop[1] = le32_to_cpu(lg->io_parameter[1]); 2251 2252 ql_dbg(ql_dbg_mbx, vha, 0x1065, 2253 "Failed to complete IOCB -- completion status (%x) " 2254 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2255 iop[0], iop[1]); 2256 2257 switch (iop[0]) { 2258 case LSC_SCODE_PORTID_USED: 2259 mb[0] = MBS_PORT_ID_USED; 2260 mb[1] = LSW(iop[1]); 2261 break; 2262 case LSC_SCODE_NPORT_USED: 2263 mb[0] = MBS_LOOP_ID_USED; 2264 break; 2265 case LSC_SCODE_NOLINK: 2266 case LSC_SCODE_NOIOCB: 2267 case LSC_SCODE_NOXCB: 2268 case LSC_SCODE_CMD_FAILED: 2269 case LSC_SCODE_NOFABRIC: 2270 case LSC_SCODE_FW_NOT_READY: 2271 case LSC_SCODE_NOT_LOGGED_IN: 2272 case LSC_SCODE_NOPCB: 2273 case LSC_SCODE_ELS_REJECT: 2274 case LSC_SCODE_CMD_PARAM_ERR: 2275 case LSC_SCODE_NONPORT: 2276 case LSC_SCODE_LOGGED_IN: 2277 case LSC_SCODE_NOFLOGI_ACC: 2278 default: 2279 mb[0] = MBS_COMMAND_ERROR; 2280 break; 2281 } 2282 } else { 2283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 2284 "Done %s.\n", __func__); 2285 2286 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2287 2288 mb[0] = MBS_COMMAND_COMPLETE; 2289 mb[1] = 0; 2290 if (iop[0] & BIT_4) { 2291 if (iop[0] & BIT_8) 2292 mb[1] |= BIT_1; 2293 } else 2294 mb[1] = BIT_0; 2295 2296 /* Passback COS information. */ 2297 mb[10] = 0; 2298 if (lg->io_parameter[7] || lg->io_parameter[8]) 2299 mb[10] |= BIT_0; /* Class 2. */ 2300 if (lg->io_parameter[9] || lg->io_parameter[10]) 2301 mb[10] |= BIT_1; /* Class 3. */ 2302 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 2303 mb[10] |= BIT_7; /* Confirmed Completion 2304 * Allowed 2305 */ 2306 } 2307 2308 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2309 2310 return rval; 2311 } 2312 2313 /* 2314 * qla2x00_login_fabric 2315 * Issue login fabric port mailbox command. 2316 * 2317 * Input: 2318 * ha = adapter block pointer. 2319 * loop_id = device loop ID. 2320 * domain = device domain. 2321 * area = device area. 2322 * al_pa = device AL_PA. 2323 * status = pointer for return status. 2324 * opt = command options. 2325 * TARGET_QUEUE_LOCK must be released. 2326 * ADAPTER_STATE_LOCK must be released. 2327 * 2328 * Returns: 2329 * qla2x00 local function return status code. 2330 * 2331 * Context: 2332 * Kernel context. 2333 */ 2334 int 2335 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2336 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2337 { 2338 int rval; 2339 mbx_cmd_t mc; 2340 mbx_cmd_t *mcp = &mc; 2341 struct qla_hw_data *ha = vha->hw; 2342 2343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2344 "Entered %s.\n", __func__); 2345 2346 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2347 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2348 if (HAS_EXTENDED_IDS(ha)) { 2349 mcp->mb[1] = loop_id; 2350 mcp->mb[10] = opt; 2351 mcp->out_mb |= MBX_10; 2352 } else { 2353 mcp->mb[1] = (loop_id << 8) | opt; 2354 } 2355 mcp->mb[2] = domain; 2356 mcp->mb[3] = area << 8 | al_pa; 2357 2358 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2359 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2360 mcp->flags = 0; 2361 rval = qla2x00_mailbox_command(vha, mcp); 2362 2363 /* Return mailbox statuses. */ 2364 if (mb != NULL) { 2365 mb[0] = mcp->mb[0]; 2366 mb[1] = mcp->mb[1]; 2367 mb[2] = mcp->mb[2]; 2368 mb[6] = mcp->mb[6]; 2369 mb[7] = mcp->mb[7]; 2370 /* COS retrieved from Get-Port-Database mailbox command. */ 2371 mb[10] = 0; 2372 } 2373 2374 if (rval != QLA_SUCCESS) { 2375 /* RLU tmp code: need to change main mailbox_command function to 2376 * return ok even when the mailbox completion value is not 2377 * SUCCESS. The caller needs to be responsible to interpret 2378 * the return values of this mailbox command if we're not 2379 * to change too much of the existing code. 2380 */ 2381 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2382 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2383 mcp->mb[0] == 0x4006) 2384 rval = QLA_SUCCESS; 2385 2386 /*EMPTY*/ 2387 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2388 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2389 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2390 } else { 2391 /*EMPTY*/ 2392 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2393 "Done %s.\n", __func__); 2394 } 2395 2396 return rval; 2397 } 2398 2399 /* 2400 * qla2x00_login_local_device 2401 * Issue login loop port mailbox command. 2402 * 2403 * Input: 2404 * ha = adapter block pointer. 2405 * loop_id = device loop ID. 2406 * opt = command options. 2407 * 2408 * Returns: 2409 * Return status code. 2410 * 2411 * Context: 2412 * Kernel context. 2413 * 2414 */ 2415 int 2416 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2417 uint16_t *mb_ret, uint8_t opt) 2418 { 2419 int rval; 2420 mbx_cmd_t mc; 2421 mbx_cmd_t *mcp = &mc; 2422 struct qla_hw_data *ha = vha->hw; 2423 2424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2425 "Entered %s.\n", __func__); 2426 2427 if (IS_FWI2_CAPABLE(ha)) 2428 return qla24xx_login_fabric(vha, fcport->loop_id, 2429 fcport->d_id.b.domain, fcport->d_id.b.area, 2430 fcport->d_id.b.al_pa, mb_ret, opt); 2431 2432 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2433 if (HAS_EXTENDED_IDS(ha)) 2434 mcp->mb[1] = fcport->loop_id; 2435 else 2436 mcp->mb[1] = fcport->loop_id << 8; 2437 mcp->mb[2] = opt; 2438 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2439 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2440 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2441 mcp->flags = 0; 2442 rval = qla2x00_mailbox_command(vha, mcp); 2443 2444 /* Return mailbox statuses. */ 2445 if (mb_ret != NULL) { 2446 mb_ret[0] = mcp->mb[0]; 2447 mb_ret[1] = mcp->mb[1]; 2448 mb_ret[6] = mcp->mb[6]; 2449 mb_ret[7] = mcp->mb[7]; 2450 } 2451 2452 if (rval != QLA_SUCCESS) { 2453 /* AV tmp code: need to change main mailbox_command function to 2454 * return ok even when the mailbox completion value is not 2455 * SUCCESS. The caller needs to be responsible to interpret 2456 * the return values of this mailbox command if we're not 2457 * to change too much of the existing code. 2458 */ 2459 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2460 rval = QLA_SUCCESS; 2461 2462 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2463 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2464 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2465 } else { 2466 /*EMPTY*/ 2467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2468 "Done %s.\n", __func__); 2469 } 2470 2471 return (rval); 2472 } 2473 2474 int 2475 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2476 uint8_t area, uint8_t al_pa) 2477 { 2478 int rval; 2479 struct logio_entry_24xx *lg; 2480 dma_addr_t lg_dma; 2481 struct qla_hw_data *ha = vha->hw; 2482 struct req_que *req; 2483 2484 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2485 "Entered %s.\n", __func__); 2486 2487 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2488 if (lg == NULL) { 2489 ql_log(ql_log_warn, vha, 0x106e, 2490 "Failed to allocate logout IOCB.\n"); 2491 return QLA_MEMORY_ALLOC_FAILED; 2492 } 2493 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2494 2495 req = vha->req; 2496 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2497 lg->entry_count = 1; 2498 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2499 lg->nport_handle = cpu_to_le16(loop_id); 2500 lg->control_flags = 2501 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2502 LCF_FREE_NPORT); 2503 lg->port_id[0] = al_pa; 2504 lg->port_id[1] = area; 2505 lg->port_id[2] = domain; 2506 lg->vp_index = vha->vp_idx; 2507 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2508 (ha->r_a_tov / 10 * 2) + 2); 2509 if (rval != QLA_SUCCESS) { 2510 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2511 "Failed to issue logout IOCB (%x).\n", rval); 2512 } else if (lg->entry_status != 0) { 2513 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2514 "Failed to complete IOCB -- error status (%x).\n", 2515 lg->entry_status); 2516 rval = QLA_FUNCTION_FAILED; 2517 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2518 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2519 "Failed to complete IOCB -- completion status (%x) " 2520 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2521 le32_to_cpu(lg->io_parameter[0]), 2522 le32_to_cpu(lg->io_parameter[1])); 2523 } else { 2524 /*EMPTY*/ 2525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2526 "Done %s.\n", __func__); 2527 } 2528 2529 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2530 2531 return rval; 2532 } 2533 2534 /* 2535 * qla2x00_fabric_logout 2536 * Issue logout fabric port mailbox command. 2537 * 2538 * Input: 2539 * ha = adapter block pointer. 2540 * loop_id = device loop ID. 2541 * TARGET_QUEUE_LOCK must be released. 2542 * ADAPTER_STATE_LOCK must be released. 2543 * 2544 * Returns: 2545 * qla2x00 local function return status code. 2546 * 2547 * Context: 2548 * Kernel context. 2549 */ 2550 int 2551 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2552 uint8_t area, uint8_t al_pa) 2553 { 2554 int rval; 2555 mbx_cmd_t mc; 2556 mbx_cmd_t *mcp = &mc; 2557 2558 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2559 "Entered %s.\n", __func__); 2560 2561 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2562 mcp->out_mb = MBX_1|MBX_0; 2563 if (HAS_EXTENDED_IDS(vha->hw)) { 2564 mcp->mb[1] = loop_id; 2565 mcp->mb[10] = 0; 2566 mcp->out_mb |= MBX_10; 2567 } else { 2568 mcp->mb[1] = loop_id << 8; 2569 } 2570 2571 mcp->in_mb = MBX_1|MBX_0; 2572 mcp->tov = MBX_TOV_SECONDS; 2573 mcp->flags = 0; 2574 rval = qla2x00_mailbox_command(vha, mcp); 2575 2576 if (rval != QLA_SUCCESS) { 2577 /*EMPTY*/ 2578 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2579 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2580 } else { 2581 /*EMPTY*/ 2582 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2583 "Done %s.\n", __func__); 2584 } 2585 2586 return rval; 2587 } 2588 2589 /* 2590 * qla2x00_full_login_lip 2591 * Issue full login LIP mailbox command. 2592 * 2593 * Input: 2594 * ha = adapter block pointer. 2595 * TARGET_QUEUE_LOCK must be released. 2596 * ADAPTER_STATE_LOCK must be released. 2597 * 2598 * Returns: 2599 * qla2x00 local function return status code. 2600 * 2601 * Context: 2602 * Kernel context. 2603 */ 2604 int 2605 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2606 { 2607 int rval; 2608 mbx_cmd_t mc; 2609 mbx_cmd_t *mcp = &mc; 2610 2611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2612 "Entered %s.\n", __func__); 2613 2614 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2615 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2616 mcp->mb[2] = 0; 2617 mcp->mb[3] = 0; 2618 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2619 mcp->in_mb = MBX_0; 2620 mcp->tov = MBX_TOV_SECONDS; 2621 mcp->flags = 0; 2622 rval = qla2x00_mailbox_command(vha, mcp); 2623 2624 if (rval != QLA_SUCCESS) { 2625 /*EMPTY*/ 2626 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2627 } else { 2628 /*EMPTY*/ 2629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2630 "Done %s.\n", __func__); 2631 } 2632 2633 return rval; 2634 } 2635 2636 /* 2637 * qla2x00_get_id_list 2638 * 2639 * Input: 2640 * ha = adapter block pointer. 2641 * 2642 * Returns: 2643 * qla2x00 local function return status code. 2644 * 2645 * Context: 2646 * Kernel context. 2647 */ 2648 int 2649 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2650 uint16_t *entries) 2651 { 2652 int rval; 2653 mbx_cmd_t mc; 2654 mbx_cmd_t *mcp = &mc; 2655 2656 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2657 "Entered %s.\n", __func__); 2658 2659 if (id_list == NULL) 2660 return QLA_FUNCTION_FAILED; 2661 2662 mcp->mb[0] = MBC_GET_ID_LIST; 2663 mcp->out_mb = MBX_0; 2664 if (IS_FWI2_CAPABLE(vha->hw)) { 2665 mcp->mb[2] = MSW(id_list_dma); 2666 mcp->mb[3] = LSW(id_list_dma); 2667 mcp->mb[6] = MSW(MSD(id_list_dma)); 2668 mcp->mb[7] = LSW(MSD(id_list_dma)); 2669 mcp->mb[8] = 0; 2670 mcp->mb[9] = vha->vp_idx; 2671 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2672 } else { 2673 mcp->mb[1] = MSW(id_list_dma); 2674 mcp->mb[2] = LSW(id_list_dma); 2675 mcp->mb[3] = MSW(MSD(id_list_dma)); 2676 mcp->mb[6] = LSW(MSD(id_list_dma)); 2677 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2678 } 2679 mcp->in_mb = MBX_1|MBX_0; 2680 mcp->tov = MBX_TOV_SECONDS; 2681 mcp->flags = 0; 2682 rval = qla2x00_mailbox_command(vha, mcp); 2683 2684 if (rval != QLA_SUCCESS) { 2685 /*EMPTY*/ 2686 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2687 } else { 2688 *entries = mcp->mb[1]; 2689 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2690 "Done %s.\n", __func__); 2691 } 2692 2693 return rval; 2694 } 2695 2696 /* 2697 * qla2x00_get_resource_cnts 2698 * Get current firmware resource counts. 2699 * 2700 * Input: 2701 * ha = adapter block pointer. 2702 * 2703 * Returns: 2704 * qla2x00 local function return status code. 2705 * 2706 * Context: 2707 * Kernel context. 2708 */ 2709 int 2710 qla2x00_get_resource_cnts(scsi_qla_host_t *vha) 2711 { 2712 struct qla_hw_data *ha = vha->hw; 2713 int rval; 2714 mbx_cmd_t mc; 2715 mbx_cmd_t *mcp = &mc; 2716 2717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2718 "Entered %s.\n", __func__); 2719 2720 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2721 mcp->out_mb = MBX_0; 2722 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2723 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2724 mcp->in_mb |= MBX_12; 2725 mcp->tov = MBX_TOV_SECONDS; 2726 mcp->flags = 0; 2727 rval = qla2x00_mailbox_command(vha, mcp); 2728 2729 if (rval != QLA_SUCCESS) { 2730 /*EMPTY*/ 2731 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2732 "Failed mb[0]=%x.\n", mcp->mb[0]); 2733 } else { 2734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2735 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2736 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2737 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2738 mcp->mb[11], mcp->mb[12]); 2739 2740 ha->orig_fw_tgt_xcb_count = mcp->mb[1]; 2741 ha->cur_fw_tgt_xcb_count = mcp->mb[2]; 2742 ha->cur_fw_xcb_count = mcp->mb[3]; 2743 ha->orig_fw_xcb_count = mcp->mb[6]; 2744 ha->cur_fw_iocb_count = mcp->mb[7]; 2745 ha->orig_fw_iocb_count = mcp->mb[10]; 2746 if (ha->flags.npiv_supported) 2747 ha->max_npiv_vports = mcp->mb[11]; 2748 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2749 ha->fw_max_fcf_count = mcp->mb[12]; 2750 } 2751 2752 return (rval); 2753 } 2754 2755 /* 2756 * qla2x00_get_fcal_position_map 2757 * Get FCAL (LILP) position map using mailbox command 2758 * 2759 * Input: 2760 * ha = adapter state pointer. 2761 * pos_map = buffer pointer (can be NULL). 2762 * 2763 * Returns: 2764 * qla2x00 local function return status code. 2765 * 2766 * Context: 2767 * Kernel context. 2768 */ 2769 int 2770 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2771 { 2772 int rval; 2773 mbx_cmd_t mc; 2774 mbx_cmd_t *mcp = &mc; 2775 char *pmap; 2776 dma_addr_t pmap_dma; 2777 struct qla_hw_data *ha = vha->hw; 2778 2779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2780 "Entered %s.\n", __func__); 2781 2782 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2783 if (pmap == NULL) { 2784 ql_log(ql_log_warn, vha, 0x1080, 2785 "Memory alloc failed.\n"); 2786 return QLA_MEMORY_ALLOC_FAILED; 2787 } 2788 memset(pmap, 0, FCAL_MAP_SIZE); 2789 2790 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2791 mcp->mb[2] = MSW(pmap_dma); 2792 mcp->mb[3] = LSW(pmap_dma); 2793 mcp->mb[6] = MSW(MSD(pmap_dma)); 2794 mcp->mb[7] = LSW(MSD(pmap_dma)); 2795 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2796 mcp->in_mb = MBX_1|MBX_0; 2797 mcp->buf_size = FCAL_MAP_SIZE; 2798 mcp->flags = MBX_DMA_IN; 2799 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2800 rval = qla2x00_mailbox_command(vha, mcp); 2801 2802 if (rval == QLA_SUCCESS) { 2803 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2804 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2805 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2806 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2807 pmap, pmap[0] + 1); 2808 2809 if (pos_map) 2810 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2811 } 2812 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2813 2814 if (rval != QLA_SUCCESS) { 2815 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2816 } else { 2817 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2818 "Done %s.\n", __func__); 2819 } 2820 2821 return rval; 2822 } 2823 2824 /* 2825 * qla2x00_get_link_status 2826 * 2827 * Input: 2828 * ha = adapter block pointer. 2829 * loop_id = device loop ID. 2830 * ret_buf = pointer to link status return buffer. 2831 * 2832 * Returns: 2833 * 0 = success. 2834 * BIT_0 = mem alloc error. 2835 * BIT_1 = mailbox error. 2836 */ 2837 int 2838 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2839 struct link_statistics *stats, dma_addr_t stats_dma) 2840 { 2841 int rval; 2842 mbx_cmd_t mc; 2843 mbx_cmd_t *mcp = &mc; 2844 uint32_t *iter = (void *)stats; 2845 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter); 2846 struct qla_hw_data *ha = vha->hw; 2847 2848 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2849 "Entered %s.\n", __func__); 2850 2851 mcp->mb[0] = MBC_GET_LINK_STATUS; 2852 mcp->mb[2] = MSW(LSD(stats_dma)); 2853 mcp->mb[3] = LSW(LSD(stats_dma)); 2854 mcp->mb[6] = MSW(MSD(stats_dma)); 2855 mcp->mb[7] = LSW(MSD(stats_dma)); 2856 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2857 mcp->in_mb = MBX_0; 2858 if (IS_FWI2_CAPABLE(ha)) { 2859 mcp->mb[1] = loop_id; 2860 mcp->mb[4] = 0; 2861 mcp->mb[10] = 0; 2862 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2863 mcp->in_mb |= MBX_1; 2864 } else if (HAS_EXTENDED_IDS(ha)) { 2865 mcp->mb[1] = loop_id; 2866 mcp->mb[10] = 0; 2867 mcp->out_mb |= MBX_10|MBX_1; 2868 } else { 2869 mcp->mb[1] = loop_id << 8; 2870 mcp->out_mb |= MBX_1; 2871 } 2872 mcp->tov = MBX_TOV_SECONDS; 2873 mcp->flags = IOCTL_CMD; 2874 rval = qla2x00_mailbox_command(vha, mcp); 2875 2876 if (rval == QLA_SUCCESS) { 2877 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2878 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2879 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2880 rval = QLA_FUNCTION_FAILED; 2881 } else { 2882 /* Re-endianize - firmware data is le32. */ 2883 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2884 "Done %s.\n", __func__); 2885 for ( ; dwords--; iter++) 2886 le32_to_cpus(iter); 2887 } 2888 } else { 2889 /* Failed. */ 2890 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2891 } 2892 2893 return rval; 2894 } 2895 2896 int 2897 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2898 dma_addr_t stats_dma, uint options) 2899 { 2900 int rval; 2901 mbx_cmd_t mc; 2902 mbx_cmd_t *mcp = &mc; 2903 uint32_t *iter, dwords; 2904 2905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2906 "Entered %s.\n", __func__); 2907 2908 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2909 mcp->mb[2] = MSW(stats_dma); 2910 mcp->mb[3] = LSW(stats_dma); 2911 mcp->mb[6] = MSW(MSD(stats_dma)); 2912 mcp->mb[7] = LSW(MSD(stats_dma)); 2913 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2914 mcp->mb[9] = vha->vp_idx; 2915 mcp->mb[10] = options; 2916 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2917 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2918 mcp->tov = MBX_TOV_SECONDS; 2919 mcp->flags = IOCTL_CMD; 2920 rval = qla2x00_mailbox_command(vha, mcp); 2921 2922 if (rval == QLA_SUCCESS) { 2923 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2924 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2925 "Failed mb[0]=%x.\n", mcp->mb[0]); 2926 rval = QLA_FUNCTION_FAILED; 2927 } else { 2928 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2929 "Done %s.\n", __func__); 2930 /* Re-endianize - firmware data is le32. */ 2931 dwords = sizeof(struct link_statistics) / 4; 2932 iter = &stats->link_fail_cnt; 2933 for ( ; dwords--; iter++) 2934 le32_to_cpus(iter); 2935 } 2936 } else { 2937 /* Failed. */ 2938 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2939 } 2940 2941 return rval; 2942 } 2943 2944 int 2945 qla24xx_abort_command(srb_t *sp) 2946 { 2947 int rval; 2948 unsigned long flags = 0; 2949 2950 struct abort_entry_24xx *abt; 2951 dma_addr_t abt_dma; 2952 uint32_t handle; 2953 fc_port_t *fcport = sp->fcport; 2954 struct scsi_qla_host *vha = fcport->vha; 2955 struct qla_hw_data *ha = vha->hw; 2956 struct req_que *req = vha->req; 2957 2958 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2959 "Entered %s.\n", __func__); 2960 2961 if (vha->flags.qpairs_available && sp->qpair) 2962 req = sp->qpair->req; 2963 2964 if (ql2xasynctmfenable) 2965 return qla24xx_async_abort_command(sp); 2966 2967 spin_lock_irqsave(&ha->hardware_lock, flags); 2968 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2969 if (req->outstanding_cmds[handle] == sp) 2970 break; 2971 } 2972 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2973 if (handle == req->num_outstanding_cmds) { 2974 /* Command not found. */ 2975 return QLA_FUNCTION_FAILED; 2976 } 2977 2978 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2979 if (abt == NULL) { 2980 ql_log(ql_log_warn, vha, 0x108d, 2981 "Failed to allocate abort IOCB.\n"); 2982 return QLA_MEMORY_ALLOC_FAILED; 2983 } 2984 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2985 2986 abt->entry_type = ABORT_IOCB_TYPE; 2987 abt->entry_count = 1; 2988 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2989 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2990 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2991 abt->port_id[0] = fcport->d_id.b.al_pa; 2992 abt->port_id[1] = fcport->d_id.b.area; 2993 abt->port_id[2] = fcport->d_id.b.domain; 2994 abt->vp_index = fcport->vha->vp_idx; 2995 2996 abt->req_que_no = cpu_to_le16(req->id); 2997 2998 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2999 if (rval != QLA_SUCCESS) { 3000 ql_dbg(ql_dbg_mbx, vha, 0x108e, 3001 "Failed to issue IOCB (%x).\n", rval); 3002 } else if (abt->entry_status != 0) { 3003 ql_dbg(ql_dbg_mbx, vha, 0x108f, 3004 "Failed to complete IOCB -- error status (%x).\n", 3005 abt->entry_status); 3006 rval = QLA_FUNCTION_FAILED; 3007 } else if (abt->nport_handle != cpu_to_le16(0)) { 3008 ql_dbg(ql_dbg_mbx, vha, 0x1090, 3009 "Failed to complete IOCB -- completion status (%x).\n", 3010 le16_to_cpu(abt->nport_handle)); 3011 if (abt->nport_handle == CS_IOCB_ERROR) 3012 rval = QLA_FUNCTION_PARAMETER_ERROR; 3013 else 3014 rval = QLA_FUNCTION_FAILED; 3015 } else { 3016 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 3017 "Done %s.\n", __func__); 3018 } 3019 3020 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 3021 3022 return rval; 3023 } 3024 3025 struct tsk_mgmt_cmd { 3026 union { 3027 struct tsk_mgmt_entry tsk; 3028 struct sts_entry_24xx sts; 3029 } p; 3030 }; 3031 3032 static int 3033 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 3034 uint64_t l, int tag) 3035 { 3036 int rval, rval2; 3037 struct tsk_mgmt_cmd *tsk; 3038 struct sts_entry_24xx *sts; 3039 dma_addr_t tsk_dma; 3040 scsi_qla_host_t *vha; 3041 struct qla_hw_data *ha; 3042 struct req_que *req; 3043 struct rsp_que *rsp; 3044 struct qla_qpair *qpair; 3045 3046 vha = fcport->vha; 3047 ha = vha->hw; 3048 req = vha->req; 3049 3050 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 3051 "Entered %s.\n", __func__); 3052 3053 if (vha->vp_idx && vha->qpair) { 3054 /* NPIV port */ 3055 qpair = vha->qpair; 3056 rsp = qpair->rsp; 3057 req = qpair->req; 3058 } else { 3059 rsp = req->rsp; 3060 } 3061 3062 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 3063 if (tsk == NULL) { 3064 ql_log(ql_log_warn, vha, 0x1093, 3065 "Failed to allocate task management IOCB.\n"); 3066 return QLA_MEMORY_ALLOC_FAILED; 3067 } 3068 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 3069 3070 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 3071 tsk->p.tsk.entry_count = 1; 3072 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 3073 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 3074 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 3075 tsk->p.tsk.control_flags = cpu_to_le32(type); 3076 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 3077 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 3078 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 3079 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 3080 if (type == TCF_LUN_RESET) { 3081 int_to_scsilun(l, &tsk->p.tsk.lun); 3082 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 3083 sizeof(tsk->p.tsk.lun)); 3084 } 3085 3086 sts = &tsk->p.sts; 3087 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 3088 if (rval != QLA_SUCCESS) { 3089 ql_dbg(ql_dbg_mbx, vha, 0x1094, 3090 "Failed to issue %s reset IOCB (%x).\n", name, rval); 3091 } else if (sts->entry_status != 0) { 3092 ql_dbg(ql_dbg_mbx, vha, 0x1095, 3093 "Failed to complete IOCB -- error status (%x).\n", 3094 sts->entry_status); 3095 rval = QLA_FUNCTION_FAILED; 3096 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 3097 ql_dbg(ql_dbg_mbx, vha, 0x1096, 3098 "Failed to complete IOCB -- completion status (%x).\n", 3099 le16_to_cpu(sts->comp_status)); 3100 rval = QLA_FUNCTION_FAILED; 3101 } else if (le16_to_cpu(sts->scsi_status) & 3102 SS_RESPONSE_INFO_LEN_VALID) { 3103 if (le32_to_cpu(sts->rsp_data_len) < 4) { 3104 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 3105 "Ignoring inconsistent data length -- not enough " 3106 "response info (%d).\n", 3107 le32_to_cpu(sts->rsp_data_len)); 3108 } else if (sts->data[3]) { 3109 ql_dbg(ql_dbg_mbx, vha, 0x1098, 3110 "Failed to complete IOCB -- response (%x).\n", 3111 sts->data[3]); 3112 rval = QLA_FUNCTION_FAILED; 3113 } 3114 } 3115 3116 /* Issue marker IOCB. */ 3117 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 3118 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 3119 if (rval2 != QLA_SUCCESS) { 3120 ql_dbg(ql_dbg_mbx, vha, 0x1099, 3121 "Failed to issue marker IOCB (%x).\n", rval2); 3122 } else { 3123 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 3124 "Done %s.\n", __func__); 3125 } 3126 3127 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 3128 3129 return rval; 3130 } 3131 3132 int 3133 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 3134 { 3135 struct qla_hw_data *ha = fcport->vha->hw; 3136 3137 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3138 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 3139 3140 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 3141 } 3142 3143 int 3144 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 3145 { 3146 struct qla_hw_data *ha = fcport->vha->hw; 3147 3148 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3149 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 3150 3151 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 3152 } 3153 3154 int 3155 qla2x00_system_error(scsi_qla_host_t *vha) 3156 { 3157 int rval; 3158 mbx_cmd_t mc; 3159 mbx_cmd_t *mcp = &mc; 3160 struct qla_hw_data *ha = vha->hw; 3161 3162 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 3163 return QLA_FUNCTION_FAILED; 3164 3165 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 3166 "Entered %s.\n", __func__); 3167 3168 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 3169 mcp->out_mb = MBX_0; 3170 mcp->in_mb = MBX_0; 3171 mcp->tov = 5; 3172 mcp->flags = 0; 3173 rval = qla2x00_mailbox_command(vha, mcp); 3174 3175 if (rval != QLA_SUCCESS) { 3176 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 3177 } else { 3178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 3179 "Done %s.\n", __func__); 3180 } 3181 3182 return rval; 3183 } 3184 3185 int 3186 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 3187 { 3188 int rval; 3189 mbx_cmd_t mc; 3190 mbx_cmd_t *mcp = &mc; 3191 3192 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3193 !IS_QLA27XX(vha->hw)) 3194 return QLA_FUNCTION_FAILED; 3195 3196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 3197 "Entered %s.\n", __func__); 3198 3199 mcp->mb[0] = MBC_WRITE_SERDES; 3200 mcp->mb[1] = addr; 3201 if (IS_QLA2031(vha->hw)) 3202 mcp->mb[2] = data & 0xff; 3203 else 3204 mcp->mb[2] = data; 3205 3206 mcp->mb[3] = 0; 3207 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 3208 mcp->in_mb = MBX_0; 3209 mcp->tov = MBX_TOV_SECONDS; 3210 mcp->flags = 0; 3211 rval = qla2x00_mailbox_command(vha, mcp); 3212 3213 if (rval != QLA_SUCCESS) { 3214 ql_dbg(ql_dbg_mbx, vha, 0x1183, 3215 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3216 } else { 3217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 3218 "Done %s.\n", __func__); 3219 } 3220 3221 return rval; 3222 } 3223 3224 int 3225 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 3226 { 3227 int rval; 3228 mbx_cmd_t mc; 3229 mbx_cmd_t *mcp = &mc; 3230 3231 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3232 !IS_QLA27XX(vha->hw)) 3233 return QLA_FUNCTION_FAILED; 3234 3235 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 3236 "Entered %s.\n", __func__); 3237 3238 mcp->mb[0] = MBC_READ_SERDES; 3239 mcp->mb[1] = addr; 3240 mcp->mb[3] = 0; 3241 mcp->out_mb = MBX_3|MBX_1|MBX_0; 3242 mcp->in_mb = MBX_1|MBX_0; 3243 mcp->tov = MBX_TOV_SECONDS; 3244 mcp->flags = 0; 3245 rval = qla2x00_mailbox_command(vha, mcp); 3246 3247 if (IS_QLA2031(vha->hw)) 3248 *data = mcp->mb[1] & 0xff; 3249 else 3250 *data = mcp->mb[1]; 3251 3252 if (rval != QLA_SUCCESS) { 3253 ql_dbg(ql_dbg_mbx, vha, 0x1186, 3254 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3255 } else { 3256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 3257 "Done %s.\n", __func__); 3258 } 3259 3260 return rval; 3261 } 3262 3263 int 3264 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 3265 { 3266 int rval; 3267 mbx_cmd_t mc; 3268 mbx_cmd_t *mcp = &mc; 3269 3270 if (!IS_QLA8044(vha->hw)) 3271 return QLA_FUNCTION_FAILED; 3272 3273 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186, 3274 "Entered %s.\n", __func__); 3275 3276 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3277 mcp->mb[1] = HCS_WRITE_SERDES; 3278 mcp->mb[3] = LSW(addr); 3279 mcp->mb[4] = MSW(addr); 3280 mcp->mb[5] = LSW(data); 3281 mcp->mb[6] = MSW(data); 3282 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 3283 mcp->in_mb = MBX_0; 3284 mcp->tov = MBX_TOV_SECONDS; 3285 mcp->flags = 0; 3286 rval = qla2x00_mailbox_command(vha, mcp); 3287 3288 if (rval != QLA_SUCCESS) { 3289 ql_dbg(ql_dbg_mbx, vha, 0x1187, 3290 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3291 } else { 3292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 3293 "Done %s.\n", __func__); 3294 } 3295 3296 return rval; 3297 } 3298 3299 int 3300 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 3301 { 3302 int rval; 3303 mbx_cmd_t mc; 3304 mbx_cmd_t *mcp = &mc; 3305 3306 if (!IS_QLA8044(vha->hw)) 3307 return QLA_FUNCTION_FAILED; 3308 3309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 3310 "Entered %s.\n", __func__); 3311 3312 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3313 mcp->mb[1] = HCS_READ_SERDES; 3314 mcp->mb[3] = LSW(addr); 3315 mcp->mb[4] = MSW(addr); 3316 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 3317 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3318 mcp->tov = MBX_TOV_SECONDS; 3319 mcp->flags = 0; 3320 rval = qla2x00_mailbox_command(vha, mcp); 3321 3322 *data = mcp->mb[2] << 16 | mcp->mb[1]; 3323 3324 if (rval != QLA_SUCCESS) { 3325 ql_dbg(ql_dbg_mbx, vha, 0x118a, 3326 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3327 } else { 3328 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3329 "Done %s.\n", __func__); 3330 } 3331 3332 return rval; 3333 } 3334 3335 /** 3336 * qla2x00_set_serdes_params() - 3337 * @ha: HA context 3338 * 3339 * Returns 3340 */ 3341 int 3342 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3343 uint16_t sw_em_2g, uint16_t sw_em_4g) 3344 { 3345 int rval; 3346 mbx_cmd_t mc; 3347 mbx_cmd_t *mcp = &mc; 3348 3349 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3350 "Entered %s.\n", __func__); 3351 3352 mcp->mb[0] = MBC_SERDES_PARAMS; 3353 mcp->mb[1] = BIT_0; 3354 mcp->mb[2] = sw_em_1g | BIT_15; 3355 mcp->mb[3] = sw_em_2g | BIT_15; 3356 mcp->mb[4] = sw_em_4g | BIT_15; 3357 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3358 mcp->in_mb = MBX_0; 3359 mcp->tov = MBX_TOV_SECONDS; 3360 mcp->flags = 0; 3361 rval = qla2x00_mailbox_command(vha, mcp); 3362 3363 if (rval != QLA_SUCCESS) { 3364 /*EMPTY*/ 3365 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3366 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3367 } else { 3368 /*EMPTY*/ 3369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3370 "Done %s.\n", __func__); 3371 } 3372 3373 return rval; 3374 } 3375 3376 int 3377 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3378 { 3379 int rval; 3380 mbx_cmd_t mc; 3381 mbx_cmd_t *mcp = &mc; 3382 3383 if (!IS_FWI2_CAPABLE(vha->hw)) 3384 return QLA_FUNCTION_FAILED; 3385 3386 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3387 "Entered %s.\n", __func__); 3388 3389 mcp->mb[0] = MBC_STOP_FIRMWARE; 3390 mcp->mb[1] = 0; 3391 mcp->out_mb = MBX_1|MBX_0; 3392 mcp->in_mb = MBX_0; 3393 mcp->tov = 5; 3394 mcp->flags = 0; 3395 rval = qla2x00_mailbox_command(vha, mcp); 3396 3397 if (rval != QLA_SUCCESS) { 3398 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3399 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3400 rval = QLA_INVALID_COMMAND; 3401 } else { 3402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3403 "Done %s.\n", __func__); 3404 } 3405 3406 return rval; 3407 } 3408 3409 int 3410 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3411 uint16_t buffers) 3412 { 3413 int rval; 3414 mbx_cmd_t mc; 3415 mbx_cmd_t *mcp = &mc; 3416 3417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3418 "Entered %s.\n", __func__); 3419 3420 if (!IS_FWI2_CAPABLE(vha->hw)) 3421 return QLA_FUNCTION_FAILED; 3422 3423 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3424 return QLA_FUNCTION_FAILED; 3425 3426 mcp->mb[0] = MBC_TRACE_CONTROL; 3427 mcp->mb[1] = TC_EFT_ENABLE; 3428 mcp->mb[2] = LSW(eft_dma); 3429 mcp->mb[3] = MSW(eft_dma); 3430 mcp->mb[4] = LSW(MSD(eft_dma)); 3431 mcp->mb[5] = MSW(MSD(eft_dma)); 3432 mcp->mb[6] = buffers; 3433 mcp->mb[7] = TC_AEN_DISABLE; 3434 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3435 mcp->in_mb = MBX_1|MBX_0; 3436 mcp->tov = MBX_TOV_SECONDS; 3437 mcp->flags = 0; 3438 rval = qla2x00_mailbox_command(vha, mcp); 3439 if (rval != QLA_SUCCESS) { 3440 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3441 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3442 rval, mcp->mb[0], mcp->mb[1]); 3443 } else { 3444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3445 "Done %s.\n", __func__); 3446 } 3447 3448 return rval; 3449 } 3450 3451 int 3452 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3453 { 3454 int rval; 3455 mbx_cmd_t mc; 3456 mbx_cmd_t *mcp = &mc; 3457 3458 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3459 "Entered %s.\n", __func__); 3460 3461 if (!IS_FWI2_CAPABLE(vha->hw)) 3462 return QLA_FUNCTION_FAILED; 3463 3464 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3465 return QLA_FUNCTION_FAILED; 3466 3467 mcp->mb[0] = MBC_TRACE_CONTROL; 3468 mcp->mb[1] = TC_EFT_DISABLE; 3469 mcp->out_mb = MBX_1|MBX_0; 3470 mcp->in_mb = MBX_1|MBX_0; 3471 mcp->tov = MBX_TOV_SECONDS; 3472 mcp->flags = 0; 3473 rval = qla2x00_mailbox_command(vha, mcp); 3474 if (rval != QLA_SUCCESS) { 3475 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3476 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3477 rval, mcp->mb[0], mcp->mb[1]); 3478 } else { 3479 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3480 "Done %s.\n", __func__); 3481 } 3482 3483 return rval; 3484 } 3485 3486 int 3487 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3488 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3489 { 3490 int rval; 3491 mbx_cmd_t mc; 3492 mbx_cmd_t *mcp = &mc; 3493 3494 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3495 "Entered %s.\n", __func__); 3496 3497 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3498 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3499 return QLA_FUNCTION_FAILED; 3500 3501 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3502 return QLA_FUNCTION_FAILED; 3503 3504 mcp->mb[0] = MBC_TRACE_CONTROL; 3505 mcp->mb[1] = TC_FCE_ENABLE; 3506 mcp->mb[2] = LSW(fce_dma); 3507 mcp->mb[3] = MSW(fce_dma); 3508 mcp->mb[4] = LSW(MSD(fce_dma)); 3509 mcp->mb[5] = MSW(MSD(fce_dma)); 3510 mcp->mb[6] = buffers; 3511 mcp->mb[7] = TC_AEN_DISABLE; 3512 mcp->mb[8] = 0; 3513 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3514 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3515 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3516 MBX_1|MBX_0; 3517 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3518 mcp->tov = MBX_TOV_SECONDS; 3519 mcp->flags = 0; 3520 rval = qla2x00_mailbox_command(vha, mcp); 3521 if (rval != QLA_SUCCESS) { 3522 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3523 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3524 rval, mcp->mb[0], mcp->mb[1]); 3525 } else { 3526 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3527 "Done %s.\n", __func__); 3528 3529 if (mb) 3530 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3531 if (dwords) 3532 *dwords = buffers; 3533 } 3534 3535 return rval; 3536 } 3537 3538 int 3539 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3540 { 3541 int rval; 3542 mbx_cmd_t mc; 3543 mbx_cmd_t *mcp = &mc; 3544 3545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3546 "Entered %s.\n", __func__); 3547 3548 if (!IS_FWI2_CAPABLE(vha->hw)) 3549 return QLA_FUNCTION_FAILED; 3550 3551 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3552 return QLA_FUNCTION_FAILED; 3553 3554 mcp->mb[0] = MBC_TRACE_CONTROL; 3555 mcp->mb[1] = TC_FCE_DISABLE; 3556 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3557 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3558 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3559 MBX_1|MBX_0; 3560 mcp->tov = MBX_TOV_SECONDS; 3561 mcp->flags = 0; 3562 rval = qla2x00_mailbox_command(vha, mcp); 3563 if (rval != QLA_SUCCESS) { 3564 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3565 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3566 rval, mcp->mb[0], mcp->mb[1]); 3567 } else { 3568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3569 "Done %s.\n", __func__); 3570 3571 if (wr) 3572 *wr = (uint64_t) mcp->mb[5] << 48 | 3573 (uint64_t) mcp->mb[4] << 32 | 3574 (uint64_t) mcp->mb[3] << 16 | 3575 (uint64_t) mcp->mb[2]; 3576 if (rd) 3577 *rd = (uint64_t) mcp->mb[9] << 48 | 3578 (uint64_t) mcp->mb[8] << 32 | 3579 (uint64_t) mcp->mb[7] << 16 | 3580 (uint64_t) mcp->mb[6]; 3581 } 3582 3583 return rval; 3584 } 3585 3586 int 3587 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3588 uint16_t *port_speed, uint16_t *mb) 3589 { 3590 int rval; 3591 mbx_cmd_t mc; 3592 mbx_cmd_t *mcp = &mc; 3593 3594 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3595 "Entered %s.\n", __func__); 3596 3597 if (!IS_IIDMA_CAPABLE(vha->hw)) 3598 return QLA_FUNCTION_FAILED; 3599 3600 mcp->mb[0] = MBC_PORT_PARAMS; 3601 mcp->mb[1] = loop_id; 3602 mcp->mb[2] = mcp->mb[3] = 0; 3603 mcp->mb[9] = vha->vp_idx; 3604 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3605 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3606 mcp->tov = MBX_TOV_SECONDS; 3607 mcp->flags = 0; 3608 rval = qla2x00_mailbox_command(vha, mcp); 3609 3610 /* Return mailbox statuses. */ 3611 if (mb != NULL) { 3612 mb[0] = mcp->mb[0]; 3613 mb[1] = mcp->mb[1]; 3614 mb[3] = mcp->mb[3]; 3615 } 3616 3617 if (rval != QLA_SUCCESS) { 3618 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3619 } else { 3620 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3621 "Done %s.\n", __func__); 3622 if (port_speed) 3623 *port_speed = mcp->mb[3]; 3624 } 3625 3626 return rval; 3627 } 3628 3629 int 3630 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3631 uint16_t port_speed, uint16_t *mb) 3632 { 3633 int rval; 3634 mbx_cmd_t mc; 3635 mbx_cmd_t *mcp = &mc; 3636 3637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3638 "Entered %s.\n", __func__); 3639 3640 if (!IS_IIDMA_CAPABLE(vha->hw)) 3641 return QLA_FUNCTION_FAILED; 3642 3643 mcp->mb[0] = MBC_PORT_PARAMS; 3644 mcp->mb[1] = loop_id; 3645 mcp->mb[2] = BIT_0; 3646 if (IS_CNA_CAPABLE(vha->hw)) 3647 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3648 else 3649 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3650 mcp->mb[9] = vha->vp_idx; 3651 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3652 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3653 mcp->tov = MBX_TOV_SECONDS; 3654 mcp->flags = 0; 3655 rval = qla2x00_mailbox_command(vha, mcp); 3656 3657 /* Return mailbox statuses. */ 3658 if (mb != NULL) { 3659 mb[0] = mcp->mb[0]; 3660 mb[1] = mcp->mb[1]; 3661 mb[3] = mcp->mb[3]; 3662 } 3663 3664 if (rval != QLA_SUCCESS) { 3665 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3666 "Failed=%x.\n", rval); 3667 } else { 3668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3669 "Done %s.\n", __func__); 3670 } 3671 3672 return rval; 3673 } 3674 3675 void 3676 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3677 struct vp_rpt_id_entry_24xx *rptid_entry) 3678 { 3679 uint8_t vp_idx; 3680 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 3681 struct qla_hw_data *ha = vha->hw; 3682 scsi_qla_host_t *vp; 3683 unsigned long flags; 3684 int found; 3685 3686 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3687 "Entered %s.\n", __func__); 3688 3689 if (rptid_entry->entry_status != 0) 3690 return; 3691 3692 if (rptid_entry->format == 0) { 3693 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3694 "Format 0 : Number of VPs setup %d, number of " 3695 "VPs acquired %d.\n", 3696 MSB(le16_to_cpu(rptid_entry->vp_count)), 3697 LSB(le16_to_cpu(rptid_entry->vp_count))); 3698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3699 "Primary port id %02x%02x%02x.\n", 3700 rptid_entry->port_id[2], rptid_entry->port_id[1], 3701 rptid_entry->port_id[0]); 3702 } else if (rptid_entry->format == 1) { 3703 vp_idx = LSB(stat); 3704 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3705 "Format 1: VP[%d] enabled - status %d - with " 3706 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 3707 rptid_entry->port_id[2], rptid_entry->port_id[1], 3708 rptid_entry->port_id[0]); 3709 3710 /* buffer to buffer credit flag */ 3711 vha->flags.bbcr_enable = (rptid_entry->bbcr & 0xf) != 0; 3712 3713 /* FA-WWN is only for physical port */ 3714 if (!vp_idx) { 3715 void *wwpn = ha->init_cb->port_name; 3716 3717 if (!MSB(stat)) { 3718 if (rptid_entry->vp_idx_map[1] & BIT_6) 3719 wwpn = rptid_entry->reserved_4 + 8; 3720 } 3721 memcpy(vha->port_name, wwpn, WWN_SIZE); 3722 fc_host_port_name(vha->host) = 3723 wwn_to_u64(vha->port_name); 3724 ql_dbg(ql_dbg_mbx, vha, 0x1018, 3725 "FA-WWN portname %016llx (%x)\n", 3726 fc_host_port_name(vha->host), MSB(stat)); 3727 } 3728 3729 vp = vha; 3730 if (vp_idx == 0) 3731 goto reg_needed; 3732 3733 if (MSB(stat) != 0 && MSB(stat) != 2) { 3734 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3735 "Could not acquire ID for VP[%d].\n", vp_idx); 3736 return; 3737 } 3738 3739 found = 0; 3740 spin_lock_irqsave(&ha->vport_slock, flags); 3741 list_for_each_entry(vp, &ha->vp_list, list) { 3742 if (vp_idx == vp->vp_idx) { 3743 found = 1; 3744 break; 3745 } 3746 } 3747 spin_unlock_irqrestore(&ha->vport_slock, flags); 3748 3749 if (!found) 3750 return; 3751 3752 vp->d_id.b.domain = rptid_entry->port_id[2]; 3753 vp->d_id.b.area = rptid_entry->port_id[1]; 3754 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3755 3756 /* 3757 * Cannot configure here as we are still sitting on the 3758 * response queue. Handle it in dpc context. 3759 */ 3760 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3761 3762 reg_needed: 3763 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3764 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3765 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3766 qla2xxx_wake_dpc(vha); 3767 } 3768 } 3769 3770 /* 3771 * qla24xx_modify_vp_config 3772 * Change VP configuration for vha 3773 * 3774 * Input: 3775 * vha = adapter block pointer. 3776 * 3777 * Returns: 3778 * qla2xxx local function return status code. 3779 * 3780 * Context: 3781 * Kernel context. 3782 */ 3783 int 3784 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3785 { 3786 int rval; 3787 struct vp_config_entry_24xx *vpmod; 3788 dma_addr_t vpmod_dma; 3789 struct qla_hw_data *ha = vha->hw; 3790 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3791 3792 /* This can be called by the parent */ 3793 3794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3795 "Entered %s.\n", __func__); 3796 3797 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3798 if (!vpmod) { 3799 ql_log(ql_log_warn, vha, 0x10bc, 3800 "Failed to allocate modify VP IOCB.\n"); 3801 return QLA_MEMORY_ALLOC_FAILED; 3802 } 3803 3804 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3805 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3806 vpmod->entry_count = 1; 3807 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3808 vpmod->vp_count = 1; 3809 vpmod->vp_index1 = vha->vp_idx; 3810 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3811 3812 qlt_modify_vp_config(vha, vpmod); 3813 3814 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3815 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3816 vpmod->entry_count = 1; 3817 3818 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3819 if (rval != QLA_SUCCESS) { 3820 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3821 "Failed to issue VP config IOCB (%x).\n", rval); 3822 } else if (vpmod->comp_status != 0) { 3823 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3824 "Failed to complete IOCB -- error status (%x).\n", 3825 vpmod->comp_status); 3826 rval = QLA_FUNCTION_FAILED; 3827 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 3828 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3829 "Failed to complete IOCB -- completion status (%x).\n", 3830 le16_to_cpu(vpmod->comp_status)); 3831 rval = QLA_FUNCTION_FAILED; 3832 } else { 3833 /* EMPTY */ 3834 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3835 "Done %s.\n", __func__); 3836 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3837 } 3838 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3839 3840 return rval; 3841 } 3842 3843 /* 3844 * qla24xx_control_vp 3845 * Enable a virtual port for given host 3846 * 3847 * Input: 3848 * ha = adapter block pointer. 3849 * vhba = virtual adapter (unused) 3850 * index = index number for enabled VP 3851 * 3852 * Returns: 3853 * qla2xxx local function return status code. 3854 * 3855 * Context: 3856 * Kernel context. 3857 */ 3858 int 3859 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3860 { 3861 int rval; 3862 int map, pos; 3863 struct vp_ctrl_entry_24xx *vce; 3864 dma_addr_t vce_dma; 3865 struct qla_hw_data *ha = vha->hw; 3866 int vp_index = vha->vp_idx; 3867 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3868 3869 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3870 "Entered %s enabling index %d.\n", __func__, vp_index); 3871 3872 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3873 return QLA_PARAMETER_ERROR; 3874 3875 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3876 if (!vce) { 3877 ql_log(ql_log_warn, vha, 0x10c2, 3878 "Failed to allocate VP control IOCB.\n"); 3879 return QLA_MEMORY_ALLOC_FAILED; 3880 } 3881 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3882 3883 vce->entry_type = VP_CTRL_IOCB_TYPE; 3884 vce->entry_count = 1; 3885 vce->command = cpu_to_le16(cmd); 3886 vce->vp_count = cpu_to_le16(1); 3887 3888 /* index map in firmware starts with 1; decrement index 3889 * this is ok as we never use index 0 3890 */ 3891 map = (vp_index - 1) / 8; 3892 pos = (vp_index - 1) & 7; 3893 mutex_lock(&ha->vport_lock); 3894 vce->vp_idx_map[map] |= 1 << pos; 3895 mutex_unlock(&ha->vport_lock); 3896 3897 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3898 if (rval != QLA_SUCCESS) { 3899 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3900 "Failed to issue VP control IOCB (%x).\n", rval); 3901 } else if (vce->entry_status != 0) { 3902 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3903 "Failed to complete IOCB -- error status (%x).\n", 3904 vce->entry_status); 3905 rval = QLA_FUNCTION_FAILED; 3906 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) { 3907 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3908 "Failed to complet IOCB -- completion status (%x).\n", 3909 le16_to_cpu(vce->comp_status)); 3910 rval = QLA_FUNCTION_FAILED; 3911 } else { 3912 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3913 "Done %s.\n", __func__); 3914 } 3915 3916 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3917 3918 return rval; 3919 } 3920 3921 /* 3922 * qla2x00_send_change_request 3923 * Receive or disable RSCN request from fabric controller 3924 * 3925 * Input: 3926 * ha = adapter block pointer 3927 * format = registration format: 3928 * 0 - Reserved 3929 * 1 - Fabric detected registration 3930 * 2 - N_port detected registration 3931 * 3 - Full registration 3932 * FF - clear registration 3933 * vp_idx = Virtual port index 3934 * 3935 * Returns: 3936 * qla2x00 local function return status code. 3937 * 3938 * Context: 3939 * Kernel Context 3940 */ 3941 3942 int 3943 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3944 uint16_t vp_idx) 3945 { 3946 int rval; 3947 mbx_cmd_t mc; 3948 mbx_cmd_t *mcp = &mc; 3949 3950 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3951 "Entered %s.\n", __func__); 3952 3953 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3954 mcp->mb[1] = format; 3955 mcp->mb[9] = vp_idx; 3956 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3957 mcp->in_mb = MBX_0|MBX_1; 3958 mcp->tov = MBX_TOV_SECONDS; 3959 mcp->flags = 0; 3960 rval = qla2x00_mailbox_command(vha, mcp); 3961 3962 if (rval == QLA_SUCCESS) { 3963 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3964 rval = BIT_1; 3965 } 3966 } else 3967 rval = BIT_1; 3968 3969 return rval; 3970 } 3971 3972 int 3973 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3974 uint32_t size) 3975 { 3976 int rval; 3977 mbx_cmd_t mc; 3978 mbx_cmd_t *mcp = &mc; 3979 3980 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3981 "Entered %s.\n", __func__); 3982 3983 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3984 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3985 mcp->mb[8] = MSW(addr); 3986 mcp->out_mb = MBX_8|MBX_0; 3987 } else { 3988 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3989 mcp->out_mb = MBX_0; 3990 } 3991 mcp->mb[1] = LSW(addr); 3992 mcp->mb[2] = MSW(req_dma); 3993 mcp->mb[3] = LSW(req_dma); 3994 mcp->mb[6] = MSW(MSD(req_dma)); 3995 mcp->mb[7] = LSW(MSD(req_dma)); 3996 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3997 if (IS_FWI2_CAPABLE(vha->hw)) { 3998 mcp->mb[4] = MSW(size); 3999 mcp->mb[5] = LSW(size); 4000 mcp->out_mb |= MBX_5|MBX_4; 4001 } else { 4002 mcp->mb[4] = LSW(size); 4003 mcp->out_mb |= MBX_4; 4004 } 4005 4006 mcp->in_mb = MBX_0; 4007 mcp->tov = MBX_TOV_SECONDS; 4008 mcp->flags = 0; 4009 rval = qla2x00_mailbox_command(vha, mcp); 4010 4011 if (rval != QLA_SUCCESS) { 4012 ql_dbg(ql_dbg_mbx, vha, 0x1008, 4013 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4014 } else { 4015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 4016 "Done %s.\n", __func__); 4017 } 4018 4019 return rval; 4020 } 4021 /* 84XX Support **************************************************************/ 4022 4023 struct cs84xx_mgmt_cmd { 4024 union { 4025 struct verify_chip_entry_84xx req; 4026 struct verify_chip_rsp_84xx rsp; 4027 } p; 4028 }; 4029 4030 int 4031 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 4032 { 4033 int rval, retry; 4034 struct cs84xx_mgmt_cmd *mn; 4035 dma_addr_t mn_dma; 4036 uint16_t options; 4037 unsigned long flags; 4038 struct qla_hw_data *ha = vha->hw; 4039 4040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 4041 "Entered %s.\n", __func__); 4042 4043 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 4044 if (mn == NULL) { 4045 return QLA_MEMORY_ALLOC_FAILED; 4046 } 4047 4048 /* Force Update? */ 4049 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 4050 /* Diagnostic firmware? */ 4051 /* options |= MENLO_DIAG_FW; */ 4052 /* We update the firmware with only one data sequence. */ 4053 options |= VCO_END_OF_DATA; 4054 4055 do { 4056 retry = 0; 4057 memset(mn, 0, sizeof(*mn)); 4058 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 4059 mn->p.req.entry_count = 1; 4060 mn->p.req.options = cpu_to_le16(options); 4061 4062 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 4063 "Dump of Verify Request.\n"); 4064 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 4065 (uint8_t *)mn, sizeof(*mn)); 4066 4067 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 4068 if (rval != QLA_SUCCESS) { 4069 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 4070 "Failed to issue verify IOCB (%x).\n", rval); 4071 goto verify_done; 4072 } 4073 4074 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 4075 "Dump of Verify Response.\n"); 4076 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 4077 (uint8_t *)mn, sizeof(*mn)); 4078 4079 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 4080 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 4081 le16_to_cpu(mn->p.rsp.failure_code) : 0; 4082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 4083 "cs=%x fc=%x.\n", status[0], status[1]); 4084 4085 if (status[0] != CS_COMPLETE) { 4086 rval = QLA_FUNCTION_FAILED; 4087 if (!(options & VCO_DONT_UPDATE_FW)) { 4088 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 4089 "Firmware update failed. Retrying " 4090 "without update firmware.\n"); 4091 options |= VCO_DONT_UPDATE_FW; 4092 options &= ~VCO_FORCE_UPDATE; 4093 retry = 1; 4094 } 4095 } else { 4096 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 4097 "Firmware updated to %x.\n", 4098 le32_to_cpu(mn->p.rsp.fw_ver)); 4099 4100 /* NOTE: we only update OP firmware. */ 4101 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 4102 ha->cs84xx->op_fw_version = 4103 le32_to_cpu(mn->p.rsp.fw_ver); 4104 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 4105 flags); 4106 } 4107 } while (retry); 4108 4109 verify_done: 4110 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 4111 4112 if (rval != QLA_SUCCESS) { 4113 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 4114 "Failed=%x.\n", rval); 4115 } else { 4116 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 4117 "Done %s.\n", __func__); 4118 } 4119 4120 return rval; 4121 } 4122 4123 int 4124 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 4125 { 4126 int rval; 4127 unsigned long flags; 4128 mbx_cmd_t mc; 4129 mbx_cmd_t *mcp = &mc; 4130 struct qla_hw_data *ha = vha->hw; 4131 4132 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 4133 "Entered %s.\n", __func__); 4134 4135 if (IS_SHADOW_REG_CAPABLE(ha)) 4136 req->options |= BIT_13; 4137 4138 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4139 mcp->mb[1] = req->options; 4140 mcp->mb[2] = MSW(LSD(req->dma)); 4141 mcp->mb[3] = LSW(LSD(req->dma)); 4142 mcp->mb[6] = MSW(MSD(req->dma)); 4143 mcp->mb[7] = LSW(MSD(req->dma)); 4144 mcp->mb[5] = req->length; 4145 if (req->rsp) 4146 mcp->mb[10] = req->rsp->id; 4147 mcp->mb[12] = req->qos; 4148 mcp->mb[11] = req->vp_idx; 4149 mcp->mb[13] = req->rid; 4150 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4151 mcp->mb[15] = 0; 4152 4153 mcp->mb[4] = req->id; 4154 /* que in ptr index */ 4155 mcp->mb[8] = 0; 4156 /* que out ptr index */ 4157 mcp->mb[9] = *req->out_ptr = 0; 4158 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 4159 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4160 mcp->in_mb = MBX_0; 4161 mcp->flags = MBX_DMA_OUT; 4162 mcp->tov = MBX_TOV_SECONDS * 2; 4163 4164 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4165 mcp->in_mb |= MBX_1; 4166 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4167 mcp->out_mb |= MBX_15; 4168 /* debug q create issue in SR-IOV */ 4169 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4170 } 4171 4172 spin_lock_irqsave(&ha->hardware_lock, flags); 4173 if (!(req->options & BIT_0)) { 4174 WRT_REG_DWORD(req->req_q_in, 0); 4175 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4176 WRT_REG_DWORD(req->req_q_out, 0); 4177 } 4178 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4179 4180 rval = qla2x00_mailbox_command(vha, mcp); 4181 if (rval != QLA_SUCCESS) { 4182 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 4183 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4184 } else { 4185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 4186 "Done %s.\n", __func__); 4187 } 4188 4189 return rval; 4190 } 4191 4192 int 4193 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 4194 { 4195 int rval; 4196 unsigned long flags; 4197 mbx_cmd_t mc; 4198 mbx_cmd_t *mcp = &mc; 4199 struct qla_hw_data *ha = vha->hw; 4200 4201 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 4202 "Entered %s.\n", __func__); 4203 4204 if (IS_SHADOW_REG_CAPABLE(ha)) 4205 rsp->options |= BIT_13; 4206 4207 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4208 mcp->mb[1] = rsp->options; 4209 mcp->mb[2] = MSW(LSD(rsp->dma)); 4210 mcp->mb[3] = LSW(LSD(rsp->dma)); 4211 mcp->mb[6] = MSW(MSD(rsp->dma)); 4212 mcp->mb[7] = LSW(MSD(rsp->dma)); 4213 mcp->mb[5] = rsp->length; 4214 mcp->mb[14] = rsp->msix->entry; 4215 mcp->mb[13] = rsp->rid; 4216 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4217 mcp->mb[15] = 0; 4218 4219 mcp->mb[4] = rsp->id; 4220 /* que in ptr index */ 4221 mcp->mb[8] = *rsp->in_ptr = 0; 4222 /* que out ptr index */ 4223 mcp->mb[9] = 0; 4224 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 4225 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4226 mcp->in_mb = MBX_0; 4227 mcp->flags = MBX_DMA_OUT; 4228 mcp->tov = MBX_TOV_SECONDS * 2; 4229 4230 if (IS_QLA81XX(ha)) { 4231 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 4232 mcp->in_mb |= MBX_1; 4233 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4234 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 4235 mcp->in_mb |= MBX_1; 4236 /* debug q create issue in SR-IOV */ 4237 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4238 } 4239 4240 spin_lock_irqsave(&ha->hardware_lock, flags); 4241 if (!(rsp->options & BIT_0)) { 4242 WRT_REG_DWORD(rsp->rsp_q_out, 0); 4243 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4244 WRT_REG_DWORD(rsp->rsp_q_in, 0); 4245 } 4246 4247 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4248 4249 rval = qla2x00_mailbox_command(vha, mcp); 4250 if (rval != QLA_SUCCESS) { 4251 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 4252 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4253 } else { 4254 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 4255 "Done %s.\n", __func__); 4256 } 4257 4258 return rval; 4259 } 4260 4261 int 4262 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 4263 { 4264 int rval; 4265 mbx_cmd_t mc; 4266 mbx_cmd_t *mcp = &mc; 4267 4268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 4269 "Entered %s.\n", __func__); 4270 4271 mcp->mb[0] = MBC_IDC_ACK; 4272 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4273 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4274 mcp->in_mb = MBX_0; 4275 mcp->tov = MBX_TOV_SECONDS; 4276 mcp->flags = 0; 4277 rval = qla2x00_mailbox_command(vha, mcp); 4278 4279 if (rval != QLA_SUCCESS) { 4280 ql_dbg(ql_dbg_mbx, vha, 0x10da, 4281 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4282 } else { 4283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 4284 "Done %s.\n", __func__); 4285 } 4286 4287 return rval; 4288 } 4289 4290 int 4291 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 4292 { 4293 int rval; 4294 mbx_cmd_t mc; 4295 mbx_cmd_t *mcp = &mc; 4296 4297 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 4298 "Entered %s.\n", __func__); 4299 4300 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4301 !IS_QLA27XX(vha->hw)) 4302 return QLA_FUNCTION_FAILED; 4303 4304 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4305 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 4306 mcp->out_mb = MBX_1|MBX_0; 4307 mcp->in_mb = MBX_1|MBX_0; 4308 mcp->tov = MBX_TOV_SECONDS; 4309 mcp->flags = 0; 4310 rval = qla2x00_mailbox_command(vha, mcp); 4311 4312 if (rval != QLA_SUCCESS) { 4313 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 4314 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4315 rval, mcp->mb[0], mcp->mb[1]); 4316 } else { 4317 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 4318 "Done %s.\n", __func__); 4319 *sector_size = mcp->mb[1]; 4320 } 4321 4322 return rval; 4323 } 4324 4325 int 4326 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 4327 { 4328 int rval; 4329 mbx_cmd_t mc; 4330 mbx_cmd_t *mcp = &mc; 4331 4332 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4333 !IS_QLA27XX(vha->hw)) 4334 return QLA_FUNCTION_FAILED; 4335 4336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4337 "Entered %s.\n", __func__); 4338 4339 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4340 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4341 FAC_OPT_CMD_WRITE_PROTECT; 4342 mcp->out_mb = MBX_1|MBX_0; 4343 mcp->in_mb = MBX_1|MBX_0; 4344 mcp->tov = MBX_TOV_SECONDS; 4345 mcp->flags = 0; 4346 rval = qla2x00_mailbox_command(vha, mcp); 4347 4348 if (rval != QLA_SUCCESS) { 4349 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4350 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4351 rval, mcp->mb[0], mcp->mb[1]); 4352 } else { 4353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4354 "Done %s.\n", __func__); 4355 } 4356 4357 return rval; 4358 } 4359 4360 int 4361 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4362 { 4363 int rval; 4364 mbx_cmd_t mc; 4365 mbx_cmd_t *mcp = &mc; 4366 4367 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4368 !IS_QLA27XX(vha->hw)) 4369 return QLA_FUNCTION_FAILED; 4370 4371 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4372 "Entered %s.\n", __func__); 4373 4374 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4375 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4376 mcp->mb[2] = LSW(start); 4377 mcp->mb[3] = MSW(start); 4378 mcp->mb[4] = LSW(finish); 4379 mcp->mb[5] = MSW(finish); 4380 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4381 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4382 mcp->tov = MBX_TOV_SECONDS; 4383 mcp->flags = 0; 4384 rval = qla2x00_mailbox_command(vha, mcp); 4385 4386 if (rval != QLA_SUCCESS) { 4387 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4388 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4389 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4390 } else { 4391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4392 "Done %s.\n", __func__); 4393 } 4394 4395 return rval; 4396 } 4397 4398 int 4399 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4400 { 4401 int rval = 0; 4402 mbx_cmd_t mc; 4403 mbx_cmd_t *mcp = &mc; 4404 4405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4406 "Entered %s.\n", __func__); 4407 4408 mcp->mb[0] = MBC_RESTART_MPI_FW; 4409 mcp->out_mb = MBX_0; 4410 mcp->in_mb = MBX_0|MBX_1; 4411 mcp->tov = MBX_TOV_SECONDS; 4412 mcp->flags = 0; 4413 rval = qla2x00_mailbox_command(vha, mcp); 4414 4415 if (rval != QLA_SUCCESS) { 4416 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4417 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4418 rval, mcp->mb[0], mcp->mb[1]); 4419 } else { 4420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4421 "Done %s.\n", __func__); 4422 } 4423 4424 return rval; 4425 } 4426 4427 int 4428 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4429 { 4430 int rval; 4431 mbx_cmd_t mc; 4432 mbx_cmd_t *mcp = &mc; 4433 int i; 4434 int len; 4435 uint16_t *str; 4436 struct qla_hw_data *ha = vha->hw; 4437 4438 if (!IS_P3P_TYPE(ha)) 4439 return QLA_FUNCTION_FAILED; 4440 4441 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4442 "Entered %s.\n", __func__); 4443 4444 str = (void *)version; 4445 len = strlen(version); 4446 4447 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4448 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4449 mcp->out_mb = MBX_1|MBX_0; 4450 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4451 mcp->mb[i] = cpu_to_le16p(str); 4452 mcp->out_mb |= 1<<i; 4453 } 4454 for (; i < 16; i++) { 4455 mcp->mb[i] = 0; 4456 mcp->out_mb |= 1<<i; 4457 } 4458 mcp->in_mb = MBX_1|MBX_0; 4459 mcp->tov = MBX_TOV_SECONDS; 4460 mcp->flags = 0; 4461 rval = qla2x00_mailbox_command(vha, mcp); 4462 4463 if (rval != QLA_SUCCESS) { 4464 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4465 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4466 } else { 4467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4468 "Done %s.\n", __func__); 4469 } 4470 4471 return rval; 4472 } 4473 4474 int 4475 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4476 { 4477 int rval; 4478 mbx_cmd_t mc; 4479 mbx_cmd_t *mcp = &mc; 4480 int len; 4481 uint16_t dwlen; 4482 uint8_t *str; 4483 dma_addr_t str_dma; 4484 struct qla_hw_data *ha = vha->hw; 4485 4486 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4487 IS_P3P_TYPE(ha)) 4488 return QLA_FUNCTION_FAILED; 4489 4490 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4491 "Entered %s.\n", __func__); 4492 4493 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4494 if (!str) { 4495 ql_log(ql_log_warn, vha, 0x117f, 4496 "Failed to allocate driver version param.\n"); 4497 return QLA_MEMORY_ALLOC_FAILED; 4498 } 4499 4500 memcpy(str, "\x7\x3\x11\x0", 4); 4501 dwlen = str[0]; 4502 len = dwlen * 4 - 4; 4503 memset(str + 4, 0, len); 4504 if (len > strlen(version)) 4505 len = strlen(version); 4506 memcpy(str + 4, version, len); 4507 4508 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4509 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4510 mcp->mb[2] = MSW(LSD(str_dma)); 4511 mcp->mb[3] = LSW(LSD(str_dma)); 4512 mcp->mb[6] = MSW(MSD(str_dma)); 4513 mcp->mb[7] = LSW(MSD(str_dma)); 4514 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4515 mcp->in_mb = MBX_1|MBX_0; 4516 mcp->tov = MBX_TOV_SECONDS; 4517 mcp->flags = 0; 4518 rval = qla2x00_mailbox_command(vha, mcp); 4519 4520 if (rval != QLA_SUCCESS) { 4521 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4522 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4523 } else { 4524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4525 "Done %s.\n", __func__); 4526 } 4527 4528 dma_pool_free(ha->s_dma_pool, str, str_dma); 4529 4530 return rval; 4531 } 4532 4533 static int 4534 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4535 { 4536 int rval; 4537 mbx_cmd_t mc; 4538 mbx_cmd_t *mcp = &mc; 4539 4540 if (!IS_FWI2_CAPABLE(vha->hw)) 4541 return QLA_FUNCTION_FAILED; 4542 4543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4544 "Entered %s.\n", __func__); 4545 4546 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4547 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4548 mcp->out_mb = MBX_1|MBX_0; 4549 mcp->in_mb = MBX_1|MBX_0; 4550 mcp->tov = MBX_TOV_SECONDS; 4551 mcp->flags = 0; 4552 rval = qla2x00_mailbox_command(vha, mcp); 4553 *temp = mcp->mb[1]; 4554 4555 if (rval != QLA_SUCCESS) { 4556 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4557 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4558 } else { 4559 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4560 "Done %s.\n", __func__); 4561 } 4562 4563 return rval; 4564 } 4565 4566 int 4567 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4568 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4569 { 4570 int rval; 4571 mbx_cmd_t mc; 4572 mbx_cmd_t *mcp = &mc; 4573 struct qla_hw_data *ha = vha->hw; 4574 4575 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4576 "Entered %s.\n", __func__); 4577 4578 if (!IS_FWI2_CAPABLE(ha)) 4579 return QLA_FUNCTION_FAILED; 4580 4581 if (len == 1) 4582 opt |= BIT_0; 4583 4584 mcp->mb[0] = MBC_READ_SFP; 4585 mcp->mb[1] = dev; 4586 mcp->mb[2] = MSW(sfp_dma); 4587 mcp->mb[3] = LSW(sfp_dma); 4588 mcp->mb[6] = MSW(MSD(sfp_dma)); 4589 mcp->mb[7] = LSW(MSD(sfp_dma)); 4590 mcp->mb[8] = len; 4591 mcp->mb[9] = off; 4592 mcp->mb[10] = opt; 4593 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4594 mcp->in_mb = MBX_1|MBX_0; 4595 mcp->tov = MBX_TOV_SECONDS; 4596 mcp->flags = 0; 4597 rval = qla2x00_mailbox_command(vha, mcp); 4598 4599 if (opt & BIT_0) 4600 *sfp = mcp->mb[1]; 4601 4602 if (rval != QLA_SUCCESS) { 4603 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4604 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4605 } else { 4606 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4607 "Done %s.\n", __func__); 4608 } 4609 4610 return rval; 4611 } 4612 4613 int 4614 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4615 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4616 { 4617 int rval; 4618 mbx_cmd_t mc; 4619 mbx_cmd_t *mcp = &mc; 4620 struct qla_hw_data *ha = vha->hw; 4621 4622 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4623 "Entered %s.\n", __func__); 4624 4625 if (!IS_FWI2_CAPABLE(ha)) 4626 return QLA_FUNCTION_FAILED; 4627 4628 if (len == 1) 4629 opt |= BIT_0; 4630 4631 if (opt & BIT_0) 4632 len = *sfp; 4633 4634 mcp->mb[0] = MBC_WRITE_SFP; 4635 mcp->mb[1] = dev; 4636 mcp->mb[2] = MSW(sfp_dma); 4637 mcp->mb[3] = LSW(sfp_dma); 4638 mcp->mb[6] = MSW(MSD(sfp_dma)); 4639 mcp->mb[7] = LSW(MSD(sfp_dma)); 4640 mcp->mb[8] = len; 4641 mcp->mb[9] = off; 4642 mcp->mb[10] = opt; 4643 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4644 mcp->in_mb = MBX_1|MBX_0; 4645 mcp->tov = MBX_TOV_SECONDS; 4646 mcp->flags = 0; 4647 rval = qla2x00_mailbox_command(vha, mcp); 4648 4649 if (rval != QLA_SUCCESS) { 4650 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4651 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4652 } else { 4653 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4654 "Done %s.\n", __func__); 4655 } 4656 4657 return rval; 4658 } 4659 4660 int 4661 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4662 uint16_t size_in_bytes, uint16_t *actual_size) 4663 { 4664 int rval; 4665 mbx_cmd_t mc; 4666 mbx_cmd_t *mcp = &mc; 4667 4668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4669 "Entered %s.\n", __func__); 4670 4671 if (!IS_CNA_CAPABLE(vha->hw)) 4672 return QLA_FUNCTION_FAILED; 4673 4674 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4675 mcp->mb[2] = MSW(stats_dma); 4676 mcp->mb[3] = LSW(stats_dma); 4677 mcp->mb[6] = MSW(MSD(stats_dma)); 4678 mcp->mb[7] = LSW(MSD(stats_dma)); 4679 mcp->mb[8] = size_in_bytes >> 2; 4680 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4681 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4682 mcp->tov = MBX_TOV_SECONDS; 4683 mcp->flags = 0; 4684 rval = qla2x00_mailbox_command(vha, mcp); 4685 4686 if (rval != QLA_SUCCESS) { 4687 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4688 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4689 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4690 } else { 4691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4692 "Done %s.\n", __func__); 4693 4694 4695 *actual_size = mcp->mb[2] << 2; 4696 } 4697 4698 return rval; 4699 } 4700 4701 int 4702 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4703 uint16_t size) 4704 { 4705 int rval; 4706 mbx_cmd_t mc; 4707 mbx_cmd_t *mcp = &mc; 4708 4709 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4710 "Entered %s.\n", __func__); 4711 4712 if (!IS_CNA_CAPABLE(vha->hw)) 4713 return QLA_FUNCTION_FAILED; 4714 4715 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4716 mcp->mb[1] = 0; 4717 mcp->mb[2] = MSW(tlv_dma); 4718 mcp->mb[3] = LSW(tlv_dma); 4719 mcp->mb[6] = MSW(MSD(tlv_dma)); 4720 mcp->mb[7] = LSW(MSD(tlv_dma)); 4721 mcp->mb[8] = size; 4722 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4723 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4724 mcp->tov = MBX_TOV_SECONDS; 4725 mcp->flags = 0; 4726 rval = qla2x00_mailbox_command(vha, mcp); 4727 4728 if (rval != QLA_SUCCESS) { 4729 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4730 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4731 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4732 } else { 4733 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4734 "Done %s.\n", __func__); 4735 } 4736 4737 return rval; 4738 } 4739 4740 int 4741 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4742 { 4743 int rval; 4744 mbx_cmd_t mc; 4745 mbx_cmd_t *mcp = &mc; 4746 4747 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4748 "Entered %s.\n", __func__); 4749 4750 if (!IS_FWI2_CAPABLE(vha->hw)) 4751 return QLA_FUNCTION_FAILED; 4752 4753 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4754 mcp->mb[1] = LSW(risc_addr); 4755 mcp->mb[8] = MSW(risc_addr); 4756 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4757 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4758 mcp->tov = 30; 4759 mcp->flags = 0; 4760 rval = qla2x00_mailbox_command(vha, mcp); 4761 if (rval != QLA_SUCCESS) { 4762 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4763 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4764 } else { 4765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4766 "Done %s.\n", __func__); 4767 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4768 } 4769 4770 return rval; 4771 } 4772 4773 int 4774 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4775 uint16_t *mresp) 4776 { 4777 int rval; 4778 mbx_cmd_t mc; 4779 mbx_cmd_t *mcp = &mc; 4780 4781 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4782 "Entered %s.\n", __func__); 4783 4784 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4785 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4786 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4787 4788 /* transfer count */ 4789 mcp->mb[10] = LSW(mreq->transfer_size); 4790 mcp->mb[11] = MSW(mreq->transfer_size); 4791 4792 /* send data address */ 4793 mcp->mb[14] = LSW(mreq->send_dma); 4794 mcp->mb[15] = MSW(mreq->send_dma); 4795 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4796 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4797 4798 /* receive data address */ 4799 mcp->mb[16] = LSW(mreq->rcv_dma); 4800 mcp->mb[17] = MSW(mreq->rcv_dma); 4801 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4802 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4803 4804 /* Iteration count */ 4805 mcp->mb[18] = LSW(mreq->iteration_count); 4806 mcp->mb[19] = MSW(mreq->iteration_count); 4807 4808 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4809 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4810 if (IS_CNA_CAPABLE(vha->hw)) 4811 mcp->out_mb |= MBX_2; 4812 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4813 4814 mcp->buf_size = mreq->transfer_size; 4815 mcp->tov = MBX_TOV_SECONDS; 4816 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4817 4818 rval = qla2x00_mailbox_command(vha, mcp); 4819 4820 if (rval != QLA_SUCCESS) { 4821 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4822 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4823 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4824 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4825 } else { 4826 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4827 "Done %s.\n", __func__); 4828 } 4829 4830 /* Copy mailbox information */ 4831 memcpy( mresp, mcp->mb, 64); 4832 return rval; 4833 } 4834 4835 int 4836 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4837 uint16_t *mresp) 4838 { 4839 int rval; 4840 mbx_cmd_t mc; 4841 mbx_cmd_t *mcp = &mc; 4842 struct qla_hw_data *ha = vha->hw; 4843 4844 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4845 "Entered %s.\n", __func__); 4846 4847 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4848 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4849 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4850 if (IS_CNA_CAPABLE(ha)) { 4851 mcp->mb[1] |= BIT_15; 4852 mcp->mb[2] = vha->fcoe_fcf_idx; 4853 } 4854 mcp->mb[16] = LSW(mreq->rcv_dma); 4855 mcp->mb[17] = MSW(mreq->rcv_dma); 4856 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4857 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4858 4859 mcp->mb[10] = LSW(mreq->transfer_size); 4860 4861 mcp->mb[14] = LSW(mreq->send_dma); 4862 mcp->mb[15] = MSW(mreq->send_dma); 4863 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4864 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4865 4866 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4867 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4868 if (IS_CNA_CAPABLE(ha)) 4869 mcp->out_mb |= MBX_2; 4870 4871 mcp->in_mb = MBX_0; 4872 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4873 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4874 mcp->in_mb |= MBX_1; 4875 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4876 mcp->in_mb |= MBX_3; 4877 4878 mcp->tov = MBX_TOV_SECONDS; 4879 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4880 mcp->buf_size = mreq->transfer_size; 4881 4882 rval = qla2x00_mailbox_command(vha, mcp); 4883 4884 if (rval != QLA_SUCCESS) { 4885 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4886 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4887 rval, mcp->mb[0], mcp->mb[1]); 4888 } else { 4889 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4890 "Done %s.\n", __func__); 4891 } 4892 4893 /* Copy mailbox information */ 4894 memcpy(mresp, mcp->mb, 64); 4895 return rval; 4896 } 4897 4898 int 4899 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4900 { 4901 int rval; 4902 mbx_cmd_t mc; 4903 mbx_cmd_t *mcp = &mc; 4904 4905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4906 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4907 4908 mcp->mb[0] = MBC_ISP84XX_RESET; 4909 mcp->mb[1] = enable_diagnostic; 4910 mcp->out_mb = MBX_1|MBX_0; 4911 mcp->in_mb = MBX_1|MBX_0; 4912 mcp->tov = MBX_TOV_SECONDS; 4913 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4914 rval = qla2x00_mailbox_command(vha, mcp); 4915 4916 if (rval != QLA_SUCCESS) 4917 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4918 else 4919 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4920 "Done %s.\n", __func__); 4921 4922 return rval; 4923 } 4924 4925 int 4926 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4927 { 4928 int rval; 4929 mbx_cmd_t mc; 4930 mbx_cmd_t *mcp = &mc; 4931 4932 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4933 "Entered %s.\n", __func__); 4934 4935 if (!IS_FWI2_CAPABLE(vha->hw)) 4936 return QLA_FUNCTION_FAILED; 4937 4938 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4939 mcp->mb[1] = LSW(risc_addr); 4940 mcp->mb[2] = LSW(data); 4941 mcp->mb[3] = MSW(data); 4942 mcp->mb[8] = MSW(risc_addr); 4943 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4944 mcp->in_mb = MBX_0; 4945 mcp->tov = 30; 4946 mcp->flags = 0; 4947 rval = qla2x00_mailbox_command(vha, mcp); 4948 if (rval != QLA_SUCCESS) { 4949 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4950 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4951 } else { 4952 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4953 "Done %s.\n", __func__); 4954 } 4955 4956 return rval; 4957 } 4958 4959 int 4960 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4961 { 4962 int rval; 4963 uint32_t stat, timer; 4964 uint16_t mb0 = 0; 4965 struct qla_hw_data *ha = vha->hw; 4966 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4967 4968 rval = QLA_SUCCESS; 4969 4970 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4971 "Entered %s.\n", __func__); 4972 4973 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4974 4975 /* Write the MBC data to the registers */ 4976 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4977 WRT_REG_WORD(®->mailbox1, mb[0]); 4978 WRT_REG_WORD(®->mailbox2, mb[1]); 4979 WRT_REG_WORD(®->mailbox3, mb[2]); 4980 WRT_REG_WORD(®->mailbox4, mb[3]); 4981 4982 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4983 4984 /* Poll for MBC interrupt */ 4985 for (timer = 6000000; timer; timer--) { 4986 /* Check for pending interrupts. */ 4987 stat = RD_REG_DWORD(®->host_status); 4988 if (stat & HSRX_RISC_INT) { 4989 stat &= 0xff; 4990 4991 if (stat == 0x1 || stat == 0x2 || 4992 stat == 0x10 || stat == 0x11) { 4993 set_bit(MBX_INTERRUPT, 4994 &ha->mbx_cmd_flags); 4995 mb0 = RD_REG_WORD(®->mailbox0); 4996 WRT_REG_DWORD(®->hccr, 4997 HCCRX_CLR_RISC_INT); 4998 RD_REG_DWORD(®->hccr); 4999 break; 5000 } 5001 } 5002 udelay(5); 5003 } 5004 5005 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 5006 rval = mb0 & MBS_MASK; 5007 else 5008 rval = QLA_FUNCTION_FAILED; 5009 5010 if (rval != QLA_SUCCESS) { 5011 ql_dbg(ql_dbg_mbx, vha, 0x1104, 5012 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 5013 } else { 5014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 5015 "Done %s.\n", __func__); 5016 } 5017 5018 return rval; 5019 } 5020 5021 int 5022 qla2x00_get_data_rate(scsi_qla_host_t *vha) 5023 { 5024 int rval; 5025 mbx_cmd_t mc; 5026 mbx_cmd_t *mcp = &mc; 5027 struct qla_hw_data *ha = vha->hw; 5028 5029 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 5030 "Entered %s.\n", __func__); 5031 5032 if (!IS_FWI2_CAPABLE(ha)) 5033 return QLA_FUNCTION_FAILED; 5034 5035 mcp->mb[0] = MBC_DATA_RATE; 5036 mcp->mb[1] = 0; 5037 mcp->out_mb = MBX_1|MBX_0; 5038 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5039 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 5040 mcp->in_mb |= MBX_3; 5041 mcp->tov = MBX_TOV_SECONDS; 5042 mcp->flags = 0; 5043 rval = qla2x00_mailbox_command(vha, mcp); 5044 if (rval != QLA_SUCCESS) { 5045 ql_dbg(ql_dbg_mbx, vha, 0x1107, 5046 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5047 } else { 5048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 5049 "Done %s.\n", __func__); 5050 if (mcp->mb[1] != 0x7) 5051 ha->link_data_rate = mcp->mb[1]; 5052 } 5053 5054 return rval; 5055 } 5056 5057 int 5058 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5059 { 5060 int rval; 5061 mbx_cmd_t mc; 5062 mbx_cmd_t *mcp = &mc; 5063 struct qla_hw_data *ha = vha->hw; 5064 5065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 5066 "Entered %s.\n", __func__); 5067 5068 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 5069 !IS_QLA27XX(ha)) 5070 return QLA_FUNCTION_FAILED; 5071 mcp->mb[0] = MBC_GET_PORT_CONFIG; 5072 mcp->out_mb = MBX_0; 5073 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5074 mcp->tov = MBX_TOV_SECONDS; 5075 mcp->flags = 0; 5076 5077 rval = qla2x00_mailbox_command(vha, mcp); 5078 5079 if (rval != QLA_SUCCESS) { 5080 ql_dbg(ql_dbg_mbx, vha, 0x110a, 5081 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5082 } else { 5083 /* Copy all bits to preserve original value */ 5084 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 5085 5086 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 5087 "Done %s.\n", __func__); 5088 } 5089 return rval; 5090 } 5091 5092 int 5093 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5094 { 5095 int rval; 5096 mbx_cmd_t mc; 5097 mbx_cmd_t *mcp = &mc; 5098 5099 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 5100 "Entered %s.\n", __func__); 5101 5102 mcp->mb[0] = MBC_SET_PORT_CONFIG; 5103 /* Copy all bits to preserve original setting */ 5104 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 5105 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5106 mcp->in_mb = MBX_0; 5107 mcp->tov = MBX_TOV_SECONDS; 5108 mcp->flags = 0; 5109 rval = qla2x00_mailbox_command(vha, mcp); 5110 5111 if (rval != QLA_SUCCESS) { 5112 ql_dbg(ql_dbg_mbx, vha, 0x110d, 5113 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5114 } else 5115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 5116 "Done %s.\n", __func__); 5117 5118 return rval; 5119 } 5120 5121 5122 int 5123 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 5124 uint16_t *mb) 5125 { 5126 int rval; 5127 mbx_cmd_t mc; 5128 mbx_cmd_t *mcp = &mc; 5129 struct qla_hw_data *ha = vha->hw; 5130 5131 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 5132 "Entered %s.\n", __func__); 5133 5134 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 5135 return QLA_FUNCTION_FAILED; 5136 5137 mcp->mb[0] = MBC_PORT_PARAMS; 5138 mcp->mb[1] = loop_id; 5139 if (ha->flags.fcp_prio_enabled) 5140 mcp->mb[2] = BIT_1; 5141 else 5142 mcp->mb[2] = BIT_2; 5143 mcp->mb[4] = priority & 0xf; 5144 mcp->mb[9] = vha->vp_idx; 5145 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5146 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5147 mcp->tov = 30; 5148 mcp->flags = 0; 5149 rval = qla2x00_mailbox_command(vha, mcp); 5150 if (mb != NULL) { 5151 mb[0] = mcp->mb[0]; 5152 mb[1] = mcp->mb[1]; 5153 mb[3] = mcp->mb[3]; 5154 mb[4] = mcp->mb[4]; 5155 } 5156 5157 if (rval != QLA_SUCCESS) { 5158 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 5159 } else { 5160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 5161 "Done %s.\n", __func__); 5162 } 5163 5164 return rval; 5165 } 5166 5167 int 5168 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 5169 { 5170 int rval = QLA_FUNCTION_FAILED; 5171 struct qla_hw_data *ha = vha->hw; 5172 uint8_t byte; 5173 5174 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 5175 ql_dbg(ql_dbg_mbx, vha, 0x1150, 5176 "Thermal not supported by this card.\n"); 5177 return rval; 5178 } 5179 5180 if (IS_QLA25XX(ha)) { 5181 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5182 ha->pdev->subsystem_device == 0x0175) { 5183 rval = qla2x00_read_sfp(vha, 0, &byte, 5184 0x98, 0x1, 1, BIT_13|BIT_0); 5185 *temp = byte; 5186 return rval; 5187 } 5188 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 5189 ha->pdev->subsystem_device == 0x338e) { 5190 rval = qla2x00_read_sfp(vha, 0, &byte, 5191 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 5192 *temp = byte; 5193 return rval; 5194 } 5195 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 5196 "Thermal not supported by this card.\n"); 5197 return rval; 5198 } 5199 5200 if (IS_QLA82XX(ha)) { 5201 *temp = qla82xx_read_temperature(vha); 5202 rval = QLA_SUCCESS; 5203 return rval; 5204 } else if (IS_QLA8044(ha)) { 5205 *temp = qla8044_read_temperature(vha); 5206 rval = QLA_SUCCESS; 5207 return rval; 5208 } 5209 5210 rval = qla2x00_read_asic_temperature(vha, temp); 5211 return rval; 5212 } 5213 5214 int 5215 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 5216 { 5217 int rval; 5218 struct qla_hw_data *ha = vha->hw; 5219 mbx_cmd_t mc; 5220 mbx_cmd_t *mcp = &mc; 5221 5222 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 5223 "Entered %s.\n", __func__); 5224 5225 if (!IS_FWI2_CAPABLE(ha)) 5226 return QLA_FUNCTION_FAILED; 5227 5228 memset(mcp, 0, sizeof(mbx_cmd_t)); 5229 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5230 mcp->mb[1] = 1; 5231 5232 mcp->out_mb = MBX_1|MBX_0; 5233 mcp->in_mb = MBX_0; 5234 mcp->tov = 30; 5235 mcp->flags = 0; 5236 5237 rval = qla2x00_mailbox_command(vha, mcp); 5238 if (rval != QLA_SUCCESS) { 5239 ql_dbg(ql_dbg_mbx, vha, 0x1016, 5240 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5241 } else { 5242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 5243 "Done %s.\n", __func__); 5244 } 5245 5246 return rval; 5247 } 5248 5249 int 5250 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 5251 { 5252 int rval; 5253 struct qla_hw_data *ha = vha->hw; 5254 mbx_cmd_t mc; 5255 mbx_cmd_t *mcp = &mc; 5256 5257 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 5258 "Entered %s.\n", __func__); 5259 5260 if (!IS_P3P_TYPE(ha)) 5261 return QLA_FUNCTION_FAILED; 5262 5263 memset(mcp, 0, sizeof(mbx_cmd_t)); 5264 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5265 mcp->mb[1] = 0; 5266 5267 mcp->out_mb = MBX_1|MBX_0; 5268 mcp->in_mb = MBX_0; 5269 mcp->tov = 30; 5270 mcp->flags = 0; 5271 5272 rval = qla2x00_mailbox_command(vha, mcp); 5273 if (rval != QLA_SUCCESS) { 5274 ql_dbg(ql_dbg_mbx, vha, 0x100c, 5275 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5276 } else { 5277 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 5278 "Done %s.\n", __func__); 5279 } 5280 5281 return rval; 5282 } 5283 5284 int 5285 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 5286 { 5287 struct qla_hw_data *ha = vha->hw; 5288 mbx_cmd_t mc; 5289 mbx_cmd_t *mcp = &mc; 5290 int rval = QLA_FUNCTION_FAILED; 5291 5292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 5293 "Entered %s.\n", __func__); 5294 5295 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5296 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5297 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5298 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 5299 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 5300 5301 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5302 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 5303 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5304 5305 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5306 mcp->tov = MBX_TOV_SECONDS; 5307 rval = qla2x00_mailbox_command(vha, mcp); 5308 5309 /* Always copy back return mailbox values. */ 5310 if (rval != QLA_SUCCESS) { 5311 ql_dbg(ql_dbg_mbx, vha, 0x1120, 5312 "mailbox command FAILED=0x%x, subcode=%x.\n", 5313 (mcp->mb[1] << 16) | mcp->mb[0], 5314 (mcp->mb[3] << 16) | mcp->mb[2]); 5315 } else { 5316 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 5317 "Done %s.\n", __func__); 5318 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 5319 if (!ha->md_template_size) { 5320 ql_dbg(ql_dbg_mbx, vha, 0x1122, 5321 "Null template size obtained.\n"); 5322 rval = QLA_FUNCTION_FAILED; 5323 } 5324 } 5325 return rval; 5326 } 5327 5328 int 5329 qla82xx_md_get_template(scsi_qla_host_t *vha) 5330 { 5331 struct qla_hw_data *ha = vha->hw; 5332 mbx_cmd_t mc; 5333 mbx_cmd_t *mcp = &mc; 5334 int rval = QLA_FUNCTION_FAILED; 5335 5336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5337 "Entered %s.\n", __func__); 5338 5339 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5340 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5341 if (!ha->md_tmplt_hdr) { 5342 ql_log(ql_log_warn, vha, 0x1124, 5343 "Unable to allocate memory for Minidump template.\n"); 5344 return rval; 5345 } 5346 5347 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5348 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5349 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5350 mcp->mb[2] = LSW(RQST_TMPLT); 5351 mcp->mb[3] = MSW(RQST_TMPLT); 5352 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5353 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5354 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5355 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5356 mcp->mb[8] = LSW(ha->md_template_size); 5357 mcp->mb[9] = MSW(ha->md_template_size); 5358 5359 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5360 mcp->tov = MBX_TOV_SECONDS; 5361 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5362 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5363 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5364 rval = qla2x00_mailbox_command(vha, mcp); 5365 5366 if (rval != QLA_SUCCESS) { 5367 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5368 "mailbox command FAILED=0x%x, subcode=%x.\n", 5369 ((mcp->mb[1] << 16) | mcp->mb[0]), 5370 ((mcp->mb[3] << 16) | mcp->mb[2])); 5371 } else 5372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5373 "Done %s.\n", __func__); 5374 return rval; 5375 } 5376 5377 int 5378 qla8044_md_get_template(scsi_qla_host_t *vha) 5379 { 5380 struct qla_hw_data *ha = vha->hw; 5381 mbx_cmd_t mc; 5382 mbx_cmd_t *mcp = &mc; 5383 int rval = QLA_FUNCTION_FAILED; 5384 int offset = 0, size = MINIDUMP_SIZE_36K; 5385 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5386 "Entered %s.\n", __func__); 5387 5388 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5389 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5390 if (!ha->md_tmplt_hdr) { 5391 ql_log(ql_log_warn, vha, 0xb11b, 5392 "Unable to allocate memory for Minidump template.\n"); 5393 return rval; 5394 } 5395 5396 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5397 while (offset < ha->md_template_size) { 5398 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5399 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5400 mcp->mb[2] = LSW(RQST_TMPLT); 5401 mcp->mb[3] = MSW(RQST_TMPLT); 5402 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5403 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5404 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5405 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5406 mcp->mb[8] = LSW(size); 5407 mcp->mb[9] = MSW(size); 5408 mcp->mb[10] = offset & 0x0000FFFF; 5409 mcp->mb[11] = offset & 0xFFFF0000; 5410 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5411 mcp->tov = MBX_TOV_SECONDS; 5412 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5413 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5414 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5415 rval = qla2x00_mailbox_command(vha, mcp); 5416 5417 if (rval != QLA_SUCCESS) { 5418 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5419 "mailbox command FAILED=0x%x, subcode=%x.\n", 5420 ((mcp->mb[1] << 16) | mcp->mb[0]), 5421 ((mcp->mb[3] << 16) | mcp->mb[2])); 5422 return rval; 5423 } else 5424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5425 "Done %s.\n", __func__); 5426 offset = offset + size; 5427 } 5428 return rval; 5429 } 5430 5431 int 5432 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5433 { 5434 int rval; 5435 struct qla_hw_data *ha = vha->hw; 5436 mbx_cmd_t mc; 5437 mbx_cmd_t *mcp = &mc; 5438 5439 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5440 return QLA_FUNCTION_FAILED; 5441 5442 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5443 "Entered %s.\n", __func__); 5444 5445 memset(mcp, 0, sizeof(mbx_cmd_t)); 5446 mcp->mb[0] = MBC_SET_LED_CONFIG; 5447 mcp->mb[1] = led_cfg[0]; 5448 mcp->mb[2] = led_cfg[1]; 5449 if (IS_QLA8031(ha)) { 5450 mcp->mb[3] = led_cfg[2]; 5451 mcp->mb[4] = led_cfg[3]; 5452 mcp->mb[5] = led_cfg[4]; 5453 mcp->mb[6] = led_cfg[5]; 5454 } 5455 5456 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5457 if (IS_QLA8031(ha)) 5458 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5459 mcp->in_mb = MBX_0; 5460 mcp->tov = 30; 5461 mcp->flags = 0; 5462 5463 rval = qla2x00_mailbox_command(vha, mcp); 5464 if (rval != QLA_SUCCESS) { 5465 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5466 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5467 } else { 5468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5469 "Done %s.\n", __func__); 5470 } 5471 5472 return rval; 5473 } 5474 5475 int 5476 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5477 { 5478 int rval; 5479 struct qla_hw_data *ha = vha->hw; 5480 mbx_cmd_t mc; 5481 mbx_cmd_t *mcp = &mc; 5482 5483 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5484 return QLA_FUNCTION_FAILED; 5485 5486 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5487 "Entered %s.\n", __func__); 5488 5489 memset(mcp, 0, sizeof(mbx_cmd_t)); 5490 mcp->mb[0] = MBC_GET_LED_CONFIG; 5491 5492 mcp->out_mb = MBX_0; 5493 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5494 if (IS_QLA8031(ha)) 5495 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5496 mcp->tov = 30; 5497 mcp->flags = 0; 5498 5499 rval = qla2x00_mailbox_command(vha, mcp); 5500 if (rval != QLA_SUCCESS) { 5501 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5502 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5503 } else { 5504 led_cfg[0] = mcp->mb[1]; 5505 led_cfg[1] = mcp->mb[2]; 5506 if (IS_QLA8031(ha)) { 5507 led_cfg[2] = mcp->mb[3]; 5508 led_cfg[3] = mcp->mb[4]; 5509 led_cfg[4] = mcp->mb[5]; 5510 led_cfg[5] = mcp->mb[6]; 5511 } 5512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5513 "Done %s.\n", __func__); 5514 } 5515 5516 return rval; 5517 } 5518 5519 int 5520 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5521 { 5522 int rval; 5523 struct qla_hw_data *ha = vha->hw; 5524 mbx_cmd_t mc; 5525 mbx_cmd_t *mcp = &mc; 5526 5527 if (!IS_P3P_TYPE(ha)) 5528 return QLA_FUNCTION_FAILED; 5529 5530 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5531 "Entered %s.\n", __func__); 5532 5533 memset(mcp, 0, sizeof(mbx_cmd_t)); 5534 mcp->mb[0] = MBC_SET_LED_CONFIG; 5535 if (enable) 5536 mcp->mb[7] = 0xE; 5537 else 5538 mcp->mb[7] = 0xD; 5539 5540 mcp->out_mb = MBX_7|MBX_0; 5541 mcp->in_mb = MBX_0; 5542 mcp->tov = MBX_TOV_SECONDS; 5543 mcp->flags = 0; 5544 5545 rval = qla2x00_mailbox_command(vha, mcp); 5546 if (rval != QLA_SUCCESS) { 5547 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5548 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5549 } else { 5550 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5551 "Done %s.\n", __func__); 5552 } 5553 5554 return rval; 5555 } 5556 5557 int 5558 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5559 { 5560 int rval; 5561 struct qla_hw_data *ha = vha->hw; 5562 mbx_cmd_t mc; 5563 mbx_cmd_t *mcp = &mc; 5564 5565 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5566 return QLA_FUNCTION_FAILED; 5567 5568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5569 "Entered %s.\n", __func__); 5570 5571 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5572 mcp->mb[1] = LSW(reg); 5573 mcp->mb[2] = MSW(reg); 5574 mcp->mb[3] = LSW(data); 5575 mcp->mb[4] = MSW(data); 5576 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5577 5578 mcp->in_mb = MBX_1|MBX_0; 5579 mcp->tov = MBX_TOV_SECONDS; 5580 mcp->flags = 0; 5581 rval = qla2x00_mailbox_command(vha, mcp); 5582 5583 if (rval != QLA_SUCCESS) { 5584 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5585 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5586 } else { 5587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5588 "Done %s.\n", __func__); 5589 } 5590 5591 return rval; 5592 } 5593 5594 int 5595 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5596 { 5597 int rval; 5598 struct qla_hw_data *ha = vha->hw; 5599 mbx_cmd_t mc; 5600 mbx_cmd_t *mcp = &mc; 5601 5602 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5603 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5604 "Implicit LOGO Unsupported.\n"); 5605 return QLA_FUNCTION_FAILED; 5606 } 5607 5608 5609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5610 "Entering %s.\n", __func__); 5611 5612 /* Perform Implicit LOGO. */ 5613 mcp->mb[0] = MBC_PORT_LOGOUT; 5614 mcp->mb[1] = fcport->loop_id; 5615 mcp->mb[10] = BIT_15; 5616 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5617 mcp->in_mb = MBX_0; 5618 mcp->tov = MBX_TOV_SECONDS; 5619 mcp->flags = 0; 5620 rval = qla2x00_mailbox_command(vha, mcp); 5621 if (rval != QLA_SUCCESS) 5622 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5623 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5624 else 5625 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5626 "Done %s.\n", __func__); 5627 5628 return rval; 5629 } 5630 5631 int 5632 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5633 { 5634 int rval; 5635 mbx_cmd_t mc; 5636 mbx_cmd_t *mcp = &mc; 5637 struct qla_hw_data *ha = vha->hw; 5638 unsigned long retry_max_time = jiffies + (2 * HZ); 5639 5640 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5641 return QLA_FUNCTION_FAILED; 5642 5643 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5644 5645 retry_rd_reg: 5646 mcp->mb[0] = MBC_READ_REMOTE_REG; 5647 mcp->mb[1] = LSW(reg); 5648 mcp->mb[2] = MSW(reg); 5649 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5650 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5651 mcp->tov = MBX_TOV_SECONDS; 5652 mcp->flags = 0; 5653 rval = qla2x00_mailbox_command(vha, mcp); 5654 5655 if (rval != QLA_SUCCESS) { 5656 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5657 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5658 rval, mcp->mb[0], mcp->mb[1]); 5659 } else { 5660 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5661 if (*data == QLA8XXX_BAD_VALUE) { 5662 /* 5663 * During soft-reset CAMRAM register reads might 5664 * return 0xbad0bad0. So retry for MAX of 2 sec 5665 * while reading camram registers. 5666 */ 5667 if (time_after(jiffies, retry_max_time)) { 5668 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5669 "Failure to read CAMRAM register. " 5670 "data=0x%x.\n", *data); 5671 return QLA_FUNCTION_FAILED; 5672 } 5673 msleep(100); 5674 goto retry_rd_reg; 5675 } 5676 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5677 } 5678 5679 return rval; 5680 } 5681 5682 int 5683 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5684 { 5685 int rval; 5686 mbx_cmd_t mc; 5687 mbx_cmd_t *mcp = &mc; 5688 struct qla_hw_data *ha = vha->hw; 5689 5690 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5691 return QLA_FUNCTION_FAILED; 5692 5693 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5694 5695 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5696 mcp->out_mb = MBX_0; 5697 mcp->in_mb = MBX_1|MBX_0; 5698 mcp->tov = MBX_TOV_SECONDS; 5699 mcp->flags = 0; 5700 rval = qla2x00_mailbox_command(vha, mcp); 5701 5702 if (rval != QLA_SUCCESS) { 5703 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5704 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5705 rval, mcp->mb[0], mcp->mb[1]); 5706 ha->isp_ops->fw_dump(vha, 0); 5707 } else { 5708 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5709 } 5710 5711 return rval; 5712 } 5713 5714 int 5715 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5716 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5717 { 5718 int rval; 5719 mbx_cmd_t mc; 5720 mbx_cmd_t *mcp = &mc; 5721 uint8_t subcode = (uint8_t)options; 5722 struct qla_hw_data *ha = vha->hw; 5723 5724 if (!IS_QLA8031(ha)) 5725 return QLA_FUNCTION_FAILED; 5726 5727 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5728 5729 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5730 mcp->mb[1] = options; 5731 mcp->out_mb = MBX_1|MBX_0; 5732 if (subcode & BIT_2) { 5733 mcp->mb[2] = LSW(start_addr); 5734 mcp->mb[3] = MSW(start_addr); 5735 mcp->mb[4] = LSW(end_addr); 5736 mcp->mb[5] = MSW(end_addr); 5737 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5738 } 5739 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5740 if (!(subcode & (BIT_2 | BIT_5))) 5741 mcp->in_mb |= MBX_4|MBX_3; 5742 mcp->tov = MBX_TOV_SECONDS; 5743 mcp->flags = 0; 5744 rval = qla2x00_mailbox_command(vha, mcp); 5745 5746 if (rval != QLA_SUCCESS) { 5747 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5748 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5749 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5750 mcp->mb[4]); 5751 ha->isp_ops->fw_dump(vha, 0); 5752 } else { 5753 if (subcode & BIT_5) 5754 *sector_size = mcp->mb[1]; 5755 else if (subcode & (BIT_6 | BIT_7)) { 5756 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5757 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5758 } else if (subcode & (BIT_3 | BIT_4)) { 5759 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5760 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5761 } 5762 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5763 } 5764 5765 return rval; 5766 } 5767 5768 int 5769 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5770 uint32_t size) 5771 { 5772 int rval; 5773 mbx_cmd_t mc; 5774 mbx_cmd_t *mcp = &mc; 5775 5776 if (!IS_MCTP_CAPABLE(vha->hw)) 5777 return QLA_FUNCTION_FAILED; 5778 5779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5780 "Entered %s.\n", __func__); 5781 5782 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5783 mcp->mb[1] = LSW(addr); 5784 mcp->mb[2] = MSW(req_dma); 5785 mcp->mb[3] = LSW(req_dma); 5786 mcp->mb[4] = MSW(size); 5787 mcp->mb[5] = LSW(size); 5788 mcp->mb[6] = MSW(MSD(req_dma)); 5789 mcp->mb[7] = LSW(MSD(req_dma)); 5790 mcp->mb[8] = MSW(addr); 5791 /* Setting RAM ID to valid */ 5792 mcp->mb[10] |= BIT_7; 5793 /* For MCTP RAM ID is 0x40 */ 5794 mcp->mb[10] |= 0x40; 5795 5796 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5797 MBX_0; 5798 5799 mcp->in_mb = MBX_0; 5800 mcp->tov = MBX_TOV_SECONDS; 5801 mcp->flags = 0; 5802 rval = qla2x00_mailbox_command(vha, mcp); 5803 5804 if (rval != QLA_SUCCESS) { 5805 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5806 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5807 } else { 5808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5809 "Done %s.\n", __func__); 5810 } 5811 5812 return rval; 5813 } 5814 5815 int 5816 qla26xx_dport_diagnostics(scsi_qla_host_t *vha, 5817 void *dd_buf, uint size, uint options) 5818 { 5819 int rval; 5820 mbx_cmd_t mc; 5821 mbx_cmd_t *mcp = &mc; 5822 dma_addr_t dd_dma; 5823 5824 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 5825 return QLA_FUNCTION_FAILED; 5826 5827 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 5828 "Entered %s.\n", __func__); 5829 5830 dd_dma = dma_map_single(&vha->hw->pdev->dev, 5831 dd_buf, size, DMA_FROM_DEVICE); 5832 if (!dd_dma) { 5833 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n"); 5834 return QLA_MEMORY_ALLOC_FAILED; 5835 } 5836 5837 memset(dd_buf, 0, size); 5838 5839 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS; 5840 mcp->mb[1] = options; 5841 mcp->mb[2] = MSW(LSD(dd_dma)); 5842 mcp->mb[3] = LSW(LSD(dd_dma)); 5843 mcp->mb[6] = MSW(MSD(dd_dma)); 5844 mcp->mb[7] = LSW(MSD(dd_dma)); 5845 mcp->mb[8] = size; 5846 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5847 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5848 mcp->buf_size = size; 5849 mcp->flags = MBX_DMA_IN; 5850 mcp->tov = MBX_TOV_SECONDS * 4; 5851 rval = qla2x00_mailbox_command(vha, mcp); 5852 5853 if (rval != QLA_SUCCESS) { 5854 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval); 5855 } else { 5856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196, 5857 "Done %s.\n", __func__); 5858 } 5859 5860 dma_unmap_single(&vha->hw->pdev->dev, dd_dma, 5861 size, DMA_FROM_DEVICE); 5862 5863 return rval; 5864 } 5865