1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 14 /* 15 * qla2x00_mailbox_command 16 * Issue mailbox command and waits for completion. 17 * 18 * Input: 19 * ha = adapter block pointer. 20 * mcp = driver internal mbx struct pointer. 21 * 22 * Output: 23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 24 * 25 * Returns: 26 * 0 : QLA_SUCCESS = cmd performed success 27 * 1 : QLA_FUNCTION_FAILED (error encountered) 28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 29 * 30 * Context: 31 * Kernel context. 32 */ 33 static int 34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 35 { 36 int rval; 37 unsigned long flags = 0; 38 device_reg_t *reg; 39 uint8_t abort_active; 40 uint8_t io_lock_on; 41 uint16_t command = 0; 42 uint16_t *iptr; 43 uint16_t __iomem *optr; 44 uint32_t cnt; 45 uint32_t mboxes; 46 unsigned long wait_time; 47 struct qla_hw_data *ha = vha->hw; 48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 49 50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 51 52 if (ha->pdev->error_state > pci_channel_io_frozen) { 53 ql_log(ql_log_warn, vha, 0x1001, 54 "error_state is greater than pci_channel_io_frozen, " 55 "exiting.\n"); 56 return QLA_FUNCTION_TIMEOUT; 57 } 58 59 if (vha->device_flags & DFLG_DEV_FAILED) { 60 ql_log(ql_log_warn, vha, 0x1002, 61 "Device in failed state, exiting.\n"); 62 return QLA_FUNCTION_TIMEOUT; 63 } 64 65 reg = ha->iobase; 66 io_lock_on = base_vha->flags.init_done; 67 68 rval = QLA_SUCCESS; 69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 70 71 72 if (ha->flags.pci_channel_io_perm_failure) { 73 ql_log(ql_log_warn, vha, 0x1003, 74 "Perm failure on EEH timeout MBX, exiting.\n"); 75 return QLA_FUNCTION_TIMEOUT; 76 } 77 78 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 79 /* Setting Link-Down error */ 80 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 81 ql_log(ql_log_warn, vha, 0x1004, 82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 83 return QLA_FUNCTION_TIMEOUT; 84 } 85 86 /* 87 * Wait for active mailbox commands to finish by waiting at most tov 88 * seconds. This is to serialize actual issuing of mailbox cmds during 89 * non ISP abort time. 90 */ 91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 92 /* Timeout occurred. Return error. */ 93 ql_log(ql_log_warn, vha, 0x1005, 94 "Cmd access timeout, cmd=0x%x, Exiting.\n", 95 mcp->mb[0]); 96 return QLA_FUNCTION_TIMEOUT; 97 } 98 99 ha->flags.mbox_busy = 1; 100 /* Save mailbox command for debug */ 101 ha->mcp = mcp; 102 103 ql_dbg(ql_dbg_mbx, vha, 0x1006, 104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 105 106 spin_lock_irqsave(&ha->hardware_lock, flags); 107 108 /* Load mailbox registers. */ 109 if (IS_P3P_TYPE(ha)) 110 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 111 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 112 optr = (uint16_t __iomem *)®->isp24.mailbox0; 113 else 114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 115 116 iptr = mcp->mb; 117 command = mcp->mb[0]; 118 mboxes = mcp->out_mb; 119 120 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111, 121 "Mailbox registers (OUT):\n"); 122 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 123 if (IS_QLA2200(ha) && cnt == 8) 124 optr = 125 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 126 if (mboxes & BIT_0) { 127 ql_dbg(ql_dbg_mbx, vha, 0x1112, 128 "mbox[%d]<-0x%04x\n", cnt, *iptr); 129 WRT_REG_WORD(optr, *iptr); 130 } 131 132 mboxes >>= 1; 133 optr++; 134 iptr++; 135 } 136 137 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 138 "I/O Address = %p.\n", optr); 139 140 /* Issue set host interrupt command to send cmd out. */ 141 ha->flags.mbox_int = 0; 142 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 143 144 /* Unlock mbx registers and wait for interrupt */ 145 ql_dbg(ql_dbg_mbx, vha, 0x100f, 146 "Going to unlock irq & waiting for interrupts. " 147 "jiffies=%lx.\n", jiffies); 148 149 /* Wait for mbx cmd completion until timeout */ 150 151 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 152 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 153 154 if (IS_P3P_TYPE(ha)) { 155 if (RD_REG_DWORD(®->isp82.hint) & 156 HINT_MBX_INT_PENDING) { 157 spin_unlock_irqrestore(&ha->hardware_lock, 158 flags); 159 ha->flags.mbox_busy = 0; 160 ql_dbg(ql_dbg_mbx, vha, 0x1010, 161 "Pending mailbox timeout, exiting.\n"); 162 rval = QLA_FUNCTION_TIMEOUT; 163 goto premature_exit; 164 } 165 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 166 } else if (IS_FWI2_CAPABLE(ha)) 167 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 168 else 169 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 170 spin_unlock_irqrestore(&ha->hardware_lock, flags); 171 172 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 173 mcp->tov * HZ)) { 174 ql_dbg(ql_dbg_mbx, vha, 0x117a, 175 "cmd=%x Timeout.\n", command); 176 spin_lock_irqsave(&ha->hardware_lock, flags); 177 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 178 spin_unlock_irqrestore(&ha->hardware_lock, flags); 179 } 180 } else { 181 ql_dbg(ql_dbg_mbx, vha, 0x1011, 182 "Cmd=%x Polling Mode.\n", command); 183 184 if (IS_P3P_TYPE(ha)) { 185 if (RD_REG_DWORD(®->isp82.hint) & 186 HINT_MBX_INT_PENDING) { 187 spin_unlock_irqrestore(&ha->hardware_lock, 188 flags); 189 ha->flags.mbox_busy = 0; 190 ql_dbg(ql_dbg_mbx, vha, 0x1012, 191 "Pending mailbox timeout, exiting.\n"); 192 rval = QLA_FUNCTION_TIMEOUT; 193 goto premature_exit; 194 } 195 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 196 } else if (IS_FWI2_CAPABLE(ha)) 197 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 198 else 199 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 200 spin_unlock_irqrestore(&ha->hardware_lock, flags); 201 202 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 203 while (!ha->flags.mbox_int) { 204 if (time_after(jiffies, wait_time)) 205 break; 206 207 /* Check for pending interrupts. */ 208 qla2x00_poll(ha->rsp_q_map[0]); 209 210 if (!ha->flags.mbox_int && 211 !(IS_QLA2200(ha) && 212 command == MBC_LOAD_RISC_RAM_EXTENDED)) 213 msleep(10); 214 } /* while */ 215 ql_dbg(ql_dbg_mbx, vha, 0x1013, 216 "Waited %d sec.\n", 217 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 218 } 219 220 /* Check whether we timed out */ 221 if (ha->flags.mbox_int) { 222 uint16_t *iptr2; 223 224 ql_dbg(ql_dbg_mbx, vha, 0x1014, 225 "Cmd=%x completed.\n", command); 226 227 /* Got interrupt. Clear the flag. */ 228 ha->flags.mbox_int = 0; 229 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 230 231 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 232 ha->flags.mbox_busy = 0; 233 /* Setting Link-Down error */ 234 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 235 ha->mcp = NULL; 236 rval = QLA_FUNCTION_FAILED; 237 ql_log(ql_log_warn, vha, 0x1015, 238 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 239 goto premature_exit; 240 } 241 242 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 243 rval = QLA_FUNCTION_FAILED; 244 245 /* Load return mailbox registers. */ 246 iptr2 = mcp->mb; 247 iptr = (uint16_t *)&ha->mailbox_out[0]; 248 mboxes = mcp->in_mb; 249 250 ql_dbg(ql_dbg_mbx, vha, 0x1113, 251 "Mailbox registers (IN):\n"); 252 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 253 if (mboxes & BIT_0) { 254 *iptr2 = *iptr; 255 ql_dbg(ql_dbg_mbx, vha, 0x1114, 256 "mbox[%d]->0x%04x\n", cnt, *iptr2); 257 } 258 259 mboxes >>= 1; 260 iptr2++; 261 iptr++; 262 } 263 } else { 264 265 uint16_t mb0; 266 uint32_t ictrl; 267 268 if (IS_FWI2_CAPABLE(ha)) { 269 mb0 = RD_REG_WORD(®->isp24.mailbox0); 270 ictrl = RD_REG_DWORD(®->isp24.ictrl); 271 } else { 272 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 273 ictrl = RD_REG_WORD(®->isp.ictrl); 274 } 275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 276 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0); 278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 279 280 /* 281 * Attempt to capture a firmware dump for further analysis 282 * of the current firmware state. We do not need to do this 283 * if we are intentionally generating a dump. 284 */ 285 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 286 ha->isp_ops->fw_dump(vha, 0); 287 288 rval = QLA_FUNCTION_TIMEOUT; 289 } 290 291 ha->flags.mbox_busy = 0; 292 293 /* Clean up */ 294 ha->mcp = NULL; 295 296 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 297 ql_dbg(ql_dbg_mbx, vha, 0x101a, 298 "Checking for additional resp interrupt.\n"); 299 300 /* polling mode for non isp_abort commands. */ 301 qla2x00_poll(ha->rsp_q_map[0]); 302 } 303 304 if (rval == QLA_FUNCTION_TIMEOUT && 305 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 306 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 307 ha->flags.eeh_busy) { 308 /* not in dpc. schedule it for dpc to take over. */ 309 ql_dbg(ql_dbg_mbx, vha, 0x101b, 310 "Timeout, schedule isp_abort_needed.\n"); 311 312 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 313 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 314 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 315 if (IS_QLA82XX(ha)) { 316 ql_dbg(ql_dbg_mbx, vha, 0x112a, 317 "disabling pause transmit on port " 318 "0 & 1.\n"); 319 qla82xx_wr_32(ha, 320 QLA82XX_CRB_NIU + 0x98, 321 CRB_NIU_XG_PAUSE_CTL_P0| 322 CRB_NIU_XG_PAUSE_CTL_P1); 323 } 324 ql_log(ql_log_info, base_vha, 0x101c, 325 "Mailbox cmd timeout occurred, cmd=0x%x, " 326 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 327 "abort.\n", command, mcp->mb[0], 328 ha->flags.eeh_busy); 329 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 330 qla2xxx_wake_dpc(vha); 331 } 332 } else if (!abort_active) { 333 /* call abort directly since we are in the DPC thread */ 334 ql_dbg(ql_dbg_mbx, vha, 0x101d, 335 "Timeout, calling abort_isp.\n"); 336 337 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 338 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 339 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 340 if (IS_QLA82XX(ha)) { 341 ql_dbg(ql_dbg_mbx, vha, 0x112b, 342 "disabling pause transmit on port " 343 "0 & 1.\n"); 344 qla82xx_wr_32(ha, 345 QLA82XX_CRB_NIU + 0x98, 346 CRB_NIU_XG_PAUSE_CTL_P0| 347 CRB_NIU_XG_PAUSE_CTL_P1); 348 } 349 ql_log(ql_log_info, base_vha, 0x101e, 350 "Mailbox cmd timeout occurred, cmd=0x%x, " 351 "mb[0]=0x%x. Scheduling ISP abort ", 352 command, mcp->mb[0]); 353 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 354 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 355 /* Allow next mbx cmd to come in. */ 356 complete(&ha->mbx_cmd_comp); 357 if (ha->isp_ops->abort_isp(vha)) { 358 /* Failed. retry later. */ 359 set_bit(ISP_ABORT_NEEDED, 360 &vha->dpc_flags); 361 } 362 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 363 ql_dbg(ql_dbg_mbx, vha, 0x101f, 364 "Finished abort_isp.\n"); 365 goto mbx_done; 366 } 367 } 368 } 369 370 premature_exit: 371 /* Allow next mbx cmd to come in. */ 372 complete(&ha->mbx_cmd_comp); 373 374 mbx_done: 375 if (rval) { 376 ql_log(ql_log_warn, base_vha, 0x1020, 377 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 378 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 379 } else { 380 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 381 } 382 383 return rval; 384 } 385 386 int 387 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 388 uint32_t risc_code_size) 389 { 390 int rval; 391 struct qla_hw_data *ha = vha->hw; 392 mbx_cmd_t mc; 393 mbx_cmd_t *mcp = &mc; 394 395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 396 "Entered %s.\n", __func__); 397 398 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 399 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 400 mcp->mb[8] = MSW(risc_addr); 401 mcp->out_mb = MBX_8|MBX_0; 402 } else { 403 mcp->mb[0] = MBC_LOAD_RISC_RAM; 404 mcp->out_mb = MBX_0; 405 } 406 mcp->mb[1] = LSW(risc_addr); 407 mcp->mb[2] = MSW(req_dma); 408 mcp->mb[3] = LSW(req_dma); 409 mcp->mb[6] = MSW(MSD(req_dma)); 410 mcp->mb[7] = LSW(MSD(req_dma)); 411 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 412 if (IS_FWI2_CAPABLE(ha)) { 413 mcp->mb[4] = MSW(risc_code_size); 414 mcp->mb[5] = LSW(risc_code_size); 415 mcp->out_mb |= MBX_5|MBX_4; 416 } else { 417 mcp->mb[4] = LSW(risc_code_size); 418 mcp->out_mb |= MBX_4; 419 } 420 421 mcp->in_mb = MBX_0; 422 mcp->tov = MBX_TOV_SECONDS; 423 mcp->flags = 0; 424 rval = qla2x00_mailbox_command(vha, mcp); 425 426 if (rval != QLA_SUCCESS) { 427 ql_dbg(ql_dbg_mbx, vha, 0x1023, 428 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 429 } else { 430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 431 "Done %s.\n", __func__); 432 } 433 434 return rval; 435 } 436 437 #define EXTENDED_BB_CREDITS BIT_0 438 /* 439 * qla2x00_execute_fw 440 * Start adapter firmware. 441 * 442 * Input: 443 * ha = adapter block pointer. 444 * TARGET_QUEUE_LOCK must be released. 445 * ADAPTER_STATE_LOCK must be released. 446 * 447 * Returns: 448 * qla2x00 local function return status code. 449 * 450 * Context: 451 * Kernel context. 452 */ 453 int 454 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 455 { 456 int rval; 457 struct qla_hw_data *ha = vha->hw; 458 mbx_cmd_t mc; 459 mbx_cmd_t *mcp = &mc; 460 461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 462 "Entered %s.\n", __func__); 463 464 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 465 mcp->out_mb = MBX_0; 466 mcp->in_mb = MBX_0; 467 if (IS_FWI2_CAPABLE(ha)) { 468 mcp->mb[1] = MSW(risc_addr); 469 mcp->mb[2] = LSW(risc_addr); 470 mcp->mb[3] = 0; 471 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 472 IS_QLA27XX(ha)) { 473 struct nvram_81xx *nv = ha->nvram; 474 mcp->mb[4] = (nv->enhanced_features & 475 EXTENDED_BB_CREDITS); 476 } else 477 mcp->mb[4] = 0; 478 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 479 mcp->in_mb |= MBX_1; 480 } else { 481 mcp->mb[1] = LSW(risc_addr); 482 mcp->out_mb |= MBX_1; 483 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 484 mcp->mb[2] = 0; 485 mcp->out_mb |= MBX_2; 486 } 487 } 488 489 mcp->tov = MBX_TOV_SECONDS; 490 mcp->flags = 0; 491 rval = qla2x00_mailbox_command(vha, mcp); 492 493 if (rval != QLA_SUCCESS) { 494 ql_dbg(ql_dbg_mbx, vha, 0x1026, 495 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 496 } else { 497 if (IS_FWI2_CAPABLE(ha)) { 498 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 499 "Done exchanges=%x.\n", mcp->mb[1]); 500 } else { 501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 502 "Done %s.\n", __func__); 503 } 504 } 505 506 return rval; 507 } 508 509 /* 510 * qla2x00_get_fw_version 511 * Get firmware version. 512 * 513 * Input: 514 * ha: adapter state pointer. 515 * major: pointer for major number. 516 * minor: pointer for minor number. 517 * subminor: pointer for subminor number. 518 * 519 * Returns: 520 * qla2x00 local function return status code. 521 * 522 * Context: 523 * Kernel context. 524 */ 525 int 526 qla2x00_get_fw_version(scsi_qla_host_t *vha) 527 { 528 int rval; 529 mbx_cmd_t mc; 530 mbx_cmd_t *mcp = &mc; 531 struct qla_hw_data *ha = vha->hw; 532 533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 534 "Entered %s.\n", __func__); 535 536 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 537 mcp->out_mb = MBX_0; 538 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 539 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 540 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 541 if (IS_FWI2_CAPABLE(ha)) 542 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 543 if (IS_QLA27XX(ha)) 544 mcp->in_mb |= MBX_21|MBX_20|MBX_19|MBX_18; 545 mcp->flags = 0; 546 mcp->tov = MBX_TOV_SECONDS; 547 rval = qla2x00_mailbox_command(vha, mcp); 548 if (rval != QLA_SUCCESS) 549 goto failed; 550 551 /* Return mailbox data. */ 552 ha->fw_major_version = mcp->mb[1]; 553 ha->fw_minor_version = mcp->mb[2]; 554 ha->fw_subminor_version = mcp->mb[3]; 555 ha->fw_attributes = mcp->mb[6]; 556 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 557 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 558 else 559 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 560 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 561 ha->mpi_version[0] = mcp->mb[10] & 0xff; 562 ha->mpi_version[1] = mcp->mb[11] >> 8; 563 ha->mpi_version[2] = mcp->mb[11] & 0xff; 564 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 565 ha->phy_version[0] = mcp->mb[8] & 0xff; 566 ha->phy_version[1] = mcp->mb[9] >> 8; 567 ha->phy_version[2] = mcp->mb[9] & 0xff; 568 } 569 if (IS_FWI2_CAPABLE(ha)) { 570 ha->fw_attributes_h = mcp->mb[15]; 571 ha->fw_attributes_ext[0] = mcp->mb[16]; 572 ha->fw_attributes_ext[1] = mcp->mb[17]; 573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 574 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 575 __func__, mcp->mb[15], mcp->mb[6]); 576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 577 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 578 __func__, mcp->mb[17], mcp->mb[16]); 579 } 580 if (IS_QLA27XX(ha)) { 581 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 582 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 583 } 584 585 failed: 586 if (rval != QLA_SUCCESS) { 587 /*EMPTY*/ 588 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 589 } else { 590 /*EMPTY*/ 591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 592 "Done %s.\n", __func__); 593 } 594 return rval; 595 } 596 597 /* 598 * qla2x00_get_fw_options 599 * Set firmware options. 600 * 601 * Input: 602 * ha = adapter block pointer. 603 * fwopt = pointer for firmware options. 604 * 605 * Returns: 606 * qla2x00 local function return status code. 607 * 608 * Context: 609 * Kernel context. 610 */ 611 int 612 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 613 { 614 int rval; 615 mbx_cmd_t mc; 616 mbx_cmd_t *mcp = &mc; 617 618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 619 "Entered %s.\n", __func__); 620 621 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 622 mcp->out_mb = MBX_0; 623 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 624 mcp->tov = MBX_TOV_SECONDS; 625 mcp->flags = 0; 626 rval = qla2x00_mailbox_command(vha, mcp); 627 628 if (rval != QLA_SUCCESS) { 629 /*EMPTY*/ 630 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 631 } else { 632 fwopts[0] = mcp->mb[0]; 633 fwopts[1] = mcp->mb[1]; 634 fwopts[2] = mcp->mb[2]; 635 fwopts[3] = mcp->mb[3]; 636 637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 638 "Done %s.\n", __func__); 639 } 640 641 return rval; 642 } 643 644 645 /* 646 * qla2x00_set_fw_options 647 * Set firmware options. 648 * 649 * Input: 650 * ha = adapter block pointer. 651 * fwopt = pointer for firmware options. 652 * 653 * Returns: 654 * qla2x00 local function return status code. 655 * 656 * Context: 657 * Kernel context. 658 */ 659 int 660 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 661 { 662 int rval; 663 mbx_cmd_t mc; 664 mbx_cmd_t *mcp = &mc; 665 666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 667 "Entered %s.\n", __func__); 668 669 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 670 mcp->mb[1] = fwopts[1]; 671 mcp->mb[2] = fwopts[2]; 672 mcp->mb[3] = fwopts[3]; 673 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 674 mcp->in_mb = MBX_0; 675 if (IS_FWI2_CAPABLE(vha->hw)) { 676 mcp->in_mb |= MBX_1; 677 } else { 678 mcp->mb[10] = fwopts[10]; 679 mcp->mb[11] = fwopts[11]; 680 mcp->mb[12] = 0; /* Undocumented, but used */ 681 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 682 } 683 mcp->tov = MBX_TOV_SECONDS; 684 mcp->flags = 0; 685 rval = qla2x00_mailbox_command(vha, mcp); 686 687 fwopts[0] = mcp->mb[0]; 688 689 if (rval != QLA_SUCCESS) { 690 /*EMPTY*/ 691 ql_dbg(ql_dbg_mbx, vha, 0x1030, 692 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 693 } else { 694 /*EMPTY*/ 695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 696 "Done %s.\n", __func__); 697 } 698 699 return rval; 700 } 701 702 /* 703 * qla2x00_mbx_reg_test 704 * Mailbox register wrap test. 705 * 706 * Input: 707 * ha = adapter block pointer. 708 * TARGET_QUEUE_LOCK must be released. 709 * ADAPTER_STATE_LOCK must be released. 710 * 711 * Returns: 712 * qla2x00 local function return status code. 713 * 714 * Context: 715 * Kernel context. 716 */ 717 int 718 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 719 { 720 int rval; 721 mbx_cmd_t mc; 722 mbx_cmd_t *mcp = &mc; 723 724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 725 "Entered %s.\n", __func__); 726 727 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 728 mcp->mb[1] = 0xAAAA; 729 mcp->mb[2] = 0x5555; 730 mcp->mb[3] = 0xAA55; 731 mcp->mb[4] = 0x55AA; 732 mcp->mb[5] = 0xA5A5; 733 mcp->mb[6] = 0x5A5A; 734 mcp->mb[7] = 0x2525; 735 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 736 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 737 mcp->tov = MBX_TOV_SECONDS; 738 mcp->flags = 0; 739 rval = qla2x00_mailbox_command(vha, mcp); 740 741 if (rval == QLA_SUCCESS) { 742 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 743 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 744 rval = QLA_FUNCTION_FAILED; 745 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 746 mcp->mb[7] != 0x2525) 747 rval = QLA_FUNCTION_FAILED; 748 } 749 750 if (rval != QLA_SUCCESS) { 751 /*EMPTY*/ 752 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 753 } else { 754 /*EMPTY*/ 755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 756 "Done %s.\n", __func__); 757 } 758 759 return rval; 760 } 761 762 /* 763 * qla2x00_verify_checksum 764 * Verify firmware checksum. 765 * 766 * Input: 767 * ha = adapter block pointer. 768 * TARGET_QUEUE_LOCK must be released. 769 * ADAPTER_STATE_LOCK must be released. 770 * 771 * Returns: 772 * qla2x00 local function return status code. 773 * 774 * Context: 775 * Kernel context. 776 */ 777 int 778 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 779 { 780 int rval; 781 mbx_cmd_t mc; 782 mbx_cmd_t *mcp = &mc; 783 784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 785 "Entered %s.\n", __func__); 786 787 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 788 mcp->out_mb = MBX_0; 789 mcp->in_mb = MBX_0; 790 if (IS_FWI2_CAPABLE(vha->hw)) { 791 mcp->mb[1] = MSW(risc_addr); 792 mcp->mb[2] = LSW(risc_addr); 793 mcp->out_mb |= MBX_2|MBX_1; 794 mcp->in_mb |= MBX_2|MBX_1; 795 } else { 796 mcp->mb[1] = LSW(risc_addr); 797 mcp->out_mb |= MBX_1; 798 mcp->in_mb |= MBX_1; 799 } 800 801 mcp->tov = MBX_TOV_SECONDS; 802 mcp->flags = 0; 803 rval = qla2x00_mailbox_command(vha, mcp); 804 805 if (rval != QLA_SUCCESS) { 806 ql_dbg(ql_dbg_mbx, vha, 0x1036, 807 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 808 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 809 } else { 810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 811 "Done %s.\n", __func__); 812 } 813 814 return rval; 815 } 816 817 /* 818 * qla2x00_issue_iocb 819 * Issue IOCB using mailbox command 820 * 821 * Input: 822 * ha = adapter state pointer. 823 * buffer = buffer pointer. 824 * phys_addr = physical address of buffer. 825 * size = size of buffer. 826 * TARGET_QUEUE_LOCK must be released. 827 * ADAPTER_STATE_LOCK must be released. 828 * 829 * Returns: 830 * qla2x00 local function return status code. 831 * 832 * Context: 833 * Kernel context. 834 */ 835 int 836 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 837 dma_addr_t phys_addr, size_t size, uint32_t tov) 838 { 839 int rval; 840 mbx_cmd_t mc; 841 mbx_cmd_t *mcp = &mc; 842 843 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 844 "Entered %s.\n", __func__); 845 846 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 847 mcp->mb[1] = 0; 848 mcp->mb[2] = MSW(phys_addr); 849 mcp->mb[3] = LSW(phys_addr); 850 mcp->mb[6] = MSW(MSD(phys_addr)); 851 mcp->mb[7] = LSW(MSD(phys_addr)); 852 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 853 mcp->in_mb = MBX_2|MBX_0; 854 mcp->tov = tov; 855 mcp->flags = 0; 856 rval = qla2x00_mailbox_command(vha, mcp); 857 858 if (rval != QLA_SUCCESS) { 859 /*EMPTY*/ 860 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 861 } else { 862 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 863 864 /* Mask reserved bits. */ 865 sts_entry->entry_status &= 866 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 868 "Done %s.\n", __func__); 869 } 870 871 return rval; 872 } 873 874 int 875 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 876 size_t size) 877 { 878 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 879 MBX_TOV_SECONDS); 880 } 881 882 /* 883 * qla2x00_abort_command 884 * Abort command aborts a specified IOCB. 885 * 886 * Input: 887 * ha = adapter block pointer. 888 * sp = SB structure pointer. 889 * 890 * Returns: 891 * qla2x00 local function return status code. 892 * 893 * Context: 894 * Kernel context. 895 */ 896 int 897 qla2x00_abort_command(srb_t *sp) 898 { 899 unsigned long flags = 0; 900 int rval; 901 uint32_t handle = 0; 902 mbx_cmd_t mc; 903 mbx_cmd_t *mcp = &mc; 904 fc_port_t *fcport = sp->fcport; 905 scsi_qla_host_t *vha = fcport->vha; 906 struct qla_hw_data *ha = vha->hw; 907 struct req_que *req = vha->req; 908 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 909 910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 911 "Entered %s.\n", __func__); 912 913 spin_lock_irqsave(&ha->hardware_lock, flags); 914 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 915 if (req->outstanding_cmds[handle] == sp) 916 break; 917 } 918 spin_unlock_irqrestore(&ha->hardware_lock, flags); 919 920 if (handle == req->num_outstanding_cmds) { 921 /* command not found */ 922 return QLA_FUNCTION_FAILED; 923 } 924 925 mcp->mb[0] = MBC_ABORT_COMMAND; 926 if (HAS_EXTENDED_IDS(ha)) 927 mcp->mb[1] = fcport->loop_id; 928 else 929 mcp->mb[1] = fcport->loop_id << 8; 930 mcp->mb[2] = (uint16_t)handle; 931 mcp->mb[3] = (uint16_t)(handle >> 16); 932 mcp->mb[6] = (uint16_t)cmd->device->lun; 933 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 934 mcp->in_mb = MBX_0; 935 mcp->tov = MBX_TOV_SECONDS; 936 mcp->flags = 0; 937 rval = qla2x00_mailbox_command(vha, mcp); 938 939 if (rval != QLA_SUCCESS) { 940 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 941 } else { 942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 943 "Done %s.\n", __func__); 944 } 945 946 return rval; 947 } 948 949 int 950 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag) 951 { 952 int rval, rval2; 953 mbx_cmd_t mc; 954 mbx_cmd_t *mcp = &mc; 955 scsi_qla_host_t *vha; 956 struct req_que *req; 957 struct rsp_que *rsp; 958 959 l = l; 960 vha = fcport->vha; 961 962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 963 "Entered %s.\n", __func__); 964 965 req = vha->hw->req_q_map[0]; 966 rsp = req->rsp; 967 mcp->mb[0] = MBC_ABORT_TARGET; 968 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 969 if (HAS_EXTENDED_IDS(vha->hw)) { 970 mcp->mb[1] = fcport->loop_id; 971 mcp->mb[10] = 0; 972 mcp->out_mb |= MBX_10; 973 } else { 974 mcp->mb[1] = fcport->loop_id << 8; 975 } 976 mcp->mb[2] = vha->hw->loop_reset_delay; 977 mcp->mb[9] = vha->vp_idx; 978 979 mcp->in_mb = MBX_0; 980 mcp->tov = MBX_TOV_SECONDS; 981 mcp->flags = 0; 982 rval = qla2x00_mailbox_command(vha, mcp); 983 if (rval != QLA_SUCCESS) { 984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 985 "Failed=%x.\n", rval); 986 } 987 988 /* Issue marker IOCB. */ 989 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 990 MK_SYNC_ID); 991 if (rval2 != QLA_SUCCESS) { 992 ql_dbg(ql_dbg_mbx, vha, 0x1040, 993 "Failed to issue marker IOCB (%x).\n", rval2); 994 } else { 995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 996 "Done %s.\n", __func__); 997 } 998 999 return rval; 1000 } 1001 1002 int 1003 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 1004 { 1005 int rval, rval2; 1006 mbx_cmd_t mc; 1007 mbx_cmd_t *mcp = &mc; 1008 scsi_qla_host_t *vha; 1009 struct req_que *req; 1010 struct rsp_que *rsp; 1011 1012 vha = fcport->vha; 1013 1014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1015 "Entered %s.\n", __func__); 1016 1017 req = vha->hw->req_q_map[0]; 1018 rsp = req->rsp; 1019 mcp->mb[0] = MBC_LUN_RESET; 1020 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1021 if (HAS_EXTENDED_IDS(vha->hw)) 1022 mcp->mb[1] = fcport->loop_id; 1023 else 1024 mcp->mb[1] = fcport->loop_id << 8; 1025 mcp->mb[2] = l; 1026 mcp->mb[3] = 0; 1027 mcp->mb[9] = vha->vp_idx; 1028 1029 mcp->in_mb = MBX_0; 1030 mcp->tov = MBX_TOV_SECONDS; 1031 mcp->flags = 0; 1032 rval = qla2x00_mailbox_command(vha, mcp); 1033 if (rval != QLA_SUCCESS) { 1034 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1035 } 1036 1037 /* Issue marker IOCB. */ 1038 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1039 MK_SYNC_ID_LUN); 1040 if (rval2 != QLA_SUCCESS) { 1041 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1042 "Failed to issue marker IOCB (%x).\n", rval2); 1043 } else { 1044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1045 "Done %s.\n", __func__); 1046 } 1047 1048 return rval; 1049 } 1050 1051 /* 1052 * qla2x00_get_adapter_id 1053 * Get adapter ID and topology. 1054 * 1055 * Input: 1056 * ha = adapter block pointer. 1057 * id = pointer for loop ID. 1058 * al_pa = pointer for AL_PA. 1059 * area = pointer for area. 1060 * domain = pointer for domain. 1061 * top = pointer for topology. 1062 * TARGET_QUEUE_LOCK must be released. 1063 * ADAPTER_STATE_LOCK must be released. 1064 * 1065 * Returns: 1066 * qla2x00 local function return status code. 1067 * 1068 * Context: 1069 * Kernel context. 1070 */ 1071 int 1072 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1073 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1074 { 1075 int rval; 1076 mbx_cmd_t mc; 1077 mbx_cmd_t *mcp = &mc; 1078 1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1080 "Entered %s.\n", __func__); 1081 1082 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1083 mcp->mb[9] = vha->vp_idx; 1084 mcp->out_mb = MBX_9|MBX_0; 1085 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1086 if (IS_CNA_CAPABLE(vha->hw)) 1087 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1088 mcp->tov = MBX_TOV_SECONDS; 1089 mcp->flags = 0; 1090 rval = qla2x00_mailbox_command(vha, mcp); 1091 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1092 rval = QLA_COMMAND_ERROR; 1093 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1094 rval = QLA_INVALID_COMMAND; 1095 1096 /* Return data. */ 1097 *id = mcp->mb[1]; 1098 *al_pa = LSB(mcp->mb[2]); 1099 *area = MSB(mcp->mb[2]); 1100 *domain = LSB(mcp->mb[3]); 1101 *top = mcp->mb[6]; 1102 *sw_cap = mcp->mb[7]; 1103 1104 if (rval != QLA_SUCCESS) { 1105 /*EMPTY*/ 1106 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1107 } else { 1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1109 "Done %s.\n", __func__); 1110 1111 if (IS_CNA_CAPABLE(vha->hw)) { 1112 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1113 vha->fcoe_fcf_idx = mcp->mb[10]; 1114 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1115 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1116 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1117 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1118 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1119 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1120 } 1121 } 1122 1123 return rval; 1124 } 1125 1126 /* 1127 * qla2x00_get_retry_cnt 1128 * Get current firmware login retry count and delay. 1129 * 1130 * Input: 1131 * ha = adapter block pointer. 1132 * retry_cnt = pointer to login retry count. 1133 * tov = pointer to login timeout value. 1134 * 1135 * Returns: 1136 * qla2x00 local function return status code. 1137 * 1138 * Context: 1139 * Kernel context. 1140 */ 1141 int 1142 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1143 uint16_t *r_a_tov) 1144 { 1145 int rval; 1146 uint16_t ratov; 1147 mbx_cmd_t mc; 1148 mbx_cmd_t *mcp = &mc; 1149 1150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1151 "Entered %s.\n", __func__); 1152 1153 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1154 mcp->out_mb = MBX_0; 1155 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1156 mcp->tov = MBX_TOV_SECONDS; 1157 mcp->flags = 0; 1158 rval = qla2x00_mailbox_command(vha, mcp); 1159 1160 if (rval != QLA_SUCCESS) { 1161 /*EMPTY*/ 1162 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1163 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1164 } else { 1165 /* Convert returned data and check our values. */ 1166 *r_a_tov = mcp->mb[3] / 2; 1167 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1168 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1169 /* Update to the larger values */ 1170 *retry_cnt = (uint8_t)mcp->mb[1]; 1171 *tov = ratov; 1172 } 1173 1174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1175 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1176 } 1177 1178 return rval; 1179 } 1180 1181 /* 1182 * qla2x00_init_firmware 1183 * Initialize adapter firmware. 1184 * 1185 * Input: 1186 * ha = adapter block pointer. 1187 * dptr = Initialization control block pointer. 1188 * size = size of initialization control block. 1189 * TARGET_QUEUE_LOCK must be released. 1190 * ADAPTER_STATE_LOCK must be released. 1191 * 1192 * Returns: 1193 * qla2x00 local function return status code. 1194 * 1195 * Context: 1196 * Kernel context. 1197 */ 1198 int 1199 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1200 { 1201 int rval; 1202 mbx_cmd_t mc; 1203 mbx_cmd_t *mcp = &mc; 1204 struct qla_hw_data *ha = vha->hw; 1205 1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1207 "Entered %s.\n", __func__); 1208 1209 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1210 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, 1211 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1212 1213 if (ha->flags.npiv_supported) 1214 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1215 else 1216 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1217 1218 mcp->mb[1] = 0; 1219 mcp->mb[2] = MSW(ha->init_cb_dma); 1220 mcp->mb[3] = LSW(ha->init_cb_dma); 1221 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1222 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1223 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1224 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1225 mcp->mb[1] = BIT_0; 1226 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1227 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1228 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1229 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1230 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1231 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1232 } 1233 /* 1 and 2 should normally be captured. */ 1234 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1235 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1236 /* mb3 is additional info about the installed SFP. */ 1237 mcp->in_mb |= MBX_3; 1238 mcp->buf_size = size; 1239 mcp->flags = MBX_DMA_OUT; 1240 mcp->tov = MBX_TOV_SECONDS; 1241 rval = qla2x00_mailbox_command(vha, mcp); 1242 1243 if (rval != QLA_SUCCESS) { 1244 /*EMPTY*/ 1245 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1246 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1247 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1248 } else { 1249 /*EMPTY*/ 1250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1251 "Done %s.\n", __func__); 1252 } 1253 1254 return rval; 1255 } 1256 1257 /* 1258 * qla2x00_get_node_name_list 1259 * Issue get node name list mailbox command, kmalloc() 1260 * and return the resulting list. Caller must kfree() it! 1261 * 1262 * Input: 1263 * ha = adapter state pointer. 1264 * out_data = resulting list 1265 * out_len = length of the resulting list 1266 * 1267 * Returns: 1268 * qla2x00 local function return status code. 1269 * 1270 * Context: 1271 * Kernel context. 1272 */ 1273 int 1274 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len) 1275 { 1276 struct qla_hw_data *ha = vha->hw; 1277 struct qla_port_24xx_data *list = NULL; 1278 void *pmap; 1279 mbx_cmd_t mc; 1280 dma_addr_t pmap_dma; 1281 ulong dma_size; 1282 int rval, left; 1283 1284 left = 1; 1285 while (left > 0) { 1286 dma_size = left * sizeof(*list); 1287 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size, 1288 &pmap_dma, GFP_KERNEL); 1289 if (!pmap) { 1290 ql_log(ql_log_warn, vha, 0x113f, 1291 "%s(%ld): DMA Alloc failed of %ld\n", 1292 __func__, vha->host_no, dma_size); 1293 rval = QLA_MEMORY_ALLOC_FAILED; 1294 goto out; 1295 } 1296 1297 mc.mb[0] = MBC_PORT_NODE_NAME_LIST; 1298 mc.mb[1] = BIT_1 | BIT_3; 1299 mc.mb[2] = MSW(pmap_dma); 1300 mc.mb[3] = LSW(pmap_dma); 1301 mc.mb[6] = MSW(MSD(pmap_dma)); 1302 mc.mb[7] = LSW(MSD(pmap_dma)); 1303 mc.mb[8] = dma_size; 1304 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8; 1305 mc.in_mb = MBX_0|MBX_1; 1306 mc.tov = 30; 1307 mc.flags = MBX_DMA_IN; 1308 1309 rval = qla2x00_mailbox_command(vha, &mc); 1310 if (rval != QLA_SUCCESS) { 1311 if ((mc.mb[0] == MBS_COMMAND_ERROR) && 1312 (mc.mb[1] == 0xA)) { 1313 left += le16_to_cpu(mc.mb[2]) / 1314 sizeof(struct qla_port_24xx_data); 1315 goto restart; 1316 } 1317 goto out_free; 1318 } 1319 1320 left = 0; 1321 1322 list = kmemdup(pmap, dma_size, GFP_KERNEL); 1323 if (!list) { 1324 ql_log(ql_log_warn, vha, 0x1140, 1325 "%s(%ld): failed to allocate node names list " 1326 "structure.\n", __func__, vha->host_no); 1327 rval = QLA_MEMORY_ALLOC_FAILED; 1328 goto out_free; 1329 } 1330 1331 restart: 1332 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1333 } 1334 1335 *out_data = list; 1336 *out_len = dma_size; 1337 1338 out: 1339 return rval; 1340 1341 out_free: 1342 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1343 return rval; 1344 } 1345 1346 /* 1347 * qla2x00_get_port_database 1348 * Issue normal/enhanced get port database mailbox command 1349 * and copy device name as necessary. 1350 * 1351 * Input: 1352 * ha = adapter state pointer. 1353 * dev = structure pointer. 1354 * opt = enhanced cmd option byte. 1355 * 1356 * Returns: 1357 * qla2x00 local function return status code. 1358 * 1359 * Context: 1360 * Kernel context. 1361 */ 1362 int 1363 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1364 { 1365 int rval; 1366 mbx_cmd_t mc; 1367 mbx_cmd_t *mcp = &mc; 1368 port_database_t *pd; 1369 struct port_database_24xx *pd24; 1370 dma_addr_t pd_dma; 1371 struct qla_hw_data *ha = vha->hw; 1372 1373 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1374 "Entered %s.\n", __func__); 1375 1376 pd24 = NULL; 1377 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1378 if (pd == NULL) { 1379 ql_log(ql_log_warn, vha, 0x1050, 1380 "Failed to allocate port database structure.\n"); 1381 return QLA_MEMORY_ALLOC_FAILED; 1382 } 1383 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1384 1385 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1386 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1387 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1388 mcp->mb[2] = MSW(pd_dma); 1389 mcp->mb[3] = LSW(pd_dma); 1390 mcp->mb[6] = MSW(MSD(pd_dma)); 1391 mcp->mb[7] = LSW(MSD(pd_dma)); 1392 mcp->mb[9] = vha->vp_idx; 1393 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1394 mcp->in_mb = MBX_0; 1395 if (IS_FWI2_CAPABLE(ha)) { 1396 mcp->mb[1] = fcport->loop_id; 1397 mcp->mb[10] = opt; 1398 mcp->out_mb |= MBX_10|MBX_1; 1399 mcp->in_mb |= MBX_1; 1400 } else if (HAS_EXTENDED_IDS(ha)) { 1401 mcp->mb[1] = fcport->loop_id; 1402 mcp->mb[10] = opt; 1403 mcp->out_mb |= MBX_10|MBX_1; 1404 } else { 1405 mcp->mb[1] = fcport->loop_id << 8 | opt; 1406 mcp->out_mb |= MBX_1; 1407 } 1408 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1409 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1410 mcp->flags = MBX_DMA_IN; 1411 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1412 rval = qla2x00_mailbox_command(vha, mcp); 1413 if (rval != QLA_SUCCESS) 1414 goto gpd_error_out; 1415 1416 if (IS_FWI2_CAPABLE(ha)) { 1417 uint64_t zero = 0; 1418 pd24 = (struct port_database_24xx *) pd; 1419 1420 /* Check for logged in state. */ 1421 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1422 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1423 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1424 "Unable to verify login-state (%x/%x) for " 1425 "loop_id %x.\n", pd24->current_login_state, 1426 pd24->last_login_state, fcport->loop_id); 1427 rval = QLA_FUNCTION_FAILED; 1428 goto gpd_error_out; 1429 } 1430 1431 if (fcport->loop_id == FC_NO_LOOP_ID || 1432 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1433 memcmp(fcport->port_name, pd24->port_name, 8))) { 1434 /* We lost the device mid way. */ 1435 rval = QLA_NOT_LOGGED_IN; 1436 goto gpd_error_out; 1437 } 1438 1439 /* Names are little-endian. */ 1440 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1441 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1442 1443 /* Get port_id of device. */ 1444 fcport->d_id.b.domain = pd24->port_id[0]; 1445 fcport->d_id.b.area = pd24->port_id[1]; 1446 fcport->d_id.b.al_pa = pd24->port_id[2]; 1447 fcport->d_id.b.rsvd_1 = 0; 1448 1449 /* If not target must be initiator or unknown type. */ 1450 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1451 fcport->port_type = FCT_INITIATOR; 1452 else 1453 fcport->port_type = FCT_TARGET; 1454 1455 /* Passback COS information. */ 1456 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1457 FC_COS_CLASS2 : FC_COS_CLASS3; 1458 1459 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1460 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1461 } else { 1462 uint64_t zero = 0; 1463 1464 /* Check for logged in state. */ 1465 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1466 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1467 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1468 "Unable to verify login-state (%x/%x) - " 1469 "portid=%02x%02x%02x.\n", pd->master_state, 1470 pd->slave_state, fcport->d_id.b.domain, 1471 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1472 rval = QLA_FUNCTION_FAILED; 1473 goto gpd_error_out; 1474 } 1475 1476 if (fcport->loop_id == FC_NO_LOOP_ID || 1477 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1478 memcmp(fcport->port_name, pd->port_name, 8))) { 1479 /* We lost the device mid way. */ 1480 rval = QLA_NOT_LOGGED_IN; 1481 goto gpd_error_out; 1482 } 1483 1484 /* Names are little-endian. */ 1485 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1486 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1487 1488 /* Get port_id of device. */ 1489 fcport->d_id.b.domain = pd->port_id[0]; 1490 fcport->d_id.b.area = pd->port_id[3]; 1491 fcport->d_id.b.al_pa = pd->port_id[2]; 1492 fcport->d_id.b.rsvd_1 = 0; 1493 1494 /* If not target must be initiator or unknown type. */ 1495 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1496 fcport->port_type = FCT_INITIATOR; 1497 else 1498 fcport->port_type = FCT_TARGET; 1499 1500 /* Passback COS information. */ 1501 fcport->supported_classes = (pd->options & BIT_4) ? 1502 FC_COS_CLASS2: FC_COS_CLASS3; 1503 } 1504 1505 gpd_error_out: 1506 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1507 1508 if (rval != QLA_SUCCESS) { 1509 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1510 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1511 mcp->mb[0], mcp->mb[1]); 1512 } else { 1513 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1514 "Done %s.\n", __func__); 1515 } 1516 1517 return rval; 1518 } 1519 1520 /* 1521 * qla2x00_get_firmware_state 1522 * Get adapter firmware state. 1523 * 1524 * Input: 1525 * ha = adapter block pointer. 1526 * dptr = pointer for firmware state. 1527 * TARGET_QUEUE_LOCK must be released. 1528 * ADAPTER_STATE_LOCK must be released. 1529 * 1530 * Returns: 1531 * qla2x00 local function return status code. 1532 * 1533 * Context: 1534 * Kernel context. 1535 */ 1536 int 1537 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1538 { 1539 int rval; 1540 mbx_cmd_t mc; 1541 mbx_cmd_t *mcp = &mc; 1542 1543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1544 "Entered %s.\n", __func__); 1545 1546 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1547 mcp->out_mb = MBX_0; 1548 if (IS_FWI2_CAPABLE(vha->hw)) 1549 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1550 else 1551 mcp->in_mb = MBX_1|MBX_0; 1552 mcp->tov = MBX_TOV_SECONDS; 1553 mcp->flags = 0; 1554 rval = qla2x00_mailbox_command(vha, mcp); 1555 1556 /* Return firmware states. */ 1557 states[0] = mcp->mb[1]; 1558 if (IS_FWI2_CAPABLE(vha->hw)) { 1559 states[1] = mcp->mb[2]; 1560 states[2] = mcp->mb[3]; 1561 states[3] = mcp->mb[4]; 1562 states[4] = mcp->mb[5]; 1563 } 1564 1565 if (rval != QLA_SUCCESS) { 1566 /*EMPTY*/ 1567 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1568 } else { 1569 /*EMPTY*/ 1570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1571 "Done %s.\n", __func__); 1572 } 1573 1574 return rval; 1575 } 1576 1577 /* 1578 * qla2x00_get_port_name 1579 * Issue get port name mailbox command. 1580 * Returned name is in big endian format. 1581 * 1582 * Input: 1583 * ha = adapter block pointer. 1584 * loop_id = loop ID of device. 1585 * name = pointer for name. 1586 * TARGET_QUEUE_LOCK must be released. 1587 * ADAPTER_STATE_LOCK must be released. 1588 * 1589 * Returns: 1590 * qla2x00 local function return status code. 1591 * 1592 * Context: 1593 * Kernel context. 1594 */ 1595 int 1596 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1597 uint8_t opt) 1598 { 1599 int rval; 1600 mbx_cmd_t mc; 1601 mbx_cmd_t *mcp = &mc; 1602 1603 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1604 "Entered %s.\n", __func__); 1605 1606 mcp->mb[0] = MBC_GET_PORT_NAME; 1607 mcp->mb[9] = vha->vp_idx; 1608 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1609 if (HAS_EXTENDED_IDS(vha->hw)) { 1610 mcp->mb[1] = loop_id; 1611 mcp->mb[10] = opt; 1612 mcp->out_mb |= MBX_10; 1613 } else { 1614 mcp->mb[1] = loop_id << 8 | opt; 1615 } 1616 1617 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1618 mcp->tov = MBX_TOV_SECONDS; 1619 mcp->flags = 0; 1620 rval = qla2x00_mailbox_command(vha, mcp); 1621 1622 if (rval != QLA_SUCCESS) { 1623 /*EMPTY*/ 1624 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1625 } else { 1626 if (name != NULL) { 1627 /* This function returns name in big endian. */ 1628 name[0] = MSB(mcp->mb[2]); 1629 name[1] = LSB(mcp->mb[2]); 1630 name[2] = MSB(mcp->mb[3]); 1631 name[3] = LSB(mcp->mb[3]); 1632 name[4] = MSB(mcp->mb[6]); 1633 name[5] = LSB(mcp->mb[6]); 1634 name[6] = MSB(mcp->mb[7]); 1635 name[7] = LSB(mcp->mb[7]); 1636 } 1637 1638 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 1639 "Done %s.\n", __func__); 1640 } 1641 1642 return rval; 1643 } 1644 1645 /* 1646 * qla24xx_link_initialization 1647 * Issue link initialization mailbox command. 1648 * 1649 * Input: 1650 * ha = adapter block pointer. 1651 * TARGET_QUEUE_LOCK must be released. 1652 * ADAPTER_STATE_LOCK must be released. 1653 * 1654 * Returns: 1655 * qla2x00 local function return status code. 1656 * 1657 * Context: 1658 * Kernel context. 1659 */ 1660 int 1661 qla24xx_link_initialize(scsi_qla_host_t *vha) 1662 { 1663 int rval; 1664 mbx_cmd_t mc; 1665 mbx_cmd_t *mcp = &mc; 1666 1667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 1668 "Entered %s.\n", __func__); 1669 1670 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 1671 return QLA_FUNCTION_FAILED; 1672 1673 mcp->mb[0] = MBC_LINK_INITIALIZATION; 1674 mcp->mb[1] = BIT_4; 1675 if (vha->hw->operating_mode == LOOP) 1676 mcp->mb[1] |= BIT_6; 1677 else 1678 mcp->mb[1] |= BIT_5; 1679 mcp->mb[2] = 0; 1680 mcp->mb[3] = 0; 1681 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1682 mcp->in_mb = MBX_0; 1683 mcp->tov = MBX_TOV_SECONDS; 1684 mcp->flags = 0; 1685 rval = qla2x00_mailbox_command(vha, mcp); 1686 1687 if (rval != QLA_SUCCESS) { 1688 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 1689 } else { 1690 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 1691 "Done %s.\n", __func__); 1692 } 1693 1694 return rval; 1695 } 1696 1697 /* 1698 * qla2x00_lip_reset 1699 * Issue LIP reset mailbox command. 1700 * 1701 * Input: 1702 * ha = adapter block pointer. 1703 * TARGET_QUEUE_LOCK must be released. 1704 * ADAPTER_STATE_LOCK must be released. 1705 * 1706 * Returns: 1707 * qla2x00 local function return status code. 1708 * 1709 * Context: 1710 * Kernel context. 1711 */ 1712 int 1713 qla2x00_lip_reset(scsi_qla_host_t *vha) 1714 { 1715 int rval; 1716 mbx_cmd_t mc; 1717 mbx_cmd_t *mcp = &mc; 1718 1719 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 1720 "Entered %s.\n", __func__); 1721 1722 if (IS_CNA_CAPABLE(vha->hw)) { 1723 /* Logout across all FCFs. */ 1724 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1725 mcp->mb[1] = BIT_1; 1726 mcp->mb[2] = 0; 1727 mcp->out_mb = MBX_2|MBX_1|MBX_0; 1728 } else if (IS_FWI2_CAPABLE(vha->hw)) { 1729 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1730 mcp->mb[1] = BIT_6; 1731 mcp->mb[2] = 0; 1732 mcp->mb[3] = vha->hw->loop_reset_delay; 1733 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1734 } else { 1735 mcp->mb[0] = MBC_LIP_RESET; 1736 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1737 if (HAS_EXTENDED_IDS(vha->hw)) { 1738 mcp->mb[1] = 0x00ff; 1739 mcp->mb[10] = 0; 1740 mcp->out_mb |= MBX_10; 1741 } else { 1742 mcp->mb[1] = 0xff00; 1743 } 1744 mcp->mb[2] = vha->hw->loop_reset_delay; 1745 mcp->mb[3] = 0; 1746 } 1747 mcp->in_mb = MBX_0; 1748 mcp->tov = MBX_TOV_SECONDS; 1749 mcp->flags = 0; 1750 rval = qla2x00_mailbox_command(vha, mcp); 1751 1752 if (rval != QLA_SUCCESS) { 1753 /*EMPTY*/ 1754 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 1755 } else { 1756 /*EMPTY*/ 1757 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 1758 "Done %s.\n", __func__); 1759 } 1760 1761 return rval; 1762 } 1763 1764 /* 1765 * qla2x00_send_sns 1766 * Send SNS command. 1767 * 1768 * Input: 1769 * ha = adapter block pointer. 1770 * sns = pointer for command. 1771 * cmd_size = command size. 1772 * buf_size = response/command size. 1773 * TARGET_QUEUE_LOCK must be released. 1774 * ADAPTER_STATE_LOCK must be released. 1775 * 1776 * Returns: 1777 * qla2x00 local function return status code. 1778 * 1779 * Context: 1780 * Kernel context. 1781 */ 1782 int 1783 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 1784 uint16_t cmd_size, size_t buf_size) 1785 { 1786 int rval; 1787 mbx_cmd_t mc; 1788 mbx_cmd_t *mcp = &mc; 1789 1790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 1791 "Entered %s.\n", __func__); 1792 1793 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 1794 "Retry cnt=%d ratov=%d total tov=%d.\n", 1795 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 1796 1797 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 1798 mcp->mb[1] = cmd_size; 1799 mcp->mb[2] = MSW(sns_phys_address); 1800 mcp->mb[3] = LSW(sns_phys_address); 1801 mcp->mb[6] = MSW(MSD(sns_phys_address)); 1802 mcp->mb[7] = LSW(MSD(sns_phys_address)); 1803 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1804 mcp->in_mb = MBX_0|MBX_1; 1805 mcp->buf_size = buf_size; 1806 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 1807 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 1808 rval = qla2x00_mailbox_command(vha, mcp); 1809 1810 if (rval != QLA_SUCCESS) { 1811 /*EMPTY*/ 1812 ql_dbg(ql_dbg_mbx, vha, 0x105f, 1813 "Failed=%x mb[0]=%x mb[1]=%x.\n", 1814 rval, mcp->mb[0], mcp->mb[1]); 1815 } else { 1816 /*EMPTY*/ 1817 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 1818 "Done %s.\n", __func__); 1819 } 1820 1821 return rval; 1822 } 1823 1824 int 1825 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1826 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1827 { 1828 int rval; 1829 1830 struct logio_entry_24xx *lg; 1831 dma_addr_t lg_dma; 1832 uint32_t iop[2]; 1833 struct qla_hw_data *ha = vha->hw; 1834 struct req_que *req; 1835 struct rsp_que *rsp; 1836 1837 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 1838 "Entered %s.\n", __func__); 1839 1840 if (ha->flags.cpu_affinity_enabled) 1841 req = ha->req_q_map[0]; 1842 else 1843 req = vha->req; 1844 rsp = req->rsp; 1845 1846 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1847 if (lg == NULL) { 1848 ql_log(ql_log_warn, vha, 0x1062, 1849 "Failed to allocate login IOCB.\n"); 1850 return QLA_MEMORY_ALLOC_FAILED; 1851 } 1852 memset(lg, 0, sizeof(struct logio_entry_24xx)); 1853 1854 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 1855 lg->entry_count = 1; 1856 lg->handle = MAKE_HANDLE(req->id, lg->handle); 1857 lg->nport_handle = cpu_to_le16(loop_id); 1858 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI); 1859 if (opt & BIT_0) 1860 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI); 1861 if (opt & BIT_1) 1862 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI); 1863 lg->port_id[0] = al_pa; 1864 lg->port_id[1] = area; 1865 lg->port_id[2] = domain; 1866 lg->vp_index = vha->vp_idx; 1867 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 1868 (ha->r_a_tov / 10 * 2) + 2); 1869 if (rval != QLA_SUCCESS) { 1870 ql_dbg(ql_dbg_mbx, vha, 0x1063, 1871 "Failed to issue login IOCB (%x).\n", rval); 1872 } else if (lg->entry_status != 0) { 1873 ql_dbg(ql_dbg_mbx, vha, 0x1064, 1874 "Failed to complete IOCB -- error status (%x).\n", 1875 lg->entry_status); 1876 rval = QLA_FUNCTION_FAILED; 1877 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 1878 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1879 iop[1] = le32_to_cpu(lg->io_parameter[1]); 1880 1881 ql_dbg(ql_dbg_mbx, vha, 0x1065, 1882 "Failed to complete IOCB -- completion status (%x) " 1883 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 1884 iop[0], iop[1]); 1885 1886 switch (iop[0]) { 1887 case LSC_SCODE_PORTID_USED: 1888 mb[0] = MBS_PORT_ID_USED; 1889 mb[1] = LSW(iop[1]); 1890 break; 1891 case LSC_SCODE_NPORT_USED: 1892 mb[0] = MBS_LOOP_ID_USED; 1893 break; 1894 case LSC_SCODE_NOLINK: 1895 case LSC_SCODE_NOIOCB: 1896 case LSC_SCODE_NOXCB: 1897 case LSC_SCODE_CMD_FAILED: 1898 case LSC_SCODE_NOFABRIC: 1899 case LSC_SCODE_FW_NOT_READY: 1900 case LSC_SCODE_NOT_LOGGED_IN: 1901 case LSC_SCODE_NOPCB: 1902 case LSC_SCODE_ELS_REJECT: 1903 case LSC_SCODE_CMD_PARAM_ERR: 1904 case LSC_SCODE_NONPORT: 1905 case LSC_SCODE_LOGGED_IN: 1906 case LSC_SCODE_NOFLOGI_ACC: 1907 default: 1908 mb[0] = MBS_COMMAND_ERROR; 1909 break; 1910 } 1911 } else { 1912 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 1913 "Done %s.\n", __func__); 1914 1915 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1916 1917 mb[0] = MBS_COMMAND_COMPLETE; 1918 mb[1] = 0; 1919 if (iop[0] & BIT_4) { 1920 if (iop[0] & BIT_8) 1921 mb[1] |= BIT_1; 1922 } else 1923 mb[1] = BIT_0; 1924 1925 /* Passback COS information. */ 1926 mb[10] = 0; 1927 if (lg->io_parameter[7] || lg->io_parameter[8]) 1928 mb[10] |= BIT_0; /* Class 2. */ 1929 if (lg->io_parameter[9] || lg->io_parameter[10]) 1930 mb[10] |= BIT_1; /* Class 3. */ 1931 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7)) 1932 mb[10] |= BIT_7; /* Confirmed Completion 1933 * Allowed 1934 */ 1935 } 1936 1937 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1938 1939 return rval; 1940 } 1941 1942 /* 1943 * qla2x00_login_fabric 1944 * Issue login fabric port mailbox command. 1945 * 1946 * Input: 1947 * ha = adapter block pointer. 1948 * loop_id = device loop ID. 1949 * domain = device domain. 1950 * area = device area. 1951 * al_pa = device AL_PA. 1952 * status = pointer for return status. 1953 * opt = command options. 1954 * TARGET_QUEUE_LOCK must be released. 1955 * ADAPTER_STATE_LOCK must be released. 1956 * 1957 * Returns: 1958 * qla2x00 local function return status code. 1959 * 1960 * Context: 1961 * Kernel context. 1962 */ 1963 int 1964 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1965 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1966 { 1967 int rval; 1968 mbx_cmd_t mc; 1969 mbx_cmd_t *mcp = &mc; 1970 struct qla_hw_data *ha = vha->hw; 1971 1972 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 1973 "Entered %s.\n", __func__); 1974 1975 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 1976 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1977 if (HAS_EXTENDED_IDS(ha)) { 1978 mcp->mb[1] = loop_id; 1979 mcp->mb[10] = opt; 1980 mcp->out_mb |= MBX_10; 1981 } else { 1982 mcp->mb[1] = (loop_id << 8) | opt; 1983 } 1984 mcp->mb[2] = domain; 1985 mcp->mb[3] = area << 8 | al_pa; 1986 1987 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 1988 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1989 mcp->flags = 0; 1990 rval = qla2x00_mailbox_command(vha, mcp); 1991 1992 /* Return mailbox statuses. */ 1993 if (mb != NULL) { 1994 mb[0] = mcp->mb[0]; 1995 mb[1] = mcp->mb[1]; 1996 mb[2] = mcp->mb[2]; 1997 mb[6] = mcp->mb[6]; 1998 mb[7] = mcp->mb[7]; 1999 /* COS retrieved from Get-Port-Database mailbox command. */ 2000 mb[10] = 0; 2001 } 2002 2003 if (rval != QLA_SUCCESS) { 2004 /* RLU tmp code: need to change main mailbox_command function to 2005 * return ok even when the mailbox completion value is not 2006 * SUCCESS. The caller needs to be responsible to interpret 2007 * the return values of this mailbox command if we're not 2008 * to change too much of the existing code. 2009 */ 2010 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2011 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2012 mcp->mb[0] == 0x4006) 2013 rval = QLA_SUCCESS; 2014 2015 /*EMPTY*/ 2016 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2017 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2018 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2019 } else { 2020 /*EMPTY*/ 2021 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2022 "Done %s.\n", __func__); 2023 } 2024 2025 return rval; 2026 } 2027 2028 /* 2029 * qla2x00_login_local_device 2030 * Issue login loop port mailbox command. 2031 * 2032 * Input: 2033 * ha = adapter block pointer. 2034 * loop_id = device loop ID. 2035 * opt = command options. 2036 * 2037 * Returns: 2038 * Return status code. 2039 * 2040 * Context: 2041 * Kernel context. 2042 * 2043 */ 2044 int 2045 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2046 uint16_t *mb_ret, uint8_t opt) 2047 { 2048 int rval; 2049 mbx_cmd_t mc; 2050 mbx_cmd_t *mcp = &mc; 2051 struct qla_hw_data *ha = vha->hw; 2052 2053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2054 "Entered %s.\n", __func__); 2055 2056 if (IS_FWI2_CAPABLE(ha)) 2057 return qla24xx_login_fabric(vha, fcport->loop_id, 2058 fcport->d_id.b.domain, fcport->d_id.b.area, 2059 fcport->d_id.b.al_pa, mb_ret, opt); 2060 2061 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2062 if (HAS_EXTENDED_IDS(ha)) 2063 mcp->mb[1] = fcport->loop_id; 2064 else 2065 mcp->mb[1] = fcport->loop_id << 8; 2066 mcp->mb[2] = opt; 2067 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2068 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2069 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2070 mcp->flags = 0; 2071 rval = qla2x00_mailbox_command(vha, mcp); 2072 2073 /* Return mailbox statuses. */ 2074 if (mb_ret != NULL) { 2075 mb_ret[0] = mcp->mb[0]; 2076 mb_ret[1] = mcp->mb[1]; 2077 mb_ret[6] = mcp->mb[6]; 2078 mb_ret[7] = mcp->mb[7]; 2079 } 2080 2081 if (rval != QLA_SUCCESS) { 2082 /* AV tmp code: need to change main mailbox_command function to 2083 * return ok even when the mailbox completion value is not 2084 * SUCCESS. The caller needs to be responsible to interpret 2085 * the return values of this mailbox command if we're not 2086 * to change too much of the existing code. 2087 */ 2088 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2089 rval = QLA_SUCCESS; 2090 2091 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2092 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2093 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2094 } else { 2095 /*EMPTY*/ 2096 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2097 "Done %s.\n", __func__); 2098 } 2099 2100 return (rval); 2101 } 2102 2103 int 2104 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2105 uint8_t area, uint8_t al_pa) 2106 { 2107 int rval; 2108 struct logio_entry_24xx *lg; 2109 dma_addr_t lg_dma; 2110 struct qla_hw_data *ha = vha->hw; 2111 struct req_que *req; 2112 struct rsp_que *rsp; 2113 2114 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2115 "Entered %s.\n", __func__); 2116 2117 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2118 if (lg == NULL) { 2119 ql_log(ql_log_warn, vha, 0x106e, 2120 "Failed to allocate logout IOCB.\n"); 2121 return QLA_MEMORY_ALLOC_FAILED; 2122 } 2123 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2124 2125 if (ql2xmaxqueues > 1) 2126 req = ha->req_q_map[0]; 2127 else 2128 req = vha->req; 2129 rsp = req->rsp; 2130 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2131 lg->entry_count = 1; 2132 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2133 lg->nport_handle = cpu_to_le16(loop_id); 2134 lg->control_flags = 2135 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2136 LCF_FREE_NPORT); 2137 lg->port_id[0] = al_pa; 2138 lg->port_id[1] = area; 2139 lg->port_id[2] = domain; 2140 lg->vp_index = vha->vp_idx; 2141 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2142 (ha->r_a_tov / 10 * 2) + 2); 2143 if (rval != QLA_SUCCESS) { 2144 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2145 "Failed to issue logout IOCB (%x).\n", rval); 2146 } else if (lg->entry_status != 0) { 2147 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2148 "Failed to complete IOCB -- error status (%x).\n", 2149 lg->entry_status); 2150 rval = QLA_FUNCTION_FAILED; 2151 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 2152 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2153 "Failed to complete IOCB -- completion status (%x) " 2154 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2155 le32_to_cpu(lg->io_parameter[0]), 2156 le32_to_cpu(lg->io_parameter[1])); 2157 } else { 2158 /*EMPTY*/ 2159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2160 "Done %s.\n", __func__); 2161 } 2162 2163 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2164 2165 return rval; 2166 } 2167 2168 /* 2169 * qla2x00_fabric_logout 2170 * Issue logout fabric port mailbox command. 2171 * 2172 * Input: 2173 * ha = adapter block pointer. 2174 * loop_id = device loop ID. 2175 * TARGET_QUEUE_LOCK must be released. 2176 * ADAPTER_STATE_LOCK must be released. 2177 * 2178 * Returns: 2179 * qla2x00 local function return status code. 2180 * 2181 * Context: 2182 * Kernel context. 2183 */ 2184 int 2185 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2186 uint8_t area, uint8_t al_pa) 2187 { 2188 int rval; 2189 mbx_cmd_t mc; 2190 mbx_cmd_t *mcp = &mc; 2191 2192 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2193 "Entered %s.\n", __func__); 2194 2195 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2196 mcp->out_mb = MBX_1|MBX_0; 2197 if (HAS_EXTENDED_IDS(vha->hw)) { 2198 mcp->mb[1] = loop_id; 2199 mcp->mb[10] = 0; 2200 mcp->out_mb |= MBX_10; 2201 } else { 2202 mcp->mb[1] = loop_id << 8; 2203 } 2204 2205 mcp->in_mb = MBX_1|MBX_0; 2206 mcp->tov = MBX_TOV_SECONDS; 2207 mcp->flags = 0; 2208 rval = qla2x00_mailbox_command(vha, mcp); 2209 2210 if (rval != QLA_SUCCESS) { 2211 /*EMPTY*/ 2212 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2213 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2214 } else { 2215 /*EMPTY*/ 2216 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2217 "Done %s.\n", __func__); 2218 } 2219 2220 return rval; 2221 } 2222 2223 /* 2224 * qla2x00_full_login_lip 2225 * Issue full login LIP mailbox command. 2226 * 2227 * Input: 2228 * ha = adapter block pointer. 2229 * TARGET_QUEUE_LOCK must be released. 2230 * ADAPTER_STATE_LOCK must be released. 2231 * 2232 * Returns: 2233 * qla2x00 local function return status code. 2234 * 2235 * Context: 2236 * Kernel context. 2237 */ 2238 int 2239 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2240 { 2241 int rval; 2242 mbx_cmd_t mc; 2243 mbx_cmd_t *mcp = &mc; 2244 2245 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2246 "Entered %s.\n", __func__); 2247 2248 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2249 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2250 mcp->mb[2] = 0; 2251 mcp->mb[3] = 0; 2252 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2253 mcp->in_mb = MBX_0; 2254 mcp->tov = MBX_TOV_SECONDS; 2255 mcp->flags = 0; 2256 rval = qla2x00_mailbox_command(vha, mcp); 2257 2258 if (rval != QLA_SUCCESS) { 2259 /*EMPTY*/ 2260 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2261 } else { 2262 /*EMPTY*/ 2263 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2264 "Done %s.\n", __func__); 2265 } 2266 2267 return rval; 2268 } 2269 2270 /* 2271 * qla2x00_get_id_list 2272 * 2273 * Input: 2274 * ha = adapter block pointer. 2275 * 2276 * Returns: 2277 * qla2x00 local function return status code. 2278 * 2279 * Context: 2280 * Kernel context. 2281 */ 2282 int 2283 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2284 uint16_t *entries) 2285 { 2286 int rval; 2287 mbx_cmd_t mc; 2288 mbx_cmd_t *mcp = &mc; 2289 2290 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2291 "Entered %s.\n", __func__); 2292 2293 if (id_list == NULL) 2294 return QLA_FUNCTION_FAILED; 2295 2296 mcp->mb[0] = MBC_GET_ID_LIST; 2297 mcp->out_mb = MBX_0; 2298 if (IS_FWI2_CAPABLE(vha->hw)) { 2299 mcp->mb[2] = MSW(id_list_dma); 2300 mcp->mb[3] = LSW(id_list_dma); 2301 mcp->mb[6] = MSW(MSD(id_list_dma)); 2302 mcp->mb[7] = LSW(MSD(id_list_dma)); 2303 mcp->mb[8] = 0; 2304 mcp->mb[9] = vha->vp_idx; 2305 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2306 } else { 2307 mcp->mb[1] = MSW(id_list_dma); 2308 mcp->mb[2] = LSW(id_list_dma); 2309 mcp->mb[3] = MSW(MSD(id_list_dma)); 2310 mcp->mb[6] = LSW(MSD(id_list_dma)); 2311 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2312 } 2313 mcp->in_mb = MBX_1|MBX_0; 2314 mcp->tov = MBX_TOV_SECONDS; 2315 mcp->flags = 0; 2316 rval = qla2x00_mailbox_command(vha, mcp); 2317 2318 if (rval != QLA_SUCCESS) { 2319 /*EMPTY*/ 2320 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2321 } else { 2322 *entries = mcp->mb[1]; 2323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2324 "Done %s.\n", __func__); 2325 } 2326 2327 return rval; 2328 } 2329 2330 /* 2331 * qla2x00_get_resource_cnts 2332 * Get current firmware resource counts. 2333 * 2334 * Input: 2335 * ha = adapter block pointer. 2336 * 2337 * Returns: 2338 * qla2x00 local function return status code. 2339 * 2340 * Context: 2341 * Kernel context. 2342 */ 2343 int 2344 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt, 2345 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt, 2346 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs) 2347 { 2348 int rval; 2349 mbx_cmd_t mc; 2350 mbx_cmd_t *mcp = &mc; 2351 2352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2353 "Entered %s.\n", __func__); 2354 2355 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2356 mcp->out_mb = MBX_0; 2357 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2358 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2359 mcp->in_mb |= MBX_12; 2360 mcp->tov = MBX_TOV_SECONDS; 2361 mcp->flags = 0; 2362 rval = qla2x00_mailbox_command(vha, mcp); 2363 2364 if (rval != QLA_SUCCESS) { 2365 /*EMPTY*/ 2366 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2367 "Failed mb[0]=%x.\n", mcp->mb[0]); 2368 } else { 2369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2370 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2371 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2372 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2373 mcp->mb[11], mcp->mb[12]); 2374 2375 if (cur_xchg_cnt) 2376 *cur_xchg_cnt = mcp->mb[3]; 2377 if (orig_xchg_cnt) 2378 *orig_xchg_cnt = mcp->mb[6]; 2379 if (cur_iocb_cnt) 2380 *cur_iocb_cnt = mcp->mb[7]; 2381 if (orig_iocb_cnt) 2382 *orig_iocb_cnt = mcp->mb[10]; 2383 if (vha->hw->flags.npiv_supported && max_npiv_vports) 2384 *max_npiv_vports = mcp->mb[11]; 2385 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs) 2386 *max_fcfs = mcp->mb[12]; 2387 } 2388 2389 return (rval); 2390 } 2391 2392 /* 2393 * qla2x00_get_fcal_position_map 2394 * Get FCAL (LILP) position map using mailbox command 2395 * 2396 * Input: 2397 * ha = adapter state pointer. 2398 * pos_map = buffer pointer (can be NULL). 2399 * 2400 * Returns: 2401 * qla2x00 local function return status code. 2402 * 2403 * Context: 2404 * Kernel context. 2405 */ 2406 int 2407 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2408 { 2409 int rval; 2410 mbx_cmd_t mc; 2411 mbx_cmd_t *mcp = &mc; 2412 char *pmap; 2413 dma_addr_t pmap_dma; 2414 struct qla_hw_data *ha = vha->hw; 2415 2416 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2417 "Entered %s.\n", __func__); 2418 2419 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2420 if (pmap == NULL) { 2421 ql_log(ql_log_warn, vha, 0x1080, 2422 "Memory alloc failed.\n"); 2423 return QLA_MEMORY_ALLOC_FAILED; 2424 } 2425 memset(pmap, 0, FCAL_MAP_SIZE); 2426 2427 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2428 mcp->mb[2] = MSW(pmap_dma); 2429 mcp->mb[3] = LSW(pmap_dma); 2430 mcp->mb[6] = MSW(MSD(pmap_dma)); 2431 mcp->mb[7] = LSW(MSD(pmap_dma)); 2432 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2433 mcp->in_mb = MBX_1|MBX_0; 2434 mcp->buf_size = FCAL_MAP_SIZE; 2435 mcp->flags = MBX_DMA_IN; 2436 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2437 rval = qla2x00_mailbox_command(vha, mcp); 2438 2439 if (rval == QLA_SUCCESS) { 2440 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2441 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2442 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2443 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2444 pmap, pmap[0] + 1); 2445 2446 if (pos_map) 2447 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2448 } 2449 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2450 2451 if (rval != QLA_SUCCESS) { 2452 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2453 } else { 2454 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2455 "Done %s.\n", __func__); 2456 } 2457 2458 return rval; 2459 } 2460 2461 /* 2462 * qla2x00_get_link_status 2463 * 2464 * Input: 2465 * ha = adapter block pointer. 2466 * loop_id = device loop ID. 2467 * ret_buf = pointer to link status return buffer. 2468 * 2469 * Returns: 2470 * 0 = success. 2471 * BIT_0 = mem alloc error. 2472 * BIT_1 = mailbox error. 2473 */ 2474 int 2475 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2476 struct link_statistics *stats, dma_addr_t stats_dma) 2477 { 2478 int rval; 2479 mbx_cmd_t mc; 2480 mbx_cmd_t *mcp = &mc; 2481 uint32_t *siter, *diter, dwords; 2482 struct qla_hw_data *ha = vha->hw; 2483 2484 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2485 "Entered %s.\n", __func__); 2486 2487 mcp->mb[0] = MBC_GET_LINK_STATUS; 2488 mcp->mb[2] = MSW(stats_dma); 2489 mcp->mb[3] = LSW(stats_dma); 2490 mcp->mb[6] = MSW(MSD(stats_dma)); 2491 mcp->mb[7] = LSW(MSD(stats_dma)); 2492 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2493 mcp->in_mb = MBX_0; 2494 if (IS_FWI2_CAPABLE(ha)) { 2495 mcp->mb[1] = loop_id; 2496 mcp->mb[4] = 0; 2497 mcp->mb[10] = 0; 2498 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2499 mcp->in_mb |= MBX_1; 2500 } else if (HAS_EXTENDED_IDS(ha)) { 2501 mcp->mb[1] = loop_id; 2502 mcp->mb[10] = 0; 2503 mcp->out_mb |= MBX_10|MBX_1; 2504 } else { 2505 mcp->mb[1] = loop_id << 8; 2506 mcp->out_mb |= MBX_1; 2507 } 2508 mcp->tov = MBX_TOV_SECONDS; 2509 mcp->flags = IOCTL_CMD; 2510 rval = qla2x00_mailbox_command(vha, mcp); 2511 2512 if (rval == QLA_SUCCESS) { 2513 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2514 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2515 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2516 rval = QLA_FUNCTION_FAILED; 2517 } else { 2518 /* Copy over data -- firmware data is LE. */ 2519 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2520 "Done %s.\n", __func__); 2521 dwords = offsetof(struct link_statistics, unused1) / 4; 2522 siter = diter = &stats->link_fail_cnt; 2523 while (dwords--) 2524 *diter++ = le32_to_cpu(*siter++); 2525 } 2526 } else { 2527 /* Failed. */ 2528 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2529 } 2530 2531 return rval; 2532 } 2533 2534 int 2535 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2536 dma_addr_t stats_dma) 2537 { 2538 int rval; 2539 mbx_cmd_t mc; 2540 mbx_cmd_t *mcp = &mc; 2541 uint32_t *siter, *diter, dwords; 2542 2543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2544 "Entered %s.\n", __func__); 2545 2546 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2547 mcp->mb[2] = MSW(stats_dma); 2548 mcp->mb[3] = LSW(stats_dma); 2549 mcp->mb[6] = MSW(MSD(stats_dma)); 2550 mcp->mb[7] = LSW(MSD(stats_dma)); 2551 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2552 mcp->mb[9] = vha->vp_idx; 2553 mcp->mb[10] = 0; 2554 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2555 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2556 mcp->tov = MBX_TOV_SECONDS; 2557 mcp->flags = IOCTL_CMD; 2558 rval = qla2x00_mailbox_command(vha, mcp); 2559 2560 if (rval == QLA_SUCCESS) { 2561 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2562 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2563 "Failed mb[0]=%x.\n", mcp->mb[0]); 2564 rval = QLA_FUNCTION_FAILED; 2565 } else { 2566 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2567 "Done %s.\n", __func__); 2568 /* Copy over data -- firmware data is LE. */ 2569 dwords = sizeof(struct link_statistics) / 4; 2570 siter = diter = &stats->link_fail_cnt; 2571 while (dwords--) 2572 *diter++ = le32_to_cpu(*siter++); 2573 } 2574 } else { 2575 /* Failed. */ 2576 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2577 } 2578 2579 return rval; 2580 } 2581 2582 int 2583 qla24xx_abort_command(srb_t *sp) 2584 { 2585 int rval; 2586 unsigned long flags = 0; 2587 2588 struct abort_entry_24xx *abt; 2589 dma_addr_t abt_dma; 2590 uint32_t handle; 2591 fc_port_t *fcport = sp->fcport; 2592 struct scsi_qla_host *vha = fcport->vha; 2593 struct qla_hw_data *ha = vha->hw; 2594 struct req_que *req = vha->req; 2595 2596 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2597 "Entered %s.\n", __func__); 2598 2599 if (ql2xasynctmfenable) 2600 return qla24xx_async_abort_command(sp); 2601 2602 spin_lock_irqsave(&ha->hardware_lock, flags); 2603 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2604 if (req->outstanding_cmds[handle] == sp) 2605 break; 2606 } 2607 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2608 if (handle == req->num_outstanding_cmds) { 2609 /* Command not found. */ 2610 return QLA_FUNCTION_FAILED; 2611 } 2612 2613 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2614 if (abt == NULL) { 2615 ql_log(ql_log_warn, vha, 0x108d, 2616 "Failed to allocate abort IOCB.\n"); 2617 return QLA_MEMORY_ALLOC_FAILED; 2618 } 2619 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2620 2621 abt->entry_type = ABORT_IOCB_TYPE; 2622 abt->entry_count = 1; 2623 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2624 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2625 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2626 abt->port_id[0] = fcport->d_id.b.al_pa; 2627 abt->port_id[1] = fcport->d_id.b.area; 2628 abt->port_id[2] = fcport->d_id.b.domain; 2629 abt->vp_index = fcport->vha->vp_idx; 2630 2631 abt->req_que_no = cpu_to_le16(req->id); 2632 2633 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2634 if (rval != QLA_SUCCESS) { 2635 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2636 "Failed to issue IOCB (%x).\n", rval); 2637 } else if (abt->entry_status != 0) { 2638 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2639 "Failed to complete IOCB -- error status (%x).\n", 2640 abt->entry_status); 2641 rval = QLA_FUNCTION_FAILED; 2642 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) { 2643 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2644 "Failed to complete IOCB -- completion status (%x).\n", 2645 le16_to_cpu(abt->nport_handle)); 2646 if (abt->nport_handle == CS_IOCB_ERROR) 2647 rval = QLA_FUNCTION_PARAMETER_ERROR; 2648 else 2649 rval = QLA_FUNCTION_FAILED; 2650 } else { 2651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 2652 "Done %s.\n", __func__); 2653 } 2654 2655 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2656 2657 return rval; 2658 } 2659 2660 struct tsk_mgmt_cmd { 2661 union { 2662 struct tsk_mgmt_entry tsk; 2663 struct sts_entry_24xx sts; 2664 } p; 2665 }; 2666 2667 static int 2668 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2669 unsigned int l, int tag) 2670 { 2671 int rval, rval2; 2672 struct tsk_mgmt_cmd *tsk; 2673 struct sts_entry_24xx *sts; 2674 dma_addr_t tsk_dma; 2675 scsi_qla_host_t *vha; 2676 struct qla_hw_data *ha; 2677 struct req_que *req; 2678 struct rsp_que *rsp; 2679 2680 vha = fcport->vha; 2681 ha = vha->hw; 2682 req = vha->req; 2683 2684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 2685 "Entered %s.\n", __func__); 2686 2687 if (ha->flags.cpu_affinity_enabled) 2688 rsp = ha->rsp_q_map[tag + 1]; 2689 else 2690 rsp = req->rsp; 2691 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2692 if (tsk == NULL) { 2693 ql_log(ql_log_warn, vha, 0x1093, 2694 "Failed to allocate task management IOCB.\n"); 2695 return QLA_MEMORY_ALLOC_FAILED; 2696 } 2697 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2698 2699 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2700 tsk->p.tsk.entry_count = 1; 2701 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2702 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2703 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2704 tsk->p.tsk.control_flags = cpu_to_le32(type); 2705 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 2706 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 2707 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 2708 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 2709 if (type == TCF_LUN_RESET) { 2710 int_to_scsilun(l, &tsk->p.tsk.lun); 2711 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 2712 sizeof(tsk->p.tsk.lun)); 2713 } 2714 2715 sts = &tsk->p.sts; 2716 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 2717 if (rval != QLA_SUCCESS) { 2718 ql_dbg(ql_dbg_mbx, vha, 0x1094, 2719 "Failed to issue %s reset IOCB (%x).\n", name, rval); 2720 } else if (sts->entry_status != 0) { 2721 ql_dbg(ql_dbg_mbx, vha, 0x1095, 2722 "Failed to complete IOCB -- error status (%x).\n", 2723 sts->entry_status); 2724 rval = QLA_FUNCTION_FAILED; 2725 } else if (sts->comp_status != 2726 __constant_cpu_to_le16(CS_COMPLETE)) { 2727 ql_dbg(ql_dbg_mbx, vha, 0x1096, 2728 "Failed to complete IOCB -- completion status (%x).\n", 2729 le16_to_cpu(sts->comp_status)); 2730 rval = QLA_FUNCTION_FAILED; 2731 } else if (le16_to_cpu(sts->scsi_status) & 2732 SS_RESPONSE_INFO_LEN_VALID) { 2733 if (le32_to_cpu(sts->rsp_data_len) < 4) { 2734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 2735 "Ignoring inconsistent data length -- not enough " 2736 "response info (%d).\n", 2737 le32_to_cpu(sts->rsp_data_len)); 2738 } else if (sts->data[3]) { 2739 ql_dbg(ql_dbg_mbx, vha, 0x1098, 2740 "Failed to complete IOCB -- response (%x).\n", 2741 sts->data[3]); 2742 rval = QLA_FUNCTION_FAILED; 2743 } 2744 } 2745 2746 /* Issue marker IOCB. */ 2747 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 2748 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 2749 if (rval2 != QLA_SUCCESS) { 2750 ql_dbg(ql_dbg_mbx, vha, 0x1099, 2751 "Failed to issue marker IOCB (%x).\n", rval2); 2752 } else { 2753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 2754 "Done %s.\n", __func__); 2755 } 2756 2757 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 2758 2759 return rval; 2760 } 2761 2762 int 2763 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag) 2764 { 2765 struct qla_hw_data *ha = fcport->vha->hw; 2766 2767 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2768 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 2769 2770 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 2771 } 2772 2773 int 2774 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 2775 { 2776 struct qla_hw_data *ha = fcport->vha->hw; 2777 2778 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2779 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 2780 2781 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 2782 } 2783 2784 int 2785 qla2x00_system_error(scsi_qla_host_t *vha) 2786 { 2787 int rval; 2788 mbx_cmd_t mc; 2789 mbx_cmd_t *mcp = &mc; 2790 struct qla_hw_data *ha = vha->hw; 2791 2792 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 2793 return QLA_FUNCTION_FAILED; 2794 2795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 2796 "Entered %s.\n", __func__); 2797 2798 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 2799 mcp->out_mb = MBX_0; 2800 mcp->in_mb = MBX_0; 2801 mcp->tov = 5; 2802 mcp->flags = 0; 2803 rval = qla2x00_mailbox_command(vha, mcp); 2804 2805 if (rval != QLA_SUCCESS) { 2806 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 2807 } else { 2808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 2809 "Done %s.\n", __func__); 2810 } 2811 2812 return rval; 2813 } 2814 2815 int 2816 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 2817 { 2818 int rval; 2819 mbx_cmd_t mc; 2820 mbx_cmd_t *mcp = &mc; 2821 2822 if (!IS_QLA2031(vha->hw)) 2823 return QLA_FUNCTION_FAILED; 2824 2825 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 2826 "Entered %s.\n", __func__); 2827 2828 mcp->mb[0] = MBC_WRITE_SERDES; 2829 mcp->mb[1] = addr; 2830 mcp->mb[2] = data & 0xff; 2831 mcp->mb[3] = 0; 2832 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2833 mcp->in_mb = MBX_0; 2834 mcp->tov = MBX_TOV_SECONDS; 2835 mcp->flags = 0; 2836 rval = qla2x00_mailbox_command(vha, mcp); 2837 2838 if (rval != QLA_SUCCESS) { 2839 ql_dbg(ql_dbg_mbx, vha, 0x1183, 2840 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2841 } else { 2842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 2843 "Done %s.\n", __func__); 2844 } 2845 2846 return rval; 2847 } 2848 2849 int 2850 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 2851 { 2852 int rval; 2853 mbx_cmd_t mc; 2854 mbx_cmd_t *mcp = &mc; 2855 2856 if (!IS_QLA2031(vha->hw)) 2857 return QLA_FUNCTION_FAILED; 2858 2859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 2860 "Entered %s.\n", __func__); 2861 2862 mcp->mb[0] = MBC_READ_SERDES; 2863 mcp->mb[1] = addr; 2864 mcp->mb[3] = 0; 2865 mcp->out_mb = MBX_3|MBX_1|MBX_0; 2866 mcp->in_mb = MBX_1|MBX_0; 2867 mcp->tov = MBX_TOV_SECONDS; 2868 mcp->flags = 0; 2869 rval = qla2x00_mailbox_command(vha, mcp); 2870 2871 *data = mcp->mb[1] & 0xff; 2872 2873 if (rval != QLA_SUCCESS) { 2874 ql_dbg(ql_dbg_mbx, vha, 0x1186, 2875 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2876 } else { 2877 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 2878 "Done %s.\n", __func__); 2879 } 2880 2881 return rval; 2882 } 2883 2884 int 2885 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 2886 { 2887 int rval; 2888 mbx_cmd_t mc; 2889 mbx_cmd_t *mcp = &mc; 2890 2891 if (!IS_QLA8044(vha->hw)) 2892 return QLA_FUNCTION_FAILED; 2893 2894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186, 2895 "Entered %s.\n", __func__); 2896 2897 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 2898 mcp->mb[1] = HCS_WRITE_SERDES; 2899 mcp->mb[3] = LSW(addr); 2900 mcp->mb[4] = MSW(addr); 2901 mcp->mb[5] = LSW(data); 2902 mcp->mb[6] = MSW(data); 2903 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 2904 mcp->in_mb = MBX_0; 2905 mcp->tov = MBX_TOV_SECONDS; 2906 mcp->flags = 0; 2907 rval = qla2x00_mailbox_command(vha, mcp); 2908 2909 if (rval != QLA_SUCCESS) { 2910 ql_dbg(ql_dbg_mbx, vha, 0x1187, 2911 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2912 } else { 2913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 2914 "Done %s.\n", __func__); 2915 } 2916 2917 return rval; 2918 } 2919 2920 int 2921 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 2922 { 2923 int rval; 2924 mbx_cmd_t mc; 2925 mbx_cmd_t *mcp = &mc; 2926 2927 if (!IS_QLA8044(vha->hw)) 2928 return QLA_FUNCTION_FAILED; 2929 2930 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 2931 "Entered %s.\n", __func__); 2932 2933 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 2934 mcp->mb[1] = HCS_READ_SERDES; 2935 mcp->mb[3] = LSW(addr); 2936 mcp->mb[4] = MSW(addr); 2937 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 2938 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2939 mcp->tov = MBX_TOV_SECONDS; 2940 mcp->flags = 0; 2941 rval = qla2x00_mailbox_command(vha, mcp); 2942 2943 *data = mcp->mb[2] << 16 | mcp->mb[1]; 2944 2945 if (rval != QLA_SUCCESS) { 2946 ql_dbg(ql_dbg_mbx, vha, 0x118a, 2947 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2948 } else { 2949 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 2950 "Done %s.\n", __func__); 2951 } 2952 2953 return rval; 2954 } 2955 2956 /** 2957 * qla2x00_set_serdes_params() - 2958 * @ha: HA context 2959 * 2960 * Returns 2961 */ 2962 int 2963 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 2964 uint16_t sw_em_2g, uint16_t sw_em_4g) 2965 { 2966 int rval; 2967 mbx_cmd_t mc; 2968 mbx_cmd_t *mcp = &mc; 2969 2970 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 2971 "Entered %s.\n", __func__); 2972 2973 mcp->mb[0] = MBC_SERDES_PARAMS; 2974 mcp->mb[1] = BIT_0; 2975 mcp->mb[2] = sw_em_1g | BIT_15; 2976 mcp->mb[3] = sw_em_2g | BIT_15; 2977 mcp->mb[4] = sw_em_4g | BIT_15; 2978 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2979 mcp->in_mb = MBX_0; 2980 mcp->tov = MBX_TOV_SECONDS; 2981 mcp->flags = 0; 2982 rval = qla2x00_mailbox_command(vha, mcp); 2983 2984 if (rval != QLA_SUCCESS) { 2985 /*EMPTY*/ 2986 ql_dbg(ql_dbg_mbx, vha, 0x109f, 2987 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2988 } else { 2989 /*EMPTY*/ 2990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 2991 "Done %s.\n", __func__); 2992 } 2993 2994 return rval; 2995 } 2996 2997 int 2998 qla2x00_stop_firmware(scsi_qla_host_t *vha) 2999 { 3000 int rval; 3001 mbx_cmd_t mc; 3002 mbx_cmd_t *mcp = &mc; 3003 3004 if (!IS_FWI2_CAPABLE(vha->hw)) 3005 return QLA_FUNCTION_FAILED; 3006 3007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3008 "Entered %s.\n", __func__); 3009 3010 mcp->mb[0] = MBC_STOP_FIRMWARE; 3011 mcp->mb[1] = 0; 3012 mcp->out_mb = MBX_1|MBX_0; 3013 mcp->in_mb = MBX_0; 3014 mcp->tov = 5; 3015 mcp->flags = 0; 3016 rval = qla2x00_mailbox_command(vha, mcp); 3017 3018 if (rval != QLA_SUCCESS) { 3019 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3020 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3021 rval = QLA_INVALID_COMMAND; 3022 } else { 3023 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3024 "Done %s.\n", __func__); 3025 } 3026 3027 return rval; 3028 } 3029 3030 int 3031 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3032 uint16_t buffers) 3033 { 3034 int rval; 3035 mbx_cmd_t mc; 3036 mbx_cmd_t *mcp = &mc; 3037 3038 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3039 "Entered %s.\n", __func__); 3040 3041 if (!IS_FWI2_CAPABLE(vha->hw)) 3042 return QLA_FUNCTION_FAILED; 3043 3044 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3045 return QLA_FUNCTION_FAILED; 3046 3047 mcp->mb[0] = MBC_TRACE_CONTROL; 3048 mcp->mb[1] = TC_EFT_ENABLE; 3049 mcp->mb[2] = LSW(eft_dma); 3050 mcp->mb[3] = MSW(eft_dma); 3051 mcp->mb[4] = LSW(MSD(eft_dma)); 3052 mcp->mb[5] = MSW(MSD(eft_dma)); 3053 mcp->mb[6] = buffers; 3054 mcp->mb[7] = TC_AEN_DISABLE; 3055 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3056 mcp->in_mb = MBX_1|MBX_0; 3057 mcp->tov = MBX_TOV_SECONDS; 3058 mcp->flags = 0; 3059 rval = qla2x00_mailbox_command(vha, mcp); 3060 if (rval != QLA_SUCCESS) { 3061 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3062 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3063 rval, mcp->mb[0], mcp->mb[1]); 3064 } else { 3065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3066 "Done %s.\n", __func__); 3067 } 3068 3069 return rval; 3070 } 3071 3072 int 3073 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3074 { 3075 int rval; 3076 mbx_cmd_t mc; 3077 mbx_cmd_t *mcp = &mc; 3078 3079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3080 "Entered %s.\n", __func__); 3081 3082 if (!IS_FWI2_CAPABLE(vha->hw)) 3083 return QLA_FUNCTION_FAILED; 3084 3085 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3086 return QLA_FUNCTION_FAILED; 3087 3088 mcp->mb[0] = MBC_TRACE_CONTROL; 3089 mcp->mb[1] = TC_EFT_DISABLE; 3090 mcp->out_mb = MBX_1|MBX_0; 3091 mcp->in_mb = MBX_1|MBX_0; 3092 mcp->tov = MBX_TOV_SECONDS; 3093 mcp->flags = 0; 3094 rval = qla2x00_mailbox_command(vha, mcp); 3095 if (rval != QLA_SUCCESS) { 3096 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3097 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3098 rval, mcp->mb[0], mcp->mb[1]); 3099 } else { 3100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3101 "Done %s.\n", __func__); 3102 } 3103 3104 return rval; 3105 } 3106 3107 int 3108 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3109 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3110 { 3111 int rval; 3112 mbx_cmd_t mc; 3113 mbx_cmd_t *mcp = &mc; 3114 3115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3116 "Entered %s.\n", __func__); 3117 3118 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3119 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3120 return QLA_FUNCTION_FAILED; 3121 3122 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3123 return QLA_FUNCTION_FAILED; 3124 3125 mcp->mb[0] = MBC_TRACE_CONTROL; 3126 mcp->mb[1] = TC_FCE_ENABLE; 3127 mcp->mb[2] = LSW(fce_dma); 3128 mcp->mb[3] = MSW(fce_dma); 3129 mcp->mb[4] = LSW(MSD(fce_dma)); 3130 mcp->mb[5] = MSW(MSD(fce_dma)); 3131 mcp->mb[6] = buffers; 3132 mcp->mb[7] = TC_AEN_DISABLE; 3133 mcp->mb[8] = 0; 3134 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3135 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3136 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3137 MBX_1|MBX_0; 3138 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3139 mcp->tov = MBX_TOV_SECONDS; 3140 mcp->flags = 0; 3141 rval = qla2x00_mailbox_command(vha, mcp); 3142 if (rval != QLA_SUCCESS) { 3143 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3144 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3145 rval, mcp->mb[0], mcp->mb[1]); 3146 } else { 3147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3148 "Done %s.\n", __func__); 3149 3150 if (mb) 3151 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3152 if (dwords) 3153 *dwords = buffers; 3154 } 3155 3156 return rval; 3157 } 3158 3159 int 3160 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3161 { 3162 int rval; 3163 mbx_cmd_t mc; 3164 mbx_cmd_t *mcp = &mc; 3165 3166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3167 "Entered %s.\n", __func__); 3168 3169 if (!IS_FWI2_CAPABLE(vha->hw)) 3170 return QLA_FUNCTION_FAILED; 3171 3172 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3173 return QLA_FUNCTION_FAILED; 3174 3175 mcp->mb[0] = MBC_TRACE_CONTROL; 3176 mcp->mb[1] = TC_FCE_DISABLE; 3177 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3178 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3179 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3180 MBX_1|MBX_0; 3181 mcp->tov = MBX_TOV_SECONDS; 3182 mcp->flags = 0; 3183 rval = qla2x00_mailbox_command(vha, mcp); 3184 if (rval != QLA_SUCCESS) { 3185 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3186 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3187 rval, mcp->mb[0], mcp->mb[1]); 3188 } else { 3189 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3190 "Done %s.\n", __func__); 3191 3192 if (wr) 3193 *wr = (uint64_t) mcp->mb[5] << 48 | 3194 (uint64_t) mcp->mb[4] << 32 | 3195 (uint64_t) mcp->mb[3] << 16 | 3196 (uint64_t) mcp->mb[2]; 3197 if (rd) 3198 *rd = (uint64_t) mcp->mb[9] << 48 | 3199 (uint64_t) mcp->mb[8] << 32 | 3200 (uint64_t) mcp->mb[7] << 16 | 3201 (uint64_t) mcp->mb[6]; 3202 } 3203 3204 return rval; 3205 } 3206 3207 int 3208 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3209 uint16_t *port_speed, uint16_t *mb) 3210 { 3211 int rval; 3212 mbx_cmd_t mc; 3213 mbx_cmd_t *mcp = &mc; 3214 3215 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3216 "Entered %s.\n", __func__); 3217 3218 if (!IS_IIDMA_CAPABLE(vha->hw)) 3219 return QLA_FUNCTION_FAILED; 3220 3221 mcp->mb[0] = MBC_PORT_PARAMS; 3222 mcp->mb[1] = loop_id; 3223 mcp->mb[2] = mcp->mb[3] = 0; 3224 mcp->mb[9] = vha->vp_idx; 3225 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3226 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3227 mcp->tov = MBX_TOV_SECONDS; 3228 mcp->flags = 0; 3229 rval = qla2x00_mailbox_command(vha, mcp); 3230 3231 /* Return mailbox statuses. */ 3232 if (mb != NULL) { 3233 mb[0] = mcp->mb[0]; 3234 mb[1] = mcp->mb[1]; 3235 mb[3] = mcp->mb[3]; 3236 } 3237 3238 if (rval != QLA_SUCCESS) { 3239 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3240 } else { 3241 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3242 "Done %s.\n", __func__); 3243 if (port_speed) 3244 *port_speed = mcp->mb[3]; 3245 } 3246 3247 return rval; 3248 } 3249 3250 int 3251 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3252 uint16_t port_speed, uint16_t *mb) 3253 { 3254 int rval; 3255 mbx_cmd_t mc; 3256 mbx_cmd_t *mcp = &mc; 3257 3258 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3259 "Entered %s.\n", __func__); 3260 3261 if (!IS_IIDMA_CAPABLE(vha->hw)) 3262 return QLA_FUNCTION_FAILED; 3263 3264 mcp->mb[0] = MBC_PORT_PARAMS; 3265 mcp->mb[1] = loop_id; 3266 mcp->mb[2] = BIT_0; 3267 if (IS_CNA_CAPABLE(vha->hw)) 3268 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3269 else 3270 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3271 mcp->mb[9] = vha->vp_idx; 3272 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3273 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3274 mcp->tov = MBX_TOV_SECONDS; 3275 mcp->flags = 0; 3276 rval = qla2x00_mailbox_command(vha, mcp); 3277 3278 /* Return mailbox statuses. */ 3279 if (mb != NULL) { 3280 mb[0] = mcp->mb[0]; 3281 mb[1] = mcp->mb[1]; 3282 mb[3] = mcp->mb[3]; 3283 } 3284 3285 if (rval != QLA_SUCCESS) { 3286 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3287 "Failed=%x.\n", rval); 3288 } else { 3289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3290 "Done %s.\n", __func__); 3291 } 3292 3293 return rval; 3294 } 3295 3296 void 3297 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3298 struct vp_rpt_id_entry_24xx *rptid_entry) 3299 { 3300 uint8_t vp_idx; 3301 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 3302 struct qla_hw_data *ha = vha->hw; 3303 scsi_qla_host_t *vp; 3304 unsigned long flags; 3305 int found; 3306 3307 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3308 "Entered %s.\n", __func__); 3309 3310 if (rptid_entry->entry_status != 0) 3311 return; 3312 3313 if (rptid_entry->format == 0) { 3314 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3315 "Format 0 : Number of VPs setup %d, number of " 3316 "VPs acquired %d.\n", 3317 MSB(le16_to_cpu(rptid_entry->vp_count)), 3318 LSB(le16_to_cpu(rptid_entry->vp_count))); 3319 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3320 "Primary port id %02x%02x%02x.\n", 3321 rptid_entry->port_id[2], rptid_entry->port_id[1], 3322 rptid_entry->port_id[0]); 3323 } else if (rptid_entry->format == 1) { 3324 vp_idx = LSB(stat); 3325 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3326 "Format 1: VP[%d] enabled - status %d - with " 3327 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 3328 rptid_entry->port_id[2], rptid_entry->port_id[1], 3329 rptid_entry->port_id[0]); 3330 3331 vp = vha; 3332 if (vp_idx == 0 && (MSB(stat) != 1)) 3333 goto reg_needed; 3334 3335 if (MSB(stat) != 0 && MSB(stat) != 2) { 3336 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3337 "Could not acquire ID for VP[%d].\n", vp_idx); 3338 return; 3339 } 3340 3341 found = 0; 3342 spin_lock_irqsave(&ha->vport_slock, flags); 3343 list_for_each_entry(vp, &ha->vp_list, list) { 3344 if (vp_idx == vp->vp_idx) { 3345 found = 1; 3346 break; 3347 } 3348 } 3349 spin_unlock_irqrestore(&ha->vport_slock, flags); 3350 3351 if (!found) 3352 return; 3353 3354 vp->d_id.b.domain = rptid_entry->port_id[2]; 3355 vp->d_id.b.area = rptid_entry->port_id[1]; 3356 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3357 3358 /* 3359 * Cannot configure here as we are still sitting on the 3360 * response queue. Handle it in dpc context. 3361 */ 3362 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3363 3364 reg_needed: 3365 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3366 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3367 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3368 qla2xxx_wake_dpc(vha); 3369 } 3370 } 3371 3372 /* 3373 * qla24xx_modify_vp_config 3374 * Change VP configuration for vha 3375 * 3376 * Input: 3377 * vha = adapter block pointer. 3378 * 3379 * Returns: 3380 * qla2xxx local function return status code. 3381 * 3382 * Context: 3383 * Kernel context. 3384 */ 3385 int 3386 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3387 { 3388 int rval; 3389 struct vp_config_entry_24xx *vpmod; 3390 dma_addr_t vpmod_dma; 3391 struct qla_hw_data *ha = vha->hw; 3392 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3393 3394 /* This can be called by the parent */ 3395 3396 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3397 "Entered %s.\n", __func__); 3398 3399 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3400 if (!vpmod) { 3401 ql_log(ql_log_warn, vha, 0x10bc, 3402 "Failed to allocate modify VP IOCB.\n"); 3403 return QLA_MEMORY_ALLOC_FAILED; 3404 } 3405 3406 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3407 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3408 vpmod->entry_count = 1; 3409 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3410 vpmod->vp_count = 1; 3411 vpmod->vp_index1 = vha->vp_idx; 3412 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3413 3414 qlt_modify_vp_config(vha, vpmod); 3415 3416 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3417 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3418 vpmod->entry_count = 1; 3419 3420 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3421 if (rval != QLA_SUCCESS) { 3422 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3423 "Failed to issue VP config IOCB (%x).\n", rval); 3424 } else if (vpmod->comp_status != 0) { 3425 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3426 "Failed to complete IOCB -- error status (%x).\n", 3427 vpmod->comp_status); 3428 rval = QLA_FUNCTION_FAILED; 3429 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3430 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3431 "Failed to complete IOCB -- completion status (%x).\n", 3432 le16_to_cpu(vpmod->comp_status)); 3433 rval = QLA_FUNCTION_FAILED; 3434 } else { 3435 /* EMPTY */ 3436 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3437 "Done %s.\n", __func__); 3438 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3439 } 3440 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3441 3442 return rval; 3443 } 3444 3445 /* 3446 * qla24xx_control_vp 3447 * Enable a virtual port for given host 3448 * 3449 * Input: 3450 * ha = adapter block pointer. 3451 * vhba = virtual adapter (unused) 3452 * index = index number for enabled VP 3453 * 3454 * Returns: 3455 * qla2xxx local function return status code. 3456 * 3457 * Context: 3458 * Kernel context. 3459 */ 3460 int 3461 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3462 { 3463 int rval; 3464 int map, pos; 3465 struct vp_ctrl_entry_24xx *vce; 3466 dma_addr_t vce_dma; 3467 struct qla_hw_data *ha = vha->hw; 3468 int vp_index = vha->vp_idx; 3469 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3470 3471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3472 "Entered %s enabling index %d.\n", __func__, vp_index); 3473 3474 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3475 return QLA_PARAMETER_ERROR; 3476 3477 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3478 if (!vce) { 3479 ql_log(ql_log_warn, vha, 0x10c2, 3480 "Failed to allocate VP control IOCB.\n"); 3481 return QLA_MEMORY_ALLOC_FAILED; 3482 } 3483 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3484 3485 vce->entry_type = VP_CTRL_IOCB_TYPE; 3486 vce->entry_count = 1; 3487 vce->command = cpu_to_le16(cmd); 3488 vce->vp_count = __constant_cpu_to_le16(1); 3489 3490 /* index map in firmware starts with 1; decrement index 3491 * this is ok as we never use index 0 3492 */ 3493 map = (vp_index - 1) / 8; 3494 pos = (vp_index - 1) & 7; 3495 mutex_lock(&ha->vport_lock); 3496 vce->vp_idx_map[map] |= 1 << pos; 3497 mutex_unlock(&ha->vport_lock); 3498 3499 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3500 if (rval != QLA_SUCCESS) { 3501 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3502 "Failed to issue VP control IOCB (%x).\n", rval); 3503 } else if (vce->entry_status != 0) { 3504 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3505 "Failed to complete IOCB -- error status (%x).\n", 3506 vce->entry_status); 3507 rval = QLA_FUNCTION_FAILED; 3508 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3509 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3510 "Failed to complet IOCB -- completion status (%x).\n", 3511 le16_to_cpu(vce->comp_status)); 3512 rval = QLA_FUNCTION_FAILED; 3513 } else { 3514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3515 "Done %s.\n", __func__); 3516 } 3517 3518 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3519 3520 return rval; 3521 } 3522 3523 /* 3524 * qla2x00_send_change_request 3525 * Receive or disable RSCN request from fabric controller 3526 * 3527 * Input: 3528 * ha = adapter block pointer 3529 * format = registration format: 3530 * 0 - Reserved 3531 * 1 - Fabric detected registration 3532 * 2 - N_port detected registration 3533 * 3 - Full registration 3534 * FF - clear registration 3535 * vp_idx = Virtual port index 3536 * 3537 * Returns: 3538 * qla2x00 local function return status code. 3539 * 3540 * Context: 3541 * Kernel Context 3542 */ 3543 3544 int 3545 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3546 uint16_t vp_idx) 3547 { 3548 int rval; 3549 mbx_cmd_t mc; 3550 mbx_cmd_t *mcp = &mc; 3551 3552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3553 "Entered %s.\n", __func__); 3554 3555 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3556 mcp->mb[1] = format; 3557 mcp->mb[9] = vp_idx; 3558 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3559 mcp->in_mb = MBX_0|MBX_1; 3560 mcp->tov = MBX_TOV_SECONDS; 3561 mcp->flags = 0; 3562 rval = qla2x00_mailbox_command(vha, mcp); 3563 3564 if (rval == QLA_SUCCESS) { 3565 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3566 rval = BIT_1; 3567 } 3568 } else 3569 rval = BIT_1; 3570 3571 return rval; 3572 } 3573 3574 int 3575 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3576 uint32_t size) 3577 { 3578 int rval; 3579 mbx_cmd_t mc; 3580 mbx_cmd_t *mcp = &mc; 3581 3582 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3583 "Entered %s.\n", __func__); 3584 3585 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3586 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3587 mcp->mb[8] = MSW(addr); 3588 mcp->out_mb = MBX_8|MBX_0; 3589 } else { 3590 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3591 mcp->out_mb = MBX_0; 3592 } 3593 mcp->mb[1] = LSW(addr); 3594 mcp->mb[2] = MSW(req_dma); 3595 mcp->mb[3] = LSW(req_dma); 3596 mcp->mb[6] = MSW(MSD(req_dma)); 3597 mcp->mb[7] = LSW(MSD(req_dma)); 3598 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3599 if (IS_FWI2_CAPABLE(vha->hw)) { 3600 mcp->mb[4] = MSW(size); 3601 mcp->mb[5] = LSW(size); 3602 mcp->out_mb |= MBX_5|MBX_4; 3603 } else { 3604 mcp->mb[4] = LSW(size); 3605 mcp->out_mb |= MBX_4; 3606 } 3607 3608 mcp->in_mb = MBX_0; 3609 mcp->tov = MBX_TOV_SECONDS; 3610 mcp->flags = 0; 3611 rval = qla2x00_mailbox_command(vha, mcp); 3612 3613 if (rval != QLA_SUCCESS) { 3614 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3615 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3616 } else { 3617 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 3618 "Done %s.\n", __func__); 3619 } 3620 3621 return rval; 3622 } 3623 /* 84XX Support **************************************************************/ 3624 3625 struct cs84xx_mgmt_cmd { 3626 union { 3627 struct verify_chip_entry_84xx req; 3628 struct verify_chip_rsp_84xx rsp; 3629 } p; 3630 }; 3631 3632 int 3633 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3634 { 3635 int rval, retry; 3636 struct cs84xx_mgmt_cmd *mn; 3637 dma_addr_t mn_dma; 3638 uint16_t options; 3639 unsigned long flags; 3640 struct qla_hw_data *ha = vha->hw; 3641 3642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 3643 "Entered %s.\n", __func__); 3644 3645 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 3646 if (mn == NULL) { 3647 return QLA_MEMORY_ALLOC_FAILED; 3648 } 3649 3650 /* Force Update? */ 3651 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 3652 /* Diagnostic firmware? */ 3653 /* options |= MENLO_DIAG_FW; */ 3654 /* We update the firmware with only one data sequence. */ 3655 options |= VCO_END_OF_DATA; 3656 3657 do { 3658 retry = 0; 3659 memset(mn, 0, sizeof(*mn)); 3660 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 3661 mn->p.req.entry_count = 1; 3662 mn->p.req.options = cpu_to_le16(options); 3663 3664 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 3665 "Dump of Verify Request.\n"); 3666 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 3667 (uint8_t *)mn, sizeof(*mn)); 3668 3669 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 3670 if (rval != QLA_SUCCESS) { 3671 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 3672 "Failed to issue verify IOCB (%x).\n", rval); 3673 goto verify_done; 3674 } 3675 3676 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 3677 "Dump of Verify Response.\n"); 3678 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 3679 (uint8_t *)mn, sizeof(*mn)); 3680 3681 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 3682 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 3683 le16_to_cpu(mn->p.rsp.failure_code) : 0; 3684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 3685 "cs=%x fc=%x.\n", status[0], status[1]); 3686 3687 if (status[0] != CS_COMPLETE) { 3688 rval = QLA_FUNCTION_FAILED; 3689 if (!(options & VCO_DONT_UPDATE_FW)) { 3690 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 3691 "Firmware update failed. Retrying " 3692 "without update firmware.\n"); 3693 options |= VCO_DONT_UPDATE_FW; 3694 options &= ~VCO_FORCE_UPDATE; 3695 retry = 1; 3696 } 3697 } else { 3698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 3699 "Firmware updated to %x.\n", 3700 le32_to_cpu(mn->p.rsp.fw_ver)); 3701 3702 /* NOTE: we only update OP firmware. */ 3703 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 3704 ha->cs84xx->op_fw_version = 3705 le32_to_cpu(mn->p.rsp.fw_ver); 3706 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 3707 flags); 3708 } 3709 } while (retry); 3710 3711 verify_done: 3712 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 3713 3714 if (rval != QLA_SUCCESS) { 3715 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 3716 "Failed=%x.\n", rval); 3717 } else { 3718 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 3719 "Done %s.\n", __func__); 3720 } 3721 3722 return rval; 3723 } 3724 3725 int 3726 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 3727 { 3728 int rval; 3729 unsigned long flags; 3730 mbx_cmd_t mc; 3731 mbx_cmd_t *mcp = &mc; 3732 struct qla_hw_data *ha = vha->hw; 3733 3734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 3735 "Entered %s.\n", __func__); 3736 3737 if (IS_SHADOW_REG_CAPABLE(ha)) 3738 req->options |= BIT_13; 3739 3740 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3741 mcp->mb[1] = req->options; 3742 mcp->mb[2] = MSW(LSD(req->dma)); 3743 mcp->mb[3] = LSW(LSD(req->dma)); 3744 mcp->mb[6] = MSW(MSD(req->dma)); 3745 mcp->mb[7] = LSW(MSD(req->dma)); 3746 mcp->mb[5] = req->length; 3747 if (req->rsp) 3748 mcp->mb[10] = req->rsp->id; 3749 mcp->mb[12] = req->qos; 3750 mcp->mb[11] = req->vp_idx; 3751 mcp->mb[13] = req->rid; 3752 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3753 mcp->mb[15] = 0; 3754 3755 mcp->mb[4] = req->id; 3756 /* que in ptr index */ 3757 mcp->mb[8] = 0; 3758 /* que out ptr index */ 3759 mcp->mb[9] = *req->out_ptr = 0; 3760 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 3761 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3762 mcp->in_mb = MBX_0; 3763 mcp->flags = MBX_DMA_OUT; 3764 mcp->tov = MBX_TOV_SECONDS * 2; 3765 3766 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3767 mcp->in_mb |= MBX_1; 3768 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3769 mcp->out_mb |= MBX_15; 3770 /* debug q create issue in SR-IOV */ 3771 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3772 } 3773 3774 spin_lock_irqsave(&ha->hardware_lock, flags); 3775 if (!(req->options & BIT_0)) { 3776 WRT_REG_DWORD(req->req_q_in, 0); 3777 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 3778 WRT_REG_DWORD(req->req_q_out, 0); 3779 } 3780 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3781 3782 rval = qla2x00_mailbox_command(vha, mcp); 3783 if (rval != QLA_SUCCESS) { 3784 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 3785 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3786 } else { 3787 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 3788 "Done %s.\n", __func__); 3789 } 3790 3791 return rval; 3792 } 3793 3794 int 3795 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 3796 { 3797 int rval; 3798 unsigned long flags; 3799 mbx_cmd_t mc; 3800 mbx_cmd_t *mcp = &mc; 3801 struct qla_hw_data *ha = vha->hw; 3802 3803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 3804 "Entered %s.\n", __func__); 3805 3806 if (IS_SHADOW_REG_CAPABLE(ha)) 3807 rsp->options |= BIT_13; 3808 3809 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3810 mcp->mb[1] = rsp->options; 3811 mcp->mb[2] = MSW(LSD(rsp->dma)); 3812 mcp->mb[3] = LSW(LSD(rsp->dma)); 3813 mcp->mb[6] = MSW(MSD(rsp->dma)); 3814 mcp->mb[7] = LSW(MSD(rsp->dma)); 3815 mcp->mb[5] = rsp->length; 3816 mcp->mb[14] = rsp->msix->entry; 3817 mcp->mb[13] = rsp->rid; 3818 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3819 mcp->mb[15] = 0; 3820 3821 mcp->mb[4] = rsp->id; 3822 /* que in ptr index */ 3823 mcp->mb[8] = *rsp->in_ptr = 0; 3824 /* que out ptr index */ 3825 mcp->mb[9] = 0; 3826 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 3827 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3828 mcp->in_mb = MBX_0; 3829 mcp->flags = MBX_DMA_OUT; 3830 mcp->tov = MBX_TOV_SECONDS * 2; 3831 3832 if (IS_QLA81XX(ha)) { 3833 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 3834 mcp->in_mb |= MBX_1; 3835 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3836 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 3837 mcp->in_mb |= MBX_1; 3838 /* debug q create issue in SR-IOV */ 3839 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3840 } 3841 3842 spin_lock_irqsave(&ha->hardware_lock, flags); 3843 if (!(rsp->options & BIT_0)) { 3844 WRT_REG_DWORD(rsp->rsp_q_out, 0); 3845 if (!IS_QLA83XX(ha)) 3846 WRT_REG_DWORD(rsp->rsp_q_in, 0); 3847 } 3848 3849 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3850 3851 rval = qla2x00_mailbox_command(vha, mcp); 3852 if (rval != QLA_SUCCESS) { 3853 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 3854 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3855 } else { 3856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 3857 "Done %s.\n", __func__); 3858 } 3859 3860 return rval; 3861 } 3862 3863 int 3864 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 3865 { 3866 int rval; 3867 mbx_cmd_t mc; 3868 mbx_cmd_t *mcp = &mc; 3869 3870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 3871 "Entered %s.\n", __func__); 3872 3873 mcp->mb[0] = MBC_IDC_ACK; 3874 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3875 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3876 mcp->in_mb = MBX_0; 3877 mcp->tov = MBX_TOV_SECONDS; 3878 mcp->flags = 0; 3879 rval = qla2x00_mailbox_command(vha, mcp); 3880 3881 if (rval != QLA_SUCCESS) { 3882 ql_dbg(ql_dbg_mbx, vha, 0x10da, 3883 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3884 } else { 3885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 3886 "Done %s.\n", __func__); 3887 } 3888 3889 return rval; 3890 } 3891 3892 int 3893 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 3894 { 3895 int rval; 3896 mbx_cmd_t mc; 3897 mbx_cmd_t *mcp = &mc; 3898 3899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 3900 "Entered %s.\n", __func__); 3901 3902 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3903 !IS_QLA27XX(vha->hw)) 3904 return QLA_FUNCTION_FAILED; 3905 3906 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3907 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 3908 mcp->out_mb = MBX_1|MBX_0; 3909 mcp->in_mb = MBX_1|MBX_0; 3910 mcp->tov = MBX_TOV_SECONDS; 3911 mcp->flags = 0; 3912 rval = qla2x00_mailbox_command(vha, mcp); 3913 3914 if (rval != QLA_SUCCESS) { 3915 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 3916 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3917 rval, mcp->mb[0], mcp->mb[1]); 3918 } else { 3919 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 3920 "Done %s.\n", __func__); 3921 *sector_size = mcp->mb[1]; 3922 } 3923 3924 return rval; 3925 } 3926 3927 int 3928 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 3929 { 3930 int rval; 3931 mbx_cmd_t mc; 3932 mbx_cmd_t *mcp = &mc; 3933 3934 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3935 !IS_QLA27XX(vha->hw)) 3936 return QLA_FUNCTION_FAILED; 3937 3938 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 3939 "Entered %s.\n", __func__); 3940 3941 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3942 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 3943 FAC_OPT_CMD_WRITE_PROTECT; 3944 mcp->out_mb = MBX_1|MBX_0; 3945 mcp->in_mb = MBX_1|MBX_0; 3946 mcp->tov = MBX_TOV_SECONDS; 3947 mcp->flags = 0; 3948 rval = qla2x00_mailbox_command(vha, mcp); 3949 3950 if (rval != QLA_SUCCESS) { 3951 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 3952 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3953 rval, mcp->mb[0], mcp->mb[1]); 3954 } else { 3955 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 3956 "Done %s.\n", __func__); 3957 } 3958 3959 return rval; 3960 } 3961 3962 int 3963 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 3964 { 3965 int rval; 3966 mbx_cmd_t mc; 3967 mbx_cmd_t *mcp = &mc; 3968 3969 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3970 !IS_QLA27XX(vha->hw)) 3971 return QLA_FUNCTION_FAILED; 3972 3973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 3974 "Entered %s.\n", __func__); 3975 3976 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3977 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 3978 mcp->mb[2] = LSW(start); 3979 mcp->mb[3] = MSW(start); 3980 mcp->mb[4] = LSW(finish); 3981 mcp->mb[5] = MSW(finish); 3982 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3983 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3984 mcp->tov = MBX_TOV_SECONDS; 3985 mcp->flags = 0; 3986 rval = qla2x00_mailbox_command(vha, mcp); 3987 3988 if (rval != QLA_SUCCESS) { 3989 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 3990 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 3991 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 3992 } else { 3993 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 3994 "Done %s.\n", __func__); 3995 } 3996 3997 return rval; 3998 } 3999 4000 int 4001 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4002 { 4003 int rval = 0; 4004 mbx_cmd_t mc; 4005 mbx_cmd_t *mcp = &mc; 4006 4007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4008 "Entered %s.\n", __func__); 4009 4010 mcp->mb[0] = MBC_RESTART_MPI_FW; 4011 mcp->out_mb = MBX_0; 4012 mcp->in_mb = MBX_0|MBX_1; 4013 mcp->tov = MBX_TOV_SECONDS; 4014 mcp->flags = 0; 4015 rval = qla2x00_mailbox_command(vha, mcp); 4016 4017 if (rval != QLA_SUCCESS) { 4018 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4019 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4020 rval, mcp->mb[0], mcp->mb[1]); 4021 } else { 4022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4023 "Done %s.\n", __func__); 4024 } 4025 4026 return rval; 4027 } 4028 4029 int 4030 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4031 { 4032 int rval; 4033 mbx_cmd_t mc; 4034 mbx_cmd_t *mcp = &mc; 4035 int i; 4036 int len; 4037 uint16_t *str; 4038 struct qla_hw_data *ha = vha->hw; 4039 4040 if (!IS_P3P_TYPE(ha)) 4041 return QLA_FUNCTION_FAILED; 4042 4043 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4044 "Entered %s.\n", __func__); 4045 4046 str = (void *)version; 4047 len = strlen(version); 4048 4049 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4050 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4051 mcp->out_mb = MBX_1|MBX_0; 4052 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4053 mcp->mb[i] = cpu_to_le16p(str); 4054 mcp->out_mb |= 1<<i; 4055 } 4056 for (; i < 16; i++) { 4057 mcp->mb[i] = 0; 4058 mcp->out_mb |= 1<<i; 4059 } 4060 mcp->in_mb = MBX_1|MBX_0; 4061 mcp->tov = MBX_TOV_SECONDS; 4062 mcp->flags = 0; 4063 rval = qla2x00_mailbox_command(vha, mcp); 4064 4065 if (rval != QLA_SUCCESS) { 4066 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4067 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4068 } else { 4069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4070 "Done %s.\n", __func__); 4071 } 4072 4073 return rval; 4074 } 4075 4076 int 4077 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4078 { 4079 int rval; 4080 mbx_cmd_t mc; 4081 mbx_cmd_t *mcp = &mc; 4082 int len; 4083 uint16_t dwlen; 4084 uint8_t *str; 4085 dma_addr_t str_dma; 4086 struct qla_hw_data *ha = vha->hw; 4087 4088 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4089 IS_P3P_TYPE(ha)) 4090 return QLA_FUNCTION_FAILED; 4091 4092 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4093 "Entered %s.\n", __func__); 4094 4095 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4096 if (!str) { 4097 ql_log(ql_log_warn, vha, 0x117f, 4098 "Failed to allocate driver version param.\n"); 4099 return QLA_MEMORY_ALLOC_FAILED; 4100 } 4101 4102 memcpy(str, "\x7\x3\x11\x0", 4); 4103 dwlen = str[0]; 4104 len = dwlen * 4 - 4; 4105 memset(str + 4, 0, len); 4106 if (len > strlen(version)) 4107 len = strlen(version); 4108 memcpy(str + 4, version, len); 4109 4110 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4111 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4112 mcp->mb[2] = MSW(LSD(str_dma)); 4113 mcp->mb[3] = LSW(LSD(str_dma)); 4114 mcp->mb[6] = MSW(MSD(str_dma)); 4115 mcp->mb[7] = LSW(MSD(str_dma)); 4116 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4117 mcp->in_mb = MBX_1|MBX_0; 4118 mcp->tov = MBX_TOV_SECONDS; 4119 mcp->flags = 0; 4120 rval = qla2x00_mailbox_command(vha, mcp); 4121 4122 if (rval != QLA_SUCCESS) { 4123 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4124 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4125 } else { 4126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4127 "Done %s.\n", __func__); 4128 } 4129 4130 dma_pool_free(ha->s_dma_pool, str, str_dma); 4131 4132 return rval; 4133 } 4134 4135 static int 4136 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4137 { 4138 int rval; 4139 mbx_cmd_t mc; 4140 mbx_cmd_t *mcp = &mc; 4141 4142 if (!IS_FWI2_CAPABLE(vha->hw)) 4143 return QLA_FUNCTION_FAILED; 4144 4145 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4146 "Entered %s.\n", __func__); 4147 4148 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4149 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4150 mcp->out_mb = MBX_1|MBX_0; 4151 mcp->in_mb = MBX_1|MBX_0; 4152 mcp->tov = MBX_TOV_SECONDS; 4153 mcp->flags = 0; 4154 rval = qla2x00_mailbox_command(vha, mcp); 4155 *temp = mcp->mb[1]; 4156 4157 if (rval != QLA_SUCCESS) { 4158 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4159 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4160 } else { 4161 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4162 "Done %s.\n", __func__); 4163 } 4164 4165 return rval; 4166 } 4167 4168 int 4169 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4170 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4171 { 4172 int rval; 4173 mbx_cmd_t mc; 4174 mbx_cmd_t *mcp = &mc; 4175 struct qla_hw_data *ha = vha->hw; 4176 4177 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4178 "Entered %s.\n", __func__); 4179 4180 if (!IS_FWI2_CAPABLE(ha)) 4181 return QLA_FUNCTION_FAILED; 4182 4183 if (len == 1) 4184 opt |= BIT_0; 4185 4186 mcp->mb[0] = MBC_READ_SFP; 4187 mcp->mb[1] = dev; 4188 mcp->mb[2] = MSW(sfp_dma); 4189 mcp->mb[3] = LSW(sfp_dma); 4190 mcp->mb[6] = MSW(MSD(sfp_dma)); 4191 mcp->mb[7] = LSW(MSD(sfp_dma)); 4192 mcp->mb[8] = len; 4193 mcp->mb[9] = off; 4194 mcp->mb[10] = opt; 4195 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4196 mcp->in_mb = MBX_1|MBX_0; 4197 mcp->tov = MBX_TOV_SECONDS; 4198 mcp->flags = 0; 4199 rval = qla2x00_mailbox_command(vha, mcp); 4200 4201 if (opt & BIT_0) 4202 *sfp = mcp->mb[1]; 4203 4204 if (rval != QLA_SUCCESS) { 4205 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4206 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4207 } else { 4208 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4209 "Done %s.\n", __func__); 4210 } 4211 4212 return rval; 4213 } 4214 4215 int 4216 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4217 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4218 { 4219 int rval; 4220 mbx_cmd_t mc; 4221 mbx_cmd_t *mcp = &mc; 4222 struct qla_hw_data *ha = vha->hw; 4223 4224 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4225 "Entered %s.\n", __func__); 4226 4227 if (!IS_FWI2_CAPABLE(ha)) 4228 return QLA_FUNCTION_FAILED; 4229 4230 if (len == 1) 4231 opt |= BIT_0; 4232 4233 if (opt & BIT_0) 4234 len = *sfp; 4235 4236 mcp->mb[0] = MBC_WRITE_SFP; 4237 mcp->mb[1] = dev; 4238 mcp->mb[2] = MSW(sfp_dma); 4239 mcp->mb[3] = LSW(sfp_dma); 4240 mcp->mb[6] = MSW(MSD(sfp_dma)); 4241 mcp->mb[7] = LSW(MSD(sfp_dma)); 4242 mcp->mb[8] = len; 4243 mcp->mb[9] = off; 4244 mcp->mb[10] = opt; 4245 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4246 mcp->in_mb = MBX_1|MBX_0; 4247 mcp->tov = MBX_TOV_SECONDS; 4248 mcp->flags = 0; 4249 rval = qla2x00_mailbox_command(vha, mcp); 4250 4251 if (rval != QLA_SUCCESS) { 4252 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4253 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4254 } else { 4255 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4256 "Done %s.\n", __func__); 4257 } 4258 4259 return rval; 4260 } 4261 4262 int 4263 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4264 uint16_t size_in_bytes, uint16_t *actual_size) 4265 { 4266 int rval; 4267 mbx_cmd_t mc; 4268 mbx_cmd_t *mcp = &mc; 4269 4270 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4271 "Entered %s.\n", __func__); 4272 4273 if (!IS_CNA_CAPABLE(vha->hw)) 4274 return QLA_FUNCTION_FAILED; 4275 4276 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4277 mcp->mb[2] = MSW(stats_dma); 4278 mcp->mb[3] = LSW(stats_dma); 4279 mcp->mb[6] = MSW(MSD(stats_dma)); 4280 mcp->mb[7] = LSW(MSD(stats_dma)); 4281 mcp->mb[8] = size_in_bytes >> 2; 4282 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4283 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4284 mcp->tov = MBX_TOV_SECONDS; 4285 mcp->flags = 0; 4286 rval = qla2x00_mailbox_command(vha, mcp); 4287 4288 if (rval != QLA_SUCCESS) { 4289 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4290 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4291 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4292 } else { 4293 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4294 "Done %s.\n", __func__); 4295 4296 4297 *actual_size = mcp->mb[2] << 2; 4298 } 4299 4300 return rval; 4301 } 4302 4303 int 4304 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4305 uint16_t size) 4306 { 4307 int rval; 4308 mbx_cmd_t mc; 4309 mbx_cmd_t *mcp = &mc; 4310 4311 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4312 "Entered %s.\n", __func__); 4313 4314 if (!IS_CNA_CAPABLE(vha->hw)) 4315 return QLA_FUNCTION_FAILED; 4316 4317 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4318 mcp->mb[1] = 0; 4319 mcp->mb[2] = MSW(tlv_dma); 4320 mcp->mb[3] = LSW(tlv_dma); 4321 mcp->mb[6] = MSW(MSD(tlv_dma)); 4322 mcp->mb[7] = LSW(MSD(tlv_dma)); 4323 mcp->mb[8] = size; 4324 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4325 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4326 mcp->tov = MBX_TOV_SECONDS; 4327 mcp->flags = 0; 4328 rval = qla2x00_mailbox_command(vha, mcp); 4329 4330 if (rval != QLA_SUCCESS) { 4331 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4332 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4333 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4334 } else { 4335 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4336 "Done %s.\n", __func__); 4337 } 4338 4339 return rval; 4340 } 4341 4342 int 4343 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4344 { 4345 int rval; 4346 mbx_cmd_t mc; 4347 mbx_cmd_t *mcp = &mc; 4348 4349 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4350 "Entered %s.\n", __func__); 4351 4352 if (!IS_FWI2_CAPABLE(vha->hw)) 4353 return QLA_FUNCTION_FAILED; 4354 4355 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4356 mcp->mb[1] = LSW(risc_addr); 4357 mcp->mb[8] = MSW(risc_addr); 4358 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4359 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4360 mcp->tov = 30; 4361 mcp->flags = 0; 4362 rval = qla2x00_mailbox_command(vha, mcp); 4363 if (rval != QLA_SUCCESS) { 4364 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4365 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4366 } else { 4367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4368 "Done %s.\n", __func__); 4369 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4370 } 4371 4372 return rval; 4373 } 4374 4375 int 4376 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4377 uint16_t *mresp) 4378 { 4379 int rval; 4380 mbx_cmd_t mc; 4381 mbx_cmd_t *mcp = &mc; 4382 4383 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4384 "Entered %s.\n", __func__); 4385 4386 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4387 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4388 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4389 4390 /* transfer count */ 4391 mcp->mb[10] = LSW(mreq->transfer_size); 4392 mcp->mb[11] = MSW(mreq->transfer_size); 4393 4394 /* send data address */ 4395 mcp->mb[14] = LSW(mreq->send_dma); 4396 mcp->mb[15] = MSW(mreq->send_dma); 4397 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4398 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4399 4400 /* receive data address */ 4401 mcp->mb[16] = LSW(mreq->rcv_dma); 4402 mcp->mb[17] = MSW(mreq->rcv_dma); 4403 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4404 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4405 4406 /* Iteration count */ 4407 mcp->mb[18] = LSW(mreq->iteration_count); 4408 mcp->mb[19] = MSW(mreq->iteration_count); 4409 4410 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4411 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4412 if (IS_CNA_CAPABLE(vha->hw)) 4413 mcp->out_mb |= MBX_2; 4414 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4415 4416 mcp->buf_size = mreq->transfer_size; 4417 mcp->tov = MBX_TOV_SECONDS; 4418 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4419 4420 rval = qla2x00_mailbox_command(vha, mcp); 4421 4422 if (rval != QLA_SUCCESS) { 4423 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4424 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4425 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4426 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4427 } else { 4428 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4429 "Done %s.\n", __func__); 4430 } 4431 4432 /* Copy mailbox information */ 4433 memcpy( mresp, mcp->mb, 64); 4434 return rval; 4435 } 4436 4437 int 4438 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4439 uint16_t *mresp) 4440 { 4441 int rval; 4442 mbx_cmd_t mc; 4443 mbx_cmd_t *mcp = &mc; 4444 struct qla_hw_data *ha = vha->hw; 4445 4446 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4447 "Entered %s.\n", __func__); 4448 4449 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4450 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4451 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4452 if (IS_CNA_CAPABLE(ha)) { 4453 mcp->mb[1] |= BIT_15; 4454 mcp->mb[2] = vha->fcoe_fcf_idx; 4455 } 4456 mcp->mb[16] = LSW(mreq->rcv_dma); 4457 mcp->mb[17] = MSW(mreq->rcv_dma); 4458 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4459 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4460 4461 mcp->mb[10] = LSW(mreq->transfer_size); 4462 4463 mcp->mb[14] = LSW(mreq->send_dma); 4464 mcp->mb[15] = MSW(mreq->send_dma); 4465 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4466 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4467 4468 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4469 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4470 if (IS_CNA_CAPABLE(ha)) 4471 mcp->out_mb |= MBX_2; 4472 4473 mcp->in_mb = MBX_0; 4474 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4475 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4476 mcp->in_mb |= MBX_1; 4477 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4478 mcp->in_mb |= MBX_3; 4479 4480 mcp->tov = MBX_TOV_SECONDS; 4481 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4482 mcp->buf_size = mreq->transfer_size; 4483 4484 rval = qla2x00_mailbox_command(vha, mcp); 4485 4486 if (rval != QLA_SUCCESS) { 4487 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4488 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4489 rval, mcp->mb[0], mcp->mb[1]); 4490 } else { 4491 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4492 "Done %s.\n", __func__); 4493 } 4494 4495 /* Copy mailbox information */ 4496 memcpy(mresp, mcp->mb, 64); 4497 return rval; 4498 } 4499 4500 int 4501 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4502 { 4503 int rval; 4504 mbx_cmd_t mc; 4505 mbx_cmd_t *mcp = &mc; 4506 4507 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4508 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4509 4510 mcp->mb[0] = MBC_ISP84XX_RESET; 4511 mcp->mb[1] = enable_diagnostic; 4512 mcp->out_mb = MBX_1|MBX_0; 4513 mcp->in_mb = MBX_1|MBX_0; 4514 mcp->tov = MBX_TOV_SECONDS; 4515 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4516 rval = qla2x00_mailbox_command(vha, mcp); 4517 4518 if (rval != QLA_SUCCESS) 4519 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4520 else 4521 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4522 "Done %s.\n", __func__); 4523 4524 return rval; 4525 } 4526 4527 int 4528 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4529 { 4530 int rval; 4531 mbx_cmd_t mc; 4532 mbx_cmd_t *mcp = &mc; 4533 4534 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4535 "Entered %s.\n", __func__); 4536 4537 if (!IS_FWI2_CAPABLE(vha->hw)) 4538 return QLA_FUNCTION_FAILED; 4539 4540 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4541 mcp->mb[1] = LSW(risc_addr); 4542 mcp->mb[2] = LSW(data); 4543 mcp->mb[3] = MSW(data); 4544 mcp->mb[8] = MSW(risc_addr); 4545 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4546 mcp->in_mb = MBX_0; 4547 mcp->tov = 30; 4548 mcp->flags = 0; 4549 rval = qla2x00_mailbox_command(vha, mcp); 4550 if (rval != QLA_SUCCESS) { 4551 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4552 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4553 } else { 4554 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4555 "Done %s.\n", __func__); 4556 } 4557 4558 return rval; 4559 } 4560 4561 int 4562 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4563 { 4564 int rval; 4565 uint32_t stat, timer; 4566 uint16_t mb0 = 0; 4567 struct qla_hw_data *ha = vha->hw; 4568 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4569 4570 rval = QLA_SUCCESS; 4571 4572 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4573 "Entered %s.\n", __func__); 4574 4575 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4576 4577 /* Write the MBC data to the registers */ 4578 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4579 WRT_REG_WORD(®->mailbox1, mb[0]); 4580 WRT_REG_WORD(®->mailbox2, mb[1]); 4581 WRT_REG_WORD(®->mailbox3, mb[2]); 4582 WRT_REG_WORD(®->mailbox4, mb[3]); 4583 4584 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4585 4586 /* Poll for MBC interrupt */ 4587 for (timer = 6000000; timer; timer--) { 4588 /* Check for pending interrupts. */ 4589 stat = RD_REG_DWORD(®->host_status); 4590 if (stat & HSRX_RISC_INT) { 4591 stat &= 0xff; 4592 4593 if (stat == 0x1 || stat == 0x2 || 4594 stat == 0x10 || stat == 0x11) { 4595 set_bit(MBX_INTERRUPT, 4596 &ha->mbx_cmd_flags); 4597 mb0 = RD_REG_WORD(®->mailbox0); 4598 WRT_REG_DWORD(®->hccr, 4599 HCCRX_CLR_RISC_INT); 4600 RD_REG_DWORD(®->hccr); 4601 break; 4602 } 4603 } 4604 udelay(5); 4605 } 4606 4607 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4608 rval = mb0 & MBS_MASK; 4609 else 4610 rval = QLA_FUNCTION_FAILED; 4611 4612 if (rval != QLA_SUCCESS) { 4613 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4614 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4615 } else { 4616 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 4617 "Done %s.\n", __func__); 4618 } 4619 4620 return rval; 4621 } 4622 4623 int 4624 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4625 { 4626 int rval; 4627 mbx_cmd_t mc; 4628 mbx_cmd_t *mcp = &mc; 4629 struct qla_hw_data *ha = vha->hw; 4630 4631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 4632 "Entered %s.\n", __func__); 4633 4634 if (!IS_FWI2_CAPABLE(ha)) 4635 return QLA_FUNCTION_FAILED; 4636 4637 mcp->mb[0] = MBC_DATA_RATE; 4638 mcp->mb[1] = 0; 4639 mcp->out_mb = MBX_1|MBX_0; 4640 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4641 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4642 mcp->in_mb |= MBX_3; 4643 mcp->tov = MBX_TOV_SECONDS; 4644 mcp->flags = 0; 4645 rval = qla2x00_mailbox_command(vha, mcp); 4646 if (rval != QLA_SUCCESS) { 4647 ql_dbg(ql_dbg_mbx, vha, 0x1107, 4648 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4649 } else { 4650 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 4651 "Done %s.\n", __func__); 4652 if (mcp->mb[1] != 0x7) 4653 ha->link_data_rate = mcp->mb[1]; 4654 } 4655 4656 return rval; 4657 } 4658 4659 int 4660 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4661 { 4662 int rval; 4663 mbx_cmd_t mc; 4664 mbx_cmd_t *mcp = &mc; 4665 struct qla_hw_data *ha = vha->hw; 4666 4667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 4668 "Entered %s.\n", __func__); 4669 4670 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 4671 !IS_QLA27XX(ha)) 4672 return QLA_FUNCTION_FAILED; 4673 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4674 mcp->out_mb = MBX_0; 4675 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4676 mcp->tov = MBX_TOV_SECONDS; 4677 mcp->flags = 0; 4678 4679 rval = qla2x00_mailbox_command(vha, mcp); 4680 4681 if (rval != QLA_SUCCESS) { 4682 ql_dbg(ql_dbg_mbx, vha, 0x110a, 4683 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4684 } else { 4685 /* Copy all bits to preserve original value */ 4686 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 4687 4688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 4689 "Done %s.\n", __func__); 4690 } 4691 return rval; 4692 } 4693 4694 int 4695 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4696 { 4697 int rval; 4698 mbx_cmd_t mc; 4699 mbx_cmd_t *mcp = &mc; 4700 4701 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 4702 "Entered %s.\n", __func__); 4703 4704 mcp->mb[0] = MBC_SET_PORT_CONFIG; 4705 /* Copy all bits to preserve original setting */ 4706 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 4707 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4708 mcp->in_mb = MBX_0; 4709 mcp->tov = MBX_TOV_SECONDS; 4710 mcp->flags = 0; 4711 rval = qla2x00_mailbox_command(vha, mcp); 4712 4713 if (rval != QLA_SUCCESS) { 4714 ql_dbg(ql_dbg_mbx, vha, 0x110d, 4715 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4716 } else 4717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 4718 "Done %s.\n", __func__); 4719 4720 return rval; 4721 } 4722 4723 4724 int 4725 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 4726 uint16_t *mb) 4727 { 4728 int rval; 4729 mbx_cmd_t mc; 4730 mbx_cmd_t *mcp = &mc; 4731 struct qla_hw_data *ha = vha->hw; 4732 4733 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 4734 "Entered %s.\n", __func__); 4735 4736 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 4737 return QLA_FUNCTION_FAILED; 4738 4739 mcp->mb[0] = MBC_PORT_PARAMS; 4740 mcp->mb[1] = loop_id; 4741 if (ha->flags.fcp_prio_enabled) 4742 mcp->mb[2] = BIT_1; 4743 else 4744 mcp->mb[2] = BIT_2; 4745 mcp->mb[4] = priority & 0xf; 4746 mcp->mb[9] = vha->vp_idx; 4747 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4748 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 4749 mcp->tov = 30; 4750 mcp->flags = 0; 4751 rval = qla2x00_mailbox_command(vha, mcp); 4752 if (mb != NULL) { 4753 mb[0] = mcp->mb[0]; 4754 mb[1] = mcp->mb[1]; 4755 mb[3] = mcp->mb[3]; 4756 mb[4] = mcp->mb[4]; 4757 } 4758 4759 if (rval != QLA_SUCCESS) { 4760 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 4761 } else { 4762 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 4763 "Done %s.\n", __func__); 4764 } 4765 4766 return rval; 4767 } 4768 4769 int 4770 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 4771 { 4772 int rval = QLA_FUNCTION_FAILED; 4773 struct qla_hw_data *ha = vha->hw; 4774 uint8_t byte; 4775 4776 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 4777 ql_dbg(ql_dbg_mbx, vha, 0x1150, 4778 "Thermal not supported by this card.\n"); 4779 return rval; 4780 } 4781 4782 if (IS_QLA25XX(ha)) { 4783 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4784 ha->pdev->subsystem_device == 0x0175) { 4785 rval = qla2x00_read_sfp(vha, 0, &byte, 4786 0x98, 0x1, 1, BIT_13|BIT_0); 4787 *temp = byte; 4788 return rval; 4789 } 4790 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 4791 ha->pdev->subsystem_device == 0x338e) { 4792 rval = qla2x00_read_sfp(vha, 0, &byte, 4793 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 4794 *temp = byte; 4795 return rval; 4796 } 4797 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 4798 "Thermal not supported by this card.\n"); 4799 return rval; 4800 } 4801 4802 if (IS_QLA82XX(ha)) { 4803 *temp = qla82xx_read_temperature(vha); 4804 rval = QLA_SUCCESS; 4805 return rval; 4806 } else if (IS_QLA8044(ha)) { 4807 *temp = qla8044_read_temperature(vha); 4808 rval = QLA_SUCCESS; 4809 return rval; 4810 } 4811 4812 rval = qla2x00_read_asic_temperature(vha, temp); 4813 return rval; 4814 } 4815 4816 int 4817 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 4818 { 4819 int rval; 4820 struct qla_hw_data *ha = vha->hw; 4821 mbx_cmd_t mc; 4822 mbx_cmd_t *mcp = &mc; 4823 4824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 4825 "Entered %s.\n", __func__); 4826 4827 if (!IS_FWI2_CAPABLE(ha)) 4828 return QLA_FUNCTION_FAILED; 4829 4830 memset(mcp, 0, sizeof(mbx_cmd_t)); 4831 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4832 mcp->mb[1] = 1; 4833 4834 mcp->out_mb = MBX_1|MBX_0; 4835 mcp->in_mb = MBX_0; 4836 mcp->tov = 30; 4837 mcp->flags = 0; 4838 4839 rval = qla2x00_mailbox_command(vha, mcp); 4840 if (rval != QLA_SUCCESS) { 4841 ql_dbg(ql_dbg_mbx, vha, 0x1016, 4842 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4843 } else { 4844 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 4845 "Done %s.\n", __func__); 4846 } 4847 4848 return rval; 4849 } 4850 4851 int 4852 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 4853 { 4854 int rval; 4855 struct qla_hw_data *ha = vha->hw; 4856 mbx_cmd_t mc; 4857 mbx_cmd_t *mcp = &mc; 4858 4859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 4860 "Entered %s.\n", __func__); 4861 4862 if (!IS_P3P_TYPE(ha)) 4863 return QLA_FUNCTION_FAILED; 4864 4865 memset(mcp, 0, sizeof(mbx_cmd_t)); 4866 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4867 mcp->mb[1] = 0; 4868 4869 mcp->out_mb = MBX_1|MBX_0; 4870 mcp->in_mb = MBX_0; 4871 mcp->tov = 30; 4872 mcp->flags = 0; 4873 4874 rval = qla2x00_mailbox_command(vha, mcp); 4875 if (rval != QLA_SUCCESS) { 4876 ql_dbg(ql_dbg_mbx, vha, 0x100c, 4877 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4878 } else { 4879 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 4880 "Done %s.\n", __func__); 4881 } 4882 4883 return rval; 4884 } 4885 4886 int 4887 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 4888 { 4889 struct qla_hw_data *ha = vha->hw; 4890 mbx_cmd_t mc; 4891 mbx_cmd_t *mcp = &mc; 4892 int rval = QLA_FUNCTION_FAILED; 4893 4894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 4895 "Entered %s.\n", __func__); 4896 4897 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4898 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4899 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4900 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 4901 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 4902 4903 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4904 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 4905 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4906 4907 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4908 mcp->tov = MBX_TOV_SECONDS; 4909 rval = qla2x00_mailbox_command(vha, mcp); 4910 4911 /* Always copy back return mailbox values. */ 4912 if (rval != QLA_SUCCESS) { 4913 ql_dbg(ql_dbg_mbx, vha, 0x1120, 4914 "mailbox command FAILED=0x%x, subcode=%x.\n", 4915 (mcp->mb[1] << 16) | mcp->mb[0], 4916 (mcp->mb[3] << 16) | mcp->mb[2]); 4917 } else { 4918 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 4919 "Done %s.\n", __func__); 4920 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 4921 if (!ha->md_template_size) { 4922 ql_dbg(ql_dbg_mbx, vha, 0x1122, 4923 "Null template size obtained.\n"); 4924 rval = QLA_FUNCTION_FAILED; 4925 } 4926 } 4927 return rval; 4928 } 4929 4930 int 4931 qla82xx_md_get_template(scsi_qla_host_t *vha) 4932 { 4933 struct qla_hw_data *ha = vha->hw; 4934 mbx_cmd_t mc; 4935 mbx_cmd_t *mcp = &mc; 4936 int rval = QLA_FUNCTION_FAILED; 4937 4938 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 4939 "Entered %s.\n", __func__); 4940 4941 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 4942 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 4943 if (!ha->md_tmplt_hdr) { 4944 ql_log(ql_log_warn, vha, 0x1124, 4945 "Unable to allocate memory for Minidump template.\n"); 4946 return rval; 4947 } 4948 4949 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4950 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4951 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4952 mcp->mb[2] = LSW(RQST_TMPLT); 4953 mcp->mb[3] = MSW(RQST_TMPLT); 4954 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 4955 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 4956 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 4957 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 4958 mcp->mb[8] = LSW(ha->md_template_size); 4959 mcp->mb[9] = MSW(ha->md_template_size); 4960 4961 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4962 mcp->tov = MBX_TOV_SECONDS; 4963 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 4964 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4965 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4966 rval = qla2x00_mailbox_command(vha, mcp); 4967 4968 if (rval != QLA_SUCCESS) { 4969 ql_dbg(ql_dbg_mbx, vha, 0x1125, 4970 "mailbox command FAILED=0x%x, subcode=%x.\n", 4971 ((mcp->mb[1] << 16) | mcp->mb[0]), 4972 ((mcp->mb[3] << 16) | mcp->mb[2])); 4973 } else 4974 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 4975 "Done %s.\n", __func__); 4976 return rval; 4977 } 4978 4979 int 4980 qla8044_md_get_template(scsi_qla_host_t *vha) 4981 { 4982 struct qla_hw_data *ha = vha->hw; 4983 mbx_cmd_t mc; 4984 mbx_cmd_t *mcp = &mc; 4985 int rval = QLA_FUNCTION_FAILED; 4986 int offset = 0, size = MINIDUMP_SIZE_36K; 4987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 4988 "Entered %s.\n", __func__); 4989 4990 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 4991 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 4992 if (!ha->md_tmplt_hdr) { 4993 ql_log(ql_log_warn, vha, 0xb11b, 4994 "Unable to allocate memory for Minidump template.\n"); 4995 return rval; 4996 } 4997 4998 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4999 while (offset < ha->md_template_size) { 5000 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5001 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5002 mcp->mb[2] = LSW(RQST_TMPLT); 5003 mcp->mb[3] = MSW(RQST_TMPLT); 5004 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5005 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5006 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5007 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5008 mcp->mb[8] = LSW(size); 5009 mcp->mb[9] = MSW(size); 5010 mcp->mb[10] = offset & 0x0000FFFF; 5011 mcp->mb[11] = offset & 0xFFFF0000; 5012 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5013 mcp->tov = MBX_TOV_SECONDS; 5014 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5015 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5016 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5017 rval = qla2x00_mailbox_command(vha, mcp); 5018 5019 if (rval != QLA_SUCCESS) { 5020 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5021 "mailbox command FAILED=0x%x, subcode=%x.\n", 5022 ((mcp->mb[1] << 16) | mcp->mb[0]), 5023 ((mcp->mb[3] << 16) | mcp->mb[2])); 5024 return rval; 5025 } else 5026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5027 "Done %s.\n", __func__); 5028 offset = offset + size; 5029 } 5030 return rval; 5031 } 5032 5033 int 5034 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5035 { 5036 int rval; 5037 struct qla_hw_data *ha = vha->hw; 5038 mbx_cmd_t mc; 5039 mbx_cmd_t *mcp = &mc; 5040 5041 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5042 return QLA_FUNCTION_FAILED; 5043 5044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5045 "Entered %s.\n", __func__); 5046 5047 memset(mcp, 0, sizeof(mbx_cmd_t)); 5048 mcp->mb[0] = MBC_SET_LED_CONFIG; 5049 mcp->mb[1] = led_cfg[0]; 5050 mcp->mb[2] = led_cfg[1]; 5051 if (IS_QLA8031(ha)) { 5052 mcp->mb[3] = led_cfg[2]; 5053 mcp->mb[4] = led_cfg[3]; 5054 mcp->mb[5] = led_cfg[4]; 5055 mcp->mb[6] = led_cfg[5]; 5056 } 5057 5058 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5059 if (IS_QLA8031(ha)) 5060 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5061 mcp->in_mb = MBX_0; 5062 mcp->tov = 30; 5063 mcp->flags = 0; 5064 5065 rval = qla2x00_mailbox_command(vha, mcp); 5066 if (rval != QLA_SUCCESS) { 5067 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5068 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5069 } else { 5070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5071 "Done %s.\n", __func__); 5072 } 5073 5074 return rval; 5075 } 5076 5077 int 5078 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5079 { 5080 int rval; 5081 struct qla_hw_data *ha = vha->hw; 5082 mbx_cmd_t mc; 5083 mbx_cmd_t *mcp = &mc; 5084 5085 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5086 return QLA_FUNCTION_FAILED; 5087 5088 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5089 "Entered %s.\n", __func__); 5090 5091 memset(mcp, 0, sizeof(mbx_cmd_t)); 5092 mcp->mb[0] = MBC_GET_LED_CONFIG; 5093 5094 mcp->out_mb = MBX_0; 5095 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5096 if (IS_QLA8031(ha)) 5097 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5098 mcp->tov = 30; 5099 mcp->flags = 0; 5100 5101 rval = qla2x00_mailbox_command(vha, mcp); 5102 if (rval != QLA_SUCCESS) { 5103 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5104 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5105 } else { 5106 led_cfg[0] = mcp->mb[1]; 5107 led_cfg[1] = mcp->mb[2]; 5108 if (IS_QLA8031(ha)) { 5109 led_cfg[2] = mcp->mb[3]; 5110 led_cfg[3] = mcp->mb[4]; 5111 led_cfg[4] = mcp->mb[5]; 5112 led_cfg[5] = mcp->mb[6]; 5113 } 5114 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5115 "Done %s.\n", __func__); 5116 } 5117 5118 return rval; 5119 } 5120 5121 int 5122 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5123 { 5124 int rval; 5125 struct qla_hw_data *ha = vha->hw; 5126 mbx_cmd_t mc; 5127 mbx_cmd_t *mcp = &mc; 5128 5129 if (!IS_P3P_TYPE(ha)) 5130 return QLA_FUNCTION_FAILED; 5131 5132 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5133 "Entered %s.\n", __func__); 5134 5135 memset(mcp, 0, sizeof(mbx_cmd_t)); 5136 mcp->mb[0] = MBC_SET_LED_CONFIG; 5137 if (enable) 5138 mcp->mb[7] = 0xE; 5139 else 5140 mcp->mb[7] = 0xD; 5141 5142 mcp->out_mb = MBX_7|MBX_0; 5143 mcp->in_mb = MBX_0; 5144 mcp->tov = MBX_TOV_SECONDS; 5145 mcp->flags = 0; 5146 5147 rval = qla2x00_mailbox_command(vha, mcp); 5148 if (rval != QLA_SUCCESS) { 5149 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5150 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5151 } else { 5152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5153 "Done %s.\n", __func__); 5154 } 5155 5156 return rval; 5157 } 5158 5159 int 5160 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5161 { 5162 int rval; 5163 struct qla_hw_data *ha = vha->hw; 5164 mbx_cmd_t mc; 5165 mbx_cmd_t *mcp = &mc; 5166 5167 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5168 return QLA_FUNCTION_FAILED; 5169 5170 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5171 "Entered %s.\n", __func__); 5172 5173 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5174 mcp->mb[1] = LSW(reg); 5175 mcp->mb[2] = MSW(reg); 5176 mcp->mb[3] = LSW(data); 5177 mcp->mb[4] = MSW(data); 5178 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5179 5180 mcp->in_mb = MBX_1|MBX_0; 5181 mcp->tov = MBX_TOV_SECONDS; 5182 mcp->flags = 0; 5183 rval = qla2x00_mailbox_command(vha, mcp); 5184 5185 if (rval != QLA_SUCCESS) { 5186 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5187 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5188 } else { 5189 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5190 "Done %s.\n", __func__); 5191 } 5192 5193 return rval; 5194 } 5195 5196 int 5197 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5198 { 5199 int rval; 5200 struct qla_hw_data *ha = vha->hw; 5201 mbx_cmd_t mc; 5202 mbx_cmd_t *mcp = &mc; 5203 5204 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5205 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5206 "Implicit LOGO Unsupported.\n"); 5207 return QLA_FUNCTION_FAILED; 5208 } 5209 5210 5211 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5212 "Entering %s.\n", __func__); 5213 5214 /* Perform Implicit LOGO. */ 5215 mcp->mb[0] = MBC_PORT_LOGOUT; 5216 mcp->mb[1] = fcport->loop_id; 5217 mcp->mb[10] = BIT_15; 5218 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5219 mcp->in_mb = MBX_0; 5220 mcp->tov = MBX_TOV_SECONDS; 5221 mcp->flags = 0; 5222 rval = qla2x00_mailbox_command(vha, mcp); 5223 if (rval != QLA_SUCCESS) 5224 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5225 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5226 else 5227 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5228 "Done %s.\n", __func__); 5229 5230 return rval; 5231 } 5232 5233 int 5234 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5235 { 5236 int rval; 5237 mbx_cmd_t mc; 5238 mbx_cmd_t *mcp = &mc; 5239 struct qla_hw_data *ha = vha->hw; 5240 unsigned long retry_max_time = jiffies + (2 * HZ); 5241 5242 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5243 return QLA_FUNCTION_FAILED; 5244 5245 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5246 5247 retry_rd_reg: 5248 mcp->mb[0] = MBC_READ_REMOTE_REG; 5249 mcp->mb[1] = LSW(reg); 5250 mcp->mb[2] = MSW(reg); 5251 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5252 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5253 mcp->tov = MBX_TOV_SECONDS; 5254 mcp->flags = 0; 5255 rval = qla2x00_mailbox_command(vha, mcp); 5256 5257 if (rval != QLA_SUCCESS) { 5258 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5259 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5260 rval, mcp->mb[0], mcp->mb[1]); 5261 } else { 5262 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5263 if (*data == QLA8XXX_BAD_VALUE) { 5264 /* 5265 * During soft-reset CAMRAM register reads might 5266 * return 0xbad0bad0. So retry for MAX of 2 sec 5267 * while reading camram registers. 5268 */ 5269 if (time_after(jiffies, retry_max_time)) { 5270 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5271 "Failure to read CAMRAM register. " 5272 "data=0x%x.\n", *data); 5273 return QLA_FUNCTION_FAILED; 5274 } 5275 msleep(100); 5276 goto retry_rd_reg; 5277 } 5278 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5279 } 5280 5281 return rval; 5282 } 5283 5284 int 5285 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5286 { 5287 int rval; 5288 mbx_cmd_t mc; 5289 mbx_cmd_t *mcp = &mc; 5290 struct qla_hw_data *ha = vha->hw; 5291 5292 if (!IS_QLA83XX(ha)) 5293 return QLA_FUNCTION_FAILED; 5294 5295 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5296 5297 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5298 mcp->out_mb = MBX_0; 5299 mcp->in_mb = MBX_1|MBX_0; 5300 mcp->tov = MBX_TOV_SECONDS; 5301 mcp->flags = 0; 5302 rval = qla2x00_mailbox_command(vha, mcp); 5303 5304 if (rval != QLA_SUCCESS) { 5305 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5306 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5307 rval, mcp->mb[0], mcp->mb[1]); 5308 ha->isp_ops->fw_dump(vha, 0); 5309 } else { 5310 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5311 } 5312 5313 return rval; 5314 } 5315 5316 int 5317 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5318 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5319 { 5320 int rval; 5321 mbx_cmd_t mc; 5322 mbx_cmd_t *mcp = &mc; 5323 uint8_t subcode = (uint8_t)options; 5324 struct qla_hw_data *ha = vha->hw; 5325 5326 if (!IS_QLA8031(ha)) 5327 return QLA_FUNCTION_FAILED; 5328 5329 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5330 5331 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5332 mcp->mb[1] = options; 5333 mcp->out_mb = MBX_1|MBX_0; 5334 if (subcode & BIT_2) { 5335 mcp->mb[2] = LSW(start_addr); 5336 mcp->mb[3] = MSW(start_addr); 5337 mcp->mb[4] = LSW(end_addr); 5338 mcp->mb[5] = MSW(end_addr); 5339 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5340 } 5341 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5342 if (!(subcode & (BIT_2 | BIT_5))) 5343 mcp->in_mb |= MBX_4|MBX_3; 5344 mcp->tov = MBX_TOV_SECONDS; 5345 mcp->flags = 0; 5346 rval = qla2x00_mailbox_command(vha, mcp); 5347 5348 if (rval != QLA_SUCCESS) { 5349 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5350 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5351 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5352 mcp->mb[4]); 5353 ha->isp_ops->fw_dump(vha, 0); 5354 } else { 5355 if (subcode & BIT_5) 5356 *sector_size = mcp->mb[1]; 5357 else if (subcode & (BIT_6 | BIT_7)) { 5358 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5359 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5360 } else if (subcode & (BIT_3 | BIT_4)) { 5361 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5362 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5363 } 5364 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5365 } 5366 5367 return rval; 5368 } 5369 5370 int 5371 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5372 uint32_t size) 5373 { 5374 int rval; 5375 mbx_cmd_t mc; 5376 mbx_cmd_t *mcp = &mc; 5377 5378 if (!IS_MCTP_CAPABLE(vha->hw)) 5379 return QLA_FUNCTION_FAILED; 5380 5381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5382 "Entered %s.\n", __func__); 5383 5384 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5385 mcp->mb[1] = LSW(addr); 5386 mcp->mb[2] = MSW(req_dma); 5387 mcp->mb[3] = LSW(req_dma); 5388 mcp->mb[4] = MSW(size); 5389 mcp->mb[5] = LSW(size); 5390 mcp->mb[6] = MSW(MSD(req_dma)); 5391 mcp->mb[7] = LSW(MSD(req_dma)); 5392 mcp->mb[8] = MSW(addr); 5393 /* Setting RAM ID to valid */ 5394 mcp->mb[10] |= BIT_7; 5395 /* For MCTP RAM ID is 0x40 */ 5396 mcp->mb[10] |= 0x40; 5397 5398 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5399 MBX_0; 5400 5401 mcp->in_mb = MBX_0; 5402 mcp->tov = MBX_TOV_SECONDS; 5403 mcp->flags = 0; 5404 rval = qla2x00_mailbox_command(vha, mcp); 5405 5406 if (rval != QLA_SUCCESS) { 5407 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5408 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5409 } else { 5410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5411 "Done %s.\n", __func__); 5412 } 5413 5414 return rval; 5415 } 5416