1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 static struct mb_cmd_name { 14 uint16_t cmd; 15 const char *str; 16 } mb_str[] = { 17 {MBC_GET_PORT_DATABASE, "GPDB"}, 18 {MBC_GET_ID_LIST, "GIDList"}, 19 {MBC_GET_LINK_PRIV_STATS, "Stats"}, 20 {MBC_GET_RESOURCE_COUNTS, "ResCnt"}, 21 }; 22 23 static const char *mb_to_str(uint16_t cmd) 24 { 25 int i; 26 struct mb_cmd_name *e; 27 28 for (i = 0; i < ARRAY_SIZE(mb_str); i++) { 29 e = mb_str + i; 30 if (cmd == e->cmd) 31 return e->str; 32 } 33 return "unknown"; 34 } 35 36 static struct rom_cmd { 37 uint16_t cmd; 38 } rom_cmds[] = { 39 { MBC_LOAD_RAM }, 40 { MBC_EXECUTE_FIRMWARE }, 41 { MBC_READ_RAM_WORD }, 42 { MBC_MAILBOX_REGISTER_TEST }, 43 { MBC_VERIFY_CHECKSUM }, 44 { MBC_GET_FIRMWARE_VERSION }, 45 { MBC_LOAD_RISC_RAM }, 46 { MBC_DUMP_RISC_RAM }, 47 { MBC_LOAD_RISC_RAM_EXTENDED }, 48 { MBC_DUMP_RISC_RAM_EXTENDED }, 49 { MBC_WRITE_RAM_WORD_EXTENDED }, 50 { MBC_READ_RAM_EXTENDED }, 51 { MBC_GET_RESOURCE_COUNTS }, 52 { MBC_SET_FIRMWARE_OPTION }, 53 { MBC_MID_INITIALIZE_FIRMWARE }, 54 { MBC_GET_FIRMWARE_STATE }, 55 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT }, 56 { MBC_GET_RETRY_COUNT }, 57 { MBC_TRACE_CONTROL }, 58 { MBC_INITIALIZE_MULTIQ }, 59 { MBC_IOCB_COMMAND_A64 }, 60 { MBC_GET_ADAPTER_LOOP_ID }, 61 { MBC_READ_SFP }, 62 }; 63 64 static int is_rom_cmd(uint16_t cmd) 65 { 66 int i; 67 struct rom_cmd *wc; 68 69 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) { 70 wc = rom_cmds + i; 71 if (wc->cmd == cmd) 72 return 1; 73 } 74 75 return 0; 76 } 77 78 /* 79 * qla2x00_mailbox_command 80 * Issue mailbox command and waits for completion. 81 * 82 * Input: 83 * ha = adapter block pointer. 84 * mcp = driver internal mbx struct pointer. 85 * 86 * Output: 87 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 88 * 89 * Returns: 90 * 0 : QLA_SUCCESS = cmd performed success 91 * 1 : QLA_FUNCTION_FAILED (error encountered) 92 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 93 * 94 * Context: 95 * Kernel context. 96 */ 97 static int 98 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 99 { 100 int rval, i; 101 unsigned long flags = 0; 102 device_reg_t *reg; 103 uint8_t abort_active; 104 uint8_t io_lock_on; 105 uint16_t command = 0; 106 uint16_t *iptr; 107 uint16_t __iomem *optr; 108 uint32_t cnt; 109 uint32_t mboxes; 110 unsigned long wait_time; 111 struct qla_hw_data *ha = vha->hw; 112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 113 114 115 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 116 117 if (ha->pdev->error_state > pci_channel_io_frozen) { 118 ql_log(ql_log_warn, vha, 0x1001, 119 "error_state is greater than pci_channel_io_frozen, " 120 "exiting.\n"); 121 return QLA_FUNCTION_TIMEOUT; 122 } 123 124 if (vha->device_flags & DFLG_DEV_FAILED) { 125 ql_log(ql_log_warn, vha, 0x1002, 126 "Device in failed state, exiting.\n"); 127 return QLA_FUNCTION_TIMEOUT; 128 } 129 130 /* if PCI error, then avoid mbx processing.*/ 131 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) && 132 test_bit(UNLOADING, &base_vha->dpc_flags)) { 133 ql_log(ql_log_warn, vha, 0xd04e, 134 "PCI error, exiting.\n"); 135 return QLA_FUNCTION_TIMEOUT; 136 } 137 138 reg = ha->iobase; 139 io_lock_on = base_vha->flags.init_done; 140 141 rval = QLA_SUCCESS; 142 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 143 144 145 if (ha->flags.pci_channel_io_perm_failure) { 146 ql_log(ql_log_warn, vha, 0x1003, 147 "Perm failure on EEH timeout MBX, exiting.\n"); 148 return QLA_FUNCTION_TIMEOUT; 149 } 150 151 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 152 /* Setting Link-Down error */ 153 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 154 ql_log(ql_log_warn, vha, 0x1004, 155 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 156 return QLA_FUNCTION_TIMEOUT; 157 } 158 159 /* check if ISP abort is active and return cmd with timeout */ 160 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 161 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 162 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) && 163 !is_rom_cmd(mcp->mb[0])) { 164 ql_log(ql_log_info, vha, 0x1005, 165 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n", 166 mcp->mb[0]); 167 return QLA_FUNCTION_TIMEOUT; 168 } 169 170 /* 171 * Wait for active mailbox commands to finish by waiting at most tov 172 * seconds. This is to serialize actual issuing of mailbox cmds during 173 * non ISP abort time. 174 */ 175 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 176 /* Timeout occurred. Return error. */ 177 ql_log(ql_log_warn, vha, 0xd035, 178 "Cmd access timeout, cmd=0x%x, Exiting.\n", 179 mcp->mb[0]); 180 return QLA_FUNCTION_TIMEOUT; 181 } 182 183 ha->flags.mbox_busy = 1; 184 /* Save mailbox command for debug */ 185 ha->mcp = mcp; 186 187 ql_dbg(ql_dbg_mbx, vha, 0x1006, 188 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 189 190 spin_lock_irqsave(&ha->hardware_lock, flags); 191 192 /* Load mailbox registers. */ 193 if (IS_P3P_TYPE(ha)) 194 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 195 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 196 optr = (uint16_t __iomem *)®->isp24.mailbox0; 197 else 198 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 199 200 iptr = mcp->mb; 201 command = mcp->mb[0]; 202 mboxes = mcp->out_mb; 203 204 ql_dbg(ql_dbg_mbx, vha, 0x1111, 205 "Mailbox registers (OUT):\n"); 206 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 207 if (IS_QLA2200(ha) && cnt == 8) 208 optr = 209 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 210 if (mboxes & BIT_0) { 211 ql_dbg(ql_dbg_mbx, vha, 0x1112, 212 "mbox[%d]<-0x%04x\n", cnt, *iptr); 213 WRT_REG_WORD(optr, *iptr); 214 } 215 216 mboxes >>= 1; 217 optr++; 218 iptr++; 219 } 220 221 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 222 "I/O Address = %p.\n", optr); 223 224 /* Issue set host interrupt command to send cmd out. */ 225 ha->flags.mbox_int = 0; 226 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 227 228 /* Unlock mbx registers and wait for interrupt */ 229 ql_dbg(ql_dbg_mbx, vha, 0x100f, 230 "Going to unlock irq & waiting for interrupts. " 231 "jiffies=%lx.\n", jiffies); 232 233 /* Wait for mbx cmd completion until timeout */ 234 235 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 236 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 237 238 if (IS_P3P_TYPE(ha)) { 239 if (RD_REG_DWORD(®->isp82.hint) & 240 HINT_MBX_INT_PENDING) { 241 spin_unlock_irqrestore(&ha->hardware_lock, 242 flags); 243 ha->flags.mbox_busy = 0; 244 ql_dbg(ql_dbg_mbx, vha, 0x1010, 245 "Pending mailbox timeout, exiting.\n"); 246 rval = QLA_FUNCTION_TIMEOUT; 247 goto premature_exit; 248 } 249 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 250 } else if (IS_FWI2_CAPABLE(ha)) 251 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 252 else 253 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 254 spin_unlock_irqrestore(&ha->hardware_lock, flags); 255 256 wait_time = jiffies; 257 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 258 mcp->tov * HZ)) { 259 ql_dbg(ql_dbg_mbx, vha, 0x117a, 260 "cmd=%x Timeout.\n", command); 261 spin_lock_irqsave(&ha->hardware_lock, flags); 262 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 263 spin_unlock_irqrestore(&ha->hardware_lock, flags); 264 } 265 if (time_after(jiffies, wait_time + 5 * HZ)) 266 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n", 267 command, jiffies_to_msecs(jiffies - wait_time)); 268 } else { 269 ql_dbg(ql_dbg_mbx, vha, 0x1011, 270 "Cmd=%x Polling Mode.\n", command); 271 272 if (IS_P3P_TYPE(ha)) { 273 if (RD_REG_DWORD(®->isp82.hint) & 274 HINT_MBX_INT_PENDING) { 275 spin_unlock_irqrestore(&ha->hardware_lock, 276 flags); 277 ha->flags.mbox_busy = 0; 278 ql_dbg(ql_dbg_mbx, vha, 0x1012, 279 "Pending mailbox timeout, exiting.\n"); 280 rval = QLA_FUNCTION_TIMEOUT; 281 goto premature_exit; 282 } 283 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 284 } else if (IS_FWI2_CAPABLE(ha)) 285 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 286 else 287 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 288 spin_unlock_irqrestore(&ha->hardware_lock, flags); 289 290 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 291 while (!ha->flags.mbox_int) { 292 if (time_after(jiffies, wait_time)) 293 break; 294 295 /* 296 * Check if it's UNLOADING, cause we cannot poll in 297 * this case, or else a NULL pointer dereference 298 * is triggered. 299 */ 300 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) 301 return QLA_FUNCTION_TIMEOUT; 302 303 /* Check for pending interrupts. */ 304 qla2x00_poll(ha->rsp_q_map[0]); 305 306 if (!ha->flags.mbox_int && 307 !(IS_QLA2200(ha) && 308 command == MBC_LOAD_RISC_RAM_EXTENDED)) 309 msleep(10); 310 } /* while */ 311 ql_dbg(ql_dbg_mbx, vha, 0x1013, 312 "Waited %d sec.\n", 313 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 314 } 315 316 /* Check whether we timed out */ 317 if (ha->flags.mbox_int) { 318 uint16_t *iptr2; 319 320 ql_dbg(ql_dbg_mbx, vha, 0x1014, 321 "Cmd=%x completed.\n", command); 322 323 /* Got interrupt. Clear the flag. */ 324 ha->flags.mbox_int = 0; 325 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 326 327 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 328 ha->flags.mbox_busy = 0; 329 /* Setting Link-Down error */ 330 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 331 ha->mcp = NULL; 332 rval = QLA_FUNCTION_FAILED; 333 ql_log(ql_log_warn, vha, 0xd048, 334 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 335 goto premature_exit; 336 } 337 338 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 339 rval = QLA_FUNCTION_FAILED; 340 341 /* Load return mailbox registers. */ 342 iptr2 = mcp->mb; 343 iptr = (uint16_t *)&ha->mailbox_out[0]; 344 mboxes = mcp->in_mb; 345 346 ql_dbg(ql_dbg_mbx, vha, 0x1113, 347 "Mailbox registers (IN):\n"); 348 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 349 if (mboxes & BIT_0) { 350 *iptr2 = *iptr; 351 ql_dbg(ql_dbg_mbx, vha, 0x1114, 352 "mbox[%d]->0x%04x\n", cnt, *iptr2); 353 } 354 355 mboxes >>= 1; 356 iptr2++; 357 iptr++; 358 } 359 } else { 360 361 uint16_t mb[8]; 362 uint32_t ictrl, host_status, hccr; 363 uint16_t w; 364 365 if (IS_FWI2_CAPABLE(ha)) { 366 mb[0] = RD_REG_WORD(®->isp24.mailbox0); 367 mb[1] = RD_REG_WORD(®->isp24.mailbox1); 368 mb[2] = RD_REG_WORD(®->isp24.mailbox2); 369 mb[3] = RD_REG_WORD(®->isp24.mailbox3); 370 mb[7] = RD_REG_WORD(®->isp24.mailbox7); 371 ictrl = RD_REG_DWORD(®->isp24.ictrl); 372 host_status = RD_REG_DWORD(®->isp24.host_status); 373 hccr = RD_REG_DWORD(®->isp24.hccr); 374 375 ql_log(ql_log_warn, vha, 0xd04c, 376 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 377 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n", 378 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3], 379 mb[7], host_status, hccr); 380 381 } else { 382 mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0); 383 ictrl = RD_REG_WORD(®->isp.ictrl); 384 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 385 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 386 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]); 387 } 388 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 389 390 /* Capture FW dump only, if PCI device active */ 391 if (!pci_channel_offline(vha->hw->pdev)) { 392 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 393 if (w == 0xffff || ictrl == 0xffffffff) { 394 /* This is special case if there is unload 395 * of driver happening and if PCI device go 396 * into bad state due to PCI error condition 397 * then only PCI ERR flag would be set. 398 * we will do premature exit for above case. 399 */ 400 ha->flags.mbox_busy = 0; 401 rval = QLA_FUNCTION_TIMEOUT; 402 goto premature_exit; 403 } 404 405 /* Attempt to capture firmware dump for further 406 * anallysis of the current formware state. we do not 407 * need to do this if we are intentionally generating 408 * a dump 409 */ 410 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 411 ha->isp_ops->fw_dump(vha, 0); 412 rval = QLA_FUNCTION_TIMEOUT; 413 } 414 } 415 416 ha->flags.mbox_busy = 0; 417 418 /* Clean up */ 419 ha->mcp = NULL; 420 421 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 422 ql_dbg(ql_dbg_mbx, vha, 0x101a, 423 "Checking for additional resp interrupt.\n"); 424 425 /* polling mode for non isp_abort commands. */ 426 qla2x00_poll(ha->rsp_q_map[0]); 427 } 428 429 if (rval == QLA_FUNCTION_TIMEOUT && 430 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 431 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 432 ha->flags.eeh_busy) { 433 /* not in dpc. schedule it for dpc to take over. */ 434 ql_dbg(ql_dbg_mbx, vha, 0x101b, 435 "Timeout, schedule isp_abort_needed.\n"); 436 437 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 438 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 439 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 440 if (IS_QLA82XX(ha)) { 441 ql_dbg(ql_dbg_mbx, vha, 0x112a, 442 "disabling pause transmit on port " 443 "0 & 1.\n"); 444 qla82xx_wr_32(ha, 445 QLA82XX_CRB_NIU + 0x98, 446 CRB_NIU_XG_PAUSE_CTL_P0| 447 CRB_NIU_XG_PAUSE_CTL_P1); 448 } 449 ql_log(ql_log_info, base_vha, 0x101c, 450 "Mailbox cmd timeout occurred, cmd=0x%x, " 451 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 452 "abort.\n", command, mcp->mb[0], 453 ha->flags.eeh_busy); 454 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 455 qla2xxx_wake_dpc(vha); 456 } 457 } else if (!abort_active) { 458 /* call abort directly since we are in the DPC thread */ 459 ql_dbg(ql_dbg_mbx, vha, 0x101d, 460 "Timeout, calling abort_isp.\n"); 461 462 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 463 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 464 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 465 if (IS_QLA82XX(ha)) { 466 ql_dbg(ql_dbg_mbx, vha, 0x112b, 467 "disabling pause transmit on port " 468 "0 & 1.\n"); 469 qla82xx_wr_32(ha, 470 QLA82XX_CRB_NIU + 0x98, 471 CRB_NIU_XG_PAUSE_CTL_P0| 472 CRB_NIU_XG_PAUSE_CTL_P1); 473 } 474 ql_log(ql_log_info, base_vha, 0x101e, 475 "Mailbox cmd timeout occurred, cmd=0x%x, " 476 "mb[0]=0x%x. Scheduling ISP abort ", 477 command, mcp->mb[0]); 478 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 479 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 480 /* Allow next mbx cmd to come in. */ 481 complete(&ha->mbx_cmd_comp); 482 if (ha->isp_ops->abort_isp(vha)) { 483 /* Failed. retry later. */ 484 set_bit(ISP_ABORT_NEEDED, 485 &vha->dpc_flags); 486 } 487 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 488 ql_dbg(ql_dbg_mbx, vha, 0x101f, 489 "Finished abort_isp.\n"); 490 goto mbx_done; 491 } 492 } 493 } 494 495 premature_exit: 496 /* Allow next mbx cmd to come in. */ 497 complete(&ha->mbx_cmd_comp); 498 499 mbx_done: 500 if (rval) { 501 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) { 502 pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR, 503 dev_name(&ha->pdev->dev), 0x1020+0x800, 504 vha->host_no); 505 mboxes = mcp->in_mb; 506 cnt = 4; 507 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1) 508 if (mboxes & BIT_0) { 509 printk(" mb[%u]=%x", i, mcp->mb[i]); 510 cnt--; 511 } 512 pr_warn(" cmd=%x ****\n", command); 513 } 514 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) { 515 ql_dbg(ql_dbg_mbx, vha, 0x1198, 516 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n", 517 RD_REG_DWORD(®->isp24.host_status), 518 RD_REG_DWORD(®->isp24.ictrl), 519 RD_REG_DWORD(®->isp24.istatus)); 520 } else { 521 ql_dbg(ql_dbg_mbx, vha, 0x1206, 522 "ctrl_status=%#x ictrl=%#x istatus=%#x\n", 523 RD_REG_WORD(®->isp.ctrl_status), 524 RD_REG_WORD(®->isp.ictrl), 525 RD_REG_WORD(®->isp.istatus)); 526 } 527 } else { 528 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 529 } 530 531 return rval; 532 } 533 534 int 535 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 536 uint32_t risc_code_size) 537 { 538 int rval; 539 struct qla_hw_data *ha = vha->hw; 540 mbx_cmd_t mc; 541 mbx_cmd_t *mcp = &mc; 542 543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 544 "Entered %s.\n", __func__); 545 546 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 547 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 548 mcp->mb[8] = MSW(risc_addr); 549 mcp->out_mb = MBX_8|MBX_0; 550 } else { 551 mcp->mb[0] = MBC_LOAD_RISC_RAM; 552 mcp->out_mb = MBX_0; 553 } 554 mcp->mb[1] = LSW(risc_addr); 555 mcp->mb[2] = MSW(req_dma); 556 mcp->mb[3] = LSW(req_dma); 557 mcp->mb[6] = MSW(MSD(req_dma)); 558 mcp->mb[7] = LSW(MSD(req_dma)); 559 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 560 if (IS_FWI2_CAPABLE(ha)) { 561 mcp->mb[4] = MSW(risc_code_size); 562 mcp->mb[5] = LSW(risc_code_size); 563 mcp->out_mb |= MBX_5|MBX_4; 564 } else { 565 mcp->mb[4] = LSW(risc_code_size); 566 mcp->out_mb |= MBX_4; 567 } 568 569 mcp->in_mb = MBX_0; 570 mcp->tov = MBX_TOV_SECONDS; 571 mcp->flags = 0; 572 rval = qla2x00_mailbox_command(vha, mcp); 573 574 if (rval != QLA_SUCCESS) { 575 ql_dbg(ql_dbg_mbx, vha, 0x1023, 576 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 577 } else { 578 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 579 "Done %s.\n", __func__); 580 } 581 582 return rval; 583 } 584 585 #define EXTENDED_BB_CREDITS BIT_0 586 #define NVME_ENABLE_FLAG BIT_3 587 static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha) 588 { 589 uint16_t mb4 = BIT_0; 590 591 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 592 mb4 |= ha->long_range_distance << LR_DIST_FW_POS; 593 594 return mb4; 595 } 596 597 static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha) 598 { 599 uint16_t mb4 = BIT_0; 600 601 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 602 struct nvram_81xx *nv = ha->nvram; 603 604 mb4 |= LR_DIST_FW_FIELD(nv->enhanced_features); 605 } 606 607 return mb4; 608 } 609 610 /* 611 * qla2x00_execute_fw 612 * Start adapter firmware. 613 * 614 * Input: 615 * ha = adapter block pointer. 616 * TARGET_QUEUE_LOCK must be released. 617 * ADAPTER_STATE_LOCK must be released. 618 * 619 * Returns: 620 * qla2x00 local function return status code. 621 * 622 * Context: 623 * Kernel context. 624 */ 625 int 626 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 627 { 628 int rval; 629 struct qla_hw_data *ha = vha->hw; 630 mbx_cmd_t mc; 631 mbx_cmd_t *mcp = &mc; 632 633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 634 "Entered %s.\n", __func__); 635 636 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 637 mcp->out_mb = MBX_0; 638 mcp->in_mb = MBX_0; 639 if (IS_FWI2_CAPABLE(ha)) { 640 mcp->mb[1] = MSW(risc_addr); 641 mcp->mb[2] = LSW(risc_addr); 642 mcp->mb[3] = 0; 643 mcp->mb[4] = 0; 644 ha->flags.using_lr_setting = 0; 645 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 646 IS_QLA27XX(ha)) { 647 if (ql2xautodetectsfp) { 648 if (ha->flags.detected_lr_sfp) { 649 mcp->mb[4] |= 650 qla25xx_set_sfp_lr_dist(ha); 651 ha->flags.using_lr_setting = 1; 652 } 653 } else { 654 struct nvram_81xx *nv = ha->nvram; 655 /* set LR distance if specified in nvram */ 656 if (nv->enhanced_features & 657 NEF_LR_DIST_ENABLE) { 658 mcp->mb[4] |= 659 qla25xx_set_nvr_lr_dist(ha); 660 ha->flags.using_lr_setting = 1; 661 } 662 } 663 } 664 665 if (ql2xnvmeenable && IS_QLA27XX(ha)) 666 mcp->mb[4] |= NVME_ENABLE_FLAG; 667 668 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 669 struct nvram_81xx *nv = ha->nvram; 670 /* set minimum speed if specified in nvram */ 671 if (nv->min_link_speed >= 2 && 672 nv->min_link_speed <= 5) { 673 mcp->mb[4] |= BIT_4; 674 mcp->mb[11] = nv->min_link_speed; 675 mcp->out_mb |= MBX_11; 676 mcp->in_mb |= BIT_5; 677 vha->min_link_speed_feat = nv->min_link_speed; 678 } 679 } 680 681 if (ha->flags.exlogins_enabled) 682 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN; 683 684 if (ha->flags.exchoffld_enabled) 685 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD; 686 687 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 688 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1; 689 } else { 690 mcp->mb[1] = LSW(risc_addr); 691 mcp->out_mb |= MBX_1; 692 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 693 mcp->mb[2] = 0; 694 mcp->out_mb |= MBX_2; 695 } 696 } 697 698 mcp->tov = MBX_TOV_SECONDS; 699 mcp->flags = 0; 700 rval = qla2x00_mailbox_command(vha, mcp); 701 702 if (rval != QLA_SUCCESS) { 703 ql_dbg(ql_dbg_mbx, vha, 0x1026, 704 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 705 } else { 706 if (IS_FWI2_CAPABLE(ha)) { 707 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2]; 708 ql_dbg(ql_dbg_mbx, vha, 0x119a, 709 "fw_ability_mask=%x.\n", ha->fw_ability_mask); 710 ql_dbg(ql_dbg_mbx, vha, 0x1027, 711 "exchanges=%x.\n", mcp->mb[1]); 712 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 713 ha->max_speed_sup = mcp->mb[2] & BIT_0; 714 ql_dbg(ql_dbg_mbx, vha, 0x119b, 715 "Maximum speed supported=%s.\n", 716 ha->max_speed_sup ? "32Gps" : "16Gps"); 717 if (vha->min_link_speed_feat) { 718 ha->min_link_speed = mcp->mb[5]; 719 ql_dbg(ql_dbg_mbx, vha, 0x119c, 720 "Minimum speed set=%s.\n", 721 mcp->mb[5] == 5 ? "32Gps" : 722 mcp->mb[5] == 4 ? "16Gps" : 723 mcp->mb[5] == 3 ? "8Gps" : 724 mcp->mb[5] == 2 ? "4Gps" : 725 "unknown"); 726 } 727 } 728 } 729 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 730 "Done.\n"); 731 } 732 733 return rval; 734 } 735 736 /* 737 * qla_get_exlogin_status 738 * Get extended login status 739 * uses the memory offload control/status Mailbox 740 * 741 * Input: 742 * ha: adapter state pointer. 743 * fwopt: firmware options 744 * 745 * Returns: 746 * qla2x00 local function status 747 * 748 * Context: 749 * Kernel context. 750 */ 751 #define FETCH_XLOGINS_STAT 0x8 752 int 753 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 754 uint16_t *ex_logins_cnt) 755 { 756 int rval; 757 mbx_cmd_t mc; 758 mbx_cmd_t *mcp = &mc; 759 760 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f, 761 "Entered %s\n", __func__); 762 763 memset(mcp->mb, 0 , sizeof(mcp->mb)); 764 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 765 mcp->mb[1] = FETCH_XLOGINS_STAT; 766 mcp->out_mb = MBX_1|MBX_0; 767 mcp->in_mb = MBX_10|MBX_4|MBX_0; 768 mcp->tov = MBX_TOV_SECONDS; 769 mcp->flags = 0; 770 771 rval = qla2x00_mailbox_command(vha, mcp); 772 if (rval != QLA_SUCCESS) { 773 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval); 774 } else { 775 *buf_sz = mcp->mb[4]; 776 *ex_logins_cnt = mcp->mb[10]; 777 778 ql_log(ql_log_info, vha, 0x1190, 779 "buffer size 0x%x, exchange login count=%d\n", 780 mcp->mb[4], mcp->mb[10]); 781 782 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116, 783 "Done %s.\n", __func__); 784 } 785 786 return rval; 787 } 788 789 /* 790 * qla_set_exlogin_mem_cfg 791 * set extended login memory configuration 792 * Mbx needs to be issues before init_cb is set 793 * 794 * Input: 795 * ha: adapter state pointer. 796 * buffer: buffer pointer 797 * phys_addr: physical address of buffer 798 * size: size of buffer 799 * TARGET_QUEUE_LOCK must be released 800 * ADAPTER_STATE_LOCK must be release 801 * 802 * Returns: 803 * qla2x00 local funxtion status code. 804 * 805 * Context: 806 * Kernel context. 807 */ 808 #define CONFIG_XLOGINS_MEM 0x3 809 int 810 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 811 { 812 int rval; 813 mbx_cmd_t mc; 814 mbx_cmd_t *mcp = &mc; 815 struct qla_hw_data *ha = vha->hw; 816 817 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a, 818 "Entered %s.\n", __func__); 819 820 memset(mcp->mb, 0 , sizeof(mcp->mb)); 821 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 822 mcp->mb[1] = CONFIG_XLOGINS_MEM; 823 mcp->mb[2] = MSW(phys_addr); 824 mcp->mb[3] = LSW(phys_addr); 825 mcp->mb[6] = MSW(MSD(phys_addr)); 826 mcp->mb[7] = LSW(MSD(phys_addr)); 827 mcp->mb[8] = MSW(ha->exlogin_size); 828 mcp->mb[9] = LSW(ha->exlogin_size); 829 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 830 mcp->in_mb = MBX_11|MBX_0; 831 mcp->tov = MBX_TOV_SECONDS; 832 mcp->flags = 0; 833 rval = qla2x00_mailbox_command(vha, mcp); 834 if (rval != QLA_SUCCESS) { 835 /*EMPTY*/ 836 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval); 837 } else { 838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 839 "Done %s.\n", __func__); 840 } 841 842 return rval; 843 } 844 845 /* 846 * qla_get_exchoffld_status 847 * Get exchange offload status 848 * uses the memory offload control/status Mailbox 849 * 850 * Input: 851 * ha: adapter state pointer. 852 * fwopt: firmware options 853 * 854 * Returns: 855 * qla2x00 local function status 856 * 857 * Context: 858 * Kernel context. 859 */ 860 #define FETCH_XCHOFFLD_STAT 0x2 861 int 862 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 863 uint16_t *ex_logins_cnt) 864 { 865 int rval; 866 mbx_cmd_t mc; 867 mbx_cmd_t *mcp = &mc; 868 869 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019, 870 "Entered %s\n", __func__); 871 872 memset(mcp->mb, 0 , sizeof(mcp->mb)); 873 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 874 mcp->mb[1] = FETCH_XCHOFFLD_STAT; 875 mcp->out_mb = MBX_1|MBX_0; 876 mcp->in_mb = MBX_10|MBX_4|MBX_0; 877 mcp->tov = MBX_TOV_SECONDS; 878 mcp->flags = 0; 879 880 rval = qla2x00_mailbox_command(vha, mcp); 881 if (rval != QLA_SUCCESS) { 882 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval); 883 } else { 884 *buf_sz = mcp->mb[4]; 885 *ex_logins_cnt = mcp->mb[10]; 886 887 ql_log(ql_log_info, vha, 0x118e, 888 "buffer size 0x%x, exchange offload count=%d\n", 889 mcp->mb[4], mcp->mb[10]); 890 891 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156, 892 "Done %s.\n", __func__); 893 } 894 895 return rval; 896 } 897 898 /* 899 * qla_set_exchoffld_mem_cfg 900 * Set exchange offload memory configuration 901 * Mbx needs to be issues before init_cb is set 902 * 903 * Input: 904 * ha: adapter state pointer. 905 * buffer: buffer pointer 906 * phys_addr: physical address of buffer 907 * size: size of buffer 908 * TARGET_QUEUE_LOCK must be released 909 * ADAPTER_STATE_LOCK must be release 910 * 911 * Returns: 912 * qla2x00 local funxtion status code. 913 * 914 * Context: 915 * Kernel context. 916 */ 917 #define CONFIG_XCHOFFLD_MEM 0x3 918 int 919 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha) 920 { 921 int rval; 922 mbx_cmd_t mc; 923 mbx_cmd_t *mcp = &mc; 924 struct qla_hw_data *ha = vha->hw; 925 926 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157, 927 "Entered %s.\n", __func__); 928 929 memset(mcp->mb, 0 , sizeof(mcp->mb)); 930 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 931 mcp->mb[1] = CONFIG_XCHOFFLD_MEM; 932 mcp->mb[2] = MSW(ha->exchoffld_buf_dma); 933 mcp->mb[3] = LSW(ha->exchoffld_buf_dma); 934 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma)); 935 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma)); 936 mcp->mb[8] = MSW(ha->exchoffld_size); 937 mcp->mb[9] = LSW(ha->exchoffld_size); 938 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 939 mcp->in_mb = MBX_11|MBX_0; 940 mcp->tov = MBX_TOV_SECONDS; 941 mcp->flags = 0; 942 rval = qla2x00_mailbox_command(vha, mcp); 943 if (rval != QLA_SUCCESS) { 944 /*EMPTY*/ 945 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval); 946 } else { 947 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 948 "Done %s.\n", __func__); 949 } 950 951 return rval; 952 } 953 954 /* 955 * qla2x00_get_fw_version 956 * Get firmware version. 957 * 958 * Input: 959 * ha: adapter state pointer. 960 * major: pointer for major number. 961 * minor: pointer for minor number. 962 * subminor: pointer for subminor number. 963 * 964 * Returns: 965 * qla2x00 local function return status code. 966 * 967 * Context: 968 * Kernel context. 969 */ 970 int 971 qla2x00_get_fw_version(scsi_qla_host_t *vha) 972 { 973 int rval; 974 mbx_cmd_t mc; 975 mbx_cmd_t *mcp = &mc; 976 struct qla_hw_data *ha = vha->hw; 977 978 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 979 "Entered %s.\n", __func__); 980 981 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 982 mcp->out_mb = MBX_0; 983 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 984 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 985 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 986 if (IS_FWI2_CAPABLE(ha)) 987 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 988 if (IS_QLA27XX(ha)) 989 mcp->in_mb |= 990 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18| 991 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8; 992 993 mcp->flags = 0; 994 mcp->tov = MBX_TOV_SECONDS; 995 rval = qla2x00_mailbox_command(vha, mcp); 996 if (rval != QLA_SUCCESS) 997 goto failed; 998 999 /* Return mailbox data. */ 1000 ha->fw_major_version = mcp->mb[1]; 1001 ha->fw_minor_version = mcp->mb[2]; 1002 ha->fw_subminor_version = mcp->mb[3]; 1003 ha->fw_attributes = mcp->mb[6]; 1004 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 1005 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 1006 else 1007 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 1008 1009 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 1010 ha->mpi_version[0] = mcp->mb[10] & 0xff; 1011 ha->mpi_version[1] = mcp->mb[11] >> 8; 1012 ha->mpi_version[2] = mcp->mb[11] & 0xff; 1013 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 1014 ha->phy_version[0] = mcp->mb[8] & 0xff; 1015 ha->phy_version[1] = mcp->mb[9] >> 8; 1016 ha->phy_version[2] = mcp->mb[9] & 0xff; 1017 } 1018 1019 if (IS_FWI2_CAPABLE(ha)) { 1020 ha->fw_attributes_h = mcp->mb[15]; 1021 ha->fw_attributes_ext[0] = mcp->mb[16]; 1022 ha->fw_attributes_ext[1] = mcp->mb[17]; 1023 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 1024 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 1025 __func__, mcp->mb[15], mcp->mb[6]); 1026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 1027 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 1028 __func__, mcp->mb[17], mcp->mb[16]); 1029 1030 if (ha->fw_attributes_h & 0x4) 1031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d, 1032 "%s: Firmware supports Extended Login 0x%x\n", 1033 __func__, ha->fw_attributes_h); 1034 1035 if (ha->fw_attributes_h & 0x8) 1036 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191, 1037 "%s: Firmware supports Exchange Offload 0x%x\n", 1038 __func__, ha->fw_attributes_h); 1039 1040 /* 1041 * FW supports nvme and driver load parameter requested nvme. 1042 * BIT 26 of fw_attributes indicates NVMe support. 1043 */ 1044 if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable) { 1045 vha->flags.nvme_enabled = 1; 1046 ql_log(ql_log_info, vha, 0xd302, 1047 "%s: FC-NVMe is Enabled (0x%x)\n", 1048 __func__, ha->fw_attributes_h); 1049 } 1050 } 1051 1052 if (IS_QLA27XX(ha)) { 1053 ha->mpi_version[0] = mcp->mb[10] & 0xff; 1054 ha->mpi_version[1] = mcp->mb[11] >> 8; 1055 ha->mpi_version[2] = mcp->mb[11] & 0xff; 1056 ha->pep_version[0] = mcp->mb[13] & 0xff; 1057 ha->pep_version[1] = mcp->mb[14] >> 8; 1058 ha->pep_version[2] = mcp->mb[14] & 0xff; 1059 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 1060 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 1061 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22]; 1062 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24]; 1063 } 1064 1065 failed: 1066 if (rval != QLA_SUCCESS) { 1067 /*EMPTY*/ 1068 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 1069 } else { 1070 /*EMPTY*/ 1071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 1072 "Done %s.\n", __func__); 1073 } 1074 return rval; 1075 } 1076 1077 /* 1078 * qla2x00_get_fw_options 1079 * Set firmware options. 1080 * 1081 * Input: 1082 * ha = adapter block pointer. 1083 * fwopt = pointer for firmware options. 1084 * 1085 * Returns: 1086 * qla2x00 local function return status code. 1087 * 1088 * Context: 1089 * Kernel context. 1090 */ 1091 int 1092 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1093 { 1094 int rval; 1095 mbx_cmd_t mc; 1096 mbx_cmd_t *mcp = &mc; 1097 1098 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 1099 "Entered %s.\n", __func__); 1100 1101 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 1102 mcp->out_mb = MBX_0; 1103 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1104 mcp->tov = MBX_TOV_SECONDS; 1105 mcp->flags = 0; 1106 rval = qla2x00_mailbox_command(vha, mcp); 1107 1108 if (rval != QLA_SUCCESS) { 1109 /*EMPTY*/ 1110 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 1111 } else { 1112 fwopts[0] = mcp->mb[0]; 1113 fwopts[1] = mcp->mb[1]; 1114 fwopts[2] = mcp->mb[2]; 1115 fwopts[3] = mcp->mb[3]; 1116 1117 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 1118 "Done %s.\n", __func__); 1119 } 1120 1121 return rval; 1122 } 1123 1124 1125 /* 1126 * qla2x00_set_fw_options 1127 * Set firmware options. 1128 * 1129 * Input: 1130 * ha = adapter block pointer. 1131 * fwopt = pointer for firmware options. 1132 * 1133 * Returns: 1134 * qla2x00 local function return status code. 1135 * 1136 * Context: 1137 * Kernel context. 1138 */ 1139 int 1140 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1141 { 1142 int rval; 1143 mbx_cmd_t mc; 1144 mbx_cmd_t *mcp = &mc; 1145 1146 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 1147 "Entered %s.\n", __func__); 1148 1149 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 1150 mcp->mb[1] = fwopts[1]; 1151 mcp->mb[2] = fwopts[2]; 1152 mcp->mb[3] = fwopts[3]; 1153 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1154 mcp->in_mb = MBX_0; 1155 if (IS_FWI2_CAPABLE(vha->hw)) { 1156 mcp->in_mb |= MBX_1; 1157 mcp->mb[10] = fwopts[10]; 1158 mcp->out_mb |= MBX_10; 1159 } else { 1160 mcp->mb[10] = fwopts[10]; 1161 mcp->mb[11] = fwopts[11]; 1162 mcp->mb[12] = 0; /* Undocumented, but used */ 1163 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 1164 } 1165 mcp->tov = MBX_TOV_SECONDS; 1166 mcp->flags = 0; 1167 rval = qla2x00_mailbox_command(vha, mcp); 1168 1169 fwopts[0] = mcp->mb[0]; 1170 1171 if (rval != QLA_SUCCESS) { 1172 /*EMPTY*/ 1173 ql_dbg(ql_dbg_mbx, vha, 0x1030, 1174 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 1175 } else { 1176 /*EMPTY*/ 1177 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 1178 "Done %s.\n", __func__); 1179 } 1180 1181 return rval; 1182 } 1183 1184 /* 1185 * qla2x00_mbx_reg_test 1186 * Mailbox register wrap test. 1187 * 1188 * Input: 1189 * ha = adapter block pointer. 1190 * TARGET_QUEUE_LOCK must be released. 1191 * ADAPTER_STATE_LOCK must be released. 1192 * 1193 * Returns: 1194 * qla2x00 local function return status code. 1195 * 1196 * Context: 1197 * Kernel context. 1198 */ 1199 int 1200 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 1201 { 1202 int rval; 1203 mbx_cmd_t mc; 1204 mbx_cmd_t *mcp = &mc; 1205 1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 1207 "Entered %s.\n", __func__); 1208 1209 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 1210 mcp->mb[1] = 0xAAAA; 1211 mcp->mb[2] = 0x5555; 1212 mcp->mb[3] = 0xAA55; 1213 mcp->mb[4] = 0x55AA; 1214 mcp->mb[5] = 0xA5A5; 1215 mcp->mb[6] = 0x5A5A; 1216 mcp->mb[7] = 0x2525; 1217 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1218 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1219 mcp->tov = MBX_TOV_SECONDS; 1220 mcp->flags = 0; 1221 rval = qla2x00_mailbox_command(vha, mcp); 1222 1223 if (rval == QLA_SUCCESS) { 1224 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 1225 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 1226 rval = QLA_FUNCTION_FAILED; 1227 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 1228 mcp->mb[7] != 0x2525) 1229 rval = QLA_FUNCTION_FAILED; 1230 } 1231 1232 if (rval != QLA_SUCCESS) { 1233 /*EMPTY*/ 1234 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 1235 } else { 1236 /*EMPTY*/ 1237 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 1238 "Done %s.\n", __func__); 1239 } 1240 1241 return rval; 1242 } 1243 1244 /* 1245 * qla2x00_verify_checksum 1246 * Verify firmware checksum. 1247 * 1248 * Input: 1249 * ha = adapter block pointer. 1250 * TARGET_QUEUE_LOCK must be released. 1251 * ADAPTER_STATE_LOCK must be released. 1252 * 1253 * Returns: 1254 * qla2x00 local function return status code. 1255 * 1256 * Context: 1257 * Kernel context. 1258 */ 1259 int 1260 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 1261 { 1262 int rval; 1263 mbx_cmd_t mc; 1264 mbx_cmd_t *mcp = &mc; 1265 1266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 1267 "Entered %s.\n", __func__); 1268 1269 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 1270 mcp->out_mb = MBX_0; 1271 mcp->in_mb = MBX_0; 1272 if (IS_FWI2_CAPABLE(vha->hw)) { 1273 mcp->mb[1] = MSW(risc_addr); 1274 mcp->mb[2] = LSW(risc_addr); 1275 mcp->out_mb |= MBX_2|MBX_1; 1276 mcp->in_mb |= MBX_2|MBX_1; 1277 } else { 1278 mcp->mb[1] = LSW(risc_addr); 1279 mcp->out_mb |= MBX_1; 1280 mcp->in_mb |= MBX_1; 1281 } 1282 1283 mcp->tov = MBX_TOV_SECONDS; 1284 mcp->flags = 0; 1285 rval = qla2x00_mailbox_command(vha, mcp); 1286 1287 if (rval != QLA_SUCCESS) { 1288 ql_dbg(ql_dbg_mbx, vha, 0x1036, 1289 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 1290 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 1291 } else { 1292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 1293 "Done %s.\n", __func__); 1294 } 1295 1296 return rval; 1297 } 1298 1299 /* 1300 * qla2x00_issue_iocb 1301 * Issue IOCB using mailbox command 1302 * 1303 * Input: 1304 * ha = adapter state pointer. 1305 * buffer = buffer pointer. 1306 * phys_addr = physical address of buffer. 1307 * size = size of buffer. 1308 * TARGET_QUEUE_LOCK must be released. 1309 * ADAPTER_STATE_LOCK must be released. 1310 * 1311 * Returns: 1312 * qla2x00 local function return status code. 1313 * 1314 * Context: 1315 * Kernel context. 1316 */ 1317 int 1318 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 1319 dma_addr_t phys_addr, size_t size, uint32_t tov) 1320 { 1321 int rval; 1322 mbx_cmd_t mc; 1323 mbx_cmd_t *mcp = &mc; 1324 1325 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 1326 "Entered %s.\n", __func__); 1327 1328 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 1329 mcp->mb[1] = 0; 1330 mcp->mb[2] = MSW(phys_addr); 1331 mcp->mb[3] = LSW(phys_addr); 1332 mcp->mb[6] = MSW(MSD(phys_addr)); 1333 mcp->mb[7] = LSW(MSD(phys_addr)); 1334 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1335 mcp->in_mb = MBX_2|MBX_0; 1336 mcp->tov = tov; 1337 mcp->flags = 0; 1338 rval = qla2x00_mailbox_command(vha, mcp); 1339 1340 if (rval != QLA_SUCCESS) { 1341 /*EMPTY*/ 1342 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 1343 } else { 1344 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 1345 1346 /* Mask reserved bits. */ 1347 sts_entry->entry_status &= 1348 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 1349 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 1350 "Done %s.\n", __func__); 1351 } 1352 1353 return rval; 1354 } 1355 1356 int 1357 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 1358 size_t size) 1359 { 1360 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 1361 MBX_TOV_SECONDS); 1362 } 1363 1364 /* 1365 * qla2x00_abort_command 1366 * Abort command aborts a specified IOCB. 1367 * 1368 * Input: 1369 * ha = adapter block pointer. 1370 * sp = SB structure pointer. 1371 * 1372 * Returns: 1373 * qla2x00 local function return status code. 1374 * 1375 * Context: 1376 * Kernel context. 1377 */ 1378 int 1379 qla2x00_abort_command(srb_t *sp) 1380 { 1381 unsigned long flags = 0; 1382 int rval; 1383 uint32_t handle = 0; 1384 mbx_cmd_t mc; 1385 mbx_cmd_t *mcp = &mc; 1386 fc_port_t *fcport = sp->fcport; 1387 scsi_qla_host_t *vha = fcport->vha; 1388 struct qla_hw_data *ha = vha->hw; 1389 struct req_que *req; 1390 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1391 1392 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 1393 "Entered %s.\n", __func__); 1394 1395 if (vha->flags.qpairs_available && sp->qpair) 1396 req = sp->qpair->req; 1397 else 1398 req = vha->req; 1399 1400 spin_lock_irqsave(&ha->hardware_lock, flags); 1401 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1402 if (req->outstanding_cmds[handle] == sp) 1403 break; 1404 } 1405 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1406 1407 if (handle == req->num_outstanding_cmds) { 1408 /* command not found */ 1409 return QLA_FUNCTION_FAILED; 1410 } 1411 1412 mcp->mb[0] = MBC_ABORT_COMMAND; 1413 if (HAS_EXTENDED_IDS(ha)) 1414 mcp->mb[1] = fcport->loop_id; 1415 else 1416 mcp->mb[1] = fcport->loop_id << 8; 1417 mcp->mb[2] = (uint16_t)handle; 1418 mcp->mb[3] = (uint16_t)(handle >> 16); 1419 mcp->mb[6] = (uint16_t)cmd->device->lun; 1420 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1421 mcp->in_mb = MBX_0; 1422 mcp->tov = MBX_TOV_SECONDS; 1423 mcp->flags = 0; 1424 rval = qla2x00_mailbox_command(vha, mcp); 1425 1426 if (rval != QLA_SUCCESS) { 1427 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 1428 } else { 1429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 1430 "Done %s.\n", __func__); 1431 } 1432 1433 return rval; 1434 } 1435 1436 int 1437 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 1438 { 1439 int rval, rval2; 1440 mbx_cmd_t mc; 1441 mbx_cmd_t *mcp = &mc; 1442 scsi_qla_host_t *vha; 1443 struct req_que *req; 1444 struct rsp_que *rsp; 1445 1446 l = l; 1447 vha = fcport->vha; 1448 1449 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 1450 "Entered %s.\n", __func__); 1451 1452 req = vha->hw->req_q_map[0]; 1453 rsp = req->rsp; 1454 mcp->mb[0] = MBC_ABORT_TARGET; 1455 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 1456 if (HAS_EXTENDED_IDS(vha->hw)) { 1457 mcp->mb[1] = fcport->loop_id; 1458 mcp->mb[10] = 0; 1459 mcp->out_mb |= MBX_10; 1460 } else { 1461 mcp->mb[1] = fcport->loop_id << 8; 1462 } 1463 mcp->mb[2] = vha->hw->loop_reset_delay; 1464 mcp->mb[9] = vha->vp_idx; 1465 1466 mcp->in_mb = MBX_0; 1467 mcp->tov = MBX_TOV_SECONDS; 1468 mcp->flags = 0; 1469 rval = qla2x00_mailbox_command(vha, mcp); 1470 if (rval != QLA_SUCCESS) { 1471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1472 "Failed=%x.\n", rval); 1473 } 1474 1475 /* Issue marker IOCB. */ 1476 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 1477 MK_SYNC_ID); 1478 if (rval2 != QLA_SUCCESS) { 1479 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1480 "Failed to issue marker IOCB (%x).\n", rval2); 1481 } else { 1482 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1483 "Done %s.\n", __func__); 1484 } 1485 1486 return rval; 1487 } 1488 1489 int 1490 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1491 { 1492 int rval, rval2; 1493 mbx_cmd_t mc; 1494 mbx_cmd_t *mcp = &mc; 1495 scsi_qla_host_t *vha; 1496 struct req_que *req; 1497 struct rsp_que *rsp; 1498 1499 vha = fcport->vha; 1500 1501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1502 "Entered %s.\n", __func__); 1503 1504 req = vha->hw->req_q_map[0]; 1505 rsp = req->rsp; 1506 mcp->mb[0] = MBC_LUN_RESET; 1507 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1508 if (HAS_EXTENDED_IDS(vha->hw)) 1509 mcp->mb[1] = fcport->loop_id; 1510 else 1511 mcp->mb[1] = fcport->loop_id << 8; 1512 mcp->mb[2] = (u32)l; 1513 mcp->mb[3] = 0; 1514 mcp->mb[9] = vha->vp_idx; 1515 1516 mcp->in_mb = MBX_0; 1517 mcp->tov = MBX_TOV_SECONDS; 1518 mcp->flags = 0; 1519 rval = qla2x00_mailbox_command(vha, mcp); 1520 if (rval != QLA_SUCCESS) { 1521 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1522 } 1523 1524 /* Issue marker IOCB. */ 1525 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1526 MK_SYNC_ID_LUN); 1527 if (rval2 != QLA_SUCCESS) { 1528 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1529 "Failed to issue marker IOCB (%x).\n", rval2); 1530 } else { 1531 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1532 "Done %s.\n", __func__); 1533 } 1534 1535 return rval; 1536 } 1537 1538 /* 1539 * qla2x00_get_adapter_id 1540 * Get adapter ID and topology. 1541 * 1542 * Input: 1543 * ha = adapter block pointer. 1544 * id = pointer for loop ID. 1545 * al_pa = pointer for AL_PA. 1546 * area = pointer for area. 1547 * domain = pointer for domain. 1548 * top = pointer for topology. 1549 * TARGET_QUEUE_LOCK must be released. 1550 * ADAPTER_STATE_LOCK must be released. 1551 * 1552 * Returns: 1553 * qla2x00 local function return status code. 1554 * 1555 * Context: 1556 * Kernel context. 1557 */ 1558 int 1559 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1560 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1561 { 1562 int rval; 1563 mbx_cmd_t mc; 1564 mbx_cmd_t *mcp = &mc; 1565 1566 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1567 "Entered %s.\n", __func__); 1568 1569 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1570 mcp->mb[9] = vha->vp_idx; 1571 mcp->out_mb = MBX_9|MBX_0; 1572 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1573 if (IS_CNA_CAPABLE(vha->hw)) 1574 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1575 if (IS_FWI2_CAPABLE(vha->hw)) 1576 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1577 if (IS_QLA27XX(vha->hw)) 1578 mcp->in_mb |= MBX_15; 1579 mcp->tov = MBX_TOV_SECONDS; 1580 mcp->flags = 0; 1581 rval = qla2x00_mailbox_command(vha, mcp); 1582 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1583 rval = QLA_COMMAND_ERROR; 1584 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1585 rval = QLA_INVALID_COMMAND; 1586 1587 /* Return data. */ 1588 *id = mcp->mb[1]; 1589 *al_pa = LSB(mcp->mb[2]); 1590 *area = MSB(mcp->mb[2]); 1591 *domain = LSB(mcp->mb[3]); 1592 *top = mcp->mb[6]; 1593 *sw_cap = mcp->mb[7]; 1594 1595 if (rval != QLA_SUCCESS) { 1596 /*EMPTY*/ 1597 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1598 } else { 1599 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1600 "Done %s.\n", __func__); 1601 1602 if (IS_CNA_CAPABLE(vha->hw)) { 1603 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1604 vha->fcoe_fcf_idx = mcp->mb[10]; 1605 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1606 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1607 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1608 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1609 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1610 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1611 } 1612 /* If FA-WWN supported */ 1613 if (IS_FAWWN_CAPABLE(vha->hw)) { 1614 if (mcp->mb[7] & BIT_14) { 1615 vha->port_name[0] = MSB(mcp->mb[16]); 1616 vha->port_name[1] = LSB(mcp->mb[16]); 1617 vha->port_name[2] = MSB(mcp->mb[17]); 1618 vha->port_name[3] = LSB(mcp->mb[17]); 1619 vha->port_name[4] = MSB(mcp->mb[18]); 1620 vha->port_name[5] = LSB(mcp->mb[18]); 1621 vha->port_name[6] = MSB(mcp->mb[19]); 1622 vha->port_name[7] = LSB(mcp->mb[19]); 1623 fc_host_port_name(vha->host) = 1624 wwn_to_u64(vha->port_name); 1625 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1626 "FA-WWN acquired %016llx\n", 1627 wwn_to_u64(vha->port_name)); 1628 } 1629 } 1630 1631 if (IS_QLA27XX(vha->hw)) 1632 vha->bbcr = mcp->mb[15]; 1633 } 1634 1635 return rval; 1636 } 1637 1638 /* 1639 * qla2x00_get_retry_cnt 1640 * Get current firmware login retry count and delay. 1641 * 1642 * Input: 1643 * ha = adapter block pointer. 1644 * retry_cnt = pointer to login retry count. 1645 * tov = pointer to login timeout value. 1646 * 1647 * Returns: 1648 * qla2x00 local function return status code. 1649 * 1650 * Context: 1651 * Kernel context. 1652 */ 1653 int 1654 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1655 uint16_t *r_a_tov) 1656 { 1657 int rval; 1658 uint16_t ratov; 1659 mbx_cmd_t mc; 1660 mbx_cmd_t *mcp = &mc; 1661 1662 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1663 "Entered %s.\n", __func__); 1664 1665 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1666 mcp->out_mb = MBX_0; 1667 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1668 mcp->tov = MBX_TOV_SECONDS; 1669 mcp->flags = 0; 1670 rval = qla2x00_mailbox_command(vha, mcp); 1671 1672 if (rval != QLA_SUCCESS) { 1673 /*EMPTY*/ 1674 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1675 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1676 } else { 1677 /* Convert returned data and check our values. */ 1678 *r_a_tov = mcp->mb[3] / 2; 1679 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1680 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1681 /* Update to the larger values */ 1682 *retry_cnt = (uint8_t)mcp->mb[1]; 1683 *tov = ratov; 1684 } 1685 1686 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1687 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1688 } 1689 1690 return rval; 1691 } 1692 1693 /* 1694 * qla2x00_init_firmware 1695 * Initialize adapter firmware. 1696 * 1697 * Input: 1698 * ha = adapter block pointer. 1699 * dptr = Initialization control block pointer. 1700 * size = size of initialization control block. 1701 * TARGET_QUEUE_LOCK must be released. 1702 * ADAPTER_STATE_LOCK must be released. 1703 * 1704 * Returns: 1705 * qla2x00 local function return status code. 1706 * 1707 * Context: 1708 * Kernel context. 1709 */ 1710 int 1711 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1712 { 1713 int rval; 1714 mbx_cmd_t mc; 1715 mbx_cmd_t *mcp = &mc; 1716 struct qla_hw_data *ha = vha->hw; 1717 1718 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1719 "Entered %s.\n", __func__); 1720 1721 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1722 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1723 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1724 1725 if (ha->flags.npiv_supported) 1726 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1727 else 1728 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1729 1730 mcp->mb[1] = 0; 1731 mcp->mb[2] = MSW(ha->init_cb_dma); 1732 mcp->mb[3] = LSW(ha->init_cb_dma); 1733 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1734 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1735 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1736 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1737 mcp->mb[1] = BIT_0; 1738 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1739 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1740 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1741 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1742 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1743 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1744 } 1745 /* 1 and 2 should normally be captured. */ 1746 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1747 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1748 /* mb3 is additional info about the installed SFP. */ 1749 mcp->in_mb |= MBX_3; 1750 mcp->buf_size = size; 1751 mcp->flags = MBX_DMA_OUT; 1752 mcp->tov = MBX_TOV_SECONDS; 1753 rval = qla2x00_mailbox_command(vha, mcp); 1754 1755 if (rval != QLA_SUCCESS) { 1756 /*EMPTY*/ 1757 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1758 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1759 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1760 } else { 1761 if (IS_QLA27XX(ha)) { 1762 if (mcp->mb[2] == 6 || mcp->mb[3] == 2) 1763 ql_dbg(ql_dbg_mbx, vha, 0x119d, 1764 "Invalid SFP/Validation Failed\n"); 1765 } 1766 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1767 "Done %s.\n", __func__); 1768 } 1769 1770 return rval; 1771 } 1772 1773 1774 /* 1775 * qla2x00_get_port_database 1776 * Issue normal/enhanced get port database mailbox command 1777 * and copy device name as necessary. 1778 * 1779 * Input: 1780 * ha = adapter state pointer. 1781 * dev = structure pointer. 1782 * opt = enhanced cmd option byte. 1783 * 1784 * Returns: 1785 * qla2x00 local function return status code. 1786 * 1787 * Context: 1788 * Kernel context. 1789 */ 1790 int 1791 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1792 { 1793 int rval; 1794 mbx_cmd_t mc; 1795 mbx_cmd_t *mcp = &mc; 1796 port_database_t *pd; 1797 struct port_database_24xx *pd24; 1798 dma_addr_t pd_dma; 1799 struct qla_hw_data *ha = vha->hw; 1800 1801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1802 "Entered %s.\n", __func__); 1803 1804 pd24 = NULL; 1805 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1806 if (pd == NULL) { 1807 ql_log(ql_log_warn, vha, 0x1050, 1808 "Failed to allocate port database structure.\n"); 1809 fcport->query = 0; 1810 return QLA_MEMORY_ALLOC_FAILED; 1811 } 1812 1813 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1814 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1815 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1816 mcp->mb[2] = MSW(pd_dma); 1817 mcp->mb[3] = LSW(pd_dma); 1818 mcp->mb[6] = MSW(MSD(pd_dma)); 1819 mcp->mb[7] = LSW(MSD(pd_dma)); 1820 mcp->mb[9] = vha->vp_idx; 1821 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1822 mcp->in_mb = MBX_0; 1823 if (IS_FWI2_CAPABLE(ha)) { 1824 mcp->mb[1] = fcport->loop_id; 1825 mcp->mb[10] = opt; 1826 mcp->out_mb |= MBX_10|MBX_1; 1827 mcp->in_mb |= MBX_1; 1828 } else if (HAS_EXTENDED_IDS(ha)) { 1829 mcp->mb[1] = fcport->loop_id; 1830 mcp->mb[10] = opt; 1831 mcp->out_mb |= MBX_10|MBX_1; 1832 } else { 1833 mcp->mb[1] = fcport->loop_id << 8 | opt; 1834 mcp->out_mb |= MBX_1; 1835 } 1836 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1837 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1838 mcp->flags = MBX_DMA_IN; 1839 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1840 rval = qla2x00_mailbox_command(vha, mcp); 1841 if (rval != QLA_SUCCESS) 1842 goto gpd_error_out; 1843 1844 if (IS_FWI2_CAPABLE(ha)) { 1845 uint64_t zero = 0; 1846 u8 current_login_state, last_login_state; 1847 1848 pd24 = (struct port_database_24xx *) pd; 1849 1850 /* Check for logged in state. */ 1851 if (fcport->fc4f_nvme) { 1852 current_login_state = pd24->current_login_state >> 4; 1853 last_login_state = pd24->last_login_state >> 4; 1854 } else { 1855 current_login_state = pd24->current_login_state & 0xf; 1856 last_login_state = pd24->last_login_state & 0xf; 1857 } 1858 fcport->current_login_state = pd24->current_login_state; 1859 fcport->last_login_state = pd24->last_login_state; 1860 1861 /* Check for logged in state. */ 1862 if (current_login_state != PDS_PRLI_COMPLETE && 1863 last_login_state != PDS_PRLI_COMPLETE) { 1864 ql_dbg(ql_dbg_mbx, vha, 0x119a, 1865 "Unable to verify login-state (%x/%x) for loop_id %x.\n", 1866 current_login_state, last_login_state, 1867 fcport->loop_id); 1868 rval = QLA_FUNCTION_FAILED; 1869 1870 if (!fcport->query) 1871 goto gpd_error_out; 1872 } 1873 1874 if (fcport->loop_id == FC_NO_LOOP_ID || 1875 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1876 memcmp(fcport->port_name, pd24->port_name, 8))) { 1877 /* We lost the device mid way. */ 1878 rval = QLA_NOT_LOGGED_IN; 1879 goto gpd_error_out; 1880 } 1881 1882 /* Names are little-endian. */ 1883 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1884 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1885 1886 /* Get port_id of device. */ 1887 fcport->d_id.b.domain = pd24->port_id[0]; 1888 fcport->d_id.b.area = pd24->port_id[1]; 1889 fcport->d_id.b.al_pa = pd24->port_id[2]; 1890 fcport->d_id.b.rsvd_1 = 0; 1891 1892 /* If not target must be initiator or unknown type. */ 1893 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1894 fcport->port_type = FCT_INITIATOR; 1895 else 1896 fcport->port_type = FCT_TARGET; 1897 1898 /* Passback COS information. */ 1899 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1900 FC_COS_CLASS2 : FC_COS_CLASS3; 1901 1902 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1903 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1904 } else { 1905 uint64_t zero = 0; 1906 1907 /* Check for logged in state. */ 1908 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1909 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1910 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1911 "Unable to verify login-state (%x/%x) - " 1912 "portid=%02x%02x%02x.\n", pd->master_state, 1913 pd->slave_state, fcport->d_id.b.domain, 1914 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1915 rval = QLA_FUNCTION_FAILED; 1916 goto gpd_error_out; 1917 } 1918 1919 if (fcport->loop_id == FC_NO_LOOP_ID || 1920 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1921 memcmp(fcport->port_name, pd->port_name, 8))) { 1922 /* We lost the device mid way. */ 1923 rval = QLA_NOT_LOGGED_IN; 1924 goto gpd_error_out; 1925 } 1926 1927 /* Names are little-endian. */ 1928 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1929 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1930 1931 /* Get port_id of device. */ 1932 fcport->d_id.b.domain = pd->port_id[0]; 1933 fcport->d_id.b.area = pd->port_id[3]; 1934 fcport->d_id.b.al_pa = pd->port_id[2]; 1935 fcport->d_id.b.rsvd_1 = 0; 1936 1937 /* If not target must be initiator or unknown type. */ 1938 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1939 fcport->port_type = FCT_INITIATOR; 1940 else 1941 fcport->port_type = FCT_TARGET; 1942 1943 /* Passback COS information. */ 1944 fcport->supported_classes = (pd->options & BIT_4) ? 1945 FC_COS_CLASS2: FC_COS_CLASS3; 1946 } 1947 1948 gpd_error_out: 1949 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1950 fcport->query = 0; 1951 1952 if (rval != QLA_SUCCESS) { 1953 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1954 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1955 mcp->mb[0], mcp->mb[1]); 1956 } else { 1957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1958 "Done %s.\n", __func__); 1959 } 1960 1961 return rval; 1962 } 1963 1964 /* 1965 * qla2x00_get_firmware_state 1966 * Get adapter firmware state. 1967 * 1968 * Input: 1969 * ha = adapter block pointer. 1970 * dptr = pointer for firmware state. 1971 * TARGET_QUEUE_LOCK must be released. 1972 * ADAPTER_STATE_LOCK must be released. 1973 * 1974 * Returns: 1975 * qla2x00 local function return status code. 1976 * 1977 * Context: 1978 * Kernel context. 1979 */ 1980 int 1981 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1982 { 1983 int rval; 1984 mbx_cmd_t mc; 1985 mbx_cmd_t *mcp = &mc; 1986 struct qla_hw_data *ha = vha->hw; 1987 1988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1989 "Entered %s.\n", __func__); 1990 1991 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1992 mcp->out_mb = MBX_0; 1993 if (IS_FWI2_CAPABLE(vha->hw)) 1994 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1995 else 1996 mcp->in_mb = MBX_1|MBX_0; 1997 mcp->tov = MBX_TOV_SECONDS; 1998 mcp->flags = 0; 1999 rval = qla2x00_mailbox_command(vha, mcp); 2000 2001 /* Return firmware states. */ 2002 states[0] = mcp->mb[1]; 2003 if (IS_FWI2_CAPABLE(vha->hw)) { 2004 states[1] = mcp->mb[2]; 2005 states[2] = mcp->mb[3]; /* SFP info */ 2006 states[3] = mcp->mb[4]; 2007 states[4] = mcp->mb[5]; 2008 states[5] = mcp->mb[6]; /* DPORT status */ 2009 } 2010 2011 if (rval != QLA_SUCCESS) { 2012 /*EMPTY*/ 2013 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 2014 } else { 2015 if (IS_QLA27XX(ha)) { 2016 if (mcp->mb[2] == 6 || mcp->mb[3] == 2) 2017 ql_dbg(ql_dbg_mbx, vha, 0x119e, 2018 "Invalid SFP/Validation Failed\n"); 2019 } 2020 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 2021 "Done %s.\n", __func__); 2022 } 2023 2024 return rval; 2025 } 2026 2027 /* 2028 * qla2x00_get_port_name 2029 * Issue get port name mailbox command. 2030 * Returned name is in big endian format. 2031 * 2032 * Input: 2033 * ha = adapter block pointer. 2034 * loop_id = loop ID of device. 2035 * name = pointer for name. 2036 * TARGET_QUEUE_LOCK must be released. 2037 * ADAPTER_STATE_LOCK must be released. 2038 * 2039 * Returns: 2040 * qla2x00 local function return status code. 2041 * 2042 * Context: 2043 * Kernel context. 2044 */ 2045 int 2046 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 2047 uint8_t opt) 2048 { 2049 int rval; 2050 mbx_cmd_t mc; 2051 mbx_cmd_t *mcp = &mc; 2052 2053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 2054 "Entered %s.\n", __func__); 2055 2056 mcp->mb[0] = MBC_GET_PORT_NAME; 2057 mcp->mb[9] = vha->vp_idx; 2058 mcp->out_mb = MBX_9|MBX_1|MBX_0; 2059 if (HAS_EXTENDED_IDS(vha->hw)) { 2060 mcp->mb[1] = loop_id; 2061 mcp->mb[10] = opt; 2062 mcp->out_mb |= MBX_10; 2063 } else { 2064 mcp->mb[1] = loop_id << 8 | opt; 2065 } 2066 2067 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2068 mcp->tov = MBX_TOV_SECONDS; 2069 mcp->flags = 0; 2070 rval = qla2x00_mailbox_command(vha, mcp); 2071 2072 if (rval != QLA_SUCCESS) { 2073 /*EMPTY*/ 2074 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 2075 } else { 2076 if (name != NULL) { 2077 /* This function returns name in big endian. */ 2078 name[0] = MSB(mcp->mb[2]); 2079 name[1] = LSB(mcp->mb[2]); 2080 name[2] = MSB(mcp->mb[3]); 2081 name[3] = LSB(mcp->mb[3]); 2082 name[4] = MSB(mcp->mb[6]); 2083 name[5] = LSB(mcp->mb[6]); 2084 name[6] = MSB(mcp->mb[7]); 2085 name[7] = LSB(mcp->mb[7]); 2086 } 2087 2088 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 2089 "Done %s.\n", __func__); 2090 } 2091 2092 return rval; 2093 } 2094 2095 /* 2096 * qla24xx_link_initialization 2097 * Issue link initialization mailbox command. 2098 * 2099 * Input: 2100 * ha = adapter block pointer. 2101 * TARGET_QUEUE_LOCK must be released. 2102 * ADAPTER_STATE_LOCK must be released. 2103 * 2104 * Returns: 2105 * qla2x00 local function return status code. 2106 * 2107 * Context: 2108 * Kernel context. 2109 */ 2110 int 2111 qla24xx_link_initialize(scsi_qla_host_t *vha) 2112 { 2113 int rval; 2114 mbx_cmd_t mc; 2115 mbx_cmd_t *mcp = &mc; 2116 2117 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 2118 "Entered %s.\n", __func__); 2119 2120 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 2121 return QLA_FUNCTION_FAILED; 2122 2123 mcp->mb[0] = MBC_LINK_INITIALIZATION; 2124 mcp->mb[1] = BIT_4; 2125 if (vha->hw->operating_mode == LOOP) 2126 mcp->mb[1] |= BIT_6; 2127 else 2128 mcp->mb[1] |= BIT_5; 2129 mcp->mb[2] = 0; 2130 mcp->mb[3] = 0; 2131 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2132 mcp->in_mb = MBX_0; 2133 mcp->tov = MBX_TOV_SECONDS; 2134 mcp->flags = 0; 2135 rval = qla2x00_mailbox_command(vha, mcp); 2136 2137 if (rval != QLA_SUCCESS) { 2138 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 2139 } else { 2140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 2141 "Done %s.\n", __func__); 2142 } 2143 2144 return rval; 2145 } 2146 2147 /* 2148 * qla2x00_lip_reset 2149 * Issue LIP reset mailbox command. 2150 * 2151 * Input: 2152 * ha = adapter block pointer. 2153 * TARGET_QUEUE_LOCK must be released. 2154 * ADAPTER_STATE_LOCK must be released. 2155 * 2156 * Returns: 2157 * qla2x00 local function return status code. 2158 * 2159 * Context: 2160 * Kernel context. 2161 */ 2162 int 2163 qla2x00_lip_reset(scsi_qla_host_t *vha) 2164 { 2165 int rval; 2166 mbx_cmd_t mc; 2167 mbx_cmd_t *mcp = &mc; 2168 2169 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 2170 "Entered %s.\n", __func__); 2171 2172 if (IS_CNA_CAPABLE(vha->hw)) { 2173 /* Logout across all FCFs. */ 2174 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2175 mcp->mb[1] = BIT_1; 2176 mcp->mb[2] = 0; 2177 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2178 } else if (IS_FWI2_CAPABLE(vha->hw)) { 2179 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2180 mcp->mb[1] = BIT_6; 2181 mcp->mb[2] = 0; 2182 mcp->mb[3] = vha->hw->loop_reset_delay; 2183 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2184 } else { 2185 mcp->mb[0] = MBC_LIP_RESET; 2186 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2187 if (HAS_EXTENDED_IDS(vha->hw)) { 2188 mcp->mb[1] = 0x00ff; 2189 mcp->mb[10] = 0; 2190 mcp->out_mb |= MBX_10; 2191 } else { 2192 mcp->mb[1] = 0xff00; 2193 } 2194 mcp->mb[2] = vha->hw->loop_reset_delay; 2195 mcp->mb[3] = 0; 2196 } 2197 mcp->in_mb = MBX_0; 2198 mcp->tov = MBX_TOV_SECONDS; 2199 mcp->flags = 0; 2200 rval = qla2x00_mailbox_command(vha, mcp); 2201 2202 if (rval != QLA_SUCCESS) { 2203 /*EMPTY*/ 2204 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 2205 } else { 2206 /*EMPTY*/ 2207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 2208 "Done %s.\n", __func__); 2209 } 2210 2211 return rval; 2212 } 2213 2214 /* 2215 * qla2x00_send_sns 2216 * Send SNS command. 2217 * 2218 * Input: 2219 * ha = adapter block pointer. 2220 * sns = pointer for command. 2221 * cmd_size = command size. 2222 * buf_size = response/command size. 2223 * TARGET_QUEUE_LOCK must be released. 2224 * ADAPTER_STATE_LOCK must be released. 2225 * 2226 * Returns: 2227 * qla2x00 local function return status code. 2228 * 2229 * Context: 2230 * Kernel context. 2231 */ 2232 int 2233 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 2234 uint16_t cmd_size, size_t buf_size) 2235 { 2236 int rval; 2237 mbx_cmd_t mc; 2238 mbx_cmd_t *mcp = &mc; 2239 2240 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 2241 "Entered %s.\n", __func__); 2242 2243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 2244 "Retry cnt=%d ratov=%d total tov=%d.\n", 2245 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 2246 2247 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 2248 mcp->mb[1] = cmd_size; 2249 mcp->mb[2] = MSW(sns_phys_address); 2250 mcp->mb[3] = LSW(sns_phys_address); 2251 mcp->mb[6] = MSW(MSD(sns_phys_address)); 2252 mcp->mb[7] = LSW(MSD(sns_phys_address)); 2253 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2254 mcp->in_mb = MBX_0|MBX_1; 2255 mcp->buf_size = buf_size; 2256 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 2257 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 2258 rval = qla2x00_mailbox_command(vha, mcp); 2259 2260 if (rval != QLA_SUCCESS) { 2261 /*EMPTY*/ 2262 ql_dbg(ql_dbg_mbx, vha, 0x105f, 2263 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2264 rval, mcp->mb[0], mcp->mb[1]); 2265 } else { 2266 /*EMPTY*/ 2267 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 2268 "Done %s.\n", __func__); 2269 } 2270 2271 return rval; 2272 } 2273 2274 int 2275 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2276 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2277 { 2278 int rval; 2279 2280 struct logio_entry_24xx *lg; 2281 dma_addr_t lg_dma; 2282 uint32_t iop[2]; 2283 struct qla_hw_data *ha = vha->hw; 2284 struct req_que *req; 2285 2286 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 2287 "Entered %s.\n", __func__); 2288 2289 if (vha->vp_idx && vha->qpair) 2290 req = vha->qpair->req; 2291 else 2292 req = ha->req_q_map[0]; 2293 2294 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2295 if (lg == NULL) { 2296 ql_log(ql_log_warn, vha, 0x1062, 2297 "Failed to allocate login IOCB.\n"); 2298 return QLA_MEMORY_ALLOC_FAILED; 2299 } 2300 2301 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2302 lg->entry_count = 1; 2303 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2304 lg->nport_handle = cpu_to_le16(loop_id); 2305 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 2306 if (opt & BIT_0) 2307 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 2308 if (opt & BIT_1) 2309 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 2310 lg->port_id[0] = al_pa; 2311 lg->port_id[1] = area; 2312 lg->port_id[2] = domain; 2313 lg->vp_index = vha->vp_idx; 2314 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2315 (ha->r_a_tov / 10 * 2) + 2); 2316 if (rval != QLA_SUCCESS) { 2317 ql_dbg(ql_dbg_mbx, vha, 0x1063, 2318 "Failed to issue login IOCB (%x).\n", rval); 2319 } else if (lg->entry_status != 0) { 2320 ql_dbg(ql_dbg_mbx, vha, 0x1064, 2321 "Failed to complete IOCB -- error status (%x).\n", 2322 lg->entry_status); 2323 rval = QLA_FUNCTION_FAILED; 2324 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2325 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2326 iop[1] = le32_to_cpu(lg->io_parameter[1]); 2327 2328 ql_dbg(ql_dbg_mbx, vha, 0x1065, 2329 "Failed to complete IOCB -- completion status (%x) " 2330 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2331 iop[0], iop[1]); 2332 2333 switch (iop[0]) { 2334 case LSC_SCODE_PORTID_USED: 2335 mb[0] = MBS_PORT_ID_USED; 2336 mb[1] = LSW(iop[1]); 2337 break; 2338 case LSC_SCODE_NPORT_USED: 2339 mb[0] = MBS_LOOP_ID_USED; 2340 break; 2341 case LSC_SCODE_NOLINK: 2342 case LSC_SCODE_NOIOCB: 2343 case LSC_SCODE_NOXCB: 2344 case LSC_SCODE_CMD_FAILED: 2345 case LSC_SCODE_NOFABRIC: 2346 case LSC_SCODE_FW_NOT_READY: 2347 case LSC_SCODE_NOT_LOGGED_IN: 2348 case LSC_SCODE_NOPCB: 2349 case LSC_SCODE_ELS_REJECT: 2350 case LSC_SCODE_CMD_PARAM_ERR: 2351 case LSC_SCODE_NONPORT: 2352 case LSC_SCODE_LOGGED_IN: 2353 case LSC_SCODE_NOFLOGI_ACC: 2354 default: 2355 mb[0] = MBS_COMMAND_ERROR; 2356 break; 2357 } 2358 } else { 2359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 2360 "Done %s.\n", __func__); 2361 2362 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2363 2364 mb[0] = MBS_COMMAND_COMPLETE; 2365 mb[1] = 0; 2366 if (iop[0] & BIT_4) { 2367 if (iop[0] & BIT_8) 2368 mb[1] |= BIT_1; 2369 } else 2370 mb[1] = BIT_0; 2371 2372 /* Passback COS information. */ 2373 mb[10] = 0; 2374 if (lg->io_parameter[7] || lg->io_parameter[8]) 2375 mb[10] |= BIT_0; /* Class 2. */ 2376 if (lg->io_parameter[9] || lg->io_parameter[10]) 2377 mb[10] |= BIT_1; /* Class 3. */ 2378 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 2379 mb[10] |= BIT_7; /* Confirmed Completion 2380 * Allowed 2381 */ 2382 } 2383 2384 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2385 2386 return rval; 2387 } 2388 2389 /* 2390 * qla2x00_login_fabric 2391 * Issue login fabric port mailbox command. 2392 * 2393 * Input: 2394 * ha = adapter block pointer. 2395 * loop_id = device loop ID. 2396 * domain = device domain. 2397 * area = device area. 2398 * al_pa = device AL_PA. 2399 * status = pointer for return status. 2400 * opt = command options. 2401 * TARGET_QUEUE_LOCK must be released. 2402 * ADAPTER_STATE_LOCK must be released. 2403 * 2404 * Returns: 2405 * qla2x00 local function return status code. 2406 * 2407 * Context: 2408 * Kernel context. 2409 */ 2410 int 2411 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2412 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2413 { 2414 int rval; 2415 mbx_cmd_t mc; 2416 mbx_cmd_t *mcp = &mc; 2417 struct qla_hw_data *ha = vha->hw; 2418 2419 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2420 "Entered %s.\n", __func__); 2421 2422 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2423 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2424 if (HAS_EXTENDED_IDS(ha)) { 2425 mcp->mb[1] = loop_id; 2426 mcp->mb[10] = opt; 2427 mcp->out_mb |= MBX_10; 2428 } else { 2429 mcp->mb[1] = (loop_id << 8) | opt; 2430 } 2431 mcp->mb[2] = domain; 2432 mcp->mb[3] = area << 8 | al_pa; 2433 2434 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2435 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2436 mcp->flags = 0; 2437 rval = qla2x00_mailbox_command(vha, mcp); 2438 2439 /* Return mailbox statuses. */ 2440 if (mb != NULL) { 2441 mb[0] = mcp->mb[0]; 2442 mb[1] = mcp->mb[1]; 2443 mb[2] = mcp->mb[2]; 2444 mb[6] = mcp->mb[6]; 2445 mb[7] = mcp->mb[7]; 2446 /* COS retrieved from Get-Port-Database mailbox command. */ 2447 mb[10] = 0; 2448 } 2449 2450 if (rval != QLA_SUCCESS) { 2451 /* RLU tmp code: need to change main mailbox_command function to 2452 * return ok even when the mailbox completion value is not 2453 * SUCCESS. The caller needs to be responsible to interpret 2454 * the return values of this mailbox command if we're not 2455 * to change too much of the existing code. 2456 */ 2457 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2458 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2459 mcp->mb[0] == 0x4006) 2460 rval = QLA_SUCCESS; 2461 2462 /*EMPTY*/ 2463 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2464 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2465 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2466 } else { 2467 /*EMPTY*/ 2468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2469 "Done %s.\n", __func__); 2470 } 2471 2472 return rval; 2473 } 2474 2475 /* 2476 * qla2x00_login_local_device 2477 * Issue login loop port mailbox command. 2478 * 2479 * Input: 2480 * ha = adapter block pointer. 2481 * loop_id = device loop ID. 2482 * opt = command options. 2483 * 2484 * Returns: 2485 * Return status code. 2486 * 2487 * Context: 2488 * Kernel context. 2489 * 2490 */ 2491 int 2492 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2493 uint16_t *mb_ret, uint8_t opt) 2494 { 2495 int rval; 2496 mbx_cmd_t mc; 2497 mbx_cmd_t *mcp = &mc; 2498 struct qla_hw_data *ha = vha->hw; 2499 2500 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2501 "Entered %s.\n", __func__); 2502 2503 if (IS_FWI2_CAPABLE(ha)) 2504 return qla24xx_login_fabric(vha, fcport->loop_id, 2505 fcport->d_id.b.domain, fcport->d_id.b.area, 2506 fcport->d_id.b.al_pa, mb_ret, opt); 2507 2508 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2509 if (HAS_EXTENDED_IDS(ha)) 2510 mcp->mb[1] = fcport->loop_id; 2511 else 2512 mcp->mb[1] = fcport->loop_id << 8; 2513 mcp->mb[2] = opt; 2514 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2515 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2516 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2517 mcp->flags = 0; 2518 rval = qla2x00_mailbox_command(vha, mcp); 2519 2520 /* Return mailbox statuses. */ 2521 if (mb_ret != NULL) { 2522 mb_ret[0] = mcp->mb[0]; 2523 mb_ret[1] = mcp->mb[1]; 2524 mb_ret[6] = mcp->mb[6]; 2525 mb_ret[7] = mcp->mb[7]; 2526 } 2527 2528 if (rval != QLA_SUCCESS) { 2529 /* AV tmp code: need to change main mailbox_command function to 2530 * return ok even when the mailbox completion value is not 2531 * SUCCESS. The caller needs to be responsible to interpret 2532 * the return values of this mailbox command if we're not 2533 * to change too much of the existing code. 2534 */ 2535 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2536 rval = QLA_SUCCESS; 2537 2538 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2539 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2540 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2541 } else { 2542 /*EMPTY*/ 2543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2544 "Done %s.\n", __func__); 2545 } 2546 2547 return (rval); 2548 } 2549 2550 int 2551 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2552 uint8_t area, uint8_t al_pa) 2553 { 2554 int rval; 2555 struct logio_entry_24xx *lg; 2556 dma_addr_t lg_dma; 2557 struct qla_hw_data *ha = vha->hw; 2558 struct req_que *req; 2559 2560 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2561 "Entered %s.\n", __func__); 2562 2563 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2564 if (lg == NULL) { 2565 ql_log(ql_log_warn, vha, 0x106e, 2566 "Failed to allocate logout IOCB.\n"); 2567 return QLA_MEMORY_ALLOC_FAILED; 2568 } 2569 2570 req = vha->req; 2571 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2572 lg->entry_count = 1; 2573 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2574 lg->nport_handle = cpu_to_le16(loop_id); 2575 lg->control_flags = 2576 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2577 LCF_FREE_NPORT); 2578 lg->port_id[0] = al_pa; 2579 lg->port_id[1] = area; 2580 lg->port_id[2] = domain; 2581 lg->vp_index = vha->vp_idx; 2582 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2583 (ha->r_a_tov / 10 * 2) + 2); 2584 if (rval != QLA_SUCCESS) { 2585 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2586 "Failed to issue logout IOCB (%x).\n", rval); 2587 } else if (lg->entry_status != 0) { 2588 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2589 "Failed to complete IOCB -- error status (%x).\n", 2590 lg->entry_status); 2591 rval = QLA_FUNCTION_FAILED; 2592 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2593 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2594 "Failed to complete IOCB -- completion status (%x) " 2595 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2596 le32_to_cpu(lg->io_parameter[0]), 2597 le32_to_cpu(lg->io_parameter[1])); 2598 } else { 2599 /*EMPTY*/ 2600 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2601 "Done %s.\n", __func__); 2602 } 2603 2604 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2605 2606 return rval; 2607 } 2608 2609 /* 2610 * qla2x00_fabric_logout 2611 * Issue logout fabric port mailbox command. 2612 * 2613 * Input: 2614 * ha = adapter block pointer. 2615 * loop_id = device loop ID. 2616 * TARGET_QUEUE_LOCK must be released. 2617 * ADAPTER_STATE_LOCK must be released. 2618 * 2619 * Returns: 2620 * qla2x00 local function return status code. 2621 * 2622 * Context: 2623 * Kernel context. 2624 */ 2625 int 2626 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2627 uint8_t area, uint8_t al_pa) 2628 { 2629 int rval; 2630 mbx_cmd_t mc; 2631 mbx_cmd_t *mcp = &mc; 2632 2633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2634 "Entered %s.\n", __func__); 2635 2636 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2637 mcp->out_mb = MBX_1|MBX_0; 2638 if (HAS_EXTENDED_IDS(vha->hw)) { 2639 mcp->mb[1] = loop_id; 2640 mcp->mb[10] = 0; 2641 mcp->out_mb |= MBX_10; 2642 } else { 2643 mcp->mb[1] = loop_id << 8; 2644 } 2645 2646 mcp->in_mb = MBX_1|MBX_0; 2647 mcp->tov = MBX_TOV_SECONDS; 2648 mcp->flags = 0; 2649 rval = qla2x00_mailbox_command(vha, mcp); 2650 2651 if (rval != QLA_SUCCESS) { 2652 /*EMPTY*/ 2653 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2654 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2655 } else { 2656 /*EMPTY*/ 2657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2658 "Done %s.\n", __func__); 2659 } 2660 2661 return rval; 2662 } 2663 2664 /* 2665 * qla2x00_full_login_lip 2666 * Issue full login LIP mailbox command. 2667 * 2668 * Input: 2669 * ha = adapter block pointer. 2670 * TARGET_QUEUE_LOCK must be released. 2671 * ADAPTER_STATE_LOCK must be released. 2672 * 2673 * Returns: 2674 * qla2x00 local function return status code. 2675 * 2676 * Context: 2677 * Kernel context. 2678 */ 2679 int 2680 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2681 { 2682 int rval; 2683 mbx_cmd_t mc; 2684 mbx_cmd_t *mcp = &mc; 2685 2686 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2687 "Entered %s.\n", __func__); 2688 2689 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2690 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2691 mcp->mb[2] = 0; 2692 mcp->mb[3] = 0; 2693 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2694 mcp->in_mb = MBX_0; 2695 mcp->tov = MBX_TOV_SECONDS; 2696 mcp->flags = 0; 2697 rval = qla2x00_mailbox_command(vha, mcp); 2698 2699 if (rval != QLA_SUCCESS) { 2700 /*EMPTY*/ 2701 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2702 } else { 2703 /*EMPTY*/ 2704 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2705 "Done %s.\n", __func__); 2706 } 2707 2708 return rval; 2709 } 2710 2711 /* 2712 * qla2x00_get_id_list 2713 * 2714 * Input: 2715 * ha = adapter block pointer. 2716 * 2717 * Returns: 2718 * qla2x00 local function return status code. 2719 * 2720 * Context: 2721 * Kernel context. 2722 */ 2723 int 2724 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2725 uint16_t *entries) 2726 { 2727 int rval; 2728 mbx_cmd_t mc; 2729 mbx_cmd_t *mcp = &mc; 2730 2731 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2732 "Entered %s.\n", __func__); 2733 2734 if (id_list == NULL) 2735 return QLA_FUNCTION_FAILED; 2736 2737 mcp->mb[0] = MBC_GET_ID_LIST; 2738 mcp->out_mb = MBX_0; 2739 if (IS_FWI2_CAPABLE(vha->hw)) { 2740 mcp->mb[2] = MSW(id_list_dma); 2741 mcp->mb[3] = LSW(id_list_dma); 2742 mcp->mb[6] = MSW(MSD(id_list_dma)); 2743 mcp->mb[7] = LSW(MSD(id_list_dma)); 2744 mcp->mb[8] = 0; 2745 mcp->mb[9] = vha->vp_idx; 2746 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2747 } else { 2748 mcp->mb[1] = MSW(id_list_dma); 2749 mcp->mb[2] = LSW(id_list_dma); 2750 mcp->mb[3] = MSW(MSD(id_list_dma)); 2751 mcp->mb[6] = LSW(MSD(id_list_dma)); 2752 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2753 } 2754 mcp->in_mb = MBX_1|MBX_0; 2755 mcp->tov = MBX_TOV_SECONDS; 2756 mcp->flags = 0; 2757 rval = qla2x00_mailbox_command(vha, mcp); 2758 2759 if (rval != QLA_SUCCESS) { 2760 /*EMPTY*/ 2761 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2762 } else { 2763 *entries = mcp->mb[1]; 2764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2765 "Done %s.\n", __func__); 2766 } 2767 2768 return rval; 2769 } 2770 2771 /* 2772 * qla2x00_get_resource_cnts 2773 * Get current firmware resource counts. 2774 * 2775 * Input: 2776 * ha = adapter block pointer. 2777 * 2778 * Returns: 2779 * qla2x00 local function return status code. 2780 * 2781 * Context: 2782 * Kernel context. 2783 */ 2784 int 2785 qla2x00_get_resource_cnts(scsi_qla_host_t *vha) 2786 { 2787 struct qla_hw_data *ha = vha->hw; 2788 int rval; 2789 mbx_cmd_t mc; 2790 mbx_cmd_t *mcp = &mc; 2791 2792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2793 "Entered %s.\n", __func__); 2794 2795 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2796 mcp->out_mb = MBX_0; 2797 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2798 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2799 mcp->in_mb |= MBX_12; 2800 mcp->tov = MBX_TOV_SECONDS; 2801 mcp->flags = 0; 2802 rval = qla2x00_mailbox_command(vha, mcp); 2803 2804 if (rval != QLA_SUCCESS) { 2805 /*EMPTY*/ 2806 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2807 "Failed mb[0]=%x.\n", mcp->mb[0]); 2808 } else { 2809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2810 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2811 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2812 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2813 mcp->mb[11], mcp->mb[12]); 2814 2815 ha->orig_fw_tgt_xcb_count = mcp->mb[1]; 2816 ha->cur_fw_tgt_xcb_count = mcp->mb[2]; 2817 ha->cur_fw_xcb_count = mcp->mb[3]; 2818 ha->orig_fw_xcb_count = mcp->mb[6]; 2819 ha->cur_fw_iocb_count = mcp->mb[7]; 2820 ha->orig_fw_iocb_count = mcp->mb[10]; 2821 if (ha->flags.npiv_supported) 2822 ha->max_npiv_vports = mcp->mb[11]; 2823 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2824 ha->fw_max_fcf_count = mcp->mb[12]; 2825 } 2826 2827 return (rval); 2828 } 2829 2830 /* 2831 * qla2x00_get_fcal_position_map 2832 * Get FCAL (LILP) position map using mailbox command 2833 * 2834 * Input: 2835 * ha = adapter state pointer. 2836 * pos_map = buffer pointer (can be NULL). 2837 * 2838 * Returns: 2839 * qla2x00 local function return status code. 2840 * 2841 * Context: 2842 * Kernel context. 2843 */ 2844 int 2845 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2846 { 2847 int rval; 2848 mbx_cmd_t mc; 2849 mbx_cmd_t *mcp = &mc; 2850 char *pmap; 2851 dma_addr_t pmap_dma; 2852 struct qla_hw_data *ha = vha->hw; 2853 2854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2855 "Entered %s.\n", __func__); 2856 2857 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2858 if (pmap == NULL) { 2859 ql_log(ql_log_warn, vha, 0x1080, 2860 "Memory alloc failed.\n"); 2861 return QLA_MEMORY_ALLOC_FAILED; 2862 } 2863 2864 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2865 mcp->mb[2] = MSW(pmap_dma); 2866 mcp->mb[3] = LSW(pmap_dma); 2867 mcp->mb[6] = MSW(MSD(pmap_dma)); 2868 mcp->mb[7] = LSW(MSD(pmap_dma)); 2869 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2870 mcp->in_mb = MBX_1|MBX_0; 2871 mcp->buf_size = FCAL_MAP_SIZE; 2872 mcp->flags = MBX_DMA_IN; 2873 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2874 rval = qla2x00_mailbox_command(vha, mcp); 2875 2876 if (rval == QLA_SUCCESS) { 2877 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2878 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2879 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2880 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2881 pmap, pmap[0] + 1); 2882 2883 if (pos_map) 2884 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2885 } 2886 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2887 2888 if (rval != QLA_SUCCESS) { 2889 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2890 } else { 2891 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2892 "Done %s.\n", __func__); 2893 } 2894 2895 return rval; 2896 } 2897 2898 /* 2899 * qla2x00_get_link_status 2900 * 2901 * Input: 2902 * ha = adapter block pointer. 2903 * loop_id = device loop ID. 2904 * ret_buf = pointer to link status return buffer. 2905 * 2906 * Returns: 2907 * 0 = success. 2908 * BIT_0 = mem alloc error. 2909 * BIT_1 = mailbox error. 2910 */ 2911 int 2912 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2913 struct link_statistics *stats, dma_addr_t stats_dma) 2914 { 2915 int rval; 2916 mbx_cmd_t mc; 2917 mbx_cmd_t *mcp = &mc; 2918 uint32_t *iter = (void *)stats; 2919 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter); 2920 struct qla_hw_data *ha = vha->hw; 2921 2922 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2923 "Entered %s.\n", __func__); 2924 2925 mcp->mb[0] = MBC_GET_LINK_STATUS; 2926 mcp->mb[2] = MSW(LSD(stats_dma)); 2927 mcp->mb[3] = LSW(LSD(stats_dma)); 2928 mcp->mb[6] = MSW(MSD(stats_dma)); 2929 mcp->mb[7] = LSW(MSD(stats_dma)); 2930 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2931 mcp->in_mb = MBX_0; 2932 if (IS_FWI2_CAPABLE(ha)) { 2933 mcp->mb[1] = loop_id; 2934 mcp->mb[4] = 0; 2935 mcp->mb[10] = 0; 2936 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2937 mcp->in_mb |= MBX_1; 2938 } else if (HAS_EXTENDED_IDS(ha)) { 2939 mcp->mb[1] = loop_id; 2940 mcp->mb[10] = 0; 2941 mcp->out_mb |= MBX_10|MBX_1; 2942 } else { 2943 mcp->mb[1] = loop_id << 8; 2944 mcp->out_mb |= MBX_1; 2945 } 2946 mcp->tov = MBX_TOV_SECONDS; 2947 mcp->flags = IOCTL_CMD; 2948 rval = qla2x00_mailbox_command(vha, mcp); 2949 2950 if (rval == QLA_SUCCESS) { 2951 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2952 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2953 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2954 rval = QLA_FUNCTION_FAILED; 2955 } else { 2956 /* Re-endianize - firmware data is le32. */ 2957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2958 "Done %s.\n", __func__); 2959 for ( ; dwords--; iter++) 2960 le32_to_cpus(iter); 2961 } 2962 } else { 2963 /* Failed. */ 2964 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2965 } 2966 2967 return rval; 2968 } 2969 2970 int 2971 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2972 dma_addr_t stats_dma, uint16_t options) 2973 { 2974 int rval; 2975 mbx_cmd_t mc; 2976 mbx_cmd_t *mcp = &mc; 2977 uint32_t *iter, dwords; 2978 2979 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2980 "Entered %s.\n", __func__); 2981 2982 memset(&mc, 0, sizeof(mc)); 2983 mc.mb[0] = MBC_GET_LINK_PRIV_STATS; 2984 mc.mb[2] = MSW(stats_dma); 2985 mc.mb[3] = LSW(stats_dma); 2986 mc.mb[6] = MSW(MSD(stats_dma)); 2987 mc.mb[7] = LSW(MSD(stats_dma)); 2988 mc.mb[8] = sizeof(struct link_statistics) / 4; 2989 mc.mb[9] = cpu_to_le16(vha->vp_idx); 2990 mc.mb[10] = cpu_to_le16(options); 2991 2992 rval = qla24xx_send_mb_cmd(vha, &mc); 2993 2994 if (rval == QLA_SUCCESS) { 2995 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2996 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2997 "Failed mb[0]=%x.\n", mcp->mb[0]); 2998 rval = QLA_FUNCTION_FAILED; 2999 } else { 3000 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 3001 "Done %s.\n", __func__); 3002 /* Re-endianize - firmware data is le32. */ 3003 dwords = sizeof(struct link_statistics) / 4; 3004 iter = &stats->link_fail_cnt; 3005 for ( ; dwords--; iter++) 3006 le32_to_cpus(iter); 3007 } 3008 } else { 3009 /* Failed. */ 3010 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 3011 } 3012 3013 return rval; 3014 } 3015 3016 int 3017 qla24xx_abort_command(srb_t *sp) 3018 { 3019 int rval; 3020 unsigned long flags = 0; 3021 3022 struct abort_entry_24xx *abt; 3023 dma_addr_t abt_dma; 3024 uint32_t handle; 3025 fc_port_t *fcport = sp->fcport; 3026 struct scsi_qla_host *vha = fcport->vha; 3027 struct qla_hw_data *ha = vha->hw; 3028 struct req_que *req = vha->req; 3029 3030 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 3031 "Entered %s.\n", __func__); 3032 3033 if (vha->flags.qpairs_available && sp->qpair) 3034 req = sp->qpair->req; 3035 3036 if (ql2xasynctmfenable) 3037 return qla24xx_async_abort_command(sp); 3038 3039 spin_lock_irqsave(&ha->hardware_lock, flags); 3040 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 3041 if (req->outstanding_cmds[handle] == sp) 3042 break; 3043 } 3044 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3045 if (handle == req->num_outstanding_cmds) { 3046 /* Command not found. */ 3047 return QLA_FUNCTION_FAILED; 3048 } 3049 3050 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 3051 if (abt == NULL) { 3052 ql_log(ql_log_warn, vha, 0x108d, 3053 "Failed to allocate abort IOCB.\n"); 3054 return QLA_MEMORY_ALLOC_FAILED; 3055 } 3056 3057 abt->entry_type = ABORT_IOCB_TYPE; 3058 abt->entry_count = 1; 3059 abt->handle = MAKE_HANDLE(req->id, abt->handle); 3060 abt->nport_handle = cpu_to_le16(fcport->loop_id); 3061 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 3062 abt->port_id[0] = fcport->d_id.b.al_pa; 3063 abt->port_id[1] = fcport->d_id.b.area; 3064 abt->port_id[2] = fcport->d_id.b.domain; 3065 abt->vp_index = fcport->vha->vp_idx; 3066 3067 abt->req_que_no = cpu_to_le16(req->id); 3068 3069 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 3070 if (rval != QLA_SUCCESS) { 3071 ql_dbg(ql_dbg_mbx, vha, 0x108e, 3072 "Failed to issue IOCB (%x).\n", rval); 3073 } else if (abt->entry_status != 0) { 3074 ql_dbg(ql_dbg_mbx, vha, 0x108f, 3075 "Failed to complete IOCB -- error status (%x).\n", 3076 abt->entry_status); 3077 rval = QLA_FUNCTION_FAILED; 3078 } else if (abt->nport_handle != cpu_to_le16(0)) { 3079 ql_dbg(ql_dbg_mbx, vha, 0x1090, 3080 "Failed to complete IOCB -- completion status (%x).\n", 3081 le16_to_cpu(abt->nport_handle)); 3082 if (abt->nport_handle == CS_IOCB_ERROR) 3083 rval = QLA_FUNCTION_PARAMETER_ERROR; 3084 else 3085 rval = QLA_FUNCTION_FAILED; 3086 } else { 3087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 3088 "Done %s.\n", __func__); 3089 } 3090 3091 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 3092 3093 return rval; 3094 } 3095 3096 struct tsk_mgmt_cmd { 3097 union { 3098 struct tsk_mgmt_entry tsk; 3099 struct sts_entry_24xx sts; 3100 } p; 3101 }; 3102 3103 static int 3104 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 3105 uint64_t l, int tag) 3106 { 3107 int rval, rval2; 3108 struct tsk_mgmt_cmd *tsk; 3109 struct sts_entry_24xx *sts; 3110 dma_addr_t tsk_dma; 3111 scsi_qla_host_t *vha; 3112 struct qla_hw_data *ha; 3113 struct req_que *req; 3114 struct rsp_que *rsp; 3115 struct qla_qpair *qpair; 3116 3117 vha = fcport->vha; 3118 ha = vha->hw; 3119 req = vha->req; 3120 3121 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 3122 "Entered %s.\n", __func__); 3123 3124 if (vha->vp_idx && vha->qpair) { 3125 /* NPIV port */ 3126 qpair = vha->qpair; 3127 rsp = qpair->rsp; 3128 req = qpair->req; 3129 } else { 3130 rsp = req->rsp; 3131 } 3132 3133 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 3134 if (tsk == NULL) { 3135 ql_log(ql_log_warn, vha, 0x1093, 3136 "Failed to allocate task management IOCB.\n"); 3137 return QLA_MEMORY_ALLOC_FAILED; 3138 } 3139 3140 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 3141 tsk->p.tsk.entry_count = 1; 3142 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 3143 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 3144 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 3145 tsk->p.tsk.control_flags = cpu_to_le32(type); 3146 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 3147 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 3148 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 3149 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 3150 if (type == TCF_LUN_RESET) { 3151 int_to_scsilun(l, &tsk->p.tsk.lun); 3152 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 3153 sizeof(tsk->p.tsk.lun)); 3154 } 3155 3156 sts = &tsk->p.sts; 3157 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 3158 if (rval != QLA_SUCCESS) { 3159 ql_dbg(ql_dbg_mbx, vha, 0x1094, 3160 "Failed to issue %s reset IOCB (%x).\n", name, rval); 3161 } else if (sts->entry_status != 0) { 3162 ql_dbg(ql_dbg_mbx, vha, 0x1095, 3163 "Failed to complete IOCB -- error status (%x).\n", 3164 sts->entry_status); 3165 rval = QLA_FUNCTION_FAILED; 3166 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 3167 ql_dbg(ql_dbg_mbx, vha, 0x1096, 3168 "Failed to complete IOCB -- completion status (%x).\n", 3169 le16_to_cpu(sts->comp_status)); 3170 rval = QLA_FUNCTION_FAILED; 3171 } else if (le16_to_cpu(sts->scsi_status) & 3172 SS_RESPONSE_INFO_LEN_VALID) { 3173 if (le32_to_cpu(sts->rsp_data_len) < 4) { 3174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 3175 "Ignoring inconsistent data length -- not enough " 3176 "response info (%d).\n", 3177 le32_to_cpu(sts->rsp_data_len)); 3178 } else if (sts->data[3]) { 3179 ql_dbg(ql_dbg_mbx, vha, 0x1098, 3180 "Failed to complete IOCB -- response (%x).\n", 3181 sts->data[3]); 3182 rval = QLA_FUNCTION_FAILED; 3183 } 3184 } 3185 3186 /* Issue marker IOCB. */ 3187 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 3188 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 3189 if (rval2 != QLA_SUCCESS) { 3190 ql_dbg(ql_dbg_mbx, vha, 0x1099, 3191 "Failed to issue marker IOCB (%x).\n", rval2); 3192 } else { 3193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 3194 "Done %s.\n", __func__); 3195 } 3196 3197 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 3198 3199 return rval; 3200 } 3201 3202 int 3203 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 3204 { 3205 struct qla_hw_data *ha = fcport->vha->hw; 3206 3207 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3208 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 3209 3210 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 3211 } 3212 3213 int 3214 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 3215 { 3216 struct qla_hw_data *ha = fcport->vha->hw; 3217 3218 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3219 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 3220 3221 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 3222 } 3223 3224 int 3225 qla2x00_system_error(scsi_qla_host_t *vha) 3226 { 3227 int rval; 3228 mbx_cmd_t mc; 3229 mbx_cmd_t *mcp = &mc; 3230 struct qla_hw_data *ha = vha->hw; 3231 3232 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 3233 return QLA_FUNCTION_FAILED; 3234 3235 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 3236 "Entered %s.\n", __func__); 3237 3238 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 3239 mcp->out_mb = MBX_0; 3240 mcp->in_mb = MBX_0; 3241 mcp->tov = 5; 3242 mcp->flags = 0; 3243 rval = qla2x00_mailbox_command(vha, mcp); 3244 3245 if (rval != QLA_SUCCESS) { 3246 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 3247 } else { 3248 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 3249 "Done %s.\n", __func__); 3250 } 3251 3252 return rval; 3253 } 3254 3255 int 3256 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 3257 { 3258 int rval; 3259 mbx_cmd_t mc; 3260 mbx_cmd_t *mcp = &mc; 3261 3262 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3263 !IS_QLA27XX(vha->hw)) 3264 return QLA_FUNCTION_FAILED; 3265 3266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 3267 "Entered %s.\n", __func__); 3268 3269 mcp->mb[0] = MBC_WRITE_SERDES; 3270 mcp->mb[1] = addr; 3271 if (IS_QLA2031(vha->hw)) 3272 mcp->mb[2] = data & 0xff; 3273 else 3274 mcp->mb[2] = data; 3275 3276 mcp->mb[3] = 0; 3277 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 3278 mcp->in_mb = MBX_0; 3279 mcp->tov = MBX_TOV_SECONDS; 3280 mcp->flags = 0; 3281 rval = qla2x00_mailbox_command(vha, mcp); 3282 3283 if (rval != QLA_SUCCESS) { 3284 ql_dbg(ql_dbg_mbx, vha, 0x1183, 3285 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3286 } else { 3287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 3288 "Done %s.\n", __func__); 3289 } 3290 3291 return rval; 3292 } 3293 3294 int 3295 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 3296 { 3297 int rval; 3298 mbx_cmd_t mc; 3299 mbx_cmd_t *mcp = &mc; 3300 3301 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3302 !IS_QLA27XX(vha->hw)) 3303 return QLA_FUNCTION_FAILED; 3304 3305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 3306 "Entered %s.\n", __func__); 3307 3308 mcp->mb[0] = MBC_READ_SERDES; 3309 mcp->mb[1] = addr; 3310 mcp->mb[3] = 0; 3311 mcp->out_mb = MBX_3|MBX_1|MBX_0; 3312 mcp->in_mb = MBX_1|MBX_0; 3313 mcp->tov = MBX_TOV_SECONDS; 3314 mcp->flags = 0; 3315 rval = qla2x00_mailbox_command(vha, mcp); 3316 3317 if (IS_QLA2031(vha->hw)) 3318 *data = mcp->mb[1] & 0xff; 3319 else 3320 *data = mcp->mb[1]; 3321 3322 if (rval != QLA_SUCCESS) { 3323 ql_dbg(ql_dbg_mbx, vha, 0x1186, 3324 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3325 } else { 3326 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 3327 "Done %s.\n", __func__); 3328 } 3329 3330 return rval; 3331 } 3332 3333 int 3334 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 3335 { 3336 int rval; 3337 mbx_cmd_t mc; 3338 mbx_cmd_t *mcp = &mc; 3339 3340 if (!IS_QLA8044(vha->hw)) 3341 return QLA_FUNCTION_FAILED; 3342 3343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0, 3344 "Entered %s.\n", __func__); 3345 3346 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3347 mcp->mb[1] = HCS_WRITE_SERDES; 3348 mcp->mb[3] = LSW(addr); 3349 mcp->mb[4] = MSW(addr); 3350 mcp->mb[5] = LSW(data); 3351 mcp->mb[6] = MSW(data); 3352 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 3353 mcp->in_mb = MBX_0; 3354 mcp->tov = MBX_TOV_SECONDS; 3355 mcp->flags = 0; 3356 rval = qla2x00_mailbox_command(vha, mcp); 3357 3358 if (rval != QLA_SUCCESS) { 3359 ql_dbg(ql_dbg_mbx, vha, 0x11a1, 3360 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3361 } else { 3362 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 3363 "Done %s.\n", __func__); 3364 } 3365 3366 return rval; 3367 } 3368 3369 int 3370 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 3371 { 3372 int rval; 3373 mbx_cmd_t mc; 3374 mbx_cmd_t *mcp = &mc; 3375 3376 if (!IS_QLA8044(vha->hw)) 3377 return QLA_FUNCTION_FAILED; 3378 3379 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 3380 "Entered %s.\n", __func__); 3381 3382 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3383 mcp->mb[1] = HCS_READ_SERDES; 3384 mcp->mb[3] = LSW(addr); 3385 mcp->mb[4] = MSW(addr); 3386 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 3387 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3388 mcp->tov = MBX_TOV_SECONDS; 3389 mcp->flags = 0; 3390 rval = qla2x00_mailbox_command(vha, mcp); 3391 3392 *data = mcp->mb[2] << 16 | mcp->mb[1]; 3393 3394 if (rval != QLA_SUCCESS) { 3395 ql_dbg(ql_dbg_mbx, vha, 0x118a, 3396 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3397 } else { 3398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3399 "Done %s.\n", __func__); 3400 } 3401 3402 return rval; 3403 } 3404 3405 /** 3406 * qla2x00_set_serdes_params() - 3407 * @vha: HA context 3408 * @sw_em_1g: 3409 * @sw_em_2g: 3410 * @sw_em_4g: 3411 * 3412 * Returns 3413 */ 3414 int 3415 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3416 uint16_t sw_em_2g, uint16_t sw_em_4g) 3417 { 3418 int rval; 3419 mbx_cmd_t mc; 3420 mbx_cmd_t *mcp = &mc; 3421 3422 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3423 "Entered %s.\n", __func__); 3424 3425 mcp->mb[0] = MBC_SERDES_PARAMS; 3426 mcp->mb[1] = BIT_0; 3427 mcp->mb[2] = sw_em_1g | BIT_15; 3428 mcp->mb[3] = sw_em_2g | BIT_15; 3429 mcp->mb[4] = sw_em_4g | BIT_15; 3430 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3431 mcp->in_mb = MBX_0; 3432 mcp->tov = MBX_TOV_SECONDS; 3433 mcp->flags = 0; 3434 rval = qla2x00_mailbox_command(vha, mcp); 3435 3436 if (rval != QLA_SUCCESS) { 3437 /*EMPTY*/ 3438 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3439 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3440 } else { 3441 /*EMPTY*/ 3442 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3443 "Done %s.\n", __func__); 3444 } 3445 3446 return rval; 3447 } 3448 3449 int 3450 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3451 { 3452 int rval; 3453 mbx_cmd_t mc; 3454 mbx_cmd_t *mcp = &mc; 3455 3456 if (!IS_FWI2_CAPABLE(vha->hw)) 3457 return QLA_FUNCTION_FAILED; 3458 3459 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3460 "Entered %s.\n", __func__); 3461 3462 mcp->mb[0] = MBC_STOP_FIRMWARE; 3463 mcp->mb[1] = 0; 3464 mcp->out_mb = MBX_1|MBX_0; 3465 mcp->in_mb = MBX_0; 3466 mcp->tov = 5; 3467 mcp->flags = 0; 3468 rval = qla2x00_mailbox_command(vha, mcp); 3469 3470 if (rval != QLA_SUCCESS) { 3471 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3472 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3473 rval = QLA_INVALID_COMMAND; 3474 } else { 3475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3476 "Done %s.\n", __func__); 3477 } 3478 3479 return rval; 3480 } 3481 3482 int 3483 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3484 uint16_t buffers) 3485 { 3486 int rval; 3487 mbx_cmd_t mc; 3488 mbx_cmd_t *mcp = &mc; 3489 3490 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3491 "Entered %s.\n", __func__); 3492 3493 if (!IS_FWI2_CAPABLE(vha->hw)) 3494 return QLA_FUNCTION_FAILED; 3495 3496 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3497 return QLA_FUNCTION_FAILED; 3498 3499 mcp->mb[0] = MBC_TRACE_CONTROL; 3500 mcp->mb[1] = TC_EFT_ENABLE; 3501 mcp->mb[2] = LSW(eft_dma); 3502 mcp->mb[3] = MSW(eft_dma); 3503 mcp->mb[4] = LSW(MSD(eft_dma)); 3504 mcp->mb[5] = MSW(MSD(eft_dma)); 3505 mcp->mb[6] = buffers; 3506 mcp->mb[7] = TC_AEN_DISABLE; 3507 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3508 mcp->in_mb = MBX_1|MBX_0; 3509 mcp->tov = MBX_TOV_SECONDS; 3510 mcp->flags = 0; 3511 rval = qla2x00_mailbox_command(vha, mcp); 3512 if (rval != QLA_SUCCESS) { 3513 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3514 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3515 rval, mcp->mb[0], mcp->mb[1]); 3516 } else { 3517 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3518 "Done %s.\n", __func__); 3519 } 3520 3521 return rval; 3522 } 3523 3524 int 3525 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3526 { 3527 int rval; 3528 mbx_cmd_t mc; 3529 mbx_cmd_t *mcp = &mc; 3530 3531 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3532 "Entered %s.\n", __func__); 3533 3534 if (!IS_FWI2_CAPABLE(vha->hw)) 3535 return QLA_FUNCTION_FAILED; 3536 3537 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3538 return QLA_FUNCTION_FAILED; 3539 3540 mcp->mb[0] = MBC_TRACE_CONTROL; 3541 mcp->mb[1] = TC_EFT_DISABLE; 3542 mcp->out_mb = MBX_1|MBX_0; 3543 mcp->in_mb = MBX_1|MBX_0; 3544 mcp->tov = MBX_TOV_SECONDS; 3545 mcp->flags = 0; 3546 rval = qla2x00_mailbox_command(vha, mcp); 3547 if (rval != QLA_SUCCESS) { 3548 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3549 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3550 rval, mcp->mb[0], mcp->mb[1]); 3551 } else { 3552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3553 "Done %s.\n", __func__); 3554 } 3555 3556 return rval; 3557 } 3558 3559 int 3560 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3561 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3562 { 3563 int rval; 3564 mbx_cmd_t mc; 3565 mbx_cmd_t *mcp = &mc; 3566 3567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3568 "Entered %s.\n", __func__); 3569 3570 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3571 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3572 return QLA_FUNCTION_FAILED; 3573 3574 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3575 return QLA_FUNCTION_FAILED; 3576 3577 mcp->mb[0] = MBC_TRACE_CONTROL; 3578 mcp->mb[1] = TC_FCE_ENABLE; 3579 mcp->mb[2] = LSW(fce_dma); 3580 mcp->mb[3] = MSW(fce_dma); 3581 mcp->mb[4] = LSW(MSD(fce_dma)); 3582 mcp->mb[5] = MSW(MSD(fce_dma)); 3583 mcp->mb[6] = buffers; 3584 mcp->mb[7] = TC_AEN_DISABLE; 3585 mcp->mb[8] = 0; 3586 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3587 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3588 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3589 MBX_1|MBX_0; 3590 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3591 mcp->tov = MBX_TOV_SECONDS; 3592 mcp->flags = 0; 3593 rval = qla2x00_mailbox_command(vha, mcp); 3594 if (rval != QLA_SUCCESS) { 3595 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3596 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3597 rval, mcp->mb[0], mcp->mb[1]); 3598 } else { 3599 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3600 "Done %s.\n", __func__); 3601 3602 if (mb) 3603 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3604 if (dwords) 3605 *dwords = buffers; 3606 } 3607 3608 return rval; 3609 } 3610 3611 int 3612 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3613 { 3614 int rval; 3615 mbx_cmd_t mc; 3616 mbx_cmd_t *mcp = &mc; 3617 3618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3619 "Entered %s.\n", __func__); 3620 3621 if (!IS_FWI2_CAPABLE(vha->hw)) 3622 return QLA_FUNCTION_FAILED; 3623 3624 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3625 return QLA_FUNCTION_FAILED; 3626 3627 mcp->mb[0] = MBC_TRACE_CONTROL; 3628 mcp->mb[1] = TC_FCE_DISABLE; 3629 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3630 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3631 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3632 MBX_1|MBX_0; 3633 mcp->tov = MBX_TOV_SECONDS; 3634 mcp->flags = 0; 3635 rval = qla2x00_mailbox_command(vha, mcp); 3636 if (rval != QLA_SUCCESS) { 3637 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3638 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3639 rval, mcp->mb[0], mcp->mb[1]); 3640 } else { 3641 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3642 "Done %s.\n", __func__); 3643 3644 if (wr) 3645 *wr = (uint64_t) mcp->mb[5] << 48 | 3646 (uint64_t) mcp->mb[4] << 32 | 3647 (uint64_t) mcp->mb[3] << 16 | 3648 (uint64_t) mcp->mb[2]; 3649 if (rd) 3650 *rd = (uint64_t) mcp->mb[9] << 48 | 3651 (uint64_t) mcp->mb[8] << 32 | 3652 (uint64_t) mcp->mb[7] << 16 | 3653 (uint64_t) mcp->mb[6]; 3654 } 3655 3656 return rval; 3657 } 3658 3659 int 3660 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3661 uint16_t *port_speed, uint16_t *mb) 3662 { 3663 int rval; 3664 mbx_cmd_t mc; 3665 mbx_cmd_t *mcp = &mc; 3666 3667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3668 "Entered %s.\n", __func__); 3669 3670 if (!IS_IIDMA_CAPABLE(vha->hw)) 3671 return QLA_FUNCTION_FAILED; 3672 3673 mcp->mb[0] = MBC_PORT_PARAMS; 3674 mcp->mb[1] = loop_id; 3675 mcp->mb[2] = mcp->mb[3] = 0; 3676 mcp->mb[9] = vha->vp_idx; 3677 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3678 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3679 mcp->tov = MBX_TOV_SECONDS; 3680 mcp->flags = 0; 3681 rval = qla2x00_mailbox_command(vha, mcp); 3682 3683 /* Return mailbox statuses. */ 3684 if (mb != NULL) { 3685 mb[0] = mcp->mb[0]; 3686 mb[1] = mcp->mb[1]; 3687 mb[3] = mcp->mb[3]; 3688 } 3689 3690 if (rval != QLA_SUCCESS) { 3691 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3692 } else { 3693 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3694 "Done %s.\n", __func__); 3695 if (port_speed) 3696 *port_speed = mcp->mb[3]; 3697 } 3698 3699 return rval; 3700 } 3701 3702 int 3703 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3704 uint16_t port_speed, uint16_t *mb) 3705 { 3706 int rval; 3707 mbx_cmd_t mc; 3708 mbx_cmd_t *mcp = &mc; 3709 3710 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3711 "Entered %s.\n", __func__); 3712 3713 if (!IS_IIDMA_CAPABLE(vha->hw)) 3714 return QLA_FUNCTION_FAILED; 3715 3716 mcp->mb[0] = MBC_PORT_PARAMS; 3717 mcp->mb[1] = loop_id; 3718 mcp->mb[2] = BIT_0; 3719 if (IS_CNA_CAPABLE(vha->hw)) 3720 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3721 else 3722 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3723 mcp->mb[9] = vha->vp_idx; 3724 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3725 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3726 mcp->tov = MBX_TOV_SECONDS; 3727 mcp->flags = 0; 3728 rval = qla2x00_mailbox_command(vha, mcp); 3729 3730 /* Return mailbox statuses. */ 3731 if (mb != NULL) { 3732 mb[0] = mcp->mb[0]; 3733 mb[1] = mcp->mb[1]; 3734 mb[3] = mcp->mb[3]; 3735 } 3736 3737 if (rval != QLA_SUCCESS) { 3738 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3739 "Failed=%x.\n", rval); 3740 } else { 3741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3742 "Done %s.\n", __func__); 3743 } 3744 3745 return rval; 3746 } 3747 3748 void 3749 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3750 struct vp_rpt_id_entry_24xx *rptid_entry) 3751 { 3752 struct qla_hw_data *ha = vha->hw; 3753 scsi_qla_host_t *vp = NULL; 3754 unsigned long flags; 3755 int found; 3756 port_id_t id; 3757 struct fc_port *fcport; 3758 3759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3760 "Entered %s.\n", __func__); 3761 3762 if (rptid_entry->entry_status != 0) 3763 return; 3764 3765 id.b.domain = rptid_entry->port_id[2]; 3766 id.b.area = rptid_entry->port_id[1]; 3767 id.b.al_pa = rptid_entry->port_id[0]; 3768 id.b.rsvd_1 = 0; 3769 ha->flags.n2n_ae = 0; 3770 3771 if (rptid_entry->format == 0) { 3772 /* loop */ 3773 ql_dbg(ql_dbg_async, vha, 0x10b7, 3774 "Format 0 : Number of VPs setup %d, number of " 3775 "VPs acquired %d.\n", rptid_entry->vp_setup, 3776 rptid_entry->vp_acquired); 3777 ql_dbg(ql_dbg_async, vha, 0x10b8, 3778 "Primary port id %02x%02x%02x.\n", 3779 rptid_entry->port_id[2], rptid_entry->port_id[1], 3780 rptid_entry->port_id[0]); 3781 ha->current_topology = ISP_CFG_NL; 3782 qlt_update_host_map(vha, id); 3783 3784 } else if (rptid_entry->format == 1) { 3785 /* fabric */ 3786 ql_dbg(ql_dbg_async, vha, 0x10b9, 3787 "Format 1: VP[%d] enabled - status %d - with " 3788 "port id %02x%02x%02x.\n", rptid_entry->vp_idx, 3789 rptid_entry->vp_status, 3790 rptid_entry->port_id[2], rptid_entry->port_id[1], 3791 rptid_entry->port_id[0]); 3792 ql_dbg(ql_dbg_async, vha, 0x5075, 3793 "Format 1: Remote WWPN %8phC.\n", 3794 rptid_entry->u.f1.port_name); 3795 3796 ql_dbg(ql_dbg_async, vha, 0x5075, 3797 "Format 1: WWPN %8phC.\n", 3798 vha->port_name); 3799 3800 /* N2N. direct connect */ 3801 if (IS_QLA27XX(ha) && 3802 ((rptid_entry->u.f1.flags>>1) & 0x7) == 2) { 3803 /* if our portname is higher then initiate N2N login */ 3804 if (wwn_to_u64(vha->port_name) > 3805 wwn_to_u64(rptid_entry->u.f1.port_name)) { 3806 // ??? qlt_update_host_map(vha, id); 3807 vha->n2n_id = 0x1; 3808 ql_dbg(ql_dbg_async, vha, 0x5075, 3809 "Format 1: Setting n2n_update_needed for id %d\n", 3810 vha->n2n_id); 3811 } else { 3812 ql_dbg(ql_dbg_async, vha, 0x5075, 3813 "Format 1: Remote login - Waiting for WWPN %8phC.\n", 3814 rptid_entry->u.f1.port_name); 3815 } 3816 3817 memcpy(vha->n2n_port_name, rptid_entry->u.f1.port_name, 3818 WWN_SIZE); 3819 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags); 3820 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags); 3821 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags); 3822 ha->flags.n2n_ae = 1; 3823 return; 3824 } 3825 3826 ha->flags.gpsc_supported = 1; 3827 ha->current_topology = ISP_CFG_F; 3828 /* buffer to buffer credit flag */ 3829 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0; 3830 3831 if (rptid_entry->vp_idx == 0) { 3832 if (rptid_entry->vp_status == VP_STAT_COMPL) { 3833 /* FA-WWN is only for physical port */ 3834 if (qla_ini_mode_enabled(vha) && 3835 ha->flags.fawwpn_enabled && 3836 (rptid_entry->u.f1.flags & 3837 BIT_6)) { 3838 memcpy(vha->port_name, 3839 rptid_entry->u.f1.port_name, 3840 WWN_SIZE); 3841 } 3842 3843 qlt_update_host_map(vha, id); 3844 } 3845 3846 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags); 3847 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags); 3848 } else { 3849 if (rptid_entry->vp_status != VP_STAT_COMPL && 3850 rptid_entry->vp_status != VP_STAT_ID_CHG) { 3851 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3852 "Could not acquire ID for VP[%d].\n", 3853 rptid_entry->vp_idx); 3854 return; 3855 } 3856 3857 found = 0; 3858 spin_lock_irqsave(&ha->vport_slock, flags); 3859 list_for_each_entry(vp, &ha->vp_list, list) { 3860 if (rptid_entry->vp_idx == vp->vp_idx) { 3861 found = 1; 3862 break; 3863 } 3864 } 3865 spin_unlock_irqrestore(&ha->vport_slock, flags); 3866 3867 if (!found) 3868 return; 3869 3870 qlt_update_host_map(vp, id); 3871 3872 /* 3873 * Cannot configure here as we are still sitting on the 3874 * response queue. Handle it in dpc context. 3875 */ 3876 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3877 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3878 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3879 } 3880 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3881 qla2xxx_wake_dpc(vha); 3882 } else if (rptid_entry->format == 2) { 3883 ql_dbg(ql_dbg_async, vha, 0x505f, 3884 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n", 3885 rptid_entry->port_id[2], rptid_entry->port_id[1], 3886 rptid_entry->port_id[0]); 3887 3888 ql_dbg(ql_dbg_async, vha, 0x5075, 3889 "N2N: Remote WWPN %8phC.\n", 3890 rptid_entry->u.f2.port_name); 3891 3892 /* N2N. direct connect */ 3893 ha->current_topology = ISP_CFG_N; 3894 ha->flags.rida_fmt2 = 1; 3895 vha->d_id.b.domain = rptid_entry->port_id[2]; 3896 vha->d_id.b.area = rptid_entry->port_id[1]; 3897 vha->d_id.b.al_pa = rptid_entry->port_id[0]; 3898 3899 ha->flags.n2n_ae = 1; 3900 spin_lock_irqsave(&ha->vport_slock, flags); 3901 qlt_update_vp_map(vha, SET_AL_PA); 3902 spin_unlock_irqrestore(&ha->vport_slock, flags); 3903 3904 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3905 fcport->scan_state = QLA_FCPORT_SCAN; 3906 } 3907 3908 fcport = qla2x00_find_fcport_by_wwpn(vha, 3909 rptid_entry->u.f2.port_name, 1); 3910 3911 if (fcport) { 3912 fcport->plogi_nack_done_deadline = jiffies + HZ; 3913 fcport->scan_state = QLA_FCPORT_FOUND; 3914 switch (fcport->disc_state) { 3915 case DSC_DELETED: 3916 ql_dbg(ql_dbg_disc, vha, 0x210d, 3917 "%s %d %8phC login\n", 3918 __func__, __LINE__, fcport->port_name); 3919 qla24xx_fcport_handle_login(vha, fcport); 3920 break; 3921 case DSC_DELETE_PEND: 3922 break; 3923 default: 3924 qlt_schedule_sess_for_deletion(fcport); 3925 break; 3926 } 3927 } else { 3928 id.b.al_pa = rptid_entry->u.f2.remote_nport_id[0]; 3929 id.b.area = rptid_entry->u.f2.remote_nport_id[1]; 3930 id.b.domain = rptid_entry->u.f2.remote_nport_id[2]; 3931 qla24xx_post_newsess_work(vha, &id, 3932 rptid_entry->u.f2.port_name, 3933 rptid_entry->u.f2.node_name, 3934 NULL, 3935 FC4_TYPE_UNKNOWN); 3936 } 3937 } 3938 } 3939 3940 /* 3941 * qla24xx_modify_vp_config 3942 * Change VP configuration for vha 3943 * 3944 * Input: 3945 * vha = adapter block pointer. 3946 * 3947 * Returns: 3948 * qla2xxx local function return status code. 3949 * 3950 * Context: 3951 * Kernel context. 3952 */ 3953 int 3954 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3955 { 3956 int rval; 3957 struct vp_config_entry_24xx *vpmod; 3958 dma_addr_t vpmod_dma; 3959 struct qla_hw_data *ha = vha->hw; 3960 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3961 3962 /* This can be called by the parent */ 3963 3964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3965 "Entered %s.\n", __func__); 3966 3967 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3968 if (!vpmod) { 3969 ql_log(ql_log_warn, vha, 0x10bc, 3970 "Failed to allocate modify VP IOCB.\n"); 3971 return QLA_MEMORY_ALLOC_FAILED; 3972 } 3973 3974 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3975 vpmod->entry_count = 1; 3976 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3977 vpmod->vp_count = 1; 3978 vpmod->vp_index1 = vha->vp_idx; 3979 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3980 3981 qlt_modify_vp_config(vha, vpmod); 3982 3983 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3984 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3985 vpmod->entry_count = 1; 3986 3987 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3988 if (rval != QLA_SUCCESS) { 3989 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3990 "Failed to issue VP config IOCB (%x).\n", rval); 3991 } else if (vpmod->comp_status != 0) { 3992 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3993 "Failed to complete IOCB -- error status (%x).\n", 3994 vpmod->comp_status); 3995 rval = QLA_FUNCTION_FAILED; 3996 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 3997 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3998 "Failed to complete IOCB -- completion status (%x).\n", 3999 le16_to_cpu(vpmod->comp_status)); 4000 rval = QLA_FUNCTION_FAILED; 4001 } else { 4002 /* EMPTY */ 4003 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 4004 "Done %s.\n", __func__); 4005 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 4006 } 4007 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 4008 4009 return rval; 4010 } 4011 4012 /* 4013 * qla2x00_send_change_request 4014 * Receive or disable RSCN request from fabric controller 4015 * 4016 * Input: 4017 * ha = adapter block pointer 4018 * format = registration format: 4019 * 0 - Reserved 4020 * 1 - Fabric detected registration 4021 * 2 - N_port detected registration 4022 * 3 - Full registration 4023 * FF - clear registration 4024 * vp_idx = Virtual port index 4025 * 4026 * Returns: 4027 * qla2x00 local function return status code. 4028 * 4029 * Context: 4030 * Kernel Context 4031 */ 4032 4033 int 4034 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 4035 uint16_t vp_idx) 4036 { 4037 int rval; 4038 mbx_cmd_t mc; 4039 mbx_cmd_t *mcp = &mc; 4040 4041 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 4042 "Entered %s.\n", __func__); 4043 4044 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 4045 mcp->mb[1] = format; 4046 mcp->mb[9] = vp_idx; 4047 mcp->out_mb = MBX_9|MBX_1|MBX_0; 4048 mcp->in_mb = MBX_0|MBX_1; 4049 mcp->tov = MBX_TOV_SECONDS; 4050 mcp->flags = 0; 4051 rval = qla2x00_mailbox_command(vha, mcp); 4052 4053 if (rval == QLA_SUCCESS) { 4054 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 4055 rval = BIT_1; 4056 } 4057 } else 4058 rval = BIT_1; 4059 4060 return rval; 4061 } 4062 4063 int 4064 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 4065 uint32_t size) 4066 { 4067 int rval; 4068 mbx_cmd_t mc; 4069 mbx_cmd_t *mcp = &mc; 4070 4071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 4072 "Entered %s.\n", __func__); 4073 4074 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 4075 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 4076 mcp->mb[8] = MSW(addr); 4077 mcp->out_mb = MBX_8|MBX_0; 4078 } else { 4079 mcp->mb[0] = MBC_DUMP_RISC_RAM; 4080 mcp->out_mb = MBX_0; 4081 } 4082 mcp->mb[1] = LSW(addr); 4083 mcp->mb[2] = MSW(req_dma); 4084 mcp->mb[3] = LSW(req_dma); 4085 mcp->mb[6] = MSW(MSD(req_dma)); 4086 mcp->mb[7] = LSW(MSD(req_dma)); 4087 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 4088 if (IS_FWI2_CAPABLE(vha->hw)) { 4089 mcp->mb[4] = MSW(size); 4090 mcp->mb[5] = LSW(size); 4091 mcp->out_mb |= MBX_5|MBX_4; 4092 } else { 4093 mcp->mb[4] = LSW(size); 4094 mcp->out_mb |= MBX_4; 4095 } 4096 4097 mcp->in_mb = MBX_0; 4098 mcp->tov = MBX_TOV_SECONDS; 4099 mcp->flags = 0; 4100 rval = qla2x00_mailbox_command(vha, mcp); 4101 4102 if (rval != QLA_SUCCESS) { 4103 ql_dbg(ql_dbg_mbx, vha, 0x1008, 4104 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4105 } else { 4106 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 4107 "Done %s.\n", __func__); 4108 } 4109 4110 return rval; 4111 } 4112 /* 84XX Support **************************************************************/ 4113 4114 struct cs84xx_mgmt_cmd { 4115 union { 4116 struct verify_chip_entry_84xx req; 4117 struct verify_chip_rsp_84xx rsp; 4118 } p; 4119 }; 4120 4121 int 4122 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 4123 { 4124 int rval, retry; 4125 struct cs84xx_mgmt_cmd *mn; 4126 dma_addr_t mn_dma; 4127 uint16_t options; 4128 unsigned long flags; 4129 struct qla_hw_data *ha = vha->hw; 4130 4131 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 4132 "Entered %s.\n", __func__); 4133 4134 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 4135 if (mn == NULL) { 4136 return QLA_MEMORY_ALLOC_FAILED; 4137 } 4138 4139 /* Force Update? */ 4140 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 4141 /* Diagnostic firmware? */ 4142 /* options |= MENLO_DIAG_FW; */ 4143 /* We update the firmware with only one data sequence. */ 4144 options |= VCO_END_OF_DATA; 4145 4146 do { 4147 retry = 0; 4148 memset(mn, 0, sizeof(*mn)); 4149 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 4150 mn->p.req.entry_count = 1; 4151 mn->p.req.options = cpu_to_le16(options); 4152 4153 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 4154 "Dump of Verify Request.\n"); 4155 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 4156 (uint8_t *)mn, sizeof(*mn)); 4157 4158 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 4159 if (rval != QLA_SUCCESS) { 4160 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 4161 "Failed to issue verify IOCB (%x).\n", rval); 4162 goto verify_done; 4163 } 4164 4165 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 4166 "Dump of Verify Response.\n"); 4167 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 4168 (uint8_t *)mn, sizeof(*mn)); 4169 4170 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 4171 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 4172 le16_to_cpu(mn->p.rsp.failure_code) : 0; 4173 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 4174 "cs=%x fc=%x.\n", status[0], status[1]); 4175 4176 if (status[0] != CS_COMPLETE) { 4177 rval = QLA_FUNCTION_FAILED; 4178 if (!(options & VCO_DONT_UPDATE_FW)) { 4179 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 4180 "Firmware update failed. Retrying " 4181 "without update firmware.\n"); 4182 options |= VCO_DONT_UPDATE_FW; 4183 options &= ~VCO_FORCE_UPDATE; 4184 retry = 1; 4185 } 4186 } else { 4187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 4188 "Firmware updated to %x.\n", 4189 le32_to_cpu(mn->p.rsp.fw_ver)); 4190 4191 /* NOTE: we only update OP firmware. */ 4192 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 4193 ha->cs84xx->op_fw_version = 4194 le32_to_cpu(mn->p.rsp.fw_ver); 4195 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 4196 flags); 4197 } 4198 } while (retry); 4199 4200 verify_done: 4201 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 4202 4203 if (rval != QLA_SUCCESS) { 4204 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 4205 "Failed=%x.\n", rval); 4206 } else { 4207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 4208 "Done %s.\n", __func__); 4209 } 4210 4211 return rval; 4212 } 4213 4214 int 4215 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 4216 { 4217 int rval; 4218 unsigned long flags; 4219 mbx_cmd_t mc; 4220 mbx_cmd_t *mcp = &mc; 4221 struct qla_hw_data *ha = vha->hw; 4222 4223 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 4224 "Entered %s.\n", __func__); 4225 4226 if (IS_SHADOW_REG_CAPABLE(ha)) 4227 req->options |= BIT_13; 4228 4229 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4230 mcp->mb[1] = req->options; 4231 mcp->mb[2] = MSW(LSD(req->dma)); 4232 mcp->mb[3] = LSW(LSD(req->dma)); 4233 mcp->mb[6] = MSW(MSD(req->dma)); 4234 mcp->mb[7] = LSW(MSD(req->dma)); 4235 mcp->mb[5] = req->length; 4236 if (req->rsp) 4237 mcp->mb[10] = req->rsp->id; 4238 mcp->mb[12] = req->qos; 4239 mcp->mb[11] = req->vp_idx; 4240 mcp->mb[13] = req->rid; 4241 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4242 mcp->mb[15] = 0; 4243 4244 mcp->mb[4] = req->id; 4245 /* que in ptr index */ 4246 mcp->mb[8] = 0; 4247 /* que out ptr index */ 4248 mcp->mb[9] = *req->out_ptr = 0; 4249 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 4250 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4251 mcp->in_mb = MBX_0; 4252 mcp->flags = MBX_DMA_OUT; 4253 mcp->tov = MBX_TOV_SECONDS * 2; 4254 4255 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4256 mcp->in_mb |= MBX_1; 4257 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4258 mcp->out_mb |= MBX_15; 4259 /* debug q create issue in SR-IOV */ 4260 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4261 } 4262 4263 spin_lock_irqsave(&ha->hardware_lock, flags); 4264 if (!(req->options & BIT_0)) { 4265 WRT_REG_DWORD(req->req_q_in, 0); 4266 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4267 WRT_REG_DWORD(req->req_q_out, 0); 4268 } 4269 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4270 4271 rval = qla2x00_mailbox_command(vha, mcp); 4272 if (rval != QLA_SUCCESS) { 4273 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 4274 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4275 } else { 4276 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 4277 "Done %s.\n", __func__); 4278 } 4279 4280 return rval; 4281 } 4282 4283 int 4284 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 4285 { 4286 int rval; 4287 unsigned long flags; 4288 mbx_cmd_t mc; 4289 mbx_cmd_t *mcp = &mc; 4290 struct qla_hw_data *ha = vha->hw; 4291 4292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 4293 "Entered %s.\n", __func__); 4294 4295 if (IS_SHADOW_REG_CAPABLE(ha)) 4296 rsp->options |= BIT_13; 4297 4298 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4299 mcp->mb[1] = rsp->options; 4300 mcp->mb[2] = MSW(LSD(rsp->dma)); 4301 mcp->mb[3] = LSW(LSD(rsp->dma)); 4302 mcp->mb[6] = MSW(MSD(rsp->dma)); 4303 mcp->mb[7] = LSW(MSD(rsp->dma)); 4304 mcp->mb[5] = rsp->length; 4305 mcp->mb[14] = rsp->msix->entry; 4306 mcp->mb[13] = rsp->rid; 4307 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4308 mcp->mb[15] = 0; 4309 4310 mcp->mb[4] = rsp->id; 4311 /* que in ptr index */ 4312 mcp->mb[8] = *rsp->in_ptr = 0; 4313 /* que out ptr index */ 4314 mcp->mb[9] = 0; 4315 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 4316 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4317 mcp->in_mb = MBX_0; 4318 mcp->flags = MBX_DMA_OUT; 4319 mcp->tov = MBX_TOV_SECONDS * 2; 4320 4321 if (IS_QLA81XX(ha)) { 4322 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 4323 mcp->in_mb |= MBX_1; 4324 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4325 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 4326 mcp->in_mb |= MBX_1; 4327 /* debug q create issue in SR-IOV */ 4328 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4329 } 4330 4331 spin_lock_irqsave(&ha->hardware_lock, flags); 4332 if (!(rsp->options & BIT_0)) { 4333 WRT_REG_DWORD(rsp->rsp_q_out, 0); 4334 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4335 WRT_REG_DWORD(rsp->rsp_q_in, 0); 4336 } 4337 4338 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4339 4340 rval = qla2x00_mailbox_command(vha, mcp); 4341 if (rval != QLA_SUCCESS) { 4342 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 4343 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4344 } else { 4345 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 4346 "Done %s.\n", __func__); 4347 } 4348 4349 return rval; 4350 } 4351 4352 int 4353 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 4354 { 4355 int rval; 4356 mbx_cmd_t mc; 4357 mbx_cmd_t *mcp = &mc; 4358 4359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 4360 "Entered %s.\n", __func__); 4361 4362 mcp->mb[0] = MBC_IDC_ACK; 4363 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4364 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4365 mcp->in_mb = MBX_0; 4366 mcp->tov = MBX_TOV_SECONDS; 4367 mcp->flags = 0; 4368 rval = qla2x00_mailbox_command(vha, mcp); 4369 4370 if (rval != QLA_SUCCESS) { 4371 ql_dbg(ql_dbg_mbx, vha, 0x10da, 4372 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4373 } else { 4374 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 4375 "Done %s.\n", __func__); 4376 } 4377 4378 return rval; 4379 } 4380 4381 int 4382 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 4383 { 4384 int rval; 4385 mbx_cmd_t mc; 4386 mbx_cmd_t *mcp = &mc; 4387 4388 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 4389 "Entered %s.\n", __func__); 4390 4391 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4392 !IS_QLA27XX(vha->hw)) 4393 return QLA_FUNCTION_FAILED; 4394 4395 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4396 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 4397 mcp->out_mb = MBX_1|MBX_0; 4398 mcp->in_mb = MBX_1|MBX_0; 4399 mcp->tov = MBX_TOV_SECONDS; 4400 mcp->flags = 0; 4401 rval = qla2x00_mailbox_command(vha, mcp); 4402 4403 if (rval != QLA_SUCCESS) { 4404 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 4405 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4406 rval, mcp->mb[0], mcp->mb[1]); 4407 } else { 4408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 4409 "Done %s.\n", __func__); 4410 *sector_size = mcp->mb[1]; 4411 } 4412 4413 return rval; 4414 } 4415 4416 int 4417 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 4418 { 4419 int rval; 4420 mbx_cmd_t mc; 4421 mbx_cmd_t *mcp = &mc; 4422 4423 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4424 !IS_QLA27XX(vha->hw)) 4425 return QLA_FUNCTION_FAILED; 4426 4427 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4428 "Entered %s.\n", __func__); 4429 4430 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4431 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4432 FAC_OPT_CMD_WRITE_PROTECT; 4433 mcp->out_mb = MBX_1|MBX_0; 4434 mcp->in_mb = MBX_1|MBX_0; 4435 mcp->tov = MBX_TOV_SECONDS; 4436 mcp->flags = 0; 4437 rval = qla2x00_mailbox_command(vha, mcp); 4438 4439 if (rval != QLA_SUCCESS) { 4440 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4441 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4442 rval, mcp->mb[0], mcp->mb[1]); 4443 } else { 4444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4445 "Done %s.\n", __func__); 4446 } 4447 4448 return rval; 4449 } 4450 4451 int 4452 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4453 { 4454 int rval; 4455 mbx_cmd_t mc; 4456 mbx_cmd_t *mcp = &mc; 4457 4458 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4459 !IS_QLA27XX(vha->hw)) 4460 return QLA_FUNCTION_FAILED; 4461 4462 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4463 "Entered %s.\n", __func__); 4464 4465 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4466 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4467 mcp->mb[2] = LSW(start); 4468 mcp->mb[3] = MSW(start); 4469 mcp->mb[4] = LSW(finish); 4470 mcp->mb[5] = MSW(finish); 4471 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4472 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4473 mcp->tov = MBX_TOV_SECONDS; 4474 mcp->flags = 0; 4475 rval = qla2x00_mailbox_command(vha, mcp); 4476 4477 if (rval != QLA_SUCCESS) { 4478 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4479 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4480 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4481 } else { 4482 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4483 "Done %s.\n", __func__); 4484 } 4485 4486 return rval; 4487 } 4488 4489 int 4490 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4491 { 4492 int rval = 0; 4493 mbx_cmd_t mc; 4494 mbx_cmd_t *mcp = &mc; 4495 4496 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4497 "Entered %s.\n", __func__); 4498 4499 mcp->mb[0] = MBC_RESTART_MPI_FW; 4500 mcp->out_mb = MBX_0; 4501 mcp->in_mb = MBX_0|MBX_1; 4502 mcp->tov = MBX_TOV_SECONDS; 4503 mcp->flags = 0; 4504 rval = qla2x00_mailbox_command(vha, mcp); 4505 4506 if (rval != QLA_SUCCESS) { 4507 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4508 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4509 rval, mcp->mb[0], mcp->mb[1]); 4510 } else { 4511 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4512 "Done %s.\n", __func__); 4513 } 4514 4515 return rval; 4516 } 4517 4518 int 4519 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4520 { 4521 int rval; 4522 mbx_cmd_t mc; 4523 mbx_cmd_t *mcp = &mc; 4524 int i; 4525 int len; 4526 uint16_t *str; 4527 struct qla_hw_data *ha = vha->hw; 4528 4529 if (!IS_P3P_TYPE(ha)) 4530 return QLA_FUNCTION_FAILED; 4531 4532 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4533 "Entered %s.\n", __func__); 4534 4535 str = (void *)version; 4536 len = strlen(version); 4537 4538 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4539 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4540 mcp->out_mb = MBX_1|MBX_0; 4541 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4542 mcp->mb[i] = cpu_to_le16p(str); 4543 mcp->out_mb |= 1<<i; 4544 } 4545 for (; i < 16; i++) { 4546 mcp->mb[i] = 0; 4547 mcp->out_mb |= 1<<i; 4548 } 4549 mcp->in_mb = MBX_1|MBX_0; 4550 mcp->tov = MBX_TOV_SECONDS; 4551 mcp->flags = 0; 4552 rval = qla2x00_mailbox_command(vha, mcp); 4553 4554 if (rval != QLA_SUCCESS) { 4555 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4556 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4557 } else { 4558 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4559 "Done %s.\n", __func__); 4560 } 4561 4562 return rval; 4563 } 4564 4565 int 4566 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4567 { 4568 int rval; 4569 mbx_cmd_t mc; 4570 mbx_cmd_t *mcp = &mc; 4571 int len; 4572 uint16_t dwlen; 4573 uint8_t *str; 4574 dma_addr_t str_dma; 4575 struct qla_hw_data *ha = vha->hw; 4576 4577 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4578 IS_P3P_TYPE(ha)) 4579 return QLA_FUNCTION_FAILED; 4580 4581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4582 "Entered %s.\n", __func__); 4583 4584 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4585 if (!str) { 4586 ql_log(ql_log_warn, vha, 0x117f, 4587 "Failed to allocate driver version param.\n"); 4588 return QLA_MEMORY_ALLOC_FAILED; 4589 } 4590 4591 memcpy(str, "\x7\x3\x11\x0", 4); 4592 dwlen = str[0]; 4593 len = dwlen * 4 - 4; 4594 memset(str + 4, 0, len); 4595 if (len > strlen(version)) 4596 len = strlen(version); 4597 memcpy(str + 4, version, len); 4598 4599 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4600 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4601 mcp->mb[2] = MSW(LSD(str_dma)); 4602 mcp->mb[3] = LSW(LSD(str_dma)); 4603 mcp->mb[6] = MSW(MSD(str_dma)); 4604 mcp->mb[7] = LSW(MSD(str_dma)); 4605 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4606 mcp->in_mb = MBX_1|MBX_0; 4607 mcp->tov = MBX_TOV_SECONDS; 4608 mcp->flags = 0; 4609 rval = qla2x00_mailbox_command(vha, mcp); 4610 4611 if (rval != QLA_SUCCESS) { 4612 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4613 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4614 } else { 4615 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4616 "Done %s.\n", __func__); 4617 } 4618 4619 dma_pool_free(ha->s_dma_pool, str, str_dma); 4620 4621 return rval; 4622 } 4623 4624 int 4625 qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma, 4626 void *buf, uint16_t bufsiz) 4627 { 4628 int rval, i; 4629 mbx_cmd_t mc; 4630 mbx_cmd_t *mcp = &mc; 4631 uint32_t *bp; 4632 4633 if (!IS_FWI2_CAPABLE(vha->hw)) 4634 return QLA_FUNCTION_FAILED; 4635 4636 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4637 "Entered %s.\n", __func__); 4638 4639 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4640 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8; 4641 mcp->mb[2] = MSW(buf_dma); 4642 mcp->mb[3] = LSW(buf_dma); 4643 mcp->mb[6] = MSW(MSD(buf_dma)); 4644 mcp->mb[7] = LSW(MSD(buf_dma)); 4645 mcp->mb[8] = bufsiz/4; 4646 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4647 mcp->in_mb = MBX_1|MBX_0; 4648 mcp->tov = MBX_TOV_SECONDS; 4649 mcp->flags = 0; 4650 rval = qla2x00_mailbox_command(vha, mcp); 4651 4652 if (rval != QLA_SUCCESS) { 4653 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4654 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4655 } else { 4656 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4657 "Done %s.\n", __func__); 4658 bp = (uint32_t *) buf; 4659 for (i = 0; i < (bufsiz-4)/4; i++, bp++) 4660 *bp = cpu_to_be32(*bp); 4661 } 4662 4663 return rval; 4664 } 4665 4666 static int 4667 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4668 { 4669 int rval; 4670 mbx_cmd_t mc; 4671 mbx_cmd_t *mcp = &mc; 4672 4673 if (!IS_FWI2_CAPABLE(vha->hw)) 4674 return QLA_FUNCTION_FAILED; 4675 4676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4677 "Entered %s.\n", __func__); 4678 4679 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4680 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4681 mcp->out_mb = MBX_1|MBX_0; 4682 mcp->in_mb = MBX_1|MBX_0; 4683 mcp->tov = MBX_TOV_SECONDS; 4684 mcp->flags = 0; 4685 rval = qla2x00_mailbox_command(vha, mcp); 4686 *temp = mcp->mb[1]; 4687 4688 if (rval != QLA_SUCCESS) { 4689 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4690 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4691 } else { 4692 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4693 "Done %s.\n", __func__); 4694 } 4695 4696 return rval; 4697 } 4698 4699 int 4700 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4701 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4702 { 4703 int rval; 4704 mbx_cmd_t mc; 4705 mbx_cmd_t *mcp = &mc; 4706 struct qla_hw_data *ha = vha->hw; 4707 4708 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4709 "Entered %s.\n", __func__); 4710 4711 if (!IS_FWI2_CAPABLE(ha)) 4712 return QLA_FUNCTION_FAILED; 4713 4714 if (len == 1) 4715 opt |= BIT_0; 4716 4717 mcp->mb[0] = MBC_READ_SFP; 4718 mcp->mb[1] = dev; 4719 mcp->mb[2] = MSW(sfp_dma); 4720 mcp->mb[3] = LSW(sfp_dma); 4721 mcp->mb[6] = MSW(MSD(sfp_dma)); 4722 mcp->mb[7] = LSW(MSD(sfp_dma)); 4723 mcp->mb[8] = len; 4724 mcp->mb[9] = off; 4725 mcp->mb[10] = opt; 4726 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4727 mcp->in_mb = MBX_1|MBX_0; 4728 mcp->tov = MBX_TOV_SECONDS; 4729 mcp->flags = 0; 4730 rval = qla2x00_mailbox_command(vha, mcp); 4731 4732 if (opt & BIT_0) 4733 *sfp = mcp->mb[1]; 4734 4735 if (rval != QLA_SUCCESS) { 4736 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4737 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4738 if (mcp->mb[0] == MBS_COMMAND_ERROR && 4739 mcp->mb[1] == 0x22) 4740 /* sfp is not there */ 4741 rval = QLA_INTERFACE_ERROR; 4742 } else { 4743 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4744 "Done %s.\n", __func__); 4745 } 4746 4747 return rval; 4748 } 4749 4750 int 4751 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4752 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4753 { 4754 int rval; 4755 mbx_cmd_t mc; 4756 mbx_cmd_t *mcp = &mc; 4757 struct qla_hw_data *ha = vha->hw; 4758 4759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4760 "Entered %s.\n", __func__); 4761 4762 if (!IS_FWI2_CAPABLE(ha)) 4763 return QLA_FUNCTION_FAILED; 4764 4765 if (len == 1) 4766 opt |= BIT_0; 4767 4768 if (opt & BIT_0) 4769 len = *sfp; 4770 4771 mcp->mb[0] = MBC_WRITE_SFP; 4772 mcp->mb[1] = dev; 4773 mcp->mb[2] = MSW(sfp_dma); 4774 mcp->mb[3] = LSW(sfp_dma); 4775 mcp->mb[6] = MSW(MSD(sfp_dma)); 4776 mcp->mb[7] = LSW(MSD(sfp_dma)); 4777 mcp->mb[8] = len; 4778 mcp->mb[9] = off; 4779 mcp->mb[10] = opt; 4780 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4781 mcp->in_mb = MBX_1|MBX_0; 4782 mcp->tov = MBX_TOV_SECONDS; 4783 mcp->flags = 0; 4784 rval = qla2x00_mailbox_command(vha, mcp); 4785 4786 if (rval != QLA_SUCCESS) { 4787 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4788 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4789 } else { 4790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4791 "Done %s.\n", __func__); 4792 } 4793 4794 return rval; 4795 } 4796 4797 int 4798 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4799 uint16_t size_in_bytes, uint16_t *actual_size) 4800 { 4801 int rval; 4802 mbx_cmd_t mc; 4803 mbx_cmd_t *mcp = &mc; 4804 4805 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4806 "Entered %s.\n", __func__); 4807 4808 if (!IS_CNA_CAPABLE(vha->hw)) 4809 return QLA_FUNCTION_FAILED; 4810 4811 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4812 mcp->mb[2] = MSW(stats_dma); 4813 mcp->mb[3] = LSW(stats_dma); 4814 mcp->mb[6] = MSW(MSD(stats_dma)); 4815 mcp->mb[7] = LSW(MSD(stats_dma)); 4816 mcp->mb[8] = size_in_bytes >> 2; 4817 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4818 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4819 mcp->tov = MBX_TOV_SECONDS; 4820 mcp->flags = 0; 4821 rval = qla2x00_mailbox_command(vha, mcp); 4822 4823 if (rval != QLA_SUCCESS) { 4824 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4825 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4826 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4827 } else { 4828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4829 "Done %s.\n", __func__); 4830 4831 4832 *actual_size = mcp->mb[2] << 2; 4833 } 4834 4835 return rval; 4836 } 4837 4838 int 4839 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4840 uint16_t size) 4841 { 4842 int rval; 4843 mbx_cmd_t mc; 4844 mbx_cmd_t *mcp = &mc; 4845 4846 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4847 "Entered %s.\n", __func__); 4848 4849 if (!IS_CNA_CAPABLE(vha->hw)) 4850 return QLA_FUNCTION_FAILED; 4851 4852 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4853 mcp->mb[1] = 0; 4854 mcp->mb[2] = MSW(tlv_dma); 4855 mcp->mb[3] = LSW(tlv_dma); 4856 mcp->mb[6] = MSW(MSD(tlv_dma)); 4857 mcp->mb[7] = LSW(MSD(tlv_dma)); 4858 mcp->mb[8] = size; 4859 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4860 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4861 mcp->tov = MBX_TOV_SECONDS; 4862 mcp->flags = 0; 4863 rval = qla2x00_mailbox_command(vha, mcp); 4864 4865 if (rval != QLA_SUCCESS) { 4866 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4867 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4868 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4869 } else { 4870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4871 "Done %s.\n", __func__); 4872 } 4873 4874 return rval; 4875 } 4876 4877 int 4878 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4879 { 4880 int rval; 4881 mbx_cmd_t mc; 4882 mbx_cmd_t *mcp = &mc; 4883 4884 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4885 "Entered %s.\n", __func__); 4886 4887 if (!IS_FWI2_CAPABLE(vha->hw)) 4888 return QLA_FUNCTION_FAILED; 4889 4890 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4891 mcp->mb[1] = LSW(risc_addr); 4892 mcp->mb[8] = MSW(risc_addr); 4893 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4894 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4895 mcp->tov = 30; 4896 mcp->flags = 0; 4897 rval = qla2x00_mailbox_command(vha, mcp); 4898 if (rval != QLA_SUCCESS) { 4899 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4900 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4901 } else { 4902 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4903 "Done %s.\n", __func__); 4904 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4905 } 4906 4907 return rval; 4908 } 4909 4910 int 4911 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4912 uint16_t *mresp) 4913 { 4914 int rval; 4915 mbx_cmd_t mc; 4916 mbx_cmd_t *mcp = &mc; 4917 4918 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4919 "Entered %s.\n", __func__); 4920 4921 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4922 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4923 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4924 4925 /* transfer count */ 4926 mcp->mb[10] = LSW(mreq->transfer_size); 4927 mcp->mb[11] = MSW(mreq->transfer_size); 4928 4929 /* send data address */ 4930 mcp->mb[14] = LSW(mreq->send_dma); 4931 mcp->mb[15] = MSW(mreq->send_dma); 4932 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4933 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4934 4935 /* receive data address */ 4936 mcp->mb[16] = LSW(mreq->rcv_dma); 4937 mcp->mb[17] = MSW(mreq->rcv_dma); 4938 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4939 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4940 4941 /* Iteration count */ 4942 mcp->mb[18] = LSW(mreq->iteration_count); 4943 mcp->mb[19] = MSW(mreq->iteration_count); 4944 4945 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4946 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4947 if (IS_CNA_CAPABLE(vha->hw)) 4948 mcp->out_mb |= MBX_2; 4949 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4950 4951 mcp->buf_size = mreq->transfer_size; 4952 mcp->tov = MBX_TOV_SECONDS; 4953 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4954 4955 rval = qla2x00_mailbox_command(vha, mcp); 4956 4957 if (rval != QLA_SUCCESS) { 4958 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4959 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4960 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4961 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4962 } else { 4963 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4964 "Done %s.\n", __func__); 4965 } 4966 4967 /* Copy mailbox information */ 4968 memcpy( mresp, mcp->mb, 64); 4969 return rval; 4970 } 4971 4972 int 4973 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4974 uint16_t *mresp) 4975 { 4976 int rval; 4977 mbx_cmd_t mc; 4978 mbx_cmd_t *mcp = &mc; 4979 struct qla_hw_data *ha = vha->hw; 4980 4981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4982 "Entered %s.\n", __func__); 4983 4984 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4985 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4986 /* BIT_6 specifies 64bit address */ 4987 mcp->mb[1] = mreq->options | BIT_15 | BIT_6; 4988 if (IS_CNA_CAPABLE(ha)) { 4989 mcp->mb[2] = vha->fcoe_fcf_idx; 4990 } 4991 mcp->mb[16] = LSW(mreq->rcv_dma); 4992 mcp->mb[17] = MSW(mreq->rcv_dma); 4993 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4994 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4995 4996 mcp->mb[10] = LSW(mreq->transfer_size); 4997 4998 mcp->mb[14] = LSW(mreq->send_dma); 4999 mcp->mb[15] = MSW(mreq->send_dma); 5000 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 5001 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 5002 5003 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 5004 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 5005 if (IS_CNA_CAPABLE(ha)) 5006 mcp->out_mb |= MBX_2; 5007 5008 mcp->in_mb = MBX_0; 5009 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 5010 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 5011 mcp->in_mb |= MBX_1; 5012 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 5013 mcp->in_mb |= MBX_3; 5014 5015 mcp->tov = MBX_TOV_SECONDS; 5016 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5017 mcp->buf_size = mreq->transfer_size; 5018 5019 rval = qla2x00_mailbox_command(vha, mcp); 5020 5021 if (rval != QLA_SUCCESS) { 5022 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 5023 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5024 rval, mcp->mb[0], mcp->mb[1]); 5025 } else { 5026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 5027 "Done %s.\n", __func__); 5028 } 5029 5030 /* Copy mailbox information */ 5031 memcpy(mresp, mcp->mb, 64); 5032 return rval; 5033 } 5034 5035 int 5036 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 5037 { 5038 int rval; 5039 mbx_cmd_t mc; 5040 mbx_cmd_t *mcp = &mc; 5041 5042 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 5043 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 5044 5045 mcp->mb[0] = MBC_ISP84XX_RESET; 5046 mcp->mb[1] = enable_diagnostic; 5047 mcp->out_mb = MBX_1|MBX_0; 5048 mcp->in_mb = MBX_1|MBX_0; 5049 mcp->tov = MBX_TOV_SECONDS; 5050 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5051 rval = qla2x00_mailbox_command(vha, mcp); 5052 5053 if (rval != QLA_SUCCESS) 5054 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 5055 else 5056 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 5057 "Done %s.\n", __func__); 5058 5059 return rval; 5060 } 5061 5062 int 5063 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 5064 { 5065 int rval; 5066 mbx_cmd_t mc; 5067 mbx_cmd_t *mcp = &mc; 5068 5069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 5070 "Entered %s.\n", __func__); 5071 5072 if (!IS_FWI2_CAPABLE(vha->hw)) 5073 return QLA_FUNCTION_FAILED; 5074 5075 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 5076 mcp->mb[1] = LSW(risc_addr); 5077 mcp->mb[2] = LSW(data); 5078 mcp->mb[3] = MSW(data); 5079 mcp->mb[8] = MSW(risc_addr); 5080 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 5081 mcp->in_mb = MBX_0; 5082 mcp->tov = 30; 5083 mcp->flags = 0; 5084 rval = qla2x00_mailbox_command(vha, mcp); 5085 if (rval != QLA_SUCCESS) { 5086 ql_dbg(ql_dbg_mbx, vha, 0x1101, 5087 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5088 } else { 5089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 5090 "Done %s.\n", __func__); 5091 } 5092 5093 return rval; 5094 } 5095 5096 int 5097 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 5098 { 5099 int rval; 5100 uint32_t stat, timer; 5101 uint16_t mb0 = 0; 5102 struct qla_hw_data *ha = vha->hw; 5103 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 5104 5105 rval = QLA_SUCCESS; 5106 5107 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 5108 "Entered %s.\n", __func__); 5109 5110 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 5111 5112 /* Write the MBC data to the registers */ 5113 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 5114 WRT_REG_WORD(®->mailbox1, mb[0]); 5115 WRT_REG_WORD(®->mailbox2, mb[1]); 5116 WRT_REG_WORD(®->mailbox3, mb[2]); 5117 WRT_REG_WORD(®->mailbox4, mb[3]); 5118 5119 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 5120 5121 /* Poll for MBC interrupt */ 5122 for (timer = 6000000; timer; timer--) { 5123 /* Check for pending interrupts. */ 5124 stat = RD_REG_DWORD(®->host_status); 5125 if (stat & HSRX_RISC_INT) { 5126 stat &= 0xff; 5127 5128 if (stat == 0x1 || stat == 0x2 || 5129 stat == 0x10 || stat == 0x11) { 5130 set_bit(MBX_INTERRUPT, 5131 &ha->mbx_cmd_flags); 5132 mb0 = RD_REG_WORD(®->mailbox0); 5133 WRT_REG_DWORD(®->hccr, 5134 HCCRX_CLR_RISC_INT); 5135 RD_REG_DWORD(®->hccr); 5136 break; 5137 } 5138 } 5139 udelay(5); 5140 } 5141 5142 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 5143 rval = mb0 & MBS_MASK; 5144 else 5145 rval = QLA_FUNCTION_FAILED; 5146 5147 if (rval != QLA_SUCCESS) { 5148 ql_dbg(ql_dbg_mbx, vha, 0x1104, 5149 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 5150 } else { 5151 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 5152 "Done %s.\n", __func__); 5153 } 5154 5155 return rval; 5156 } 5157 5158 int 5159 qla2x00_get_data_rate(scsi_qla_host_t *vha) 5160 { 5161 int rval; 5162 mbx_cmd_t mc; 5163 mbx_cmd_t *mcp = &mc; 5164 struct qla_hw_data *ha = vha->hw; 5165 5166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 5167 "Entered %s.\n", __func__); 5168 5169 if (!IS_FWI2_CAPABLE(ha)) 5170 return QLA_FUNCTION_FAILED; 5171 5172 mcp->mb[0] = MBC_DATA_RATE; 5173 mcp->mb[1] = 0; 5174 mcp->out_mb = MBX_1|MBX_0; 5175 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5176 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 5177 mcp->in_mb |= MBX_3; 5178 mcp->tov = MBX_TOV_SECONDS; 5179 mcp->flags = 0; 5180 rval = qla2x00_mailbox_command(vha, mcp); 5181 if (rval != QLA_SUCCESS) { 5182 ql_dbg(ql_dbg_mbx, vha, 0x1107, 5183 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5184 } else { 5185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 5186 "Done %s.\n", __func__); 5187 if (mcp->mb[1] != 0x7) 5188 ha->link_data_rate = mcp->mb[1]; 5189 } 5190 5191 return rval; 5192 } 5193 5194 int 5195 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5196 { 5197 int rval; 5198 mbx_cmd_t mc; 5199 mbx_cmd_t *mcp = &mc; 5200 struct qla_hw_data *ha = vha->hw; 5201 5202 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 5203 "Entered %s.\n", __func__); 5204 5205 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 5206 !IS_QLA27XX(ha)) 5207 return QLA_FUNCTION_FAILED; 5208 mcp->mb[0] = MBC_GET_PORT_CONFIG; 5209 mcp->out_mb = MBX_0; 5210 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5211 mcp->tov = MBX_TOV_SECONDS; 5212 mcp->flags = 0; 5213 5214 rval = qla2x00_mailbox_command(vha, mcp); 5215 5216 if (rval != QLA_SUCCESS) { 5217 ql_dbg(ql_dbg_mbx, vha, 0x110a, 5218 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5219 } else { 5220 /* Copy all bits to preserve original value */ 5221 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 5222 5223 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 5224 "Done %s.\n", __func__); 5225 } 5226 return rval; 5227 } 5228 5229 int 5230 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5231 { 5232 int rval; 5233 mbx_cmd_t mc; 5234 mbx_cmd_t *mcp = &mc; 5235 5236 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 5237 "Entered %s.\n", __func__); 5238 5239 mcp->mb[0] = MBC_SET_PORT_CONFIG; 5240 /* Copy all bits to preserve original setting */ 5241 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 5242 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5243 mcp->in_mb = MBX_0; 5244 mcp->tov = MBX_TOV_SECONDS; 5245 mcp->flags = 0; 5246 rval = qla2x00_mailbox_command(vha, mcp); 5247 5248 if (rval != QLA_SUCCESS) { 5249 ql_dbg(ql_dbg_mbx, vha, 0x110d, 5250 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5251 } else 5252 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 5253 "Done %s.\n", __func__); 5254 5255 return rval; 5256 } 5257 5258 5259 int 5260 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 5261 uint16_t *mb) 5262 { 5263 int rval; 5264 mbx_cmd_t mc; 5265 mbx_cmd_t *mcp = &mc; 5266 struct qla_hw_data *ha = vha->hw; 5267 5268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 5269 "Entered %s.\n", __func__); 5270 5271 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 5272 return QLA_FUNCTION_FAILED; 5273 5274 mcp->mb[0] = MBC_PORT_PARAMS; 5275 mcp->mb[1] = loop_id; 5276 if (ha->flags.fcp_prio_enabled) 5277 mcp->mb[2] = BIT_1; 5278 else 5279 mcp->mb[2] = BIT_2; 5280 mcp->mb[4] = priority & 0xf; 5281 mcp->mb[9] = vha->vp_idx; 5282 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5283 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5284 mcp->tov = 30; 5285 mcp->flags = 0; 5286 rval = qla2x00_mailbox_command(vha, mcp); 5287 if (mb != NULL) { 5288 mb[0] = mcp->mb[0]; 5289 mb[1] = mcp->mb[1]; 5290 mb[3] = mcp->mb[3]; 5291 mb[4] = mcp->mb[4]; 5292 } 5293 5294 if (rval != QLA_SUCCESS) { 5295 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 5296 } else { 5297 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 5298 "Done %s.\n", __func__); 5299 } 5300 5301 return rval; 5302 } 5303 5304 int 5305 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 5306 { 5307 int rval = QLA_FUNCTION_FAILED; 5308 struct qla_hw_data *ha = vha->hw; 5309 uint8_t byte; 5310 5311 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 5312 ql_dbg(ql_dbg_mbx, vha, 0x1150, 5313 "Thermal not supported by this card.\n"); 5314 return rval; 5315 } 5316 5317 if (IS_QLA25XX(ha)) { 5318 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5319 ha->pdev->subsystem_device == 0x0175) { 5320 rval = qla2x00_read_sfp(vha, 0, &byte, 5321 0x98, 0x1, 1, BIT_13|BIT_0); 5322 *temp = byte; 5323 return rval; 5324 } 5325 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 5326 ha->pdev->subsystem_device == 0x338e) { 5327 rval = qla2x00_read_sfp(vha, 0, &byte, 5328 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 5329 *temp = byte; 5330 return rval; 5331 } 5332 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 5333 "Thermal not supported by this card.\n"); 5334 return rval; 5335 } 5336 5337 if (IS_QLA82XX(ha)) { 5338 *temp = qla82xx_read_temperature(vha); 5339 rval = QLA_SUCCESS; 5340 return rval; 5341 } else if (IS_QLA8044(ha)) { 5342 *temp = qla8044_read_temperature(vha); 5343 rval = QLA_SUCCESS; 5344 return rval; 5345 } 5346 5347 rval = qla2x00_read_asic_temperature(vha, temp); 5348 return rval; 5349 } 5350 5351 int 5352 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 5353 { 5354 int rval; 5355 struct qla_hw_data *ha = vha->hw; 5356 mbx_cmd_t mc; 5357 mbx_cmd_t *mcp = &mc; 5358 5359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 5360 "Entered %s.\n", __func__); 5361 5362 if (!IS_FWI2_CAPABLE(ha)) 5363 return QLA_FUNCTION_FAILED; 5364 5365 memset(mcp, 0, sizeof(mbx_cmd_t)); 5366 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5367 mcp->mb[1] = 1; 5368 5369 mcp->out_mb = MBX_1|MBX_0; 5370 mcp->in_mb = MBX_0; 5371 mcp->tov = 30; 5372 mcp->flags = 0; 5373 5374 rval = qla2x00_mailbox_command(vha, mcp); 5375 if (rval != QLA_SUCCESS) { 5376 ql_dbg(ql_dbg_mbx, vha, 0x1016, 5377 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5378 } else { 5379 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 5380 "Done %s.\n", __func__); 5381 } 5382 5383 return rval; 5384 } 5385 5386 int 5387 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 5388 { 5389 int rval; 5390 struct qla_hw_data *ha = vha->hw; 5391 mbx_cmd_t mc; 5392 mbx_cmd_t *mcp = &mc; 5393 5394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 5395 "Entered %s.\n", __func__); 5396 5397 if (!IS_P3P_TYPE(ha)) 5398 return QLA_FUNCTION_FAILED; 5399 5400 memset(mcp, 0, sizeof(mbx_cmd_t)); 5401 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5402 mcp->mb[1] = 0; 5403 5404 mcp->out_mb = MBX_1|MBX_0; 5405 mcp->in_mb = MBX_0; 5406 mcp->tov = 30; 5407 mcp->flags = 0; 5408 5409 rval = qla2x00_mailbox_command(vha, mcp); 5410 if (rval != QLA_SUCCESS) { 5411 ql_dbg(ql_dbg_mbx, vha, 0x100c, 5412 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5413 } else { 5414 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 5415 "Done %s.\n", __func__); 5416 } 5417 5418 return rval; 5419 } 5420 5421 int 5422 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 5423 { 5424 struct qla_hw_data *ha = vha->hw; 5425 mbx_cmd_t mc; 5426 mbx_cmd_t *mcp = &mc; 5427 int rval = QLA_FUNCTION_FAILED; 5428 5429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 5430 "Entered %s.\n", __func__); 5431 5432 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5433 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5434 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5435 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 5436 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 5437 5438 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5439 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 5440 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5441 5442 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5443 mcp->tov = MBX_TOV_SECONDS; 5444 rval = qla2x00_mailbox_command(vha, mcp); 5445 5446 /* Always copy back return mailbox values. */ 5447 if (rval != QLA_SUCCESS) { 5448 ql_dbg(ql_dbg_mbx, vha, 0x1120, 5449 "mailbox command FAILED=0x%x, subcode=%x.\n", 5450 (mcp->mb[1] << 16) | mcp->mb[0], 5451 (mcp->mb[3] << 16) | mcp->mb[2]); 5452 } else { 5453 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 5454 "Done %s.\n", __func__); 5455 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 5456 if (!ha->md_template_size) { 5457 ql_dbg(ql_dbg_mbx, vha, 0x1122, 5458 "Null template size obtained.\n"); 5459 rval = QLA_FUNCTION_FAILED; 5460 } 5461 } 5462 return rval; 5463 } 5464 5465 int 5466 qla82xx_md_get_template(scsi_qla_host_t *vha) 5467 { 5468 struct qla_hw_data *ha = vha->hw; 5469 mbx_cmd_t mc; 5470 mbx_cmd_t *mcp = &mc; 5471 int rval = QLA_FUNCTION_FAILED; 5472 5473 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5474 "Entered %s.\n", __func__); 5475 5476 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5477 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5478 if (!ha->md_tmplt_hdr) { 5479 ql_log(ql_log_warn, vha, 0x1124, 5480 "Unable to allocate memory for Minidump template.\n"); 5481 return rval; 5482 } 5483 5484 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5485 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5486 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5487 mcp->mb[2] = LSW(RQST_TMPLT); 5488 mcp->mb[3] = MSW(RQST_TMPLT); 5489 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5490 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5491 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5492 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5493 mcp->mb[8] = LSW(ha->md_template_size); 5494 mcp->mb[9] = MSW(ha->md_template_size); 5495 5496 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5497 mcp->tov = MBX_TOV_SECONDS; 5498 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5499 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5500 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5501 rval = qla2x00_mailbox_command(vha, mcp); 5502 5503 if (rval != QLA_SUCCESS) { 5504 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5505 "mailbox command FAILED=0x%x, subcode=%x.\n", 5506 ((mcp->mb[1] << 16) | mcp->mb[0]), 5507 ((mcp->mb[3] << 16) | mcp->mb[2])); 5508 } else 5509 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5510 "Done %s.\n", __func__); 5511 return rval; 5512 } 5513 5514 int 5515 qla8044_md_get_template(scsi_qla_host_t *vha) 5516 { 5517 struct qla_hw_data *ha = vha->hw; 5518 mbx_cmd_t mc; 5519 mbx_cmd_t *mcp = &mc; 5520 int rval = QLA_FUNCTION_FAILED; 5521 int offset = 0, size = MINIDUMP_SIZE_36K; 5522 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5523 "Entered %s.\n", __func__); 5524 5525 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5526 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5527 if (!ha->md_tmplt_hdr) { 5528 ql_log(ql_log_warn, vha, 0xb11b, 5529 "Unable to allocate memory for Minidump template.\n"); 5530 return rval; 5531 } 5532 5533 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5534 while (offset < ha->md_template_size) { 5535 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5536 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5537 mcp->mb[2] = LSW(RQST_TMPLT); 5538 mcp->mb[3] = MSW(RQST_TMPLT); 5539 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5540 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5541 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5542 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5543 mcp->mb[8] = LSW(size); 5544 mcp->mb[9] = MSW(size); 5545 mcp->mb[10] = offset & 0x0000FFFF; 5546 mcp->mb[11] = offset & 0xFFFF0000; 5547 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5548 mcp->tov = MBX_TOV_SECONDS; 5549 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5550 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5551 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5552 rval = qla2x00_mailbox_command(vha, mcp); 5553 5554 if (rval != QLA_SUCCESS) { 5555 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5556 "mailbox command FAILED=0x%x, subcode=%x.\n", 5557 ((mcp->mb[1] << 16) | mcp->mb[0]), 5558 ((mcp->mb[3] << 16) | mcp->mb[2])); 5559 return rval; 5560 } else 5561 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5562 "Done %s.\n", __func__); 5563 offset = offset + size; 5564 } 5565 return rval; 5566 } 5567 5568 int 5569 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5570 { 5571 int rval; 5572 struct qla_hw_data *ha = vha->hw; 5573 mbx_cmd_t mc; 5574 mbx_cmd_t *mcp = &mc; 5575 5576 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5577 return QLA_FUNCTION_FAILED; 5578 5579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5580 "Entered %s.\n", __func__); 5581 5582 memset(mcp, 0, sizeof(mbx_cmd_t)); 5583 mcp->mb[0] = MBC_SET_LED_CONFIG; 5584 mcp->mb[1] = led_cfg[0]; 5585 mcp->mb[2] = led_cfg[1]; 5586 if (IS_QLA8031(ha)) { 5587 mcp->mb[3] = led_cfg[2]; 5588 mcp->mb[4] = led_cfg[3]; 5589 mcp->mb[5] = led_cfg[4]; 5590 mcp->mb[6] = led_cfg[5]; 5591 } 5592 5593 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5594 if (IS_QLA8031(ha)) 5595 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5596 mcp->in_mb = MBX_0; 5597 mcp->tov = 30; 5598 mcp->flags = 0; 5599 5600 rval = qla2x00_mailbox_command(vha, mcp); 5601 if (rval != QLA_SUCCESS) { 5602 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5603 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5604 } else { 5605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5606 "Done %s.\n", __func__); 5607 } 5608 5609 return rval; 5610 } 5611 5612 int 5613 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5614 { 5615 int rval; 5616 struct qla_hw_data *ha = vha->hw; 5617 mbx_cmd_t mc; 5618 mbx_cmd_t *mcp = &mc; 5619 5620 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5621 return QLA_FUNCTION_FAILED; 5622 5623 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5624 "Entered %s.\n", __func__); 5625 5626 memset(mcp, 0, sizeof(mbx_cmd_t)); 5627 mcp->mb[0] = MBC_GET_LED_CONFIG; 5628 5629 mcp->out_mb = MBX_0; 5630 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5631 if (IS_QLA8031(ha)) 5632 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5633 mcp->tov = 30; 5634 mcp->flags = 0; 5635 5636 rval = qla2x00_mailbox_command(vha, mcp); 5637 if (rval != QLA_SUCCESS) { 5638 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5639 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5640 } else { 5641 led_cfg[0] = mcp->mb[1]; 5642 led_cfg[1] = mcp->mb[2]; 5643 if (IS_QLA8031(ha)) { 5644 led_cfg[2] = mcp->mb[3]; 5645 led_cfg[3] = mcp->mb[4]; 5646 led_cfg[4] = mcp->mb[5]; 5647 led_cfg[5] = mcp->mb[6]; 5648 } 5649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5650 "Done %s.\n", __func__); 5651 } 5652 5653 return rval; 5654 } 5655 5656 int 5657 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5658 { 5659 int rval; 5660 struct qla_hw_data *ha = vha->hw; 5661 mbx_cmd_t mc; 5662 mbx_cmd_t *mcp = &mc; 5663 5664 if (!IS_P3P_TYPE(ha)) 5665 return QLA_FUNCTION_FAILED; 5666 5667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5668 "Entered %s.\n", __func__); 5669 5670 memset(mcp, 0, sizeof(mbx_cmd_t)); 5671 mcp->mb[0] = MBC_SET_LED_CONFIG; 5672 if (enable) 5673 mcp->mb[7] = 0xE; 5674 else 5675 mcp->mb[7] = 0xD; 5676 5677 mcp->out_mb = MBX_7|MBX_0; 5678 mcp->in_mb = MBX_0; 5679 mcp->tov = MBX_TOV_SECONDS; 5680 mcp->flags = 0; 5681 5682 rval = qla2x00_mailbox_command(vha, mcp); 5683 if (rval != QLA_SUCCESS) { 5684 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5685 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5686 } else { 5687 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5688 "Done %s.\n", __func__); 5689 } 5690 5691 return rval; 5692 } 5693 5694 int 5695 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5696 { 5697 int rval; 5698 struct qla_hw_data *ha = vha->hw; 5699 mbx_cmd_t mc; 5700 mbx_cmd_t *mcp = &mc; 5701 5702 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5703 return QLA_FUNCTION_FAILED; 5704 5705 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5706 "Entered %s.\n", __func__); 5707 5708 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5709 mcp->mb[1] = LSW(reg); 5710 mcp->mb[2] = MSW(reg); 5711 mcp->mb[3] = LSW(data); 5712 mcp->mb[4] = MSW(data); 5713 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5714 5715 mcp->in_mb = MBX_1|MBX_0; 5716 mcp->tov = MBX_TOV_SECONDS; 5717 mcp->flags = 0; 5718 rval = qla2x00_mailbox_command(vha, mcp); 5719 5720 if (rval != QLA_SUCCESS) { 5721 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5722 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5723 } else { 5724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5725 "Done %s.\n", __func__); 5726 } 5727 5728 return rval; 5729 } 5730 5731 int 5732 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5733 { 5734 int rval; 5735 struct qla_hw_data *ha = vha->hw; 5736 mbx_cmd_t mc; 5737 mbx_cmd_t *mcp = &mc; 5738 5739 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5740 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5741 "Implicit LOGO Unsupported.\n"); 5742 return QLA_FUNCTION_FAILED; 5743 } 5744 5745 5746 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5747 "Entering %s.\n", __func__); 5748 5749 /* Perform Implicit LOGO. */ 5750 mcp->mb[0] = MBC_PORT_LOGOUT; 5751 mcp->mb[1] = fcport->loop_id; 5752 mcp->mb[10] = BIT_15; 5753 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5754 mcp->in_mb = MBX_0; 5755 mcp->tov = MBX_TOV_SECONDS; 5756 mcp->flags = 0; 5757 rval = qla2x00_mailbox_command(vha, mcp); 5758 if (rval != QLA_SUCCESS) 5759 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5760 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5761 else 5762 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5763 "Done %s.\n", __func__); 5764 5765 return rval; 5766 } 5767 5768 int 5769 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5770 { 5771 int rval; 5772 mbx_cmd_t mc; 5773 mbx_cmd_t *mcp = &mc; 5774 struct qla_hw_data *ha = vha->hw; 5775 unsigned long retry_max_time = jiffies + (2 * HZ); 5776 5777 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5778 return QLA_FUNCTION_FAILED; 5779 5780 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5781 5782 retry_rd_reg: 5783 mcp->mb[0] = MBC_READ_REMOTE_REG; 5784 mcp->mb[1] = LSW(reg); 5785 mcp->mb[2] = MSW(reg); 5786 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5787 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5788 mcp->tov = MBX_TOV_SECONDS; 5789 mcp->flags = 0; 5790 rval = qla2x00_mailbox_command(vha, mcp); 5791 5792 if (rval != QLA_SUCCESS) { 5793 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5794 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5795 rval, mcp->mb[0], mcp->mb[1]); 5796 } else { 5797 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5798 if (*data == QLA8XXX_BAD_VALUE) { 5799 /* 5800 * During soft-reset CAMRAM register reads might 5801 * return 0xbad0bad0. So retry for MAX of 2 sec 5802 * while reading camram registers. 5803 */ 5804 if (time_after(jiffies, retry_max_time)) { 5805 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5806 "Failure to read CAMRAM register. " 5807 "data=0x%x.\n", *data); 5808 return QLA_FUNCTION_FAILED; 5809 } 5810 msleep(100); 5811 goto retry_rd_reg; 5812 } 5813 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5814 } 5815 5816 return rval; 5817 } 5818 5819 int 5820 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5821 { 5822 int rval; 5823 mbx_cmd_t mc; 5824 mbx_cmd_t *mcp = &mc; 5825 struct qla_hw_data *ha = vha->hw; 5826 5827 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5828 return QLA_FUNCTION_FAILED; 5829 5830 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5831 5832 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5833 mcp->out_mb = MBX_0; 5834 mcp->in_mb = MBX_1|MBX_0; 5835 mcp->tov = MBX_TOV_SECONDS; 5836 mcp->flags = 0; 5837 rval = qla2x00_mailbox_command(vha, mcp); 5838 5839 if (rval != QLA_SUCCESS) { 5840 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5841 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5842 rval, mcp->mb[0], mcp->mb[1]); 5843 ha->isp_ops->fw_dump(vha, 0); 5844 } else { 5845 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5846 } 5847 5848 return rval; 5849 } 5850 5851 int 5852 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5853 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5854 { 5855 int rval; 5856 mbx_cmd_t mc; 5857 mbx_cmd_t *mcp = &mc; 5858 uint8_t subcode = (uint8_t)options; 5859 struct qla_hw_data *ha = vha->hw; 5860 5861 if (!IS_QLA8031(ha)) 5862 return QLA_FUNCTION_FAILED; 5863 5864 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5865 5866 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5867 mcp->mb[1] = options; 5868 mcp->out_mb = MBX_1|MBX_0; 5869 if (subcode & BIT_2) { 5870 mcp->mb[2] = LSW(start_addr); 5871 mcp->mb[3] = MSW(start_addr); 5872 mcp->mb[4] = LSW(end_addr); 5873 mcp->mb[5] = MSW(end_addr); 5874 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5875 } 5876 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5877 if (!(subcode & (BIT_2 | BIT_5))) 5878 mcp->in_mb |= MBX_4|MBX_3; 5879 mcp->tov = MBX_TOV_SECONDS; 5880 mcp->flags = 0; 5881 rval = qla2x00_mailbox_command(vha, mcp); 5882 5883 if (rval != QLA_SUCCESS) { 5884 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5885 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5886 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5887 mcp->mb[4]); 5888 ha->isp_ops->fw_dump(vha, 0); 5889 } else { 5890 if (subcode & BIT_5) 5891 *sector_size = mcp->mb[1]; 5892 else if (subcode & (BIT_6 | BIT_7)) { 5893 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5894 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5895 } else if (subcode & (BIT_3 | BIT_4)) { 5896 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5897 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5898 } 5899 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5900 } 5901 5902 return rval; 5903 } 5904 5905 int 5906 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5907 uint32_t size) 5908 { 5909 int rval; 5910 mbx_cmd_t mc; 5911 mbx_cmd_t *mcp = &mc; 5912 5913 if (!IS_MCTP_CAPABLE(vha->hw)) 5914 return QLA_FUNCTION_FAILED; 5915 5916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5917 "Entered %s.\n", __func__); 5918 5919 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5920 mcp->mb[1] = LSW(addr); 5921 mcp->mb[2] = MSW(req_dma); 5922 mcp->mb[3] = LSW(req_dma); 5923 mcp->mb[4] = MSW(size); 5924 mcp->mb[5] = LSW(size); 5925 mcp->mb[6] = MSW(MSD(req_dma)); 5926 mcp->mb[7] = LSW(MSD(req_dma)); 5927 mcp->mb[8] = MSW(addr); 5928 /* Setting RAM ID to valid */ 5929 mcp->mb[10] |= BIT_7; 5930 /* For MCTP RAM ID is 0x40 */ 5931 mcp->mb[10] |= 0x40; 5932 5933 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5934 MBX_0; 5935 5936 mcp->in_mb = MBX_0; 5937 mcp->tov = MBX_TOV_SECONDS; 5938 mcp->flags = 0; 5939 rval = qla2x00_mailbox_command(vha, mcp); 5940 5941 if (rval != QLA_SUCCESS) { 5942 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5943 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5944 } else { 5945 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5946 "Done %s.\n", __func__); 5947 } 5948 5949 return rval; 5950 } 5951 5952 int 5953 qla26xx_dport_diagnostics(scsi_qla_host_t *vha, 5954 void *dd_buf, uint size, uint options) 5955 { 5956 int rval; 5957 mbx_cmd_t mc; 5958 mbx_cmd_t *mcp = &mc; 5959 dma_addr_t dd_dma; 5960 5961 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 5962 return QLA_FUNCTION_FAILED; 5963 5964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f, 5965 "Entered %s.\n", __func__); 5966 5967 dd_dma = dma_map_single(&vha->hw->pdev->dev, 5968 dd_buf, size, DMA_FROM_DEVICE); 5969 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) { 5970 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n"); 5971 return QLA_MEMORY_ALLOC_FAILED; 5972 } 5973 5974 memset(dd_buf, 0, size); 5975 5976 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS; 5977 mcp->mb[1] = options; 5978 mcp->mb[2] = MSW(LSD(dd_dma)); 5979 mcp->mb[3] = LSW(LSD(dd_dma)); 5980 mcp->mb[6] = MSW(MSD(dd_dma)); 5981 mcp->mb[7] = LSW(MSD(dd_dma)); 5982 mcp->mb[8] = size; 5983 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5984 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5985 mcp->buf_size = size; 5986 mcp->flags = MBX_DMA_IN; 5987 mcp->tov = MBX_TOV_SECONDS * 4; 5988 rval = qla2x00_mailbox_command(vha, mcp); 5989 5990 if (rval != QLA_SUCCESS) { 5991 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval); 5992 } else { 5993 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196, 5994 "Done %s.\n", __func__); 5995 } 5996 5997 dma_unmap_single(&vha->hw->pdev->dev, dd_dma, 5998 size, DMA_FROM_DEVICE); 5999 6000 return rval; 6001 } 6002 6003 static void qla2x00_async_mb_sp_done(void *s, int res) 6004 { 6005 struct srb *sp = s; 6006 6007 sp->u.iocb_cmd.u.mbx.rc = res; 6008 6009 complete(&sp->u.iocb_cmd.u.mbx.comp); 6010 /* don't free sp here. Let the caller do the free */ 6011 } 6012 6013 /* 6014 * This mailbox uses the iocb interface to send MB command. 6015 * This allows non-critial (non chip setup) command to go 6016 * out in parrallel. 6017 */ 6018 int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp) 6019 { 6020 int rval = QLA_FUNCTION_FAILED; 6021 srb_t *sp; 6022 struct srb_iocb *c; 6023 6024 if (!vha->hw->flags.fw_started) 6025 goto done; 6026 6027 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL); 6028 if (!sp) 6029 goto done; 6030 6031 sp->type = SRB_MB_IOCB; 6032 sp->name = mb_to_str(mcp->mb[0]); 6033 6034 c = &sp->u.iocb_cmd; 6035 c->timeout = qla2x00_async_iocb_timeout; 6036 init_completion(&c->u.mbx.comp); 6037 6038 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 6039 6040 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG); 6041 6042 sp->done = qla2x00_async_mb_sp_done; 6043 6044 rval = qla2x00_start_sp(sp); 6045 if (rval != QLA_SUCCESS) { 6046 ql_dbg(ql_dbg_mbx, vha, 0x1018, 6047 "%s: %s Failed submission. %x.\n", 6048 __func__, sp->name, rval); 6049 goto done_free_sp; 6050 } 6051 6052 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n", 6053 sp->name, sp->handle); 6054 6055 wait_for_completion(&c->u.mbx.comp); 6056 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG); 6057 6058 rval = c->u.mbx.rc; 6059 switch (rval) { 6060 case QLA_FUNCTION_TIMEOUT: 6061 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n", 6062 __func__, sp->name, rval); 6063 break; 6064 case QLA_SUCCESS: 6065 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n", 6066 __func__, sp->name); 6067 sp->free(sp); 6068 break; 6069 default: 6070 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n", 6071 __func__, sp->name, rval); 6072 sp->free(sp); 6073 break; 6074 } 6075 6076 return rval; 6077 6078 done_free_sp: 6079 sp->free(sp); 6080 done: 6081 return rval; 6082 } 6083 6084 /* 6085 * qla24xx_gpdb_wait 6086 * NOTE: Do not call this routine from DPC thread 6087 */ 6088 int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 6089 { 6090 int rval = QLA_FUNCTION_FAILED; 6091 dma_addr_t pd_dma; 6092 struct port_database_24xx *pd; 6093 struct qla_hw_data *ha = vha->hw; 6094 mbx_cmd_t mc; 6095 6096 if (!vha->hw->flags.fw_started) 6097 goto done; 6098 6099 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 6100 if (pd == NULL) { 6101 ql_log(ql_log_warn, vha, 0xd047, 6102 "Failed to allocate port database structure.\n"); 6103 goto done_free_sp; 6104 } 6105 6106 memset(&mc, 0, sizeof(mc)); 6107 mc.mb[0] = MBC_GET_PORT_DATABASE; 6108 mc.mb[1] = cpu_to_le16(fcport->loop_id); 6109 mc.mb[2] = MSW(pd_dma); 6110 mc.mb[3] = LSW(pd_dma); 6111 mc.mb[6] = MSW(MSD(pd_dma)); 6112 mc.mb[7] = LSW(MSD(pd_dma)); 6113 mc.mb[9] = cpu_to_le16(vha->vp_idx); 6114 mc.mb[10] = cpu_to_le16((uint16_t)opt); 6115 6116 rval = qla24xx_send_mb_cmd(vha, &mc); 6117 if (rval != QLA_SUCCESS) { 6118 ql_dbg(ql_dbg_mbx, vha, 0x1193, 6119 "%s: %8phC fail\n", __func__, fcport->port_name); 6120 goto done_free_sp; 6121 } 6122 6123 rval = __qla24xx_parse_gpdb(vha, fcport, pd); 6124 6125 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n", 6126 __func__, fcport->port_name); 6127 6128 done_free_sp: 6129 if (pd) 6130 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 6131 done: 6132 return rval; 6133 } 6134 6135 int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, 6136 struct port_database_24xx *pd) 6137 { 6138 int rval = QLA_SUCCESS; 6139 uint64_t zero = 0; 6140 u8 current_login_state, last_login_state; 6141 6142 if (fcport->fc4f_nvme) { 6143 current_login_state = pd->current_login_state >> 4; 6144 last_login_state = pd->last_login_state >> 4; 6145 } else { 6146 current_login_state = pd->current_login_state & 0xf; 6147 last_login_state = pd->last_login_state & 0xf; 6148 } 6149 6150 /* Check for logged in state. */ 6151 if (current_login_state != PDS_PRLI_COMPLETE) { 6152 ql_dbg(ql_dbg_mbx, vha, 0x119a, 6153 "Unable to verify login-state (%x/%x) for loop_id %x.\n", 6154 current_login_state, last_login_state, fcport->loop_id); 6155 rval = QLA_FUNCTION_FAILED; 6156 goto gpd_error_out; 6157 } 6158 6159 if (fcport->loop_id == FC_NO_LOOP_ID || 6160 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 6161 memcmp(fcport->port_name, pd->port_name, 8))) { 6162 /* We lost the device mid way. */ 6163 rval = QLA_NOT_LOGGED_IN; 6164 goto gpd_error_out; 6165 } 6166 6167 /* Names are little-endian. */ 6168 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 6169 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 6170 6171 /* Get port_id of device. */ 6172 fcport->d_id.b.domain = pd->port_id[0]; 6173 fcport->d_id.b.area = pd->port_id[1]; 6174 fcport->d_id.b.al_pa = pd->port_id[2]; 6175 fcport->d_id.b.rsvd_1 = 0; 6176 6177 if (fcport->fc4f_nvme) { 6178 fcport->nvme_prli_service_param = 6179 pd->prli_nvme_svc_param_word_3; 6180 fcport->port_type = FCT_NVME; 6181 } else { 6182 /* If not target must be initiator or unknown type. */ 6183 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 6184 fcport->port_type = FCT_INITIATOR; 6185 else 6186 fcport->port_type = FCT_TARGET; 6187 } 6188 /* Passback COS information. */ 6189 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ? 6190 FC_COS_CLASS2 : FC_COS_CLASS3; 6191 6192 if (pd->prli_svc_param_word_3[0] & BIT_7) { 6193 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 6194 fcport->conf_compl_supported = 1; 6195 } 6196 6197 gpd_error_out: 6198 return rval; 6199 } 6200 6201 /* 6202 * qla24xx_gidlist__wait 6203 * NOTE: don't call this routine from DPC thread. 6204 */ 6205 int qla24xx_gidlist_wait(struct scsi_qla_host *vha, 6206 void *id_list, dma_addr_t id_list_dma, uint16_t *entries) 6207 { 6208 int rval = QLA_FUNCTION_FAILED; 6209 mbx_cmd_t mc; 6210 6211 if (!vha->hw->flags.fw_started) 6212 goto done; 6213 6214 memset(&mc, 0, sizeof(mc)); 6215 mc.mb[0] = MBC_GET_ID_LIST; 6216 mc.mb[2] = MSW(id_list_dma); 6217 mc.mb[3] = LSW(id_list_dma); 6218 mc.mb[6] = MSW(MSD(id_list_dma)); 6219 mc.mb[7] = LSW(MSD(id_list_dma)); 6220 mc.mb[8] = 0; 6221 mc.mb[9] = cpu_to_le16(vha->vp_idx); 6222 6223 rval = qla24xx_send_mb_cmd(vha, &mc); 6224 if (rval != QLA_SUCCESS) { 6225 ql_dbg(ql_dbg_mbx, vha, 0x119b, 6226 "%s: fail\n", __func__); 6227 } else { 6228 *entries = mc.mb[1]; 6229 ql_dbg(ql_dbg_mbx, vha, 0x119c, 6230 "%s: done\n", __func__); 6231 } 6232 done: 6233 return rval; 6234 } 6235 6236 int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value) 6237 { 6238 int rval; 6239 mbx_cmd_t mc; 6240 mbx_cmd_t *mcp = &mc; 6241 6242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200, 6243 "Entered %s\n", __func__); 6244 6245 memset(mcp->mb, 0 , sizeof(mcp->mb)); 6246 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD; 6247 mcp->mb[1] = cpu_to_le16(1); 6248 mcp->mb[2] = cpu_to_le16(value); 6249 mcp->out_mb = MBX_2 | MBX_1 | MBX_0; 6250 mcp->in_mb = MBX_2 | MBX_0; 6251 mcp->tov = MBX_TOV_SECONDS; 6252 mcp->flags = 0; 6253 6254 rval = qla2x00_mailbox_command(vha, mcp); 6255 6256 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n", 6257 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval); 6258 6259 return rval; 6260 } 6261 6262 int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value) 6263 { 6264 int rval; 6265 mbx_cmd_t mc; 6266 mbx_cmd_t *mcp = &mc; 6267 6268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203, 6269 "Entered %s\n", __func__); 6270 6271 memset(mcp->mb, 0, sizeof(mcp->mb)); 6272 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD; 6273 mcp->mb[1] = cpu_to_le16(0); 6274 mcp->out_mb = MBX_1 | MBX_0; 6275 mcp->in_mb = MBX_2 | MBX_0; 6276 mcp->tov = MBX_TOV_SECONDS; 6277 mcp->flags = 0; 6278 6279 rval = qla2x00_mailbox_command(vha, mcp); 6280 if (rval == QLA_SUCCESS) 6281 *value = mc.mb[2]; 6282 6283 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n", 6284 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval); 6285 6286 return rval; 6287 } 6288 6289 int 6290 qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count) 6291 { 6292 struct qla_hw_data *ha = vha->hw; 6293 uint16_t iter, addr, offset; 6294 dma_addr_t phys_addr; 6295 int rval, c; 6296 u8 *sfp_data; 6297 6298 memset(ha->sfp_data, 0, SFP_DEV_SIZE); 6299 addr = 0xa0; 6300 phys_addr = ha->sfp_data_dma; 6301 sfp_data = ha->sfp_data; 6302 offset = c = 0; 6303 6304 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) { 6305 if (iter == 4) { 6306 /* Skip to next device address. */ 6307 addr = 0xa2; 6308 offset = 0; 6309 } 6310 6311 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data, 6312 addr, offset, SFP_BLOCK_SIZE, BIT_1); 6313 if (rval != QLA_SUCCESS) { 6314 ql_log(ql_log_warn, vha, 0x706d, 6315 "Unable to read SFP data (%x/%x/%x).\n", rval, 6316 addr, offset); 6317 6318 return rval; 6319 } 6320 6321 if (buf && (c < count)) { 6322 u16 sz; 6323 6324 if ((count - c) >= SFP_BLOCK_SIZE) 6325 sz = SFP_BLOCK_SIZE; 6326 else 6327 sz = count - c; 6328 6329 memcpy(buf, sfp_data, sz); 6330 buf += SFP_BLOCK_SIZE; 6331 c += sz; 6332 } 6333 phys_addr += SFP_BLOCK_SIZE; 6334 sfp_data += SFP_BLOCK_SIZE; 6335 offset += SFP_BLOCK_SIZE; 6336 } 6337 6338 return rval; 6339 } 6340 6341 int qla24xx_res_count_wait(struct scsi_qla_host *vha, 6342 uint16_t *out_mb, int out_mb_sz) 6343 { 6344 int rval = QLA_FUNCTION_FAILED; 6345 mbx_cmd_t mc; 6346 6347 if (!vha->hw->flags.fw_started) 6348 goto done; 6349 6350 memset(&mc, 0, sizeof(mc)); 6351 mc.mb[0] = MBC_GET_RESOURCE_COUNTS; 6352 6353 rval = qla24xx_send_mb_cmd(vha, &mc); 6354 if (rval != QLA_SUCCESS) { 6355 ql_dbg(ql_dbg_mbx, vha, 0xffff, 6356 "%s: fail\n", __func__); 6357 } else { 6358 if (out_mb_sz <= SIZEOF_IOCB_MB_REG) 6359 memcpy(out_mb, mc.mb, out_mb_sz); 6360 else 6361 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG); 6362 6363 ql_dbg(ql_dbg_mbx, vha, 0xffff, 6364 "%s: done\n", __func__); 6365 } 6366 done: 6367 return rval; 6368 } 6369